diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_1/block1_env.yaml b/UVM_Framework/UVMF_2022.3/challenge_3/block_1/block1_env.yaml new file mode 100644 index 00000000..8ab5da03 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_1/block1_env.yaml @@ -0,0 +1,84 @@ +uvmf: + benches: + "block_1" : + ## Specify the top-level block + top_env: "block_1" + clock_half_period: "5ns" + reset_assertion_level: "True" + reset_duration: "200ns" + active_passive: + - bfm_name: "apb_master" + value: "ACTIVE" + - bfm_name: "axi_master1" + value: "ACTIVE" + - bfm_name: "axi_master2" + value: "ACTIVE" + - bfm_name: "spi_slave" + value: "PASSIVE" + environments: + "block_1" : + agents : + - name: "apb_master" + type: "apb_m" + initiator_responder: "INITIATOR" + + - name: "axi_master1" + type: "axi_m" + initiator_responder: "INITIATOR" + + - name: "axi_master2" + type: "axi_m" + initiator_responder: "INITIATOR" + + - name: "spi_slave" + type: "spi_s" + initiator_responder: "RESPONDER" + + analysis_components : + - name: "block_1_pred" + type: "block_1_predictor" + - name: "block_1_sb" + type: "block_1_scoreboard" + + analysis_ports : + - name: "apb_master_ap" + trans_type: "apb_m_transaction" + connected_to: "apb_master.monitored_ap" + - name: "axi_master1_ap" + trans_type: "axi_m_transaction" + connected_to: "axi_master1.monitored_ap" + - name: "axi_master2_ap" + trans_type: "axi_m_transaction" + connected_to: "axi_master2.monitored_ap" + - name: "spi_slave_ap" + trans_type: "spi_s_transaction" + connected_to: "spi_slave.monitored_ap" + # - name: "block_1_ap1" + # trans_type: "apb_m_transaction" + # connected_to: "apb_master.monitored_ap" + # - name: "block_1_ap2" + # trans_type: "axi_m_transaction" + # connected_to: "axi_master1.monitored_ap" + # - name: "block_1_ap3" + # trans_type: "axi_m_transaction" + # connected_to: "axi_master2.monitored_ap" + # - name: "block_2_ap1" + # trans_type: "spi_s_transaction" + # connected_to: "spi_slave.monitored_ap" + + tlm_connections: + - driver: "spi_slave.monitored_ap" + receiver: "block_1_sb.spi_ae" + - driver: "apb_master.monitored_ap" + receiver: "block_1_pred.apb_ae" + - driver: "axi_master1.monitored_ap" + receiver: "block_1_pred.axi_1_ae" + - driver: "axi_master2.monitored_ap" + receiver: "block_1_pred.axi_2_ae" + - driver: "block_1_pred.pre_to_sco_ap" + receiver: "block_1_sb.sco_from_pre_ae" + + config_vars : + - name: "has_scoreboard" + type : "bit" + isrand : "False" diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_1/block1_util.yaml b/UVM_Framework/UVMF_2022.3/challenge_3/block_1/block1_util.yaml new file mode 100644 index 00000000..bb4d18b6 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_1/block1_util.yaml @@ -0,0 +1,22 @@ +uvmf: + util_components: + block_1_predictor: + analysis_exports: + - name: apb_ae + type: 'apb_m_transaction' + - name: axi_1_ae + type: 'axi_m_transaction' + - name: axi_2_ae + type: 'axi_m_transaction' + analysis_ports: + - name: pre_to_sco_ap + type: 'spi_s_transaction' + existing_library_component: 'True' + type: predictor + block_1_scoreboard: + analysis_exports: + - name: spi_ae + type: 'spi_s_transaction' + - name: sco_from_pre_ae + type: 'spi_s_transaction' + type: scoreboard diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_1/block_1.csh b/UVM_Framework/UVMF_2022.3/challenge_3/block_1/block_1.csh new file mode 100644 index 00000000..a707f4b7 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_1/block_1.csh @@ -0,0 +1,7 @@ +# Setting the path for making "make cli" command works fine. + +setenv UVMF_HOME /hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3/ + +# This is the command to generate you block_1_level bench + +python ../../../UVMF_2022.3/scripts/yaml2uvmf.py ../intf/apb_m_intf.yaml ../intf/axi_m_intf.yaml ../intf/spi_s_intf.yaml ../block_1/block1_env.yaml ../block_1/block1_util.yaml diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/project_benches/block_1/.project b/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/project_benches/block_1/.project new file mode 100644 index 00000000..f8d875b5 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/project_benches/block_1/.project @@ -0,0 +1,37 @@ + + + block_1 + + + + + + org.python.pydev.PyDevBuilder + + + + + net.sf.sveditor.core.SVProjectBuilder + + + + + + net.sf.sveditor.core.SVNature + org.python.pydev.pythonNature + + + + verification_ip + 2 + UVMF_VIP_LIBRARY_HOME + + + + + UVMF_VIP_LIBRARY_HOME + $%7BPARENT-2-PROJECT_LOC%7D/verification_ip + + + + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/project_benches/block_1/.svproject b/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/project_benches/block_1/.svproject new file mode 100644 index 00000000..2bcfbf34 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/project_benches/block_1/.svproject @@ -0,0 +1,16 @@ + + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/project_benches/block_1/block_1_sve.F b/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/project_benches/block_1/block_1_sve.F new file mode 100644 index 00000000..08e278c3 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/project_benches/block_1/block_1_sve.F @@ -0,0 +1,29 @@ + +// UVM ++incdir+${UVM_HOME}/src +${UVM_HOME}/src/uvm_pkg.sv + +// Common UVMF files +-f ${UVMF_HOME}/common/common_sve.f + +// BFM Files +-F ${UVMF_VIP_LIBRARY_HOME}/interface_packages/apb_m_pkg/apb_m_pkg_sve.F +-F ${UVMF_VIP_LIBRARY_HOME}/interface_packages/axi_m_pkg/axi_m_pkg_sve.F +-F ${UVMF_VIP_LIBRARY_HOME}/interface_packages/spi_s_pkg/spi_s_pkg_sve.F + +// Environment Files +-F ${UVMF_VIP_LIBRARY_HOME}/environment_packages/block_1_env_pkg/block_1_env_pkg_sve.F + +// Bench Files ++incdir+./tb/tests +./tb/tests/block_1_tests_pkg.sv + ++incdir+./tb/sequences +./tb/sequences/block_1_sequences_pkg.sv + ++incdir+./tb/parameters +./tb/parameters/block_1_parameters_pkg.sv + +./tb/testbench/hdl_top.sv +./tb/testbench/hvl_top.sv + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/project_benches/block_1/docs/interfaces.csv b/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/project_benches/block_1/docs/interfaces.csv new file mode 100644 index 00000000..784f480a --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/project_benches/block_1/docs/interfaces.csv @@ -0,0 +1,16 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// + +, +Interface Description, Interface Type, Interface Transaction, Interface Name, +apb_master, apb_m_driver_bfm apb_m_monitor_bfm, apb_m_transaction, apb_m_pkg_apb_master_BFM, +axi_master1, axi_m_driver_bfm axi_m_monitor_bfm, axi_m_transaction, axi_m_pkg_axi_master1_BFM, +axi_master2, axi_m_driver_bfm axi_m_monitor_bfm, axi_m_transaction, axi_m_pkg_axi_master2_BFM, +spi_slave, spi_s_driver_bfm spi_s_monitor_bfm, spi_s_transaction, spi_s_pkg_spi_slave_BFM, + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/project_benches/block_1/rtl/dut.compile b/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/project_benches/block_1/rtl/dut.compile new file mode 100644 index 00000000..9b0008fc --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/project_benches/block_1/rtl/dut.compile @@ -0,0 +1,6 @@ + +# pragma uvmf custom dut_compile_info begin +src: + - ./vhdl/vhdl_dut.vhd + - ./verilog/verilog_dut.v +# pragma uvmf custom dut_compile_info end diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/project_benches/block_1/rtl/verilog/verilog_dut.v b/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/project_benches/block_1/rtl/verilog/verilog_dut.v new file mode 100644 index 00000000..96198441 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/project_benches/block_1/rtl/verilog/verilog_dut.v @@ -0,0 +1,21 @@ +module verilog_dut(clk, rst, in_signal, out_signal); + +input clk; +input rst; +input in_signal; +output out_signal; + +reg out_signal_o; + +always @(posedge clk) begin + if (rst) begin + out_signal_o <= 0; + end + else begin + out_signal_o <= ~in_signal; + end + end + +assign out_signal = out_signal_o; + +endmodule diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/project_benches/block_1/rtl/verilog/verilog_dut.vinfo b/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/project_benches/block_1/rtl/verilog/verilog_dut.vinfo new file mode 100644 index 00000000..87e95f36 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/project_benches/block_1/rtl/verilog/verilog_dut.vinfo @@ -0,0 +1 @@ +verilog_dut.v diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/project_benches/block_1/rtl/vhdl/vhdl_dut.vhd b/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/project_benches/block_1/rtl/vhdl/vhdl_dut.vhd new file mode 100644 index 00000000..904aa37d --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/project_benches/block_1/rtl/vhdl/vhdl_dut.vhd @@ -0,0 +1,21 @@ +library ieee; +use ieee.std_logic_1164.all ; + +entity vhdl_dut is + port ( clk : in std_logic ; + rst : in std_logic ; + in_signal : in std_logic ; + out_signal :out std_logic + ); +end vhdl_dut; + +architecture rtl of vhdl_dut is + begin + P1: process + variable out_signal_o : std_logic; + begin + wait until clk'event and clk = '1'; + out_signal_o := in_signal; + out_signal <= out_signal_o; + end process; + end rtl; diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/project_benches/block_1/sim/Makefile b/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/project_benches/block_1/sim/Makefile new file mode 100644 index 00000000..8bf96331 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/project_benches/block_1/sim/Makefile @@ -0,0 +1,200 @@ + +# +#---------------------------------------------------------------------- +# +# DESCRIPTION: This makefile includes the shared makefile and contains +# bench level make targets. +# +#---------------------------------------------------------------------- + + +# pragma uvmf custom additional begin +# pragma uvmf custom additional end + +# ********************************************************************************************* +# UVMF library directory: +# This variable points to the UVMF release where uvmf_base_pkg directory resides. +# This variable points to release code that is not user modified. +# This variable allows for UVMF release directories to reside independent of project related verification IP and project bench directories. +# This code below looks "upward" for directory starting with UVMF_* and returns first match for use with the release examples. +UVMF_HOME ?= ___PLEASE_SET_AN_ENVIRONMENT_VARIABLE_NAMED_UVMF_HOME_TO_POINT_TO_THE_UVMF_INSTALLATION___ + +# pragma uvmf custom exports begin +# +# Project(s) specific verification IP library: +# Directory where reusable verification packages for interfaces, environments, utilities, etc. reside. +# This variable allows for your verification IP to reside independent of project bench and UVMF release directories. +# For examples deployed with UVMF this will be $(UVMF_HOME)//verification_ip +export UVMF_VIP_LIBRARY_HOME ?= $(PWD)/../../../verification_ip +# +# Project specific bench: +# Directory where bench specific code is located. +# This variable allows for project_benches to reside independent of verification IP and UVMF release directories. +# For examples deployed with UVMF this will be $(UVMF_HOME)//project_benches/ +export UVMF_PROJECT_DIR ?= $(PWD)/.. +# +# +# pragma uvmf custom exports end +# ********************************************************************************************* + +## Check PATH for required vinfo scripts +PVAL := $(shell command -v make_filelist.py 2> /dev/null) +ifndef PVAL + MFLIST = $(UVMF_HOME)/scripts/make_filelist.py +else + MFLIST = make_filelist.py +endif + + +# Set test case specific Variables +TEST_NAME ?= test_top + +TEST_SEED ?= random +UVM_CLI_ARGS = + +# Usage of Veloce, etc. to be input by the user (subject to defaults) +USE_VELOCE ?= 0 + +# Usage of vinfo flow for generating file list +USE_VINFO ?= 0 + +# Usage of Veloce and Questa profilers +USE_VELOCE_PROFILER ?= 0 +USE_QUESTA_PROFILER ?= 0 + + +# Set project Variables +TEST_PLAN_NAME = block_1_TestPlan +REPORTING_DO_FILE = block_1_reports_script + + +# Include makefile that includes targets for UVM_VIP_Library packages +include $(UVMF_HOME)/scripts/Makefile + + + + +# Include all requisite interface package targets for this bench +include $(UVMF_VIP_LIBRARY_HOME)/interface_packages/apb_m_pkg/Makefile +include $(UVMF_VIP_LIBRARY_HOME)/interface_packages/axi_m_pkg/Makefile +include $(UVMF_VIP_LIBRARY_HOME)/interface_packages/spi_s_pkg/Makefile + +# Include all requisite environment package targets for this bench +include $(UVMF_VIP_LIBRARY_HOME)/environment_packages/block_1_env_pkg/Makefile + + + +# Add to default compile/load/run arguments +VCOM_ARGS += + +# Note: vsim-3009 error can be eliminated by adding -timescale 1ps/1ps to VLOG_ARGS + +VLOG_ARGS += $(UVM_DISABLE_FILE_LINE_CMD) + +VELANALYZE_ARGS += +VELANALYZE_HVL_ARGS += + +BATCH_VOPT_ARGS += +DEBUG_VOPT_ARGS += +EXTRA_VOPT_TOPS += +COMMON_VSIM_ARGS += +COMMON_VSIM_ARGS += + + +BATCH_VSIM_ARGS += #-uvmcontrol=none +DEBUG_VSIM_ARGS += +EXTRA_VSIM_TOPS += + +# pragma uvmf custom additional_args begin +# pragma uvmf custom additional_args end + + +# Project bench package source +block_1_PARAMETERS_PKG ?=\ +$(UVMF_PROJECT_DIR)/tb/parameters/block_1_parameters_pkg.sv + + +block_1_SEQUENCES_PKG ?=\ +$(UVMF_PROJECT_DIR)/tb/sequences/block_1_sequences_pkg.sv + + +block_1_TEST_PKG ?=\ +$(UVMF_PROJECT_DIR)/tb/tests/block_1_tests_pkg.sv + +# pragma uvmf custom dut_files begin +# UVMF_CHANGE_ME : Reference Verilog DUT source. +block_1_VERILOG_DUT ?=\ +$(UVMF_PROJECT_DIR)/rtl/verilog/verilog_dut.v + +# UVMF_CHANGE_ME : Reference VHDL DUT source. +block_1_VHDL_DUT ?=\ +$(UVMF_PROJECT_DIR)/rtl/vhdl/vhdl_dut.vhd +# pragma uvmf custom dut_files end + + +# Project bench package targets +COMP_block_1_PARAMETERS_PKG_TGT_0 = q_comp_block_1_parameters_pkg +COMP_block_1_PARAMETERS_PKG_TGT_1 = v_comp_block_1_parameters_pkg +COMP_block_1_PARAMETERS_PKG_TGT = $(COMP_block_1_PARAMETERS_PKG_TGT_$(USE_VELOCE)) + +comp_block_1_parameters_pkg: $(COMP_block_1_PARAMETERS_PKG_TGT) + +q_comp_block_1_parameters_pkg: + $(HVL_COMP_CMD) +incdir+$(UVMF_PROJECT_DIR)/tb/parameters $(block_1_PARAMETERS_PKG) + +v_comp_block_1_parameters_pkg: q_comp_block_1_parameters_pkg + $(HDL_COMP_CMD) +incdir+$(UVMF_PROJECT_DIR)/tb/parameters $(block_1_PARAMETERS_PKG) + + +comp_block_1_sequence_pkg: + $(HVL_COMP_CMD) +incdir+$(UVMF_PROJECT_DIR)/tb/sequences $(block_1_SEQUENCES_PKG) + +comp_block_1_tests_pkg: + $(HVL_COMP_CMD) +incdir+$(UVMF_PROJECT_DIR)/tb/tests $(block_1_TEST_PKG) + +# pragma uvmf custom dut_compile_make_target begin +# UVMF_CHANGE_ME : Add make target to compile your verilog dut here +comp_block_1_verilog_dut: + echo "Compile your verilog DUT here" + $(HDL_COMP_CMD) $(block_1_VERILOG_DUT) + +# UVMF_CHANGE_ME : Add make target to compile your vhdl dut here +comp_block_1_vhdl_dut: + echo "Compile your vhdl DUT here" + $(HDL_COMP_CMD_VHDL) $(block_1_VHDL_DUT) + +# UVMF_CHANGE_ME : Add make target to compile your dut here +comp_block_1_dut: comp_block_1_vhdl_dut comp_block_1_verilog_dut +# pragma uvmf custom dut_compile_make_target end + + +BUILD_TGT_0 = make_build +BUILD_TGT_1 = vinfo_build +BUILD_TGT = $(BUILD_TGT_$(USE_VINFO)) + + +comp_hvl : comp_hvl_core + + +comp_hvl_core : \ + comp_apb_m_pkg comp_axi_m_pkg comp_spi_s_pkg \ + comp_block_1_env_pkg \ + comp_block_1_parameters_pkg comp_block_1_sequence_pkg comp_block_1_tests_pkg + +comp_uvmf_core : comp_uvm_pkg comp_uvmf_base_pkg + +make_build: comp_block_1_dut comp_uvmf_core comp_hvl comp_test_bench + +hvl_build: q_comp_apb_m_pkg q_comp_axi_m_pkg q_comp_spi_s_pkg comp_block_1_env_pkg comp_block_1_sequence_pkg comp_block_1_tests_pkg hvl_comp_testbench link optimize + + +vinfo_build: comp_block_1_vhdl_dut build_hdl_vinfo build_hvl_vinfo $(VINFO_TGT) + + $(HDL_COMP_CMD) -F hdl.vf + $(VEL_COMP) + +build: $(BUILD_TGT) + +# pragma uvmf custom additional_targets begin +# pragma uvmf custom additional_targets end + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/project_benches/block_1/sim/bcr_testlist b/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/project_benches/block_1/sim/bcr_testlist new file mode 100644 index 00000000..def2371e --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/project_benches/block_1/sim/bcr_testlist @@ -0,0 +1,19 @@ + + + +# Test list for use by RMDB file +# File syntax is +# TB_INFO { } { } +# TB ## All subsequent tests will run on this bench until a different "TB" line is seen +# TEST <1st_seed> ... +# If not enough seeds are provided then random seeds are used to pad +# If no repeat count is given, default is 1 +# pragma uvmf custom tb_info begin +TB_INFO block_1 { } { } +# pragma uvmf custom tb_info end +TB block_1 +# pragma uvmf custom regression_suite begin +TEST test_top 3 +# pragma uvmf custom regression_suite end + + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/project_benches/block_1/sim/bcr_testlist.yaml b/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/project_benches/block_1/sim/bcr_testlist.yaml new file mode 100644 index 00000000..e9f7fa3e --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/project_benches/block_1/sim/bcr_testlist.yaml @@ -0,0 +1,44 @@ + + + +# YAML test list for use by RMDB file +# File syntax is +# uvmf_testlist: +# testbenches: +# - name: +# extra_build_options: +# extra_run_options: +# - name: +# ... +# - name: +# tests: +# - name: +# uvm_testname: (defaults to test_name) +# testbench: (defaults to last tb name seen) +# repeat: (defaults to 1) +# seeds: [,,...,] (defaults to all random) +# extra_test_options: +# - name: +# ... +# - name: +# include: +# - (relative path reference is to the including YAML file) +# - +# ... +# - + +uvmf_testlist: + testbenches: +# pragma uvmf custom tb_info begin + - name: block_1 + extra_build_options: "" + extra_run_options: "" +# pragma uvmf custom tb_info end + tests: + - testbench: block_1 +# pragma uvmf custom regression_suite begin + - name: test_top + repeat: 3 +# pragma uvmf custom regression_suite end + + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/project_benches/block_1/sim/compile.do b/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/project_benches/block_1/sim/compile.do new file mode 100644 index 00000000..9f27636d --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/project_benches/block_1/sim/compile.do @@ -0,0 +1,72 @@ + + +################################################################## +## ENVIRONMENT VARIABLES +################################################################## +quietly set ::env(UVMF_VIP_LIBRARY_HOME) ../../../verification_ip +quietly set ::env(UVMF_PROJECT_DIR) .. + +## Using VRM means that the build is occuring several more directories deeper underneath +## the sim directory, need to prepend some more '..' +if {[info exists ::env(VRM_BUILD)]} { + quietly set ::env(UVMF_VIP_LIBRARY_HOME) "../../../../../$::env(UVMF_VIP_LIBRARY_HOME)" + quietly set ::env(UVMF_PROJECT_DIR) "../../../../../$::env(UVMF_PROJECT_DIR)" +} +quietly set ::env(UVMF_VIP_LIBRARY_HOME) [file normalize $::env(UVMF_VIP_LIBRARY_HOME)] +quietly set ::env(UVMF_PROJECT_DIR) [file normalize $::env(UVMF_PROJECT_DIR)] +quietly echo "UVMF_VIP_LIBRARY_HOME = $::env(UVMF_VIP_LIBRARY_HOME)" +quietly echo "UVMF_PROJECT_DIR = $::env(UVMF_PROJECT_DIR)" + + +################################################################### +## HOUSEKEEPING : DELETE FILES THAT WILL BE REGENERATED +################################################################### +file delete -force *~ *.ucdb vsim.dbg *.vstf *.log work *.mem *.transcript.txt certe_dump.xml *.wlf covhtmlreport VRMDATA +file delete -force design.bin qwave.db dpiheader.h visualizer*.ses +file delete -force veloce.med veloce.wave veloce.map tbxbindings.h edsenv velrunopts.ini +file delete -force sv_connect.* + +################################################################### +## COMPILE DUT SOURCE CODE +################################################################### +vlib work +# pragma uvmf custom dut_compile_dofile_target begin +# UVMF_CHANGE_ME : Add commands to compile your dut here, replacing the default examples +vlog -sv -timescale 1ps/1ps -suppress 2223,2286 $env(UVMF_PROJECT_DIR)/rtl/verilog/verilog_dut.v +vcom $env(UVMF_PROJECT_DIR)/rtl/vhdl/vhdl_dut.vhd +# pragma uvmf custom dut_compile_dofile_target end + +################################################################### +## COMPILE UVMF BASE/COMMON SOURCE CODE +################################################################### +vlog -sv -timescale 1ps/1ps -suppress 2223 -suppress 2286 +incdir+$env(UVMF_HOME)/uvmf_base_pkg -F $env(UVMF_HOME)/uvmf_base_pkg/uvmf_base_pkg_filelist_hdl.f +vlog -sv -timescale 1ps/1ps -suppress 2223 -suppress 2286 +incdir+$env(UVMF_HOME)/uvmf_base_pkg -F $env(UVMF_HOME)/uvmf_base_pkg/uvmf_base_pkg_filelist_hvl.f + + +################################################################### +## UVMF INTERFACE COMPILATION +################################################################### +do $env(UVMF_VIP_LIBRARY_HOME)/interface_packages/apb_m_pkg/compile.do +do $env(UVMF_VIP_LIBRARY_HOME)/interface_packages/axi_m_pkg/compile.do +do $env(UVMF_VIP_LIBRARY_HOME)/interface_packages/spi_s_pkg/compile.do + +################################################################### +## UVMF ENVIRONMENT COMPILATION +################################################################### +do $env(UVMF_VIP_LIBRARY_HOME)/environment_packages/block_1_env_pkg/compile.do + +################################################################### +## UVMF BENCHES COMPILATION +################################################################### +vlog -sv -timescale 1ps/1ps -suppress 2223 -suppress 2286 +incdir+$env(UVMF_PROJECT_DIR)/tb/parameters $env(UVMF_PROJECT_DIR)/tb/parameters/block_1_parameters_pkg.sv +vlog -sv -timescale 1ps/1ps -suppress 2223 -suppress 2286 +incdir+$env(UVMF_PROJECT_DIR)/tb/sequences $env(UVMF_PROJECT_DIR)/tb/sequences/block_1_sequences_pkg.sv +vlog -sv -timescale 1ps/1ps -suppress 2223 -suppress 2286 +incdir+$env(UVMF_PROJECT_DIR)/tb/tests $env(UVMF_PROJECT_DIR)/tb/tests/block_1_tests_pkg.sv + +vlog -sv -timescale 1ps/1ps -suppress 2223 -suppress 2286 +incdir+$env(UVMF_PROJECT_DIR)/tb/testbench -F $env(UVMF_PROJECT_DIR)/tb/testbench/top_filelist_hdl.f +vlog -sv -timescale 1ps/1ps -suppress 2223 -suppress 2286 +incdir+$env(UVMF_PROJECT_DIR)/tb/testbench -F $env(UVMF_PROJECT_DIR)/tb/testbench/top_filelist_hvl.f + +################################################################### +## OPTIMIZATION +################################################################### +vopt hvl_top hdl_top -o optimized_batch_top_tb +vopt +acc hvl_top hdl_top -o optimized_debug_top_tb diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/project_benches/block_1/sim/hdl.compile b/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/project_benches/block_1/sim/hdl.compile new file mode 100644 index 00000000..8e7bd41a --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/project_benches/block_1/sim/hdl.compile @@ -0,0 +1,5 @@ +needs: +# pragma uvmf custom dut_compile_info begin + - ../rtl/dut.compile +# pragma uvmf custom dut_compile_info end + - ../tb/testbench/hdl_top.compile diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/project_benches/block_1/sim/hdl.vinfo b/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/project_benches/block_1/sim/hdl.vinfo new file mode 100644 index 00000000..da27ec77 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/project_benches/block_1/sim/hdl.vinfo @@ -0,0 +1 @@ +@use $UVMF_PROJECT_DIR/tb/testbench/hdl_top.vinfo diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/project_benches/block_1/sim/hvl.compile b/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/project_benches/block_1/sim/hvl.compile new file mode 100644 index 00000000..ce952549 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/project_benches/block_1/sim/hvl.compile @@ -0,0 +1,2 @@ +needs: + - ../tb/testbench/hvl_top.compile diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/project_benches/block_1/sim/hvl.vinfo b/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/project_benches/block_1/sim/hvl.vinfo new file mode 100644 index 00000000..d22eff33 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/project_benches/block_1/sim/hvl.vinfo @@ -0,0 +1 @@ +@use $UVMF_PROJECT_DIR/tb/testbench/hvl_top.vinfo diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/project_benches/block_1/sim/run.do b/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/project_benches/block_1/sim/run.do new file mode 100644 index 00000000..101ddc48 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/project_benches/block_1/sim/run.do @@ -0,0 +1,21 @@ + + +quietly set svLibs "" +quietly set extra_vsim_args "" + +################################################################### +## Check for additional vsim arguments passed using env var $UVMF_EXTRA_VSIM_ARGS +################################################################### +if {[info exists ::env(UVMF_EXTRA_VSIM_ARGS)]} { + echo "Adding more args to vsim command" + quietly set extra_vsim_args $::env(UVMF_EXTRA_VSIM_ARGS) +} + +################################################################## +## Launch Questa : generate vsim command line and execute +################################################################## +# pragma uvmf custom dut_run_dofile_target begin +# UVMF_CHANGE_ME : Change the UVM_TESTNAME plusarg to run a different test +quietly set cmd [format "vsim -i -sv_seed random +UVM_TESTNAME=test_top +UVM_VERBOSITY=UVM_HIGH -permit_unmatched_virtual_intf +notimingchecks -suppress 8887 %s %s -uvmcontrol=all -msgmode both -classdebug -assertdebug +uvm_set_config_int=*,enable_transaction_viewing,1 -do { set NoQuitOnFinish 1; onbreak {resume}; run 0; do wave.do; set PrefSource(OpenOnBreak) 0; radix hex showbase; } optimized_debug_top_tb" $svLibs $extra_vsim_args] +# pragma uvmf custom dut_run_dofile_target end +eval $cmd diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/project_benches/block_1/sim/tbx.config b/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/project_benches/block_1/sim/tbx.config new file mode 100644 index 00000000..eec58168 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/project_benches/block_1/sim/tbx.config @@ -0,0 +1,10 @@ + + + + + +comp -questa +velsyn -D1S +rtlc -allow_4ST + + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/project_benches/block_1/sim/testlist b/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/project_benches/block_1/sim/testlist new file mode 100644 index 00000000..5ca4f2cc --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/project_benches/block_1/sim/testlist @@ -0,0 +1,20 @@ + + + + +# Test list for use by RMDB file +# File syntax is +# TB_INFO { } { } +# TB ## All subsequent tests will run on this bench until a different "TB" line is seen +# TEST <1st_seed> ... +# If not enough seeds are provided then random seeds are used to pad +# If no repeat count is given, default is 1 +# pragma uvmf custom tb_info begin +TB_INFO block_1 { UVMF_VIP_LIBRARY_HOME=../../../../../../../../verification_ip UVMF_PROJECT_DIR=../../../../../../../block_1 } { } +# pragma uvmf custom tb_info end +TB block_1 +# pragma uvmf custom regression_suite begin +TEST test_top 3 +# pragma uvmf custom regression_suite end + + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/project_benches/block_1/sim/testlist.yaml b/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/project_benches/block_1/sim/testlist.yaml new file mode 100644 index 00000000..113ec8a9 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/project_benches/block_1/sim/testlist.yaml @@ -0,0 +1,44 @@ + + + +# YAML test list for use by RMDB file +# File syntax is +# uvmf_testlist: +# testbenches: +# - name: +# extra_build_options: +# extra_run_options: +# - name: +# ... +# - name: +# tests: +# - name: +# uvm_testname: (defaults to test_name) +# testbench: (defaults to last tb name seen) +# repeat: (defaults to 1) +# seeds: [,,...,] (defaults to all random) +# extra_test_options: +# - name: +# ... +# - name: +# include: +# - (relative path reference is to the including YAML file) +# - +# ... +# - + +uvmf_testlist: + testbenches: +# pragma uvmf custom tb_info begin + - name: block_1 + extra_build_options: "UVMF_VIP_LIBRARY_HOME=../../../../../../../../verification_ip UVMF_PROJECT_DIR=../../../../../../../block_1" + extra_run_options: "" +# pragma uvmf custom tb_info end + tests: + - testbench: block_1 +# pragma uvmf custom regression_suite begin + - name: test_top + repeat: 3 +# pragma uvmf custom regression_suite end + + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/project_benches/block_1/sim/top.compile b/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/project_benches/block_1/sim/top.compile new file mode 100644 index 00000000..efd51c07 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/project_benches/block_1/sim/top.compile @@ -0,0 +1,3 @@ +needs: + - hvl.compile + - hdl.compile diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/project_benches/block_1/sim/veloce.config b/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/project_benches/block_1/sim/veloce.config new file mode 100644 index 00000000..d0975155 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/project_benches/block_1/sim/veloce.config @@ -0,0 +1,26 @@ + + + + + +# pragma uvmf custom additional begin +comp -num_boards 1 +comp -hvl questa +# Please choose the correct emulator type code for +# comp -platform command or else velcomp will fail +# Available types are: +# - Veloce2 Quattro: D2 +# - Veloce2 Maximus: D2M +# - Veloce Strato TiL, Ti, and Mi: Strato +# - Veloce Strato M and Strato T: StratoM +# - comp -platform +comp -platform Strato + +rtlc -enable_tbx_pragma_checks +rtlc -allow_4ST +rtlc -allow_MDR +rtlc -compile_display +rtlc -xwave_siglist xwaves.sigs +# pragma uvmf custom additional end + + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/project_benches/block_1/sim/viswave.do b/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/project_benches/block_1/sim/viswave.do new file mode 100644 index 00000000..5e690492 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/project_benches/block_1/sim/viswave.do @@ -0,0 +1,34 @@ + + +onerror resume +wave tags F0 +wave update off + +wave spacer -backgroundcolor Salmon { apb_master } +wave add uvm_test_top.environment.apb_master.apb_master_monitor.txn_stream -radix string -tag F0 +wave group apb_master_bus +wave add -group apb_master_bus hdl_top.apb_master_bus.* -radix hexadecimal -tag F0 +wave group apb_master_bus -collapse +wave insertion [expr [wave index insertpoint] +1] +wave spacer -backgroundcolor Salmon { axi_master1 } +wave add uvm_test_top.environment.axi_master1.axi_master1_monitor.txn_stream -radix string -tag F0 +wave group axi_master1_bus +wave add -group axi_master1_bus hdl_top.axi_master1_bus.* -radix hexadecimal -tag F0 +wave group axi_master1_bus -collapse +wave insertion [expr [wave index insertpoint] +1] +wave spacer -backgroundcolor Salmon { axi_master2 } +wave add uvm_test_top.environment.axi_master2.axi_master2_monitor.txn_stream -radix string -tag F0 +wave group axi_master2_bus +wave add -group axi_master2_bus hdl_top.axi_master2_bus.* -radix hexadecimal -tag F0 +wave group axi_master2_bus -collapse +wave insertion [expr [wave index insertpoint] +1] +wave spacer -backgroundcolor Salmon { spi_slave } +wave add uvm_test_top.environment.spi_slave.spi_slave_monitor.txn_stream -radix string -tag F0 +wave group spi_slave_bus +wave add -group spi_slave_bus hdl_top.spi_slave_bus.* -radix hexadecimal -tag F0 +wave group spi_slave_bus -collapse +wave insertion [expr [wave index insertpoint] +1] + +wave update on +WaveSetStreamView + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/project_benches/block_1/sim/wave.do b/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/project_benches/block_1/sim/wave.do new file mode 100644 index 00000000..a290af05 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/project_benches/block_1/sim/wave.do @@ -0,0 +1,36 @@ + + +onerror {resume} +quietly WaveActivateNextPane {} 0 + +add wave -noupdate -divider apb_master +add wave -noupdate /uvm_root/uvm_test_top/environment/apb_master/apb_master_monitor/txn_stream +add wave -noupdate -group apb_master_bus /hdl_top/apb_master_bus/* +add wave -noupdate -divider axi_master1 +add wave -noupdate /uvm_root/uvm_test_top/environment/axi_master1/axi_master1_monitor/txn_stream +add wave -noupdate -group axi_master1_bus /hdl_top/axi_master1_bus/* +add wave -noupdate -divider axi_master2 +add wave -noupdate /uvm_root/uvm_test_top/environment/axi_master2/axi_master2_monitor/txn_stream +add wave -noupdate -group axi_master2_bus /hdl_top/axi_master2_bus/* +add wave -noupdate -divider spi_slave +add wave -noupdate /uvm_root/uvm_test_top/environment/spi_slave/spi_slave_monitor/txn_stream +add wave -noupdate -group spi_slave_bus /hdl_top/spi_slave_bus/* + +TreeUpdate [SetDefaultTree] +quietly wave cursor active 0 +configure wave -namecolwidth 472 +configure wave -valuecolwidth 100 +configure wave -justifyvalue left +configure wave -signalnamewidth 0 +configure wave -snapdistance 10 +configure wave -datasetprefix 0 +configure wave -rowmargin 4 +configure wave -childrowmargin 2 +configure wave -gridoffset 0 +configure wave -gridperiod 1 +configure wave -griddelta 40 +configure wave -timeline 0 +configure wave -timelineunits ns +update +WaveRestoreZoom {27 ns} {168 ns} + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/project_benches/block_1/sim/xwaves.sigs b/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/project_benches/block_1/sim/xwaves.sigs new file mode 100644 index 00000000..d75f0a57 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/project_benches/block_1/sim/xwaves.sigs @@ -0,0 +1,17 @@ + + + + + +# pragma uvmf custom additional begin + +Group All + +#Top level signals +hdl_top.* +#Add additional levels or individual signals as needed +hdl_top.*.* + +# pragma uvmf custom additional end + + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/project_benches/block_1/tb/parameters/block_1_parameters_pkg.compile b/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/project_benches/block_1/tb/parameters/block_1_parameters_pkg.compile new file mode 100644 index 00000000..e2a26586 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/project_benches/block_1/tb/parameters/block_1_parameters_pkg.compile @@ -0,0 +1,4 @@ +needs: + - $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg_hdl.compile +src: + - block_1_parameters_pkg.sv diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/project_benches/block_1/tb/parameters/block_1_parameters_pkg.sv b/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/project_benches/block_1/tb/parameters/block_1_parameters_pkg.sv new file mode 100644 index 00000000..455ee2fb --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/project_benches/block_1/tb/parameters/block_1_parameters_pkg.sv @@ -0,0 +1,40 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This package contains test level parameters +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// + + +package block_1_parameters_pkg; + + import uvmf_base_pkg_hdl::*; + + // pragma uvmf custom package_imports_additional begin + // pragma uvmf custom package_imports_additional end + + + // These parameters are used to uniquely identify each interface. The monitor_bfm and + // driver_bfm are placed into and retrieved from the uvm_config_db using these string + // names as the field_name. The parameter is also used to enable transaction viewing + // from the command line for selected interfaces using the UVM command line processing. + parameter string apb_master_BFM = "apb_master_BFM"; /* [0] */ + parameter string axi_master1_BFM = "axi_master1_BFM"; /* [1] */ + parameter string axi_master2_BFM = "axi_master2_BFM"; /* [2] */ + parameter string spi_slave_BFM = "spi_slave_BFM"; /* [3] */ + + // pragma uvmf custom package_item_additional begin + // pragma uvmf custom package_item_additional end + +endpackage + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/project_benches/block_1/tb/parameters/block_1_parameters_pkg.vinfo b/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/project_benches/block_1/tb/parameters/block_1_parameters_pkg.vinfo new file mode 100644 index 00000000..8b0adcd9 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/project_benches/block_1/tb/parameters/block_1_parameters_pkg.vinfo @@ -0,0 +1,2 @@ +@use $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg_hdl.vinfo +block_1_parameters_pkg.sv diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/project_benches/block_1/tb/sequences/block_1_sequences_pkg.compile b/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/project_benches/block_1/tb/sequences/block_1_sequences_pkg.compile new file mode 100644 index 00000000..1497180c --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/project_benches/block_1/tb/sequences/block_1_sequences_pkg.compile @@ -0,0 +1,9 @@ +needs: + - $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg.compile + - ../../../../verification_ip/interface_packages/apb_m_pkg/apb_m.compile + - ../../../../verification_ip/interface_packages/axi_m_pkg/axi_m.compile + - ../../../../verification_ip/interface_packages/spi_s_pkg/spi_s.compile + - ../../../../verification_ip/environment_packages/block_1_env_pkg/block_1_env_pkg.compile + - ../parameters/block_1_parameters_pkg.compile +src: + - block_1_sequences_pkg.sv diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/project_benches/block_1/tb/sequences/block_1_sequences_pkg.sv b/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/project_benches/block_1/tb/sequences/block_1_sequences_pkg.sv new file mode 100644 index 00000000..983d03ec --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/project_benches/block_1/tb/sequences/block_1_sequences_pkg.sv @@ -0,0 +1,53 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This package includes all high level sequence classes used +// in the environment. These include utility sequences and top +// level sequences. +// +// CONTAINS: +// - +// - +// +//---------------------------------------------------------------------- +// +//---------------------------------------------------------------------- +// + +package block_1_sequences_pkg; + import uvm_pkg::*; + import uvmf_base_pkg::*; + import apb_m_pkg::*; + import apb_m_pkg_hdl::*; + import axi_m_pkg::*; + import axi_m_pkg_hdl::*; + import spi_s_pkg::*; + import spi_s_pkg_hdl::*; + import block_1_parameters_pkg::*; + import block_1_env_pkg::*; + `include "uvm_macros.svh" + + // pragma uvmf custom package_imports_additional begin + // pragma uvmf custom package_imports_additional end + + `include "src/block_1_bench_sequence_base.svh" + `include "src/register_test_sequence.svh" + `include "src/example_derived_test_sequence.svh" + + // pragma uvmf custom package_item_additional begin + // UVMF_CHANGE_ME : When adding new sequences to the src directory + // be sure to add the sequence file here so that it will be + // compiled as part of the sequence package. Be sure to place + // the new sequence after any base sequences of the new sequence. + // pragma uvmf custom package_item_additional end + +endpackage + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/project_benches/block_1/tb/sequences/block_1_sequences_pkg.vinfo b/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/project_benches/block_1/tb/sequences/block_1_sequences_pkg.vinfo new file mode 100644 index 00000000..b67a290f --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/project_benches/block_1/tb/sequences/block_1_sequences_pkg.vinfo @@ -0,0 +1,8 @@ +@use $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg.vinfo +@use $UVMF_VIP_LIBRARY_HOME/interface_packages/apb_m_pkg/apb_m_pkg.vinfo +@use $UVMF_VIP_LIBRARY_HOME/interface_packages/axi_m_pkg/axi_m_pkg.vinfo +@use $UVMF_VIP_LIBRARY_HOME/interface_packages/spi_s_pkg/spi_s_pkg.vinfo +@use $UVMF_VIP_LIBRARY_HOME/environment_packages/block_1_env_pkg/block_1_env_pkg.vinfo +@use $UVMF_PROJECT_DIR/tb/parameters/block_1_parameters_pkg.vinfo ++incdir+@vinfodir +block_1_sequences_pkg.sv diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/project_benches/block_1/tb/sequences/src/block_1_bench_sequence_base.svh b/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/project_benches/block_1/tb/sequences/src/block_1_bench_sequence_base.svh new file mode 100644 index 00000000..719d0905 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/project_benches/block_1/tb/sequences/src/block_1_bench_sequence_base.svh @@ -0,0 +1,145 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// Description: This file contains the top level and utility sequences +// used by test_top. It can be extended to create derivative top +// level sequences. +// +//---------------------------------------------------------------------- +// +//---------------------------------------------------------------------- +// + + +typedef block_1_env_configuration block_1_env_configuration_t; + +class block_1_bench_sequence_base extends uvmf_sequence_base #(uvm_sequence_item); + + `uvm_object_utils( block_1_bench_sequence_base ); + + // pragma uvmf custom sequences begin + +typedef block_1_env_sequence_base #( + .CONFIG_T(block_1_env_configuration_t) + ) + block_1_env_sequence_base_t; +rand block_1_env_sequence_base_t block_1_env_seq; + + + + // UVMF_CHANGE_ME : Instantiate, construct, and start sequences as needed to create stimulus scenarios. + // Instantiate sequences here + typedef apb_m_random_sequence apb_master_random_seq_t; + apb_master_random_seq_t apb_master_random_seq; + typedef axi_m_random_sequence axi_master1_random_seq_t; + axi_master1_random_seq_t axi_master1_random_seq; + typedef axi_m_random_sequence axi_master2_random_seq_t; + axi_master2_random_seq_t axi_master2_random_seq; + // pragma uvmf custom sequences end + + // Sequencer handles for each active interface in the environment + typedef apb_m_transaction apb_master_transaction_t; + uvm_sequencer #(apb_master_transaction_t) apb_master_sequencer; + typedef axi_m_transaction axi_master1_transaction_t; + uvm_sequencer #(axi_master1_transaction_t) axi_master1_sequencer; + typedef axi_m_transaction axi_master2_transaction_t; + uvm_sequencer #(axi_master2_transaction_t) axi_master2_sequencer; + + + // Top level environment configuration handle + block_1_env_configuration_t top_configuration; + + // Configuration handles to access interface BFM's + apb_m_configuration apb_master_config; + axi_m_configuration axi_master1_config; + axi_m_configuration axi_master2_config; + spi_s_configuration spi_slave_config; + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + // **************************************************************************** + function new( string name = "" ); + super.new( name ); + // Retrieve the configuration handles from the uvm_config_db + + // Retrieve top level configuration handle + if ( !uvm_config_db#(block_1_env_configuration_t)::get(null,UVMF_CONFIGURATIONS, "TOP_ENV_CONFIG",top_configuration) ) begin + `uvm_info("CFG", "*** FATAL *** uvm_config_db::get can not find TOP_ENV_CONFIG. Are you using an older UVMF release than what was used to generate this bench?",UVM_NONE); + `uvm_fatal("CFG", "uvm_config_db#(block_1_env_configuration_t)::get cannot find resource TOP_ENV_CONFIG"); + end + + // Retrieve config handles for all agents + if( !uvm_config_db #( apb_m_configuration )::get( null , UVMF_CONFIGURATIONS , apb_master_BFM , apb_master_config ) ) + `uvm_fatal("CFG" , "uvm_config_db #( apb_m_configuration )::get cannot find resource apb_master_BFM" ) + if( !uvm_config_db #( axi_m_configuration )::get( null , UVMF_CONFIGURATIONS , axi_master1_BFM , axi_master1_config ) ) + `uvm_fatal("CFG" , "uvm_config_db #( axi_m_configuration )::get cannot find resource axi_master1_BFM" ) + if( !uvm_config_db #( axi_m_configuration )::get( null , UVMF_CONFIGURATIONS , axi_master2_BFM , axi_master2_config ) ) + `uvm_fatal("CFG" , "uvm_config_db #( axi_m_configuration )::get cannot find resource axi_master2_BFM" ) + if( !uvm_config_db #( spi_s_configuration )::get( null , UVMF_CONFIGURATIONS , spi_slave_BFM , spi_slave_config ) ) + `uvm_fatal("CFG" , "uvm_config_db #( spi_s_configuration )::get cannot find resource spi_slave_BFM" ) + + // Assign the sequencer handles from the handles within agent configurations + apb_master_sequencer = apb_master_config.get_sequencer(); + axi_master1_sequencer = axi_master1_config.get_sequencer(); + axi_master2_sequencer = axi_master2_config.get_sequencer(); + + + + // pragma uvmf custom new begin + // pragma uvmf custom new end + + endfunction + + // **************************************************************************** + virtual task body(); + // pragma uvmf custom body begin + + // Construct sequences here + + block_1_env_seq = block_1_env_sequence_base_t::type_id::create("block_1_env_seq"); + + apb_master_random_seq = apb_master_random_seq_t::type_id::create("apb_master_random_seq"); + axi_master1_random_seq = axi_master1_random_seq_t::type_id::create("axi_master1_random_seq"); + axi_master2_random_seq = axi_master2_random_seq_t::type_id::create("axi_master2_random_seq"); + fork + apb_master_config.wait_for_reset(); + axi_master1_config.wait_for_reset(); + axi_master2_config.wait_for_reset(); + spi_slave_config.wait_for_reset(); + join + // Start RESPONDER sequences here + fork + join_none + // Start INITIATOR sequences here + fork + repeat (25) apb_master_random_seq.start(apb_master_sequencer); + repeat (25) axi_master1_random_seq.start(axi_master1_sequencer); + repeat (25) axi_master2_random_seq.start(axi_master2_sequencer); + join + +block_1_env_seq.start(top_configuration.vsqr); + + // UVMF_CHANGE_ME : Extend the simulation XXX number of clocks after + // the last sequence to allow for the last sequence item to flow + // through the design. + fork + apb_master_config.wait_for_num_clocks(400); + axi_master1_config.wait_for_num_clocks(400); + axi_master2_config.wait_for_num_clocks(400); + spi_slave_config.wait_for_num_clocks(400); + join + + // pragma uvmf custom body end + endtask + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/project_benches/block_1/tb/sequences/src/example_derived_test_sequence.svh b/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/project_benches/block_1/tb/sequences/src/example_derived_test_sequence.svh new file mode 100644 index 00000000..b4127d2f --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/project_benches/block_1/tb/sequences/src/example_derived_test_sequence.svh @@ -0,0 +1,30 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +// +//---------------------------------------------------------------------- +// +// DESCRIPTION: This file contains the top level sequence used in example_derived_test. +// It is an example of a sequence that is extended from %(benchName)_bench_sequence_base +// and can override %(benchName)_bench_sequence_base. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// + +class example_derived_test_sequence extends block_1_bench_sequence_base; + + `uvm_object_utils( example_derived_test_sequence ); + + function new(string name = "" ); + super.new(name); + endfunction + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/project_benches/block_1/tb/sequences/src/register_test_sequence.svh b/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/project_benches/block_1/tb/sequences/src/register_test_sequence.svh new file mode 100644 index 00000000..dd9e3574 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/project_benches/block_1/tb/sequences/src/register_test_sequence.svh @@ -0,0 +1,59 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This file contains the top level sequence used in register_test. +// It uses the UVM built in register test. Specific UVM built-in tests can be +// selected in the body task. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// + +class register_test_sequence extends block_1_bench_sequence_base; + + `uvm_object_utils( register_test_sequence ); + + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + function new(string name = "" ); + super.new(name); + endfunction + + // **************************************************************************** + virtual task body(); + + // Reset the DUT + fork + // pragma uvmf custom register_test_reset begin + // UVMF_CHANGE_ME + // Select the desired wait_for_reset or provide custom mechanism. + // fork-join for this code block may be unnecessary based on your situation. + apb_master_config.wait_for_reset(); + axi_master1_config.wait_for_reset(); + axi_master2_config.wait_for_reset(); + spi_slave_config.wait_for_reset(); + // pragma uvmf custom register_test_reset end + join + + // pragma uvmf custom register_test_setup begin + // UVMF_CHANGE_ME perform potentially necessary operations before running the sequence. + // pragma uvmf custom register_test_setup end + + // pragma uvmf custom register_test_operation begin + // UVMF_CHANGE_ME Perform your custom register test + // pragma uvmf custom register_test_operation end + + endtask + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/project_benches/block_1/tb/testbench/hdl_top.compile b/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/project_benches/block_1/tb/testbench/hdl_top.compile new file mode 100644 index 00000000..09b570fb --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/project_benches/block_1/tb/testbench/hdl_top.compile @@ -0,0 +1,11 @@ +incdir: + - ${uvm_path}/src + - . +needs: + - $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg_hdl.compile + - ../parameters/block_1_parameters_pkg.compile + - ../../../../verification_ip/interface_packages/apb_m_pkg/apb_m_hdl.compile + - ../../../../verification_ip/interface_packages/axi_m_pkg/axi_m_hdl.compile + - ../../../../verification_ip/interface_packages/spi_s_pkg/spi_s_hdl.compile +src: + - hdl_top.sv diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/project_benches/block_1/tb/testbench/hdl_top.sv b/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/project_benches/block_1/tb/testbench/hdl_top.sv new file mode 100644 index 00000000..d8645a94 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/project_benches/block_1/tb/testbench/hdl_top.sv @@ -0,0 +1,117 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// Description: This top level module instantiates all synthesizable +// static content. This and tb_top.sv are the two top level modules +// of the simulation. +// +// This module instantiates the following: +// DUT: The Design Under Test +// Interfaces: Signal bundles that contain signals connected to DUT +// Driver BFM's: BFM's that actively drive interface signals +// Monitor BFM's: BFM's that passively monitor interface signals +// +//---------------------------------------------------------------------- + +//---------------------------------------------------------------------- +// + +module hdl_top; + +import block_1_parameters_pkg::*; +import uvmf_base_pkg_hdl::*; + + // pragma attribute hdl_top partition_module_xrtl +// pragma uvmf custom clock_generator begin + bit clk; + // Instantiate a clk driver + // tbx clkgen + initial begin + clk = 0; + #9ns; + forever begin + clk = ~clk; + #5ns; + end + end +// pragma uvmf custom clock_generator end + +// pragma uvmf custom reset_generator begin + bit rst; + // Instantiate a rst driver + // tbx clkgen + initial begin + rst = 1; + #200ns; + rst = 0; + end +// pragma uvmf custom reset_generator end + + // pragma uvmf custom module_item_additional begin + // pragma uvmf custom module_item_additional end + + // Instantiate the signal bundle, monitor bfm and driver bfm for each interface. + // The signal bundle, _if, contains signals to be connected to the DUT. + // The monitor, monitor_bfm, observes the bus, _if, and captures transactions. + // The driver, driver_bfm, drives transactions onto the bus, _if. + apb_m_if apb_master_bus( + // pragma uvmf custom apb_master_bus_connections begin + .pclk(clk), .presetn(rst) + // pragma uvmf custom apb_master_bus_connections end + ); + axi_m_if axi_master1_bus( + // pragma uvmf custom axi_master1_bus_connections begin + .axi_clk(clk), .rst(rst) + // pragma uvmf custom axi_master1_bus_connections end + ); + axi_m_if axi_master2_bus( + // pragma uvmf custom axi_master2_bus_connections begin + .axi_clk(clk), .rst(rst) + // pragma uvmf custom axi_master2_bus_connections end + ); + spi_s_if spi_slave_bus( + // pragma uvmf custom spi_slave_bus_connections begin + .sck(clk), .rst(rst) + // pragma uvmf custom spi_slave_bus_connections end + ); + apb_m_monitor_bfm apb_master_mon_bfm(apb_master_bus.monitor_port); + axi_m_monitor_bfm axi_master1_mon_bfm(axi_master1_bus.monitor_port); + axi_m_monitor_bfm axi_master2_mon_bfm(axi_master2_bus.monitor_port); + spi_s_monitor_bfm spi_slave_mon_bfm(spi_slave_bus.monitor_port); + apb_m_driver_bfm apb_master_drv_bfm(apb_master_bus.initiator_port); + axi_m_driver_bfm axi_master1_drv_bfm(axi_master1_bus.initiator_port); + axi_m_driver_bfm axi_master2_drv_bfm(axi_master2_bus.initiator_port); + + // pragma uvmf custom dut_instantiation begin + // UVMF_CHANGE_ME : Add DUT and connect to signals in _bus interfaces listed above + // Instantiate your DUT here + // These DUT's instantiated to show verilog and vhdl instantiation + verilog_dut dut_verilog( .clk(clk), .rst(rst), .in_signal(vhdl_to_verilog_signal), .out_signal(verilog_to_vhdl_signal)); + vhdl_dut dut_vhdl ( .clk(clk), .rst(rst), .in_signal(verilog_to_vhdl_signal), .out_signal(vhdl_to_verilog_signal)); + // pragma uvmf custom dut_instantiation end + + initial begin // tbx vif_binding_block + import uvm_pkg::uvm_config_db; + // The monitor_bfm and driver_bfm for each interface is placed into the uvm_config_db. + // They are placed into the uvm_config_db using the string names defined in the parameters package. + // The string names are passed to the agent configurations by test_top through the top level configuration. + // They are retrieved by the agents configuration class for use by the agent. + uvm_config_db #( virtual apb_m_monitor_bfm )::set( null , UVMF_VIRTUAL_INTERFACES , apb_master_BFM , apb_master_mon_bfm ); + uvm_config_db #( virtual axi_m_monitor_bfm )::set( null , UVMF_VIRTUAL_INTERFACES , axi_master1_BFM , axi_master1_mon_bfm ); + uvm_config_db #( virtual axi_m_monitor_bfm )::set( null , UVMF_VIRTUAL_INTERFACES , axi_master2_BFM , axi_master2_mon_bfm ); + uvm_config_db #( virtual spi_s_monitor_bfm )::set( null , UVMF_VIRTUAL_INTERFACES , spi_slave_BFM , spi_slave_mon_bfm ); + uvm_config_db #( virtual apb_m_driver_bfm )::set( null , UVMF_VIRTUAL_INTERFACES , apb_master_BFM , apb_master_drv_bfm ); + uvm_config_db #( virtual axi_m_driver_bfm )::set( null , UVMF_VIRTUAL_INTERFACES , axi_master1_BFM , axi_master1_drv_bfm ); + uvm_config_db #( virtual axi_m_driver_bfm )::set( null , UVMF_VIRTUAL_INTERFACES , axi_master2_BFM , axi_master2_drv_bfm ); + end + +endmodule + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/project_benches/block_1/tb/testbench/hdl_top.vinfo b/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/project_benches/block_1/tb/testbench/hdl_top.vinfo new file mode 100644 index 00000000..43c7c76e --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/project_benches/block_1/tb/testbench/hdl_top.vinfo @@ -0,0 +1,7 @@ +@use $UVMF_PROJECT_DIR/rtl/verilog/verilog_dut.vinfo +@use $UVMF_PROJECT_DIR/tb/parameters/block_1_parameters_pkg.vinfo +@use $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg_hdl.vinfo +@use $UVMF_VIP_LIBRARY_HOME/interface_packages/apb_m_pkg/apb_m_bfm.vinfo +@use $UVMF_VIP_LIBRARY_HOME/interface_packages/axi_m_pkg/axi_m_bfm.vinfo +@use $UVMF_VIP_LIBRARY_HOME/interface_packages/spi_s_pkg/spi_s_bfm.vinfo +hdl_top.sv diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/project_benches/block_1/tb/testbench/hvl_top.compile b/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/project_benches/block_1/tb/testbench/hvl_top.compile new file mode 100644 index 00000000..d8d273c1 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/project_benches/block_1/tb/testbench/hvl_top.compile @@ -0,0 +1,7 @@ +incdir: + - ${uvm_path}/src + - . +needs: + - ../tests/block_1_tests_pkg.compile +src: + - hvl_top.sv diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/project_benches/block_1/tb/testbench/hvl_top.sv b/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/project_benches/block_1/tb/testbench/hvl_top.sv new file mode 100644 index 00000000..89ae61f4 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/project_benches/block_1/tb/testbench/hvl_top.sv @@ -0,0 +1,33 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +// +//---------------------------------------------------------------------- +// +// DESCRIPTION: This module loads the test package and starts the UVM phases. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// + +module hvl_top; + +import uvm_pkg::*; +import block_1_tests_pkg::*; + + // pragma uvmf custom module_item_additional begin + // pragma uvmf custom module_item_additional end + + initial begin + $timeformat(-9,3,"ns",5); + run_test(); + end + +endmodule + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/project_benches/block_1/tb/testbench/hvl_top.vinfo b/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/project_benches/block_1/tb/testbench/hvl_top.vinfo new file mode 100644 index 00000000..7bc43d3a --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/project_benches/block_1/tb/testbench/hvl_top.vinfo @@ -0,0 +1,2 @@ +@use $UVMF_PROJECT_DIR/tb/tests/block_1_tests_pkg.vinfo +hvl_top.sv diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/project_benches/block_1/tb/testbench/top_filelist_hdl.f b/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/project_benches/block_1/tb/testbench/top_filelist_hdl.f new file mode 100644 index 00000000..1e9dab65 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/project_benches/block_1/tb/testbench/top_filelist_hdl.f @@ -0,0 +1,3 @@ +$UVMF_PROJECT_DIR/tb/testbench/hdl_top.sv +// pragma uvmf custom additional begin +// pragma uvmf custom additional end diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/project_benches/block_1/tb/testbench/top_filelist_hvl.f b/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/project_benches/block_1/tb/testbench/top_filelist_hvl.f new file mode 100644 index 00000000..42383ab2 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/project_benches/block_1/tb/testbench/top_filelist_hvl.f @@ -0,0 +1,3 @@ +$UVMF_PROJECT_DIR/tb/testbench/hvl_top.sv +// pragma uvmf custom additional begin +// pragma uvmf custom additional end diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/project_benches/block_1/tb/tests/block_1_tests_pkg.compile b/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/project_benches/block_1/tb/tests/block_1_tests_pkg.compile new file mode 100644 index 00000000..ccf235f0 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/project_benches/block_1/tb/tests/block_1_tests_pkg.compile @@ -0,0 +1,10 @@ +needs: + - $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg.compile + - ../../../../verification_ip/interface_packages/apb_m_pkg/apb_m.compile + - ../../../../verification_ip/interface_packages/axi_m_pkg/axi_m.compile + - ../../../../verification_ip/interface_packages/spi_s_pkg/spi_s.compile + - ../../../../verification_ip/environment_packages/block_1_env_pkg/block_1_env_pkg.compile + - ../parameters/block_1_parameters_pkg.compile + - ../sequences/block_1_sequences_pkg.compile +src: + - block_1_tests_pkg.sv diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/project_benches/block_1/tb/tests/block_1_tests_pkg.sv b/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/project_benches/block_1/tb/tests/block_1_tests_pkg.sv new file mode 100644 index 00000000..933ace9a --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/project_benches/block_1/tb/tests/block_1_tests_pkg.sv @@ -0,0 +1,56 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This package contains all tests currently written for +// the simulation project. Once compiled, any test can be selected +// from the vsim command line using +UVM_TESTNAME=yourTestNameHere +// +// CONTAINS: +// - +// - +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// + +package block_1_tests_pkg; + + import uvm_pkg::*; + import uvmf_base_pkg::*; + import block_1_parameters_pkg::*; + import block_1_env_pkg::*; + import block_1_sequences_pkg::*; + import apb_m_pkg::*; + import apb_m_pkg_hdl::*; + import axi_m_pkg::*; + import axi_m_pkg_hdl::*; + import spi_s_pkg::*; + import spi_s_pkg_hdl::*; + + + `include "uvm_macros.svh" + + // pragma uvmf custom package_imports_additional begin + // pragma uvmf custom package_imports_additional end + + `include "src/test_top.svh" + `include "src/register_test.svh" + `include "src/example_derived_test.svh" + + // pragma uvmf custom package_item_additional begin + // UVMF_CHANGE_ME : When adding new tests to the src directory + // be sure to add the test file here so that it will be + // compiled as part of the test package. Be sure to place + // the new test after any base tests of the new test. + // pragma uvmf custom package_item_additional end + +endpackage + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/project_benches/block_1/tb/tests/block_1_tests_pkg.vinfo b/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/project_benches/block_1/tb/tests/block_1_tests_pkg.vinfo new file mode 100644 index 00000000..9fe7bfbf --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/project_benches/block_1/tb/tests/block_1_tests_pkg.vinfo @@ -0,0 +1,9 @@ +@use $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg.vinfo +@use $UVMF_VIP_LIBRARY_HOME/interface_packages/apb_m_pkg/apb_m_pkg.vinfo +@use $UVMF_VIP_LIBRARY_HOME/interface_packages/axi_m_pkg/axi_m_pkg.vinfo +@use $UVMF_VIP_LIBRARY_HOME/interface_packages/spi_s_pkg/spi_s_pkg.vinfo +@use $UVMF_VIP_LIBRARY_HOME/environment_packages/block_1_env_pkg/block_1_env_pkg.vinfo +@use $UVMF_PROJECT_DIR/tb/parameters/block_1_parameters_pkg.vinfo +@use $UVMF_PROJECT_DIR/tb/sequences/block_1_sequences_pkg.vinfo ++incdir+@vinfodir +block_1_tests_pkg.sv diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/project_benches/block_1/tb/tests/src/example_derived_test.svh b/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/project_benches/block_1/tb/tests/src/example_derived_test.svh new file mode 100644 index 00000000..346ac7c4 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/project_benches/block_1/tb/tests/src/example_derived_test.svh @@ -0,0 +1,43 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This test extends test_top and makes +// changes to test_top using the UVM factory type_override: +// +// Test scenario: +// This is a template test that can be used to create future tests. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// + +class example_derived_test extends test_top; + + `uvm_component_utils( example_derived_test ); + + function new( string name = "", uvm_component parent = null ); + super.new( name, parent ); + endfunction + + virtual function void build_phase(uvm_phase phase); + // The factory override below is an example of how to replace the block_1_bench_sequence_base + // sequence with the example_derived_test_sequence. + block_1_bench_sequence_base::type_id::set_type_override(example_derived_test_sequence::get_type()); + // Execute the build_phase of test_top AFTER all factory overrides have been created. + super.build_phase(phase); + // pragma uvmf custom configuration_settings_post_randomize begin + // UVMF_CHANGE_ME Test specific configuration values can be set here. + // The configuration structure has already been randomized. + // pragma uvmf custom configuration_settings_post_randomize end + endfunction + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/project_benches/block_1/tb/tests/src/register_test.svh b/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/project_benches/block_1/tb/tests/src/register_test.svh new file mode 100644 index 00000000..ae1d329c --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/project_benches/block_1/tb/tests/src/register_test.svh @@ -0,0 +1,40 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This test extends test_top and makes +// changes to test_top using the UVM factory type_override: +// +// Test scenario: +// This is a template test that can be used to create future tests. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// + +class register_test extends test_top; + + `uvm_component_utils( register_test ); + + function new( string name = "", uvm_component parent = null ); + super.new( name, parent ); + endfunction + + virtual function void build_phase(uvm_phase phase); + // The factory override below replaces the block_1_bench_sequence_base + // sequence with the register_test_sequence. + block_1_bench_sequence_base::type_id::set_type_override(register_test_sequence::get_type()); + // Execute the build_phase of test_top AFTER all factory overrides have been created. + super.build_phase(phase); + endfunction + + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/project_benches/block_1/tb/tests/src/test_top.svh b/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/project_benches/block_1/tb/tests/src/test_top.svh new file mode 100644 index 00000000..108d124e --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/project_benches/block_1/tb/tests/src/test_top.svh @@ -0,0 +1,82 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// Description: This top level UVM test is the base class for all +// future tests created for this project. +// +// This test class contains: +// Configuration: The top level configuration for the project. +// Environment: The top level environment for the project. +// Top_level_sequence: The top level sequence for the project. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// + +typedef block_1_env_configuration block_1_env_configuration_t; +typedef block_1_environment block_1_environment_t; + +class test_top extends uvmf_test_base #(.CONFIG_T(block_1_env_configuration_t), + .ENV_T(block_1_environment_t), + .TOP_LEVEL_SEQ_T(block_1_bench_sequence_base)); + + `uvm_component_utils( test_top ); + + + + string interface_names[] = { + apb_master_BFM /* apb_master [0] */ , + axi_master1_BFM /* axi_master1 [1] */ , + axi_master2_BFM /* axi_master2 [2] */ , + spi_slave_BFM /* spi_slave [3] */ +}; + +uvmf_active_passive_t interface_activities[] = { + ACTIVE /* apb_master [0] */ , + ACTIVE /* axi_master1 [1] */ , + ACTIVE /* axi_master2 [2] */ , + PASSIVE /* spi_slave [3] */ }; + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + // **************************************************************************** + // FUNCTION: new() + // This is the standard systemVerilog constructor. All components are + // constructed in the build_phase to allow factory overriding. + // + function new( string name = "", uvm_component parent = null ); + super.new( name ,parent ); + endfunction + + + + // **************************************************************************** + // FUNCTION: build_phase() + // The construction of the configuration and environment classes is done in + // the build_phase of uvmf_test_base. Once the configuraton and environment + // classes are built then the initialize call is made to perform the + // following: + // Monitor and driver BFM virtual interface handle passing into agents + // Set the active/passive state for each agent + // Once this build_phase completes, the build_phase of the environment is + // executed which builds the agents. + // + virtual function void build_phase(uvm_phase phase); +// pragma uvmf custom build_phase_pre_super begin +// pragma uvmf custom build_phase_pre_super end + super.build_phase(phase); + // pragma uvmf custom configuration_settings_post_randomize begin + // pragma uvmf custom configuration_settings_post_randomize end + configuration.initialize(NA, "uvm_test_top.environment", interface_names, null, interface_activities); + endfunction + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/project_benches/block_1/yaml/block_1_bench.yaml b/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/project_benches/block_1/yaml/block_1_bench.yaml new file mode 100644 index 00000000..81d1e38d --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/project_benches/block_1/yaml/block_1_bench.yaml @@ -0,0 +1,21 @@ +uvmf: + benches: + block_1: + active_passive: + - bfm_name: apb_master + value: ACTIVE + - bfm_name: axi_master1 + value: ACTIVE + - bfm_name: axi_master2 + value: ACTIVE + - bfm_name: spi_slave + value: PASSIVE + active_passive_default: ACTIVE + clock_half_period: 5ns + clock_phase_offset: 9ns + existing_library_component: 'True' + interface_params: [] + reset_assertion_level: 'True' + reset_duration: 200ns + top_env: block_1 + use_dpi_link: 'False' diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/verification_ip/environment_packages/block_1_env_pkg/.project b/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/verification_ip/environment_packages/block_1_env_pkg/.project new file mode 100644 index 00000000..db755a2e --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/verification_ip/environment_packages/block_1_env_pkg/.project @@ -0,0 +1,32 @@ + + + block_1_env_pkg + + + + + + org.python.pydev.PyDevBuilder + + + + + net.sf.sveditor.core.SVProjectBuilder + + + + + + net.sf.sveditor.core.SVNature + org.python.pydev.pythonNature + + + + + + UVMF_VIP_LIBRARY_HOME + $%7BPARENT-2-PROJECT_LOC%7D + + + + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/verification_ip/environment_packages/block_1_env_pkg/.svproject b/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/verification_ip/environment_packages/block_1_env_pkg/.svproject new file mode 100644 index 00000000..148d5d69 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/verification_ip/environment_packages/block_1_env_pkg/.svproject @@ -0,0 +1,16 @@ + + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/verification_ip/environment_packages/block_1_env_pkg/Makefile b/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/verification_ip/environment_packages/block_1_env_pkg/Makefile new file mode 100644 index 00000000..d0b7efd8 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/verification_ip/environment_packages/block_1_env_pkg/Makefile @@ -0,0 +1,56 @@ +# block_1 environment packages source and make target + +# pragma uvmf custom additional begin +# pragma uvmf custom additional end + +# Include all requisite sub-environment package targets for this bench + +block_1_ENV_PKG =\ + $(UVMF_VIP_LIBRARY_HOME)/environment_packages/block_1_env_pkg/block_1_env_pkg.sv + +COMP_block_1_PKG_TGT_0 = q_comp_block_1_env_pkg +COMP_block_1_PKG_TGT_1 = v_comp_block_1_env_pkg +COMP_block_1_PKG_TGT = $(COMP_block_1_PKG_TGT_$(USE_VELOCE)) + +comp_block_1_env_pkg: $(COMP_block_1_PKG_TGT) + +q_comp_block_1_env_pkg: + $(HVL_COMP_CMD) +incdir+$(UVMF_VIP_LIBRARY_HOME)/environment_packages/block_1_env_pkg $(block_1_ENV_PKG) + +v_comp_block_1_env_pkg: q_comp_block_1_env_pkg + $(VELANALYZE_HVL_CMD) +incdir+$(UVMF_VIP_LIBRARY_HOME)/environment_packages/block_1_env_pkg $(block_1_ENV_PKG) + + + +ifeq ($(MTI_VCO_MODE),64) + GCC_COMP_ARCH = -m64 +else + GCC_COMP_ARCH = -m32 +endif + +export block_1_ENV_DPI_SRC ?= $(UVMF_VIP_LIBRARY_HOME)/environment_packages/block_1_env_pkg/dpi + +C_FILE_COMPILE_LIST_block_1_env_pkg = \ + +O_FILE_COMPILE_LIST_block_1_env_pkg = $(notdir $(C_FILE_COMPILE_LIST_block_1_env_pkg:.c=.o)) + +GCC_COMP_ARGS_block_1_env_pkg += -I$(block_1_ENV_DPI_SRC) \ + -fPIC + +GCC_COMP_ARGS_block_1_env_pkg += $(block_1_ENV_GCC_COMP_ARGUMENTS) + +GCC_LINK_ARGS_block_1_env_pkg += \ + \ + -o .so + +comp_block_1_env_pkg_c_files: + @echo "--------------------------------" + @echo "Compiling Environment C source" + @echo "--------------------------------" + gcc $(GCC_COMP_ARCH) $(GCC_COMP_ARGS_block_1_env_pkg) $(C_FILE_COMPILE_LIST_block_1_env_pkg) + @echo "--------------------------------" + @echo "Linking Environment C objects into a shared object" + @echo "--------------------------------" + gcc $(GCC_COMP_ARCH) $(GCC_LINK_ARGS_block_1_env_pkg) $(O_FILE_COMPILE_LIST_block_1_env_pkg) + @echo "--------------------------------" + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/verification_ip/environment_packages/block_1_env_pkg/block_1_env_pkg.compile b/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/verification_ip/environment_packages/block_1_env_pkg/block_1_env_pkg.compile new file mode 100644 index 00000000..4c6f4844 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/verification_ip/environment_packages/block_1_env_pkg/block_1_env_pkg.compile @@ -0,0 +1,9 @@ +needs: + - $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg.compile + - ../../../verification_ip/interface_packages/apb_m_pkg/apb_m_hvl.compile + - ../../../verification_ip/interface_packages/axi_m_pkg/axi_m_hvl.compile + - ../../../verification_ip/interface_packages/spi_s_pkg/spi_s_hvl.compile + +src: + - block_1_env_pkg.sv + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/verification_ip/environment_packages/block_1_env_pkg/block_1_env_pkg.sv b/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/verification_ip/environment_packages/block_1_env_pkg/block_1_env_pkg.sv new file mode 100644 index 00000000..490ba8f1 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/verification_ip/environment_packages/block_1_env_pkg/block_1_env_pkg.sv @@ -0,0 +1,63 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// PACKAGE: This file defines all of the files contained in the +// environment package that will run on the host simulator. +// +// CONTAINS: +// - +// - +// - +// - +// - +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +package block_1_env_pkg; + + import uvm_pkg::*; + `include "uvm_macros.svh" + import uvmf_base_pkg::*; + import apb_m_pkg::*; + import apb_m_pkg_hdl::*; + import axi_m_pkg::*; + import axi_m_pkg_hdl::*; + import spi_s_pkg::*; + import spi_s_pkg_hdl::*; + + `uvm_analysis_imp_decl(_axi_2_ae) + `uvm_analysis_imp_decl(_apb_ae) + `uvm_analysis_imp_decl(_axi_1_ae) + `uvm_analysis_imp_decl(_sco_from_pre_ae) + `uvm_analysis_imp_decl(_spi_ae) + + // pragma uvmf custom package_imports_additional begin + // pragma uvmf custom package_imports_additional end + + // Parameters defined as HVL parameters + + `include "src/block_1_env_typedefs.svh" + `include "src/block_1_env_configuration.svh" + `include "src/block_1_predictor.svh" + `include "src/block_1_scoreboard.svh" + `include "src/block_1_environment.svh" + `include "src/block_1_env_sequence_base.svh" + + // pragma uvmf custom package_item_additional begin + // UVMF_CHANGE_ME : When adding new environment level sequences to the src directory + // be sure to add the sequence file here so that it will be + // compiled as part of the environment package. Be sure to place + // the new sequence after any base sequence of the new sequence. + // pragma uvmf custom package_item_additional end + +endpackage + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/verification_ip/environment_packages/block_1_env_pkg/block_1_env_pkg.vinfo b/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/verification_ip/environment_packages/block_1_env_pkg/block_1_env_pkg.vinfo new file mode 100644 index 00000000..c2733a14 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/verification_ip/environment_packages/block_1_env_pkg/block_1_env_pkg.vinfo @@ -0,0 +1,6 @@ +@use $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg.vinfo +@use $UVMF_VIP_LIBRARY_HOME/interface_packages/apb_m_pkg/apb_m_pkg.vinfo +@use $UVMF_VIP_LIBRARY_HOME/interface_packages/axi_m_pkg/axi_m_pkg.vinfo +@use $UVMF_VIP_LIBRARY_HOME/interface_packages/spi_s_pkg/spi_s_pkg.vinfo ++incdir+@vinfodir +block_1_env_pkg.sv diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/verification_ip/environment_packages/block_1_env_pkg/block_1_env_pkg_sve.F b/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/verification_ip/environment_packages/block_1_env_pkg/block_1_env_pkg_sve.F new file mode 100644 index 00000000..c6edfc2e --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/verification_ip/environment_packages/block_1_env_pkg/block_1_env_pkg_sve.F @@ -0,0 +1,12 @@ + +// UVM ++incdir+${UVM_HOME}/src +${UVM_HOME}/src/uvm_pkg.sv + +// Common UVMF files +-f ${UVMF_HOME}/common/common_sve.f + +// Sub-Environments + ++incdir+. +./block_1_env_pkg.sv diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/verification_ip/environment_packages/block_1_env_pkg/compile.do b/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/verification_ip/environment_packages/block_1_env_pkg/compile.do new file mode 100644 index 00000000..bac5463f --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/verification_ip/environment_packages/block_1_env_pkg/compile.do @@ -0,0 +1,12 @@ +# Tcl do file for compile of block_1 interface + +# pragma uvmf custom additional begin +# pragma uvmf custom additional end + + + +quietly set cmd [format "vlog -timescale 1ps/1ps +incdir+%s/environment_packages/block_1_env_pkg" $env(UVMF_VIP_LIBRARY_HOME)] +quietly set cmd [format "%s %s/environment_packages/block_1_env_pkg/block_1_env_pkg.sv" $cmd $env(UVMF_VIP_LIBRARY_HOME)] +eval $cmd + + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/verification_ip/environment_packages/block_1_env_pkg/src/block_1_env_configuration.svh b/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/verification_ip/environment_packages/block_1_env_pkg/src/block_1_env_configuration.svh new file mode 100644 index 00000000..56f80daa --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/verification_ip/environment_packages/block_1_env_pkg/src/block_1_env_configuration.svh @@ -0,0 +1,162 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: THis is the configuration for the block_1 environment. +// it contains configuration classes for each agent. It also contains +// environment level configuration variables. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class block_1_env_configuration +extends uvmf_environment_configuration_base; + + `uvm_object_utils( block_1_env_configuration ) + + bit has_scoreboard; + +//Constraints for the configuration variables: + + + covergroup block_1_configuration_cg; + // pragma uvmf custom covergroup begin + option.auto_bin_max=1024; + coverpoint has_scoreboard; + // pragma uvmf custom covergroup end + endgroup + + + typedef apb_m_configuration apb_master_config_t; + rand apb_master_config_t apb_master_config; + + typedef axi_m_configuration axi_master1_config_t; + rand axi_master1_config_t axi_master1_config; + + typedef axi_m_configuration axi_master2_config_t; + rand axi_master2_config_t axi_master2_config; + + typedef spi_s_configuration spi_slave_config_t; + rand spi_slave_config_t spi_slave_config; + + + + + typedef uvmf_virtual_sequencer_base #(.CONFIG_T(block_1_env_configuration)) block_1_vsqr_t; + block_1_vsqr_t vsqr; + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + +// **************************************************************************** +// FUNCTION : new() +// This function is the standard SystemVerilog constructor. +// This function constructs the configuration object for each agent in the environment. +// + function new( string name = "" ); + super.new( name ); + + + apb_master_config = apb_master_config_t::type_id::create("apb_master_config"); + axi_master1_config = axi_master1_config_t::type_id::create("axi_master1_config"); + axi_master2_config = axi_master2_config_t::type_id::create("axi_master2_config"); + spi_slave_config = spi_slave_config_t::type_id::create("spi_slave_config"); + + + block_1_configuration_cg=new; + `uvm_warning("COVERAGE_MODEL_REVIEW", "A covergroup has been constructed which may need review because of either generation or re-generation with merging. Please note that configuration variables added as a result of re-generation and merging are not automatically added to the covergroup. Remove this warning after the covergroup has been reviewed.") + + // pragma uvmf custom new begin + // pragma uvmf custom new end + endfunction + +// **************************************************************************** +// FUNCTION : set_vsqr() +// This function is used to assign the vsqr handle. + virtual function void set_vsqr( block_1_vsqr_t vsqr); + this.vsqr = vsqr; + endfunction : set_vsqr + +// **************************************************************************** +// FUNCTION: post_randomize() +// This function is automatically called after the randomize() function +// is executed. +// + function void post_randomize(); + super.post_randomize(); + // pragma uvmf custom post_randomize begin + // pragma uvmf custom post_randomize end + endfunction + +// **************************************************************************** +// FUNCTION: convert2string() +// This function converts all variables in this class to a single string for +// logfile reporting. This function concatenates the convert2string result for +// each agent configuration in this configuration class. +// + virtual function string convert2string(); + // pragma uvmf custom convert2string begin + return { + $sformatf("has_scoreboard:0x%x ",has_scoreboard), + "\n", apb_master_config.convert2string, + "\n", axi_master1_config.convert2string, + "\n", axi_master2_config.convert2string, + "\n", spi_slave_config.convert2string + + + }; + // pragma uvmf custom convert2string end + endfunction +// **************************************************************************** +// FUNCTION: initialize(); +// This function configures each interface agents configuration class. The +// sim level determines the active/passive state of the agent. The environment_path +// identifies the hierarchy down to and including the instantiation name of the +// environment for this configuration class. Each instance of the environment +// has its own configuration class. The string interface names are used by +// the agent configurations to identify the virtual interface handle to pull from +// the uvm_config_db. +// + function void initialize(uvmf_sim_level_t sim_level, + string environment_path, + string interface_names[], + uvm_reg_block register_model = null, + uvmf_active_passive_t interface_activity[] = {} + ); + + super.initialize(sim_level, environment_path, interface_names, register_model, interface_activity); + + + + // Interface initialization for local agents + apb_master_config.initialize( interface_activity[0], {environment_path,".apb_master"}, interface_names[0]); + apb_master_config.initiator_responder = INITIATOR; + // apb_master_config.has_coverage = 1; + axi_master1_config.initialize( interface_activity[1], {environment_path,".axi_master1"}, interface_names[1]); + axi_master1_config.initiator_responder = INITIATOR; + // axi_master1_config.has_coverage = 1; + axi_master2_config.initialize( interface_activity[2], {environment_path,".axi_master2"}, interface_names[2]); + axi_master2_config.initiator_responder = INITIATOR; + // axi_master2_config.has_coverage = 1; + spi_slave_config.initialize( interface_activity[3], {environment_path,".spi_slave"}, interface_names[3]); + spi_slave_config.initiator_responder = RESPONDER; + // spi_slave_config.has_coverage = 1; + + + + + + // pragma uvmf custom initialize begin + // pragma uvmf custom initialize end + + endfunction + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/verification_ip/environment_packages/block_1_env_pkg/src/block_1_env_sequence_base.svh b/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/verification_ip/environment_packages/block_1_env_pkg/src/block_1_env_sequence_base.svh new file mode 100644 index 00000000..949ecd3c --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/verification_ip/environment_packages/block_1_env_pkg/src/block_1_env_sequence_base.svh @@ -0,0 +1,83 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This file contains environment level sequences that will +// be reused from block to top level simulations. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class block_1_env_sequence_base #( + type CONFIG_T + ) extends uvmf_virtual_sequence_base #(.CONFIG_T(CONFIG_T)); + + + `uvm_object_param_utils( block_1_env_sequence_base #( + CONFIG_T + ) ); + + +// This block_1_env_sequence_base contains a handle to a block_1_env_configuration object +// named configuration. This configuration variable contains a handle to each +// sequencer within each agent within this environment and any sub-environments. +// The configuration object handle is automatically assigned in the pre_body in the +// base class of this sequence. The configuration handle is retrieved from the +// virtual sequencer that this sequence is started on. +// Available sequencer handles within the environment configuration: + + // Initiator agent sequencers in block_1_environment: + // configuration.apb_master_config.sequencer + // configuration.axi_master1_config.sequencer + // configuration.axi_master2_config.sequencer + + // Responder agent sequencers in block_1_environment: + // configuration.spi_slave_config.sequencer + + + typedef apb_m_random_sequence apb_master_random_sequence_t; + apb_master_random_sequence_t apb_master_rand_seq; + + typedef axi_m_random_sequence axi_master1_random_sequence_t; + axi_master1_random_sequence_t axi_master1_rand_seq; + + typedef axi_m_random_sequence axi_master2_random_sequence_t; + axi_master2_random_sequence_t axi_master2_rand_seq; + + + + + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + function new(string name = "" ); + super.new(name); + apb_master_rand_seq = apb_master_random_sequence_t::type_id::create("apb_master_rand_seq"); + axi_master1_rand_seq = axi_master1_random_sequence_t::type_id::create("axi_master1_rand_seq"); + axi_master2_rand_seq = axi_master2_random_sequence_t::type_id::create("axi_master2_rand_seq"); + + + endfunction + + virtual task body(); + + if ( configuration.apb_master_config.sequencer != null ) + repeat (25) apb_master_rand_seq.start(configuration.apb_master_config.sequencer); + if ( configuration.axi_master1_config.sequencer != null ) + repeat (25) axi_master1_rand_seq.start(configuration.axi_master1_config.sequencer); + if ( configuration.axi_master2_config.sequencer != null ) + repeat (25) axi_master2_rand_seq.start(configuration.axi_master2_config.sequencer); + + + endtask + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/verification_ip/environment_packages/block_1_env_pkg/src/block_1_env_typedefs.svh b/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/verification_ip/environment_packages/block_1_env_pkg/src/block_1_env_typedefs.svh new file mode 100644 index 00000000..9814bd58 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/verification_ip/environment_packages/block_1_env_pkg/src/block_1_env_typedefs.svh @@ -0,0 +1,20 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: +// This file contains defines and typedefs to be compiled for use in +// the environment package. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// + + + // pragma uvmf custom additional begin + // pragma uvmf custom additional end + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/verification_ip/environment_packages/block_1_env_pkg/src/block_1_environment.svh b/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/verification_ip/environment_packages/block_1_env_pkg/src/block_1_environment.svh new file mode 100644 index 00000000..f8fc649f --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/verification_ip/environment_packages/block_1_env_pkg/src/block_1_environment.svh @@ -0,0 +1,145 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This environment contains all agents, predictors and +// scoreboards required for the block level design. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// + +class block_1_environment extends uvmf_environment_base #( + .CONFIG_T( block_1_env_configuration + )); + `uvm_component_utils( block_1_environment ) + + + + uvm_analysis_port #(apb_m_transaction) apb_master_ap; + uvm_analysis_port #(axi_m_transaction) axi_master1_ap; + uvm_analysis_port #(axi_m_transaction) axi_master2_ap; + uvm_analysis_port #(spi_s_transaction) spi_slave_ap; + + + typedef apb_m_agent apb_master_t; + apb_master_t apb_master; + + typedef axi_m_agent axi_master1_t; + axi_master1_t axi_master1; + + typedef axi_m_agent axi_master2_t; + axi_master2_t axi_master2; + + typedef spi_s_agent spi_slave_t; + spi_slave_t spi_slave; + + + + + typedef block_1_predictor #( + .CONFIG_T(CONFIG_T) + ) block_1_pred_t; + block_1_pred_t block_1_pred; + typedef block_1_scoreboard #( + .CONFIG_T(CONFIG_T) + ) block_1_sb_t; + block_1_sb_t block_1_sb; + + + + + typedef uvmf_virtual_sequencer_base #(.CONFIG_T(block_1_env_configuration)) block_1_vsqr_t; + block_1_vsqr_t vsqr; + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + +// **************************************************************************** +// FUNCTION : new() +// This function is the standard SystemVerilog constructor. +// + function new( string name = "", uvm_component parent = null ); + super.new( name, parent ); + endfunction + +// **************************************************************************** +// FUNCTION: build_phase() +// This function builds all components within this environment. +// + virtual function void build_phase(uvm_phase phase); +// pragma uvmf custom build_phase_pre_super begin +// pragma uvmf custom build_phase_pre_super end + super.build_phase(phase); + apb_master_ap = new("apb_master_ap",this); + axi_master1_ap = new("axi_master1_ap",this); + axi_master2_ap = new("axi_master2_ap",this); + spi_slave_ap = new("spi_slave_ap",this); + apb_master = apb_master_t::type_id::create("apb_master",this); + apb_master.set_config(configuration.apb_master_config); + axi_master1 = axi_master1_t::type_id::create("axi_master1",this); + axi_master1.set_config(configuration.axi_master1_config); + axi_master2 = axi_master2_t::type_id::create("axi_master2",this); + axi_master2.set_config(configuration.axi_master2_config); + spi_slave = spi_slave_t::type_id::create("spi_slave",this); + spi_slave.set_config(configuration.spi_slave_config); + block_1_pred = block_1_pred_t::type_id::create("block_1_pred",this); + block_1_pred.configuration = configuration; + block_1_sb = block_1_sb_t::type_id::create("block_1_sb",this); + block_1_sb.configuration = configuration; + + vsqr = block_1_vsqr_t::type_id::create("vsqr", this); + vsqr.set_config(configuration); + configuration.set_vsqr(vsqr); + + // pragma uvmf custom build_phase begin + // pragma uvmf custom build_phase end + endfunction + +// **************************************************************************** +// FUNCTION: connect_phase() +// This function makes all connections within this environment. Connections +// typically inclue agent to predictor, predictor to scoreboard and scoreboard +// to agent. +// + virtual function void connect_phase(uvm_phase phase); +// pragma uvmf custom connect_phase_pre_super begin +// pragma uvmf custom connect_phase_pre_super end + super.connect_phase(phase); + spi_slave.monitored_ap.connect(block_1_sb.spi_ae); + apb_master.monitored_ap.connect(block_1_pred.apb_ae); + axi_master1.monitored_ap.connect(block_1_pred.axi_1_ae); + axi_master2.monitored_ap.connect(block_1_pred.axi_2_ae); + block_1_pred.pre_to_sco_ap.connect(block_1_sb.sco_from_pre_ae); + apb_master.monitored_ap.connect(apb_master_ap); + axi_master1.monitored_ap.connect(axi_master1_ap); + axi_master2.monitored_ap.connect(axi_master2_ap); + spi_slave.monitored_ap.connect(spi_slave_ap); + // pragma uvmf custom reg_model_connect_phase begin + // pragma uvmf custom reg_model_connect_phase end + endfunction + +// **************************************************************************** +// FUNCTION: end_of_simulation_phase() +// This function is executed just prior to executing run_phase. This function +// was added to the environment to sample environment configuration settings +// just before the simulation exits time 0. The configuration structure is +// randomized in the build phase before the environment structure is constructed. +// Configuration variables can be customized after randomization in the build_phase +// of the extended test. +// If a sequence modifies values in the configuration structure then the sequence is +// responsible for sampling the covergroup in the configuration if required. +// + virtual function void start_of_simulation_phase(uvm_phase phase); + configuration.block_1_configuration_cg.sample(); + endfunction + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/verification_ip/environment_packages/block_1_env_pkg/src/block_1_predictor.svh b/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/verification_ip/environment_packages/block_1_env_pkg/src/block_1_predictor.svh new file mode 100644 index 00000000..c81a2e81 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/verification_ip/environment_packages/block_1_env_pkg/src/block_1_predictor.svh @@ -0,0 +1,176 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +// +//---------------------------------------------------------------------- +// +// DESCRIPTION: This analysis component contains analysis_exports for receiving +// data and analysis_ports for sending data. +// +// This analysis component has the following analysis_exports that receive the +// listed transaction type. +// +// axi_2_ae receives transactions of type axi_m_transaction +// apb_ae receives transactions of type apb_m_transaction +// axi_1_ae receives transactions of type axi_m_transaction +// +// This analysis component has the following analysis_ports that can broadcast +// the listed transaction type. +// +// pre_to_sco_ap broadcasts transactions of type spi_s_transaction +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// + +class block_1_predictor #( + type CONFIG_T, + type BASE_T = uvm_component + ) extends BASE_T; + + // Factory registration of this class + `uvm_component_param_utils( block_1_predictor #( + CONFIG_T, + BASE_T + )) + + + // Instantiate a handle to the configuration of the environment in which this component resides + CONFIG_T configuration; + + + // Instantiate the analysis exports + uvm_analysis_imp_axi_2_ae #(axi_m_transaction, block_1_predictor #( + .CONFIG_T(CONFIG_T), + .BASE_T(BASE_T) + )) axi_2_ae; + uvm_analysis_imp_apb_ae #(apb_m_transaction, block_1_predictor #( + .CONFIG_T(CONFIG_T), + .BASE_T(BASE_T) + )) apb_ae; + uvm_analysis_imp_axi_1_ae #(axi_m_transaction, block_1_predictor #( + .CONFIG_T(CONFIG_T), + .BASE_T(BASE_T) + )) axi_1_ae; + + + // Instantiate the analysis ports + uvm_analysis_port #(spi_s_transaction) pre_to_sco_ap; + + + // Transaction variable for predicted values to be sent out pre_to_sco_ap + // Once a transaction is sent through an analysis_port, another transaction should + // be constructed for the next predicted transaction. + typedef spi_s_transaction pre_to_sco_ap_output_transaction_t; + pre_to_sco_ap_output_transaction_t pre_to_sco_ap_output_transaction; + // Code for sending output transaction out through pre_to_sco_ap + // pre_to_sco_ap.write(pre_to_sco_ap_output_transaction); + + // Define transaction handles for debug visibility + axi_m_transaction axi_2_ae_debug; + apb_m_transaction apb_ae_debug; + axi_m_transaction axi_1_ae_debug; + + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + // FUNCTION: new + function new(string name, uvm_component parent); + super.new(name,parent); + `uvm_warning("PREDICTOR_REVIEW", "This predictor has been created either through generation or re-generation with merging. Remove this warning after the predictor has been reviewed.") + // pragma uvmf custom new begin + // pragma uvmf custom new end + endfunction + + // FUNCTION: build_phase + virtual function void build_phase (uvm_phase phase); + + axi_2_ae = new("axi_2_ae", this); + apb_ae = new("apb_ae", this); + axi_1_ae = new("axi_1_ae", this); + pre_to_sco_ap =new("pre_to_sco_ap", this ); + // pragma uvmf custom build_phase begin + // pragma uvmf custom build_phase end + endfunction + + // FUNCTION: write_axi_2_ae + // Transactions received through axi_2_ae initiate the execution of this function. + // This function performs prediction of DUT output values based on DUT input, configuration and state + virtual function void write_axi_2_ae(axi_m_transaction t); + // pragma uvmf custom axi_2_ae_predictor begin + axi_2_ae_debug = t; + `uvm_info("PRED", "Transaction Received through axi_2_ae", UVM_MEDIUM) + `uvm_info("PRED", {" Data: ",t.convert2string()}, UVM_FULL) + // Construct one of each output transaction type. + pre_to_sco_ap_output_transaction = pre_to_sco_ap_output_transaction_t::type_id::create("pre_to_sco_ap_output_transaction"); + // UVMF_CHANGE_ME: Implement predictor model here. + `uvm_info("UNIMPLEMENTED_PREDICTOR_MODEL", "******************************************************************************************************",UVM_NONE) + `uvm_info("UNIMPLEMENTED_PREDICTOR_MODEL", "UVMF_CHANGE_ME: The block_1_predictor::write_axi_2_ae function needs to be completed with DUT prediction model",UVM_NONE) + `uvm_info("UNIMPLEMENTED_PREDICTOR_MODEL", "******************************************************************************************************",UVM_NONE) + + // Code for sending output transaction out through pre_to_sco_ap + // Please note that each broadcasted transaction should be a different object than previously + // broadcasted transactions. Creation of a different object is done by constructing the transaction + // using either new() or create(). Broadcasting a transaction object more than once to either the + // same subscriber or multiple subscribers will result in unexpected and incorrect behavior. + pre_to_sco_ap.write(pre_to_sco_ap_output_transaction); + // pragma uvmf custom axi_2_ae_predictor end + endfunction + + // FUNCTION: write_apb_ae + // Transactions received through apb_ae initiate the execution of this function. + // This function performs prediction of DUT output values based on DUT input, configuration and state + virtual function void write_apb_ae(apb_m_transaction t); + // pragma uvmf custom apb_ae_predictor begin + apb_ae_debug = t; + `uvm_info("PRED", "Transaction Received through apb_ae", UVM_MEDIUM) + `uvm_info("PRED", {" Data: ",t.convert2string()}, UVM_FULL) + // Construct one of each output transaction type. + pre_to_sco_ap_output_transaction = pre_to_sco_ap_output_transaction_t::type_id::create("pre_to_sco_ap_output_transaction"); + // UVMF_CHANGE_ME: Implement predictor model here. + `uvm_info("UNIMPLEMENTED_PREDICTOR_MODEL", "******************************************************************************************************",UVM_NONE) + `uvm_info("UNIMPLEMENTED_PREDICTOR_MODEL", "UVMF_CHANGE_ME: The block_1_predictor::write_apb_ae function needs to be completed with DUT prediction model",UVM_NONE) + `uvm_info("UNIMPLEMENTED_PREDICTOR_MODEL", "******************************************************************************************************",UVM_NONE) + + // Code for sending output transaction out through pre_to_sco_ap + // Please note that each broadcasted transaction should be a different object than previously + // broadcasted transactions. Creation of a different object is done by constructing the transaction + // using either new() or create(). Broadcasting a transaction object more than once to either the + // same subscriber or multiple subscribers will result in unexpected and incorrect behavior. + pre_to_sco_ap.write(pre_to_sco_ap_output_transaction); + // pragma uvmf custom apb_ae_predictor end + endfunction + + // FUNCTION: write_axi_1_ae + // Transactions received through axi_1_ae initiate the execution of this function. + // This function performs prediction of DUT output values based on DUT input, configuration and state + virtual function void write_axi_1_ae(axi_m_transaction t); + // pragma uvmf custom axi_1_ae_predictor begin + axi_1_ae_debug = t; + `uvm_info("PRED", "Transaction Received through axi_1_ae", UVM_MEDIUM) + `uvm_info("PRED", {" Data: ",t.convert2string()}, UVM_FULL) + // Construct one of each output transaction type. + pre_to_sco_ap_output_transaction = pre_to_sco_ap_output_transaction_t::type_id::create("pre_to_sco_ap_output_transaction"); + // UVMF_CHANGE_ME: Implement predictor model here. + `uvm_info("UNIMPLEMENTED_PREDICTOR_MODEL", "******************************************************************************************************",UVM_NONE) + `uvm_info("UNIMPLEMENTED_PREDICTOR_MODEL", "UVMF_CHANGE_ME: The block_1_predictor::write_axi_1_ae function needs to be completed with DUT prediction model",UVM_NONE) + `uvm_info("UNIMPLEMENTED_PREDICTOR_MODEL", "******************************************************************************************************",UVM_NONE) + + // Code for sending output transaction out through pre_to_sco_ap + // Please note that each broadcasted transaction should be a different object than previously + // broadcasted transactions. Creation of a different object is done by constructing the transaction + // using either new() or create(). Broadcasting a transaction object more than once to either the + // same subscriber or multiple subscribers will result in unexpected and incorrect behavior. + pre_to_sco_ap.write(pre_to_sco_ap_output_transaction); + // pragma uvmf custom axi_1_ae_predictor end + endfunction + + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/verification_ip/environment_packages/block_1_env_pkg/src/block_1_scoreboard.svh b/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/verification_ip/environment_packages/block_1_env_pkg/src/block_1_scoreboard.svh new file mode 100644 index 00000000..46ee1bf8 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/verification_ip/environment_packages/block_1_env_pkg/src/block_1_scoreboard.svh @@ -0,0 +1,131 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This analysis component contains analysis_exports for receiving +// data and analysis_ports for sending data. +// +// This analysis component has the following analysis_exports that receive the +// listed transaction type. +// +// sco_from_pre_ae receives transactions of type spi_s_transaction +// spi_ae receives transactions of type spi_s_transaction +// +// This analysis component has the following analysis_ports that can broadcast +// the listed transaction type. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// + + +class block_1_scoreboard #( + type CONFIG_T, + type BASE_T = uvm_component + ) extends BASE_T; + + // Factory registration of this class + `uvm_component_param_utils( block_1_scoreboard #( + CONFIG_T, + BASE_T + )) + + + // Instantiate a handle to the configuration of the environment in which this component resides + CONFIG_T configuration; + + + // Instantiate the analysis exports + uvm_analysis_imp_sco_from_pre_ae #(spi_s_transaction, block_1_scoreboard #( + .CONFIG_T(CONFIG_T), + .BASE_T(BASE_T) + )) sco_from_pre_ae; + uvm_analysis_imp_spi_ae #(spi_s_transaction, block_1_scoreboard #( + .CONFIG_T(CONFIG_T), + .BASE_T(BASE_T) + )) spi_ae; + + + + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + // FUNCTION: new + function new(string name, uvm_component parent); + super.new(name,parent); + // pragma uvmf custom new begin + // pragma uvmf custom new end + endfunction + + // FUNCTION: build_phase + virtual function void build_phase (uvm_phase phase); + + sco_from_pre_ae = new("sco_from_pre_ae", this); + spi_ae = new("spi_ae", this); + // pragma uvmf custom build_phase begin + // pragma uvmf custom build_phase end + endfunction + + // FUNCTION: write_sco_from_pre_ae + // Transactions received through sco_from_pre_ae initiate the execution of this function. + // This function performs prediction of DUT output values based on DUT input, configuration and state + virtual function void write_sco_from_pre_ae(spi_s_transaction t); + // pragma uvmf custom sco_from_pre_ae_scoreboard begin + `uvm_info("PRED", "Transaction Received through sco_from_pre_ae", UVM_MEDIUM) + `uvm_info("PRED", {" Data: ",t.convert2string()}, UVM_FULL) + // UVMF_CHANGE_ME: Implement custom scoreboard here. + `uvm_info("UNIMPLEMENTED_CUSTOM_SCOREBOARD", "******************************************************************************************************",UVM_NONE) + `uvm_info("UNIMPLEMENTED_CUSTOM_SCOREBOARD", "UVMF_CHANGE_ME: The block_1_scoreboard::write_sco_from_pre_ae function needs to be completed with custom scoreboard functionality",UVM_NONE) + `uvm_info("UNIMPLEMENTED_CUSTOM_SCOREBOARD", "******************************************************************************************************",UVM_NONE) + + // pragma uvmf custom sco_from_pre_ae_scoreboard end + endfunction + + // FUNCTION: write_spi_ae + // Transactions received through spi_ae initiate the execution of this function. + // This function performs prediction of DUT output values based on DUT input, configuration and state + virtual function void write_spi_ae(spi_s_transaction t); + // pragma uvmf custom spi_ae_scoreboard begin + `uvm_info("PRED", "Transaction Received through spi_ae", UVM_MEDIUM) + `uvm_info("PRED", {" Data: ",t.convert2string()}, UVM_FULL) + // UVMF_CHANGE_ME: Implement custom scoreboard here. + `uvm_info("UNIMPLEMENTED_CUSTOM_SCOREBOARD", "******************************************************************************************************",UVM_NONE) + `uvm_info("UNIMPLEMENTED_CUSTOM_SCOREBOARD", "UVMF_CHANGE_ME: The block_1_scoreboard::write_spi_ae function needs to be completed with custom scoreboard functionality",UVM_NONE) + `uvm_info("UNIMPLEMENTED_CUSTOM_SCOREBOARD", "******************************************************************************************************",UVM_NONE) + + // pragma uvmf custom spi_ae_scoreboard end + endfunction + + + + // FUNCTION: extract_phase + virtual function void extract_phase(uvm_phase phase); +// pragma uvmf custom extract_phase begin + super.extract_phase(phase); +// pragma uvmf custom extract_phase end + endfunction + + // FUNCTION: check_phase + virtual function void check_phase(uvm_phase phase); +// pragma uvmf custom check_phase begin + super.check_phase(phase); +// pragma uvmf custom check_phase end + endfunction + + // FUNCTION: report_phase + virtual function void report_phase(uvm_phase phase); +// pragma uvmf custom report_phase begin + super.report_phase(phase); +// pragma uvmf custom report_phase end + endfunction + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/verification_ip/environment_packages/block_1_env_pkg/yaml/block_1_environment.yaml b/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/verification_ip/environment_packages/block_1_env_pkg/yaml/block_1_environment.yaml new file mode 100644 index 00000000..e13560e8 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/verification_ip/environment_packages/block_1_env_pkg/yaml/block_1_environment.yaml @@ -0,0 +1,67 @@ +uvmf: + environments: + block_1: + agents: + - initiator_responder: INITIATOR + name: apb_master + type: apb_m + - initiator_responder: INITIATOR + name: axi_master1 + type: axi_m + - initiator_responder: INITIATOR + name: axi_master2 + type: axi_m + - initiator_responder: RESPONDER + name: spi_slave + type: spi_s + analysis_components: + - name: block_1_pred + parameters: [] + type: block_1_predictor + - name: block_1_sb + parameters: [] + type: block_1_scoreboard + analysis_exports: [] + analysis_ports: + - connected_to: apb_master.monitored_ap + name: apb_master_ap + trans_type: apb_m_transaction + - connected_to: axi_master1.monitored_ap + name: axi_master1_ap + trans_type: axi_m_transaction + - connected_to: axi_master2.monitored_ap + name: axi_master2_ap + trans_type: axi_m_transaction + - connected_to: spi_slave.monitored_ap + name: spi_slave_ap + trans_type: spi_s_transaction + config_constraints: [] + config_vars: + - comment: '' + isrand: 'False' + name: has_scoreboard + type: bit + value: '' + existing_library_component: 'True' + hvl_pkg_parameters: [] + non_uvmf_components: [] + parameters: [] + qvip_memory_agents: [] + scoreboards: [] + subenvs: [] + tlm_connections: + - driver: spi_slave.monitored_ap + receiver: block_1_sb.spi_ae + validate: 'True' + - driver: apb_master.monitored_ap + receiver: block_1_pred.apb_ae + validate: 'True' + - driver: axi_master1.monitored_ap + receiver: block_1_pred.axi_1_ae + validate: 'True' + - driver: axi_master2.monitored_ap + receiver: block_1_pred.axi_2_ae + validate: 'True' + - driver: block_1_pred.pre_to_sco_ap + receiver: block_1_sb.sco_from_pre_ae + validate: 'True' diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/verification_ip/environment_packages/block_1_env_pkg/yaml/block_1_util_comp_block_1_predictor.yaml b/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/verification_ip/environment_packages/block_1_env_pkg/yaml/block_1_util_comp_block_1_predictor.yaml new file mode 100644 index 00000000..ce520abe --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/verification_ip/environment_packages/block_1_env_pkg/yaml/block_1_util_comp_block_1_predictor.yaml @@ -0,0 +1,15 @@ +uvmf: + util_components: + block_1_predictor: + analysis_exports: + - name: axi_2_ae + type: axi_m_transaction + - name: apb_ae + type: apb_m_transaction + - name: axi_1_ae + type: axi_m_transaction + analysis_ports: + - name: pre_to_sco_ap + type: spi_s_transaction + existing_library_component: 'True' + type: predictor diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/verification_ip/environment_packages/block_1_env_pkg/yaml/block_1_util_comp_block_1_scoreboard.yaml b/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/verification_ip/environment_packages/block_1_env_pkg/yaml/block_1_util_comp_block_1_scoreboard.yaml new file mode 100644 index 00000000..e1fb20d8 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/verification_ip/environment_packages/block_1_env_pkg/yaml/block_1_util_comp_block_1_scoreboard.yaml @@ -0,0 +1,10 @@ +uvmf: + util_components: + block_1_scoreboard: + analysis_exports: + - name: sco_from_pre_ae + type: spi_s_transaction + - name: spi_ae + type: spi_s_transaction + existing_library_component: 'True' + type: scoreboard diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/verification_ip/interface_packages/apb_m_pkg/.project b/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/verification_ip/interface_packages/apb_m_pkg/.project new file mode 100644 index 00000000..6da82621 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/verification_ip/interface_packages/apb_m_pkg/.project @@ -0,0 +1,30 @@ + + + apb_m_pkg + + + + + + org.python.pydev.PyDevBuilder + + + + + net.sf.sveditor.core.SVProjectBuilder + + + + + + net.sf.sveditor.core.SVNature + org.python.pydev.pythonNature + + + + UVMF_VIP_LIBRARY_HOME + $%7BPARENT-2-PROJECT_LOC%7D + + + + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/verification_ip/interface_packages/apb_m_pkg/.svproject b/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/verification_ip/interface_packages/apb_m_pkg/.svproject new file mode 100644 index 00000000..e17b552f --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/verification_ip/interface_packages/apb_m_pkg/.svproject @@ -0,0 +1,16 @@ + + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/verification_ip/interface_packages/apb_m_pkg/Makefile b/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/verification_ip/interface_packages/apb_m_pkg/Makefile new file mode 100644 index 00000000..eec7d999 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/verification_ip/interface_packages/apb_m_pkg/Makefile @@ -0,0 +1,66 @@ +# apb_m interface packages source +# pragma uvmf custom additional begin +# pragma uvmf custom additional end + +apb_m_PKG = \ + +incdir+$(UVMF_VIP_LIBRARY_HOME)/interface_packages/apb_m_pkg \ + -F $(UVMF_VIP_LIBRARY_HOME)/interface_packages/apb_m_pkg/apb_m_filelist_hvl.f + +apb_m_PKG_HDL = \ + +incdir+$(UVMF_VIP_LIBRARY_HOME)/interface_packages/apb_m_pkg \ + -F $(UVMF_VIP_LIBRARY_HOME)/interface_packages/apb_m_pkg/apb_m_filelist_hdl.f + +apb_m_PKG_XRTL = \ + +incdir+$(UVMF_VIP_LIBRARY_HOME)/interface_packages/apb_m_pkg \ + -F $(UVMF_VIP_LIBRARY_HOME)/interface_packages/apb_m_pkg/apb_m_filelist_xrtl.f + +COMP_apb_m_PKG_TGT_0 = q_comp_apb_m_pkg +COMP_apb_m_PKG_TGT_1 = v_comp_apb_m_pkg +COMP_apb_m_PKG_TGT = $(COMP_apb_m_PKG_TGT_$(USE_VELOCE)) + +comp_apb_m_pkg: $(COMP_apb_m_PKG_TGT) + +q_comp_apb_m_pkg: + $(HDL_COMP_CMD) $(apb_m_PKG_HDL) + $(HVL_COMP_CMD) $(apb_m_PKG) + $(HDL_COMP_CMD) $(apb_m_PKG_XRTL) + +v_comp_apb_m_pkg: + $(HVL_COMP_CMD) $(apb_m_PKG_HDL) + $(HVL_COMP_CMD) $(apb_m_PKG) + $(VELANALYZE_CMD) $(apb_m_PKG_HDL) + $(VELANALYZE_HVL_CMD) $(apb_m_PKG) + $(HDL_COMP_CMD) $(apb_m_PKG_XRTL) + +ifeq ($(MTI_VCO_MODE),64) + GCC_COMP_ARCH = -m64 +else + GCC_COMP_ARCH = -m32 +endif + +export apb_m_IF_DPI_SRC ?= $(UVMF_VIP_LIBRARY_HOME)/interface_packages/apb_m_pkg/dpi + +C_FILE_COMPILE_LIST_apb_m_pkg = \ + +O_FILE_COMPILE_LIST_apb_m_pkg = $(notdir $(C_FILE_COMPILE_LIST_apb_m_pkg:.c=.o)) + +GCC_COMP_ARGS_apb_m_pkg += -I$(apb_m_IF_DPI_SRC) \ + -fPIC + +GCC_COMP_ARGS_apb_m_pkg += $(apb_m_IF_GCC_COMP_ARGUMENTS) + +GCC_LINK_ARGS_apb_m_pkg += \ + \ + -o .so + +comp_apb_m_pkg_c_files: + @echo "--------------------------------" + @echo "Compiling Interface C source" + @echo "--------------------------------" + gcc $(GCC_COMP_ARCH) $(GCC_COMP_ARGS_apb_m_pkg) $(C_FILE_COMPILE_LIST_apb_m_pkg) + @echo "--------------------------------" + @echo "Linking Interface C objects into a shared object" + @echo "--------------------------------" + gcc $(GCC_COMP_ARCH) $(GCC_LINK_ARGS_apb_m_pkg) $(O_FILE_COMPILE_LIST_apb_m_pkg) + @echo "--------------------------------" + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/verification_ip/interface_packages/apb_m_pkg/apb_m.compile b/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/verification_ip/interface_packages/apb_m_pkg/apb_m.compile new file mode 100644 index 00000000..d77eb23e --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/verification_ip/interface_packages/apb_m_pkg/apb_m.compile @@ -0,0 +1,3 @@ +needs: + - apb_m_hvl.compile + - apb_m_hdl.compile diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/verification_ip/interface_packages/apb_m_pkg/apb_m_bfm.vinfo b/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/verification_ip/interface_packages/apb_m_pkg/apb_m_bfm.vinfo new file mode 100644 index 00000000..8d4b80f9 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/verification_ip/interface_packages/apb_m_pkg/apb_m_bfm.vinfo @@ -0,0 +1,6 @@ +@use $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg_hdl.vinfo +@use apb_m_pkg_hdl.vinfo ++incdir+@vinfodir +src/apb_m_if.sv +src/apb_m_driver_bfm.sv +src/apb_m_monitor_bfm.sv diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/verification_ip/interface_packages/apb_m_pkg/apb_m_common.compile b/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/verification_ip/interface_packages/apb_m_pkg/apb_m_common.compile new file mode 100644 index 00000000..26821a84 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/verification_ip/interface_packages/apb_m_pkg/apb_m_common.compile @@ -0,0 +1,7 @@ +needs: + - $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg_hdl.compile +incdir: + - . + - ${uvm_path}/src +src: + - apb_m_pkg_hdl.sv diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/verification_ip/interface_packages/apb_m_pkg/apb_m_filelist_hdl.f b/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/verification_ip/interface_packages/apb_m_pkg/apb_m_filelist_hdl.f new file mode 100644 index 00000000..0d2a4c9d --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/verification_ip/interface_packages/apb_m_pkg/apb_m_filelist_hdl.f @@ -0,0 +1 @@ +$UVMF_VIP_LIBRARY_HOME/interface_packages/apb_m_pkg/apb_m_pkg_hdl.sv diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/verification_ip/interface_packages/apb_m_pkg/apb_m_filelist_hvl.f b/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/verification_ip/interface_packages/apb_m_pkg/apb_m_filelist_hvl.f new file mode 100644 index 00000000..0d4b8d6b --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/verification_ip/interface_packages/apb_m_pkg/apb_m_filelist_hvl.f @@ -0,0 +1 @@ +$UVMF_VIP_LIBRARY_HOME/interface_packages/apb_m_pkg/apb_m_pkg.sv \ No newline at end of file diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/verification_ip/interface_packages/apb_m_pkg/apb_m_filelist_xrtl.f b/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/verification_ip/interface_packages/apb_m_pkg/apb_m_filelist_xrtl.f new file mode 100644 index 00000000..d2cef722 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/verification_ip/interface_packages/apb_m_pkg/apb_m_filelist_xrtl.f @@ -0,0 +1,3 @@ +$UVMF_VIP_LIBRARY_HOME/interface_packages/apb_m_pkg/src/apb_m_if.sv +$UVMF_VIP_LIBRARY_HOME/interface_packages/apb_m_pkg/src/apb_m_monitor_bfm.sv +$UVMF_VIP_LIBRARY_HOME/interface_packages/apb_m_pkg/src/apb_m_driver_bfm.sv diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/verification_ip/interface_packages/apb_m_pkg/apb_m_hdl.compile b/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/verification_ip/interface_packages/apb_m_pkg/apb_m_hdl.compile new file mode 100644 index 00000000..83ce2876 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/verification_ip/interface_packages/apb_m_pkg/apb_m_hdl.compile @@ -0,0 +1,9 @@ +needs: + - $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg_hdl.compile + - ./apb_m_common.compile +incdir: + - . +src: + - src/apb_m_if.sv + - src/apb_m_monitor_bfm.sv + - src/apb_m_driver_bfm.sv diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/verification_ip/interface_packages/apb_m_pkg/apb_m_hvl.compile b/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/verification_ip/interface_packages/apb_m_pkg/apb_m_hvl.compile new file mode 100644 index 00000000..2b4533f6 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/verification_ip/interface_packages/apb_m_pkg/apb_m_hvl.compile @@ -0,0 +1,7 @@ +needs: + - $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg.compile + - ./apb_m_common.compile +incdir: + - . +src: + - apb_m_pkg.sv diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/verification_ip/interface_packages/apb_m_pkg/apb_m_pkg.sv b/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/verification_ip/interface_packages/apb_m_pkg/apb_m_pkg.sv new file mode 100644 index 00000000..453883f5 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/verification_ip/interface_packages/apb_m_pkg/apb_m_pkg.sv @@ -0,0 +1,77 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// PACKAGE: This file defines all of the files contained in the +// interface package that will run on the host simulator. +// +// CONTAINS: +// - +// - +// - + +// - +// - +// - + +// - +// - +// - + +// - +// - +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +package apb_m_pkg; + + import uvm_pkg::*; + import uvmf_base_pkg_hdl::*; + import uvmf_base_pkg::*; + import apb_m_pkg_hdl::*; + + `include "uvm_macros.svh" + + // pragma uvmf custom package_imports_additional begin + // pragma uvmf custom package_imports_additional end + `include "src/apb_m_macros.svh" + + export apb_m_pkg_hdl::*; + + + + // Parameters defined as HVL parameters + + `include "src/apb_m_typedefs.svh" + `include "src/apb_m_transaction.svh" + + `include "src/apb_m_configuration.svh" + `include "src/apb_m_driver.svh" + `include "src/apb_m_monitor.svh" + + `include "src/apb_m_transaction_coverage.svh" + `include "src/apb_m_sequence_base.svh" + `include "src/apb_m_random_sequence.svh" + + `include "src/apb_m_responder_sequence.svh" + `include "src/apb_m2reg_adapter.svh" + + `include "src/apb_m_agent.svh" + + // pragma uvmf custom package_item_additional begin + // UVMF_CHANGE_ME : When adding new interface sequences to the src directory + // be sure to add the sequence file here so that it will be + // compiled as part of the interface package. Be sure to place + // the new sequence after any base sequences of the new sequence. + // pragma uvmf custom package_item_additional end + +endpackage + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/verification_ip/interface_packages/apb_m_pkg/apb_m_pkg.vinfo b/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/verification_ip/interface_packages/apb_m_pkg/apb_m_pkg.vinfo new file mode 100644 index 00000000..e6a8b7c1 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/verification_ip/interface_packages/apb_m_pkg/apb_m_pkg.vinfo @@ -0,0 +1,4 @@ +@use $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg.vinfo +@use apb_m_pkg_hdl.vinfo ++incdir+@vinfodir +apb_m_pkg.sv diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/verification_ip/interface_packages/apb_m_pkg/apb_m_pkg_hdl.sv b/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/verification_ip/interface_packages/apb_m_pkg/apb_m_pkg_hdl.sv new file mode 100644 index 00000000..b657eb44 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/verification_ip/interface_packages/apb_m_pkg/apb_m_pkg_hdl.sv @@ -0,0 +1,38 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// PACKAGE: This file defines all of the files contained in the +// interface package that needs to be compiled and synthesized +// for running on Veloce. +// +// CONTAINS: +// - +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +package apb_m_pkg_hdl; + + import uvmf_base_pkg_hdl::*; + + // pragma uvmf custom package_imports_additional begin + // pragma uvmf custom package_imports_additional end + + // Parameters defined as HDL parameters + + `include "src/apb_m_typedefs_hdl.svh" + `include "src/apb_m_macros.svh" + + // pragma uvmf custom package_item_additional begin + // pragma uvmf custom package_item_additional end + +endpackage + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/verification_ip/interface_packages/apb_m_pkg/apb_m_pkg_hdl.vinfo b/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/verification_ip/interface_packages/apb_m_pkg/apb_m_pkg_hdl.vinfo new file mode 100644 index 00000000..3e5dc166 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/verification_ip/interface_packages/apb_m_pkg/apb_m_pkg_hdl.vinfo @@ -0,0 +1,2 @@ +@use $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg_hdl.vinfo +apb_m_pkg_hdl.sv diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/verification_ip/interface_packages/apb_m_pkg/apb_m_pkg_sve.F b/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/verification_ip/interface_packages/apb_m_pkg/apb_m_pkg_sve.F new file mode 100644 index 00000000..b934c1a1 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/verification_ip/interface_packages/apb_m_pkg/apb_m_pkg_sve.F @@ -0,0 +1,10 @@ +// UVM ++incdir+${UVM_HOME}/src +${UVM_HOME}/src/uvm_pkg.sv + +// Common UVMF files +-f ${UVMF_HOME}/common/common_sve.f + ++incdir+. +-f ${UVMF_VIP_LIBRARY_HOME}/interface_packages/apb_m_pkg/apb_m_filelist_hdl.f +-f ${UVMF_VIP_LIBRARY_HOME}/interface_packages/apb_m_pkg/apb_m_filelist_hvl.f diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/verification_ip/interface_packages/apb_m_pkg/compile.do b/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/verification_ip/interface_packages/apb_m_pkg/compile.do new file mode 100644 index 00000000..944fd712 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/verification_ip/interface_packages/apb_m_pkg/compile.do @@ -0,0 +1,14 @@ +# Tcl do file for compile of apb_m interface + +# pragma uvmf custom additional begin +# pragma uvmf custom additional end + + +vlog -sv -timescale 1ps/1ps -suppress 2223,2286 +incdir+$env(UVMF_VIP_LIBRARY_HOME)/interface_packages/apb_m_pkg \ + -F $env(UVMF_VIP_LIBRARY_HOME)/interface_packages/apb_m_pkg/apb_m_filelist_hdl.f + +vlog -sv -timescale 1ps/1ps -suppress 2223,2286 +incdir+$env(UVMF_VIP_LIBRARY_HOME)/interface_packages/apb_m_pkg \ + -F $env(UVMF_VIP_LIBRARY_HOME)/interface_packages/apb_m_pkg/apb_m_filelist_hvl.f + +vlog -sv -timescale 1ps/1ps -suppress 2223,2286 +incdir+$env(UVMF_VIP_LIBRARY_HOME)/interface_packages/apb_m_pkg \ + -F $env(UVMF_VIP_LIBRARY_HOME)/interface_packages/apb_m_pkg/apb_m_filelist_xrtl.f \ No newline at end of file diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/verification_ip/interface_packages/apb_m_pkg/src/apb_m2reg_adapter.svh b/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/verification_ip/interface_packages/apb_m_pkg/src/apb_m2reg_adapter.svh new file mode 100644 index 00000000..bbbd0c42 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/verification_ip/interface_packages/apb_m_pkg/src/apb_m2reg_adapter.svh @@ -0,0 +1,118 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: +// This file contains the UVM register adapter for the apb_m interface. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class apb_m2reg_adapter #( + int APB_ADDR_WIDTH = 32, + int APB_DATA_WIDTH = 32, + int STRB_LEN = APB_ADDR_WIDTH/8 + ) extends uvm_reg_adapter; + + `uvm_object_param_utils( apb_m2reg_adapter #( + APB_ADDR_WIDTH, + APB_DATA_WIDTH, + STRB_LEN + )) + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + //-------------------------------------------------------------------- + // new + //-------------------------------------------------------------------- + function new (string name = "apb_m2reg_adapter" ); + super.new(name); + // pragma uvmf custom new begin + // UVMF_CHANGE_ME : Configure the adapter regarding byte enables and provides response. + + // Does the protocol the Agent is modeling support byte enables? + // 0 = NO + // 1 = YES + supports_byte_enable = 0; + + // Does the Agent's Driver provide separate response sequence items? + // i.e. Does the driver call seq_item_port.put() + // and do the sequences call get_response()? + // 0 = NO + // 1 = YES + provides_responses = 0; + // pragma uvmf custom new end + + endfunction: new + + //-------------------------------------------------------------------- + // reg2bus + //-------------------------------------------------------------------- + virtual function uvm_sequence_item reg2bus(const ref uvm_reg_bus_op rw); + + apb_m_transaction #( + .APB_ADDR_WIDTH(APB_ADDR_WIDTH), + .APB_DATA_WIDTH(APB_DATA_WIDTH), + .STRB_LEN(STRB_LEN) + ) trans_h = apb_m_transaction #( + .APB_ADDR_WIDTH(APB_ADDR_WIDTH), + .APB_DATA_WIDTH(APB_DATA_WIDTH), + .STRB_LEN(STRB_LEN) + )::type_id::create("trans_h"); + + // pragma uvmf custom reg2bus begin + // UVMF_CHANGE_ME : Fill in the reg2bus adapter mapping registe fields to protocol fields. + + //Adapt the following for your sequence item type + // trans_h.op = (rw.kind == UVM_READ) ? WB_READ : WB_WRITE; + //Copy over address + // trans_h.addr = rw.addr; + //Copy over write data + // trans_h.data = rw.data; + + // pragma uvmf custom reg2bus end + + // Return the adapted transaction + return trans_h; + + endfunction: reg2bus + + //-------------------------------------------------------------------- + // bus2reg + //-------------------------------------------------------------------- + virtual function void bus2reg(uvm_sequence_item bus_item, + ref uvm_reg_bus_op rw); + apb_m_transaction #( + .APB_ADDR_WIDTH(APB_ADDR_WIDTH), + .APB_DATA_WIDTH(APB_DATA_WIDTH), + .STRB_LEN(STRB_LEN) + ) trans_h; + if (!$cast(trans_h, bus_item)) begin + `uvm_fatal("ADAPT","Provided bus_item is not of the correct type") + return; + end + // pragma uvmf custom bus2reg begin + // UVMF_CHANGE_ME : Fill in the bus2reg adapter mapping protocol fields to register fields. + //Adapt the following for your sequence item type + //Copy over instruction type + // rw.kind = (trans_h.op == WB_WRITE) ? UVM_WRITE : UVM_READ; + //Copy over address + // rw.addr = trans_h.addr; + //Copy over read data + // rw.data = trans_h.data; + //Check for errors on the bus and return UVM_NOT_OK if there is an error + // rw.status = UVM_IS_OK; + // pragma uvmf custom bus2reg end + + endfunction: bus2reg + +endclass : apb_m2reg_adapter + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/verification_ip/interface_packages/apb_m_pkg/src/apb_m_agent.svh b/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/verification_ip/interface_packages/apb_m_pkg/src/apb_m_agent.svh new file mode 100644 index 00000000..8fbbff4d --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/verification_ip/interface_packages/apb_m_pkg/src/apb_m_agent.svh @@ -0,0 +1,81 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: Protocol specific agent class definition +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class apb_m_agent #( + int APB_ADDR_WIDTH = 32, + int APB_DATA_WIDTH = 32, + int STRB_LEN = APB_ADDR_WIDTH/8 + ) extends uvmf_parameterized_agent #( + .CONFIG_T(apb_m_configuration #( + .APB_ADDR_WIDTH(APB_ADDR_WIDTH), + .APB_DATA_WIDTH(APB_DATA_WIDTH), + .STRB_LEN(STRB_LEN) + )), + .DRIVER_T(apb_m_driver #( + .APB_ADDR_WIDTH(APB_ADDR_WIDTH), + .APB_DATA_WIDTH(APB_DATA_WIDTH), + .STRB_LEN(STRB_LEN) + )), + .MONITOR_T(apb_m_monitor #( + .APB_ADDR_WIDTH(APB_ADDR_WIDTH), + .APB_DATA_WIDTH(APB_DATA_WIDTH), + .STRB_LEN(STRB_LEN) + )), + .COVERAGE_T(apb_m_transaction_coverage #( + .APB_ADDR_WIDTH(APB_ADDR_WIDTH), + .APB_DATA_WIDTH(APB_DATA_WIDTH), + .STRB_LEN(STRB_LEN) + )), + .TRANS_T(apb_m_transaction #( + .APB_ADDR_WIDTH(APB_ADDR_WIDTH), + .APB_DATA_WIDTH(APB_DATA_WIDTH), + .STRB_LEN(STRB_LEN) + )) + ); + + `uvm_component_param_utils( apb_m_agent #( + APB_ADDR_WIDTH, + APB_DATA_WIDTH, + STRB_LEN + )) + +// pragma uvmf custom class_item_additional begin +// pragma uvmf custom class_item_additional end + +// **************************************************************************** +// FUNCTION : new() +// This function is the standard SystemVerilog constructor. +// + function new( string name = "", uvm_component parent = null ); + super.new( name, parent ); + endfunction + +// **************************************************************************** + // FUNCTION: build_phase + virtual function void build_phase(uvm_phase phase); +// pragma uvmf custom build_phase_pre_super begin +// pragma uvmf custom build_phase_pre_super end + super.build_phase(phase); + if (configuration.active_passive == ACTIVE) begin + // Place sequencer handle into configuration object + // so that it may be retrieved from configuration + // rather than using uvm_config_db + configuration.sequencer = this.sequencer; + end + endfunction + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/verification_ip/interface_packages/apb_m_pkg/src/apb_m_configuration.svh b/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/verification_ip/interface_packages/apb_m_pkg/src/apb_m_configuration.svh new file mode 100644 index 00000000..e01c8416 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/verification_ip/interface_packages/apb_m_pkg/src/apb_m_configuration.svh @@ -0,0 +1,211 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This class contains all variables and functions used +// to configure the apb_m agent and its bfm's. It gets the +// bfm's from the uvm_config_db for use by the agent. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class apb_m_configuration #( + int APB_ADDR_WIDTH = 32, + int APB_DATA_WIDTH = 32, + int STRB_LEN = APB_ADDR_WIDTH/8 + ) extends uvmf_parameterized_agent_configuration_base #( + .DRIVER_BFM_BIND_T(virtual apb_m_driver_bfm #( + .APB_ADDR_WIDTH(APB_ADDR_WIDTH), + .APB_DATA_WIDTH(APB_DATA_WIDTH), + .STRB_LEN(STRB_LEN) + )), + .MONITOR_BFM_BIND_T( virtual apb_m_monitor_bfm #( + .APB_ADDR_WIDTH(APB_ADDR_WIDTH), + .APB_DATA_WIDTH(APB_DATA_WIDTH), + .STRB_LEN(STRB_LEN) + ))); + + `uvm_object_param_utils( apb_m_configuration #( + APB_ADDR_WIDTH, + APB_DATA_WIDTH, + STRB_LEN + )) + + + // Sequencer handle populated by agent + uvm_sequencer #(apb_m_transaction #( + .APB_ADDR_WIDTH(APB_ADDR_WIDTH), + .APB_DATA_WIDTH(APB_DATA_WIDTH), + .STRB_LEN(STRB_LEN) + ) ) sequencer; + + //Constraints for the configuration variables: + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + covergroup apb_m_configuration_cg; + // pragma uvmf custom covergroup begin + option.auto_bin_max=1024; + // pragma uvmf custom covergroup end + endgroup + + //******************************************************************* + //******************************************************************* + // Structure used to pass configuration variables to monitor and driver BFM's. + // Use to_struct function to pack variables into structure. + // Use from_struct function to unpack variables from structure. + // This structure is defined in apb_m_macros.svh + `apb_m_CONFIGURATION_STRUCT + apb_m_configuration_s apb_m_configuration_struct; + //******************************************************************* + // FUNCTION: to_struct() + // This function packs variables into a apb_m_configuration_s + // structure. The function returns the handle to the apb_m_configuration_struct. + // This function is defined in apb_m_macros.svh + `apb_m_CONFIGURATION_TO_STRUCT_FUNCTION + //******************************************************************* + // FUNCTION: from_struct() + // This function unpacks the struct provided as an argument into + // variables of this class. + // This function is defined in apb_m_macros.svh + `apb_m_CONFIGURATION_FROM_STRUCT_FUNCTION + + // **************************************************************************** + // FUNCTION : new() + // This function is the standard SystemVerilog constructor. + // + function new( string name = "" ); + super.new( name ); + // Construct the covergroup for this configuration class + apb_m_configuration_cg = new; + endfunction + + // **************************************************************************** + // FUNCTION: post_randomize() + // This function is automatically called after the randomize() function + // is executed. + // + function void post_randomize(); + super.post_randomize(); + apb_m_configuration_cg.sample(); + endfunction + + // **************************************************************************** + // FUNCTION: initialize + // This function causes the configuration to retrieve + // its virtual interface handle from the uvm_config_db. + // This function also makes itself available to its + // agent through the uvm_config_db. + // + // ARGUMENTS: + // uvmf_active_passive_t activity: + // This argument identifies the simulation level + // as either BLOCK, CHIP, SIMULATION, etc. + // + // AGENT_PATH: + // This argument identifies the path to this + // configurations agent. This configuration + // makes itself available to the agent specified + // by agent_path by placing itself into the + // uvm_config_db. + // + // INTERFACE_NAME: + // This argument identifies the string name of + // this configurations BFM's. This string + // name is used to retrieve the driver and + // monitor BFM from the uvm_config_db. + // + virtual function void initialize(uvmf_active_passive_t activity, + string agent_path, + string interface_name); + + super.initialize( activity, agent_path, interface_name); + // The covergroup is given the same name as the interface + apb_m_configuration_cg.set_inst_name(interface_name); + + // This configuration places itself into the uvm_config_db for the agent, identified by the agent_path variable, to retrieve. + uvm_config_db #( apb_m_configuration #( + .APB_ADDR_WIDTH(APB_ADDR_WIDTH), + .APB_DATA_WIDTH(APB_DATA_WIDTH), + .STRB_LEN(STRB_LEN) + ) + )::set( null ,agent_path,UVMF_AGENT_CONFIG, this ); + + // This configuration also places itself in the config db using the same identifier used by the interface. This allows users to access + // configuration variables and the interface through the bfm api class rather than directly accessing the BFM. This is useful for + // accessingthe BFM when using Veloce + uvm_config_db #( apb_m_configuration #( + .APB_ADDR_WIDTH(APB_ADDR_WIDTH), + .APB_DATA_WIDTH(APB_DATA_WIDTH), + .STRB_LEN(STRB_LEN) + ) + )::set( null ,UVMF_CONFIGURATIONS, interface_name, this ); + + apb_m_configuration_cg.set_inst_name($sformatf("apb_m_configuration_cg_%s",get_full_name())); + +// This code is to aid in debugging parameter mismatches between the BFM and its corresponding agent. +// Enable this debug by setting UVM_VERBOSITY to UVM_DEBUG +// Setting UVM_VERBOSITY to UVM_DEBUG causes all BFM's and all agents to display their parameter settings. +// All of the messages from this feature have a UVM messaging id value of "CFG" +// The transcript or run.log can be parsed to ensure BFM parameter settings match its corresponding agents parameter settings. + `uvm_info("CFG", + $psprintf("The agent at '%s' is using interface named %s has the following parameters: APB_ADDR_WIDTH=%x APB_DATA_WIDTH=%x STRB_LEN=%x ", agent_path, interface_name, APB_ADDR_WIDTH ,APB_DATA_WIDTH ,STRB_LEN ), + UVM_DEBUG) + + // pragma uvmf custom initialize begin + // This controls whether or not the agent returns a transaction handle in the driver when calling + // item_done() back into the sequencer or not. If set to 1, a transaction is sent back which means + // the sequence on the other end must use the get_response() part of the driver/sequence API. If + // this doesn't occur, there will eventually be response_queue overflow errors during the test. + return_transaction_response = 1'b0; + + // pragma uvmf custom initialize end + + endfunction + + // **************************************************************************** + // TASK: wait_for_reset + // *[Required]* Blocks until reset is released. The wait_for_reset operation is performed + // by a task in the monitor bfm. + virtual task wait_for_reset(); + monitor_bfm.wait_for_reset(); + endtask + + // **************************************************************************** + // TASK: wait_for_num_clocks + // *[Required]* Blocks until specified number of clocks have elapsed. The wait_for_num_clocks + // operation is performed by a task in the monitor bfm. + virtual task wait_for_num_clocks(int clocks); + monitor_bfm.wait_for_num_clocks(clocks); + endtask + + // **************************************************************************** + // FUNCTION : convert2string() + // This function is used to convert variables in this class into a string for log messaging. + // + virtual function string convert2string (); + // pragma uvmf custom convert2string begin + return $sformatf(""); + // pragma uvmf custom convert2string end + endfunction + + // **************************************************************************** + // FUNCTION: get_sequencer + function uvm_sequencer #(apb_m_transaction#( + .APB_ADDR_WIDTH(APB_ADDR_WIDTH), + .APB_DATA_WIDTH(APB_DATA_WIDTH), + .STRB_LEN(STRB_LEN) + )) get_sequencer(); + return sequencer; + endfunction + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/verification_ip/interface_packages/apb_m_pkg/src/apb_m_driver.svh b/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/verification_ip/interface_packages/apb_m_pkg/src/apb_m_driver.svh new file mode 100644 index 00000000..0c3b8285 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/verification_ip/interface_packages/apb_m_pkg/src/apb_m_driver.svh @@ -0,0 +1,115 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This class passes transactions between the sequencer +// and the BFM driver interface. It accesses the driver BFM +// through the bfm handle. This driver +// passes transactions to the driver BFM through the access +// task. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class apb_m_driver #( + int APB_ADDR_WIDTH = 32, + int APB_DATA_WIDTH = 32, + int STRB_LEN = APB_ADDR_WIDTH/8 + ) extends uvmf_driver_base #( + .CONFIG_T(apb_m_configuration #( + .APB_ADDR_WIDTH(APB_ADDR_WIDTH), + .APB_DATA_WIDTH(APB_DATA_WIDTH), + .STRB_LEN(STRB_LEN) + ) ), + .BFM_BIND_T(virtual apb_m_driver_bfm #( + .APB_ADDR_WIDTH(APB_ADDR_WIDTH), + .APB_DATA_WIDTH(APB_DATA_WIDTH), + .STRB_LEN(STRB_LEN) + ) ), + .REQ(apb_m_transaction #( + .APB_ADDR_WIDTH(APB_ADDR_WIDTH), + .APB_DATA_WIDTH(APB_DATA_WIDTH), + .STRB_LEN(STRB_LEN) + ) ), + .RSP(apb_m_transaction #( + .APB_ADDR_WIDTH(APB_ADDR_WIDTH), + .APB_DATA_WIDTH(APB_DATA_WIDTH), + .STRB_LEN(STRB_LEN) + ) )); + + `uvm_component_param_utils( apb_m_driver #( + APB_ADDR_WIDTH, + APB_DATA_WIDTH, + STRB_LEN + )) +//******************************************************************* +// Macros that define structs located in apb_m_macros.svh +//******************************************************************* +// Initiator macro used by apb_m_driver and apb_m_driver_bfm +// to communicate initiator driven data to apb_m_driver_bfm. +`apb_m_INITIATOR_STRUCT + apb_m_initiator_s apb_m_initiator_struct; +//******************************************************************* +// Responder macro used by apb_m_driver and apb_m_driver_bfm +// to communicate Responder driven data to apb_m_driver_bfm. +`apb_m_RESPONDER_STRUCT + apb_m_responder_s apb_m_responder_struct; + +// pragma uvmf custom class_item_additional begin +// pragma uvmf custom class_item_additional end + +// **************************************************************************** +// This function is the standard SystemVerilog constructor. +// + function new( string name = "", uvm_component parent=null ); + super.new( name, parent ); + endfunction + +// **************************************************************************** +// This function sends configuration object variables to the driver BFM +// using the configuration struct. +// + virtual function void configure(input CONFIG_T cfg); + bfm.configure( cfg.to_struct() ); + endfunction + +// **************************************************************************** +// This function places a handle to this class in the proxy variable in the +// driver BFM. This allows the driver BFM to call tasks and function within this class. +// + virtual function void set_bfm_proxy_handle(); + bfm.proxy = this; endfunction + +// **************************************************************************** +// This task is called by the run_phase in uvmf_driver_base. + virtual task access( inout REQ txn ); +// pragma uvmf custom access begin + if (configuration.initiator_responder==RESPONDER) begin + // Complete current transfer and wait for next transfer + bfm.respond_and_wait_for_next_transfer( + apb_m_initiator_struct, + txn.to_responder_struct() + ); + // Unpack information about initiated transfer received by this responder + txn.from_initiator_struct(apb_m_initiator_struct); + end else begin + // Initiate a transfer and get response + bfm.initiate_and_get_response( + txn.to_initiator_struct(), + apb_m_responder_struct + ); + // Unpack transfer response information received by this initiator + txn.from_responder_struct(apb_m_responder_struct); + end +// pragma uvmf custom access end + endtask + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/verification_ip/interface_packages/apb_m_pkg/src/apb_m_driver_bfm.sv b/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/verification_ip/interface_packages/apb_m_pkg/src/apb_m_driver_bfm.sv new file mode 100644 index 00000000..d4e614a4 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/verification_ip/interface_packages/apb_m_pkg/src/apb_m_driver_bfm.sv @@ -0,0 +1,378 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: +// This interface performs the apb_m signal driving. It is +// accessed by the uvm apb_m driver through a virtual interface +// handle in the apb_m configuration. It drives the singals passed +// in through the port connection named bus of type apb_m_if. +// +// Input signals from the apb_m_if are assigned to an internal input +// signal with a _i suffix. The _i signal should be used for sampling. +// +// The input signal connections are as follows: +// bus.signal -> signal_i +// +// This bfm drives signals with a _o suffix. These signals +// are driven onto signals within apb_m_if based on INITIATOR/RESPONDER and/or +// ARBITRATION/GRANT status. +// +// The output signal connections are as follows: +// signal_o -> bus.signal +// +// +// Interface functions and tasks used by UVM components: +// +// configure: +// This function gets configuration attributes from the +// UVM driver to set any required BFM configuration +// variables such as 'initiator_responder'. +// +// initiate_and_get_response: +// This task is used to perform signaling activity for initiating +// a protocol transfer. The task initiates the transfer, using +// input data from the initiator struct. Then the task captures +// response data, placing the data into the response struct. +// The response struct is returned to the driver class. +// +// respond_and_wait_for_next_transfer: +// This task is used to complete a current transfer as a responder +// and then wait for the initiator to start the next transfer. +// The task uses data in the responder struct to drive protocol +// signals to complete the transfer. The task then waits for +// the next transfer. Once the next transfer begins, data from +// the initiator is placed into the initiator struct and sent +// to the responder sequence for processing to determine +// what data to respond with. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +import uvmf_base_pkg_hdl::*; +import apb_m_pkg_hdl::*; +`include "src/apb_m_macros.svh" + +interface apb_m_driver_bfm #( + int APB_ADDR_WIDTH = 32, + int APB_DATA_WIDTH = 32, + int STRB_LEN = APB_ADDR_WIDTH/8 + ) + (apb_m_if bus); + // The following pragma and additional ones in-lined further below are for running this BFM on Veloce + // pragma attribute apb_m_driver_bfm partition_interface_xif + +`ifndef XRTL +// This code is to aid in debugging parameter mismatches between the BFM and its corresponding agent. +// Enable this debug by setting UVM_VERBOSITY to UVM_DEBUG +// Setting UVM_VERBOSITY to UVM_DEBUG causes all BFM's and all agents to display their parameter settings. +// All of the messages from this feature have a UVM messaging id value of "CFG" +// The transcript or run.log can be parsed to ensure BFM parameter settings match its corresponding agents parameter settings. +import uvm_pkg::*; +`include "uvm_macros.svh" +initial begin : bfm_vs_agent_parameter_debug + `uvm_info("CFG", + $psprintf("The BFM at '%m' has the following parameters: APB_ADDR_WIDTH=%x APB_DATA_WIDTH=%x STRB_LEN=%x ", APB_ADDR_WIDTH,APB_DATA_WIDTH,STRB_LEN), + UVM_DEBUG) +end +`endif + + // Config value to determine if this is an initiator or a responder + uvmf_initiator_responder_t initiator_responder; + // Custom configuration variables. + // These are set using the configure function which is called during the UVM connect_phase + + logic pclk_i; + logic presetn_i; + + // Signal list (all signals are capable of being inputs and outputs for the sake + // of supporting both INITIATOR and RESPONDER mode operation. Expectation is that + // directionality in the config file was from the point-of-view of the INITIATOR + + // INITIATOR mode input signals + tri [APB_DATA_WIDTH-1:0] prdata_i; + reg [APB_DATA_WIDTH-1:0] prdata_o = 'b0; + tri pready_i; + reg pready_o = 0; + tri pslverr_i; + reg pslverr_o = 0; + + // INITIATOR mode output signals + tri [15:0] psel_i; + reg [15:0] psel_o = 'b0; + tri penable_i; + reg penable_o = 'b0; + tri [APB_ADDR_WIDTH-1:0] paddr_i; + reg [APB_ADDR_WIDTH-1:0] paddr_o = 'b0; + tri [APB_DATA_WIDTH-1:0] pwdata_i; + reg [APB_DATA_WIDTH-1:0] pwdata_o = 'b0; + tri pwrite_i; + reg pwrite_o = 'b0; + tri [STRB_LEN-1:0] pstrb_i; + reg [STRB_LEN-1:0] pstrb_o = 'b0; + tri [2:0] pprot_i; + reg [2:0] pprot_o = 'b0; + + // Bi-directional signals + + + assign pclk_i = bus.pclk; + assign presetn_i = bus.presetn; + + // These are signals marked as 'input' by the config file, but the signals will be + // driven by this BFM if put into RESPONDER mode (flipping all signal directions around) + assign prdata_i = bus.prdata; + assign bus.prdata = (initiator_responder == RESPONDER) ? prdata_o : 'bz; + assign pready_i = bus.pready; + assign bus.pready = (initiator_responder == RESPONDER) ? pready_o : 'bz; + assign pslverr_i = bus.pslverr; + assign bus.pslverr = (initiator_responder == RESPONDER) ? pslverr_o : 'bz; + + + // These are signals marked as 'output' by the config file, but the outputs will + // not be driven by this BFM unless placed in INITIATOR mode. + assign bus.psel = (initiator_responder == INITIATOR) ? psel_o : 'bz; + assign psel_i = bus.psel; + assign bus.penable = (initiator_responder == INITIATOR) ? penable_o : 'bz; + assign penable_i = bus.penable; + assign bus.paddr = (initiator_responder == INITIATOR) ? paddr_o : 'bz; + assign paddr_i = bus.paddr; + assign bus.pwdata = (initiator_responder == INITIATOR) ? pwdata_o : 'bz; + assign pwdata_i = bus.pwdata; + assign bus.pwrite = (initiator_responder == INITIATOR) ? pwrite_o : 'bz; + assign pwrite_i = bus.pwrite; + assign bus.pstrb = (initiator_responder == INITIATOR) ? pstrb_o : 'bz; + assign pstrb_i = bus.pstrb; + assign bus.pprot = (initiator_responder == INITIATOR) ? pprot_o : 'bz; + assign pprot_i = bus.pprot; + + // Proxy handle to UVM driver + apb_m_pkg::apb_m_driver #( + .APB_ADDR_WIDTH(APB_ADDR_WIDTH), + .APB_DATA_WIDTH(APB_DATA_WIDTH), + .STRB_LEN(STRB_LEN) + ) proxy; + // pragma tbx oneway proxy.my_function_name_in_uvm_driver + + // **************************************************************************** + // **************************************************************************** + // Macros that define structs located in apb_m_macros.svh + // **************************************************************************** + // Struct for passing configuration data from apb_m_driver to this BFM + // **************************************************************************** + `apb_m_CONFIGURATION_STRUCT + // **************************************************************************** + // Structs for INITIATOR and RESPONDER data flow + //******************************************************************* + // Initiator macro used by apb_m_driver and apb_m_driver_bfm + // to communicate initiator driven data to apb_m_driver_bfm. + `apb_m_INITIATOR_STRUCT + apb_m_initiator_s initiator_struct; + // Responder macro used by apb_m_driver and apb_m_driver_bfm + // to communicate Responder driven data to apb_m_driver_bfm. + `apb_m_RESPONDER_STRUCT + apb_m_responder_s responder_struct; + + // **************************************************************************** +// pragma uvmf custom reset_condition_and_response begin + // Always block used to return signals to reset value upon assertion of reset + always @( negedge presetn_i ) + begin + // RESPONDER mode output signals + prdata_o <= 'b0; + pready_o <= 0; + pslverr_o <= 0; + // INITIATOR mode output signals + psel_o <= 'b0; + penable_o <= 'b0; + paddr_o <= 'b0; + pwdata_o <= 'b0; + pwrite_o <= 'b0; + pstrb_o <= 'b0; + pprot_o <= 'b0; + // Bi-directional signals + + end +// pragma uvmf custom reset_condition_and_response end + + // pragma uvmf custom interface_item_additional begin + // pragma uvmf custom interface_item_additional end + + //****************************************************************** + // The configure() function is used to pass agent configuration + // variables to the driver BFM. It is called by the driver within + // the agent at the beginning of the simulation. It may be called + // during the simulation if agent configuration variables are updated + // and the driver BFM needs to be aware of the new configuration + // variables. + // + + function void configure(apb_m_configuration_s apb_m_configuration_arg); // pragma tbx xtf + initiator_responder = apb_m_configuration_arg.initiator_responder; + // pragma uvmf custom configure begin + // pragma uvmf custom configure end + endfunction + +// pragma uvmf custom initiate_and_get_response begin +// **************************************************************************** +// UVMF_CHANGE_ME +// This task is used by an initator. The task first initiates a transfer then +// waits for the responder to complete the transfer. + task initiate_and_get_response( + // This argument passes transaction variables used by an initiator + // to perform the initial part of a protocol transfer. The values + // come from a sequence item created in a sequence. + input apb_m_initiator_s apb_m_initiator_struct, + // This argument is used to send data received from the responder + // back to the sequence item. The sequence item is returned to the sequence. + output apb_m_responder_s apb_m_responder_struct + );// pragma tbx xtf + // + // Members within the apb_m_initiator_struct: + // bit psel ; + // bit penable ; + // bit [APB_ADDR_WIDTH-1:0] paddr ; + // bit [APB_DATA_WIDTH-1:0] pwdata ; + // bit pwrite ; + // bit [STRB_LEN:0] pstrb ; + // bit [3:0] pprot ; + // bit [APB_DATA_WIDTH-1:0] prdata ; + // bit pready ; + // bit pslverr ; + // Members within the apb_m_responder_struct: + // bit psel ; + // bit penable ; + // bit [APB_ADDR_WIDTH-1:0] paddr ; + // bit [APB_DATA_WIDTH-1:0] pwdata ; + // bit pwrite ; + // bit [STRB_LEN:0] pstrb ; + // bit [3:0] pprot ; + // bit [APB_DATA_WIDTH-1:0] prdata ; + // bit pready ; + // bit pslverr ; + initiator_struct = apb_m_initiator_struct; + // + // Reference code; + // How to wait for signal value + // while (control_signal == 1'b1) @(posedge pclk_i); + // + // How to assign a responder struct member, named xyz, from a signal. + // All available initiator input and inout signals listed. + // Initiator input signals + // apb_m_responder_struct.xyz = prdata_i; // [APB_DATA_WIDTH-1:0] + // apb_m_responder_struct.xyz = pready_i; // + // apb_m_responder_struct.xyz = pslverr_i; // + // Initiator inout signals + // How to assign a signal from an initiator struct member named xyz. + // All available initiator output and inout signals listed. + // Notice the _o. Those are storage variables that allow for procedural assignment. + // Initiator output signals + // psel_o <= apb_m_initiator_struct.xyz; // [15:0] + // penable_o <= apb_m_initiator_struct.xyz; // + // paddr_o <= apb_m_initiator_struct.xyz; // [APB_ADDR_WIDTH-1:0] + // pwdata_o <= apb_m_initiator_struct.xyz; // [APB_DATA_WIDTH-1:0] + // pwrite_o <= apb_m_initiator_struct.xyz; // + // pstrb_o <= apb_m_initiator_struct.xyz; // [STRB_LEN-1:0] + // pprot_o <= apb_m_initiator_struct.xyz; // [2:0] + // Initiator inout signals + // Initiate a transfer using the data received. + @(posedge pclk_i); + @(posedge pclk_i); + // Wait for the responder to complete the transfer then place the responder data into + // apb_m_responder_struct. + @(posedge pclk_i); + @(posedge pclk_i); + responder_struct = apb_m_responder_struct; + endtask +// pragma uvmf custom initiate_and_get_response end + +// pragma uvmf custom respond_and_wait_for_next_transfer begin +// **************************************************************************** +// The first_transfer variable is used to prevent completing a transfer in the +// first call to this task. For the first call to this task, there is not +// current transfer to complete. +bit first_transfer=1; + +// UVMF_CHANGE_ME +// This task is used by a responder. The task first completes the current +// transfer in progress then waits for the initiator to start the next transfer. + task respond_and_wait_for_next_transfer( + // This argument is used to send data received from the initiator + // back to the sequence item. The sequence determines how to respond. + output apb_m_initiator_s apb_m_initiator_struct, + // This argument passes transaction variables used by a responder + // to complete a protocol transfer. The values come from a sequence item. + input apb_m_responder_s apb_m_responder_struct + );// pragma tbx xtf + // Variables within the apb_m_initiator_struct: + // bit psel ; + // bit penable ; + // bit [APB_ADDR_WIDTH-1:0] paddr ; + // bit [APB_DATA_WIDTH-1:0] pwdata ; + // bit pwrite ; + // bit [STRB_LEN:0] pstrb ; + // bit [3:0] pprot ; + // bit [APB_DATA_WIDTH-1:0] prdata ; + // bit pready ; + // bit pslverr ; + // Variables within the apb_m_responder_struct: + // bit psel ; + // bit penable ; + // bit [APB_ADDR_WIDTH-1:0] paddr ; + // bit [APB_DATA_WIDTH-1:0] pwdata ; + // bit pwrite ; + // bit [STRB_LEN:0] pstrb ; + // bit [3:0] pprot ; + // bit [APB_DATA_WIDTH-1:0] prdata ; + // bit pready ; + // bit pslverr ; + // Reference code; + // How to wait for signal value + // while (control_signal == 1'b1) @(posedge pclk_i); + // + // How to assign a responder struct member, named xyz, from a signal. + // All available responder input and inout signals listed. + // Responder input signals + // apb_m_responder_struct.xyz = psel_i; // [15:0] + // apb_m_responder_struct.xyz = penable_i; // + // apb_m_responder_struct.xyz = paddr_i; // [APB_ADDR_WIDTH-1:0] + // apb_m_responder_struct.xyz = pwdata_i; // [APB_DATA_WIDTH-1:0] + // apb_m_responder_struct.xyz = pwrite_i; // + // apb_m_responder_struct.xyz = pstrb_i; // [STRB_LEN-1:0] + // apb_m_responder_struct.xyz = pprot_i; // [2:0] + // Responder inout signals + // How to assign a signal, named xyz, from an initiator struct member. + // All available responder output and inout signals listed. + // Notice the _o. Those are storage variables that allow for procedural assignment. + // Responder output signals + // prdata_o <= apb_m_initiator_struct.xyz; // [APB_DATA_WIDTH-1:0] + // pready_o <= apb_m_initiator_struct.xyz; // + // pslverr_o <= apb_m_initiator_struct.xyz; // + // Responder inout signals + + @(posedge pclk_i); + if (!first_transfer) begin + // Perform transfer response here. + // Reply using data recieved in the apb_m_responder_struct. + @(posedge pclk_i); + // Reply using data recieved in the transaction handle. + @(posedge pclk_i); + end + // Wait for next transfer then gather info from intiator about the transfer. + // Place the data into the apb_m_initiator_struct. + @(posedge pclk_i); + @(posedge pclk_i); + first_transfer = 0; + endtask +// pragma uvmf custom respond_and_wait_for_next_transfer end + + +endinterface + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/verification_ip/interface_packages/apb_m_pkg/src/apb_m_if.sv b/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/verification_ip/interface_packages/apb_m_pkg/src/apb_m_if.sv new file mode 100644 index 00000000..6747ba27 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/verification_ip/interface_packages/apb_m_pkg/src/apb_m_if.sv @@ -0,0 +1,113 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This interface contains the apb_m interface signals. +// It is instantiated once per apb_m bus. Bus Functional Models, +// BFM's named apb_m_driver_bfm, are used to drive signals on the bus. +// BFM's named apb_m_monitor_bfm are used to monitor signals on the +// bus. This interface signal bundle is passed in the port list of +// the BFM in order to give the BFM access to the signals in this +// interface. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// This template can be used to connect a DUT to these signals +// +// .dut_signal_port(apb_m_bus.psel), // Agent output +// .dut_signal_port(apb_m_bus.penable), // Agent output +// .dut_signal_port(apb_m_bus.paddr), // Agent output +// .dut_signal_port(apb_m_bus.pwdata), // Agent output +// .dut_signal_port(apb_m_bus.pwrite), // Agent output +// .dut_signal_port(apb_m_bus.pstrb), // Agent output +// .dut_signal_port(apb_m_bus.pprot), // Agent output +// .dut_signal_port(apb_m_bus.prdata), // Agent input +// .dut_signal_port(apb_m_bus.pready), // Agent input +// .dut_signal_port(apb_m_bus.pslverr), // Agent input + +import uvmf_base_pkg_hdl::*; +import apb_m_pkg_hdl::*; + +interface apb_m_if #( + int APB_ADDR_WIDTH = 32, + int APB_DATA_WIDTH = 32, + int STRB_LEN = APB_ADDR_WIDTH/8 + ) + + ( + input logic pclk, + input logic presetn, + output logic [15:0] psel, + output logic penable, + output logic [APB_ADDR_WIDTH-1:0] paddr, + output logic [APB_DATA_WIDTH-1:0] pwdata, + output logic pwrite, + output logic [STRB_LEN-1:0] pstrb, + output logic [2:0] pprot, + input logic [APB_DATA_WIDTH-1:0] prdata, + input logic pready, + input logic pslverr + ); + +modport monitor_port + ( + input pclk, + input presetn, + input psel, + input penable, + input paddr, + input pwdata, + input pwrite, + input pstrb, + input pprot, + input prdata, + input pready, + input pslverr + ); + +modport initiator_port + ( + input pclk, + input presetn, + output psel, + output penable, + output paddr, + output pwdata, + output pwrite, + output pstrb, + output pprot, + input prdata, + input pready, + input pslverr + ); + +modport responder_port + ( + input pclk, + input presetn, + input psel, + input penable, + input paddr, + input pwdata, + input pwrite, + input pstrb, + input pprot, + output prdata, + output pready, + output pslverr + ); + + +// pragma uvmf custom interface_item_additional begin +// pragma uvmf custom interface_item_additional end + +endinterface + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/verification_ip/interface_packages/apb_m_pkg/src/apb_m_infact_coverage_strategy.csv b/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/verification_ip/interface_packages/apb_m_pkg/src/apb_m_infact_coverage_strategy.csv new file mode 100644 index 00000000..1c218e14 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/verification_ip/interface_packages/apb_m_pkg/src/apb_m_infact_coverage_strategy.csv @@ -0,0 +1,6 @@ +Global +auto_bin_max, 64 + +Name,Type,Include +rand_fields,coverpoint,=rand *.** + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/verification_ip/interface_packages/apb_m_pkg/src/apb_m_macros.svh b/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/verification_ip/interface_packages/apb_m_pkg/src/apb_m_macros.svh new file mode 100644 index 00000000..631c4b12 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/verification_ip/interface_packages/apb_m_pkg/src/apb_m_macros.svh @@ -0,0 +1,202 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This file contains macros used with the apb_m package. +// These macros include packed struct definitions. These structs are +// used to pass data between classes, hvl, and BFM's, hdl. Use of +// structs are more efficient and simpler to modify. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// + +// **************************************************************************** +// When changing the contents of this struct, be sure to update the to_struct +// and from_struct methods defined in the macros below that are used in +// the apb_m_configuration class. +// + `define apb_m_CONFIGURATION_STRUCT \ +typedef struct packed { \ + uvmf_active_passive_t active_passive; \ + uvmf_initiator_responder_t initiator_responder; \ + } apb_m_configuration_s; + + `define apb_m_CONFIGURATION_TO_STRUCT_FUNCTION \ + virtual function apb_m_configuration_s to_struct();\ + apb_m_configuration_struct = \ + {\ + this.active_passive,\ + this.initiator_responder\ + };\ + return ( apb_m_configuration_struct );\ + endfunction + + `define apb_m_CONFIGURATION_FROM_STRUCT_FUNCTION \ + virtual function void from_struct(apb_m_configuration_s apb_m_configuration_struct);\ + {\ + this.active_passive,\ + this.initiator_responder \ + } = apb_m_configuration_struct;\ + endfunction + +// **************************************************************************** +// When changing the contents of this struct, be sure to update the to_monitor_struct +// and from_monitor_struct methods of the apb_m_transaction class. +// + `define apb_m_MONITOR_STRUCT typedef struct packed { \ + bit psel ; \ + bit penable ; \ + bit [APB_ADDR_WIDTH-1:0] paddr ; \ + bit [APB_DATA_WIDTH-1:0] pwdata ; \ + bit pwrite ; \ + bit [STRB_LEN:0] pstrb ; \ + bit [3:0] pprot ; \ + bit [APB_DATA_WIDTH-1:0] prdata ; \ + bit pready ; \ + bit pslverr ; \ + } apb_m_monitor_s; + + `define apb_m_TO_MONITOR_STRUCT_FUNCTION \ + virtual function apb_m_monitor_s to_monitor_struct();\ + apb_m_monitor_struct = \ + { \ + this.psel , \ + this.penable , \ + this.paddr , \ + this.pwdata , \ + this.pwrite , \ + this.pstrb , \ + this.pprot , \ + this.prdata , \ + this.pready , \ + this.pslverr \ + };\ + return ( apb_m_monitor_struct);\ + endfunction\ + + `define apb_m_FROM_MONITOR_STRUCT_FUNCTION \ + virtual function void from_monitor_struct(apb_m_monitor_s apb_m_monitor_struct);\ + {\ + this.psel , \ + this.penable , \ + this.paddr , \ + this.pwdata , \ + this.pwrite , \ + this.pstrb , \ + this.pprot , \ + this.prdata , \ + this.pready , \ + this.pslverr \ + } = apb_m_monitor_struct;\ + endfunction + +// **************************************************************************** +// When changing the contents of this struct, be sure to update the to_initiator_struct +// and from_initiator_struct methods of the apb_m_transaction class. +// Also update the comments in the driver BFM. +// + `define apb_m_INITIATOR_STRUCT typedef struct packed { \ + bit psel ; \ + bit penable ; \ + bit [APB_ADDR_WIDTH-1:0] paddr ; \ + bit [APB_DATA_WIDTH-1:0] pwdata ; \ + bit pwrite ; \ + bit [STRB_LEN:0] pstrb ; \ + bit [3:0] pprot ; \ + bit [APB_DATA_WIDTH-1:0] prdata ; \ + bit pready ; \ + bit pslverr ; \ + } apb_m_initiator_s; + + `define apb_m_TO_INITIATOR_STRUCT_FUNCTION \ + virtual function apb_m_initiator_s to_initiator_struct();\ + apb_m_initiator_struct = \ + {\ + this.psel , \ + this.penable , \ + this.paddr , \ + this.pwdata , \ + this.pwrite , \ + this.pstrb , \ + this.pprot , \ + this.prdata , \ + this.pready , \ + this.pslverr \ + };\ + return ( apb_m_initiator_struct);\ + endfunction + + `define apb_m_FROM_INITIATOR_STRUCT_FUNCTION \ + virtual function void from_initiator_struct(apb_m_initiator_s apb_m_initiator_struct);\ + {\ + this.psel , \ + this.penable , \ + this.paddr , \ + this.pwdata , \ + this.pwrite , \ + this.pstrb , \ + this.pprot , \ + this.prdata , \ + this.pready , \ + this.pslverr \ + } = apb_m_initiator_struct;\ + endfunction + +// **************************************************************************** +// When changing the contents of this struct, be sure to update the to_responder_struct +// and from_responder_struct methods of the apb_m_transaction class. +// Also update the comments in the driver BFM. +// + `define apb_m_RESPONDER_STRUCT typedef struct packed { \ + bit psel ; \ + bit penable ; \ + bit [APB_ADDR_WIDTH-1:0] paddr ; \ + bit [APB_DATA_WIDTH-1:0] pwdata ; \ + bit pwrite ; \ + bit [STRB_LEN:0] pstrb ; \ + bit [3:0] pprot ; \ + bit [APB_DATA_WIDTH-1:0] prdata ; \ + bit pready ; \ + bit pslverr ; \ + } apb_m_responder_s; + + `define apb_m_TO_RESPONDER_STRUCT_FUNCTION \ + virtual function apb_m_responder_s to_responder_struct();\ + apb_m_responder_struct = \ + {\ + this.psel , \ + this.penable , \ + this.paddr , \ + this.pwdata , \ + this.pwrite , \ + this.pstrb , \ + this.pprot , \ + this.prdata , \ + this.pready , \ + this.pslverr \ + };\ + return ( apb_m_responder_struct);\ + endfunction + + `define apb_m_FROM_RESPONDER_STRUCT_FUNCTION \ + virtual function void from_responder_struct(apb_m_responder_s apb_m_responder_struct);\ + {\ + this.psel , \ + this.penable , \ + this.paddr , \ + this.pwdata , \ + this.pwrite , \ + this.pstrb , \ + this.pprot , \ + this.prdata , \ + this.pready , \ + this.pslverr \ + } = apb_m_responder_struct;\ + endfunction +// pragma uvmf custom additional begin +// pragma uvmf custom additional end diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/verification_ip/interface_packages/apb_m_pkg/src/apb_m_monitor.svh b/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/verification_ip/interface_packages/apb_m_pkg/src/apb_m_monitor.svh new file mode 100644 index 00000000..7f0c5966 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/verification_ip/interface_packages/apb_m_pkg/src/apb_m_monitor.svh @@ -0,0 +1,107 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This class receives apb_m transactions observed by the +// apb_m monitor BFM and broadcasts them through the analysis port +// on the agent. It accesses the monitor BFM through the monitor +// task. This UVM component captures transactions +// for viewing in the waveform viewer if the +// enable_transaction_viewing flag is set in the configuration. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class apb_m_monitor #( + int APB_ADDR_WIDTH = 32, + int APB_DATA_WIDTH = 32, + int STRB_LEN = APB_ADDR_WIDTH/8 + ) extends uvmf_monitor_base #( + .CONFIG_T(apb_m_configuration #( + .APB_ADDR_WIDTH(APB_ADDR_WIDTH), + .APB_DATA_WIDTH(APB_DATA_WIDTH), + .STRB_LEN(STRB_LEN) + )), + .BFM_BIND_T(virtual apb_m_monitor_bfm #( + .APB_ADDR_WIDTH(APB_ADDR_WIDTH), + .APB_DATA_WIDTH(APB_DATA_WIDTH), + .STRB_LEN(STRB_LEN) + )), + .TRANS_T(apb_m_transaction #( + .APB_ADDR_WIDTH(APB_ADDR_WIDTH), + .APB_DATA_WIDTH(APB_DATA_WIDTH), + .STRB_LEN(STRB_LEN) + ))); + + `uvm_component_param_utils( apb_m_monitor #( + APB_ADDR_WIDTH, + APB_DATA_WIDTH, + STRB_LEN + )) + +// Structure used to pass data from monitor BFM to monitor class in agent. +// Use to_monitor_struct function to pack transaction variables into structure. +// Use from_monitor_struct function to unpack transaction variables from structure. +`apb_m_MONITOR_STRUCT + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + +// **************************************************************************** +// This function is the standard SystemVerilog constructor. +// + function new( string name = "", uvm_component parent = null ); + super.new( name, parent ); + endfunction + +// **************************************************************************** +// This function sends configuration object variables to the monitor BFM +// using the configuration struct. +// + virtual function void configure(input CONFIG_T cfg); + bfm.configure( cfg.to_struct() ); + + endfunction + +// **************************************************************************** +// This function places a handle to this class in the proxy variable in the +// monitor BFM. This allows the monitor BFM to call the notify_transaction +// function within this class. +// + virtual function void set_bfm_proxy_handle(); + bfm.proxy = this; endfunction + +// *************************************************************************** + virtual task run_phase(uvm_phase phase); + // Start monitor BFM thread and don't call super.run() in order to + // override the default monitor proxy 'pull' behavior with the more + // emulation-friendly BFM 'push' approach using the notify_transaction + // function below + bfm.start_monitoring(); + endtask + +// ************************************************************************** + +// This function is called by the monitor BFM. It receives data observed by the +// monitor BFM. Data is passed using the apb_m_monitor_struct. + virtual function void notify_transaction(input apb_m_monitor_s apb_m_monitor_struct); + + + trans = new("trans"); + trans.from_monitor_struct(apb_m_monitor_struct); + trans.start_time = time_stamp; + trans.end_time = $time; + time_stamp = trans.end_time; + + analyze(trans); + endfunction + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/verification_ip/interface_packages/apb_m_pkg/src/apb_m_monitor_bfm.sv b/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/verification_ip/interface_packages/apb_m_pkg/src/apb_m_monitor_bfm.sv new file mode 100644 index 00000000..c1f68c5a --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/verification_ip/interface_packages/apb_m_pkg/src/apb_m_monitor_bfm.sv @@ -0,0 +1,218 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This interface performs the apb_m signal monitoring. +// It is accessed by the uvm apb_m monitor through a virtual +// interface handle in the apb_m configuration. It monitors the +// signals passed in through the port connection named bus of +// type apb_m_if. +// +// Input signals from the apb_m_if are assigned to an internal input +// signal with a _i suffix. The _i signal should be used for sampling. +// +// The input signal connections are as follows: +// bus.signal -> signal_i +// +// Interface functions and tasks used by UVM components: +// monitor(inout TRANS_T txn); +// This task receives the transaction, txn, from the +// UVM monitor and then populates variables in txn +// from values observed on bus activity. This task +// blocks until an operation on the apb_m bus is complete. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +import uvmf_base_pkg_hdl::*; +import apb_m_pkg_hdl::*; +`include "src/apb_m_macros.svh" + + +interface apb_m_monitor_bfm #( + int APB_ADDR_WIDTH = 32, + int APB_DATA_WIDTH = 32, + int STRB_LEN = APB_ADDR_WIDTH/8 + ) + ( apb_m_if bus ); + // The pragma below and additional ones in-lined further down are for running this BFM on Veloce + // pragma attribute apb_m_monitor_bfm partition_interface_xif + +`ifndef XRTL +// This code is to aid in debugging parameter mismatches between the BFM and its corresponding agent. +// Enable this debug by setting UVM_VERBOSITY to UVM_DEBUG +// Setting UVM_VERBOSITY to UVM_DEBUG causes all BFM's and all agents to display their parameter settings. +// All of the messages from this feature have a UVM messaging id value of "CFG" +// The transcript or run.log can be parsed to ensure BFM parameter settings match its corresponding agents parameter settings. +import uvm_pkg::*; +`include "uvm_macros.svh" +initial begin : bfm_vs_agent_parameter_debug + `uvm_info("CFG", + $psprintf("The BFM at '%m' has the following parameters: APB_ADDR_WIDTH=%x APB_DATA_WIDTH=%x STRB_LEN=%x ", APB_ADDR_WIDTH,APB_DATA_WIDTH,STRB_LEN), + UVM_DEBUG) +end +`endif + + + // Structure used to pass transaction data from monitor BFM to monitor class in agent. +`apb_m_MONITOR_STRUCT + apb_m_monitor_s apb_m_monitor_struct; + + // Structure used to pass configuration data from monitor class to monitor BFM. + `apb_m_CONFIGURATION_STRUCT + + + // Config value to determine if this is an initiator or a responder + uvmf_initiator_responder_t initiator_responder; + // Custom configuration variables. + // These are set using the configure function which is called during the UVM connect_phase + + logic pclk_i; + logic presetn_i; + tri [15:0] psel_i; + tri penable_i; + tri [APB_ADDR_WIDTH-1:0] paddr_i; + tri [APB_DATA_WIDTH-1:0] pwdata_i; + tri pwrite_i; + tri [STRB_LEN-1:0] pstrb_i; + tri [2:0] pprot_i; + tri [APB_DATA_WIDTH-1:0] prdata_i; + tri pready_i; + tri pslverr_i; + assign pclk_i = bus.pclk; + assign presetn_i = bus.presetn; + assign psel_i = bus.psel; + assign penable_i = bus.penable; + assign paddr_i = bus.paddr; + assign pwdata_i = bus.pwdata; + assign pwrite_i = bus.pwrite; + assign pstrb_i = bus.pstrb; + assign pprot_i = bus.pprot; + assign prdata_i = bus.prdata; + assign pready_i = bus.pready; + assign pslverr_i = bus.pslverr; + + // Proxy handle to UVM monitor + apb_m_pkg::apb_m_monitor #( + .APB_ADDR_WIDTH(APB_ADDR_WIDTH), + .APB_DATA_WIDTH(APB_DATA_WIDTH), + .STRB_LEN(STRB_LEN) + ) proxy; + // pragma tbx oneway proxy.notify_transaction + + // pragma uvmf custom interface_item_additional begin + // pragma uvmf custom interface_item_additional end + + //****************************************************************** + task wait_for_reset();// pragma tbx xtf + @(posedge pclk_i) ; + do_wait_for_reset(); + endtask + + // **************************************************************************** + task do_wait_for_reset(); + // pragma uvmf custom reset_condition begin + wait ( presetn_i === 1 ) ; + @(posedge pclk_i) ; + // pragma uvmf custom reset_condition end + endtask + + //****************************************************************** + + task wait_for_num_clocks(input int unsigned count); // pragma tbx xtf + @(posedge pclk_i); + + repeat (count-1) @(posedge pclk_i); + endtask + + //****************************************************************** + event go; + function void start_monitoring();// pragma tbx xtf + -> go; + endfunction + + // **************************************************************************** + initial begin + @go; + forever begin + @(posedge pclk_i); + do_monitor( apb_m_monitor_struct ); + + + proxy.notify_transaction( apb_m_monitor_struct ); + + end + end + + //****************************************************************** + // The configure() function is used to pass agent configuration + // variables to the monitor BFM. It is called by the monitor within + // the agent at the beginning of the simulation. It may be called + // during the simulation if agent configuration variables are updated + // and the monitor BFM needs to be aware of the new configuration + // variables. + // + function void configure(apb_m_configuration_s apb_m_configuration_arg); // pragma tbx xtf + initiator_responder = apb_m_configuration_arg.initiator_responder; + // pragma uvmf custom configure begin + // pragma uvmf custom configure end + endfunction + + + // **************************************************************************** + + task do_monitor(output apb_m_monitor_s apb_m_monitor_struct); + // + // Available struct members: + // // apb_m_monitor_struct.psel + // // apb_m_monitor_struct.penable + // // apb_m_monitor_struct.paddr + // // apb_m_monitor_struct.pwdata + // // apb_m_monitor_struct.pwrite + // // apb_m_monitor_struct.pstrb + // // apb_m_monitor_struct.pprot + // // apb_m_monitor_struct.prdata + // // apb_m_monitor_struct.pready + // // apb_m_monitor_struct.pslverr + // // + // Reference code; + // How to wait for signal value + // while (control_signal === 1'b1) @(posedge pclk_i); + // + // How to assign a struct member, named xyz, from a signal. + // All available input signals listed. + // apb_m_monitor_struct.xyz = psel_i; // [15:0] + // apb_m_monitor_struct.xyz = penable_i; // + // apb_m_monitor_struct.xyz = paddr_i; // [APB_ADDR_WIDTH-1:0] + // apb_m_monitor_struct.xyz = pwdata_i; // [APB_DATA_WIDTH-1:0] + // apb_m_monitor_struct.xyz = pwrite_i; // + // apb_m_monitor_struct.xyz = pstrb_i; // [STRB_LEN-1:0] + // apb_m_monitor_struct.xyz = pprot_i; // [2:0] + // apb_m_monitor_struct.xyz = prdata_i; // [APB_DATA_WIDTH-1:0] + // apb_m_monitor_struct.xyz = pready_i; // + // apb_m_monitor_struct.xyz = pslverr_i; // + // pragma uvmf custom do_monitor begin + // UVMF_CHANGE_ME : Implement protocol monitoring. The commented reference code + // below are examples of how to capture signal values and assign them to + // structure members. All available input signals are listed. The 'while' + // code example shows how to wait for a synchronous flow control signal. This + // task should return when a complete transfer has been observed. Once this task is + // exited with captured values, it is then called again to wait for and observe + // the next transfer. One clock cycle is consumed between calls to do_monitor. + @(posedge pclk_i); + @(posedge pclk_i); + @(posedge pclk_i); + @(posedge pclk_i); + // pragma uvmf custom do_monitor end + endtask + + +endinterface + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/verification_ip/interface_packages/apb_m_pkg/src/apb_m_random_sequence.svh b/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/verification_ip/interface_packages/apb_m_pkg/src/apb_m_random_sequence.svh new file mode 100644 index 00000000..6ad36e08 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/verification_ip/interface_packages/apb_m_pkg/src/apb_m_random_sequence.svh @@ -0,0 +1,69 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: +// This sequences randomizes the apb_m transaction and sends it +// to the UVM driver. +// +// This sequence constructs and randomizes a apb_m_transaction. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class apb_m_random_sequence #( + int APB_ADDR_WIDTH = 32, + int APB_DATA_WIDTH = 32, + int STRB_LEN = APB_ADDR_WIDTH/8 + ) + extends apb_m_sequence_base #( + .APB_ADDR_WIDTH(APB_ADDR_WIDTH), + .APB_DATA_WIDTH(APB_DATA_WIDTH), + .STRB_LEN(STRB_LEN) + ); + + `uvm_object_param_utils( apb_m_random_sequence #( + APB_ADDR_WIDTH, + APB_DATA_WIDTH, + STRB_LEN + )) + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + //***************************************************************** + function new(string name = ""); + super.new(name); + endfunction: new + + // **************************************************************************** + // TASK : body() + // This task is automatically executed when this sequence is started using the + // start(sequencerHandle) task. + // + task body(); + + // Construct the transaction + req=apb_m_transaction#( + .APB_ADDR_WIDTH(APB_ADDR_WIDTH), + .APB_DATA_WIDTH(APB_DATA_WIDTH), + .STRB_LEN(STRB_LEN) + )::type_id::create("req"); + start_item(req); + // Randomize the transaction + if(!req.randomize()) `uvm_fatal("SEQ", "apb_m_random_sequence::body()-apb_m_transaction randomization failed") + // Send the transaction to the apb_m_driver_bfm via the sequencer and apb_m_driver. + finish_item(req); + `uvm_info("SEQ", {"Response:",req.convert2string()},UVM_MEDIUM) + + endtask + +endclass: apb_m_random_sequence + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/verification_ip/interface_packages/apb_m_pkg/src/apb_m_responder_sequence.svh b/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/verification_ip/interface_packages/apb_m_pkg/src/apb_m_responder_sequence.svh new file mode 100644 index 00000000..b493b9c2 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/verification_ip/interface_packages/apb_m_pkg/src/apb_m_responder_sequence.svh @@ -0,0 +1,65 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This class can be used to provide stimulus when an interface +// has been configured to run in a responder mode. It +// will never finish by default, always going back to the driver +// and driver BFM for the next transaction with which to respond. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class apb_m_responder_sequence #( + int APB_ADDR_WIDTH = 32, + int APB_DATA_WIDTH = 32, + int STRB_LEN = APB_ADDR_WIDTH/8 + ) + extends apb_m_sequence_base #( + .APB_ADDR_WIDTH(APB_ADDR_WIDTH), + .APB_DATA_WIDTH(APB_DATA_WIDTH), + .STRB_LEN(STRB_LEN) + ); + + `uvm_object_param_utils( apb_m_responder_sequence #( + APB_ADDR_WIDTH, + APB_DATA_WIDTH, + STRB_LEN + )) + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + function new(string name = "apb_m_responder_sequence"); + super.new(name); + endfunction + + task body(); + req=apb_m_transaction#( + .APB_ADDR_WIDTH(APB_ADDR_WIDTH), + .APB_DATA_WIDTH(APB_DATA_WIDTH), + .STRB_LEN(STRB_LEN) + )::type_id::create("req"); + forever begin + start_item(req); + finish_item(req); + // pragma uvmf custom body begin + // UVMF_CHANGE_ME : Do something here with the resulting req item. The + // finish_item() call above will block until the req transaction is ready + // to be handled by the responder sequence. + // If this was an item that required a response, the expectation is + // that the response should be populated within this transaction now. + `uvm_info("SEQ",$sformatf("Processed txn: %s",req.convert2string()),UVM_HIGH) + // pragma uvmf custom body end + end + endtask + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/verification_ip/interface_packages/apb_m_pkg/src/apb_m_sequence_base.svh b/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/verification_ip/interface_packages/apb_m_pkg/src/apb_m_sequence_base.svh new file mode 100644 index 00000000..df1d671e --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/verification_ip/interface_packages/apb_m_pkg/src/apb_m_sequence_base.svh @@ -0,0 +1,120 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: +// This file contains the class used as the base class for all sequences +// for this interface. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class apb_m_sequence_base #( + int APB_ADDR_WIDTH = 32, + int APB_DATA_WIDTH = 32, + int STRB_LEN = APB_ADDR_WIDTH/8 + ) extends uvmf_sequence_base #( + .REQ(apb_m_transaction #( + .APB_ADDR_WIDTH(APB_ADDR_WIDTH), + .APB_DATA_WIDTH(APB_DATA_WIDTH), + .STRB_LEN(STRB_LEN) + )), + .RSP(apb_m_transaction #( + .APB_ADDR_WIDTH(APB_ADDR_WIDTH), + .APB_DATA_WIDTH(APB_DATA_WIDTH), + .STRB_LEN(STRB_LEN) + ))); + + `uvm_object_param_utils( apb_m_sequence_base #( + APB_ADDR_WIDTH, + APB_DATA_WIDTH, + STRB_LEN + )) + + // variables + typedef apb_m_transaction #( + .APB_ADDR_WIDTH(APB_ADDR_WIDTH), + .APB_DATA_WIDTH(APB_DATA_WIDTH), + .STRB_LEN(STRB_LEN) + ) apb_m_transaction_req_t; + apb_m_transaction_req_t req; + typedef apb_m_transaction #( + .APB_ADDR_WIDTH(APB_ADDR_WIDTH), + .APB_DATA_WIDTH(APB_DATA_WIDTH), + .STRB_LEN(STRB_LEN) + ) apb_m_transaction_rsp_t; + apb_m_transaction_rsp_t rsp; + + // Event for identifying when a response was received from the sequencer + event new_rsp; + + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + // **************************************************************************** + // TASK : get_responses() + // This task recursively gets sequence item responses from the sequencer. + // + virtual task get_responses(); + fork + begin + // Block until new rsp available + get_response(rsp); + // New rsp received. Indicate to sequence using event. + ->new_rsp; + // Display the received response transaction + `uvm_info("SEQ", {"New response transaction:",rsp.convert2string()}, UVM_MEDIUM) + end + join_none + endtask + + // **************************************************************************** + // TASK : pre_body() + // This task is called automatically when start is called with call_pre_post set to 1 (default). + // By calling get_responses() within pre_body() any derived sequences are automatically + // processing response transactions. Only un-comment this call to get_responses() if you + // have configured the interface driver to utilize the response transaction path by setting + // the configuration variable "return_transaction_response" to 1. Otherwise it is possible + // to impact runtime performance and memory utilization. + // + virtual task pre_body(); + // pragma uvmf custom pre_body begin +// get_responses(); + // pragma uvmf custom pre_body end + endtask + + // **************************************************************************** + // TASK : body() + // This task is called automatically when start is called. This sequence sends + // a req sequence item to the sequencer identified as an argument in the call + // to start. + // + virtual task body(); + // pragma uvmf custom body begin + start_item(req); + finish_item(req); + // pragma uvmf custom body end + endtask + + // **************************************************************************** + // FUNCTION : new() + // This function is the standard SystemVerilog constructor. + // + function new( string name =""); + super.new( name ); + // pragma uvmf custom new begin + req = apb_m_transaction_req_t::type_id::create("req"); + rsp = apb_m_transaction_rsp_t::type_id::create("rsp"); + // pragma uvmf custom new end + endfunction + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/verification_ip/interface_packages/apb_m_pkg/src/apb_m_transaction.svh b/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/verification_ip/interface_packages/apb_m_pkg/src/apb_m_transaction.svh new file mode 100644 index 00000000..f254cabe --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/verification_ip/interface_packages/apb_m_pkg/src/apb_m_transaction.svh @@ -0,0 +1,233 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This class defines the variables required for an apb_m +// transaction. Class variables to be displayed in waveform transaction +// viewing are added to the transaction viewing stream in the add_to_wave +// function. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class apb_m_transaction #( + int APB_ADDR_WIDTH = 32, + int APB_DATA_WIDTH = 32, + int STRB_LEN = APB_ADDR_WIDTH/8 + ) extends uvmf_transaction_base; + + `uvm_object_param_utils( apb_m_transaction #( + APB_ADDR_WIDTH, + APB_DATA_WIDTH, + STRB_LEN + )) + + rand bit psel ; + rand bit penable ; + rand bit [APB_ADDR_WIDTH-1:0] paddr ; + rand bit [APB_DATA_WIDTH-1:0] pwdata ; + rand bit pwrite ; + rand bit [STRB_LEN:0] pstrb ; + rand bit [3:0] pprot ; + bit [APB_DATA_WIDTH-1:0] prdata ; + bit pready ; + bit pslverr ; + + //Constraints for the transaction variables: + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + //******************************************************************* + //******************************************************************* + // Macros that define structs and associated functions are + // located in apb_m_macros.svh + + //******************************************************************* + // Monitor macro used by apb_m_monitor and apb_m_monitor_bfm + // This struct is defined in apb_m_macros.svh + `apb_m_MONITOR_STRUCT + apb_m_monitor_s apb_m_monitor_struct; + //******************************************************************* + // FUNCTION: to_monitor_struct() + // This function packs transaction variables into a apb_m_monitor_s + // structure. The function returns the handle to the apb_m_monitor_struct. + // This function is defined in apb_m_macros.svh + `apb_m_TO_MONITOR_STRUCT_FUNCTION + //******************************************************************* + // FUNCTION: from_monitor_struct() + // This function unpacks the struct provided as an argument into transaction + // variables of this class. + // This function is defined in apb_m_macros.svh + `apb_m_FROM_MONITOR_STRUCT_FUNCTION + + //******************************************************************* + // Initiator macro used by apb_m_driver and apb_m_driver_bfm + // to communicate initiator driven data to apb_m_driver_bfm. + // This struct is defined in apb_m_macros.svh + `apb_m_INITIATOR_STRUCT + apb_m_initiator_s apb_m_initiator_struct; + //******************************************************************* + // FUNCTION: to_initiator_struct() + // This function packs transaction variables into a apb_m_initiator_s + // structure. The function returns the handle to the apb_m_initiator_struct. + // This function is defined in apb_m_macros.svh + `apb_m_TO_INITIATOR_STRUCT_FUNCTION + //******************************************************************* + // FUNCTION: from_initiator_struct() + // This function unpacks the struct provided as an argument into transaction + // variables of this class. + // This function is defined in apb_m_macros.svh + `apb_m_FROM_INITIATOR_STRUCT_FUNCTION + + //******************************************************************* + // Responder macro used by apb_m_driver and apb_m_driver_bfm + // to communicate Responder driven data to apb_m_driver_bfm. + // This struct is defined in apb_m_macros.svh + `apb_m_RESPONDER_STRUCT + apb_m_responder_s apb_m_responder_struct; + //******************************************************************* + // FUNCTION: to_responder_struct() + // This function packs transaction variables into a apb_m_responder_s + // structure. The function returns the handle to the apb_m_responder_struct. + // This function is defined in apb_m_macros.svh + `apb_m_TO_RESPONDER_STRUCT_FUNCTION + //******************************************************************* + // FUNCTION: from_responder_struct() + // This function unpacks the struct provided as an argument into transaction + // variables of this class. + // This function is defined in apb_m_macros.svh + `apb_m_FROM_RESPONDER_STRUCT_FUNCTION + // **************************************************************************** + // FUNCTION : new() + // This function is the standard SystemVerilog constructor. + // + function new( string name = "" ); + super.new( name ); + endfunction + + // **************************************************************************** + // FUNCTION: convert2string() + // This function converts all variables in this class to a single string for + // logfile reporting. + // + virtual function string convert2string(); + // pragma uvmf custom convert2string begin + // UVMF_CHANGE_ME : Customize format if desired. + return $sformatf("psel:0x%x penable:0x%x paddr:0x%x pwdata:0x%x pwrite:0x%x pstrb:0x%x pprot:0x%x prdata:0x%x pready:0x%x pslverr:0x%x ",psel,penable,paddr,pwdata,pwrite,pstrb,pprot,prdata,pready,pslverr); + // pragma uvmf custom convert2string end + endfunction + + //******************************************************************* + // FUNCTION: do_print() + // This function is automatically called when the .print() function + // is called on this class. + // + virtual function void do_print(uvm_printer printer); + // pragma uvmf custom do_print begin + // UVMF_CHANGE_ME : Current contents of do_print allows for the use of UVM 1.1d, 1.2 or P1800.2. + // Update based on your own printing preference according to your preferred UVM version + $display(convert2string()); + // pragma uvmf custom do_print end + endfunction + + //******************************************************************* + // FUNCTION: do_compare() + // This function is automatically called when the .compare() function + // is called on this class. + // + virtual function bit do_compare (uvm_object rhs, uvm_comparer comparer); + apb_m_transaction #( + .APB_ADDR_WIDTH(APB_ADDR_WIDTH), + .APB_DATA_WIDTH(APB_DATA_WIDTH), + .STRB_LEN(STRB_LEN) + ) RHS; + if (!$cast(RHS,rhs)) return 0; + // pragma uvmf custom do_compare begin + // UVMF_CHANGE_ME : Eliminate comparison of variables not to be used for compare + return (super.do_compare(rhs,comparer) + &&(this.penable == RHS.penable) + &&(this.paddr == RHS.paddr) + &&(this.pwdata == RHS.pwdata) + &&(this.pwrite == RHS.pwrite) + &&(this.pstrb == RHS.pstrb) + &&(this.pprot == RHS.pprot) + &&(this.prdata == RHS.prdata) + &&(this.pready == RHS.pready) + &&(this.pslverr == RHS.pslverr) + ); + // pragma uvmf custom do_compare end + endfunction + + //******************************************************************* + // FUNCTION: do_copy() + // This function is automatically called when the .copy() function + // is called on this class. + // + virtual function void do_copy (uvm_object rhs); + apb_m_transaction #( + .APB_ADDR_WIDTH(APB_ADDR_WIDTH), + .APB_DATA_WIDTH(APB_DATA_WIDTH), + .STRB_LEN(STRB_LEN) + ) RHS; + assert($cast(RHS,rhs)); + // pragma uvmf custom do_copy begin + super.do_copy(rhs); + this.psel = RHS.psel; + this.penable = RHS.penable; + this.paddr = RHS.paddr; + this.pwdata = RHS.pwdata; + this.pwrite = RHS.pwrite; + this.pstrb = RHS.pstrb; + this.pprot = RHS.pprot; + this.prdata = RHS.prdata; + this.pready = RHS.pready; + this.pslverr = RHS.pslverr; + // pragma uvmf custom do_copy end + endfunction + + // **************************************************************************** + // FUNCTION: add_to_wave() + // This function is used to display variables in this class in the waveform + // viewer. The start_time and end_time variables must be set before this + // function is called. If the start_time and end_time variables are not set + // the transaction will be hidden at 0ns on the waveform display. + // + virtual function void add_to_wave(int transaction_viewing_stream_h); + `ifdef QUESTA + if (transaction_view_h == 0) begin + transaction_view_h = $begin_transaction(transaction_viewing_stream_h,"apb_m_transaction",start_time); + end + super.add_to_wave(transaction_view_h); + // pragma uvmf custom add_to_wave begin + // UVMF_CHANGE_ME : Color can be applied to transaction entries based on content, example below + // case() + // 1 : $add_color(transaction_view_h,"red"); + // default : $add_color(transaction_view_h,"grey"); + // endcase + // UVMF_CHANGE_ME : Eliminate transaction variables not wanted in transaction viewing in the waveform viewer + $add_attribute(transaction_view_h,psel,"psel"); + $add_attribute(transaction_view_h,penable,"penable"); + $add_attribute(transaction_view_h,paddr,"paddr"); + $add_attribute(transaction_view_h,pwdata,"pwdata"); + $add_attribute(transaction_view_h,pwrite,"pwrite"); + $add_attribute(transaction_view_h,pstrb,"pstrb"); + $add_attribute(transaction_view_h,pprot,"pprot"); + $add_attribute(transaction_view_h,prdata,"prdata"); + $add_attribute(transaction_view_h,pready,"pready"); + $add_attribute(transaction_view_h,pslverr,"pslverr"); + // pragma uvmf custom add_to_wave end + $end_transaction(transaction_view_h,end_time); + $free_transaction(transaction_view_h); + `endif // QUESTA + endfunction + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/verification_ip/interface_packages/apb_m_pkg/src/apb_m_transaction_coverage.svh b/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/verification_ip/interface_packages/apb_m_pkg/src/apb_m_transaction_coverage.svh new file mode 100644 index 00000000..0d1b9c58 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/verification_ip/interface_packages/apb_m_pkg/src/apb_m_transaction_coverage.svh @@ -0,0 +1,91 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This class records apb_m transaction information using +// a covergroup named apb_m_transaction_cg. An instance of this +// coverage component is instantiated in the uvmf_parameterized_agent +// if the has_coverage flag is set. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class apb_m_transaction_coverage #( + int APB_ADDR_WIDTH = 32, + int APB_DATA_WIDTH = 32, + int STRB_LEN = APB_ADDR_WIDTH/8 + ) extends uvm_subscriber #(.T(apb_m_transaction #( + .APB_ADDR_WIDTH(APB_ADDR_WIDTH), + .APB_DATA_WIDTH(APB_DATA_WIDTH), + .STRB_LEN(STRB_LEN) + ))); + + `uvm_component_param_utils( apb_m_transaction_coverage #( + APB_ADDR_WIDTH, + APB_DATA_WIDTH, + STRB_LEN + )) + + T coverage_trans; + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + // **************************************************************************** + covergroup apb_m_transaction_cg; + // pragma uvmf custom covergroup begin + // UVMF_CHANGE_ME : Add coverage bins, crosses, exclusions, etc. according to coverage needs. + option.auto_bin_max=1024; + option.per_instance=1; + psel: coverpoint coverage_trans.psel; + penable: coverpoint coverage_trans.penable; + paddr: coverpoint coverage_trans.paddr; + pwdata: coverpoint coverage_trans.pwdata; + pwrite: coverpoint coverage_trans.pwrite; + pstrb: coverpoint coverage_trans.pstrb; + pprot: coverpoint coverage_trans.pprot; + prdata: coverpoint coverage_trans.prdata; + pready: coverpoint coverage_trans.pready; + pslverr: coverpoint coverage_trans.pslverr; + // pragma uvmf custom covergroup end + endgroup + + // **************************************************************************** + // FUNCTION : new() + // This function is the standard SystemVerilog constructor. + // + function new(string name="", uvm_component parent=null); + super.new(name,parent); + apb_m_transaction_cg=new; + `uvm_warning("COVERAGE_MODEL_REVIEW", "A covergroup has been constructed which may need review because of either generation or re-generation with merging. Please note that transaction variables added as a result of re-generation and merging are not automatically added to the covergroup. Remove this warning after the covergroup has been reviewed.") + endfunction + + // **************************************************************************** + // FUNCTION : build_phase() + // This function is the standard UVM build_phase. + // + function void build_phase(uvm_phase phase); + apb_m_transaction_cg.set_inst_name($sformatf("apb_m_transaction_cg_%s",get_full_name())); + endfunction + + // **************************************************************************** + // FUNCTION: write (T t) + // This function is automatically executed when a transaction arrives on the + // analysis_export. It copies values from the variables in the transaction + // to local variables used to collect functional coverage. + // + virtual function void write (T t); + `uvm_info("COV","Received transaction",UVM_HIGH); + coverage_trans = t; + apb_m_transaction_cg.sample(); + endfunction + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/verification_ip/interface_packages/apb_m_pkg/src/apb_m_typedefs.svh b/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/verification_ip/interface_packages/apb_m_pkg/src/apb_m_typedefs.svh new file mode 100644 index 00000000..43d85640 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/verification_ip/interface_packages/apb_m_pkg/src/apb_m_typedefs.svh @@ -0,0 +1,20 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: +// This file contains defines and typedefs to be compiled for use in +// the simulation running on the host server when using Veloce. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// + + +// pragma uvmf custom additional begin +// pragma uvmf custom additional end + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/verification_ip/interface_packages/apb_m_pkg/src/apb_m_typedefs_hdl.svh b/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/verification_ip/interface_packages/apb_m_pkg/src/apb_m_typedefs_hdl.svh new file mode 100644 index 00000000..74738c8c --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/verification_ip/interface_packages/apb_m_pkg/src/apb_m_typedefs_hdl.svh @@ -0,0 +1,21 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: +// This file contains defines and typedefs to be compiled for use in +// the simulation running on the emulator when using Veloce. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// + + + +// pragma uvmf custom additional begin +// pragma uvmf custom additional end + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/verification_ip/interface_packages/apb_m_pkg/yaml/apb_m_interface.yaml b/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/verification_ip/interface_packages/apb_m_pkg/yaml/apb_m_interface.yaml new file mode 100644 index 00000000..f49301e8 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/verification_ip/interface_packages/apb_m_pkg/yaml/apb_m_interface.yaml @@ -0,0 +1,128 @@ +uvmf: + interfaces: + apb_m: + clock: pclk + config_constraints: [] + config_vars: [] + existing_library_component: 'True' + gen_inbound_streaming_driver: 'False' + hdl_pkg_parameters: [] + hdl_typedefs: [] + hvl_pkg_parameters: [] + hvl_typedefs: [] + parameters: + - name: APB_ADDR_WIDTH + type: int + value: '32' + - name: APB_DATA_WIDTH + type: int + value: '32' + - name: STRB_LEN + type: int + value: APB_ADDR_WIDTH/8 + ports: + - dir: output + name: psel + reset_value: '''b0' + width: '16' + - dir: output + name: penable + reset_value: '''b0' + width: '1' + - dir: output + name: paddr + reset_value: '''b0' + width: APB_ADDR_WIDTH + - dir: output + name: pwdata + reset_value: '''b0' + width: APB_DATA_WIDTH + - dir: output + name: pwrite + reset_value: '''b0' + width: '1' + - dir: output + name: pstrb + reset_value: '''b0' + width: STRB_LEN + - dir: output + name: pprot + reset_value: '''b0' + width: '3' + - dir: input + name: prdata + reset_value: '''b0' + width: APB_DATA_WIDTH + - dir: input + name: pready + reset_value: '0' + width: '1' + - dir: input + name: pslverr + reset_value: '0' + width: '1' + reset: presetn + reset_assertion_level: 'False' + transaction_constraints: [] + transaction_vars: + - comment: '' + iscompare: 'False' + isrand: 'True' + name: psel + type: bit + unpacked_dimension: '' + - comment: '' + iscompare: 'True' + isrand: 'True' + name: penable + type: bit + unpacked_dimension: '' + - comment: '' + iscompare: 'True' + isrand: 'True' + name: paddr + type: bit [APB_ADDR_WIDTH-1:0] + unpacked_dimension: '' + - comment: '' + iscompare: 'True' + isrand: 'True' + name: pwdata + type: bit [APB_DATA_WIDTH-1:0] + unpacked_dimension: '' + - comment: '' + iscompare: 'True' + isrand: 'True' + name: pwrite + type: bit + unpacked_dimension: '' + - comment: '' + iscompare: 'True' + isrand: 'True' + name: pstrb + type: bit [STRB_LEN:0] + unpacked_dimension: '' + - comment: '' + iscompare: 'True' + isrand: 'True' + name: pprot + type: bit [3:0] + unpacked_dimension: '' + - comment: '' + iscompare: 'True' + isrand: 'False' + name: prdata + type: bit [APB_DATA_WIDTH-1:0] + unpacked_dimension: '' + - comment: '' + iscompare: 'True' + isrand: 'False' + name: pready + type: bit + unpacked_dimension: '' + - comment: '' + iscompare: 'True' + isrand: 'False' + name: pslverr + type: bit + unpacked_dimension: '' + use_dpi_link: 'False' diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/verification_ip/interface_packages/axi_m_pkg/.project b/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/verification_ip/interface_packages/axi_m_pkg/.project new file mode 100644 index 00000000..7afbc306 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/verification_ip/interface_packages/axi_m_pkg/.project @@ -0,0 +1,30 @@ + + + axi_m_pkg + + + + + + org.python.pydev.PyDevBuilder + + + + + net.sf.sveditor.core.SVProjectBuilder + + + + + + net.sf.sveditor.core.SVNature + org.python.pydev.pythonNature + + + + UVMF_VIP_LIBRARY_HOME + $%7BPARENT-2-PROJECT_LOC%7D + + + + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/verification_ip/interface_packages/axi_m_pkg/.svproject b/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/verification_ip/interface_packages/axi_m_pkg/.svproject new file mode 100644 index 00000000..5c637646 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/verification_ip/interface_packages/axi_m_pkg/.svproject @@ -0,0 +1,16 @@ + + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/verification_ip/interface_packages/axi_m_pkg/Makefile b/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/verification_ip/interface_packages/axi_m_pkg/Makefile new file mode 100644 index 00000000..49510a8d --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/verification_ip/interface_packages/axi_m_pkg/Makefile @@ -0,0 +1,66 @@ +# axi_m interface packages source +# pragma uvmf custom additional begin +# pragma uvmf custom additional end + +axi_m_PKG = \ + +incdir+$(UVMF_VIP_LIBRARY_HOME)/interface_packages/axi_m_pkg \ + -F $(UVMF_VIP_LIBRARY_HOME)/interface_packages/axi_m_pkg/axi_m_filelist_hvl.f + +axi_m_PKG_HDL = \ + +incdir+$(UVMF_VIP_LIBRARY_HOME)/interface_packages/axi_m_pkg \ + -F $(UVMF_VIP_LIBRARY_HOME)/interface_packages/axi_m_pkg/axi_m_filelist_hdl.f + +axi_m_PKG_XRTL = \ + +incdir+$(UVMF_VIP_LIBRARY_HOME)/interface_packages/axi_m_pkg \ + -F $(UVMF_VIP_LIBRARY_HOME)/interface_packages/axi_m_pkg/axi_m_filelist_xrtl.f + +COMP_axi_m_PKG_TGT_0 = q_comp_axi_m_pkg +COMP_axi_m_PKG_TGT_1 = v_comp_axi_m_pkg +COMP_axi_m_PKG_TGT = $(COMP_axi_m_PKG_TGT_$(USE_VELOCE)) + +comp_axi_m_pkg: $(COMP_axi_m_PKG_TGT) + +q_comp_axi_m_pkg: + $(HDL_COMP_CMD) $(axi_m_PKG_HDL) + $(HVL_COMP_CMD) $(axi_m_PKG) + $(HDL_COMP_CMD) $(axi_m_PKG_XRTL) + +v_comp_axi_m_pkg: + $(HVL_COMP_CMD) $(axi_m_PKG_HDL) + $(HVL_COMP_CMD) $(axi_m_PKG) + $(VELANALYZE_CMD) $(axi_m_PKG_HDL) + $(VELANALYZE_HVL_CMD) $(axi_m_PKG) + $(HDL_COMP_CMD) $(axi_m_PKG_XRTL) + +ifeq ($(MTI_VCO_MODE),64) + GCC_COMP_ARCH = -m64 +else + GCC_COMP_ARCH = -m32 +endif + +export axi_m_IF_DPI_SRC ?= $(UVMF_VIP_LIBRARY_HOME)/interface_packages/axi_m_pkg/dpi + +C_FILE_COMPILE_LIST_axi_m_pkg = \ + +O_FILE_COMPILE_LIST_axi_m_pkg = $(notdir $(C_FILE_COMPILE_LIST_axi_m_pkg:.c=.o)) + +GCC_COMP_ARGS_axi_m_pkg += -I$(axi_m_IF_DPI_SRC) \ + -fPIC + +GCC_COMP_ARGS_axi_m_pkg += $(axi_m_IF_GCC_COMP_ARGUMENTS) + +GCC_LINK_ARGS_axi_m_pkg += \ + \ + -o .so + +comp_axi_m_pkg_c_files: + @echo "--------------------------------" + @echo "Compiling Interface C source" + @echo "--------------------------------" + gcc $(GCC_COMP_ARCH) $(GCC_COMP_ARGS_axi_m_pkg) $(C_FILE_COMPILE_LIST_axi_m_pkg) + @echo "--------------------------------" + @echo "Linking Interface C objects into a shared object" + @echo "--------------------------------" + gcc $(GCC_COMP_ARCH) $(GCC_LINK_ARGS_axi_m_pkg) $(O_FILE_COMPILE_LIST_axi_m_pkg) + @echo "--------------------------------" + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/verification_ip/interface_packages/axi_m_pkg/axi_m.compile b/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/verification_ip/interface_packages/axi_m_pkg/axi_m.compile new file mode 100644 index 00000000..c1de0879 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/verification_ip/interface_packages/axi_m_pkg/axi_m.compile @@ -0,0 +1,3 @@ +needs: + - axi_m_hvl.compile + - axi_m_hdl.compile diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/verification_ip/interface_packages/axi_m_pkg/axi_m_bfm.vinfo b/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/verification_ip/interface_packages/axi_m_pkg/axi_m_bfm.vinfo new file mode 100644 index 00000000..69c6a9be --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/verification_ip/interface_packages/axi_m_pkg/axi_m_bfm.vinfo @@ -0,0 +1,6 @@ +@use $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg_hdl.vinfo +@use axi_m_pkg_hdl.vinfo ++incdir+@vinfodir +src/axi_m_if.sv +src/axi_m_driver_bfm.sv +src/axi_m_monitor_bfm.sv diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/verification_ip/interface_packages/axi_m_pkg/axi_m_common.compile b/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/verification_ip/interface_packages/axi_m_pkg/axi_m_common.compile new file mode 100644 index 00000000..325f4c25 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/verification_ip/interface_packages/axi_m_pkg/axi_m_common.compile @@ -0,0 +1,7 @@ +needs: + - $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg_hdl.compile +incdir: + - . + - ${uvm_path}/src +src: + - axi_m_pkg_hdl.sv diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/verification_ip/interface_packages/axi_m_pkg/axi_m_filelist_hdl.f b/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/verification_ip/interface_packages/axi_m_pkg/axi_m_filelist_hdl.f new file mode 100644 index 00000000..af073f29 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/verification_ip/interface_packages/axi_m_pkg/axi_m_filelist_hdl.f @@ -0,0 +1 @@ +$UVMF_VIP_LIBRARY_HOME/interface_packages/axi_m_pkg/axi_m_pkg_hdl.sv diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/verification_ip/interface_packages/axi_m_pkg/axi_m_filelist_hvl.f b/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/verification_ip/interface_packages/axi_m_pkg/axi_m_filelist_hvl.f new file mode 100644 index 00000000..0c583aa9 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/verification_ip/interface_packages/axi_m_pkg/axi_m_filelist_hvl.f @@ -0,0 +1 @@ +$UVMF_VIP_LIBRARY_HOME/interface_packages/axi_m_pkg/axi_m_pkg.sv \ No newline at end of file diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/verification_ip/interface_packages/axi_m_pkg/axi_m_filelist_xrtl.f b/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/verification_ip/interface_packages/axi_m_pkg/axi_m_filelist_xrtl.f new file mode 100644 index 00000000..0348c6ae --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/verification_ip/interface_packages/axi_m_pkg/axi_m_filelist_xrtl.f @@ -0,0 +1,3 @@ +$UVMF_VIP_LIBRARY_HOME/interface_packages/axi_m_pkg/src/axi_m_if.sv +$UVMF_VIP_LIBRARY_HOME/interface_packages/axi_m_pkg/src/axi_m_monitor_bfm.sv +$UVMF_VIP_LIBRARY_HOME/interface_packages/axi_m_pkg/src/axi_m_driver_bfm.sv diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/verification_ip/interface_packages/axi_m_pkg/axi_m_hdl.compile b/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/verification_ip/interface_packages/axi_m_pkg/axi_m_hdl.compile new file mode 100644 index 00000000..59f061bc --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/verification_ip/interface_packages/axi_m_pkg/axi_m_hdl.compile @@ -0,0 +1,9 @@ +needs: + - $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg_hdl.compile + - ./axi_m_common.compile +incdir: + - . +src: + - src/axi_m_if.sv + - src/axi_m_monitor_bfm.sv + - src/axi_m_driver_bfm.sv diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/verification_ip/interface_packages/axi_m_pkg/axi_m_hvl.compile b/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/verification_ip/interface_packages/axi_m_pkg/axi_m_hvl.compile new file mode 100644 index 00000000..b72727cc --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/verification_ip/interface_packages/axi_m_pkg/axi_m_hvl.compile @@ -0,0 +1,7 @@ +needs: + - $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg.compile + - ./axi_m_common.compile +incdir: + - . +src: + - axi_m_pkg.sv diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/verification_ip/interface_packages/axi_m_pkg/axi_m_pkg.sv b/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/verification_ip/interface_packages/axi_m_pkg/axi_m_pkg.sv new file mode 100644 index 00000000..4e2e996f --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/verification_ip/interface_packages/axi_m_pkg/axi_m_pkg.sv @@ -0,0 +1,77 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// PACKAGE: This file defines all of the files contained in the +// interface package that will run on the host simulator. +// +// CONTAINS: +// - +// - +// - + +// - +// - +// - + +// - +// - +// - + +// - +// - +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +package axi_m_pkg; + + import uvm_pkg::*; + import uvmf_base_pkg_hdl::*; + import uvmf_base_pkg::*; + import axi_m_pkg_hdl::*; + + `include "uvm_macros.svh" + + // pragma uvmf custom package_imports_additional begin + // pragma uvmf custom package_imports_additional end + `include "src/axi_m_macros.svh" + + export axi_m_pkg_hdl::*; + + + + // Parameters defined as HVL parameters + + `include "src/axi_m_typedefs.svh" + `include "src/axi_m_transaction.svh" + + `include "src/axi_m_configuration.svh" + `include "src/axi_m_driver.svh" + `include "src/axi_m_monitor.svh" + + `include "src/axi_m_transaction_coverage.svh" + `include "src/axi_m_sequence_base.svh" + `include "src/axi_m_random_sequence.svh" + + `include "src/axi_m_responder_sequence.svh" + `include "src/axi_m2reg_adapter.svh" + + `include "src/axi_m_agent.svh" + + // pragma uvmf custom package_item_additional begin + // UVMF_CHANGE_ME : When adding new interface sequences to the src directory + // be sure to add the sequence file here so that it will be + // compiled as part of the interface package. Be sure to place + // the new sequence after any base sequences of the new sequence. + // pragma uvmf custom package_item_additional end + +endpackage + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/verification_ip/interface_packages/axi_m_pkg/axi_m_pkg.vinfo b/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/verification_ip/interface_packages/axi_m_pkg/axi_m_pkg.vinfo new file mode 100644 index 00000000..dae51d0c --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/verification_ip/interface_packages/axi_m_pkg/axi_m_pkg.vinfo @@ -0,0 +1,4 @@ +@use $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg.vinfo +@use axi_m_pkg_hdl.vinfo ++incdir+@vinfodir +axi_m_pkg.sv diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/verification_ip/interface_packages/axi_m_pkg/axi_m_pkg_hdl.sv b/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/verification_ip/interface_packages/axi_m_pkg/axi_m_pkg_hdl.sv new file mode 100644 index 00000000..37e46870 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/verification_ip/interface_packages/axi_m_pkg/axi_m_pkg_hdl.sv @@ -0,0 +1,38 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// PACKAGE: This file defines all of the files contained in the +// interface package that needs to be compiled and synthesized +// for running on Veloce. +// +// CONTAINS: +// - +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +package axi_m_pkg_hdl; + + import uvmf_base_pkg_hdl::*; + + // pragma uvmf custom package_imports_additional begin + // pragma uvmf custom package_imports_additional end + + // Parameters defined as HDL parameters + + `include "src/axi_m_typedefs_hdl.svh" + `include "src/axi_m_macros.svh" + + // pragma uvmf custom package_item_additional begin + // pragma uvmf custom package_item_additional end + +endpackage + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/verification_ip/interface_packages/axi_m_pkg/axi_m_pkg_hdl.vinfo b/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/verification_ip/interface_packages/axi_m_pkg/axi_m_pkg_hdl.vinfo new file mode 100644 index 00000000..4bcea0fb --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/verification_ip/interface_packages/axi_m_pkg/axi_m_pkg_hdl.vinfo @@ -0,0 +1,2 @@ +@use $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg_hdl.vinfo +axi_m_pkg_hdl.sv diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/verification_ip/interface_packages/axi_m_pkg/axi_m_pkg_sve.F b/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/verification_ip/interface_packages/axi_m_pkg/axi_m_pkg_sve.F new file mode 100644 index 00000000..fd118edd --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/verification_ip/interface_packages/axi_m_pkg/axi_m_pkg_sve.F @@ -0,0 +1,10 @@ +// UVM ++incdir+${UVM_HOME}/src +${UVM_HOME}/src/uvm_pkg.sv + +// Common UVMF files +-f ${UVMF_HOME}/common/common_sve.f + ++incdir+. +-f ${UVMF_VIP_LIBRARY_HOME}/interface_packages/axi_m_pkg/axi_m_filelist_hdl.f +-f ${UVMF_VIP_LIBRARY_HOME}/interface_packages/axi_m_pkg/axi_m_filelist_hvl.f diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/verification_ip/interface_packages/axi_m_pkg/compile.do b/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/verification_ip/interface_packages/axi_m_pkg/compile.do new file mode 100644 index 00000000..ea448b12 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/verification_ip/interface_packages/axi_m_pkg/compile.do @@ -0,0 +1,14 @@ +# Tcl do file for compile of axi_m interface + +# pragma uvmf custom additional begin +# pragma uvmf custom additional end + + +vlog -sv -timescale 1ps/1ps -suppress 2223,2286 +incdir+$env(UVMF_VIP_LIBRARY_HOME)/interface_packages/axi_m_pkg \ + -F $env(UVMF_VIP_LIBRARY_HOME)/interface_packages/axi_m_pkg/axi_m_filelist_hdl.f + +vlog -sv -timescale 1ps/1ps -suppress 2223,2286 +incdir+$env(UVMF_VIP_LIBRARY_HOME)/interface_packages/axi_m_pkg \ + -F $env(UVMF_VIP_LIBRARY_HOME)/interface_packages/axi_m_pkg/axi_m_filelist_hvl.f + +vlog -sv -timescale 1ps/1ps -suppress 2223,2286 +incdir+$env(UVMF_VIP_LIBRARY_HOME)/interface_packages/axi_m_pkg \ + -F $env(UVMF_VIP_LIBRARY_HOME)/interface_packages/axi_m_pkg/axi_m_filelist_xrtl.f \ No newline at end of file diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/verification_ip/interface_packages/axi_m_pkg/src/axi_m2reg_adapter.svh b/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/verification_ip/interface_packages/axi_m_pkg/src/axi_m2reg_adapter.svh new file mode 100644 index 00000000..5e9efca8 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/verification_ip/interface_packages/axi_m_pkg/src/axi_m2reg_adapter.svh @@ -0,0 +1,123 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: +// This file contains the UVM register adapter for the axi_m interface. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class axi_m2reg_adapter #( + int AW_WIDTH = 32, + int LEN = 8, + int DATA_WIDTH = 32, + int X = 16 + ) extends uvm_reg_adapter; + + `uvm_object_param_utils( axi_m2reg_adapter #( + AW_WIDTH, + LEN, + DATA_WIDTH, + X + )) + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + //-------------------------------------------------------------------- + // new + //-------------------------------------------------------------------- + function new (string name = "axi_m2reg_adapter" ); + super.new(name); + // pragma uvmf custom new begin + // UVMF_CHANGE_ME : Configure the adapter regarding byte enables and provides response. + + // Does the protocol the Agent is modeling support byte enables? + // 0 = NO + // 1 = YES + supports_byte_enable = 0; + + // Does the Agent's Driver provide separate response sequence items? + // i.e. Does the driver call seq_item_port.put() + // and do the sequences call get_response()? + // 0 = NO + // 1 = YES + provides_responses = 0; + // pragma uvmf custom new end + + endfunction: new + + //-------------------------------------------------------------------- + // reg2bus + //-------------------------------------------------------------------- + virtual function uvm_sequence_item reg2bus(const ref uvm_reg_bus_op rw); + + axi_m_transaction #( + .AW_WIDTH(AW_WIDTH), + .LEN(LEN), + .DATA_WIDTH(DATA_WIDTH), + .X(X) + ) trans_h = axi_m_transaction #( + .AW_WIDTH(AW_WIDTH), + .LEN(LEN), + .DATA_WIDTH(DATA_WIDTH), + .X(X) + )::type_id::create("trans_h"); + + // pragma uvmf custom reg2bus begin + // UVMF_CHANGE_ME : Fill in the reg2bus adapter mapping registe fields to protocol fields. + + //Adapt the following for your sequence item type + // trans_h.op = (rw.kind == UVM_READ) ? WB_READ : WB_WRITE; + //Copy over address + // trans_h.addr = rw.addr; + //Copy over write data + // trans_h.data = rw.data; + + // pragma uvmf custom reg2bus end + + // Return the adapted transaction + return trans_h; + + endfunction: reg2bus + + //-------------------------------------------------------------------- + // bus2reg + //-------------------------------------------------------------------- + virtual function void bus2reg(uvm_sequence_item bus_item, + ref uvm_reg_bus_op rw); + axi_m_transaction #( + .AW_WIDTH(AW_WIDTH), + .LEN(LEN), + .DATA_WIDTH(DATA_WIDTH), + .X(X) + ) trans_h; + if (!$cast(trans_h, bus_item)) begin + `uvm_fatal("ADAPT","Provided bus_item is not of the correct type") + return; + end + // pragma uvmf custom bus2reg begin + // UVMF_CHANGE_ME : Fill in the bus2reg adapter mapping protocol fields to register fields. + //Adapt the following for your sequence item type + //Copy over instruction type + // rw.kind = (trans_h.op == WB_WRITE) ? UVM_WRITE : UVM_READ; + //Copy over address + // rw.addr = trans_h.addr; + //Copy over read data + // rw.data = trans_h.data; + //Check for errors on the bus and return UVM_NOT_OK if there is an error + // rw.status = UVM_IS_OK; + // pragma uvmf custom bus2reg end + + endfunction: bus2reg + +endclass : axi_m2reg_adapter + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/verification_ip/interface_packages/axi_m_pkg/src/axi_m_agent.svh b/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/verification_ip/interface_packages/axi_m_pkg/src/axi_m_agent.svh new file mode 100644 index 00000000..6da6dbed --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/verification_ip/interface_packages/axi_m_pkg/src/axi_m_agent.svh @@ -0,0 +1,88 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: Protocol specific agent class definition +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class axi_m_agent #( + int AW_WIDTH = 32, + int LEN = 8, + int DATA_WIDTH = 32, + int X = 16 + ) extends uvmf_parameterized_agent #( + .CONFIG_T(axi_m_configuration #( + .AW_WIDTH(AW_WIDTH), + .LEN(LEN), + .DATA_WIDTH(DATA_WIDTH), + .X(X) + )), + .DRIVER_T(axi_m_driver #( + .AW_WIDTH(AW_WIDTH), + .LEN(LEN), + .DATA_WIDTH(DATA_WIDTH), + .X(X) + )), + .MONITOR_T(axi_m_monitor #( + .AW_WIDTH(AW_WIDTH), + .LEN(LEN), + .DATA_WIDTH(DATA_WIDTH), + .X(X) + )), + .COVERAGE_T(axi_m_transaction_coverage #( + .AW_WIDTH(AW_WIDTH), + .LEN(LEN), + .DATA_WIDTH(DATA_WIDTH), + .X(X) + )), + .TRANS_T(axi_m_transaction #( + .AW_WIDTH(AW_WIDTH), + .LEN(LEN), + .DATA_WIDTH(DATA_WIDTH), + .X(X) + )) + ); + + `uvm_component_param_utils( axi_m_agent #( + AW_WIDTH, + LEN, + DATA_WIDTH, + X + )) + +// pragma uvmf custom class_item_additional begin +// pragma uvmf custom class_item_additional end + +// **************************************************************************** +// FUNCTION : new() +// This function is the standard SystemVerilog constructor. +// + function new( string name = "", uvm_component parent = null ); + super.new( name, parent ); + endfunction + +// **************************************************************************** + // FUNCTION: build_phase + virtual function void build_phase(uvm_phase phase); +// pragma uvmf custom build_phase_pre_super begin +// pragma uvmf custom build_phase_pre_super end + super.build_phase(phase); + if (configuration.active_passive == ACTIVE) begin + // Place sequencer handle into configuration object + // so that it may be retrieved from configuration + // rather than using uvm_config_db + configuration.sequencer = this.sequencer; + end + endfunction + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/verification_ip/interface_packages/axi_m_pkg/src/axi_m_configuration.svh b/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/verification_ip/interface_packages/axi_m_pkg/src/axi_m_configuration.svh new file mode 100644 index 00000000..2cecbe25 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/verification_ip/interface_packages/axi_m_pkg/src/axi_m_configuration.svh @@ -0,0 +1,219 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This class contains all variables and functions used +// to configure the axi_m agent and its bfm's. It gets the +// bfm's from the uvm_config_db for use by the agent. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class axi_m_configuration #( + int AW_WIDTH = 32, + int LEN = 8, + int DATA_WIDTH = 32, + int X = 16 + ) extends uvmf_parameterized_agent_configuration_base #( + .DRIVER_BFM_BIND_T(virtual axi_m_driver_bfm #( + .AW_WIDTH(AW_WIDTH), + .LEN(LEN), + .DATA_WIDTH(DATA_WIDTH), + .X(X) + )), + .MONITOR_BFM_BIND_T( virtual axi_m_monitor_bfm #( + .AW_WIDTH(AW_WIDTH), + .LEN(LEN), + .DATA_WIDTH(DATA_WIDTH), + .X(X) + ))); + + `uvm_object_param_utils( axi_m_configuration #( + AW_WIDTH, + LEN, + DATA_WIDTH, + X + )) + + + // Sequencer handle populated by agent + uvm_sequencer #(axi_m_transaction #( + .AW_WIDTH(AW_WIDTH), + .LEN(LEN), + .DATA_WIDTH(DATA_WIDTH), + .X(X) + ) ) sequencer; + + //Constraints for the configuration variables: + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + covergroup axi_m_configuration_cg; + // pragma uvmf custom covergroup begin + option.auto_bin_max=1024; + // pragma uvmf custom covergroup end + endgroup + + //******************************************************************* + //******************************************************************* + // Structure used to pass configuration variables to monitor and driver BFM's. + // Use to_struct function to pack variables into structure. + // Use from_struct function to unpack variables from structure. + // This structure is defined in axi_m_macros.svh + `axi_m_CONFIGURATION_STRUCT + axi_m_configuration_s axi_m_configuration_struct; + //******************************************************************* + // FUNCTION: to_struct() + // This function packs variables into a axi_m_configuration_s + // structure. The function returns the handle to the axi_m_configuration_struct. + // This function is defined in axi_m_macros.svh + `axi_m_CONFIGURATION_TO_STRUCT_FUNCTION + //******************************************************************* + // FUNCTION: from_struct() + // This function unpacks the struct provided as an argument into + // variables of this class. + // This function is defined in axi_m_macros.svh + `axi_m_CONFIGURATION_FROM_STRUCT_FUNCTION + + // **************************************************************************** + // FUNCTION : new() + // This function is the standard SystemVerilog constructor. + // + function new( string name = "" ); + super.new( name ); + // Construct the covergroup for this configuration class + axi_m_configuration_cg = new; + endfunction + + // **************************************************************************** + // FUNCTION: post_randomize() + // This function is automatically called after the randomize() function + // is executed. + // + function void post_randomize(); + super.post_randomize(); + axi_m_configuration_cg.sample(); + endfunction + + // **************************************************************************** + // FUNCTION: initialize + // This function causes the configuration to retrieve + // its virtual interface handle from the uvm_config_db. + // This function also makes itself available to its + // agent through the uvm_config_db. + // + // ARGUMENTS: + // uvmf_active_passive_t activity: + // This argument identifies the simulation level + // as either BLOCK, CHIP, SIMULATION, etc. + // + // AGENT_PATH: + // This argument identifies the path to this + // configurations agent. This configuration + // makes itself available to the agent specified + // by agent_path by placing itself into the + // uvm_config_db. + // + // INTERFACE_NAME: + // This argument identifies the string name of + // this configurations BFM's. This string + // name is used to retrieve the driver and + // monitor BFM from the uvm_config_db. + // + virtual function void initialize(uvmf_active_passive_t activity, + string agent_path, + string interface_name); + + super.initialize( activity, agent_path, interface_name); + // The covergroup is given the same name as the interface + axi_m_configuration_cg.set_inst_name(interface_name); + + // This configuration places itself into the uvm_config_db for the agent, identified by the agent_path variable, to retrieve. + uvm_config_db #( axi_m_configuration #( + .AW_WIDTH(AW_WIDTH), + .LEN(LEN), + .DATA_WIDTH(DATA_WIDTH), + .X(X) + ) + )::set( null ,agent_path,UVMF_AGENT_CONFIG, this ); + + // This configuration also places itself in the config db using the same identifier used by the interface. This allows users to access + // configuration variables and the interface through the bfm api class rather than directly accessing the BFM. This is useful for + // accessingthe BFM when using Veloce + uvm_config_db #( axi_m_configuration #( + .AW_WIDTH(AW_WIDTH), + .LEN(LEN), + .DATA_WIDTH(DATA_WIDTH), + .X(X) + ) + )::set( null ,UVMF_CONFIGURATIONS, interface_name, this ); + + axi_m_configuration_cg.set_inst_name($sformatf("axi_m_configuration_cg_%s",get_full_name())); + +// This code is to aid in debugging parameter mismatches between the BFM and its corresponding agent. +// Enable this debug by setting UVM_VERBOSITY to UVM_DEBUG +// Setting UVM_VERBOSITY to UVM_DEBUG causes all BFM's and all agents to display their parameter settings. +// All of the messages from this feature have a UVM messaging id value of "CFG" +// The transcript or run.log can be parsed to ensure BFM parameter settings match its corresponding agents parameter settings. + `uvm_info("CFG", + $psprintf("The agent at '%s' is using interface named %s has the following parameters: AW_WIDTH=%x LEN=%x DATA_WIDTH=%x X=%x ", agent_path, interface_name, AW_WIDTH ,LEN ,DATA_WIDTH ,X ), + UVM_DEBUG) + + // pragma uvmf custom initialize begin + // This controls whether or not the agent returns a transaction handle in the driver when calling + // item_done() back into the sequencer or not. If set to 1, a transaction is sent back which means + // the sequence on the other end must use the get_response() part of the driver/sequence API. If + // this doesn't occur, there will eventually be response_queue overflow errors during the test. + return_transaction_response = 1'b0; + + // pragma uvmf custom initialize end + + endfunction + + // **************************************************************************** + // TASK: wait_for_reset + // *[Required]* Blocks until reset is released. The wait_for_reset operation is performed + // by a task in the monitor bfm. + virtual task wait_for_reset(); + monitor_bfm.wait_for_reset(); + endtask + + // **************************************************************************** + // TASK: wait_for_num_clocks + // *[Required]* Blocks until specified number of clocks have elapsed. The wait_for_num_clocks + // operation is performed by a task in the monitor bfm. + virtual task wait_for_num_clocks(int clocks); + monitor_bfm.wait_for_num_clocks(clocks); + endtask + + // **************************************************************************** + // FUNCTION : convert2string() + // This function is used to convert variables in this class into a string for log messaging. + // + virtual function string convert2string (); + // pragma uvmf custom convert2string begin + return $sformatf(""); + // pragma uvmf custom convert2string end + endfunction + + // **************************************************************************** + // FUNCTION: get_sequencer + function uvm_sequencer #(axi_m_transaction#( + .AW_WIDTH(AW_WIDTH), + .LEN(LEN), + .DATA_WIDTH(DATA_WIDTH), + .X(X) + )) get_sequencer(); + return sequencer; + endfunction + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/verification_ip/interface_packages/axi_m_pkg/src/axi_m_driver.svh b/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/verification_ip/interface_packages/axi_m_pkg/src/axi_m_driver.svh new file mode 100644 index 00000000..aca314e5 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/verification_ip/interface_packages/axi_m_pkg/src/axi_m_driver.svh @@ -0,0 +1,121 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This class passes transactions between the sequencer +// and the BFM driver interface. It accesses the driver BFM +// through the bfm handle. This driver +// passes transactions to the driver BFM through the access +// task. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class axi_m_driver #( + int AW_WIDTH = 32, + int LEN = 8, + int DATA_WIDTH = 32, + int X = 16 + ) extends uvmf_driver_base #( + .CONFIG_T(axi_m_configuration #( + .AW_WIDTH(AW_WIDTH), + .LEN(LEN), + .DATA_WIDTH(DATA_WIDTH), + .X(X) + ) ), + .BFM_BIND_T(virtual axi_m_driver_bfm #( + .AW_WIDTH(AW_WIDTH), + .LEN(LEN), + .DATA_WIDTH(DATA_WIDTH), + .X(X) + ) ), + .REQ(axi_m_transaction #( + .AW_WIDTH(AW_WIDTH), + .LEN(LEN), + .DATA_WIDTH(DATA_WIDTH), + .X(X) + ) ), + .RSP(axi_m_transaction #( + .AW_WIDTH(AW_WIDTH), + .LEN(LEN), + .DATA_WIDTH(DATA_WIDTH), + .X(X) + ) )); + + `uvm_component_param_utils( axi_m_driver #( + AW_WIDTH, + LEN, + DATA_WIDTH, + X + )) +//******************************************************************* +// Macros that define structs located in axi_m_macros.svh +//******************************************************************* +// Initiator macro used by axi_m_driver and axi_m_driver_bfm +// to communicate initiator driven data to axi_m_driver_bfm. +`axi_m_INITIATOR_STRUCT + axi_m_initiator_s axi_m_initiator_struct; +//******************************************************************* +// Responder macro used by axi_m_driver and axi_m_driver_bfm +// to communicate Responder driven data to axi_m_driver_bfm. +`axi_m_RESPONDER_STRUCT + axi_m_responder_s axi_m_responder_struct; + +// pragma uvmf custom class_item_additional begin +// pragma uvmf custom class_item_additional end + +// **************************************************************************** +// This function is the standard SystemVerilog constructor. +// + function new( string name = "", uvm_component parent=null ); + super.new( name, parent ); + endfunction + +// **************************************************************************** +// This function sends configuration object variables to the driver BFM +// using the configuration struct. +// + virtual function void configure(input CONFIG_T cfg); + bfm.configure( cfg.to_struct() ); + endfunction + +// **************************************************************************** +// This function places a handle to this class in the proxy variable in the +// driver BFM. This allows the driver BFM to call tasks and function within this class. +// + virtual function void set_bfm_proxy_handle(); + bfm.proxy = this; endfunction + +// **************************************************************************** +// This task is called by the run_phase in uvmf_driver_base. + virtual task access( inout REQ txn ); +// pragma uvmf custom access begin + if (configuration.initiator_responder==RESPONDER) begin + // Complete current transfer and wait for next transfer + bfm.respond_and_wait_for_next_transfer( + axi_m_initiator_struct, + txn.to_responder_struct() + ); + // Unpack information about initiated transfer received by this responder + txn.from_initiator_struct(axi_m_initiator_struct); + end else begin + // Initiate a transfer and get response + bfm.initiate_and_get_response( + txn.to_initiator_struct(), + axi_m_responder_struct + ); + // Unpack transfer response information received by this initiator + txn.from_responder_struct(axi_m_responder_struct); + end +// pragma uvmf custom access end + endtask + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/verification_ip/interface_packages/axi_m_pkg/src/axi_m_driver_bfm.sv b/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/verification_ip/interface_packages/axi_m_pkg/src/axi_m_driver_bfm.sv new file mode 100644 index 00000000..79c5ef38 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/verification_ip/interface_packages/axi_m_pkg/src/axi_m_driver_bfm.sv @@ -0,0 +1,765 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: +// This interface performs the axi_m signal driving. It is +// accessed by the uvm axi_m driver through a virtual interface +// handle in the axi_m configuration. It drives the singals passed +// in through the port connection named bus of type axi_m_if. +// +// Input signals from the axi_m_if are assigned to an internal input +// signal with a _i suffix. The _i signal should be used for sampling. +// +// The input signal connections are as follows: +// bus.signal -> signal_i +// +// This bfm drives signals with a _o suffix. These signals +// are driven onto signals within axi_m_if based on INITIATOR/RESPONDER and/or +// ARBITRATION/GRANT status. +// +// The output signal connections are as follows: +// signal_o -> bus.signal +// +// +// Interface functions and tasks used by UVM components: +// +// configure: +// This function gets configuration attributes from the +// UVM driver to set any required BFM configuration +// variables such as 'initiator_responder'. +// +// initiate_and_get_response: +// This task is used to perform signaling activity for initiating +// a protocol transfer. The task initiates the transfer, using +// input data from the initiator struct. Then the task captures +// response data, placing the data into the response struct. +// The response struct is returned to the driver class. +// +// respond_and_wait_for_next_transfer: +// This task is used to complete a current transfer as a responder +// and then wait for the initiator to start the next transfer. +// The task uses data in the responder struct to drive protocol +// signals to complete the transfer. The task then waits for +// the next transfer. Once the next transfer begins, data from +// the initiator is placed into the initiator struct and sent +// to the responder sequence for processing to determine +// what data to respond with. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +import uvmf_base_pkg_hdl::*; +import axi_m_pkg_hdl::*; +`include "src/axi_m_macros.svh" + +interface axi_m_driver_bfm #( + int AW_WIDTH = 32, + int LEN = 8, + int DATA_WIDTH = 32, + int X = 16 + ) + (axi_m_if bus); + // The following pragma and additional ones in-lined further below are for running this BFM on Veloce + // pragma attribute axi_m_driver_bfm partition_interface_xif + +`ifndef XRTL +// This code is to aid in debugging parameter mismatches between the BFM and its corresponding agent. +// Enable this debug by setting UVM_VERBOSITY to UVM_DEBUG +// Setting UVM_VERBOSITY to UVM_DEBUG causes all BFM's and all agents to display their parameter settings. +// All of the messages from this feature have a UVM messaging id value of "CFG" +// The transcript or run.log can be parsed to ensure BFM parameter settings match its corresponding agents parameter settings. +import uvm_pkg::*; +`include "uvm_macros.svh" +initial begin : bfm_vs_agent_parameter_debug + `uvm_info("CFG", + $psprintf("The BFM at '%m' has the following parameters: AW_WIDTH=%x LEN=%x DATA_WIDTH=%x X=%x ", AW_WIDTH,LEN,DATA_WIDTH,X), + UVM_DEBUG) +end +`endif + + // Config value to determine if this is an initiator or a responder + uvmf_initiator_responder_t initiator_responder; + // Custom configuration variables. + // These are set using the configure function which is called during the UVM connect_phase + + logic axi_clk_i; + logic rst_i; + + // Signal list (all signals are capable of being inputs and outputs for the sake + // of supporting both INITIATOR and RESPONDER mode operation. Expectation is that + // directionality in the config file was from the point-of-view of the INITIATOR + + // INITIATOR mode input signals + tri awready_i; + reg awready_o = 'bz; + tri wready_i; + reg wready_o = 'bz; + tri bwvalid_i; + reg bwvalid_o = 'bz; + tri [1:0] bresp_i; + reg [1:0] bresp_o = 'bz; + tri [X-1:0] bid_i; + reg [X-1:0] bid_o = 'bz; + tri [X-1:0] buser_i; + reg [X-1:0] buser_o = 'bz; + tri aready_i; + reg aready_o = 'bz; + tri rvalid_i; + reg rvalid_o = 'bz; + tri rlast_i; + reg rlast_o = 'bz; + tri [DATA_WIDTH-1:0] rdata_i; + reg [DATA_WIDTH-1:0] rdata_o = 'bz; + tri [X-1:0] rid_i; + reg [X-1:0] rid_o = 'bz; + tri [X-1:0] ruser_i; + reg [X-1:0] ruser_o = 'bz; + tri [1:0] rresp_i; + reg [1:0] rresp_o = 'bz; + + // INITIATOR mode output signals + tri awvalid_i; + reg awvalid_o = 'bz; + tri [AW_WIDTH-1:0] awaddr_i; + reg [AW_WIDTH-1:0] awaddr_o = 'bz; + tri [2:0] awsize_i; + reg [2:0] awsize_o = 'bz; + tri [1:0] awburst_i; + reg [1:0] awburst_o = 'bz; + tri [3:0] awcache_i; + reg [3:0] awcache_o = 'bz; + tri [2:0] awprot_i; + reg [2:0] awprot_o = 'bz; + tri [X-1:0] awid_i; + reg [X-1:0] awid_o = 'bz; + tri [LEN-1:0] awlen_i; + reg [LEN-1:0] awlen_o = 'bz; + tri awlock_i; + reg awlock_o = 'bz; + tri [3:0] awqos_i; + reg [3:0] awqos_o = 'bz; + tri [3:0] awregion_i; + reg [3:0] awregion_o = 'bz; + tri [X-1:0] awuser_i; + reg [X-1:0] awuser_o = 'bz; + tri wvalid_i; + reg wvalid_o = 'bz; + tri wlast_i; + reg wlast_o = 'bz; + tri [DATA_WIDTH-1:0] wdata_i; + reg [DATA_WIDTH-1:0] wdata_o = 'bz; + tri [DATA_WIDTH/8-1:0] wstrb_i; + reg [DATA_WIDTH/8-1:0] wstrb_o = 'bz; + tri [X-1:0] wid_i; + reg [X-1:0] wid_o = 'bz; + tri [X-1:0] wuser_i; + reg [X-1:0] wuser_o = 'bz; + tri bwready_i; + reg bwready_o = 'bz; + tri arvalid_i; + reg arvalid_o = 'bz; + tri [AW_WIDTH-1:0] araddr_i; + reg [AW_WIDTH-1:0] araddr_o = 'bz; + tri [2:0] arsize_i; + reg [2:0] arsize_o = 'bz; + tri [1:0] arburst_i; + reg [1:0] arburst_o = 'bz; + tri [3:0] arcache_i; + reg [3:0] arcache_o = 'bz; + tri [2:0] arprot_i; + reg [2:0] arprot_o = 'bz; + tri [X-1:0] arid_i; + reg [X-1:0] arid_o = 'bz; + tri [LEN-1:0] arlen_i; + reg [LEN-1:0] arlen_o = 'bz; + tri arlock_i; + reg arlock_o = 'bz; + tri [3:0] arqos_i; + reg [3:0] arqos_o = 'bz; + tri [3:0] aregion_i; + reg [3:0] aregion_o = 'bz; + tri [X-1:0] aruser_i; + reg [X-1:0] aruser_o = 'bz; + tri rready_i; + reg rready_o = 'bz; + + // Bi-directional signals + + + assign axi_clk_i = bus.axi_clk; + assign rst_i = bus.rst; + + // These are signals marked as 'input' by the config file, but the signals will be + // driven by this BFM if put into RESPONDER mode (flipping all signal directions around) + assign awready_i = bus.awready; + assign bus.awready = (initiator_responder == RESPONDER) ? awready_o : 'bz; + assign wready_i = bus.wready; + assign bus.wready = (initiator_responder == RESPONDER) ? wready_o : 'bz; + assign bwvalid_i = bus.bwvalid; + assign bus.bwvalid = (initiator_responder == RESPONDER) ? bwvalid_o : 'bz; + assign bresp_i = bus.bresp; + assign bus.bresp = (initiator_responder == RESPONDER) ? bresp_o : 'bz; + assign bid_i = bus.bid; + assign bus.bid = (initiator_responder == RESPONDER) ? bid_o : 'bz; + assign buser_i = bus.buser; + assign bus.buser = (initiator_responder == RESPONDER) ? buser_o : 'bz; + assign aready_i = bus.aready; + assign bus.aready = (initiator_responder == RESPONDER) ? aready_o : 'bz; + assign rvalid_i = bus.rvalid; + assign bus.rvalid = (initiator_responder == RESPONDER) ? rvalid_o : 'bz; + assign rlast_i = bus.rlast; + assign bus.rlast = (initiator_responder == RESPONDER) ? rlast_o : 'bz; + assign rdata_i = bus.rdata; + assign bus.rdata = (initiator_responder == RESPONDER) ? rdata_o : 'bz; + assign rid_i = bus.rid; + assign bus.rid = (initiator_responder == RESPONDER) ? rid_o : 'bz; + assign ruser_i = bus.ruser; + assign bus.ruser = (initiator_responder == RESPONDER) ? ruser_o : 'bz; + assign rresp_i = bus.rresp; + assign bus.rresp = (initiator_responder == RESPONDER) ? rresp_o : 'bz; + + + // These are signals marked as 'output' by the config file, but the outputs will + // not be driven by this BFM unless placed in INITIATOR mode. + assign bus.awvalid = (initiator_responder == INITIATOR) ? awvalid_o : 'bz; + assign awvalid_i = bus.awvalid; + assign bus.awaddr = (initiator_responder == INITIATOR) ? awaddr_o : 'bz; + assign awaddr_i = bus.awaddr; + assign bus.awsize = (initiator_responder == INITIATOR) ? awsize_o : 'bz; + assign awsize_i = bus.awsize; + assign bus.awburst = (initiator_responder == INITIATOR) ? awburst_o : 'bz; + assign awburst_i = bus.awburst; + assign bus.awcache = (initiator_responder == INITIATOR) ? awcache_o : 'bz; + assign awcache_i = bus.awcache; + assign bus.awprot = (initiator_responder == INITIATOR) ? awprot_o : 'bz; + assign awprot_i = bus.awprot; + assign bus.awid = (initiator_responder == INITIATOR) ? awid_o : 'bz; + assign awid_i = bus.awid; + assign bus.awlen = (initiator_responder == INITIATOR) ? awlen_o : 'bz; + assign awlen_i = bus.awlen; + assign bus.awlock = (initiator_responder == INITIATOR) ? awlock_o : 'bz; + assign awlock_i = bus.awlock; + assign bus.awqos = (initiator_responder == INITIATOR) ? awqos_o : 'bz; + assign awqos_i = bus.awqos; + assign bus.awregion = (initiator_responder == INITIATOR) ? awregion_o : 'bz; + assign awregion_i = bus.awregion; + assign bus.awuser = (initiator_responder == INITIATOR) ? awuser_o : 'bz; + assign awuser_i = bus.awuser; + assign bus.wvalid = (initiator_responder == INITIATOR) ? wvalid_o : 'bz; + assign wvalid_i = bus.wvalid; + assign bus.wlast = (initiator_responder == INITIATOR) ? wlast_o : 'bz; + assign wlast_i = bus.wlast; + assign bus.wdata = (initiator_responder == INITIATOR) ? wdata_o : 'bz; + assign wdata_i = bus.wdata; + assign bus.wstrb = (initiator_responder == INITIATOR) ? wstrb_o : 'bz; + assign wstrb_i = bus.wstrb; + assign bus.wid = (initiator_responder == INITIATOR) ? wid_o : 'bz; + assign wid_i = bus.wid; + assign bus.wuser = (initiator_responder == INITIATOR) ? wuser_o : 'bz; + assign wuser_i = bus.wuser; + assign bus.bwready = (initiator_responder == INITIATOR) ? bwready_o : 'bz; + assign bwready_i = bus.bwready; + assign bus.arvalid = (initiator_responder == INITIATOR) ? arvalid_o : 'bz; + assign arvalid_i = bus.arvalid; + assign bus.araddr = (initiator_responder == INITIATOR) ? araddr_o : 'bz; + assign araddr_i = bus.araddr; + assign bus.arsize = (initiator_responder == INITIATOR) ? arsize_o : 'bz; + assign arsize_i = bus.arsize; + assign bus.arburst = (initiator_responder == INITIATOR) ? arburst_o : 'bz; + assign arburst_i = bus.arburst; + assign bus.arcache = (initiator_responder == INITIATOR) ? arcache_o : 'bz; + assign arcache_i = bus.arcache; + assign bus.arprot = (initiator_responder == INITIATOR) ? arprot_o : 'bz; + assign arprot_i = bus.arprot; + assign bus.arid = (initiator_responder == INITIATOR) ? arid_o : 'bz; + assign arid_i = bus.arid; + assign bus.arlen = (initiator_responder == INITIATOR) ? arlen_o : 'bz; + assign arlen_i = bus.arlen; + assign bus.arlock = (initiator_responder == INITIATOR) ? arlock_o : 'bz; + assign arlock_i = bus.arlock; + assign bus.arqos = (initiator_responder == INITIATOR) ? arqos_o : 'bz; + assign arqos_i = bus.arqos; + assign bus.aregion = (initiator_responder == INITIATOR) ? aregion_o : 'bz; + assign aregion_i = bus.aregion; + assign bus.aruser = (initiator_responder == INITIATOR) ? aruser_o : 'bz; + assign aruser_i = bus.aruser; + assign bus.rready = (initiator_responder == INITIATOR) ? rready_o : 'bz; + assign rready_i = bus.rready; + + // Proxy handle to UVM driver + axi_m_pkg::axi_m_driver #( + .AW_WIDTH(AW_WIDTH), + .LEN(LEN), + .DATA_WIDTH(DATA_WIDTH), + .X(X) + ) proxy; + // pragma tbx oneway proxy.my_function_name_in_uvm_driver + + // **************************************************************************** + // **************************************************************************** + // Macros that define structs located in axi_m_macros.svh + // **************************************************************************** + // Struct for passing configuration data from axi_m_driver to this BFM + // **************************************************************************** + `axi_m_CONFIGURATION_STRUCT + // **************************************************************************** + // Structs for INITIATOR and RESPONDER data flow + //******************************************************************* + // Initiator macro used by axi_m_driver and axi_m_driver_bfm + // to communicate initiator driven data to axi_m_driver_bfm. + `axi_m_INITIATOR_STRUCT + axi_m_initiator_s initiator_struct; + // Responder macro used by axi_m_driver and axi_m_driver_bfm + // to communicate Responder driven data to axi_m_driver_bfm. + `axi_m_RESPONDER_STRUCT + axi_m_responder_s responder_struct; + + // **************************************************************************** +// pragma uvmf custom reset_condition_and_response begin + // Always block used to return signals to reset value upon assertion of reset + always @( negedge rst_i ) + begin + // RESPONDER mode output signals + awready_o <= 'bz; + wready_o <= 'bz; + bwvalid_o <= 'bz; + bresp_o <= 'bz; + bid_o <= 'bz; + buser_o <= 'bz; + aready_o <= 'bz; + rvalid_o <= 'bz; + rlast_o <= 'bz; + rdata_o <= 'bz; + rid_o <= 'bz; + ruser_o <= 'bz; + rresp_o <= 'bz; + // INITIATOR mode output signals + awvalid_o <= 'bz; + awaddr_o <= 'bz; + awsize_o <= 'bz; + awburst_o <= 'bz; + awcache_o <= 'bz; + awprot_o <= 'bz; + awid_o <= 'bz; + awlen_o <= 'bz; + awlock_o <= 'bz; + awqos_o <= 'bz; + awregion_o <= 'bz; + awuser_o <= 'bz; + wvalid_o <= 'bz; + wlast_o <= 'bz; + wdata_o <= 'bz; + wstrb_o <= 'bz; + wid_o <= 'bz; + wuser_o <= 'bz; + bwready_o <= 'bz; + arvalid_o <= 'bz; + araddr_o <= 'bz; + arsize_o <= 'bz; + arburst_o <= 'bz; + arcache_o <= 'bz; + arprot_o <= 'bz; + arid_o <= 'bz; + arlen_o <= 'bz; + arlock_o <= 'bz; + arqos_o <= 'bz; + aregion_o <= 'bz; + aruser_o <= 'bz; + rready_o <= 'bz; + // Bi-directional signals + + end +// pragma uvmf custom reset_condition_and_response end + + // pragma uvmf custom interface_item_additional begin + // pragma uvmf custom interface_item_additional end + + //****************************************************************** + // The configure() function is used to pass agent configuration + // variables to the driver BFM. It is called by the driver within + // the agent at the beginning of the simulation. It may be called + // during the simulation if agent configuration variables are updated + // and the driver BFM needs to be aware of the new configuration + // variables. + // + + function void configure(axi_m_configuration_s axi_m_configuration_arg); // pragma tbx xtf + initiator_responder = axi_m_configuration_arg.initiator_responder; + // pragma uvmf custom configure begin + // pragma uvmf custom configure end + endfunction + +// pragma uvmf custom initiate_and_get_response begin +// **************************************************************************** +// UVMF_CHANGE_ME +// This task is used by an initator. The task first initiates a transfer then +// waits for the responder to complete the transfer. + task initiate_and_get_response( + // This argument passes transaction variables used by an initiator + // to perform the initial part of a protocol transfer. The values + // come from a sequence item created in a sequence. + input axi_m_initiator_s axi_m_initiator_struct, + // This argument is used to send data received from the responder + // back to the sequence item. The sequence item is returned to the sequence. + output axi_m_responder_s axi_m_responder_struct + );// pragma tbx xtf + // + // Members within the axi_m_initiator_struct: + // bit awvalid ; + // bit awready ; + // bit [AW_WIDTH-1:0] awaddr ; + // bit awsize ; + // bit awburst ; + // bit awcache ; + // bit awprot ; + // bit [X-1:0] awid ; + // bit [LEN-1:0] awlen ; + // bit awlock ; + // bit awqos ; + // bit awregion ; + // bit [X-1:0] awuser ; + // bit wvalid ; + // bit wready ; + // bit wlast ; + // bit [DATA_WIDTH-1:0] wdata ; + // bit [DATA_WIDTH/8-1:0] wstrb ; + // bit [X-1:0] wid ; + // bit [X-1:0] wuser ; + // bit bwvalid ; + // bit bwready ; + // bit bresp ; + // bit [X-1:0] bid ; + // bit [X-1:0] buser ; + // bit arvalid ; + // bit aready ; + // bit [AW_WIDTH-1:0] araddr ; + // bit arsize ; + // bit arburst ; + // bit arcache ; + // bit arprot ; + // bit [X-1:0] arid ; + // bit [LEN-1:0] arlen ; + // bit arlock ; + // bit arqos ; + // bit aregion ; + // bit [X-1:0] aruser ; + // bit rvalid ; + // bit rready ; + // bit rlast ; + // bit [DATA_WIDTH-1:0] rdata ; + // bit [X-1:0] rid ; + // bit [X-1:0] ruser ; + // bit rresp ; + // Members within the axi_m_responder_struct: + // bit awvalid ; + // bit awready ; + // bit [AW_WIDTH-1:0] awaddr ; + // bit awsize ; + // bit awburst ; + // bit awcache ; + // bit awprot ; + // bit [X-1:0] awid ; + // bit [LEN-1:0] awlen ; + // bit awlock ; + // bit awqos ; + // bit awregion ; + // bit [X-1:0] awuser ; + // bit wvalid ; + // bit wready ; + // bit wlast ; + // bit [DATA_WIDTH-1:0] wdata ; + // bit [DATA_WIDTH/8-1:0] wstrb ; + // bit [X-1:0] wid ; + // bit [X-1:0] wuser ; + // bit bwvalid ; + // bit bwready ; + // bit bresp ; + // bit [X-1:0] bid ; + // bit [X-1:0] buser ; + // bit arvalid ; + // bit aready ; + // bit [AW_WIDTH-1:0] araddr ; + // bit arsize ; + // bit arburst ; + // bit arcache ; + // bit arprot ; + // bit [X-1:0] arid ; + // bit [LEN-1:0] arlen ; + // bit arlock ; + // bit arqos ; + // bit aregion ; + // bit [X-1:0] aruser ; + // bit rvalid ; + // bit rready ; + // bit rlast ; + // bit [DATA_WIDTH-1:0] rdata ; + // bit [X-1:0] rid ; + // bit [X-1:0] ruser ; + // bit rresp ; + initiator_struct = axi_m_initiator_struct; + // + // Reference code; + // How to wait for signal value + // while (control_signal == 1'b1) @(posedge axi_clk_i); + // + // How to assign a responder struct member, named xyz, from a signal. + // All available initiator input and inout signals listed. + // Initiator input signals + // axi_m_responder_struct.xyz = awready_i; // + // axi_m_responder_struct.xyz = wready_i; // + // axi_m_responder_struct.xyz = bwvalid_i; // + // axi_m_responder_struct.xyz = bresp_i; // [1:0] + // axi_m_responder_struct.xyz = bid_i; // [X-1:0] + // axi_m_responder_struct.xyz = buser_i; // [X-1:0] + // axi_m_responder_struct.xyz = aready_i; // + // axi_m_responder_struct.xyz = rvalid_i; // + // axi_m_responder_struct.xyz = rlast_i; // + // axi_m_responder_struct.xyz = rdata_i; // [DATA_WIDTH-1:0] + // axi_m_responder_struct.xyz = rid_i; // [X-1:0] + // axi_m_responder_struct.xyz = ruser_i; // [X-1:0] + // axi_m_responder_struct.xyz = rresp_i; // [1:0] + // Initiator inout signals + // How to assign a signal from an initiator struct member named xyz. + // All available initiator output and inout signals listed. + // Notice the _o. Those are storage variables that allow for procedural assignment. + // Initiator output signals + // awvalid_o <= axi_m_initiator_struct.xyz; // + // awaddr_o <= axi_m_initiator_struct.xyz; // [AW_WIDTH-1:0] + // awsize_o <= axi_m_initiator_struct.xyz; // [2:0] + // awburst_o <= axi_m_initiator_struct.xyz; // [1:0] + // awcache_o <= axi_m_initiator_struct.xyz; // [3:0] + // awprot_o <= axi_m_initiator_struct.xyz; // [2:0] + // awid_o <= axi_m_initiator_struct.xyz; // [X-1:0] + // awlen_o <= axi_m_initiator_struct.xyz; // [LEN-1:0] + // awlock_o <= axi_m_initiator_struct.xyz; // + // awqos_o <= axi_m_initiator_struct.xyz; // [3:0] + // awregion_o <= axi_m_initiator_struct.xyz; // [3:0] + // awuser_o <= axi_m_initiator_struct.xyz; // [X-1:0] + // wvalid_o <= axi_m_initiator_struct.xyz; // + // wlast_o <= axi_m_initiator_struct.xyz; // + // wdata_o <= axi_m_initiator_struct.xyz; // [DATA_WIDTH-1:0] + // wstrb_o <= axi_m_initiator_struct.xyz; // [DATA_WIDTH/8-1:0] + // wid_o <= axi_m_initiator_struct.xyz; // [X-1:0] + // wuser_o <= axi_m_initiator_struct.xyz; // [X-1:0] + // bwready_o <= axi_m_initiator_struct.xyz; // + // arvalid_o <= axi_m_initiator_struct.xyz; // + // araddr_o <= axi_m_initiator_struct.xyz; // [AW_WIDTH-1:0] + // arsize_o <= axi_m_initiator_struct.xyz; // [2:0] + // arburst_o <= axi_m_initiator_struct.xyz; // [1:0] + // arcache_o <= axi_m_initiator_struct.xyz; // [3:0] + // arprot_o <= axi_m_initiator_struct.xyz; // [2:0] + // arid_o <= axi_m_initiator_struct.xyz; // [X-1:0] + // arlen_o <= axi_m_initiator_struct.xyz; // [LEN-1:0] + // arlock_o <= axi_m_initiator_struct.xyz; // + // arqos_o <= axi_m_initiator_struct.xyz; // [3:0] + // aregion_o <= axi_m_initiator_struct.xyz; // [3:0] + // aruser_o <= axi_m_initiator_struct.xyz; // [X-1:0] + // rready_o <= axi_m_initiator_struct.xyz; // + // Initiator inout signals + // Initiate a transfer using the data received. + @(posedge axi_clk_i); + @(posedge axi_clk_i); + // Wait for the responder to complete the transfer then place the responder data into + // axi_m_responder_struct. + @(posedge axi_clk_i); + @(posedge axi_clk_i); + responder_struct = axi_m_responder_struct; + endtask +// pragma uvmf custom initiate_and_get_response end + +// pragma uvmf custom respond_and_wait_for_next_transfer begin +// **************************************************************************** +// The first_transfer variable is used to prevent completing a transfer in the +// first call to this task. For the first call to this task, there is not +// current transfer to complete. +bit first_transfer=1; + +// UVMF_CHANGE_ME +// This task is used by a responder. The task first completes the current +// transfer in progress then waits for the initiator to start the next transfer. + task respond_and_wait_for_next_transfer( + // This argument is used to send data received from the initiator + // back to the sequence item. The sequence determines how to respond. + output axi_m_initiator_s axi_m_initiator_struct, + // This argument passes transaction variables used by a responder + // to complete a protocol transfer. The values come from a sequence item. + input axi_m_responder_s axi_m_responder_struct + );// pragma tbx xtf + // Variables within the axi_m_initiator_struct: + // bit awvalid ; + // bit awready ; + // bit [AW_WIDTH-1:0] awaddr ; + // bit awsize ; + // bit awburst ; + // bit awcache ; + // bit awprot ; + // bit [X-1:0] awid ; + // bit [LEN-1:0] awlen ; + // bit awlock ; + // bit awqos ; + // bit awregion ; + // bit [X-1:0] awuser ; + // bit wvalid ; + // bit wready ; + // bit wlast ; + // bit [DATA_WIDTH-1:0] wdata ; + // bit [DATA_WIDTH/8-1:0] wstrb ; + // bit [X-1:0] wid ; + // bit [X-1:0] wuser ; + // bit bwvalid ; + // bit bwready ; + // bit bresp ; + // bit [X-1:0] bid ; + // bit [X-1:0] buser ; + // bit arvalid ; + // bit aready ; + // bit [AW_WIDTH-1:0] araddr ; + // bit arsize ; + // bit arburst ; + // bit arcache ; + // bit arprot ; + // bit [X-1:0] arid ; + // bit [LEN-1:0] arlen ; + // bit arlock ; + // bit arqos ; + // bit aregion ; + // bit [X-1:0] aruser ; + // bit rvalid ; + // bit rready ; + // bit rlast ; + // bit [DATA_WIDTH-1:0] rdata ; + // bit [X-1:0] rid ; + // bit [X-1:0] ruser ; + // bit rresp ; + // Variables within the axi_m_responder_struct: + // bit awvalid ; + // bit awready ; + // bit [AW_WIDTH-1:0] awaddr ; + // bit awsize ; + // bit awburst ; + // bit awcache ; + // bit awprot ; + // bit [X-1:0] awid ; + // bit [LEN-1:0] awlen ; + // bit awlock ; + // bit awqos ; + // bit awregion ; + // bit [X-1:0] awuser ; + // bit wvalid ; + // bit wready ; + // bit wlast ; + // bit [DATA_WIDTH-1:0] wdata ; + // bit [DATA_WIDTH/8-1:0] wstrb ; + // bit [X-1:0] wid ; + // bit [X-1:0] wuser ; + // bit bwvalid ; + // bit bwready ; + // bit bresp ; + // bit [X-1:0] bid ; + // bit [X-1:0] buser ; + // bit arvalid ; + // bit aready ; + // bit [AW_WIDTH-1:0] araddr ; + // bit arsize ; + // bit arburst ; + // bit arcache ; + // bit arprot ; + // bit [X-1:0] arid ; + // bit [LEN-1:0] arlen ; + // bit arlock ; + // bit arqos ; + // bit aregion ; + // bit [X-1:0] aruser ; + // bit rvalid ; + // bit rready ; + // bit rlast ; + // bit [DATA_WIDTH-1:0] rdata ; + // bit [X-1:0] rid ; + // bit [X-1:0] ruser ; + // bit rresp ; + // Reference code; + // How to wait for signal value + // while (control_signal == 1'b1) @(posedge axi_clk_i); + // + // How to assign a responder struct member, named xyz, from a signal. + // All available responder input and inout signals listed. + // Responder input signals + // axi_m_responder_struct.xyz = awvalid_i; // + // axi_m_responder_struct.xyz = awaddr_i; // [AW_WIDTH-1:0] + // axi_m_responder_struct.xyz = awsize_i; // [2:0] + // axi_m_responder_struct.xyz = awburst_i; // [1:0] + // axi_m_responder_struct.xyz = awcache_i; // [3:0] + // axi_m_responder_struct.xyz = awprot_i; // [2:0] + // axi_m_responder_struct.xyz = awid_i; // [X-1:0] + // axi_m_responder_struct.xyz = awlen_i; // [LEN-1:0] + // axi_m_responder_struct.xyz = awlock_i; // + // axi_m_responder_struct.xyz = awqos_i; // [3:0] + // axi_m_responder_struct.xyz = awregion_i; // [3:0] + // axi_m_responder_struct.xyz = awuser_i; // [X-1:0] + // axi_m_responder_struct.xyz = wvalid_i; // + // axi_m_responder_struct.xyz = wlast_i; // + // axi_m_responder_struct.xyz = wdata_i; // [DATA_WIDTH-1:0] + // axi_m_responder_struct.xyz = wstrb_i; // [DATA_WIDTH/8-1:0] + // axi_m_responder_struct.xyz = wid_i; // [X-1:0] + // axi_m_responder_struct.xyz = wuser_i; // [X-1:0] + // axi_m_responder_struct.xyz = bwready_i; // + // axi_m_responder_struct.xyz = arvalid_i; // + // axi_m_responder_struct.xyz = araddr_i; // [AW_WIDTH-1:0] + // axi_m_responder_struct.xyz = arsize_i; // [2:0] + // axi_m_responder_struct.xyz = arburst_i; // [1:0] + // axi_m_responder_struct.xyz = arcache_i; // [3:0] + // axi_m_responder_struct.xyz = arprot_i; // [2:0] + // axi_m_responder_struct.xyz = arid_i; // [X-1:0] + // axi_m_responder_struct.xyz = arlen_i; // [LEN-1:0] + // axi_m_responder_struct.xyz = arlock_i; // + // axi_m_responder_struct.xyz = arqos_i; // [3:0] + // axi_m_responder_struct.xyz = aregion_i; // [3:0] + // axi_m_responder_struct.xyz = aruser_i; // [X-1:0] + // axi_m_responder_struct.xyz = rready_i; // + // Responder inout signals + // How to assign a signal, named xyz, from an initiator struct member. + // All available responder output and inout signals listed. + // Notice the _o. Those are storage variables that allow for procedural assignment. + // Responder output signals + // awready_o <= axi_m_initiator_struct.xyz; // + // wready_o <= axi_m_initiator_struct.xyz; // + // bwvalid_o <= axi_m_initiator_struct.xyz; // + // bresp_o <= axi_m_initiator_struct.xyz; // [1:0] + // bid_o <= axi_m_initiator_struct.xyz; // [X-1:0] + // buser_o <= axi_m_initiator_struct.xyz; // [X-1:0] + // aready_o <= axi_m_initiator_struct.xyz; // + // rvalid_o <= axi_m_initiator_struct.xyz; // + // rlast_o <= axi_m_initiator_struct.xyz; // + // rdata_o <= axi_m_initiator_struct.xyz; // [DATA_WIDTH-1:0] + // rid_o <= axi_m_initiator_struct.xyz; // [X-1:0] + // ruser_o <= axi_m_initiator_struct.xyz; // [X-1:0] + // rresp_o <= axi_m_initiator_struct.xyz; // [1:0] + // Responder inout signals + + @(posedge axi_clk_i); + if (!first_transfer) begin + // Perform transfer response here. + // Reply using data recieved in the axi_m_responder_struct. + @(posedge axi_clk_i); + // Reply using data recieved in the transaction handle. + @(posedge axi_clk_i); + end + // Wait for next transfer then gather info from intiator about the transfer. + // Place the data into the axi_m_initiator_struct. + @(posedge axi_clk_i); + @(posedge axi_clk_i); + first_transfer = 0; + endtask +// pragma uvmf custom respond_and_wait_for_next_transfer end + + +endinterface + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/verification_ip/interface_packages/axi_m_pkg/src/axi_m_if.sv b/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/verification_ip/interface_packages/axi_m_pkg/src/axi_m_if.sv new file mode 100644 index 00000000..90295099 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/verification_ip/interface_packages/axi_m_pkg/src/axi_m_if.sv @@ -0,0 +1,289 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This interface contains the axi_m interface signals. +// It is instantiated once per axi_m bus. Bus Functional Models, +// BFM's named axi_m_driver_bfm, are used to drive signals on the bus. +// BFM's named axi_m_monitor_bfm are used to monitor signals on the +// bus. This interface signal bundle is passed in the port list of +// the BFM in order to give the BFM access to the signals in this +// interface. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// This template can be used to connect a DUT to these signals +// +// .dut_signal_port(axi_m_bus.awvalid), // Agent output +// .dut_signal_port(axi_m_bus.awready), // Agent input +// .dut_signal_port(axi_m_bus.awaddr), // Agent output +// .dut_signal_port(axi_m_bus.awsize), // Agent output +// .dut_signal_port(axi_m_bus.awburst), // Agent output +// .dut_signal_port(axi_m_bus.awcache), // Agent output +// .dut_signal_port(axi_m_bus.awprot), // Agent output +// .dut_signal_port(axi_m_bus.awid), // Agent output +// .dut_signal_port(axi_m_bus.awlen), // Agent output +// .dut_signal_port(axi_m_bus.awlock), // Agent output +// .dut_signal_port(axi_m_bus.awqos), // Agent output +// .dut_signal_port(axi_m_bus.awregion), // Agent output +// .dut_signal_port(axi_m_bus.awuser), // Agent output +// .dut_signal_port(axi_m_bus.wvalid), // Agent output +// .dut_signal_port(axi_m_bus.wready), // Agent input +// .dut_signal_port(axi_m_bus.wlast), // Agent output +// .dut_signal_port(axi_m_bus.wdata), // Agent output +// .dut_signal_port(axi_m_bus.wstrb), // Agent output +// .dut_signal_port(axi_m_bus.wid), // Agent output +// .dut_signal_port(axi_m_bus.wuser), // Agent output +// .dut_signal_port(axi_m_bus.bwvalid), // Agent input +// .dut_signal_port(axi_m_bus.bwready), // Agent output +// .dut_signal_port(axi_m_bus.bresp), // Agent input +// .dut_signal_port(axi_m_bus.bid), // Agent input +// .dut_signal_port(axi_m_bus.buser), // Agent input +// .dut_signal_port(axi_m_bus.arvalid), // Agent output +// .dut_signal_port(axi_m_bus.aready), // Agent input +// .dut_signal_port(axi_m_bus.araddr), // Agent output +// .dut_signal_port(axi_m_bus.arsize), // Agent output +// .dut_signal_port(axi_m_bus.arburst), // Agent output +// .dut_signal_port(axi_m_bus.arcache), // Agent output +// .dut_signal_port(axi_m_bus.arprot), // Agent output +// .dut_signal_port(axi_m_bus.arid), // Agent output +// .dut_signal_port(axi_m_bus.arlen), // Agent output +// .dut_signal_port(axi_m_bus.arlock), // Agent output +// .dut_signal_port(axi_m_bus.arqos), // Agent output +// .dut_signal_port(axi_m_bus.aregion), // Agent output +// .dut_signal_port(axi_m_bus.aruser), // Agent output +// .dut_signal_port(axi_m_bus.rvalid), // Agent input +// .dut_signal_port(axi_m_bus.rready), // Agent output +// .dut_signal_port(axi_m_bus.rlast), // Agent input +// .dut_signal_port(axi_m_bus.rdata), // Agent input +// .dut_signal_port(axi_m_bus.rid), // Agent input +// .dut_signal_port(axi_m_bus.ruser), // Agent input +// .dut_signal_port(axi_m_bus.rresp), // Agent input + +import uvmf_base_pkg_hdl::*; +import axi_m_pkg_hdl::*; + +interface axi_m_if #( + int AW_WIDTH = 32, + int LEN = 8, + int DATA_WIDTH = 32, + int X = 16 + ) + + ( + input logic axi_clk, + input logic rst, + output logic awvalid, + input logic awready, + output logic [AW_WIDTH-1:0] awaddr, + output logic [2:0] awsize, + output logic [1:0] awburst, + output logic [3:0] awcache, + output logic [2:0] awprot, + output logic [X-1:0] awid, + output logic [LEN-1:0] awlen, + output logic awlock, + output logic [3:0] awqos, + output logic [3:0] awregion, + output logic [X-1:0] awuser, + output logic wvalid, + input logic wready, + output logic wlast, + output logic [DATA_WIDTH-1:0] wdata, + output logic [DATA_WIDTH/8-1:0] wstrb, + output logic [X-1:0] wid, + output logic [X-1:0] wuser, + input logic bwvalid, + output logic bwready, + input logic [1:0] bresp, + input logic [X-1:0] bid, + input logic [X-1:0] buser, + output logic arvalid, + input logic aready, + output logic [AW_WIDTH-1:0] araddr, + output logic [2:0] arsize, + output logic [1:0] arburst, + output logic [3:0] arcache, + output logic [2:0] arprot, + output logic [X-1:0] arid, + output logic [LEN-1:0] arlen, + output logic arlock, + output logic [3:0] arqos, + output logic [3:0] aregion, + output logic [X-1:0] aruser, + input logic rvalid, + output logic rready, + input logic rlast, + input logic [DATA_WIDTH-1:0] rdata, + input logic [X-1:0] rid, + input logic [X-1:0] ruser, + input logic [1:0] rresp + ); + +modport monitor_port + ( + input axi_clk, + input rst, + input awvalid, + input awready, + input awaddr, + input awsize, + input awburst, + input awcache, + input awprot, + input awid, + input awlen, + input awlock, + input awqos, + input awregion, + input awuser, + input wvalid, + input wready, + input wlast, + input wdata, + input wstrb, + input wid, + input wuser, + input bwvalid, + input bwready, + input bresp, + input bid, + input buser, + input arvalid, + input aready, + input araddr, + input arsize, + input arburst, + input arcache, + input arprot, + input arid, + input arlen, + input arlock, + input arqos, + input aregion, + input aruser, + input rvalid, + input rready, + input rlast, + input rdata, + input rid, + input ruser, + input rresp + ); + +modport initiator_port + ( + input axi_clk, + input rst, + output awvalid, + input awready, + output awaddr, + output awsize, + output awburst, + output awcache, + output awprot, + output awid, + output awlen, + output awlock, + output awqos, + output awregion, + output awuser, + output wvalid, + input wready, + output wlast, + output wdata, + output wstrb, + output wid, + output wuser, + input bwvalid, + output bwready, + input bresp, + input bid, + input buser, + output arvalid, + input aready, + output araddr, + output arsize, + output arburst, + output arcache, + output arprot, + output arid, + output arlen, + output arlock, + output arqos, + output aregion, + output aruser, + input rvalid, + output rready, + input rlast, + input rdata, + input rid, + input ruser, + input rresp + ); + +modport responder_port + ( + input axi_clk, + input rst, + input awvalid, + output awready, + input awaddr, + input awsize, + input awburst, + input awcache, + input awprot, + input awid, + input awlen, + input awlock, + input awqos, + input awregion, + input awuser, + input wvalid, + output wready, + input wlast, + input wdata, + input wstrb, + input wid, + input wuser, + output bwvalid, + input bwready, + output bresp, + output bid, + output buser, + input arvalid, + output aready, + input araddr, + input arsize, + input arburst, + input arcache, + input arprot, + input arid, + input arlen, + input arlock, + input arqos, + input aregion, + input aruser, + output rvalid, + input rready, + output rlast, + output rdata, + output rid, + output ruser, + output rresp + ); + + +// pragma uvmf custom interface_item_additional begin +// pragma uvmf custom interface_item_additional end + +endinterface + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/verification_ip/interface_packages/axi_m_pkg/src/axi_m_infact_coverage_strategy.csv b/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/verification_ip/interface_packages/axi_m_pkg/src/axi_m_infact_coverage_strategy.csv new file mode 100644 index 00000000..1c218e14 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/verification_ip/interface_packages/axi_m_pkg/src/axi_m_infact_coverage_strategy.csv @@ -0,0 +1,6 @@ +Global +auto_bin_max, 64 + +Name,Type,Include +rand_fields,coverpoint,=rand *.** + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/verification_ip/interface_packages/axi_m_pkg/src/axi_m_macros.svh b/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/verification_ip/interface_packages/axi_m_pkg/src/axi_m_macros.svh new file mode 100644 index 00000000..f04eaa78 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/verification_ip/interface_packages/axi_m_pkg/src/axi_m_macros.svh @@ -0,0 +1,517 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This file contains macros used with the axi_m package. +// These macros include packed struct definitions. These structs are +// used to pass data between classes, hvl, and BFM's, hdl. Use of +// structs are more efficient and simpler to modify. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// + +// **************************************************************************** +// When changing the contents of this struct, be sure to update the to_struct +// and from_struct methods defined in the macros below that are used in +// the axi_m_configuration class. +// + `define axi_m_CONFIGURATION_STRUCT \ +typedef struct packed { \ + uvmf_active_passive_t active_passive; \ + uvmf_initiator_responder_t initiator_responder; \ + } axi_m_configuration_s; + + `define axi_m_CONFIGURATION_TO_STRUCT_FUNCTION \ + virtual function axi_m_configuration_s to_struct();\ + axi_m_configuration_struct = \ + {\ + this.active_passive,\ + this.initiator_responder\ + };\ + return ( axi_m_configuration_struct );\ + endfunction + + `define axi_m_CONFIGURATION_FROM_STRUCT_FUNCTION \ + virtual function void from_struct(axi_m_configuration_s axi_m_configuration_struct);\ + {\ + this.active_passive,\ + this.initiator_responder \ + } = axi_m_configuration_struct;\ + endfunction + +// **************************************************************************** +// When changing the contents of this struct, be sure to update the to_monitor_struct +// and from_monitor_struct methods of the axi_m_transaction class. +// + `define axi_m_MONITOR_STRUCT typedef struct packed { \ + bit awvalid ; \ + bit awready ; \ + bit [AW_WIDTH-1:0] awaddr ; \ + bit awsize ; \ + bit awburst ; \ + bit awcache ; \ + bit awprot ; \ + bit [X-1:0] awid ; \ + bit [LEN-1:0] awlen ; \ + bit awlock ; \ + bit awqos ; \ + bit awregion ; \ + bit [X-1:0] awuser ; \ + bit wvalid ; \ + bit wready ; \ + bit wlast ; \ + bit [DATA_WIDTH-1:0] wdata ; \ + bit [DATA_WIDTH/8-1:0] wstrb ; \ + bit [X-1:0] wid ; \ + bit [X-1:0] wuser ; \ + bit bwvalid ; \ + bit bwready ; \ + bit bresp ; \ + bit [X-1:0] bid ; \ + bit [X-1:0] buser ; \ + bit arvalid ; \ + bit aready ; \ + bit [AW_WIDTH-1:0] araddr ; \ + bit arsize ; \ + bit arburst ; \ + bit arcache ; \ + bit arprot ; \ + bit [X-1:0] arid ; \ + bit [LEN-1:0] arlen ; \ + bit arlock ; \ + bit arqos ; \ + bit aregion ; \ + bit [X-1:0] aruser ; \ + bit rvalid ; \ + bit rready ; \ + bit rlast ; \ + bit [DATA_WIDTH-1:0] rdata ; \ + bit [X-1:0] rid ; \ + bit [X-1:0] ruser ; \ + bit rresp ; \ + } axi_m_monitor_s; + + `define axi_m_TO_MONITOR_STRUCT_FUNCTION \ + virtual function axi_m_monitor_s to_monitor_struct();\ + axi_m_monitor_struct = \ + { \ + this.awvalid , \ + this.awready , \ + this.awaddr , \ + this.awsize , \ + this.awburst , \ + this.awcache , \ + this.awprot , \ + this.awid , \ + this.awlen , \ + this.awlock , \ + this.awqos , \ + this.awregion , \ + this.awuser , \ + this.wvalid , \ + this.wready , \ + this.wlast , \ + this.wdata , \ + this.wstrb , \ + this.wid , \ + this.wuser , \ + this.bwvalid , \ + this.bwready , \ + this.bresp , \ + this.bid , \ + this.buser , \ + this.arvalid , \ + this.aready , \ + this.araddr , \ + this.arsize , \ + this.arburst , \ + this.arcache , \ + this.arprot , \ + this.arid , \ + this.arlen , \ + this.arlock , \ + this.arqos , \ + this.aregion , \ + this.aruser , \ + this.rvalid , \ + this.rready , \ + this.rlast , \ + this.rdata , \ + this.rid , \ + this.ruser , \ + this.rresp \ + };\ + return ( axi_m_monitor_struct);\ + endfunction\ + + `define axi_m_FROM_MONITOR_STRUCT_FUNCTION \ + virtual function void from_monitor_struct(axi_m_monitor_s axi_m_monitor_struct);\ + {\ + this.awvalid , \ + this.awready , \ + this.awaddr , \ + this.awsize , \ + this.awburst , \ + this.awcache , \ + this.awprot , \ + this.awid , \ + this.awlen , \ + this.awlock , \ + this.awqos , \ + this.awregion , \ + this.awuser , \ + this.wvalid , \ + this.wready , \ + this.wlast , \ + this.wdata , \ + this.wstrb , \ + this.wid , \ + this.wuser , \ + this.bwvalid , \ + this.bwready , \ + this.bresp , \ + this.bid , \ + this.buser , \ + this.arvalid , \ + this.aready , \ + this.araddr , \ + this.arsize , \ + this.arburst , \ + this.arcache , \ + this.arprot , \ + this.arid , \ + this.arlen , \ + this.arlock , \ + this.arqos , \ + this.aregion , \ + this.aruser , \ + this.rvalid , \ + this.rready , \ + this.rlast , \ + this.rdata , \ + this.rid , \ + this.ruser , \ + this.rresp \ + } = axi_m_monitor_struct;\ + endfunction + +// **************************************************************************** +// When changing the contents of this struct, be sure to update the to_initiator_struct +// and from_initiator_struct methods of the axi_m_transaction class. +// Also update the comments in the driver BFM. +// + `define axi_m_INITIATOR_STRUCT typedef struct packed { \ + bit awvalid ; \ + bit awready ; \ + bit [AW_WIDTH-1:0] awaddr ; \ + bit awsize ; \ + bit awburst ; \ + bit awcache ; \ + bit awprot ; \ + bit [X-1:0] awid ; \ + bit [LEN-1:0] awlen ; \ + bit awlock ; \ + bit awqos ; \ + bit awregion ; \ + bit [X-1:0] awuser ; \ + bit wvalid ; \ + bit wready ; \ + bit wlast ; \ + bit [DATA_WIDTH-1:0] wdata ; \ + bit [DATA_WIDTH/8-1:0] wstrb ; \ + bit [X-1:0] wid ; \ + bit [X-1:0] wuser ; \ + bit bwvalid ; \ + bit bwready ; \ + bit bresp ; \ + bit [X-1:0] bid ; \ + bit [X-1:0] buser ; \ + bit arvalid ; \ + bit aready ; \ + bit [AW_WIDTH-1:0] araddr ; \ + bit arsize ; \ + bit arburst ; \ + bit arcache ; \ + bit arprot ; \ + bit [X-1:0] arid ; \ + bit [LEN-1:0] arlen ; \ + bit arlock ; \ + bit arqos ; \ + bit aregion ; \ + bit [X-1:0] aruser ; \ + bit rvalid ; \ + bit rready ; \ + bit rlast ; \ + bit [DATA_WIDTH-1:0] rdata ; \ + bit [X-1:0] rid ; \ + bit [X-1:0] ruser ; \ + bit rresp ; \ + } axi_m_initiator_s; + + `define axi_m_TO_INITIATOR_STRUCT_FUNCTION \ + virtual function axi_m_initiator_s to_initiator_struct();\ + axi_m_initiator_struct = \ + {\ + this.awvalid , \ + this.awready , \ + this.awaddr , \ + this.awsize , \ + this.awburst , \ + this.awcache , \ + this.awprot , \ + this.awid , \ + this.awlen , \ + this.awlock , \ + this.awqos , \ + this.awregion , \ + this.awuser , \ + this.wvalid , \ + this.wready , \ + this.wlast , \ + this.wdata , \ + this.wstrb , \ + this.wid , \ + this.wuser , \ + this.bwvalid , \ + this.bwready , \ + this.bresp , \ + this.bid , \ + this.buser , \ + this.arvalid , \ + this.aready , \ + this.araddr , \ + this.arsize , \ + this.arburst , \ + this.arcache , \ + this.arprot , \ + this.arid , \ + this.arlen , \ + this.arlock , \ + this.arqos , \ + this.aregion , \ + this.aruser , \ + this.rvalid , \ + this.rready , \ + this.rlast , \ + this.rdata , \ + this.rid , \ + this.ruser , \ + this.rresp \ + };\ + return ( axi_m_initiator_struct);\ + endfunction + + `define axi_m_FROM_INITIATOR_STRUCT_FUNCTION \ + virtual function void from_initiator_struct(axi_m_initiator_s axi_m_initiator_struct);\ + {\ + this.awvalid , \ + this.awready , \ + this.awaddr , \ + this.awsize , \ + this.awburst , \ + this.awcache , \ + this.awprot , \ + this.awid , \ + this.awlen , \ + this.awlock , \ + this.awqos , \ + this.awregion , \ + this.awuser , \ + this.wvalid , \ + this.wready , \ + this.wlast , \ + this.wdata , \ + this.wstrb , \ + this.wid , \ + this.wuser , \ + this.bwvalid , \ + this.bwready , \ + this.bresp , \ + this.bid , \ + this.buser , \ + this.arvalid , \ + this.aready , \ + this.araddr , \ + this.arsize , \ + this.arburst , \ + this.arcache , \ + this.arprot , \ + this.arid , \ + this.arlen , \ + this.arlock , \ + this.arqos , \ + this.aregion , \ + this.aruser , \ + this.rvalid , \ + this.rready , \ + this.rlast , \ + this.rdata , \ + this.rid , \ + this.ruser , \ + this.rresp \ + } = axi_m_initiator_struct;\ + endfunction + +// **************************************************************************** +// When changing the contents of this struct, be sure to update the to_responder_struct +// and from_responder_struct methods of the axi_m_transaction class. +// Also update the comments in the driver BFM. +// + `define axi_m_RESPONDER_STRUCT typedef struct packed { \ + bit awvalid ; \ + bit awready ; \ + bit [AW_WIDTH-1:0] awaddr ; \ + bit awsize ; \ + bit awburst ; \ + bit awcache ; \ + bit awprot ; \ + bit [X-1:0] awid ; \ + bit [LEN-1:0] awlen ; \ + bit awlock ; \ + bit awqos ; \ + bit awregion ; \ + bit [X-1:0] awuser ; \ + bit wvalid ; \ + bit wready ; \ + bit wlast ; \ + bit [DATA_WIDTH-1:0] wdata ; \ + bit [DATA_WIDTH/8-1:0] wstrb ; \ + bit [X-1:0] wid ; \ + bit [X-1:0] wuser ; \ + bit bwvalid ; \ + bit bwready ; \ + bit bresp ; \ + bit [X-1:0] bid ; \ + bit [X-1:0] buser ; \ + bit arvalid ; \ + bit aready ; \ + bit [AW_WIDTH-1:0] araddr ; \ + bit arsize ; \ + bit arburst ; \ + bit arcache ; \ + bit arprot ; \ + bit [X-1:0] arid ; \ + bit [LEN-1:0] arlen ; \ + bit arlock ; \ + bit arqos ; \ + bit aregion ; \ + bit [X-1:0] aruser ; \ + bit rvalid ; \ + bit rready ; \ + bit rlast ; \ + bit [DATA_WIDTH-1:0] rdata ; \ + bit [X-1:0] rid ; \ + bit [X-1:0] ruser ; \ + bit rresp ; \ + } axi_m_responder_s; + + `define axi_m_TO_RESPONDER_STRUCT_FUNCTION \ + virtual function axi_m_responder_s to_responder_struct();\ + axi_m_responder_struct = \ + {\ + this.awvalid , \ + this.awready , \ + this.awaddr , \ + this.awsize , \ + this.awburst , \ + this.awcache , \ + this.awprot , \ + this.awid , \ + this.awlen , \ + this.awlock , \ + this.awqos , \ + this.awregion , \ + this.awuser , \ + this.wvalid , \ + this.wready , \ + this.wlast , \ + this.wdata , \ + this.wstrb , \ + this.wid , \ + this.wuser , \ + this.bwvalid , \ + this.bwready , \ + this.bresp , \ + this.bid , \ + this.buser , \ + this.arvalid , \ + this.aready , \ + this.araddr , \ + this.arsize , \ + this.arburst , \ + this.arcache , \ + this.arprot , \ + this.arid , \ + this.arlen , \ + this.arlock , \ + this.arqos , \ + this.aregion , \ + this.aruser , \ + this.rvalid , \ + this.rready , \ + this.rlast , \ + this.rdata , \ + this.rid , \ + this.ruser , \ + this.rresp \ + };\ + return ( axi_m_responder_struct);\ + endfunction + + `define axi_m_FROM_RESPONDER_STRUCT_FUNCTION \ + virtual function void from_responder_struct(axi_m_responder_s axi_m_responder_struct);\ + {\ + this.awvalid , \ + this.awready , \ + this.awaddr , \ + this.awsize , \ + this.awburst , \ + this.awcache , \ + this.awprot , \ + this.awid , \ + this.awlen , \ + this.awlock , \ + this.awqos , \ + this.awregion , \ + this.awuser , \ + this.wvalid , \ + this.wready , \ + this.wlast , \ + this.wdata , \ + this.wstrb , \ + this.wid , \ + this.wuser , \ + this.bwvalid , \ + this.bwready , \ + this.bresp , \ + this.bid , \ + this.buser , \ + this.arvalid , \ + this.aready , \ + this.araddr , \ + this.arsize , \ + this.arburst , \ + this.arcache , \ + this.arprot , \ + this.arid , \ + this.arlen , \ + this.arlock , \ + this.arqos , \ + this.aregion , \ + this.aruser , \ + this.rvalid , \ + this.rready , \ + this.rlast , \ + this.rdata , \ + this.rid , \ + this.ruser , \ + this.rresp \ + } = axi_m_responder_struct;\ + endfunction +// pragma uvmf custom additional begin +// pragma uvmf custom additional end diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/verification_ip/interface_packages/axi_m_pkg/src/axi_m_monitor.svh b/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/verification_ip/interface_packages/axi_m_pkg/src/axi_m_monitor.svh new file mode 100644 index 00000000..c5f4c0df --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/verification_ip/interface_packages/axi_m_pkg/src/axi_m_monitor.svh @@ -0,0 +1,112 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This class receives axi_m transactions observed by the +// axi_m monitor BFM and broadcasts them through the analysis port +// on the agent. It accesses the monitor BFM through the monitor +// task. This UVM component captures transactions +// for viewing in the waveform viewer if the +// enable_transaction_viewing flag is set in the configuration. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class axi_m_monitor #( + int AW_WIDTH = 32, + int LEN = 8, + int DATA_WIDTH = 32, + int X = 16 + ) extends uvmf_monitor_base #( + .CONFIG_T(axi_m_configuration #( + .AW_WIDTH(AW_WIDTH), + .LEN(LEN), + .DATA_WIDTH(DATA_WIDTH), + .X(X) + )), + .BFM_BIND_T(virtual axi_m_monitor_bfm #( + .AW_WIDTH(AW_WIDTH), + .LEN(LEN), + .DATA_WIDTH(DATA_WIDTH), + .X(X) + )), + .TRANS_T(axi_m_transaction #( + .AW_WIDTH(AW_WIDTH), + .LEN(LEN), + .DATA_WIDTH(DATA_WIDTH), + .X(X) + ))); + + `uvm_component_param_utils( axi_m_monitor #( + AW_WIDTH, + LEN, + DATA_WIDTH, + X + )) + +// Structure used to pass data from monitor BFM to monitor class in agent. +// Use to_monitor_struct function to pack transaction variables into structure. +// Use from_monitor_struct function to unpack transaction variables from structure. +`axi_m_MONITOR_STRUCT + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + +// **************************************************************************** +// This function is the standard SystemVerilog constructor. +// + function new( string name = "", uvm_component parent = null ); + super.new( name, parent ); + endfunction + +// **************************************************************************** +// This function sends configuration object variables to the monitor BFM +// using the configuration struct. +// + virtual function void configure(input CONFIG_T cfg); + bfm.configure( cfg.to_struct() ); + + endfunction + +// **************************************************************************** +// This function places a handle to this class in the proxy variable in the +// monitor BFM. This allows the monitor BFM to call the notify_transaction +// function within this class. +// + virtual function void set_bfm_proxy_handle(); + bfm.proxy = this; endfunction + +// *************************************************************************** + virtual task run_phase(uvm_phase phase); + // Start monitor BFM thread and don't call super.run() in order to + // override the default monitor proxy 'pull' behavior with the more + // emulation-friendly BFM 'push' approach using the notify_transaction + // function below + bfm.start_monitoring(); + endtask + +// ************************************************************************** + +// This function is called by the monitor BFM. It receives data observed by the +// monitor BFM. Data is passed using the axi_m_monitor_struct. + virtual function void notify_transaction(input axi_m_monitor_s axi_m_monitor_struct); + + + trans = new("trans"); + trans.from_monitor_struct(axi_m_monitor_struct); + trans.start_time = time_stamp; + trans.end_time = $time; + time_stamp = trans.end_time; + + analyze(trans); + endfunction + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/verification_ip/interface_packages/axi_m_pkg/src/axi_m_monitor_bfm.sv b/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/verification_ip/interface_packages/axi_m_pkg/src/axi_m_monitor_bfm.sv new file mode 100644 index 00000000..649ee7d6 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/verification_ip/interface_packages/axi_m_pkg/src/axi_m_monitor_bfm.sv @@ -0,0 +1,360 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This interface performs the axi_m signal monitoring. +// It is accessed by the uvm axi_m monitor through a virtual +// interface handle in the axi_m configuration. It monitors the +// signals passed in through the port connection named bus of +// type axi_m_if. +// +// Input signals from the axi_m_if are assigned to an internal input +// signal with a _i suffix. The _i signal should be used for sampling. +// +// The input signal connections are as follows: +// bus.signal -> signal_i +// +// Interface functions and tasks used by UVM components: +// monitor(inout TRANS_T txn); +// This task receives the transaction, txn, from the +// UVM monitor and then populates variables in txn +// from values observed on bus activity. This task +// blocks until an operation on the axi_m bus is complete. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +import uvmf_base_pkg_hdl::*; +import axi_m_pkg_hdl::*; +`include "src/axi_m_macros.svh" + + +interface axi_m_monitor_bfm #( + int AW_WIDTH = 32, + int LEN = 8, + int DATA_WIDTH = 32, + int X = 16 + ) + ( axi_m_if bus ); + // The pragma below and additional ones in-lined further down are for running this BFM on Veloce + // pragma attribute axi_m_monitor_bfm partition_interface_xif + +`ifndef XRTL +// This code is to aid in debugging parameter mismatches between the BFM and its corresponding agent. +// Enable this debug by setting UVM_VERBOSITY to UVM_DEBUG +// Setting UVM_VERBOSITY to UVM_DEBUG causes all BFM's and all agents to display their parameter settings. +// All of the messages from this feature have a UVM messaging id value of "CFG" +// The transcript or run.log can be parsed to ensure BFM parameter settings match its corresponding agents parameter settings. +import uvm_pkg::*; +`include "uvm_macros.svh" +initial begin : bfm_vs_agent_parameter_debug + `uvm_info("CFG", + $psprintf("The BFM at '%m' has the following parameters: AW_WIDTH=%x LEN=%x DATA_WIDTH=%x X=%x ", AW_WIDTH,LEN,DATA_WIDTH,X), + UVM_DEBUG) +end +`endif + + + // Structure used to pass transaction data from monitor BFM to monitor class in agent. +`axi_m_MONITOR_STRUCT + axi_m_monitor_s axi_m_monitor_struct; + + // Structure used to pass configuration data from monitor class to monitor BFM. + `axi_m_CONFIGURATION_STRUCT + + + // Config value to determine if this is an initiator or a responder + uvmf_initiator_responder_t initiator_responder; + // Custom configuration variables. + // These are set using the configure function which is called during the UVM connect_phase + + logic axi_clk_i; + logic rst_i; + tri awvalid_i; + tri awready_i; + tri [AW_WIDTH-1:0] awaddr_i; + tri [2:0] awsize_i; + tri [1:0] awburst_i; + tri [3:0] awcache_i; + tri [2:0] awprot_i; + tri [X-1:0] awid_i; + tri [LEN-1:0] awlen_i; + tri awlock_i; + tri [3:0] awqos_i; + tri [3:0] awregion_i; + tri [X-1:0] awuser_i; + tri wvalid_i; + tri wready_i; + tri wlast_i; + tri [DATA_WIDTH-1:0] wdata_i; + tri [DATA_WIDTH/8-1:0] wstrb_i; + tri [X-1:0] wid_i; + tri [X-1:0] wuser_i; + tri bwvalid_i; + tri bwready_i; + tri [1:0] bresp_i; + tri [X-1:0] bid_i; + tri [X-1:0] buser_i; + tri arvalid_i; + tri aready_i; + tri [AW_WIDTH-1:0] araddr_i; + tri [2:0] arsize_i; + tri [1:0] arburst_i; + tri [3:0] arcache_i; + tri [2:0] arprot_i; + tri [X-1:0] arid_i; + tri [LEN-1:0] arlen_i; + tri arlock_i; + tri [3:0] arqos_i; + tri [3:0] aregion_i; + tri [X-1:0] aruser_i; + tri rvalid_i; + tri rready_i; + tri rlast_i; + tri [DATA_WIDTH-1:0] rdata_i; + tri [X-1:0] rid_i; + tri [X-1:0] ruser_i; + tri [1:0] rresp_i; + assign axi_clk_i = bus.axi_clk; + assign rst_i = bus.rst; + assign awvalid_i = bus.awvalid; + assign awready_i = bus.awready; + assign awaddr_i = bus.awaddr; + assign awsize_i = bus.awsize; + assign awburst_i = bus.awburst; + assign awcache_i = bus.awcache; + assign awprot_i = bus.awprot; + assign awid_i = bus.awid; + assign awlen_i = bus.awlen; + assign awlock_i = bus.awlock; + assign awqos_i = bus.awqos; + assign awregion_i = bus.awregion; + assign awuser_i = bus.awuser; + assign wvalid_i = bus.wvalid; + assign wready_i = bus.wready; + assign wlast_i = bus.wlast; + assign wdata_i = bus.wdata; + assign wstrb_i = bus.wstrb; + assign wid_i = bus.wid; + assign wuser_i = bus.wuser; + assign bwvalid_i = bus.bwvalid; + assign bwready_i = bus.bwready; + assign bresp_i = bus.bresp; + assign bid_i = bus.bid; + assign buser_i = bus.buser; + assign arvalid_i = bus.arvalid; + assign aready_i = bus.aready; + assign araddr_i = bus.araddr; + assign arsize_i = bus.arsize; + assign arburst_i = bus.arburst; + assign arcache_i = bus.arcache; + assign arprot_i = bus.arprot; + assign arid_i = bus.arid; + assign arlen_i = bus.arlen; + assign arlock_i = bus.arlock; + assign arqos_i = bus.arqos; + assign aregion_i = bus.aregion; + assign aruser_i = bus.aruser; + assign rvalid_i = bus.rvalid; + assign rready_i = bus.rready; + assign rlast_i = bus.rlast; + assign rdata_i = bus.rdata; + assign rid_i = bus.rid; + assign ruser_i = bus.ruser; + assign rresp_i = bus.rresp; + + // Proxy handle to UVM monitor + axi_m_pkg::axi_m_monitor #( + .AW_WIDTH(AW_WIDTH), + .LEN(LEN), + .DATA_WIDTH(DATA_WIDTH), + .X(X) + ) proxy; + // pragma tbx oneway proxy.notify_transaction + + // pragma uvmf custom interface_item_additional begin + // pragma uvmf custom interface_item_additional end + + //****************************************************************** + task wait_for_reset();// pragma tbx xtf + @(posedge axi_clk_i) ; + do_wait_for_reset(); + endtask + + // **************************************************************************** + task do_wait_for_reset(); + // pragma uvmf custom reset_condition begin + wait ( rst_i === 1 ) ; + @(posedge axi_clk_i) ; + // pragma uvmf custom reset_condition end + endtask + + //****************************************************************** + + task wait_for_num_clocks(input int unsigned count); // pragma tbx xtf + @(posedge axi_clk_i); + + repeat (count-1) @(posedge axi_clk_i); + endtask + + //****************************************************************** + event go; + function void start_monitoring();// pragma tbx xtf + -> go; + endfunction + + // **************************************************************************** + initial begin + @go; + forever begin + @(posedge axi_clk_i); + do_monitor( axi_m_monitor_struct ); + + + proxy.notify_transaction( axi_m_monitor_struct ); + + end + end + + //****************************************************************** + // The configure() function is used to pass agent configuration + // variables to the monitor BFM. It is called by the monitor within + // the agent at the beginning of the simulation. It may be called + // during the simulation if agent configuration variables are updated + // and the monitor BFM needs to be aware of the new configuration + // variables. + // + function void configure(axi_m_configuration_s axi_m_configuration_arg); // pragma tbx xtf + initiator_responder = axi_m_configuration_arg.initiator_responder; + // pragma uvmf custom configure begin + // pragma uvmf custom configure end + endfunction + + + // **************************************************************************** + + task do_monitor(output axi_m_monitor_s axi_m_monitor_struct); + // + // Available struct members: + // // axi_m_monitor_struct.awvalid + // // axi_m_monitor_struct.awready + // // axi_m_monitor_struct.awaddr + // // axi_m_monitor_struct.awsize + // // axi_m_monitor_struct.awburst + // // axi_m_monitor_struct.awcache + // // axi_m_monitor_struct.awprot + // // axi_m_monitor_struct.awid + // // axi_m_monitor_struct.awlen + // // axi_m_monitor_struct.awlock + // // axi_m_monitor_struct.awqos + // // axi_m_monitor_struct.awregion + // // axi_m_monitor_struct.awuser + // // axi_m_monitor_struct.wvalid + // // axi_m_monitor_struct.wready + // // axi_m_monitor_struct.wlast + // // axi_m_monitor_struct.wdata + // // axi_m_monitor_struct.wstrb + // // axi_m_monitor_struct.wid + // // axi_m_monitor_struct.wuser + // // axi_m_monitor_struct.bwvalid + // // axi_m_monitor_struct.bwready + // // axi_m_monitor_struct.bresp + // // axi_m_monitor_struct.bid + // // axi_m_monitor_struct.buser + // // axi_m_monitor_struct.arvalid + // // axi_m_monitor_struct.aready + // // axi_m_monitor_struct.araddr + // // axi_m_monitor_struct.arsize + // // axi_m_monitor_struct.arburst + // // axi_m_monitor_struct.arcache + // // axi_m_monitor_struct.arprot + // // axi_m_monitor_struct.arid + // // axi_m_monitor_struct.arlen + // // axi_m_monitor_struct.arlock + // // axi_m_monitor_struct.arqos + // // axi_m_monitor_struct.aregion + // // axi_m_monitor_struct.aruser + // // axi_m_monitor_struct.rvalid + // // axi_m_monitor_struct.rready + // // axi_m_monitor_struct.rlast + // // axi_m_monitor_struct.rdata + // // axi_m_monitor_struct.rid + // // axi_m_monitor_struct.ruser + // // axi_m_monitor_struct.rresp + // // + // Reference code; + // How to wait for signal value + // while (control_signal === 1'b1) @(posedge axi_clk_i); + // + // How to assign a struct member, named xyz, from a signal. + // All available input signals listed. + // axi_m_monitor_struct.xyz = awvalid_i; // + // axi_m_monitor_struct.xyz = awready_i; // + // axi_m_monitor_struct.xyz = awaddr_i; // [AW_WIDTH-1:0] + // axi_m_monitor_struct.xyz = awsize_i; // [2:0] + // axi_m_monitor_struct.xyz = awburst_i; // [1:0] + // axi_m_monitor_struct.xyz = awcache_i; // [3:0] + // axi_m_monitor_struct.xyz = awprot_i; // [2:0] + // axi_m_monitor_struct.xyz = awid_i; // [X-1:0] + // axi_m_monitor_struct.xyz = awlen_i; // [LEN-1:0] + // axi_m_monitor_struct.xyz = awlock_i; // + // axi_m_monitor_struct.xyz = awqos_i; // [3:0] + // axi_m_monitor_struct.xyz = awregion_i; // [3:0] + // axi_m_monitor_struct.xyz = awuser_i; // [X-1:0] + // axi_m_monitor_struct.xyz = wvalid_i; // + // axi_m_monitor_struct.xyz = wready_i; // + // axi_m_monitor_struct.xyz = wlast_i; // + // axi_m_monitor_struct.xyz = wdata_i; // [DATA_WIDTH-1:0] + // axi_m_monitor_struct.xyz = wstrb_i; // [DATA_WIDTH/8-1:0] + // axi_m_monitor_struct.xyz = wid_i; // [X-1:0] + // axi_m_monitor_struct.xyz = wuser_i; // [X-1:0] + // axi_m_monitor_struct.xyz = bwvalid_i; // + // axi_m_monitor_struct.xyz = bwready_i; // + // axi_m_monitor_struct.xyz = bresp_i; // [1:0] + // axi_m_monitor_struct.xyz = bid_i; // [X-1:0] + // axi_m_monitor_struct.xyz = buser_i; // [X-1:0] + // axi_m_monitor_struct.xyz = arvalid_i; // + // axi_m_monitor_struct.xyz = aready_i; // + // axi_m_monitor_struct.xyz = araddr_i; // [AW_WIDTH-1:0] + // axi_m_monitor_struct.xyz = arsize_i; // [2:0] + // axi_m_monitor_struct.xyz = arburst_i; // [1:0] + // axi_m_monitor_struct.xyz = arcache_i; // [3:0] + // axi_m_monitor_struct.xyz = arprot_i; // [2:0] + // axi_m_monitor_struct.xyz = arid_i; // [X-1:0] + // axi_m_monitor_struct.xyz = arlen_i; // [LEN-1:0] + // axi_m_monitor_struct.xyz = arlock_i; // + // axi_m_monitor_struct.xyz = arqos_i; // [3:0] + // axi_m_monitor_struct.xyz = aregion_i; // [3:0] + // axi_m_monitor_struct.xyz = aruser_i; // [X-1:0] + // axi_m_monitor_struct.xyz = rvalid_i; // + // axi_m_monitor_struct.xyz = rready_i; // + // axi_m_monitor_struct.xyz = rlast_i; // + // axi_m_monitor_struct.xyz = rdata_i; // [DATA_WIDTH-1:0] + // axi_m_monitor_struct.xyz = rid_i; // [X-1:0] + // axi_m_monitor_struct.xyz = ruser_i; // [X-1:0] + // axi_m_monitor_struct.xyz = rresp_i; // [1:0] + // pragma uvmf custom do_monitor begin + // UVMF_CHANGE_ME : Implement protocol monitoring. The commented reference code + // below are examples of how to capture signal values and assign them to + // structure members. All available input signals are listed. The 'while' + // code example shows how to wait for a synchronous flow control signal. This + // task should return when a complete transfer has been observed. Once this task is + // exited with captured values, it is then called again to wait for and observe + // the next transfer. One clock cycle is consumed between calls to do_monitor. + @(posedge axi_clk_i); + @(posedge axi_clk_i); + @(posedge axi_clk_i); + @(posedge axi_clk_i); + // pragma uvmf custom do_monitor end + endtask + + +endinterface + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/verification_ip/interface_packages/axi_m_pkg/src/axi_m_random_sequence.svh b/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/verification_ip/interface_packages/axi_m_pkg/src/axi_m_random_sequence.svh new file mode 100644 index 00000000..06a95ce8 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/verification_ip/interface_packages/axi_m_pkg/src/axi_m_random_sequence.svh @@ -0,0 +1,73 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: +// This sequences randomizes the axi_m transaction and sends it +// to the UVM driver. +// +// This sequence constructs and randomizes a axi_m_transaction. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class axi_m_random_sequence #( + int AW_WIDTH = 32, + int LEN = 8, + int DATA_WIDTH = 32, + int X = 16 + ) + extends axi_m_sequence_base #( + .AW_WIDTH(AW_WIDTH), + .LEN(LEN), + .DATA_WIDTH(DATA_WIDTH), + .X(X) + ); + + `uvm_object_param_utils( axi_m_random_sequence #( + AW_WIDTH, + LEN, + DATA_WIDTH, + X + )) + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + //***************************************************************** + function new(string name = ""); + super.new(name); + endfunction: new + + // **************************************************************************** + // TASK : body() + // This task is automatically executed when this sequence is started using the + // start(sequencerHandle) task. + // + task body(); + + // Construct the transaction + req=axi_m_transaction#( + .AW_WIDTH(AW_WIDTH), + .LEN(LEN), + .DATA_WIDTH(DATA_WIDTH), + .X(X) + )::type_id::create("req"); + start_item(req); + // Randomize the transaction + if(!req.randomize()) `uvm_fatal("SEQ", "axi_m_random_sequence::body()-axi_m_transaction randomization failed") + // Send the transaction to the axi_m_driver_bfm via the sequencer and axi_m_driver. + finish_item(req); + `uvm_info("SEQ", {"Response:",req.convert2string()},UVM_MEDIUM) + + endtask + +endclass: axi_m_random_sequence + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/verification_ip/interface_packages/axi_m_pkg/src/axi_m_responder_sequence.svh b/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/verification_ip/interface_packages/axi_m_pkg/src/axi_m_responder_sequence.svh new file mode 100644 index 00000000..caf31664 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/verification_ip/interface_packages/axi_m_pkg/src/axi_m_responder_sequence.svh @@ -0,0 +1,69 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This class can be used to provide stimulus when an interface +// has been configured to run in a responder mode. It +// will never finish by default, always going back to the driver +// and driver BFM for the next transaction with which to respond. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class axi_m_responder_sequence #( + int AW_WIDTH = 32, + int LEN = 8, + int DATA_WIDTH = 32, + int X = 16 + ) + extends axi_m_sequence_base #( + .AW_WIDTH(AW_WIDTH), + .LEN(LEN), + .DATA_WIDTH(DATA_WIDTH), + .X(X) + ); + + `uvm_object_param_utils( axi_m_responder_sequence #( + AW_WIDTH, + LEN, + DATA_WIDTH, + X + )) + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + function new(string name = "axi_m_responder_sequence"); + super.new(name); + endfunction + + task body(); + req=axi_m_transaction#( + .AW_WIDTH(AW_WIDTH), + .LEN(LEN), + .DATA_WIDTH(DATA_WIDTH), + .X(X) + )::type_id::create("req"); + forever begin + start_item(req); + finish_item(req); + // pragma uvmf custom body begin + // UVMF_CHANGE_ME : Do something here with the resulting req item. The + // finish_item() call above will block until the req transaction is ready + // to be handled by the responder sequence. + // If this was an item that required a response, the expectation is + // that the response should be populated within this transaction now. + `uvm_info("SEQ",$sformatf("Processed txn: %s",req.convert2string()),UVM_HIGH) + // pragma uvmf custom body end + end + endtask + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/verification_ip/interface_packages/axi_m_pkg/src/axi_m_sequence_base.svh b/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/verification_ip/interface_packages/axi_m_pkg/src/axi_m_sequence_base.svh new file mode 100644 index 00000000..3924f333 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/verification_ip/interface_packages/axi_m_pkg/src/axi_m_sequence_base.svh @@ -0,0 +1,126 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: +// This file contains the class used as the base class for all sequences +// for this interface. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class axi_m_sequence_base #( + int AW_WIDTH = 32, + int LEN = 8, + int DATA_WIDTH = 32, + int X = 16 + ) extends uvmf_sequence_base #( + .REQ(axi_m_transaction #( + .AW_WIDTH(AW_WIDTH), + .LEN(LEN), + .DATA_WIDTH(DATA_WIDTH), + .X(X) + )), + .RSP(axi_m_transaction #( + .AW_WIDTH(AW_WIDTH), + .LEN(LEN), + .DATA_WIDTH(DATA_WIDTH), + .X(X) + ))); + + `uvm_object_param_utils( axi_m_sequence_base #( + AW_WIDTH, + LEN, + DATA_WIDTH, + X + )) + + // variables + typedef axi_m_transaction #( + .AW_WIDTH(AW_WIDTH), + .LEN(LEN), + .DATA_WIDTH(DATA_WIDTH), + .X(X) + ) axi_m_transaction_req_t; + axi_m_transaction_req_t req; + typedef axi_m_transaction #( + .AW_WIDTH(AW_WIDTH), + .LEN(LEN), + .DATA_WIDTH(DATA_WIDTH), + .X(X) + ) axi_m_transaction_rsp_t; + axi_m_transaction_rsp_t rsp; + + // Event for identifying when a response was received from the sequencer + event new_rsp; + + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + // **************************************************************************** + // TASK : get_responses() + // This task recursively gets sequence item responses from the sequencer. + // + virtual task get_responses(); + fork + begin + // Block until new rsp available + get_response(rsp); + // New rsp received. Indicate to sequence using event. + ->new_rsp; + // Display the received response transaction + `uvm_info("SEQ", {"New response transaction:",rsp.convert2string()}, UVM_MEDIUM) + end + join_none + endtask + + // **************************************************************************** + // TASK : pre_body() + // This task is called automatically when start is called with call_pre_post set to 1 (default). + // By calling get_responses() within pre_body() any derived sequences are automatically + // processing response transactions. Only un-comment this call to get_responses() if you + // have configured the interface driver to utilize the response transaction path by setting + // the configuration variable "return_transaction_response" to 1. Otherwise it is possible + // to impact runtime performance and memory utilization. + // + virtual task pre_body(); + // pragma uvmf custom pre_body begin +// get_responses(); + // pragma uvmf custom pre_body end + endtask + + // **************************************************************************** + // TASK : body() + // This task is called automatically when start is called. This sequence sends + // a req sequence item to the sequencer identified as an argument in the call + // to start. + // + virtual task body(); + // pragma uvmf custom body begin + start_item(req); + finish_item(req); + // pragma uvmf custom body end + endtask + + // **************************************************************************** + // FUNCTION : new() + // This function is the standard SystemVerilog constructor. + // + function new( string name =""); + super.new( name ); + // pragma uvmf custom new begin + req = axi_m_transaction_req_t::type_id::create("req"); + rsp = axi_m_transaction_rsp_t::type_id::create("rsp"); + // pragma uvmf custom new end + endfunction + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/verification_ip/interface_packages/axi_m_pkg/src/axi_m_transaction.svh b/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/verification_ip/interface_packages/axi_m_pkg/src/axi_m_transaction.svh new file mode 100644 index 00000000..18c07970 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/verification_ip/interface_packages/axi_m_pkg/src/axi_m_transaction.svh @@ -0,0 +1,333 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This class defines the variables required for an axi_m +// transaction. Class variables to be displayed in waveform transaction +// viewing are added to the transaction viewing stream in the add_to_wave +// function. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class axi_m_transaction #( + int AW_WIDTH = 32, + int LEN = 8, + int DATA_WIDTH = 32, + int X = 16 + ) extends uvmf_transaction_base; + + `uvm_object_param_utils( axi_m_transaction #( + AW_WIDTH, + LEN, + DATA_WIDTH, + X + )) + + bit awvalid ; + bit awready ; + rand bit [AW_WIDTH-1:0] awaddr ; + rand bit awsize ; + rand bit awburst ; + rand bit awcache ; + rand bit awprot ; + rand bit [X-1:0] awid ; + rand bit [LEN-1:0] awlen ; + rand bit awlock ; + rand bit awqos ; + rand bit awregion ; + rand bit [X-1:0] awuser ; + bit wvalid ; + bit wready ; + bit wlast ; + rand bit [DATA_WIDTH-1:0] wdata ; + rand bit [DATA_WIDTH/8-1:0] wstrb ; + bit [X-1:0] wid ; + rand bit [X-1:0] wuser ; + bit bwvalid ; + bit bwready ; + rand bit bresp ; + bit [X-1:0] bid ; + rand bit [X-1:0] buser ; + bit arvalid ; + bit aready ; + rand bit [AW_WIDTH-1:0] araddr ; + rand bit arsize ; + rand bit arburst ; + rand bit arcache ; + rand bit arprot ; + rand bit [X-1:0] arid ; + rand bit [LEN-1:0] arlen ; + rand bit arlock ; + rand bit arqos ; + rand bit aregion ; + rand bit [X-1:0] aruser ; + bit rvalid ; + bit rready ; + bit rlast ; + rand bit [DATA_WIDTH-1:0] rdata ; + rand bit [X-1:0] rid ; + rand bit [X-1:0] ruser ; + rand bit rresp ; + + //Constraints for the transaction variables: + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + //******************************************************************* + //******************************************************************* + // Macros that define structs and associated functions are + // located in axi_m_macros.svh + + //******************************************************************* + // Monitor macro used by axi_m_monitor and axi_m_monitor_bfm + // This struct is defined in axi_m_macros.svh + `axi_m_MONITOR_STRUCT + axi_m_monitor_s axi_m_monitor_struct; + //******************************************************************* + // FUNCTION: to_monitor_struct() + // This function packs transaction variables into a axi_m_monitor_s + // structure. The function returns the handle to the axi_m_monitor_struct. + // This function is defined in axi_m_macros.svh + `axi_m_TO_MONITOR_STRUCT_FUNCTION + //******************************************************************* + // FUNCTION: from_monitor_struct() + // This function unpacks the struct provided as an argument into transaction + // variables of this class. + // This function is defined in axi_m_macros.svh + `axi_m_FROM_MONITOR_STRUCT_FUNCTION + + //******************************************************************* + // Initiator macro used by axi_m_driver and axi_m_driver_bfm + // to communicate initiator driven data to axi_m_driver_bfm. + // This struct is defined in axi_m_macros.svh + `axi_m_INITIATOR_STRUCT + axi_m_initiator_s axi_m_initiator_struct; + //******************************************************************* + // FUNCTION: to_initiator_struct() + // This function packs transaction variables into a axi_m_initiator_s + // structure. The function returns the handle to the axi_m_initiator_struct. + // This function is defined in axi_m_macros.svh + `axi_m_TO_INITIATOR_STRUCT_FUNCTION + //******************************************************************* + // FUNCTION: from_initiator_struct() + // This function unpacks the struct provided as an argument into transaction + // variables of this class. + // This function is defined in axi_m_macros.svh + `axi_m_FROM_INITIATOR_STRUCT_FUNCTION + + //******************************************************************* + // Responder macro used by axi_m_driver and axi_m_driver_bfm + // to communicate Responder driven data to axi_m_driver_bfm. + // This struct is defined in axi_m_macros.svh + `axi_m_RESPONDER_STRUCT + axi_m_responder_s axi_m_responder_struct; + //******************************************************************* + // FUNCTION: to_responder_struct() + // This function packs transaction variables into a axi_m_responder_s + // structure. The function returns the handle to the axi_m_responder_struct. + // This function is defined in axi_m_macros.svh + `axi_m_TO_RESPONDER_STRUCT_FUNCTION + //******************************************************************* + // FUNCTION: from_responder_struct() + // This function unpacks the struct provided as an argument into transaction + // variables of this class. + // This function is defined in axi_m_macros.svh + `axi_m_FROM_RESPONDER_STRUCT_FUNCTION + // **************************************************************************** + // FUNCTION : new() + // This function is the standard SystemVerilog constructor. + // + function new( string name = "" ); + super.new( name ); + endfunction + + // **************************************************************************** + // FUNCTION: convert2string() + // This function converts all variables in this class to a single string for + // logfile reporting. + // + virtual function string convert2string(); + // pragma uvmf custom convert2string begin + // UVMF_CHANGE_ME : Customize format if desired. + return $sformatf("awvalid:0x%x awready:0x%x awaddr:0x%x awsize:0x%x awburst:0x%x awcache:0x%x awprot:0x%x awid:0x%x awlen:0x%x awlock:0x%x awqos:0x%x awregion:0x%x awuser:0x%x wvalid:0x%x wready:0x%x wlast:0x%x wdata:0x%x wstrb:0x%x wid:0x%x wuser:0x%x bwvalid:0x%x bwready:0x%x bresp:0x%x bid:0x%x buser:0x%x arvalid:0x%x aready:0x%x araddr:0x%x arsize:0x%x arburst:0x%x arcache:0x%x arprot:0x%x arid:0x%x arlen:0x%x arlock:0x%x arqos:0x%x aregion:0x%x aruser:0x%x rvalid:0x%x rready:0x%x rlast:0x%x rdata:0x%x rid:0x%x ruser:0x%x rresp:0x%x ",awvalid,awready,awaddr,awsize,awburst,awcache,awprot,awid,awlen,awlock,awqos,awregion,awuser,wvalid,wready,wlast,wdata,wstrb,wid,wuser,bwvalid,bwready,bresp,bid,buser,arvalid,aready,araddr,arsize,arburst,arcache,arprot,arid,arlen,arlock,arqos,aregion,aruser,rvalid,rready,rlast,rdata,rid,ruser,rresp); + // pragma uvmf custom convert2string end + endfunction + + //******************************************************************* + // FUNCTION: do_print() + // This function is automatically called when the .print() function + // is called on this class. + // + virtual function void do_print(uvm_printer printer); + // pragma uvmf custom do_print begin + // UVMF_CHANGE_ME : Current contents of do_print allows for the use of UVM 1.1d, 1.2 or P1800.2. + // Update based on your own printing preference according to your preferred UVM version + $display(convert2string()); + // pragma uvmf custom do_print end + endfunction + + //******************************************************************* + // FUNCTION: do_compare() + // This function is automatically called when the .compare() function + // is called on this class. + // + virtual function bit do_compare (uvm_object rhs, uvm_comparer comparer); + axi_m_transaction #( + .AW_WIDTH(AW_WIDTH), + .LEN(LEN), + .DATA_WIDTH(DATA_WIDTH), + .X(X) + ) RHS; + if (!$cast(RHS,rhs)) return 0; + // pragma uvmf custom do_compare begin + // UVMF_CHANGE_ME : Eliminate comparison of variables not to be used for compare + return (super.do_compare(rhs,comparer) + ); + // pragma uvmf custom do_compare end + endfunction + + //******************************************************************* + // FUNCTION: do_copy() + // This function is automatically called when the .copy() function + // is called on this class. + // + virtual function void do_copy (uvm_object rhs); + axi_m_transaction #( + .AW_WIDTH(AW_WIDTH), + .LEN(LEN), + .DATA_WIDTH(DATA_WIDTH), + .X(X) + ) RHS; + assert($cast(RHS,rhs)); + // pragma uvmf custom do_copy begin + super.do_copy(rhs); + this.awvalid = RHS.awvalid; + this.awready = RHS.awready; + this.awaddr = RHS.awaddr; + this.awsize = RHS.awsize; + this.awburst = RHS.awburst; + this.awcache = RHS.awcache; + this.awprot = RHS.awprot; + this.awid = RHS.awid; + this.awlen = RHS.awlen; + this.awlock = RHS.awlock; + this.awqos = RHS.awqos; + this.awregion = RHS.awregion; + this.awuser = RHS.awuser; + this.wvalid = RHS.wvalid; + this.wready = RHS.wready; + this.wlast = RHS.wlast; + this.wdata = RHS.wdata; + this.wstrb = RHS.wstrb; + this.wid = RHS.wid; + this.wuser = RHS.wuser; + this.bwvalid = RHS.bwvalid; + this.bwready = RHS.bwready; + this.bresp = RHS.bresp; + this.bid = RHS.bid; + this.buser = RHS.buser; + this.arvalid = RHS.arvalid; + this.aready = RHS.aready; + this.araddr = RHS.araddr; + this.arsize = RHS.arsize; + this.arburst = RHS.arburst; + this.arcache = RHS.arcache; + this.arprot = RHS.arprot; + this.arid = RHS.arid; + this.arlen = RHS.arlen; + this.arlock = RHS.arlock; + this.arqos = RHS.arqos; + this.aregion = RHS.aregion; + this.aruser = RHS.aruser; + this.rvalid = RHS.rvalid; + this.rready = RHS.rready; + this.rlast = RHS.rlast; + this.rdata = RHS.rdata; + this.rid = RHS.rid; + this.ruser = RHS.ruser; + this.rresp = RHS.rresp; + // pragma uvmf custom do_copy end + endfunction + + // **************************************************************************** + // FUNCTION: add_to_wave() + // This function is used to display variables in this class in the waveform + // viewer. The start_time and end_time variables must be set before this + // function is called. If the start_time and end_time variables are not set + // the transaction will be hidden at 0ns on the waveform display. + // + virtual function void add_to_wave(int transaction_viewing_stream_h); + `ifdef QUESTA + if (transaction_view_h == 0) begin + transaction_view_h = $begin_transaction(transaction_viewing_stream_h,"axi_m_transaction",start_time); + end + super.add_to_wave(transaction_view_h); + // pragma uvmf custom add_to_wave begin + // UVMF_CHANGE_ME : Color can be applied to transaction entries based on content, example below + // case() + // 1 : $add_color(transaction_view_h,"red"); + // default : $add_color(transaction_view_h,"grey"); + // endcase + // UVMF_CHANGE_ME : Eliminate transaction variables not wanted in transaction viewing in the waveform viewer + $add_attribute(transaction_view_h,awvalid,"awvalid"); + $add_attribute(transaction_view_h,awready,"awready"); + $add_attribute(transaction_view_h,awaddr,"awaddr"); + $add_attribute(transaction_view_h,awsize,"awsize"); + $add_attribute(transaction_view_h,awburst,"awburst"); + $add_attribute(transaction_view_h,awcache,"awcache"); + $add_attribute(transaction_view_h,awprot,"awprot"); + $add_attribute(transaction_view_h,awid,"awid"); + $add_attribute(transaction_view_h,awlen,"awlen"); + $add_attribute(transaction_view_h,awlock,"awlock"); + $add_attribute(transaction_view_h,awqos,"awqos"); + $add_attribute(transaction_view_h,awregion,"awregion"); + $add_attribute(transaction_view_h,awuser,"awuser"); + $add_attribute(transaction_view_h,wvalid,"wvalid"); + $add_attribute(transaction_view_h,wready,"wready"); + $add_attribute(transaction_view_h,wlast,"wlast"); + $add_attribute(transaction_view_h,wdata,"wdata"); + $add_attribute(transaction_view_h,wstrb,"wstrb"); + $add_attribute(transaction_view_h,wid,"wid"); + $add_attribute(transaction_view_h,wuser,"wuser"); + $add_attribute(transaction_view_h,bwvalid,"bwvalid"); + $add_attribute(transaction_view_h,bwready,"bwready"); + $add_attribute(transaction_view_h,bresp,"bresp"); + $add_attribute(transaction_view_h,bid,"bid"); + $add_attribute(transaction_view_h,buser,"buser"); + $add_attribute(transaction_view_h,arvalid,"arvalid"); + $add_attribute(transaction_view_h,aready,"aready"); + $add_attribute(transaction_view_h,araddr,"araddr"); + $add_attribute(transaction_view_h,arsize,"arsize"); + $add_attribute(transaction_view_h,arburst,"arburst"); + $add_attribute(transaction_view_h,arcache,"arcache"); + $add_attribute(transaction_view_h,arprot,"arprot"); + $add_attribute(transaction_view_h,arid,"arid"); + $add_attribute(transaction_view_h,arlen,"arlen"); + $add_attribute(transaction_view_h,arlock,"arlock"); + $add_attribute(transaction_view_h,arqos,"arqos"); + $add_attribute(transaction_view_h,aregion,"aregion"); + $add_attribute(transaction_view_h,aruser,"aruser"); + $add_attribute(transaction_view_h,rvalid,"rvalid"); + $add_attribute(transaction_view_h,rready,"rready"); + $add_attribute(transaction_view_h,rlast,"rlast"); + $add_attribute(transaction_view_h,rdata,"rdata"); + $add_attribute(transaction_view_h,rid,"rid"); + $add_attribute(transaction_view_h,ruser,"ruser"); + $add_attribute(transaction_view_h,rresp,"rresp"); + // pragma uvmf custom add_to_wave end + $end_transaction(transaction_view_h,end_time); + $free_transaction(transaction_view_h); + `endif // QUESTA + endfunction + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/verification_ip/interface_packages/axi_m_pkg/src/axi_m_transaction_coverage.svh b/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/verification_ip/interface_packages/axi_m_pkg/src/axi_m_transaction_coverage.svh new file mode 100644 index 00000000..088ea2eb --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/verification_ip/interface_packages/axi_m_pkg/src/axi_m_transaction_coverage.svh @@ -0,0 +1,129 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This class records axi_m transaction information using +// a covergroup named axi_m_transaction_cg. An instance of this +// coverage component is instantiated in the uvmf_parameterized_agent +// if the has_coverage flag is set. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class axi_m_transaction_coverage #( + int AW_WIDTH = 32, + int LEN = 8, + int DATA_WIDTH = 32, + int X = 16 + ) extends uvm_subscriber #(.T(axi_m_transaction #( + .AW_WIDTH(AW_WIDTH), + .LEN(LEN), + .DATA_WIDTH(DATA_WIDTH), + .X(X) + ))); + + `uvm_component_param_utils( axi_m_transaction_coverage #( + AW_WIDTH, + LEN, + DATA_WIDTH, + X + )) + + T coverage_trans; + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + // **************************************************************************** + covergroup axi_m_transaction_cg; + // pragma uvmf custom covergroup begin + // UVMF_CHANGE_ME : Add coverage bins, crosses, exclusions, etc. according to coverage needs. + option.auto_bin_max=1024; + option.per_instance=1; + awvalid: coverpoint coverage_trans.awvalid; + awready: coverpoint coverage_trans.awready; + awaddr: coverpoint coverage_trans.awaddr; + awsize: coverpoint coverage_trans.awsize; + awburst: coverpoint coverage_trans.awburst; + awcache: coverpoint coverage_trans.awcache; + awprot: coverpoint coverage_trans.awprot; + awid: coverpoint coverage_trans.awid; + awlen: coverpoint coverage_trans.awlen; + awlock: coverpoint coverage_trans.awlock; + awqos: coverpoint coverage_trans.awqos; + awregion: coverpoint coverage_trans.awregion; + awuser: coverpoint coverage_trans.awuser; + wvalid: coverpoint coverage_trans.wvalid; + wready: coverpoint coverage_trans.wready; + wlast: coverpoint coverage_trans.wlast; + wdata: coverpoint coverage_trans.wdata; + wstrb: coverpoint coverage_trans.wstrb; + wid: coverpoint coverage_trans.wid; + wuser: coverpoint coverage_trans.wuser; + bwvalid: coverpoint coverage_trans.bwvalid; + bwready: coverpoint coverage_trans.bwready; + bresp: coverpoint coverage_trans.bresp; + bid: coverpoint coverage_trans.bid; + buser: coverpoint coverage_trans.buser; + arvalid: coverpoint coverage_trans.arvalid; + aready: coverpoint coverage_trans.aready; + araddr: coverpoint coverage_trans.araddr; + arsize: coverpoint coverage_trans.arsize; + arburst: coverpoint coverage_trans.arburst; + arcache: coverpoint coverage_trans.arcache; + arprot: coverpoint coverage_trans.arprot; + arid: coverpoint coverage_trans.arid; + arlen: coverpoint coverage_trans.arlen; + arlock: coverpoint coverage_trans.arlock; + arqos: coverpoint coverage_trans.arqos; + aregion: coverpoint coverage_trans.aregion; + aruser: coverpoint coverage_trans.aruser; + rvalid: coverpoint coverage_trans.rvalid; + rready: coverpoint coverage_trans.rready; + rlast: coverpoint coverage_trans.rlast; + rdata: coverpoint coverage_trans.rdata; + rid: coverpoint coverage_trans.rid; + ruser: coverpoint coverage_trans.ruser; + rresp: coverpoint coverage_trans.rresp; + // pragma uvmf custom covergroup end + endgroup + + // **************************************************************************** + // FUNCTION : new() + // This function is the standard SystemVerilog constructor. + // + function new(string name="", uvm_component parent=null); + super.new(name,parent); + axi_m_transaction_cg=new; + `uvm_warning("COVERAGE_MODEL_REVIEW", "A covergroup has been constructed which may need review because of either generation or re-generation with merging. Please note that transaction variables added as a result of re-generation and merging are not automatically added to the covergroup. Remove this warning after the covergroup has been reviewed.") + endfunction + + // **************************************************************************** + // FUNCTION : build_phase() + // This function is the standard UVM build_phase. + // + function void build_phase(uvm_phase phase); + axi_m_transaction_cg.set_inst_name($sformatf("axi_m_transaction_cg_%s",get_full_name())); + endfunction + + // **************************************************************************** + // FUNCTION: write (T t) + // This function is automatically executed when a transaction arrives on the + // analysis_export. It copies values from the variables in the transaction + // to local variables used to collect functional coverage. + // + virtual function void write (T t); + `uvm_info("COV","Received transaction",UVM_HIGH); + coverage_trans = t; + axi_m_transaction_cg.sample(); + endfunction + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/verification_ip/interface_packages/axi_m_pkg/src/axi_m_typedefs.svh b/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/verification_ip/interface_packages/axi_m_pkg/src/axi_m_typedefs.svh new file mode 100644 index 00000000..43d85640 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/verification_ip/interface_packages/axi_m_pkg/src/axi_m_typedefs.svh @@ -0,0 +1,20 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: +// This file contains defines and typedefs to be compiled for use in +// the simulation running on the host server when using Veloce. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// + + +// pragma uvmf custom additional begin +// pragma uvmf custom additional end + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/verification_ip/interface_packages/axi_m_pkg/src/axi_m_typedefs_hdl.svh b/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/verification_ip/interface_packages/axi_m_pkg/src/axi_m_typedefs_hdl.svh new file mode 100644 index 00000000..74738c8c --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/verification_ip/interface_packages/axi_m_pkg/src/axi_m_typedefs_hdl.svh @@ -0,0 +1,21 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: +// This file contains defines and typedefs to be compiled for use in +// the simulation running on the emulator when using Veloce. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// + + + +// pragma uvmf custom additional begin +// pragma uvmf custom additional end + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/verification_ip/interface_packages/axi_m_pkg/yaml/axi_m_interface.yaml b/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/verification_ip/interface_packages/axi_m_pkg/yaml/axi_m_interface.yaml new file mode 100644 index 00000000..98e0bca3 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/verification_ip/interface_packages/axi_m_pkg/yaml/axi_m_interface.yaml @@ -0,0 +1,481 @@ +uvmf: + interfaces: + axi_m: + clock: axi_clk + config_constraints: [] + config_vars: [] + existing_library_component: 'True' + gen_inbound_streaming_driver: 'False' + hdl_pkg_parameters: [] + hdl_typedefs: [] + hvl_pkg_parameters: [] + hvl_typedefs: [] + parameters: + - name: AW_WIDTH + type: int + value: '32' + - name: LEN + type: int + value: '8' + - name: DATA_WIDTH + type: int + value: '32' + - name: X + type: int + value: '16' + ports: + - dir: output + name: awvalid + reset_value: '''bz' + width: '1' + - dir: input + name: awready + reset_value: '''bz' + width: '1' + - dir: output + name: awaddr + reset_value: '''bz' + width: AW_WIDTH + - dir: output + name: awsize + reset_value: '''bz' + width: '3' + - dir: output + name: awburst + reset_value: '''bz' + width: '2' + - dir: output + name: awcache + reset_value: '''bz' + width: '4' + - dir: output + name: awprot + reset_value: '''bz' + width: '3' + - dir: output + name: awid + reset_value: '''bz' + width: X + - dir: output + name: awlen + reset_value: '''bz' + width: LEN + - dir: output + name: awlock + reset_value: '''bz' + width: '1' + - dir: output + name: awqos + reset_value: '''bz' + width: '4' + - dir: output + name: awregion + reset_value: '''bz' + width: '4' + - dir: output + name: awuser + reset_value: '''bz' + width: X + - dir: output + name: wvalid + reset_value: '''bz' + width: '1' + - dir: input + name: wready + reset_value: '''bz' + width: '1' + - dir: output + name: wlast + reset_value: '''bz' + width: '1' + - dir: output + name: wdata + reset_value: '''bz' + width: DATA_WIDTH + - dir: output + name: wstrb + reset_value: '''bz' + width: DATA_WIDTH/8 + - dir: output + name: wid + reset_value: '''bz' + width: X + - dir: output + name: wuser + reset_value: '''bz' + width: X + - dir: input + name: bwvalid + reset_value: '''bz' + width: '1' + - dir: output + name: bwready + reset_value: '''bz' + width: '1' + - dir: input + name: bresp + reset_value: '''bz' + width: '2' + - dir: input + name: bid + reset_value: '''bz' + width: X + - dir: input + name: buser + reset_value: '''bz' + width: X + - dir: output + name: arvalid + reset_value: '''bz' + width: '1' + - dir: input + name: aready + reset_value: '''bz' + width: '1' + - dir: output + name: araddr + reset_value: '''bz' + width: AW_WIDTH + - dir: output + name: arsize + reset_value: '''bz' + width: '3' + - dir: output + name: arburst + reset_value: '''bz' + width: '2' + - dir: output + name: arcache + reset_value: '''bz' + width: '4' + - dir: output + name: arprot + reset_value: '''bz' + width: '3' + - dir: output + name: arid + reset_value: '''bz' + width: X + - dir: output + name: arlen + reset_value: '''bz' + width: LEN + - dir: output + name: arlock + reset_value: '''bz' + width: '1' + - dir: output + name: arqos + reset_value: '''bz' + width: '4' + - dir: output + name: aregion + reset_value: '''bz' + width: '4' + - dir: output + name: aruser + reset_value: '''bz' + width: X + - dir: input + name: rvalid + reset_value: '''bz' + width: '1' + - dir: output + name: rready + reset_value: '''bz' + width: '1' + - dir: input + name: rlast + reset_value: '''bz' + width: '1' + - dir: input + name: rdata + reset_value: '''bz' + width: DATA_WIDTH + - dir: input + name: rid + reset_value: '''bz' + width: X + - dir: input + name: ruser + reset_value: '''bz' + width: X + - dir: input + name: rresp + reset_value: '''bz' + width: '2' + reset: rst + reset_assertion_level: 'False' + transaction_constraints: [] + transaction_vars: + - comment: '' + iscompare: 'False' + isrand: 'False' + name: awvalid + type: bit + unpacked_dimension: '' + - comment: '' + iscompare: 'False' + isrand: 'False' + name: awready + type: bit + unpacked_dimension: '' + - comment: '' + iscompare: 'False' + isrand: 'True' + name: awaddr + type: bit [AW_WIDTH-1:0] + unpacked_dimension: '' + - comment: '' + iscompare: 'False' + isrand: 'True' + name: awsize + type: bit + unpacked_dimension: '' + - comment: '' + iscompare: 'False' + isrand: 'True' + name: awburst + type: bit + unpacked_dimension: '' + - comment: '' + iscompare: 'False' + isrand: 'True' + name: awcache + type: bit + unpacked_dimension: '' + - comment: '' + iscompare: 'False' + isrand: 'True' + name: awprot + type: bit + unpacked_dimension: '' + - comment: '' + iscompare: 'False' + isrand: 'True' + name: awid + type: bit [X-1:0] + unpacked_dimension: '' + - comment: '' + iscompare: 'False' + isrand: 'True' + name: awlen + type: bit [LEN-1:0] + unpacked_dimension: '' + - comment: '' + iscompare: 'False' + isrand: 'True' + name: awlock + type: bit + unpacked_dimension: '' + - comment: '' + iscompare: 'False' + isrand: 'True' + name: awqos + type: bit + unpacked_dimension: '' + - comment: '' + iscompare: 'False' + isrand: 'True' + name: awregion + type: bit + unpacked_dimension: '' + - comment: '' + iscompare: 'False' + isrand: 'True' + name: awuser + type: bit [X-1:0] + unpacked_dimension: '' + - comment: '' + iscompare: 'False' + isrand: 'False' + name: wvalid + type: bit + unpacked_dimension: '' + - comment: '' + iscompare: 'False' + isrand: 'False' + name: wready + type: bit + unpacked_dimension: '' + - comment: '' + iscompare: 'False' + isrand: 'False' + name: wlast + type: bit + unpacked_dimension: '' + - comment: '' + iscompare: 'False' + isrand: 'True' + name: wdata + type: bit [DATA_WIDTH-1:0] + unpacked_dimension: '' + - comment: '' + iscompare: 'False' + isrand: 'True' + name: wstrb + type: bit [DATA_WIDTH/8-1:0] + unpacked_dimension: '' + - comment: '' + iscompare: 'False' + isrand: 'False' + name: wid + type: bit [X-1:0] + unpacked_dimension: '' + - comment: '' + iscompare: 'False' + isrand: 'True' + name: wuser + type: bit [X-1:0] + unpacked_dimension: '' + - comment: '' + iscompare: 'False' + isrand: 'False' + name: bwvalid + type: bit + unpacked_dimension: '' + - comment: '' + iscompare: 'False' + isrand: 'False' + name: bwready + type: bit + unpacked_dimension: '' + - comment: '' + iscompare: 'False' + isrand: 'True' + name: bresp + type: bit + unpacked_dimension: '' + - comment: '' + iscompare: 'False' + isrand: 'False' + name: bid + type: bit [X-1:0] + unpacked_dimension: '' + - comment: '' + iscompare: 'False' + isrand: 'True' + name: buser + type: bit [X-1:0] + unpacked_dimension: '' + - comment: '' + iscompare: 'False' + isrand: 'False' + name: arvalid + type: bit + unpacked_dimension: '' + - comment: '' + iscompare: 'False' + isrand: 'False' + name: aready + type: bit + unpacked_dimension: '' + - comment: '' + iscompare: 'False' + isrand: 'True' + name: araddr + type: bit [AW_WIDTH-1:0] + unpacked_dimension: '' + - comment: '' + iscompare: 'False' + isrand: 'True' + name: arsize + type: bit + unpacked_dimension: '' + - comment: '' + iscompare: 'False' + isrand: 'True' + name: arburst + type: bit + unpacked_dimension: '' + - comment: '' + iscompare: 'False' + isrand: 'True' + name: arcache + type: bit + unpacked_dimension: '' + - comment: '' + iscompare: 'False' + isrand: 'True' + name: arprot + type: bit + unpacked_dimension: '' + - comment: '' + iscompare: 'False' + isrand: 'True' + name: arid + type: bit [X-1:0] + unpacked_dimension: '' + - comment: '' + iscompare: 'False' + isrand: 'True' + name: arlen + type: bit [LEN-1:0] + unpacked_dimension: '' + - comment: '' + iscompare: 'False' + isrand: 'True' + name: arlock + type: bit + unpacked_dimension: '' + - comment: '' + iscompare: 'False' + isrand: 'True' + name: arqos + type: bit + unpacked_dimension: '' + - comment: '' + iscompare: 'False' + isrand: 'True' + name: aregion + type: bit + unpacked_dimension: '' + - comment: '' + iscompare: 'False' + isrand: 'True' + name: aruser + type: bit [X-1:0] + unpacked_dimension: '' + - comment: '' + iscompare: 'False' + isrand: 'False' + name: rvalid + type: bit + unpacked_dimension: '' + - comment: '' + iscompare: 'False' + isrand: 'False' + name: rready + type: bit + unpacked_dimension: '' + - comment: '' + iscompare: 'False' + isrand: 'False' + name: rlast + type: bit + unpacked_dimension: '' + - comment: '' + iscompare: 'False' + isrand: 'True' + name: rdata + type: bit [DATA_WIDTH-1:0] + unpacked_dimension: '' + - comment: '' + iscompare: 'False' + isrand: 'True' + name: rid + type: bit [X-1:0] + unpacked_dimension: '' + - comment: '' + iscompare: 'False' + isrand: 'True' + name: ruser + type: bit [X-1:0] + unpacked_dimension: '' + - comment: '' + iscompare: 'False' + isrand: 'True' + name: rresp + type: bit + unpacked_dimension: '' + use_dpi_link: 'False' diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/verification_ip/interface_packages/spi_s_pkg/.project b/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/verification_ip/interface_packages/spi_s_pkg/.project new file mode 100644 index 00000000..548e937e --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/verification_ip/interface_packages/spi_s_pkg/.project @@ -0,0 +1,30 @@ + + + spi_s_pkg + + + + + + org.python.pydev.PyDevBuilder + + + + + net.sf.sveditor.core.SVProjectBuilder + + + + + + net.sf.sveditor.core.SVNature + org.python.pydev.pythonNature + + + + UVMF_VIP_LIBRARY_HOME + $%7BPARENT-2-PROJECT_LOC%7D + + + + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/verification_ip/interface_packages/spi_s_pkg/.svproject b/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/verification_ip/interface_packages/spi_s_pkg/.svproject new file mode 100644 index 00000000..dbc66e83 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/verification_ip/interface_packages/spi_s_pkg/.svproject @@ -0,0 +1,16 @@ + + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/verification_ip/interface_packages/spi_s_pkg/Makefile b/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/verification_ip/interface_packages/spi_s_pkg/Makefile new file mode 100644 index 00000000..d4c678b7 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/verification_ip/interface_packages/spi_s_pkg/Makefile @@ -0,0 +1,66 @@ +# spi_s interface packages source +# pragma uvmf custom additional begin +# pragma uvmf custom additional end + +spi_s_PKG = \ + +incdir+$(UVMF_VIP_LIBRARY_HOME)/interface_packages/spi_s_pkg \ + -F $(UVMF_VIP_LIBRARY_HOME)/interface_packages/spi_s_pkg/spi_s_filelist_hvl.f + +spi_s_PKG_HDL = \ + +incdir+$(UVMF_VIP_LIBRARY_HOME)/interface_packages/spi_s_pkg \ + -F $(UVMF_VIP_LIBRARY_HOME)/interface_packages/spi_s_pkg/spi_s_filelist_hdl.f + +spi_s_PKG_XRTL = \ + +incdir+$(UVMF_VIP_LIBRARY_HOME)/interface_packages/spi_s_pkg \ + -F $(UVMF_VIP_LIBRARY_HOME)/interface_packages/spi_s_pkg/spi_s_filelist_xrtl.f + +COMP_spi_s_PKG_TGT_0 = q_comp_spi_s_pkg +COMP_spi_s_PKG_TGT_1 = v_comp_spi_s_pkg +COMP_spi_s_PKG_TGT = $(COMP_spi_s_PKG_TGT_$(USE_VELOCE)) + +comp_spi_s_pkg: $(COMP_spi_s_PKG_TGT) + +q_comp_spi_s_pkg: + $(HDL_COMP_CMD) $(spi_s_PKG_HDL) + $(HVL_COMP_CMD) $(spi_s_PKG) + $(HDL_COMP_CMD) $(spi_s_PKG_XRTL) + +v_comp_spi_s_pkg: + $(HVL_COMP_CMD) $(spi_s_PKG_HDL) + $(HVL_COMP_CMD) $(spi_s_PKG) + $(VELANALYZE_CMD) $(spi_s_PKG_HDL) + $(VELANALYZE_HVL_CMD) $(spi_s_PKG) + $(HDL_COMP_CMD) $(spi_s_PKG_XRTL) + +ifeq ($(MTI_VCO_MODE),64) + GCC_COMP_ARCH = -m64 +else + GCC_COMP_ARCH = -m32 +endif + +export spi_s_IF_DPI_SRC ?= $(UVMF_VIP_LIBRARY_HOME)/interface_packages/spi_s_pkg/dpi + +C_FILE_COMPILE_LIST_spi_s_pkg = \ + +O_FILE_COMPILE_LIST_spi_s_pkg = $(notdir $(C_FILE_COMPILE_LIST_spi_s_pkg:.c=.o)) + +GCC_COMP_ARGS_spi_s_pkg += -I$(spi_s_IF_DPI_SRC) \ + -fPIC + +GCC_COMP_ARGS_spi_s_pkg += $(spi_s_IF_GCC_COMP_ARGUMENTS) + +GCC_LINK_ARGS_spi_s_pkg += \ + \ + -o .so + +comp_spi_s_pkg_c_files: + @echo "--------------------------------" + @echo "Compiling Interface C source" + @echo "--------------------------------" + gcc $(GCC_COMP_ARCH) $(GCC_COMP_ARGS_spi_s_pkg) $(C_FILE_COMPILE_LIST_spi_s_pkg) + @echo "--------------------------------" + @echo "Linking Interface C objects into a shared object" + @echo "--------------------------------" + gcc $(GCC_COMP_ARCH) $(GCC_LINK_ARGS_spi_s_pkg) $(O_FILE_COMPILE_LIST_spi_s_pkg) + @echo "--------------------------------" + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/verification_ip/interface_packages/spi_s_pkg/compile.do b/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/verification_ip/interface_packages/spi_s_pkg/compile.do new file mode 100644 index 00000000..303c17b2 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/verification_ip/interface_packages/spi_s_pkg/compile.do @@ -0,0 +1,14 @@ +# Tcl do file for compile of spi_s interface + +# pragma uvmf custom additional begin +# pragma uvmf custom additional end + + +vlog -sv -timescale 1ps/1ps -suppress 2223,2286 +incdir+$env(UVMF_VIP_LIBRARY_HOME)/interface_packages/spi_s_pkg \ + -F $env(UVMF_VIP_LIBRARY_HOME)/interface_packages/spi_s_pkg/spi_s_filelist_hdl.f + +vlog -sv -timescale 1ps/1ps -suppress 2223,2286 +incdir+$env(UVMF_VIP_LIBRARY_HOME)/interface_packages/spi_s_pkg \ + -F $env(UVMF_VIP_LIBRARY_HOME)/interface_packages/spi_s_pkg/spi_s_filelist_hvl.f + +vlog -sv -timescale 1ps/1ps -suppress 2223,2286 +incdir+$env(UVMF_VIP_LIBRARY_HOME)/interface_packages/spi_s_pkg \ + -F $env(UVMF_VIP_LIBRARY_HOME)/interface_packages/spi_s_pkg/spi_s_filelist_xrtl.f \ No newline at end of file diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/verification_ip/interface_packages/spi_s_pkg/spi_s.compile b/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/verification_ip/interface_packages/spi_s_pkg/spi_s.compile new file mode 100644 index 00000000..8b8aa6e2 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/verification_ip/interface_packages/spi_s_pkg/spi_s.compile @@ -0,0 +1,3 @@ +needs: + - spi_s_hvl.compile + - spi_s_hdl.compile diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/verification_ip/interface_packages/spi_s_pkg/spi_s_bfm.vinfo b/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/verification_ip/interface_packages/spi_s_pkg/spi_s_bfm.vinfo new file mode 100644 index 00000000..0f12baaf --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/verification_ip/interface_packages/spi_s_pkg/spi_s_bfm.vinfo @@ -0,0 +1,6 @@ +@use $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg_hdl.vinfo +@use spi_s_pkg_hdl.vinfo ++incdir+@vinfodir +src/spi_s_if.sv +src/spi_s_driver_bfm.sv +src/spi_s_monitor_bfm.sv diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/verification_ip/interface_packages/spi_s_pkg/spi_s_common.compile b/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/verification_ip/interface_packages/spi_s_pkg/spi_s_common.compile new file mode 100644 index 00000000..08bd125f --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/verification_ip/interface_packages/spi_s_pkg/spi_s_common.compile @@ -0,0 +1,7 @@ +needs: + - $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg_hdl.compile +incdir: + - . + - ${uvm_path}/src +src: + - spi_s_pkg_hdl.sv diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/verification_ip/interface_packages/spi_s_pkg/spi_s_filelist_hdl.f b/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/verification_ip/interface_packages/spi_s_pkg/spi_s_filelist_hdl.f new file mode 100644 index 00000000..d7724020 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/verification_ip/interface_packages/spi_s_pkg/spi_s_filelist_hdl.f @@ -0,0 +1 @@ +$UVMF_VIP_LIBRARY_HOME/interface_packages/spi_s_pkg/spi_s_pkg_hdl.sv diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/verification_ip/interface_packages/spi_s_pkg/spi_s_filelist_hvl.f b/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/verification_ip/interface_packages/spi_s_pkg/spi_s_filelist_hvl.f new file mode 100644 index 00000000..cbc4a9ef --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/verification_ip/interface_packages/spi_s_pkg/spi_s_filelist_hvl.f @@ -0,0 +1 @@ +$UVMF_VIP_LIBRARY_HOME/interface_packages/spi_s_pkg/spi_s_pkg.sv \ No newline at end of file diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/verification_ip/interface_packages/spi_s_pkg/spi_s_filelist_xrtl.f b/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/verification_ip/interface_packages/spi_s_pkg/spi_s_filelist_xrtl.f new file mode 100644 index 00000000..175919ef --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/verification_ip/interface_packages/spi_s_pkg/spi_s_filelist_xrtl.f @@ -0,0 +1,3 @@ +$UVMF_VIP_LIBRARY_HOME/interface_packages/spi_s_pkg/src/spi_s_if.sv +$UVMF_VIP_LIBRARY_HOME/interface_packages/spi_s_pkg/src/spi_s_monitor_bfm.sv +$UVMF_VIP_LIBRARY_HOME/interface_packages/spi_s_pkg/src/spi_s_driver_bfm.sv diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/verification_ip/interface_packages/spi_s_pkg/spi_s_hdl.compile b/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/verification_ip/interface_packages/spi_s_pkg/spi_s_hdl.compile new file mode 100644 index 00000000..e63a6a97 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/verification_ip/interface_packages/spi_s_pkg/spi_s_hdl.compile @@ -0,0 +1,9 @@ +needs: + - $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg_hdl.compile + - ./spi_s_common.compile +incdir: + - . +src: + - src/spi_s_if.sv + - src/spi_s_monitor_bfm.sv + - src/spi_s_driver_bfm.sv diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/verification_ip/interface_packages/spi_s_pkg/spi_s_hvl.compile b/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/verification_ip/interface_packages/spi_s_pkg/spi_s_hvl.compile new file mode 100644 index 00000000..569dc399 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/verification_ip/interface_packages/spi_s_pkg/spi_s_hvl.compile @@ -0,0 +1,7 @@ +needs: + - $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg.compile + - ./spi_s_common.compile +incdir: + - . +src: + - spi_s_pkg.sv diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/verification_ip/interface_packages/spi_s_pkg/spi_s_pkg.sv b/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/verification_ip/interface_packages/spi_s_pkg/spi_s_pkg.sv new file mode 100644 index 00000000..90ad9fe1 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/verification_ip/interface_packages/spi_s_pkg/spi_s_pkg.sv @@ -0,0 +1,77 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// PACKAGE: This file defines all of the files contained in the +// interface package that will run on the host simulator. +// +// CONTAINS: +// - +// - +// - + +// - +// - +// - + +// - +// - +// - + +// - +// - +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +package spi_s_pkg; + + import uvm_pkg::*; + import uvmf_base_pkg_hdl::*; + import uvmf_base_pkg::*; + import spi_s_pkg_hdl::*; + + `include "uvm_macros.svh" + + // pragma uvmf custom package_imports_additional begin + // pragma uvmf custom package_imports_additional end + `include "src/spi_s_macros.svh" + + export spi_s_pkg_hdl::*; + + + + // Parameters defined as HVL parameters + + `include "src/spi_s_typedefs.svh" + `include "src/spi_s_transaction.svh" + + `include "src/spi_s_configuration.svh" + `include "src/spi_s_driver.svh" + `include "src/spi_s_monitor.svh" + + `include "src/spi_s_transaction_coverage.svh" + `include "src/spi_s_sequence_base.svh" + `include "src/spi_s_random_sequence.svh" + + `include "src/spi_s_responder_sequence.svh" + `include "src/spi_s2reg_adapter.svh" + + `include "src/spi_s_agent.svh" + + // pragma uvmf custom package_item_additional begin + // UVMF_CHANGE_ME : When adding new interface sequences to the src directory + // be sure to add the sequence file here so that it will be + // compiled as part of the interface package. Be sure to place + // the new sequence after any base sequences of the new sequence. + // pragma uvmf custom package_item_additional end + +endpackage + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/verification_ip/interface_packages/spi_s_pkg/spi_s_pkg.vinfo b/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/verification_ip/interface_packages/spi_s_pkg/spi_s_pkg.vinfo new file mode 100644 index 00000000..b849145a --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/verification_ip/interface_packages/spi_s_pkg/spi_s_pkg.vinfo @@ -0,0 +1,4 @@ +@use $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg.vinfo +@use spi_s_pkg_hdl.vinfo ++incdir+@vinfodir +spi_s_pkg.sv diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/verification_ip/interface_packages/spi_s_pkg/spi_s_pkg_hdl.sv b/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/verification_ip/interface_packages/spi_s_pkg/spi_s_pkg_hdl.sv new file mode 100644 index 00000000..d2773bc0 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/verification_ip/interface_packages/spi_s_pkg/spi_s_pkg_hdl.sv @@ -0,0 +1,38 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// PACKAGE: This file defines all of the files contained in the +// interface package that needs to be compiled and synthesized +// for running on Veloce. +// +// CONTAINS: +// - +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +package spi_s_pkg_hdl; + + import uvmf_base_pkg_hdl::*; + + // pragma uvmf custom package_imports_additional begin + // pragma uvmf custom package_imports_additional end + + // Parameters defined as HDL parameters + + `include "src/spi_s_typedefs_hdl.svh" + `include "src/spi_s_macros.svh" + + // pragma uvmf custom package_item_additional begin + // pragma uvmf custom package_item_additional end + +endpackage + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/verification_ip/interface_packages/spi_s_pkg/spi_s_pkg_hdl.vinfo b/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/verification_ip/interface_packages/spi_s_pkg/spi_s_pkg_hdl.vinfo new file mode 100644 index 00000000..969589c7 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/verification_ip/interface_packages/spi_s_pkg/spi_s_pkg_hdl.vinfo @@ -0,0 +1,2 @@ +@use $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg_hdl.vinfo +spi_s_pkg_hdl.sv diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/verification_ip/interface_packages/spi_s_pkg/spi_s_pkg_sve.F b/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/verification_ip/interface_packages/spi_s_pkg/spi_s_pkg_sve.F new file mode 100644 index 00000000..13508e71 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/verification_ip/interface_packages/spi_s_pkg/spi_s_pkg_sve.F @@ -0,0 +1,10 @@ +// UVM ++incdir+${UVM_HOME}/src +${UVM_HOME}/src/uvm_pkg.sv + +// Common UVMF files +-f ${UVMF_HOME}/common/common_sve.f + ++incdir+. +-f ${UVMF_VIP_LIBRARY_HOME}/interface_packages/spi_s_pkg/spi_s_filelist_hdl.f +-f ${UVMF_VIP_LIBRARY_HOME}/interface_packages/spi_s_pkg/spi_s_filelist_hvl.f diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/verification_ip/interface_packages/spi_s_pkg/src/spi_s2reg_adapter.svh b/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/verification_ip/interface_packages/spi_s_pkg/src/spi_s2reg_adapter.svh new file mode 100644 index 00000000..f6ce4828 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/verification_ip/interface_packages/spi_s_pkg/src/spi_s2reg_adapter.svh @@ -0,0 +1,98 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: +// This file contains the UVM register adapter for the spi_s interface. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class spi_s2reg_adapter extends uvm_reg_adapter; + + `uvm_object_utils( spi_s2reg_adapter ) + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + //-------------------------------------------------------------------- + // new + //-------------------------------------------------------------------- + function new (string name = "spi_s2reg_adapter" ); + super.new(name); + // pragma uvmf custom new begin + // UVMF_CHANGE_ME : Configure the adapter regarding byte enables and provides response. + + // Does the protocol the Agent is modeling support byte enables? + // 0 = NO + // 1 = YES + supports_byte_enable = 0; + + // Does the Agent's Driver provide separate response sequence items? + // i.e. Does the driver call seq_item_port.put() + // and do the sequences call get_response()? + // 0 = NO + // 1 = YES + provides_responses = 0; + // pragma uvmf custom new end + + endfunction: new + + //-------------------------------------------------------------------- + // reg2bus + //-------------------------------------------------------------------- + virtual function uvm_sequence_item reg2bus(const ref uvm_reg_bus_op rw); + + spi_s_transaction trans_h = spi_s_transaction ::type_id::create("trans_h"); + + // pragma uvmf custom reg2bus begin + // UVMF_CHANGE_ME : Fill in the reg2bus adapter mapping registe fields to protocol fields. + + //Adapt the following for your sequence item type + // trans_h.op = (rw.kind == UVM_READ) ? WB_READ : WB_WRITE; + //Copy over address + // trans_h.addr = rw.addr; + //Copy over write data + // trans_h.data = rw.data; + + // pragma uvmf custom reg2bus end + + // Return the adapted transaction + return trans_h; + + endfunction: reg2bus + + //-------------------------------------------------------------------- + // bus2reg + //-------------------------------------------------------------------- + virtual function void bus2reg(uvm_sequence_item bus_item, + ref uvm_reg_bus_op rw); + spi_s_transaction trans_h; + if (!$cast(trans_h, bus_item)) begin + `uvm_fatal("ADAPT","Provided bus_item is not of the correct type") + return; + end + // pragma uvmf custom bus2reg begin + // UVMF_CHANGE_ME : Fill in the bus2reg adapter mapping protocol fields to register fields. + //Adapt the following for your sequence item type + //Copy over instruction type + // rw.kind = (trans_h.op == WB_WRITE) ? UVM_WRITE : UVM_READ; + //Copy over address + // rw.addr = trans_h.addr; + //Copy over read data + // rw.data = trans_h.data; + //Check for errors on the bus and return UVM_NOT_OK if there is an error + // rw.status = UVM_IS_OK; + // pragma uvmf custom bus2reg end + + endfunction: bus2reg + +endclass : spi_s2reg_adapter + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/verification_ip/interface_packages/spi_s_pkg/src/spi_s_agent.svh b/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/verification_ip/interface_packages/spi_s_pkg/src/spi_s_agent.svh new file mode 100644 index 00000000..9a9a24d8 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/verification_ip/interface_packages/spi_s_pkg/src/spi_s_agent.svh @@ -0,0 +1,53 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: Protocol specific agent class definition +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class spi_s_agent extends uvmf_parameterized_agent #( + .CONFIG_T(spi_s_configuration ), + .DRIVER_T(spi_s_driver ), + .MONITOR_T(spi_s_monitor ), + .COVERAGE_T(spi_s_transaction_coverage ), + .TRANS_T(spi_s_transaction ) + ); + + `uvm_component_utils( spi_s_agent ) + +// pragma uvmf custom class_item_additional begin +// pragma uvmf custom class_item_additional end + +// **************************************************************************** +// FUNCTION : new() +// This function is the standard SystemVerilog constructor. +// + function new( string name = "", uvm_component parent = null ); + super.new( name, parent ); + endfunction + +// **************************************************************************** + // FUNCTION: build_phase + virtual function void build_phase(uvm_phase phase); +// pragma uvmf custom build_phase_pre_super begin +// pragma uvmf custom build_phase_pre_super end + super.build_phase(phase); + if (configuration.active_passive == ACTIVE) begin + // Place sequencer handle into configuration object + // so that it may be retrieved from configuration + // rather than using uvm_config_db + configuration.sequencer = this.sequencer; + end + endfunction + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/verification_ip/interface_packages/spi_s_pkg/src/spi_s_configuration.svh b/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/verification_ip/interface_packages/spi_s_pkg/src/spi_s_configuration.svh new file mode 100644 index 00000000..14c2735b --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/verification_ip/interface_packages/spi_s_pkg/src/spi_s_configuration.svh @@ -0,0 +1,179 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This class contains all variables and functions used +// to configure the spi_s agent and its bfm's. It gets the +// bfm's from the uvm_config_db for use by the agent. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class spi_s_configuration extends uvmf_parameterized_agent_configuration_base #( + .DRIVER_BFM_BIND_T(virtual spi_s_driver_bfm ), + .MONITOR_BFM_BIND_T( virtual spi_s_monitor_bfm )); + + `uvm_object_utils( spi_s_configuration ) + + + // Sequencer handle populated by agent + uvm_sequencer #(spi_s_transaction ) sequencer; + + //Constraints for the configuration variables: + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + covergroup spi_s_configuration_cg; + // pragma uvmf custom covergroup begin + option.auto_bin_max=1024; + // pragma uvmf custom covergroup end + endgroup + + //******************************************************************* + //******************************************************************* + // Structure used to pass configuration variables to monitor and driver BFM's. + // Use to_struct function to pack variables into structure. + // Use from_struct function to unpack variables from structure. + // This structure is defined in spi_s_macros.svh + `spi_s_CONFIGURATION_STRUCT + spi_s_configuration_s spi_s_configuration_struct; + //******************************************************************* + // FUNCTION: to_struct() + // This function packs variables into a spi_s_configuration_s + // structure. The function returns the handle to the spi_s_configuration_struct. + // This function is defined in spi_s_macros.svh + `spi_s_CONFIGURATION_TO_STRUCT_FUNCTION + //******************************************************************* + // FUNCTION: from_struct() + // This function unpacks the struct provided as an argument into + // variables of this class. + // This function is defined in spi_s_macros.svh + `spi_s_CONFIGURATION_FROM_STRUCT_FUNCTION + + // **************************************************************************** + // FUNCTION : new() + // This function is the standard SystemVerilog constructor. + // + function new( string name = "" ); + super.new( name ); + // Construct the covergroup for this configuration class + spi_s_configuration_cg = new; + endfunction + + // **************************************************************************** + // FUNCTION: post_randomize() + // This function is automatically called after the randomize() function + // is executed. + // + function void post_randomize(); + super.post_randomize(); + spi_s_configuration_cg.sample(); + endfunction + + // **************************************************************************** + // FUNCTION: initialize + // This function causes the configuration to retrieve + // its virtual interface handle from the uvm_config_db. + // This function also makes itself available to its + // agent through the uvm_config_db. + // + // ARGUMENTS: + // uvmf_active_passive_t activity: + // This argument identifies the simulation level + // as either BLOCK, CHIP, SIMULATION, etc. + // + // AGENT_PATH: + // This argument identifies the path to this + // configurations agent. This configuration + // makes itself available to the agent specified + // by agent_path by placing itself into the + // uvm_config_db. + // + // INTERFACE_NAME: + // This argument identifies the string name of + // this configurations BFM's. This string + // name is used to retrieve the driver and + // monitor BFM from the uvm_config_db. + // + virtual function void initialize(uvmf_active_passive_t activity, + string agent_path, + string interface_name); + + super.initialize( activity, agent_path, interface_name); + // The covergroup is given the same name as the interface + spi_s_configuration_cg.set_inst_name(interface_name); + + // This configuration places itself into the uvm_config_db for the agent, identified by the agent_path variable, to retrieve. + uvm_config_db #( spi_s_configuration + )::set( null ,agent_path,UVMF_AGENT_CONFIG, this ); + + // This configuration also places itself in the config db using the same identifier used by the interface. This allows users to access + // configuration variables and the interface through the bfm api class rather than directly accessing the BFM. This is useful for + // accessingthe BFM when using Veloce + uvm_config_db #( spi_s_configuration + )::set( null ,UVMF_CONFIGURATIONS, interface_name, this ); + + spi_s_configuration_cg.set_inst_name($sformatf("spi_s_configuration_cg_%s",get_full_name())); + +// This code is to aid in debugging parameter mismatches between the BFM and its corresponding agent. +// Enable this debug by setting UVM_VERBOSITY to UVM_DEBUG +// Setting UVM_VERBOSITY to UVM_DEBUG causes all BFM's and all agents to display their parameter settings. +// All of the messages from this feature have a UVM messaging id value of "CFG" +// The transcript or run.log can be parsed to ensure BFM parameter settings match its corresponding agents parameter settings. + `uvm_info("CFG", + $psprintf("The agent at '%s' is using interface named %s has the following parameters: ", agent_path, interface_name, ), + UVM_DEBUG) + + // pragma uvmf custom initialize begin + // This controls whether or not the agent returns a transaction handle in the driver when calling + // item_done() back into the sequencer or not. If set to 1, a transaction is sent back which means + // the sequence on the other end must use the get_response() part of the driver/sequence API. If + // this doesn't occur, there will eventually be response_queue overflow errors during the test. + return_transaction_response = 1'b0; + + // pragma uvmf custom initialize end + + endfunction + + // **************************************************************************** + // TASK: wait_for_reset + // *[Required]* Blocks until reset is released. The wait_for_reset operation is performed + // by a task in the monitor bfm. + virtual task wait_for_reset(); + monitor_bfm.wait_for_reset(); + endtask + + // **************************************************************************** + // TASK: wait_for_num_clocks + // *[Required]* Blocks until specified number of clocks have elapsed. The wait_for_num_clocks + // operation is performed by a task in the monitor bfm. + virtual task wait_for_num_clocks(int clocks); + monitor_bfm.wait_for_num_clocks(clocks); + endtask + + // **************************************************************************** + // FUNCTION : convert2string() + // This function is used to convert variables in this class into a string for log messaging. + // + virtual function string convert2string (); + // pragma uvmf custom convert2string begin + return $sformatf(""); + // pragma uvmf custom convert2string end + endfunction + + // **************************************************************************** + // FUNCTION: get_sequencer + function uvm_sequencer #(spi_s_transaction) get_sequencer(); + return sequencer; + endfunction + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/verification_ip/interface_packages/spi_s_pkg/src/spi_s_driver.svh b/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/verification_ip/interface_packages/spi_s_pkg/src/spi_s_driver.svh new file mode 100644 index 00000000..2ef57307 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/verification_ip/interface_packages/spi_s_pkg/src/spi_s_driver.svh @@ -0,0 +1,91 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This class passes transactions between the sequencer +// and the BFM driver interface. It accesses the driver BFM +// through the bfm handle. This driver +// passes transactions to the driver BFM through the access +// task. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class spi_s_driver extends uvmf_driver_base #( + .CONFIG_T(spi_s_configuration ), + .BFM_BIND_T(virtual spi_s_driver_bfm ), + .REQ(spi_s_transaction ), + .RSP(spi_s_transaction )); + + `uvm_component_utils( spi_s_driver ) +//******************************************************************* +// Macros that define structs located in spi_s_macros.svh +//******************************************************************* +// Initiator macro used by spi_s_driver and spi_s_driver_bfm +// to communicate initiator driven data to spi_s_driver_bfm. +`spi_s_INITIATOR_STRUCT + spi_s_initiator_s spi_s_initiator_struct; +//******************************************************************* +// Responder macro used by spi_s_driver and spi_s_driver_bfm +// to communicate Responder driven data to spi_s_driver_bfm. +`spi_s_RESPONDER_STRUCT + spi_s_responder_s spi_s_responder_struct; + +// pragma uvmf custom class_item_additional begin +// pragma uvmf custom class_item_additional end + +// **************************************************************************** +// This function is the standard SystemVerilog constructor. +// + function new( string name = "", uvm_component parent=null ); + super.new( name, parent ); + endfunction + +// **************************************************************************** +// This function sends configuration object variables to the driver BFM +// using the configuration struct. +// + virtual function void configure(input CONFIG_T cfg); + bfm.configure( cfg.to_struct() ); + endfunction + +// **************************************************************************** +// This function places a handle to this class in the proxy variable in the +// driver BFM. This allows the driver BFM to call tasks and function within this class. +// + virtual function void set_bfm_proxy_handle(); + bfm.proxy = this; endfunction + +// **************************************************************************** +// This task is called by the run_phase in uvmf_driver_base. + virtual task access( inout REQ txn ); +// pragma uvmf custom access begin + if (configuration.initiator_responder==RESPONDER) begin + // Complete current transfer and wait for next transfer + bfm.respond_and_wait_for_next_transfer( + spi_s_initiator_struct, + txn.to_responder_struct() + ); + // Unpack information about initiated transfer received by this responder + txn.from_initiator_struct(spi_s_initiator_struct); + end else begin + // Initiate a transfer and get response + bfm.initiate_and_get_response( + txn.to_initiator_struct(), + spi_s_responder_struct + ); + // Unpack transfer response information received by this initiator + txn.from_responder_struct(spi_s_responder_struct); + end +// pragma uvmf custom access end + endtask + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/verification_ip/interface_packages/spi_s_pkg/src/spi_s_driver_bfm.sv b/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/verification_ip/interface_packages/spi_s_pkg/src/spi_s_driver_bfm.sv new file mode 100644 index 00000000..fe0026ab --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/verification_ip/interface_packages/spi_s_pkg/src/spi_s_driver_bfm.sv @@ -0,0 +1,300 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: +// This interface performs the spi_s signal driving. It is +// accessed by the uvm spi_s driver through a virtual interface +// handle in the spi_s configuration. It drives the singals passed +// in through the port connection named bus of type spi_s_if. +// +// Input signals from the spi_s_if are assigned to an internal input +// signal with a _i suffix. The _i signal should be used for sampling. +// +// The input signal connections are as follows: +// bus.signal -> signal_i +// +// This bfm drives signals with a _o suffix. These signals +// are driven onto signals within spi_s_if based on INITIATOR/RESPONDER and/or +// ARBITRATION/GRANT status. +// +// The output signal connections are as follows: +// signal_o -> bus.signal +// +// +// Interface functions and tasks used by UVM components: +// +// configure: +// This function gets configuration attributes from the +// UVM driver to set any required BFM configuration +// variables such as 'initiator_responder'. +// +// initiate_and_get_response: +// This task is used to perform signaling activity for initiating +// a protocol transfer. The task initiates the transfer, using +// input data from the initiator struct. Then the task captures +// response data, placing the data into the response struct. +// The response struct is returned to the driver class. +// +// respond_and_wait_for_next_transfer: +// This task is used to complete a current transfer as a responder +// and then wait for the initiator to start the next transfer. +// The task uses data in the responder struct to drive protocol +// signals to complete the transfer. The task then waits for +// the next transfer. Once the next transfer begins, data from +// the initiator is placed into the initiator struct and sent +// to the responder sequence for processing to determine +// what data to respond with. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +import uvmf_base_pkg_hdl::*; +import spi_s_pkg_hdl::*; +`include "src/spi_s_macros.svh" + +interface spi_s_driver_bfm + (spi_s_if bus); + // The following pragma and additional ones in-lined further below are for running this BFM on Veloce + // pragma attribute spi_s_driver_bfm partition_interface_xif + +`ifndef XRTL +// This code is to aid in debugging parameter mismatches between the BFM and its corresponding agent. +// Enable this debug by setting UVM_VERBOSITY to UVM_DEBUG +// Setting UVM_VERBOSITY to UVM_DEBUG causes all BFM's and all agents to display their parameter settings. +// All of the messages from this feature have a UVM messaging id value of "CFG" +// The transcript or run.log can be parsed to ensure BFM parameter settings match its corresponding agents parameter settings. +import uvm_pkg::*; +`include "uvm_macros.svh" +initial begin : bfm_vs_agent_parameter_debug + `uvm_info("CFG", + $psprintf("The BFM at '%m' has the following parameters: ", ), + UVM_DEBUG) +end +`endif + + // Config value to determine if this is an initiator or a responder + uvmf_initiator_responder_t initiator_responder; + // Custom configuration variables. + // These are set using the configure function which is called during the UVM connect_phase + + logic sck_i; + logic rst_i; + + // Signal list (all signals are capable of being inputs and outputs for the sake + // of supporting both INITIATOR and RESPONDER mode operation. Expectation is that + // directionality in the config file was from the point-of-view of the INITIATOR + + // INITIATOR mode input signals + tri sclk_i; + reg sclk_o = 'b0; + tri ss_i; + reg ss_o = 'b0; + tri [7:0] mosi_i; + reg [7:0] mosi_o = 'b0; + + // INITIATOR mode output signals + tri [7:0] miso_i; + reg [7:0] miso_o = 'b0; + + // Bi-directional signals + + + assign sck_i = bus.sck; + assign rst_i = bus.rst; + + // These are signals marked as 'input' by the config file, but the signals will be + // driven by this BFM if put into RESPONDER mode (flipping all signal directions around) + assign sclk_i = bus.sclk; + assign bus.sclk = (initiator_responder == RESPONDER) ? sclk_o : 'bz; + assign ss_i = bus.ss; + assign bus.ss = (initiator_responder == RESPONDER) ? ss_o : 'bz; + assign mosi_i = bus.mosi; + assign bus.mosi = (initiator_responder == RESPONDER) ? mosi_o : 'bz; + + + // These are signals marked as 'output' by the config file, but the outputs will + // not be driven by this BFM unless placed in INITIATOR mode. + assign bus.miso = (initiator_responder == INITIATOR) ? miso_o : 'bz; + assign miso_i = bus.miso; + + // Proxy handle to UVM driver + spi_s_pkg::spi_s_driver proxy; + // pragma tbx oneway proxy.my_function_name_in_uvm_driver + + // **************************************************************************** + // **************************************************************************** + // Macros that define structs located in spi_s_macros.svh + // **************************************************************************** + // Struct for passing configuration data from spi_s_driver to this BFM + // **************************************************************************** + `spi_s_CONFIGURATION_STRUCT + // **************************************************************************** + // Structs for INITIATOR and RESPONDER data flow + //******************************************************************* + // Initiator macro used by spi_s_driver and spi_s_driver_bfm + // to communicate initiator driven data to spi_s_driver_bfm. + `spi_s_INITIATOR_STRUCT + spi_s_initiator_s initiator_struct; + // Responder macro used by spi_s_driver and spi_s_driver_bfm + // to communicate Responder driven data to spi_s_driver_bfm. + `spi_s_RESPONDER_STRUCT + spi_s_responder_s responder_struct; + + // **************************************************************************** +// pragma uvmf custom reset_condition_and_response begin + // Always block used to return signals to reset value upon assertion of reset + always @( posedge rst_i ) + begin + // RESPONDER mode output signals + sclk_o <= 'b0; + ss_o <= 'b0; + mosi_o <= 'b0; + // INITIATOR mode output signals + miso_o <= 'b0; + // Bi-directional signals + + end +// pragma uvmf custom reset_condition_and_response end + + // pragma uvmf custom interface_item_additional begin + // pragma uvmf custom interface_item_additional end + + //****************************************************************** + // The configure() function is used to pass agent configuration + // variables to the driver BFM. It is called by the driver within + // the agent at the beginning of the simulation. It may be called + // during the simulation if agent configuration variables are updated + // and the driver BFM needs to be aware of the new configuration + // variables. + // + + function void configure(spi_s_configuration_s spi_s_configuration_arg); // pragma tbx xtf + initiator_responder = spi_s_configuration_arg.initiator_responder; + // pragma uvmf custom configure begin + // pragma uvmf custom configure end + endfunction + +// pragma uvmf custom initiate_and_get_response begin +// **************************************************************************** +// UVMF_CHANGE_ME +// This task is used by an initator. The task first initiates a transfer then +// waits for the responder to complete the transfer. + task initiate_and_get_response( + // This argument passes transaction variables used by an initiator + // to perform the initial part of a protocol transfer. The values + // come from a sequence item created in a sequence. + input spi_s_initiator_s spi_s_initiator_struct, + // This argument is used to send data received from the responder + // back to the sequence item. The sequence item is returned to the sequence. + output spi_s_responder_s spi_s_responder_struct + );// pragma tbx xtf + // + // Members within the spi_s_initiator_struct: + // bit ssel ; + // bit [7:0] mosi ; + // bit [7:0] miso ; + // Members within the spi_s_responder_struct: + // bit ssel ; + // bit [7:0] mosi ; + // bit [7:0] miso ; + initiator_struct = spi_s_initiator_struct; + // + // Reference code; + // How to wait for signal value + // while (control_signal == 1'b1) @(posedge sck_i); + // + // How to assign a responder struct member, named xyz, from a signal. + // All available initiator input and inout signals listed. + // Initiator input signals + // spi_s_responder_struct.xyz = sclk_i; // + // spi_s_responder_struct.xyz = ss_i; // + // spi_s_responder_struct.xyz = mosi_i; // [7:0] + // Initiator inout signals + // How to assign a signal from an initiator struct member named xyz. + // All available initiator output and inout signals listed. + // Notice the _o. Those are storage variables that allow for procedural assignment. + // Initiator output signals + // miso_o <= spi_s_initiator_struct.xyz; // [7:0] + // Initiator inout signals + // Initiate a transfer using the data received. + @(posedge sck_i); + @(posedge sck_i); + // Wait for the responder to complete the transfer then place the responder data into + // spi_s_responder_struct. + @(posedge sck_i); + @(posedge sck_i); + responder_struct = spi_s_responder_struct; + endtask +// pragma uvmf custom initiate_and_get_response end + +// pragma uvmf custom respond_and_wait_for_next_transfer begin +// **************************************************************************** +// The first_transfer variable is used to prevent completing a transfer in the +// first call to this task. For the first call to this task, there is not +// current transfer to complete. +bit first_transfer=1; + +// UVMF_CHANGE_ME +// This task is used by a responder. The task first completes the current +// transfer in progress then waits for the initiator to start the next transfer. + task respond_and_wait_for_next_transfer( + // This argument is used to send data received from the initiator + // back to the sequence item. The sequence determines how to respond. + output spi_s_initiator_s spi_s_initiator_struct, + // This argument passes transaction variables used by a responder + // to complete a protocol transfer. The values come from a sequence item. + input spi_s_responder_s spi_s_responder_struct + );// pragma tbx xtf + // Variables within the spi_s_initiator_struct: + // bit ssel ; + // bit [7:0] mosi ; + // bit [7:0] miso ; + // Variables within the spi_s_responder_struct: + // bit ssel ; + // bit [7:0] mosi ; + // bit [7:0] miso ; + // Reference code; + // How to wait for signal value + // while (control_signal == 1'b1) @(posedge sck_i); + // + // How to assign a responder struct member, named xyz, from a signal. + // All available responder input and inout signals listed. + // Responder input signals + // spi_s_responder_struct.xyz = miso_i; // [7:0] + // Responder inout signals + // How to assign a signal, named xyz, from an initiator struct member. + // All available responder output and inout signals listed. + // Notice the _o. Those are storage variables that allow for procedural assignment. + // Responder output signals + // sclk_o <= spi_s_initiator_struct.xyz; // + // ss_o <= spi_s_initiator_struct.xyz; // + // mosi_o <= spi_s_initiator_struct.xyz; // [7:0] + // Responder inout signals + + @(posedge sck_i); + if (!first_transfer) begin + // Perform transfer response here. + // Reply using data recieved in the spi_s_responder_struct. + @(posedge sck_i); + // Reply using data recieved in the transaction handle. + @(posedge sck_i); + end + // Wait for next transfer then gather info from intiator about the transfer. + // Place the data into the spi_s_initiator_struct. + @(posedge sck_i); + @(posedge sck_i); + first_transfer = 0; + endtask +// pragma uvmf custom respond_and_wait_for_next_transfer end + + +endinterface + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/verification_ip/interface_packages/spi_s_pkg/src/spi_s_if.sv b/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/verification_ip/interface_packages/spi_s_pkg/src/spi_s_if.sv new file mode 100644 index 00000000..47150e10 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/verification_ip/interface_packages/spi_s_pkg/src/spi_s_if.sv @@ -0,0 +1,79 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This interface contains the spi_s interface signals. +// It is instantiated once per spi_s bus. Bus Functional Models, +// BFM's named spi_s_driver_bfm, are used to drive signals on the bus. +// BFM's named spi_s_monitor_bfm are used to monitor signals on the +// bus. This interface signal bundle is passed in the port list of +// the BFM in order to give the BFM access to the signals in this +// interface. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// This template can be used to connect a DUT to these signals +// +// .dut_signal_port(spi_s_bus.sclk), // Agent input +// .dut_signal_port(spi_s_bus.ss), // Agent input +// .dut_signal_port(spi_s_bus.mosi), // Agent input +// .dut_signal_port(spi_s_bus.miso), // Agent output + +import uvmf_base_pkg_hdl::*; +import spi_s_pkg_hdl::*; + +interface spi_s_if + + ( + input logic sck, + input logic rst, + input logic sclk, + input logic ss, + input logic [7:0] mosi, + output logic [7:0] miso + ); + +modport monitor_port + ( + input sck, + input rst, + input sclk, + input ss, + input mosi, + input miso + ); + +modport initiator_port + ( + input sck, + input rst, + input sclk, + input ss, + input mosi, + output miso + ); + +modport responder_port + ( + input sck, + input rst, + output sclk, + output ss, + output mosi, + input miso + ); + + +// pragma uvmf custom interface_item_additional begin +// pragma uvmf custom interface_item_additional end + +endinterface + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/verification_ip/interface_packages/spi_s_pkg/src/spi_s_infact_coverage_strategy.csv b/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/verification_ip/interface_packages/spi_s_pkg/src/spi_s_infact_coverage_strategy.csv new file mode 100644 index 00000000..1c218e14 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/verification_ip/interface_packages/spi_s_pkg/src/spi_s_infact_coverage_strategy.csv @@ -0,0 +1,6 @@ +Global +auto_bin_max, 64 + +Name,Type,Include +rand_fields,coverpoint,=rand *.** + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/verification_ip/interface_packages/spi_s_pkg/src/spi_s_macros.svh b/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/verification_ip/interface_packages/spi_s_pkg/src/spi_s_macros.svh new file mode 100644 index 00000000..cbf12ff6 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/verification_ip/interface_packages/spi_s_pkg/src/spi_s_macros.svh @@ -0,0 +1,139 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This file contains macros used with the spi_s package. +// These macros include packed struct definitions. These structs are +// used to pass data between classes, hvl, and BFM's, hdl. Use of +// structs are more efficient and simpler to modify. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// + +// **************************************************************************** +// When changing the contents of this struct, be sure to update the to_struct +// and from_struct methods defined in the macros below that are used in +// the spi_s_configuration class. +// + `define spi_s_CONFIGURATION_STRUCT \ +typedef struct packed { \ + uvmf_active_passive_t active_passive; \ + uvmf_initiator_responder_t initiator_responder; \ + } spi_s_configuration_s; + + `define spi_s_CONFIGURATION_TO_STRUCT_FUNCTION \ + virtual function spi_s_configuration_s to_struct();\ + spi_s_configuration_struct = \ + {\ + this.active_passive,\ + this.initiator_responder\ + };\ + return ( spi_s_configuration_struct );\ + endfunction + + `define spi_s_CONFIGURATION_FROM_STRUCT_FUNCTION \ + virtual function void from_struct(spi_s_configuration_s spi_s_configuration_struct);\ + {\ + this.active_passive,\ + this.initiator_responder \ + } = spi_s_configuration_struct;\ + endfunction + +// **************************************************************************** +// When changing the contents of this struct, be sure to update the to_monitor_struct +// and from_monitor_struct methods of the spi_s_transaction class. +// + `define spi_s_MONITOR_STRUCT typedef struct packed { \ + bit ssel ; \ + bit [7:0] mosi ; \ + bit [7:0] miso ; \ + } spi_s_monitor_s; + + `define spi_s_TO_MONITOR_STRUCT_FUNCTION \ + virtual function spi_s_monitor_s to_monitor_struct();\ + spi_s_monitor_struct = \ + { \ + this.ssel , \ + this.mosi , \ + this.miso \ + };\ + return ( spi_s_monitor_struct);\ + endfunction\ + + `define spi_s_FROM_MONITOR_STRUCT_FUNCTION \ + virtual function void from_monitor_struct(spi_s_monitor_s spi_s_monitor_struct);\ + {\ + this.ssel , \ + this.mosi , \ + this.miso \ + } = spi_s_monitor_struct;\ + endfunction + +// **************************************************************************** +// When changing the contents of this struct, be sure to update the to_initiator_struct +// and from_initiator_struct methods of the spi_s_transaction class. +// Also update the comments in the driver BFM. +// + `define spi_s_INITIATOR_STRUCT typedef struct packed { \ + bit ssel ; \ + bit [7:0] mosi ; \ + bit [7:0] miso ; \ + } spi_s_initiator_s; + + `define spi_s_TO_INITIATOR_STRUCT_FUNCTION \ + virtual function spi_s_initiator_s to_initiator_struct();\ + spi_s_initiator_struct = \ + {\ + this.ssel , \ + this.mosi , \ + this.miso \ + };\ + return ( spi_s_initiator_struct);\ + endfunction + + `define spi_s_FROM_INITIATOR_STRUCT_FUNCTION \ + virtual function void from_initiator_struct(spi_s_initiator_s spi_s_initiator_struct);\ + {\ + this.ssel , \ + this.mosi , \ + this.miso \ + } = spi_s_initiator_struct;\ + endfunction + +// **************************************************************************** +// When changing the contents of this struct, be sure to update the to_responder_struct +// and from_responder_struct methods of the spi_s_transaction class. +// Also update the comments in the driver BFM. +// + `define spi_s_RESPONDER_STRUCT typedef struct packed { \ + bit ssel ; \ + bit [7:0] mosi ; \ + bit [7:0] miso ; \ + } spi_s_responder_s; + + `define spi_s_TO_RESPONDER_STRUCT_FUNCTION \ + virtual function spi_s_responder_s to_responder_struct();\ + spi_s_responder_struct = \ + {\ + this.ssel , \ + this.mosi , \ + this.miso \ + };\ + return ( spi_s_responder_struct);\ + endfunction + + `define spi_s_FROM_RESPONDER_STRUCT_FUNCTION \ + virtual function void from_responder_struct(spi_s_responder_s spi_s_responder_struct);\ + {\ + this.ssel , \ + this.mosi , \ + this.miso \ + } = spi_s_responder_struct;\ + endfunction +// pragma uvmf custom additional begin +// pragma uvmf custom additional end diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/verification_ip/interface_packages/spi_s_pkg/src/spi_s_monitor.svh b/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/verification_ip/interface_packages/spi_s_pkg/src/spi_s_monitor.svh new file mode 100644 index 00000000..31289dd6 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/verification_ip/interface_packages/spi_s_pkg/src/spi_s_monitor.svh @@ -0,0 +1,87 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This class receives spi_s transactions observed by the +// spi_s monitor BFM and broadcasts them through the analysis port +// on the agent. It accesses the monitor BFM through the monitor +// task. This UVM component captures transactions +// for viewing in the waveform viewer if the +// enable_transaction_viewing flag is set in the configuration. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class spi_s_monitor extends uvmf_monitor_base #( + .CONFIG_T(spi_s_configuration ), + .BFM_BIND_T(virtual spi_s_monitor_bfm ), + .TRANS_T(spi_s_transaction )); + + `uvm_component_utils( spi_s_monitor ) + +// Structure used to pass data from monitor BFM to monitor class in agent. +// Use to_monitor_struct function to pack transaction variables into structure. +// Use from_monitor_struct function to unpack transaction variables from structure. +`spi_s_MONITOR_STRUCT + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + +// **************************************************************************** +// This function is the standard SystemVerilog constructor. +// + function new( string name = "", uvm_component parent = null ); + super.new( name, parent ); + endfunction + +// **************************************************************************** +// This function sends configuration object variables to the monitor BFM +// using the configuration struct. +// + virtual function void configure(input CONFIG_T cfg); + bfm.configure( cfg.to_struct() ); + + endfunction + +// **************************************************************************** +// This function places a handle to this class in the proxy variable in the +// monitor BFM. This allows the monitor BFM to call the notify_transaction +// function within this class. +// + virtual function void set_bfm_proxy_handle(); + bfm.proxy = this; endfunction + +// *************************************************************************** + virtual task run_phase(uvm_phase phase); + // Start monitor BFM thread and don't call super.run() in order to + // override the default monitor proxy 'pull' behavior with the more + // emulation-friendly BFM 'push' approach using the notify_transaction + // function below + bfm.start_monitoring(); + endtask + +// ************************************************************************** + +// This function is called by the monitor BFM. It receives data observed by the +// monitor BFM. Data is passed using the spi_s_monitor_struct. + virtual function void notify_transaction(input spi_s_monitor_s spi_s_monitor_struct); + + + trans = new("trans"); + trans.from_monitor_struct(spi_s_monitor_struct); + trans.start_time = time_stamp; + trans.end_time = $time; + time_stamp = trans.end_time; + + analyze(trans); + endfunction + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/verification_ip/interface_packages/spi_s_pkg/src/spi_s_monitor_bfm.sv b/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/verification_ip/interface_packages/spi_s_pkg/src/spi_s_monitor_bfm.sv new file mode 100644 index 00000000..68438155 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/verification_ip/interface_packages/spi_s_pkg/src/spi_s_monitor_bfm.sv @@ -0,0 +1,185 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This interface performs the spi_s signal monitoring. +// It is accessed by the uvm spi_s monitor through a virtual +// interface handle in the spi_s configuration. It monitors the +// signals passed in through the port connection named bus of +// type spi_s_if. +// +// Input signals from the spi_s_if are assigned to an internal input +// signal with a _i suffix. The _i signal should be used for sampling. +// +// The input signal connections are as follows: +// bus.signal -> signal_i +// +// Interface functions and tasks used by UVM components: +// monitor(inout TRANS_T txn); +// This task receives the transaction, txn, from the +// UVM monitor and then populates variables in txn +// from values observed on bus activity. This task +// blocks until an operation on the spi_s bus is complete. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +import uvmf_base_pkg_hdl::*; +import spi_s_pkg_hdl::*; +`include "src/spi_s_macros.svh" + + +interface spi_s_monitor_bfm + ( spi_s_if bus ); + // The pragma below and additional ones in-lined further down are for running this BFM on Veloce + // pragma attribute spi_s_monitor_bfm partition_interface_xif + +`ifndef XRTL +// This code is to aid in debugging parameter mismatches between the BFM and its corresponding agent. +// Enable this debug by setting UVM_VERBOSITY to UVM_DEBUG +// Setting UVM_VERBOSITY to UVM_DEBUG causes all BFM's and all agents to display their parameter settings. +// All of the messages from this feature have a UVM messaging id value of "CFG" +// The transcript or run.log can be parsed to ensure BFM parameter settings match its corresponding agents parameter settings. +import uvm_pkg::*; +`include "uvm_macros.svh" +initial begin : bfm_vs_agent_parameter_debug + `uvm_info("CFG", + $psprintf("The BFM at '%m' has the following parameters: ", ), + UVM_DEBUG) +end +`endif + + + // Structure used to pass transaction data from monitor BFM to monitor class in agent. +`spi_s_MONITOR_STRUCT + spi_s_monitor_s spi_s_monitor_struct; + + // Structure used to pass configuration data from monitor class to monitor BFM. + `spi_s_CONFIGURATION_STRUCT + + + // Config value to determine if this is an initiator or a responder + uvmf_initiator_responder_t initiator_responder; + // Custom configuration variables. + // These are set using the configure function which is called during the UVM connect_phase + + logic sck_i; + logic rst_i; + tri sclk_i; + tri ss_i; + tri [7:0] mosi_i; + tri [7:0] miso_i; + assign sck_i = bus.sck; + assign rst_i = bus.rst; + assign sclk_i = bus.sclk; + assign ss_i = bus.ss; + assign mosi_i = bus.mosi; + assign miso_i = bus.miso; + + // Proxy handle to UVM monitor + spi_s_pkg::spi_s_monitor proxy; + // pragma tbx oneway proxy.notify_transaction + + // pragma uvmf custom interface_item_additional begin + // pragma uvmf custom interface_item_additional end + + //****************************************************************** + task wait_for_reset();// pragma tbx xtf + @(posedge sck_i) ; + do_wait_for_reset(); + endtask + + // **************************************************************************** + task do_wait_for_reset(); + // pragma uvmf custom reset_condition begin + wait ( rst_i === 0 ) ; + @(posedge sck_i) ; + // pragma uvmf custom reset_condition end + endtask + + //****************************************************************** + + task wait_for_num_clocks(input int unsigned count); // pragma tbx xtf + @(posedge sck_i); + + repeat (count-1) @(posedge sck_i); + endtask + + //****************************************************************** + event go; + function void start_monitoring();// pragma tbx xtf + -> go; + endfunction + + // **************************************************************************** + initial begin + @go; + forever begin + @(posedge sck_i); + do_monitor( spi_s_monitor_struct ); + + + proxy.notify_transaction( spi_s_monitor_struct ); + + end + end + + //****************************************************************** + // The configure() function is used to pass agent configuration + // variables to the monitor BFM. It is called by the monitor within + // the agent at the beginning of the simulation. It may be called + // during the simulation if agent configuration variables are updated + // and the monitor BFM needs to be aware of the new configuration + // variables. + // + function void configure(spi_s_configuration_s spi_s_configuration_arg); // pragma tbx xtf + initiator_responder = spi_s_configuration_arg.initiator_responder; + // pragma uvmf custom configure begin + // pragma uvmf custom configure end + endfunction + + + // **************************************************************************** + + task do_monitor(output spi_s_monitor_s spi_s_monitor_struct); + // + // Available struct members: + // // spi_s_monitor_struct.ssel + // // spi_s_monitor_struct.mosi + // // spi_s_monitor_struct.miso + // // + // Reference code; + // How to wait for signal value + // while (control_signal === 1'b1) @(posedge sck_i); + // + // How to assign a struct member, named xyz, from a signal. + // All available input signals listed. + // spi_s_monitor_struct.xyz = sclk_i; // + // spi_s_monitor_struct.xyz = ss_i; // + // spi_s_monitor_struct.xyz = mosi_i; // [7:0] + // spi_s_monitor_struct.xyz = miso_i; // [7:0] + // pragma uvmf custom do_monitor begin + // UVMF_CHANGE_ME : Implement protocol monitoring. The commented reference code + // below are examples of how to capture signal values and assign them to + // structure members. All available input signals are listed. The 'while' + // code example shows how to wait for a synchronous flow control signal. This + // task should return when a complete transfer has been observed. Once this task is + // exited with captured values, it is then called again to wait for and observe + // the next transfer. One clock cycle is consumed between calls to do_monitor. + @(posedge sck_i); + @(posedge sck_i); + @(posedge sck_i); + @(posedge sck_i); + // pragma uvmf custom do_monitor end + endtask + + +endinterface + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/verification_ip/interface_packages/spi_s_pkg/src/spi_s_random_sequence.svh b/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/verification_ip/interface_packages/spi_s_pkg/src/spi_s_random_sequence.svh new file mode 100644 index 00000000..799ca4ff --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/verification_ip/interface_packages/spi_s_pkg/src/spi_s_random_sequence.svh @@ -0,0 +1,53 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: +// This sequences randomizes the spi_s transaction and sends it +// to the UVM driver. +// +// This sequence constructs and randomizes a spi_s_transaction. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class spi_s_random_sequence + extends spi_s_sequence_base ; + + `uvm_object_utils( spi_s_random_sequence ) + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + //***************************************************************** + function new(string name = ""); + super.new(name); + endfunction: new + + // **************************************************************************** + // TASK : body() + // This task is automatically executed when this sequence is started using the + // start(sequencerHandle) task. + // + task body(); + + // Construct the transaction + req=spi_s_transaction::type_id::create("req"); + start_item(req); + // Randomize the transaction + if(!req.randomize()) `uvm_fatal("SEQ", "spi_s_random_sequence::body()-spi_s_transaction randomization failed") + // Send the transaction to the spi_s_driver_bfm via the sequencer and spi_s_driver. + finish_item(req); + `uvm_info("SEQ", {"Response:",req.convert2string()},UVM_MEDIUM) + + endtask + +endclass: spi_s_random_sequence + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/verification_ip/interface_packages/spi_s_pkg/src/spi_s_responder_sequence.svh b/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/verification_ip/interface_packages/spi_s_pkg/src/spi_s_responder_sequence.svh new file mode 100644 index 00000000..f7a9964e --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/verification_ip/interface_packages/spi_s_pkg/src/spi_s_responder_sequence.svh @@ -0,0 +1,49 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This class can be used to provide stimulus when an interface +// has been configured to run in a responder mode. It +// will never finish by default, always going back to the driver +// and driver BFM for the next transaction with which to respond. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class spi_s_responder_sequence + extends spi_s_sequence_base ; + + `uvm_object_utils( spi_s_responder_sequence ) + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + function new(string name = "spi_s_responder_sequence"); + super.new(name); + endfunction + + task body(); + req=spi_s_transaction::type_id::create("req"); + forever begin + start_item(req); + finish_item(req); + // pragma uvmf custom body begin + // UVMF_CHANGE_ME : Do something here with the resulting req item. The + // finish_item() call above will block until the req transaction is ready + // to be handled by the responder sequence. + // If this was an item that required a response, the expectation is + // that the response should be populated within this transaction now. + `uvm_info("SEQ",$sformatf("Processed txn: %s",req.convert2string()),UVM_HIGH) + // pragma uvmf custom body end + end + endtask + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/verification_ip/interface_packages/spi_s_pkg/src/spi_s_sequence_base.svh b/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/verification_ip/interface_packages/spi_s_pkg/src/spi_s_sequence_base.svh new file mode 100644 index 00000000..fca6ae59 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/verification_ip/interface_packages/spi_s_pkg/src/spi_s_sequence_base.svh @@ -0,0 +1,96 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: +// This file contains the class used as the base class for all sequences +// for this interface. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class spi_s_sequence_base extends uvmf_sequence_base #( + .REQ(spi_s_transaction ), + .RSP(spi_s_transaction )); + + `uvm_object_utils( spi_s_sequence_base ) + + // variables + typedef spi_s_transaction spi_s_transaction_req_t; + spi_s_transaction_req_t req; + typedef spi_s_transaction spi_s_transaction_rsp_t; + spi_s_transaction_rsp_t rsp; + + // Event for identifying when a response was received from the sequencer + event new_rsp; + + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + // **************************************************************************** + // TASK : get_responses() + // This task recursively gets sequence item responses from the sequencer. + // + virtual task get_responses(); + fork + begin + // Block until new rsp available + get_response(rsp); + // New rsp received. Indicate to sequence using event. + ->new_rsp; + // Display the received response transaction + `uvm_info("SEQ", {"New response transaction:",rsp.convert2string()}, UVM_MEDIUM) + end + join_none + endtask + + // **************************************************************************** + // TASK : pre_body() + // This task is called automatically when start is called with call_pre_post set to 1 (default). + // By calling get_responses() within pre_body() any derived sequences are automatically + // processing response transactions. Only un-comment this call to get_responses() if you + // have configured the interface driver to utilize the response transaction path by setting + // the configuration variable "return_transaction_response" to 1. Otherwise it is possible + // to impact runtime performance and memory utilization. + // + virtual task pre_body(); + // pragma uvmf custom pre_body begin +// get_responses(); + // pragma uvmf custom pre_body end + endtask + + // **************************************************************************** + // TASK : body() + // This task is called automatically when start is called. This sequence sends + // a req sequence item to the sequencer identified as an argument in the call + // to start. + // + virtual task body(); + // pragma uvmf custom body begin + start_item(req); + finish_item(req); + // pragma uvmf custom body end + endtask + + // **************************************************************************** + // FUNCTION : new() + // This function is the standard SystemVerilog constructor. + // + function new( string name =""); + super.new( name ); + // pragma uvmf custom new begin + req = spi_s_transaction_req_t::type_id::create("req"); + rsp = spi_s_transaction_rsp_t::type_id::create("rsp"); + // pragma uvmf custom new end + endfunction + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/verification_ip/interface_packages/spi_s_pkg/src/spi_s_transaction.svh b/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/verification_ip/interface_packages/spi_s_pkg/src/spi_s_transaction.svh new file mode 100644 index 00000000..7edd633c --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/verification_ip/interface_packages/spi_s_pkg/src/spi_s_transaction.svh @@ -0,0 +1,190 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This class defines the variables required for an spi_s +// transaction. Class variables to be displayed in waveform transaction +// viewing are added to the transaction viewing stream in the add_to_wave +// function. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class spi_s_transaction extends uvmf_transaction_base; + + `uvm_object_utils( spi_s_transaction ) + + bit ssel ; + bit [7:0] mosi ; + rand bit [7:0] miso ; + + //Constraints for the transaction variables: + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + //******************************************************************* + //******************************************************************* + // Macros that define structs and associated functions are + // located in spi_s_macros.svh + + //******************************************************************* + // Monitor macro used by spi_s_monitor and spi_s_monitor_bfm + // This struct is defined in spi_s_macros.svh + `spi_s_MONITOR_STRUCT + spi_s_monitor_s spi_s_monitor_struct; + //******************************************************************* + // FUNCTION: to_monitor_struct() + // This function packs transaction variables into a spi_s_monitor_s + // structure. The function returns the handle to the spi_s_monitor_struct. + // This function is defined in spi_s_macros.svh + `spi_s_TO_MONITOR_STRUCT_FUNCTION + //******************************************************************* + // FUNCTION: from_monitor_struct() + // This function unpacks the struct provided as an argument into transaction + // variables of this class. + // This function is defined in spi_s_macros.svh + `spi_s_FROM_MONITOR_STRUCT_FUNCTION + + //******************************************************************* + // Initiator macro used by spi_s_driver and spi_s_driver_bfm + // to communicate initiator driven data to spi_s_driver_bfm. + // This struct is defined in spi_s_macros.svh + `spi_s_INITIATOR_STRUCT + spi_s_initiator_s spi_s_initiator_struct; + //******************************************************************* + // FUNCTION: to_initiator_struct() + // This function packs transaction variables into a spi_s_initiator_s + // structure. The function returns the handle to the spi_s_initiator_struct. + // This function is defined in spi_s_macros.svh + `spi_s_TO_INITIATOR_STRUCT_FUNCTION + //******************************************************************* + // FUNCTION: from_initiator_struct() + // This function unpacks the struct provided as an argument into transaction + // variables of this class. + // This function is defined in spi_s_macros.svh + `spi_s_FROM_INITIATOR_STRUCT_FUNCTION + + //******************************************************************* + // Responder macro used by spi_s_driver and spi_s_driver_bfm + // to communicate Responder driven data to spi_s_driver_bfm. + // This struct is defined in spi_s_macros.svh + `spi_s_RESPONDER_STRUCT + spi_s_responder_s spi_s_responder_struct; + //******************************************************************* + // FUNCTION: to_responder_struct() + // This function packs transaction variables into a spi_s_responder_s + // structure. The function returns the handle to the spi_s_responder_struct. + // This function is defined in spi_s_macros.svh + `spi_s_TO_RESPONDER_STRUCT_FUNCTION + //******************************************************************* + // FUNCTION: from_responder_struct() + // This function unpacks the struct provided as an argument into transaction + // variables of this class. + // This function is defined in spi_s_macros.svh + `spi_s_FROM_RESPONDER_STRUCT_FUNCTION + // **************************************************************************** + // FUNCTION : new() + // This function is the standard SystemVerilog constructor. + // + function new( string name = "" ); + super.new( name ); + endfunction + + // **************************************************************************** + // FUNCTION: convert2string() + // This function converts all variables in this class to a single string for + // logfile reporting. + // + virtual function string convert2string(); + // pragma uvmf custom convert2string begin + // UVMF_CHANGE_ME : Customize format if desired. + return $sformatf("ssel:0x%x mosi:0x%x miso:0x%x ",ssel,mosi,miso); + // pragma uvmf custom convert2string end + endfunction + + //******************************************************************* + // FUNCTION: do_print() + // This function is automatically called when the .print() function + // is called on this class. + // + virtual function void do_print(uvm_printer printer); + // pragma uvmf custom do_print begin + // UVMF_CHANGE_ME : Current contents of do_print allows for the use of UVM 1.1d, 1.2 or P1800.2. + // Update based on your own printing preference according to your preferred UVM version + $display(convert2string()); + // pragma uvmf custom do_print end + endfunction + + //******************************************************************* + // FUNCTION: do_compare() + // This function is automatically called when the .compare() function + // is called on this class. + // + virtual function bit do_compare (uvm_object rhs, uvm_comparer comparer); + spi_s_transaction RHS; + if (!$cast(RHS,rhs)) return 0; + // pragma uvmf custom do_compare begin + // UVMF_CHANGE_ME : Eliminate comparison of variables not to be used for compare + return (super.do_compare(rhs,comparer) + &&(this.ssel == RHS.ssel) + &&(this.mosi == RHS.mosi) + &&(this.miso == RHS.miso) + ); + // pragma uvmf custom do_compare end + endfunction + + //******************************************************************* + // FUNCTION: do_copy() + // This function is automatically called when the .copy() function + // is called on this class. + // + virtual function void do_copy (uvm_object rhs); + spi_s_transaction RHS; + assert($cast(RHS,rhs)); + // pragma uvmf custom do_copy begin + super.do_copy(rhs); + this.ssel = RHS.ssel; + this.mosi = RHS.mosi; + this.miso = RHS.miso; + // pragma uvmf custom do_copy end + endfunction + + // **************************************************************************** + // FUNCTION: add_to_wave() + // This function is used to display variables in this class in the waveform + // viewer. The start_time and end_time variables must be set before this + // function is called. If the start_time and end_time variables are not set + // the transaction will be hidden at 0ns on the waveform display. + // + virtual function void add_to_wave(int transaction_viewing_stream_h); + `ifdef QUESTA + if (transaction_view_h == 0) begin + transaction_view_h = $begin_transaction(transaction_viewing_stream_h,"spi_s_transaction",start_time); + end + super.add_to_wave(transaction_view_h); + // pragma uvmf custom add_to_wave begin + // UVMF_CHANGE_ME : Color can be applied to transaction entries based on content, example below + // case() + // 1 : $add_color(transaction_view_h,"red"); + // default : $add_color(transaction_view_h,"grey"); + // endcase + // UVMF_CHANGE_ME : Eliminate transaction variables not wanted in transaction viewing in the waveform viewer + $add_attribute(transaction_view_h,ssel,"ssel"); + $add_attribute(transaction_view_h,mosi,"mosi"); + $add_attribute(transaction_view_h,miso,"miso"); + // pragma uvmf custom add_to_wave end + $end_transaction(transaction_view_h,end_time); + $free_transaction(transaction_view_h); + `endif // QUESTA + endfunction + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/verification_ip/interface_packages/spi_s_pkg/src/spi_s_transaction_coverage.svh b/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/verification_ip/interface_packages/spi_s_pkg/src/spi_s_transaction_coverage.svh new file mode 100644 index 00000000..cbde0275 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/verification_ip/interface_packages/spi_s_pkg/src/spi_s_transaction_coverage.svh @@ -0,0 +1,72 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This class records spi_s transaction information using +// a covergroup named spi_s_transaction_cg. An instance of this +// coverage component is instantiated in the uvmf_parameterized_agent +// if the has_coverage flag is set. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class spi_s_transaction_coverage extends uvm_subscriber #(.T(spi_s_transaction )); + + `uvm_component_utils( spi_s_transaction_coverage ) + + T coverage_trans; + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + // **************************************************************************** + covergroup spi_s_transaction_cg; + // pragma uvmf custom covergroup begin + // UVMF_CHANGE_ME : Add coverage bins, crosses, exclusions, etc. according to coverage needs. + option.auto_bin_max=1024; + option.per_instance=1; + ssel: coverpoint coverage_trans.ssel; + mosi: coverpoint coverage_trans.mosi; + miso: coverpoint coverage_trans.miso; + // pragma uvmf custom covergroup end + endgroup + + // **************************************************************************** + // FUNCTION : new() + // This function is the standard SystemVerilog constructor. + // + function new(string name="", uvm_component parent=null); + super.new(name,parent); + spi_s_transaction_cg=new; + `uvm_warning("COVERAGE_MODEL_REVIEW", "A covergroup has been constructed which may need review because of either generation or re-generation with merging. Please note that transaction variables added as a result of re-generation and merging are not automatically added to the covergroup. Remove this warning after the covergroup has been reviewed.") + endfunction + + // **************************************************************************** + // FUNCTION : build_phase() + // This function is the standard UVM build_phase. + // + function void build_phase(uvm_phase phase); + spi_s_transaction_cg.set_inst_name($sformatf("spi_s_transaction_cg_%s",get_full_name())); + endfunction + + // **************************************************************************** + // FUNCTION: write (T t) + // This function is automatically executed when a transaction arrives on the + // analysis_export. It copies values from the variables in the transaction + // to local variables used to collect functional coverage. + // + virtual function void write (T t); + `uvm_info("COV","Received transaction",UVM_HIGH); + coverage_trans = t; + spi_s_transaction_cg.sample(); + endfunction + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/verification_ip/interface_packages/spi_s_pkg/src/spi_s_typedefs.svh b/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/verification_ip/interface_packages/spi_s_pkg/src/spi_s_typedefs.svh new file mode 100644 index 00000000..43d85640 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/verification_ip/interface_packages/spi_s_pkg/src/spi_s_typedefs.svh @@ -0,0 +1,20 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: +// This file contains defines and typedefs to be compiled for use in +// the simulation running on the host server when using Veloce. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// + + +// pragma uvmf custom additional begin +// pragma uvmf custom additional end + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/verification_ip/interface_packages/spi_s_pkg/src/spi_s_typedefs_hdl.svh b/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/verification_ip/interface_packages/spi_s_pkg/src/spi_s_typedefs_hdl.svh new file mode 100644 index 00000000..74738c8c --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/verification_ip/interface_packages/spi_s_pkg/src/spi_s_typedefs_hdl.svh @@ -0,0 +1,21 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: +// This file contains defines and typedefs to be compiled for use in +// the simulation running on the emulator when using Veloce. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// + + + +// pragma uvmf custom additional begin +// pragma uvmf custom additional end + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/verification_ip/interface_packages/spi_s_pkg/yaml/spi_s_interface.yaml b/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/verification_ip/interface_packages/spi_s_pkg/yaml/spi_s_interface.yaml new file mode 100644 index 00000000..b00c98ca --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/verification_ip/interface_packages/spi_s_pkg/yaml/spi_s_interface.yaml @@ -0,0 +1,53 @@ +uvmf: + interfaces: + spi_s: + clock: sck + config_constraints: [] + config_vars: [] + existing_library_component: 'True' + gen_inbound_streaming_driver: 'False' + hdl_pkg_parameters: [] + hdl_typedefs: [] + hvl_pkg_parameters: [] + hvl_typedefs: [] + parameters: [] + ports: + - dir: input + name: sclk + reset_value: '''b0' + width: '1' + - dir: input + name: ss + reset_value: '''b0' + width: '1' + - dir: input + name: mosi + reset_value: '''b0' + width: '8' + - dir: output + name: miso + reset_value: '''b0' + width: '8' + reset: rst + reset_assertion_level: 'True' + transaction_constraints: [] + transaction_vars: + - comment: '' + iscompare: 'True' + isrand: 'False' + name: ssel + type: bit + unpacked_dimension: '' + - comment: '' + iscompare: 'True' + isrand: 'False' + name: mosi + type: bit [7:0] + unpacked_dimension: '' + - comment: '' + iscompare: 'True' + isrand: 'True' + name: miso + type: bit [7:0] + unpacked_dimension: '' + use_dpi_link: 'False' diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_2/block2_env.yaml b/UVM_Framework/UVMF_2022.3/challenge_3/block_2/block2_env.yaml new file mode 100644 index 00000000..1ae94aaa --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_2/block2_env.yaml @@ -0,0 +1,44 @@ +uvmf: + benches: + "block_2" : + top_env: "block_2" + clock_half_period: "5ns" + reset_assertion_level: "True" + reset_duration: "200ns" + active_passive: + - bfm_name: "spi_master" + value: "ACTIVE" + - bfm_name: "wb_slave" + value: "PASSIVE" + environments: + "block_2" : + agents : + - name: "spi_master" + type: "spi_m" + initiator_responder: "INITIATOR" + - name: "wb_slave" + type: "wb_s" + initiator_responder: "RESPONDER" + analysis_components : + - name: "block_2_pred" + type: "block_2_predictor" + - name: "block_2_sb" + type: "block_2_scoreboard" + analysis_ports : + - name: "spi_master_ap" + trans_type: "spi_m_transaction" + connected_to: "spi_master.monitored_ap" + - name: "wb_slave_ap" + trans_type: "wb_s_transaction" + connected_to: "wb_slave.monitored_ap" + tlm_connections: + - driver: "spi_master.monitored_ap" + receiver: "block_2_pred.spi_ae" + - driver: "wb_slave.monitored_ap" + receiver: "block_2_sb.wb_ae" + - driver: "block_2_pred.pre_to_sco_ap" + receiver: "block_2_sb.sco_from_pre_ae" + config_vars : + - name: "has_scoreboard" + type : "bit" + isrand : "False" diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_2/block2_util.yaml b/UVM_Framework/UVMF_2022.3/challenge_3/block_2/block2_util.yaml new file mode 100644 index 00000000..ebf62361 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_2/block2_util.yaml @@ -0,0 +1,18 @@ +uvmf: + util_components: + block_2_predictor: + analysis_exports: + - name: spi_ae + type: 'spi_m_transaction' + analysis_ports: + - name: pre_to_sco_ap + type: 'wb_s_transaction' + existing_library_component: 'True' + type: predictor + block_2_scoreboard: + analysis_exports: + - name: wb_ae + type: 'wb_s_transaction' + - name: sco_from_pre_ae + type: 'wb_s_transaction' + type: scoreboard diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_2/block_2.csh b/UVM_Framework/UVMF_2022.3/challenge_3/block_2/block_2.csh new file mode 100644 index 00000000..cdb2ebf2 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_2/block_2.csh @@ -0,0 +1,7 @@ +# Setting the path for making "make cli" command works fine. + +setenv UVMF_HOME /hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3/ + +# This is the command to generate you block_2_level bench + +python ../../../UVMF_2022.3/scripts/yaml2uvmf.py ../intf/spi_m_intf.yaml ../intf/wb_s_intf.yaml ../block_2/block2_env.yaml ../block_2/block2_util.yaml diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/project_benches/block_2/.project b/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/project_benches/block_2/.project new file mode 100644 index 00000000..e070225f --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/project_benches/block_2/.project @@ -0,0 +1,37 @@ + + + block_2 + + + + + + org.python.pydev.PyDevBuilder + + + + + net.sf.sveditor.core.SVProjectBuilder + + + + + + net.sf.sveditor.core.SVNature + org.python.pydev.pythonNature + + + + verification_ip + 2 + UVMF_VIP_LIBRARY_HOME + + + + + UVMF_VIP_LIBRARY_HOME + $%7BPARENT-2-PROJECT_LOC%7D/verification_ip + + + + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/project_benches/block_2/.svproject b/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/project_benches/block_2/.svproject new file mode 100644 index 00000000..b5a7f95a --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/project_benches/block_2/.svproject @@ -0,0 +1,16 @@ + + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/project_benches/block_2/block_2_sve.F b/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/project_benches/block_2/block_2_sve.F new file mode 100644 index 00000000..83f3e49e --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/project_benches/block_2/block_2_sve.F @@ -0,0 +1,28 @@ + +// UVM ++incdir+${UVM_HOME}/src +${UVM_HOME}/src/uvm_pkg.sv + +// Common UVMF files +-f ${UVMF_HOME}/common/common_sve.f + +// BFM Files +-F ${UVMF_VIP_LIBRARY_HOME}/interface_packages/spi_m_pkg/spi_m_pkg_sve.F +-F ${UVMF_VIP_LIBRARY_HOME}/interface_packages/wb_s_pkg/wb_s_pkg_sve.F + +// Environment Files +-F ${UVMF_VIP_LIBRARY_HOME}/environment_packages/block_2_env_pkg/block_2_env_pkg_sve.F + +// Bench Files ++incdir+./tb/tests +./tb/tests/block_2_tests_pkg.sv + ++incdir+./tb/sequences +./tb/sequences/block_2_sequences_pkg.sv + ++incdir+./tb/parameters +./tb/parameters/block_2_parameters_pkg.sv + +./tb/testbench/hdl_top.sv +./tb/testbench/hvl_top.sv + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/project_benches/block_2/docs/interfaces.csv b/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/project_benches/block_2/docs/interfaces.csv new file mode 100644 index 00000000..de1a17a2 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/project_benches/block_2/docs/interfaces.csv @@ -0,0 +1,14 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// + +, +Interface Description, Interface Type, Interface Transaction, Interface Name, +spi_master, spi_m_driver_bfm spi_m_monitor_bfm, spi_m_transaction, spi_m_pkg_spi_master_BFM, +wb_slave, wb_s_driver_bfm wb_s_monitor_bfm, wb_s_transaction, wb_s_pkg_wb_slave_BFM, + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/project_benches/block_2/rtl/dut.compile b/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/project_benches/block_2/rtl/dut.compile new file mode 100644 index 00000000..9b0008fc --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/project_benches/block_2/rtl/dut.compile @@ -0,0 +1,6 @@ + +# pragma uvmf custom dut_compile_info begin +src: + - ./vhdl/vhdl_dut.vhd + - ./verilog/verilog_dut.v +# pragma uvmf custom dut_compile_info end diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/project_benches/block_2/rtl/verilog/verilog_dut.v b/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/project_benches/block_2/rtl/verilog/verilog_dut.v new file mode 100644 index 00000000..96198441 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/project_benches/block_2/rtl/verilog/verilog_dut.v @@ -0,0 +1,21 @@ +module verilog_dut(clk, rst, in_signal, out_signal); + +input clk; +input rst; +input in_signal; +output out_signal; + +reg out_signal_o; + +always @(posedge clk) begin + if (rst) begin + out_signal_o <= 0; + end + else begin + out_signal_o <= ~in_signal; + end + end + +assign out_signal = out_signal_o; + +endmodule diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/project_benches/block_2/rtl/verilog/verilog_dut.vinfo b/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/project_benches/block_2/rtl/verilog/verilog_dut.vinfo new file mode 100644 index 00000000..87e95f36 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/project_benches/block_2/rtl/verilog/verilog_dut.vinfo @@ -0,0 +1 @@ +verilog_dut.v diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/project_benches/block_2/rtl/vhdl/vhdl_dut.vhd b/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/project_benches/block_2/rtl/vhdl/vhdl_dut.vhd new file mode 100644 index 00000000..904aa37d --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/project_benches/block_2/rtl/vhdl/vhdl_dut.vhd @@ -0,0 +1,21 @@ +library ieee; +use ieee.std_logic_1164.all ; + +entity vhdl_dut is + port ( clk : in std_logic ; + rst : in std_logic ; + in_signal : in std_logic ; + out_signal :out std_logic + ); +end vhdl_dut; + +architecture rtl of vhdl_dut is + begin + P1: process + variable out_signal_o : std_logic; + begin + wait until clk'event and clk = '1'; + out_signal_o := in_signal; + out_signal <= out_signal_o; + end process; + end rtl; diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/project_benches/block_2/sim/Makefile b/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/project_benches/block_2/sim/Makefile new file mode 100644 index 00000000..4bea4673 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/project_benches/block_2/sim/Makefile @@ -0,0 +1,199 @@ + +# +#---------------------------------------------------------------------- +# +# DESCRIPTION: This makefile includes the shared makefile and contains +# bench level make targets. +# +#---------------------------------------------------------------------- + + +# pragma uvmf custom additional begin +# pragma uvmf custom additional end + +# ********************************************************************************************* +# UVMF library directory: +# This variable points to the UVMF release where uvmf_base_pkg directory resides. +# This variable points to release code that is not user modified. +# This variable allows for UVMF release directories to reside independent of project related verification IP and project bench directories. +# This code below looks "upward" for directory starting with UVMF_* and returns first match for use with the release examples. +UVMF_HOME ?= ___PLEASE_SET_AN_ENVIRONMENT_VARIABLE_NAMED_UVMF_HOME_TO_POINT_TO_THE_UVMF_INSTALLATION___ + +# pragma uvmf custom exports begin +# +# Project(s) specific verification IP library: +# Directory where reusable verification packages for interfaces, environments, utilities, etc. reside. +# This variable allows for your verification IP to reside independent of project bench and UVMF release directories. +# For examples deployed with UVMF this will be $(UVMF_HOME)//verification_ip +export UVMF_VIP_LIBRARY_HOME ?= $(PWD)/../../../verification_ip +# +# Project specific bench: +# Directory where bench specific code is located. +# This variable allows for project_benches to reside independent of verification IP and UVMF release directories. +# For examples deployed with UVMF this will be $(UVMF_HOME)//project_benches/ +export UVMF_PROJECT_DIR ?= $(PWD)/.. +# +# +# pragma uvmf custom exports end +# ********************************************************************************************* + +## Check PATH for required vinfo scripts +PVAL := $(shell command -v make_filelist.py 2> /dev/null) +ifndef PVAL + MFLIST = $(UVMF_HOME)/scripts/make_filelist.py +else + MFLIST = make_filelist.py +endif + + +# Set test case specific Variables +TEST_NAME ?= test_top + +TEST_SEED ?= random +UVM_CLI_ARGS = + +# Usage of Veloce, etc. to be input by the user (subject to defaults) +USE_VELOCE ?= 0 + +# Usage of vinfo flow for generating file list +USE_VINFO ?= 0 + +# Usage of Veloce and Questa profilers +USE_VELOCE_PROFILER ?= 0 +USE_QUESTA_PROFILER ?= 0 + + +# Set project Variables +TEST_PLAN_NAME = block_2_TestPlan +REPORTING_DO_FILE = block_2_reports_script + + +# Include makefile that includes targets for UVM_VIP_Library packages +include $(UVMF_HOME)/scripts/Makefile + + + + +# Include all requisite interface package targets for this bench +include $(UVMF_VIP_LIBRARY_HOME)/interface_packages/spi_m_pkg/Makefile +include $(UVMF_VIP_LIBRARY_HOME)/interface_packages/wb_s_pkg/Makefile + +# Include all requisite environment package targets for this bench +include $(UVMF_VIP_LIBRARY_HOME)/environment_packages/block_2_env_pkg/Makefile + + + +# Add to default compile/load/run arguments +VCOM_ARGS += + +# Note: vsim-3009 error can be eliminated by adding -timescale 1ps/1ps to VLOG_ARGS + +VLOG_ARGS += $(UVM_DISABLE_FILE_LINE_CMD) + +VELANALYZE_ARGS += +VELANALYZE_HVL_ARGS += + +BATCH_VOPT_ARGS += +DEBUG_VOPT_ARGS += +EXTRA_VOPT_TOPS += +COMMON_VSIM_ARGS += +COMMON_VSIM_ARGS += + + +BATCH_VSIM_ARGS += #-uvmcontrol=none +DEBUG_VSIM_ARGS += +EXTRA_VSIM_TOPS += + +# pragma uvmf custom additional_args begin +# pragma uvmf custom additional_args end + + +# Project bench package source +block_2_PARAMETERS_PKG ?=\ +$(UVMF_PROJECT_DIR)/tb/parameters/block_2_parameters_pkg.sv + + +block_2_SEQUENCES_PKG ?=\ +$(UVMF_PROJECT_DIR)/tb/sequences/block_2_sequences_pkg.sv + + +block_2_TEST_PKG ?=\ +$(UVMF_PROJECT_DIR)/tb/tests/block_2_tests_pkg.sv + +# pragma uvmf custom dut_files begin +# UVMF_CHANGE_ME : Reference Verilog DUT source. +block_2_VERILOG_DUT ?=\ +$(UVMF_PROJECT_DIR)/rtl/verilog/verilog_dut.v + +# UVMF_CHANGE_ME : Reference VHDL DUT source. +block_2_VHDL_DUT ?=\ +$(UVMF_PROJECT_DIR)/rtl/vhdl/vhdl_dut.vhd +# pragma uvmf custom dut_files end + + +# Project bench package targets +COMP_block_2_PARAMETERS_PKG_TGT_0 = q_comp_block_2_parameters_pkg +COMP_block_2_PARAMETERS_PKG_TGT_1 = v_comp_block_2_parameters_pkg +COMP_block_2_PARAMETERS_PKG_TGT = $(COMP_block_2_PARAMETERS_PKG_TGT_$(USE_VELOCE)) + +comp_block_2_parameters_pkg: $(COMP_block_2_PARAMETERS_PKG_TGT) + +q_comp_block_2_parameters_pkg: + $(HVL_COMP_CMD) +incdir+$(UVMF_PROJECT_DIR)/tb/parameters $(block_2_PARAMETERS_PKG) + +v_comp_block_2_parameters_pkg: q_comp_block_2_parameters_pkg + $(HDL_COMP_CMD) +incdir+$(UVMF_PROJECT_DIR)/tb/parameters $(block_2_PARAMETERS_PKG) + + +comp_block_2_sequence_pkg: + $(HVL_COMP_CMD) +incdir+$(UVMF_PROJECT_DIR)/tb/sequences $(block_2_SEQUENCES_PKG) + +comp_block_2_tests_pkg: + $(HVL_COMP_CMD) +incdir+$(UVMF_PROJECT_DIR)/tb/tests $(block_2_TEST_PKG) + +# pragma uvmf custom dut_compile_make_target begin +# UVMF_CHANGE_ME : Add make target to compile your verilog dut here +comp_block_2_verilog_dut: + echo "Compile your verilog DUT here" + $(HDL_COMP_CMD) $(block_2_VERILOG_DUT) + +# UVMF_CHANGE_ME : Add make target to compile your vhdl dut here +comp_block_2_vhdl_dut: + echo "Compile your vhdl DUT here" + $(HDL_COMP_CMD_VHDL) $(block_2_VHDL_DUT) + +# UVMF_CHANGE_ME : Add make target to compile your dut here +comp_block_2_dut: comp_block_2_vhdl_dut comp_block_2_verilog_dut +# pragma uvmf custom dut_compile_make_target end + + +BUILD_TGT_0 = make_build +BUILD_TGT_1 = vinfo_build +BUILD_TGT = $(BUILD_TGT_$(USE_VINFO)) + + +comp_hvl : comp_hvl_core + + +comp_hvl_core : \ + comp_spi_m_pkg comp_wb_s_pkg \ + comp_block_2_env_pkg \ + comp_block_2_parameters_pkg comp_block_2_sequence_pkg comp_block_2_tests_pkg + +comp_uvmf_core : comp_uvm_pkg comp_uvmf_base_pkg + +make_build: comp_block_2_dut comp_uvmf_core comp_hvl comp_test_bench + +hvl_build: q_comp_spi_m_pkg q_comp_wb_s_pkg comp_block_2_env_pkg comp_block_2_sequence_pkg comp_block_2_tests_pkg hvl_comp_testbench link optimize + + +vinfo_build: comp_block_2_vhdl_dut build_hdl_vinfo build_hvl_vinfo $(VINFO_TGT) + + $(HDL_COMP_CMD) -F hdl.vf + $(VEL_COMP) + +build: $(BUILD_TGT) + +# pragma uvmf custom additional_targets begin +# pragma uvmf custom additional_targets end + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/project_benches/block_2/sim/bcr_testlist b/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/project_benches/block_2/sim/bcr_testlist new file mode 100644 index 00000000..5c61ad72 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/project_benches/block_2/sim/bcr_testlist @@ -0,0 +1,19 @@ + + + +# Test list for use by RMDB file +# File syntax is +# TB_INFO { } { } +# TB ## All subsequent tests will run on this bench until a different "TB" line is seen +# TEST <1st_seed> ... +# If not enough seeds are provided then random seeds are used to pad +# If no repeat count is given, default is 1 +# pragma uvmf custom tb_info begin +TB_INFO block_2 { } { } +# pragma uvmf custom tb_info end +TB block_2 +# pragma uvmf custom regression_suite begin +TEST test_top 3 +# pragma uvmf custom regression_suite end + + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/project_benches/block_2/sim/bcr_testlist.yaml b/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/project_benches/block_2/sim/bcr_testlist.yaml new file mode 100644 index 00000000..1a81a584 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/project_benches/block_2/sim/bcr_testlist.yaml @@ -0,0 +1,44 @@ + + + +# YAML test list for use by RMDB file +# File syntax is +# uvmf_testlist: +# testbenches: +# - name: +# extra_build_options: +# extra_run_options: +# - name: +# ... +# - name: +# tests: +# - name: +# uvm_testname: (defaults to test_name) +# testbench: (defaults to last tb name seen) +# repeat: (defaults to 1) +# seeds: [,,...,] (defaults to all random) +# extra_test_options: +# - name: +# ... +# - name: +# include: +# - (relative path reference is to the including YAML file) +# - +# ... +# - + +uvmf_testlist: + testbenches: +# pragma uvmf custom tb_info begin + - name: block_2 + extra_build_options: "" + extra_run_options: "" +# pragma uvmf custom tb_info end + tests: + - testbench: block_2 +# pragma uvmf custom regression_suite begin + - name: test_top + repeat: 3 +# pragma uvmf custom regression_suite end + + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/project_benches/block_2/sim/compile.do b/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/project_benches/block_2/sim/compile.do new file mode 100644 index 00000000..74950ae6 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/project_benches/block_2/sim/compile.do @@ -0,0 +1,71 @@ + + +################################################################## +## ENVIRONMENT VARIABLES +################################################################## +quietly set ::env(UVMF_VIP_LIBRARY_HOME) ../../../verification_ip +quietly set ::env(UVMF_PROJECT_DIR) .. + +## Using VRM means that the build is occuring several more directories deeper underneath +## the sim directory, need to prepend some more '..' +if {[info exists ::env(VRM_BUILD)]} { + quietly set ::env(UVMF_VIP_LIBRARY_HOME) "../../../../../$::env(UVMF_VIP_LIBRARY_HOME)" + quietly set ::env(UVMF_PROJECT_DIR) "../../../../../$::env(UVMF_PROJECT_DIR)" +} +quietly set ::env(UVMF_VIP_LIBRARY_HOME) [file normalize $::env(UVMF_VIP_LIBRARY_HOME)] +quietly set ::env(UVMF_PROJECT_DIR) [file normalize $::env(UVMF_PROJECT_DIR)] +quietly echo "UVMF_VIP_LIBRARY_HOME = $::env(UVMF_VIP_LIBRARY_HOME)" +quietly echo "UVMF_PROJECT_DIR = $::env(UVMF_PROJECT_DIR)" + + +################################################################### +## HOUSEKEEPING : DELETE FILES THAT WILL BE REGENERATED +################################################################### +file delete -force *~ *.ucdb vsim.dbg *.vstf *.log work *.mem *.transcript.txt certe_dump.xml *.wlf covhtmlreport VRMDATA +file delete -force design.bin qwave.db dpiheader.h visualizer*.ses +file delete -force veloce.med veloce.wave veloce.map tbxbindings.h edsenv velrunopts.ini +file delete -force sv_connect.* + +################################################################### +## COMPILE DUT SOURCE CODE +################################################################### +vlib work +# pragma uvmf custom dut_compile_dofile_target begin +# UVMF_CHANGE_ME : Add commands to compile your dut here, replacing the default examples +vlog -sv -timescale 1ps/1ps -suppress 2223,2286 $env(UVMF_PROJECT_DIR)/rtl/verilog/verilog_dut.v +vcom $env(UVMF_PROJECT_DIR)/rtl/vhdl/vhdl_dut.vhd +# pragma uvmf custom dut_compile_dofile_target end + +################################################################### +## COMPILE UVMF BASE/COMMON SOURCE CODE +################################################################### +vlog -sv -timescale 1ps/1ps -suppress 2223 -suppress 2286 +incdir+$env(UVMF_HOME)/uvmf_base_pkg -F $env(UVMF_HOME)/uvmf_base_pkg/uvmf_base_pkg_filelist_hdl.f +vlog -sv -timescale 1ps/1ps -suppress 2223 -suppress 2286 +incdir+$env(UVMF_HOME)/uvmf_base_pkg -F $env(UVMF_HOME)/uvmf_base_pkg/uvmf_base_pkg_filelist_hvl.f + + +################################################################### +## UVMF INTERFACE COMPILATION +################################################################### +do $env(UVMF_VIP_LIBRARY_HOME)/interface_packages/spi_m_pkg/compile.do +do $env(UVMF_VIP_LIBRARY_HOME)/interface_packages/wb_s_pkg/compile.do + +################################################################### +## UVMF ENVIRONMENT COMPILATION +################################################################### +do $env(UVMF_VIP_LIBRARY_HOME)/environment_packages/block_2_env_pkg/compile.do + +################################################################### +## UVMF BENCHES COMPILATION +################################################################### +vlog -sv -timescale 1ps/1ps -suppress 2223 -suppress 2286 +incdir+$env(UVMF_PROJECT_DIR)/tb/parameters $env(UVMF_PROJECT_DIR)/tb/parameters/block_2_parameters_pkg.sv +vlog -sv -timescale 1ps/1ps -suppress 2223 -suppress 2286 +incdir+$env(UVMF_PROJECT_DIR)/tb/sequences $env(UVMF_PROJECT_DIR)/tb/sequences/block_2_sequences_pkg.sv +vlog -sv -timescale 1ps/1ps -suppress 2223 -suppress 2286 +incdir+$env(UVMF_PROJECT_DIR)/tb/tests $env(UVMF_PROJECT_DIR)/tb/tests/block_2_tests_pkg.sv + +vlog -sv -timescale 1ps/1ps -suppress 2223 -suppress 2286 +incdir+$env(UVMF_PROJECT_DIR)/tb/testbench -F $env(UVMF_PROJECT_DIR)/tb/testbench/top_filelist_hdl.f +vlog -sv -timescale 1ps/1ps -suppress 2223 -suppress 2286 +incdir+$env(UVMF_PROJECT_DIR)/tb/testbench -F $env(UVMF_PROJECT_DIR)/tb/testbench/top_filelist_hvl.f + +################################################################### +## OPTIMIZATION +################################################################### +vopt hvl_top hdl_top -o optimized_batch_top_tb +vopt +acc hvl_top hdl_top -o optimized_debug_top_tb diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/project_benches/block_2/sim/hdl.compile b/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/project_benches/block_2/sim/hdl.compile new file mode 100644 index 00000000..8e7bd41a --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/project_benches/block_2/sim/hdl.compile @@ -0,0 +1,5 @@ +needs: +# pragma uvmf custom dut_compile_info begin + - ../rtl/dut.compile +# pragma uvmf custom dut_compile_info end + - ../tb/testbench/hdl_top.compile diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/project_benches/block_2/sim/hdl.vinfo b/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/project_benches/block_2/sim/hdl.vinfo new file mode 100644 index 00000000..da27ec77 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/project_benches/block_2/sim/hdl.vinfo @@ -0,0 +1 @@ +@use $UVMF_PROJECT_DIR/tb/testbench/hdl_top.vinfo diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/project_benches/block_2/sim/hvl.compile b/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/project_benches/block_2/sim/hvl.compile new file mode 100644 index 00000000..ce952549 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/project_benches/block_2/sim/hvl.compile @@ -0,0 +1,2 @@ +needs: + - ../tb/testbench/hvl_top.compile diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/project_benches/block_2/sim/hvl.vinfo b/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/project_benches/block_2/sim/hvl.vinfo new file mode 100644 index 00000000..d22eff33 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/project_benches/block_2/sim/hvl.vinfo @@ -0,0 +1 @@ +@use $UVMF_PROJECT_DIR/tb/testbench/hvl_top.vinfo diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/project_benches/block_2/sim/run.do b/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/project_benches/block_2/sim/run.do new file mode 100644 index 00000000..101ddc48 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/project_benches/block_2/sim/run.do @@ -0,0 +1,21 @@ + + +quietly set svLibs "" +quietly set extra_vsim_args "" + +################################################################### +## Check for additional vsim arguments passed using env var $UVMF_EXTRA_VSIM_ARGS +################################################################### +if {[info exists ::env(UVMF_EXTRA_VSIM_ARGS)]} { + echo "Adding more args to vsim command" + quietly set extra_vsim_args $::env(UVMF_EXTRA_VSIM_ARGS) +} + +################################################################## +## Launch Questa : generate vsim command line and execute +################################################################## +# pragma uvmf custom dut_run_dofile_target begin +# UVMF_CHANGE_ME : Change the UVM_TESTNAME plusarg to run a different test +quietly set cmd [format "vsim -i -sv_seed random +UVM_TESTNAME=test_top +UVM_VERBOSITY=UVM_HIGH -permit_unmatched_virtual_intf +notimingchecks -suppress 8887 %s %s -uvmcontrol=all -msgmode both -classdebug -assertdebug +uvm_set_config_int=*,enable_transaction_viewing,1 -do { set NoQuitOnFinish 1; onbreak {resume}; run 0; do wave.do; set PrefSource(OpenOnBreak) 0; radix hex showbase; } optimized_debug_top_tb" $svLibs $extra_vsim_args] +# pragma uvmf custom dut_run_dofile_target end +eval $cmd diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/project_benches/block_2/sim/tbx.config b/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/project_benches/block_2/sim/tbx.config new file mode 100644 index 00000000..eec58168 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/project_benches/block_2/sim/tbx.config @@ -0,0 +1,10 @@ + + + + + +comp -questa +velsyn -D1S +rtlc -allow_4ST + + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/project_benches/block_2/sim/testlist b/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/project_benches/block_2/sim/testlist new file mode 100644 index 00000000..f92fb15b --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/project_benches/block_2/sim/testlist @@ -0,0 +1,20 @@ + + + + +# Test list for use by RMDB file +# File syntax is +# TB_INFO { } { } +# TB ## All subsequent tests will run on this bench until a different "TB" line is seen +# TEST <1st_seed> ... +# If not enough seeds are provided then random seeds are used to pad +# If no repeat count is given, default is 1 +# pragma uvmf custom tb_info begin +TB_INFO block_2 { UVMF_VIP_LIBRARY_HOME=../../../../../../../../verification_ip UVMF_PROJECT_DIR=../../../../../../../block_2 } { } +# pragma uvmf custom tb_info end +TB block_2 +# pragma uvmf custom regression_suite begin +TEST test_top 3 +# pragma uvmf custom regression_suite end + + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/project_benches/block_2/sim/testlist.yaml b/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/project_benches/block_2/sim/testlist.yaml new file mode 100644 index 00000000..f6cabad6 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/project_benches/block_2/sim/testlist.yaml @@ -0,0 +1,44 @@ + + + +# YAML test list for use by RMDB file +# File syntax is +# uvmf_testlist: +# testbenches: +# - name: +# extra_build_options: +# extra_run_options: +# - name: +# ... +# - name: +# tests: +# - name: +# uvm_testname: (defaults to test_name) +# testbench: (defaults to last tb name seen) +# repeat: (defaults to 1) +# seeds: [,,...,] (defaults to all random) +# extra_test_options: +# - name: +# ... +# - name: +# include: +# - (relative path reference is to the including YAML file) +# - +# ... +# - + +uvmf_testlist: + testbenches: +# pragma uvmf custom tb_info begin + - name: block_2 + extra_build_options: "UVMF_VIP_LIBRARY_HOME=../../../../../../../../verification_ip UVMF_PROJECT_DIR=../../../../../../../block_2" + extra_run_options: "" +# pragma uvmf custom tb_info end + tests: + - testbench: block_2 +# pragma uvmf custom regression_suite begin + - name: test_top + repeat: 3 +# pragma uvmf custom regression_suite end + + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/project_benches/block_2/sim/top.compile b/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/project_benches/block_2/sim/top.compile new file mode 100644 index 00000000..efd51c07 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/project_benches/block_2/sim/top.compile @@ -0,0 +1,3 @@ +needs: + - hvl.compile + - hdl.compile diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/project_benches/block_2/sim/veloce.config b/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/project_benches/block_2/sim/veloce.config new file mode 100644 index 00000000..d0975155 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/project_benches/block_2/sim/veloce.config @@ -0,0 +1,26 @@ + + + + + +# pragma uvmf custom additional begin +comp -num_boards 1 +comp -hvl questa +# Please choose the correct emulator type code for +# comp -platform command or else velcomp will fail +# Available types are: +# - Veloce2 Quattro: D2 +# - Veloce2 Maximus: D2M +# - Veloce Strato TiL, Ti, and Mi: Strato +# - Veloce Strato M and Strato T: StratoM +# - comp -platform +comp -platform Strato + +rtlc -enable_tbx_pragma_checks +rtlc -allow_4ST +rtlc -allow_MDR +rtlc -compile_display +rtlc -xwave_siglist xwaves.sigs +# pragma uvmf custom additional end + + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/project_benches/block_2/sim/viswave.do b/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/project_benches/block_2/sim/viswave.do new file mode 100644 index 00000000..e6989769 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/project_benches/block_2/sim/viswave.do @@ -0,0 +1,22 @@ + + +onerror resume +wave tags F0 +wave update off + +wave spacer -backgroundcolor Salmon { spi_master } +wave add uvm_test_top.environment.spi_master.spi_master_monitor.txn_stream -radix string -tag F0 +wave group spi_master_bus +wave add -group spi_master_bus hdl_top.spi_master_bus.* -radix hexadecimal -tag F0 +wave group spi_master_bus -collapse +wave insertion [expr [wave index insertpoint] +1] +wave spacer -backgroundcolor Salmon { wb_slave } +wave add uvm_test_top.environment.wb_slave.wb_slave_monitor.txn_stream -radix string -tag F0 +wave group wb_slave_bus +wave add -group wb_slave_bus hdl_top.wb_slave_bus.* -radix hexadecimal -tag F0 +wave group wb_slave_bus -collapse +wave insertion [expr [wave index insertpoint] +1] + +wave update on +WaveSetStreamView + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/project_benches/block_2/sim/wave.do b/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/project_benches/block_2/sim/wave.do new file mode 100644 index 00000000..128637c8 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/project_benches/block_2/sim/wave.do @@ -0,0 +1,30 @@ + + +onerror {resume} +quietly WaveActivateNextPane {} 0 + +add wave -noupdate -divider spi_master +add wave -noupdate /uvm_root/uvm_test_top/environment/spi_master/spi_master_monitor/txn_stream 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!s108 1672041001.000000 +!s107 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+S1 +R0 +R10 +8/hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/project_benches/block_2/sim/../tb/testbench/hvl_top.sv +F/hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/project_benches/block_2/sim/../tb/testbench/hvl_top.sv +R27 +R24 +r1 +!s85 0 +31 +R33 +!s107 /hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/project_benches/block_2/sim/../tb/testbench/hvl_top.sv| +!s90 -sv|-suppress|2223|-suppress|2286|+define+UVM_REPORT_DISABLE_FILE_LINE|+define+UVM_REPORT_DISABLE_FILE_LINE|+incdir+/questa_mvc_src/sv|+incdir+/hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/project_benches/block_2/sim/../tb/testbench|-F|/hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/project_benches/block_2/sim/../tb/testbench/top_filelist_hvl.f| +!i113 0 +R25 +!s92 -suppress 2223 -suppress 2286 -sv +define+UVM_REPORT_DISABLE_FILE_LINE +define+UVM_REPORT_DISABLE_FILE_LINE +incdir+/questa_mvc_src/sv +incdir+/hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/project_benches/block_2/sim/../tb/testbench -L mtiAvm -L mtiRnm -L mtiOvm -L mtiUvm -L mtiUPF -L infact +R26 +Toptimized_batch_top_tb +!s110 1672041003 +V2Kbdk55cGb^MlO_MJKUBR3 +Z36 04 7 4 work hvl_top fast 0 +Z37 04 7 4 work hdl_top fast 0 +o +R26 +noptimized_batch_top_tb +Z38 OE;O;10.6c;65 +R0 +Toptimized_debug_top_tb +!s110 1672041006 +VE13D8>=I<6AXDRL2 +R36 +R37 +o+acc +R26 +noptimized_debug_top_tb +R38 +Yspi_m_driver_bfm +R1 +R3 +R5 +DXx4 work 24 spi_m_driver_bfm_sv_unit 0 22 FMfb6JO]keVijVni0Vn^f2 +R2 +R4 +R6 +R35 +r1 +!s85 0 +31 +!i10b 1 +!s100 EhV6BeBCVCm^9jWBi_@ZZ2 +IOnBFhNOW1oD33ZGBbN=O]2 +!s105 spi_m_driver_bfm_sv_unit +S1 +R0 +Z39 w1672040981 +Z40 8/hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/project_benches/block_2/sim/../../../verification_ip/interface_packages/spi_m_pkg/src/spi_m_driver_bfm.sv +Z41 F/hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/project_benches/block_2/sim/../../../verification_ip/interface_packages/spi_m_pkg/src/spi_m_driver_bfm.sv +R11 +R12 +R13 +R14 +R15 +R16 +R17 +R18 +R19 +R20 +R21 +R22 +Z42 L0 60 +R24 +Z43 !s108 1672040996.000000 +Z44 !s107 /tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/macros/uvm_deprecated_defines.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/macros/uvm_reg_defines.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/macros/uvm_callback_defines.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/macros/uvm_sequence_defines.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/tlm1/uvm_tlm_imps.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/macros/uvm_tlm_defines.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/macros/uvm_printer_defines.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/macros/uvm_object_defines.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/macros/uvm_phase_defines.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/macros/uvm_message_defines.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/macros/uvm_version_defines.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/uvm_macros.svh|/hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/project_benches/block_2/sim/../../../verification_ip/interface_packages/spi_m_pkg/src/spi_m_macros.svh|/hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/project_benches/block_2/sim/../../../verification_ip/interface_packages/spi_m_pkg/src/spi_m_driver_bfm.sv|/hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/project_benches/block_2/sim/../../../verification_ip/interface_packages/spi_m_pkg/src/spi_m_monitor_bfm.sv|/hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/project_benches/block_2/sim/../../../verification_ip/interface_packages/spi_m_pkg/src/spi_m_if.sv| +Z45 !s90 -sv|-suppress|2223|-suppress|2286|+define+UVM_REPORT_DISABLE_FILE_LINE|+define+UVM_REPORT_DISABLE_FILE_LINE|+incdir+/hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/project_benches/block_2/sim/../../../verification_ip/interface_packages/spi_m_pkg|-F|/hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/project_benches/block_2/sim/../../../verification_ip/interface_packages/spi_m_pkg/spi_m_filelist_xrtl.f| +!i113 0 +R25 +Z46 !s92 -suppress 2223 -suppress 2286 -sv +define+UVM_REPORT_DISABLE_FILE_LINE +define+UVM_REPORT_DISABLE_FILE_LINE +incdir+/hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/project_benches/block_2/sim/../../../verification_ip/interface_packages/spi_m_pkg -L mtiAvm -L mtiRnm -L mtiOvm -L mtiUvm -L mtiUPF -L infact +R26 +Xspi_m_driver_bfm_sv_unit +R1 +R3 +R5 +VFMfb6JO]keVijVni0Vn^f2 +r1 +!s85 0 +31 +!i10b 1 +!s100 om=fogKFBFb:`m3EELZGE0 +IFMfb6JO]keVijVni0Vn^f2 +!i103 1 +S1 +R0 +R39 +R40 +R41 +Z47 F/hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/project_benches/block_2/sim/../../../verification_ip/interface_packages/spi_m_pkg/src/spi_m_macros.svh +Z48 L0 56 +R24 +R43 +R44 +R45 +!i113 0 +R25 +R46 +R26 +Yspi_m_if +R1 +R3 +R5 +DXx4 work 16 spi_m_if_sv_unit 0 22 0HgTDWKcQm=HdDYajT6gI1 +R35 +r1 +!s85 0 +31 +!i10b 1 +!s100 ONGKTVnNf@BHVO9lJ<35L2 +Io4V1:hXR?0VlOBUHH?4I_2 +!s105 spi_m_if_sv_unit +S1 +R0 +Z49 w1672040980 +Z50 8/hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/project_benches/block_2/sim/../../../verification_ip/interface_packages/spi_m_pkg/src/spi_m_if.sv +Z51 F/hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/project_benches/block_2/sim/../../../verification_ip/interface_packages/spi_m_pkg/src/spi_m_if.sv +L0 30 +R24 +R43 +R44 +R45 +!i113 0 +R25 +R46 +R26 +Xspi_m_if_sv_unit +R1 +R3 +R5 +V0HgTDWKcQm=HdDYajT6gI1 +r1 +!s85 0 +31 +!i10b 1 +!s100 FzQ@RRdj;DGEmaClVXo>93 +I0HgTDWKcQm=HdDYajT6gI1 +!i103 1 +S1 +R0 +R49 +R50 +R51 +L0 27 +R24 +R43 +R44 +R45 +!i113 0 +R25 +R46 +R26 +Yspi_m_monitor_bfm +R1 +R3 +R5 +DXx4 work 25 spi_m_monitor_bfm_sv_unit 0 22 n9MJl2E5kPE8KWR>@NeZ]1 +R2 +R4 +R6 +R35 +r1 +!s85 0 +31 +!i10b 1 +!s100 XDjIL]C>?]n;oEW=3EY8P3 +Io9?F;g7A9Pc7e?ak;U:0O3 +!s105 spi_m_monitor_bfm_sv_unit +S1 +R0 +R49 +Z52 8/hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/project_benches/block_2/sim/../../../verification_ip/interface_packages/spi_m_pkg/src/spi_m_monitor_bfm.sv +Z53 F/hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/project_benches/block_2/sim/../../../verification_ip/interface_packages/spi_m_pkg/src/spi_m_monitor_bfm.sv +R11 +R12 +R13 +R14 +R15 +R16 +R17 +R18 +R19 +R20 +R21 +R22 +Z54 L0 36 +R24 +R43 +R44 +R45 +!i113 0 +R25 +R46 +R26 +Xspi_m_monitor_bfm_sv_unit +R1 +R3 +R5 +Vn9MJl2E5kPE8KWR>@NeZ]1 +r1 +!s85 0 +31 +!i10b 1 +!s100 R86fbRSEA;]?B5Da5ziZ@3 +In9MJl2E5kPE8KWR>@NeZ]1 +!i103 1 +S1 +R0 +R49 +R52 +R53 +R47 +Z55 L0 31 +R24 +R43 +R44 +R45 +!i113 0 +R25 +R46 +R26 +Xspi_m_pkg +!s115 spi_m_monitor_bfm +!s115 spi_m_driver_bfm +R1 +R2 +R3 +R4 +R5 +!s110 1672040996 +!i10b 1 +!s100 3SV5fSZh6m@WVmX:nGE1E1 +IzdWd]a@SHa1@eQ3of`eXX2 +VzdWd]a@SHa1@eQ3of`eXX2 +S1 +R0 +R39 +8/hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/project_benches/block_2/sim/../../../verification_ip/interface_packages/spi_m_pkg/spi_m_pkg.sv +F/hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/project_benches/block_2/sim/../../../verification_ip/interface_packages/spi_m_pkg/spi_m_pkg.sv +R11 +R12 +R13 +R14 +R15 +R16 +R17 +R18 +R19 +R20 +R21 +R22 +R47 +F/hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/project_benches/block_2/sim/../../../verification_ip/interface_packages/spi_m_pkg/src/spi_m_typedefs.svh +F/hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/project_benches/block_2/sim/../../../verification_ip/interface_packages/spi_m_pkg/src/spi_m_transaction.svh +F/hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/project_benches/block_2/sim/../../../verification_ip/interface_packages/spi_m_pkg/src/spi_m_configuration.svh +F/hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/project_benches/block_2/sim/../../../verification_ip/interface_packages/spi_m_pkg/src/spi_m_driver.svh +F/hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/project_benches/block_2/sim/../../../verification_ip/interface_packages/spi_m_pkg/src/spi_m_monitor.svh +F/hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/project_benches/block_2/sim/../../../verification_ip/interface_packages/spi_m_pkg/src/spi_m_transaction_coverage.svh +F/hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/project_benches/block_2/sim/../../../verification_ip/interface_packages/spi_m_pkg/src/spi_m_sequence_base.svh +F/hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/project_benches/block_2/sim/../../../verification_ip/interface_packages/spi_m_pkg/src/spi_m_random_sequence.svh +F/hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/project_benches/block_2/sim/../../../verification_ip/interface_packages/spi_m_pkg/src/spi_m_responder_sequence.svh +F/hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/project_benches/block_2/sim/../../../verification_ip/interface_packages/spi_m_pkg/src/spi_m2reg_adapter.svh +F/hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/project_benches/block_2/sim/../../../verification_ip/interface_packages/spi_m_pkg/src/spi_m_agent.svh +R55 +R24 +r1 +!s85 0 +31 +Z56 !s108 1672040995.000000 +!s107 /hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/project_benches/block_2/sim/../../../verification_ip/interface_packages/spi_m_pkg/src/spi_m_agent.svh|/hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/project_benches/block_2/sim/../../../verification_ip/interface_packages/spi_m_pkg/src/spi_m2reg_adapter.svh|/hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/project_benches/block_2/sim/../../../verification_ip/interface_packages/spi_m_pkg/src/spi_m_responder_sequence.svh|/hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/project_benches/block_2/sim/../../../verification_ip/interface_packages/spi_m_pkg/src/spi_m_random_sequence.svh|/hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/project_benches/block_2/sim/../../../verification_ip/interface_packages/spi_m_pkg/src/spi_m_sequence_base.svh|/hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/project_benches/block_2/sim/../../../verification_ip/interface_packages/spi_m_pkg/src/spi_m_transaction_coverage.svh|/hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/project_benches/block_2/sim/../../../verification_ip/interface_packages/spi_m_pkg/src/spi_m_monitor.svh|/hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/project_benches/block_2/sim/../../../verification_ip/interface_packages/spi_m_pkg/src/spi_m_driver.svh|/hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/project_benches/block_2/sim/../../../verification_ip/interface_packages/spi_m_pkg/src/spi_m_configuration.svh|/hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/project_benches/block_2/sim/../../../verification_ip/interface_packages/spi_m_pkg/src/spi_m_transaction.svh|/hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/project_benches/block_2/sim/../../../verification_ip/interface_packages/spi_m_pkg/src/spi_m_typedefs.svh|/hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/project_benches/block_2/sim/../../../verification_ip/interface_packages/spi_m_pkg/src/spi_m_macros.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/macros/uvm_deprecated_defines.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/macros/uvm_reg_defines.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/macros/uvm_callback_defines.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/macros/uvm_sequence_defines.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/tlm1/uvm_tlm_imps.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/macros/uvm_tlm_defines.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/macros/uvm_printer_defines.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/macros/uvm_object_defines.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/macros/uvm_phase_defines.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/macros/uvm_message_defines.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/macros/uvm_version_defines.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/uvm_macros.svh|/hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/project_benches/block_2/sim/../../../verification_ip/interface_packages/spi_m_pkg/spi_m_pkg.sv| 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a/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/project_benches/block_2/sim/work/optimized_debug_top_tb/_lib5_0.qtl b/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/project_benches/block_2/sim/work/optimized_debug_top_tb/_lib5_0.qtl new file mode 100644 index 00000000..6714891d Binary files /dev/null and b/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/project_benches/block_2/sim/work/optimized_debug_top_tb/_lib5_0.qtl differ diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/project_benches/block_2/sim/xwaves.sigs b/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/project_benches/block_2/sim/xwaves.sigs new file mode 100644 index 00000000..d75f0a57 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/project_benches/block_2/sim/xwaves.sigs @@ -0,0 +1,17 @@ + + + + + +# pragma uvmf custom additional begin + +Group All + +#Top level signals +hdl_top.* +#Add additional levels or individual signals as needed +hdl_top.*.* + +# pragma uvmf custom additional end + + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/project_benches/block_2/tb/parameters/block_2_parameters_pkg.compile b/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/project_benches/block_2/tb/parameters/block_2_parameters_pkg.compile new file mode 100644 index 00000000..1d5f4608 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/project_benches/block_2/tb/parameters/block_2_parameters_pkg.compile @@ -0,0 +1,4 @@ +needs: + - $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg_hdl.compile +src: + - block_2_parameters_pkg.sv diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/project_benches/block_2/tb/parameters/block_2_parameters_pkg.sv b/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/project_benches/block_2/tb/parameters/block_2_parameters_pkg.sv new file mode 100644 index 00000000..67f61b95 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/project_benches/block_2/tb/parameters/block_2_parameters_pkg.sv @@ -0,0 +1,38 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This package contains test level parameters +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// + + +package block_2_parameters_pkg; + + import uvmf_base_pkg_hdl::*; + + // pragma uvmf custom package_imports_additional begin + // pragma uvmf custom package_imports_additional end + + + // These parameters are used to uniquely identify each interface. The monitor_bfm and + // driver_bfm are placed into and retrieved from the uvm_config_db using these string + // names as the field_name. The parameter is also used to enable transaction viewing + // from the command line for selected interfaces using the UVM command line processing. + parameter string spi_master_BFM = "spi_master_BFM"; /* [0] */ + parameter string wb_slave_BFM = "wb_slave_BFM"; /* [1] */ + + // pragma uvmf custom package_item_additional begin + // pragma uvmf custom package_item_additional end + +endpackage + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/project_benches/block_2/tb/parameters/block_2_parameters_pkg.vinfo b/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/project_benches/block_2/tb/parameters/block_2_parameters_pkg.vinfo new file mode 100644 index 00000000..7d0528cc --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/project_benches/block_2/tb/parameters/block_2_parameters_pkg.vinfo @@ -0,0 +1,2 @@ +@use $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg_hdl.vinfo +block_2_parameters_pkg.sv diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/project_benches/block_2/tb/sequences/block_2_sequences_pkg.compile b/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/project_benches/block_2/tb/sequences/block_2_sequences_pkg.compile new file mode 100644 index 00000000..60acb579 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/project_benches/block_2/tb/sequences/block_2_sequences_pkg.compile @@ -0,0 +1,8 @@ +needs: + - $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg.compile + - ../../../../verification_ip/interface_packages/spi_m_pkg/spi_m.compile + - ../../../../verification_ip/interface_packages/wb_s_pkg/wb_s.compile + - ../../../../verification_ip/environment_packages/block_2_env_pkg/block_2_env_pkg.compile + - ../parameters/block_2_parameters_pkg.compile +src: + - block_2_sequences_pkg.sv diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/project_benches/block_2/tb/sequences/block_2_sequences_pkg.sv b/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/project_benches/block_2/tb/sequences/block_2_sequences_pkg.sv new file mode 100644 index 00000000..3948b622 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/project_benches/block_2/tb/sequences/block_2_sequences_pkg.sv @@ -0,0 +1,51 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This package includes all high level sequence classes used +// in the environment. These include utility sequences and top +// level sequences. +// +// CONTAINS: +// - +// - +// +//---------------------------------------------------------------------- +// +//---------------------------------------------------------------------- +// + +package block_2_sequences_pkg; + import uvm_pkg::*; + import uvmf_base_pkg::*; + import spi_m_pkg::*; + import spi_m_pkg_hdl::*; + import wb_s_pkg::*; + import wb_s_pkg_hdl::*; + import block_2_parameters_pkg::*; + import block_2_env_pkg::*; + `include "uvm_macros.svh" + + // pragma uvmf custom package_imports_additional begin + // pragma uvmf custom package_imports_additional end + + `include "src/block_2_bench_sequence_base.svh" + `include "src/register_test_sequence.svh" + `include "src/example_derived_test_sequence.svh" + + // pragma uvmf custom package_item_additional begin + // UVMF_CHANGE_ME : When adding new sequences to the src directory + // be sure to add the sequence file here so that it will be + // compiled as part of the sequence package. Be sure to place + // the new sequence after any base sequences of the new sequence. + // pragma uvmf custom package_item_additional end + +endpackage + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/project_benches/block_2/tb/sequences/block_2_sequences_pkg.vinfo b/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/project_benches/block_2/tb/sequences/block_2_sequences_pkg.vinfo new file mode 100644 index 00000000..9d82a0e6 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/project_benches/block_2/tb/sequences/block_2_sequences_pkg.vinfo @@ -0,0 +1,7 @@ +@use $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg.vinfo +@use $UVMF_VIP_LIBRARY_HOME/interface_packages/spi_m_pkg/spi_m_pkg.vinfo +@use $UVMF_VIP_LIBRARY_HOME/interface_packages/wb_s_pkg/wb_s_pkg.vinfo +@use $UVMF_VIP_LIBRARY_HOME/environment_packages/block_2_env_pkg/block_2_env_pkg.vinfo +@use $UVMF_PROJECT_DIR/tb/parameters/block_2_parameters_pkg.vinfo ++incdir+@vinfodir +block_2_sequences_pkg.sv diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/project_benches/block_2/tb/sequences/src/block_2_bench_sequence_base.svh b/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/project_benches/block_2/tb/sequences/src/block_2_bench_sequence_base.svh new file mode 100644 index 00000000..33b1b8c1 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/project_benches/block_2/tb/sequences/src/block_2_bench_sequence_base.svh @@ -0,0 +1,121 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// Description: This file contains the top level and utility sequences +// used by test_top. It can be extended to create derivative top +// level sequences. +// +//---------------------------------------------------------------------- +// +//---------------------------------------------------------------------- +// + + +typedef block_2_env_configuration block_2_env_configuration_t; + +class block_2_bench_sequence_base extends uvmf_sequence_base #(uvm_sequence_item); + + `uvm_object_utils( block_2_bench_sequence_base ); + + // pragma uvmf custom sequences begin + +typedef block_2_env_sequence_base #( + .CONFIG_T(block_2_env_configuration_t) + ) + block_2_env_sequence_base_t; +rand block_2_env_sequence_base_t block_2_env_seq; + + + + // UVMF_CHANGE_ME : Instantiate, construct, and start sequences as needed to create stimulus scenarios. + // Instantiate sequences here + typedef spi_m_random_sequence spi_master_random_seq_t; + spi_master_random_seq_t spi_master_random_seq; + // pragma uvmf custom sequences end + + // Sequencer handles for each active interface in the environment + typedef spi_m_transaction spi_master_transaction_t; + uvm_sequencer #(spi_master_transaction_t) spi_master_sequencer; + + + // Top level environment configuration handle + block_2_env_configuration_t top_configuration; + + // Configuration handles to access interface BFM's + spi_m_configuration spi_master_config; + wb_s_configuration wb_slave_config; + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + // **************************************************************************** + function new( string name = "" ); + super.new( name ); + // Retrieve the configuration handles from the uvm_config_db + + // Retrieve top level configuration handle + if ( !uvm_config_db#(block_2_env_configuration_t)::get(null,UVMF_CONFIGURATIONS, "TOP_ENV_CONFIG",top_configuration) ) begin + `uvm_info("CFG", "*** FATAL *** uvm_config_db::get can not find TOP_ENV_CONFIG. Are you using an older UVMF release than what was used to generate this bench?",UVM_NONE); + `uvm_fatal("CFG", "uvm_config_db#(block_2_env_configuration_t)::get cannot find resource TOP_ENV_CONFIG"); + end + + // Retrieve config handles for all agents + if( !uvm_config_db #( spi_m_configuration )::get( null , UVMF_CONFIGURATIONS , spi_master_BFM , spi_master_config ) ) + `uvm_fatal("CFG" , "uvm_config_db #( spi_m_configuration )::get cannot find resource spi_master_BFM" ) + if( !uvm_config_db #( wb_s_configuration )::get( null , UVMF_CONFIGURATIONS , wb_slave_BFM , wb_slave_config ) ) + `uvm_fatal("CFG" , "uvm_config_db #( wb_s_configuration )::get cannot find resource wb_slave_BFM" ) + + // Assign the sequencer handles from the handles within agent configurations + spi_master_sequencer = spi_master_config.get_sequencer(); + + + + // pragma uvmf custom new begin + // pragma uvmf custom new end + + endfunction + + // **************************************************************************** + virtual task body(); + // pragma uvmf custom body begin + + // Construct sequences here + + block_2_env_seq = block_2_env_sequence_base_t::type_id::create("block_2_env_seq"); + + spi_master_random_seq = spi_master_random_seq_t::type_id::create("spi_master_random_seq"); + fork + spi_master_config.wait_for_reset(); + wb_slave_config.wait_for_reset(); + join + // Start RESPONDER sequences here + fork + join_none + // Start INITIATOR sequences here + fork + repeat (25) spi_master_random_seq.start(spi_master_sequencer); + join + +block_2_env_seq.start(top_configuration.vsqr); + + // UVMF_CHANGE_ME : Extend the simulation XXX number of clocks after + // the last sequence to allow for the last sequence item to flow + // through the design. + fork + spi_master_config.wait_for_num_clocks(400); + wb_slave_config.wait_for_num_clocks(400); + join + + // pragma uvmf custom body end + endtask + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/project_benches/block_2/tb/sequences/src/example_derived_test_sequence.svh b/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/project_benches/block_2/tb/sequences/src/example_derived_test_sequence.svh new file mode 100644 index 00000000..8bd3e555 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/project_benches/block_2/tb/sequences/src/example_derived_test_sequence.svh @@ -0,0 +1,30 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +// +//---------------------------------------------------------------------- +// +// DESCRIPTION: This file contains the top level sequence used in example_derived_test. +// It is an example of a sequence that is extended from %(benchName)_bench_sequence_base +// and can override %(benchName)_bench_sequence_base. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// + +class example_derived_test_sequence extends block_2_bench_sequence_base; + + `uvm_object_utils( example_derived_test_sequence ); + + function new(string name = "" ); + super.new(name); + endfunction + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/project_benches/block_2/tb/sequences/src/register_test_sequence.svh b/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/project_benches/block_2/tb/sequences/src/register_test_sequence.svh new file mode 100644 index 00000000..6948b861 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/project_benches/block_2/tb/sequences/src/register_test_sequence.svh @@ -0,0 +1,57 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This file contains the top level sequence used in register_test. +// It uses the UVM built in register test. Specific UVM built-in tests can be +// selected in the body task. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// + +class register_test_sequence extends block_2_bench_sequence_base; + + `uvm_object_utils( register_test_sequence ); + + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + function new(string name = "" ); + super.new(name); + endfunction + + // **************************************************************************** + virtual task body(); + + // Reset the DUT + fork + // pragma uvmf custom register_test_reset begin + // UVMF_CHANGE_ME + // Select the desired wait_for_reset or provide custom mechanism. + // fork-join for this code block may be unnecessary based on your situation. + spi_master_config.wait_for_reset(); + wb_slave_config.wait_for_reset(); + // pragma uvmf custom register_test_reset end + join + + // pragma uvmf custom register_test_setup begin + // UVMF_CHANGE_ME perform potentially necessary operations before running the sequence. + // pragma uvmf custom register_test_setup end + + // pragma uvmf custom register_test_operation begin + // UVMF_CHANGE_ME Perform your custom register test + // pragma uvmf custom register_test_operation end + + endtask + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/project_benches/block_2/tb/testbench/hdl_top.compile b/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/project_benches/block_2/tb/testbench/hdl_top.compile new file mode 100644 index 00000000..96a0acc9 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/project_benches/block_2/tb/testbench/hdl_top.compile @@ -0,0 +1,10 @@ +incdir: + - ${uvm_path}/src + - . +needs: + - $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg_hdl.compile + - ../parameters/block_2_parameters_pkg.compile + - ../../../../verification_ip/interface_packages/spi_m_pkg/spi_m_hdl.compile + - ../../../../verification_ip/interface_packages/wb_s_pkg/wb_s_hdl.compile +src: + - hdl_top.sv diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/project_benches/block_2/tb/testbench/hdl_top.sv b/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/project_benches/block_2/tb/testbench/hdl_top.sv new file mode 100644 index 00000000..1d30b34f --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/project_benches/block_2/tb/testbench/hdl_top.sv @@ -0,0 +1,99 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// Description: This top level module instantiates all synthesizable +// static content. This and tb_top.sv are the two top level modules +// of the simulation. +// +// This module instantiates the following: +// DUT: The Design Under Test +// Interfaces: Signal bundles that contain signals connected to DUT +// Driver BFM's: BFM's that actively drive interface signals +// Monitor BFM's: BFM's that passively monitor interface signals +// +//---------------------------------------------------------------------- + +//---------------------------------------------------------------------- +// + +module hdl_top; + +import block_2_parameters_pkg::*; +import uvmf_base_pkg_hdl::*; + + // pragma attribute hdl_top partition_module_xrtl +// pragma uvmf custom clock_generator begin + bit clk; + // Instantiate a clk driver + // tbx clkgen + initial begin + clk = 0; + #9ns; + forever begin + clk = ~clk; + #5ns; + end + end +// pragma uvmf custom clock_generator end + +// pragma uvmf custom reset_generator begin + bit rst; + // Instantiate a rst driver + // tbx clkgen + initial begin + rst = 1; + #200ns; + rst = 0; + end +// pragma uvmf custom reset_generator end + + // pragma uvmf custom module_item_additional begin + // pragma uvmf custom module_item_additional end + + // Instantiate the signal bundle, monitor bfm and driver bfm for each interface. + // The signal bundle, _if, contains signals to be connected to the DUT. + // The monitor, monitor_bfm, observes the bus, _if, and captures transactions. + // The driver, driver_bfm, drives transactions onto the bus, _if. + spi_m_if spi_master_bus( + // pragma uvmf custom spi_master_bus_connections begin + .sck(clk), .rst(rst) + // pragma uvmf custom spi_master_bus_connections end + ); + wb_s_if wb_slave_bus( + // pragma uvmf custom wb_slave_bus_connections begin + .clock(clk), .reset(rst) + // pragma uvmf custom wb_slave_bus_connections end + ); + spi_m_monitor_bfm spi_master_mon_bfm(spi_master_bus.monitor_port); + wb_s_monitor_bfm wb_slave_mon_bfm(wb_slave_bus.monitor_port); + spi_m_driver_bfm spi_master_drv_bfm(spi_master_bus.initiator_port); + + // pragma uvmf custom dut_instantiation begin + // UVMF_CHANGE_ME : Add DUT and connect to signals in _bus interfaces listed above + // Instantiate your DUT here + // These DUT's instantiated to show verilog and vhdl instantiation + verilog_dut dut_verilog( .clk(clk), .rst(rst), .in_signal(vhdl_to_verilog_signal), .out_signal(verilog_to_vhdl_signal)); + vhdl_dut dut_vhdl ( .clk(clk), .rst(rst), .in_signal(verilog_to_vhdl_signal), .out_signal(vhdl_to_verilog_signal)); + // pragma uvmf custom dut_instantiation end + + initial begin // tbx vif_binding_block + import uvm_pkg::uvm_config_db; + // The monitor_bfm and driver_bfm for each interface is placed into the uvm_config_db. + // They are placed into the uvm_config_db using the string names defined in the parameters package. + // The string names are passed to the agent configurations by test_top through the top level configuration. + // They are retrieved by the agents configuration class for use by the agent. + uvm_config_db #( virtual spi_m_monitor_bfm )::set( null , UVMF_VIRTUAL_INTERFACES , spi_master_BFM , spi_master_mon_bfm ); + uvm_config_db #( virtual wb_s_monitor_bfm )::set( null , UVMF_VIRTUAL_INTERFACES , wb_slave_BFM , wb_slave_mon_bfm ); + uvm_config_db #( virtual spi_m_driver_bfm )::set( null , UVMF_VIRTUAL_INTERFACES , spi_master_BFM , spi_master_drv_bfm ); + end + +endmodule + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/project_benches/block_2/tb/testbench/hdl_top.vinfo b/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/project_benches/block_2/tb/testbench/hdl_top.vinfo new file mode 100644 index 00000000..dce0a508 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/project_benches/block_2/tb/testbench/hdl_top.vinfo @@ -0,0 +1,6 @@ +@use $UVMF_PROJECT_DIR/rtl/verilog/verilog_dut.vinfo +@use $UVMF_PROJECT_DIR/tb/parameters/block_2_parameters_pkg.vinfo +@use $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg_hdl.vinfo +@use $UVMF_VIP_LIBRARY_HOME/interface_packages/spi_m_pkg/spi_m_bfm.vinfo +@use $UVMF_VIP_LIBRARY_HOME/interface_packages/wb_s_pkg/wb_s_bfm.vinfo +hdl_top.sv diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/project_benches/block_2/tb/testbench/hvl_top.compile b/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/project_benches/block_2/tb/testbench/hvl_top.compile new file mode 100644 index 00000000..381340b2 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/project_benches/block_2/tb/testbench/hvl_top.compile @@ -0,0 +1,7 @@ +incdir: + - ${uvm_path}/src + - . +needs: + - ../tests/block_2_tests_pkg.compile +src: + - hvl_top.sv diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/project_benches/block_2/tb/testbench/hvl_top.sv b/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/project_benches/block_2/tb/testbench/hvl_top.sv new file mode 100644 index 00000000..1cd56838 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/project_benches/block_2/tb/testbench/hvl_top.sv @@ -0,0 +1,33 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +// +//---------------------------------------------------------------------- +// +// DESCRIPTION: This module loads the test package and starts the UVM phases. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// + +module hvl_top; + +import uvm_pkg::*; +import block_2_tests_pkg::*; + + // pragma uvmf custom module_item_additional begin + // pragma uvmf custom module_item_additional end + + initial begin + $timeformat(-9,3,"ns",5); + run_test(); + end + +endmodule + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/project_benches/block_2/tb/testbench/hvl_top.vinfo b/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/project_benches/block_2/tb/testbench/hvl_top.vinfo new file mode 100644 index 00000000..fd98547a --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/project_benches/block_2/tb/testbench/hvl_top.vinfo @@ -0,0 +1,2 @@ +@use $UVMF_PROJECT_DIR/tb/tests/block_2_tests_pkg.vinfo +hvl_top.sv diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/project_benches/block_2/tb/testbench/top_filelist_hdl.f b/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/project_benches/block_2/tb/testbench/top_filelist_hdl.f new file mode 100644 index 00000000..1e9dab65 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/project_benches/block_2/tb/testbench/top_filelist_hdl.f @@ -0,0 +1,3 @@ +$UVMF_PROJECT_DIR/tb/testbench/hdl_top.sv +// pragma uvmf custom additional begin +// pragma uvmf custom additional end diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/project_benches/block_2/tb/testbench/top_filelist_hvl.f b/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/project_benches/block_2/tb/testbench/top_filelist_hvl.f new file mode 100644 index 00000000..42383ab2 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/project_benches/block_2/tb/testbench/top_filelist_hvl.f @@ -0,0 +1,3 @@ +$UVMF_PROJECT_DIR/tb/testbench/hvl_top.sv +// pragma uvmf custom additional begin +// pragma uvmf custom additional end diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/project_benches/block_2/tb/tests/block_2_tests_pkg.compile b/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/project_benches/block_2/tb/tests/block_2_tests_pkg.compile new file mode 100644 index 00000000..fcd92c08 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/project_benches/block_2/tb/tests/block_2_tests_pkg.compile @@ -0,0 +1,9 @@ +needs: + - $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg.compile + - ../../../../verification_ip/interface_packages/spi_m_pkg/spi_m.compile + - ../../../../verification_ip/interface_packages/wb_s_pkg/wb_s.compile + - ../../../../verification_ip/environment_packages/block_2_env_pkg/block_2_env_pkg.compile + - ../parameters/block_2_parameters_pkg.compile + - ../sequences/block_2_sequences_pkg.compile +src: + - block_2_tests_pkg.sv diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/project_benches/block_2/tb/tests/block_2_tests_pkg.sv b/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/project_benches/block_2/tb/tests/block_2_tests_pkg.sv new file mode 100644 index 00000000..cc8e3ddb --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/project_benches/block_2/tb/tests/block_2_tests_pkg.sv @@ -0,0 +1,54 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This package contains all tests currently written for +// the simulation project. Once compiled, any test can be selected +// from the vsim command line using +UVM_TESTNAME=yourTestNameHere +// +// CONTAINS: +// - +// - +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// + +package block_2_tests_pkg; + + import uvm_pkg::*; + import uvmf_base_pkg::*; + import block_2_parameters_pkg::*; + import block_2_env_pkg::*; + import block_2_sequences_pkg::*; + import spi_m_pkg::*; + import spi_m_pkg_hdl::*; + import wb_s_pkg::*; + import wb_s_pkg_hdl::*; + + + `include "uvm_macros.svh" + + // pragma uvmf custom package_imports_additional begin + // pragma uvmf custom package_imports_additional end + + `include "src/test_top.svh" + `include "src/register_test.svh" + `include "src/example_derived_test.svh" + + // pragma uvmf custom package_item_additional begin + // UVMF_CHANGE_ME : When adding new tests to the src directory + // be sure to add the test file here so that it will be + // compiled as part of the test package. Be sure to place + // the new test after any base tests of the new test. + // pragma uvmf custom package_item_additional end + +endpackage + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/project_benches/block_2/tb/tests/block_2_tests_pkg.vinfo b/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/project_benches/block_2/tb/tests/block_2_tests_pkg.vinfo new file mode 100644 index 00000000..9992ff94 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/project_benches/block_2/tb/tests/block_2_tests_pkg.vinfo @@ -0,0 +1,8 @@ +@use $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg.vinfo +@use $UVMF_VIP_LIBRARY_HOME/interface_packages/spi_m_pkg/spi_m_pkg.vinfo +@use $UVMF_VIP_LIBRARY_HOME/interface_packages/wb_s_pkg/wb_s_pkg.vinfo +@use $UVMF_VIP_LIBRARY_HOME/environment_packages/block_2_env_pkg/block_2_env_pkg.vinfo +@use $UVMF_PROJECT_DIR/tb/parameters/block_2_parameters_pkg.vinfo +@use $UVMF_PROJECT_DIR/tb/sequences/block_2_sequences_pkg.vinfo ++incdir+@vinfodir +block_2_tests_pkg.sv diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/project_benches/block_2/tb/tests/src/example_derived_test.svh b/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/project_benches/block_2/tb/tests/src/example_derived_test.svh new file mode 100644 index 00000000..24753c75 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/project_benches/block_2/tb/tests/src/example_derived_test.svh @@ -0,0 +1,43 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This test extends test_top and makes +// changes to test_top using the UVM factory type_override: +// +// Test scenario: +// This is a template test that can be used to create future tests. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// + +class example_derived_test extends test_top; + + `uvm_component_utils( example_derived_test ); + + function new( string name = "", uvm_component parent = null ); + super.new( name, parent ); + endfunction + + virtual function void build_phase(uvm_phase phase); + // The factory override below is an example of how to replace the block_2_bench_sequence_base + // sequence with the example_derived_test_sequence. + block_2_bench_sequence_base::type_id::set_type_override(example_derived_test_sequence::get_type()); + // Execute the build_phase of test_top AFTER all factory overrides have been created. + super.build_phase(phase); + // pragma uvmf custom configuration_settings_post_randomize begin + // UVMF_CHANGE_ME Test specific configuration values can be set here. + // The configuration structure has already been randomized. + // pragma uvmf custom configuration_settings_post_randomize end + endfunction + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/project_benches/block_2/tb/tests/src/register_test.svh b/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/project_benches/block_2/tb/tests/src/register_test.svh new file mode 100644 index 00000000..2340b0f7 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/project_benches/block_2/tb/tests/src/register_test.svh @@ -0,0 +1,40 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This test extends test_top and makes +// changes to test_top using the UVM factory type_override: +// +// Test scenario: +// This is a template test that can be used to create future tests. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// + +class register_test extends test_top; + + `uvm_component_utils( register_test ); + + function new( string name = "", uvm_component parent = null ); + super.new( name, parent ); + endfunction + + virtual function void build_phase(uvm_phase phase); + // The factory override below replaces the block_2_bench_sequence_base + // sequence with the register_test_sequence. + block_2_bench_sequence_base::type_id::set_type_override(register_test_sequence::get_type()); + // Execute the build_phase of test_top AFTER all factory overrides have been created. + super.build_phase(phase); + endfunction + + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/project_benches/block_2/tb/tests/src/test_top.svh b/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/project_benches/block_2/tb/tests/src/test_top.svh new file mode 100644 index 00000000..d177a8dd --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/project_benches/block_2/tb/tests/src/test_top.svh @@ -0,0 +1,78 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// Description: This top level UVM test is the base class for all +// future tests created for this project. +// +// This test class contains: +// Configuration: The top level configuration for the project. +// Environment: The top level environment for the project. +// Top_level_sequence: The top level sequence for the project. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// + +typedef block_2_env_configuration block_2_env_configuration_t; +typedef block_2_environment block_2_environment_t; + +class test_top extends uvmf_test_base #(.CONFIG_T(block_2_env_configuration_t), + .ENV_T(block_2_environment_t), + .TOP_LEVEL_SEQ_T(block_2_bench_sequence_base)); + + `uvm_component_utils( test_top ); + + + + string interface_names[] = { + spi_master_BFM /* spi_master [0] */ , + wb_slave_BFM /* wb_slave [1] */ +}; + +uvmf_active_passive_t interface_activities[] = { + ACTIVE /* spi_master [0] */ , + PASSIVE /* wb_slave [1] */ }; + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + // **************************************************************************** + // FUNCTION: new() + // This is the standard systemVerilog constructor. All components are + // constructed in the build_phase to allow factory overriding. + // + function new( string name = "", uvm_component parent = null ); + super.new( name ,parent ); + endfunction + + + + // **************************************************************************** + // FUNCTION: build_phase() + // The construction of the configuration and environment classes is done in + // the build_phase of uvmf_test_base. Once the configuraton and environment + // classes are built then the initialize call is made to perform the + // following: + // Monitor and driver BFM virtual interface handle passing into agents + // Set the active/passive state for each agent + // Once this build_phase completes, the build_phase of the environment is + // executed which builds the agents. + // + virtual function void build_phase(uvm_phase phase); +// pragma uvmf custom build_phase_pre_super begin +// pragma uvmf custom build_phase_pre_super end + super.build_phase(phase); + // pragma uvmf custom configuration_settings_post_randomize begin + // pragma uvmf custom configuration_settings_post_randomize end + configuration.initialize(NA, "uvm_test_top.environment", interface_names, null, interface_activities); + endfunction + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/project_benches/block_2/yaml/block_2_bench.yaml b/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/project_benches/block_2/yaml/block_2_bench.yaml new file mode 100644 index 00000000..abfe0941 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/project_benches/block_2/yaml/block_2_bench.yaml @@ -0,0 +1,17 @@ +uvmf: + benches: + block_2: + active_passive: + - bfm_name: spi_master + value: ACTIVE + - bfm_name: wb_slave + value: PASSIVE + active_passive_default: ACTIVE + clock_half_period: 5ns + clock_phase_offset: 9ns + existing_library_component: 'True' + interface_params: [] + reset_assertion_level: 'True' + reset_duration: 200ns + top_env: block_2 + use_dpi_link: 'False' diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/verification_ip/environment_packages/block_2_env_pkg/.project b/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/verification_ip/environment_packages/block_2_env_pkg/.project new file mode 100644 index 00000000..a03fd98f --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/verification_ip/environment_packages/block_2_env_pkg/.project @@ -0,0 +1,32 @@ + + + block_2_env_pkg + + + + + + org.python.pydev.PyDevBuilder + + + + + net.sf.sveditor.core.SVProjectBuilder + + + + + + net.sf.sveditor.core.SVNature + org.python.pydev.pythonNature + + + + + + UVMF_VIP_LIBRARY_HOME + $%7BPARENT-2-PROJECT_LOC%7D + + + + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/verification_ip/environment_packages/block_2_env_pkg/.svproject b/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/verification_ip/environment_packages/block_2_env_pkg/.svproject new file mode 100644 index 00000000..8f384931 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/verification_ip/environment_packages/block_2_env_pkg/.svproject @@ -0,0 +1,16 @@ + + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/verification_ip/environment_packages/block_2_env_pkg/Makefile b/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/verification_ip/environment_packages/block_2_env_pkg/Makefile new file mode 100644 index 00000000..68a7f9f1 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/verification_ip/environment_packages/block_2_env_pkg/Makefile @@ -0,0 +1,56 @@ +# block_2 environment packages source and make target + +# pragma uvmf custom additional begin +# pragma uvmf custom additional end + +# Include all requisite sub-environment package targets for this bench + +block_2_ENV_PKG =\ + $(UVMF_VIP_LIBRARY_HOME)/environment_packages/block_2_env_pkg/block_2_env_pkg.sv + +COMP_block_2_PKG_TGT_0 = q_comp_block_2_env_pkg +COMP_block_2_PKG_TGT_1 = v_comp_block_2_env_pkg +COMP_block_2_PKG_TGT = $(COMP_block_2_PKG_TGT_$(USE_VELOCE)) + +comp_block_2_env_pkg: $(COMP_block_2_PKG_TGT) + +q_comp_block_2_env_pkg: + $(HVL_COMP_CMD) +incdir+$(UVMF_VIP_LIBRARY_HOME)/environment_packages/block_2_env_pkg $(block_2_ENV_PKG) + +v_comp_block_2_env_pkg: q_comp_block_2_env_pkg + $(VELANALYZE_HVL_CMD) +incdir+$(UVMF_VIP_LIBRARY_HOME)/environment_packages/block_2_env_pkg $(block_2_ENV_PKG) + + + +ifeq ($(MTI_VCO_MODE),64) + GCC_COMP_ARCH = -m64 +else + GCC_COMP_ARCH = -m32 +endif + +export block_2_ENV_DPI_SRC ?= $(UVMF_VIP_LIBRARY_HOME)/environment_packages/block_2_env_pkg/dpi + +C_FILE_COMPILE_LIST_block_2_env_pkg = \ + +O_FILE_COMPILE_LIST_block_2_env_pkg = $(notdir $(C_FILE_COMPILE_LIST_block_2_env_pkg:.c=.o)) + +GCC_COMP_ARGS_block_2_env_pkg += -I$(block_2_ENV_DPI_SRC) \ + -fPIC + +GCC_COMP_ARGS_block_2_env_pkg += $(block_2_ENV_GCC_COMP_ARGUMENTS) + +GCC_LINK_ARGS_block_2_env_pkg += \ + \ + -o .so + +comp_block_2_env_pkg_c_files: + @echo "--------------------------------" + @echo "Compiling Environment C source" + @echo "--------------------------------" + gcc $(GCC_COMP_ARCH) $(GCC_COMP_ARGS_block_2_env_pkg) $(C_FILE_COMPILE_LIST_block_2_env_pkg) + @echo "--------------------------------" + @echo "Linking Environment C objects into a shared object" + @echo "--------------------------------" + gcc $(GCC_COMP_ARCH) $(GCC_LINK_ARGS_block_2_env_pkg) $(O_FILE_COMPILE_LIST_block_2_env_pkg) + @echo "--------------------------------" + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/verification_ip/environment_packages/block_2_env_pkg/block_2_env_pkg.compile b/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/verification_ip/environment_packages/block_2_env_pkg/block_2_env_pkg.compile new file mode 100644 index 00000000..f00e42c6 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/verification_ip/environment_packages/block_2_env_pkg/block_2_env_pkg.compile @@ -0,0 +1,8 @@ +needs: + - $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg.compile + - ../../../verification_ip/interface_packages/spi_m_pkg/spi_m_hvl.compile + - ../../../verification_ip/interface_packages/wb_s_pkg/wb_s_hvl.compile + +src: + - block_2_env_pkg.sv + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/verification_ip/environment_packages/block_2_env_pkg/block_2_env_pkg.sv b/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/verification_ip/environment_packages/block_2_env_pkg/block_2_env_pkg.sv new file mode 100644 index 00000000..737c1244 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/verification_ip/environment_packages/block_2_env_pkg/block_2_env_pkg.sv @@ -0,0 +1,59 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// PACKAGE: This file defines all of the files contained in the +// environment package that will run on the host simulator. +// +// CONTAINS: +// - +// - +// - +// - +// - +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +package block_2_env_pkg; + + import uvm_pkg::*; + `include "uvm_macros.svh" + import uvmf_base_pkg::*; + import spi_m_pkg::*; + import spi_m_pkg_hdl::*; + import wb_s_pkg::*; + import wb_s_pkg_hdl::*; + + `uvm_analysis_imp_decl(_spi_ae) + `uvm_analysis_imp_decl(_sco_from_pre_ae) + `uvm_analysis_imp_decl(_wb_ae) + + // pragma uvmf custom package_imports_additional begin + // pragma uvmf custom package_imports_additional end + + // Parameters defined as HVL parameters + + `include "src/block_2_env_typedefs.svh" + `include "src/block_2_env_configuration.svh" + `include "src/block_2_predictor.svh" + `include "src/block_2_scoreboard.svh" + `include "src/block_2_environment.svh" + `include "src/block_2_env_sequence_base.svh" + + // pragma uvmf custom package_item_additional begin + // UVMF_CHANGE_ME : When adding new environment level sequences to the src directory + // be sure to add the sequence file here so that it will be + // compiled as part of the environment package. Be sure to place + // the new sequence after any base sequence of the new sequence. + // pragma uvmf custom package_item_additional end + +endpackage + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/verification_ip/environment_packages/block_2_env_pkg/block_2_env_pkg.vinfo b/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/verification_ip/environment_packages/block_2_env_pkg/block_2_env_pkg.vinfo new file mode 100644 index 00000000..edc8f1de --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/verification_ip/environment_packages/block_2_env_pkg/block_2_env_pkg.vinfo @@ -0,0 +1,5 @@ +@use $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg.vinfo +@use $UVMF_VIP_LIBRARY_HOME/interface_packages/spi_m_pkg/spi_m_pkg.vinfo +@use $UVMF_VIP_LIBRARY_HOME/interface_packages/wb_s_pkg/wb_s_pkg.vinfo ++incdir+@vinfodir +block_2_env_pkg.sv diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/verification_ip/environment_packages/block_2_env_pkg/block_2_env_pkg_sve.F b/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/verification_ip/environment_packages/block_2_env_pkg/block_2_env_pkg_sve.F new file mode 100644 index 00000000..7c09328b --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/verification_ip/environment_packages/block_2_env_pkg/block_2_env_pkg_sve.F @@ -0,0 +1,12 @@ + +// UVM ++incdir+${UVM_HOME}/src +${UVM_HOME}/src/uvm_pkg.sv + +// Common UVMF files +-f ${UVMF_HOME}/common/common_sve.f + +// Sub-Environments + ++incdir+. +./block_2_env_pkg.sv diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/verification_ip/environment_packages/block_2_env_pkg/compile.do b/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/verification_ip/environment_packages/block_2_env_pkg/compile.do new file mode 100644 index 00000000..93c75466 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/verification_ip/environment_packages/block_2_env_pkg/compile.do @@ -0,0 +1,12 @@ +# Tcl do file for compile of block_2 interface + +# pragma uvmf custom additional begin +# pragma uvmf custom additional end + + + +quietly set cmd [format "vlog -timescale 1ps/1ps +incdir+%s/environment_packages/block_2_env_pkg" $env(UVMF_VIP_LIBRARY_HOME)] +quietly set cmd [format "%s %s/environment_packages/block_2_env_pkg/block_2_env_pkg.sv" $cmd $env(UVMF_VIP_LIBRARY_HOME)] +eval $cmd + + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/verification_ip/environment_packages/block_2_env_pkg/src/block_2_env_configuration.svh b/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/verification_ip/environment_packages/block_2_env_pkg/src/block_2_env_configuration.svh new file mode 100644 index 00000000..b1d059e5 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/verification_ip/environment_packages/block_2_env_pkg/src/block_2_env_configuration.svh @@ -0,0 +1,146 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: THis is the configuration for the block_2 environment. +// it contains configuration classes for each agent. It also contains +// environment level configuration variables. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class block_2_env_configuration +extends uvmf_environment_configuration_base; + + `uvm_object_utils( block_2_env_configuration ) + + bit has_scoreboard; + +//Constraints for the configuration variables: + + + covergroup block_2_configuration_cg; + // pragma uvmf custom covergroup begin + option.auto_bin_max=1024; + coverpoint has_scoreboard; + // pragma uvmf custom covergroup end + endgroup + + + typedef spi_m_configuration spi_master_config_t; + rand spi_master_config_t spi_master_config; + + typedef wb_s_configuration wb_slave_config_t; + rand wb_slave_config_t wb_slave_config; + + + + + typedef uvmf_virtual_sequencer_base #(.CONFIG_T(block_2_env_configuration)) block_2_vsqr_t; + block_2_vsqr_t vsqr; + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + +// **************************************************************************** +// FUNCTION : new() +// This function is the standard SystemVerilog constructor. +// This function constructs the configuration object for each agent in the environment. +// + function new( string name = "" ); + super.new( name ); + + + spi_master_config = spi_master_config_t::type_id::create("spi_master_config"); + wb_slave_config = wb_slave_config_t::type_id::create("wb_slave_config"); + + + block_2_configuration_cg=new; + `uvm_warning("COVERAGE_MODEL_REVIEW", "A covergroup has been constructed which may need review because of either generation or re-generation with merging. Please note that configuration variables added as a result of re-generation and merging are not automatically added to the covergroup. Remove this warning after the covergroup has been reviewed.") + + // pragma uvmf custom new begin + // pragma uvmf custom new end + endfunction + +// **************************************************************************** +// FUNCTION : set_vsqr() +// This function is used to assign the vsqr handle. + virtual function void set_vsqr( block_2_vsqr_t vsqr); + this.vsqr = vsqr; + endfunction : set_vsqr + +// **************************************************************************** +// FUNCTION: post_randomize() +// This function is automatically called after the randomize() function +// is executed. +// + function void post_randomize(); + super.post_randomize(); + // pragma uvmf custom post_randomize begin + // pragma uvmf custom post_randomize end + endfunction + +// **************************************************************************** +// FUNCTION: convert2string() +// This function converts all variables in this class to a single string for +// logfile reporting. This function concatenates the convert2string result for +// each agent configuration in this configuration class. +// + virtual function string convert2string(); + // pragma uvmf custom convert2string begin + return { + $sformatf("has_scoreboard:0x%x ",has_scoreboard), + "\n", spi_master_config.convert2string, + "\n", wb_slave_config.convert2string + + + }; + // pragma uvmf custom convert2string end + endfunction +// **************************************************************************** +// FUNCTION: initialize(); +// This function configures each interface agents configuration class. The +// sim level determines the active/passive state of the agent. The environment_path +// identifies the hierarchy down to and including the instantiation name of the +// environment for this configuration class. Each instance of the environment +// has its own configuration class. The string interface names are used by +// the agent configurations to identify the virtual interface handle to pull from +// the uvm_config_db. +// + function void initialize(uvmf_sim_level_t sim_level, + string environment_path, + string interface_names[], + uvm_reg_block register_model = null, + uvmf_active_passive_t interface_activity[] = {} + ); + + super.initialize(sim_level, environment_path, interface_names, register_model, interface_activity); + + + + // Interface initialization for local agents + spi_master_config.initialize( interface_activity[0], {environment_path,".spi_master"}, interface_names[0]); + spi_master_config.initiator_responder = INITIATOR; + // spi_master_config.has_coverage = 1; + wb_slave_config.initialize( interface_activity[1], {environment_path,".wb_slave"}, interface_names[1]); + wb_slave_config.initiator_responder = RESPONDER; + // wb_slave_config.has_coverage = 1; + + + + + + // pragma uvmf custom initialize begin + // pragma uvmf custom initialize end + + endfunction + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/verification_ip/environment_packages/block_2_env_pkg/src/block_2_env_sequence_base.svh b/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/verification_ip/environment_packages/block_2_env_pkg/src/block_2_env_sequence_base.svh new file mode 100644 index 00000000..809e05e3 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/verification_ip/environment_packages/block_2_env_pkg/src/block_2_env_sequence_base.svh @@ -0,0 +1,69 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This file contains environment level sequences that will +// be reused from block to top level simulations. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class block_2_env_sequence_base #( + type CONFIG_T + ) extends uvmf_virtual_sequence_base #(.CONFIG_T(CONFIG_T)); + + + `uvm_object_param_utils( block_2_env_sequence_base #( + CONFIG_T + ) ); + + +// This block_2_env_sequence_base contains a handle to a block_2_env_configuration object +// named configuration. This configuration variable contains a handle to each +// sequencer within each agent within this environment and any sub-environments. +// The configuration object handle is automatically assigned in the pre_body in the +// base class of this sequence. The configuration handle is retrieved from the +// virtual sequencer that this sequence is started on. +// Available sequencer handles within the environment configuration: + + // Initiator agent sequencers in block_2_environment: + // configuration.spi_master_config.sequencer + + // Responder agent sequencers in block_2_environment: + // configuration.wb_slave_config.sequencer + + + typedef spi_m_random_sequence spi_master_random_sequence_t; + spi_master_random_sequence_t spi_master_rand_seq; + + + + + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + function new(string name = "" ); + super.new(name); + spi_master_rand_seq = spi_master_random_sequence_t::type_id::create("spi_master_rand_seq"); + + + endfunction + + virtual task body(); + + if ( configuration.spi_master_config.sequencer != null ) + repeat (25) spi_master_rand_seq.start(configuration.spi_master_config.sequencer); + + + endtask + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/verification_ip/environment_packages/block_2_env_pkg/src/block_2_env_typedefs.svh b/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/verification_ip/environment_packages/block_2_env_pkg/src/block_2_env_typedefs.svh new file mode 100644 index 00000000..9814bd58 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/verification_ip/environment_packages/block_2_env_pkg/src/block_2_env_typedefs.svh @@ -0,0 +1,20 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: +// This file contains defines and typedefs to be compiled for use in +// the environment package. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// + + + // pragma uvmf custom additional begin + // pragma uvmf custom additional end + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/verification_ip/environment_packages/block_2_env_pkg/src/block_2_environment.svh b/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/verification_ip/environment_packages/block_2_env_pkg/src/block_2_environment.svh new file mode 100644 index 00000000..b6a94f85 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/verification_ip/environment_packages/block_2_env_pkg/src/block_2_environment.svh @@ -0,0 +1,127 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This environment contains all agents, predictors and +// scoreboards required for the block level design. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// + +class block_2_environment extends uvmf_environment_base #( + .CONFIG_T( block_2_env_configuration + )); + `uvm_component_utils( block_2_environment ) + + + + uvm_analysis_port #(spi_m_transaction) spi_master_ap; + uvm_analysis_port #(wb_s_transaction) wb_slave_ap; + + + typedef spi_m_agent spi_master_t; + spi_master_t spi_master; + + typedef wb_s_agent wb_slave_t; + wb_slave_t wb_slave; + + + + + typedef block_2_predictor #( + .CONFIG_T(CONFIG_T) + ) block_2_pred_t; + block_2_pred_t block_2_pred; + typedef block_2_scoreboard #( + .CONFIG_T(CONFIG_T) + ) block_2_sb_t; + block_2_sb_t block_2_sb; + + + + + typedef uvmf_virtual_sequencer_base #(.CONFIG_T(block_2_env_configuration)) block_2_vsqr_t; + block_2_vsqr_t vsqr; + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + +// **************************************************************************** +// FUNCTION : new() +// This function is the standard SystemVerilog constructor. +// + function new( string name = "", uvm_component parent = null ); + super.new( name, parent ); + endfunction + +// **************************************************************************** +// FUNCTION: build_phase() +// This function builds all components within this environment. +// + virtual function void build_phase(uvm_phase phase); +// pragma uvmf custom build_phase_pre_super begin +// pragma uvmf custom build_phase_pre_super end + super.build_phase(phase); + spi_master_ap = new("spi_master_ap",this); + wb_slave_ap = new("wb_slave_ap",this); + spi_master = spi_master_t::type_id::create("spi_master",this); + spi_master.set_config(configuration.spi_master_config); + wb_slave = wb_slave_t::type_id::create("wb_slave",this); + wb_slave.set_config(configuration.wb_slave_config); + block_2_pred = block_2_pred_t::type_id::create("block_2_pred",this); + block_2_pred.configuration = configuration; + block_2_sb = block_2_sb_t::type_id::create("block_2_sb",this); + block_2_sb.configuration = configuration; + + vsqr = block_2_vsqr_t::type_id::create("vsqr", this); + vsqr.set_config(configuration); + configuration.set_vsqr(vsqr); + + // pragma uvmf custom build_phase begin + // pragma uvmf custom build_phase end + endfunction + +// **************************************************************************** +// FUNCTION: connect_phase() +// This function makes all connections within this environment. Connections +// typically inclue agent to predictor, predictor to scoreboard and scoreboard +// to agent. +// + virtual function void connect_phase(uvm_phase phase); +// pragma uvmf custom connect_phase_pre_super begin +// pragma uvmf custom connect_phase_pre_super end + super.connect_phase(phase); + spi_master.monitored_ap.connect(block_2_pred.spi_ae); + wb_slave.monitored_ap.connect(block_2_sb.wb_ae); + block_2_pred.pre_to_sco_ap.connect(block_2_sb.sco_from_pre_ae); + spi_master.monitored_ap.connect(spi_master_ap); + wb_slave.monitored_ap.connect(wb_slave_ap); + // pragma uvmf custom reg_model_connect_phase begin + // pragma uvmf custom reg_model_connect_phase end + endfunction + +// **************************************************************************** +// FUNCTION: end_of_simulation_phase() +// This function is executed just prior to executing run_phase. This function +// was added to the environment to sample environment configuration settings +// just before the simulation exits time 0. The configuration structure is +// randomized in the build phase before the environment structure is constructed. +// Configuration variables can be customized after randomization in the build_phase +// of the extended test. +// If a sequence modifies values in the configuration structure then the sequence is +// responsible for sampling the covergroup in the configuration if required. +// + virtual function void start_of_simulation_phase(uvm_phase phase); + configuration.block_2_configuration_cg.sample(); + endfunction + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/verification_ip/environment_packages/block_2_env_pkg/src/block_2_predictor.svh b/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/verification_ip/environment_packages/block_2_env_pkg/src/block_2_predictor.svh new file mode 100644 index 00000000..6eac733c --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/verification_ip/environment_packages/block_2_env_pkg/src/block_2_predictor.svh @@ -0,0 +1,114 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +// +//---------------------------------------------------------------------- +// +// DESCRIPTION: This analysis component contains analysis_exports for receiving +// data and analysis_ports for sending data. +// +// This analysis component has the following analysis_exports that receive the +// listed transaction type. +// +// spi_ae receives transactions of type spi_m_transaction +// +// This analysis component has the following analysis_ports that can broadcast +// the listed transaction type. +// +// pre_to_sco_ap broadcasts transactions of type wb_s_transaction +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// + +class block_2_predictor #( + type CONFIG_T, + type BASE_T = uvm_component + ) extends BASE_T; + + // Factory registration of this class + `uvm_component_param_utils( block_2_predictor #( + CONFIG_T, + BASE_T + )) + + + // Instantiate a handle to the configuration of the environment in which this component resides + CONFIG_T configuration; + + + // Instantiate the analysis exports + uvm_analysis_imp_spi_ae #(spi_m_transaction, block_2_predictor #( + .CONFIG_T(CONFIG_T), + .BASE_T(BASE_T) + )) spi_ae; + + + // Instantiate the analysis ports + uvm_analysis_port #(wb_s_transaction) pre_to_sco_ap; + + + // Transaction variable for predicted values to be sent out pre_to_sco_ap + // Once a transaction is sent through an analysis_port, another transaction should + // be constructed for the next predicted transaction. + typedef wb_s_transaction pre_to_sco_ap_output_transaction_t; + pre_to_sco_ap_output_transaction_t pre_to_sco_ap_output_transaction; + // Code for sending output transaction out through pre_to_sco_ap + // pre_to_sco_ap.write(pre_to_sco_ap_output_transaction); + + // Define transaction handles for debug visibility + spi_m_transaction spi_ae_debug; + + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + // FUNCTION: new + function new(string name, uvm_component parent); + super.new(name,parent); + `uvm_warning("PREDICTOR_REVIEW", "This predictor has been created either through generation or re-generation with merging. Remove this warning after the predictor has been reviewed.") + // pragma uvmf custom new begin + // pragma uvmf custom new end + endfunction + + // FUNCTION: build_phase + virtual function void build_phase (uvm_phase phase); + + spi_ae = new("spi_ae", this); + pre_to_sco_ap =new("pre_to_sco_ap", this ); + // pragma uvmf custom build_phase begin + // pragma uvmf custom build_phase end + endfunction + + // FUNCTION: write_spi_ae + // Transactions received through spi_ae initiate the execution of this function. + // This function performs prediction of DUT output values based on DUT input, configuration and state + virtual function void write_spi_ae(spi_m_transaction t); + // pragma uvmf custom spi_ae_predictor begin + spi_ae_debug = t; + `uvm_info("PRED", "Transaction Received through spi_ae", UVM_MEDIUM) + `uvm_info("PRED", {" Data: ",t.convert2string()}, UVM_FULL) + // Construct one of each output transaction type. + pre_to_sco_ap_output_transaction = pre_to_sco_ap_output_transaction_t::type_id::create("pre_to_sco_ap_output_transaction"); + // UVMF_CHANGE_ME: Implement predictor model here. + `uvm_info("UNIMPLEMENTED_PREDICTOR_MODEL", "******************************************************************************************************",UVM_NONE) + `uvm_info("UNIMPLEMENTED_PREDICTOR_MODEL", "UVMF_CHANGE_ME: The block_2_predictor::write_spi_ae function needs to be completed with DUT prediction model",UVM_NONE) + `uvm_info("UNIMPLEMENTED_PREDICTOR_MODEL", "******************************************************************************************************",UVM_NONE) + + // Code for sending output transaction out through pre_to_sco_ap + // Please note that each broadcasted transaction should be a different object than previously + // broadcasted transactions. Creation of a different object is done by constructing the transaction + // using either new() or create(). Broadcasting a transaction object more than once to either the + // same subscriber or multiple subscribers will result in unexpected and incorrect behavior. + pre_to_sco_ap.write(pre_to_sco_ap_output_transaction); + // pragma uvmf custom spi_ae_predictor end + endfunction + + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/verification_ip/environment_packages/block_2_env_pkg/src/block_2_scoreboard.svh b/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/verification_ip/environment_packages/block_2_env_pkg/src/block_2_scoreboard.svh new file mode 100644 index 00000000..82863e51 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/verification_ip/environment_packages/block_2_env_pkg/src/block_2_scoreboard.svh @@ -0,0 +1,131 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This analysis component contains analysis_exports for receiving +// data and analysis_ports for sending data. +// +// This analysis component has the following analysis_exports that receive the +// listed transaction type. +// +// sco_from_pre_ae receives transactions of type wb_s_transaction +// wb_ae receives transactions of type wb_s_transaction +// +// This analysis component has the following analysis_ports that can broadcast +// the listed transaction type. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// + + +class block_2_scoreboard #( + type CONFIG_T, + type BASE_T = uvm_component + ) extends BASE_T; + + // Factory registration of this class + `uvm_component_param_utils( block_2_scoreboard #( + CONFIG_T, + BASE_T + )) + + + // Instantiate a handle to the configuration of the environment in which this component resides + CONFIG_T configuration; + + + // Instantiate the analysis exports + uvm_analysis_imp_sco_from_pre_ae #(wb_s_transaction, block_2_scoreboard #( + .CONFIG_T(CONFIG_T), + .BASE_T(BASE_T) + )) sco_from_pre_ae; + uvm_analysis_imp_wb_ae #(wb_s_transaction, block_2_scoreboard #( + .CONFIG_T(CONFIG_T), + .BASE_T(BASE_T) + )) wb_ae; + + + + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + // FUNCTION: new + function new(string name, uvm_component parent); + super.new(name,parent); + // pragma uvmf custom new begin + // pragma uvmf custom new end + endfunction + + // FUNCTION: build_phase + virtual function void build_phase (uvm_phase phase); + + sco_from_pre_ae = new("sco_from_pre_ae", this); + wb_ae = new("wb_ae", this); + // pragma uvmf custom build_phase begin + // pragma uvmf custom build_phase end + endfunction + + // FUNCTION: write_sco_from_pre_ae + // Transactions received through sco_from_pre_ae initiate the execution of this function. + // This function performs prediction of DUT output values based on DUT input, configuration and state + virtual function void write_sco_from_pre_ae(wb_s_transaction t); + // pragma uvmf custom sco_from_pre_ae_scoreboard begin + `uvm_info("PRED", "Transaction Received through sco_from_pre_ae", UVM_MEDIUM) + `uvm_info("PRED", {" Data: ",t.convert2string()}, UVM_FULL) + // UVMF_CHANGE_ME: Implement custom scoreboard here. + `uvm_info("UNIMPLEMENTED_CUSTOM_SCOREBOARD", "******************************************************************************************************",UVM_NONE) + `uvm_info("UNIMPLEMENTED_CUSTOM_SCOREBOARD", "UVMF_CHANGE_ME: The block_2_scoreboard::write_sco_from_pre_ae function needs to be completed with custom scoreboard functionality",UVM_NONE) + `uvm_info("UNIMPLEMENTED_CUSTOM_SCOREBOARD", "******************************************************************************************************",UVM_NONE) + + // pragma uvmf custom sco_from_pre_ae_scoreboard end + endfunction + + // FUNCTION: write_wb_ae + // Transactions received through wb_ae initiate the execution of this function. + // This function performs prediction of DUT output values based on DUT input, configuration and state + virtual function void write_wb_ae(wb_s_transaction t); + // pragma uvmf custom wb_ae_scoreboard begin + `uvm_info("PRED", "Transaction Received through wb_ae", UVM_MEDIUM) + `uvm_info("PRED", {" Data: ",t.convert2string()}, UVM_FULL) + // UVMF_CHANGE_ME: Implement custom scoreboard here. + `uvm_info("UNIMPLEMENTED_CUSTOM_SCOREBOARD", "******************************************************************************************************",UVM_NONE) + `uvm_info("UNIMPLEMENTED_CUSTOM_SCOREBOARD", "UVMF_CHANGE_ME: The block_2_scoreboard::write_wb_ae function needs to be completed with custom scoreboard functionality",UVM_NONE) + `uvm_info("UNIMPLEMENTED_CUSTOM_SCOREBOARD", "******************************************************************************************************",UVM_NONE) + + // pragma uvmf custom wb_ae_scoreboard end + endfunction + + + + // FUNCTION: extract_phase + virtual function void extract_phase(uvm_phase phase); +// pragma uvmf custom extract_phase begin + super.extract_phase(phase); +// pragma uvmf custom extract_phase end + endfunction + + // FUNCTION: check_phase + virtual function void check_phase(uvm_phase phase); +// pragma uvmf custom check_phase begin + super.check_phase(phase); +// pragma uvmf custom check_phase end + endfunction + + // FUNCTION: report_phase + virtual function void report_phase(uvm_phase phase); +// pragma uvmf custom report_phase begin + super.report_phase(phase); +// pragma uvmf custom report_phase end + endfunction + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/verification_ip/environment_packages/block_2_env_pkg/yaml/block_2_environment.yaml b/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/verification_ip/environment_packages/block_2_env_pkg/yaml/block_2_environment.yaml new file mode 100644 index 00000000..dc04d0c3 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/verification_ip/environment_packages/block_2_env_pkg/yaml/block_2_environment.yaml @@ -0,0 +1,49 @@ +uvmf: + environments: + block_2: + agents: + - initiator_responder: INITIATOR + name: spi_master + type: spi_m + - initiator_responder: RESPONDER + name: wb_slave + type: wb_s + analysis_components: + - name: block_2_pred + parameters: [] + type: block_2_predictor + - name: block_2_sb + parameters: [] + type: block_2_scoreboard + analysis_exports: [] + analysis_ports: + - connected_to: spi_master.monitored_ap + name: spi_master_ap + trans_type: spi_m_transaction + - connected_to: wb_slave.monitored_ap + name: wb_slave_ap + trans_type: wb_s_transaction + config_constraints: [] + config_vars: + - comment: '' + isrand: 'False' + name: has_scoreboard + type: bit + value: '' + existing_library_component: 'True' + hvl_pkg_parameters: [] + non_uvmf_components: [] + parameters: [] + qvip_memory_agents: [] + scoreboards: [] + subenvs: [] + tlm_connections: + - driver: spi_master.monitored_ap + receiver: block_2_pred.spi_ae + validate: 'True' + - driver: wb_slave.monitored_ap + receiver: block_2_sb.wb_ae + validate: 'True' + - driver: block_2_pred.pre_to_sco_ap + receiver: block_2_sb.sco_from_pre_ae + validate: 'True' diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/verification_ip/environment_packages/block_2_env_pkg/yaml/block_2_util_comp_block_2_predictor.yaml b/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/verification_ip/environment_packages/block_2_env_pkg/yaml/block_2_util_comp_block_2_predictor.yaml new file mode 100644 index 00000000..c4fe0e50 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/verification_ip/environment_packages/block_2_env_pkg/yaml/block_2_util_comp_block_2_predictor.yaml @@ -0,0 +1,11 @@ +uvmf: + util_components: + block_2_predictor: + analysis_exports: + - name: spi_ae + type: spi_m_transaction + analysis_ports: + - name: pre_to_sco_ap + type: wb_s_transaction + existing_library_component: 'True' + type: predictor diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/verification_ip/environment_packages/block_2_env_pkg/yaml/block_2_util_comp_block_2_scoreboard.yaml b/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/verification_ip/environment_packages/block_2_env_pkg/yaml/block_2_util_comp_block_2_scoreboard.yaml new file mode 100644 index 00000000..b0e3bf1a --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/verification_ip/environment_packages/block_2_env_pkg/yaml/block_2_util_comp_block_2_scoreboard.yaml @@ -0,0 +1,10 @@ +uvmf: + util_components: + block_2_scoreboard: + analysis_exports: + - name: sco_from_pre_ae + type: wb_s_transaction + - name: wb_ae + type: wb_s_transaction + existing_library_component: 'True' + type: scoreboard diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/verification_ip/interface_packages/spi_m_pkg/.project b/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/verification_ip/interface_packages/spi_m_pkg/.project new file mode 100644 index 00000000..712c4d7d --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/verification_ip/interface_packages/spi_m_pkg/.project @@ -0,0 +1,30 @@ + + + spi_m_pkg + + + + + + org.python.pydev.PyDevBuilder + + + + + net.sf.sveditor.core.SVProjectBuilder + + + + + + net.sf.sveditor.core.SVNature + org.python.pydev.pythonNature + + + + UVMF_VIP_LIBRARY_HOME + $%7BPARENT-2-PROJECT_LOC%7D + + + + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/verification_ip/interface_packages/spi_m_pkg/.svproject b/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/verification_ip/interface_packages/spi_m_pkg/.svproject new file mode 100644 index 00000000..df5b00f1 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/verification_ip/interface_packages/spi_m_pkg/.svproject @@ -0,0 +1,16 @@ + + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/verification_ip/interface_packages/spi_m_pkg/Makefile b/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/verification_ip/interface_packages/spi_m_pkg/Makefile new file mode 100644 index 00000000..1dd05009 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/verification_ip/interface_packages/spi_m_pkg/Makefile @@ -0,0 +1,66 @@ +# spi_m interface packages source +# pragma uvmf custom additional begin +# pragma uvmf custom additional end + +spi_m_PKG = \ + +incdir+$(UVMF_VIP_LIBRARY_HOME)/interface_packages/spi_m_pkg \ + -F $(UVMF_VIP_LIBRARY_HOME)/interface_packages/spi_m_pkg/spi_m_filelist_hvl.f + +spi_m_PKG_HDL = \ + +incdir+$(UVMF_VIP_LIBRARY_HOME)/interface_packages/spi_m_pkg \ + -F $(UVMF_VIP_LIBRARY_HOME)/interface_packages/spi_m_pkg/spi_m_filelist_hdl.f + +spi_m_PKG_XRTL = \ + +incdir+$(UVMF_VIP_LIBRARY_HOME)/interface_packages/spi_m_pkg \ + -F $(UVMF_VIP_LIBRARY_HOME)/interface_packages/spi_m_pkg/spi_m_filelist_xrtl.f + +COMP_spi_m_PKG_TGT_0 = q_comp_spi_m_pkg +COMP_spi_m_PKG_TGT_1 = v_comp_spi_m_pkg +COMP_spi_m_PKG_TGT = $(COMP_spi_m_PKG_TGT_$(USE_VELOCE)) + +comp_spi_m_pkg: $(COMP_spi_m_PKG_TGT) + +q_comp_spi_m_pkg: + $(HDL_COMP_CMD) $(spi_m_PKG_HDL) + $(HVL_COMP_CMD) $(spi_m_PKG) + $(HDL_COMP_CMD) $(spi_m_PKG_XRTL) + +v_comp_spi_m_pkg: + $(HVL_COMP_CMD) $(spi_m_PKG_HDL) + $(HVL_COMP_CMD) $(spi_m_PKG) + $(VELANALYZE_CMD) $(spi_m_PKG_HDL) + $(VELANALYZE_HVL_CMD) $(spi_m_PKG) + $(HDL_COMP_CMD) $(spi_m_PKG_XRTL) + +ifeq ($(MTI_VCO_MODE),64) + GCC_COMP_ARCH = -m64 +else + GCC_COMP_ARCH = -m32 +endif + +export spi_m_IF_DPI_SRC ?= $(UVMF_VIP_LIBRARY_HOME)/interface_packages/spi_m_pkg/dpi + +C_FILE_COMPILE_LIST_spi_m_pkg = \ + +O_FILE_COMPILE_LIST_spi_m_pkg = $(notdir $(C_FILE_COMPILE_LIST_spi_m_pkg:.c=.o)) + +GCC_COMP_ARGS_spi_m_pkg += -I$(spi_m_IF_DPI_SRC) \ + -fPIC + +GCC_COMP_ARGS_spi_m_pkg += $(spi_m_IF_GCC_COMP_ARGUMENTS) + +GCC_LINK_ARGS_spi_m_pkg += \ + \ + -o .so + +comp_spi_m_pkg_c_files: + @echo "--------------------------------" + @echo "Compiling Interface C source" + @echo "--------------------------------" + gcc $(GCC_COMP_ARCH) $(GCC_COMP_ARGS_spi_m_pkg) $(C_FILE_COMPILE_LIST_spi_m_pkg) + @echo "--------------------------------" + @echo "Linking Interface C objects into a shared object" + @echo "--------------------------------" + gcc $(GCC_COMP_ARCH) $(GCC_LINK_ARGS_spi_m_pkg) $(O_FILE_COMPILE_LIST_spi_m_pkg) + @echo "--------------------------------" + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/verification_ip/interface_packages/spi_m_pkg/compile.do b/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/verification_ip/interface_packages/spi_m_pkg/compile.do new file mode 100644 index 00000000..13f6b813 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/verification_ip/interface_packages/spi_m_pkg/compile.do @@ -0,0 +1,14 @@ +# Tcl do file for compile of spi_m interface + +# pragma uvmf custom additional begin +# pragma uvmf custom additional end + + +vlog -sv -timescale 1ps/1ps -suppress 2223,2286 +incdir+$env(UVMF_VIP_LIBRARY_HOME)/interface_packages/spi_m_pkg \ + -F $env(UVMF_VIP_LIBRARY_HOME)/interface_packages/spi_m_pkg/spi_m_filelist_hdl.f + +vlog -sv -timescale 1ps/1ps -suppress 2223,2286 +incdir+$env(UVMF_VIP_LIBRARY_HOME)/interface_packages/spi_m_pkg \ + -F $env(UVMF_VIP_LIBRARY_HOME)/interface_packages/spi_m_pkg/spi_m_filelist_hvl.f + +vlog -sv -timescale 1ps/1ps -suppress 2223,2286 +incdir+$env(UVMF_VIP_LIBRARY_HOME)/interface_packages/spi_m_pkg \ + -F $env(UVMF_VIP_LIBRARY_HOME)/interface_packages/spi_m_pkg/spi_m_filelist_xrtl.f \ No newline at end of file diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/verification_ip/interface_packages/spi_m_pkg/spi_m.compile b/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/verification_ip/interface_packages/spi_m_pkg/spi_m.compile new file mode 100644 index 00000000..6cfb1a16 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/verification_ip/interface_packages/spi_m_pkg/spi_m.compile @@ -0,0 +1,3 @@ +needs: + - spi_m_hvl.compile + - spi_m_hdl.compile diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/verification_ip/interface_packages/spi_m_pkg/spi_m_bfm.vinfo b/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/verification_ip/interface_packages/spi_m_pkg/spi_m_bfm.vinfo new file mode 100644 index 00000000..054f46b2 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/verification_ip/interface_packages/spi_m_pkg/spi_m_bfm.vinfo @@ -0,0 +1,6 @@ +@use $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg_hdl.vinfo +@use spi_m_pkg_hdl.vinfo ++incdir+@vinfodir +src/spi_m_if.sv +src/spi_m_driver_bfm.sv +src/spi_m_monitor_bfm.sv diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/verification_ip/interface_packages/spi_m_pkg/spi_m_common.compile b/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/verification_ip/interface_packages/spi_m_pkg/spi_m_common.compile new file mode 100644 index 00000000..31a2c1bc --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/verification_ip/interface_packages/spi_m_pkg/spi_m_common.compile @@ -0,0 +1,7 @@ +needs: + - $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg_hdl.compile +incdir: + - . + - ${uvm_path}/src +src: + - spi_m_pkg_hdl.sv diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/verification_ip/interface_packages/spi_m_pkg/spi_m_filelist_hdl.f b/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/verification_ip/interface_packages/spi_m_pkg/spi_m_filelist_hdl.f new file mode 100644 index 00000000..952ce3e3 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/verification_ip/interface_packages/spi_m_pkg/spi_m_filelist_hdl.f @@ -0,0 +1 @@ +$UVMF_VIP_LIBRARY_HOME/interface_packages/spi_m_pkg/spi_m_pkg_hdl.sv diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/verification_ip/interface_packages/spi_m_pkg/spi_m_filelist_hvl.f b/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/verification_ip/interface_packages/spi_m_pkg/spi_m_filelist_hvl.f new file mode 100644 index 00000000..f7b45778 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/verification_ip/interface_packages/spi_m_pkg/spi_m_filelist_hvl.f @@ -0,0 +1 @@ +$UVMF_VIP_LIBRARY_HOME/interface_packages/spi_m_pkg/spi_m_pkg.sv \ No newline at end of file diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/verification_ip/interface_packages/spi_m_pkg/spi_m_filelist_xrtl.f b/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/verification_ip/interface_packages/spi_m_pkg/spi_m_filelist_xrtl.f new file mode 100644 index 00000000..996b7bf9 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/verification_ip/interface_packages/spi_m_pkg/spi_m_filelist_xrtl.f @@ -0,0 +1,3 @@ +$UVMF_VIP_LIBRARY_HOME/interface_packages/spi_m_pkg/src/spi_m_if.sv +$UVMF_VIP_LIBRARY_HOME/interface_packages/spi_m_pkg/src/spi_m_monitor_bfm.sv +$UVMF_VIP_LIBRARY_HOME/interface_packages/spi_m_pkg/src/spi_m_driver_bfm.sv diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/verification_ip/interface_packages/spi_m_pkg/spi_m_hdl.compile b/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/verification_ip/interface_packages/spi_m_pkg/spi_m_hdl.compile new file mode 100644 index 00000000..e0606ef0 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/verification_ip/interface_packages/spi_m_pkg/spi_m_hdl.compile @@ -0,0 +1,9 @@ +needs: + - $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg_hdl.compile + - ./spi_m_common.compile +incdir: + - . +src: + - src/spi_m_if.sv + - src/spi_m_monitor_bfm.sv + - src/spi_m_driver_bfm.sv diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/verification_ip/interface_packages/spi_m_pkg/spi_m_hvl.compile b/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/verification_ip/interface_packages/spi_m_pkg/spi_m_hvl.compile new file mode 100644 index 00000000..ef56d81f --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/verification_ip/interface_packages/spi_m_pkg/spi_m_hvl.compile @@ -0,0 +1,7 @@ +needs: + - $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg.compile + - ./spi_m_common.compile +incdir: + - . +src: + - spi_m_pkg.sv diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/verification_ip/interface_packages/spi_m_pkg/spi_m_pkg.sv b/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/verification_ip/interface_packages/spi_m_pkg/spi_m_pkg.sv new file mode 100644 index 00000000..326e87d4 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/verification_ip/interface_packages/spi_m_pkg/spi_m_pkg.sv @@ -0,0 +1,77 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// PACKAGE: This file defines all of the files contained in the +// interface package that will run on the host simulator. +// +// CONTAINS: +// - +// - +// - + +// - +// - +// - + +// - +// - +// - + +// - +// - +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +package spi_m_pkg; + + import uvm_pkg::*; + import uvmf_base_pkg_hdl::*; + import uvmf_base_pkg::*; + import spi_m_pkg_hdl::*; + + `include "uvm_macros.svh" + + // pragma uvmf custom package_imports_additional begin + // pragma uvmf custom package_imports_additional end + `include "src/spi_m_macros.svh" + + export spi_m_pkg_hdl::*; + + + + // Parameters defined as HVL parameters + + `include "src/spi_m_typedefs.svh" + `include "src/spi_m_transaction.svh" + + `include "src/spi_m_configuration.svh" + `include "src/spi_m_driver.svh" + `include "src/spi_m_monitor.svh" + + `include "src/spi_m_transaction_coverage.svh" + `include "src/spi_m_sequence_base.svh" + `include "src/spi_m_random_sequence.svh" + + `include "src/spi_m_responder_sequence.svh" + `include "src/spi_m2reg_adapter.svh" + + `include "src/spi_m_agent.svh" + + // pragma uvmf custom package_item_additional begin + // UVMF_CHANGE_ME : When adding new interface sequences to the src directory + // be sure to add the sequence file here so that it will be + // compiled as part of the interface package. Be sure to place + // the new sequence after any base sequences of the new sequence. + // pragma uvmf custom package_item_additional end + +endpackage + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/verification_ip/interface_packages/spi_m_pkg/spi_m_pkg.vinfo b/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/verification_ip/interface_packages/spi_m_pkg/spi_m_pkg.vinfo new file mode 100644 index 00000000..a05007a1 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/verification_ip/interface_packages/spi_m_pkg/spi_m_pkg.vinfo @@ -0,0 +1,4 @@ +@use $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg.vinfo +@use spi_m_pkg_hdl.vinfo ++incdir+@vinfodir +spi_m_pkg.sv diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/verification_ip/interface_packages/spi_m_pkg/spi_m_pkg_hdl.sv b/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/verification_ip/interface_packages/spi_m_pkg/spi_m_pkg_hdl.sv new file mode 100644 index 00000000..632e6786 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/verification_ip/interface_packages/spi_m_pkg/spi_m_pkg_hdl.sv @@ -0,0 +1,38 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// PACKAGE: This file defines all of the files contained in the +// interface package that needs to be compiled and synthesized +// for running on Veloce. +// +// CONTAINS: +// - +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +package spi_m_pkg_hdl; + + import uvmf_base_pkg_hdl::*; + + // pragma uvmf custom package_imports_additional begin + // pragma uvmf custom package_imports_additional end + + // Parameters defined as HDL parameters + + `include "src/spi_m_typedefs_hdl.svh" + `include "src/spi_m_macros.svh" + + // pragma uvmf custom package_item_additional begin + // pragma uvmf custom package_item_additional end + +endpackage + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/verification_ip/interface_packages/spi_m_pkg/spi_m_pkg_hdl.vinfo b/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/verification_ip/interface_packages/spi_m_pkg/spi_m_pkg_hdl.vinfo new file mode 100644 index 00000000..ed83921b --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/verification_ip/interface_packages/spi_m_pkg/spi_m_pkg_hdl.vinfo @@ -0,0 +1,2 @@ +@use $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg_hdl.vinfo +spi_m_pkg_hdl.sv diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/verification_ip/interface_packages/spi_m_pkg/spi_m_pkg_sve.F b/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/verification_ip/interface_packages/spi_m_pkg/spi_m_pkg_sve.F new file mode 100644 index 00000000..b48ecf8c --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/verification_ip/interface_packages/spi_m_pkg/spi_m_pkg_sve.F @@ -0,0 +1,10 @@ +// UVM ++incdir+${UVM_HOME}/src +${UVM_HOME}/src/uvm_pkg.sv + +// Common UVMF files +-f ${UVMF_HOME}/common/common_sve.f + ++incdir+. +-f ${UVMF_VIP_LIBRARY_HOME}/interface_packages/spi_m_pkg/spi_m_filelist_hdl.f +-f ${UVMF_VIP_LIBRARY_HOME}/interface_packages/spi_m_pkg/spi_m_filelist_hvl.f diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/verification_ip/interface_packages/spi_m_pkg/src/spi_m2reg_adapter.svh b/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/verification_ip/interface_packages/spi_m_pkg/src/spi_m2reg_adapter.svh new file mode 100644 index 00000000..800ec5da --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/verification_ip/interface_packages/spi_m_pkg/src/spi_m2reg_adapter.svh @@ -0,0 +1,98 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: +// This file contains the UVM register adapter for the spi_m interface. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class spi_m2reg_adapter extends uvm_reg_adapter; + + `uvm_object_utils( spi_m2reg_adapter ) + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + //-------------------------------------------------------------------- + // new + //-------------------------------------------------------------------- + function new (string name = "spi_m2reg_adapter" ); + super.new(name); + // pragma uvmf custom new begin + // UVMF_CHANGE_ME : Configure the adapter regarding byte enables and provides response. + + // Does the protocol the Agent is modeling support byte enables? + // 0 = NO + // 1 = YES + supports_byte_enable = 0; + + // Does the Agent's Driver provide separate response sequence items? + // i.e. Does the driver call seq_item_port.put() + // and do the sequences call get_response()? + // 0 = NO + // 1 = YES + provides_responses = 0; + // pragma uvmf custom new end + + endfunction: new + + //-------------------------------------------------------------------- + // reg2bus + //-------------------------------------------------------------------- + virtual function uvm_sequence_item reg2bus(const ref uvm_reg_bus_op rw); + + spi_m_transaction trans_h = spi_m_transaction ::type_id::create("trans_h"); + + // pragma uvmf custom reg2bus begin + // UVMF_CHANGE_ME : Fill in the reg2bus adapter mapping registe fields to protocol fields. + + //Adapt the following for your sequence item type + // trans_h.op = (rw.kind == UVM_READ) ? WB_READ : WB_WRITE; + //Copy over address + // trans_h.addr = rw.addr; + //Copy over write data + // trans_h.data = rw.data; + + // pragma uvmf custom reg2bus end + + // Return the adapted transaction + return trans_h; + + endfunction: reg2bus + + //-------------------------------------------------------------------- + // bus2reg + //-------------------------------------------------------------------- + virtual function void bus2reg(uvm_sequence_item bus_item, + ref uvm_reg_bus_op rw); + spi_m_transaction trans_h; + if (!$cast(trans_h, bus_item)) begin + `uvm_fatal("ADAPT","Provided bus_item is not of the correct type") + return; + end + // pragma uvmf custom bus2reg begin + // UVMF_CHANGE_ME : Fill in the bus2reg adapter mapping protocol fields to register fields. + //Adapt the following for your sequence item type + //Copy over instruction type + // rw.kind = (trans_h.op == WB_WRITE) ? UVM_WRITE : UVM_READ; + //Copy over address + // rw.addr = trans_h.addr; + //Copy over read data + // rw.data = trans_h.data; + //Check for errors on the bus and return UVM_NOT_OK if there is an error + // rw.status = UVM_IS_OK; + // pragma uvmf custom bus2reg end + + endfunction: bus2reg + +endclass : spi_m2reg_adapter + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/verification_ip/interface_packages/spi_m_pkg/src/spi_m_agent.svh b/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/verification_ip/interface_packages/spi_m_pkg/src/spi_m_agent.svh new file mode 100644 index 00000000..99c5d200 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/verification_ip/interface_packages/spi_m_pkg/src/spi_m_agent.svh @@ -0,0 +1,53 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: Protocol specific agent class definition +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class spi_m_agent extends uvmf_parameterized_agent #( + .CONFIG_T(spi_m_configuration ), + .DRIVER_T(spi_m_driver ), + .MONITOR_T(spi_m_monitor ), + .COVERAGE_T(spi_m_transaction_coverage ), + .TRANS_T(spi_m_transaction ) + ); + + `uvm_component_utils( spi_m_agent ) + +// pragma uvmf custom class_item_additional begin +// pragma uvmf custom class_item_additional end + +// **************************************************************************** +// FUNCTION : new() +// This function is the standard SystemVerilog constructor. +// + function new( string name = "", uvm_component parent = null ); + super.new( name, parent ); + endfunction + +// **************************************************************************** + // FUNCTION: build_phase + virtual function void build_phase(uvm_phase phase); +// pragma uvmf custom build_phase_pre_super begin +// pragma uvmf custom build_phase_pre_super end + super.build_phase(phase); + if (configuration.active_passive == ACTIVE) begin + // Place sequencer handle into configuration object + // so that it may be retrieved from configuration + // rather than using uvm_config_db + configuration.sequencer = this.sequencer; + end + endfunction + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/verification_ip/interface_packages/spi_m_pkg/src/spi_m_configuration.svh b/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/verification_ip/interface_packages/spi_m_pkg/src/spi_m_configuration.svh new file mode 100644 index 00000000..9c71a8ea --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/verification_ip/interface_packages/spi_m_pkg/src/spi_m_configuration.svh @@ -0,0 +1,179 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This class contains all variables and functions used +// to configure the spi_m agent and its bfm's. It gets the +// bfm's from the uvm_config_db for use by the agent. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class spi_m_configuration extends uvmf_parameterized_agent_configuration_base #( + .DRIVER_BFM_BIND_T(virtual spi_m_driver_bfm ), + .MONITOR_BFM_BIND_T( virtual spi_m_monitor_bfm )); + + `uvm_object_utils( spi_m_configuration ) + + + // Sequencer handle populated by agent + uvm_sequencer #(spi_m_transaction ) sequencer; + + //Constraints for the configuration variables: + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + covergroup spi_m_configuration_cg; + // pragma uvmf custom covergroup begin + option.auto_bin_max=1024; + // pragma uvmf custom covergroup end + endgroup + + //******************************************************************* + //******************************************************************* + // Structure used to pass configuration variables to monitor and driver BFM's. + // Use to_struct function to pack variables into structure. + // Use from_struct function to unpack variables from structure. + // This structure is defined in spi_m_macros.svh + `spi_m_CONFIGURATION_STRUCT + spi_m_configuration_s spi_m_configuration_struct; + //******************************************************************* + // FUNCTION: to_struct() + // This function packs variables into a spi_m_configuration_s + // structure. The function returns the handle to the spi_m_configuration_struct. + // This function is defined in spi_m_macros.svh + `spi_m_CONFIGURATION_TO_STRUCT_FUNCTION + //******************************************************************* + // FUNCTION: from_struct() + // This function unpacks the struct provided as an argument into + // variables of this class. + // This function is defined in spi_m_macros.svh + `spi_m_CONFIGURATION_FROM_STRUCT_FUNCTION + + // **************************************************************************** + // FUNCTION : new() + // This function is the standard SystemVerilog constructor. + // + function new( string name = "" ); + super.new( name ); + // Construct the covergroup for this configuration class + spi_m_configuration_cg = new; + endfunction + + // **************************************************************************** + // FUNCTION: post_randomize() + // This function is automatically called after the randomize() function + // is executed. + // + function void post_randomize(); + super.post_randomize(); + spi_m_configuration_cg.sample(); + endfunction + + // **************************************************************************** + // FUNCTION: initialize + // This function causes the configuration to retrieve + // its virtual interface handle from the uvm_config_db. + // This function also makes itself available to its + // agent through the uvm_config_db. + // + // ARGUMENTS: + // uvmf_active_passive_t activity: + // This argument identifies the simulation level + // as either BLOCK, CHIP, SIMULATION, etc. + // + // AGENT_PATH: + // This argument identifies the path to this + // configurations agent. This configuration + // makes itself available to the agent specified + // by agent_path by placing itself into the + // uvm_config_db. + // + // INTERFACE_NAME: + // This argument identifies the string name of + // this configurations BFM's. This string + // name is used to retrieve the driver and + // monitor BFM from the uvm_config_db. + // + virtual function void initialize(uvmf_active_passive_t activity, + string agent_path, + string interface_name); + + super.initialize( activity, agent_path, interface_name); + // The covergroup is given the same name as the interface + spi_m_configuration_cg.set_inst_name(interface_name); + + // This configuration places itself into the uvm_config_db for the agent, identified by the agent_path variable, to retrieve. + uvm_config_db #( spi_m_configuration + )::set( null ,agent_path,UVMF_AGENT_CONFIG, this ); + + // This configuration also places itself in the config db using the same identifier used by the interface. This allows users to access + // configuration variables and the interface through the bfm api class rather than directly accessing the BFM. This is useful for + // accessingthe BFM when using Veloce + uvm_config_db #( spi_m_configuration + )::set( null ,UVMF_CONFIGURATIONS, interface_name, this ); + + spi_m_configuration_cg.set_inst_name($sformatf("spi_m_configuration_cg_%s",get_full_name())); + +// This code is to aid in debugging parameter mismatches between the BFM and its corresponding agent. +// Enable this debug by setting UVM_VERBOSITY to UVM_DEBUG +// Setting UVM_VERBOSITY to UVM_DEBUG causes all BFM's and all agents to display their parameter settings. +// All of the messages from this feature have a UVM messaging id value of "CFG" +// The transcript or run.log can be parsed to ensure BFM parameter settings match its corresponding agents parameter settings. + `uvm_info("CFG", + $psprintf("The agent at '%s' is using interface named %s has the following parameters: ", agent_path, interface_name, ), + UVM_DEBUG) + + // pragma uvmf custom initialize begin + // This controls whether or not the agent returns a transaction handle in the driver when calling + // item_done() back into the sequencer or not. If set to 1, a transaction is sent back which means + // the sequence on the other end must use the get_response() part of the driver/sequence API. If + // this doesn't occur, there will eventually be response_queue overflow errors during the test. + return_transaction_response = 1'b0; + + // pragma uvmf custom initialize end + + endfunction + + // **************************************************************************** + // TASK: wait_for_reset + // *[Required]* Blocks until reset is released. The wait_for_reset operation is performed + // by a task in the monitor bfm. + virtual task wait_for_reset(); + monitor_bfm.wait_for_reset(); + endtask + + // **************************************************************************** + // TASK: wait_for_num_clocks + // *[Required]* Blocks until specified number of clocks have elapsed. The wait_for_num_clocks + // operation is performed by a task in the monitor bfm. + virtual task wait_for_num_clocks(int clocks); + monitor_bfm.wait_for_num_clocks(clocks); + endtask + + // **************************************************************************** + // FUNCTION : convert2string() + // This function is used to convert variables in this class into a string for log messaging. + // + virtual function string convert2string (); + // pragma uvmf custom convert2string begin + return $sformatf(""); + // pragma uvmf custom convert2string end + endfunction + + // **************************************************************************** + // FUNCTION: get_sequencer + function uvm_sequencer #(spi_m_transaction) get_sequencer(); + return sequencer; + endfunction + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/verification_ip/interface_packages/spi_m_pkg/src/spi_m_driver.svh b/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/verification_ip/interface_packages/spi_m_pkg/src/spi_m_driver.svh new file mode 100644 index 00000000..89417864 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/verification_ip/interface_packages/spi_m_pkg/src/spi_m_driver.svh @@ -0,0 +1,91 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This class passes transactions between the sequencer +// and the BFM driver interface. It accesses the driver BFM +// through the bfm handle. This driver +// passes transactions to the driver BFM through the access +// task. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class spi_m_driver extends uvmf_driver_base #( + .CONFIG_T(spi_m_configuration ), + .BFM_BIND_T(virtual spi_m_driver_bfm ), + .REQ(spi_m_transaction ), + .RSP(spi_m_transaction )); + + `uvm_component_utils( spi_m_driver ) +//******************************************************************* +// Macros that define structs located in spi_m_macros.svh +//******************************************************************* +// Initiator macro used by spi_m_driver and spi_m_driver_bfm +// to communicate initiator driven data to spi_m_driver_bfm. +`spi_m_INITIATOR_STRUCT + spi_m_initiator_s spi_m_initiator_struct; +//******************************************************************* +// Responder macro used by spi_m_driver and spi_m_driver_bfm +// to communicate Responder driven data to spi_m_driver_bfm. +`spi_m_RESPONDER_STRUCT + spi_m_responder_s spi_m_responder_struct; + +// pragma uvmf custom class_item_additional begin +// pragma uvmf custom class_item_additional end + +// **************************************************************************** +// This function is the standard SystemVerilog constructor. +// + function new( string name = "", uvm_component parent=null ); + super.new( name, parent ); + endfunction + +// **************************************************************************** +// This function sends configuration object variables to the driver BFM +// using the configuration struct. +// + virtual function void configure(input CONFIG_T cfg); + bfm.configure( cfg.to_struct() ); + endfunction + +// **************************************************************************** +// This function places a handle to this class in the proxy variable in the +// driver BFM. This allows the driver BFM to call tasks and function within this class. +// + virtual function void set_bfm_proxy_handle(); + bfm.proxy = this; endfunction + +// **************************************************************************** +// This task is called by the run_phase in uvmf_driver_base. + virtual task access( inout REQ txn ); +// pragma uvmf custom access begin + if (configuration.initiator_responder==RESPONDER) begin + // Complete current transfer and wait for next transfer + bfm.respond_and_wait_for_next_transfer( + spi_m_initiator_struct, + txn.to_responder_struct() + ); + // Unpack information about initiated transfer received by this responder + txn.from_initiator_struct(spi_m_initiator_struct); + end else begin + // Initiate a transfer and get response + bfm.initiate_and_get_response( + txn.to_initiator_struct(), + spi_m_responder_struct + ); + // Unpack transfer response information received by this initiator + txn.from_responder_struct(spi_m_responder_struct); + end +// pragma uvmf custom access end + endtask + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/verification_ip/interface_packages/spi_m_pkg/src/spi_m_driver_bfm.sv b/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/verification_ip/interface_packages/spi_m_pkg/src/spi_m_driver_bfm.sv new file mode 100644 index 00000000..7b70757a --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/verification_ip/interface_packages/spi_m_pkg/src/spi_m_driver_bfm.sv @@ -0,0 +1,300 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: +// This interface performs the spi_m signal driving. It is +// accessed by the uvm spi_m driver through a virtual interface +// handle in the spi_m configuration. It drives the singals passed +// in through the port connection named bus of type spi_m_if. +// +// Input signals from the spi_m_if are assigned to an internal input +// signal with a _i suffix. The _i signal should be used for sampling. +// +// The input signal connections are as follows: +// bus.signal -> signal_i +// +// This bfm drives signals with a _o suffix. These signals +// are driven onto signals within spi_m_if based on INITIATOR/RESPONDER and/or +// ARBITRATION/GRANT status. +// +// The output signal connections are as follows: +// signal_o -> bus.signal +// +// +// Interface functions and tasks used by UVM components: +// +// configure: +// This function gets configuration attributes from the +// UVM driver to set any required BFM configuration +// variables such as 'initiator_responder'. +// +// initiate_and_get_response: +// This task is used to perform signaling activity for initiating +// a protocol transfer. The task initiates the transfer, using +// input data from the initiator struct. Then the task captures +// response data, placing the data into the response struct. +// The response struct is returned to the driver class. +// +// respond_and_wait_for_next_transfer: +// This task is used to complete a current transfer as a responder +// and then wait for the initiator to start the next transfer. +// The task uses data in the responder struct to drive protocol +// signals to complete the transfer. The task then waits for +// the next transfer. Once the next transfer begins, data from +// the initiator is placed into the initiator struct and sent +// to the responder sequence for processing to determine +// what data to respond with. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +import uvmf_base_pkg_hdl::*; +import spi_m_pkg_hdl::*; +`include "src/spi_m_macros.svh" + +interface spi_m_driver_bfm + (spi_m_if bus); + // The following pragma and additional ones in-lined further below are for running this BFM on Veloce + // pragma attribute spi_m_driver_bfm partition_interface_xif + +`ifndef XRTL +// This code is to aid in debugging parameter mismatches between the BFM and its corresponding agent. +// Enable this debug by setting UVM_VERBOSITY to UVM_DEBUG +// Setting UVM_VERBOSITY to UVM_DEBUG causes all BFM's and all agents to display their parameter settings. +// All of the messages from this feature have a UVM messaging id value of "CFG" +// The transcript or run.log can be parsed to ensure BFM parameter settings match its corresponding agents parameter settings. +import uvm_pkg::*; +`include "uvm_macros.svh" +initial begin : bfm_vs_agent_parameter_debug + `uvm_info("CFG", + $psprintf("The BFM at '%m' has the following parameters: ", ), + UVM_DEBUG) +end +`endif + + // Config value to determine if this is an initiator or a responder + uvmf_initiator_responder_t initiator_responder; + // Custom configuration variables. + // These are set using the configure function which is called during the UVM connect_phase + + logic sck_i; + logic rst_i; + + // Signal list (all signals are capable of being inputs and outputs for the sake + // of supporting both INITIATOR and RESPONDER mode operation. Expectation is that + // directionality in the config file was from the point-of-view of the INITIATOR + + // INITIATOR mode input signals + tri [7:0] miso_i; + reg [7:0] miso_o = 'b0; + + // INITIATOR mode output signals + tri sclk_i; + reg sclk_o = 'b0; + tri ss_i; + reg ss_o = 'b0; + tri [7:0] mosi_i; + reg [7:0] mosi_o = 'b0; + + // Bi-directional signals + + + assign sck_i = bus.sck; + assign rst_i = bus.rst; + + // These are signals marked as 'input' by the config file, but the signals will be + // driven by this BFM if put into RESPONDER mode (flipping all signal directions around) + assign miso_i = bus.miso; + assign bus.miso = (initiator_responder == RESPONDER) ? miso_o : 'bz; + + + // These are signals marked as 'output' by the config file, but the outputs will + // not be driven by this BFM unless placed in INITIATOR mode. + assign bus.sclk = (initiator_responder == INITIATOR) ? sclk_o : 'bz; + assign sclk_i = bus.sclk; + assign bus.ss = (initiator_responder == INITIATOR) ? ss_o : 'bz; + assign ss_i = bus.ss; + assign bus.mosi = (initiator_responder == INITIATOR) ? mosi_o : 'bz; + assign mosi_i = bus.mosi; + + // Proxy handle to UVM driver + spi_m_pkg::spi_m_driver proxy; + // pragma tbx oneway proxy.my_function_name_in_uvm_driver + + // **************************************************************************** + // **************************************************************************** + // Macros that define structs located in spi_m_macros.svh + // **************************************************************************** + // Struct for passing configuration data from spi_m_driver to this BFM + // **************************************************************************** + `spi_m_CONFIGURATION_STRUCT + // **************************************************************************** + // Structs for INITIATOR and RESPONDER data flow + //******************************************************************* + // Initiator macro used by spi_m_driver and spi_m_driver_bfm + // to communicate initiator driven data to spi_m_driver_bfm. + `spi_m_INITIATOR_STRUCT + spi_m_initiator_s initiator_struct; + // Responder macro used by spi_m_driver and spi_m_driver_bfm + // to communicate Responder driven data to spi_m_driver_bfm. + `spi_m_RESPONDER_STRUCT + spi_m_responder_s responder_struct; + + // **************************************************************************** +// pragma uvmf custom reset_condition_and_response begin + // Always block used to return signals to reset value upon assertion of reset + always @( posedge rst_i ) + begin + // RESPONDER mode output signals + miso_o <= 'b0; + // INITIATOR mode output signals + sclk_o <= 'b0; + ss_o <= 'b0; + mosi_o <= 'b0; + // Bi-directional signals + + end +// pragma uvmf custom reset_condition_and_response end + + // pragma uvmf custom interface_item_additional begin + // pragma uvmf custom interface_item_additional end + + //****************************************************************** + // The configure() function is used to pass agent configuration + // variables to the driver BFM. It is called by the driver within + // the agent at the beginning of the simulation. It may be called + // during the simulation if agent configuration variables are updated + // and the driver BFM needs to be aware of the new configuration + // variables. + // + + function void configure(spi_m_configuration_s spi_m_configuration_arg); // pragma tbx xtf + initiator_responder = spi_m_configuration_arg.initiator_responder; + // pragma uvmf custom configure begin + // pragma uvmf custom configure end + endfunction + +// pragma uvmf custom initiate_and_get_response begin +// **************************************************************************** +// UVMF_CHANGE_ME +// This task is used by an initator. The task first initiates a transfer then +// waits for the responder to complete the transfer. + task initiate_and_get_response( + // This argument passes transaction variables used by an initiator + // to perform the initial part of a protocol transfer. The values + // come from a sequence item created in a sequence. + input spi_m_initiator_s spi_m_initiator_struct, + // This argument is used to send data received from the responder + // back to the sequence item. The sequence item is returned to the sequence. + output spi_m_responder_s spi_m_responder_struct + );// pragma tbx xtf + // + // Members within the spi_m_initiator_struct: + // bit ssel ; + // bit [7:0] mosi ; + // bit [7:0] miso ; + // Members within the spi_m_responder_struct: + // bit ssel ; + // bit [7:0] mosi ; + // bit [7:0] miso ; + initiator_struct = spi_m_initiator_struct; + // + // Reference code; + // How to wait for signal value + // while (control_signal == 1'b1) @(posedge sck_i); + // + // How to assign a responder struct member, named xyz, from a signal. + // All available initiator input and inout signals listed. + // Initiator input signals + // spi_m_responder_struct.xyz = miso_i; // [7:0] + // Initiator inout signals + // How to assign a signal from an initiator struct member named xyz. + // All available initiator output and inout signals listed. + // Notice the _o. Those are storage variables that allow for procedural assignment. + // Initiator output signals + // sclk_o <= spi_m_initiator_struct.xyz; // + // ss_o <= spi_m_initiator_struct.xyz; // + // mosi_o <= spi_m_initiator_struct.xyz; // [7:0] + // Initiator inout signals + // Initiate a transfer using the data received. + @(posedge sck_i); + @(posedge sck_i); + // Wait for the responder to complete the transfer then place the responder data into + // spi_m_responder_struct. + @(posedge sck_i); + @(posedge sck_i); + responder_struct = spi_m_responder_struct; + endtask +// pragma uvmf custom initiate_and_get_response end + +// pragma uvmf custom respond_and_wait_for_next_transfer begin +// **************************************************************************** +// The first_transfer variable is used to prevent completing a transfer in the +// first call to this task. For the first call to this task, there is not +// current transfer to complete. +bit first_transfer=1; + +// UVMF_CHANGE_ME +// This task is used by a responder. The task first completes the current +// transfer in progress then waits for the initiator to start the next transfer. + task respond_and_wait_for_next_transfer( + // This argument is used to send data received from the initiator + // back to the sequence item. The sequence determines how to respond. + output spi_m_initiator_s spi_m_initiator_struct, + // This argument passes transaction variables used by a responder + // to complete a protocol transfer. The values come from a sequence item. + input spi_m_responder_s spi_m_responder_struct + );// pragma tbx xtf + // Variables within the spi_m_initiator_struct: + // bit ssel ; + // bit [7:0] mosi ; + // bit [7:0] miso ; + // Variables within the spi_m_responder_struct: + // bit ssel ; + // bit [7:0] mosi ; + // bit [7:0] miso ; + // Reference code; + // How to wait for signal value + // while (control_signal == 1'b1) @(posedge sck_i); + // + // How to assign a responder struct member, named xyz, from a signal. + // All available responder input and inout signals listed. + // Responder input signals + // spi_m_responder_struct.xyz = sclk_i; // + // spi_m_responder_struct.xyz = ss_i; // + // spi_m_responder_struct.xyz = mosi_i; // [7:0] + // Responder inout signals + // How to assign a signal, named xyz, from an initiator struct member. + // All available responder output and inout signals listed. + // Notice the _o. Those are storage variables that allow for procedural assignment. + // Responder output signals + // miso_o <= spi_m_initiator_struct.xyz; // [7:0] + // Responder inout signals + + @(posedge sck_i); + if (!first_transfer) begin + // Perform transfer response here. + // Reply using data recieved in the spi_m_responder_struct. + @(posedge sck_i); + // Reply using data recieved in the transaction handle. + @(posedge sck_i); + end + // Wait for next transfer then gather info from intiator about the transfer. + // Place the data into the spi_m_initiator_struct. + @(posedge sck_i); + @(posedge sck_i); + first_transfer = 0; + endtask +// pragma uvmf custom respond_and_wait_for_next_transfer end + + +endinterface + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/verification_ip/interface_packages/spi_m_pkg/src/spi_m_if.sv b/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/verification_ip/interface_packages/spi_m_pkg/src/spi_m_if.sv new file mode 100644 index 00000000..3f88074f --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/verification_ip/interface_packages/spi_m_pkg/src/spi_m_if.sv @@ -0,0 +1,79 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This interface contains the spi_m interface signals. +// It is instantiated once per spi_m bus. Bus Functional Models, +// BFM's named spi_m_driver_bfm, are used to drive signals on the bus. +// BFM's named spi_m_monitor_bfm are used to monitor signals on the +// bus. This interface signal bundle is passed in the port list of +// the BFM in order to give the BFM access to the signals in this +// interface. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// This template can be used to connect a DUT to these signals +// +// .dut_signal_port(spi_m_bus.sclk), // Agent output +// .dut_signal_port(spi_m_bus.ss), // Agent output +// .dut_signal_port(spi_m_bus.mosi), // Agent output +// .dut_signal_port(spi_m_bus.miso), // Agent input + +import uvmf_base_pkg_hdl::*; +import spi_m_pkg_hdl::*; + +interface spi_m_if + + ( + input logic sck, + input logic rst, + output logic sclk, + output logic ss, + output logic [7:0] mosi, + input logic [7:0] miso + ); + +modport monitor_port + ( + input sck, + input rst, + input sclk, + input ss, + input mosi, + input miso + ); + +modport initiator_port + ( + input sck, + input rst, + output sclk, + output ss, + output mosi, + input miso + ); + +modport responder_port + ( + input sck, + input rst, + input sclk, + input ss, + input mosi, + output miso + ); + + +// pragma uvmf custom interface_item_additional begin +// pragma uvmf custom interface_item_additional end + +endinterface + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/verification_ip/interface_packages/spi_m_pkg/src/spi_m_infact_coverage_strategy.csv b/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/verification_ip/interface_packages/spi_m_pkg/src/spi_m_infact_coverage_strategy.csv new file mode 100644 index 00000000..1c218e14 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/verification_ip/interface_packages/spi_m_pkg/src/spi_m_infact_coverage_strategy.csv @@ -0,0 +1,6 @@ +Global +auto_bin_max, 64 + +Name,Type,Include +rand_fields,coverpoint,=rand *.** + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/verification_ip/interface_packages/spi_m_pkg/src/spi_m_macros.svh b/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/verification_ip/interface_packages/spi_m_pkg/src/spi_m_macros.svh new file mode 100644 index 00000000..a67d1c47 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/verification_ip/interface_packages/spi_m_pkg/src/spi_m_macros.svh @@ -0,0 +1,139 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This file contains macros used with the spi_m package. +// These macros include packed struct definitions. These structs are +// used to pass data between classes, hvl, and BFM's, hdl. Use of +// structs are more efficient and simpler to modify. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// + +// **************************************************************************** +// When changing the contents of this struct, be sure to update the to_struct +// and from_struct methods defined in the macros below that are used in +// the spi_m_configuration class. +// + `define spi_m_CONFIGURATION_STRUCT \ +typedef struct packed { \ + uvmf_active_passive_t active_passive; \ + uvmf_initiator_responder_t initiator_responder; \ + } spi_m_configuration_s; + + `define spi_m_CONFIGURATION_TO_STRUCT_FUNCTION \ + virtual function spi_m_configuration_s to_struct();\ + spi_m_configuration_struct = \ + {\ + this.active_passive,\ + this.initiator_responder\ + };\ + return ( spi_m_configuration_struct );\ + endfunction + + `define spi_m_CONFIGURATION_FROM_STRUCT_FUNCTION \ + virtual function void from_struct(spi_m_configuration_s spi_m_configuration_struct);\ + {\ + this.active_passive,\ + this.initiator_responder \ + } = spi_m_configuration_struct;\ + endfunction + +// **************************************************************************** +// When changing the contents of this struct, be sure to update the to_monitor_struct +// and from_monitor_struct methods of the spi_m_transaction class. +// + `define spi_m_MONITOR_STRUCT typedef struct packed { \ + bit ssel ; \ + bit [7:0] mosi ; \ + bit [7:0] miso ; \ + } spi_m_monitor_s; + + `define spi_m_TO_MONITOR_STRUCT_FUNCTION \ + virtual function spi_m_monitor_s to_monitor_struct();\ + spi_m_monitor_struct = \ + { \ + this.ssel , \ + this.mosi , \ + this.miso \ + };\ + return ( spi_m_monitor_struct);\ + endfunction\ + + `define spi_m_FROM_MONITOR_STRUCT_FUNCTION \ + virtual function void from_monitor_struct(spi_m_monitor_s spi_m_monitor_struct);\ + {\ + this.ssel , \ + this.mosi , \ + this.miso \ + } = spi_m_monitor_struct;\ + endfunction + +// **************************************************************************** +// When changing the contents of this struct, be sure to update the to_initiator_struct +// and from_initiator_struct methods of the spi_m_transaction class. +// Also update the comments in the driver BFM. +// + `define spi_m_INITIATOR_STRUCT typedef struct packed { \ + bit ssel ; \ + bit [7:0] mosi ; \ + bit [7:0] miso ; \ + } spi_m_initiator_s; + + `define spi_m_TO_INITIATOR_STRUCT_FUNCTION \ + virtual function spi_m_initiator_s to_initiator_struct();\ + spi_m_initiator_struct = \ + {\ + this.ssel , \ + this.mosi , \ + this.miso \ + };\ + return ( spi_m_initiator_struct);\ + endfunction + + `define spi_m_FROM_INITIATOR_STRUCT_FUNCTION \ + virtual function void from_initiator_struct(spi_m_initiator_s spi_m_initiator_struct);\ + {\ + this.ssel , \ + this.mosi , \ + this.miso \ + } = spi_m_initiator_struct;\ + endfunction + +// **************************************************************************** +// When changing the contents of this struct, be sure to update the to_responder_struct +// and from_responder_struct methods of the spi_m_transaction class. +// Also update the comments in the driver BFM. +// + `define spi_m_RESPONDER_STRUCT typedef struct packed { \ + bit ssel ; \ + bit [7:0] mosi ; \ + bit [7:0] miso ; \ + } spi_m_responder_s; + + `define spi_m_TO_RESPONDER_STRUCT_FUNCTION \ + virtual function spi_m_responder_s to_responder_struct();\ + spi_m_responder_struct = \ + {\ + this.ssel , \ + this.mosi , \ + this.miso \ + };\ + return ( spi_m_responder_struct);\ + endfunction + + `define spi_m_FROM_RESPONDER_STRUCT_FUNCTION \ + virtual function void from_responder_struct(spi_m_responder_s spi_m_responder_struct);\ + {\ + this.ssel , \ + this.mosi , \ + this.miso \ + } = spi_m_responder_struct;\ + endfunction +// pragma uvmf custom additional begin +// pragma uvmf custom additional end diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/verification_ip/interface_packages/spi_m_pkg/src/spi_m_monitor.svh b/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/verification_ip/interface_packages/spi_m_pkg/src/spi_m_monitor.svh new file mode 100644 index 00000000..594666de --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/verification_ip/interface_packages/spi_m_pkg/src/spi_m_monitor.svh @@ -0,0 +1,87 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This class receives spi_m transactions observed by the +// spi_m monitor BFM and broadcasts them through the analysis port +// on the agent. It accesses the monitor BFM through the monitor +// task. This UVM component captures transactions +// for viewing in the waveform viewer if the +// enable_transaction_viewing flag is set in the configuration. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class spi_m_monitor extends uvmf_monitor_base #( + .CONFIG_T(spi_m_configuration ), + .BFM_BIND_T(virtual spi_m_monitor_bfm ), + .TRANS_T(spi_m_transaction )); + + `uvm_component_utils( spi_m_monitor ) + +// Structure used to pass data from monitor BFM to monitor class in agent. +// Use to_monitor_struct function to pack transaction variables into structure. +// Use from_monitor_struct function to unpack transaction variables from structure. +`spi_m_MONITOR_STRUCT + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + +// **************************************************************************** +// This function is the standard SystemVerilog constructor. +// + function new( string name = "", uvm_component parent = null ); + super.new( name, parent ); + endfunction + +// **************************************************************************** +// This function sends configuration object variables to the monitor BFM +// using the configuration struct. +// + virtual function void configure(input CONFIG_T cfg); + bfm.configure( cfg.to_struct() ); + + endfunction + +// **************************************************************************** +// This function places a handle to this class in the proxy variable in the +// monitor BFM. This allows the monitor BFM to call the notify_transaction +// function within this class. +// + virtual function void set_bfm_proxy_handle(); + bfm.proxy = this; endfunction + +// *************************************************************************** + virtual task run_phase(uvm_phase phase); + // Start monitor BFM thread and don't call super.run() in order to + // override the default monitor proxy 'pull' behavior with the more + // emulation-friendly BFM 'push' approach using the notify_transaction + // function below + bfm.start_monitoring(); + endtask + +// ************************************************************************** + +// This function is called by the monitor BFM. It receives data observed by the +// monitor BFM. Data is passed using the spi_m_monitor_struct. + virtual function void notify_transaction(input spi_m_monitor_s spi_m_monitor_struct); + + + trans = new("trans"); + trans.from_monitor_struct(spi_m_monitor_struct); + trans.start_time = time_stamp; + trans.end_time = $time; + time_stamp = trans.end_time; + + analyze(trans); + endfunction + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/verification_ip/interface_packages/spi_m_pkg/src/spi_m_monitor_bfm.sv b/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/verification_ip/interface_packages/spi_m_pkg/src/spi_m_monitor_bfm.sv new file mode 100644 index 00000000..c727952e --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/verification_ip/interface_packages/spi_m_pkg/src/spi_m_monitor_bfm.sv @@ -0,0 +1,185 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This interface performs the spi_m signal monitoring. +// It is accessed by the uvm spi_m monitor through a virtual +// interface handle in the spi_m configuration. It monitors the +// signals passed in through the port connection named bus of +// type spi_m_if. +// +// Input signals from the spi_m_if are assigned to an internal input +// signal with a _i suffix. The _i signal should be used for sampling. +// +// The input signal connections are as follows: +// bus.signal -> signal_i +// +// Interface functions and tasks used by UVM components: +// monitor(inout TRANS_T txn); +// This task receives the transaction, txn, from the +// UVM monitor and then populates variables in txn +// from values observed on bus activity. This task +// blocks until an operation on the spi_m bus is complete. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +import uvmf_base_pkg_hdl::*; +import spi_m_pkg_hdl::*; +`include "src/spi_m_macros.svh" + + +interface spi_m_monitor_bfm + ( spi_m_if bus ); + // The pragma below and additional ones in-lined further down are for running this BFM on Veloce + // pragma attribute spi_m_monitor_bfm partition_interface_xif + +`ifndef XRTL +// This code is to aid in debugging parameter mismatches between the BFM and its corresponding agent. +// Enable this debug by setting UVM_VERBOSITY to UVM_DEBUG +// Setting UVM_VERBOSITY to UVM_DEBUG causes all BFM's and all agents to display their parameter settings. +// All of the messages from this feature have a UVM messaging id value of "CFG" +// The transcript or run.log can be parsed to ensure BFM parameter settings match its corresponding agents parameter settings. +import uvm_pkg::*; +`include "uvm_macros.svh" +initial begin : bfm_vs_agent_parameter_debug + `uvm_info("CFG", + $psprintf("The BFM at '%m' has the following parameters: ", ), + UVM_DEBUG) +end +`endif + + + // Structure used to pass transaction data from monitor BFM to monitor class in agent. +`spi_m_MONITOR_STRUCT + spi_m_monitor_s spi_m_monitor_struct; + + // Structure used to pass configuration data from monitor class to monitor BFM. + `spi_m_CONFIGURATION_STRUCT + + + // Config value to determine if this is an initiator or a responder + uvmf_initiator_responder_t initiator_responder; + // Custom configuration variables. + // These are set using the configure function which is called during the UVM connect_phase + + logic sck_i; + logic rst_i; + tri sclk_i; + tri ss_i; + tri [7:0] mosi_i; + tri [7:0] miso_i; + assign sck_i = bus.sck; + assign rst_i = bus.rst; + assign sclk_i = bus.sclk; + assign ss_i = bus.ss; + assign mosi_i = bus.mosi; + assign miso_i = bus.miso; + + // Proxy handle to UVM monitor + spi_m_pkg::spi_m_monitor proxy; + // pragma tbx oneway proxy.notify_transaction + + // pragma uvmf custom interface_item_additional begin + // pragma uvmf custom interface_item_additional end + + //****************************************************************** + task wait_for_reset();// pragma tbx xtf + @(posedge sck_i) ; + do_wait_for_reset(); + endtask + + // **************************************************************************** + task do_wait_for_reset(); + // pragma uvmf custom reset_condition begin + wait ( rst_i === 0 ) ; + @(posedge sck_i) ; + // pragma uvmf custom reset_condition end + endtask + + //****************************************************************** + + task wait_for_num_clocks(input int unsigned count); // pragma tbx xtf + @(posedge sck_i); + + repeat (count-1) @(posedge sck_i); + endtask + + //****************************************************************** + event go; + function void start_monitoring();// pragma tbx xtf + -> go; + endfunction + + // **************************************************************************** + initial begin + @go; + forever begin + @(posedge sck_i); + do_monitor( spi_m_monitor_struct ); + + + proxy.notify_transaction( spi_m_monitor_struct ); + + end + end + + //****************************************************************** + // The configure() function is used to pass agent configuration + // variables to the monitor BFM. It is called by the monitor within + // the agent at the beginning of the simulation. It may be called + // during the simulation if agent configuration variables are updated + // and the monitor BFM needs to be aware of the new configuration + // variables. + // + function void configure(spi_m_configuration_s spi_m_configuration_arg); // pragma tbx xtf + initiator_responder = spi_m_configuration_arg.initiator_responder; + // pragma uvmf custom configure begin + // pragma uvmf custom configure end + endfunction + + + // **************************************************************************** + + task do_monitor(output spi_m_monitor_s spi_m_monitor_struct); + // + // Available struct members: + // // spi_m_monitor_struct.ssel + // // spi_m_monitor_struct.mosi + // // spi_m_monitor_struct.miso + // // + // Reference code; + // How to wait for signal value + // while (control_signal === 1'b1) @(posedge sck_i); + // + // How to assign a struct member, named xyz, from a signal. + // All available input signals listed. + // spi_m_monitor_struct.xyz = sclk_i; // + // spi_m_monitor_struct.xyz = ss_i; // + // spi_m_monitor_struct.xyz = mosi_i; // [7:0] + // spi_m_monitor_struct.xyz = miso_i; // [7:0] + // pragma uvmf custom do_monitor begin + // UVMF_CHANGE_ME : Implement protocol monitoring. The commented reference code + // below are examples of how to capture signal values and assign them to + // structure members. All available input signals are listed. The 'while' + // code example shows how to wait for a synchronous flow control signal. This + // task should return when a complete transfer has been observed. Once this task is + // exited with captured values, it is then called again to wait for and observe + // the next transfer. One clock cycle is consumed between calls to do_monitor. + @(posedge sck_i); + @(posedge sck_i); + @(posedge sck_i); + @(posedge sck_i); + // pragma uvmf custom do_monitor end + endtask + + +endinterface + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/verification_ip/interface_packages/spi_m_pkg/src/spi_m_random_sequence.svh b/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/verification_ip/interface_packages/spi_m_pkg/src/spi_m_random_sequence.svh new file mode 100644 index 00000000..53962025 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/verification_ip/interface_packages/spi_m_pkg/src/spi_m_random_sequence.svh @@ -0,0 +1,53 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: +// This sequences randomizes the spi_m transaction and sends it +// to the UVM driver. +// +// This sequence constructs and randomizes a spi_m_transaction. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class spi_m_random_sequence + extends spi_m_sequence_base ; + + `uvm_object_utils( spi_m_random_sequence ) + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + //***************************************************************** + function new(string name = ""); + super.new(name); + endfunction: new + + // **************************************************************************** + // TASK : body() + // This task is automatically executed when this sequence is started using the + // start(sequencerHandle) task. + // + task body(); + + // Construct the transaction + req=spi_m_transaction::type_id::create("req"); + start_item(req); + // Randomize the transaction + if(!req.randomize()) `uvm_fatal("SEQ", "spi_m_random_sequence::body()-spi_m_transaction randomization failed") + // Send the transaction to the spi_m_driver_bfm via the sequencer and spi_m_driver. + finish_item(req); + `uvm_info("SEQ", {"Response:",req.convert2string()},UVM_MEDIUM) + + endtask + +endclass: spi_m_random_sequence + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/verification_ip/interface_packages/spi_m_pkg/src/spi_m_responder_sequence.svh b/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/verification_ip/interface_packages/spi_m_pkg/src/spi_m_responder_sequence.svh new file mode 100644 index 00000000..ee97f025 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/verification_ip/interface_packages/spi_m_pkg/src/spi_m_responder_sequence.svh @@ -0,0 +1,49 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This class can be used to provide stimulus when an interface +// has been configured to run in a responder mode. It +// will never finish by default, always going back to the driver +// and driver BFM for the next transaction with which to respond. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class spi_m_responder_sequence + extends spi_m_sequence_base ; + + `uvm_object_utils( spi_m_responder_sequence ) + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + function new(string name = "spi_m_responder_sequence"); + super.new(name); + endfunction + + task body(); + req=spi_m_transaction::type_id::create("req"); + forever begin + start_item(req); + finish_item(req); + // pragma uvmf custom body begin + // UVMF_CHANGE_ME : Do something here with the resulting req item. The + // finish_item() call above will block until the req transaction is ready + // to be handled by the responder sequence. + // If this was an item that required a response, the expectation is + // that the response should be populated within this transaction now. + `uvm_info("SEQ",$sformatf("Processed txn: %s",req.convert2string()),UVM_HIGH) + // pragma uvmf custom body end + end + endtask + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/verification_ip/interface_packages/spi_m_pkg/src/spi_m_sequence_base.svh b/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/verification_ip/interface_packages/spi_m_pkg/src/spi_m_sequence_base.svh new file mode 100644 index 00000000..d603b978 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/verification_ip/interface_packages/spi_m_pkg/src/spi_m_sequence_base.svh @@ -0,0 +1,96 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: +// This file contains the class used as the base class for all sequences +// for this interface. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class spi_m_sequence_base extends uvmf_sequence_base #( + .REQ(spi_m_transaction ), + .RSP(spi_m_transaction )); + + `uvm_object_utils( spi_m_sequence_base ) + + // variables + typedef spi_m_transaction spi_m_transaction_req_t; + spi_m_transaction_req_t req; + typedef spi_m_transaction spi_m_transaction_rsp_t; + spi_m_transaction_rsp_t rsp; + + // Event for identifying when a response was received from the sequencer + event new_rsp; + + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + // **************************************************************************** + // TASK : get_responses() + // This task recursively gets sequence item responses from the sequencer. + // + virtual task get_responses(); + fork + begin + // Block until new rsp available + get_response(rsp); + // New rsp received. Indicate to sequence using event. + ->new_rsp; + // Display the received response transaction + `uvm_info("SEQ", {"New response transaction:",rsp.convert2string()}, UVM_MEDIUM) + end + join_none + endtask + + // **************************************************************************** + // TASK : pre_body() + // This task is called automatically when start is called with call_pre_post set to 1 (default). + // By calling get_responses() within pre_body() any derived sequences are automatically + // processing response transactions. Only un-comment this call to get_responses() if you + // have configured the interface driver to utilize the response transaction path by setting + // the configuration variable "return_transaction_response" to 1. Otherwise it is possible + // to impact runtime performance and memory utilization. + // + virtual task pre_body(); + // pragma uvmf custom pre_body begin +// get_responses(); + // pragma uvmf custom pre_body end + endtask + + // **************************************************************************** + // TASK : body() + // This task is called automatically when start is called. This sequence sends + // a req sequence item to the sequencer identified as an argument in the call + // to start. + // + virtual task body(); + // pragma uvmf custom body begin + start_item(req); + finish_item(req); + // pragma uvmf custom body end + endtask + + // **************************************************************************** + // FUNCTION : new() + // This function is the standard SystemVerilog constructor. + // + function new( string name =""); + super.new( name ); + // pragma uvmf custom new begin + req = spi_m_transaction_req_t::type_id::create("req"); + rsp = spi_m_transaction_rsp_t::type_id::create("rsp"); + // pragma uvmf custom new end + endfunction + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/verification_ip/interface_packages/spi_m_pkg/src/spi_m_transaction.svh b/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/verification_ip/interface_packages/spi_m_pkg/src/spi_m_transaction.svh new file mode 100644 index 00000000..99a7fd1c --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/verification_ip/interface_packages/spi_m_pkg/src/spi_m_transaction.svh @@ -0,0 +1,190 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This class defines the variables required for an spi_m +// transaction. Class variables to be displayed in waveform transaction +// viewing are added to the transaction viewing stream in the add_to_wave +// function. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class spi_m_transaction extends uvmf_transaction_base; + + `uvm_object_utils( spi_m_transaction ) + + rand bit ssel ; + rand bit [7:0] mosi ; + bit [7:0] miso ; + + //Constraints for the transaction variables: + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + //******************************************************************* + //******************************************************************* + // Macros that define structs and associated functions are + // located in spi_m_macros.svh + + //******************************************************************* + // Monitor macro used by spi_m_monitor and spi_m_monitor_bfm + // This struct is defined in spi_m_macros.svh + `spi_m_MONITOR_STRUCT + spi_m_monitor_s spi_m_monitor_struct; + //******************************************************************* + // FUNCTION: to_monitor_struct() + // This function packs transaction variables into a spi_m_monitor_s + // structure. The function returns the handle to the spi_m_monitor_struct. + // This function is defined in spi_m_macros.svh + `spi_m_TO_MONITOR_STRUCT_FUNCTION + //******************************************************************* + // FUNCTION: from_monitor_struct() + // This function unpacks the struct provided as an argument into transaction + // variables of this class. + // This function is defined in spi_m_macros.svh + `spi_m_FROM_MONITOR_STRUCT_FUNCTION + + //******************************************************************* + // Initiator macro used by spi_m_driver and spi_m_driver_bfm + // to communicate initiator driven data to spi_m_driver_bfm. + // This struct is defined in spi_m_macros.svh + `spi_m_INITIATOR_STRUCT + spi_m_initiator_s spi_m_initiator_struct; + //******************************************************************* + // FUNCTION: to_initiator_struct() + // This function packs transaction variables into a spi_m_initiator_s + // structure. The function returns the handle to the spi_m_initiator_struct. + // This function is defined in spi_m_macros.svh + `spi_m_TO_INITIATOR_STRUCT_FUNCTION + //******************************************************************* + // FUNCTION: from_initiator_struct() + // This function unpacks the struct provided as an argument into transaction + // variables of this class. + // This function is defined in spi_m_macros.svh + `spi_m_FROM_INITIATOR_STRUCT_FUNCTION + + //******************************************************************* + // Responder macro used by spi_m_driver and spi_m_driver_bfm + // to communicate Responder driven data to spi_m_driver_bfm. + // This struct is defined in spi_m_macros.svh + `spi_m_RESPONDER_STRUCT + spi_m_responder_s spi_m_responder_struct; + //******************************************************************* + // FUNCTION: to_responder_struct() + // This function packs transaction variables into a spi_m_responder_s + // structure. The function returns the handle to the spi_m_responder_struct. + // This function is defined in spi_m_macros.svh + `spi_m_TO_RESPONDER_STRUCT_FUNCTION + //******************************************************************* + // FUNCTION: from_responder_struct() + // This function unpacks the struct provided as an argument into transaction + // variables of this class. + // This function is defined in spi_m_macros.svh + `spi_m_FROM_RESPONDER_STRUCT_FUNCTION + // **************************************************************************** + // FUNCTION : new() + // This function is the standard SystemVerilog constructor. + // + function new( string name = "" ); + super.new( name ); + endfunction + + // **************************************************************************** + // FUNCTION: convert2string() + // This function converts all variables in this class to a single string for + // logfile reporting. + // + virtual function string convert2string(); + // pragma uvmf custom convert2string begin + // UVMF_CHANGE_ME : Customize format if desired. + return $sformatf("ssel:0x%x mosi:0x%x miso:0x%x ",ssel,mosi,miso); + // pragma uvmf custom convert2string end + endfunction + + //******************************************************************* + // FUNCTION: do_print() + // This function is automatically called when the .print() function + // is called on this class. + // + virtual function void do_print(uvm_printer printer); + // pragma uvmf custom do_print begin + // UVMF_CHANGE_ME : Current contents of do_print allows for the use of UVM 1.1d, 1.2 or P1800.2. + // Update based on your own printing preference according to your preferred UVM version + $display(convert2string()); + // pragma uvmf custom do_print end + endfunction + + //******************************************************************* + // FUNCTION: do_compare() + // This function is automatically called when the .compare() function + // is called on this class. + // + virtual function bit do_compare (uvm_object rhs, uvm_comparer comparer); + spi_m_transaction RHS; + if (!$cast(RHS,rhs)) return 0; + // pragma uvmf custom do_compare begin + // UVMF_CHANGE_ME : Eliminate comparison of variables not to be used for compare + return (super.do_compare(rhs,comparer) + &&(this.ssel == RHS.ssel) + &&(this.mosi == RHS.mosi) + &&(this.miso == RHS.miso) + ); + // pragma uvmf custom do_compare end + endfunction + + //******************************************************************* + // FUNCTION: do_copy() + // This function is automatically called when the .copy() function + // is called on this class. + // + virtual function void do_copy (uvm_object rhs); + spi_m_transaction RHS; + assert($cast(RHS,rhs)); + // pragma uvmf custom do_copy begin + super.do_copy(rhs); + this.ssel = RHS.ssel; + this.mosi = RHS.mosi; + this.miso = RHS.miso; + // pragma uvmf custom do_copy end + endfunction + + // **************************************************************************** + // FUNCTION: add_to_wave() + // This function is used to display variables in this class in the waveform + // viewer. The start_time and end_time variables must be set before this + // function is called. If the start_time and end_time variables are not set + // the transaction will be hidden at 0ns on the waveform display. + // + virtual function void add_to_wave(int transaction_viewing_stream_h); + `ifdef QUESTA + if (transaction_view_h == 0) begin + transaction_view_h = $begin_transaction(transaction_viewing_stream_h,"spi_m_transaction",start_time); + end + super.add_to_wave(transaction_view_h); + // pragma uvmf custom add_to_wave begin + // UVMF_CHANGE_ME : Color can be applied to transaction entries based on content, example below + // case() + // 1 : $add_color(transaction_view_h,"red"); + // default : $add_color(transaction_view_h,"grey"); + // endcase + // UVMF_CHANGE_ME : Eliminate transaction variables not wanted in transaction viewing in the waveform viewer + $add_attribute(transaction_view_h,ssel,"ssel"); + $add_attribute(transaction_view_h,mosi,"mosi"); + $add_attribute(transaction_view_h,miso,"miso"); + // pragma uvmf custom add_to_wave end + $end_transaction(transaction_view_h,end_time); + $free_transaction(transaction_view_h); + `endif // QUESTA + endfunction + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/verification_ip/interface_packages/spi_m_pkg/src/spi_m_transaction_coverage.svh b/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/verification_ip/interface_packages/spi_m_pkg/src/spi_m_transaction_coverage.svh new file mode 100644 index 00000000..95cda794 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/verification_ip/interface_packages/spi_m_pkg/src/spi_m_transaction_coverage.svh @@ -0,0 +1,72 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This class records spi_m transaction information using +// a covergroup named spi_m_transaction_cg. An instance of this +// coverage component is instantiated in the uvmf_parameterized_agent +// if the has_coverage flag is set. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class spi_m_transaction_coverage extends uvm_subscriber #(.T(spi_m_transaction )); + + `uvm_component_utils( spi_m_transaction_coverage ) + + T coverage_trans; + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + // **************************************************************************** + covergroup spi_m_transaction_cg; + // pragma uvmf custom covergroup begin + // UVMF_CHANGE_ME : Add coverage bins, crosses, exclusions, etc. according to coverage needs. + option.auto_bin_max=1024; + option.per_instance=1; + ssel: coverpoint coverage_trans.ssel; + mosi: coverpoint coverage_trans.mosi; + miso: coverpoint coverage_trans.miso; + // pragma uvmf custom covergroup end + endgroup + + // **************************************************************************** + // FUNCTION : new() + // This function is the standard SystemVerilog constructor. + // + function new(string name="", uvm_component parent=null); + super.new(name,parent); + spi_m_transaction_cg=new; + `uvm_warning("COVERAGE_MODEL_REVIEW", "A covergroup has been constructed which may need review because of either generation or re-generation with merging. Please note that transaction variables added as a result of re-generation and merging are not automatically added to the covergroup. Remove this warning after the covergroup has been reviewed.") + endfunction + + // **************************************************************************** + // FUNCTION : build_phase() + // This function is the standard UVM build_phase. + // + function void build_phase(uvm_phase phase); + spi_m_transaction_cg.set_inst_name($sformatf("spi_m_transaction_cg_%s",get_full_name())); + endfunction + + // **************************************************************************** + // FUNCTION: write (T t) + // This function is automatically executed when a transaction arrives on the + // analysis_export. It copies values from the variables in the transaction + // to local variables used to collect functional coverage. + // + virtual function void write (T t); + `uvm_info("COV","Received transaction",UVM_HIGH); + coverage_trans = t; + spi_m_transaction_cg.sample(); + endfunction + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/verification_ip/interface_packages/spi_m_pkg/src/spi_m_typedefs.svh b/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/verification_ip/interface_packages/spi_m_pkg/src/spi_m_typedefs.svh new file mode 100644 index 00000000..43d85640 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/verification_ip/interface_packages/spi_m_pkg/src/spi_m_typedefs.svh @@ -0,0 +1,20 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: +// This file contains defines and typedefs to be compiled for use in +// the simulation running on the host server when using Veloce. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// + + +// pragma uvmf custom additional begin +// pragma uvmf custom additional end + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/verification_ip/interface_packages/spi_m_pkg/src/spi_m_typedefs_hdl.svh b/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/verification_ip/interface_packages/spi_m_pkg/src/spi_m_typedefs_hdl.svh new file mode 100644 index 00000000..74738c8c --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/verification_ip/interface_packages/spi_m_pkg/src/spi_m_typedefs_hdl.svh @@ -0,0 +1,21 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: +// This file contains defines and typedefs to be compiled for use in +// the simulation running on the emulator when using Veloce. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// + + + +// pragma uvmf custom additional begin +// pragma uvmf custom additional end + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/verification_ip/interface_packages/spi_m_pkg/yaml/spi_m_interface.yaml b/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/verification_ip/interface_packages/spi_m_pkg/yaml/spi_m_interface.yaml new file mode 100644 index 00000000..1eca4f64 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/verification_ip/interface_packages/spi_m_pkg/yaml/spi_m_interface.yaml @@ -0,0 +1,53 @@ +uvmf: + interfaces: + spi_m: + clock: sck + config_constraints: [] + config_vars: [] + existing_library_component: 'True' + gen_inbound_streaming_driver: 'False' + hdl_pkg_parameters: [] + hdl_typedefs: [] + hvl_pkg_parameters: [] + hvl_typedefs: [] + parameters: [] + ports: + - dir: output + name: sclk + reset_value: '''b0' + width: '1' + - dir: output + name: ss + reset_value: '''b0' + width: '1' + - dir: output + name: mosi + reset_value: '''b0' + width: '8' + - dir: input + name: miso + reset_value: '''b0' + width: '8' + reset: rst + reset_assertion_level: 'True' + transaction_constraints: [] + transaction_vars: + - comment: '' + iscompare: 'True' + isrand: 'True' + name: ssel + type: bit + unpacked_dimension: '' + - comment: '' + iscompare: 'True' + isrand: 'True' + name: mosi + type: bit [7:0] + unpacked_dimension: '' + - comment: '' + iscompare: 'True' + isrand: 'False' + name: miso + type: bit [7:0] + unpacked_dimension: '' + use_dpi_link: 'False' diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/verification_ip/interface_packages/wb_s_pkg/.project b/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/verification_ip/interface_packages/wb_s_pkg/.project new file mode 100644 index 00000000..d9963c6a --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/verification_ip/interface_packages/wb_s_pkg/.project @@ -0,0 +1,30 @@ + + + wb_s_pkg + + + + + + org.python.pydev.PyDevBuilder + + + + + net.sf.sveditor.core.SVProjectBuilder + + + + + + net.sf.sveditor.core.SVNature + org.python.pydev.pythonNature + + + + UVMF_VIP_LIBRARY_HOME + $%7BPARENT-2-PROJECT_LOC%7D + + + + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/verification_ip/interface_packages/wb_s_pkg/.svproject b/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/verification_ip/interface_packages/wb_s_pkg/.svproject new file mode 100644 index 00000000..0edf84a9 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/verification_ip/interface_packages/wb_s_pkg/.svproject @@ -0,0 +1,16 @@ + + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/verification_ip/interface_packages/wb_s_pkg/Makefile b/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/verification_ip/interface_packages/wb_s_pkg/Makefile new file mode 100644 index 00000000..2ccf8e80 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/verification_ip/interface_packages/wb_s_pkg/Makefile @@ -0,0 +1,66 @@ +# wb_s interface packages source +# pragma uvmf custom additional begin +# pragma uvmf custom additional end + +wb_s_PKG = \ + +incdir+$(UVMF_VIP_LIBRARY_HOME)/interface_packages/wb_s_pkg \ + -F $(UVMF_VIP_LIBRARY_HOME)/interface_packages/wb_s_pkg/wb_s_filelist_hvl.f + +wb_s_PKG_HDL = \ + +incdir+$(UVMF_VIP_LIBRARY_HOME)/interface_packages/wb_s_pkg \ + -F $(UVMF_VIP_LIBRARY_HOME)/interface_packages/wb_s_pkg/wb_s_filelist_hdl.f + +wb_s_PKG_XRTL = \ + +incdir+$(UVMF_VIP_LIBRARY_HOME)/interface_packages/wb_s_pkg \ + -F $(UVMF_VIP_LIBRARY_HOME)/interface_packages/wb_s_pkg/wb_s_filelist_xrtl.f + +COMP_wb_s_PKG_TGT_0 = q_comp_wb_s_pkg +COMP_wb_s_PKG_TGT_1 = v_comp_wb_s_pkg +COMP_wb_s_PKG_TGT = $(COMP_wb_s_PKG_TGT_$(USE_VELOCE)) + +comp_wb_s_pkg: $(COMP_wb_s_PKG_TGT) + +q_comp_wb_s_pkg: + $(HDL_COMP_CMD) $(wb_s_PKG_HDL) + $(HVL_COMP_CMD) $(wb_s_PKG) + $(HDL_COMP_CMD) $(wb_s_PKG_XRTL) + +v_comp_wb_s_pkg: + $(HVL_COMP_CMD) $(wb_s_PKG_HDL) + $(HVL_COMP_CMD) $(wb_s_PKG) + $(VELANALYZE_CMD) $(wb_s_PKG_HDL) + $(VELANALYZE_HVL_CMD) $(wb_s_PKG) + $(HDL_COMP_CMD) $(wb_s_PKG_XRTL) + +ifeq ($(MTI_VCO_MODE),64) + GCC_COMP_ARCH = -m64 +else + GCC_COMP_ARCH = -m32 +endif + +export wb_s_IF_DPI_SRC ?= $(UVMF_VIP_LIBRARY_HOME)/interface_packages/wb_s_pkg/dpi + +C_FILE_COMPILE_LIST_wb_s_pkg = \ + +O_FILE_COMPILE_LIST_wb_s_pkg = $(notdir $(C_FILE_COMPILE_LIST_wb_s_pkg:.c=.o)) + +GCC_COMP_ARGS_wb_s_pkg += -I$(wb_s_IF_DPI_SRC) \ + -fPIC + +GCC_COMP_ARGS_wb_s_pkg += $(wb_s_IF_GCC_COMP_ARGUMENTS) + +GCC_LINK_ARGS_wb_s_pkg += \ + \ + -o .so + +comp_wb_s_pkg_c_files: + @echo "--------------------------------" + @echo "Compiling Interface C source" + @echo "--------------------------------" + gcc $(GCC_COMP_ARCH) $(GCC_COMP_ARGS_wb_s_pkg) $(C_FILE_COMPILE_LIST_wb_s_pkg) + @echo "--------------------------------" + @echo "Linking Interface C objects into a shared object" + @echo "--------------------------------" + gcc $(GCC_COMP_ARCH) $(GCC_LINK_ARGS_wb_s_pkg) $(O_FILE_COMPILE_LIST_wb_s_pkg) + @echo "--------------------------------" + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/verification_ip/interface_packages/wb_s_pkg/compile.do b/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/verification_ip/interface_packages/wb_s_pkg/compile.do new file mode 100644 index 00000000..55cf9dcd --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/verification_ip/interface_packages/wb_s_pkg/compile.do @@ -0,0 +1,14 @@ +# Tcl do file for compile of wb_s interface + +# pragma uvmf custom additional begin +# pragma uvmf custom additional end + + +vlog -sv -timescale 1ps/1ps -suppress 2223,2286 +incdir+$env(UVMF_VIP_LIBRARY_HOME)/interface_packages/wb_s_pkg \ + -F $env(UVMF_VIP_LIBRARY_HOME)/interface_packages/wb_s_pkg/wb_s_filelist_hdl.f + +vlog -sv -timescale 1ps/1ps -suppress 2223,2286 +incdir+$env(UVMF_VIP_LIBRARY_HOME)/interface_packages/wb_s_pkg \ + -F $env(UVMF_VIP_LIBRARY_HOME)/interface_packages/wb_s_pkg/wb_s_filelist_hvl.f + +vlog -sv -timescale 1ps/1ps -suppress 2223,2286 +incdir+$env(UVMF_VIP_LIBRARY_HOME)/interface_packages/wb_s_pkg \ + -F $env(UVMF_VIP_LIBRARY_HOME)/interface_packages/wb_s_pkg/wb_s_filelist_xrtl.f \ No newline at end of file diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/verification_ip/interface_packages/wb_s_pkg/src/wb_s2reg_adapter.svh b/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/verification_ip/interface_packages/wb_s_pkg/src/wb_s2reg_adapter.svh new file mode 100644 index 00000000..b8230f45 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/verification_ip/interface_packages/wb_s_pkg/src/wb_s2reg_adapter.svh @@ -0,0 +1,113 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: +// This file contains the UVM register adapter for the wb_s interface. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class wb_s2reg_adapter #( + int WB_ADDR_WIDTH = 32, + int WB_DATA_WIDTH = 16 + ) extends uvm_reg_adapter; + + `uvm_object_param_utils( wb_s2reg_adapter #( + WB_ADDR_WIDTH, + WB_DATA_WIDTH + )) + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + //-------------------------------------------------------------------- + // new + //-------------------------------------------------------------------- + function new (string name = "wb_s2reg_adapter" ); + super.new(name); + // pragma uvmf custom new begin + // UVMF_CHANGE_ME : Configure the adapter regarding byte enables and provides response. + + // Does the protocol the Agent is modeling support byte enables? + // 0 = NO + // 1 = YES + supports_byte_enable = 0; + + // Does the Agent's Driver provide separate response sequence items? + // i.e. Does the driver call seq_item_port.put() + // and do the sequences call get_response()? + // 0 = NO + // 1 = YES + provides_responses = 0; + // pragma uvmf custom new end + + endfunction: new + + //-------------------------------------------------------------------- + // reg2bus + //-------------------------------------------------------------------- + virtual function uvm_sequence_item reg2bus(const ref uvm_reg_bus_op rw); + + wb_s_transaction #( + .WB_ADDR_WIDTH(WB_ADDR_WIDTH), + .WB_DATA_WIDTH(WB_DATA_WIDTH) + ) trans_h = wb_s_transaction #( + .WB_ADDR_WIDTH(WB_ADDR_WIDTH), + .WB_DATA_WIDTH(WB_DATA_WIDTH) + )::type_id::create("trans_h"); + + // pragma uvmf custom reg2bus begin + // UVMF_CHANGE_ME : Fill in the reg2bus adapter mapping registe fields to protocol fields. + + //Adapt the following for your sequence item type + // trans_h.op = (rw.kind == UVM_READ) ? WB_READ : WB_WRITE; + //Copy over address + // trans_h.addr = rw.addr; + //Copy over write data + // trans_h.data = rw.data; + + // pragma uvmf custom reg2bus end + + // Return the adapted transaction + return trans_h; + + endfunction: reg2bus + + //-------------------------------------------------------------------- + // bus2reg + //-------------------------------------------------------------------- + virtual function void bus2reg(uvm_sequence_item bus_item, + ref uvm_reg_bus_op rw); + wb_s_transaction #( + .WB_ADDR_WIDTH(WB_ADDR_WIDTH), + .WB_DATA_WIDTH(WB_DATA_WIDTH) + ) trans_h; + if (!$cast(trans_h, bus_item)) begin + `uvm_fatal("ADAPT","Provided bus_item is not of the correct type") + return; + end + // pragma uvmf custom bus2reg begin + // UVMF_CHANGE_ME : Fill in the bus2reg adapter mapping protocol fields to register fields. + //Adapt the following for your sequence item type + //Copy over instruction type + // rw.kind = (trans_h.op == WB_WRITE) ? UVM_WRITE : UVM_READ; + //Copy over address + // rw.addr = trans_h.addr; + //Copy over read data + // rw.data = trans_h.data; + //Check for errors on the bus and return UVM_NOT_OK if there is an error + // rw.status = UVM_IS_OK; + // pragma uvmf custom bus2reg end + + endfunction: bus2reg + +endclass : wb_s2reg_adapter + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/verification_ip/interface_packages/wb_s_pkg/src/wb_s_agent.svh b/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/verification_ip/interface_packages/wb_s_pkg/src/wb_s_agent.svh new file mode 100644 index 00000000..de099f9c --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/verification_ip/interface_packages/wb_s_pkg/src/wb_s_agent.svh @@ -0,0 +1,74 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: Protocol specific agent class definition +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class wb_s_agent #( + int WB_ADDR_WIDTH = 32, + int WB_DATA_WIDTH = 16 + ) extends uvmf_parameterized_agent #( + .CONFIG_T(wb_s_configuration #( + .WB_ADDR_WIDTH(WB_ADDR_WIDTH), + .WB_DATA_WIDTH(WB_DATA_WIDTH) + )), + .DRIVER_T(wb_s_driver #( + .WB_ADDR_WIDTH(WB_ADDR_WIDTH), + .WB_DATA_WIDTH(WB_DATA_WIDTH) + )), + .MONITOR_T(wb_s_monitor #( + .WB_ADDR_WIDTH(WB_ADDR_WIDTH), + .WB_DATA_WIDTH(WB_DATA_WIDTH) + )), + .COVERAGE_T(wb_s_transaction_coverage #( + .WB_ADDR_WIDTH(WB_ADDR_WIDTH), + .WB_DATA_WIDTH(WB_DATA_WIDTH) + )), + .TRANS_T(wb_s_transaction #( + .WB_ADDR_WIDTH(WB_ADDR_WIDTH), + .WB_DATA_WIDTH(WB_DATA_WIDTH) + )) + ); + + `uvm_component_param_utils( wb_s_agent #( + WB_ADDR_WIDTH, + WB_DATA_WIDTH + )) + +// pragma uvmf custom class_item_additional begin +// pragma uvmf custom class_item_additional end + +// **************************************************************************** +// FUNCTION : new() +// This function is the standard SystemVerilog constructor. +// + function new( string name = "", uvm_component parent = null ); + super.new( name, parent ); + endfunction + +// **************************************************************************** + // FUNCTION: build_phase + virtual function void build_phase(uvm_phase phase); +// pragma uvmf custom build_phase_pre_super begin +// pragma uvmf custom build_phase_pre_super end + super.build_phase(phase); + if (configuration.active_passive == ACTIVE) begin + // Place sequencer handle into configuration object + // so that it may be retrieved from configuration + // rather than using uvm_config_db + configuration.sequencer = this.sequencer; + end + endfunction + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/verification_ip/interface_packages/wb_s_pkg/src/wb_s_configuration.svh b/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/verification_ip/interface_packages/wb_s_pkg/src/wb_s_configuration.svh new file mode 100644 index 00000000..bb3d38e1 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/verification_ip/interface_packages/wb_s_pkg/src/wb_s_configuration.svh @@ -0,0 +1,203 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This class contains all variables and functions used +// to configure the wb_s agent and its bfm's. It gets the +// bfm's from the uvm_config_db for use by the agent. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class wb_s_configuration #( + int WB_ADDR_WIDTH = 32, + int WB_DATA_WIDTH = 16 + ) extends uvmf_parameterized_agent_configuration_base #( + .DRIVER_BFM_BIND_T(virtual wb_s_driver_bfm #( + .WB_ADDR_WIDTH(WB_ADDR_WIDTH), + .WB_DATA_WIDTH(WB_DATA_WIDTH) + )), + .MONITOR_BFM_BIND_T( virtual wb_s_monitor_bfm #( + .WB_ADDR_WIDTH(WB_ADDR_WIDTH), + .WB_DATA_WIDTH(WB_DATA_WIDTH) + ))); + + `uvm_object_param_utils( wb_s_configuration #( + WB_ADDR_WIDTH, + WB_DATA_WIDTH + )) + + + // Sequencer handle populated by agent + uvm_sequencer #(wb_s_transaction #( + .WB_ADDR_WIDTH(WB_ADDR_WIDTH), + .WB_DATA_WIDTH(WB_DATA_WIDTH) + ) ) sequencer; + + //Constraints for the configuration variables: + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + covergroup wb_s_configuration_cg; + // pragma uvmf custom covergroup begin + option.auto_bin_max=1024; + // pragma uvmf custom covergroup end + endgroup + + //******************************************************************* + //******************************************************************* + // Structure used to pass configuration variables to monitor and driver BFM's. + // Use to_struct function to pack variables into structure. + // Use from_struct function to unpack variables from structure. + // This structure is defined in wb_s_macros.svh + `wb_s_CONFIGURATION_STRUCT + wb_s_configuration_s wb_s_configuration_struct; + //******************************************************************* + // FUNCTION: to_struct() + // This function packs variables into a wb_s_configuration_s + // structure. The function returns the handle to the wb_s_configuration_struct. + // This function is defined in wb_s_macros.svh + `wb_s_CONFIGURATION_TO_STRUCT_FUNCTION + //******************************************************************* + // FUNCTION: from_struct() + // This function unpacks the struct provided as an argument into + // variables of this class. + // This function is defined in wb_s_macros.svh + `wb_s_CONFIGURATION_FROM_STRUCT_FUNCTION + + // **************************************************************************** + // FUNCTION : new() + // This function is the standard SystemVerilog constructor. + // + function new( string name = "" ); + super.new( name ); + // Construct the covergroup for this configuration class + wb_s_configuration_cg = new; + endfunction + + // **************************************************************************** + // FUNCTION: post_randomize() + // This function is automatically called after the randomize() function + // is executed. + // + function void post_randomize(); + super.post_randomize(); + wb_s_configuration_cg.sample(); + endfunction + + // **************************************************************************** + // FUNCTION: initialize + // This function causes the configuration to retrieve + // its virtual interface handle from the uvm_config_db. + // This function also makes itself available to its + // agent through the uvm_config_db. + // + // ARGUMENTS: + // uvmf_active_passive_t activity: + // This argument identifies the simulation level + // as either BLOCK, CHIP, SIMULATION, etc. + // + // AGENT_PATH: + // This argument identifies the path to this + // configurations agent. This configuration + // makes itself available to the agent specified + // by agent_path by placing itself into the + // uvm_config_db. + // + // INTERFACE_NAME: + // This argument identifies the string name of + // this configurations BFM's. This string + // name is used to retrieve the driver and + // monitor BFM from the uvm_config_db. + // + virtual function void initialize(uvmf_active_passive_t activity, + string agent_path, + string interface_name); + + super.initialize( activity, agent_path, interface_name); + // The covergroup is given the same name as the interface + wb_s_configuration_cg.set_inst_name(interface_name); + + // This configuration places itself into the uvm_config_db for the agent, identified by the agent_path variable, to retrieve. + uvm_config_db #( wb_s_configuration #( + .WB_ADDR_WIDTH(WB_ADDR_WIDTH), + .WB_DATA_WIDTH(WB_DATA_WIDTH) + ) + )::set( null ,agent_path,UVMF_AGENT_CONFIG, this ); + + // This configuration also places itself in the config db using the same identifier used by the interface. This allows users to access + // configuration variables and the interface through the bfm api class rather than directly accessing the BFM. This is useful for + // accessingthe BFM when using Veloce + uvm_config_db #( wb_s_configuration #( + .WB_ADDR_WIDTH(WB_ADDR_WIDTH), + .WB_DATA_WIDTH(WB_DATA_WIDTH) + ) + )::set( null ,UVMF_CONFIGURATIONS, interface_name, this ); + + wb_s_configuration_cg.set_inst_name($sformatf("wb_s_configuration_cg_%s",get_full_name())); + +// This code is to aid in debugging parameter mismatches between the BFM and its corresponding agent. +// Enable this debug by setting UVM_VERBOSITY to UVM_DEBUG +// Setting UVM_VERBOSITY to UVM_DEBUG causes all BFM's and all agents to display their parameter settings. +// All of the messages from this feature have a UVM messaging id value of "CFG" +// The transcript or run.log can be parsed to ensure BFM parameter settings match its corresponding agents parameter settings. + `uvm_info("CFG", + $psprintf("The agent at '%s' is using interface named %s has the following parameters: WB_ADDR_WIDTH=%x WB_DATA_WIDTH=%x ", agent_path, interface_name, WB_ADDR_WIDTH ,WB_DATA_WIDTH ), + UVM_DEBUG) + + // pragma uvmf custom initialize begin + // This controls whether or not the agent returns a transaction handle in the driver when calling + // item_done() back into the sequencer or not. If set to 1, a transaction is sent back which means + // the sequence on the other end must use the get_response() part of the driver/sequence API. If + // this doesn't occur, there will eventually be response_queue overflow errors during the test. + return_transaction_response = 1'b0; + + // pragma uvmf custom initialize end + + endfunction + + // **************************************************************************** + // TASK: wait_for_reset + // *[Required]* Blocks until reset is released. The wait_for_reset operation is performed + // by a task in the monitor bfm. + virtual task wait_for_reset(); + monitor_bfm.wait_for_reset(); + endtask + + // **************************************************************************** + // TASK: wait_for_num_clocks + // *[Required]* Blocks until specified number of clocks have elapsed. The wait_for_num_clocks + // operation is performed by a task in the monitor bfm. + virtual task wait_for_num_clocks(int clocks); + monitor_bfm.wait_for_num_clocks(clocks); + endtask + + // **************************************************************************** + // FUNCTION : convert2string() + // This function is used to convert variables in this class into a string for log messaging. + // + virtual function string convert2string (); + // pragma uvmf custom convert2string begin + return $sformatf(""); + // pragma uvmf custom convert2string end + endfunction + + // **************************************************************************** + // FUNCTION: get_sequencer + function uvm_sequencer #(wb_s_transaction#( + .WB_ADDR_WIDTH(WB_ADDR_WIDTH), + .WB_DATA_WIDTH(WB_DATA_WIDTH) + )) get_sequencer(); + return sequencer; + endfunction + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/verification_ip/interface_packages/wb_s_pkg/src/wb_s_driver.svh b/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/verification_ip/interface_packages/wb_s_pkg/src/wb_s_driver.svh new file mode 100644 index 00000000..af5bd8e1 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/verification_ip/interface_packages/wb_s_pkg/src/wb_s_driver.svh @@ -0,0 +1,109 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This class passes transactions between the sequencer +// and the BFM driver interface. It accesses the driver BFM +// through the bfm handle. This driver +// passes transactions to the driver BFM through the access +// task. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class wb_s_driver #( + int WB_ADDR_WIDTH = 32, + int WB_DATA_WIDTH = 16 + ) extends uvmf_driver_base #( + .CONFIG_T(wb_s_configuration #( + .WB_ADDR_WIDTH(WB_ADDR_WIDTH), + .WB_DATA_WIDTH(WB_DATA_WIDTH) + ) ), + .BFM_BIND_T(virtual wb_s_driver_bfm #( + .WB_ADDR_WIDTH(WB_ADDR_WIDTH), + .WB_DATA_WIDTH(WB_DATA_WIDTH) + ) ), + .REQ(wb_s_transaction #( + .WB_ADDR_WIDTH(WB_ADDR_WIDTH), + .WB_DATA_WIDTH(WB_DATA_WIDTH) + ) ), + .RSP(wb_s_transaction #( + .WB_ADDR_WIDTH(WB_ADDR_WIDTH), + .WB_DATA_WIDTH(WB_DATA_WIDTH) + ) )); + + `uvm_component_param_utils( wb_s_driver #( + WB_ADDR_WIDTH, + WB_DATA_WIDTH + )) +//******************************************************************* +// Macros that define structs located in wb_s_macros.svh +//******************************************************************* +// Initiator macro used by wb_s_driver and wb_s_driver_bfm +// to communicate initiator driven data to wb_s_driver_bfm. +`wb_s_INITIATOR_STRUCT + wb_s_initiator_s wb_s_initiator_struct; +//******************************************************************* +// Responder macro used by wb_s_driver and wb_s_driver_bfm +// to communicate Responder driven data to wb_s_driver_bfm. +`wb_s_RESPONDER_STRUCT + wb_s_responder_s wb_s_responder_struct; + +// pragma uvmf custom class_item_additional begin +// pragma uvmf custom class_item_additional end + +// **************************************************************************** +// This function is the standard SystemVerilog constructor. +// + function new( string name = "", uvm_component parent=null ); + super.new( name, parent ); + endfunction + +// **************************************************************************** +// This function sends configuration object variables to the driver BFM +// using the configuration struct. +// + virtual function void configure(input CONFIG_T cfg); + bfm.configure( cfg.to_struct() ); + endfunction + +// **************************************************************************** +// This function places a handle to this class in the proxy variable in the +// driver BFM. This allows the driver BFM to call tasks and function within this class. +// + virtual function void set_bfm_proxy_handle(); + bfm.proxy = this; endfunction + +// **************************************************************************** +// This task is called by the run_phase in uvmf_driver_base. + virtual task access( inout REQ txn ); +// pragma uvmf custom access begin + if (configuration.initiator_responder==RESPONDER) begin + // Complete current transfer and wait for next transfer + bfm.respond_and_wait_for_next_transfer( + wb_s_initiator_struct, + txn.to_responder_struct() + ); + // Unpack information about initiated transfer received by this responder + txn.from_initiator_struct(wb_s_initiator_struct); + end else begin + // Initiate a transfer and get response + bfm.initiate_and_get_response( + txn.to_initiator_struct(), + wb_s_responder_struct + ); + // Unpack transfer response information received by this initiator + txn.from_responder_struct(wb_s_responder_struct); + end +// pragma uvmf custom access end + endtask + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/verification_ip/interface_packages/wb_s_pkg/src/wb_s_driver_bfm.sv b/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/verification_ip/interface_packages/wb_s_pkg/src/wb_s_driver_bfm.sv new file mode 100644 index 00000000..4acfa6a7 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/verification_ip/interface_packages/wb_s_pkg/src/wb_s_driver_bfm.sv @@ -0,0 +1,347 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: +// This interface performs the wb_s signal driving. It is +// accessed by the uvm wb_s driver through a virtual interface +// handle in the wb_s configuration. It drives the singals passed +// in through the port connection named bus of type wb_s_if. +// +// Input signals from the wb_s_if are assigned to an internal input +// signal with a _i suffix. The _i signal should be used for sampling. +// +// The input signal connections are as follows: +// bus.signal -> signal_i +// +// This bfm drives signals with a _o suffix. These signals +// are driven onto signals within wb_s_if based on INITIATOR/RESPONDER and/or +// ARBITRATION/GRANT status. +// +// The output signal connections are as follows: +// signal_o -> bus.signal +// +// +// Interface functions and tasks used by UVM components: +// +// configure: +// This function gets configuration attributes from the +// UVM driver to set any required BFM configuration +// variables such as 'initiator_responder'. +// +// initiate_and_get_response: +// This task is used to perform signaling activity for initiating +// a protocol transfer. The task initiates the transfer, using +// input data from the initiator struct. Then the task captures +// response data, placing the data into the response struct. +// The response struct is returned to the driver class. +// +// respond_and_wait_for_next_transfer: +// This task is used to complete a current transfer as a responder +// and then wait for the initiator to start the next transfer. +// The task uses data in the responder struct to drive protocol +// signals to complete the transfer. The task then waits for +// the next transfer. Once the next transfer begins, data from +// the initiator is placed into the initiator struct and sent +// to the responder sequence for processing to determine +// what data to respond with. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +import uvmf_base_pkg_hdl::*; +import wb_s_pkg_hdl::*; +`include "src/wb_s_macros.svh" + +interface wb_s_driver_bfm #( + int WB_ADDR_WIDTH = 32, + int WB_DATA_WIDTH = 16 + ) + (wb_s_if bus); + // The following pragma and additional ones in-lined further below are for running this BFM on Veloce + // pragma attribute wb_s_driver_bfm partition_interface_xif + +`ifndef XRTL +// This code is to aid in debugging parameter mismatches between the BFM and its corresponding agent. +// Enable this debug by setting UVM_VERBOSITY to UVM_DEBUG +// Setting UVM_VERBOSITY to UVM_DEBUG causes all BFM's and all agents to display their parameter settings. +// All of the messages from this feature have a UVM messaging id value of "CFG" +// The transcript or run.log can be parsed to ensure BFM parameter settings match its corresponding agents parameter settings. +import uvm_pkg::*; +`include "uvm_macros.svh" +initial begin : bfm_vs_agent_parameter_debug + `uvm_info("CFG", + $psprintf("The BFM at '%m' has the following parameters: WB_ADDR_WIDTH=%x WB_DATA_WIDTH=%x ", WB_ADDR_WIDTH,WB_DATA_WIDTH), + UVM_DEBUG) +end +`endif + + // Config value to determine if this is an initiator or a responder + uvmf_initiator_responder_t initiator_responder; + // Custom configuration variables. + // These are set using the configure function which is called during the UVM connect_phase + + logic clock_i; + logic reset_i; + + // Signal list (all signals are capable of being inputs and outputs for the sake + // of supporting both INITIATOR and RESPONDER mode operation. Expectation is that + // directionality in the config file was from the point-of-view of the INITIATOR + + // INITIATOR mode input signals + tri [WB_DATA_WIDTH-1:0] din_i; + reg [WB_DATA_WIDTH-1:0] din_o = 'b0; + tri [WB_DATA_WIDTH-1:0] TGD_I_i; + reg [WB_DATA_WIDTH-1:0] TGD_I_o = 'bz; + tri [WB_ADDR_WIDTH-1:0] adr_i; + reg [WB_ADDR_WIDTH-1:0] adr_o = 'b0; + tri cyc_i; + reg cyc_o = 0; + tri we_i; + reg we_o = 0; + tri stb_i; + reg stb_o = 0; + tri [WB_DATA_WIDTH/8-1:0] sel_i; + reg [WB_DATA_WIDTH/8-1:0] sel_o = 'b0; + + // INITIATOR mode output signals + tri [WB_DATA_WIDTH-1:0] dout_i; + reg [WB_DATA_WIDTH-1:0] dout_o = 'b0; + tri [WB_DATA_WIDTH-1:0] TGD_O_i; + reg [WB_DATA_WIDTH-1:0] TGD_O_o = 'bz; + tri ack_i; + reg ack_o = 'b0; + tri err_i; + reg err_o = 'b0; + + // Bi-directional signals + + + assign clock_i = bus.clock; + assign reset_i = bus.reset; + + // These are signals marked as 'input' by the config file, but the signals will be + // driven by this BFM if put into RESPONDER mode (flipping all signal directions around) + assign din_i = bus.din; + assign bus.din = (initiator_responder == RESPONDER) ? din_o : 'bz; + assign TGD_I_i = bus.TGD_I; + assign bus.TGD_I = (initiator_responder == RESPONDER) ? TGD_I_o : 'bz; + assign adr_i = bus.adr; + assign bus.adr = (initiator_responder == RESPONDER) ? adr_o : 'bz; + assign cyc_i = bus.cyc; + assign bus.cyc = (initiator_responder == RESPONDER) ? cyc_o : 'bz; + assign we_i = bus.we; + assign bus.we = (initiator_responder == RESPONDER) ? we_o : 'bz; + assign stb_i = bus.stb; + assign bus.stb = (initiator_responder == RESPONDER) ? stb_o : 'bz; + assign sel_i = bus.sel; + assign bus.sel = (initiator_responder == RESPONDER) ? sel_o : 'bz; + + + // These are signals marked as 'output' by the config file, but the outputs will + // not be driven by this BFM unless placed in INITIATOR mode. + assign bus.dout = (initiator_responder == INITIATOR) ? dout_o : 'bz; + assign dout_i = bus.dout; + assign bus.TGD_O = (initiator_responder == INITIATOR) ? TGD_O_o : 'bz; + assign TGD_O_i = bus.TGD_O; + assign bus.ack = (initiator_responder == INITIATOR) ? ack_o : 'bz; + assign ack_i = bus.ack; + assign bus.err = (initiator_responder == INITIATOR) ? err_o : 'bz; + assign err_i = bus.err; + + // Proxy handle to UVM driver + wb_s_pkg::wb_s_driver #( + .WB_ADDR_WIDTH(WB_ADDR_WIDTH), + .WB_DATA_WIDTH(WB_DATA_WIDTH) + ) proxy; + // pragma tbx oneway proxy.my_function_name_in_uvm_driver + + // **************************************************************************** + // **************************************************************************** + // Macros that define structs located in wb_s_macros.svh + // **************************************************************************** + // Struct for passing configuration data from wb_s_driver to this BFM + // **************************************************************************** + `wb_s_CONFIGURATION_STRUCT + // **************************************************************************** + // Structs for INITIATOR and RESPONDER data flow + //******************************************************************* + // Initiator macro used by wb_s_driver and wb_s_driver_bfm + // to communicate initiator driven data to wb_s_driver_bfm. + `wb_s_INITIATOR_STRUCT + wb_s_initiator_s initiator_struct; + // Responder macro used by wb_s_driver and wb_s_driver_bfm + // to communicate Responder driven data to wb_s_driver_bfm. + `wb_s_RESPONDER_STRUCT + wb_s_responder_s responder_struct; + + // **************************************************************************** +// pragma uvmf custom reset_condition_and_response begin + // Always block used to return signals to reset value upon assertion of reset + always @( posedge reset_i ) + begin + // RESPONDER mode output signals + din_o <= 'b0; + TGD_I_o <= 'bz; + adr_o <= 'b0; + cyc_o <= 0; + we_o <= 0; + stb_o <= 0; + sel_o <= 'b0; + // INITIATOR mode output signals + dout_o <= 'b0; + TGD_O_o <= 'bz; + ack_o <= 'b0; + err_o <= 'b0; + // Bi-directional signals + + end +// pragma uvmf custom reset_condition_and_response end + + // pragma uvmf custom interface_item_additional begin + // pragma uvmf custom interface_item_additional end + + //****************************************************************** + // The configure() function is used to pass agent configuration + // variables to the driver BFM. It is called by the driver within + // the agent at the beginning of the simulation. It may be called + // during the simulation if agent configuration variables are updated + // and the driver BFM needs to be aware of the new configuration + // variables. + // + + function void configure(wb_s_configuration_s wb_s_configuration_arg); // pragma tbx xtf + initiator_responder = wb_s_configuration_arg.initiator_responder; + // pragma uvmf custom configure begin + // pragma uvmf custom configure end + endfunction + +// pragma uvmf custom initiate_and_get_response begin +// **************************************************************************** +// UVMF_CHANGE_ME +// This task is used by an initator. The task first initiates a transfer then +// waits for the responder to complete the transfer. + task initiate_and_get_response( + // This argument passes transaction variables used by an initiator + // to perform the initial part of a protocol transfer. The values + // come from a sequence item created in a sequence. + input wb_s_initiator_s wb_s_initiator_struct, + // This argument is used to send data received from the responder + // back to the sequence item. The sequence item is returned to the sequence. + output wb_s_responder_s wb_s_responder_struct + );// pragma tbx xtf + // + // Members within the wb_s_initiator_struct: + // bit [WB_DATA_WIDTH-1:0] data ; + // Members within the wb_s_responder_struct: + // bit [WB_DATA_WIDTH-1:0] data ; + initiator_struct = wb_s_initiator_struct; + // + // Reference code; + // How to wait for signal value + // while (control_signal == 1'b1) @(posedge clock_i); + // + // How to assign a responder struct member, named xyz, from a signal. + // All available initiator input and inout signals listed. + // Initiator input signals + // wb_s_responder_struct.xyz = din_i; // [WB_DATA_WIDTH-1:0] + // wb_s_responder_struct.xyz = TGD_I_i; // [WB_DATA_WIDTH-1:0] + // wb_s_responder_struct.xyz = adr_i; // [WB_ADDR_WIDTH-1:0] + // wb_s_responder_struct.xyz = cyc_i; // + // wb_s_responder_struct.xyz = we_i; // + // wb_s_responder_struct.xyz = stb_i; // + // wb_s_responder_struct.xyz = sel_i; // [WB_DATA_WIDTH/8-1:0] + // Initiator inout signals + // How to assign a signal from an initiator struct member named xyz. + // All available initiator output and inout signals listed. + // Notice the _o. Those are storage variables that allow for procedural assignment. + // Initiator output signals + // dout_o <= wb_s_initiator_struct.xyz; // [WB_DATA_WIDTH-1:0] + // TGD_O_o <= wb_s_initiator_struct.xyz; // [WB_DATA_WIDTH-1:0] + // ack_o <= wb_s_initiator_struct.xyz; // + // err_o <= wb_s_initiator_struct.xyz; // + // Initiator inout signals + // Initiate a transfer using the data received. + @(posedge clock_i); + @(posedge clock_i); + // Wait for the responder to complete the transfer then place the responder data into + // wb_s_responder_struct. + @(posedge clock_i); + @(posedge clock_i); + responder_struct = wb_s_responder_struct; + endtask +// pragma uvmf custom initiate_and_get_response end + +// pragma uvmf custom respond_and_wait_for_next_transfer begin +// **************************************************************************** +// The first_transfer variable is used to prevent completing a transfer in the +// first call to this task. For the first call to this task, there is not +// current transfer to complete. +bit first_transfer=1; + +// UVMF_CHANGE_ME +// This task is used by a responder. The task first completes the current +// transfer in progress then waits for the initiator to start the next transfer. + task respond_and_wait_for_next_transfer( + // This argument is used to send data received from the initiator + // back to the sequence item. The sequence determines how to respond. + output wb_s_initiator_s wb_s_initiator_struct, + // This argument passes transaction variables used by a responder + // to complete a protocol transfer. The values come from a sequence item. + input wb_s_responder_s wb_s_responder_struct + );// pragma tbx xtf + // Variables within the wb_s_initiator_struct: + // bit [WB_DATA_WIDTH-1:0] data ; + // Variables within the wb_s_responder_struct: + // bit [WB_DATA_WIDTH-1:0] data ; + // Reference code; + // How to wait for signal value + // while (control_signal == 1'b1) @(posedge clock_i); + // + // How to assign a responder struct member, named xyz, from a signal. + // All available responder input and inout signals listed. + // Responder input signals + // wb_s_responder_struct.xyz = dout_i; // [WB_DATA_WIDTH-1:0] + // wb_s_responder_struct.xyz = TGD_O_i; // [WB_DATA_WIDTH-1:0] + // wb_s_responder_struct.xyz = ack_i; // + // wb_s_responder_struct.xyz = err_i; // + // Responder inout signals + // How to assign a signal, named xyz, from an initiator struct member. + // All available responder output and inout signals listed. + // Notice the _o. Those are storage variables that allow for procedural assignment. + // Responder output signals + // din_o <= wb_s_initiator_struct.xyz; // [WB_DATA_WIDTH-1:0] + // TGD_I_o <= wb_s_initiator_struct.xyz; // [WB_DATA_WIDTH-1:0] + // adr_o <= wb_s_initiator_struct.xyz; // [WB_ADDR_WIDTH-1:0] + // cyc_o <= wb_s_initiator_struct.xyz; // + // we_o <= wb_s_initiator_struct.xyz; // + // stb_o <= wb_s_initiator_struct.xyz; // + // sel_o <= wb_s_initiator_struct.xyz; // [WB_DATA_WIDTH/8-1:0] + // Responder inout signals + + @(posedge clock_i); + if (!first_transfer) begin + // Perform transfer response here. + // Reply using data recieved in the wb_s_responder_struct. + @(posedge clock_i); + // Reply using data recieved in the transaction handle. + @(posedge clock_i); + end + // Wait for next transfer then gather info from intiator about the transfer. + // Place the data into the wb_s_initiator_struct. + @(posedge clock_i); + @(posedge clock_i); + first_transfer = 0; + endtask +// pragma uvmf custom respond_and_wait_for_next_transfer end + + +endinterface + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/verification_ip/interface_packages/wb_s_pkg/src/wb_s_if.sv b/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/verification_ip/interface_packages/wb_s_pkg/src/wb_s_if.sv new file mode 100644 index 00000000..98000bcc --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/verification_ip/interface_packages/wb_s_pkg/src/wb_s_if.sv @@ -0,0 +1,117 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This interface contains the wb_s interface signals. +// It is instantiated once per wb_s bus. Bus Functional Models, +// BFM's named wb_s_driver_bfm, are used to drive signals on the bus. +// BFM's named wb_s_monitor_bfm are used to monitor signals on the +// bus. This interface signal bundle is passed in the port list of +// the BFM in order to give the BFM access to the signals in this +// interface. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// This template can be used to connect a DUT to these signals +// +// .dut_signal_port(wb_s_bus.din), // Agent input +// .dut_signal_port(wb_s_bus.dout), // Agent output +// .dut_signal_port(wb_s_bus.TGD_I), // Agent input +// .dut_signal_port(wb_s_bus.TGD_O), // Agent output +// .dut_signal_port(wb_s_bus.ack), // Agent output +// .dut_signal_port(wb_s_bus.adr), // Agent input +// .dut_signal_port(wb_s_bus.cyc), // Agent input +// .dut_signal_port(wb_s_bus.err), // Agent output +// .dut_signal_port(wb_s_bus.we), // Agent input +// .dut_signal_port(wb_s_bus.stb), // Agent input +// .dut_signal_port(wb_s_bus.sel), // Agent input + +import uvmf_base_pkg_hdl::*; +import wb_s_pkg_hdl::*; + +interface wb_s_if #( + int WB_ADDR_WIDTH = 32, + int WB_DATA_WIDTH = 16 + ) + + ( + input logic clock, + input logic reset, + input logic [WB_DATA_WIDTH-1:0] din, + output logic [WB_DATA_WIDTH-1:0] dout, + input logic [WB_DATA_WIDTH-1:0] TGD_I, + output logic [WB_DATA_WIDTH-1:0] TGD_O, + output logic ack, + input logic [WB_ADDR_WIDTH-1:0] adr, + input logic cyc, + output logic err, + input logic we, + input logic stb, + input logic [WB_DATA_WIDTH/8-1:0] sel + ); + +modport monitor_port + ( + input clock, + input reset, + input din, + input dout, + input TGD_I, + input TGD_O, + input ack, + input adr, + input cyc, + input err, + input we, + input stb, + input sel + ); + +modport initiator_port + ( + input clock, + input reset, + input din, + output dout, + input TGD_I, + output TGD_O, + output ack, + input adr, + input cyc, + output err, + input we, + input stb, + input sel + ); + +modport responder_port + ( + input clock, + input reset, + output din, + input dout, + output TGD_I, + input TGD_O, + input ack, + output adr, + output cyc, + input err, + output we, + output stb, + output sel + ); + + +// pragma uvmf custom interface_item_additional begin +// pragma uvmf custom interface_item_additional end + +endinterface + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/verification_ip/interface_packages/wb_s_pkg/src/wb_s_infact_coverage_strategy.csv b/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/verification_ip/interface_packages/wb_s_pkg/src/wb_s_infact_coverage_strategy.csv new file mode 100644 index 00000000..1c218e14 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/verification_ip/interface_packages/wb_s_pkg/src/wb_s_infact_coverage_strategy.csv @@ -0,0 +1,6 @@ +Global +auto_bin_max, 64 + +Name,Type,Include +rand_fields,coverpoint,=rand *.** + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/verification_ip/interface_packages/wb_s_pkg/src/wb_s_macros.svh b/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/verification_ip/interface_packages/wb_s_pkg/src/wb_s_macros.svh new file mode 100644 index 00000000..5758385f --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/verification_ip/interface_packages/wb_s_pkg/src/wb_s_macros.svh @@ -0,0 +1,121 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This file contains macros used with the wb_s package. +// These macros include packed struct definitions. These structs are +// used to pass data between classes, hvl, and BFM's, hdl. Use of +// structs are more efficient and simpler to modify. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// + +// **************************************************************************** +// When changing the contents of this struct, be sure to update the to_struct +// and from_struct methods defined in the macros below that are used in +// the wb_s_configuration class. +// + `define wb_s_CONFIGURATION_STRUCT \ +typedef struct packed { \ + uvmf_active_passive_t active_passive; \ + uvmf_initiator_responder_t initiator_responder; \ + } wb_s_configuration_s; + + `define wb_s_CONFIGURATION_TO_STRUCT_FUNCTION \ + virtual function wb_s_configuration_s to_struct();\ + wb_s_configuration_struct = \ + {\ + this.active_passive,\ + this.initiator_responder\ + };\ + return ( wb_s_configuration_struct );\ + endfunction + + `define wb_s_CONFIGURATION_FROM_STRUCT_FUNCTION \ + virtual function void from_struct(wb_s_configuration_s wb_s_configuration_struct);\ + {\ + this.active_passive,\ + this.initiator_responder \ + } = wb_s_configuration_struct;\ + endfunction + +// **************************************************************************** +// When changing the contents of this struct, be sure to update the to_monitor_struct +// and from_monitor_struct methods of the wb_s_transaction class. +// + `define wb_s_MONITOR_STRUCT typedef struct packed { \ + bit [WB_DATA_WIDTH-1:0] data ; \ + } wb_s_monitor_s; + + `define wb_s_TO_MONITOR_STRUCT_FUNCTION \ + virtual function wb_s_monitor_s to_monitor_struct();\ + wb_s_monitor_struct = \ + { \ + this.data \ + };\ + return ( wb_s_monitor_struct);\ + endfunction\ + + `define wb_s_FROM_MONITOR_STRUCT_FUNCTION \ + virtual function void from_monitor_struct(wb_s_monitor_s wb_s_monitor_struct);\ + {\ + this.data \ + } = wb_s_monitor_struct;\ + endfunction + +// **************************************************************************** +// When changing the contents of this struct, be sure to update the to_initiator_struct +// and from_initiator_struct methods of the wb_s_transaction class. +// Also update the comments in the driver BFM. +// + `define wb_s_INITIATOR_STRUCT typedef struct packed { \ + bit [WB_DATA_WIDTH-1:0] data ; \ + } wb_s_initiator_s; + + `define wb_s_TO_INITIATOR_STRUCT_FUNCTION \ + virtual function wb_s_initiator_s to_initiator_struct();\ + wb_s_initiator_struct = \ + {\ + this.data \ + };\ + return ( wb_s_initiator_struct);\ + endfunction + + `define wb_s_FROM_INITIATOR_STRUCT_FUNCTION \ + virtual function void from_initiator_struct(wb_s_initiator_s wb_s_initiator_struct);\ + {\ + this.data \ + } = wb_s_initiator_struct;\ + endfunction + +// **************************************************************************** +// When changing the contents of this struct, be sure to update the to_responder_struct +// and from_responder_struct methods of the wb_s_transaction class. +// Also update the comments in the driver BFM. +// + `define wb_s_RESPONDER_STRUCT typedef struct packed { \ + bit [WB_DATA_WIDTH-1:0] data ; \ + } wb_s_responder_s; + + `define wb_s_TO_RESPONDER_STRUCT_FUNCTION \ + virtual function wb_s_responder_s to_responder_struct();\ + wb_s_responder_struct = \ + {\ + this.data \ + };\ + return ( wb_s_responder_struct);\ + endfunction + + `define wb_s_FROM_RESPONDER_STRUCT_FUNCTION \ + virtual function void from_responder_struct(wb_s_responder_s wb_s_responder_struct);\ + {\ + this.data \ + } = wb_s_responder_struct;\ + endfunction +// pragma uvmf custom additional begin +// pragma uvmf custom additional end diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/verification_ip/interface_packages/wb_s_pkg/src/wb_s_monitor.svh b/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/verification_ip/interface_packages/wb_s_pkg/src/wb_s_monitor.svh new file mode 100644 index 00000000..904d0a5b --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/verification_ip/interface_packages/wb_s_pkg/src/wb_s_monitor.svh @@ -0,0 +1,102 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This class receives wb_s transactions observed by the +// wb_s monitor BFM and broadcasts them through the analysis port +// on the agent. It accesses the monitor BFM through the monitor +// task. This UVM component captures transactions +// for viewing in the waveform viewer if the +// enable_transaction_viewing flag is set in the configuration. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class wb_s_monitor #( + int WB_ADDR_WIDTH = 32, + int WB_DATA_WIDTH = 16 + ) extends uvmf_monitor_base #( + .CONFIG_T(wb_s_configuration #( + .WB_ADDR_WIDTH(WB_ADDR_WIDTH), + .WB_DATA_WIDTH(WB_DATA_WIDTH) + )), + .BFM_BIND_T(virtual wb_s_monitor_bfm #( + .WB_ADDR_WIDTH(WB_ADDR_WIDTH), + .WB_DATA_WIDTH(WB_DATA_WIDTH) + )), + .TRANS_T(wb_s_transaction #( + .WB_ADDR_WIDTH(WB_ADDR_WIDTH), + .WB_DATA_WIDTH(WB_DATA_WIDTH) + ))); + + `uvm_component_param_utils( wb_s_monitor #( + WB_ADDR_WIDTH, + WB_DATA_WIDTH + )) + +// Structure used to pass data from monitor BFM to monitor class in agent. +// Use to_monitor_struct function to pack transaction variables into structure. +// Use from_monitor_struct function to unpack transaction variables from structure. +`wb_s_MONITOR_STRUCT + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + +// **************************************************************************** +// This function is the standard SystemVerilog constructor. +// + function new( string name = "", uvm_component parent = null ); + super.new( name, parent ); + endfunction + +// **************************************************************************** +// This function sends configuration object variables to the monitor BFM +// using the configuration struct. +// + virtual function void configure(input CONFIG_T cfg); + bfm.configure( cfg.to_struct() ); + + endfunction + +// **************************************************************************** +// This function places a handle to this class in the proxy variable in the +// monitor BFM. This allows the monitor BFM to call the notify_transaction +// function within this class. +// + virtual function void set_bfm_proxy_handle(); + bfm.proxy = this; endfunction + +// *************************************************************************** + virtual task run_phase(uvm_phase phase); + // Start monitor BFM thread and don't call super.run() in order to + // override the default monitor proxy 'pull' behavior with the more + // emulation-friendly BFM 'push' approach using the notify_transaction + // function below + bfm.start_monitoring(); + endtask + +// ************************************************************************** + +// This function is called by the monitor BFM. It receives data observed by the +// monitor BFM. Data is passed using the wb_s_monitor_struct. + virtual function void notify_transaction(input wb_s_monitor_s wb_s_monitor_struct); + + + trans = new("trans"); + trans.from_monitor_struct(wb_s_monitor_struct); + trans.start_time = time_stamp; + trans.end_time = $time; + time_stamp = trans.end_time; + + analyze(trans); + endfunction + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/verification_ip/interface_packages/wb_s_pkg/src/wb_s_monitor_bfm.sv b/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/verification_ip/interface_packages/wb_s_pkg/src/wb_s_monitor_bfm.sv new file mode 100644 index 00000000..fa19c337 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/verification_ip/interface_packages/wb_s_pkg/src/wb_s_monitor_bfm.sv @@ -0,0 +1,210 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This interface performs the wb_s signal monitoring. +// It is accessed by the uvm wb_s monitor through a virtual +// interface handle in the wb_s configuration. It monitors the +// signals passed in through the port connection named bus of +// type wb_s_if. +// +// Input signals from the wb_s_if are assigned to an internal input +// signal with a _i suffix. The _i signal should be used for sampling. +// +// The input signal connections are as follows: +// bus.signal -> signal_i +// +// Interface functions and tasks used by UVM components: +// monitor(inout TRANS_T txn); +// This task receives the transaction, txn, from the +// UVM monitor and then populates variables in txn +// from values observed on bus activity. This task +// blocks until an operation on the wb_s bus is complete. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +import uvmf_base_pkg_hdl::*; +import wb_s_pkg_hdl::*; +`include "src/wb_s_macros.svh" + + +interface wb_s_monitor_bfm #( + int WB_ADDR_WIDTH = 32, + int WB_DATA_WIDTH = 16 + ) + ( wb_s_if bus ); + // The pragma below and additional ones in-lined further down are for running this BFM on Veloce + // pragma attribute wb_s_monitor_bfm partition_interface_xif + +`ifndef XRTL +// This code is to aid in debugging parameter mismatches between the BFM and its corresponding agent. +// Enable this debug by setting UVM_VERBOSITY to UVM_DEBUG +// Setting UVM_VERBOSITY to UVM_DEBUG causes all BFM's and all agents to display their parameter settings. +// All of the messages from this feature have a UVM messaging id value of "CFG" +// The transcript or run.log can be parsed to ensure BFM parameter settings match its corresponding agents parameter settings. +import uvm_pkg::*; +`include "uvm_macros.svh" +initial begin : bfm_vs_agent_parameter_debug + `uvm_info("CFG", + $psprintf("The BFM at '%m' has the following parameters: WB_ADDR_WIDTH=%x WB_DATA_WIDTH=%x ", WB_ADDR_WIDTH,WB_DATA_WIDTH), + UVM_DEBUG) +end +`endif + + + // Structure used to pass transaction data from monitor BFM to monitor class in agent. +`wb_s_MONITOR_STRUCT + wb_s_monitor_s wb_s_monitor_struct; + + // Structure used to pass configuration data from monitor class to monitor BFM. + `wb_s_CONFIGURATION_STRUCT + + + // Config value to determine if this is an initiator or a responder + uvmf_initiator_responder_t initiator_responder; + // Custom configuration variables. + // These are set using the configure function which is called during the UVM connect_phase + + logic clock_i; + logic reset_i; + tri [WB_DATA_WIDTH-1:0] din_i; + tri [WB_DATA_WIDTH-1:0] dout_i; + tri [WB_DATA_WIDTH-1:0] TGD_I_i; + tri [WB_DATA_WIDTH-1:0] TGD_O_i; + tri ack_i; + tri [WB_ADDR_WIDTH-1:0] adr_i; + tri cyc_i; + tri err_i; + tri we_i; + tri stb_i; + tri [WB_DATA_WIDTH/8-1:0] sel_i; + assign clock_i = bus.clock; + assign reset_i = bus.reset; + assign din_i = bus.din; + assign dout_i = bus.dout; + assign TGD_I_i = bus.TGD_I; + assign TGD_O_i = bus.TGD_O; + assign ack_i = bus.ack; + assign adr_i = bus.adr; + assign cyc_i = bus.cyc; + assign err_i = bus.err; + assign we_i = bus.we; + assign stb_i = bus.stb; + assign sel_i = bus.sel; + + // Proxy handle to UVM monitor + wb_s_pkg::wb_s_monitor #( + .WB_ADDR_WIDTH(WB_ADDR_WIDTH), + .WB_DATA_WIDTH(WB_DATA_WIDTH) + ) proxy; + // pragma tbx oneway proxy.notify_transaction + + // pragma uvmf custom interface_item_additional begin + // pragma uvmf custom interface_item_additional end + + //****************************************************************** + task wait_for_reset();// pragma tbx xtf + @(posedge clock_i) ; + do_wait_for_reset(); + endtask + + // **************************************************************************** + task do_wait_for_reset(); + // pragma uvmf custom reset_condition begin + wait ( reset_i === 0 ) ; + @(posedge clock_i) ; + // pragma uvmf custom reset_condition end + endtask + + //****************************************************************** + + task wait_for_num_clocks(input int unsigned count); // pragma tbx xtf + @(posedge clock_i); + + repeat (count-1) @(posedge clock_i); + endtask + + //****************************************************************** + event go; + function void start_monitoring();// pragma tbx xtf + -> go; + endfunction + + // **************************************************************************** + initial begin + @go; + forever begin + @(posedge clock_i); + do_monitor( wb_s_monitor_struct ); + + + proxy.notify_transaction( wb_s_monitor_struct ); + + end + end + + //****************************************************************** + // The configure() function is used to pass agent configuration + // variables to the monitor BFM. It is called by the monitor within + // the agent at the beginning of the simulation. It may be called + // during the simulation if agent configuration variables are updated + // and the monitor BFM needs to be aware of the new configuration + // variables. + // + function void configure(wb_s_configuration_s wb_s_configuration_arg); // pragma tbx xtf + initiator_responder = wb_s_configuration_arg.initiator_responder; + // pragma uvmf custom configure begin + // pragma uvmf custom configure end + endfunction + + + // **************************************************************************** + + task do_monitor(output wb_s_monitor_s wb_s_monitor_struct); + // + // Available struct members: + // // wb_s_monitor_struct.data + // // + // Reference code; + // How to wait for signal value + // while (control_signal === 1'b1) @(posedge clock_i); + // + // How to assign a struct member, named xyz, from a signal. + // All available input signals listed. + // wb_s_monitor_struct.xyz = din_i; // [WB_DATA_WIDTH-1:0] + // wb_s_monitor_struct.xyz = dout_i; // [WB_DATA_WIDTH-1:0] + // wb_s_monitor_struct.xyz = TGD_I_i; // [WB_DATA_WIDTH-1:0] + // wb_s_monitor_struct.xyz = TGD_O_i; // [WB_DATA_WIDTH-1:0] + // wb_s_monitor_struct.xyz = ack_i; // + // wb_s_monitor_struct.xyz = adr_i; // [WB_ADDR_WIDTH-1:0] + // wb_s_monitor_struct.xyz = cyc_i; // + // wb_s_monitor_struct.xyz = err_i; // + // wb_s_monitor_struct.xyz = we_i; // + // wb_s_monitor_struct.xyz = stb_i; // + // wb_s_monitor_struct.xyz = sel_i; // [WB_DATA_WIDTH/8-1:0] + // pragma uvmf custom do_monitor begin + // UVMF_CHANGE_ME : Implement protocol monitoring. The commented reference code + // below are examples of how to capture signal values and assign them to + // structure members. All available input signals are listed. The 'while' + // code example shows how to wait for a synchronous flow control signal. This + // task should return when a complete transfer has been observed. Once this task is + // exited with captured values, it is then called again to wait for and observe + // the next transfer. One clock cycle is consumed between calls to do_monitor. + @(posedge clock_i); + @(posedge clock_i); + @(posedge clock_i); + @(posedge clock_i); + // pragma uvmf custom do_monitor end + endtask + + +endinterface + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/verification_ip/interface_packages/wb_s_pkg/src/wb_s_random_sequence.svh b/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/verification_ip/interface_packages/wb_s_pkg/src/wb_s_random_sequence.svh new file mode 100644 index 00000000..92df7b61 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/verification_ip/interface_packages/wb_s_pkg/src/wb_s_random_sequence.svh @@ -0,0 +1,65 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: +// This sequences randomizes the wb_s transaction and sends it +// to the UVM driver. +// +// This sequence constructs and randomizes a wb_s_transaction. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class wb_s_random_sequence #( + int WB_ADDR_WIDTH = 32, + int WB_DATA_WIDTH = 16 + ) + extends wb_s_sequence_base #( + .WB_ADDR_WIDTH(WB_ADDR_WIDTH), + .WB_DATA_WIDTH(WB_DATA_WIDTH) + ); + + `uvm_object_param_utils( wb_s_random_sequence #( + WB_ADDR_WIDTH, + WB_DATA_WIDTH + )) + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + //***************************************************************** + function new(string name = ""); + super.new(name); + endfunction: new + + // **************************************************************************** + // TASK : body() + // This task is automatically executed when this sequence is started using the + // start(sequencerHandle) task. + // + task body(); + + // Construct the transaction + req=wb_s_transaction#( + .WB_ADDR_WIDTH(WB_ADDR_WIDTH), + .WB_DATA_WIDTH(WB_DATA_WIDTH) + )::type_id::create("req"); + start_item(req); + // Randomize the transaction + if(!req.randomize()) `uvm_fatal("SEQ", "wb_s_random_sequence::body()-wb_s_transaction randomization failed") + // Send the transaction to the wb_s_driver_bfm via the sequencer and wb_s_driver. + finish_item(req); + `uvm_info("SEQ", {"Response:",req.convert2string()},UVM_MEDIUM) + + endtask + +endclass: wb_s_random_sequence + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/verification_ip/interface_packages/wb_s_pkg/src/wb_s_responder_sequence.svh b/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/verification_ip/interface_packages/wb_s_pkg/src/wb_s_responder_sequence.svh new file mode 100644 index 00000000..730ec16e --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/verification_ip/interface_packages/wb_s_pkg/src/wb_s_responder_sequence.svh @@ -0,0 +1,61 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This class can be used to provide stimulus when an interface +// has been configured to run in a responder mode. It +// will never finish by default, always going back to the driver +// and driver BFM for the next transaction with which to respond. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class wb_s_responder_sequence #( + int WB_ADDR_WIDTH = 32, + int WB_DATA_WIDTH = 16 + ) + extends wb_s_sequence_base #( + .WB_ADDR_WIDTH(WB_ADDR_WIDTH), + .WB_DATA_WIDTH(WB_DATA_WIDTH) + ); + + `uvm_object_param_utils( wb_s_responder_sequence #( + WB_ADDR_WIDTH, + WB_DATA_WIDTH + )) + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + function new(string name = "wb_s_responder_sequence"); + super.new(name); + endfunction + + task body(); + req=wb_s_transaction#( + .WB_ADDR_WIDTH(WB_ADDR_WIDTH), + .WB_DATA_WIDTH(WB_DATA_WIDTH) + )::type_id::create("req"); + forever begin + start_item(req); + finish_item(req); + // pragma uvmf custom body begin + // UVMF_CHANGE_ME : Do something here with the resulting req item. The + // finish_item() call above will block until the req transaction is ready + // to be handled by the responder sequence. + // If this was an item that required a response, the expectation is + // that the response should be populated within this transaction now. + `uvm_info("SEQ",$sformatf("Processed txn: %s",req.convert2string()),UVM_HIGH) + // pragma uvmf custom body end + end + endtask + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/verification_ip/interface_packages/wb_s_pkg/src/wb_s_sequence_base.svh b/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/verification_ip/interface_packages/wb_s_pkg/src/wb_s_sequence_base.svh new file mode 100644 index 00000000..78d29786 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/verification_ip/interface_packages/wb_s_pkg/src/wb_s_sequence_base.svh @@ -0,0 +1,114 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: +// This file contains the class used as the base class for all sequences +// for this interface. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class wb_s_sequence_base #( + int WB_ADDR_WIDTH = 32, + int WB_DATA_WIDTH = 16 + ) extends uvmf_sequence_base #( + .REQ(wb_s_transaction #( + .WB_ADDR_WIDTH(WB_ADDR_WIDTH), + .WB_DATA_WIDTH(WB_DATA_WIDTH) + )), + .RSP(wb_s_transaction #( + .WB_ADDR_WIDTH(WB_ADDR_WIDTH), + .WB_DATA_WIDTH(WB_DATA_WIDTH) + ))); + + `uvm_object_param_utils( wb_s_sequence_base #( + WB_ADDR_WIDTH, + WB_DATA_WIDTH + )) + + // variables + typedef wb_s_transaction #( + .WB_ADDR_WIDTH(WB_ADDR_WIDTH), + .WB_DATA_WIDTH(WB_DATA_WIDTH) + ) wb_s_transaction_req_t; + wb_s_transaction_req_t req; + typedef wb_s_transaction #( + .WB_ADDR_WIDTH(WB_ADDR_WIDTH), + .WB_DATA_WIDTH(WB_DATA_WIDTH) + ) wb_s_transaction_rsp_t; + wb_s_transaction_rsp_t rsp; + + // Event for identifying when a response was received from the sequencer + event new_rsp; + + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + // **************************************************************************** + // TASK : get_responses() + // This task recursively gets sequence item responses from the sequencer. + // + virtual task get_responses(); + fork + begin + // Block until new rsp available + get_response(rsp); + // New rsp received. Indicate to sequence using event. + ->new_rsp; + // Display the received response transaction + `uvm_info("SEQ", {"New response transaction:",rsp.convert2string()}, UVM_MEDIUM) + end + join_none + endtask + + // **************************************************************************** + // TASK : pre_body() + // This task is called automatically when start is called with call_pre_post set to 1 (default). + // By calling get_responses() within pre_body() any derived sequences are automatically + // processing response transactions. Only un-comment this call to get_responses() if you + // have configured the interface driver to utilize the response transaction path by setting + // the configuration variable "return_transaction_response" to 1. Otherwise it is possible + // to impact runtime performance and memory utilization. + // + virtual task pre_body(); + // pragma uvmf custom pre_body begin +// get_responses(); + // pragma uvmf custom pre_body end + endtask + + // **************************************************************************** + // TASK : body() + // This task is called automatically when start is called. This sequence sends + // a req sequence item to the sequencer identified as an argument in the call + // to start. + // + virtual task body(); + // pragma uvmf custom body begin + start_item(req); + finish_item(req); + // pragma uvmf custom body end + endtask + + // **************************************************************************** + // FUNCTION : new() + // This function is the standard SystemVerilog constructor. + // + function new( string name =""); + super.new( name ); + // pragma uvmf custom new begin + req = wb_s_transaction_req_t::type_id::create("req"); + rsp = wb_s_transaction_rsp_t::type_id::create("rsp"); + // pragma uvmf custom new end + endfunction + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/verification_ip/interface_packages/wb_s_pkg/src/wb_s_transaction.svh b/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/verification_ip/interface_packages/wb_s_pkg/src/wb_s_transaction.svh new file mode 100644 index 00000000..7548f786 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/verification_ip/interface_packages/wb_s_pkg/src/wb_s_transaction.svh @@ -0,0 +1,194 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This class defines the variables required for an wb_s +// transaction. Class variables to be displayed in waveform transaction +// viewing are added to the transaction viewing stream in the add_to_wave +// function. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class wb_s_transaction #( + int WB_ADDR_WIDTH = 32, + int WB_DATA_WIDTH = 16 + ) extends uvmf_transaction_base; + + `uvm_object_param_utils( wb_s_transaction #( + WB_ADDR_WIDTH, + WB_DATA_WIDTH + )) + + rand bit [WB_DATA_WIDTH-1:0] data ; + + //Constraints for the transaction variables: + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + //******************************************************************* + //******************************************************************* + // Macros that define structs and associated functions are + // located in wb_s_macros.svh + + //******************************************************************* + // Monitor macro used by wb_s_monitor and wb_s_monitor_bfm + // This struct is defined in wb_s_macros.svh + `wb_s_MONITOR_STRUCT + wb_s_monitor_s wb_s_monitor_struct; + //******************************************************************* + // FUNCTION: to_monitor_struct() + // This function packs transaction variables into a wb_s_monitor_s + // structure. The function returns the handle to the wb_s_monitor_struct. + // This function is defined in wb_s_macros.svh + `wb_s_TO_MONITOR_STRUCT_FUNCTION + //******************************************************************* + // FUNCTION: from_monitor_struct() + // This function unpacks the struct provided as an argument into transaction + // variables of this class. + // This function is defined in wb_s_macros.svh + `wb_s_FROM_MONITOR_STRUCT_FUNCTION + + //******************************************************************* + // Initiator macro used by wb_s_driver and wb_s_driver_bfm + // to communicate initiator driven data to wb_s_driver_bfm. + // This struct is defined in wb_s_macros.svh + `wb_s_INITIATOR_STRUCT + wb_s_initiator_s wb_s_initiator_struct; + //******************************************************************* + // FUNCTION: to_initiator_struct() + // This function packs transaction variables into a wb_s_initiator_s + // structure. The function returns the handle to the wb_s_initiator_struct. + // This function is defined in wb_s_macros.svh + `wb_s_TO_INITIATOR_STRUCT_FUNCTION + //******************************************************************* + // FUNCTION: from_initiator_struct() + // This function unpacks the struct provided as an argument into transaction + // variables of this class. + // This function is defined in wb_s_macros.svh + `wb_s_FROM_INITIATOR_STRUCT_FUNCTION + + //******************************************************************* + // Responder macro used by wb_s_driver and wb_s_driver_bfm + // to communicate Responder driven data to wb_s_driver_bfm. + // This struct is defined in wb_s_macros.svh + `wb_s_RESPONDER_STRUCT + wb_s_responder_s wb_s_responder_struct; + //******************************************************************* + // FUNCTION: to_responder_struct() + // This function packs transaction variables into a wb_s_responder_s + // structure. The function returns the handle to the wb_s_responder_struct. + // This function is defined in wb_s_macros.svh + `wb_s_TO_RESPONDER_STRUCT_FUNCTION + //******************************************************************* + // FUNCTION: from_responder_struct() + // This function unpacks the struct provided as an argument into transaction + // variables of this class. + // This function is defined in wb_s_macros.svh + `wb_s_FROM_RESPONDER_STRUCT_FUNCTION + // **************************************************************************** + // FUNCTION : new() + // This function is the standard SystemVerilog constructor. + // + function new( string name = "" ); + super.new( name ); + endfunction + + // **************************************************************************** + // FUNCTION: convert2string() + // This function converts all variables in this class to a single string for + // logfile reporting. + // + virtual function string convert2string(); + // pragma uvmf custom convert2string begin + // UVMF_CHANGE_ME : Customize format if desired. + return $sformatf("data:0x%x ",data); + // pragma uvmf custom convert2string end + endfunction + + //******************************************************************* + // FUNCTION: do_print() + // This function is automatically called when the .print() function + // is called on this class. + // + virtual function void do_print(uvm_printer printer); + // pragma uvmf custom do_print begin + // UVMF_CHANGE_ME : Current contents of do_print allows for the use of UVM 1.1d, 1.2 or P1800.2. + // Update based on your own printing preference according to your preferred UVM version + $display(convert2string()); + // pragma uvmf custom do_print end + endfunction + + //******************************************************************* + // FUNCTION: do_compare() + // This function is automatically called when the .compare() function + // is called on this class. + // + virtual function bit do_compare (uvm_object rhs, uvm_comparer comparer); + wb_s_transaction #( + .WB_ADDR_WIDTH(WB_ADDR_WIDTH), + .WB_DATA_WIDTH(WB_DATA_WIDTH) + ) RHS; + if (!$cast(RHS,rhs)) return 0; + // pragma uvmf custom do_compare begin + // UVMF_CHANGE_ME : Eliminate comparison of variables not to be used for compare + return (super.do_compare(rhs,comparer) + &&(this.data == RHS.data) + ); + // pragma uvmf custom do_compare end + endfunction + + //******************************************************************* + // FUNCTION: do_copy() + // This function is automatically called when the .copy() function + // is called on this class. + // + virtual function void do_copy (uvm_object rhs); + wb_s_transaction #( + .WB_ADDR_WIDTH(WB_ADDR_WIDTH), + .WB_DATA_WIDTH(WB_DATA_WIDTH) + ) RHS; + assert($cast(RHS,rhs)); + // pragma uvmf custom do_copy begin + super.do_copy(rhs); + this.data = RHS.data; + // pragma uvmf custom do_copy end + endfunction + + // **************************************************************************** + // FUNCTION: add_to_wave() + // This function is used to display variables in this class in the waveform + // viewer. The start_time and end_time variables must be set before this + // function is called. If the start_time and end_time variables are not set + // the transaction will be hidden at 0ns on the waveform display. + // + virtual function void add_to_wave(int transaction_viewing_stream_h); + `ifdef QUESTA + if (transaction_view_h == 0) begin + transaction_view_h = $begin_transaction(transaction_viewing_stream_h,"wb_s_transaction",start_time); + end + super.add_to_wave(transaction_view_h); + // pragma uvmf custom add_to_wave begin + // UVMF_CHANGE_ME : Color can be applied to transaction entries based on content, example below + // case() + // 1 : $add_color(transaction_view_h,"red"); + // default : $add_color(transaction_view_h,"grey"); + // endcase + // UVMF_CHANGE_ME : Eliminate transaction variables not wanted in transaction viewing in the waveform viewer + $add_attribute(transaction_view_h,data,"data"); + // pragma uvmf custom add_to_wave end + $end_transaction(transaction_view_h,end_time); + $free_transaction(transaction_view_h); + `endif // QUESTA + endfunction + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/verification_ip/interface_packages/wb_s_pkg/src/wb_s_transaction_coverage.svh b/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/verification_ip/interface_packages/wb_s_pkg/src/wb_s_transaction_coverage.svh new file mode 100644 index 00000000..01295fc0 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/verification_ip/interface_packages/wb_s_pkg/src/wb_s_transaction_coverage.svh @@ -0,0 +1,79 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This class records wb_s transaction information using +// a covergroup named wb_s_transaction_cg. An instance of this +// coverage component is instantiated in the uvmf_parameterized_agent +// if the has_coverage flag is set. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class wb_s_transaction_coverage #( + int WB_ADDR_WIDTH = 32, + int WB_DATA_WIDTH = 16 + ) extends uvm_subscriber #(.T(wb_s_transaction #( + .WB_ADDR_WIDTH(WB_ADDR_WIDTH), + .WB_DATA_WIDTH(WB_DATA_WIDTH) + ))); + + `uvm_component_param_utils( wb_s_transaction_coverage #( + WB_ADDR_WIDTH, + WB_DATA_WIDTH + )) + + T coverage_trans; + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + // **************************************************************************** + covergroup wb_s_transaction_cg; + // pragma uvmf custom covergroup begin + // UVMF_CHANGE_ME : Add coverage bins, crosses, exclusions, etc. according to coverage needs. + option.auto_bin_max=1024; + option.per_instance=1; + data: coverpoint coverage_trans.data; + // pragma uvmf custom covergroup end + endgroup + + // **************************************************************************** + // FUNCTION : new() + // This function is the standard SystemVerilog constructor. + // + function new(string name="", uvm_component parent=null); + super.new(name,parent); + wb_s_transaction_cg=new; + `uvm_warning("COVERAGE_MODEL_REVIEW", "A covergroup has been constructed which may need review because of either generation or re-generation with merging. Please note that transaction variables added as a result of re-generation and merging are not automatically added to the covergroup. Remove this warning after the covergroup has been reviewed.") + endfunction + + // **************************************************************************** + // FUNCTION : build_phase() + // This function is the standard UVM build_phase. + // + function void build_phase(uvm_phase phase); + wb_s_transaction_cg.set_inst_name($sformatf("wb_s_transaction_cg_%s",get_full_name())); + endfunction + + // **************************************************************************** + // FUNCTION: write (T t) + // This function is automatically executed when a transaction arrives on the + // analysis_export. It copies values from the variables in the transaction + // to local variables used to collect functional coverage. + // + virtual function void write (T t); + `uvm_info("COV","Received transaction",UVM_HIGH); + coverage_trans = t; + wb_s_transaction_cg.sample(); + endfunction + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/verification_ip/interface_packages/wb_s_pkg/src/wb_s_typedefs.svh b/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/verification_ip/interface_packages/wb_s_pkg/src/wb_s_typedefs.svh new file mode 100644 index 00000000..43d85640 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/verification_ip/interface_packages/wb_s_pkg/src/wb_s_typedefs.svh @@ -0,0 +1,20 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: +// This file contains defines and typedefs to be compiled for use in +// the simulation running on the host server when using Veloce. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// + + +// pragma uvmf custom additional begin +// pragma uvmf custom additional end + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/verification_ip/interface_packages/wb_s_pkg/src/wb_s_typedefs_hdl.svh b/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/verification_ip/interface_packages/wb_s_pkg/src/wb_s_typedefs_hdl.svh new file mode 100644 index 00000000..74738c8c --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/verification_ip/interface_packages/wb_s_pkg/src/wb_s_typedefs_hdl.svh @@ -0,0 +1,21 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: +// This file contains defines and typedefs to be compiled for use in +// the simulation running on the emulator when using Veloce. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// + + + +// pragma uvmf custom additional begin +// pragma uvmf custom additional end + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/verification_ip/interface_packages/wb_s_pkg/wb_s.compile b/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/verification_ip/interface_packages/wb_s_pkg/wb_s.compile new file mode 100644 index 00000000..177c6693 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/verification_ip/interface_packages/wb_s_pkg/wb_s.compile @@ -0,0 +1,3 @@ +needs: + - wb_s_hvl.compile + - wb_s_hdl.compile diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/verification_ip/interface_packages/wb_s_pkg/wb_s_bfm.vinfo b/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/verification_ip/interface_packages/wb_s_pkg/wb_s_bfm.vinfo new file mode 100644 index 00000000..712d86d9 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/verification_ip/interface_packages/wb_s_pkg/wb_s_bfm.vinfo @@ -0,0 +1,6 @@ +@use $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg_hdl.vinfo +@use wb_s_pkg_hdl.vinfo ++incdir+@vinfodir +src/wb_s_if.sv +src/wb_s_driver_bfm.sv +src/wb_s_monitor_bfm.sv diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/verification_ip/interface_packages/wb_s_pkg/wb_s_common.compile b/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/verification_ip/interface_packages/wb_s_pkg/wb_s_common.compile new file mode 100644 index 00000000..cab218ee --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/verification_ip/interface_packages/wb_s_pkg/wb_s_common.compile @@ -0,0 +1,7 @@ +needs: + - $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg_hdl.compile +incdir: + - . + - ${uvm_path}/src +src: + - wb_s_pkg_hdl.sv diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/verification_ip/interface_packages/wb_s_pkg/wb_s_filelist_hdl.f b/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/verification_ip/interface_packages/wb_s_pkg/wb_s_filelist_hdl.f new file mode 100644 index 00000000..569bcef6 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/verification_ip/interface_packages/wb_s_pkg/wb_s_filelist_hdl.f @@ -0,0 +1 @@ +$UVMF_VIP_LIBRARY_HOME/interface_packages/wb_s_pkg/wb_s_pkg_hdl.sv diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/verification_ip/interface_packages/wb_s_pkg/wb_s_filelist_hvl.f b/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/verification_ip/interface_packages/wb_s_pkg/wb_s_filelist_hvl.f new file mode 100644 index 00000000..6c9a363f --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/verification_ip/interface_packages/wb_s_pkg/wb_s_filelist_hvl.f @@ -0,0 +1 @@ +$UVMF_VIP_LIBRARY_HOME/interface_packages/wb_s_pkg/wb_s_pkg.sv \ No newline at end of file diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/verification_ip/interface_packages/wb_s_pkg/wb_s_filelist_xrtl.f b/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/verification_ip/interface_packages/wb_s_pkg/wb_s_filelist_xrtl.f new file mode 100644 index 00000000..23f4bc76 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/verification_ip/interface_packages/wb_s_pkg/wb_s_filelist_xrtl.f @@ -0,0 +1,3 @@ +$UVMF_VIP_LIBRARY_HOME/interface_packages/wb_s_pkg/src/wb_s_if.sv +$UVMF_VIP_LIBRARY_HOME/interface_packages/wb_s_pkg/src/wb_s_monitor_bfm.sv +$UVMF_VIP_LIBRARY_HOME/interface_packages/wb_s_pkg/src/wb_s_driver_bfm.sv diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/verification_ip/interface_packages/wb_s_pkg/wb_s_hdl.compile b/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/verification_ip/interface_packages/wb_s_pkg/wb_s_hdl.compile new file mode 100644 index 00000000..4f4110eb --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/verification_ip/interface_packages/wb_s_pkg/wb_s_hdl.compile @@ -0,0 +1,9 @@ +needs: + - $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg_hdl.compile + - ./wb_s_common.compile +incdir: + - . +src: + - src/wb_s_if.sv + - src/wb_s_monitor_bfm.sv + - src/wb_s_driver_bfm.sv diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/verification_ip/interface_packages/wb_s_pkg/wb_s_hvl.compile b/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/verification_ip/interface_packages/wb_s_pkg/wb_s_hvl.compile new file mode 100644 index 00000000..e94eaf9b --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/verification_ip/interface_packages/wb_s_pkg/wb_s_hvl.compile @@ -0,0 +1,7 @@ +needs: + - $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg.compile + - ./wb_s_common.compile +incdir: + - . +src: + - wb_s_pkg.sv diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/verification_ip/interface_packages/wb_s_pkg/wb_s_pkg.sv b/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/verification_ip/interface_packages/wb_s_pkg/wb_s_pkg.sv new file mode 100644 index 00000000..64813566 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/verification_ip/interface_packages/wb_s_pkg/wb_s_pkg.sv @@ -0,0 +1,77 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// PACKAGE: This file defines all of the files contained in the +// interface package that will run on the host simulator. +// +// CONTAINS: +// - +// - +// - + +// - +// - +// - + +// - +// - +// - + +// - +// - +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +package wb_s_pkg; + + import uvm_pkg::*; + import uvmf_base_pkg_hdl::*; + import uvmf_base_pkg::*; + import wb_s_pkg_hdl::*; + + `include "uvm_macros.svh" + + // pragma uvmf custom package_imports_additional begin + // pragma uvmf custom package_imports_additional end + `include "src/wb_s_macros.svh" + + export wb_s_pkg_hdl::*; + + + + // Parameters defined as HVL parameters + + `include "src/wb_s_typedefs.svh" + `include "src/wb_s_transaction.svh" + + `include "src/wb_s_configuration.svh" + `include "src/wb_s_driver.svh" + `include "src/wb_s_monitor.svh" + + `include "src/wb_s_transaction_coverage.svh" + `include "src/wb_s_sequence_base.svh" + `include "src/wb_s_random_sequence.svh" + + `include "src/wb_s_responder_sequence.svh" + `include "src/wb_s2reg_adapter.svh" + + `include "src/wb_s_agent.svh" + + // pragma uvmf custom package_item_additional begin + // UVMF_CHANGE_ME : When adding new interface sequences to the src directory + // be sure to add the sequence file here so that it will be + // compiled as part of the interface package. Be sure to place + // the new sequence after any base sequences of the new sequence. + // pragma uvmf custom package_item_additional end + +endpackage + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/verification_ip/interface_packages/wb_s_pkg/wb_s_pkg.vinfo b/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/verification_ip/interface_packages/wb_s_pkg/wb_s_pkg.vinfo new file mode 100644 index 00000000..617cce78 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/verification_ip/interface_packages/wb_s_pkg/wb_s_pkg.vinfo @@ -0,0 +1,4 @@ +@use $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg.vinfo +@use wb_s_pkg_hdl.vinfo ++incdir+@vinfodir +wb_s_pkg.sv diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/verification_ip/interface_packages/wb_s_pkg/wb_s_pkg_hdl.sv b/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/verification_ip/interface_packages/wb_s_pkg/wb_s_pkg_hdl.sv new file mode 100644 index 00000000..49908ae3 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/verification_ip/interface_packages/wb_s_pkg/wb_s_pkg_hdl.sv @@ -0,0 +1,38 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// PACKAGE: This file defines all of the files contained in the +// interface package that needs to be compiled and synthesized +// for running on Veloce. +// +// CONTAINS: +// - +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +package wb_s_pkg_hdl; + + import uvmf_base_pkg_hdl::*; + + // pragma uvmf custom package_imports_additional begin + // pragma uvmf custom package_imports_additional end + + // Parameters defined as HDL parameters + + `include "src/wb_s_typedefs_hdl.svh" + `include "src/wb_s_macros.svh" + + // pragma uvmf custom package_item_additional begin + // pragma uvmf custom package_item_additional end + +endpackage + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/verification_ip/interface_packages/wb_s_pkg/wb_s_pkg_hdl.vinfo b/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/verification_ip/interface_packages/wb_s_pkg/wb_s_pkg_hdl.vinfo new file mode 100644 index 00000000..51a2e086 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/verification_ip/interface_packages/wb_s_pkg/wb_s_pkg_hdl.vinfo @@ -0,0 +1,2 @@ +@use $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg_hdl.vinfo +wb_s_pkg_hdl.sv diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/verification_ip/interface_packages/wb_s_pkg/wb_s_pkg_sve.F b/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/verification_ip/interface_packages/wb_s_pkg/wb_s_pkg_sve.F new file mode 100644 index 00000000..75e70906 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/verification_ip/interface_packages/wb_s_pkg/wb_s_pkg_sve.F @@ -0,0 +1,10 @@ +// UVM ++incdir+${UVM_HOME}/src +${UVM_HOME}/src/uvm_pkg.sv + +// Common UVMF files +-f ${UVMF_HOME}/common/common_sve.f + ++incdir+. +-f ${UVMF_VIP_LIBRARY_HOME}/interface_packages/wb_s_pkg/wb_s_filelist_hdl.f +-f ${UVMF_VIP_LIBRARY_HOME}/interface_packages/wb_s_pkg/wb_s_filelist_hvl.f diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/verification_ip/interface_packages/wb_s_pkg/yaml/wb_s_interface.yaml b/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/verification_ip/interface_packages/wb_s_pkg/yaml/wb_s_interface.yaml new file mode 100644 index 00000000..f37041fc --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_2/uvmf_template_output/verification_ip/interface_packages/wb_s_pkg/yaml/wb_s_interface.yaml @@ -0,0 +1,75 @@ +uvmf: + interfaces: + wb_s: + clock: clock + config_constraints: [] + config_vars: [] + existing_library_component: 'True' + gen_inbound_streaming_driver: 'False' + hdl_pkg_parameters: [] + hdl_typedefs: [] + hvl_pkg_parameters: [] + hvl_typedefs: [] + parameters: + - name: WB_ADDR_WIDTH + type: int + value: '32' + - name: WB_DATA_WIDTH + type: int + value: '16' + ports: + - dir: input + name: din + reset_value: '''b0' + width: WB_DATA_WIDTH + - dir: output + name: dout + reset_value: '''b0' + width: WB_DATA_WIDTH + - dir: input + name: TGD_I + reset_value: '''bz' + width: WB_DATA_WIDTH + - dir: output + name: TGD_O + reset_value: '''bz' + width: WB_DATA_WIDTH + - dir: output + name: ack + reset_value: '''b0' + width: '1' + - dir: input + name: adr + reset_value: '''b0' + width: WB_ADDR_WIDTH + - dir: input + name: cyc + reset_value: '0' + width: '1' + - dir: output + name: err + reset_value: '''b0' + width: '1' + - dir: input + name: we + reset_value: '0' + width: '1' + - dir: input + name: stb + reset_value: '0' + width: '1' + - dir: input + name: sel + reset_value: '''b0' + width: WB_DATA_WIDTH/8 + reset: reset + reset_assertion_level: 'True' + transaction_constraints: [] + transaction_vars: + - comment: '' + iscompare: 'True' + isrand: 'True' + name: data + type: bit [WB_DATA_WIDTH-1:0] + unpacked_dimension: '' + use_dpi_link: 'False' diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_3/block3_env.yaml b/UVM_Framework/UVMF_2022.3/challenge_3/block_3/block3_env.yaml new file mode 100644 index 00000000..2b65247a --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_3/block3_env.yaml @@ -0,0 +1,45 @@ +uvmf: + benches: + "block_3" : + ## Specify the top-level block + top_env: "block_3" + clock_half_period: "5ns" + reset_assertion_level: "True" + reset_duration: "200ns" + environments: + "block_3" : + agents : + - name: "wb_master" + type: "wb_m" + initiator_responder: "INITIATOR" + - name: "axi_slave" + type: "axi_s" + initiator_responder: "RESPONDER" + analysis_components : + - name: "block_3_pred" + type: "block_3_predictor" + - name: "block_3_sb" + type: "block_3_scoreboard" + + analysis_ports: + - name: wb_master_ap + trans_type: wb_m_transaction + connected_to: wb_master.monitored_ap + - name: axi_slave_ap + trans_type: axi_s_transaction + connected_to: axi_slave.monitored_ap + + tlm_connections: + - driver: wb_master.monitored_ap + receiver: block_3_pred.wb_ae + - driver: axi_slave.monitored_ap + receiver: block_3_sb.axi_ae + - driver: block_3_pred.pre_to_sco_ap + receiver: block_3_sb.sco_from_pre_ae + + config_vars: + - name: "has_scoreboard" + type: bit + isrand: "False" + + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_3/block3_util.yaml b/UVM_Framework/UVMF_2022.3/challenge_3/block_3/block3_util.yaml new file mode 100644 index 00000000..bf858e70 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_3/block3_util.yaml @@ -0,0 +1,17 @@ +uvmf: + util_components: + block_3_predictor: + analysis_exports: + - name: wb_ae + type: 'wb_m_transaction' + analysis_ports: + - name: pre_to_sco_ap + type: 'axi_s_transaction' + type: predictor + block_3_scoreboard: + analysis_exports: + - name: axi_ae + type: 'axi_s_transaction' + - name: sco_from_pre_ae + type: 'axi_s_transaction' + type: scoreboard diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_3/block_3.csh b/UVM_Framework/UVMF_2022.3/challenge_3/block_3/block_3.csh new file mode 100644 index 00000000..bed83e97 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_3/block_3.csh @@ -0,0 +1,7 @@ +# Setting the path for making "make cli" command works fine. + +setenv UVMF_HOME /hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3/ + +# This is the command to generate you block_3_level bench + +python ../../../UVMF_2022.3/scripts/yaml2uvmf.py ../intf/wb_m_intf.yaml ../intf/axi_s_intf.yaml ../block_3/block3_env.yaml ../block_3/block3_util.yaml diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/project_benches/block_3/.project b/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/project_benches/block_3/.project new file mode 100644 index 00000000..ba9cab02 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/project_benches/block_3/.project @@ -0,0 +1,37 @@ + + + block_3 + + + + + + org.python.pydev.PyDevBuilder + + + + + net.sf.sveditor.core.SVProjectBuilder + + + + + + net.sf.sveditor.core.SVNature + org.python.pydev.pythonNature + + + + verification_ip + 2 + UVMF_VIP_LIBRARY_HOME + + + + + UVMF_VIP_LIBRARY_HOME + $%7BPARENT-2-PROJECT_LOC%7D/verification_ip + + + + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/project_benches/block_3/.svproject b/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/project_benches/block_3/.svproject new file mode 100644 index 00000000..e998cea7 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/project_benches/block_3/.svproject @@ -0,0 +1,16 @@ + + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/project_benches/block_3/block_3_sve.F b/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/project_benches/block_3/block_3_sve.F new file mode 100644 index 00000000..0c6abe1a --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/project_benches/block_3/block_3_sve.F @@ -0,0 +1,28 @@ + +// UVM ++incdir+${UVM_HOME}/src +${UVM_HOME}/src/uvm_pkg.sv + +// Common UVMF files +-f ${UVMF_HOME}/common/common_sve.f + +// BFM Files +-F ${UVMF_VIP_LIBRARY_HOME}/interface_packages/wb_m_pkg/wb_m_pkg_sve.F +-F ${UVMF_VIP_LIBRARY_HOME}/interface_packages/axi_s_pkg/axi_s_pkg_sve.F + +// Environment Files +-F ${UVMF_VIP_LIBRARY_HOME}/environment_packages/block_3_env_pkg/block_3_env_pkg_sve.F + +// Bench Files ++incdir+./tb/tests +./tb/tests/block_3_tests_pkg.sv + ++incdir+./tb/sequences +./tb/sequences/block_3_sequences_pkg.sv + ++incdir+./tb/parameters +./tb/parameters/block_3_parameters_pkg.sv + +./tb/testbench/hdl_top.sv +./tb/testbench/hvl_top.sv + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/project_benches/block_3/docs/interfaces.csv b/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/project_benches/block_3/docs/interfaces.csv new file mode 100644 index 00000000..82c2e9d0 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/project_benches/block_3/docs/interfaces.csv @@ -0,0 +1,14 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// + +, +Interface Description, Interface Type, Interface Transaction, Interface Name, +wb_master, wb_m_driver_bfm wb_m_monitor_bfm, wb_m_transaction, wb_m_pkg_wb_master_BFM, +axi_slave, axi_s_driver_bfm axi_s_monitor_bfm, axi_s_transaction, axi_s_pkg_axi_slave_BFM, + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/project_benches/block_3/rtl/dut.compile b/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/project_benches/block_3/rtl/dut.compile new file mode 100644 index 00000000..9b0008fc --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/project_benches/block_3/rtl/dut.compile @@ -0,0 +1,6 @@ + +# pragma uvmf custom dut_compile_info begin +src: + - ./vhdl/vhdl_dut.vhd + - ./verilog/verilog_dut.v +# pragma uvmf custom dut_compile_info end diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/project_benches/block_3/rtl/verilog/verilog_dut.v b/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/project_benches/block_3/rtl/verilog/verilog_dut.v new file mode 100644 index 00000000..96198441 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/project_benches/block_3/rtl/verilog/verilog_dut.v @@ -0,0 +1,21 @@ +module verilog_dut(clk, rst, in_signal, out_signal); + +input clk; +input rst; +input in_signal; +output out_signal; + +reg out_signal_o; + +always @(posedge clk) begin + if (rst) begin + out_signal_o <= 0; + end + else begin + out_signal_o <= ~in_signal; + end + end + +assign out_signal = out_signal_o; + +endmodule diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/project_benches/block_3/rtl/verilog/verilog_dut.vinfo b/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/project_benches/block_3/rtl/verilog/verilog_dut.vinfo new file mode 100644 index 00000000..87e95f36 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/project_benches/block_3/rtl/verilog/verilog_dut.vinfo @@ -0,0 +1 @@ +verilog_dut.v diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/project_benches/block_3/rtl/vhdl/vhdl_dut.vhd b/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/project_benches/block_3/rtl/vhdl/vhdl_dut.vhd new file mode 100644 index 00000000..904aa37d --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/project_benches/block_3/rtl/vhdl/vhdl_dut.vhd @@ -0,0 +1,21 @@ +library ieee; +use ieee.std_logic_1164.all ; + +entity vhdl_dut is + port ( clk : in std_logic ; + rst : in std_logic ; + in_signal : in std_logic ; + out_signal :out std_logic + ); +end vhdl_dut; + +architecture rtl of vhdl_dut is + begin + P1: process + variable out_signal_o : std_logic; + begin + wait until clk'event and clk = '1'; + out_signal_o := in_signal; + out_signal <= out_signal_o; + end process; + end rtl; diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/project_benches/block_3/sim/Makefile b/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/project_benches/block_3/sim/Makefile new file mode 100644 index 00000000..3866116c --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/project_benches/block_3/sim/Makefile @@ -0,0 +1,199 @@ + +# +#---------------------------------------------------------------------- +# +# DESCRIPTION: This makefile includes the shared makefile and contains +# bench level make targets. +# +#---------------------------------------------------------------------- + + +# pragma uvmf custom additional begin +# pragma uvmf custom additional end + +# ********************************************************************************************* +# UVMF library directory: +# This variable points to the UVMF release where uvmf_base_pkg directory resides. +# This variable points to release code that is not user modified. +# This variable allows for UVMF release directories to reside independent of project related verification IP and project bench directories. +# This code below looks "upward" for directory starting with UVMF_* and returns first match for use with the release examples. +UVMF_HOME ?= ___PLEASE_SET_AN_ENVIRONMENT_VARIABLE_NAMED_UVMF_HOME_TO_POINT_TO_THE_UVMF_INSTALLATION___ + +# pragma uvmf custom exports begin +# +# Project(s) specific verification IP library: +# Directory where reusable verification packages for interfaces, environments, utilities, etc. reside. +# This variable allows for your verification IP to reside independent of project bench and UVMF release directories. +# For examples deployed with UVMF this will be $(UVMF_HOME)//verification_ip +export UVMF_VIP_LIBRARY_HOME ?= $(PWD)/../../../verification_ip +# +# Project specific bench: +# Directory where bench specific code is located. +# This variable allows for project_benches to reside independent of verification IP and UVMF release directories. +# For examples deployed with UVMF this will be $(UVMF_HOME)//project_benches/ +export UVMF_PROJECT_DIR ?= $(PWD)/.. +# +# +# pragma uvmf custom exports end +# ********************************************************************************************* + +## Check PATH for required vinfo scripts +PVAL := $(shell command -v make_filelist.py 2> /dev/null) +ifndef PVAL + MFLIST = $(UVMF_HOME)/scripts/make_filelist.py +else + MFLIST = make_filelist.py +endif + + +# Set test case specific Variables +TEST_NAME ?= test_top + +TEST_SEED ?= random +UVM_CLI_ARGS = + +# Usage of Veloce, etc. to be input by the user (subject to defaults) +USE_VELOCE ?= 0 + +# Usage of vinfo flow for generating file list +USE_VINFO ?= 0 + +# Usage of Veloce and Questa profilers +USE_VELOCE_PROFILER ?= 0 +USE_QUESTA_PROFILER ?= 0 + + +# Set project Variables +TEST_PLAN_NAME = block_3_TestPlan +REPORTING_DO_FILE = block_3_reports_script + + +# Include makefile that includes targets for UVM_VIP_Library packages +include $(UVMF_HOME)/scripts/Makefile + + + + +# Include all requisite interface package targets for this bench +include $(UVMF_VIP_LIBRARY_HOME)/interface_packages/wb_m_pkg/Makefile +include $(UVMF_VIP_LIBRARY_HOME)/interface_packages/axi_s_pkg/Makefile + +# Include all requisite environment package targets for this bench +include $(UVMF_VIP_LIBRARY_HOME)/environment_packages/block_3_env_pkg/Makefile + + + +# Add to default compile/load/run arguments +VCOM_ARGS += + +# Note: vsim-3009 error can be eliminated by adding -timescale 1ps/1ps to VLOG_ARGS + +VLOG_ARGS += $(UVM_DISABLE_FILE_LINE_CMD) + +VELANALYZE_ARGS += +VELANALYZE_HVL_ARGS += + +BATCH_VOPT_ARGS += +DEBUG_VOPT_ARGS += +EXTRA_VOPT_TOPS += +COMMON_VSIM_ARGS += +COMMON_VSIM_ARGS += + + +BATCH_VSIM_ARGS += #-uvmcontrol=none +DEBUG_VSIM_ARGS += +EXTRA_VSIM_TOPS += + +# pragma uvmf custom additional_args begin +# pragma uvmf custom additional_args end + + +# Project bench package source +block_3_PARAMETERS_PKG ?=\ +$(UVMF_PROJECT_DIR)/tb/parameters/block_3_parameters_pkg.sv + + +block_3_SEQUENCES_PKG ?=\ +$(UVMF_PROJECT_DIR)/tb/sequences/block_3_sequences_pkg.sv + + +block_3_TEST_PKG ?=\ +$(UVMF_PROJECT_DIR)/tb/tests/block_3_tests_pkg.sv + +# pragma uvmf custom dut_files begin +# UVMF_CHANGE_ME : Reference Verilog DUT source. +block_3_VERILOG_DUT ?=\ +$(UVMF_PROJECT_DIR)/rtl/verilog/verilog_dut.v + +# UVMF_CHANGE_ME : Reference VHDL DUT source. +block_3_VHDL_DUT ?=\ +$(UVMF_PROJECT_DIR)/rtl/vhdl/vhdl_dut.vhd +# pragma uvmf custom dut_files end + + +# Project bench package targets +COMP_block_3_PARAMETERS_PKG_TGT_0 = q_comp_block_3_parameters_pkg +COMP_block_3_PARAMETERS_PKG_TGT_1 = v_comp_block_3_parameters_pkg +COMP_block_3_PARAMETERS_PKG_TGT = $(COMP_block_3_PARAMETERS_PKG_TGT_$(USE_VELOCE)) + +comp_block_3_parameters_pkg: $(COMP_block_3_PARAMETERS_PKG_TGT) + +q_comp_block_3_parameters_pkg: + $(HVL_COMP_CMD) +incdir+$(UVMF_PROJECT_DIR)/tb/parameters $(block_3_PARAMETERS_PKG) + +v_comp_block_3_parameters_pkg: q_comp_block_3_parameters_pkg + $(HDL_COMP_CMD) +incdir+$(UVMF_PROJECT_DIR)/tb/parameters $(block_3_PARAMETERS_PKG) + + +comp_block_3_sequence_pkg: + $(HVL_COMP_CMD) +incdir+$(UVMF_PROJECT_DIR)/tb/sequences $(block_3_SEQUENCES_PKG) + +comp_block_3_tests_pkg: + $(HVL_COMP_CMD) +incdir+$(UVMF_PROJECT_DIR)/tb/tests $(block_3_TEST_PKG) + +# pragma uvmf custom dut_compile_make_target begin +# UVMF_CHANGE_ME : Add make target to compile your verilog dut here +comp_block_3_verilog_dut: + echo "Compile your verilog DUT here" + $(HDL_COMP_CMD) $(block_3_VERILOG_DUT) + +# UVMF_CHANGE_ME : Add make target to compile your vhdl dut here +comp_block_3_vhdl_dut: + echo "Compile your vhdl DUT here" + $(HDL_COMP_CMD_VHDL) $(block_3_VHDL_DUT) + +# UVMF_CHANGE_ME : Add make target to compile your dut here +comp_block_3_dut: comp_block_3_vhdl_dut comp_block_3_verilog_dut +# pragma uvmf custom dut_compile_make_target end + + +BUILD_TGT_0 = make_build +BUILD_TGT_1 = vinfo_build +BUILD_TGT = $(BUILD_TGT_$(USE_VINFO)) + + +comp_hvl : comp_hvl_core + + +comp_hvl_core : \ + comp_wb_m_pkg comp_axi_s_pkg \ + comp_block_3_env_pkg \ + comp_block_3_parameters_pkg comp_block_3_sequence_pkg comp_block_3_tests_pkg + +comp_uvmf_core : comp_uvm_pkg comp_uvmf_base_pkg + +make_build: comp_block_3_dut comp_uvmf_core comp_hvl comp_test_bench + +hvl_build: q_comp_wb_m_pkg q_comp_axi_s_pkg comp_block_3_env_pkg comp_block_3_sequence_pkg comp_block_3_tests_pkg hvl_comp_testbench link optimize + + +vinfo_build: comp_block_3_vhdl_dut build_hdl_vinfo build_hvl_vinfo $(VINFO_TGT) + + $(HDL_COMP_CMD) -F hdl.vf + $(VEL_COMP) + +build: $(BUILD_TGT) + +# pragma uvmf custom additional_targets begin +# pragma uvmf custom additional_targets end + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/project_benches/block_3/sim/bcr_testlist b/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/project_benches/block_3/sim/bcr_testlist new file mode 100644 index 00000000..482f01fc --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/project_benches/block_3/sim/bcr_testlist @@ -0,0 +1,19 @@ + + + +# Test list for use by RMDB file +# File syntax is +# TB_INFO { } { } +# TB ## All subsequent tests will run on this bench until a different "TB" line is seen +# TEST <1st_seed> ... +# If not enough seeds are provided then random seeds are used to pad +# If no repeat count is given, default is 1 +# pragma uvmf custom tb_info begin +TB_INFO block_3 { } { } +# pragma uvmf custom tb_info end +TB block_3 +# pragma uvmf custom regression_suite begin +TEST test_top 3 +# pragma uvmf custom regression_suite end + + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/project_benches/block_3/sim/bcr_testlist.yaml b/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/project_benches/block_3/sim/bcr_testlist.yaml new file mode 100644 index 00000000..ac85d606 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/project_benches/block_3/sim/bcr_testlist.yaml @@ -0,0 +1,44 @@ + + + +# YAML test list for use by RMDB file +# File syntax is +# uvmf_testlist: +# testbenches: +# - name: +# extra_build_options: +# extra_run_options: +# - name: +# ... +# - name: +# tests: +# - name: +# uvm_testname: (defaults to test_name) +# testbench: (defaults to last tb name seen) +# repeat: (defaults to 1) +# seeds: [,,...,] (defaults to all random) +# extra_test_options: +# - name: +# ... +# - name: +# include: +# - (relative path reference is to the including YAML file) +# - +# ... +# - + +uvmf_testlist: + testbenches: +# pragma uvmf custom tb_info begin + - name: block_3 + extra_build_options: "" + extra_run_options: "" +# pragma uvmf custom tb_info end + tests: + - testbench: block_3 +# pragma uvmf custom regression_suite begin + - name: test_top + repeat: 3 +# pragma uvmf custom regression_suite end + + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/project_benches/block_3/sim/compile.do b/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/project_benches/block_3/sim/compile.do new file mode 100644 index 00000000..dba7d6f1 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/project_benches/block_3/sim/compile.do @@ -0,0 +1,71 @@ + + +################################################################## +## ENVIRONMENT VARIABLES +################################################################## +quietly set ::env(UVMF_VIP_LIBRARY_HOME) ../../../verification_ip +quietly set ::env(UVMF_PROJECT_DIR) .. + +## Using VRM means that the build is occuring several more directories deeper underneath +## the sim directory, need to prepend some more '..' +if {[info exists ::env(VRM_BUILD)]} { + quietly set ::env(UVMF_VIP_LIBRARY_HOME) "../../../../../$::env(UVMF_VIP_LIBRARY_HOME)" + quietly set ::env(UVMF_PROJECT_DIR) "../../../../../$::env(UVMF_PROJECT_DIR)" +} +quietly set ::env(UVMF_VIP_LIBRARY_HOME) [file normalize $::env(UVMF_VIP_LIBRARY_HOME)] +quietly set ::env(UVMF_PROJECT_DIR) [file normalize $::env(UVMF_PROJECT_DIR)] +quietly echo "UVMF_VIP_LIBRARY_HOME = $::env(UVMF_VIP_LIBRARY_HOME)" +quietly echo "UVMF_PROJECT_DIR = $::env(UVMF_PROJECT_DIR)" + + +################################################################### +## HOUSEKEEPING : DELETE FILES THAT WILL BE REGENERATED +################################################################### +file delete -force *~ *.ucdb vsim.dbg *.vstf *.log work *.mem *.transcript.txt certe_dump.xml *.wlf covhtmlreport VRMDATA +file delete -force design.bin qwave.db dpiheader.h visualizer*.ses +file delete -force veloce.med veloce.wave veloce.map tbxbindings.h edsenv velrunopts.ini +file delete -force sv_connect.* + +################################################################### +## COMPILE DUT SOURCE CODE +################################################################### +vlib work +# pragma uvmf custom dut_compile_dofile_target begin +# UVMF_CHANGE_ME : Add commands to compile your dut here, replacing the default examples +vlog -sv -timescale 1ps/1ps -suppress 2223,2286 $env(UVMF_PROJECT_DIR)/rtl/verilog/verilog_dut.v +vcom $env(UVMF_PROJECT_DIR)/rtl/vhdl/vhdl_dut.vhd +# pragma uvmf custom dut_compile_dofile_target end + +################################################################### +## COMPILE UVMF BASE/COMMON SOURCE CODE +################################################################### +vlog -sv -timescale 1ps/1ps -suppress 2223 -suppress 2286 +incdir+$env(UVMF_HOME)/uvmf_base_pkg -F $env(UVMF_HOME)/uvmf_base_pkg/uvmf_base_pkg_filelist_hdl.f +vlog -sv -timescale 1ps/1ps -suppress 2223 -suppress 2286 +incdir+$env(UVMF_HOME)/uvmf_base_pkg -F $env(UVMF_HOME)/uvmf_base_pkg/uvmf_base_pkg_filelist_hvl.f + + +################################################################### +## UVMF INTERFACE COMPILATION +################################################################### +do $env(UVMF_VIP_LIBRARY_HOME)/interface_packages/wb_m_pkg/compile.do +do $env(UVMF_VIP_LIBRARY_HOME)/interface_packages/axi_s_pkg/compile.do + +################################################################### +## UVMF ENVIRONMENT COMPILATION +################################################################### +do $env(UVMF_VIP_LIBRARY_HOME)/environment_packages/block_3_env_pkg/compile.do + +################################################################### +## UVMF BENCHES COMPILATION +################################################################### +vlog -sv -timescale 1ps/1ps -suppress 2223 -suppress 2286 +incdir+$env(UVMF_PROJECT_DIR)/tb/parameters $env(UVMF_PROJECT_DIR)/tb/parameters/block_3_parameters_pkg.sv +vlog -sv -timescale 1ps/1ps -suppress 2223 -suppress 2286 +incdir+$env(UVMF_PROJECT_DIR)/tb/sequences $env(UVMF_PROJECT_DIR)/tb/sequences/block_3_sequences_pkg.sv +vlog -sv -timescale 1ps/1ps -suppress 2223 -suppress 2286 +incdir+$env(UVMF_PROJECT_DIR)/tb/tests $env(UVMF_PROJECT_DIR)/tb/tests/block_3_tests_pkg.sv + +vlog -sv -timescale 1ps/1ps -suppress 2223 -suppress 2286 +incdir+$env(UVMF_PROJECT_DIR)/tb/testbench -F $env(UVMF_PROJECT_DIR)/tb/testbench/top_filelist_hdl.f +vlog -sv -timescale 1ps/1ps -suppress 2223 -suppress 2286 +incdir+$env(UVMF_PROJECT_DIR)/tb/testbench -F $env(UVMF_PROJECT_DIR)/tb/testbench/top_filelist_hvl.f + +################################################################### +## OPTIMIZATION +################################################################### +vopt hvl_top hdl_top -o optimized_batch_top_tb +vopt +acc hvl_top hdl_top -o optimized_debug_top_tb diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/project_benches/block_3/sim/hdl.compile b/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/project_benches/block_3/sim/hdl.compile new file mode 100644 index 00000000..8e7bd41a --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/project_benches/block_3/sim/hdl.compile @@ -0,0 +1,5 @@ +needs: +# pragma uvmf custom dut_compile_info begin + - ../rtl/dut.compile +# pragma uvmf custom dut_compile_info end + - ../tb/testbench/hdl_top.compile diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/project_benches/block_3/sim/hdl.vinfo b/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/project_benches/block_3/sim/hdl.vinfo new file mode 100644 index 00000000..da27ec77 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/project_benches/block_3/sim/hdl.vinfo @@ -0,0 +1 @@ +@use $UVMF_PROJECT_DIR/tb/testbench/hdl_top.vinfo diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/project_benches/block_3/sim/hvl.compile b/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/project_benches/block_3/sim/hvl.compile new file mode 100644 index 00000000..ce952549 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/project_benches/block_3/sim/hvl.compile @@ -0,0 +1,2 @@ +needs: + - ../tb/testbench/hvl_top.compile diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/project_benches/block_3/sim/hvl.vinfo b/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/project_benches/block_3/sim/hvl.vinfo new file mode 100644 index 00000000..d22eff33 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/project_benches/block_3/sim/hvl.vinfo @@ -0,0 +1 @@ +@use $UVMF_PROJECT_DIR/tb/testbench/hvl_top.vinfo diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/project_benches/block_3/sim/run.do b/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/project_benches/block_3/sim/run.do new file mode 100644 index 00000000..101ddc48 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/project_benches/block_3/sim/run.do @@ -0,0 +1,21 @@ + + +quietly set svLibs "" +quietly set extra_vsim_args "" + +################################################################### +## Check for additional vsim arguments passed using env var $UVMF_EXTRA_VSIM_ARGS +################################################################### +if {[info exists ::env(UVMF_EXTRA_VSIM_ARGS)]} { + echo "Adding more args to vsim command" + quietly set extra_vsim_args $::env(UVMF_EXTRA_VSIM_ARGS) +} + +################################################################## +## Launch Questa : generate vsim command line and execute +################################################################## +# pragma uvmf custom dut_run_dofile_target begin +# UVMF_CHANGE_ME : Change the UVM_TESTNAME plusarg to run a different test +quietly set cmd [format "vsim -i -sv_seed random +UVM_TESTNAME=test_top +UVM_VERBOSITY=UVM_HIGH -permit_unmatched_virtual_intf +notimingchecks -suppress 8887 %s %s -uvmcontrol=all -msgmode both -classdebug -assertdebug +uvm_set_config_int=*,enable_transaction_viewing,1 -do { set NoQuitOnFinish 1; onbreak {resume}; run 0; do wave.do; set PrefSource(OpenOnBreak) 0; radix hex showbase; } optimized_debug_top_tb" $svLibs $extra_vsim_args] +# pragma uvmf custom dut_run_dofile_target end +eval $cmd diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/project_benches/block_3/sim/tbx.config b/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/project_benches/block_3/sim/tbx.config new file mode 100644 index 00000000..eec58168 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/project_benches/block_3/sim/tbx.config @@ -0,0 +1,10 @@ + + + + + +comp -questa +velsyn -D1S +rtlc -allow_4ST + + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/project_benches/block_3/sim/testlist b/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/project_benches/block_3/sim/testlist new file mode 100644 index 00000000..c770870e --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/project_benches/block_3/sim/testlist @@ -0,0 +1,20 @@ + + + + +# Test list for use by RMDB file +# File syntax is +# TB_INFO { } { } +# TB ## All subsequent tests will run on this bench until a different "TB" line is seen +# TEST <1st_seed> ... +# If not enough seeds are provided then random seeds are used to pad +# If no repeat count is given, default is 1 +# pragma uvmf custom tb_info begin +TB_INFO block_3 { UVMF_VIP_LIBRARY_HOME=../../../../../../../../verification_ip UVMF_PROJECT_DIR=../../../../../../../block_3 } { } +# pragma uvmf custom tb_info end +TB block_3 +# pragma uvmf custom regression_suite begin +TEST test_top 3 +# pragma uvmf custom regression_suite end + + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/project_benches/block_3/sim/testlist.yaml b/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/project_benches/block_3/sim/testlist.yaml new file mode 100644 index 00000000..2eb1c8dc --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/project_benches/block_3/sim/testlist.yaml @@ -0,0 +1,44 @@ + + + +# YAML test list for use by RMDB file +# File syntax is +# uvmf_testlist: +# testbenches: +# - name: +# extra_build_options: +# extra_run_options: +# - name: +# ... +# - name: +# tests: +# - name: +# uvm_testname: (defaults to test_name) +# testbench: (defaults to last tb name seen) +# repeat: (defaults to 1) +# seeds: [,,...,] (defaults to all random) +# extra_test_options: +# - name: +# ... +# - name: +# include: +# - (relative path reference is to the including YAML file) +# - +# ... +# - + +uvmf_testlist: + testbenches: +# pragma uvmf custom tb_info begin + - name: block_3 + extra_build_options: "UVMF_VIP_LIBRARY_HOME=../../../../../../../../verification_ip UVMF_PROJECT_DIR=../../../../../../../block_3" + extra_run_options: "" +# pragma uvmf custom tb_info end + tests: + - testbench: block_3 +# pragma uvmf custom regression_suite begin + - name: test_top + repeat: 3 +# pragma uvmf custom regression_suite end + + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/project_benches/block_3/sim/top.compile b/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/project_benches/block_3/sim/top.compile new file mode 100644 index 00000000..efd51c07 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/project_benches/block_3/sim/top.compile @@ -0,0 +1,3 @@ +needs: + - hvl.compile + - hdl.compile diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/project_benches/block_3/sim/veloce.config b/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/project_benches/block_3/sim/veloce.config new file mode 100644 index 00000000..d0975155 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/project_benches/block_3/sim/veloce.config @@ -0,0 +1,26 @@ + + + + + +# pragma uvmf custom additional begin +comp -num_boards 1 +comp -hvl questa +# Please choose the correct emulator type code for +# comp -platform command or else velcomp will fail +# Available types are: +# - Veloce2 Quattro: D2 +# - Veloce2 Maximus: D2M +# - Veloce Strato TiL, Ti, and Mi: Strato +# - Veloce Strato M and Strato T: StratoM +# - comp -platform +comp -platform Strato + +rtlc -enable_tbx_pragma_checks +rtlc -allow_4ST +rtlc -allow_MDR +rtlc -compile_display +rtlc -xwave_siglist xwaves.sigs +# pragma uvmf custom additional end + + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/project_benches/block_3/sim/viswave.do b/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/project_benches/block_3/sim/viswave.do new file mode 100644 index 00000000..6b69c9ea --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/project_benches/block_3/sim/viswave.do @@ -0,0 +1,22 @@ + + +onerror resume +wave tags F0 +wave update off + +wave spacer -backgroundcolor Salmon { wb_master } +wave add uvm_test_top.environment.wb_master.wb_master_monitor.txn_stream -radix string -tag F0 +wave group wb_master_bus +wave add -group wb_master_bus hdl_top.wb_master_bus.* -radix hexadecimal -tag F0 +wave group wb_master_bus -collapse +wave insertion [expr [wave index insertpoint] +1] +wave spacer -backgroundcolor Salmon { axi_slave } +wave add uvm_test_top.environment.axi_slave.axi_slave_monitor.txn_stream -radix string -tag F0 +wave group axi_slave_bus +wave add -group axi_slave_bus hdl_top.axi_slave_bus.* -radix hexadecimal -tag F0 +wave group axi_slave_bus -collapse +wave insertion [expr [wave index insertpoint] +1] + +wave update on +WaveSetStreamView + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/project_benches/block_3/sim/wave.do b/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/project_benches/block_3/sim/wave.do new file mode 100644 index 00000000..ad8536c6 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/project_benches/block_3/sim/wave.do @@ -0,0 +1,30 @@ + + +onerror {resume} +quietly WaveActivateNextPane {} 0 + +add wave -noupdate -divider wb_master +add wave -noupdate /uvm_root/uvm_test_top/environment/wb_master/wb_master_monitor/txn_stream +add wave -noupdate -group wb_master_bus /hdl_top/wb_master_bus/* +add wave -noupdate -divider axi_slave +add wave -noupdate /uvm_root/uvm_test_top/environment/axi_slave/axi_slave_monitor/txn_stream +add wave -noupdate -group axi_slave_bus /hdl_top/axi_slave_bus/* + +TreeUpdate [SetDefaultTree] +quietly wave cursor active 0 +configure wave -namecolwidth 472 +configure wave -valuecolwidth 100 +configure wave -justifyvalue left +configure wave -signalnamewidth 0 +configure wave -snapdistance 10 +configure wave -datasetprefix 0 +configure wave -rowmargin 4 +configure wave -childrowmargin 2 +configure wave -gridoffset 0 +configure wave -gridperiod 1 +configure wave -griddelta 40 +configure wave -timeline 0 +configure wave -timelineunits ns +update +WaveRestoreZoom {27 ns} {168 ns} + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/project_benches/block_3/sim/work/_info b/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/project_benches/block_3/sim/work/_info new file mode 100644 index 00000000..6e78a329 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/project_benches/block_3/sim/work/_info @@ -0,0 +1,1328 @@ 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/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/macros/uvm_deprecated_defines.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/macros/uvm_reg_defines.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/macros/uvm_callback_defines.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/macros/uvm_sequence_defines.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/tlm1/uvm_tlm_imps.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/macros/uvm_tlm_defines.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/macros/uvm_printer_defines.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/macros/uvm_object_defines.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/macros/uvm_phase_defines.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/macros/uvm_message_defines.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/macros/uvm_version_defines.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/uvm_macros.svh|/hwetools/work_area/frontend/vineeth_b7/system/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/project_benches/block_3/sim/../../../verification_ip/interface_packages/axi_s_pkg/src/axi_s_macros.svh|/hwetools/work_area/frontend/vineeth_b7/system/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/project_benches/block_3/sim/../../../verification_ip/interface_packages/axi_s_pkg/src/axi_s_driver_bfm.sv|/hwetools/work_area/frontend/vineeth_b7/system/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/project_benches/block_3/sim/../../../verification_ip/interface_packages/axi_s_pkg/src/axi_s_monitor_bfm.sv|/hwetools/work_area/frontend/vineeth_b7/system/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/project_benches/block_3/sim/../../../verification_ip/interface_packages/axi_s_pkg/src/axi_s_if.sv| +Z27 !s90 -sv|-suppress|2223|-suppress|2286|+define+UVM_REPORT_DISABLE_FILE_LINE|+define+UVM_REPORT_DISABLE_FILE_LINE|+incdir+/hwetools/work_area/frontend/vineeth_b7/system/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/project_benches/block_3/sim/../../../verification_ip/interface_packages/axi_s_pkg|-F|/hwetools/work_area/frontend/vineeth_b7/system/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/project_benches/block_3/sim/../../../verification_ip/interface_packages/axi_s_pkg/axi_s_filelist_xrtl.f| +>>>>>>> ceab28f188594b972dededef57152e3a46196cbf +!i113 0 +Z28 o-suppress 2223 -suppress 2286 -sv -L mtiAvm -L mtiRnm -L mtiOvm -L mtiUvm -L mtiUPF -L infact +Z29 !s92 -suppress 2223 -suppress 2286 -sv +define+UVM_REPORT_DISABLE_FILE_LINE +define+UVM_REPORT_DISABLE_FILE_LINE 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ceab28f188594b972dededef57152e3a46196cbf +!i10b 1 +!s100 eK8QGRQH_g_00l:imN4l=2 +IPEbFemIkj1Bf2b01UW0MC1 +VPEbFemIkj1Bf2b01UW0MC1 +S1 +R0 +<<<<<<< HEAD +Z40 w1672041095 +8/hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/project_benches/block_3/sim/../../../verification_ip/interface_packages/axi_s_pkg/axi_s_pkg.sv +F/hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/project_benches/block_3/sim/../../../verification_ip/interface_packages/axi_s_pkg/axi_s_pkg.sv +======= +R8 +8/hwetools/work_area/frontend/vineeth_b7/system/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/project_benches/block_3/sim/../../../verification_ip/interface_packages/axi_s_pkg/axi_s_pkg.sv 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/hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/project_benches/block_3/sim/../../../verification_ip/environment_packages/block_3_env_pkg/src/block_3_env_sequence_base.svh|/hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/project_benches/block_3/sim/../../../verification_ip/environment_packages/block_3_env_pkg/src/block_3_environment.svh|/hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/project_benches/block_3/sim/../../../verification_ip/environment_packages/block_3_env_pkg/src/block_3_scoreboard.svh|/hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/project_benches/block_3/sim/../../../verification_ip/environment_packages/block_3_env_pkg/src/block_3_predictor.svh|/hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/project_benches/block_3/sim/../../../verification_ip/environment_packages/block_3_env_pkg/src/block_3_env_configuration.svh|/hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/project_benches/block_3/sim/../../../verification_ip/environment_packages/block_3_env_pkg/src/block_3_env_typedefs.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/macros/uvm_deprecated_defines.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/macros/uvm_reg_defines.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/macros/uvm_callback_defines.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/macros/uvm_sequence_defines.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/tlm1/uvm_tlm_imps.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/macros/uvm_tlm_defines.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/macros/uvm_printer_defines.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/macros/uvm_object_defines.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/macros/uvm_phase_defines.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/macros/uvm_message_defines.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/macros/uvm_version_defines.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/uvm_macros.svh|/hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/project_benches/block_3/sim/../../../verification_ip/environment_packages/block_3_env_pkg/block_3_env_pkg.sv| +!s90 -sv|-suppress|2223|-suppress|2286|+define+UVM_REPORT_DISABLE_FILE_LINE|+define+UVM_REPORT_DISABLE_FILE_LINE|+incdir+/hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/project_benches/block_3/sim/../../../verification_ip/environment_packages/block_3_env_pkg|/hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/project_benches/block_3/sim/../../../verification_ip/environment_packages/block_3_env_pkg/block_3_env_pkg.sv| +======= +!s108 1672030791.000000 +!s107 /hwetools/work_area/frontend/vineeth_b7/system/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/project_benches/block_3/sim/../../../verification_ip/environment_packages/block_3_env_pkg/src/block_3_env_sequence_base.svh|/hwetools/work_area/frontend/vineeth_b7/system/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/project_benches/block_3/sim/../../../verification_ip/environment_packages/block_3_env_pkg/src/block_3_environment.svh|/hwetools/work_area/frontend/vineeth_b7/system/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/project_benches/block_3/sim/../../../verification_ip/environment_packages/block_3_env_pkg/src/block_3_scoreboard.svh|/hwetools/work_area/frontend/vineeth_b7/system/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/project_benches/block_3/sim/../../../verification_ip/environment_packages/block_3_env_pkg/src/block_3_predictor.svh|/hwetools/work_area/frontend/vineeth_b7/system/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/project_benches/block_3/sim/../../../verification_ip/environment_packages/block_3_env_pkg/src/block_3_env_configuration.svh|/hwetools/work_area/frontend/vineeth_b7/system/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/project_benches/block_3/sim/../../../verification_ip/environment_packages/block_3_env_pkg/src/block_3_env_typedefs.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/macros/uvm_deprecated_defines.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/macros/uvm_reg_defines.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/macros/uvm_callback_defines.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/macros/uvm_sequence_defines.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/tlm1/uvm_tlm_imps.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/macros/uvm_tlm_defines.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/macros/uvm_printer_defines.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/macros/uvm_object_defines.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/macros/uvm_phase_defines.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/macros/uvm_message_defines.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/macros/uvm_version_defines.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/uvm_macros.svh|/hwetools/work_area/frontend/vineeth_b7/system/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/project_benches/block_3/sim/../../../verification_ip/environment_packages/block_3_env_pkg/block_3_env_pkg.sv| +!s90 -sv|-suppress|2223|-suppress|2286|+define+UVM_REPORT_DISABLE_FILE_LINE|+define+UVM_REPORT_DISABLE_FILE_LINE|+incdir+/hwetools/work_area/frontend/vineeth_b7/system/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/project_benches/block_3/sim/../../../verification_ip/environment_packages/block_3_env_pkg|/hwetools/work_area/frontend/vineeth_b7/system/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/project_benches/block_3/sim/../../../verification_ip/environment_packages/block_3_env_pkg/block_3_env_pkg.sv| +>>>>>>> ceab28f188594b972dededef57152e3a46196cbf +!i113 0 +R28 +!s92 -suppress 2223 -suppress 2286 -sv +define+UVM_REPORT_DISABLE_FILE_LINE +define+UVM_REPORT_DISABLE_FILE_LINE +incdir+/hwetools/work_area/frontend/vineeth_b7/system/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/project_benches/block_3/sim/../../../verification_ip/environment_packages/block_3_env_pkg -L mtiAvm -L mtiRnm -L mtiOvm -L mtiUvm -L mtiUPF -L infact +R30 +Xblock_3_parameters_pkg +R1 +R2 +<<<<<<< HEAD +Z47 !s110 1672041114 +======= +R43 +>>>>>>> ceab28f188594b972dededef57152e3a46196cbf +!i10b 1 +!s100 BHcS[[?[Y^M`KffVL`RED2 +I=ad:JHHjUGd9cF:==h0e;2 +V=ad:JHHjUGd9cF:==h0e;2 +S1 +R0 +<<<<<<< HEAD +R44 +8/hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/project_benches/block_3/sim/../tb/parameters/block_3_parameters_pkg.sv +F/hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/project_benches/block_3/sim/../tb/parameters/block_3_parameters_pkg.sv +Z48 L0 16 +======= +Z45 w1671991596 +8/hwetools/work_area/frontend/vineeth_b7/system/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/project_benches/block_3/sim/../tb/parameters/block_3_parameters_pkg.sv +F/hwetools/work_area/frontend/vineeth_b7/system/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/project_benches/block_3/sim/../tb/parameters/block_3_parameters_pkg.sv +Z46 L0 16 +>>>>>>> ceab28f188594b972dededef57152e3a46196cbf +R24 +r1 +!s85 0 +31 +<<<<<<< HEAD +R46 +!s107 /hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/project_benches/block_3/sim/../tb/parameters/block_3_parameters_pkg.sv| +!s90 -sv|-suppress|2223|-suppress|2286|+define+UVM_REPORT_DISABLE_FILE_LINE|+define+UVM_REPORT_DISABLE_FILE_LINE|+incdir+/hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/project_benches/block_3/sim/../tb/parameters|/hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/project_benches/block_3/sim/../tb/parameters/block_3_parameters_pkg.sv| +======= +Z47 !s108 1672030792.000000 +!s107 /hwetools/work_area/frontend/vineeth_b7/system/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/project_benches/block_3/sim/../tb/parameters/block_3_parameters_pkg.sv| +!s90 -sv|-suppress|2223|-suppress|2286|+define+UVM_REPORT_DISABLE_FILE_LINE|+define+UVM_REPORT_DISABLE_FILE_LINE|+incdir+/hwetools/work_area/frontend/vineeth_b7/system/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/project_benches/block_3/sim/../tb/parameters|/hwetools/work_area/frontend/vineeth_b7/system/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/project_benches/block_3/sim/../tb/parameters/block_3_parameters_pkg.sv| +>>>>>>> ceab28f188594b972dededef57152e3a46196cbf +!i113 0 +R28 +!s92 -suppress 2223 -suppress 2286 -sv +define+UVM_REPORT_DISABLE_FILE_LINE +define+UVM_REPORT_DISABLE_FILE_LINE +incdir+/hwetools/work_area/frontend/vineeth_b7/system/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/project_benches/block_3/sim/../tb/parameters -L mtiAvm -L mtiRnm -L mtiOvm -L mtiUvm -L mtiUPF -L infact +R30 +Xblock_3_sequences_pkg +R1 +R4 +R2 +R5 +R41 +R42 +R3 +R6 +<<<<<<< HEAD +Z49 DXx4 work 22 block_3_parameters_pkg 0 22 P112DR>CH`D_K]2Ybk_YE2 +Z50 DXx4 work 15 block_3_env_pkg 0 22 `cSKIhG[h0TScX_YTHH?T1 +R47 +!i10b 1 +!s100 o?:ebkiG:1 +VJH8E8Rc83F6MFlI?7>iG:1 +S1 +R0 +R44 +8/hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/project_benches/block_3/sim/../tb/sequences/block_3_sequences_pkg.sv +F/hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/project_benches/block_3/sim/../tb/sequences/block_3_sequences_pkg.sv +======= +Z48 DXx4 work 22 block_3_parameters_pkg 0 22 =ad:JHHjUGd9cF:==h0e;2 +Z49 DXx4 work 15 block_3_env_pkg 0 22 WN>YjDklbN@92gJ_FAEG50 +R43 +!i10b 1 +!s100 o?:ebk>>>>>> ceab28f188594b972dededef57152e3a46196cbf +R11 +R12 +R13 +R14 +R15 +R16 +R17 +R18 +R19 +R20 +R21 +R22 +<<<<<<< HEAD +F/hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/project_benches/block_3/sim/../tb/sequences/src/block_3_bench_sequence_base.svh +F/hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/project_benches/block_3/sim/../tb/sequences/src/register_test_sequence.svh +F/hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/project_benches/block_3/sim/../tb/sequences/src/example_derived_test_sequence.svh +R45 +======= +F/hwetools/work_area/frontend/vineeth_b7/system/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/project_benches/block_3/sim/../tb/sequences/src/block_3_bench_sequence_base.svh +F/hwetools/work_area/frontend/vineeth_b7/system/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/project_benches/block_3/sim/../tb/sequences/src/register_test_sequence.svh +F/hwetools/work_area/frontend/vineeth_b7/system/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/project_benches/block_3/sim/../tb/sequences/src/example_derived_test_sequence.svh +R44 +>>>>>>> ceab28f188594b972dededef57152e3a46196cbf +R24 +r1 +!s85 0 +31 +<<<<<<< HEAD +Z51 !s108 1672041114.000000 +!s107 /hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/project_benches/block_3/sim/../tb/sequences/src/example_derived_test_sequence.svh|/hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/project_benches/block_3/sim/../tb/sequences/src/register_test_sequence.svh|/hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/project_benches/block_3/sim/../tb/sequences/src/block_3_bench_sequence_base.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/macros/uvm_deprecated_defines.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/macros/uvm_reg_defines.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/macros/uvm_callback_defines.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/macros/uvm_sequence_defines.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/tlm1/uvm_tlm_imps.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/macros/uvm_tlm_defines.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/macros/uvm_printer_defines.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/macros/uvm_object_defines.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/macros/uvm_phase_defines.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/macros/uvm_message_defines.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/macros/uvm_version_defines.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/uvm_macros.svh|/hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/project_benches/block_3/sim/../tb/sequences/block_3_sequences_pkg.sv| +!s90 -sv|-suppress|2223|-suppress|2286|+define+UVM_REPORT_DISABLE_FILE_LINE|+define+UVM_REPORT_DISABLE_FILE_LINE|+incdir+/hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/project_benches/block_3/sim/../tb/sequences|/hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/project_benches/block_3/sim/../tb/sequences/block_3_sequences_pkg.sv| +======= +R47 +!s107 /hwetools/work_area/frontend/vineeth_b7/system/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/project_benches/block_3/sim/../tb/sequences/src/example_derived_test_sequence.svh|/hwetools/work_area/frontend/vineeth_b7/system/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/project_benches/block_3/sim/../tb/sequences/src/register_test_sequence.svh|/hwetools/work_area/frontend/vineeth_b7/system/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/project_benches/block_3/sim/../tb/sequences/src/block_3_bench_sequence_base.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/macros/uvm_deprecated_defines.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/macros/uvm_reg_defines.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/macros/uvm_callback_defines.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/macros/uvm_sequence_defines.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/tlm1/uvm_tlm_imps.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/macros/uvm_tlm_defines.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/macros/uvm_printer_defines.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/macros/uvm_object_defines.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/macros/uvm_phase_defines.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/macros/uvm_message_defines.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/macros/uvm_version_defines.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/uvm_macros.svh|/hwetools/work_area/frontend/vineeth_b7/system/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/project_benches/block_3/sim/../tb/sequences/block_3_sequences_pkg.sv| +!s90 -sv|-suppress|2223|-suppress|2286|+define+UVM_REPORT_DISABLE_FILE_LINE|+define+UVM_REPORT_DISABLE_FILE_LINE|+incdir+/hwetools/work_area/frontend/vineeth_b7/system/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/project_benches/block_3/sim/../tb/sequences|/hwetools/work_area/frontend/vineeth_b7/system/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/project_benches/block_3/sim/../tb/sequences/block_3_sequences_pkg.sv| +>>>>>>> ceab28f188594b972dededef57152e3a46196cbf +!i113 0 +R28 +!s92 -suppress 2223 -suppress 2286 -sv +define+UVM_REPORT_DISABLE_FILE_LINE +define+UVM_REPORT_DISABLE_FILE_LINE +incdir+/hwetools/work_area/frontend/vineeth_b7/system/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/project_benches/block_3/sim/../tb/sequences -L mtiAvm -L mtiRnm -L mtiOvm -L mtiUvm -L mtiUPF -L infact +R30 +Xblock_3_tests_pkg +R1 +R4 +R2 +R5 +R48 +R41 +R42 +R3 +R6 +<<<<<<< HEAD +R50 +Z52 DXx4 work 21 block_3_sequences_pkg 0 22 JH8E8Rc83F6MFlI?7>iG:1 +Z53 !s110 1672041115 +!i10b 1 +!s100 ;_aOC0`JVLWOPTzN?PTzN?>>>>>> ceab28f188594b972dededef57152e3a46196cbf +R11 +R12 +R13 +R14 +R15 +R16 +R17 +R18 +R19 +R20 +R21 +R22 +F/hwetools/work_area/frontend/vineeth_b7/system/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/project_benches/block_3/sim/../tb/tests/src/test_top.svh +F/hwetools/work_area/frontend/vineeth_b7/system/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/project_benches/block_3/sim/../tb/tests/src/register_test.svh +F/hwetools/work_area/frontend/vineeth_b7/system/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/project_benches/block_3/sim/../tb/tests/src/example_derived_test.svh +L0 21 +R24 +r1 +!s85 0 +31 +<<<<<<< HEAD +R51 +!s107 /hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/project_benches/block_3/sim/../tb/tests/src/example_derived_test.svh|/hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/project_benches/block_3/sim/../tb/tests/src/register_test.svh|/hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/project_benches/block_3/sim/../tb/tests/src/test_top.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/macros/uvm_deprecated_defines.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/macros/uvm_reg_defines.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/macros/uvm_callback_defines.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/macros/uvm_sequence_defines.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/tlm1/uvm_tlm_imps.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/macros/uvm_tlm_defines.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/macros/uvm_printer_defines.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/macros/uvm_object_defines.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/macros/uvm_phase_defines.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/macros/uvm_message_defines.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/macros/uvm_version_defines.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/uvm_macros.svh|/hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/project_benches/block_3/sim/../tb/tests/block_3_tests_pkg.sv| +!s90 -sv|-suppress|2223|-suppress|2286|+define+UVM_REPORT_DISABLE_FILE_LINE|+define+UVM_REPORT_DISABLE_FILE_LINE|+incdir+/hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/project_benches/block_3/sim/../tb/tests|/hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/project_benches/block_3/sim/../tb/tests/block_3_tests_pkg.sv| +======= +R47 +!s107 /hwetools/work_area/frontend/vineeth_b7/system/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/project_benches/block_3/sim/../tb/tests/src/example_derived_test.svh|/hwetools/work_area/frontend/vineeth_b7/system/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/project_benches/block_3/sim/../tb/tests/src/register_test.svh|/hwetools/work_area/frontend/vineeth_b7/system/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/project_benches/block_3/sim/../tb/tests/src/test_top.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/macros/uvm_deprecated_defines.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/macros/uvm_reg_defines.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/macros/uvm_callback_defines.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/macros/uvm_sequence_defines.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/tlm1/uvm_tlm_imps.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/macros/uvm_tlm_defines.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/macros/uvm_printer_defines.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/macros/uvm_object_defines.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/macros/uvm_phase_defines.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/macros/uvm_message_defines.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/macros/uvm_version_defines.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/uvm_macros.svh|/hwetools/work_area/frontend/vineeth_b7/system/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/project_benches/block_3/sim/../tb/tests/block_3_tests_pkg.sv| +!s90 -sv|-suppress|2223|-suppress|2286|+define+UVM_REPORT_DISABLE_FILE_LINE|+define+UVM_REPORT_DISABLE_FILE_LINE|+incdir+/hwetools/work_area/frontend/vineeth_b7/system/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/project_benches/block_3/sim/../tb/tests|/hwetools/work_area/frontend/vineeth_b7/system/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/project_benches/block_3/sim/../tb/tests/block_3_tests_pkg.sv| +>>>>>>> ceab28f188594b972dededef57152e3a46196cbf +!i113 0 +R28 +!s92 -suppress 2223 -suppress 2286 -sv +define+UVM_REPORT_DISABLE_FILE_LINE +define+UVM_REPORT_DISABLE_FILE_LINE +incdir+/hwetools/work_area/frontend/vineeth_b7/system/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/project_benches/block_3/sim/../tb/tests -L mtiAvm -L mtiRnm -L mtiOvm -L mtiUvm -L mtiUPF -L infact +R30 +vhdl_top +R1 +R2 +R48 +R4 +<<<<<<< HEAD +!s110 1672041116 +======= +Z51 !s110 1672030794 +>>>>>>> ceab28f188594b972dededef57152e3a46196cbf +!i10b 1 +!s100 4b=7eCU_oC`9AHMn5>>>>>> ceab28f188594b972dededef57152e3a46196cbf +L0 24 +R24 +r1 +!s85 0 +31 +<<<<<<< HEAD +Z54 !s108 1672041115.000000 +!s107 /hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/project_benches/block_3/sim/../tb/testbench/hdl_top.sv| +!s90 -sv|-suppress|2223|-suppress|2286|+define+UVM_REPORT_DISABLE_FILE_LINE|+define+UVM_REPORT_DISABLE_FILE_LINE|+incdir+/hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/project_benches/block_3/sim/../tb/testbench|-F|/hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/project_benches/block_3/sim/../tb/testbench/top_filelist_hdl.f| +======= +!s108 1672030794.000000 +!s107 /hwetools/work_area/frontend/vineeth_b7/system/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/project_benches/block_3/sim/../tb/testbench/hdl_top.sv| +!s90 -sv|-suppress|2223|-suppress|2286|+define+UVM_REPORT_DISABLE_FILE_LINE|+define+UVM_REPORT_DISABLE_FILE_LINE|+incdir+/hwetools/work_area/frontend/vineeth_b7/system/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/project_benches/block_3/sim/../tb/testbench|-F|/hwetools/work_area/frontend/vineeth_b7/system/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/project_benches/block_3/sim/../tb/testbench/top_filelist_hdl.f| +>>>>>>> ceab28f188594b972dededef57152e3a46196cbf +!i113 0 +R28 +!s92 -suppress 2223 -suppress 2286 -sv +define+UVM_REPORT_DISABLE_FILE_LINE +define+UVM_REPORT_DISABLE_FILE_LINE +incdir+/hwetools/work_area/frontend/vineeth_b7/system/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/project_benches/block_3/sim/../tb/testbench -L mtiAvm -L mtiRnm -L mtiOvm -L mtiUvm -L mtiUPF -L infact +R30 +vhvl_top +R1 +R4 +R2 +R5 +R48 +R41 +R42 +R3 +R6 +R49 +R50 +<<<<<<< HEAD +R52 +DXx4 work 17 block_3_tests_pkg 0 22 g;C@HC2GHkf<6EM6dzi:J3 +R53 +!i10b 1 +!s100 BHmbimaJ3CUP3j]YgRKjf2 +Im;JNhHPTzN?>>>>>> ceab28f188594b972dededef57152e3a46196cbf +R7 +!s105 hvl_top_sv_unit +S1 +R0 +<<<<<<< HEAD +R44 +8/hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/project_benches/block_3/sim/../tb/testbench/hvl_top.sv +F/hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/project_benches/block_3/sim/../tb/testbench/hvl_top.sv +R48 +======= +R45 +8/hwetools/work_area/frontend/vineeth_b7/system/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/project_benches/block_3/sim/../tb/testbench/hvl_top.sv +F/hwetools/work_area/frontend/vineeth_b7/system/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/project_benches/block_3/sim/../tb/testbench/hvl_top.sv +R46 +>>>>>>> ceab28f188594b972dededef57152e3a46196cbf +R24 +r1 +!s85 0 +31 +!s108 1672030793.000000 +!s107 /hwetools/work_area/frontend/vineeth_b7/system/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/project_benches/block_3/sim/../tb/testbench/hvl_top.sv| +!s90 -sv|-suppress|2223|-suppress|2286|+define+UVM_REPORT_DISABLE_FILE_LINE|+define+UVM_REPORT_DISABLE_FILE_LINE|+incdir+/questa_mvc_src/sv|+incdir+/hwetools/work_area/frontend/vineeth_b7/system/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/project_benches/block_3/sim/../tb/testbench|-F|/hwetools/work_area/frontend/vineeth_b7/system/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/project_benches/block_3/sim/../tb/testbench/top_filelist_hvl.f| +!i113 0 +R28 +!s92 -suppress 2223 -suppress 2286 -sv +define+UVM_REPORT_DISABLE_FILE_LINE +define+UVM_REPORT_DISABLE_FILE_LINE +incdir+/questa_mvc_src/sv +incdir+/hwetools/work_area/frontend/vineeth_b7/system/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/project_benches/block_3/sim/../tb/testbench -L mtiAvm -L mtiRnm -L mtiOvm -L mtiUvm -L mtiUPF -L infact +R30 +Toptimized_batch_top_tb +<<<<<<< HEAD +!s110 1672041117 +VLYz3HU6^8UY=7N0in]?J@3 +Z55 04 7 4 work hvl_top fast 0 +Z56 04 7 4 work hdl_top fast 0 +======= +!s110 1672030795 +VD:_jG?Pf1E0031QYALzR50 +Z52 04 7 4 work hvl_top fast 0 +Z53 04 7 4 work hdl_top fast 0 +>>>>>>> ceab28f188594b972dededef57152e3a46196cbf +o +R30 +noptimized_batch_top_tb +Z54 OE;O;10.6c;65 +R0 +Toptimized_debug_top_tb +<<<<<<< HEAD +!s110 1672041119 +Vhb9]3A]iXb]BS;@YUnckA0 +R55 +R56 +======= +!s110 1672030798 +V@DefDY03;VD1;kMLAQe:H0 +R52 +R53 +>>>>>>> ceab28f188594b972dededef57152e3a46196cbf +o+acc +R30 +noptimized_debug_top_tb +R54 +Xuvmf_base_pkg +R1 +R4 +R2 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+!s90 -sv|-suppress|2223|-suppress|2286|+define+UVM_REPORT_DISABLE_FILE_LINE|+define+UVM_REPORT_DISABLE_FILE_LINE|+incdir+/hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3//uvmf_base_pkg|-F|/hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3//uvmf_base_pkg/uvmf_base_pkg_filelist_hvl.f| +======= +Z57 !s108 1672030786.000000 +!s107 /hwetools/work_area/frontend/vineeth_b7/system/UVMF/UVM_Framework/UVMF_2022.3//uvmf_base_pkg/src/uvmf_test_base.svh|/hwetools/work_area/frontend/vineeth_b7/system/UVMF/UVM_Framework/UVMF_2022.3//uvmf_base_pkg/src/uvmf_parameterized_3agent_environment.svh|/hwetools/work_area/frontend/vineeth_b7/system/UVMF/UVM_Framework/UVMF_2022.3//uvmf_base_pkg/src/uvmf_parameterized_2agent_environment.svh|/hwetools/work_area/frontend/vineeth_b7/system/UVMF/UVM_Framework/UVMF_2022.3//uvmf_base_pkg/src/uvmf_parameterized_1agent_environment.svh|/hwetools/work_area/frontend/vineeth_b7/system/UVMF/UVM_Framework/UVMF_2022.3//uvmf_base_pkg/src/uvmf_parameterized_simplex_environment.svh|/hwetools/work_area/frontend/vineeth_b7/system/UVMF/UVM_Framework/UVMF_2022.3//uvmf_base_pkg/src/uvmf_environment_base.svh|/hwetools/work_area/frontend/vineeth_b7/system/UVMF/UVM_Framework/UVMF_2022.3//uvmf_base_pkg/src/uvmf_environment_configuration_base.svh|/hwetools/work_area/frontend/vineeth_b7/system/UVMF/UVM_Framework/UVMF_2022.3//uvmf_base_pkg/src/uvmf_virtual_sequence_base.svh|/hwetools/work_area/frontend/vineeth_b7/system/UVMF/UVM_Framework/UVMF_2022.3//uvmf_base_pkg/src/uvmf_virtual_sequencer_base.svh|/hwetools/work_area/frontend/vineeth_b7/system/UVMF/UVM_Framework/UVMF_2022.3//uvmf_base_pkg/src/uvmf_parameterized_agent.svh|/hwetools/work_area/frontend/vineeth_b7/system/UVMF/UVM_Framework/UVMF_2022.3//uvmf_base_pkg/src/uvmf_monitor_base.svh|/hwetools/work_area/frontend/vineeth_b7/system/UVMF/UVM_Framework/UVMF_2022.3//uvmf_base_pkg/src/uvmf_driver_base.svh|/hwetools/work_area/frontend/vineeth_b7/system/UVMF/UVM_Framework/UVMF_2022.3//uvmf_base_pkg/src/uvmf_parameterized_agent_configuration_base.svh|/hwetools/work_area/frontend/vineeth_b7/system/UVMF/UVM_Framework/UVMF_2022.3//uvmf_base_pkg/src/uvmf_sorting_predictor_base.svh|/hwetools/work_area/frontend/vineeth_b7/system/UVMF/UVM_Framework/UVMF_2022.3//uvmf_base_pkg/src/uvmf_predictor_base.svh|/hwetools/work_area/frontend/vineeth_b7/system/UVMF/UVM_Framework/UVMF_2022.3//uvmf_base_pkg/src/uvmf_catapult_scoreboard.svh|/hwetools/work_area/frontend/vineeth_b7/system/UVMF/UVM_Framework/UVMF_2022.3//uvmf_base_pkg/src/uvmf_in_order_scoreboard_array.svh|/hwetools/work_area/frontend/vineeth_b7/system/UVMF/UVM_Framework/UVMF_2022.3//uvmf_base_pkg/src/uvmf_out_of_order_race_scoreboard.svh|/hwetools/work_area/frontend/vineeth_b7/system/UVMF/UVM_Framework/UVMF_2022.3//uvmf_base_pkg/src/uvmf_out_of_order_scoreboard.svh|/hwetools/work_area/frontend/vineeth_b7/system/UVMF/UVM_Framework/UVMF_2022.3//uvmf_base_pkg/src/uvmf_in_order_race_scoreboard_array.svh|/hwetools/work_area/frontend/vineeth_b7/system/UVMF/UVM_Framework/UVMF_2022.3//uvmf_base_pkg/src/uvmf_in_order_race_scoreboard.svh|/hwetools/work_area/frontend/vineeth_b7/system/UVMF/UVM_Framework/UVMF_2022.3//uvmf_base_pkg/src/uvmf_in_order_scoreboard.svh|/hwetools/work_area/frontend/vineeth_b7/system/UVMF/UVM_Framework/UVMF_2022.3//uvmf_base_pkg/src/uvmf_scoreboard_base.svh|/hwetools/work_area/frontend/vineeth_b7/system/UVMF/UVM_Framework/UVMF_2022.3//uvmf_base_pkg/src/uvmf_sequence_base.svh|/hwetools/work_area/frontend/vineeth_b7/system/UVMF/UVM_Framework/UVMF_2022.3//uvmf_base_pkg/src/uvmf_transaction_base.svh|/hwetools/work_area/frontend/vineeth_b7/system/UVMF/UVM_Framework/UVMF_2022.3//uvmf_base_pkg/src/uvmf_base_typedefs.svh|/hwetools/work_area/frontend/vineeth_b7/system/UVMF/UVM_Framework/UVMF_2022.3//uvmf_base_pkg/src/uvmf_version.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/macros/uvm_deprecated_defines.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/macros/uvm_reg_defines.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/macros/uvm_callback_defines.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/macros/uvm_sequence_defines.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/tlm1/uvm_tlm_imps.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/macros/uvm_tlm_defines.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/macros/uvm_printer_defines.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/macros/uvm_object_defines.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/macros/uvm_phase_defines.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/macros/uvm_message_defines.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/macros/uvm_version_defines.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/uvm_macros.svh|/hwetools/work_area/frontend/vineeth_b7/system/UVMF/UVM_Framework/UVMF_2022.3//uvmf_base_pkg/uvmf_base_pkg.sv| +!s90 -sv|-suppress|2223|-suppress|2286|+define+UVM_REPORT_DISABLE_FILE_LINE|+define+UVM_REPORT_DISABLE_FILE_LINE|+incdir+/hwetools/work_area/frontend/vineeth_b7/system/UVMF/UVM_Framework/UVMF_2022.3//uvmf_base_pkg|-F|/hwetools/work_area/frontend/vineeth_b7/system/UVMF/UVM_Framework/UVMF_2022.3//uvmf_base_pkg/uvmf_base_pkg_filelist_hvl.f| +>>>>>>> ceab28f188594b972dededef57152e3a46196cbf +!i113 0 +R28 +Z58 !s92 -suppress 2223 -suppress 2286 -sv +define+UVM_REPORT_DISABLE_FILE_LINE +define+UVM_REPORT_DISABLE_FILE_LINE +incdir+/hwetools/work_area/frontend/vineeth_b7/system/UVMF/UVM_Framework/UVMF_2022.3//uvmf_base_pkg -L mtiAvm -L mtiRnm -L mtiOvm -L mtiUvm -L mtiUPF -L infact +R30 +Xuvmf_base_pkg_hdl +R1 +<<<<<<< HEAD +Z62 !s110 1672041108 +======= +Z59 !s110 1672030786 +>>>>>>> ceab28f188594b972dededef57152e3a46196cbf +!i10b 1 +!s100 N^6_:OJbG>>>>>> ceab28f188594b972dededef57152e3a46196cbf +!i10b 1 +!s100 ^UD9ZTL3>>>>>> ceab28f188594b972dededef57152e3a46196cbf +L0 1 +R24 +r1 +!s85 0 +31 +R57 +!s107 /hwetools/work_area/frontend/vineeth_b7/system/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/project_benches/block_3/sim/../rtl/verilog/verilog_dut.v| +!s90 -sv|-suppress|2223|-suppress|2286|+define+UVM_REPORT_DISABLE_FILE_LINE|+define+UVM_REPORT_DISABLE_FILE_LINE|/hwetools/work_area/frontend/vineeth_b7/system/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/project_benches/block_3/sim/../rtl/verilog/verilog_dut.v| +!i113 0 +R28 +!s92 -suppress 2223 -suppress 2286 -sv +define+UVM_REPORT_DISABLE_FILE_LINE +define+UVM_REPORT_DISABLE_FILE_LINE -L mtiAvm -L mtiRnm -L mtiOvm -L mtiUvm -L mtiUPF -L infact +R30 +Evhdl_dut +<<<<<<< HEAD +R44 +Z63 DPx3 std 6 textio 0 22 zE1`LPoLg^DX3Oz^4Fj1K3 +Z64 DPx4 ieee 14 std_logic_1164 0 22 eNV`TJ_GofJTzYa?f<@Oe1 +R0 +Z65 8/hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/project_benches/block_3/sim/../rtl/vhdl/vhdl_dut.vhd +Z66 F/hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/project_benches/block_3/sim/../rtl/vhdl/vhdl_dut.vhd +======= +R45 +Z60 DPx3 std 6 textio 0 22 zE1`LPoLg^DX3Oz^4Fj1K3 +Z61 DPx4 ieee 14 std_logic_1164 0 22 eNV`TJ_GofJTzYa?f<@Oe1 +R0 +Z62 8/hwetools/work_area/frontend/vineeth_b7/system/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/project_benches/block_3/sim/../rtl/vhdl/vhdl_dut.vhd +Z63 F/hwetools/work_area/frontend/vineeth_b7/system/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/project_benches/block_3/sim/../rtl/vhdl/vhdl_dut.vhd +>>>>>>> ceab28f188594b972dededef57152e3a46196cbf +l0 +L4 +V4_]Q6fT]^UP;BkHShHi9j2 +!s100 YHiX09^FS?9c7;MH[92@@2 +<<<<<<< HEAD +Z67 OE;C;10.6c;65 +32 +R62 +!i10b 1 +R60 +Z68 !s90 /hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/project_benches/block_3/sim/../rtl/vhdl/vhdl_dut.vhd| +Z69 !s107 /hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/project_benches/block_3/sim/../rtl/vhdl/vhdl_dut.vhd| +!i113 0 +Z70 tExplicit 1 CvgOpt 0 +Artl +R63 +R64 +======= +Z64 OE;C;10.6c;65 +32 +R59 +!i10b 1 +R57 +Z65 !s90 /hwetools/work_area/frontend/vineeth_b7/system/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/project_benches/block_3/sim/../rtl/vhdl/vhdl_dut.vhd| +Z66 !s107 /hwetools/work_area/frontend/vineeth_b7/system/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/project_benches/block_3/sim/../rtl/vhdl/vhdl_dut.vhd| +!i113 0 +Z67 tExplicit 1 CvgOpt 0 +Artl +R60 +R61 +>>>>>>> ceab28f188594b972dededef57152e3a46196cbf +DEx4 work 8 vhdl_dut 0 22 4_]Q6fT]^UP;BkHShHi9j2 +l13 +L12 +VD8Z[WTM3SDlI>>>>>> ceab28f188594b972dededef57152e3a46196cbf +Ywb_m_driver_bfm +R1 +R2 +R41 +DXx4 work 23 wb_m_driver_bfm_sv_unit 0 22 `R[0zVCk73RlG7j>>>>>> ceab28f188594b972dededef57152e3a46196cbf +R11 +R12 +R13 +R14 +R15 +R16 +R17 +R18 +R19 +R20 +R21 +R22 +R23 +R24 +<<<<<<< HEAD +Z74 !s108 1672041109.000000 +Z75 !s107 /tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/macros/uvm_deprecated_defines.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/macros/uvm_reg_defines.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/macros/uvm_callback_defines.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/macros/uvm_sequence_defines.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/tlm1/uvm_tlm_imps.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/macros/uvm_tlm_defines.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/macros/uvm_printer_defines.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/macros/uvm_object_defines.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/macros/uvm_phase_defines.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/macros/uvm_message_defines.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/macros/uvm_version_defines.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/uvm_macros.svh|/hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/project_benches/block_3/sim/../../../verification_ip/interface_packages/wb_m_pkg/src/wb_m_macros.svh|/hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/project_benches/block_3/sim/../../../verification_ip/interface_packages/wb_m_pkg/src/wb_m_driver_bfm.sv|/hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/project_benches/block_3/sim/../../../verification_ip/interface_packages/wb_m_pkg/src/wb_m_monitor_bfm.sv|/hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/project_benches/block_3/sim/../../../verification_ip/interface_packages/wb_m_pkg/src/wb_m_if.sv| +Z76 !s90 -sv|-suppress|2223|-suppress|2286|+define+UVM_REPORT_DISABLE_FILE_LINE|+define+UVM_REPORT_DISABLE_FILE_LINE|+incdir+/hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/project_benches/block_3/sim/../../../verification_ip/interface_packages/wb_m_pkg|-F|/hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/project_benches/block_3/sim/../../../verification_ip/interface_packages/wb_m_pkg/wb_m_filelist_xrtl.f| +!i113 0 +R28 +Z77 !s92 -suppress 2223 -suppress 2286 -sv +define+UVM_REPORT_DISABLE_FILE_LINE +define+UVM_REPORT_DISABLE_FILE_LINE +incdir+/hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/project_benches/block_3/sim/../../../verification_ip/interface_packages/wb_m_pkg -L mtiAvm -L mtiRnm -L mtiOvm -L mtiUvm -L mtiUPF -L infact +======= +Z70 !s108 1672030788.000000 +Z71 !s107 /tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/macros/uvm_deprecated_defines.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/macros/uvm_reg_defines.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/macros/uvm_callback_defines.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/macros/uvm_sequence_defines.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/tlm1/uvm_tlm_imps.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/macros/uvm_tlm_defines.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/macros/uvm_printer_defines.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/macros/uvm_object_defines.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/macros/uvm_phase_defines.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/macros/uvm_message_defines.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/macros/uvm_version_defines.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/uvm_macros.svh|/hwetools/work_area/frontend/vineeth_b7/system/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/project_benches/block_3/sim/../../../verification_ip/interface_packages/wb_m_pkg/src/wb_m_macros.svh|/hwetools/work_area/frontend/vineeth_b7/system/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/project_benches/block_3/sim/../../../verification_ip/interface_packages/wb_m_pkg/src/wb_m_driver_bfm.sv|/hwetools/work_area/frontend/vineeth_b7/system/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/project_benches/block_3/sim/../../../verification_ip/interface_packages/wb_m_pkg/src/wb_m_monitor_bfm.sv|/hwetools/work_area/frontend/vineeth_b7/system/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/project_benches/block_3/sim/../../../verification_ip/interface_packages/wb_m_pkg/src/wb_m_if.sv| +Z72 !s90 -sv|-suppress|2223|-suppress|2286|+define+UVM_REPORT_DISABLE_FILE_LINE|+define+UVM_REPORT_DISABLE_FILE_LINE|+incdir+/hwetools/work_area/frontend/vineeth_b7/system/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/project_benches/block_3/sim/../../../verification_ip/interface_packages/wb_m_pkg|-F|/hwetools/work_area/frontend/vineeth_b7/system/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/project_benches/block_3/sim/../../../verification_ip/interface_packages/wb_m_pkg/wb_m_filelist_xrtl.f| +!i113 0 +R28 +Z73 !s92 -suppress 2223 -suppress 2286 -sv +define+UVM_REPORT_DISABLE_FILE_LINE +define+UVM_REPORT_DISABLE_FILE_LINE +incdir+/hwetools/work_area/frontend/vineeth_b7/system/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/project_benches/block_3/sim/../../../verification_ip/interface_packages/wb_m_pkg -L mtiAvm -L mtiRnm -L mtiOvm -L mtiUvm -L mtiUPF -L infact +>>>>>>> ceab28f188594b972dededef57152e3a46196cbf +R30 +Xwb_m_driver_bfm_sv_unit +R1 +R2 +R41 +V`R[0zVCk73RlG7j>>>>>> ceab28f188594b972dededef57152e3a46196cbf +R30 +Ywb_m_if +R1 +R2 +R41 +DXx4 work 15 wb_m_if_sv_unit 0 22 DoQgz_ij;aDNDLnFUHE1i3 +R7 +r1 +!s85 0 +31 +!i10b 1 +!s100 :gZ:@4XWQLO?aBgX9=F_o0 +ICfaOjXaJ1il_VmH3J>Y?Q3 +!s105 wb_m_if_sv_unit +S1 +R0 +<<<<<<< HEAD +R40 +Z79 8/hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/project_benches/block_3/sim/../../../verification_ip/interface_packages/wb_m_pkg/src/wb_m_if.sv +Z80 F/hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/project_benches/block_3/sim/../../../verification_ip/interface_packages/wb_m_pkg/src/wb_m_if.sv +L0 37 +R24 +R74 +R75 +R76 +!i113 0 +R28 +R77 +======= +R45 +Z75 8/hwetools/work_area/frontend/vineeth_b7/system/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/project_benches/block_3/sim/../../../verification_ip/interface_packages/wb_m_pkg/src/wb_m_if.sv +Z76 F/hwetools/work_area/frontend/vineeth_b7/system/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/project_benches/block_3/sim/../../../verification_ip/interface_packages/wb_m_pkg/src/wb_m_if.sv +L0 37 +R24 +R70 +R71 +R72 +!i113 0 +R28 +R73 +>>>>>>> ceab28f188594b972dededef57152e3a46196cbf +R30 +Xwb_m_if_sv_unit +R1 +R2 +R41 +VDoQgz_ij;aDNDLnFUHE1i3 +r1 +!s85 0 +31 +!i10b 1 +!s100 0^ECJz[?]<_Dh0;3coeYE1 +IDoQgz_ij;aDNDLnFUHE1i3 +!i103 1 +S1 +R0 +<<<<<<< HEAD +R40 +R79 +R80 +L0 34 +R24 +R74 +R75 +R76 +!i113 0 +R28 +R77 +======= +R45 +R75 +R76 +L0 34 +R24 +R70 +R71 +R72 +!i113 0 +R28 +R73 +>>>>>>> ceab28f188594b972dededef57152e3a46196cbf +R30 +Ywb_m_monitor_bfm +R1 +R2 +R41 +DXx4 work 24 wb_m_monitor_bfm_sv_unit 0 22 mP45`b^4e81=K;[nmS3OE3 +R4 +R5 +R42 +R7 +r1 +!s85 0 +31 +!i10b 1 +!s100 =81^AG;jGEIMGY]e7]Of=2 +IzU5e]>ALb8]AJ^FmS4PB<2 +!s105 wb_m_monitor_bfm_sv_unit +S1 +R0 +<<<<<<< HEAD +R40 +Z81 8/hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/project_benches/block_3/sim/../../../verification_ip/interface_packages/wb_m_pkg/src/wb_m_monitor_bfm.sv +Z82 F/hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/project_benches/block_3/sim/../../../verification_ip/interface_packages/wb_m_pkg/src/wb_m_monitor_bfm.sv +======= +R45 +Z77 8/hwetools/work_area/frontend/vineeth_b7/system/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/project_benches/block_3/sim/../../../verification_ip/interface_packages/wb_m_pkg/src/wb_m_monitor_bfm.sv +Z78 F/hwetools/work_area/frontend/vineeth_b7/system/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/project_benches/block_3/sim/../../../verification_ip/interface_packages/wb_m_pkg/src/wb_m_monitor_bfm.sv +>>>>>>> ceab28f188594b972dededef57152e3a46196cbf +R11 +R12 +R13 +R14 +R15 +R16 +R17 +R18 +R19 +R20 +R21 +R22 +R37 +R24 +<<<<<<< HEAD +R74 +R75 +R76 +!i113 0 +R28 +R77 +======= +R70 +R71 +R72 +!i113 0 +R28 +R73 +>>>>>>> ceab28f188594b972dededef57152e3a46196cbf +R30 +Xwb_m_monitor_bfm_sv_unit +R1 +R2 +R41 +VmP45`b^4e81=K;[nmS3OE3 +r1 +!s85 0 +31 +!i10b 1 +!s100 DD@c7:cgePQ=0YP6M0ggm1 +ImP45`b^4e81=K;[nmS3OE3 +!i103 1 +S1 +R0 +<<<<<<< HEAD +R40 +R81 +R82 +R78 +R38 +R24 +R74 +R75 +R76 +!i113 0 +R28 +R77 +======= +R45 +R77 +R78 +R74 +R38 +R24 +R70 +R71 +R72 +!i113 0 +R28 +R73 +>>>>>>> ceab28f188594b972dededef57152e3a46196cbf +R30 +Xwb_m_pkg +!s115 wb_m_monitor_bfm +!s115 wb_m_driver_bfm +R1 +R4 +R2 +R5 +<<<<<<< HEAD +R42 +R58 +======= +R41 +!s110 1672030788 +>>>>>>> ceab28f188594b972dededef57152e3a46196cbf +!i10b 1 +!s100 m7eVogi1j6O5]dVDSC27m1 +IM_K3_NOE:l@NI>>>>>> ceab28f188594b972dededef57152e3a46196cbf +R11 +R12 +R13 +R14 +R15 +R16 +R17 +R18 +R19 +R20 +R21 +R22 +<<<<<<< HEAD +R78 +F/hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/project_benches/block_3/sim/../../../verification_ip/interface_packages/wb_m_pkg/src/wb_m_typedefs.svh +F/hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/project_benches/block_3/sim/../../../verification_ip/interface_packages/wb_m_pkg/src/wb_m_transaction.svh +F/hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/project_benches/block_3/sim/../../../verification_ip/interface_packages/wb_m_pkg/src/wb_m_configuration.svh +F/hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/project_benches/block_3/sim/../../../verification_ip/interface_packages/wb_m_pkg/src/wb_m_driver.svh +F/hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/project_benches/block_3/sim/../../../verification_ip/interface_packages/wb_m_pkg/src/wb_m_monitor.svh +F/hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/project_benches/block_3/sim/../../../verification_ip/interface_packages/wb_m_pkg/src/wb_m_transaction_coverage.svh +F/hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/project_benches/block_3/sim/../../../verification_ip/interface_packages/wb_m_pkg/src/wb_m_sequence_base.svh +F/hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/project_benches/block_3/sim/../../../verification_ip/interface_packages/wb_m_pkg/src/wb_m_random_sequence.svh +F/hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/project_benches/block_3/sim/../../../verification_ip/interface_packages/wb_m_pkg/src/wb_m_responder_sequence.svh +F/hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/project_benches/block_3/sim/../../../verification_ip/interface_packages/wb_m_pkg/src/wb_m2reg_adapter.svh +F/hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/project_benches/block_3/sim/../../../verification_ip/interface_packages/wb_m_pkg/src/wb_m_agent.svh +======= +R74 +F/hwetools/work_area/frontend/vineeth_b7/system/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/project_benches/block_3/sim/../../../verification_ip/interface_packages/wb_m_pkg/src/wb_m_typedefs.svh +F/hwetools/work_area/frontend/vineeth_b7/system/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/project_benches/block_3/sim/../../../verification_ip/interface_packages/wb_m_pkg/src/wb_m_transaction.svh +F/hwetools/work_area/frontend/vineeth_b7/system/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/project_benches/block_3/sim/../../../verification_ip/interface_packages/wb_m_pkg/src/wb_m_configuration.svh +F/hwetools/work_area/frontend/vineeth_b7/system/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/project_benches/block_3/sim/../../../verification_ip/interface_packages/wb_m_pkg/src/wb_m_driver.svh +F/hwetools/work_area/frontend/vineeth_b7/system/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/project_benches/block_3/sim/../../../verification_ip/interface_packages/wb_m_pkg/src/wb_m_monitor.svh +F/hwetools/work_area/frontend/vineeth_b7/system/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/project_benches/block_3/sim/../../../verification_ip/interface_packages/wb_m_pkg/src/wb_m_transaction_coverage.svh +F/hwetools/work_area/frontend/vineeth_b7/system/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/project_benches/block_3/sim/../../../verification_ip/interface_packages/wb_m_pkg/src/wb_m_sequence_base.svh +F/hwetools/work_area/frontend/vineeth_b7/system/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/project_benches/block_3/sim/../../../verification_ip/interface_packages/wb_m_pkg/src/wb_m_random_sequence.svh +F/hwetools/work_area/frontend/vineeth_b7/system/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/project_benches/block_3/sim/../../../verification_ip/interface_packages/wb_m_pkg/src/wb_m_responder_sequence.svh +F/hwetools/work_area/frontend/vineeth_b7/system/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/project_benches/block_3/sim/../../../verification_ip/interface_packages/wb_m_pkg/src/wb_m2reg_adapter.svh +F/hwetools/work_area/frontend/vineeth_b7/system/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/project_benches/block_3/sim/../../../verification_ip/interface_packages/wb_m_pkg/src/wb_m_agent.svh +>>>>>>> ceab28f188594b972dededef57152e3a46196cbf +R38 +R24 +r1 +!s85 0 +31 +<<<<<<< HEAD +R74 +!s107 /hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/project_benches/block_3/sim/../../../verification_ip/interface_packages/wb_m_pkg/src/wb_m_agent.svh|/hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/project_benches/block_3/sim/../../../verification_ip/interface_packages/wb_m_pkg/src/wb_m2reg_adapter.svh|/hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/project_benches/block_3/sim/../../../verification_ip/interface_packages/wb_m_pkg/src/wb_m_responder_sequence.svh|/hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/project_benches/block_3/sim/../../../verification_ip/interface_packages/wb_m_pkg/src/wb_m_random_sequence.svh|/hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/project_benches/block_3/sim/../../../verification_ip/interface_packages/wb_m_pkg/src/wb_m_sequence_base.svh|/hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/project_benches/block_3/sim/../../../verification_ip/interface_packages/wb_m_pkg/src/wb_m_transaction_coverage.svh|/hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/project_benches/block_3/sim/../../../verification_ip/interface_packages/wb_m_pkg/src/wb_m_monitor.svh|/hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/project_benches/block_3/sim/../../../verification_ip/interface_packages/wb_m_pkg/src/wb_m_driver.svh|/hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/project_benches/block_3/sim/../../../verification_ip/interface_packages/wb_m_pkg/src/wb_m_configuration.svh|/hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/project_benches/block_3/sim/../../../verification_ip/interface_packages/wb_m_pkg/src/wb_m_transaction.svh|/hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/project_benches/block_3/sim/../../../verification_ip/interface_packages/wb_m_pkg/src/wb_m_typedefs.svh|/hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/project_benches/block_3/sim/../../../verification_ip/interface_packages/wb_m_pkg/src/wb_m_macros.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/macros/uvm_deprecated_defines.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/macros/uvm_reg_defines.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/macros/uvm_callback_defines.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/macros/uvm_sequence_defines.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/tlm1/uvm_tlm_imps.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/macros/uvm_tlm_defines.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/macros/uvm_printer_defines.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/macros/uvm_object_defines.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/macros/uvm_phase_defines.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/macros/uvm_message_defines.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/macros/uvm_version_defines.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/uvm_macros.svh|/hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/project_benches/block_3/sim/../../../verification_ip/interface_packages/wb_m_pkg/wb_m_pkg.sv| +!s90 -sv|-suppress|2223|-suppress|2286|+define+UVM_REPORT_DISABLE_FILE_LINE|+define+UVM_REPORT_DISABLE_FILE_LINE|+incdir+/hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/project_benches/block_3/sim/../../../verification_ip/interface_packages/wb_m_pkg|-F|/hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/project_benches/block_3/sim/../../../verification_ip/interface_packages/wb_m_pkg/wb_m_filelist_hvl.f| +!i113 0 +R28 +R77 +======= +Z79 !s108 1672030787.000000 +!s107 /hwetools/work_area/frontend/vineeth_b7/system/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/project_benches/block_3/sim/../../../verification_ip/interface_packages/wb_m_pkg/src/wb_m_agent.svh|/hwetools/work_area/frontend/vineeth_b7/system/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/project_benches/block_3/sim/../../../verification_ip/interface_packages/wb_m_pkg/src/wb_m2reg_adapter.svh|/hwetools/work_area/frontend/vineeth_b7/system/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/project_benches/block_3/sim/../../../verification_ip/interface_packages/wb_m_pkg/src/wb_m_responder_sequence.svh|/hwetools/work_area/frontend/vineeth_b7/system/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/project_benches/block_3/sim/../../../verification_ip/interface_packages/wb_m_pkg/src/wb_m_random_sequence.svh|/hwetools/work_area/frontend/vineeth_b7/system/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/project_benches/block_3/sim/../../../verification_ip/interface_packages/wb_m_pkg/src/wb_m_sequence_base.svh|/hwetools/work_area/frontend/vineeth_b7/system/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/project_benches/block_3/sim/../../../verification_ip/interface_packages/wb_m_pkg/src/wb_m_transaction_coverage.svh|/hwetools/work_area/frontend/vineeth_b7/system/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/project_benches/block_3/sim/../../../verification_ip/interface_packages/wb_m_pkg/src/wb_m_monitor.svh|/hwetools/work_area/frontend/vineeth_b7/system/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/project_benches/block_3/sim/../../../verification_ip/interface_packages/wb_m_pkg/src/wb_m_driver.svh|/hwetools/work_area/frontend/vineeth_b7/system/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/project_benches/block_3/sim/../../../verification_ip/interface_packages/wb_m_pkg/src/wb_m_configuration.svh|/hwetools/work_area/frontend/vineeth_b7/system/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/project_benches/block_3/sim/../../../verification_ip/interface_packages/wb_m_pkg/src/wb_m_transaction.svh|/hwetools/work_area/frontend/vineeth_b7/system/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/project_benches/block_3/sim/../../../verification_ip/interface_packages/wb_m_pkg/src/wb_m_typedefs.svh|/hwetools/work_area/frontend/vineeth_b7/system/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/project_benches/block_3/sim/../../../verification_ip/interface_packages/wb_m_pkg/src/wb_m_macros.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/macros/uvm_deprecated_defines.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/macros/uvm_reg_defines.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/macros/uvm_callback_defines.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/macros/uvm_sequence_defines.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/tlm1/uvm_tlm_imps.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/macros/uvm_tlm_defines.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/macros/uvm_printer_defines.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/macros/uvm_object_defines.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/macros/uvm_phase_defines.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/macros/uvm_message_defines.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/macros/uvm_version_defines.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/uvm_macros.svh|/hwetools/work_area/frontend/vineeth_b7/system/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/project_benches/block_3/sim/../../../verification_ip/interface_packages/wb_m_pkg/wb_m_pkg.sv| +!s90 -sv|-suppress|2223|-suppress|2286|+define+UVM_REPORT_DISABLE_FILE_LINE|+define+UVM_REPORT_DISABLE_FILE_LINE|+incdir+/hwetools/work_area/frontend/vineeth_b7/system/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/project_benches/block_3/sim/../../../verification_ip/interface_packages/wb_m_pkg|-F|/hwetools/work_area/frontend/vineeth_b7/system/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/project_benches/block_3/sim/../../../verification_ip/interface_packages/wb_m_pkg/wb_m_filelist_hvl.f| +!i113 0 +R28 +R73 +>>>>>>> ceab28f188594b972dededef57152e3a46196cbf +R30 +Xwb_m_pkg_hdl +R1 +R2 +<<<<<<< HEAD +R58 +======= +R55 +>>>>>>> ceab28f188594b972dededef57152e3a46196cbf +!i10b 1 +!s100 ASz066ARKe13gfOnJXm5?0 +IS^_`lHEo0g>>>>>> ceab28f188594b972dededef57152e3a46196cbf +R24 +r1 +!s85 0 +31 +<<<<<<< HEAD +R74 +!s107 /hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/project_benches/block_3/sim/../../../verification_ip/interface_packages/wb_m_pkg/src/wb_m_macros.svh|/hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/project_benches/block_3/sim/../../../verification_ip/interface_packages/wb_m_pkg/src/wb_m_typedefs_hdl.svh|/hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/project_benches/block_3/sim/../../../verification_ip/interface_packages/wb_m_pkg/wb_m_pkg_hdl.sv| +!s90 -sv|-suppress|2223|-suppress|2286|+define+UVM_REPORT_DISABLE_FILE_LINE|+define+UVM_REPORT_DISABLE_FILE_LINE|+incdir+/hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/project_benches/block_3/sim/../../../verification_ip/interface_packages/wb_m_pkg|-F|/hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/project_benches/block_3/sim/../../../verification_ip/interface_packages/wb_m_pkg/wb_m_filelist_hdl.f| +!i113 0 +R28 +R77 +======= +R79 +!s107 /hwetools/work_area/frontend/vineeth_b7/system/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/project_benches/block_3/sim/../../../verification_ip/interface_packages/wb_m_pkg/src/wb_m_macros.svh|/hwetools/work_area/frontend/vineeth_b7/system/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/project_benches/block_3/sim/../../../verification_ip/interface_packages/wb_m_pkg/src/wb_m_typedefs_hdl.svh|/hwetools/work_area/frontend/vineeth_b7/system/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/project_benches/block_3/sim/../../../verification_ip/interface_packages/wb_m_pkg/wb_m_pkg_hdl.sv| +!s90 -sv|-suppress|2223|-suppress|2286|+define+UVM_REPORT_DISABLE_FILE_LINE|+define+UVM_REPORT_DISABLE_FILE_LINE|+incdir+/hwetools/work_area/frontend/vineeth_b7/system/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/project_benches/block_3/sim/../../../verification_ip/interface_packages/wb_m_pkg|-F|/hwetools/work_area/frontend/vineeth_b7/system/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/project_benches/block_3/sim/../../../verification_ip/interface_packages/wb_m_pkg/wb_m_filelist_hdl.f| +!i113 0 +R28 +R73 +>>>>>>> ceab28f188594b972dededef57152e3a46196cbf +R30 diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/project_benches/block_3/sim/work/_lib.qdb b/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/project_benches/block_3/sim/work/_lib.qdb new file mode 100644 index 00000000..e4995a14 Binary files /dev/null and b/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/project_benches/block_3/sim/work/_lib.qdb differ diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/project_benches/block_3/sim/work/_lib1_0.qdb b/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/project_benches/block_3/sim/work/_lib1_0.qdb new file mode 100644 index 00000000..9dd74216 Binary files /dev/null and b/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/project_benches/block_3/sim/work/_lib1_0.qdb differ diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/project_benches/block_3/sim/work/_lib1_0.qpg b/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/project_benches/block_3/sim/work/_lib1_0.qpg new file mode 100644 index 00000000..49d9a3f0 Binary files /dev/null and b/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/project_benches/block_3/sim/work/_lib1_0.qpg differ diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/project_benches/block_3/sim/work/_lib1_0.qtl b/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/project_benches/block_3/sim/work/_lib1_0.qtl new file mode 100644 index 00000000..5f0668e1 Binary files /dev/null and b/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/project_benches/block_3/sim/work/_lib1_0.qtl differ diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/project_benches/block_3/sim/work/_vmake b/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/project_benches/block_3/sim/work/_vmake new file mode 100644 index 00000000..37aa36a8 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/project_benches/block_3/sim/work/_vmake @@ -0,0 +1,4 @@ +m255 +K4 +z0 +cModel Technology diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/project_benches/block_3/sim/work/optimized_batch_top_tb/_dpi/dpi.tfdb b/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/project_benches/block_3/sim/work/optimized_batch_top_tb/_dpi/dpi.tfdb new file mode 100644 index 00000000..c9e30288 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/project_benches/block_3/sim/work/optimized_batch_top_tb/_dpi/dpi.tfdb @@ -0,0 +1,1489 @@ +VERSION 10 1 1 +SYM_BEGIN 270 +159 13 +uvm_reg_bd_cb +252 15 +uvm_dpi_regexec +<<<<<<< HEAD +51 23 +uvm_pkg::uvm_config_int +105 34 +uvm_pkg::uvm_tlm_response_status_e +134 12 +uvm_access_e +56 19 +uvm_objection_cbs_t +38 13 +uvm_report_cb +85 23 +uvm_pkg::uvm_config_seq +138 13 +uvm_predict_e +69 23 +uvm_pkg:: +12 4 +size +127 19 +uvm_pkg::uvm_path_e +100 32 +uvm_default_sequencer_param_type +232 29 +uvm_pkg::uvm_printer_row_info +230 27 +uvm_pkg::uvm_config_wrapper +266 15 +uvm_hdl_release +53 26 +uvm_pkg::uvm_config_string +137 19 +======= +47 23 +uvm_pkg::uvm_config_int +27 34 +uvm_pkg::uvm_tlm_response_status_e +169 12 +uvm_access_e +52 19 +uvm_objection_cbs_t +34 13 +uvm_report_cb +7 23 +uvm_pkg::uvm_config_seq +173 13 +uvm_predict_e +9 30 +uvm_pkg::uvm_virtual_sequencer +107 4 +size +120 14 +begin_elements +22 32 +uvm_default_sequencer_param_type +204 21 +uvm_reg_field_cb_iter +101 27 +uvm_pkg::uvm_config_wrapper +266 15 +uvm_hdl_release +49 26 +uvm_pkg::uvm_config_string +172 19 +>>>>>>> ceab28f188594b972dededef57152e3a46196cbf +uvm_pkg::uvm_hier_e +264 13 +uvm_hdl_force +186 53 +uvm_pkg:: +<<<<<<< HEAD +66 23 +uvm_active_passive_enum +219 16 +uvm_barrier_pool +87 30 +uvm_pkg::uvm_virtual_sequencer +44 17 +uvm_id_file_array +91 56 +======= +58 23 +uvm_active_passive_enum +90 16 +uvm_barrier_pool +61 23 +uvm_pkg:: +40 17 +uvm_id_file_array +13 56 +>>>>>>> ceab28f188594b972dededef57152e3a46196cbf +uvm_pkg:: +240 53 + +166 24 +uvm_pkg::uvm_mem_cb_iter +<<<<<<< HEAD +34 11 +value_width +253 4 +preg +115 26 +uvm_pkg::uvm_reg_byte_en_t +77 22 +uvm_pkg::uvm_verbosity +130 16 +uvm_endianness_e +154 50 +uvm_pkg:: +54 17 +uvm_config_object +233 5 +level +======= +139 11 +value_width +253 4 +preg +150 26 +uvm_pkg::uvm_reg_byte_en_t +69 22 +uvm_pkg::uvm_verbosity +102 20 +uvm_printer_row_info +189 50 +uvm_pkg:: +50 17 +uvm_config_object +162 19 +uvm_pkg::uvm_path_e +>>>>>>> ceab28f188594b972dededef57152e3a46196cbf +245 57 +uvm_pkg:: +236 48 + +167 16 +uvm_reg_field_cb +<<<<<<< HEAD +86 21 +uvm_virtual_sequencer +102 17 +uvm_tlm_command_e +151 7 +byte_en +140 22 +uvm_reg_map_addr_range +231 20 +uvm_printer_row_info +92 43 +======= +8 21 +uvm_virtual_sequencer +24 17 +uvm_tlm_command_e +186 7 +byte_en +175 22 +uvm_reg_map_addr_range +165 16 +uvm_endianness_e +14 43 +>>>>>>> ceab28f188594b972dededef57152e3a46196cbf + +190 49 +uvm_pkg:: +256 17 +uvm_dump_re_cache +<<<<<<< HEAD +228 45 +======= +99 45 +>>>>>>> ceab28f188594b972dededef57152e3a46196cbf +uvm_pkg:: +162 27 +uvm_pkg::uvm_reg_bd_cb_iter +237 57 +uvm_pkg:: +<<<<<<< HEAD +10 10 +identifier +244 48 + +47 33 +uvm_pkg::uvm_id_verbosities_array +113 29 +uvm_pkg::uvm_reg_addr_logic_t +171 17 +======= +117 10 +identifier +244 48 + +43 33 +uvm_pkg::uvm_id_verbosities_array +88 13 +uvm_apprepend +206 17 +>>>>>>> ceab28f188594b972dededef57152e3a46196cbf +uvm_vreg_field_cb +185 44 + +255 15 +uvm_dpi_regfree +177 11 +uvm_vreg_cb +247 46 +verilog_src/uvm-1.1d/src/dpi/uvm_svcmd_dpi.svh +<<<<<<< HEAD +80 19 +uvm_heartbeat_modes +145 14 +uvm_reg_bus_op +263 5 +value +32 10 +type_width +217 13 +uvm_apprepend +215 19 +uvm_objection_event +108 14 +uvm_tlm_sync_e +109 23 +uvm_pkg::uvm_tlm_sync_e +26 9 +oct_radix +75 24 +uvm_pkg::uvm_action_type +71 26 +uvm_pkg::uvm_severity_type +148 4 +addr +267 24 +uvm_hdl_release_and_read +121 6 +offset +78 15 +uvm_port_type_e +65 34 +uvm_pkg::uvm_recursion_policy_enum +139 22 +uvm_pkg::uvm_predict_e +152 6 +status +50 14 +uvm_config_int +63 23 +uvm_pkg::uvm_radix_enum +234 4 +name +110 19 +uvm_reg_mem_tests_e +94 25 +uvm_default_sequence_type +124 12 +uvm_status_e +111 28 +======= +2 19 +uvm_heartbeat_modes +180 14 +uvm_reg_bus_op +263 5 +value +25 26 +uvm_pkg::uvm_tlm_command_e +148 29 +uvm_pkg::uvm_reg_addr_logic_t +86 19 +uvm_objection_event +143 14 +uvm_tlm_sync_e +144 23 +uvm_pkg::uvm_tlm_sync_e +131 9 +oct_radix +67 24 +uvm_pkg::uvm_action_type +63 26 +uvm_pkg::uvm_severity_type +183 4 +addr +267 24 +uvm_hdl_release_and_read +95 44 +uvm_pkg:: +70 15 +uvm_port_type_e +57 34 +uvm_pkg::uvm_recursion_policy_enum +174 22 +uvm_pkg::uvm_predict_e +187 6 +status +46 14 +uvm_config_int +55 23 +uvm_pkg::uvm_radix_enum +105 4 +name +145 19 +uvm_reg_mem_tests_e +16 25 +uvm_default_sequence_type +159 12 +uvm_status_e +146 28 +>>>>>>> ceab28f188594b972dededef57152e3a46196cbf +uvm_pkg::uvm_reg_mem_tests_e +188 55 +uvm_pkg:: +<<<<<<< HEAD +175 49 + +224 44 +uvm_pkg:: +103 26 +uvm_pkg::uvm_tlm_command_e +36 20 +uvm_pack_bitstream_t +28 9 +hex_radix +62 14 +uvm_radix_enum +3 31 +======= +72 12 +SEQ_ARB_TYPE +156 6 +offset +137 10 +type_width +32 20 +uvm_pack_bitstream_t +33 29 +uvm_pkg::uvm_pack_bitstream_t +54 14 +uvm_radix_enum +110 31 +>>>>>>> ceab28f188594b972dededef57152e3a46196cbf +uvm_pkg::uvm_tree_printer_knobs +161 18 +uvm_reg_bd_cb_iter +<<<<<<< HEAD +88 42 + +39 22 +======= +10 42 + +35 22 +>>>>>>> ceab28f188594b972dededef57152e3a46196cbf +uvm_pkg::uvm_report_cb +238 49 + +192 57 +uvm_pkg:: +<<<<<<< HEAD +201 12 +SEQ_ARB_TYPE +106 15 +uvm_tlm_phase_e +114 17 +uvm_reg_byte_en_t +37 29 +uvm_pkg::uvm_pack_bitstream_t +======= +210 49 + +141 15 +uvm_tlm_phase_e +149 17 +uvm_reg_byte_en_t +83 29 +uvm_pkg::uvm_phase_transition +>>>>>>> ceab28f188594b972dededef57152e3a46196cbf +242 47 + +189 40 + +<<<<<<< HEAD +46 24 +uvm_id_verbosities_array +22 10 +show_radix +======= +42 24 +uvm_id_verbosities_array +41 26 +uvm_pkg::uvm_id_file_array +>>>>>>> ceab28f188594b972dededef57152e3a46196cbf +259 4 +glob +158 24 +uvm_pkg::uvm_reg_cb_iter +<<<<<<< HEAD +131 25 +uvm_pkg::uvm_endianness_e +135 21 +uvm_pkg::uvm_access_e +74 15 +uvm_action_type +18 6 +indent +122 19 +uvm_reg_cvr_rsrc_db +246 22 +uvm_dpi_get_next_arg_c +64 25 +uvm_recursion_policy_enum +31 10 +name_width +194 51 +uvm_pkg:: +209 15 +uvm_phase_state +45 26 +uvm_pkg::uvm_id_file_array +83 28 +uvm_pkg::uvm_heartbeat_cbs_t +184 59 +uvm_pkg:: +172 26 +uvm_pkg::uvm_vreg_field_cb +21 9 +separator +191 48 + +60 14 + +68 14 + +11 9 +======= +166 25 +uvm_pkg::uvm_endianness_e +82 20 +uvm_phase_transition +66 15 +uvm_action_type +123 6 +indent +157 19 +uvm_reg_cvr_rsrc_db +246 22 +uvm_dpi_get_next_arg_c +56 25 +uvm_recursion_policy_enum +60 14 + +229 51 +uvm_pkg:: +80 15 +uvm_phase_state +127 10 +show_radix +5 28 +uvm_pkg::uvm_heartbeat_cbs_t +170 21 +uvm_pkg::uvm_access_e +207 26 +uvm_pkg::uvm_vreg_field_cb +126 9 +separator +78 14 +uvm_phase_type +30 14 + +136 10 +name_width +106 9 +>>>>>>> ceab28f188594b972dededef57152e3a46196cbf +type_name +165 15 +uvm_mem_cb_iter +<<<<<<< HEAD +93 52 +======= +15 52 +>>>>>>> ceab28f188594b972dededef57152e3a46196cbf +uvm_pkg:: +211 20 +uvm_phase_transition +183 50 + +180 25 +uvm_pkg::uvm_vreg_cb_iter +<<<<<<< HEAD +40 18 +uvm_report_cb_iter +58 14 +uvm_hdl_data_t +4 6 +#vtbl# +212 29 +uvm_pkg::uvm_phase_transition +146 23 +uvm_pkg::uvm_reg_bus_op +269 2 +re +107 24 +======= +36 18 +uvm_report_cb_iter +28 14 +uvm_hdl_data_t +111 6 +#vtbl# +133 9 +hex_radix +181 23 +uvm_pkg::uvm_reg_bus_op +269 2 +re +142 24 +>>>>>>> ceab28f188594b972dededef57152e3a46196cbf +uvm_pkg::uvm_tlm_phase_e +195 48 + +193 42 + +<<<<<<< HEAD +210 24 +uvm_pkg::uvm_phase_state +196 57 +uvm_pkg:: +13 5 +depth +149 4 +data +89 51 +uvm_pkg:: +57 28 +======= +81 24 +uvm_pkg::uvm_phase_state +100 18 +uvm_config_wrapper +118 5 +depth +184 4 +data +11 51 +uvm_pkg:: +53 28 +>>>>>>> ceab28f188594b972dededef57152e3a46196cbf +uvm_pkg::uvm_objection_cbs_t +176 58 +uvm_pkg:: +<<<<<<< HEAD +29 9 +max_width +118 18 +uvm_hdl_path_slice +41 27 +uvm_pkg::uvm_report_cb_iter +207 14 +uvm_phase_type +7 6 +header +96 26 +uvm_default_sequencer_type +120 4 +path +73 23 +uvm_pkg:: +33 10 +size_width +126 10 +uvm_path_e +251 5 +regex +19 9 +show_root +81 28 +uvm_pkg::uvm_heartbeat_modes +150 6 +n_bits +61 23 +uvm_pkg:: +261 40 +verilog_src/uvm-1.1d/src/dpi/uvm_hdl.svh +141 31 +uvm_pkg::uvm_reg_map_addr_range +187 46 + +147 4 +kind +249 26 +uvm_dpi_get_tool_version_c +95 34 +uvm_pkg::uvm_default_sequence_type +129 20 +uvm_pkg::uvm_check_e +90 47 + +24 9 +dec_radix +222 23 +uvm_pkg::uvm_event_pool +203 23 +uvm_sequence_state_enum +125 21 +uvm_pkg::uvm_status_e +260 18 +uvm_hdl_check_path +144 6 +stride +213 11 +uvm_wait_op +84 14 +uvm_config_seq +216 28 +======= +134 9 +max_width +153 18 +uvm_hdl_path_slice +37 27 +uvm_pkg::uvm_report_cb_iter +226 48 + +3 28 +uvm_pkg::uvm_heartbeat_modes +18 26 +uvm_default_sequencer_type +84 11 +uvm_wait_op +65 23 +uvm_pkg:: +138 10 +size_width +161 10 +uvm_path_e +251 5 +regex +124 9 +show_root +12 47 + +185 6 +n_bits +31 23 +uvm_pkg:: +261 40 +verilog_src/uvm-1.1d/src/dpi/uvm_hdl.svh +176 31 +uvm_pkg::uvm_reg_map_addr_range +155 4 +path +182 4 +kind +249 26 +uvm_dpi_get_tool_version_c +17 34 +uvm_pkg::uvm_default_sequence_type +164 20 +uvm_pkg::uvm_check_e +114 6 +header +129 9 +dec_radix +93 23 +uvm_pkg::uvm_event_pool +74 23 +uvm_sequence_state_enum +96 38 + +260 18 +uvm_hdl_check_path +179 6 +stride +222 46 + +6 14 +uvm_config_seq +87 28 +>>>>>>> ceab28f188594b972dededef57152e3a46196cbf +uvm_pkg::uvm_objection_event +199 46 + +<<<<<<< HEAD +223 35 +======= +94 35 +>>>>>>> ceab28f188594b972dededef57152e3a46196cbf + +163 10 +uvm_mem_cb +<<<<<<< HEAD +20 3 +mcd +220 25 +uvm_pkg::uvm_barrier_pool +206 30 +uvm_pkg::uvm_sequence_lib_mode +143 3 +max +116 20 +uvm_coverage_model_e +55 26 +uvm_pkg::uvm_config_object +227 36 + +59 23 +uvm_pkg::uvm_hdl_data_t +67 32 +uvm_pkg::uvm_active_passive_enum +104 25 +======= +125 3 +mcd +91 25 +uvm_pkg::uvm_barrier_pool +77 30 +uvm_pkg::uvm_sequence_lib_mode +160 21 +uvm_pkg::uvm_status_e +151 20 +uvm_coverage_model_e +51 26 +uvm_pkg::uvm_config_object +98 36 + +29 23 +uvm_pkg::uvm_hdl_data_t +59 32 +uvm_pkg::uvm_active_passive_enum +26 25 +>>>>>>> ceab28f188594b972dededef57152e3a46196cbf +uvm_tlm_response_status_e +164 19 +uvm_pkg::uvm_mem_cb +<<<<<<< HEAD +128 11 +uvm_check_e +52 17 +uvm_config_string +======= +163 11 +uvm_check_e +19 35 +uvm_pkg::uvm_default_sequencer_type +>>>>>>> ceab28f188594b972dededef57152e3a46196cbf +1 23 +uvm_pkg:: +160 22 +uvm_pkg::uvm_reg_bd_cb +<<<<<<< HEAD +208 23 +uvm_pkg::uvm_phase_type +225 38 + +25 9 +bin_radix +0 14 + +6 6 +#ciid# +229 18 +uvm_config_wrapper +218 22 +uvm_pkg::uvm_apprepend +97 35 +uvm_pkg::uvm_default_sequencer_type +======= +79 23 +uvm_pkg::uvm_phase_type +178 3 +max +130 9 +bin_radix +0 14 + +113 6 +#ciid# +231 57 +uvm_pkg:: +89 22 +uvm_pkg::uvm_apprepend +48 17 +uvm_config_string +>>>>>>> ceab28f188594b972dededef57152e3a46196cbf +257 42 +verilog_src/uvm-1.1d/src/dpi/uvm_regex.svh +197 42 + +<<<<<<< HEAD +23 13 +default_radix +119 27 +uvm_pkg::uvm_hdl_path_slice +17 6 +======= +128 13 +default_radix +154 27 +uvm_pkg::uvm_hdl_path_slice +122 6 +>>>>>>> ceab28f188594b972dededef57152e3a46196cbf +prefix +248 23 +uvm_dpi_get_tool_name_c +200 55 +uvm_pkg:: +<<<<<<< HEAD +2 22 +======= +109 22 +>>>>>>> ceab28f188594b972dededef57152e3a46196cbf +uvm_tree_printer_knobs +198 51 +uvm_pkg:: +243 56 +uvm_pkg:: +<<<<<<< HEAD +123 28 +uvm_pkg::uvm_reg_cvr_rsrc_db +168 25 +uvm_pkg::uvm_reg_field_cb +49 31 +uvm_pkg::uvm_sev_override_array +101 41 +uvm_pkg::uvm_default_sequencer_param_type +43 29 +======= +158 28 +uvm_pkg::uvm_reg_cvr_rsrc_db +97 47 +uvm_pkg:: +45 31 +uvm_pkg::uvm_sev_override_array +23 41 +uvm_pkg::uvm_default_sequencer_param_type +39 29 +>>>>>>> ceab28f188594b972dededef57152e3a46196cbf +uvm_pkg::uvm_id_actions_array +173 22 +uvm_vreg_field_cb_iter +<<<<<<< HEAD +16 12 +end_elements +258 14 +uvm_glob_to_re +27 14 +unsigned_radix +42 20 +uvm_id_actions_array +226 47 +uvm_pkg:: +133 24 +uvm_pkg::uvm_elem_kind_e +157 15 +uvm_reg_cb_iter +174 31 +uvm_pkg::uvm_vreg_field_cb_iter +76 13 +uvm_verbosity +35 6 +sprint +265 12 +uvm_hdl_read +8 6 +footer +250 15 +uvm_dpi_regcomp +72 14 + +70 17 +======= +121 12 +end_elements +258 14 +uvm_glob_to_re +132 14 +unsigned_radix +38 20 +uvm_id_actions_array +203 25 +uvm_pkg::uvm_reg_field_cb +103 29 +uvm_pkg::uvm_printer_row_info +85 20 +uvm_pkg::uvm_wait_op +209 31 +uvm_pkg::uvm_vreg_field_cb_iter +68 13 +uvm_verbosity +140 6 +sprint +265 12 +uvm_hdl_read +115 6 +footer +250 15 +uvm_dpi_regcomp +64 14 + +62 17 +>>>>>>> ceab28f188594b972dededef57152e3a46196cbf +uvm_severity_type +178 20 +uvm_pkg::uvm_vreg_cb +<<<<<<< HEAD +153 41 + +82 19 +uvm_heartbeat_cbs_t +156 19 +uvm_pkg::uvm_reg_cb +214 20 +uvm_pkg::uvm_wait_op +112 20 +======= +188 41 + +4 19 +uvm_heartbeat_cbs_t +168 24 +uvm_pkg::uvm_elem_kind_e +192 15 +uvm_reg_cb_iter +147 20 +>>>>>>> ceab28f188594b972dededef57152e3a46196cbf +uvm_reg_addr_logic_t +239 58 +uvm_pkg:: +179 16 +uvm_vreg_cb_iter +<<<<<<< HEAD +142 3 +======= +177 3 +>>>>>>> ceab28f188594b972dededef57152e3a46196cbf +min +182 52 +uvm_pkg:: +<<<<<<< HEAD +30 10 +truncation +132 15 +uvm_elem_kind_e +254 3 +str +169 21 +uvm_reg_field_cb_iter +170 30 +uvm_pkg::uvm_reg_field_cb_iter +241 62 +uvm_pkg:: +204 32 +uvm_pkg::uvm_sequence_state_enum +5 12 +#rand_state# +48 22 +uvm_sev_override_array +117 29 +uvm_pkg::uvm_coverage_model_e +205 21 +uvm_sequence_lib_mode +99 32 +uvm_pkg::uvm_default_driver_type +98 23 +uvm_default_driver_type +14 9 +reference +181 43 + +136 10 +uvm_hier_e +221 14 +uvm_event_pool +79 24 +uvm_pkg::uvm_port_type_e +202 21 +uvm_pkg::SEQ_ARB_TYPE +235 3 +======= +135 10 +truncation +76 21 +uvm_sequence_lib_mode +254 3 +str +191 19 +uvm_pkg::uvm_reg_cb +205 30 +uvm_pkg::uvm_reg_field_cb_iter +241 62 +uvm_pkg:: +75 32 +uvm_pkg::uvm_sequence_state_enum +73 21 +uvm_pkg::SEQ_ARB_TYPE +44 22 +uvm_sev_override_array +152 29 +uvm_pkg::uvm_coverage_model_e +167 15 +uvm_elem_kind_e +21 32 +uvm_pkg::uvm_default_driver_type +20 23 +uvm_default_driver_type +119 9 +reference +216 43 + +171 10 +uvm_hier_e +92 14 +uvm_event_pool +71 24 +uvm_pkg::uvm_port_type_e +112 12 +#rand_state# +108 3 +>>>>>>> ceab28f188594b972dededef57152e3a46196cbf +val +262 15 +uvm_hdl_deposit +268 12 +uvm_re_match +<<<<<<< HEAD +9 9 +full_name +15 14 +begin_elements +155 10 +======= +116 9 +full_name +104 5 +level +190 10 +>>>>>>> ceab28f188594b972dededef57152e3a46196cbf +uvm_reg_cb +SYM_END +TYPEDEF_BEGIN 100 +0 52 +0 -1 1 0x0 1 0 52 16 1 4 17413 0 0 0 -1 0 0 0x1 1 0 +<<<<<<< HEAD +2 1890 +2 -1 3 0x0 1 0 24 0 1 4 33 32 0 0 0 0 0x0 1 0 2 0 0 120 1 490 32 32 0 0 0x2 1 32 4 0 0x0 1 0 25 0 -1 4 278561 32 0 31 31 0 32 0x1 0 0 0 -1 5 4 0x0 1 0 25 0 -1 4 278561 32 0 31 31 0 32 0x1 0 0 0 -1 6 8 0x0 1 0 12 0 -1 8 278571 64 0 63 63 0 64 0x1 0 0 0 -1 7 16 0x0 1 0 12 0 1 1 41 1 0 0 0 0 1 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b/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/project_benches/block_3/sim/work/optimized_debug_top_tb/_dpi/dpi.tfdb @@ -0,0 +1,1402 @@ +VERSION 10 1 1 +SYM_BEGIN 270 +132 13 +uvm_reg_bd_cb +252 15 +uvm_dpi_regexec +<<<<<<< HEAD +229 23 +uvm_pkg::uvm_config_int +77 34 +======= +47 23 +uvm_pkg::uvm_config_int +27 34 +>>>>>>> ceab28f188594b972dededef57152e3a46196cbf +uvm_pkg::uvm_tlm_response_status_e +107 12 +uvm_access_e +<<<<<<< HEAD +234 19 +uvm_objection_cbs_t +216 13 +uvm_report_cb +24 16 +uvm_barrier_pool +111 13 +uvm_predict_e +45 23 +uvm_pkg:: +94 4 +size +178 5 +level +72 32 +uvm_default_sequencer_param_type +192 9 +reference +175 27 +uvm_pkg::uvm_config_wrapper +266 15 +uvm_hdl_release +231 26 +======= +52 19 +uvm_objection_cbs_t +34 13 +uvm_report_cb +7 23 +uvm_pkg::uvm_config_seq +173 13 +uvm_predict_e +9 30 +uvm_pkg::uvm_virtual_sequencer +107 4 +size +120 14 +begin_elements +22 32 +uvm_default_sequencer_param_type +204 21 +uvm_reg_field_cb_iter +101 27 +uvm_pkg::uvm_config_wrapper +266 15 +uvm_hdl_release +49 26 +>>>>>>> ceab28f188594b972dededef57152e3a46196cbf +uvm_pkg::uvm_config_string +110 19 +uvm_pkg::uvm_hier_e +264 13 +uvm_hdl_force +159 53 +uvm_pkg:: +<<<<<<< HEAD +42 23 +uvm_active_passive_enum +57 23 +uvm_pkg::uvm_config_seq +59 30 +uvm_pkg::uvm_virtual_sequencer +193 14 +begin_elements +63 56 +======= +58 23 +uvm_active_passive_enum +90 16 +uvm_barrier_pool +61 23 +uvm_pkg:: +40 17 +uvm_id_file_array +13 56 +>>>>>>> ceab28f188594b972dededef57152e3a46196cbf +uvm_pkg:: +240 53 + +139 24 +uvm_pkg::uvm_mem_cb_iter +<<<<<<< HEAD +212 11 +======= +139 11 +>>>>>>> ceab28f188594b972dededef57152e3a46196cbf +value_width +253 4 +preg +87 26 +uvm_pkg::uvm_reg_byte_en_t +<<<<<<< HEAD +3 22 +uvm_pkg::uvm_verbosity +103 16 +uvm_endianness_e +127 50 +uvm_pkg:: +232 17 +======= +69 22 +uvm_pkg::uvm_verbosity +102 20 +uvm_printer_row_info +189 50 +uvm_pkg:: +50 17 +>>>>>>> ceab28f188594b972dededef57152e3a46196cbf +uvm_config_object +222 17 +uvm_id_file_array +245 57 +uvm_pkg:: +236 48 + +140 16 +uvm_reg_field_cb +<<<<<<< HEAD +58 21 +uvm_virtual_sequencer +74 17 +======= +8 21 +uvm_virtual_sequencer +24 17 +>>>>>>> ceab28f188594b972dededef57152e3a46196cbf +uvm_tlm_command_e +124 7 +byte_en +113 22 +uvm_reg_map_addr_range +<<<<<<< HEAD +176 20 +uvm_printer_row_info +22 13 +uvm_apprepend +163 49 +uvm_pkg:: +256 17 +uvm_dump_re_cache +33 45 +======= +165 16 +uvm_endianness_e +14 43 + +225 49 +uvm_pkg:: +256 17 +uvm_dump_re_cache +99 45 +>>>>>>> ceab28f188594b972dededef57152e3a46196cbf +uvm_pkg:: +135 27 +uvm_pkg::uvm_reg_bd_cb_iter +237 57 +uvm_pkg:: +<<<<<<< HEAD +190 10 +identifier +244 48 + +4 15 +uvm_port_type_e +64 43 + +144 17 +======= +117 10 +identifier +244 48 + +43 33 +uvm_pkg::uvm_id_verbosities_array +88 13 +uvm_apprepend +206 17 +>>>>>>> ceab28f188594b972dededef57152e3a46196cbf +uvm_vreg_field_cb +158 44 + +255 15 +uvm_dpi_regfree +150 11 +uvm_vreg_cb +247 46 +verilog_src/uvm-1.1d/src/dpi/uvm_svcmd_dpi.svh +<<<<<<< HEAD +52 19 +======= +2 19 +>>>>>>> ceab28f188594b972dededef57152e3a46196cbf +uvm_heartbeat_modes +118 14 +uvm_reg_bus_op +263 5 +value +<<<<<<< HEAD +75 26 +uvm_pkg::uvm_tlm_command_e +85 29 +uvm_pkg::uvm_reg_addr_logic_t +20 19 +======= +25 26 +uvm_pkg::uvm_tlm_command_e +148 29 +uvm_pkg::uvm_reg_addr_logic_t +86 19 +>>>>>>> ceab28f188594b972dededef57152e3a46196cbf +uvm_objection_event +80 14 +uvm_tlm_sync_e +81 23 +uvm_pkg::uvm_tlm_sync_e +<<<<<<< HEAD +204 9 +oct_radix +51 24 +uvm_pkg::uvm_action_type +47 26 +======= +131 9 +oct_radix +67 24 +uvm_pkg::uvm_action_type +63 26 +>>>>>>> ceab28f188594b972dededef57152e3a46196cbf +uvm_pkg::uvm_severity_type +121 4 +addr +267 24 +uvm_hdl_release_and_read +<<<<<<< HEAD +29 44 +uvm_pkg:: +78 15 +uvm_tlm_phase_e +41 34 +======= +95 44 +uvm_pkg:: +70 15 +uvm_port_type_e +57 34 +>>>>>>> ceab28f188594b972dededef57152e3a46196cbf +uvm_pkg::uvm_recursion_policy_enum +112 22 +uvm_pkg::uvm_predict_e +125 6 +status +<<<<<<< HEAD +228 14 +uvm_config_int +39 23 +uvm_pkg::uvm_radix_enum +179 4 +======= +46 14 +uvm_config_int +55 23 +uvm_pkg::uvm_radix_enum +105 4 +>>>>>>> ceab28f188594b972dededef57152e3a46196cbf +name +82 19 +uvm_reg_mem_tests_e +<<<<<<< HEAD +66 25 +======= +16 25 +>>>>>>> ceab28f188594b972dededef57152e3a46196cbf +uvm_default_sequence_type +97 12 +uvm_status_e +83 28 +uvm_pkg::uvm_reg_mem_tests_e +161 55 +uvm_pkg:: +<<<<<<< HEAD +6 12 +======= +72 12 +>>>>>>> ceab28f188594b972dededef57152e3a46196cbf +SEQ_ARB_TYPE +93 6 +offset +<<<<<<< HEAD +210 10 +type_width +214 20 +uvm_pack_bitstream_t +17 29 +uvm_pkg::uvm_phase_transition +38 14 +uvm_radix_enum +183 31 +======= +137 10 +type_width +32 20 +uvm_pack_bitstream_t +33 29 +uvm_pkg::uvm_pack_bitstream_t +54 14 +uvm_radix_enum +110 31 +>>>>>>> ceab28f188594b972dededef57152e3a46196cbf +uvm_pkg::uvm_tree_printer_knobs +134 18 +uvm_reg_bd_cb_iter +<<<<<<< HEAD +60 42 + +16 20 +uvm_phase_transition +======= +10 42 + +35 22 +uvm_pkg::uvm_report_cb +>>>>>>> ceab28f188594b972dededef57152e3a46196cbf +238 49 + +165 57 +uvm_pkg:: +148 49 + +225 33 +uvm_pkg::uvm_id_verbosities_array +86 17 +uvm_reg_byte_en_t +<<<<<<< HEAD +206 9 +hex_radix +======= +83 29 +uvm_pkg::uvm_phase_transition +>>>>>>> ceab28f188594b972dededef57152e3a46196cbf +242 47 + +162 40 + +<<<<<<< HEAD +224 24 +uvm_id_verbosities_array +200 10 +show_radix +======= +42 24 +uvm_id_verbosities_array +41 26 +uvm_pkg::uvm_id_file_array +>>>>>>> ceab28f188594b972dededef57152e3a46196cbf +259 4 +glob +131 24 +uvm_pkg::uvm_reg_cb_iter +104 25 +uvm_pkg::uvm_endianness_e +<<<<<<< HEAD +108 21 +uvm_pkg::uvm_access_e +50 15 +uvm_action_type +153 25 +uvm_pkg::uvm_vreg_cb_iter +95 19 +uvm_reg_cvr_rsrc_db +246 22 +uvm_dpi_get_next_arg_c +40 25 +uvm_recursion_policy_enum +44 14 + +167 51 +uvm_pkg:: +14 15 +uvm_phase_state +138 15 +uvm_mem_cb_iter +55 28 +======= +82 20 +uvm_phase_transition +66 15 +uvm_action_type +123 6 +indent +157 19 +uvm_reg_cvr_rsrc_db +246 22 +uvm_dpi_get_next_arg_c +56 25 +uvm_recursion_policy_enum +60 14 + +229 51 +uvm_pkg:: +80 15 +uvm_phase_state +127 10 +show_radix +5 28 +>>>>>>> ceab28f188594b972dededef57152e3a46196cbf +uvm_pkg::uvm_heartbeat_cbs_t +157 59 +uvm_pkg:: +145 26 +uvm_pkg::uvm_vreg_field_cb +<<<<<<< HEAD +199 9 +separator +12 14 +uvm_phase_type +36 14 + +119 23 +uvm_pkg::uvm_reg_bus_op +180 9 +type_name +223 26 +uvm_pkg::uvm_id_file_array +65 52 +======= +126 9 +separator +78 14 +uvm_phase_type +30 14 + +136 10 +name_width +106 9 +type_name +200 15 +uvm_mem_cb_iter +15 52 +>>>>>>> ceab28f188594b972dededef57152e3a46196cbf +uvm_pkg:: +217 22 +uvm_pkg::uvm_report_cb +156 50 + +<<<<<<< HEAD +166 42 + +218 18 +uvm_report_cb_iter +34 14 +uvm_hdl_data_t +184 6 +#vtbl# +215 29 +uvm_pkg::uvm_pack_bitstream_t +209 10 +name_width +======= +215 25 +uvm_pkg::uvm_vreg_cb_iter +36 18 +uvm_report_cb_iter +28 14 +uvm_hdl_data_t +111 6 +#vtbl# +133 9 +hex_radix +181 23 +uvm_pkg::uvm_reg_bus_op +>>>>>>> ceab28f188594b972dededef57152e3a46196cbf +269 2 +re +79 24 +uvm_pkg::uvm_tlm_phase_e +168 48 + +<<<<<<< HEAD +196 6 +indent +15 24 +uvm_pkg::uvm_phase_state +164 48 + +191 5 +======= +228 42 + +81 24 +uvm_pkg::uvm_phase_state +100 18 +uvm_config_wrapper +118 5 +>>>>>>> ceab28f188594b972dededef57152e3a46196cbf +depth +122 4 +data +<<<<<<< HEAD +61 51 +uvm_pkg:: +235 28 +======= +11 51 +uvm_pkg:: +53 28 +>>>>>>> ceab28f188594b972dededef57152e3a46196cbf +uvm_pkg::uvm_objection_cbs_t +149 58 +uvm_pkg:: +<<<<<<< HEAD +207 9 +======= +134 9 +>>>>>>> ceab28f188594b972dededef57152e3a46196cbf +max_width +90 18 +uvm_hdl_path_slice +<<<<<<< HEAD +219 27 +uvm_pkg::uvm_report_cb_iter +169 57 +uvm_pkg:: +53 28 +uvm_pkg::uvm_heartbeat_modes +68 26 +uvm_default_sequencer_type +18 11 +uvm_wait_op +49 23 +uvm_pkg:: +211 10 +======= +37 27 +uvm_pkg::uvm_report_cb_iter +226 48 + +3 28 +uvm_pkg::uvm_heartbeat_modes +18 26 +uvm_default_sequencer_type +84 11 +uvm_wait_op +65 23 +uvm_pkg:: +138 10 +>>>>>>> ceab28f188594b972dededef57152e3a46196cbf +size_width +99 10 +uvm_path_e +251 5 +regex +<<<<<<< HEAD +174 18 +uvm_config_wrapper +62 47 + +123 6 +n_bits +37 23 +======= +124 9 +show_root +12 47 + +185 6 +n_bits +31 23 +>>>>>>> ceab28f188594b972dededef57152e3a46196cbf +uvm_pkg:: +261 40 +verilog_src/uvm-1.1d/src/dpi/uvm_hdl.svh +114 31 +uvm_pkg::uvm_reg_map_addr_range +92 4 +path +120 4 +kind +249 26 +uvm_dpi_get_tool_version_c +<<<<<<< HEAD +67 34 +======= +17 34 +>>>>>>> ceab28f188594b972dededef57152e3a46196cbf +uvm_pkg::uvm_default_sequence_type +102 20 +uvm_pkg::uvm_check_e +<<<<<<< HEAD +101 11 +uvm_check_e +202 9 +dec_radix +27 23 +uvm_pkg::uvm_event_pool +8 23 +uvm_sequence_state_enum +30 38 +======= +114 6 +header +129 9 +dec_radix +93 23 +uvm_pkg::uvm_event_pool +74 23 +uvm_sequence_state_enum +96 38 +>>>>>>> ceab28f188594b972dededef57152e3a46196cbf + +260 18 +uvm_hdl_check_path +117 6 +stride +160 46 + +<<<<<<< HEAD +56 14 +uvm_config_seq +21 28 +======= +6 14 +uvm_config_seq +87 28 +>>>>>>> ceab28f188594b972dededef57152e3a46196cbf +uvm_pkg::uvm_objection_event +172 46 + +<<<<<<< HEAD +28 35 +======= +94 35 +>>>>>>> ceab28f188594b972dededef57152e3a46196cbf + +136 10 +uvm_mem_cb +<<<<<<< HEAD +187 6 +header +25 25 +uvm_pkg::uvm_barrier_pool +11 30 +======= +125 3 +mcd +91 25 +uvm_pkg::uvm_barrier_pool +77 30 +>>>>>>> ceab28f188594b972dededef57152e3a46196cbf +uvm_pkg::uvm_sequence_lib_mode +98 21 +uvm_pkg::uvm_status_e +88 20 +uvm_coverage_model_e +<<<<<<< HEAD +233 26 +uvm_pkg::uvm_config_object +32 36 + +35 23 +uvm_pkg::uvm_hdl_data_t +43 32 +uvm_pkg::uvm_active_passive_enum +76 25 +======= +51 26 +uvm_pkg::uvm_config_object +98 36 + +29 23 +uvm_pkg::uvm_hdl_data_t +59 32 +uvm_pkg::uvm_active_passive_enum +26 25 +>>>>>>> ceab28f188594b972dededef57152e3a46196cbf +uvm_tlm_response_status_e +137 19 +uvm_pkg::uvm_mem_cb +<<<<<<< HEAD +198 3 +mcd +69 35 +======= +163 11 +uvm_check_e +19 35 +>>>>>>> ceab28f188594b972dededef57152e3a46196cbf +uvm_pkg::uvm_default_sequencer_type +1 23 +uvm_pkg:: +133 22 +uvm_pkg::uvm_reg_bd_cb +<<<<<<< HEAD +13 23 +======= +79 23 +>>>>>>> ceab28f188594b972dededef57152e3a46196cbf +uvm_pkg::uvm_phase_type +116 3 +max +<<<<<<< HEAD +203 9 +bin_radix +0 14 + +173 55 +uvm_pkg:: +197 9 +show_root +23 22 +uvm_pkg::uvm_apprepend +171 51 +uvm_pkg:: +======= +130 9 +bin_radix +0 14 + +113 6 +#ciid# +231 57 +uvm_pkg:: +89 22 +uvm_pkg::uvm_apprepend +48 17 +uvm_config_string +>>>>>>> ceab28f188594b972dededef57152e3a46196cbf +257 42 +verilog_src/uvm-1.1d/src/dpi/uvm_regex.svh +170 42 + +<<<<<<< HEAD +201 13 +======= +128 13 +>>>>>>> ceab28f188594b972dededef57152e3a46196cbf +default_radix +91 27 +uvm_pkg::uvm_hdl_path_slice +<<<<<<< HEAD +195 6 +prefix +248 23 +uvm_dpi_get_tool_name_c +186 6 +#ciid# +182 22 +======= +122 6 +prefix +248 23 +uvm_dpi_get_tool_name_c +235 55 +uvm_pkg:: +109 22 +>>>>>>> ceab28f188594b972dededef57152e3a46196cbf +uvm_tree_printer_knobs +230 17 +uvm_config_string +243 56 +uvm_pkg:: +96 28 +uvm_pkg::uvm_reg_cvr_rsrc_db +<<<<<<< HEAD +31 47 +uvm_pkg:: +19 20 +uvm_pkg::uvm_wait_op +73 41 +uvm_pkg::uvm_default_sequencer_param_type +147 31 +uvm_pkg::uvm_vreg_field_cb_iter +146 22 +uvm_vreg_field_cb_iter +194 12 +end_elements +258 14 +uvm_glob_to_re +205 14 +unsigned_radix +48 14 + +141 25 +uvm_pkg::uvm_reg_field_cb +106 24 +uvm_pkg::uvm_elem_kind_e +130 15 +uvm_reg_cb_iter +221 29 +uvm_pkg::uvm_id_actions_array +2 13 +uvm_verbosity +213 6 +sprint +265 12 +uvm_hdl_read +188 6 +footer +250 15 +uvm_dpi_regcomp +220 20 +uvm_id_actions_array +46 17 +======= +97 47 +uvm_pkg:: +45 31 +uvm_pkg::uvm_sev_override_array +23 41 +uvm_pkg::uvm_default_sequencer_param_type +39 29 +uvm_pkg::uvm_id_actions_array +208 22 +uvm_vreg_field_cb_iter +121 12 +end_elements +258 14 +uvm_glob_to_re +132 14 +unsigned_radix +38 20 +uvm_id_actions_array +203 25 +uvm_pkg::uvm_reg_field_cb +103 29 +uvm_pkg::uvm_printer_row_info +85 20 +uvm_pkg::uvm_wait_op +209 31 +uvm_pkg::uvm_vreg_field_cb_iter +68 13 +uvm_verbosity +140 6 +sprint +265 12 +uvm_hdl_read +115 6 +footer +250 15 +uvm_dpi_regcomp +64 14 + +62 17 +>>>>>>> ceab28f188594b972dededef57152e3a46196cbf +uvm_severity_type +151 20 +uvm_pkg::uvm_vreg_cb +126 41 + +<<<<<<< HEAD +54 19 +======= +4 19 +>>>>>>> ceab28f188594b972dededef57152e3a46196cbf +uvm_heartbeat_cbs_t +129 19 +uvm_pkg::uvm_reg_cb +227 31 +uvm_pkg::uvm_sev_override_array +84 20 +uvm_reg_addr_logic_t +239 58 +uvm_pkg:: +152 16 +uvm_vreg_cb_iter +115 3 +min +155 52 +uvm_pkg:: +<<<<<<< HEAD +208 10 +truncation +10 21 +======= +135 10 +truncation +76 21 +>>>>>>> ceab28f188594b972dededef57152e3a46196cbf +uvm_sequence_lib_mode +254 3 +str +142 21 +uvm_reg_field_cb_iter +143 30 +uvm_pkg::uvm_reg_field_cb_iter +241 62 +uvm_pkg:: +<<<<<<< HEAD +9 32 +uvm_pkg::uvm_sequence_state_enum +7 21 +uvm_pkg::SEQ_ARB_TYPE +181 3 +val +89 29 +======= +75 32 +uvm_pkg::uvm_sequence_state_enum +73 21 +uvm_pkg::SEQ_ARB_TYPE +44 22 +uvm_sev_override_array +152 29 +>>>>>>> ceab28f188594b972dededef57152e3a46196cbf +uvm_pkg::uvm_coverage_model_e +105 15 +uvm_elem_kind_e +<<<<<<< HEAD +71 32 +uvm_pkg::uvm_default_driver_type +70 23 +uvm_default_driver_type +128 10 +uvm_reg_cb +154 43 +======= +21 32 +uvm_pkg::uvm_default_driver_type +20 23 +uvm_default_driver_type +119 9 +reference +216 43 +>>>>>>> ceab28f188594b972dededef57152e3a46196cbf + +109 10 +uvm_hier_e +<<<<<<< HEAD +26 14 +uvm_event_pool +5 24 +uvm_pkg::uvm_port_type_e +185 12 +#rand_state# +226 22 +uvm_sev_override_array +======= +92 14 +uvm_event_pool +71 24 +uvm_pkg::uvm_port_type_e +112 12 +#rand_state# +108 3 +val +>>>>>>> ceab28f188594b972dededef57152e3a46196cbf +262 15 +uvm_hdl_deposit +268 12 +uvm_re_match +<<<<<<< HEAD +189 9 +full_name +100 19 +uvm_pkg::uvm_path_e +177 29 +uvm_pkg::uvm_printer_row_info +======= +116 9 +full_name +104 5 +level +190 10 +uvm_reg_cb +>>>>>>> ceab28f188594b972dededef57152e3a46196cbf +SYM_END +TYPEDEF_BEGIN 100 +0 52 +0 -1 1 0x0 1 0 52 16 1 4 17413 0 0 0 -1 0 0 0x1 1 0 +2 56 +2 -1 3 0x0 1 0 12 0 -1 4 278571 32 0 31 31 0 32 0x1 2 0 +<<<<<<< HEAD +4 56 +4 -1 5 0x0 1 0 12 0 -1 4 278571 32 0 31 31 0 32 0x1 3 0 +6 56 +6 -1 7 0x0 1 0 12 0 -1 4 278571 32 0 31 31 0 32 0x1 4 0 +8 56 +8 -1 9 0x0 1 0 12 0 -1 4 278571 32 0 31 31 0 32 0x1 5 0 +10 58 +10 -1 11 0x0 1 0 12 0 -1 4 278571 32 0 31 31 0 32 0x1 6 0 +12 58 +12 -1 13 0x0 1 0 12 0 -1 4 278571 32 0 31 31 0 32 0x1 7 0 +14 58 +14 -1 15 0x0 1 0 12 0 -1 4 278571 32 0 31 31 0 32 0x1 8 0 +16 58 +16 -1 17 0x0 1 0 12 0 -1 4 278571 32 0 31 31 0 32 0x1 9 0 +18 59 +18 -1 19 0x0 1 0 12 0 -1 4 278571 32 0 31 31 0 32 0x1 10 0 +20 59 +20 -1 21 0x0 1 0 12 0 -1 4 278571 32 0 31 31 0 32 0x1 11 0 +22 59 +22 -1 23 0x0 1 0 12 0 -1 4 278571 32 0 31 31 0 32 0x1 12 0 +24 84 +24 -1 25 0x0 1 0 24 0 1 4 33 32 0 0 0 0 0x0 1 0 22 0 1 8 9 1 0 0 0 0 1 0x1 0x1 13 0 +26 84 +26 -1 27 0x0 1 0 24 0 1 4 33 32 0 0 0 0 0x0 1 0 22 0 1 8 9 1 0 0 0 0 1 0x1 0x1 14 0 +28 84 +28 -1 29 0x0 1 0 24 0 1 4 33 32 0 0 0 0 0x0 1 0 22 0 1 8 9 1 0 0 0 0 1 0x1 0x1 15 0 +30 84 +30 -1 31 0x0 1 0 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index 00000000..e69de29b diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/project_benches/block_3/sim/work/optimized_debug_top_tb/_lib5_0.qtl b/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/project_benches/block_3/sim/work/optimized_debug_top_tb/_lib5_0.qtl new file mode 100644 index 00000000..74eefbb8 Binary files /dev/null and b/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/project_benches/block_3/sim/work/optimized_debug_top_tb/_lib5_0.qtl differ diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/project_benches/block_3/sim/xwaves.sigs b/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/project_benches/block_3/sim/xwaves.sigs new file mode 100644 index 00000000..d75f0a57 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/project_benches/block_3/sim/xwaves.sigs @@ -0,0 +1,17 @@ + + + + + +# pragma uvmf custom additional begin + +Group All + +#Top level signals +hdl_top.* +#Add additional levels or individual signals as needed +hdl_top.*.* + +# pragma uvmf custom additional end + + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/project_benches/block_3/tb/parameters/block_3_parameters_pkg.compile b/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/project_benches/block_3/tb/parameters/block_3_parameters_pkg.compile new file mode 100644 index 00000000..5315773a --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/project_benches/block_3/tb/parameters/block_3_parameters_pkg.compile @@ -0,0 +1,4 @@ +needs: + - $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg_hdl.compile +src: + - block_3_parameters_pkg.sv diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/project_benches/block_3/tb/parameters/block_3_parameters_pkg.sv b/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/project_benches/block_3/tb/parameters/block_3_parameters_pkg.sv new file mode 100644 index 00000000..d23d05b6 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/project_benches/block_3/tb/parameters/block_3_parameters_pkg.sv @@ -0,0 +1,38 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This package contains test level parameters +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// + + +package block_3_parameters_pkg; + + import uvmf_base_pkg_hdl::*; + + // pragma uvmf custom package_imports_additional begin + // pragma uvmf custom package_imports_additional end + + + // These parameters are used to uniquely identify each interface. The monitor_bfm and + // driver_bfm are placed into and retrieved from the uvm_config_db using these string + // names as the field_name. The parameter is also used to enable transaction viewing + // from the command line for selected interfaces using the UVM command line processing. + parameter string wb_master_BFM = "wb_master_BFM"; /* [0] */ + parameter string axi_slave_BFM = "axi_slave_BFM"; /* [1] */ + + // pragma uvmf custom package_item_additional begin + // pragma uvmf custom package_item_additional end + +endpackage + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/project_benches/block_3/tb/parameters/block_3_parameters_pkg.vinfo b/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/project_benches/block_3/tb/parameters/block_3_parameters_pkg.vinfo new file mode 100644 index 00000000..2e4b56d0 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/project_benches/block_3/tb/parameters/block_3_parameters_pkg.vinfo @@ -0,0 +1,2 @@ +@use $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg_hdl.vinfo +block_3_parameters_pkg.sv diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/project_benches/block_3/tb/sequences/block_3_sequences_pkg.compile b/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/project_benches/block_3/tb/sequences/block_3_sequences_pkg.compile new file mode 100644 index 00000000..bb608184 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/project_benches/block_3/tb/sequences/block_3_sequences_pkg.compile @@ -0,0 +1,8 @@ +needs: + - $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg.compile + - ../../../../verification_ip/interface_packages/wb_m_pkg/wb_m.compile + - ../../../../verification_ip/interface_packages/axi_s_pkg/axi_s.compile + - ../../../../verification_ip/environment_packages/block_3_env_pkg/block_3_env_pkg.compile + - ../parameters/block_3_parameters_pkg.compile +src: + - block_3_sequences_pkg.sv diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/project_benches/block_3/tb/sequences/block_3_sequences_pkg.sv b/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/project_benches/block_3/tb/sequences/block_3_sequences_pkg.sv new file mode 100644 index 00000000..ae20b8a7 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/project_benches/block_3/tb/sequences/block_3_sequences_pkg.sv @@ -0,0 +1,51 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This package includes all high level sequence classes used +// in the environment. These include utility sequences and top +// level sequences. +// +// CONTAINS: +// - +// - +// +//---------------------------------------------------------------------- +// +//---------------------------------------------------------------------- +// + +package block_3_sequences_pkg; + import uvm_pkg::*; + import uvmf_base_pkg::*; + import wb_m_pkg::*; + import wb_m_pkg_hdl::*; + import axi_s_pkg::*; + import axi_s_pkg_hdl::*; + import block_3_parameters_pkg::*; + import block_3_env_pkg::*; + `include "uvm_macros.svh" + + // pragma uvmf custom package_imports_additional begin + // pragma uvmf custom package_imports_additional end + + `include "src/block_3_bench_sequence_base.svh" + `include "src/register_test_sequence.svh" + `include "src/example_derived_test_sequence.svh" + + // pragma uvmf custom package_item_additional begin + // UVMF_CHANGE_ME : When adding new sequences to the src directory + // be sure to add the sequence file here so that it will be + // compiled as part of the sequence package. Be sure to place + // the new sequence after any base sequences of the new sequence. + // pragma uvmf custom package_item_additional end + +endpackage + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/project_benches/block_3/tb/sequences/block_3_sequences_pkg.vinfo b/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/project_benches/block_3/tb/sequences/block_3_sequences_pkg.vinfo new file mode 100644 index 00000000..1e7146b0 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/project_benches/block_3/tb/sequences/block_3_sequences_pkg.vinfo @@ -0,0 +1,7 @@ +@use $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg.vinfo +@use $UVMF_VIP_LIBRARY_HOME/interface_packages/wb_m_pkg/wb_m_pkg.vinfo +@use $UVMF_VIP_LIBRARY_HOME/interface_packages/axi_s_pkg/axi_s_pkg.vinfo +@use $UVMF_VIP_LIBRARY_HOME/environment_packages/block_3_env_pkg/block_3_env_pkg.vinfo +@use $UVMF_PROJECT_DIR/tb/parameters/block_3_parameters_pkg.vinfo ++incdir+@vinfodir +block_3_sequences_pkg.sv diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/project_benches/block_3/tb/sequences/src/block_3_bench_sequence_base.svh b/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/project_benches/block_3/tb/sequences/src/block_3_bench_sequence_base.svh new file mode 100644 index 00000000..5a70a701 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/project_benches/block_3/tb/sequences/src/block_3_bench_sequence_base.svh @@ -0,0 +1,128 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// Description: This file contains the top level and utility sequences +// used by test_top. It can be extended to create derivative top +// level sequences. +// +//---------------------------------------------------------------------- +// +//---------------------------------------------------------------------- +// + + +typedef block_3_env_configuration block_3_env_configuration_t; + +class block_3_bench_sequence_base extends uvmf_sequence_base #(uvm_sequence_item); + + `uvm_object_utils( block_3_bench_sequence_base ); + + // pragma uvmf custom sequences begin + +typedef block_3_env_sequence_base #( + .CONFIG_T(block_3_env_configuration_t) + ) + block_3_env_sequence_base_t; +rand block_3_env_sequence_base_t block_3_env_seq; + + + + // UVMF_CHANGE_ME : Instantiate, construct, and start sequences as needed to create stimulus scenarios. + // Instantiate sequences here + typedef wb_m_random_sequence wb_master_random_seq_t; + wb_master_random_seq_t wb_master_random_seq; + typedef axi_s_responder_sequence axi_slave_responder_seq_t; + axi_slave_responder_seq_t axi_slave_responder_seq; + // pragma uvmf custom sequences end + + // Sequencer handles for each active interface in the environment + typedef wb_m_transaction wb_master_transaction_t; + uvm_sequencer #(wb_master_transaction_t) wb_master_sequencer; + typedef axi_s_transaction axi_slave_transaction_t; + uvm_sequencer #(axi_slave_transaction_t) axi_slave_sequencer; + + + // Top level environment configuration handle + block_3_env_configuration_t top_configuration; + + // Configuration handles to access interface BFM's + wb_m_configuration wb_master_config; + axi_s_configuration axi_slave_config; + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + // **************************************************************************** + function new( string name = "" ); + super.new( name ); + // Retrieve the configuration handles from the uvm_config_db + + // Retrieve top level configuration handle + if ( !uvm_config_db#(block_3_env_configuration_t)::get(null,UVMF_CONFIGURATIONS, "TOP_ENV_CONFIG",top_configuration) ) begin + `uvm_info("CFG", "*** FATAL *** uvm_config_db::get can not find TOP_ENV_CONFIG. Are you using an older UVMF release than what was used to generate this bench?",UVM_NONE); + `uvm_fatal("CFG", "uvm_config_db#(block_3_env_configuration_t)::get cannot find resource TOP_ENV_CONFIG"); + end + + // Retrieve config handles for all agents + if( !uvm_config_db #( wb_m_configuration )::get( null , UVMF_CONFIGURATIONS , wb_master_BFM , wb_master_config ) ) + `uvm_fatal("CFG" , "uvm_config_db #( wb_m_configuration )::get cannot find resource wb_master_BFM" ) + if( !uvm_config_db #( axi_s_configuration )::get( null , UVMF_CONFIGURATIONS , axi_slave_BFM , axi_slave_config ) ) + `uvm_fatal("CFG" , "uvm_config_db #( axi_s_configuration )::get cannot find resource axi_slave_BFM" ) + + // Assign the sequencer handles from the handles within agent configurations + wb_master_sequencer = wb_master_config.get_sequencer(); + axi_slave_sequencer = axi_slave_config.get_sequencer(); + + + + // pragma uvmf custom new begin + // pragma uvmf custom new end + + endfunction + + // **************************************************************************** + virtual task body(); + // pragma uvmf custom body begin + + // Construct sequences here + + block_3_env_seq = block_3_env_sequence_base_t::type_id::create("block_3_env_seq"); + + wb_master_random_seq = wb_master_random_seq_t::type_id::create("wb_master_random_seq"); + axi_slave_responder_seq = axi_slave_responder_seq_t::type_id::create("axi_slave_responder_seq"); + fork + wb_master_config.wait_for_reset(); + axi_slave_config.wait_for_reset(); + join + // Start RESPONDER sequences here + fork + axi_slave_responder_seq.start(axi_slave_sequencer); + join_none + // Start INITIATOR sequences here + fork + repeat (25) wb_master_random_seq.start(wb_master_sequencer); + join + +block_3_env_seq.start(top_configuration.vsqr); + + // UVMF_CHANGE_ME : Extend the simulation XXX number of clocks after + // the last sequence to allow for the last sequence item to flow + // through the design. + fork + wb_master_config.wait_for_num_clocks(400); + axi_slave_config.wait_for_num_clocks(400); + join + + // pragma uvmf custom body end + endtask + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/project_benches/block_3/tb/sequences/src/example_derived_test_sequence.svh b/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/project_benches/block_3/tb/sequences/src/example_derived_test_sequence.svh new file mode 100644 index 00000000..a97eb77b --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/project_benches/block_3/tb/sequences/src/example_derived_test_sequence.svh @@ -0,0 +1,30 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +// +//---------------------------------------------------------------------- +// +// DESCRIPTION: This file contains the top level sequence used in example_derived_test. +// It is an example of a sequence that is extended from %(benchName)_bench_sequence_base +// and can override %(benchName)_bench_sequence_base. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// + +class example_derived_test_sequence extends block_3_bench_sequence_base; + + `uvm_object_utils( example_derived_test_sequence ); + + function new(string name = "" ); + super.new(name); + endfunction + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/project_benches/block_3/tb/sequences/src/register_test_sequence.svh b/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/project_benches/block_3/tb/sequences/src/register_test_sequence.svh new file mode 100644 index 00000000..81a4e867 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/project_benches/block_3/tb/sequences/src/register_test_sequence.svh @@ -0,0 +1,57 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This file contains the top level sequence used in register_test. +// It uses the UVM built in register test. Specific UVM built-in tests can be +// selected in the body task. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// + +class register_test_sequence extends block_3_bench_sequence_base; + + `uvm_object_utils( register_test_sequence ); + + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + function new(string name = "" ); + super.new(name); + endfunction + + // **************************************************************************** + virtual task body(); + + // Reset the DUT + fork + // pragma uvmf custom register_test_reset begin + // UVMF_CHANGE_ME + // Select the desired wait_for_reset or provide custom mechanism. + // fork-join for this code block may be unnecessary based on your situation. + wb_master_config.wait_for_reset(); + axi_slave_config.wait_for_reset(); + // pragma uvmf custom register_test_reset end + join + + // pragma uvmf custom register_test_setup begin + // UVMF_CHANGE_ME perform potentially necessary operations before running the sequence. + // pragma uvmf custom register_test_setup end + + // pragma uvmf custom register_test_operation begin + // UVMF_CHANGE_ME Perform your custom register test + // pragma uvmf custom register_test_operation end + + endtask + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/project_benches/block_3/tb/testbench/hdl_top.compile b/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/project_benches/block_3/tb/testbench/hdl_top.compile new file mode 100644 index 00000000..e5040eb0 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/project_benches/block_3/tb/testbench/hdl_top.compile @@ -0,0 +1,10 @@ +incdir: + - ${uvm_path}/src + - . +needs: + - $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg_hdl.compile + - ../parameters/block_3_parameters_pkg.compile + - ../../../../verification_ip/interface_packages/wb_m_pkg/wb_m_hdl.compile + - ../../../../verification_ip/interface_packages/axi_s_pkg/axi_s_hdl.compile +src: + - hdl_top.sv diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/project_benches/block_3/tb/testbench/hdl_top.sv b/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/project_benches/block_3/tb/testbench/hdl_top.sv new file mode 100644 index 00000000..1f2599cb --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/project_benches/block_3/tb/testbench/hdl_top.sv @@ -0,0 +1,101 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// Description: This top level module instantiates all synthesizable +// static content. This and tb_top.sv are the two top level modules +// of the simulation. +// +// This module instantiates the following: +// DUT: The Design Under Test +// Interfaces: Signal bundles that contain signals connected to DUT +// Driver BFM's: BFM's that actively drive interface signals +// Monitor BFM's: BFM's that passively monitor interface signals +// +//---------------------------------------------------------------------- + +//---------------------------------------------------------------------- +// + +module hdl_top; + +import block_3_parameters_pkg::*; +import uvmf_base_pkg_hdl::*; + + // pragma attribute hdl_top partition_module_xrtl +// pragma uvmf custom clock_generator begin + bit clk; + // Instantiate a clk driver + // tbx clkgen + initial begin + clk = 0; + #9ns; + forever begin + clk = ~clk; + #5ns; + end + end +// pragma uvmf custom clock_generator end + +// pragma uvmf custom reset_generator begin + bit rst; + // Instantiate a rst driver + // tbx clkgen + initial begin + rst = 1; + #200ns; + rst = 0; + end +// pragma uvmf custom reset_generator end + + // pragma uvmf custom module_item_additional begin + // pragma uvmf custom module_item_additional end + + // Instantiate the signal bundle, monitor bfm and driver bfm for each interface. + // The signal bundle, _if, contains signals to be connected to the DUT. + // The monitor, monitor_bfm, observes the bus, _if, and captures transactions. + // The driver, driver_bfm, drives transactions onto the bus, _if. + wb_m_if wb_master_bus( + // pragma uvmf custom wb_master_bus_connections begin + .clock(clk), .reset(rst) + // pragma uvmf custom wb_master_bus_connections end + ); + axi_s_if axi_slave_bus( + // pragma uvmf custom axi_slave_bus_connections begin + .axi_clk(clk), .rst(rst) + // pragma uvmf custom axi_slave_bus_connections end + ); + wb_m_monitor_bfm wb_master_mon_bfm(wb_master_bus.monitor_port); + axi_s_monitor_bfm axi_slave_mon_bfm(axi_slave_bus.monitor_port); + wb_m_driver_bfm wb_master_drv_bfm(wb_master_bus.initiator_port); + axi_s_driver_bfm axi_slave_drv_bfm(axi_slave_bus.responder_port); + + // pragma uvmf custom dut_instantiation begin + // UVMF_CHANGE_ME : Add DUT and connect to signals in _bus interfaces listed above + // Instantiate your DUT here + // These DUT's instantiated to show verilog and vhdl instantiation + verilog_dut dut_verilog( .clk(clk), .rst(rst), .in_signal(vhdl_to_verilog_signal), .out_signal(verilog_to_vhdl_signal)); + vhdl_dut dut_vhdl ( .clk(clk), .rst(rst), .in_signal(verilog_to_vhdl_signal), .out_signal(vhdl_to_verilog_signal)); + // pragma uvmf custom dut_instantiation end + + initial begin // tbx vif_binding_block + import uvm_pkg::uvm_config_db; + // The monitor_bfm and driver_bfm for each interface is placed into the uvm_config_db. + // They are placed into the uvm_config_db using the string names defined in the parameters package. + // The string names are passed to the agent configurations by test_top through the top level configuration. + // They are retrieved by the agents configuration class for use by the agent. + uvm_config_db #( virtual wb_m_monitor_bfm )::set( null , UVMF_VIRTUAL_INTERFACES , wb_master_BFM , wb_master_mon_bfm ); + uvm_config_db #( virtual axi_s_monitor_bfm )::set( null , UVMF_VIRTUAL_INTERFACES , axi_slave_BFM , axi_slave_mon_bfm ); + uvm_config_db #( virtual wb_m_driver_bfm )::set( null , UVMF_VIRTUAL_INTERFACES , wb_master_BFM , wb_master_drv_bfm ); + uvm_config_db #( virtual axi_s_driver_bfm )::set( null , UVMF_VIRTUAL_INTERFACES , axi_slave_BFM , axi_slave_drv_bfm ); + end + +endmodule + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/project_benches/block_3/tb/testbench/hdl_top.vinfo b/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/project_benches/block_3/tb/testbench/hdl_top.vinfo new file mode 100644 index 00000000..881203b6 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/project_benches/block_3/tb/testbench/hdl_top.vinfo @@ -0,0 +1,6 @@ +@use $UVMF_PROJECT_DIR/rtl/verilog/verilog_dut.vinfo +@use $UVMF_PROJECT_DIR/tb/parameters/block_3_parameters_pkg.vinfo +@use $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg_hdl.vinfo +@use $UVMF_VIP_LIBRARY_HOME/interface_packages/wb_m_pkg/wb_m_bfm.vinfo +@use $UVMF_VIP_LIBRARY_HOME/interface_packages/axi_s_pkg/axi_s_bfm.vinfo +hdl_top.sv diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/project_benches/block_3/tb/testbench/hvl_top.compile b/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/project_benches/block_3/tb/testbench/hvl_top.compile new file mode 100644 index 00000000..d9bfbc86 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/project_benches/block_3/tb/testbench/hvl_top.compile @@ -0,0 +1,7 @@ +incdir: + - ${uvm_path}/src + - . +needs: + - ../tests/block_3_tests_pkg.compile +src: + - hvl_top.sv diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/project_benches/block_3/tb/testbench/hvl_top.sv b/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/project_benches/block_3/tb/testbench/hvl_top.sv new file mode 100644 index 00000000..785b6f37 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/project_benches/block_3/tb/testbench/hvl_top.sv @@ -0,0 +1,33 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +// +//---------------------------------------------------------------------- +// +// DESCRIPTION: This module loads the test package and starts the UVM phases. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// + +module hvl_top; + +import uvm_pkg::*; +import block_3_tests_pkg::*; + + // pragma uvmf custom module_item_additional begin + // pragma uvmf custom module_item_additional end + + initial begin + $timeformat(-9,3,"ns",5); + run_test(); + end + +endmodule + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/project_benches/block_3/tb/testbench/hvl_top.vinfo b/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/project_benches/block_3/tb/testbench/hvl_top.vinfo new file mode 100644 index 00000000..fe43bc9c --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/project_benches/block_3/tb/testbench/hvl_top.vinfo @@ -0,0 +1,2 @@ +@use $UVMF_PROJECT_DIR/tb/tests/block_3_tests_pkg.vinfo +hvl_top.sv diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/project_benches/block_3/tb/testbench/top_filelist_hdl.f b/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/project_benches/block_3/tb/testbench/top_filelist_hdl.f new file mode 100644 index 00000000..1e9dab65 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/project_benches/block_3/tb/testbench/top_filelist_hdl.f @@ -0,0 +1,3 @@ +$UVMF_PROJECT_DIR/tb/testbench/hdl_top.sv +// pragma uvmf custom additional begin +// pragma uvmf custom additional end diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/project_benches/block_3/tb/testbench/top_filelist_hvl.f b/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/project_benches/block_3/tb/testbench/top_filelist_hvl.f new file mode 100644 index 00000000..42383ab2 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/project_benches/block_3/tb/testbench/top_filelist_hvl.f @@ -0,0 +1,3 @@ +$UVMF_PROJECT_DIR/tb/testbench/hvl_top.sv +// pragma uvmf custom additional begin +// pragma uvmf custom additional end diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/project_benches/block_3/tb/tests/block_3_tests_pkg.compile b/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/project_benches/block_3/tb/tests/block_3_tests_pkg.compile new file mode 100644 index 00000000..344eca11 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/project_benches/block_3/tb/tests/block_3_tests_pkg.compile @@ -0,0 +1,9 @@ +needs: + - $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg.compile + - ../../../../verification_ip/interface_packages/wb_m_pkg/wb_m.compile + - ../../../../verification_ip/interface_packages/axi_s_pkg/axi_s.compile + - ../../../../verification_ip/environment_packages/block_3_env_pkg/block_3_env_pkg.compile + - ../parameters/block_3_parameters_pkg.compile + - ../sequences/block_3_sequences_pkg.compile +src: + - block_3_tests_pkg.sv diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/project_benches/block_3/tb/tests/block_3_tests_pkg.sv b/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/project_benches/block_3/tb/tests/block_3_tests_pkg.sv new file mode 100644 index 00000000..69d11784 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/project_benches/block_3/tb/tests/block_3_tests_pkg.sv @@ -0,0 +1,54 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This package contains all tests currently written for +// the simulation project. Once compiled, any test can be selected +// from the vsim command line using +UVM_TESTNAME=yourTestNameHere +// +// CONTAINS: +// - +// - +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// + +package block_3_tests_pkg; + + import uvm_pkg::*; + import uvmf_base_pkg::*; + import block_3_parameters_pkg::*; + import block_3_env_pkg::*; + import block_3_sequences_pkg::*; + import wb_m_pkg::*; + import wb_m_pkg_hdl::*; + import axi_s_pkg::*; + import axi_s_pkg_hdl::*; + + + `include "uvm_macros.svh" + + // pragma uvmf custom package_imports_additional begin + // pragma uvmf custom package_imports_additional end + + `include "src/test_top.svh" + `include "src/register_test.svh" + `include "src/example_derived_test.svh" + + // pragma uvmf custom package_item_additional begin + // UVMF_CHANGE_ME : When adding new tests to the src directory + // be sure to add the test file here so that it will be + // compiled as part of the test package. Be sure to place + // the new test after any base tests of the new test. + // pragma uvmf custom package_item_additional end + +endpackage + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/project_benches/block_3/tb/tests/block_3_tests_pkg.vinfo b/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/project_benches/block_3/tb/tests/block_3_tests_pkg.vinfo new file mode 100644 index 00000000..2fb6da4d --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/project_benches/block_3/tb/tests/block_3_tests_pkg.vinfo @@ -0,0 +1,8 @@ +@use $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg.vinfo +@use $UVMF_VIP_LIBRARY_HOME/interface_packages/wb_m_pkg/wb_m_pkg.vinfo +@use $UVMF_VIP_LIBRARY_HOME/interface_packages/axi_s_pkg/axi_s_pkg.vinfo +@use $UVMF_VIP_LIBRARY_HOME/environment_packages/block_3_env_pkg/block_3_env_pkg.vinfo +@use $UVMF_PROJECT_DIR/tb/parameters/block_3_parameters_pkg.vinfo +@use $UVMF_PROJECT_DIR/tb/sequences/block_3_sequences_pkg.vinfo ++incdir+@vinfodir +block_3_tests_pkg.sv diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/project_benches/block_3/tb/tests/src/example_derived_test.svh b/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/project_benches/block_3/tb/tests/src/example_derived_test.svh new file mode 100644 index 00000000..4638fe47 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/project_benches/block_3/tb/tests/src/example_derived_test.svh @@ -0,0 +1,43 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This test extends test_top and makes +// changes to test_top using the UVM factory type_override: +// +// Test scenario: +// This is a template test that can be used to create future tests. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// + +class example_derived_test extends test_top; + + `uvm_component_utils( example_derived_test ); + + function new( string name = "", uvm_component parent = null ); + super.new( name, parent ); + endfunction + + virtual function void build_phase(uvm_phase phase); + // The factory override below is an example of how to replace the block_3_bench_sequence_base + // sequence with the example_derived_test_sequence. + block_3_bench_sequence_base::type_id::set_type_override(example_derived_test_sequence::get_type()); + // Execute the build_phase of test_top AFTER all factory overrides have been created. + super.build_phase(phase); + // pragma uvmf custom configuration_settings_post_randomize begin + // UVMF_CHANGE_ME Test specific configuration values can be set here. + // The configuration structure has already been randomized. + // pragma uvmf custom configuration_settings_post_randomize end + endfunction + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/project_benches/block_3/tb/tests/src/register_test.svh b/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/project_benches/block_3/tb/tests/src/register_test.svh new file mode 100644 index 00000000..984802f0 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/project_benches/block_3/tb/tests/src/register_test.svh @@ -0,0 +1,40 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This test extends test_top and makes +// changes to test_top using the UVM factory type_override: +// +// Test scenario: +// This is a template test that can be used to create future tests. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// + +class register_test extends test_top; + + `uvm_component_utils( register_test ); + + function new( string name = "", uvm_component parent = null ); + super.new( name, parent ); + endfunction + + virtual function void build_phase(uvm_phase phase); + // The factory override below replaces the block_3_bench_sequence_base + // sequence with the register_test_sequence. + block_3_bench_sequence_base::type_id::set_type_override(register_test_sequence::get_type()); + // Execute the build_phase of test_top AFTER all factory overrides have been created. + super.build_phase(phase); + endfunction + + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/project_benches/block_3/tb/tests/src/test_top.svh b/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/project_benches/block_3/tb/tests/src/test_top.svh new file mode 100644 index 00000000..c62a6fe0 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/project_benches/block_3/tb/tests/src/test_top.svh @@ -0,0 +1,78 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// Description: This top level UVM test is the base class for all +// future tests created for this project. +// +// This test class contains: +// Configuration: The top level configuration for the project. +// Environment: The top level environment for the project. +// Top_level_sequence: The top level sequence for the project. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// + +typedef block_3_env_configuration block_3_env_configuration_t; +typedef block_3_environment block_3_environment_t; + +class test_top extends uvmf_test_base #(.CONFIG_T(block_3_env_configuration_t), + .ENV_T(block_3_environment_t), + .TOP_LEVEL_SEQ_T(block_3_bench_sequence_base)); + + `uvm_component_utils( test_top ); + + + + string interface_names[] = { + wb_master_BFM /* wb_master [0] */ , + axi_slave_BFM /* axi_slave [1] */ +}; + +uvmf_active_passive_t interface_activities[] = { + ACTIVE /* wb_master [0] */ , + ACTIVE /* axi_slave [1] */ }; + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + // **************************************************************************** + // FUNCTION: new() + // This is the standard systemVerilog constructor. All components are + // constructed in the build_phase to allow factory overriding. + // + function new( string name = "", uvm_component parent = null ); + super.new( name ,parent ); + endfunction + + + + // **************************************************************************** + // FUNCTION: build_phase() + // The construction of the configuration and environment classes is done in + // the build_phase of uvmf_test_base. Once the configuraton and environment + // classes are built then the initialize call is made to perform the + // following: + // Monitor and driver BFM virtual interface handle passing into agents + // Set the active/passive state for each agent + // Once this build_phase completes, the build_phase of the environment is + // executed which builds the agents. + // + virtual function void build_phase(uvm_phase phase); +// pragma uvmf custom build_phase_pre_super begin +// pragma uvmf custom build_phase_pre_super end + super.build_phase(phase); + // pragma uvmf custom configuration_settings_post_randomize begin + // pragma uvmf custom configuration_settings_post_randomize end + configuration.initialize(NA, "uvm_test_top.environment", interface_names, null, interface_activities); + endfunction + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/project_benches/block_3/yaml/block_3_bench.yaml b/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/project_benches/block_3/yaml/block_3_bench.yaml new file mode 100644 index 00000000..385d405c --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/project_benches/block_3/yaml/block_3_bench.yaml @@ -0,0 +1,17 @@ +uvmf: + benches: + block_3: + active_passive: + - bfm_name: wb_master + value: ACTIVE + - bfm_name: axi_slave + value: ACTIVE + active_passive_default: ACTIVE + clock_half_period: 5ns + clock_phase_offset: 9ns + existing_library_component: 'True' + interface_params: [] + reset_assertion_level: 'True' + reset_duration: 200ns + top_env: block_3 + use_dpi_link: 'False' diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/verification_ip/environment_packages/block_3_env_pkg/.project b/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/verification_ip/environment_packages/block_3_env_pkg/.project new file mode 100644 index 00000000..2bda5dd2 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/verification_ip/environment_packages/block_3_env_pkg/.project @@ -0,0 +1,32 @@ + + + block_3_env_pkg + + + + + + org.python.pydev.PyDevBuilder + + + + + net.sf.sveditor.core.SVProjectBuilder + + + + + + net.sf.sveditor.core.SVNature + org.python.pydev.pythonNature + + + + + + UVMF_VIP_LIBRARY_HOME + $%7BPARENT-2-PROJECT_LOC%7D + + + + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/verification_ip/environment_packages/block_3_env_pkg/.svproject b/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/verification_ip/environment_packages/block_3_env_pkg/.svproject new file mode 100644 index 00000000..62b5e4b4 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/verification_ip/environment_packages/block_3_env_pkg/.svproject @@ -0,0 +1,16 @@ + + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/verification_ip/environment_packages/block_3_env_pkg/Makefile b/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/verification_ip/environment_packages/block_3_env_pkg/Makefile new file mode 100644 index 00000000..945868c5 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/verification_ip/environment_packages/block_3_env_pkg/Makefile @@ -0,0 +1,56 @@ +# block_3 environment packages source and make target + +# pragma uvmf custom additional begin +# pragma uvmf custom additional end + +# Include all requisite sub-environment package targets for this bench + +block_3_ENV_PKG =\ + $(UVMF_VIP_LIBRARY_HOME)/environment_packages/block_3_env_pkg/block_3_env_pkg.sv + +COMP_block_3_PKG_TGT_0 = q_comp_block_3_env_pkg +COMP_block_3_PKG_TGT_1 = v_comp_block_3_env_pkg +COMP_block_3_PKG_TGT = $(COMP_block_3_PKG_TGT_$(USE_VELOCE)) + +comp_block_3_env_pkg: $(COMP_block_3_PKG_TGT) + +q_comp_block_3_env_pkg: + $(HVL_COMP_CMD) +incdir+$(UVMF_VIP_LIBRARY_HOME)/environment_packages/block_3_env_pkg $(block_3_ENV_PKG) + +v_comp_block_3_env_pkg: q_comp_block_3_env_pkg + $(VELANALYZE_HVL_CMD) +incdir+$(UVMF_VIP_LIBRARY_HOME)/environment_packages/block_3_env_pkg $(block_3_ENV_PKG) + + + +ifeq ($(MTI_VCO_MODE),64) + GCC_COMP_ARCH = -m64 +else + GCC_COMP_ARCH = -m32 +endif + +export block_3_ENV_DPI_SRC ?= $(UVMF_VIP_LIBRARY_HOME)/environment_packages/block_3_env_pkg/dpi + +C_FILE_COMPILE_LIST_block_3_env_pkg = \ + +O_FILE_COMPILE_LIST_block_3_env_pkg = $(notdir $(C_FILE_COMPILE_LIST_block_3_env_pkg:.c=.o)) + +GCC_COMP_ARGS_block_3_env_pkg += -I$(block_3_ENV_DPI_SRC) \ + -fPIC + +GCC_COMP_ARGS_block_3_env_pkg += $(block_3_ENV_GCC_COMP_ARGUMENTS) + +GCC_LINK_ARGS_block_3_env_pkg += \ + \ + -o .so + +comp_block_3_env_pkg_c_files: + @echo "--------------------------------" + @echo "Compiling Environment C source" + @echo "--------------------------------" + gcc $(GCC_COMP_ARCH) $(GCC_COMP_ARGS_block_3_env_pkg) $(C_FILE_COMPILE_LIST_block_3_env_pkg) + @echo "--------------------------------" + @echo "Linking Environment C objects into a shared object" + @echo "--------------------------------" + gcc $(GCC_COMP_ARCH) $(GCC_LINK_ARGS_block_3_env_pkg) $(O_FILE_COMPILE_LIST_block_3_env_pkg) + @echo "--------------------------------" + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/verification_ip/environment_packages/block_3_env_pkg/block_3_env_pkg.compile b/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/verification_ip/environment_packages/block_3_env_pkg/block_3_env_pkg.compile new file mode 100644 index 00000000..67f11230 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/verification_ip/environment_packages/block_3_env_pkg/block_3_env_pkg.compile @@ -0,0 +1,8 @@ +needs: + - $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg.compile + - ../../../verification_ip/interface_packages/wb_m_pkg/wb_m_hvl.compile + - ../../../verification_ip/interface_packages/axi_s_pkg/axi_s_hvl.compile + +src: + - block_3_env_pkg.sv + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/verification_ip/environment_packages/block_3_env_pkg/block_3_env_pkg.sv b/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/verification_ip/environment_packages/block_3_env_pkg/block_3_env_pkg.sv new file mode 100644 index 00000000..e4200aaf --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/verification_ip/environment_packages/block_3_env_pkg/block_3_env_pkg.sv @@ -0,0 +1,59 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// PACKAGE: This file defines all of the files contained in the +// environment package that will run on the host simulator. +// +// CONTAINS: +// - +// - +// - +// - +// - +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +package block_3_env_pkg; + + import uvm_pkg::*; + `include "uvm_macros.svh" + import uvmf_base_pkg::*; + import wb_m_pkg::*; + import wb_m_pkg_hdl::*; + import axi_s_pkg::*; + import axi_s_pkg_hdl::*; + + `uvm_analysis_imp_decl(_wb_ae) + `uvm_analysis_imp_decl(_sco_from_pre_ae) + `uvm_analysis_imp_decl(_axi_ae) + + // pragma uvmf custom package_imports_additional begin + // pragma uvmf custom package_imports_additional end + + // Parameters defined as HVL parameters + + `include "src/block_3_env_typedefs.svh" + `include "src/block_3_env_configuration.svh" + `include "src/block_3_predictor.svh" + `include "src/block_3_scoreboard.svh" + `include "src/block_3_environment.svh" + `include "src/block_3_env_sequence_base.svh" + + // pragma uvmf custom package_item_additional begin + // UVMF_CHANGE_ME : When adding new environment level sequences to the src directory + // be sure to add the sequence file here so that it will be + // compiled as part of the environment package. Be sure to place + // the new sequence after any base sequence of the new sequence. + // pragma uvmf custom package_item_additional end + +endpackage + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/verification_ip/environment_packages/block_3_env_pkg/block_3_env_pkg.vinfo b/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/verification_ip/environment_packages/block_3_env_pkg/block_3_env_pkg.vinfo new file mode 100644 index 00000000..ac8db6f3 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/verification_ip/environment_packages/block_3_env_pkg/block_3_env_pkg.vinfo @@ -0,0 +1,5 @@ +@use $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg.vinfo +@use $UVMF_VIP_LIBRARY_HOME/interface_packages/wb_m_pkg/wb_m_pkg.vinfo +@use $UVMF_VIP_LIBRARY_HOME/interface_packages/axi_s_pkg/axi_s_pkg.vinfo ++incdir+@vinfodir +block_3_env_pkg.sv diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/verification_ip/environment_packages/block_3_env_pkg/block_3_env_pkg_sve.F b/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/verification_ip/environment_packages/block_3_env_pkg/block_3_env_pkg_sve.F new file mode 100644 index 00000000..01f8db54 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/verification_ip/environment_packages/block_3_env_pkg/block_3_env_pkg_sve.F @@ -0,0 +1,12 @@ + +// UVM ++incdir+${UVM_HOME}/src +${UVM_HOME}/src/uvm_pkg.sv + +// Common UVMF files +-f ${UVMF_HOME}/common/common_sve.f + +// Sub-Environments + ++incdir+. +./block_3_env_pkg.sv diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/verification_ip/environment_packages/block_3_env_pkg/compile.do b/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/verification_ip/environment_packages/block_3_env_pkg/compile.do new file mode 100644 index 00000000..a35e5e59 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/verification_ip/environment_packages/block_3_env_pkg/compile.do @@ -0,0 +1,12 @@ +# Tcl do file for compile of block_3 interface + +# pragma uvmf custom additional begin +# pragma uvmf custom additional end + + + +quietly set cmd [format "vlog -timescale 1ps/1ps +incdir+%s/environment_packages/block_3_env_pkg" $env(UVMF_VIP_LIBRARY_HOME)] +quietly set cmd [format "%s %s/environment_packages/block_3_env_pkg/block_3_env_pkg.sv" $cmd $env(UVMF_VIP_LIBRARY_HOME)] +eval $cmd + + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/verification_ip/environment_packages/block_3_env_pkg/src/block_3_env_configuration.svh b/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/verification_ip/environment_packages/block_3_env_pkg/src/block_3_env_configuration.svh new file mode 100644 index 00000000..a08d0052 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/verification_ip/environment_packages/block_3_env_pkg/src/block_3_env_configuration.svh @@ -0,0 +1,146 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: THis is the configuration for the block_3 environment. +// it contains configuration classes for each agent. It also contains +// environment level configuration variables. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class block_3_env_configuration +extends uvmf_environment_configuration_base; + + `uvm_object_utils( block_3_env_configuration ) + + bit has_scoreboard; + +//Constraints for the configuration variables: + + + covergroup block_3_configuration_cg; + // pragma uvmf custom covergroup begin + option.auto_bin_max=1024; + coverpoint has_scoreboard; + // pragma uvmf custom covergroup end + endgroup + + + typedef wb_m_configuration wb_master_config_t; + rand wb_master_config_t wb_master_config; + + typedef axi_s_configuration axi_slave_config_t; + rand axi_slave_config_t axi_slave_config; + + + + + typedef uvmf_virtual_sequencer_base #(.CONFIG_T(block_3_env_configuration)) block_3_vsqr_t; + block_3_vsqr_t vsqr; + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + +// **************************************************************************** +// FUNCTION : new() +// This function is the standard SystemVerilog constructor. +// This function constructs the configuration object for each agent in the environment. +// + function new( string name = "" ); + super.new( name ); + + + wb_master_config = wb_master_config_t::type_id::create("wb_master_config"); + axi_slave_config = axi_slave_config_t::type_id::create("axi_slave_config"); + + + block_3_configuration_cg=new; + `uvm_warning("COVERAGE_MODEL_REVIEW", "A covergroup has been constructed which may need review because of either generation or re-generation with merging. Please note that configuration variables added as a result of re-generation and merging are not automatically added to the covergroup. Remove this warning after the covergroup has been reviewed.") + + // pragma uvmf custom new begin + // pragma uvmf custom new end + endfunction + +// **************************************************************************** +// FUNCTION : set_vsqr() +// This function is used to assign the vsqr handle. + virtual function void set_vsqr( block_3_vsqr_t vsqr); + this.vsqr = vsqr; + endfunction : set_vsqr + +// **************************************************************************** +// FUNCTION: post_randomize() +// This function is automatically called after the randomize() function +// is executed. +// + function void post_randomize(); + super.post_randomize(); + // pragma uvmf custom post_randomize begin + // pragma uvmf custom post_randomize end + endfunction + +// **************************************************************************** +// FUNCTION: convert2string() +// This function converts all variables in this class to a single string for +// logfile reporting. This function concatenates the convert2string result for +// each agent configuration in this configuration class. +// + virtual function string convert2string(); + // pragma uvmf custom convert2string begin + return { + $sformatf("has_scoreboard:0x%x ",has_scoreboard), + "\n", wb_master_config.convert2string, + "\n", axi_slave_config.convert2string + + + }; + // pragma uvmf custom convert2string end + endfunction +// **************************************************************************** +// FUNCTION: initialize(); +// This function configures each interface agents configuration class. The +// sim level determines the active/passive state of the agent. The environment_path +// identifies the hierarchy down to and including the instantiation name of the +// environment for this configuration class. Each instance of the environment +// has its own configuration class. The string interface names are used by +// the agent configurations to identify the virtual interface handle to pull from +// the uvm_config_db. +// + function void initialize(uvmf_sim_level_t sim_level, + string environment_path, + string interface_names[], + uvm_reg_block register_model = null, + uvmf_active_passive_t interface_activity[] = {} + ); + + super.initialize(sim_level, environment_path, interface_names, register_model, interface_activity); + + + + // Interface initialization for local agents + wb_master_config.initialize( interface_activity[0], {environment_path,".wb_master"}, interface_names[0]); + wb_master_config.initiator_responder = INITIATOR; + // wb_master_config.has_coverage = 1; + axi_slave_config.initialize( interface_activity[1], {environment_path,".axi_slave"}, interface_names[1]); + axi_slave_config.initiator_responder = RESPONDER; + // axi_slave_config.has_coverage = 1; + + + + + + // pragma uvmf custom initialize begin + // pragma uvmf custom initialize end + + endfunction + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/verification_ip/environment_packages/block_3_env_pkg/src/block_3_env_sequence_base.svh b/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/verification_ip/environment_packages/block_3_env_pkg/src/block_3_env_sequence_base.svh new file mode 100644 index 00000000..62b3b6d3 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/verification_ip/environment_packages/block_3_env_pkg/src/block_3_env_sequence_base.svh @@ -0,0 +1,69 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This file contains environment level sequences that will +// be reused from block to top level simulations. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class block_3_env_sequence_base #( + type CONFIG_T + ) extends uvmf_virtual_sequence_base #(.CONFIG_T(CONFIG_T)); + + + `uvm_object_param_utils( block_3_env_sequence_base #( + CONFIG_T + ) ); + + +// This block_3_env_sequence_base contains a handle to a block_3_env_configuration object +// named configuration. This configuration variable contains a handle to each +// sequencer within each agent within this environment and any sub-environments. +// The configuration object handle is automatically assigned in the pre_body in the +// base class of this sequence. The configuration handle is retrieved from the +// virtual sequencer that this sequence is started on. +// Available sequencer handles within the environment configuration: + + // Initiator agent sequencers in block_3_environment: + // configuration.wb_master_config.sequencer + + // Responder agent sequencers in block_3_environment: + // configuration.axi_slave_config.sequencer + + + typedef wb_m_random_sequence wb_master_random_sequence_t; + wb_master_random_sequence_t wb_master_rand_seq; + + + + + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + function new(string name = "" ); + super.new(name); + wb_master_rand_seq = wb_master_random_sequence_t::type_id::create("wb_master_rand_seq"); + + + endfunction + + virtual task body(); + + if ( configuration.wb_master_config.sequencer != null ) + repeat (25) wb_master_rand_seq.start(configuration.wb_master_config.sequencer); + + + endtask + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/verification_ip/environment_packages/block_3_env_pkg/src/block_3_env_typedefs.svh b/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/verification_ip/environment_packages/block_3_env_pkg/src/block_3_env_typedefs.svh new file mode 100644 index 00000000..9814bd58 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/verification_ip/environment_packages/block_3_env_pkg/src/block_3_env_typedefs.svh @@ -0,0 +1,20 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: +// This file contains defines and typedefs to be compiled for use in +// the environment package. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// + + + // pragma uvmf custom additional begin + // pragma uvmf custom additional end + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/verification_ip/environment_packages/block_3_env_pkg/src/block_3_environment.svh b/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/verification_ip/environment_packages/block_3_env_pkg/src/block_3_environment.svh new file mode 100644 index 00000000..48821376 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/verification_ip/environment_packages/block_3_env_pkg/src/block_3_environment.svh @@ -0,0 +1,127 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This environment contains all agents, predictors and +// scoreboards required for the block level design. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// + +class block_3_environment extends uvmf_environment_base #( + .CONFIG_T( block_3_env_configuration + )); + `uvm_component_utils( block_3_environment ) + + + + uvm_analysis_port #(wb_m_transaction) wb_master_ap; + uvm_analysis_port #(axi_s_transaction) axi_slave_ap; + + + typedef wb_m_agent wb_master_t; + wb_master_t wb_master; + + typedef axi_s_agent axi_slave_t; + axi_slave_t axi_slave; + + + + + typedef block_3_predictor #( + .CONFIG_T(CONFIG_T) + ) block_3_pred_t; + block_3_pred_t block_3_pred; + typedef block_3_scoreboard #( + .CONFIG_T(CONFIG_T) + ) block_3_sb_t; + block_3_sb_t block_3_sb; + + + + + typedef uvmf_virtual_sequencer_base #(.CONFIG_T(block_3_env_configuration)) block_3_vsqr_t; + block_3_vsqr_t vsqr; + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + +// **************************************************************************** +// FUNCTION : new() +// This function is the standard SystemVerilog constructor. +// + function new( string name = "", uvm_component parent = null ); + super.new( name, parent ); + endfunction + +// **************************************************************************** +// FUNCTION: build_phase() +// This function builds all components within this environment. +// + virtual function void build_phase(uvm_phase phase); +// pragma uvmf custom build_phase_pre_super begin +// pragma uvmf custom build_phase_pre_super end + super.build_phase(phase); + wb_master_ap = new("wb_master_ap",this); + axi_slave_ap = new("axi_slave_ap",this); + wb_master = wb_master_t::type_id::create("wb_master",this); + wb_master.set_config(configuration.wb_master_config); + axi_slave = axi_slave_t::type_id::create("axi_slave",this); + axi_slave.set_config(configuration.axi_slave_config); + block_3_pred = block_3_pred_t::type_id::create("block_3_pred",this); + block_3_pred.configuration = configuration; + block_3_sb = block_3_sb_t::type_id::create("block_3_sb",this); + block_3_sb.configuration = configuration; + + vsqr = block_3_vsqr_t::type_id::create("vsqr", this); + vsqr.set_config(configuration); + configuration.set_vsqr(vsqr); + + // pragma uvmf custom build_phase begin + // pragma uvmf custom build_phase end + endfunction + +// **************************************************************************** +// FUNCTION: connect_phase() +// This function makes all connections within this environment. Connections +// typically inclue agent to predictor, predictor to scoreboard and scoreboard +// to agent. +// + virtual function void connect_phase(uvm_phase phase); +// pragma uvmf custom connect_phase_pre_super begin +// pragma uvmf custom connect_phase_pre_super end + super.connect_phase(phase); + wb_master.monitored_ap.connect(block_3_pred.wb_ae); + axi_slave.monitored_ap.connect(block_3_sb.axi_ae); + block_3_pred.pre_to_sco_ap.connect(block_3_sb.sco_from_pre_ae); + wb_master.monitored_ap.connect(wb_master_ap); + axi_slave.monitored_ap.connect(axi_slave_ap); + // pragma uvmf custom reg_model_connect_phase begin + // pragma uvmf custom reg_model_connect_phase end + endfunction + +// **************************************************************************** +// FUNCTION: end_of_simulation_phase() +// This function is executed just prior to executing run_phase. This function +// was added to the environment to sample environment configuration settings +// just before the simulation exits time 0. The configuration structure is +// randomized in the build phase before the environment structure is constructed. +// Configuration variables can be customized after randomization in the build_phase +// of the extended test. +// If a sequence modifies values in the configuration structure then the sequence is +// responsible for sampling the covergroup in the configuration if required. +// + virtual function void start_of_simulation_phase(uvm_phase phase); + configuration.block_3_configuration_cg.sample(); + endfunction + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/verification_ip/environment_packages/block_3_env_pkg/src/block_3_predictor.svh b/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/verification_ip/environment_packages/block_3_env_pkg/src/block_3_predictor.svh new file mode 100644 index 00000000..a8a52695 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/verification_ip/environment_packages/block_3_env_pkg/src/block_3_predictor.svh @@ -0,0 +1,114 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +// +//---------------------------------------------------------------------- +// +// DESCRIPTION: This analysis component contains analysis_exports for receiving +// data and analysis_ports for sending data. +// +// This analysis component has the following analysis_exports that receive the +// listed transaction type. +// +// wb_ae receives transactions of type wb_m_transaction +// +// This analysis component has the following analysis_ports that can broadcast +// the listed transaction type. +// +// pre_to_sco_ap broadcasts transactions of type axi_s_transaction +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// + +class block_3_predictor #( + type CONFIG_T, + type BASE_T = uvm_component + ) extends BASE_T; + + // Factory registration of this class + `uvm_component_param_utils( block_3_predictor #( + CONFIG_T, + BASE_T + )) + + + // Instantiate a handle to the configuration of the environment in which this component resides + CONFIG_T configuration; + + + // Instantiate the analysis exports + uvm_analysis_imp_wb_ae #(wb_m_transaction, block_3_predictor #( + .CONFIG_T(CONFIG_T), + .BASE_T(BASE_T) + )) wb_ae; + + + // Instantiate the analysis ports + uvm_analysis_port #(axi_s_transaction) pre_to_sco_ap; + + + // Transaction variable for predicted values to be sent out pre_to_sco_ap + // Once a transaction is sent through an analysis_port, another transaction should + // be constructed for the next predicted transaction. + typedef axi_s_transaction pre_to_sco_ap_output_transaction_t; + pre_to_sco_ap_output_transaction_t pre_to_sco_ap_output_transaction; + // Code for sending output transaction out through pre_to_sco_ap + // pre_to_sco_ap.write(pre_to_sco_ap_output_transaction); + + // Define transaction handles for debug visibility + wb_m_transaction wb_ae_debug; + + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + // FUNCTION: new + function new(string name, uvm_component parent); + super.new(name,parent); + `uvm_warning("PREDICTOR_REVIEW", "This predictor has been created either through generation or re-generation with merging. Remove this warning after the predictor has been reviewed.") + // pragma uvmf custom new begin + // pragma uvmf custom new end + endfunction + + // FUNCTION: build_phase + virtual function void build_phase (uvm_phase phase); + + wb_ae = new("wb_ae", this); + pre_to_sco_ap =new("pre_to_sco_ap", this ); + // pragma uvmf custom build_phase begin + // pragma uvmf custom build_phase end + endfunction + + // FUNCTION: write_wb_ae + // Transactions received through wb_ae initiate the execution of this function. + // This function performs prediction of DUT output values based on DUT input, configuration and state + virtual function void write_wb_ae(wb_m_transaction t); + // pragma uvmf custom wb_ae_predictor begin + wb_ae_debug = t; + `uvm_info("PRED", "Transaction Received through wb_ae", UVM_MEDIUM) + `uvm_info("PRED", {" Data: ",t.convert2string()}, UVM_FULL) + // Construct one of each output transaction type. + pre_to_sco_ap_output_transaction = pre_to_sco_ap_output_transaction_t::type_id::create("pre_to_sco_ap_output_transaction"); + // UVMF_CHANGE_ME: Implement predictor model here. + `uvm_info("UNIMPLEMENTED_PREDICTOR_MODEL", "******************************************************************************************************",UVM_NONE) + `uvm_info("UNIMPLEMENTED_PREDICTOR_MODEL", "UVMF_CHANGE_ME: The block_3_predictor::write_wb_ae function needs to be completed with DUT prediction model",UVM_NONE) + `uvm_info("UNIMPLEMENTED_PREDICTOR_MODEL", "******************************************************************************************************",UVM_NONE) + + // Code for sending output transaction out through pre_to_sco_ap + // Please note that each broadcasted transaction should be a different object than previously + // broadcasted transactions. Creation of a different object is done by constructing the transaction + // using either new() or create(). Broadcasting a transaction object more than once to either the + // same subscriber or multiple subscribers will result in unexpected and incorrect behavior. + pre_to_sco_ap.write(pre_to_sco_ap_output_transaction); + // pragma uvmf custom wb_ae_predictor end + endfunction + + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/verification_ip/environment_packages/block_3_env_pkg/src/block_3_scoreboard.svh b/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/verification_ip/environment_packages/block_3_env_pkg/src/block_3_scoreboard.svh new file mode 100644 index 00000000..313c3505 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/verification_ip/environment_packages/block_3_env_pkg/src/block_3_scoreboard.svh @@ -0,0 +1,131 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This analysis component contains analysis_exports for receiving +// data and analysis_ports for sending data. +// +// This analysis component has the following analysis_exports that receive the +// listed transaction type. +// +// sco_from_pre_ae receives transactions of type axi_s_transaction +// axi_ae receives transactions of type axi_s_transaction +// +// This analysis component has the following analysis_ports that can broadcast +// the listed transaction type. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// + + +class block_3_scoreboard #( + type CONFIG_T, + type BASE_T = uvm_component + ) extends BASE_T; + + // Factory registration of this class + `uvm_component_param_utils( block_3_scoreboard #( + CONFIG_T, + BASE_T + )) + + + // Instantiate a handle to the configuration of the environment in which this component resides + CONFIG_T configuration; + + + // Instantiate the analysis exports + uvm_analysis_imp_sco_from_pre_ae #(axi_s_transaction, block_3_scoreboard #( + .CONFIG_T(CONFIG_T), + .BASE_T(BASE_T) + )) sco_from_pre_ae; + uvm_analysis_imp_axi_ae #(axi_s_transaction, block_3_scoreboard #( + .CONFIG_T(CONFIG_T), + .BASE_T(BASE_T) + )) axi_ae; + + + + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + // FUNCTION: new + function new(string name, uvm_component parent); + super.new(name,parent); + // pragma uvmf custom new begin + // pragma uvmf custom new end + endfunction + + // FUNCTION: build_phase + virtual function void build_phase (uvm_phase phase); + + sco_from_pre_ae = new("sco_from_pre_ae", this); + axi_ae = new("axi_ae", this); + // pragma uvmf custom build_phase begin + // pragma uvmf custom build_phase end + endfunction + + // FUNCTION: write_sco_from_pre_ae + // Transactions received through sco_from_pre_ae initiate the execution of this function. + // This function performs prediction of DUT output values based on DUT input, configuration and state + virtual function void write_sco_from_pre_ae(axi_s_transaction t); + // pragma uvmf custom sco_from_pre_ae_scoreboard begin + `uvm_info("PRED", "Transaction Received through sco_from_pre_ae", UVM_MEDIUM) + `uvm_info("PRED", {" Data: ",t.convert2string()}, UVM_FULL) + // UVMF_CHANGE_ME: Implement custom scoreboard here. + `uvm_info("UNIMPLEMENTED_CUSTOM_SCOREBOARD", "******************************************************************************************************",UVM_NONE) + `uvm_info("UNIMPLEMENTED_CUSTOM_SCOREBOARD", "UVMF_CHANGE_ME: The block_3_scoreboard::write_sco_from_pre_ae function needs to be completed with custom scoreboard functionality",UVM_NONE) + `uvm_info("UNIMPLEMENTED_CUSTOM_SCOREBOARD", "******************************************************************************************************",UVM_NONE) + + // pragma uvmf custom sco_from_pre_ae_scoreboard end + endfunction + + // FUNCTION: write_axi_ae + // Transactions received through axi_ae initiate the execution of this function. + // This function performs prediction of DUT output values based on DUT input, configuration and state + virtual function void write_axi_ae(axi_s_transaction t); + // pragma uvmf custom axi_ae_scoreboard begin + `uvm_info("PRED", "Transaction Received through axi_ae", UVM_MEDIUM) + `uvm_info("PRED", {" Data: ",t.convert2string()}, UVM_FULL) + // UVMF_CHANGE_ME: Implement custom scoreboard here. + `uvm_info("UNIMPLEMENTED_CUSTOM_SCOREBOARD", "******************************************************************************************************",UVM_NONE) + `uvm_info("UNIMPLEMENTED_CUSTOM_SCOREBOARD", "UVMF_CHANGE_ME: The block_3_scoreboard::write_axi_ae function needs to be completed with custom scoreboard functionality",UVM_NONE) + `uvm_info("UNIMPLEMENTED_CUSTOM_SCOREBOARD", "******************************************************************************************************",UVM_NONE) + + // pragma uvmf custom axi_ae_scoreboard end + endfunction + + + + // FUNCTION: extract_phase + virtual function void extract_phase(uvm_phase phase); +// pragma uvmf custom extract_phase begin + super.extract_phase(phase); +// pragma uvmf custom extract_phase end + endfunction + + // FUNCTION: check_phase + virtual function void check_phase(uvm_phase phase); +// pragma uvmf custom check_phase begin + super.check_phase(phase); +// pragma uvmf custom check_phase end + endfunction + + // FUNCTION: report_phase + virtual function void report_phase(uvm_phase phase); +// pragma uvmf custom report_phase begin + super.report_phase(phase); +// pragma uvmf custom report_phase end + endfunction + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/verification_ip/environment_packages/block_3_env_pkg/yaml/block_3_environment.yaml b/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/verification_ip/environment_packages/block_3_env_pkg/yaml/block_3_environment.yaml new file mode 100644 index 00000000..9bb7bd0d --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/verification_ip/environment_packages/block_3_env_pkg/yaml/block_3_environment.yaml @@ -0,0 +1,49 @@ +uvmf: + environments: + block_3: + agents: + - initiator_responder: INITIATOR + name: wb_master + type: wb_m + - initiator_responder: RESPONDER + name: axi_slave + type: axi_s + analysis_components: + - name: block_3_pred + parameters: [] + type: block_3_predictor + - name: block_3_sb + parameters: [] + type: block_3_scoreboard + analysis_exports: [] + analysis_ports: + - connected_to: wb_master.monitored_ap + name: wb_master_ap + trans_type: wb_m_transaction + - connected_to: axi_slave.monitored_ap + name: axi_slave_ap + trans_type: axi_s_transaction + config_constraints: [] + config_vars: + - comment: '' + isrand: 'False' + name: has_scoreboard + type: bit + value: '' + existing_library_component: 'True' + hvl_pkg_parameters: [] + non_uvmf_components: [] + parameters: [] + qvip_memory_agents: [] + scoreboards: [] + subenvs: [] + tlm_connections: + - driver: wb_master.monitored_ap + receiver: block_3_pred.wb_ae + validate: 'True' + - driver: axi_slave.monitored_ap + receiver: block_3_sb.axi_ae + validate: 'True' + - driver: block_3_pred.pre_to_sco_ap + receiver: block_3_sb.sco_from_pre_ae + validate: 'True' diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/verification_ip/environment_packages/block_3_env_pkg/yaml/block_3_util_comp_block_3_predictor.yaml b/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/verification_ip/environment_packages/block_3_env_pkg/yaml/block_3_util_comp_block_3_predictor.yaml new file mode 100644 index 00000000..f521bd67 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/verification_ip/environment_packages/block_3_env_pkg/yaml/block_3_util_comp_block_3_predictor.yaml @@ -0,0 +1,11 @@ +uvmf: + util_components: + block_3_predictor: + analysis_exports: + - name: wb_ae + type: wb_m_transaction + analysis_ports: + - name: pre_to_sco_ap + type: axi_s_transaction + existing_library_component: 'True' + type: predictor diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/verification_ip/environment_packages/block_3_env_pkg/yaml/block_3_util_comp_block_3_scoreboard.yaml b/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/verification_ip/environment_packages/block_3_env_pkg/yaml/block_3_util_comp_block_3_scoreboard.yaml new file mode 100644 index 00000000..79d8d7d2 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/verification_ip/environment_packages/block_3_env_pkg/yaml/block_3_util_comp_block_3_scoreboard.yaml @@ -0,0 +1,10 @@ +uvmf: + util_components: + block_3_scoreboard: + analysis_exports: + - name: sco_from_pre_ae + type: axi_s_transaction + - name: axi_ae + type: axi_s_transaction + existing_library_component: 'True' + type: scoreboard diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/verification_ip/interface_packages/axi_s_pkg/.project b/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/verification_ip/interface_packages/axi_s_pkg/.project new file mode 100644 index 00000000..009c04fc --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/verification_ip/interface_packages/axi_s_pkg/.project @@ -0,0 +1,30 @@ + + + axi_s_pkg + + + + + + org.python.pydev.PyDevBuilder + + + + + net.sf.sveditor.core.SVProjectBuilder + + + + + + net.sf.sveditor.core.SVNature + org.python.pydev.pythonNature + + + + UVMF_VIP_LIBRARY_HOME + $%7BPARENT-2-PROJECT_LOC%7D + + + + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/verification_ip/interface_packages/axi_s_pkg/.svproject b/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/verification_ip/interface_packages/axi_s_pkg/.svproject new file mode 100644 index 00000000..2f7c662b --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/verification_ip/interface_packages/axi_s_pkg/.svproject @@ -0,0 +1,16 @@ + + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/verification_ip/interface_packages/axi_s_pkg/Makefile b/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/verification_ip/interface_packages/axi_s_pkg/Makefile new file mode 100644 index 00000000..63d28f13 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/verification_ip/interface_packages/axi_s_pkg/Makefile @@ -0,0 +1,66 @@ +# axi_s interface packages source +# pragma uvmf custom additional begin +# pragma uvmf custom additional end + +axi_s_PKG = \ + +incdir+$(UVMF_VIP_LIBRARY_HOME)/interface_packages/axi_s_pkg \ + -F $(UVMF_VIP_LIBRARY_HOME)/interface_packages/axi_s_pkg/axi_s_filelist_hvl.f + +axi_s_PKG_HDL = \ + +incdir+$(UVMF_VIP_LIBRARY_HOME)/interface_packages/axi_s_pkg \ + -F $(UVMF_VIP_LIBRARY_HOME)/interface_packages/axi_s_pkg/axi_s_filelist_hdl.f + +axi_s_PKG_XRTL = \ + +incdir+$(UVMF_VIP_LIBRARY_HOME)/interface_packages/axi_s_pkg \ + -F $(UVMF_VIP_LIBRARY_HOME)/interface_packages/axi_s_pkg/axi_s_filelist_xrtl.f + +COMP_axi_s_PKG_TGT_0 = q_comp_axi_s_pkg +COMP_axi_s_PKG_TGT_1 = v_comp_axi_s_pkg +COMP_axi_s_PKG_TGT = $(COMP_axi_s_PKG_TGT_$(USE_VELOCE)) + +comp_axi_s_pkg: $(COMP_axi_s_PKG_TGT) + +q_comp_axi_s_pkg: + $(HDL_COMP_CMD) $(axi_s_PKG_HDL) + $(HVL_COMP_CMD) $(axi_s_PKG) + $(HDL_COMP_CMD) $(axi_s_PKG_XRTL) + +v_comp_axi_s_pkg: + $(HVL_COMP_CMD) $(axi_s_PKG_HDL) + $(HVL_COMP_CMD) $(axi_s_PKG) + $(VELANALYZE_CMD) $(axi_s_PKG_HDL) + $(VELANALYZE_HVL_CMD) $(axi_s_PKG) + $(HDL_COMP_CMD) $(axi_s_PKG_XRTL) + +ifeq ($(MTI_VCO_MODE),64) + GCC_COMP_ARCH = -m64 +else + GCC_COMP_ARCH = -m32 +endif + +export axi_s_IF_DPI_SRC ?= $(UVMF_VIP_LIBRARY_HOME)/interface_packages/axi_s_pkg/dpi + +C_FILE_COMPILE_LIST_axi_s_pkg = \ + +O_FILE_COMPILE_LIST_axi_s_pkg = $(notdir $(C_FILE_COMPILE_LIST_axi_s_pkg:.c=.o)) + +GCC_COMP_ARGS_axi_s_pkg += -I$(axi_s_IF_DPI_SRC) \ + -fPIC + +GCC_COMP_ARGS_axi_s_pkg += $(axi_s_IF_GCC_COMP_ARGUMENTS) + +GCC_LINK_ARGS_axi_s_pkg += \ + \ + -o .so + +comp_axi_s_pkg_c_files: + @echo "--------------------------------" + @echo "Compiling Interface C source" + @echo "--------------------------------" + gcc $(GCC_COMP_ARCH) $(GCC_COMP_ARGS_axi_s_pkg) $(C_FILE_COMPILE_LIST_axi_s_pkg) + @echo "--------------------------------" + @echo "Linking Interface C objects into a shared object" + @echo "--------------------------------" + gcc $(GCC_COMP_ARCH) $(GCC_LINK_ARGS_axi_s_pkg) $(O_FILE_COMPILE_LIST_axi_s_pkg) + @echo "--------------------------------" + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/verification_ip/interface_packages/axi_s_pkg/axi_s.compile b/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/verification_ip/interface_packages/axi_s_pkg/axi_s.compile new file mode 100644 index 00000000..96602b5a --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/verification_ip/interface_packages/axi_s_pkg/axi_s.compile @@ -0,0 +1,3 @@ +needs: + - axi_s_hvl.compile + - axi_s_hdl.compile diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/verification_ip/interface_packages/axi_s_pkg/axi_s_bfm.vinfo b/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/verification_ip/interface_packages/axi_s_pkg/axi_s_bfm.vinfo new file mode 100644 index 00000000..dc6f9acc --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/verification_ip/interface_packages/axi_s_pkg/axi_s_bfm.vinfo @@ -0,0 +1,6 @@ +@use $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg_hdl.vinfo +@use axi_s_pkg_hdl.vinfo ++incdir+@vinfodir +src/axi_s_if.sv +src/axi_s_driver_bfm.sv +src/axi_s_monitor_bfm.sv diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/verification_ip/interface_packages/axi_s_pkg/axi_s_common.compile b/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/verification_ip/interface_packages/axi_s_pkg/axi_s_common.compile new file mode 100644 index 00000000..cb7464be --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/verification_ip/interface_packages/axi_s_pkg/axi_s_common.compile @@ -0,0 +1,7 @@ +needs: + - $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg_hdl.compile +incdir: + - . + - ${uvm_path}/src +src: + - axi_s_pkg_hdl.sv diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/verification_ip/interface_packages/axi_s_pkg/axi_s_filelist_hdl.f b/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/verification_ip/interface_packages/axi_s_pkg/axi_s_filelist_hdl.f new file mode 100644 index 00000000..99d98e31 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/verification_ip/interface_packages/axi_s_pkg/axi_s_filelist_hdl.f @@ -0,0 +1 @@ +$UVMF_VIP_LIBRARY_HOME/interface_packages/axi_s_pkg/axi_s_pkg_hdl.sv diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/verification_ip/interface_packages/axi_s_pkg/axi_s_filelist_hvl.f b/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/verification_ip/interface_packages/axi_s_pkg/axi_s_filelist_hvl.f new file mode 100644 index 00000000..40ec1992 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/verification_ip/interface_packages/axi_s_pkg/axi_s_filelist_hvl.f @@ -0,0 +1 @@ +$UVMF_VIP_LIBRARY_HOME/interface_packages/axi_s_pkg/axi_s_pkg.sv \ No newline at end of file diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/verification_ip/interface_packages/axi_s_pkg/axi_s_filelist_xrtl.f b/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/verification_ip/interface_packages/axi_s_pkg/axi_s_filelist_xrtl.f new file mode 100644 index 00000000..d329ce6c --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/verification_ip/interface_packages/axi_s_pkg/axi_s_filelist_xrtl.f @@ -0,0 +1,3 @@ +$UVMF_VIP_LIBRARY_HOME/interface_packages/axi_s_pkg/src/axi_s_if.sv +$UVMF_VIP_LIBRARY_HOME/interface_packages/axi_s_pkg/src/axi_s_monitor_bfm.sv +$UVMF_VIP_LIBRARY_HOME/interface_packages/axi_s_pkg/src/axi_s_driver_bfm.sv diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/verification_ip/interface_packages/axi_s_pkg/axi_s_hdl.compile b/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/verification_ip/interface_packages/axi_s_pkg/axi_s_hdl.compile new file mode 100644 index 00000000..f5769a4f --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/verification_ip/interface_packages/axi_s_pkg/axi_s_hdl.compile @@ -0,0 +1,9 @@ +needs: + - $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg_hdl.compile + - ./axi_s_common.compile +incdir: + - . +src: + - src/axi_s_if.sv + - src/axi_s_monitor_bfm.sv + - src/axi_s_driver_bfm.sv diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/verification_ip/interface_packages/axi_s_pkg/axi_s_hvl.compile b/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/verification_ip/interface_packages/axi_s_pkg/axi_s_hvl.compile new file mode 100644 index 00000000..d65e6473 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/verification_ip/interface_packages/axi_s_pkg/axi_s_hvl.compile @@ -0,0 +1,7 @@ +needs: + - $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg.compile + - ./axi_s_common.compile +incdir: + - . +src: + - axi_s_pkg.sv diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/verification_ip/interface_packages/axi_s_pkg/axi_s_pkg.sv b/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/verification_ip/interface_packages/axi_s_pkg/axi_s_pkg.sv new file mode 100644 index 00000000..b699cccd --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/verification_ip/interface_packages/axi_s_pkg/axi_s_pkg.sv @@ -0,0 +1,77 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// PACKAGE: This file defines all of the files contained in the +// interface package that will run on the host simulator. +// +// CONTAINS: +// - +// - +// - + +// - +// - +// - + +// - +// - +// - + +// - +// - +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +package axi_s_pkg; + + import uvm_pkg::*; + import uvmf_base_pkg_hdl::*; + import uvmf_base_pkg::*; + import axi_s_pkg_hdl::*; + + `include "uvm_macros.svh" + + // pragma uvmf custom package_imports_additional begin + // pragma uvmf custom package_imports_additional end + `include "src/axi_s_macros.svh" + + export axi_s_pkg_hdl::*; + + + + // Parameters defined as HVL parameters + + `include "src/axi_s_typedefs.svh" + `include "src/axi_s_transaction.svh" + + `include "src/axi_s_configuration.svh" + `include "src/axi_s_driver.svh" + `include "src/axi_s_monitor.svh" + + `include "src/axi_s_transaction_coverage.svh" + `include "src/axi_s_sequence_base.svh" + `include "src/axi_s_random_sequence.svh" + + `include "src/axi_s_responder_sequence.svh" + `include "src/axi_s2reg_adapter.svh" + + `include "src/axi_s_agent.svh" + + // pragma uvmf custom package_item_additional begin + // UVMF_CHANGE_ME : When adding new interface sequences to the src directory + // be sure to add the sequence file here so that it will be + // compiled as part of the interface package. Be sure to place + // the new sequence after any base sequences of the new sequence. + // pragma uvmf custom package_item_additional end + +endpackage + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/verification_ip/interface_packages/axi_s_pkg/axi_s_pkg.vinfo b/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/verification_ip/interface_packages/axi_s_pkg/axi_s_pkg.vinfo new file mode 100644 index 00000000..4f79b005 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/verification_ip/interface_packages/axi_s_pkg/axi_s_pkg.vinfo @@ -0,0 +1,4 @@ +@use $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg.vinfo +@use axi_s_pkg_hdl.vinfo ++incdir+@vinfodir +axi_s_pkg.sv diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/verification_ip/interface_packages/axi_s_pkg/axi_s_pkg_hdl.sv b/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/verification_ip/interface_packages/axi_s_pkg/axi_s_pkg_hdl.sv new file mode 100644 index 00000000..67e47049 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/verification_ip/interface_packages/axi_s_pkg/axi_s_pkg_hdl.sv @@ -0,0 +1,38 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// PACKAGE: This file defines all of the files contained in the +// interface package that needs to be compiled and synthesized +// for running on Veloce. +// +// CONTAINS: +// - +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +package axi_s_pkg_hdl; + + import uvmf_base_pkg_hdl::*; + + // pragma uvmf custom package_imports_additional begin + // pragma uvmf custom package_imports_additional end + + // Parameters defined as HDL parameters + + `include "src/axi_s_typedefs_hdl.svh" + `include "src/axi_s_macros.svh" + + // pragma uvmf custom package_item_additional begin + // pragma uvmf custom package_item_additional end + +endpackage + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/verification_ip/interface_packages/axi_s_pkg/axi_s_pkg_hdl.vinfo b/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/verification_ip/interface_packages/axi_s_pkg/axi_s_pkg_hdl.vinfo new file mode 100644 index 00000000..62905353 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/verification_ip/interface_packages/axi_s_pkg/axi_s_pkg_hdl.vinfo @@ -0,0 +1,2 @@ +@use $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg_hdl.vinfo +axi_s_pkg_hdl.sv diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/verification_ip/interface_packages/axi_s_pkg/axi_s_pkg_sve.F b/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/verification_ip/interface_packages/axi_s_pkg/axi_s_pkg_sve.F new file mode 100644 index 00000000..13538815 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/verification_ip/interface_packages/axi_s_pkg/axi_s_pkg_sve.F @@ -0,0 +1,10 @@ +// UVM ++incdir+${UVM_HOME}/src +${UVM_HOME}/src/uvm_pkg.sv + +// Common UVMF files +-f ${UVMF_HOME}/common/common_sve.f + ++incdir+. +-f ${UVMF_VIP_LIBRARY_HOME}/interface_packages/axi_s_pkg/axi_s_filelist_hdl.f +-f ${UVMF_VIP_LIBRARY_HOME}/interface_packages/axi_s_pkg/axi_s_filelist_hvl.f diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/verification_ip/interface_packages/axi_s_pkg/compile.do b/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/verification_ip/interface_packages/axi_s_pkg/compile.do new file mode 100644 index 00000000..6a9b5a78 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/verification_ip/interface_packages/axi_s_pkg/compile.do @@ -0,0 +1,14 @@ +# Tcl do file for compile of axi_s interface + +# pragma uvmf custom additional begin +# pragma uvmf custom additional end + + +vlog -sv -timescale 1ps/1ps -suppress 2223,2286 +incdir+$env(UVMF_VIP_LIBRARY_HOME)/interface_packages/axi_s_pkg \ + -F $env(UVMF_VIP_LIBRARY_HOME)/interface_packages/axi_s_pkg/axi_s_filelist_hdl.f + +vlog -sv -timescale 1ps/1ps -suppress 2223,2286 +incdir+$env(UVMF_VIP_LIBRARY_HOME)/interface_packages/axi_s_pkg \ + -F $env(UVMF_VIP_LIBRARY_HOME)/interface_packages/axi_s_pkg/axi_s_filelist_hvl.f + +vlog -sv -timescale 1ps/1ps -suppress 2223,2286 +incdir+$env(UVMF_VIP_LIBRARY_HOME)/interface_packages/axi_s_pkg \ + -F $env(UVMF_VIP_LIBRARY_HOME)/interface_packages/axi_s_pkg/axi_s_filelist_xrtl.f \ No newline at end of file diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/verification_ip/interface_packages/axi_s_pkg/src/axi_s2reg_adapter.svh b/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/verification_ip/interface_packages/axi_s_pkg/src/axi_s2reg_adapter.svh new file mode 100644 index 00000000..fc6ac9bf --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/verification_ip/interface_packages/axi_s_pkg/src/axi_s2reg_adapter.svh @@ -0,0 +1,123 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: +// This file contains the UVM register adapter for the axi_s interface. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class axi_s2reg_adapter #( + int AW_WIDTH = 32, + int LEN = 8, + int DATA_WIDTH = 32, + int X = 16 + ) extends uvm_reg_adapter; + + `uvm_object_param_utils( axi_s2reg_adapter #( + AW_WIDTH, + LEN, + DATA_WIDTH, + X + )) + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + //-------------------------------------------------------------------- + // new + //-------------------------------------------------------------------- + function new (string name = "axi_s2reg_adapter" ); + super.new(name); + // pragma uvmf custom new begin + // UVMF_CHANGE_ME : Configure the adapter regarding byte enables and provides response. + + // Does the protocol the Agent is modeling support byte enables? + // 0 = NO + // 1 = YES + supports_byte_enable = 0; + + // Does the Agent's Driver provide separate response sequence items? + // i.e. Does the driver call seq_item_port.put() + // and do the sequences call get_response()? + // 0 = NO + // 1 = YES + provides_responses = 0; + // pragma uvmf custom new end + + endfunction: new + + //-------------------------------------------------------------------- + // reg2bus + //-------------------------------------------------------------------- + virtual function uvm_sequence_item reg2bus(const ref uvm_reg_bus_op rw); + + axi_s_transaction #( + .AW_WIDTH(AW_WIDTH), + .LEN(LEN), + .DATA_WIDTH(DATA_WIDTH), + .X(X) + ) trans_h = axi_s_transaction #( + .AW_WIDTH(AW_WIDTH), + .LEN(LEN), + .DATA_WIDTH(DATA_WIDTH), + .X(X) + )::type_id::create("trans_h"); + + // pragma uvmf custom reg2bus begin + // UVMF_CHANGE_ME : Fill in the reg2bus adapter mapping registe fields to protocol fields. + + //Adapt the following for your sequence item type + // trans_h.op = (rw.kind == UVM_READ) ? WB_READ : WB_WRITE; + //Copy over address + // trans_h.addr = rw.addr; + //Copy over write data + // trans_h.data = rw.data; + + // pragma uvmf custom reg2bus end + + // Return the adapted transaction + return trans_h; + + endfunction: reg2bus + + //-------------------------------------------------------------------- + // bus2reg + //-------------------------------------------------------------------- + virtual function void bus2reg(uvm_sequence_item bus_item, + ref uvm_reg_bus_op rw); + axi_s_transaction #( + .AW_WIDTH(AW_WIDTH), + .LEN(LEN), + .DATA_WIDTH(DATA_WIDTH), + .X(X) + ) trans_h; + if (!$cast(trans_h, bus_item)) begin + `uvm_fatal("ADAPT","Provided bus_item is not of the correct type") + return; + end + // pragma uvmf custom bus2reg begin + // UVMF_CHANGE_ME : Fill in the bus2reg adapter mapping protocol fields to register fields. + //Adapt the following for your sequence item type + //Copy over instruction type + // rw.kind = (trans_h.op == WB_WRITE) ? UVM_WRITE : UVM_READ; + //Copy over address + // rw.addr = trans_h.addr; + //Copy over read data + // rw.data = trans_h.data; + //Check for errors on the bus and return UVM_NOT_OK if there is an error + // rw.status = UVM_IS_OK; + // pragma uvmf custom bus2reg end + + endfunction: bus2reg + +endclass : axi_s2reg_adapter + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/verification_ip/interface_packages/axi_s_pkg/src/axi_s_agent.svh b/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/verification_ip/interface_packages/axi_s_pkg/src/axi_s_agent.svh new file mode 100644 index 00000000..faf4da95 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/verification_ip/interface_packages/axi_s_pkg/src/axi_s_agent.svh @@ -0,0 +1,88 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: Protocol specific agent class definition +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class axi_s_agent #( + int AW_WIDTH = 32, + int LEN = 8, + int DATA_WIDTH = 32, + int X = 16 + ) extends uvmf_parameterized_agent #( + .CONFIG_T(axi_s_configuration #( + .AW_WIDTH(AW_WIDTH), + .LEN(LEN), + .DATA_WIDTH(DATA_WIDTH), + .X(X) + )), + .DRIVER_T(axi_s_driver #( + .AW_WIDTH(AW_WIDTH), + .LEN(LEN), + .DATA_WIDTH(DATA_WIDTH), + .X(X) + )), + .MONITOR_T(axi_s_monitor #( + .AW_WIDTH(AW_WIDTH), + .LEN(LEN), + .DATA_WIDTH(DATA_WIDTH), + .X(X) + )), + .COVERAGE_T(axi_s_transaction_coverage #( + .AW_WIDTH(AW_WIDTH), + .LEN(LEN), + .DATA_WIDTH(DATA_WIDTH), + .X(X) + )), + .TRANS_T(axi_s_transaction #( + .AW_WIDTH(AW_WIDTH), + .LEN(LEN), + .DATA_WIDTH(DATA_WIDTH), + .X(X) + )) + ); + + `uvm_component_param_utils( axi_s_agent #( + AW_WIDTH, + LEN, + DATA_WIDTH, + X + )) + +// pragma uvmf custom class_item_additional begin +// pragma uvmf custom class_item_additional end + +// **************************************************************************** +// FUNCTION : new() +// This function is the standard SystemVerilog constructor. +// + function new( string name = "", uvm_component parent = null ); + super.new( name, parent ); + endfunction + +// **************************************************************************** + // FUNCTION: build_phase + virtual function void build_phase(uvm_phase phase); +// pragma uvmf custom build_phase_pre_super begin +// pragma uvmf custom build_phase_pre_super end + super.build_phase(phase); + if (configuration.active_passive == ACTIVE) begin + // Place sequencer handle into configuration object + // so that it may be retrieved from configuration + // rather than using uvm_config_db + configuration.sequencer = this.sequencer; + end + endfunction + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/verification_ip/interface_packages/axi_s_pkg/src/axi_s_configuration.svh b/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/verification_ip/interface_packages/axi_s_pkg/src/axi_s_configuration.svh new file mode 100644 index 00000000..2bbcfc4a --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/verification_ip/interface_packages/axi_s_pkg/src/axi_s_configuration.svh @@ -0,0 +1,219 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This class contains all variables and functions used +// to configure the axi_s agent and its bfm's. It gets the +// bfm's from the uvm_config_db for use by the agent. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class axi_s_configuration #( + int AW_WIDTH = 32, + int LEN = 8, + int DATA_WIDTH = 32, + int X = 16 + ) extends uvmf_parameterized_agent_configuration_base #( + .DRIVER_BFM_BIND_T(virtual axi_s_driver_bfm #( + .AW_WIDTH(AW_WIDTH), + .LEN(LEN), + .DATA_WIDTH(DATA_WIDTH), + .X(X) + )), + .MONITOR_BFM_BIND_T( virtual axi_s_monitor_bfm #( + .AW_WIDTH(AW_WIDTH), + .LEN(LEN), + .DATA_WIDTH(DATA_WIDTH), + .X(X) + ))); + + `uvm_object_param_utils( axi_s_configuration #( + AW_WIDTH, + LEN, + DATA_WIDTH, + X + )) + + + // Sequencer handle populated by agent + uvm_sequencer #(axi_s_transaction #( + .AW_WIDTH(AW_WIDTH), + .LEN(LEN), + .DATA_WIDTH(DATA_WIDTH), + .X(X) + ) ) sequencer; + + //Constraints for the configuration variables: + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + covergroup axi_s_configuration_cg; + // pragma uvmf custom covergroup begin + option.auto_bin_max=1024; + // pragma uvmf custom covergroup end + endgroup + + //******************************************************************* + //******************************************************************* + // Structure used to pass configuration variables to monitor and driver BFM's. + // Use to_struct function to pack variables into structure. + // Use from_struct function to unpack variables from structure. + // This structure is defined in axi_s_macros.svh + `axi_s_CONFIGURATION_STRUCT + axi_s_configuration_s axi_s_configuration_struct; + //******************************************************************* + // FUNCTION: to_struct() + // This function packs variables into a axi_s_configuration_s + // structure. The function returns the handle to the axi_s_configuration_struct. + // This function is defined in axi_s_macros.svh + `axi_s_CONFIGURATION_TO_STRUCT_FUNCTION + //******************************************************************* + // FUNCTION: from_struct() + // This function unpacks the struct provided as an argument into + // variables of this class. + // This function is defined in axi_s_macros.svh + `axi_s_CONFIGURATION_FROM_STRUCT_FUNCTION + + // **************************************************************************** + // FUNCTION : new() + // This function is the standard SystemVerilog constructor. + // + function new( string name = "" ); + super.new( name ); + // Construct the covergroup for this configuration class + axi_s_configuration_cg = new; + endfunction + + // **************************************************************************** + // FUNCTION: post_randomize() + // This function is automatically called after the randomize() function + // is executed. + // + function void post_randomize(); + super.post_randomize(); + axi_s_configuration_cg.sample(); + endfunction + + // **************************************************************************** + // FUNCTION: initialize + // This function causes the configuration to retrieve + // its virtual interface handle from the uvm_config_db. + // This function also makes itself available to its + // agent through the uvm_config_db. + // + // ARGUMENTS: + // uvmf_active_passive_t activity: + // This argument identifies the simulation level + // as either BLOCK, CHIP, SIMULATION, etc. + // + // AGENT_PATH: + // This argument identifies the path to this + // configurations agent. This configuration + // makes itself available to the agent specified + // by agent_path by placing itself into the + // uvm_config_db. + // + // INTERFACE_NAME: + // This argument identifies the string name of + // this configurations BFM's. This string + // name is used to retrieve the driver and + // monitor BFM from the uvm_config_db. + // + virtual function void initialize(uvmf_active_passive_t activity, + string agent_path, + string interface_name); + + super.initialize( activity, agent_path, interface_name); + // The covergroup is given the same name as the interface + axi_s_configuration_cg.set_inst_name(interface_name); + + // This configuration places itself into the uvm_config_db for the agent, identified by the agent_path variable, to retrieve. + uvm_config_db #( axi_s_configuration #( + .AW_WIDTH(AW_WIDTH), + .LEN(LEN), + .DATA_WIDTH(DATA_WIDTH), + .X(X) + ) + )::set( null ,agent_path,UVMF_AGENT_CONFIG, this ); + + // This configuration also places itself in the config db using the same identifier used by the interface. This allows users to access + // configuration variables and the interface through the bfm api class rather than directly accessing the BFM. This is useful for + // accessingthe BFM when using Veloce + uvm_config_db #( axi_s_configuration #( + .AW_WIDTH(AW_WIDTH), + .LEN(LEN), + .DATA_WIDTH(DATA_WIDTH), + .X(X) + ) + )::set( null ,UVMF_CONFIGURATIONS, interface_name, this ); + + axi_s_configuration_cg.set_inst_name($sformatf("axi_s_configuration_cg_%s",get_full_name())); + +// This code is to aid in debugging parameter mismatches between the BFM and its corresponding agent. +// Enable this debug by setting UVM_VERBOSITY to UVM_DEBUG +// Setting UVM_VERBOSITY to UVM_DEBUG causes all BFM's and all agents to display their parameter settings. +// All of the messages from this feature have a UVM messaging id value of "CFG" +// The transcript or run.log can be parsed to ensure BFM parameter settings match its corresponding agents parameter settings. + `uvm_info("CFG", + $psprintf("The agent at '%s' is using interface named %s has the following parameters: AW_WIDTH=%x LEN=%x DATA_WIDTH=%x X=%x ", agent_path, interface_name, AW_WIDTH ,LEN ,DATA_WIDTH ,X ), + UVM_DEBUG) + + // pragma uvmf custom initialize begin + // This controls whether or not the agent returns a transaction handle in the driver when calling + // item_done() back into the sequencer or not. If set to 1, a transaction is sent back which means + // the sequence on the other end must use the get_response() part of the driver/sequence API. If + // this doesn't occur, there will eventually be response_queue overflow errors during the test. + return_transaction_response = 1'b0; + + // pragma uvmf custom initialize end + + endfunction + + // **************************************************************************** + // TASK: wait_for_reset + // *[Required]* Blocks until reset is released. The wait_for_reset operation is performed + // by a task in the monitor bfm. + virtual task wait_for_reset(); + monitor_bfm.wait_for_reset(); + endtask + + // **************************************************************************** + // TASK: wait_for_num_clocks + // *[Required]* Blocks until specified number of clocks have elapsed. The wait_for_num_clocks + // operation is performed by a task in the monitor bfm. + virtual task wait_for_num_clocks(int clocks); + monitor_bfm.wait_for_num_clocks(clocks); + endtask + + // **************************************************************************** + // FUNCTION : convert2string() + // This function is used to convert variables in this class into a string for log messaging. + // + virtual function string convert2string (); + // pragma uvmf custom convert2string begin + return $sformatf(""); + // pragma uvmf custom convert2string end + endfunction + + // **************************************************************************** + // FUNCTION: get_sequencer + function uvm_sequencer #(axi_s_transaction#( + .AW_WIDTH(AW_WIDTH), + .LEN(LEN), + .DATA_WIDTH(DATA_WIDTH), + .X(X) + )) get_sequencer(); + return sequencer; + endfunction + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/verification_ip/interface_packages/axi_s_pkg/src/axi_s_driver.svh b/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/verification_ip/interface_packages/axi_s_pkg/src/axi_s_driver.svh new file mode 100644 index 00000000..7b6765cf --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/verification_ip/interface_packages/axi_s_pkg/src/axi_s_driver.svh @@ -0,0 +1,121 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This class passes transactions between the sequencer +// and the BFM driver interface. It accesses the driver BFM +// through the bfm handle. This driver +// passes transactions to the driver BFM through the access +// task. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class axi_s_driver #( + int AW_WIDTH = 32, + int LEN = 8, + int DATA_WIDTH = 32, + int X = 16 + ) extends uvmf_driver_base #( + .CONFIG_T(axi_s_configuration #( + .AW_WIDTH(AW_WIDTH), + .LEN(LEN), + .DATA_WIDTH(DATA_WIDTH), + .X(X) + ) ), + .BFM_BIND_T(virtual axi_s_driver_bfm #( + .AW_WIDTH(AW_WIDTH), + .LEN(LEN), + .DATA_WIDTH(DATA_WIDTH), + .X(X) + ) ), + .REQ(axi_s_transaction #( + .AW_WIDTH(AW_WIDTH), + .LEN(LEN), + .DATA_WIDTH(DATA_WIDTH), + .X(X) + ) ), + .RSP(axi_s_transaction #( + .AW_WIDTH(AW_WIDTH), + .LEN(LEN), + .DATA_WIDTH(DATA_WIDTH), + .X(X) + ) )); + + `uvm_component_param_utils( axi_s_driver #( + AW_WIDTH, + LEN, + DATA_WIDTH, + X + )) +//******************************************************************* +// Macros that define structs located in axi_s_macros.svh +//******************************************************************* +// Initiator macro used by axi_s_driver and axi_s_driver_bfm +// to communicate initiator driven data to axi_s_driver_bfm. +`axi_s_INITIATOR_STRUCT + axi_s_initiator_s axi_s_initiator_struct; +//******************************************************************* +// Responder macro used by axi_s_driver and axi_s_driver_bfm +// to communicate Responder driven data to axi_s_driver_bfm. +`axi_s_RESPONDER_STRUCT + axi_s_responder_s axi_s_responder_struct; + +// pragma uvmf custom class_item_additional begin +// pragma uvmf custom class_item_additional end + +// **************************************************************************** +// This function is the standard SystemVerilog constructor. +// + function new( string name = "", uvm_component parent=null ); + super.new( name, parent ); + endfunction + +// **************************************************************************** +// This function sends configuration object variables to the driver BFM +// using the configuration struct. +// + virtual function void configure(input CONFIG_T cfg); + bfm.configure( cfg.to_struct() ); + endfunction + +// **************************************************************************** +// This function places a handle to this class in the proxy variable in the +// driver BFM. This allows the driver BFM to call tasks and function within this class. +// + virtual function void set_bfm_proxy_handle(); + bfm.proxy = this; endfunction + +// **************************************************************************** +// This task is called by the run_phase in uvmf_driver_base. + virtual task access( inout REQ txn ); +// pragma uvmf custom access begin + if (configuration.initiator_responder==RESPONDER) begin + // Complete current transfer and wait for next transfer + bfm.respond_and_wait_for_next_transfer( + axi_s_initiator_struct, + txn.to_responder_struct() + ); + // Unpack information about initiated transfer received by this responder + txn.from_initiator_struct(axi_s_initiator_struct); + end else begin + // Initiate a transfer and get response + bfm.initiate_and_get_response( + txn.to_initiator_struct(), + axi_s_responder_struct + ); + // Unpack transfer response information received by this initiator + txn.from_responder_struct(axi_s_responder_struct); + end +// pragma uvmf custom access end + endtask + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/verification_ip/interface_packages/axi_s_pkg/src/axi_s_driver_bfm.sv b/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/verification_ip/interface_packages/axi_s_pkg/src/axi_s_driver_bfm.sv new file mode 100644 index 00000000..c2f44c62 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/verification_ip/interface_packages/axi_s_pkg/src/axi_s_driver_bfm.sv @@ -0,0 +1,765 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: +// This interface performs the axi_s signal driving. It is +// accessed by the uvm axi_s driver through a virtual interface +// handle in the axi_s configuration. It drives the singals passed +// in through the port connection named bus of type axi_s_if. +// +// Input signals from the axi_s_if are assigned to an internal input +// signal with a _i suffix. The _i signal should be used for sampling. +// +// The input signal connections are as follows: +// bus.signal -> signal_i +// +// This bfm drives signals with a _o suffix. These signals +// are driven onto signals within axi_s_if based on INITIATOR/RESPONDER and/or +// ARBITRATION/GRANT status. +// +// The output signal connections are as follows: +// signal_o -> bus.signal +// +// +// Interface functions and tasks used by UVM components: +// +// configure: +// This function gets configuration attributes from the +// UVM driver to set any required BFM configuration +// variables such as 'initiator_responder'. +// +// initiate_and_get_response: +// This task is used to perform signaling activity for initiating +// a protocol transfer. The task initiates the transfer, using +// input data from the initiator struct. Then the task captures +// response data, placing the data into the response struct. +// The response struct is returned to the driver class. +// +// respond_and_wait_for_next_transfer: +// This task is used to complete a current transfer as a responder +// and then wait for the initiator to start the next transfer. +// The task uses data in the responder struct to drive protocol +// signals to complete the transfer. The task then waits for +// the next transfer. Once the next transfer begins, data from +// the initiator is placed into the initiator struct and sent +// to the responder sequence for processing to determine +// what data to respond with. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +import uvmf_base_pkg_hdl::*; +import axi_s_pkg_hdl::*; +`include "src/axi_s_macros.svh" + +interface axi_s_driver_bfm #( + int AW_WIDTH = 32, + int LEN = 8, + int DATA_WIDTH = 32, + int X = 16 + ) + (axi_s_if bus); + // The following pragma and additional ones in-lined further below are for running this BFM on Veloce + // pragma attribute axi_s_driver_bfm partition_interface_xif + +`ifndef XRTL +// This code is to aid in debugging parameter mismatches between the BFM and its corresponding agent. +// Enable this debug by setting UVM_VERBOSITY to UVM_DEBUG +// Setting UVM_VERBOSITY to UVM_DEBUG causes all BFM's and all agents to display their parameter settings. +// All of the messages from this feature have a UVM messaging id value of "CFG" +// The transcript or run.log can be parsed to ensure BFM parameter settings match its corresponding agents parameter settings. +import uvm_pkg::*; +`include "uvm_macros.svh" +initial begin : bfm_vs_agent_parameter_debug + `uvm_info("CFG", + $psprintf("The BFM at '%m' has the following parameters: AW_WIDTH=%x LEN=%x DATA_WIDTH=%x X=%x ", AW_WIDTH,LEN,DATA_WIDTH,X), + UVM_DEBUG) +end +`endif + + // Config value to determine if this is an initiator or a responder + uvmf_initiator_responder_t initiator_responder; + // Custom configuration variables. + // These are set using the configure function which is called during the UVM connect_phase + + logic axi_clk_i; + logic rst_i; + + // Signal list (all signals are capable of being inputs and outputs for the sake + // of supporting both INITIATOR and RESPONDER mode operation. Expectation is that + // directionality in the config file was from the point-of-view of the INITIATOR + + // INITIATOR mode input signals + tri awvalid_i; + reg awvalid_o = 'bz; + tri [AW_WIDTH-1:0] awaddr_i; + reg [AW_WIDTH-1:0] awaddr_o = 'bz; + tri [2:0] awsize_i; + reg [2:0] awsize_o = 'bz; + tri [1:0] awburst_i; + reg [1:0] awburst_o = 'bz; + tri [3:0] awcache_i; + reg [3:0] awcache_o = 'bz; + tri [2:0] awprot_i; + reg [2:0] awprot_o = 'bz; + tri [X-1:0] awid_i; + reg [X-1:0] awid_o = 'bz; + tri [LEN-1:0] awlen_i; + reg [LEN-1:0] awlen_o = 'bz; + tri awlock_i; + reg awlock_o = 'bz; + tri [3:0] awqos_i; + reg [3:0] awqos_o = 'bz; + tri [3:0] awregion_i; + reg [3:0] awregion_o = 'bz; + tri [X-1:0] awuser_i; + reg [X-1:0] awuser_o = 'bz; + tri wvalid_i; + reg wvalid_o = 'bz; + tri wlast_i; + reg wlast_o = 'bz; + tri [DATA_WIDTH-1:0] wdata_i; + reg [DATA_WIDTH-1:0] wdata_o = 'bz; + tri [DATA_WIDTH/8-1:0] wstrb_i; + reg [DATA_WIDTH/8-1:0] wstrb_o = 'bz; + tri [X-1:0] wid_i; + reg [X-1:0] wid_o = 'bz; + tri [X-1:0] wuser_i; + reg [X-1:0] wuser_o = 'bz; + tri [1:0] bresp_i; + reg [1:0] bresp_o = 'bz; + tri arvalid_i; + reg arvalid_o = 'bz; + tri [AW_WIDTH-1:0] araddr_i; + reg [AW_WIDTH-1:0] araddr_o = 'bz; + tri [2:0] arsize_i; + reg [2:0] arsize_o = 'bz; + tri [1:0] arburst_i; + reg [1:0] arburst_o = 'bz; + tri [3:0] arcache_i; + reg [3:0] arcache_o = 'bz; + tri [2:0] arprot_i; + reg [2:0] arprot_o = 'bz; + tri [X-1:0] arid_i; + reg [X-1:0] arid_o = 'bz; + tri [LEN-1:0] arlen_i; + reg [LEN-1:0] arlen_o = 'bz; + tri arlock_i; + reg arlock_o = 'bz; + tri [3:0] arqos_i; + reg [3:0] arqos_o = 'bz; + tri [3:0] aregion_i; + reg [3:0] aregion_o = 'bz; + tri [X-1:0] aruser_i; + reg [X-1:0] aruser_o = 'bz; + tri rready_i; + reg rready_o = 'bz; + + // INITIATOR mode output signals + tri awready_i; + reg awready_o = 'bz; + tri wready_i; + reg wready_o = 'bz; + tri bwvalid_i; + reg bwvalid_o = 'bz; + tri bwready_i; + reg bwready_o = 'bz; + tri [X-1:0] bid_i; + reg [X-1:0] bid_o = 'bz; + tri [X-1:0] buser_i; + reg [X-1:0] buser_o = 'bz; + tri aready_i; + reg aready_o = 'bz; + tri rvalid_i; + reg rvalid_o = 'bz; + tri rlast_i; + reg rlast_o = 'bz; + tri [DATA_WIDTH-1:0] rdata_i; + reg [DATA_WIDTH-1:0] rdata_o = 'bz; + tri [X-1:0] rid_i; + reg [X-1:0] rid_o = 'bz; + tri [X-1:0] ruser_i; + reg [X-1:0] ruser_o = 'bz; + tri [1:0] rresp_i; + reg [1:0] rresp_o = 'bz; + + // Bi-directional signals + + + assign axi_clk_i = bus.axi_clk; + assign rst_i = bus.rst; + + // These are signals marked as 'input' by the config file, but the signals will be + // driven by this BFM if put into RESPONDER mode (flipping all signal directions around) + assign awvalid_i = bus.awvalid; + assign bus.awvalid = (initiator_responder == RESPONDER) ? awvalid_o : 'bz; + assign awaddr_i = bus.awaddr; + assign bus.awaddr = (initiator_responder == RESPONDER) ? awaddr_o : 'bz; + assign awsize_i = bus.awsize; + assign bus.awsize = (initiator_responder == RESPONDER) ? awsize_o : 'bz; + assign awburst_i = bus.awburst; + assign bus.awburst = (initiator_responder == RESPONDER) ? awburst_o : 'bz; + assign awcache_i = bus.awcache; + assign bus.awcache = (initiator_responder == RESPONDER) ? awcache_o : 'bz; + assign awprot_i = bus.awprot; + assign bus.awprot = (initiator_responder == RESPONDER) ? awprot_o : 'bz; + assign awid_i = bus.awid; + assign bus.awid = (initiator_responder == RESPONDER) ? awid_o : 'bz; + assign awlen_i = bus.awlen; + assign bus.awlen = (initiator_responder == RESPONDER) ? awlen_o : 'bz; + assign awlock_i = bus.awlock; + assign bus.awlock = (initiator_responder == RESPONDER) ? awlock_o : 'bz; + assign awqos_i = bus.awqos; + assign bus.awqos = (initiator_responder == RESPONDER) ? awqos_o : 'bz; + assign awregion_i = bus.awregion; + assign bus.awregion = (initiator_responder == RESPONDER) ? awregion_o : 'bz; + assign awuser_i = bus.awuser; + assign bus.awuser = (initiator_responder == RESPONDER) ? awuser_o : 'bz; + assign wvalid_i = bus.wvalid; + assign bus.wvalid = (initiator_responder == RESPONDER) ? wvalid_o : 'bz; + assign wlast_i = bus.wlast; + assign bus.wlast = (initiator_responder == RESPONDER) ? wlast_o : 'bz; + assign wdata_i = bus.wdata; + assign bus.wdata = (initiator_responder == RESPONDER) ? wdata_o : 'bz; + assign wstrb_i = bus.wstrb; + assign bus.wstrb = (initiator_responder == RESPONDER) ? wstrb_o : 'bz; + assign wid_i = bus.wid; + assign bus.wid = (initiator_responder == RESPONDER) ? wid_o : 'bz; + assign wuser_i = bus.wuser; + assign bus.wuser = (initiator_responder == RESPONDER) ? wuser_o : 'bz; + assign bresp_i = bus.bresp; + assign bus.bresp = (initiator_responder == RESPONDER) ? bresp_o : 'bz; + assign arvalid_i = bus.arvalid; + assign bus.arvalid = (initiator_responder == RESPONDER) ? arvalid_o : 'bz; + assign araddr_i = bus.araddr; + assign bus.araddr = (initiator_responder == RESPONDER) ? araddr_o : 'bz; + assign arsize_i = bus.arsize; + assign bus.arsize = (initiator_responder == RESPONDER) ? arsize_o : 'bz; + assign arburst_i = bus.arburst; + assign bus.arburst = (initiator_responder == RESPONDER) ? arburst_o : 'bz; + assign arcache_i = bus.arcache; + assign bus.arcache = (initiator_responder == RESPONDER) ? arcache_o : 'bz; + assign arprot_i = bus.arprot; + assign bus.arprot = (initiator_responder == RESPONDER) ? arprot_o : 'bz; + assign arid_i = bus.arid; + assign bus.arid = (initiator_responder == RESPONDER) ? arid_o : 'bz; + assign arlen_i = bus.arlen; + assign bus.arlen = (initiator_responder == RESPONDER) ? arlen_o : 'bz; + assign arlock_i = bus.arlock; + assign bus.arlock = (initiator_responder == RESPONDER) ? arlock_o : 'bz; + assign arqos_i = bus.arqos; + assign bus.arqos = (initiator_responder == RESPONDER) ? arqos_o : 'bz; + assign aregion_i = bus.aregion; + assign bus.aregion = (initiator_responder == RESPONDER) ? aregion_o : 'bz; + assign aruser_i = bus.aruser; + assign bus.aruser = (initiator_responder == RESPONDER) ? aruser_o : 'bz; + assign rready_i = bus.rready; + assign bus.rready = (initiator_responder == RESPONDER) ? rready_o : 'bz; + + + // These are signals marked as 'output' by the config file, but the outputs will + // not be driven by this BFM unless placed in INITIATOR mode. + assign bus.awready = (initiator_responder == INITIATOR) ? awready_o : 'bz; + assign awready_i = bus.awready; + assign bus.wready = (initiator_responder == INITIATOR) ? wready_o : 'bz; + assign wready_i = bus.wready; + assign bus.bwvalid = (initiator_responder == INITIATOR) ? bwvalid_o : 'bz; + assign bwvalid_i = bus.bwvalid; + assign bus.bwready = (initiator_responder == INITIATOR) ? bwready_o : 'bz; + assign bwready_i = bus.bwready; + assign bus.bid = (initiator_responder == INITIATOR) ? bid_o : 'bz; + assign bid_i = bus.bid; + assign bus.buser = (initiator_responder == INITIATOR) ? buser_o : 'bz; + assign buser_i = bus.buser; + assign bus.aready = (initiator_responder == INITIATOR) ? aready_o : 'bz; + assign aready_i = bus.aready; + assign bus.rvalid = (initiator_responder == INITIATOR) ? rvalid_o : 'bz; + assign rvalid_i = bus.rvalid; + assign bus.rlast = (initiator_responder == INITIATOR) ? rlast_o : 'bz; + assign rlast_i = bus.rlast; + assign bus.rdata = (initiator_responder == INITIATOR) ? rdata_o : 'bz; + assign rdata_i = bus.rdata; + assign bus.rid = (initiator_responder == INITIATOR) ? rid_o : 'bz; + assign rid_i = bus.rid; + assign bus.ruser = (initiator_responder == INITIATOR) ? ruser_o : 'bz; + assign ruser_i = bus.ruser; + assign bus.rresp = (initiator_responder == INITIATOR) ? rresp_o : 'bz; + assign rresp_i = bus.rresp; + + // Proxy handle to UVM driver + axi_s_pkg::axi_s_driver #( + .AW_WIDTH(AW_WIDTH), + .LEN(LEN), + .DATA_WIDTH(DATA_WIDTH), + .X(X) + ) proxy; + // pragma tbx oneway proxy.my_function_name_in_uvm_driver + + // **************************************************************************** + // **************************************************************************** + // Macros that define structs located in axi_s_macros.svh + // **************************************************************************** + // Struct for passing configuration data from axi_s_driver to this BFM + // **************************************************************************** + `axi_s_CONFIGURATION_STRUCT + // **************************************************************************** + // Structs for INITIATOR and RESPONDER data flow + //******************************************************************* + // Initiator macro used by axi_s_driver and axi_s_driver_bfm + // to communicate initiator driven data to axi_s_driver_bfm. + `axi_s_INITIATOR_STRUCT + axi_s_initiator_s initiator_struct; + // Responder macro used by axi_s_driver and axi_s_driver_bfm + // to communicate Responder driven data to axi_s_driver_bfm. + `axi_s_RESPONDER_STRUCT + axi_s_responder_s responder_struct; + + // **************************************************************************** +// pragma uvmf custom reset_condition_and_response begin + // Always block used to return signals to reset value upon assertion of reset + always @( negedge rst_i ) + begin + // RESPONDER mode output signals + awvalid_o <= 'bz; + awaddr_o <= 'bz; + awsize_o <= 'bz; + awburst_o <= 'bz; + awcache_o <= 'bz; + awprot_o <= 'bz; + awid_o <= 'bz; + awlen_o <= 'bz; + awlock_o <= 'bz; + awqos_o <= 'bz; + awregion_o <= 'bz; + awuser_o <= 'bz; + wvalid_o <= 'bz; + wlast_o <= 'bz; + wdata_o <= 'bz; + wstrb_o <= 'bz; + wid_o <= 'bz; + wuser_o <= 'bz; + bresp_o <= 'bz; + arvalid_o <= 'bz; + araddr_o <= 'bz; + arsize_o <= 'bz; + arburst_o <= 'bz; + arcache_o <= 'bz; + arprot_o <= 'bz; + arid_o <= 'bz; + arlen_o <= 'bz; + arlock_o <= 'bz; + arqos_o <= 'bz; + aregion_o <= 'bz; + aruser_o <= 'bz; + rready_o <= 'bz; + // INITIATOR mode output signals + awready_o <= 'bz; + wready_o <= 'bz; + bwvalid_o <= 'bz; + bwready_o <= 'bz; + bid_o <= 'bz; + buser_o <= 'bz; + aready_o <= 'bz; + rvalid_o <= 'bz; + rlast_o <= 'bz; + rdata_o <= 'bz; + rid_o <= 'bz; + ruser_o <= 'bz; + rresp_o <= 'bz; + // Bi-directional signals + + end +// pragma uvmf custom reset_condition_and_response end + + // pragma uvmf custom interface_item_additional begin + // pragma uvmf custom interface_item_additional end + + //****************************************************************** + // The configure() function is used to pass agent configuration + // variables to the driver BFM. It is called by the driver within + // the agent at the beginning of the simulation. It may be called + // during the simulation if agent configuration variables are updated + // and the driver BFM needs to be aware of the new configuration + // variables. + // + + function void configure(axi_s_configuration_s axi_s_configuration_arg); // pragma tbx xtf + initiator_responder = axi_s_configuration_arg.initiator_responder; + // pragma uvmf custom configure begin + // pragma uvmf custom configure end + endfunction + +// pragma uvmf custom initiate_and_get_response begin +// **************************************************************************** +// UVMF_CHANGE_ME +// This task is used by an initator. The task first initiates a transfer then +// waits for the responder to complete the transfer. + task initiate_and_get_response( + // This argument passes transaction variables used by an initiator + // to perform the initial part of a protocol transfer. The values + // come from a sequence item created in a sequence. + input axi_s_initiator_s axi_s_initiator_struct, + // This argument is used to send data received from the responder + // back to the sequence item. The sequence item is returned to the sequence. + output axi_s_responder_s axi_s_responder_struct + );// pragma tbx xtf + // + // Members within the axi_s_initiator_struct: + // bit awvalid ; + // bit awready ; + // bit [AW_WIDTH-1:0] awaddr ; + // bit awsize ; + // bit awburst ; + // bit awcache ; + // bit awprot ; + // bit [X-1:0] awid ; + // bit [LEN-1:0] awlen ; + // bit awlock ; + // bit awqos ; + // bit awregion ; + // bit [X-1:0] awuser ; + // bit wvalid ; + // bit wready ; + // bit wlast ; + // bit [DATA_WIDTH-1:0] wdata ; + // bit [DATA_WIDTH/8-1:0] wstrb ; + // bit [X-1:0] wid ; + // bit [X-1:0] wuser ; + // bit bwvalid ; + // bit bwready ; + // bit bresp ; + // bit [X-1:0] bid ; + // bit [X-1:0] buser ; + // bit arvalid ; + // bit aready ; + // bit [AW_WIDTH-1:0] araddr ; + // bit arsize ; + // bit arburst ; + // bit arcache ; + // bit arprot ; + // bit [X-1:0] arid ; + // bit [LEN-1:0] arlen ; + // bit arlock ; + // bit arqos ; + // bit aregion ; + // bit [X-1:0] aruser ; + // bit rvalid ; + // bit rready ; + // bit rlast ; + // bit [DATA_WIDTH-1:0] rdata ; + // bit [X-1:0] rid ; + // bit [X-1:0] ruser ; + // bit rresp ; + // Members within the axi_s_responder_struct: + // bit awvalid ; + // bit awready ; + // bit [AW_WIDTH-1:0] awaddr ; + // bit awsize ; + // bit awburst ; + // bit awcache ; + // bit awprot ; + // bit [X-1:0] awid ; + // bit [LEN-1:0] awlen ; + // bit awlock ; + // bit awqos ; + // bit awregion ; + // bit [X-1:0] awuser ; + // bit wvalid ; + // bit wready ; + // bit wlast ; + // bit [DATA_WIDTH-1:0] wdata ; + // bit [DATA_WIDTH/8-1:0] wstrb ; + // bit [X-1:0] wid ; + // bit [X-1:0] wuser ; + // bit bwvalid ; + // bit bwready ; + // bit bresp ; + // bit [X-1:0] bid ; + // bit [X-1:0] buser ; + // bit arvalid ; + // bit aready ; + // bit [AW_WIDTH-1:0] araddr ; + // bit arsize ; + // bit arburst ; + // bit arcache ; + // bit arprot ; + // bit [X-1:0] arid ; + // bit [LEN-1:0] arlen ; + // bit arlock ; + // bit arqos ; + // bit aregion ; + // bit [X-1:0] aruser ; + // bit rvalid ; + // bit rready ; + // bit rlast ; + // bit [DATA_WIDTH-1:0] rdata ; + // bit [X-1:0] rid ; + // bit [X-1:0] ruser ; + // bit rresp ; + initiator_struct = axi_s_initiator_struct; + // + // Reference code; + // How to wait for signal value + // while (control_signal == 1'b1) @(posedge axi_clk_i); + // + // How to assign a responder struct member, named xyz, from a signal. + // All available initiator input and inout signals listed. + // Initiator input signals + // axi_s_responder_struct.xyz = awvalid_i; // + // axi_s_responder_struct.xyz = awaddr_i; // [AW_WIDTH-1:0] + // axi_s_responder_struct.xyz = awsize_i; // [2:0] + // axi_s_responder_struct.xyz = awburst_i; // [1:0] + // axi_s_responder_struct.xyz = awcache_i; // [3:0] + // axi_s_responder_struct.xyz = awprot_i; // [2:0] + // axi_s_responder_struct.xyz = awid_i; // [X-1:0] + // axi_s_responder_struct.xyz = awlen_i; // [LEN-1:0] + // axi_s_responder_struct.xyz = awlock_i; // + // axi_s_responder_struct.xyz = awqos_i; // [3:0] + // axi_s_responder_struct.xyz = awregion_i; // [3:0] + // axi_s_responder_struct.xyz = awuser_i; // [X-1:0] + // axi_s_responder_struct.xyz = wvalid_i; // + // axi_s_responder_struct.xyz = wlast_i; // + // axi_s_responder_struct.xyz = wdata_i; // [DATA_WIDTH-1:0] + // axi_s_responder_struct.xyz = wstrb_i; // [DATA_WIDTH/8-1:0] + // axi_s_responder_struct.xyz = wid_i; // [X-1:0] + // axi_s_responder_struct.xyz = wuser_i; // [X-1:0] + // axi_s_responder_struct.xyz = bresp_i; // [1:0] + // axi_s_responder_struct.xyz = arvalid_i; // + // axi_s_responder_struct.xyz = araddr_i; // [AW_WIDTH-1:0] + // axi_s_responder_struct.xyz = arsize_i; // [2:0] + // axi_s_responder_struct.xyz = arburst_i; // [1:0] + // axi_s_responder_struct.xyz = arcache_i; // [3:0] + // axi_s_responder_struct.xyz = arprot_i; // [2:0] + // axi_s_responder_struct.xyz = arid_i; // [X-1:0] + // axi_s_responder_struct.xyz = arlen_i; // [LEN-1:0] + // axi_s_responder_struct.xyz = arlock_i; // + // axi_s_responder_struct.xyz = arqos_i; // [3:0] + // axi_s_responder_struct.xyz = aregion_i; // [3:0] + // axi_s_responder_struct.xyz = aruser_i; // [X-1:0] + // axi_s_responder_struct.xyz = rready_i; // + // Initiator inout signals + // How to assign a signal from an initiator struct member named xyz. + // All available initiator output and inout signals listed. + // Notice the _o. Those are storage variables that allow for procedural assignment. + // Initiator output signals + // awready_o <= axi_s_initiator_struct.xyz; // + // wready_o <= axi_s_initiator_struct.xyz; // + // bwvalid_o <= axi_s_initiator_struct.xyz; // + // bwready_o <= axi_s_initiator_struct.xyz; // + // bid_o <= axi_s_initiator_struct.xyz; // [X-1:0] + // buser_o <= axi_s_initiator_struct.xyz; // [X-1:0] + // aready_o <= axi_s_initiator_struct.xyz; // + // rvalid_o <= axi_s_initiator_struct.xyz; // + // rlast_o <= axi_s_initiator_struct.xyz; // + // rdata_o <= axi_s_initiator_struct.xyz; // [DATA_WIDTH-1:0] + // rid_o <= axi_s_initiator_struct.xyz; // [X-1:0] + // ruser_o <= axi_s_initiator_struct.xyz; // [X-1:0] + // rresp_o <= axi_s_initiator_struct.xyz; // [1:0] + // Initiator inout signals + // Initiate a transfer using the data received. + @(posedge axi_clk_i); + @(posedge axi_clk_i); + // Wait for the responder to complete the transfer then place the responder data into + // axi_s_responder_struct. + @(posedge axi_clk_i); + @(posedge axi_clk_i); + responder_struct = axi_s_responder_struct; + endtask +// pragma uvmf custom initiate_and_get_response end + +// pragma uvmf custom respond_and_wait_for_next_transfer begin +// **************************************************************************** +// The first_transfer variable is used to prevent completing a transfer in the +// first call to this task. For the first call to this task, there is not +// current transfer to complete. +bit first_transfer=1; + +// UVMF_CHANGE_ME +// This task is used by a responder. The task first completes the current +// transfer in progress then waits for the initiator to start the next transfer. + task respond_and_wait_for_next_transfer( + // This argument is used to send data received from the initiator + // back to the sequence item. The sequence determines how to respond. + output axi_s_initiator_s axi_s_initiator_struct, + // This argument passes transaction variables used by a responder + // to complete a protocol transfer. The values come from a sequence item. + input axi_s_responder_s axi_s_responder_struct + );// pragma tbx xtf + // Variables within the axi_s_initiator_struct: + // bit awvalid ; + // bit awready ; + // bit [AW_WIDTH-1:0] awaddr ; + // bit awsize ; + // bit awburst ; + // bit awcache ; + // bit awprot ; + // bit [X-1:0] awid ; + // bit [LEN-1:0] awlen ; + // bit awlock ; + // bit awqos ; + // bit awregion ; + // bit [X-1:0] awuser ; + // bit wvalid ; + // bit wready ; + // bit wlast ; + // bit [DATA_WIDTH-1:0] wdata ; + // bit [DATA_WIDTH/8-1:0] wstrb ; + // bit [X-1:0] wid ; + // bit [X-1:0] wuser ; + // bit bwvalid ; + // bit bwready ; + // bit bresp ; + // bit [X-1:0] bid ; + // bit [X-1:0] buser ; + // bit arvalid ; + // bit aready ; + // bit [AW_WIDTH-1:0] araddr ; + // bit arsize ; + // bit arburst ; + // bit arcache ; + // bit arprot ; + // bit [X-1:0] arid ; + // bit [LEN-1:0] arlen ; + // bit arlock ; + // bit arqos ; + // bit aregion ; + // bit [X-1:0] aruser ; + // bit rvalid ; + // bit rready ; + // bit rlast ; + // bit [DATA_WIDTH-1:0] rdata ; + // bit [X-1:0] rid ; + // bit [X-1:0] ruser ; + // bit rresp ; + // Variables within the axi_s_responder_struct: + // bit awvalid ; + // bit awready ; + // bit [AW_WIDTH-1:0] awaddr ; + // bit awsize ; + // bit awburst ; + // bit awcache ; + // bit awprot ; + // bit [X-1:0] awid ; + // bit [LEN-1:0] awlen ; + // bit awlock ; + // bit awqos ; + // bit awregion ; + // bit [X-1:0] awuser ; + // bit wvalid ; + // bit wready ; + // bit wlast ; + // bit [DATA_WIDTH-1:0] wdata ; + // bit [DATA_WIDTH/8-1:0] wstrb ; + // bit [X-1:0] wid ; + // bit [X-1:0] wuser ; + // bit bwvalid ; + // bit bwready ; + // bit bresp ; + // bit [X-1:0] bid ; + // bit [X-1:0] buser ; + // bit arvalid ; + // bit aready ; + // bit [AW_WIDTH-1:0] araddr ; + // bit arsize ; + // bit arburst ; + // bit arcache ; + // bit arprot ; + // bit [X-1:0] arid ; + // bit [LEN-1:0] arlen ; + // bit arlock ; + // bit arqos ; + // bit aregion ; + // bit [X-1:0] aruser ; + // bit rvalid ; + // bit rready ; + // bit rlast ; + // bit [DATA_WIDTH-1:0] rdata ; + // bit [X-1:0] rid ; + // bit [X-1:0] ruser ; + // bit rresp ; + // Reference code; + // How to wait for signal value + // while (control_signal == 1'b1) @(posedge axi_clk_i); + // + // How to assign a responder struct member, named xyz, from a signal. + // All available responder input and inout signals listed. + // Responder input signals + // axi_s_responder_struct.xyz = awready_i; // + // axi_s_responder_struct.xyz = wready_i; // + // axi_s_responder_struct.xyz = bwvalid_i; // + // axi_s_responder_struct.xyz = bwready_i; // + // axi_s_responder_struct.xyz = bid_i; // [X-1:0] + // axi_s_responder_struct.xyz = buser_i; // [X-1:0] + // axi_s_responder_struct.xyz = aready_i; // + // axi_s_responder_struct.xyz = rvalid_i; // + // axi_s_responder_struct.xyz = rlast_i; // + // axi_s_responder_struct.xyz = rdata_i; // [DATA_WIDTH-1:0] + // axi_s_responder_struct.xyz = rid_i; // [X-1:0] + // axi_s_responder_struct.xyz = ruser_i; // [X-1:0] + // axi_s_responder_struct.xyz = rresp_i; // [1:0] + // Responder inout signals + // How to assign a signal, named xyz, from an initiator struct member. + // All available responder output and inout signals listed. + // Notice the _o. Those are storage variables that allow for procedural assignment. + // Responder output signals + // awvalid_o <= axi_s_initiator_struct.xyz; // + // awaddr_o <= axi_s_initiator_struct.xyz; // [AW_WIDTH-1:0] + // awsize_o <= axi_s_initiator_struct.xyz; // [2:0] + // awburst_o <= axi_s_initiator_struct.xyz; // [1:0] + // awcache_o <= axi_s_initiator_struct.xyz; // [3:0] + // awprot_o <= axi_s_initiator_struct.xyz; // [2:0] + // awid_o <= axi_s_initiator_struct.xyz; // [X-1:0] + // awlen_o <= axi_s_initiator_struct.xyz; // [LEN-1:0] + // awlock_o <= axi_s_initiator_struct.xyz; // + // awqos_o <= axi_s_initiator_struct.xyz; // [3:0] + // awregion_o <= axi_s_initiator_struct.xyz; // [3:0] + // awuser_o <= axi_s_initiator_struct.xyz; // [X-1:0] + // wvalid_o <= axi_s_initiator_struct.xyz; // + // wlast_o <= axi_s_initiator_struct.xyz; // + // wdata_o <= axi_s_initiator_struct.xyz; // [DATA_WIDTH-1:0] + // wstrb_o <= axi_s_initiator_struct.xyz; // [DATA_WIDTH/8-1:0] + // wid_o <= axi_s_initiator_struct.xyz; // [X-1:0] + // wuser_o <= axi_s_initiator_struct.xyz; // [X-1:0] + // bresp_o <= axi_s_initiator_struct.xyz; // [1:0] + // arvalid_o <= axi_s_initiator_struct.xyz; // + // araddr_o <= axi_s_initiator_struct.xyz; // [AW_WIDTH-1:0] + // arsize_o <= axi_s_initiator_struct.xyz; // [2:0] + // arburst_o <= axi_s_initiator_struct.xyz; // [1:0] + // arcache_o <= axi_s_initiator_struct.xyz; // [3:0] + // arprot_o <= axi_s_initiator_struct.xyz; // [2:0] + // arid_o <= axi_s_initiator_struct.xyz; // [X-1:0] + // arlen_o <= axi_s_initiator_struct.xyz; // [LEN-1:0] + // arlock_o <= axi_s_initiator_struct.xyz; // + // arqos_o <= axi_s_initiator_struct.xyz; // [3:0] + // aregion_o <= axi_s_initiator_struct.xyz; // [3:0] + // aruser_o <= axi_s_initiator_struct.xyz; // [X-1:0] + // rready_o <= axi_s_initiator_struct.xyz; // + // Responder inout signals + + @(posedge axi_clk_i); + if (!first_transfer) begin + // Perform transfer response here. + // Reply using data recieved in the axi_s_responder_struct. + @(posedge axi_clk_i); + // Reply using data recieved in the transaction handle. + @(posedge axi_clk_i); + end + // Wait for next transfer then gather info from intiator about the transfer. + // Place the data into the axi_s_initiator_struct. + @(posedge axi_clk_i); + @(posedge axi_clk_i); + first_transfer = 0; + endtask +// pragma uvmf custom respond_and_wait_for_next_transfer end + + +endinterface + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/verification_ip/interface_packages/axi_s_pkg/src/axi_s_if.sv b/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/verification_ip/interface_packages/axi_s_pkg/src/axi_s_if.sv new file mode 100644 index 00000000..fcd5d49b --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/verification_ip/interface_packages/axi_s_pkg/src/axi_s_if.sv @@ -0,0 +1,289 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This interface contains the axi_s interface signals. +// It is instantiated once per axi_s bus. Bus Functional Models, +// BFM's named axi_s_driver_bfm, are used to drive signals on the bus. +// BFM's named axi_s_monitor_bfm are used to monitor signals on the +// bus. This interface signal bundle is passed in the port list of +// the BFM in order to give the BFM access to the signals in this +// interface. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// This template can be used to connect a DUT to these signals +// +// .dut_signal_port(axi_s_bus.awvalid), // Agent input +// .dut_signal_port(axi_s_bus.awready), // Agent output +// .dut_signal_port(axi_s_bus.awaddr), // Agent input +// .dut_signal_port(axi_s_bus.awsize), // Agent input +// .dut_signal_port(axi_s_bus.awburst), // Agent input +// .dut_signal_port(axi_s_bus.awcache), // Agent input +// .dut_signal_port(axi_s_bus.awprot), // Agent input +// .dut_signal_port(axi_s_bus.awid), // Agent input +// .dut_signal_port(axi_s_bus.awlen), // Agent input +// .dut_signal_port(axi_s_bus.awlock), // Agent input +// .dut_signal_port(axi_s_bus.awqos), // Agent input +// .dut_signal_port(axi_s_bus.awregion), // Agent input +// .dut_signal_port(axi_s_bus.awuser), // Agent input +// .dut_signal_port(axi_s_bus.wvalid), // Agent input +// .dut_signal_port(axi_s_bus.wready), // Agent output +// .dut_signal_port(axi_s_bus.wlast), // Agent input +// .dut_signal_port(axi_s_bus.wdata), // Agent input +// .dut_signal_port(axi_s_bus.wstrb), // Agent input +// .dut_signal_port(axi_s_bus.wid), // Agent input +// .dut_signal_port(axi_s_bus.wuser), // Agent input +// .dut_signal_port(axi_s_bus.bwvalid), // Agent output +// .dut_signal_port(axi_s_bus.bwready), // Agent output +// .dut_signal_port(axi_s_bus.bresp), // Agent input +// .dut_signal_port(axi_s_bus.bid), // Agent output +// .dut_signal_port(axi_s_bus.buser), // Agent output +// .dut_signal_port(axi_s_bus.arvalid), // Agent input +// .dut_signal_port(axi_s_bus.aready), // Agent output +// .dut_signal_port(axi_s_bus.araddr), // Agent input +// .dut_signal_port(axi_s_bus.arsize), // Agent input +// .dut_signal_port(axi_s_bus.arburst), // Agent input +// .dut_signal_port(axi_s_bus.arcache), // Agent input +// .dut_signal_port(axi_s_bus.arprot), // Agent input +// .dut_signal_port(axi_s_bus.arid), // Agent input +// .dut_signal_port(axi_s_bus.arlen), // Agent input +// .dut_signal_port(axi_s_bus.arlock), // Agent input +// .dut_signal_port(axi_s_bus.arqos), // Agent input +// .dut_signal_port(axi_s_bus.aregion), // Agent input +// .dut_signal_port(axi_s_bus.aruser), // Agent input +// .dut_signal_port(axi_s_bus.rvalid), // Agent output +// .dut_signal_port(axi_s_bus.rready), // Agent input +// .dut_signal_port(axi_s_bus.rlast), // Agent output +// .dut_signal_port(axi_s_bus.rdata), // Agent output +// .dut_signal_port(axi_s_bus.rid), // Agent output +// .dut_signal_port(axi_s_bus.ruser), // Agent output +// .dut_signal_port(axi_s_bus.rresp), // Agent output + +import uvmf_base_pkg_hdl::*; +import axi_s_pkg_hdl::*; + +interface axi_s_if #( + int AW_WIDTH = 32, + int LEN = 8, + int DATA_WIDTH = 32, + int X = 16 + ) + + ( + input logic axi_clk, + input logic rst, + input logic awvalid, + output logic awready, + input logic [AW_WIDTH-1:0] awaddr, + input logic [2:0] awsize, + input logic [1:0] awburst, + input logic [3:0] awcache, + input logic [2:0] awprot, + input logic [X-1:0] awid, + input logic [LEN-1:0] awlen, + input logic awlock, + input logic [3:0] awqos, + input logic [3:0] awregion, + input logic [X-1:0] awuser, + input logic wvalid, + output logic wready, + input logic wlast, + input logic [DATA_WIDTH-1:0] wdata, + input logic [DATA_WIDTH/8-1:0] wstrb, + input logic [X-1:0] wid, + input logic [X-1:0] wuser, + output logic bwvalid, + output logic bwready, + input logic [1:0] bresp, + output logic [X-1:0] bid, + output logic [X-1:0] buser, + input logic arvalid, + output logic aready, + input logic [AW_WIDTH-1:0] araddr, + input logic [2:0] arsize, + input logic [1:0] arburst, + input logic [3:0] arcache, + input logic [2:0] arprot, + input logic [X-1:0] arid, + input logic [LEN-1:0] arlen, + input logic arlock, + input logic [3:0] arqos, + input logic [3:0] aregion, + input logic [X-1:0] aruser, + output logic rvalid, + input logic rready, + output logic rlast, + output logic [DATA_WIDTH-1:0] rdata, + output logic [X-1:0] rid, + output logic [X-1:0] ruser, + output logic [1:0] rresp + ); + +modport monitor_port + ( + input axi_clk, + input rst, + input awvalid, + input awready, + input awaddr, + input awsize, + input awburst, + input awcache, + input awprot, + input awid, + input awlen, + input awlock, + input awqos, + input awregion, + input awuser, + input wvalid, + input wready, + input wlast, + input wdata, + input wstrb, + input wid, + input wuser, + input bwvalid, + input bwready, + input bresp, + input bid, + input buser, + input arvalid, + input aready, + input araddr, + input arsize, + input arburst, + input arcache, + input arprot, + input arid, + input arlen, + input arlock, + input arqos, + input aregion, + input aruser, + input rvalid, + input rready, + input rlast, + input rdata, + input rid, + input ruser, + input rresp + ); + +modport initiator_port + ( + input axi_clk, + input rst, + input awvalid, + output awready, + input awaddr, + input awsize, + input awburst, + input awcache, + input awprot, + input awid, + input awlen, + input awlock, + input awqos, + input awregion, + input awuser, + input wvalid, + output wready, + input wlast, + input wdata, + input wstrb, + input wid, + input wuser, + output bwvalid, + output bwready, + input bresp, + output bid, + output buser, + input arvalid, + output aready, + input araddr, + input arsize, + input arburst, + input arcache, + input arprot, + input arid, + input arlen, + input arlock, + input arqos, + input aregion, + input aruser, + output rvalid, + input rready, + output rlast, + output rdata, + output rid, + output ruser, + output rresp + ); + +modport responder_port + ( + input axi_clk, + input rst, + output awvalid, + input awready, + output awaddr, + output awsize, + output awburst, + output awcache, + output awprot, + output awid, + output awlen, + output awlock, + output awqos, + output awregion, + output awuser, + output wvalid, + input wready, + output wlast, + output wdata, + output wstrb, + output wid, + output wuser, + input bwvalid, + input bwready, + output bresp, + input bid, + input buser, + output arvalid, + input aready, + output araddr, + output arsize, + output arburst, + output arcache, + output arprot, + output arid, + output arlen, + output arlock, + output arqos, + output aregion, + output aruser, + input rvalid, + output rready, + input rlast, + input rdata, + input rid, + input ruser, + input rresp + ); + + +// pragma uvmf custom interface_item_additional begin +// pragma uvmf custom interface_item_additional end + +endinterface + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/verification_ip/interface_packages/axi_s_pkg/src/axi_s_infact_coverage_strategy.csv b/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/verification_ip/interface_packages/axi_s_pkg/src/axi_s_infact_coverage_strategy.csv new file mode 100644 index 00000000..1c218e14 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/verification_ip/interface_packages/axi_s_pkg/src/axi_s_infact_coverage_strategy.csv @@ -0,0 +1,6 @@ +Global +auto_bin_max, 64 + +Name,Type,Include +rand_fields,coverpoint,=rand *.** + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/verification_ip/interface_packages/axi_s_pkg/src/axi_s_macros.svh b/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/verification_ip/interface_packages/axi_s_pkg/src/axi_s_macros.svh new file mode 100644 index 00000000..84dc9f36 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/verification_ip/interface_packages/axi_s_pkg/src/axi_s_macros.svh @@ -0,0 +1,517 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This file contains macros used with the axi_s package. +// These macros include packed struct definitions. These structs are +// used to pass data between classes, hvl, and BFM's, hdl. Use of +// structs are more efficient and simpler to modify. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// + +// **************************************************************************** +// When changing the contents of this struct, be sure to update the to_struct +// and from_struct methods defined in the macros below that are used in +// the axi_s_configuration class. +// + `define axi_s_CONFIGURATION_STRUCT \ +typedef struct packed { \ + uvmf_active_passive_t active_passive; \ + uvmf_initiator_responder_t initiator_responder; \ + } axi_s_configuration_s; + + `define axi_s_CONFIGURATION_TO_STRUCT_FUNCTION \ + virtual function axi_s_configuration_s to_struct();\ + axi_s_configuration_struct = \ + {\ + this.active_passive,\ + this.initiator_responder\ + };\ + return ( axi_s_configuration_struct );\ + endfunction + + `define axi_s_CONFIGURATION_FROM_STRUCT_FUNCTION \ + virtual function void from_struct(axi_s_configuration_s axi_s_configuration_struct);\ + {\ + this.active_passive,\ + this.initiator_responder \ + } = axi_s_configuration_struct;\ + endfunction + +// **************************************************************************** +// When changing the contents of this struct, be sure to update the to_monitor_struct +// and from_monitor_struct methods of the axi_s_transaction class. +// + `define axi_s_MONITOR_STRUCT typedef struct packed { \ + bit awvalid ; \ + bit awready ; \ + bit [AW_WIDTH-1:0] awaddr ; \ + bit awsize ; \ + bit awburst ; \ + bit awcache ; \ + bit awprot ; \ + bit [X-1:0] awid ; \ + bit [LEN-1:0] awlen ; \ + bit awlock ; \ + bit awqos ; \ + bit awregion ; \ + bit [X-1:0] awuser ; \ + bit wvalid ; \ + bit wready ; \ + bit wlast ; \ + bit [DATA_WIDTH-1:0] wdata ; \ + bit [DATA_WIDTH/8-1:0] wstrb ; \ + bit [X-1:0] wid ; \ + bit [X-1:0] wuser ; \ + bit bwvalid ; \ + bit bwready ; \ + bit bresp ; \ + bit [X-1:0] bid ; \ + bit [X-1:0] buser ; \ + bit arvalid ; \ + bit aready ; \ + bit [AW_WIDTH-1:0] araddr ; \ + bit arsize ; \ + bit arburst ; \ + bit arcache ; \ + bit arprot ; \ + bit [X-1:0] arid ; \ + bit [LEN-1:0] arlen ; \ + bit arlock ; \ + bit arqos ; \ + bit aregion ; \ + bit [X-1:0] aruser ; \ + bit rvalid ; \ + bit rready ; \ + bit rlast ; \ + bit [DATA_WIDTH-1:0] rdata ; \ + bit [X-1:0] rid ; \ + bit [X-1:0] ruser ; \ + bit rresp ; \ + } axi_s_monitor_s; + + `define axi_s_TO_MONITOR_STRUCT_FUNCTION \ + virtual function axi_s_monitor_s to_monitor_struct();\ + axi_s_monitor_struct = \ + { \ + this.awvalid , \ + this.awready , \ + this.awaddr , \ + this.awsize , \ + this.awburst , \ + this.awcache , \ + this.awprot , \ + this.awid , \ + this.awlen , \ + this.awlock , \ + this.awqos , \ + this.awregion , \ + this.awuser , \ + this.wvalid , \ + this.wready , \ + this.wlast , \ + this.wdata , \ + this.wstrb , \ + this.wid , \ + this.wuser , \ + this.bwvalid , \ + this.bwready , \ + this.bresp , \ + this.bid , \ + this.buser , \ + this.arvalid , \ + this.aready , \ + this.araddr , \ + this.arsize , \ + this.arburst , \ + this.arcache , \ + this.arprot , \ + this.arid , \ + this.arlen , \ + this.arlock , \ + this.arqos , \ + this.aregion , \ + this.aruser , \ + this.rvalid , \ + this.rready , \ + this.rlast , \ + this.rdata , \ + this.rid , \ + this.ruser , \ + this.rresp \ + };\ + return ( axi_s_monitor_struct);\ + endfunction\ + + `define axi_s_FROM_MONITOR_STRUCT_FUNCTION \ + virtual function void from_monitor_struct(axi_s_monitor_s axi_s_monitor_struct);\ + {\ + this.awvalid , \ + this.awready , \ + this.awaddr , \ + this.awsize , \ + this.awburst , \ + this.awcache , \ + this.awprot , \ + this.awid , \ + this.awlen , \ + this.awlock , \ + this.awqos , \ + this.awregion , \ + this.awuser , \ + this.wvalid , \ + this.wready , \ + this.wlast , \ + this.wdata , \ + this.wstrb , \ + this.wid , \ + this.wuser , \ + this.bwvalid , \ + this.bwready , \ + this.bresp , \ + this.bid , \ + this.buser , \ + this.arvalid , \ + this.aready , \ + this.araddr , \ + this.arsize , \ + this.arburst , \ + this.arcache , \ + this.arprot , \ + this.arid , \ + this.arlen , \ + this.arlock , \ + this.arqos , \ + this.aregion , \ + this.aruser , \ + this.rvalid , \ + this.rready , \ + this.rlast , \ + this.rdata , \ + this.rid , \ + this.ruser , \ + this.rresp \ + } = axi_s_monitor_struct;\ + endfunction + +// **************************************************************************** +// When changing the contents of this struct, be sure to update the to_initiator_struct +// and from_initiator_struct methods of the axi_s_transaction class. +// Also update the comments in the driver BFM. +// + `define axi_s_INITIATOR_STRUCT typedef struct packed { \ + bit awvalid ; \ + bit awready ; \ + bit [AW_WIDTH-1:0] awaddr ; \ + bit awsize ; \ + bit awburst ; \ + bit awcache ; \ + bit awprot ; \ + bit [X-1:0] awid ; \ + bit [LEN-1:0] awlen ; \ + bit awlock ; \ + bit awqos ; \ + bit awregion ; \ + bit [X-1:0] awuser ; \ + bit wvalid ; \ + bit wready ; \ + bit wlast ; \ + bit [DATA_WIDTH-1:0] wdata ; \ + bit [DATA_WIDTH/8-1:0] wstrb ; \ + bit [X-1:0] wid ; \ + bit [X-1:0] wuser ; \ + bit bwvalid ; \ + bit bwready ; \ + bit bresp ; \ + bit [X-1:0] bid ; \ + bit [X-1:0] buser ; \ + bit arvalid ; \ + bit aready ; \ + bit [AW_WIDTH-1:0] araddr ; \ + bit arsize ; \ + bit arburst ; \ + bit arcache ; \ + bit arprot ; \ + bit [X-1:0] arid ; \ + bit [LEN-1:0] arlen ; \ + bit arlock ; \ + bit arqos ; \ + bit aregion ; \ + bit [X-1:0] aruser ; \ + bit rvalid ; \ + bit rready ; \ + bit rlast ; \ + bit [DATA_WIDTH-1:0] rdata ; \ + bit [X-1:0] rid ; \ + bit [X-1:0] ruser ; \ + bit rresp ; \ + } axi_s_initiator_s; + + `define axi_s_TO_INITIATOR_STRUCT_FUNCTION \ + virtual function axi_s_initiator_s to_initiator_struct();\ + axi_s_initiator_struct = \ + {\ + this.awvalid , \ + this.awready , \ + this.awaddr , \ + this.awsize , \ + this.awburst , \ + this.awcache , \ + this.awprot , \ + this.awid , \ + this.awlen , \ + this.awlock , \ + this.awqos , \ + this.awregion , \ + this.awuser , \ + this.wvalid , \ + this.wready , \ + this.wlast , \ + this.wdata , \ + this.wstrb , \ + this.wid , \ + this.wuser , \ + this.bwvalid , \ + this.bwready , \ + this.bresp , \ + this.bid , \ + this.buser , \ + this.arvalid , \ + this.aready , \ + this.araddr , \ + this.arsize , \ + this.arburst , \ + this.arcache , \ + this.arprot , \ + this.arid , \ + this.arlen , \ + this.arlock , \ + this.arqos , \ + this.aregion , \ + this.aruser , \ + this.rvalid , \ + this.rready , \ + this.rlast , \ + this.rdata , \ + this.rid , \ + this.ruser , \ + this.rresp \ + };\ + return ( axi_s_initiator_struct);\ + endfunction + + `define axi_s_FROM_INITIATOR_STRUCT_FUNCTION \ + virtual function void from_initiator_struct(axi_s_initiator_s axi_s_initiator_struct);\ + {\ + this.awvalid , \ + this.awready , \ + this.awaddr , \ + this.awsize , \ + this.awburst , \ + this.awcache , \ + this.awprot , \ + this.awid , \ + this.awlen , \ + this.awlock , \ + this.awqos , \ + this.awregion , \ + this.awuser , \ + this.wvalid , \ + this.wready , \ + this.wlast , \ + this.wdata , \ + this.wstrb , \ + this.wid , \ + this.wuser , \ + this.bwvalid , \ + this.bwready , \ + this.bresp , \ + this.bid , \ + this.buser , \ + this.arvalid , \ + this.aready , \ + this.araddr , \ + this.arsize , \ + this.arburst , \ + this.arcache , \ + this.arprot , \ + this.arid , \ + this.arlen , \ + this.arlock , \ + this.arqos , \ + this.aregion , \ + this.aruser , \ + this.rvalid , \ + this.rready , \ + this.rlast , \ + this.rdata , \ + this.rid , \ + this.ruser , \ + this.rresp \ + } = axi_s_initiator_struct;\ + endfunction + +// **************************************************************************** +// When changing the contents of this struct, be sure to update the to_responder_struct +// and from_responder_struct methods of the axi_s_transaction class. +// Also update the comments in the driver BFM. +// + `define axi_s_RESPONDER_STRUCT typedef struct packed { \ + bit awvalid ; \ + bit awready ; \ + bit [AW_WIDTH-1:0] awaddr ; \ + bit awsize ; \ + bit awburst ; \ + bit awcache ; \ + bit awprot ; \ + bit [X-1:0] awid ; \ + bit [LEN-1:0] awlen ; \ + bit awlock ; \ + bit awqos ; \ + bit awregion ; \ + bit [X-1:0] awuser ; \ + bit wvalid ; \ + bit wready ; \ + bit wlast ; \ + bit [DATA_WIDTH-1:0] wdata ; \ + bit [DATA_WIDTH/8-1:0] wstrb ; \ + bit [X-1:0] wid ; \ + bit [X-1:0] wuser ; \ + bit bwvalid ; \ + bit bwready ; \ + bit bresp ; \ + bit [X-1:0] bid ; \ + bit [X-1:0] buser ; \ + bit arvalid ; \ + bit aready ; \ + bit [AW_WIDTH-1:0] araddr ; \ + bit arsize ; \ + bit arburst ; \ + bit arcache ; \ + bit arprot ; \ + bit [X-1:0] arid ; \ + bit [LEN-1:0] arlen ; \ + bit arlock ; \ + bit arqos ; \ + bit aregion ; \ + bit [X-1:0] aruser ; \ + bit rvalid ; \ + bit rready ; \ + bit rlast ; \ + bit [DATA_WIDTH-1:0] rdata ; \ + bit [X-1:0] rid ; \ + bit [X-1:0] ruser ; \ + bit rresp ; \ + } axi_s_responder_s; + + `define axi_s_TO_RESPONDER_STRUCT_FUNCTION \ + virtual function axi_s_responder_s to_responder_struct();\ + axi_s_responder_struct = \ + {\ + this.awvalid , \ + this.awready , \ + this.awaddr , \ + this.awsize , \ + this.awburst , \ + this.awcache , \ + this.awprot , \ + this.awid , \ + this.awlen , \ + this.awlock , \ + this.awqos , \ + this.awregion , \ + this.awuser , \ + this.wvalid , \ + this.wready , \ + this.wlast , \ + this.wdata , \ + this.wstrb , \ + this.wid , \ + this.wuser , \ + this.bwvalid , \ + this.bwready , \ + this.bresp , \ + this.bid , \ + this.buser , \ + this.arvalid , \ + this.aready , \ + this.araddr , \ + this.arsize , \ + this.arburst , \ + this.arcache , \ + this.arprot , \ + this.arid , \ + this.arlen , \ + this.arlock , \ + this.arqos , \ + this.aregion , \ + this.aruser , \ + this.rvalid , \ + this.rready , \ + this.rlast , \ + this.rdata , \ + this.rid , \ + this.ruser , \ + this.rresp \ + };\ + return ( axi_s_responder_struct);\ + endfunction + + `define axi_s_FROM_RESPONDER_STRUCT_FUNCTION \ + virtual function void from_responder_struct(axi_s_responder_s axi_s_responder_struct);\ + {\ + this.awvalid , \ + this.awready , \ + this.awaddr , \ + this.awsize , \ + this.awburst , \ + this.awcache , \ + this.awprot , \ + this.awid , \ + this.awlen , \ + this.awlock , \ + this.awqos , \ + this.awregion , \ + this.awuser , \ + this.wvalid , \ + this.wready , \ + this.wlast , \ + this.wdata , \ + this.wstrb , \ + this.wid , \ + this.wuser , \ + this.bwvalid , \ + this.bwready , \ + this.bresp , \ + this.bid , \ + this.buser , \ + this.arvalid , \ + this.aready , \ + this.araddr , \ + this.arsize , \ + this.arburst , \ + this.arcache , \ + this.arprot , \ + this.arid , \ + this.arlen , \ + this.arlock , \ + this.arqos , \ + this.aregion , \ + this.aruser , \ + this.rvalid , \ + this.rready , \ + this.rlast , \ + this.rdata , \ + this.rid , \ + this.ruser , \ + this.rresp \ + } = axi_s_responder_struct;\ + endfunction +// pragma uvmf custom additional begin +// pragma uvmf custom additional end diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/verification_ip/interface_packages/axi_s_pkg/src/axi_s_monitor.svh b/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/verification_ip/interface_packages/axi_s_pkg/src/axi_s_monitor.svh new file mode 100644 index 00000000..63bc38e6 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/verification_ip/interface_packages/axi_s_pkg/src/axi_s_monitor.svh @@ -0,0 +1,112 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This class receives axi_s transactions observed by the +// axi_s monitor BFM and broadcasts them through the analysis port +// on the agent. It accesses the monitor BFM through the monitor +// task. This UVM component captures transactions +// for viewing in the waveform viewer if the +// enable_transaction_viewing flag is set in the configuration. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class axi_s_monitor #( + int AW_WIDTH = 32, + int LEN = 8, + int DATA_WIDTH = 32, + int X = 16 + ) extends uvmf_monitor_base #( + .CONFIG_T(axi_s_configuration #( + .AW_WIDTH(AW_WIDTH), + .LEN(LEN), + .DATA_WIDTH(DATA_WIDTH), + .X(X) + )), + .BFM_BIND_T(virtual axi_s_monitor_bfm #( + .AW_WIDTH(AW_WIDTH), + .LEN(LEN), + .DATA_WIDTH(DATA_WIDTH), + .X(X) + )), + .TRANS_T(axi_s_transaction #( + .AW_WIDTH(AW_WIDTH), + .LEN(LEN), + .DATA_WIDTH(DATA_WIDTH), + .X(X) + ))); + + `uvm_component_param_utils( axi_s_monitor #( + AW_WIDTH, + LEN, + DATA_WIDTH, + X + )) + +// Structure used to pass data from monitor BFM to monitor class in agent. +// Use to_monitor_struct function to pack transaction variables into structure. +// Use from_monitor_struct function to unpack transaction variables from structure. +`axi_s_MONITOR_STRUCT + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + +// **************************************************************************** +// This function is the standard SystemVerilog constructor. +// + function new( string name = "", uvm_component parent = null ); + super.new( name, parent ); + endfunction + +// **************************************************************************** +// This function sends configuration object variables to the monitor BFM +// using the configuration struct. +// + virtual function void configure(input CONFIG_T cfg); + bfm.configure( cfg.to_struct() ); + + endfunction + +// **************************************************************************** +// This function places a handle to this class in the proxy variable in the +// monitor BFM. This allows the monitor BFM to call the notify_transaction +// function within this class. +// + virtual function void set_bfm_proxy_handle(); + bfm.proxy = this; endfunction + +// *************************************************************************** + virtual task run_phase(uvm_phase phase); + // Start monitor BFM thread and don't call super.run() in order to + // override the default monitor proxy 'pull' behavior with the more + // emulation-friendly BFM 'push' approach using the notify_transaction + // function below + bfm.start_monitoring(); + endtask + +// ************************************************************************** + +// This function is called by the monitor BFM. It receives data observed by the +// monitor BFM. Data is passed using the axi_s_monitor_struct. + virtual function void notify_transaction(input axi_s_monitor_s axi_s_monitor_struct); + + + trans = new("trans"); + trans.from_monitor_struct(axi_s_monitor_struct); + trans.start_time = time_stamp; + trans.end_time = $time; + time_stamp = trans.end_time; + + analyze(trans); + endfunction + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/verification_ip/interface_packages/axi_s_pkg/src/axi_s_monitor_bfm.sv b/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/verification_ip/interface_packages/axi_s_pkg/src/axi_s_monitor_bfm.sv new file mode 100644 index 00000000..d8a65d39 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/verification_ip/interface_packages/axi_s_pkg/src/axi_s_monitor_bfm.sv @@ -0,0 +1,360 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This interface performs the axi_s signal monitoring. +// It is accessed by the uvm axi_s monitor through a virtual +// interface handle in the axi_s configuration. It monitors the +// signals passed in through the port connection named bus of +// type axi_s_if. +// +// Input signals from the axi_s_if are assigned to an internal input +// signal with a _i suffix. The _i signal should be used for sampling. +// +// The input signal connections are as follows: +// bus.signal -> signal_i +// +// Interface functions and tasks used by UVM components: +// monitor(inout TRANS_T txn); +// This task receives the transaction, txn, from the +// UVM monitor and then populates variables in txn +// from values observed on bus activity. This task +// blocks until an operation on the axi_s bus is complete. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +import uvmf_base_pkg_hdl::*; +import axi_s_pkg_hdl::*; +`include "src/axi_s_macros.svh" + + +interface axi_s_monitor_bfm #( + int AW_WIDTH = 32, + int LEN = 8, + int DATA_WIDTH = 32, + int X = 16 + ) + ( axi_s_if bus ); + // The pragma below and additional ones in-lined further down are for running this BFM on Veloce + // pragma attribute axi_s_monitor_bfm partition_interface_xif + +`ifndef XRTL +// This code is to aid in debugging parameter mismatches between the BFM and its corresponding agent. +// Enable this debug by setting UVM_VERBOSITY to UVM_DEBUG +// Setting UVM_VERBOSITY to UVM_DEBUG causes all BFM's and all agents to display their parameter settings. +// All of the messages from this feature have a UVM messaging id value of "CFG" +// The transcript or run.log can be parsed to ensure BFM parameter settings match its corresponding agents parameter settings. +import uvm_pkg::*; +`include "uvm_macros.svh" +initial begin : bfm_vs_agent_parameter_debug + `uvm_info("CFG", + $psprintf("The BFM at '%m' has the following parameters: AW_WIDTH=%x LEN=%x DATA_WIDTH=%x X=%x ", AW_WIDTH,LEN,DATA_WIDTH,X), + UVM_DEBUG) +end +`endif + + + // Structure used to pass transaction data from monitor BFM to monitor class in agent. +`axi_s_MONITOR_STRUCT + axi_s_monitor_s axi_s_monitor_struct; + + // Structure used to pass configuration data from monitor class to monitor BFM. + `axi_s_CONFIGURATION_STRUCT + + + // Config value to determine if this is an initiator or a responder + uvmf_initiator_responder_t initiator_responder; + // Custom configuration variables. + // These are set using the configure function which is called during the UVM connect_phase + + logic axi_clk_i; + logic rst_i; + tri awvalid_i; + tri awready_i; + tri [AW_WIDTH-1:0] awaddr_i; + tri [2:0] awsize_i; + tri [1:0] awburst_i; + tri [3:0] awcache_i; + tri [2:0] awprot_i; + tri [X-1:0] awid_i; + tri [LEN-1:0] awlen_i; + tri awlock_i; + tri [3:0] awqos_i; + tri [3:0] awregion_i; + tri [X-1:0] awuser_i; + tri wvalid_i; + tri wready_i; + tri wlast_i; + tri [DATA_WIDTH-1:0] wdata_i; + tri [DATA_WIDTH/8-1:0] wstrb_i; + tri [X-1:0] wid_i; + tri [X-1:0] wuser_i; + tri bwvalid_i; + tri bwready_i; + tri [1:0] bresp_i; + tri [X-1:0] bid_i; + tri [X-1:0] buser_i; + tri arvalid_i; + tri aready_i; + tri [AW_WIDTH-1:0] araddr_i; + tri [2:0] arsize_i; + tri [1:0] arburst_i; + tri [3:0] arcache_i; + tri [2:0] arprot_i; + tri [X-1:0] arid_i; + tri [LEN-1:0] arlen_i; + tri arlock_i; + tri [3:0] arqos_i; + tri [3:0] aregion_i; + tri [X-1:0] aruser_i; + tri rvalid_i; + tri rready_i; + tri rlast_i; + tri [DATA_WIDTH-1:0] rdata_i; + tri [X-1:0] rid_i; + tri [X-1:0] ruser_i; + tri [1:0] rresp_i; + assign axi_clk_i = bus.axi_clk; + assign rst_i = bus.rst; + assign awvalid_i = bus.awvalid; + assign awready_i = bus.awready; + assign awaddr_i = bus.awaddr; + assign awsize_i = bus.awsize; + assign awburst_i = bus.awburst; + assign awcache_i = bus.awcache; + assign awprot_i = bus.awprot; + assign awid_i = bus.awid; + assign awlen_i = bus.awlen; + assign awlock_i = bus.awlock; + assign awqos_i = bus.awqos; + assign awregion_i = bus.awregion; + assign awuser_i = bus.awuser; + assign wvalid_i = bus.wvalid; + assign wready_i = bus.wready; + assign wlast_i = bus.wlast; + assign wdata_i = bus.wdata; + assign wstrb_i = bus.wstrb; + assign wid_i = bus.wid; + assign wuser_i = bus.wuser; + assign bwvalid_i = bus.bwvalid; + assign bwready_i = bus.bwready; + assign bresp_i = bus.bresp; + assign bid_i = bus.bid; + assign buser_i = bus.buser; + assign arvalid_i = bus.arvalid; + assign aready_i = bus.aready; + assign araddr_i = bus.araddr; + assign arsize_i = bus.arsize; + assign arburst_i = bus.arburst; + assign arcache_i = bus.arcache; + assign arprot_i = bus.arprot; + assign arid_i = bus.arid; + assign arlen_i = bus.arlen; + assign arlock_i = bus.arlock; + assign arqos_i = bus.arqos; + assign aregion_i = bus.aregion; + assign aruser_i = bus.aruser; + assign rvalid_i = bus.rvalid; + assign rready_i = bus.rready; + assign rlast_i = bus.rlast; + assign rdata_i = bus.rdata; + assign rid_i = bus.rid; + assign ruser_i = bus.ruser; + assign rresp_i = bus.rresp; + + // Proxy handle to UVM monitor + axi_s_pkg::axi_s_monitor #( + .AW_WIDTH(AW_WIDTH), + .LEN(LEN), + .DATA_WIDTH(DATA_WIDTH), + .X(X) + ) proxy; + // pragma tbx oneway proxy.notify_transaction + + // pragma uvmf custom interface_item_additional begin + // pragma uvmf custom interface_item_additional end + + //****************************************************************** + task wait_for_reset();// pragma tbx xtf + @(posedge axi_clk_i) ; + do_wait_for_reset(); + endtask + + // **************************************************************************** + task do_wait_for_reset(); + // pragma uvmf custom reset_condition begin + wait ( rst_i === 1 ) ; + @(posedge axi_clk_i) ; + // pragma uvmf custom reset_condition end + endtask + + //****************************************************************** + + task wait_for_num_clocks(input int unsigned count); // pragma tbx xtf + @(posedge axi_clk_i); + + repeat (count-1) @(posedge axi_clk_i); + endtask + + //****************************************************************** + event go; + function void start_monitoring();// pragma tbx xtf + -> go; + endfunction + + // **************************************************************************** + initial begin + @go; + forever begin + @(posedge axi_clk_i); + do_monitor( axi_s_monitor_struct ); + + + proxy.notify_transaction( axi_s_monitor_struct ); + + end + end + + //****************************************************************** + // The configure() function is used to pass agent configuration + // variables to the monitor BFM. It is called by the monitor within + // the agent at the beginning of the simulation. It may be called + // during the simulation if agent configuration variables are updated + // and the monitor BFM needs to be aware of the new configuration + // variables. + // + function void configure(axi_s_configuration_s axi_s_configuration_arg); // pragma tbx xtf + initiator_responder = axi_s_configuration_arg.initiator_responder; + // pragma uvmf custom configure begin + // pragma uvmf custom configure end + endfunction + + + // **************************************************************************** + + task do_monitor(output axi_s_monitor_s axi_s_monitor_struct); + // + // Available struct members: + // // axi_s_monitor_struct.awvalid + // // axi_s_monitor_struct.awready + // // axi_s_monitor_struct.awaddr + // // axi_s_monitor_struct.awsize + // // axi_s_monitor_struct.awburst + // // axi_s_monitor_struct.awcache + // // axi_s_monitor_struct.awprot + // // axi_s_monitor_struct.awid + // // axi_s_monitor_struct.awlen + // // axi_s_monitor_struct.awlock + // // axi_s_monitor_struct.awqos + // // axi_s_monitor_struct.awregion + // // axi_s_monitor_struct.awuser + // // axi_s_monitor_struct.wvalid + // // axi_s_monitor_struct.wready + // // axi_s_monitor_struct.wlast + // // axi_s_monitor_struct.wdata + // // axi_s_monitor_struct.wstrb + // // axi_s_monitor_struct.wid + // // axi_s_monitor_struct.wuser + // // axi_s_monitor_struct.bwvalid + // // axi_s_monitor_struct.bwready + // // axi_s_monitor_struct.bresp + // // axi_s_monitor_struct.bid + // // axi_s_monitor_struct.buser + // // axi_s_monitor_struct.arvalid + // // axi_s_monitor_struct.aready + // // axi_s_monitor_struct.araddr + // // axi_s_monitor_struct.arsize + // // axi_s_monitor_struct.arburst + // // axi_s_monitor_struct.arcache + // // axi_s_monitor_struct.arprot + // // axi_s_monitor_struct.arid + // // axi_s_monitor_struct.arlen + // // axi_s_monitor_struct.arlock + // // axi_s_monitor_struct.arqos + // // axi_s_monitor_struct.aregion + // // axi_s_monitor_struct.aruser + // // axi_s_monitor_struct.rvalid + // // axi_s_monitor_struct.rready + // // axi_s_monitor_struct.rlast + // // axi_s_monitor_struct.rdata + // // axi_s_monitor_struct.rid + // // axi_s_monitor_struct.ruser + // // axi_s_monitor_struct.rresp + // // + // Reference code; + // How to wait for signal value + // while (control_signal === 1'b1) @(posedge axi_clk_i); + // + // How to assign a struct member, named xyz, from a signal. + // All available input signals listed. + // axi_s_monitor_struct.xyz = awvalid_i; // + // axi_s_monitor_struct.xyz = awready_i; // + // axi_s_monitor_struct.xyz = awaddr_i; // [AW_WIDTH-1:0] + // axi_s_monitor_struct.xyz = awsize_i; // [2:0] + // axi_s_monitor_struct.xyz = awburst_i; // [1:0] + // axi_s_monitor_struct.xyz = awcache_i; // [3:0] + // axi_s_monitor_struct.xyz = awprot_i; // [2:0] + // axi_s_monitor_struct.xyz = awid_i; // [X-1:0] + // axi_s_monitor_struct.xyz = awlen_i; // [LEN-1:0] + // axi_s_monitor_struct.xyz = awlock_i; // + // axi_s_monitor_struct.xyz = awqos_i; // [3:0] + // axi_s_monitor_struct.xyz = awregion_i; // [3:0] + // axi_s_monitor_struct.xyz = awuser_i; // [X-1:0] + // axi_s_monitor_struct.xyz = wvalid_i; // + // axi_s_monitor_struct.xyz = wready_i; // + // axi_s_monitor_struct.xyz = wlast_i; // + // axi_s_monitor_struct.xyz = wdata_i; // [DATA_WIDTH-1:0] + // axi_s_monitor_struct.xyz = wstrb_i; // [DATA_WIDTH/8-1:0] + // axi_s_monitor_struct.xyz = wid_i; // [X-1:0] + // axi_s_monitor_struct.xyz = wuser_i; // [X-1:0] + // axi_s_monitor_struct.xyz = bwvalid_i; // + // axi_s_monitor_struct.xyz = bwready_i; // + // axi_s_monitor_struct.xyz = bresp_i; // [1:0] + // axi_s_monitor_struct.xyz = bid_i; // [X-1:0] + // axi_s_monitor_struct.xyz = buser_i; // [X-1:0] + // axi_s_monitor_struct.xyz = arvalid_i; // + // axi_s_monitor_struct.xyz = aready_i; // + // axi_s_monitor_struct.xyz = araddr_i; // [AW_WIDTH-1:0] + // axi_s_monitor_struct.xyz = arsize_i; // [2:0] + // axi_s_monitor_struct.xyz = arburst_i; // [1:0] + // axi_s_monitor_struct.xyz = arcache_i; // [3:0] + // axi_s_monitor_struct.xyz = arprot_i; // [2:0] + // axi_s_monitor_struct.xyz = arid_i; // [X-1:0] + // axi_s_monitor_struct.xyz = arlen_i; // [LEN-1:0] + // axi_s_monitor_struct.xyz = arlock_i; // + // axi_s_monitor_struct.xyz = arqos_i; // [3:0] + // axi_s_monitor_struct.xyz = aregion_i; // [3:0] + // axi_s_monitor_struct.xyz = aruser_i; // [X-1:0] + // axi_s_monitor_struct.xyz = rvalid_i; // + // axi_s_monitor_struct.xyz = rready_i; // + // axi_s_monitor_struct.xyz = rlast_i; // + // axi_s_monitor_struct.xyz = rdata_i; // [DATA_WIDTH-1:0] + // axi_s_monitor_struct.xyz = rid_i; // [X-1:0] + // axi_s_monitor_struct.xyz = ruser_i; // [X-1:0] + // axi_s_monitor_struct.xyz = rresp_i; // [1:0] + // pragma uvmf custom do_monitor begin + // UVMF_CHANGE_ME : Implement protocol monitoring. The commented reference code + // below are examples of how to capture signal values and assign them to + // structure members. All available input signals are listed. The 'while' + // code example shows how to wait for a synchronous flow control signal. This + // task should return when a complete transfer has been observed. Once this task is + // exited with captured values, it is then called again to wait for and observe + // the next transfer. One clock cycle is consumed between calls to do_monitor. + @(posedge axi_clk_i); + @(posedge axi_clk_i); + @(posedge axi_clk_i); + @(posedge axi_clk_i); + // pragma uvmf custom do_monitor end + endtask + + +endinterface + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/verification_ip/interface_packages/axi_s_pkg/src/axi_s_random_sequence.svh b/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/verification_ip/interface_packages/axi_s_pkg/src/axi_s_random_sequence.svh new file mode 100644 index 00000000..3eed0e3c --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/verification_ip/interface_packages/axi_s_pkg/src/axi_s_random_sequence.svh @@ -0,0 +1,73 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: +// This sequences randomizes the axi_s transaction and sends it +// to the UVM driver. +// +// This sequence constructs and randomizes a axi_s_transaction. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class axi_s_random_sequence #( + int AW_WIDTH = 32, + int LEN = 8, + int DATA_WIDTH = 32, + int X = 16 + ) + extends axi_s_sequence_base #( + .AW_WIDTH(AW_WIDTH), + .LEN(LEN), + .DATA_WIDTH(DATA_WIDTH), + .X(X) + ); + + `uvm_object_param_utils( axi_s_random_sequence #( + AW_WIDTH, + LEN, + DATA_WIDTH, + X + )) + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + //***************************************************************** + function new(string name = ""); + super.new(name); + endfunction: new + + // **************************************************************************** + // TASK : body() + // This task is automatically executed when this sequence is started using the + // start(sequencerHandle) task. + // + task body(); + + // Construct the transaction + req=axi_s_transaction#( + .AW_WIDTH(AW_WIDTH), + .LEN(LEN), + .DATA_WIDTH(DATA_WIDTH), + .X(X) + )::type_id::create("req"); + start_item(req); + // Randomize the transaction + if(!req.randomize()) `uvm_fatal("SEQ", "axi_s_random_sequence::body()-axi_s_transaction randomization failed") + // Send the transaction to the axi_s_driver_bfm via the sequencer and axi_s_driver. + finish_item(req); + `uvm_info("SEQ", {"Response:",req.convert2string()},UVM_MEDIUM) + + endtask + +endclass: axi_s_random_sequence + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/verification_ip/interface_packages/axi_s_pkg/src/axi_s_responder_sequence.svh b/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/verification_ip/interface_packages/axi_s_pkg/src/axi_s_responder_sequence.svh new file mode 100644 index 00000000..bf30907b --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/verification_ip/interface_packages/axi_s_pkg/src/axi_s_responder_sequence.svh @@ -0,0 +1,69 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This class can be used to provide stimulus when an interface +// has been configured to run in a responder mode. It +// will never finish by default, always going back to the driver +// and driver BFM for the next transaction with which to respond. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class axi_s_responder_sequence #( + int AW_WIDTH = 32, + int LEN = 8, + int DATA_WIDTH = 32, + int X = 16 + ) + extends axi_s_sequence_base #( + .AW_WIDTH(AW_WIDTH), + .LEN(LEN), + .DATA_WIDTH(DATA_WIDTH), + .X(X) + ); + + `uvm_object_param_utils( axi_s_responder_sequence #( + AW_WIDTH, + LEN, + DATA_WIDTH, + X + )) + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + function new(string name = "axi_s_responder_sequence"); + super.new(name); + endfunction + + task body(); + req=axi_s_transaction#( + .AW_WIDTH(AW_WIDTH), + .LEN(LEN), + .DATA_WIDTH(DATA_WIDTH), + .X(X) + )::type_id::create("req"); + forever begin + start_item(req); + finish_item(req); + // pragma uvmf custom body begin + // UVMF_CHANGE_ME : Do something here with the resulting req item. The + // finish_item() call above will block until the req transaction is ready + // to be handled by the responder sequence. + // If this was an item that required a response, the expectation is + // that the response should be populated within this transaction now. + `uvm_info("SEQ",$sformatf("Processed txn: %s",req.convert2string()),UVM_HIGH) + // pragma uvmf custom body end + end + endtask + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/verification_ip/interface_packages/axi_s_pkg/src/axi_s_sequence_base.svh b/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/verification_ip/interface_packages/axi_s_pkg/src/axi_s_sequence_base.svh new file mode 100644 index 00000000..1a75be44 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/verification_ip/interface_packages/axi_s_pkg/src/axi_s_sequence_base.svh @@ -0,0 +1,126 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: +// This file contains the class used as the base class for all sequences +// for this interface. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class axi_s_sequence_base #( + int AW_WIDTH = 32, + int LEN = 8, + int DATA_WIDTH = 32, + int X = 16 + ) extends uvmf_sequence_base #( + .REQ(axi_s_transaction #( + .AW_WIDTH(AW_WIDTH), + .LEN(LEN), + .DATA_WIDTH(DATA_WIDTH), + .X(X) + )), + .RSP(axi_s_transaction #( + .AW_WIDTH(AW_WIDTH), + .LEN(LEN), + .DATA_WIDTH(DATA_WIDTH), + .X(X) + ))); + + `uvm_object_param_utils( axi_s_sequence_base #( + AW_WIDTH, + LEN, + DATA_WIDTH, + X + )) + + // variables + typedef axi_s_transaction #( + .AW_WIDTH(AW_WIDTH), + .LEN(LEN), + .DATA_WIDTH(DATA_WIDTH), + .X(X) + ) axi_s_transaction_req_t; + axi_s_transaction_req_t req; + typedef axi_s_transaction #( + .AW_WIDTH(AW_WIDTH), + .LEN(LEN), + .DATA_WIDTH(DATA_WIDTH), + .X(X) + ) axi_s_transaction_rsp_t; + axi_s_transaction_rsp_t rsp; + + // Event for identifying when a response was received from the sequencer + event new_rsp; + + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + // **************************************************************************** + // TASK : get_responses() + // This task recursively gets sequence item responses from the sequencer. + // + virtual task get_responses(); + fork + begin + // Block until new rsp available + get_response(rsp); + // New rsp received. Indicate to sequence using event. + ->new_rsp; + // Display the received response transaction + `uvm_info("SEQ", {"New response transaction:",rsp.convert2string()}, UVM_MEDIUM) + end + join_none + endtask + + // **************************************************************************** + // TASK : pre_body() + // This task is called automatically when start is called with call_pre_post set to 1 (default). + // By calling get_responses() within pre_body() any derived sequences are automatically + // processing response transactions. Only un-comment this call to get_responses() if you + // have configured the interface driver to utilize the response transaction path by setting + // the configuration variable "return_transaction_response" to 1. Otherwise it is possible + // to impact runtime performance and memory utilization. + // + virtual task pre_body(); + // pragma uvmf custom pre_body begin +// get_responses(); + // pragma uvmf custom pre_body end + endtask + + // **************************************************************************** + // TASK : body() + // This task is called automatically when start is called. This sequence sends + // a req sequence item to the sequencer identified as an argument in the call + // to start. + // + virtual task body(); + // pragma uvmf custom body begin + start_item(req); + finish_item(req); + // pragma uvmf custom body end + endtask + + // **************************************************************************** + // FUNCTION : new() + // This function is the standard SystemVerilog constructor. + // + function new( string name =""); + super.new( name ); + // pragma uvmf custom new begin + req = axi_s_transaction_req_t::type_id::create("req"); + rsp = axi_s_transaction_rsp_t::type_id::create("rsp"); + // pragma uvmf custom new end + endfunction + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/verification_ip/interface_packages/axi_s_pkg/src/axi_s_transaction.svh b/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/verification_ip/interface_packages/axi_s_pkg/src/axi_s_transaction.svh new file mode 100644 index 00000000..f8776dc6 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/verification_ip/interface_packages/axi_s_pkg/src/axi_s_transaction.svh @@ -0,0 +1,333 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This class defines the variables required for an axi_s +// transaction. Class variables to be displayed in waveform transaction +// viewing are added to the transaction viewing stream in the add_to_wave +// function. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class axi_s_transaction #( + int AW_WIDTH = 32, + int LEN = 8, + int DATA_WIDTH = 32, + int X = 16 + ) extends uvmf_transaction_base; + + `uvm_object_param_utils( axi_s_transaction #( + AW_WIDTH, + LEN, + DATA_WIDTH, + X + )) + + bit awvalid ; + bit awready ; + bit [AW_WIDTH-1:0] awaddr ; + bit awsize ; + bit awburst ; + bit awcache ; + bit awprot ; + bit [X-1:0] awid ; + bit [LEN-1:0] awlen ; + bit awlock ; + bit awqos ; + bit awregion ; + bit [X-1:0] awuser ; + bit wvalid ; + bit wready ; + bit wlast ; + bit [DATA_WIDTH-1:0] wdata ; + bit [DATA_WIDTH/8-1:0] wstrb ; + bit [X-1:0] wid ; + bit [X-1:0] wuser ; + bit bwvalid ; + bit bwready ; + rand bit bresp ; + bit [X-1:0] bid ; + rand bit [X-1:0] buser ; + bit arvalid ; + bit aready ; + rand bit [AW_WIDTH-1:0] araddr ; + rand bit arsize ; + rand bit arburst ; + rand bit arcache ; + rand bit arprot ; + rand bit [X-1:0] arid ; + rand bit [LEN-1:0] arlen ; + rand bit arlock ; + rand bit arqos ; + bit aregion ; + bit [X-1:0] aruser ; + bit rvalid ; + bit rready ; + bit rlast ; + rand bit [DATA_WIDTH-1:0] rdata ; + rand bit [X-1:0] rid ; + rand bit [X-1:0] ruser ; + rand bit rresp ; + + //Constraints for the transaction variables: + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + //******************************************************************* + //******************************************************************* + // Macros that define structs and associated functions are + // located in axi_s_macros.svh + + //******************************************************************* + // Monitor macro used by axi_s_monitor and axi_s_monitor_bfm + // This struct is defined in axi_s_macros.svh + `axi_s_MONITOR_STRUCT + axi_s_monitor_s axi_s_monitor_struct; + //******************************************************************* + // FUNCTION: to_monitor_struct() + // This function packs transaction variables into a axi_s_monitor_s + // structure. The function returns the handle to the axi_s_monitor_struct. + // This function is defined in axi_s_macros.svh + `axi_s_TO_MONITOR_STRUCT_FUNCTION + //******************************************************************* + // FUNCTION: from_monitor_struct() + // This function unpacks the struct provided as an argument into transaction + // variables of this class. + // This function is defined in axi_s_macros.svh + `axi_s_FROM_MONITOR_STRUCT_FUNCTION + + //******************************************************************* + // Initiator macro used by axi_s_driver and axi_s_driver_bfm + // to communicate initiator driven data to axi_s_driver_bfm. + // This struct is defined in axi_s_macros.svh + `axi_s_INITIATOR_STRUCT + axi_s_initiator_s axi_s_initiator_struct; + //******************************************************************* + // FUNCTION: to_initiator_struct() + // This function packs transaction variables into a axi_s_initiator_s + // structure. The function returns the handle to the axi_s_initiator_struct. + // This function is defined in axi_s_macros.svh + `axi_s_TO_INITIATOR_STRUCT_FUNCTION + //******************************************************************* + // FUNCTION: from_initiator_struct() + // This function unpacks the struct provided as an argument into transaction + // variables of this class. + // This function is defined in axi_s_macros.svh + `axi_s_FROM_INITIATOR_STRUCT_FUNCTION + + //******************************************************************* + // Responder macro used by axi_s_driver and axi_s_driver_bfm + // to communicate Responder driven data to axi_s_driver_bfm. + // This struct is defined in axi_s_macros.svh + `axi_s_RESPONDER_STRUCT + axi_s_responder_s axi_s_responder_struct; + //******************************************************************* + // FUNCTION: to_responder_struct() + // This function packs transaction variables into a axi_s_responder_s + // structure. The function returns the handle to the axi_s_responder_struct. + // This function is defined in axi_s_macros.svh + `axi_s_TO_RESPONDER_STRUCT_FUNCTION + //******************************************************************* + // FUNCTION: from_responder_struct() + // This function unpacks the struct provided as an argument into transaction + // variables of this class. + // This function is defined in axi_s_macros.svh + `axi_s_FROM_RESPONDER_STRUCT_FUNCTION + // **************************************************************************** + // FUNCTION : new() + // This function is the standard SystemVerilog constructor. + // + function new( string name = "" ); + super.new( name ); + endfunction + + // **************************************************************************** + // FUNCTION: convert2string() + // This function converts all variables in this class to a single string for + // logfile reporting. + // + virtual function string convert2string(); + // pragma uvmf custom convert2string begin + // UVMF_CHANGE_ME : Customize format if desired. + return $sformatf("awvalid:0x%x awready:0x%x awaddr:0x%x awsize:0x%x awburst:0x%x awcache:0x%x awprot:0x%x awid:0x%x awlen:0x%x awlock:0x%x awqos:0x%x awregion:0x%x awuser:0x%x wvalid:0x%x wready:0x%x wlast:0x%x wdata:0x%x wstrb:0x%x wid:0x%x wuser:0x%x bwvalid:0x%x bwready:0x%x bresp:0x%x bid:0x%x buser:0x%x arvalid:0x%x aready:0x%x araddr:0x%x arsize:0x%x arburst:0x%x arcache:0x%x arprot:0x%x arid:0x%x arlen:0x%x arlock:0x%x arqos:0x%x aregion:0x%x aruser:0x%x rvalid:0x%x rready:0x%x rlast:0x%x rdata:0x%x rid:0x%x ruser:0x%x rresp:0x%x ",awvalid,awready,awaddr,awsize,awburst,awcache,awprot,awid,awlen,awlock,awqos,awregion,awuser,wvalid,wready,wlast,wdata,wstrb,wid,wuser,bwvalid,bwready,bresp,bid,buser,arvalid,aready,araddr,arsize,arburst,arcache,arprot,arid,arlen,arlock,arqos,aregion,aruser,rvalid,rready,rlast,rdata,rid,ruser,rresp); + // pragma uvmf custom convert2string end + endfunction + + //******************************************************************* + // FUNCTION: do_print() + // This function is automatically called when the .print() function + // is called on this class. + // + virtual function void do_print(uvm_printer printer); + // pragma uvmf custom do_print begin + // UVMF_CHANGE_ME : Current contents of do_print allows for the use of UVM 1.1d, 1.2 or P1800.2. + // Update based on your own printing preference according to your preferred UVM version + $display(convert2string()); + // pragma uvmf custom do_print end + endfunction + + //******************************************************************* + // FUNCTION: do_compare() + // This function is automatically called when the .compare() function + // is called on this class. + // + virtual function bit do_compare (uvm_object rhs, uvm_comparer comparer); + axi_s_transaction #( + .AW_WIDTH(AW_WIDTH), + .LEN(LEN), + .DATA_WIDTH(DATA_WIDTH), + .X(X) + ) RHS; + if (!$cast(RHS,rhs)) return 0; + // pragma uvmf custom do_compare begin + // UVMF_CHANGE_ME : Eliminate comparison of variables not to be used for compare + return (super.do_compare(rhs,comparer) + ); + // pragma uvmf custom do_compare end + endfunction + + //******************************************************************* + // FUNCTION: do_copy() + // This function is automatically called when the .copy() function + // is called on this class. + // + virtual function void do_copy (uvm_object rhs); + axi_s_transaction #( + .AW_WIDTH(AW_WIDTH), + .LEN(LEN), + .DATA_WIDTH(DATA_WIDTH), + .X(X) + ) RHS; + assert($cast(RHS,rhs)); + // pragma uvmf custom do_copy begin + super.do_copy(rhs); + this.awvalid = RHS.awvalid; + this.awready = RHS.awready; + this.awaddr = RHS.awaddr; + this.awsize = RHS.awsize; + this.awburst = RHS.awburst; + this.awcache = RHS.awcache; + this.awprot = RHS.awprot; + this.awid = RHS.awid; + this.awlen = RHS.awlen; + this.awlock = RHS.awlock; + this.awqos = RHS.awqos; + this.awregion = RHS.awregion; + this.awuser = RHS.awuser; + this.wvalid = RHS.wvalid; + this.wready = RHS.wready; + this.wlast = RHS.wlast; + this.wdata = RHS.wdata; + this.wstrb = RHS.wstrb; + this.wid = RHS.wid; + this.wuser = RHS.wuser; + this.bwvalid = RHS.bwvalid; + this.bwready = RHS.bwready; + this.bresp = RHS.bresp; + this.bid = RHS.bid; + this.buser = RHS.buser; + this.arvalid = RHS.arvalid; + this.aready = RHS.aready; + this.araddr = RHS.araddr; + this.arsize = RHS.arsize; + this.arburst = RHS.arburst; + this.arcache = RHS.arcache; + this.arprot = RHS.arprot; + this.arid = RHS.arid; + this.arlen = RHS.arlen; + this.arlock = RHS.arlock; + this.arqos = RHS.arqos; + this.aregion = RHS.aregion; + this.aruser = RHS.aruser; + this.rvalid = RHS.rvalid; + this.rready = RHS.rready; + this.rlast = RHS.rlast; + this.rdata = RHS.rdata; + this.rid = RHS.rid; + this.ruser = RHS.ruser; + this.rresp = RHS.rresp; + // pragma uvmf custom do_copy end + endfunction + + // **************************************************************************** + // FUNCTION: add_to_wave() + // This function is used to display variables in this class in the waveform + // viewer. The start_time and end_time variables must be set before this + // function is called. If the start_time and end_time variables are not set + // the transaction will be hidden at 0ns on the waveform display. + // + virtual function void add_to_wave(int transaction_viewing_stream_h); + `ifdef QUESTA + if (transaction_view_h == 0) begin + transaction_view_h = $begin_transaction(transaction_viewing_stream_h,"axi_s_transaction",start_time); + end + super.add_to_wave(transaction_view_h); + // pragma uvmf custom add_to_wave begin + // UVMF_CHANGE_ME : Color can be applied to transaction entries based on content, example below + // case() + // 1 : $add_color(transaction_view_h,"red"); + // default : $add_color(transaction_view_h,"grey"); + // endcase + // UVMF_CHANGE_ME : Eliminate transaction variables not wanted in transaction viewing in the waveform viewer + $add_attribute(transaction_view_h,awvalid,"awvalid"); + $add_attribute(transaction_view_h,awready,"awready"); + $add_attribute(transaction_view_h,awaddr,"awaddr"); + $add_attribute(transaction_view_h,awsize,"awsize"); + $add_attribute(transaction_view_h,awburst,"awburst"); + $add_attribute(transaction_view_h,awcache,"awcache"); + $add_attribute(transaction_view_h,awprot,"awprot"); + $add_attribute(transaction_view_h,awid,"awid"); + $add_attribute(transaction_view_h,awlen,"awlen"); + $add_attribute(transaction_view_h,awlock,"awlock"); + $add_attribute(transaction_view_h,awqos,"awqos"); + $add_attribute(transaction_view_h,awregion,"awregion"); + $add_attribute(transaction_view_h,awuser,"awuser"); + $add_attribute(transaction_view_h,wvalid,"wvalid"); + $add_attribute(transaction_view_h,wready,"wready"); + $add_attribute(transaction_view_h,wlast,"wlast"); + $add_attribute(transaction_view_h,wdata,"wdata"); + $add_attribute(transaction_view_h,wstrb,"wstrb"); + $add_attribute(transaction_view_h,wid,"wid"); + $add_attribute(transaction_view_h,wuser,"wuser"); + $add_attribute(transaction_view_h,bwvalid,"bwvalid"); + $add_attribute(transaction_view_h,bwready,"bwready"); + $add_attribute(transaction_view_h,bresp,"bresp"); + $add_attribute(transaction_view_h,bid,"bid"); + $add_attribute(transaction_view_h,buser,"buser"); + $add_attribute(transaction_view_h,arvalid,"arvalid"); + $add_attribute(transaction_view_h,aready,"aready"); + $add_attribute(transaction_view_h,araddr,"araddr"); + $add_attribute(transaction_view_h,arsize,"arsize"); + $add_attribute(transaction_view_h,arburst,"arburst"); + $add_attribute(transaction_view_h,arcache,"arcache"); + $add_attribute(transaction_view_h,arprot,"arprot"); + $add_attribute(transaction_view_h,arid,"arid"); + $add_attribute(transaction_view_h,arlen,"arlen"); + $add_attribute(transaction_view_h,arlock,"arlock"); + $add_attribute(transaction_view_h,arqos,"arqos"); + $add_attribute(transaction_view_h,aregion,"aregion"); + $add_attribute(transaction_view_h,aruser,"aruser"); + $add_attribute(transaction_view_h,rvalid,"rvalid"); + $add_attribute(transaction_view_h,rready,"rready"); + $add_attribute(transaction_view_h,rlast,"rlast"); + $add_attribute(transaction_view_h,rdata,"rdata"); + $add_attribute(transaction_view_h,rid,"rid"); + $add_attribute(transaction_view_h,ruser,"ruser"); + $add_attribute(transaction_view_h,rresp,"rresp"); + // pragma uvmf custom add_to_wave end + $end_transaction(transaction_view_h,end_time); + $free_transaction(transaction_view_h); + `endif // QUESTA + endfunction + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/verification_ip/interface_packages/axi_s_pkg/src/axi_s_transaction_coverage.svh b/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/verification_ip/interface_packages/axi_s_pkg/src/axi_s_transaction_coverage.svh new file mode 100644 index 00000000..03e4a490 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/verification_ip/interface_packages/axi_s_pkg/src/axi_s_transaction_coverage.svh @@ -0,0 +1,129 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This class records axi_s transaction information using +// a covergroup named axi_s_transaction_cg. An instance of this +// coverage component is instantiated in the uvmf_parameterized_agent +// if the has_coverage flag is set. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class axi_s_transaction_coverage #( + int AW_WIDTH = 32, + int LEN = 8, + int DATA_WIDTH = 32, + int X = 16 + ) extends uvm_subscriber #(.T(axi_s_transaction #( + .AW_WIDTH(AW_WIDTH), + .LEN(LEN), + .DATA_WIDTH(DATA_WIDTH), + .X(X) + ))); + + `uvm_component_param_utils( axi_s_transaction_coverage #( + AW_WIDTH, + LEN, + DATA_WIDTH, + X + )) + + T coverage_trans; + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + // **************************************************************************** + covergroup axi_s_transaction_cg; + // pragma uvmf custom covergroup begin + // UVMF_CHANGE_ME : Add coverage bins, crosses, exclusions, etc. according to coverage needs. + option.auto_bin_max=1024; + option.per_instance=1; + awvalid: coverpoint coverage_trans.awvalid; + awready: coverpoint coverage_trans.awready; + awaddr: coverpoint coverage_trans.awaddr; + awsize: coverpoint coverage_trans.awsize; + awburst: coverpoint coverage_trans.awburst; + awcache: coverpoint coverage_trans.awcache; + awprot: coverpoint coverage_trans.awprot; + awid: coverpoint coverage_trans.awid; + awlen: coverpoint coverage_trans.awlen; + awlock: coverpoint coverage_trans.awlock; + awqos: coverpoint coverage_trans.awqos; + awregion: coverpoint coverage_trans.awregion; + awuser: coverpoint coverage_trans.awuser; + wvalid: coverpoint coverage_trans.wvalid; + wready: coverpoint coverage_trans.wready; + wlast: coverpoint coverage_trans.wlast; + wdata: coverpoint coverage_trans.wdata; + wstrb: coverpoint coverage_trans.wstrb; + wid: coverpoint coverage_trans.wid; + wuser: coverpoint coverage_trans.wuser; + bwvalid: coverpoint coverage_trans.bwvalid; + bwready: coverpoint coverage_trans.bwready; + bresp: coverpoint coverage_trans.bresp; + bid: coverpoint coverage_trans.bid; + buser: coverpoint coverage_trans.buser; + arvalid: coverpoint coverage_trans.arvalid; + aready: coverpoint coverage_trans.aready; + araddr: coverpoint coverage_trans.araddr; + arsize: coverpoint coverage_trans.arsize; + arburst: coverpoint coverage_trans.arburst; + arcache: coverpoint coverage_trans.arcache; + arprot: coverpoint coverage_trans.arprot; + arid: coverpoint coverage_trans.arid; + arlen: coverpoint coverage_trans.arlen; + arlock: coverpoint coverage_trans.arlock; + arqos: coverpoint coverage_trans.arqos; + aregion: coverpoint coverage_trans.aregion; + aruser: coverpoint coverage_trans.aruser; + rvalid: coverpoint coverage_trans.rvalid; + rready: coverpoint coverage_trans.rready; + rlast: coverpoint coverage_trans.rlast; + rdata: coverpoint coverage_trans.rdata; + rid: coverpoint coverage_trans.rid; + ruser: coverpoint coverage_trans.ruser; + rresp: coverpoint coverage_trans.rresp; + // pragma uvmf custom covergroup end + endgroup + + // **************************************************************************** + // FUNCTION : new() + // This function is the standard SystemVerilog constructor. + // + function new(string name="", uvm_component parent=null); + super.new(name,parent); + axi_s_transaction_cg=new; + `uvm_warning("COVERAGE_MODEL_REVIEW", "A covergroup has been constructed which may need review because of either generation or re-generation with merging. Please note that transaction variables added as a result of re-generation and merging are not automatically added to the covergroup. Remove this warning after the covergroup has been reviewed.") + endfunction + + // **************************************************************************** + // FUNCTION : build_phase() + // This function is the standard UVM build_phase. + // + function void build_phase(uvm_phase phase); + axi_s_transaction_cg.set_inst_name($sformatf("axi_s_transaction_cg_%s",get_full_name())); + endfunction + + // **************************************************************************** + // FUNCTION: write (T t) + // This function is automatically executed when a transaction arrives on the + // analysis_export. It copies values from the variables in the transaction + // to local variables used to collect functional coverage. + // + virtual function void write (T t); + `uvm_info("COV","Received transaction",UVM_HIGH); + coverage_trans = t; + axi_s_transaction_cg.sample(); + endfunction + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/verification_ip/interface_packages/axi_s_pkg/src/axi_s_typedefs.svh b/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/verification_ip/interface_packages/axi_s_pkg/src/axi_s_typedefs.svh new file mode 100644 index 00000000..43d85640 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/verification_ip/interface_packages/axi_s_pkg/src/axi_s_typedefs.svh @@ -0,0 +1,20 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: +// This file contains defines and typedefs to be compiled for use in +// the simulation running on the host server when using Veloce. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// + + +// pragma uvmf custom additional begin +// pragma uvmf custom additional end + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/verification_ip/interface_packages/axi_s_pkg/src/axi_s_typedefs_hdl.svh b/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/verification_ip/interface_packages/axi_s_pkg/src/axi_s_typedefs_hdl.svh new file mode 100644 index 00000000..74738c8c --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/verification_ip/interface_packages/axi_s_pkg/src/axi_s_typedefs_hdl.svh @@ -0,0 +1,21 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: +// This file contains defines and typedefs to be compiled for use in +// the simulation running on the emulator when using Veloce. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// + + + +// pragma uvmf custom additional begin +// pragma uvmf custom additional end + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/verification_ip/interface_packages/axi_s_pkg/yaml/axi_s_interface.yaml b/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/verification_ip/interface_packages/axi_s_pkg/yaml/axi_s_interface.yaml new file mode 100644 index 00000000..5f0bb407 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/verification_ip/interface_packages/axi_s_pkg/yaml/axi_s_interface.yaml @@ -0,0 +1,481 @@ +uvmf: + interfaces: + axi_s: + clock: axi_clk + config_constraints: [] + config_vars: [] + existing_library_component: 'True' + gen_inbound_streaming_driver: 'False' + hdl_pkg_parameters: [] + hdl_typedefs: [] + hvl_pkg_parameters: [] + hvl_typedefs: [] + parameters: + - name: AW_WIDTH + type: int + value: '32' + - name: LEN + type: int + value: '8' + - name: DATA_WIDTH + type: int + value: '32' + - name: X + type: int + value: '16' + ports: + - dir: input + name: awvalid + reset_value: '''bz' + width: '1' + - dir: output + name: awready + reset_value: '''bz' + width: '1' + - dir: input + name: awaddr + reset_value: '''bz' + width: AW_WIDTH + - dir: input + name: awsize + reset_value: '''bz' + width: '3' + - dir: input + name: awburst + reset_value: '''bz' + width: '2' + - dir: input + name: awcache + reset_value: '''bz' + width: '4' + - dir: input + name: awprot + reset_value: '''bz' + width: '3' + - dir: input + name: awid + reset_value: '''bz' + width: X + - dir: input + name: awlen + reset_value: '''bz' + width: LEN + - dir: input + name: awlock + reset_value: '''bz' + width: '1' + - dir: input + name: awqos + reset_value: '''bz' + width: '4' + - dir: input + name: awregion + reset_value: '''bz' + width: '4' + - dir: input + name: awuser + reset_value: '''bz' + width: X + - dir: input + name: wvalid + reset_value: '''bz' + width: '1' + - dir: output + name: wready + reset_value: '''bz' + width: '1' + - dir: input + name: wlast + reset_value: '''bz' + width: '1' + - dir: input + name: wdata + reset_value: '''bz' + width: DATA_WIDTH + - dir: input + name: wstrb + reset_value: '''bz' + width: DATA_WIDTH/8 + - dir: input + name: wid + reset_value: '''bz' + width: X + - dir: input + name: wuser + reset_value: '''bz' + width: X + - dir: output + name: bwvalid + reset_value: '''bz' + width: '1' + - dir: output + name: bwready + reset_value: '''bz' + width: '1' + - dir: input + name: bresp + reset_value: '''bz' + width: '2' + - dir: output + name: bid + reset_value: '''bz' + width: X + - dir: output + name: buser + reset_value: '''bz' + width: X + - dir: input + name: arvalid + reset_value: '''bz' + width: '1' + - dir: output + name: aready + reset_value: '''bz' + width: '1' + - dir: input + name: araddr + reset_value: '''bz' + width: AW_WIDTH + - dir: input + name: arsize + reset_value: '''bz' + width: '3' + - dir: input + name: arburst + reset_value: '''bz' + width: '2' + - dir: input + name: arcache + reset_value: '''bz' + width: '4' + - dir: input + name: arprot + reset_value: '''bz' + width: '3' + - dir: input + name: arid + reset_value: '''bz' + width: X + - dir: input + name: arlen + reset_value: '''bz' + width: LEN + - dir: input + name: arlock + reset_value: '''bz' + width: '1' + - dir: input + name: arqos + reset_value: '''bz' + width: '4' + - dir: input + name: aregion + reset_value: '''bz' + width: '4' + - dir: input + name: aruser + reset_value: '''bz' + width: X + - dir: output + name: rvalid + reset_value: '''bz' + width: '1' + - dir: input + name: rready + reset_value: '''bz' + width: '1' + - dir: output + name: rlast + reset_value: '''bz' + width: '1' + - dir: output + name: rdata + reset_value: '''bz' + width: DATA_WIDTH + - dir: output + name: rid + reset_value: '''bz' + width: X + - dir: output + name: ruser + reset_value: '''bz' + width: X + - dir: output + name: rresp + reset_value: '''bz' + width: '2' + reset: rst + reset_assertion_level: 'False' + transaction_constraints: [] + transaction_vars: + - comment: '' + iscompare: 'False' + isrand: 'False' + name: awvalid + type: bit + unpacked_dimension: '' + - comment: '' + iscompare: 'False' + isrand: 'False' + name: awready + type: bit + unpacked_dimension: '' + - comment: '' + iscompare: 'False' + isrand: 'False' + name: awaddr + type: bit [AW_WIDTH-1:0] + unpacked_dimension: '' + - comment: '' + iscompare: 'False' + isrand: 'False' + name: awsize + type: bit + unpacked_dimension: '' + - comment: '' + iscompare: 'False' + isrand: 'False' + name: awburst + type: bit + unpacked_dimension: '' + - comment: '' + iscompare: 'False' + isrand: 'False' + name: awcache + type: bit + unpacked_dimension: '' + - comment: '' + iscompare: 'False' + isrand: 'False' + name: awprot + type: bit + unpacked_dimension: '' + - comment: '' + iscompare: 'False' + isrand: 'False' + name: awid + type: bit [X-1:0] + unpacked_dimension: '' + - comment: '' + iscompare: 'False' + isrand: 'False' + name: awlen + type: bit [LEN-1:0] + unpacked_dimension: '' + - comment: '' + iscompare: 'False' + isrand: 'False' + name: awlock + type: bit + unpacked_dimension: '' + - comment: '' + iscompare: 'False' + isrand: 'False' + name: awqos + type: bit + unpacked_dimension: '' + - comment: '' + iscompare: 'False' + isrand: 'False' + name: awregion + type: bit + unpacked_dimension: '' + - comment: '' + iscompare: 'False' + isrand: 'False' + name: awuser + type: bit [X-1:0] + unpacked_dimension: '' + - comment: '' + iscompare: 'False' + isrand: 'False' + name: wvalid + type: bit + unpacked_dimension: '' + - comment: '' + iscompare: 'False' + isrand: 'False' + name: wready + type: bit + unpacked_dimension: '' + - comment: '' + iscompare: 'False' + isrand: 'False' + name: wlast + type: bit + unpacked_dimension: '' + - comment: '' + iscompare: 'False' + isrand: 'False' + name: wdata + type: bit [DATA_WIDTH-1:0] + unpacked_dimension: '' + - comment: '' + iscompare: 'False' + isrand: 'False' + name: wstrb + type: bit [DATA_WIDTH/8-1:0] + unpacked_dimension: '' + - comment: '' + iscompare: 'False' + isrand: 'False' + name: wid + type: bit [X-1:0] + unpacked_dimension: '' + - comment: '' + iscompare: 'False' + isrand: 'False' + name: wuser + type: bit [X-1:0] + unpacked_dimension: '' + - comment: '' + iscompare: 'False' + isrand: 'False' + name: bwvalid + type: bit + unpacked_dimension: '' + - comment: '' + iscompare: 'False' + isrand: 'False' + name: bwready + type: bit + unpacked_dimension: '' + - comment: '' + iscompare: 'False' + isrand: 'True' + name: bresp + type: bit + unpacked_dimension: '' + - comment: '' + iscompare: 'False' + isrand: 'False' + name: bid + type: bit [X-1:0] + unpacked_dimension: '' + - comment: '' + iscompare: 'False' + isrand: 'True' + name: buser + type: bit [X-1:0] + unpacked_dimension: '' + - comment: '' + iscompare: 'False' + isrand: 'False' + name: arvalid + type: bit + unpacked_dimension: '' + - comment: '' + iscompare: 'False' + isrand: 'False' + name: aready + type: bit + unpacked_dimension: '' + - comment: '' + iscompare: 'False' + isrand: 'True' + name: araddr + type: bit [AW_WIDTH-1:0] + unpacked_dimension: '' + - comment: '' + iscompare: 'False' + isrand: 'True' + name: arsize + type: bit + unpacked_dimension: '' + - comment: '' + iscompare: 'False' + isrand: 'True' + name: arburst + type: bit + unpacked_dimension: '' + - comment: '' + iscompare: 'False' + isrand: 'True' + name: arcache + type: bit + unpacked_dimension: '' + - comment: '' + iscompare: 'False' + isrand: 'True' + name: arprot + type: bit + unpacked_dimension: '' + - comment: '' + iscompare: 'False' + isrand: 'True' + name: arid + type: bit [X-1:0] + unpacked_dimension: '' + - comment: '' + iscompare: 'False' + isrand: 'True' + name: arlen + type: bit [LEN-1:0] + unpacked_dimension: '' + - comment: '' + iscompare: 'False' + isrand: 'True' + name: arlock + type: bit + unpacked_dimension: '' + - comment: '' + iscompare: 'False' + isrand: 'True' + name: arqos + type: bit + unpacked_dimension: '' + - comment: '' + iscompare: 'False' + isrand: 'False' + name: aregion + type: bit + unpacked_dimension: '' + - comment: '' + iscompare: 'False' + isrand: 'False' + name: aruser + type: bit [X-1:0] + unpacked_dimension: '' + - comment: '' + iscompare: 'False' + isrand: 'False' + name: rvalid + type: bit + unpacked_dimension: '' + - comment: '' + iscompare: 'False' + isrand: 'False' + name: rready + type: bit + unpacked_dimension: '' + - comment: '' + iscompare: 'False' + isrand: 'False' + name: rlast + type: bit + unpacked_dimension: '' + - comment: '' + iscompare: 'False' + isrand: 'True' + name: rdata + type: bit [DATA_WIDTH-1:0] + unpacked_dimension: '' + - comment: '' + iscompare: 'False' + isrand: 'True' + name: rid + type: bit [X-1:0] + unpacked_dimension: '' + - comment: '' + iscompare: 'False' + isrand: 'True' + name: ruser + type: bit [X-1:0] + unpacked_dimension: '' + - comment: '' + iscompare: 'False' + isrand: 'True' + name: rresp + type: bit + unpacked_dimension: '' + use_dpi_link: 'False' diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/verification_ip/interface_packages/wb_m_pkg/.project b/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/verification_ip/interface_packages/wb_m_pkg/.project new file mode 100644 index 00000000..fd80e149 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/verification_ip/interface_packages/wb_m_pkg/.project @@ -0,0 +1,30 @@ + + + wb_m_pkg + + + + + + org.python.pydev.PyDevBuilder + + + + + net.sf.sveditor.core.SVProjectBuilder + + + + + + net.sf.sveditor.core.SVNature + org.python.pydev.pythonNature + + + + UVMF_VIP_LIBRARY_HOME + $%7BPARENT-2-PROJECT_LOC%7D + + + + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/verification_ip/interface_packages/wb_m_pkg/.svproject b/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/verification_ip/interface_packages/wb_m_pkg/.svproject new file mode 100644 index 00000000..51ce829e --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/verification_ip/interface_packages/wb_m_pkg/.svproject @@ -0,0 +1,16 @@ + + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/verification_ip/interface_packages/wb_m_pkg/Makefile b/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/verification_ip/interface_packages/wb_m_pkg/Makefile new file mode 100644 index 00000000..c00e8a8f --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/verification_ip/interface_packages/wb_m_pkg/Makefile @@ -0,0 +1,66 @@ +# wb_m interface packages source +# pragma uvmf custom additional begin +# pragma uvmf custom additional end + +wb_m_PKG = \ + +incdir+$(UVMF_VIP_LIBRARY_HOME)/interface_packages/wb_m_pkg \ + -F $(UVMF_VIP_LIBRARY_HOME)/interface_packages/wb_m_pkg/wb_m_filelist_hvl.f + +wb_m_PKG_HDL = \ + +incdir+$(UVMF_VIP_LIBRARY_HOME)/interface_packages/wb_m_pkg \ + -F $(UVMF_VIP_LIBRARY_HOME)/interface_packages/wb_m_pkg/wb_m_filelist_hdl.f + +wb_m_PKG_XRTL = \ + +incdir+$(UVMF_VIP_LIBRARY_HOME)/interface_packages/wb_m_pkg \ + -F $(UVMF_VIP_LIBRARY_HOME)/interface_packages/wb_m_pkg/wb_m_filelist_xrtl.f + +COMP_wb_m_PKG_TGT_0 = q_comp_wb_m_pkg +COMP_wb_m_PKG_TGT_1 = v_comp_wb_m_pkg +COMP_wb_m_PKG_TGT = $(COMP_wb_m_PKG_TGT_$(USE_VELOCE)) + +comp_wb_m_pkg: $(COMP_wb_m_PKG_TGT) + +q_comp_wb_m_pkg: + $(HDL_COMP_CMD) $(wb_m_PKG_HDL) + $(HVL_COMP_CMD) $(wb_m_PKG) + $(HDL_COMP_CMD) $(wb_m_PKG_XRTL) + +v_comp_wb_m_pkg: + $(HVL_COMP_CMD) $(wb_m_PKG_HDL) + $(HVL_COMP_CMD) $(wb_m_PKG) + $(VELANALYZE_CMD) $(wb_m_PKG_HDL) + $(VELANALYZE_HVL_CMD) $(wb_m_PKG) + $(HDL_COMP_CMD) $(wb_m_PKG_XRTL) + +ifeq ($(MTI_VCO_MODE),64) + GCC_COMP_ARCH = -m64 +else + GCC_COMP_ARCH = -m32 +endif + +export wb_m_IF_DPI_SRC ?= $(UVMF_VIP_LIBRARY_HOME)/interface_packages/wb_m_pkg/dpi + +C_FILE_COMPILE_LIST_wb_m_pkg = \ + +O_FILE_COMPILE_LIST_wb_m_pkg = $(notdir $(C_FILE_COMPILE_LIST_wb_m_pkg:.c=.o)) + +GCC_COMP_ARGS_wb_m_pkg += -I$(wb_m_IF_DPI_SRC) \ + -fPIC + +GCC_COMP_ARGS_wb_m_pkg += $(wb_m_IF_GCC_COMP_ARGUMENTS) + +GCC_LINK_ARGS_wb_m_pkg += \ + \ + -o .so + +comp_wb_m_pkg_c_files: + @echo "--------------------------------" + @echo "Compiling Interface C source" + @echo "--------------------------------" + gcc $(GCC_COMP_ARCH) $(GCC_COMP_ARGS_wb_m_pkg) $(C_FILE_COMPILE_LIST_wb_m_pkg) + @echo "--------------------------------" + @echo "Linking Interface C objects into a shared object" + @echo "--------------------------------" + gcc $(GCC_COMP_ARCH) $(GCC_LINK_ARGS_wb_m_pkg) $(O_FILE_COMPILE_LIST_wb_m_pkg) + @echo "--------------------------------" + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/verification_ip/interface_packages/wb_m_pkg/compile.do b/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/verification_ip/interface_packages/wb_m_pkg/compile.do new file mode 100644 index 00000000..6e931196 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/verification_ip/interface_packages/wb_m_pkg/compile.do @@ -0,0 +1,14 @@ +# Tcl do file for compile of wb_m interface + +# pragma uvmf custom additional begin +# pragma uvmf custom additional end + + +vlog -sv -timescale 1ps/1ps -suppress 2223,2286 +incdir+$env(UVMF_VIP_LIBRARY_HOME)/interface_packages/wb_m_pkg \ + -F $env(UVMF_VIP_LIBRARY_HOME)/interface_packages/wb_m_pkg/wb_m_filelist_hdl.f + +vlog -sv -timescale 1ps/1ps -suppress 2223,2286 +incdir+$env(UVMF_VIP_LIBRARY_HOME)/interface_packages/wb_m_pkg \ + -F $env(UVMF_VIP_LIBRARY_HOME)/interface_packages/wb_m_pkg/wb_m_filelist_hvl.f + +vlog -sv -timescale 1ps/1ps -suppress 2223,2286 +incdir+$env(UVMF_VIP_LIBRARY_HOME)/interface_packages/wb_m_pkg \ + -F $env(UVMF_VIP_LIBRARY_HOME)/interface_packages/wb_m_pkg/wb_m_filelist_xrtl.f \ No newline at end of file diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/verification_ip/interface_packages/wb_m_pkg/src/wb_m2reg_adapter.svh b/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/verification_ip/interface_packages/wb_m_pkg/src/wb_m2reg_adapter.svh new file mode 100644 index 00000000..5469da22 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/verification_ip/interface_packages/wb_m_pkg/src/wb_m2reg_adapter.svh @@ -0,0 +1,113 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: +// This file contains the UVM register adapter for the wb_m interface. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class wb_m2reg_adapter #( + int WB_ADDR_WIDTH = 32, + int WB_DATA_WIDTH = 16 + ) extends uvm_reg_adapter; + + `uvm_object_param_utils( wb_m2reg_adapter #( + WB_ADDR_WIDTH, + WB_DATA_WIDTH + )) + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + //-------------------------------------------------------------------- + // new + //-------------------------------------------------------------------- + function new (string name = "wb_m2reg_adapter" ); + super.new(name); + // pragma uvmf custom new begin + // UVMF_CHANGE_ME : Configure the adapter regarding byte enables and provides response. + + // Does the protocol the Agent is modeling support byte enables? + // 0 = NO + // 1 = YES + supports_byte_enable = 0; + + // Does the Agent's Driver provide separate response sequence items? + // i.e. Does the driver call seq_item_port.put() + // and do the sequences call get_response()? + // 0 = NO + // 1 = YES + provides_responses = 0; + // pragma uvmf custom new end + + endfunction: new + + //-------------------------------------------------------------------- + // reg2bus + //-------------------------------------------------------------------- + virtual function uvm_sequence_item reg2bus(const ref uvm_reg_bus_op rw); + + wb_m_transaction #( + .WB_ADDR_WIDTH(WB_ADDR_WIDTH), + .WB_DATA_WIDTH(WB_DATA_WIDTH) + ) trans_h = wb_m_transaction #( + .WB_ADDR_WIDTH(WB_ADDR_WIDTH), + .WB_DATA_WIDTH(WB_DATA_WIDTH) + )::type_id::create("trans_h"); + + // pragma uvmf custom reg2bus begin + // UVMF_CHANGE_ME : Fill in the reg2bus adapter mapping registe fields to protocol fields. + + //Adapt the following for your sequence item type + // trans_h.op = (rw.kind == UVM_READ) ? WB_READ : WB_WRITE; + //Copy over address + // trans_h.addr = rw.addr; + //Copy over write data + // trans_h.data = rw.data; + + // pragma uvmf custom reg2bus end + + // Return the adapted transaction + return trans_h; + + endfunction: reg2bus + + //-------------------------------------------------------------------- + // bus2reg + //-------------------------------------------------------------------- + virtual function void bus2reg(uvm_sequence_item bus_item, + ref uvm_reg_bus_op rw); + wb_m_transaction #( + .WB_ADDR_WIDTH(WB_ADDR_WIDTH), + .WB_DATA_WIDTH(WB_DATA_WIDTH) + ) trans_h; + if (!$cast(trans_h, bus_item)) begin + `uvm_fatal("ADAPT","Provided bus_item is not of the correct type") + return; + end + // pragma uvmf custom bus2reg begin + // UVMF_CHANGE_ME : Fill in the bus2reg adapter mapping protocol fields to register fields. + //Adapt the following for your sequence item type + //Copy over instruction type + // rw.kind = (trans_h.op == WB_WRITE) ? UVM_WRITE : UVM_READ; + //Copy over address + // rw.addr = trans_h.addr; + //Copy over read data + // rw.data = trans_h.data; + //Check for errors on the bus and return UVM_NOT_OK if there is an error + // rw.status = UVM_IS_OK; + // pragma uvmf custom bus2reg end + + endfunction: bus2reg + +endclass : wb_m2reg_adapter + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/verification_ip/interface_packages/wb_m_pkg/src/wb_m_agent.svh b/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/verification_ip/interface_packages/wb_m_pkg/src/wb_m_agent.svh new file mode 100644 index 00000000..0417dbe8 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/verification_ip/interface_packages/wb_m_pkg/src/wb_m_agent.svh @@ -0,0 +1,74 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: Protocol specific agent class definition +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class wb_m_agent #( + int WB_ADDR_WIDTH = 32, + int WB_DATA_WIDTH = 16 + ) extends uvmf_parameterized_agent #( + .CONFIG_T(wb_m_configuration #( + .WB_ADDR_WIDTH(WB_ADDR_WIDTH), + .WB_DATA_WIDTH(WB_DATA_WIDTH) + )), + .DRIVER_T(wb_m_driver #( + .WB_ADDR_WIDTH(WB_ADDR_WIDTH), + .WB_DATA_WIDTH(WB_DATA_WIDTH) + )), + .MONITOR_T(wb_m_monitor #( + .WB_ADDR_WIDTH(WB_ADDR_WIDTH), + .WB_DATA_WIDTH(WB_DATA_WIDTH) + )), + .COVERAGE_T(wb_m_transaction_coverage #( + .WB_ADDR_WIDTH(WB_ADDR_WIDTH), + .WB_DATA_WIDTH(WB_DATA_WIDTH) + )), + .TRANS_T(wb_m_transaction #( + .WB_ADDR_WIDTH(WB_ADDR_WIDTH), + .WB_DATA_WIDTH(WB_DATA_WIDTH) + )) + ); + + `uvm_component_param_utils( wb_m_agent #( + WB_ADDR_WIDTH, + WB_DATA_WIDTH + )) + +// pragma uvmf custom class_item_additional begin +// pragma uvmf custom class_item_additional end + +// **************************************************************************** +// FUNCTION : new() +// This function is the standard SystemVerilog constructor. +// + function new( string name = "", uvm_component parent = null ); + super.new( name, parent ); + endfunction + +// **************************************************************************** + // FUNCTION: build_phase + virtual function void build_phase(uvm_phase phase); +// pragma uvmf custom build_phase_pre_super begin +// pragma uvmf custom build_phase_pre_super end + super.build_phase(phase); + if (configuration.active_passive == ACTIVE) begin + // Place sequencer handle into configuration object + // so that it may be retrieved from configuration + // rather than using uvm_config_db + configuration.sequencer = this.sequencer; + end + endfunction + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/verification_ip/interface_packages/wb_m_pkg/src/wb_m_configuration.svh b/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/verification_ip/interface_packages/wb_m_pkg/src/wb_m_configuration.svh new file mode 100644 index 00000000..fa1ede60 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/verification_ip/interface_packages/wb_m_pkg/src/wb_m_configuration.svh @@ -0,0 +1,203 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This class contains all variables and functions used +// to configure the wb_m agent and its bfm's. It gets the +// bfm's from the uvm_config_db for use by the agent. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class wb_m_configuration #( + int WB_ADDR_WIDTH = 32, + int WB_DATA_WIDTH = 16 + ) extends uvmf_parameterized_agent_configuration_base #( + .DRIVER_BFM_BIND_T(virtual wb_m_driver_bfm #( + .WB_ADDR_WIDTH(WB_ADDR_WIDTH), + .WB_DATA_WIDTH(WB_DATA_WIDTH) + )), + .MONITOR_BFM_BIND_T( virtual wb_m_monitor_bfm #( + .WB_ADDR_WIDTH(WB_ADDR_WIDTH), + .WB_DATA_WIDTH(WB_DATA_WIDTH) + ))); + + `uvm_object_param_utils( wb_m_configuration #( + WB_ADDR_WIDTH, + WB_DATA_WIDTH + )) + + + // Sequencer handle populated by agent + uvm_sequencer #(wb_m_transaction #( + .WB_ADDR_WIDTH(WB_ADDR_WIDTH), + .WB_DATA_WIDTH(WB_DATA_WIDTH) + ) ) sequencer; + + //Constraints for the configuration variables: + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + covergroup wb_m_configuration_cg; + // pragma uvmf custom covergroup begin + option.auto_bin_max=1024; + // pragma uvmf custom covergroup end + endgroup + + //******************************************************************* + //******************************************************************* + // Structure used to pass configuration variables to monitor and driver BFM's. + // Use to_struct function to pack variables into structure. + // Use from_struct function to unpack variables from structure. + // This structure is defined in wb_m_macros.svh + `wb_m_CONFIGURATION_STRUCT + wb_m_configuration_s wb_m_configuration_struct; + //******************************************************************* + // FUNCTION: to_struct() + // This function packs variables into a wb_m_configuration_s + // structure. The function returns the handle to the wb_m_configuration_struct. + // This function is defined in wb_m_macros.svh + `wb_m_CONFIGURATION_TO_STRUCT_FUNCTION + //******************************************************************* + // FUNCTION: from_struct() + // This function unpacks the struct provided as an argument into + // variables of this class. + // This function is defined in wb_m_macros.svh + `wb_m_CONFIGURATION_FROM_STRUCT_FUNCTION + + // **************************************************************************** + // FUNCTION : new() + // This function is the standard SystemVerilog constructor. + // + function new( string name = "" ); + super.new( name ); + // Construct the covergroup for this configuration class + wb_m_configuration_cg = new; + endfunction + + // **************************************************************************** + // FUNCTION: post_randomize() + // This function is automatically called after the randomize() function + // is executed. + // + function void post_randomize(); + super.post_randomize(); + wb_m_configuration_cg.sample(); + endfunction + + // **************************************************************************** + // FUNCTION: initialize + // This function causes the configuration to retrieve + // its virtual interface handle from the uvm_config_db. + // This function also makes itself available to its + // agent through the uvm_config_db. + // + // ARGUMENTS: + // uvmf_active_passive_t activity: + // This argument identifies the simulation level + // as either BLOCK, CHIP, SIMULATION, etc. + // + // AGENT_PATH: + // This argument identifies the path to this + // configurations agent. This configuration + // makes itself available to the agent specified + // by agent_path by placing itself into the + // uvm_config_db. + // + // INTERFACE_NAME: + // This argument identifies the string name of + // this configurations BFM's. This string + // name is used to retrieve the driver and + // monitor BFM from the uvm_config_db. + // + virtual function void initialize(uvmf_active_passive_t activity, + string agent_path, + string interface_name); + + super.initialize( activity, agent_path, interface_name); + // The covergroup is given the same name as the interface + wb_m_configuration_cg.set_inst_name(interface_name); + + // This configuration places itself into the uvm_config_db for the agent, identified by the agent_path variable, to retrieve. + uvm_config_db #( wb_m_configuration #( + .WB_ADDR_WIDTH(WB_ADDR_WIDTH), + .WB_DATA_WIDTH(WB_DATA_WIDTH) + ) + )::set( null ,agent_path,UVMF_AGENT_CONFIG, this ); + + // This configuration also places itself in the config db using the same identifier used by the interface. This allows users to access + // configuration variables and the interface through the bfm api class rather than directly accessing the BFM. This is useful for + // accessingthe BFM when using Veloce + uvm_config_db #( wb_m_configuration #( + .WB_ADDR_WIDTH(WB_ADDR_WIDTH), + .WB_DATA_WIDTH(WB_DATA_WIDTH) + ) + )::set( null ,UVMF_CONFIGURATIONS, interface_name, this ); + + wb_m_configuration_cg.set_inst_name($sformatf("wb_m_configuration_cg_%s",get_full_name())); + +// This code is to aid in debugging parameter mismatches between the BFM and its corresponding agent. +// Enable this debug by setting UVM_VERBOSITY to UVM_DEBUG +// Setting UVM_VERBOSITY to UVM_DEBUG causes all BFM's and all agents to display their parameter settings. +// All of the messages from this feature have a UVM messaging id value of "CFG" +// The transcript or run.log can be parsed to ensure BFM parameter settings match its corresponding agents parameter settings. + `uvm_info("CFG", + $psprintf("The agent at '%s' is using interface named %s has the following parameters: WB_ADDR_WIDTH=%x WB_DATA_WIDTH=%x ", agent_path, interface_name, WB_ADDR_WIDTH ,WB_DATA_WIDTH ), + UVM_DEBUG) + + // pragma uvmf custom initialize begin + // This controls whether or not the agent returns a transaction handle in the driver when calling + // item_done() back into the sequencer or not. If set to 1, a transaction is sent back which means + // the sequence on the other end must use the get_response() part of the driver/sequence API. If + // this doesn't occur, there will eventually be response_queue overflow errors during the test. + return_transaction_response = 1'b0; + + // pragma uvmf custom initialize end + + endfunction + + // **************************************************************************** + // TASK: wait_for_reset + // *[Required]* Blocks until reset is released. The wait_for_reset operation is performed + // by a task in the monitor bfm. + virtual task wait_for_reset(); + monitor_bfm.wait_for_reset(); + endtask + + // **************************************************************************** + // TASK: wait_for_num_clocks + // *[Required]* Blocks until specified number of clocks have elapsed. The wait_for_num_clocks + // operation is performed by a task in the monitor bfm. + virtual task wait_for_num_clocks(int clocks); + monitor_bfm.wait_for_num_clocks(clocks); + endtask + + // **************************************************************************** + // FUNCTION : convert2string() + // This function is used to convert variables in this class into a string for log messaging. + // + virtual function string convert2string (); + // pragma uvmf custom convert2string begin + return $sformatf(""); + // pragma uvmf custom convert2string end + endfunction + + // **************************************************************************** + // FUNCTION: get_sequencer + function uvm_sequencer #(wb_m_transaction#( + .WB_ADDR_WIDTH(WB_ADDR_WIDTH), + .WB_DATA_WIDTH(WB_DATA_WIDTH) + )) get_sequencer(); + return sequencer; + endfunction + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/verification_ip/interface_packages/wb_m_pkg/src/wb_m_driver.svh b/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/verification_ip/interface_packages/wb_m_pkg/src/wb_m_driver.svh new file mode 100644 index 00000000..ac8bfa95 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/verification_ip/interface_packages/wb_m_pkg/src/wb_m_driver.svh @@ -0,0 +1,109 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This class passes transactions between the sequencer +// and the BFM driver interface. It accesses the driver BFM +// through the bfm handle. This driver +// passes transactions to the driver BFM through the access +// task. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class wb_m_driver #( + int WB_ADDR_WIDTH = 32, + int WB_DATA_WIDTH = 16 + ) extends uvmf_driver_base #( + .CONFIG_T(wb_m_configuration #( + .WB_ADDR_WIDTH(WB_ADDR_WIDTH), + .WB_DATA_WIDTH(WB_DATA_WIDTH) + ) ), + .BFM_BIND_T(virtual wb_m_driver_bfm #( + .WB_ADDR_WIDTH(WB_ADDR_WIDTH), + .WB_DATA_WIDTH(WB_DATA_WIDTH) + ) ), + .REQ(wb_m_transaction #( + .WB_ADDR_WIDTH(WB_ADDR_WIDTH), + .WB_DATA_WIDTH(WB_DATA_WIDTH) + ) ), + .RSP(wb_m_transaction #( + .WB_ADDR_WIDTH(WB_ADDR_WIDTH), + .WB_DATA_WIDTH(WB_DATA_WIDTH) + ) )); + + `uvm_component_param_utils( wb_m_driver #( + WB_ADDR_WIDTH, + WB_DATA_WIDTH + )) +//******************************************************************* +// Macros that define structs located in wb_m_macros.svh +//******************************************************************* +// Initiator macro used by wb_m_driver and wb_m_driver_bfm +// to communicate initiator driven data to wb_m_driver_bfm. +`wb_m_INITIATOR_STRUCT + wb_m_initiator_s wb_m_initiator_struct; +//******************************************************************* +// Responder macro used by wb_m_driver and wb_m_driver_bfm +// to communicate Responder driven data to wb_m_driver_bfm. +`wb_m_RESPONDER_STRUCT + wb_m_responder_s wb_m_responder_struct; + +// pragma uvmf custom class_item_additional begin +// pragma uvmf custom class_item_additional end + +// **************************************************************************** +// This function is the standard SystemVerilog constructor. +// + function new( string name = "", uvm_component parent=null ); + super.new( name, parent ); + endfunction + +// **************************************************************************** +// This function sends configuration object variables to the driver BFM +// using the configuration struct. +// + virtual function void configure(input CONFIG_T cfg); + bfm.configure( cfg.to_struct() ); + endfunction + +// **************************************************************************** +// This function places a handle to this class in the proxy variable in the +// driver BFM. This allows the driver BFM to call tasks and function within this class. +// + virtual function void set_bfm_proxy_handle(); + bfm.proxy = this; endfunction + +// **************************************************************************** +// This task is called by the run_phase in uvmf_driver_base. + virtual task access( inout REQ txn ); +// pragma uvmf custom access begin + if (configuration.initiator_responder==RESPONDER) begin + // Complete current transfer and wait for next transfer + bfm.respond_and_wait_for_next_transfer( + wb_m_initiator_struct, + txn.to_responder_struct() + ); + // Unpack information about initiated transfer received by this responder + txn.from_initiator_struct(wb_m_initiator_struct); + end else begin + // Initiate a transfer and get response + bfm.initiate_and_get_response( + txn.to_initiator_struct(), + wb_m_responder_struct + ); + // Unpack transfer response information received by this initiator + txn.from_responder_struct(wb_m_responder_struct); + end +// pragma uvmf custom access end + endtask + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/verification_ip/interface_packages/wb_m_pkg/src/wb_m_driver_bfm.sv b/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/verification_ip/interface_packages/wb_m_pkg/src/wb_m_driver_bfm.sv new file mode 100644 index 00000000..cbeee25e --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/verification_ip/interface_packages/wb_m_pkg/src/wb_m_driver_bfm.sv @@ -0,0 +1,359 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: +// This interface performs the wb_m signal driving. It is +// accessed by the uvm wb_m driver through a virtual interface +// handle in the wb_m configuration. It drives the singals passed +// in through the port connection named bus of type wb_m_if. +// +// Input signals from the wb_m_if are assigned to an internal input +// signal with a _i suffix. The _i signal should be used for sampling. +// +// The input signal connections are as follows: +// bus.signal -> signal_i +// +// This bfm drives signals with a _o suffix. These signals +// are driven onto signals within wb_m_if based on INITIATOR/RESPONDER and/or +// ARBITRATION/GRANT status. +// +// The output signal connections are as follows: +// signal_o -> bus.signal +// +// +// Interface functions and tasks used by UVM components: +// +// configure: +// This function gets configuration attributes from the +// UVM driver to set any required BFM configuration +// variables such as 'initiator_responder'. +// +// initiate_and_get_response: +// This task is used to perform signaling activity for initiating +// a protocol transfer. The task initiates the transfer, using +// input data from the initiator struct. Then the task captures +// response data, placing the data into the response struct. +// The response struct is returned to the driver class. +// +// respond_and_wait_for_next_transfer: +// This task is used to complete a current transfer as a responder +// and then wait for the initiator to start the next transfer. +// The task uses data in the responder struct to drive protocol +// signals to complete the transfer. The task then waits for +// the next transfer. Once the next transfer begins, data from +// the initiator is placed into the initiator struct and sent +// to the responder sequence for processing to determine +// what data to respond with. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +import uvmf_base_pkg_hdl::*; +import wb_m_pkg_hdl::*; +`include "src/wb_m_macros.svh" + +interface wb_m_driver_bfm #( + int WB_ADDR_WIDTH = 32, + int WB_DATA_WIDTH = 16 + ) + (wb_m_if bus); + // The following pragma and additional ones in-lined further below are for running this BFM on Veloce + // pragma attribute wb_m_driver_bfm partition_interface_xif + +`ifndef XRTL +// This code is to aid in debugging parameter mismatches between the BFM and its corresponding agent. +// Enable this debug by setting UVM_VERBOSITY to UVM_DEBUG +// Setting UVM_VERBOSITY to UVM_DEBUG causes all BFM's and all agents to display their parameter settings. +// All of the messages from this feature have a UVM messaging id value of "CFG" +// The transcript or run.log can be parsed to ensure BFM parameter settings match its corresponding agents parameter settings. +import uvm_pkg::*; +`include "uvm_macros.svh" +initial begin : bfm_vs_agent_parameter_debug + `uvm_info("CFG", + $psprintf("The BFM at '%m' has the following parameters: WB_ADDR_WIDTH=%x WB_DATA_WIDTH=%x ", WB_ADDR_WIDTH,WB_DATA_WIDTH), + UVM_DEBUG) +end +`endif + + // Config value to determine if this is an initiator or a responder + uvmf_initiator_responder_t initiator_responder; + // Custom configuration variables. + // These are set using the configure function which is called during the UVM connect_phase + + logic clock_i; + logic reset_i; + + // Signal list (all signals are capable of being inputs and outputs for the sake + // of supporting both INITIATOR and RESPONDER mode operation. Expectation is that + // directionality in the config file was from the point-of-view of the INITIATOR + + // INITIATOR mode input signals + tri [WB_DATA_WIDTH-1:0] din_i; + reg [WB_DATA_WIDTH-1:0] din_o = 'b0; + tri [WB_DATA_WIDTH-1:0] TGD_I_i; + reg [WB_DATA_WIDTH-1:0] TGD_I_o = 'bz; + tri err_i; + reg err_o = 'b0; + + // INITIATOR mode output signals + tri [WB_DATA_WIDTH-1:0] dout_i; + reg [WB_DATA_WIDTH-1:0] dout_o = 'b0; + tri [WB_DATA_WIDTH-1:0] TGD_O_i; + reg [WB_DATA_WIDTH-1:0] TGD_O_o = 'bz; + tri ack_i; + reg ack_o = 1'b0; + tri [WB_ADDR_WIDTH-1:0] adr_i; + reg [WB_ADDR_WIDTH-1:0] adr_o = 'b0; + tri cyc_i; + reg cyc_o = 0; + tri we_i; + reg we_o = 0; + tri stb_i; + reg stb_o = 0; + tri [WB_DATA_WIDTH/8-1:0] sel_i; + reg [WB_DATA_WIDTH/8-1:0] sel_o = 'b0; + + // Bi-directional signals + + + assign clock_i = bus.clock; + assign reset_i = bus.reset; + + // These are signals marked as 'input' by the config file, but the signals will be + // driven by this BFM if put into RESPONDER mode (flipping all signal directions around) + assign din_i = bus.din; + assign bus.din = (initiator_responder == RESPONDER) ? din_o : 'bz; + assign TGD_I_i = bus.TGD_I; + assign bus.TGD_I = (initiator_responder == RESPONDER) ? TGD_I_o : 'bz; + assign err_i = bus.err; + assign bus.err = (initiator_responder == RESPONDER) ? err_o : 'bz; + + + // These are signals marked as 'output' by the config file, but the outputs will + // not be driven by this BFM unless placed in INITIATOR mode. + assign bus.dout = (initiator_responder == INITIATOR) ? dout_o : 'bz; + assign dout_i = bus.dout; + assign bus.TGD_O = (initiator_responder == INITIATOR) ? TGD_O_o : 'bz; + assign TGD_O_i = bus.TGD_O; + assign bus.ack = (initiator_responder == INITIATOR) ? ack_o : 'bz; + assign ack_i = bus.ack; + assign bus.adr = (initiator_responder == INITIATOR) ? adr_o : 'bz; + assign adr_i = bus.adr; + assign bus.cyc = (initiator_responder == INITIATOR) ? cyc_o : 'bz; + assign cyc_i = bus.cyc; + assign bus.we = (initiator_responder == INITIATOR) ? we_o : 'bz; + assign we_i = bus.we; + assign bus.stb = (initiator_responder == INITIATOR) ? stb_o : 'bz; + assign stb_i = bus.stb; + assign bus.sel = (initiator_responder == INITIATOR) ? sel_o : 'bz; + assign sel_i = bus.sel; + + // Proxy handle to UVM driver + wb_m_pkg::wb_m_driver #( + .WB_ADDR_WIDTH(WB_ADDR_WIDTH), + .WB_DATA_WIDTH(WB_DATA_WIDTH) + ) proxy; + // pragma tbx oneway proxy.my_function_name_in_uvm_driver + + // **************************************************************************** + // **************************************************************************** + // Macros that define structs located in wb_m_macros.svh + // **************************************************************************** + // Struct for passing configuration data from wb_m_driver to this BFM + // **************************************************************************** + `wb_m_CONFIGURATION_STRUCT + // **************************************************************************** + // Structs for INITIATOR and RESPONDER data flow + //******************************************************************* + // Initiator macro used by wb_m_driver and wb_m_driver_bfm + // to communicate initiator driven data to wb_m_driver_bfm. + `wb_m_INITIATOR_STRUCT + wb_m_initiator_s initiator_struct; + // Responder macro used by wb_m_driver and wb_m_driver_bfm + // to communicate Responder driven data to wb_m_driver_bfm. + `wb_m_RESPONDER_STRUCT + wb_m_responder_s responder_struct; + + // **************************************************************************** +// pragma uvmf custom reset_condition_and_response begin + // Always block used to return signals to reset value upon assertion of reset + always @( posedge reset_i ) + begin + // RESPONDER mode output signals + din_o <= 'b0; + TGD_I_o <= 'bz; + err_o <= 'b0; + // INITIATOR mode output signals + dout_o <= 'b0; + TGD_O_o <= 'bz; + ack_o <= 1'b0; + adr_o <= 'b0; + cyc_o <= 0; + we_o <= 0; + stb_o <= 0; + sel_o <= 'b0; + // Bi-directional signals + + end +// pragma uvmf custom reset_condition_and_response end + + // pragma uvmf custom interface_item_additional begin + // pragma uvmf custom interface_item_additional end + + //****************************************************************** + // The configure() function is used to pass agent configuration + // variables to the driver BFM. It is called by the driver within + // the agent at the beginning of the simulation. It may be called + // during the simulation if agent configuration variables are updated + // and the driver BFM needs to be aware of the new configuration + // variables. + // + + function void configure(wb_m_configuration_s wb_m_configuration_arg); // pragma tbx xtf + initiator_responder = wb_m_configuration_arg.initiator_responder; + // pragma uvmf custom configure begin + // pragma uvmf custom configure end + endfunction + +// pragma uvmf custom initiate_and_get_response begin +// **************************************************************************** +// UVMF_CHANGE_ME +// This task is used by an initator. The task first initiates a transfer then +// waits for the responder to complete the transfer. + task initiate_and_get_response( + // This argument passes transaction variables used by an initiator + // to perform the initial part of a protocol transfer. The values + // come from a sequence item created in a sequence. + input wb_m_initiator_s wb_m_initiator_struct, + // This argument is used to send data received from the responder + // back to the sequence item. The sequence item is returned to the sequence. + output wb_m_responder_s wb_m_responder_struct + );// pragma tbx xtf + // + // Members within the wb_m_initiator_struct: + // bit [WB_DATA_WIDTH-1:0] data ; + // bit [(WB_DATA_WIDTH/8)-1:0] byte_select ; + // bit WrENB ; + // bit selslv ; + // Members within the wb_m_responder_struct: + // bit [WB_DATA_WIDTH-1:0] data ; + // bit [(WB_DATA_WIDTH/8)-1:0] byte_select ; + // bit WrENB ; + // bit selslv ; + initiator_struct = wb_m_initiator_struct; + // + // Reference code; + // How to wait for signal value + // while (control_signal == 1'b1) @(posedge clock_i); + // + // How to assign a responder struct member, named xyz, from a signal. + // All available initiator input and inout signals listed. + // Initiator input signals + // wb_m_responder_struct.xyz = din_i; // [WB_DATA_WIDTH-1:0] + // wb_m_responder_struct.xyz = TGD_I_i; // [WB_DATA_WIDTH-1:0] + // wb_m_responder_struct.xyz = err_i; // + // Initiator inout signals + // How to assign a signal from an initiator struct member named xyz. + // All available initiator output and inout signals listed. + // Notice the _o. Those are storage variables that allow for procedural assignment. + // Initiator output signals + // dout_o <= wb_m_initiator_struct.xyz; // [WB_DATA_WIDTH-1:0] + // TGD_O_o <= wb_m_initiator_struct.xyz; // [WB_DATA_WIDTH-1:0] + // ack_o <= wb_m_initiator_struct.xyz; // + // adr_o <= wb_m_initiator_struct.xyz; // [WB_ADDR_WIDTH-1:0] + // cyc_o <= wb_m_initiator_struct.xyz; // + // we_o <= wb_m_initiator_struct.xyz; // + // stb_o <= wb_m_initiator_struct.xyz; // + // sel_o <= wb_m_initiator_struct.xyz; // [WB_DATA_WIDTH/8-1:0] + // Initiator inout signals + // Initiate a transfer using the data received. + @(posedge clock_i); + @(posedge clock_i); + // Wait for the responder to complete the transfer then place the responder data into + // wb_m_responder_struct. + @(posedge clock_i); + @(posedge clock_i); + responder_struct = wb_m_responder_struct; + endtask +// pragma uvmf custom initiate_and_get_response end + +// pragma uvmf custom respond_and_wait_for_next_transfer begin +// **************************************************************************** +// The first_transfer variable is used to prevent completing a transfer in the +// first call to this task. For the first call to this task, there is not +// current transfer to complete. +bit first_transfer=1; + +// UVMF_CHANGE_ME +// This task is used by a responder. The task first completes the current +// transfer in progress then waits for the initiator to start the next transfer. + task respond_and_wait_for_next_transfer( + // This argument is used to send data received from the initiator + // back to the sequence item. The sequence determines how to respond. + output wb_m_initiator_s wb_m_initiator_struct, + // This argument passes transaction variables used by a responder + // to complete a protocol transfer. The values come from a sequence item. + input wb_m_responder_s wb_m_responder_struct + );// pragma tbx xtf + // Variables within the wb_m_initiator_struct: + // bit [WB_DATA_WIDTH-1:0] data ; + // bit [(WB_DATA_WIDTH/8)-1:0] byte_select ; + // bit WrENB ; + // bit selslv ; + // Variables within the wb_m_responder_struct: + // bit [WB_DATA_WIDTH-1:0] data ; + // bit [(WB_DATA_WIDTH/8)-1:0] byte_select ; + // bit WrENB ; + // bit selslv ; + // Reference code; + // How to wait for signal value + // while (control_signal == 1'b1) @(posedge clock_i); + // + // How to assign a responder struct member, named xyz, from a signal. + // All available responder input and inout signals listed. + // Responder input signals + // wb_m_responder_struct.xyz = dout_i; // [WB_DATA_WIDTH-1:0] + // wb_m_responder_struct.xyz = TGD_O_i; // [WB_DATA_WIDTH-1:0] + // wb_m_responder_struct.xyz = ack_i; // + // wb_m_responder_struct.xyz = adr_i; // [WB_ADDR_WIDTH-1:0] + // wb_m_responder_struct.xyz = cyc_i; // + // wb_m_responder_struct.xyz = we_i; // + // wb_m_responder_struct.xyz = stb_i; // + // wb_m_responder_struct.xyz = sel_i; // [WB_DATA_WIDTH/8-1:0] + // Responder inout signals + // How to assign a signal, named xyz, from an initiator struct member. + // All available responder output and inout signals listed. + // Notice the _o. Those are storage variables that allow for procedural assignment. + // Responder output signals + // din_o <= wb_m_initiator_struct.xyz; // [WB_DATA_WIDTH-1:0] + // TGD_I_o <= wb_m_initiator_struct.xyz; // [WB_DATA_WIDTH-1:0] + // err_o <= wb_m_initiator_struct.xyz; // + // Responder inout signals + + @(posedge clock_i); + if (!first_transfer) begin + // Perform transfer response here. + // Reply using data recieved in the wb_m_responder_struct. + @(posedge clock_i); + // Reply using data recieved in the transaction handle. + @(posedge clock_i); + end + // Wait for next transfer then gather info from intiator about the transfer. + // Place the data into the wb_m_initiator_struct. + @(posedge clock_i); + @(posedge clock_i); + first_transfer = 0; + endtask +// pragma uvmf custom respond_and_wait_for_next_transfer end + + +endinterface + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/verification_ip/interface_packages/wb_m_pkg/src/wb_m_if.sv b/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/verification_ip/interface_packages/wb_m_pkg/src/wb_m_if.sv new file mode 100644 index 00000000..f90899c4 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/verification_ip/interface_packages/wb_m_pkg/src/wb_m_if.sv @@ -0,0 +1,117 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This interface contains the wb_m interface signals. +// It is instantiated once per wb_m bus. Bus Functional Models, +// BFM's named wb_m_driver_bfm, are used to drive signals on the bus. +// BFM's named wb_m_monitor_bfm are used to monitor signals on the +// bus. This interface signal bundle is passed in the port list of +// the BFM in order to give the BFM access to the signals in this +// interface. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// This template can be used to connect a DUT to these signals +// +// .dut_signal_port(wb_m_bus.din), // Agent input +// .dut_signal_port(wb_m_bus.dout), // Agent output +// .dut_signal_port(wb_m_bus.TGD_I), // Agent input +// .dut_signal_port(wb_m_bus.TGD_O), // Agent output +// .dut_signal_port(wb_m_bus.ack), // Agent output +// .dut_signal_port(wb_m_bus.adr), // Agent output +// .dut_signal_port(wb_m_bus.cyc), // Agent output +// .dut_signal_port(wb_m_bus.err), // Agent input +// .dut_signal_port(wb_m_bus.we), // Agent output +// .dut_signal_port(wb_m_bus.stb), // Agent output +// .dut_signal_port(wb_m_bus.sel), // Agent output + +import uvmf_base_pkg_hdl::*; +import wb_m_pkg_hdl::*; + +interface wb_m_if #( + int WB_ADDR_WIDTH = 32, + int WB_DATA_WIDTH = 16 + ) + + ( + input logic clock, + input logic reset, + input logic [WB_DATA_WIDTH-1:0] din, + output logic [WB_DATA_WIDTH-1:0] dout, + input logic [WB_DATA_WIDTH-1:0] TGD_I, + output logic [WB_DATA_WIDTH-1:0] TGD_O, + output logic ack, + output logic [WB_ADDR_WIDTH-1:0] adr, + output logic cyc, + input logic err, + output logic we, + output logic stb, + output logic [WB_DATA_WIDTH/8-1:0] sel + ); + +modport monitor_port + ( + input clock, + input reset, + input din, + input dout, + input TGD_I, + input TGD_O, + input ack, + input adr, + input cyc, + input err, + input we, + input stb, + input sel + ); + +modport initiator_port + ( + input clock, + input reset, + input din, + output dout, + input TGD_I, + output TGD_O, + output ack, + output adr, + output cyc, + input err, + output we, + output stb, + output sel + ); + +modport responder_port + ( + input clock, + input reset, + output din, + input dout, + output TGD_I, + input TGD_O, + input ack, + input adr, + input cyc, + output err, + input we, + input stb, + input sel + ); + + +// pragma uvmf custom interface_item_additional begin +// pragma uvmf custom interface_item_additional end + +endinterface + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/verification_ip/interface_packages/wb_m_pkg/src/wb_m_infact_coverage_strategy.csv b/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/verification_ip/interface_packages/wb_m_pkg/src/wb_m_infact_coverage_strategy.csv new file mode 100644 index 00000000..1c218e14 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/verification_ip/interface_packages/wb_m_pkg/src/wb_m_infact_coverage_strategy.csv @@ -0,0 +1,6 @@ +Global +auto_bin_max, 64 + +Name,Type,Include +rand_fields,coverpoint,=rand *.** + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/verification_ip/interface_packages/wb_m_pkg/src/wb_m_macros.svh b/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/verification_ip/interface_packages/wb_m_pkg/src/wb_m_macros.svh new file mode 100644 index 00000000..9977f6fa --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/verification_ip/interface_packages/wb_m_pkg/src/wb_m_macros.svh @@ -0,0 +1,148 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This file contains macros used with the wb_m package. +// These macros include packed struct definitions. These structs are +// used to pass data between classes, hvl, and BFM's, hdl. Use of +// structs are more efficient and simpler to modify. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// + +// **************************************************************************** +// When changing the contents of this struct, be sure to update the to_struct +// and from_struct methods defined in the macros below that are used in +// the wb_m_configuration class. +// + `define wb_m_CONFIGURATION_STRUCT \ +typedef struct packed { \ + uvmf_active_passive_t active_passive; \ + uvmf_initiator_responder_t initiator_responder; \ + } wb_m_configuration_s; + + `define wb_m_CONFIGURATION_TO_STRUCT_FUNCTION \ + virtual function wb_m_configuration_s to_struct();\ + wb_m_configuration_struct = \ + {\ + this.active_passive,\ + this.initiator_responder\ + };\ + return ( wb_m_configuration_struct );\ + endfunction + + `define wb_m_CONFIGURATION_FROM_STRUCT_FUNCTION \ + virtual function void from_struct(wb_m_configuration_s wb_m_configuration_struct);\ + {\ + this.active_passive,\ + this.initiator_responder \ + } = wb_m_configuration_struct;\ + endfunction + +// **************************************************************************** +// When changing the contents of this struct, be sure to update the to_monitor_struct +// and from_monitor_struct methods of the wb_m_transaction class. +// + `define wb_m_MONITOR_STRUCT typedef struct packed { \ + bit [WB_DATA_WIDTH-1:0] data ; \ + bit [(WB_DATA_WIDTH/8)-1:0] byte_select ; \ + bit WrENB ; \ + bit selslv ; \ + } wb_m_monitor_s; + + `define wb_m_TO_MONITOR_STRUCT_FUNCTION \ + virtual function wb_m_monitor_s to_monitor_struct();\ + wb_m_monitor_struct = \ + { \ + this.data , \ + this.byte_select , \ + this.WrENB , \ + this.selslv \ + };\ + return ( wb_m_monitor_struct);\ + endfunction\ + + `define wb_m_FROM_MONITOR_STRUCT_FUNCTION \ + virtual function void from_monitor_struct(wb_m_monitor_s wb_m_monitor_struct);\ + {\ + this.data , \ + this.byte_select , \ + this.WrENB , \ + this.selslv \ + } = wb_m_monitor_struct;\ + endfunction + +// **************************************************************************** +// When changing the contents of this struct, be sure to update the to_initiator_struct +// and from_initiator_struct methods of the wb_m_transaction class. +// Also update the comments in the driver BFM. +// + `define wb_m_INITIATOR_STRUCT typedef struct packed { \ + bit [WB_DATA_WIDTH-1:0] data ; \ + bit [(WB_DATA_WIDTH/8)-1:0] byte_select ; \ + bit WrENB ; \ + bit selslv ; \ + } wb_m_initiator_s; + + `define wb_m_TO_INITIATOR_STRUCT_FUNCTION \ + virtual function wb_m_initiator_s to_initiator_struct();\ + wb_m_initiator_struct = \ + {\ + this.data , \ + this.byte_select , \ + this.WrENB , \ + this.selslv \ + };\ + return ( wb_m_initiator_struct);\ + endfunction + + `define wb_m_FROM_INITIATOR_STRUCT_FUNCTION \ + virtual function void from_initiator_struct(wb_m_initiator_s wb_m_initiator_struct);\ + {\ + this.data , \ + this.byte_select , \ + this.WrENB , \ + this.selslv \ + } = wb_m_initiator_struct;\ + endfunction + +// **************************************************************************** +// When changing the contents of this struct, be sure to update the to_responder_struct +// and from_responder_struct methods of the wb_m_transaction class. +// Also update the comments in the driver BFM. +// + `define wb_m_RESPONDER_STRUCT typedef struct packed { \ + bit [WB_DATA_WIDTH-1:0] data ; \ + bit [(WB_DATA_WIDTH/8)-1:0] byte_select ; \ + bit WrENB ; \ + bit selslv ; \ + } wb_m_responder_s; + + `define wb_m_TO_RESPONDER_STRUCT_FUNCTION \ + virtual function wb_m_responder_s to_responder_struct();\ + wb_m_responder_struct = \ + {\ + this.data , \ + this.byte_select , \ + this.WrENB , \ + this.selslv \ + };\ + return ( wb_m_responder_struct);\ + endfunction + + `define wb_m_FROM_RESPONDER_STRUCT_FUNCTION \ + virtual function void from_responder_struct(wb_m_responder_s wb_m_responder_struct);\ + {\ + this.data , \ + this.byte_select , \ + this.WrENB , \ + this.selslv \ + } = wb_m_responder_struct;\ + endfunction +// pragma uvmf custom additional begin +// pragma uvmf custom additional end diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/verification_ip/interface_packages/wb_m_pkg/src/wb_m_monitor.svh b/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/verification_ip/interface_packages/wb_m_pkg/src/wb_m_monitor.svh new file mode 100644 index 00000000..68abbbf2 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/verification_ip/interface_packages/wb_m_pkg/src/wb_m_monitor.svh @@ -0,0 +1,102 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This class receives wb_m transactions observed by the +// wb_m monitor BFM and broadcasts them through the analysis port +// on the agent. It accesses the monitor BFM through the monitor +// task. This UVM component captures transactions +// for viewing in the waveform viewer if the +// enable_transaction_viewing flag is set in the configuration. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class wb_m_monitor #( + int WB_ADDR_WIDTH = 32, + int WB_DATA_WIDTH = 16 + ) extends uvmf_monitor_base #( + .CONFIG_T(wb_m_configuration #( + .WB_ADDR_WIDTH(WB_ADDR_WIDTH), + .WB_DATA_WIDTH(WB_DATA_WIDTH) + )), + .BFM_BIND_T(virtual wb_m_monitor_bfm #( + .WB_ADDR_WIDTH(WB_ADDR_WIDTH), + .WB_DATA_WIDTH(WB_DATA_WIDTH) + )), + .TRANS_T(wb_m_transaction #( + .WB_ADDR_WIDTH(WB_ADDR_WIDTH), + .WB_DATA_WIDTH(WB_DATA_WIDTH) + ))); + + `uvm_component_param_utils( wb_m_monitor #( + WB_ADDR_WIDTH, + WB_DATA_WIDTH + )) + +// Structure used to pass data from monitor BFM to monitor class in agent. +// Use to_monitor_struct function to pack transaction variables into structure. +// Use from_monitor_struct function to unpack transaction variables from structure. +`wb_m_MONITOR_STRUCT + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + +// **************************************************************************** +// This function is the standard SystemVerilog constructor. +// + function new( string name = "", uvm_component parent = null ); + super.new( name, parent ); + endfunction + +// **************************************************************************** +// This function sends configuration object variables to the monitor BFM +// using the configuration struct. +// + virtual function void configure(input CONFIG_T cfg); + bfm.configure( cfg.to_struct() ); + + endfunction + +// **************************************************************************** +// This function places a handle to this class in the proxy variable in the +// monitor BFM. This allows the monitor BFM to call the notify_transaction +// function within this class. +// + virtual function void set_bfm_proxy_handle(); + bfm.proxy = this; endfunction + +// *************************************************************************** + virtual task run_phase(uvm_phase phase); + // Start monitor BFM thread and don't call super.run() in order to + // override the default monitor proxy 'pull' behavior with the more + // emulation-friendly BFM 'push' approach using the notify_transaction + // function below + bfm.start_monitoring(); + endtask + +// ************************************************************************** + +// This function is called by the monitor BFM. It receives data observed by the +// monitor BFM. Data is passed using the wb_m_monitor_struct. + virtual function void notify_transaction(input wb_m_monitor_s wb_m_monitor_struct); + + + trans = new("trans"); + trans.from_monitor_struct(wb_m_monitor_struct); + trans.start_time = time_stamp; + trans.end_time = $time; + time_stamp = trans.end_time; + + analyze(trans); + endfunction + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/verification_ip/interface_packages/wb_m_pkg/src/wb_m_monitor_bfm.sv b/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/verification_ip/interface_packages/wb_m_pkg/src/wb_m_monitor_bfm.sv new file mode 100644 index 00000000..8d760446 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/verification_ip/interface_packages/wb_m_pkg/src/wb_m_monitor_bfm.sv @@ -0,0 +1,213 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This interface performs the wb_m signal monitoring. +// It is accessed by the uvm wb_m monitor through a virtual +// interface handle in the wb_m configuration. It monitors the +// signals passed in through the port connection named bus of +// type wb_m_if. +// +// Input signals from the wb_m_if are assigned to an internal input +// signal with a _i suffix. The _i signal should be used for sampling. +// +// The input signal connections are as follows: +// bus.signal -> signal_i +// +// Interface functions and tasks used by UVM components: +// monitor(inout TRANS_T txn); +// This task receives the transaction, txn, from the +// UVM monitor and then populates variables in txn +// from values observed on bus activity. This task +// blocks until an operation on the wb_m bus is complete. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +import uvmf_base_pkg_hdl::*; +import wb_m_pkg_hdl::*; +`include "src/wb_m_macros.svh" + + +interface wb_m_monitor_bfm #( + int WB_ADDR_WIDTH = 32, + int WB_DATA_WIDTH = 16 + ) + ( wb_m_if bus ); + // The pragma below and additional ones in-lined further down are for running this BFM on Veloce + // pragma attribute wb_m_monitor_bfm partition_interface_xif + +`ifndef XRTL +// This code is to aid in debugging parameter mismatches between the BFM and its corresponding agent. +// Enable this debug by setting UVM_VERBOSITY to UVM_DEBUG +// Setting UVM_VERBOSITY to UVM_DEBUG causes all BFM's and all agents to display their parameter settings. +// All of the messages from this feature have a UVM messaging id value of "CFG" +// The transcript or run.log can be parsed to ensure BFM parameter settings match its corresponding agents parameter settings. +import uvm_pkg::*; +`include "uvm_macros.svh" +initial begin : bfm_vs_agent_parameter_debug + `uvm_info("CFG", + $psprintf("The BFM at '%m' has the following parameters: WB_ADDR_WIDTH=%x WB_DATA_WIDTH=%x ", WB_ADDR_WIDTH,WB_DATA_WIDTH), + UVM_DEBUG) +end +`endif + + + // Structure used to pass transaction data from monitor BFM to monitor class in agent. +`wb_m_MONITOR_STRUCT + wb_m_monitor_s wb_m_monitor_struct; + + // Structure used to pass configuration data from monitor class to monitor BFM. + `wb_m_CONFIGURATION_STRUCT + + + // Config value to determine if this is an initiator or a responder + uvmf_initiator_responder_t initiator_responder; + // Custom configuration variables. + // These are set using the configure function which is called during the UVM connect_phase + + logic clock_i; + logic reset_i; + tri [WB_DATA_WIDTH-1:0] din_i; + tri [WB_DATA_WIDTH-1:0] dout_i; + tri [WB_DATA_WIDTH-1:0] TGD_I_i; + tri [WB_DATA_WIDTH-1:0] TGD_O_i; + tri ack_i; + tri [WB_ADDR_WIDTH-1:0] adr_i; + tri cyc_i; + tri err_i; + tri we_i; + tri stb_i; + tri [WB_DATA_WIDTH/8-1:0] sel_i; + assign clock_i = bus.clock; + assign reset_i = bus.reset; + assign din_i = bus.din; + assign dout_i = bus.dout; + assign TGD_I_i = bus.TGD_I; + assign TGD_O_i = bus.TGD_O; + assign ack_i = bus.ack; + assign adr_i = bus.adr; + assign cyc_i = bus.cyc; + assign err_i = bus.err; + assign we_i = bus.we; + assign stb_i = bus.stb; + assign sel_i = bus.sel; + + // Proxy handle to UVM monitor + wb_m_pkg::wb_m_monitor #( + .WB_ADDR_WIDTH(WB_ADDR_WIDTH), + .WB_DATA_WIDTH(WB_DATA_WIDTH) + ) proxy; + // pragma tbx oneway proxy.notify_transaction + + // pragma uvmf custom interface_item_additional begin + // pragma uvmf custom interface_item_additional end + + //****************************************************************** + task wait_for_reset();// pragma tbx xtf + @(posedge clock_i) ; + do_wait_for_reset(); + endtask + + // **************************************************************************** + task do_wait_for_reset(); + // pragma uvmf custom reset_condition begin + wait ( reset_i === 0 ) ; + @(posedge clock_i) ; + // pragma uvmf custom reset_condition end + endtask + + //****************************************************************** + + task wait_for_num_clocks(input int unsigned count); // pragma tbx xtf + @(posedge clock_i); + + repeat (count-1) @(posedge clock_i); + endtask + + //****************************************************************** + event go; + function void start_monitoring();// pragma tbx xtf + -> go; + endfunction + + // **************************************************************************** + initial begin + @go; + forever begin + @(posedge clock_i); + do_monitor( wb_m_monitor_struct ); + + + proxy.notify_transaction( wb_m_monitor_struct ); + + end + end + + //****************************************************************** + // The configure() function is used to pass agent configuration + // variables to the monitor BFM. It is called by the monitor within + // the agent at the beginning of the simulation. It may be called + // during the simulation if agent configuration variables are updated + // and the monitor BFM needs to be aware of the new configuration + // variables. + // + function void configure(wb_m_configuration_s wb_m_configuration_arg); // pragma tbx xtf + initiator_responder = wb_m_configuration_arg.initiator_responder; + // pragma uvmf custom configure begin + // pragma uvmf custom configure end + endfunction + + + // **************************************************************************** + + task do_monitor(output wb_m_monitor_s wb_m_monitor_struct); + // + // Available struct members: + // // wb_m_monitor_struct.data + // // wb_m_monitor_struct.byte_select + // // wb_m_monitor_struct.WrENB + // // wb_m_monitor_struct.selslv + // // + // Reference code; + // How to wait for signal value + // while (control_signal === 1'b1) @(posedge clock_i); + // + // How to assign a struct member, named xyz, from a signal. + // All available input signals listed. + // wb_m_monitor_struct.xyz = din_i; // [WB_DATA_WIDTH-1:0] + // wb_m_monitor_struct.xyz = dout_i; // [WB_DATA_WIDTH-1:0] + // wb_m_monitor_struct.xyz = TGD_I_i; // [WB_DATA_WIDTH-1:0] + // wb_m_monitor_struct.xyz = TGD_O_i; // [WB_DATA_WIDTH-1:0] + // wb_m_monitor_struct.xyz = ack_i; // + // wb_m_monitor_struct.xyz = adr_i; // [WB_ADDR_WIDTH-1:0] + // wb_m_monitor_struct.xyz = cyc_i; // + // wb_m_monitor_struct.xyz = err_i; // + // wb_m_monitor_struct.xyz = we_i; // + // wb_m_monitor_struct.xyz = stb_i; // + // wb_m_monitor_struct.xyz = sel_i; // [WB_DATA_WIDTH/8-1:0] + // pragma uvmf custom do_monitor begin + // UVMF_CHANGE_ME : Implement protocol monitoring. The commented reference code + // below are examples of how to capture signal values and assign them to + // structure members. All available input signals are listed. The 'while' + // code example shows how to wait for a synchronous flow control signal. This + // task should return when a complete transfer has been observed. Once this task is + // exited with captured values, it is then called again to wait for and observe + // the next transfer. One clock cycle is consumed between calls to do_monitor. + @(posedge clock_i); + @(posedge clock_i); + @(posedge clock_i); + @(posedge clock_i); + // pragma uvmf custom do_monitor end + endtask + + +endinterface + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/verification_ip/interface_packages/wb_m_pkg/src/wb_m_random_sequence.svh b/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/verification_ip/interface_packages/wb_m_pkg/src/wb_m_random_sequence.svh new file mode 100644 index 00000000..03e64780 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/verification_ip/interface_packages/wb_m_pkg/src/wb_m_random_sequence.svh @@ -0,0 +1,65 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: +// This sequences randomizes the wb_m transaction and sends it +// to the UVM driver. +// +// This sequence constructs and randomizes a wb_m_transaction. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class wb_m_random_sequence #( + int WB_ADDR_WIDTH = 32, + int WB_DATA_WIDTH = 16 + ) + extends wb_m_sequence_base #( + .WB_ADDR_WIDTH(WB_ADDR_WIDTH), + .WB_DATA_WIDTH(WB_DATA_WIDTH) + ); + + `uvm_object_param_utils( wb_m_random_sequence #( + WB_ADDR_WIDTH, + WB_DATA_WIDTH + )) + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + //***************************************************************** + function new(string name = ""); + super.new(name); + endfunction: new + + // **************************************************************************** + // TASK : body() + // This task is automatically executed when this sequence is started using the + // start(sequencerHandle) task. + // + task body(); + + // Construct the transaction + req=wb_m_transaction#( + .WB_ADDR_WIDTH(WB_ADDR_WIDTH), + .WB_DATA_WIDTH(WB_DATA_WIDTH) + )::type_id::create("req"); + start_item(req); + // Randomize the transaction + if(!req.randomize()) `uvm_fatal("SEQ", "wb_m_random_sequence::body()-wb_m_transaction randomization failed") + // Send the transaction to the wb_m_driver_bfm via the sequencer and wb_m_driver. + finish_item(req); + `uvm_info("SEQ", {"Response:",req.convert2string()},UVM_MEDIUM) + + endtask + +endclass: wb_m_random_sequence + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/verification_ip/interface_packages/wb_m_pkg/src/wb_m_responder_sequence.svh b/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/verification_ip/interface_packages/wb_m_pkg/src/wb_m_responder_sequence.svh new file mode 100644 index 00000000..ae47fb04 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/verification_ip/interface_packages/wb_m_pkg/src/wb_m_responder_sequence.svh @@ -0,0 +1,61 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This class can be used to provide stimulus when an interface +// has been configured to run in a responder mode. It +// will never finish by default, always going back to the driver +// and driver BFM for the next transaction with which to respond. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class wb_m_responder_sequence #( + int WB_ADDR_WIDTH = 32, + int WB_DATA_WIDTH = 16 + ) + extends wb_m_sequence_base #( + .WB_ADDR_WIDTH(WB_ADDR_WIDTH), + .WB_DATA_WIDTH(WB_DATA_WIDTH) + ); + + `uvm_object_param_utils( wb_m_responder_sequence #( + WB_ADDR_WIDTH, + WB_DATA_WIDTH + )) + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + function new(string name = "wb_m_responder_sequence"); + super.new(name); + endfunction + + task body(); + req=wb_m_transaction#( + .WB_ADDR_WIDTH(WB_ADDR_WIDTH), + .WB_DATA_WIDTH(WB_DATA_WIDTH) + )::type_id::create("req"); + forever begin + start_item(req); + finish_item(req); + // pragma uvmf custom body begin + // UVMF_CHANGE_ME : Do something here with the resulting req item. The + // finish_item() call above will block until the req transaction is ready + // to be handled by the responder sequence. + // If this was an item that required a response, the expectation is + // that the response should be populated within this transaction now. + `uvm_info("SEQ",$sformatf("Processed txn: %s",req.convert2string()),UVM_HIGH) + // pragma uvmf custom body end + end + endtask + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/verification_ip/interface_packages/wb_m_pkg/src/wb_m_sequence_base.svh b/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/verification_ip/interface_packages/wb_m_pkg/src/wb_m_sequence_base.svh new file mode 100644 index 00000000..972a578f --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/verification_ip/interface_packages/wb_m_pkg/src/wb_m_sequence_base.svh @@ -0,0 +1,114 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: +// This file contains the class used as the base class for all sequences +// for this interface. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class wb_m_sequence_base #( + int WB_ADDR_WIDTH = 32, + int WB_DATA_WIDTH = 16 + ) extends uvmf_sequence_base #( + .REQ(wb_m_transaction #( + .WB_ADDR_WIDTH(WB_ADDR_WIDTH), + .WB_DATA_WIDTH(WB_DATA_WIDTH) + )), + .RSP(wb_m_transaction #( + .WB_ADDR_WIDTH(WB_ADDR_WIDTH), + .WB_DATA_WIDTH(WB_DATA_WIDTH) + ))); + + `uvm_object_param_utils( wb_m_sequence_base #( + WB_ADDR_WIDTH, + WB_DATA_WIDTH + )) + + // variables + typedef wb_m_transaction #( + .WB_ADDR_WIDTH(WB_ADDR_WIDTH), + .WB_DATA_WIDTH(WB_DATA_WIDTH) + ) wb_m_transaction_req_t; + wb_m_transaction_req_t req; + typedef wb_m_transaction #( + .WB_ADDR_WIDTH(WB_ADDR_WIDTH), + .WB_DATA_WIDTH(WB_DATA_WIDTH) + ) wb_m_transaction_rsp_t; + wb_m_transaction_rsp_t rsp; + + // Event for identifying when a response was received from the sequencer + event new_rsp; + + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + // **************************************************************************** + // TASK : get_responses() + // This task recursively gets sequence item responses from the sequencer. + // + virtual task get_responses(); + fork + begin + // Block until new rsp available + get_response(rsp); + // New rsp received. Indicate to sequence using event. + ->new_rsp; + // Display the received response transaction + `uvm_info("SEQ", {"New response transaction:",rsp.convert2string()}, UVM_MEDIUM) + end + join_none + endtask + + // **************************************************************************** + // TASK : pre_body() + // This task is called automatically when start is called with call_pre_post set to 1 (default). + // By calling get_responses() within pre_body() any derived sequences are automatically + // processing response transactions. Only un-comment this call to get_responses() if you + // have configured the interface driver to utilize the response transaction path by setting + // the configuration variable "return_transaction_response" to 1. Otherwise it is possible + // to impact runtime performance and memory utilization. + // + virtual task pre_body(); + // pragma uvmf custom pre_body begin +// get_responses(); + // pragma uvmf custom pre_body end + endtask + + // **************************************************************************** + // TASK : body() + // This task is called automatically when start is called. This sequence sends + // a req sequence item to the sequencer identified as an argument in the call + // to start. + // + virtual task body(); + // pragma uvmf custom body begin + start_item(req); + finish_item(req); + // pragma uvmf custom body end + endtask + + // **************************************************************************** + // FUNCTION : new() + // This function is the standard SystemVerilog constructor. + // + function new( string name =""); + super.new( name ); + // pragma uvmf custom new begin + req = wb_m_transaction_req_t::type_id::create("req"); + rsp = wb_m_transaction_rsp_t::type_id::create("rsp"); + // pragma uvmf custom new end + endfunction + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/verification_ip/interface_packages/wb_m_pkg/src/wb_m_transaction.svh b/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/verification_ip/interface_packages/wb_m_pkg/src/wb_m_transaction.svh new file mode 100644 index 00000000..f7dc5a3d --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/verification_ip/interface_packages/wb_m_pkg/src/wb_m_transaction.svh @@ -0,0 +1,206 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This class defines the variables required for an wb_m +// transaction. Class variables to be displayed in waveform transaction +// viewing are added to the transaction viewing stream in the add_to_wave +// function. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class wb_m_transaction #( + int WB_ADDR_WIDTH = 32, + int WB_DATA_WIDTH = 16 + ) extends uvmf_transaction_base; + + `uvm_object_param_utils( wb_m_transaction #( + WB_ADDR_WIDTH, + WB_DATA_WIDTH + )) + + rand bit [WB_DATA_WIDTH-1:0] data ; + rand bit [(WB_DATA_WIDTH/8)-1:0] byte_select ; + rand bit WrENB ; + rand bit selslv ; + + //Constraints for the transaction variables: + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + //******************************************************************* + //******************************************************************* + // Macros that define structs and associated functions are + // located in wb_m_macros.svh + + //******************************************************************* + // Monitor macro used by wb_m_monitor and wb_m_monitor_bfm + // This struct is defined in wb_m_macros.svh + `wb_m_MONITOR_STRUCT + wb_m_monitor_s wb_m_monitor_struct; + //******************************************************************* + // FUNCTION: to_monitor_struct() + // This function packs transaction variables into a wb_m_monitor_s + // structure. The function returns the handle to the wb_m_monitor_struct. + // This function is defined in wb_m_macros.svh + `wb_m_TO_MONITOR_STRUCT_FUNCTION + //******************************************************************* + // FUNCTION: from_monitor_struct() + // This function unpacks the struct provided as an argument into transaction + // variables of this class. + // This function is defined in wb_m_macros.svh + `wb_m_FROM_MONITOR_STRUCT_FUNCTION + + //******************************************************************* + // Initiator macro used by wb_m_driver and wb_m_driver_bfm + // to communicate initiator driven data to wb_m_driver_bfm. + // This struct is defined in wb_m_macros.svh + `wb_m_INITIATOR_STRUCT + wb_m_initiator_s wb_m_initiator_struct; + //******************************************************************* + // FUNCTION: to_initiator_struct() + // This function packs transaction variables into a wb_m_initiator_s + // structure. The function returns the handle to the wb_m_initiator_struct. + // This function is defined in wb_m_macros.svh + `wb_m_TO_INITIATOR_STRUCT_FUNCTION + //******************************************************************* + // FUNCTION: from_initiator_struct() + // This function unpacks the struct provided as an argument into transaction + // variables of this class. + // This function is defined in wb_m_macros.svh + `wb_m_FROM_INITIATOR_STRUCT_FUNCTION + + //******************************************************************* + // Responder macro used by wb_m_driver and wb_m_driver_bfm + // to communicate Responder driven data to wb_m_driver_bfm. + // This struct is defined in wb_m_macros.svh + `wb_m_RESPONDER_STRUCT + wb_m_responder_s wb_m_responder_struct; + //******************************************************************* + // FUNCTION: to_responder_struct() + // This function packs transaction variables into a wb_m_responder_s + // structure. The function returns the handle to the wb_m_responder_struct. + // This function is defined in wb_m_macros.svh + `wb_m_TO_RESPONDER_STRUCT_FUNCTION + //******************************************************************* + // FUNCTION: from_responder_struct() + // This function unpacks the struct provided as an argument into transaction + // variables of this class. + // This function is defined in wb_m_macros.svh + `wb_m_FROM_RESPONDER_STRUCT_FUNCTION + // **************************************************************************** + // FUNCTION : new() + // This function is the standard SystemVerilog constructor. + // + function new( string name = "" ); + super.new( name ); + endfunction + + // **************************************************************************** + // FUNCTION: convert2string() + // This function converts all variables in this class to a single string for + // logfile reporting. + // + virtual function string convert2string(); + // pragma uvmf custom convert2string begin + // UVMF_CHANGE_ME : Customize format if desired. + return $sformatf("data:0x%x byte_select:0x%x WrENB:0x%x selslv:0x%x ",data,byte_select,WrENB,selslv); + // pragma uvmf custom convert2string end + endfunction + + //******************************************************************* + // FUNCTION: do_print() + // This function is automatically called when the .print() function + // is called on this class. + // + virtual function void do_print(uvm_printer printer); + // pragma uvmf custom do_print begin + // UVMF_CHANGE_ME : Current contents of do_print allows for the use of UVM 1.1d, 1.2 or P1800.2. + // Update based on your own printing preference according to your preferred UVM version + $display(convert2string()); + // pragma uvmf custom do_print end + endfunction + + //******************************************************************* + // FUNCTION: do_compare() + // This function is automatically called when the .compare() function + // is called on this class. + // + virtual function bit do_compare (uvm_object rhs, uvm_comparer comparer); + wb_m_transaction #( + .WB_ADDR_WIDTH(WB_ADDR_WIDTH), + .WB_DATA_WIDTH(WB_DATA_WIDTH) + ) RHS; + if (!$cast(RHS,rhs)) return 0; + // pragma uvmf custom do_compare begin + // UVMF_CHANGE_ME : Eliminate comparison of variables not to be used for compare + return (super.do_compare(rhs,comparer) + &&(this.data == RHS.data) + &&(this.byte_select == RHS.byte_select) + &&(this.WrENB == RHS.WrENB) + &&(this.selslv == RHS.selslv) + ); + // pragma uvmf custom do_compare end + endfunction + + //******************************************************************* + // FUNCTION: do_copy() + // This function is automatically called when the .copy() function + // is called on this class. + // + virtual function void do_copy (uvm_object rhs); + wb_m_transaction #( + .WB_ADDR_WIDTH(WB_ADDR_WIDTH), + .WB_DATA_WIDTH(WB_DATA_WIDTH) + ) RHS; + assert($cast(RHS,rhs)); + // pragma uvmf custom do_copy begin + super.do_copy(rhs); + this.data = RHS.data; + this.byte_select = RHS.byte_select; + this.WrENB = RHS.WrENB; + this.selslv = RHS.selslv; + // pragma uvmf custom do_copy end + endfunction + + // **************************************************************************** + // FUNCTION: add_to_wave() + // This function is used to display variables in this class in the waveform + // viewer. The start_time and end_time variables must be set before this + // function is called. If the start_time and end_time variables are not set + // the transaction will be hidden at 0ns on the waveform display. + // + virtual function void add_to_wave(int transaction_viewing_stream_h); + `ifdef QUESTA + if (transaction_view_h == 0) begin + transaction_view_h = $begin_transaction(transaction_viewing_stream_h,"wb_m_transaction",start_time); + end + super.add_to_wave(transaction_view_h); + // pragma uvmf custom add_to_wave begin + // UVMF_CHANGE_ME : Color can be applied to transaction entries based on content, example below + // case() + // 1 : $add_color(transaction_view_h,"red"); + // default : $add_color(transaction_view_h,"grey"); + // endcase + // UVMF_CHANGE_ME : Eliminate transaction variables not wanted in transaction viewing in the waveform viewer + $add_attribute(transaction_view_h,data,"data"); + $add_attribute(transaction_view_h,byte_select,"byte_select"); + $add_attribute(transaction_view_h,WrENB,"WrENB"); + $add_attribute(transaction_view_h,selslv,"selslv"); + // pragma uvmf custom add_to_wave end + $end_transaction(transaction_view_h,end_time); + $free_transaction(transaction_view_h); + `endif // QUESTA + endfunction + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/verification_ip/interface_packages/wb_m_pkg/src/wb_m_transaction_coverage.svh b/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/verification_ip/interface_packages/wb_m_pkg/src/wb_m_transaction_coverage.svh new file mode 100644 index 00000000..ff958912 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/verification_ip/interface_packages/wb_m_pkg/src/wb_m_transaction_coverage.svh @@ -0,0 +1,82 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This class records wb_m transaction information using +// a covergroup named wb_m_transaction_cg. An instance of this +// coverage component is instantiated in the uvmf_parameterized_agent +// if the has_coverage flag is set. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class wb_m_transaction_coverage #( + int WB_ADDR_WIDTH = 32, + int WB_DATA_WIDTH = 16 + ) extends uvm_subscriber #(.T(wb_m_transaction #( + .WB_ADDR_WIDTH(WB_ADDR_WIDTH), + .WB_DATA_WIDTH(WB_DATA_WIDTH) + ))); + + `uvm_component_param_utils( wb_m_transaction_coverage #( + WB_ADDR_WIDTH, + WB_DATA_WIDTH + )) + + T coverage_trans; + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + // **************************************************************************** + covergroup wb_m_transaction_cg; + // pragma uvmf custom covergroup begin + // UVMF_CHANGE_ME : Add coverage bins, crosses, exclusions, etc. according to coverage needs. + option.auto_bin_max=1024; + option.per_instance=1; + data: coverpoint coverage_trans.data; + byte_select: coverpoint coverage_trans.byte_select; + WrENB: coverpoint coverage_trans.WrENB; + selslv: coverpoint coverage_trans.selslv; + // pragma uvmf custom covergroup end + endgroup + + // **************************************************************************** + // FUNCTION : new() + // This function is the standard SystemVerilog constructor. + // + function new(string name="", uvm_component parent=null); + super.new(name,parent); + wb_m_transaction_cg=new; + `uvm_warning("COVERAGE_MODEL_REVIEW", "A covergroup has been constructed which may need review because of either generation or re-generation with merging. Please note that transaction variables added as a result of re-generation and merging are not automatically added to the covergroup. Remove this warning after the covergroup has been reviewed.") + endfunction + + // **************************************************************************** + // FUNCTION : build_phase() + // This function is the standard UVM build_phase. + // + function void build_phase(uvm_phase phase); + wb_m_transaction_cg.set_inst_name($sformatf("wb_m_transaction_cg_%s",get_full_name())); + endfunction + + // **************************************************************************** + // FUNCTION: write (T t) + // This function is automatically executed when a transaction arrives on the + // analysis_export. It copies values from the variables in the transaction + // to local variables used to collect functional coverage. + // + virtual function void write (T t); + `uvm_info("COV","Received transaction",UVM_HIGH); + coverage_trans = t; + wb_m_transaction_cg.sample(); + endfunction + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/verification_ip/interface_packages/wb_m_pkg/src/wb_m_typedefs.svh b/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/verification_ip/interface_packages/wb_m_pkg/src/wb_m_typedefs.svh new file mode 100644 index 00000000..43d85640 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/verification_ip/interface_packages/wb_m_pkg/src/wb_m_typedefs.svh @@ -0,0 +1,20 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: +// This file contains defines and typedefs to be compiled for use in +// the simulation running on the host server when using Veloce. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// + + +// pragma uvmf custom additional begin +// pragma uvmf custom additional end + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/verification_ip/interface_packages/wb_m_pkg/src/wb_m_typedefs_hdl.svh b/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/verification_ip/interface_packages/wb_m_pkg/src/wb_m_typedefs_hdl.svh new file mode 100644 index 00000000..74738c8c --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/verification_ip/interface_packages/wb_m_pkg/src/wb_m_typedefs_hdl.svh @@ -0,0 +1,21 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: +// This file contains defines and typedefs to be compiled for use in +// the simulation running on the emulator when using Veloce. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// + + + +// pragma uvmf custom additional begin +// pragma uvmf custom additional end + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/verification_ip/interface_packages/wb_m_pkg/wb_m.compile b/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/verification_ip/interface_packages/wb_m_pkg/wb_m.compile new file mode 100644 index 00000000..fd2781af --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/verification_ip/interface_packages/wb_m_pkg/wb_m.compile @@ -0,0 +1,3 @@ +needs: + - wb_m_hvl.compile + - wb_m_hdl.compile diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/verification_ip/interface_packages/wb_m_pkg/wb_m_bfm.vinfo b/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/verification_ip/interface_packages/wb_m_pkg/wb_m_bfm.vinfo new file mode 100644 index 00000000..41134f65 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/verification_ip/interface_packages/wb_m_pkg/wb_m_bfm.vinfo @@ -0,0 +1,6 @@ +@use $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg_hdl.vinfo +@use wb_m_pkg_hdl.vinfo ++incdir+@vinfodir +src/wb_m_if.sv +src/wb_m_driver_bfm.sv +src/wb_m_monitor_bfm.sv diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/verification_ip/interface_packages/wb_m_pkg/wb_m_common.compile b/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/verification_ip/interface_packages/wb_m_pkg/wb_m_common.compile new file mode 100644 index 00000000..abbb916d --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/verification_ip/interface_packages/wb_m_pkg/wb_m_common.compile @@ -0,0 +1,7 @@ +needs: + - $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg_hdl.compile +incdir: + - . + - ${uvm_path}/src +src: + - wb_m_pkg_hdl.sv diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/verification_ip/interface_packages/wb_m_pkg/wb_m_filelist_hdl.f b/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/verification_ip/interface_packages/wb_m_pkg/wb_m_filelist_hdl.f new file mode 100644 index 00000000..2b237fad --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/verification_ip/interface_packages/wb_m_pkg/wb_m_filelist_hdl.f @@ -0,0 +1 @@ +$UVMF_VIP_LIBRARY_HOME/interface_packages/wb_m_pkg/wb_m_pkg_hdl.sv diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/verification_ip/interface_packages/wb_m_pkg/wb_m_filelist_hvl.f b/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/verification_ip/interface_packages/wb_m_pkg/wb_m_filelist_hvl.f new file mode 100644 index 00000000..4ec20bef --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/verification_ip/interface_packages/wb_m_pkg/wb_m_filelist_hvl.f @@ -0,0 +1 @@ +$UVMF_VIP_LIBRARY_HOME/interface_packages/wb_m_pkg/wb_m_pkg.sv \ No newline at end of file diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/verification_ip/interface_packages/wb_m_pkg/wb_m_filelist_xrtl.f b/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/verification_ip/interface_packages/wb_m_pkg/wb_m_filelist_xrtl.f new file mode 100644 index 00000000..6e2ee491 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/verification_ip/interface_packages/wb_m_pkg/wb_m_filelist_xrtl.f @@ -0,0 +1,3 @@ +$UVMF_VIP_LIBRARY_HOME/interface_packages/wb_m_pkg/src/wb_m_if.sv +$UVMF_VIP_LIBRARY_HOME/interface_packages/wb_m_pkg/src/wb_m_monitor_bfm.sv +$UVMF_VIP_LIBRARY_HOME/interface_packages/wb_m_pkg/src/wb_m_driver_bfm.sv diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/verification_ip/interface_packages/wb_m_pkg/wb_m_hdl.compile b/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/verification_ip/interface_packages/wb_m_pkg/wb_m_hdl.compile new file mode 100644 index 00000000..0096f879 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/verification_ip/interface_packages/wb_m_pkg/wb_m_hdl.compile @@ -0,0 +1,9 @@ +needs: + - $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg_hdl.compile + - ./wb_m_common.compile +incdir: + - . +src: + - src/wb_m_if.sv + - src/wb_m_monitor_bfm.sv + - src/wb_m_driver_bfm.sv diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/verification_ip/interface_packages/wb_m_pkg/wb_m_hvl.compile b/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/verification_ip/interface_packages/wb_m_pkg/wb_m_hvl.compile new file mode 100644 index 00000000..dd992808 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/verification_ip/interface_packages/wb_m_pkg/wb_m_hvl.compile @@ -0,0 +1,7 @@ +needs: + - $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg.compile + - ./wb_m_common.compile +incdir: + - . +src: + - wb_m_pkg.sv diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/verification_ip/interface_packages/wb_m_pkg/wb_m_pkg.sv b/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/verification_ip/interface_packages/wb_m_pkg/wb_m_pkg.sv new file mode 100644 index 00000000..0cbe3dd0 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/verification_ip/interface_packages/wb_m_pkg/wb_m_pkg.sv @@ -0,0 +1,77 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// PACKAGE: This file defines all of the files contained in the +// interface package that will run on the host simulator. +// +// CONTAINS: +// - +// - +// - + +// - +// - +// - + +// - +// - +// - + +// - +// - +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +package wb_m_pkg; + + import uvm_pkg::*; + import uvmf_base_pkg_hdl::*; + import uvmf_base_pkg::*; + import wb_m_pkg_hdl::*; + + `include "uvm_macros.svh" + + // pragma uvmf custom package_imports_additional begin + // pragma uvmf custom package_imports_additional end + `include "src/wb_m_macros.svh" + + export wb_m_pkg_hdl::*; + + + + // Parameters defined as HVL parameters + + `include "src/wb_m_typedefs.svh" + `include "src/wb_m_transaction.svh" + + `include "src/wb_m_configuration.svh" + `include "src/wb_m_driver.svh" + `include "src/wb_m_monitor.svh" + + `include "src/wb_m_transaction_coverage.svh" + `include "src/wb_m_sequence_base.svh" + `include "src/wb_m_random_sequence.svh" + + `include "src/wb_m_responder_sequence.svh" + `include "src/wb_m2reg_adapter.svh" + + `include "src/wb_m_agent.svh" + + // pragma uvmf custom package_item_additional begin + // UVMF_CHANGE_ME : When adding new interface sequences to the src directory + // be sure to add the sequence file here so that it will be + // compiled as part of the interface package. Be sure to place + // the new sequence after any base sequences of the new sequence. + // pragma uvmf custom package_item_additional end + +endpackage + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/verification_ip/interface_packages/wb_m_pkg/wb_m_pkg.vinfo b/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/verification_ip/interface_packages/wb_m_pkg/wb_m_pkg.vinfo new file mode 100644 index 00000000..5507608c --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/verification_ip/interface_packages/wb_m_pkg/wb_m_pkg.vinfo @@ -0,0 +1,4 @@ +@use $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg.vinfo +@use wb_m_pkg_hdl.vinfo ++incdir+@vinfodir +wb_m_pkg.sv diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/verification_ip/interface_packages/wb_m_pkg/wb_m_pkg_hdl.sv b/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/verification_ip/interface_packages/wb_m_pkg/wb_m_pkg_hdl.sv new file mode 100644 index 00000000..670e7245 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/verification_ip/interface_packages/wb_m_pkg/wb_m_pkg_hdl.sv @@ -0,0 +1,38 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// PACKAGE: This file defines all of the files contained in the +// interface package that needs to be compiled and synthesized +// for running on Veloce. +// +// CONTAINS: +// - +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +package wb_m_pkg_hdl; + + import uvmf_base_pkg_hdl::*; + + // pragma uvmf custom package_imports_additional begin + // pragma uvmf custom package_imports_additional end + + // Parameters defined as HDL parameters + + `include "src/wb_m_typedefs_hdl.svh" + `include "src/wb_m_macros.svh" + + // pragma uvmf custom package_item_additional begin + // pragma uvmf custom package_item_additional end + +endpackage + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/verification_ip/interface_packages/wb_m_pkg/wb_m_pkg_hdl.vinfo b/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/verification_ip/interface_packages/wb_m_pkg/wb_m_pkg_hdl.vinfo new file mode 100644 index 00000000..24e5d862 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/verification_ip/interface_packages/wb_m_pkg/wb_m_pkg_hdl.vinfo @@ -0,0 +1,2 @@ +@use $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg_hdl.vinfo +wb_m_pkg_hdl.sv diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/verification_ip/interface_packages/wb_m_pkg/wb_m_pkg_sve.F b/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/verification_ip/interface_packages/wb_m_pkg/wb_m_pkg_sve.F new file mode 100644 index 00000000..2f158a42 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/verification_ip/interface_packages/wb_m_pkg/wb_m_pkg_sve.F @@ -0,0 +1,10 @@ +// UVM ++incdir+${UVM_HOME}/src +${UVM_HOME}/src/uvm_pkg.sv + +// Common UVMF files +-f ${UVMF_HOME}/common/common_sve.f + ++incdir+. +-f ${UVMF_VIP_LIBRARY_HOME}/interface_packages/wb_m_pkg/wb_m_filelist_hdl.f +-f ${UVMF_VIP_LIBRARY_HOME}/interface_packages/wb_m_pkg/wb_m_filelist_hvl.f diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/verification_ip/interface_packages/wb_m_pkg/yaml/wb_m_interface.yaml b/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/verification_ip/interface_packages/wb_m_pkg/yaml/wb_m_interface.yaml new file mode 100644 index 00000000..0057e3d0 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/block_3/uvmf_template_output/verification_ip/interface_packages/wb_m_pkg/yaml/wb_m_interface.yaml @@ -0,0 +1,93 @@ +uvmf: + interfaces: + wb_m: + clock: clock + config_constraints: [] + config_vars: [] + existing_library_component: 'True' + gen_inbound_streaming_driver: 'False' + hdl_pkg_parameters: [] + hdl_typedefs: [] + hvl_pkg_parameters: [] + hvl_typedefs: [] + parameters: + - name: WB_ADDR_WIDTH + type: int + value: '32' + - name: WB_DATA_WIDTH + type: int + value: '16' + ports: + - dir: input + name: din + reset_value: '''b0' + width: WB_DATA_WIDTH + - dir: output + name: dout + reset_value: '''b0' + width: WB_DATA_WIDTH + - dir: input + name: TGD_I + reset_value: '''bz' + width: WB_DATA_WIDTH + - dir: output + name: TGD_O + reset_value: '''bz' + width: WB_DATA_WIDTH + - dir: output + name: ack + reset_value: 1'b0 + width: '1' + - dir: output + name: adr + reset_value: '''b0' + width: WB_ADDR_WIDTH + - dir: output + name: cyc + reset_value: '0' + width: '1' + - dir: input + name: err + reset_value: '''b0' + width: '1' + - dir: output + name: we + reset_value: '0' + width: '1' + - dir: output + name: stb + reset_value: '0' + width: '1' + - dir: output + name: sel + reset_value: '''b0' + width: WB_DATA_WIDTH/8 + reset: reset + reset_assertion_level: 'True' + transaction_constraints: [] + transaction_vars: + - comment: '' + iscompare: 'True' + isrand: 'True' + name: data + type: bit [WB_DATA_WIDTH-1:0] + unpacked_dimension: '' + - comment: '' + iscompare: 'True' + isrand: 'True' + name: byte_select + type: bit [(WB_DATA_WIDTH/8)-1:0] + unpacked_dimension: '' + - comment: '' + iscompare: 'True' + isrand: 'True' + name: WrENB + type: bit + unpacked_dimension: '' + - comment: '' + iscompare: 'True' + isrand: 'True' + name: selslv + type: bit + unpacked_dimension: '' + use_dpi_link: 'False' diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/intf/apb_m_intf.yaml b/UVM_Framework/UVMF_2022.3/challenge_3/intf/apb_m_intf.yaml new file mode 100644 index 00000000..057c01f0 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/intf/apb_m_intf.yaml @@ -0,0 +1,99 @@ +uvmf: + interfaces: + "apb_m": + clock: "pclk" + reset: "presetn" + veloce_ready: "True" + reset_assertion_level: 'False' + parameters: + - name: "APB_ADDR_WIDTH" + type: "int" + value: '32' + - name: "APB_DATA_WIDTH" + type: "int" + value: '32' + - name: "STRB_LEN" + type: "int" + value: "APB_ADDR_WIDTH/8" + ports: + - dir: "output" + name: "psel" + reset_value: '''b0' + width: '16' + - dir: "output" + name: "penable" + reset_value: '''b0' + width: '1' + - dir: "output" + name: "paddr" + reset_value: '''b0' + width: "APB_ADDR_WIDTH" + - dir: "output" + name: "pwdata" + reset_value: '''b0' + width: "APB_DATA_WIDTH" + - dir: "output" + name: "pwrite" + reset_value: '''b0' + width: '1' + - dir: "output" + name: "pstrb" + reset_value: '''b0' + width: 'STRB_LEN' + - dir: "output" + name: "pprot" + reset_value: '''b0' + width: '3' + - dir: "input" + name: "prdata" + reset_value: '''b0' + width: "APB_DATA_WIDTH" + - dir: "input" + name: "pready" + reset_value: '0' + width: '1' + - dir: "input" + name: "pslverr" + reset_value: '0' + width: '1' + transaction_vars: + - iscompare: 'False' + isrand: 'True' + name: "psel" + type: "bit" + - iscompare: 'True' + isrand: 'True' + name: "penable" + type: "bit" + - iscompare: 'True' + isrand: 'True' + name: "paddr" + type: "bit [APB_ADDR_WIDTH-1:0]" + - iscompare: 'True' + isrand: 'True' + name: "pwdata" + type: "bit [APB_DATA_WIDTH-1:0]" + - iscompare: 'True' + isrand: 'True' + name: "pwrite" + type: "bit" + - iscompare: 'True' + isrand: 'True' + name: "pstrb" + type: "bit [STRB_LEN:0]" + - iscompare: 'True' + isrand: 'True' + name: "pprot" + type: "bit [3:0]" + - iscompare: 'True' + isrand: 'False' + name: "prdata" + type: "bit [APB_DATA_WIDTH-1:0]" + - iscompare: 'True' + isrand: 'False' + name: "pready" + type: "bit" + - iscompare: 'True' + isrand: 'False' + name: "pslverr" + type: "bit" diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/intf/axi_m_intf.yaml b/UVM_Framework/UVMF_2022.3/challenge_3/intf/axi_m_intf.yaml new file mode 100644 index 00000000..6921d053 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/intf/axi_m_intf.yaml @@ -0,0 +1,396 @@ +uvmf: + interfaces: + "axi_m": + clock: axi_clk + reset: rst + reset_assertion_level: "False" + veloce_ready: "True" + parameters: + - name: "AW_WIDTH" + type: "int" + value: "32" + - name: "LEN" + type: "int" + value: "8" + - name: "DATA_WIDTH" + type: "int" + value: "32" + - name: "X" + type: "int" + value: "16" + ports: + # write address channel + - name: awvalid + dir: output + width: "1" + - name: awready + dir: input + width: "1" + - name: awaddr + dir: output + width: "AW_WIDTH" + - name: awsize + dir: output + width: "3" + - name: awburst + dir: output + width: "2" + - name: awcache + dir: output + width: "4" + - name: awprot + dir: output + width: "3" + - name: awid + dir: output + width: "X" + - name: awlen + dir: output + width: "LEN" + - name: awlock + dir: output + width: "1" + - name: awqos + dir: output + width: "4" + - name: awregion + dir: output + width: "4" + - name: awuser + dir: output + width: "X" + # write data channel + - name: wvalid + dir: output + width: "1" + - name: wready + dir: input + width: "1" + - name: wlast + dir: output + width: "1" + - name: wdata + dir: output + width: "DATA_WIDTH" + - name: wstrb + dir: output + width: "DATA_WIDTH/8" + - name: wid + dir: output + width: "X" + - name: wuser + dir: output + width: "X" + # write response channel + - name: bwvalid + dir: input + width: "1" + - name: bwready + dir: output + width: "1" + - name: bresp + dir: input + width: "2" + - name: bid + dir: input + width: "X" + - name: buser + dir: input + width: "X" + #read address channel + - name: arvalid + dir: output + width: "1" + - name: aready + dir: input + width: "1" + - name: araddr + dir: output + width: "AW_WIDTH" + - name: arsize + dir: output + width: "3" + - name: arburst + dir: output + width: "2" + - name: arcache + dir: output + width: "4" + - name: arprot + dir: output + width: "3" + - name: arid + dir: output + width: "X" + - name: arlen + dir: output + width: "LEN" + - name: arlock + dir: output + width: "1" + - name: arqos + dir: output + width: "4" + - name: aregion + dir: output + width: "4" + - name: aruser + dir: output + width: "X" + #read data channel + - name: rvalid + dir: input + width: "1" + - name: rready + dir: output + width: "1" + - name: rlast + dir: input + width: "1" + - name: rdata + dir: input + width: "DATA_WIDTH" + - name: rid + dir: input + width: "X" + - name: ruser + dir: input + width: "X" + - name: rresp + dir: input + width: "2" + transaction_vars: + #write address channel + - name: "awvalid" + type: "bit" + isrand: "False" + iscompare: "False" + + - name: "awready" + type: "bit" + isrand: "False" + iscompare: "False" + + - name: "awaddr" + type: "bit [AW_WIDTH-1:0]" + isrand: "True" + iscompare: "False" + + - name: "awsize" + type: "bit" + isrand: "True" + iscompare: "False" + + - name: "awburst" + type: "bit" + isrand: "True" + iscompare: "False" + + - name: "awcache" + type: "bit" + isrand: "True" + iscompare: "False" + + - name: "awprot" + type: "bit" + isrand: "True" + iscompare: "False" + + - name: "awid" + type: "bit [X-1:0]" + isrand: "True" + iscompare: "False" + + - name: "awlen" + type: "bit [LEN-1:0]" + isrand: "True" + iscompare: "False" + + - name: "awlock" + type: "bit" + isrand: "True" + iscompare: "False" + + - name: "awqos" + type: "bit" + isrand: "True" + iscompare: "False" + + - name: "awregion" + type: "bit" + isrand: "True" + iscompare: "False" + + - name: "awuser" + type: "bit [X-1:0]" + isrand: "True" + iscompare: "False" + + #write data channel + - name: "wvalid" + type: "bit" + isrand: "False" + iscompare: "False" + + - name: "wready" + type: "bit" + isrand: "False" + iscompare: "False" + + - name: "wlast" + type: "bit" + isrand: "False" + iscompare: "False" + + - name: "wdata" + type: "bit [DATA_WIDTH-1:0]" + isrand: "True" + iscompare: "False" + + - name: "wstrb" + type: "bit [DATA_WIDTH/8-1:0]" + isrand: "True" + iscompare: "False" + + - name: "wid" + type: "bit [X-1:0]" + isrand: "False" + iscompare: "False" + + - name: "wuser" + type: "bit [X-1:0]" + isrand: "True" + iscompare: "False" + + #write response channel + - name: "bwvalid" + type: "bit" + isrand: "False" + iscompare: "False" + + - name: "bwready" + type: "bit" + isrand: "False" + iscompare: "False" + + - name: "bresp" + type: "bit" + isrand: "True" + iscompare: "False" + + - name: "bid" + type: "bit [X-1:0]" + isrand: "False" + iscompare: "False" + + - name: "buser" + type: "bit [X-1:0]" + isrand: "True" + iscompare: "False" + + #ready address channel + - name: "arvalid" + type: "bit" + isrand: "False" + iscompare: "False" + + - name: "aready" + type: "bit" + isrand: "False" + iscompare: "False" + + - name: "araddr" + type: "bit [AW_WIDTH-1:0]" + isrand: "True" + iscompare: "False" + + - name: "arsize" + type: "bit" + isrand: "True" + iscompare: "False" + + - name: "arburst" + type: "bit" + isrand: "True" + iscompare: "False" + + - name: "arcache" + type: "bit" + isrand: "True" + iscompare: "False" + + - name: "arprot" + type: "bit" + isrand: "True" + iscompare: "False" + + - name: "arid" + type: "bit [X-1:0]" + isrand: "True" + iscompare: "False" + + - name: "arlen" + type: "bit [LEN-1:0]" + isrand: "True" + iscompare: "False" + + - name: "arlock" + type: "bit" + isrand: "True" + iscompare: "False" + + - name: "arqos" + type: "bit" + isrand: "True" + iscompare: "False" + + - name: "aregion" + type: "bit" + isrand: "True" + iscompare: "False" + + - name: "aruser" + type: "bit [X-1:0]" + isrand: "True" + iscompare: "False" + + #ready data channel + + - name: "rvalid" + type: "bit" + isrand: "False" + iscompare: "False" + + - name: "rready" + type: "bit" + isrand: "False" + iscompare: "False" + + - name: "rlast" + type: "bit" + isrand: "False" + iscompare: "False" + + - name: "rdata" + type: "bit [DATA_WIDTH-1:0]" + isrand: "True" + iscompare: "False" + + - name: "rid" + type: "bit [X-1:0]" + isrand: "True" + iscompare: "False" + + - name: "ruser" + type: "bit [X-1:0]" + isrand: "True" + iscompare: "False" + + - name: "rresp" + type: "bit" + isrand: "True" + iscompare: "False" + + + + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/intf/axi_s_intf.yaml b/UVM_Framework/UVMF_2022.3/challenge_3/intf/axi_s_intf.yaml new file mode 100644 index 00000000..0e3aa936 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/intf/axi_s_intf.yaml @@ -0,0 +1,396 @@ +uvmf: + interfaces: + "axi_s": + clock: axi_clk + reset: rst + reset_assertion_level: "False" + veloce_ready: "True" + parameters: + - name: "AW_WIDTH" + type: "int" + value: "32" + - name: "LEN" + type: "int" + value: "8" + - name: "DATA_WIDTH" + type: "int" + value: "32" + - name: "X" + type: "int" + value: "16" + ports: + # write address channel + - name: awvalid + dir: input + width: "1" + - name: awready + dir: output + width: "1" + - name: awaddr + dir: input + width: "AW_WIDTH" + - name: awsize + dir: input + width: "3" + - name: awburst + dir: input + width: "2" + - name: awcache + dir: input + width: "4" + - name: awprot + dir: input + width: "3" + - name: awid + dir: input + width: "X" + - name: awlen + dir: input + width: "LEN" + - name: awlock + dir: input + width: "1" + - name: awqos + dir: input + width: "4" + - name: awregion + dir: input + width: "4" + - name: awuser + dir: input + width: "X" + # write data channel + - name: wvalid + dir: input + width: "1" + - name: wready + dir: output + width: "1" + - name: wlast + dir: input + width: "1" + - name: wdata + dir: input + width: "DATA_WIDTH" + - name: wstrb + dir: input + width: "DATA_WIDTH/8" + - name: wid + dir: input + width: "X" + - name: wuser + dir: input + width: "X" + # write response channel + - name: bwvalid + dir: output + width: "1" + - name: bwready + dir: output + width: "1" + - name: bresp + dir: input + width: "2" + - name: bid + dir: output + width: "X" + - name: buser + dir: output + width: "X" + #read address channel + - name: arvalid + dir: input + width: "1" + - name: aready + dir: output + width: "1" + - name: araddr + dir: input + width: "AW_WIDTH" + - name: arsize + dir: input + width: "3" + - name: arburst + dir: input + width: "2" + - name: arcache + dir: input + width: "4" + - name: arprot + dir: input + width: "3" + - name: arid + dir: input + width: "X" + - name: arlen + dir: input + width: "LEN" + - name: arlock + dir: input + width: "1" + - name: arqos + dir: input + width: "4" + - name: aregion + dir: input + width: "4" + - name: aruser + dir: input + width: "X" + #read data channel + - name: rvalid + dir: output + width: "1" + - name: rready + dir: input + width: "1" + - name: rlast + dir: output + width: "1" + - name: rdata + dir: output + width: "DATA_WIDTH" + - name: rid + dir: output + width: "X" + - name: ruser + dir: output + width: "X" + - name: rresp + dir: output + width: "2" + transaction_vars: + #write address channel + - name: "awvalid" + type: "bit" + isrand: "False" + iscompare: "False" + + - name: "awready" + type: "bit" + isrand: "False" + iscompare: "False" + + - name: "awaddr" + type: "bit [AW_WIDTH-1:0]" + isrand: "False" + iscompare: "False" + + - name: "awsize" + type: "bit" + isrand: "False" + iscompare: "False" + + - name: "awburst" + type: "bit" + isrand: "False" + iscompare: "False" + + - name: "awcache" + type: "bit" + isrand: "False" + iscompare: "False" + + - name: "awprot" + type: "bit" + isrand: "False" + iscompare: "False" + + - name: "awid" + type: "bit [X-1:0]" + isrand: "False" + iscompare: "False" + + - name: "awlen" + type: "bit [LEN-1:0]" + isrand: "False" + iscompare: "False" + + - name: "awlock" + type: "bit" + isrand: "False" + iscompare: "False" + + - name: "awqos" + type: "bit" + isrand: "False" + iscompare: "False" + + - name: "awregion" + type: "bit" + isrand: "False" + iscompare: "False" + + - name: "awuser" + type: "bit [X-1:0]" + isrand: "False" + iscompare: "False" + + #write data channel + - name: "wvalid" + type: "bit" + isrand: "False" + iscompare: "False" + + - name: "wready" + type: "bit" + isrand: "False" + iscompare: "False" + + - name: "wlast" + type: "bit" + isrand: "False" + iscompare: "False" + + - name: "wdata" + type: "bit [DATA_WIDTH-1:0]" + isrand: "False" + iscompare: "False" + + - name: "wstrb" + type: "bit [DATA_WIDTH/8-1:0]" + isrand: "False" + iscompare: "False" + + - name: "wid" + type: "bit [X-1:0]" + isrand: "False" + iscompare: "False" + + - name: "wuser" + type: "bit [X-1:0]" + isrand: "False" + iscompare: "False" + + #write response channel + - name: "bwvalid" + type: "bit" + isrand: "False" + iscompare: "False" + + - name: "bwready" + type: "bit" + isrand: "False" + iscompare: "False" + + - name: "bresp" + type: "bit" + isrand: "True" + iscompare: "False" + + - name: "bid" + type: "bit [X-1:0]" + isrand: "False" + iscompare: "False" + + - name: "buser" + type: "bit [X-1:0]" + isrand: "True" + iscompare: "False" + + #ready address channeli + - name: "arvalid" + type: "bit" + isrand: "False" + iscompare: "False" + + - name: "aready" + type: "bit" + isrand: "False" + iscompare: "False" + + - name: "araddr" + type: "bit [AW_WIDTH-1:0]" + isrand: "True" + iscompare: "False" + + - name: "arsize" + type: "bit" + isrand: "True" + iscompare: "False" + + - name: "arburst" + type: "bit" + isrand: "True" + iscompare: "False" + + - name: "arcache" + type: "bit" + isrand: "True" + iscompare: "False" + + - name: "arprot" + type: "bit" + isrand: "True" + iscompare: "False" + + - name: "arid" + type: "bit [X-1:0]" + isrand: "True" + iscompare: "False" + + - name: "arlen" + type: "bit [LEN-1:0]" + isrand: "True" + iscompare: "False" + + - name: "arlock" + type: "bit" + isrand: "True" + iscompare: "False" + + - name: "arqos" + type: "bit" + isrand: "True" + iscompare: "False" + + - name: "aregion" + type: "bit" + isrand: "False" + iscompare: "False" + + - name: "aruser" + type: "bit [X-1:0]" + isrand: "False" + iscompare: "False" + + #ready data channel + + - name: "rvalid" + type: "bit" + isrand: "False" + iscompare: "False" + + - name: "rready" + type: "bit" + isrand: "False" + iscompare: "False" + + - name: "rlast" + type: "bit" + isrand: "False" + iscompare: "False" + + - name: "rdata" + type: "bit [DATA_WIDTH-1:0]" + isrand: "True" + iscompare: "False" + + - name: "rid" + type: "bit [X-1:0]" + isrand: "True" + iscompare: "False" + + - name: "ruser" + type: "bit [X-1:0]" + isrand: "True" + iscompare: "False" + + - name: "rresp" + type: "bit" + isrand: "True" + iscompare: "False" + + + + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/intf/spi_m_intf.yaml b/UVM_Framework/UVMF_2022.3/challenge_3/intf/spi_m_intf.yaml new file mode 100644 index 00000000..37ddf31a --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/intf/spi_m_intf.yaml @@ -0,0 +1,36 @@ +uvmf: + interfaces: + "spi_m": + clock: "sck" + reset: "rst" + reset_assertion_level: "True" + ports: + - name: "sclk" + dir: "output" + width: "1" + reset_value: "'b0" + - name: "ss" + dir: "output" + width: "1" + reset_value: "'b0" + - name: "mosi" + dir: "output" + width: '8' + reset_value: "'b0" + - name: "miso" + dir: "input" + width: '8' + reset_value: "'b0" + transaction_vars: + - iscompare: "True" + isrand: "True" + name: "ssel" + type: "bit" + - iscompare: "True" + isrand: "True" + name: "mosi" + type: "bit [7:0]" + - iscompare: "True" + isrand: "False" + name: "miso" + type: "bit [7:0]" diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/intf/spi_s_intf.yaml b/UVM_Framework/UVMF_2022.3/challenge_3/intf/spi_s_intf.yaml new file mode 100644 index 00000000..5b6d832b --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/intf/spi_s_intf.yaml @@ -0,0 +1,36 @@ +uvmf: + interfaces: + "spi_s": + clock: "sck" + reset: "rst" + reset_assertion_level: "True" + ports: + - name: "sclk" + dir: "input" + width: "1" + reset_value: "'b0" + - name: "ss" + dir: "input" + width: "1" + reset_value: "'b0" + - name: "mosi" + dir: "input" + width: '8' + reset_value: "'b0" + - name: "miso" + dir: "output" + width: '8' + reset_value: "'b0" + transaction_vars: + - iscompare: "True" + isrand: "False" + name: "ssel" + type: "bit" + - iscompare: "True" + isrand: "False" + name: "mosi" + type: "bit [7:0]" + - iscompare: "True" + isrand: "True" + name: "miso" + type: "bit [7:0]" diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/intf/wb_m_intf.yaml b/UVM_Framework/UVMF_2022.3/challenge_3/intf/wb_m_intf.yaml new file mode 100644 index 00000000..368d70a2 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/intf/wb_m_intf.yaml @@ -0,0 +1,73 @@ +uvmf: + interfaces: + "wb_m": + clock: "clock" + reset: "reset" + reset_assertion_level: 'True' + parameters: + - name: WB_ADDR_WIDTH + type: int + value: '32' + - name: WB_DATA_WIDTH + type: int + value: '16' + ports: + - dir: input + name: din + reset_value: '''b0' + width: WB_DATA_WIDTH + - dir: output + name: dout + reset_value: '''b0' + width: WB_DATA_WIDTH + - dir: input + name: "TGD_I" + width: WB_DATA_WIDTH + - dir: output + name: "TGD_O" + width: WB_DATA_WIDTH + - dir: output + name: ack + reset_value: 1'b0 + width: '1' + - dir: output + name: adr + reset_value: '''b0' + width: WB_ADDR_WIDTH + - dir: output + name: cyc + reset_value: '0' + width: '1' + - dir: input + name: err + reset_value: '''b0' + width: '1' + - dir: output + name: we + reset_value: '0' + width: '1' + - dir: output + name: stb + reset_value: '0' + width: '1' + - dir: output + name: sel + reset_value: '''b0' + width: WB_DATA_WIDTH/8 + transaction_vars: + - iscompare: 'True' + isrand: 'True' + name: data + type: "bit [WB_DATA_WIDTH-1:0]" + - iscompare: 'True' + isrand: 'True' + name: byte_select + type: "bit [(WB_DATA_WIDTH/8)-1:0]" + - iscompare: "True" + isrand: "True" + name: WrENB + type: "bit" + - iscompare: "True" + isrand: "True" + name: selslv + type: "bit" diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/intf/wb_s_intf.yaml b/UVM_Framework/UVMF_2022.3/challenge_3/intf/wb_s_intf.yaml new file mode 100644 index 00000000..8d5eadf0 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/intf/wb_s_intf.yaml @@ -0,0 +1,61 @@ +uvmf: + interfaces: + "wb_s": + clock: "clock" + reset: "reset" + reset_assertion_level: 'True' + parameters: + - name: "WB_ADDR_WIDTH" + type: int + value: '32' + - name: "WB_DATA_WIDTH" + type: int + value: '16' + ports: + - dir: "input" + name: "din" + reset_value: '''b0' + width: "WB_DATA_WIDTH" + - dir: "output" + name: "dout" + reset_value: '''b0' + width: "WB_DATA_WIDTH" + - dir: "input" + name: "TGD_I" + width: "WB_DATA_WIDTH" + - dir: "output" + name: "TGD_O" + width: "WB_DATA_WIDTH" + - dir: "output" + name: "ack" + reset_value: '''b0' + width: '1' + - dir: "input" + name: "adr" + reset_value: '''b0' + width: "WB_ADDR_WIDTH" + - dir: "input" + name: "cyc" + reset_value: '0' + width: '1' + - dir: "output" + name: "err" + reset_value: '''b0' + width: '1' + - dir: "input" + name: "we" + reset_value: '0' + width: '1' + - dir: "input" + name: "stb" + reset_value: '0' + width: '1' + - dir: "input" + name: "sel" + reset_value: '''b0' + width: "WB_DATA_WIDTH/8" + transaction_vars: + - iscompare: 'True' + isrand: 'True' + name: "data" + type: "bit [WB_DATA_WIDTH-1:0]" diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/subsystem.csh b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/subsystem.csh new file mode 100644 index 00000000..947a3a1c --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/subsystem.csh @@ -0,0 +1,7 @@ +# Setting the path for making "make cli" command works fine. + +setenv UVMF_HOME /hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3/ + +# This is the command to generate you subsystem_1_level bench + +python ../../../UVMF_2022.3/scripts/yaml2uvmf.py ../intf/apb_m_intf.yaml ../intf/axi_m_intf.yaml ../intf/axi_s_intf.yaml ../intf/spi_s_intf.yaml ../intf/spi_m_intf.yaml ../intf/wb_s_intf.yaml ../block_1/block1_env.yaml ../block_1/block1_util.yaml ../block_2/block2_env.yaml ../block_2/block2_util.yaml ../subsystem/subsystem.yaml ../subsystem/subsystem_utils.yaml diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/subsystem.yaml b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/subsystem.yaml new file mode 100644 index 00000000..d9c9aef5 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/subsystem.yaml @@ -0,0 +1,67 @@ +uvmf: + benches: + "subsys" : + ## Specify the top-level block + top_env: "subsys" + clock_half_period: "5ns" + reset_assertion_level: "True" + reset_duration: "200ns" + active_passive: + - bfm_name: "b1_spi_slave" + value: "PASSIVE" + - bfm_name: "b2_spi_master" + value: "PASSIVE" + + environments: + "subsys": + subenvs: + - name: "b1" + type: "block_1" + - name: "b2" + type: "block_2" + analysis_components: + - name: "sub_pred" + type: "subsys_predictor" + - name: "sub_sb" + type: "subsys_scoreboard" + + # Importing the individual interfacing agent packages + imports: + - name: apb_m_pkg + - name: axi_m_pkg + - name: wb_s_pkg + + analysis_ports : + - name: "block_1_ap1" + trans_type: "apb_m_transaction" + connected_to: "b1.apb_master_ap" + + - name: "block_1_ap2" + trans_type: "axi_m_transaction" + connected_to: "b1.axi_master1_ap" + + - name: "block_1_ap3" + trans_type: "axi_m_transaction" + connected_to: "b1.axi_master2_ap" + + - name: "block_2_ap1" + trans_type: "wb_s_transaction" + connected_to: "b2.wb_slave_ap" + + tlm_connections: + - driver: "b1.apb_master_ap" + receiver: "sub_pred.subsys_apb_ae" + - driver: "b1.axi_master1_ap" + receiver: "sub_pred.subsys_axi_1_ae" + - driver: "b1.axi_master2_ap" + receiver: "sub_pred.subsys_axi_2_ae" + + - driver: "sub_pred.subsys_pre_to_sco_ap" + receiver: "sub_sb.subsys_sco_from_pre_ae" + - driver: "b2.wb_slave_ap" + receiver: "sub_sb.subsys_wb_ae" + + config_vars : + - name: "has_scoreboard" + type : "bit" + isrand : "False" diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/subsystem_utils.yaml b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/subsystem_utils.yaml new file mode 100644 index 00000000..7af87c8c --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/subsystem_utils.yaml @@ -0,0 +1,26 @@ +uvmf: + util_components: + subsys_predictor: + analysis_exports: + - name: "subsys_apb_ae" + type: "apb_m_transaction" + - name: "subsys_axi_1_ae" + type: "axi_m_transaction" + - name: "subsys_axi_2_ae" + type: "axi_m_transaction" + analysis_ports: + - name: "subsys_pre_to_sco_ap" + type: "wb_s_transaction" + existing_library_component: 'True' + type: predictor + subsys_scoreboard: + analysis_exports: + - name: "subsys_wb_ae" + type: "wb_s_transaction" + - name: "subsys_sco_from_pre_ae" + type: "wb_s_transaction" + type: scoreboard + + + + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/block_1/.project b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/block_1/.project new file mode 100644 index 00000000..f8d875b5 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/block_1/.project @@ -0,0 +1,37 @@ + + + block_1 + + + + + + org.python.pydev.PyDevBuilder + + + + + net.sf.sveditor.core.SVProjectBuilder + + + + + + net.sf.sveditor.core.SVNature + org.python.pydev.pythonNature + + + + verification_ip + 2 + UVMF_VIP_LIBRARY_HOME + + + + + UVMF_VIP_LIBRARY_HOME + $%7BPARENT-2-PROJECT_LOC%7D/verification_ip + + + + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/block_1/.svproject b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/block_1/.svproject new file mode 100644 index 00000000..2bcfbf34 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/block_1/.svproject @@ -0,0 +1,16 @@ + + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/block_1/block_1_sve.F b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/block_1/block_1_sve.F new file mode 100644 index 00000000..08e278c3 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/block_1/block_1_sve.F @@ -0,0 +1,29 @@ + +// UVM ++incdir+${UVM_HOME}/src +${UVM_HOME}/src/uvm_pkg.sv + +// Common UVMF files +-f ${UVMF_HOME}/common/common_sve.f + +// BFM Files +-F ${UVMF_VIP_LIBRARY_HOME}/interface_packages/apb_m_pkg/apb_m_pkg_sve.F +-F ${UVMF_VIP_LIBRARY_HOME}/interface_packages/axi_m_pkg/axi_m_pkg_sve.F +-F ${UVMF_VIP_LIBRARY_HOME}/interface_packages/spi_s_pkg/spi_s_pkg_sve.F + +// Environment Files +-F ${UVMF_VIP_LIBRARY_HOME}/environment_packages/block_1_env_pkg/block_1_env_pkg_sve.F + +// Bench Files ++incdir+./tb/tests +./tb/tests/block_1_tests_pkg.sv + ++incdir+./tb/sequences +./tb/sequences/block_1_sequences_pkg.sv + ++incdir+./tb/parameters +./tb/parameters/block_1_parameters_pkg.sv + +./tb/testbench/hdl_top.sv +./tb/testbench/hvl_top.sv + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/block_1/docs/interfaces.csv b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/block_1/docs/interfaces.csv new file mode 100644 index 00000000..784f480a --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/block_1/docs/interfaces.csv @@ -0,0 +1,16 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// + +, +Interface Description, Interface Type, Interface Transaction, Interface Name, +apb_master, apb_m_driver_bfm apb_m_monitor_bfm, apb_m_transaction, apb_m_pkg_apb_master_BFM, +axi_master1, axi_m_driver_bfm axi_m_monitor_bfm, axi_m_transaction, axi_m_pkg_axi_master1_BFM, +axi_master2, axi_m_driver_bfm axi_m_monitor_bfm, axi_m_transaction, axi_m_pkg_axi_master2_BFM, +spi_slave, spi_s_driver_bfm spi_s_monitor_bfm, spi_s_transaction, spi_s_pkg_spi_slave_BFM, + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/block_1/rtl/dut.compile b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/block_1/rtl/dut.compile new file mode 100644 index 00000000..9b0008fc --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/block_1/rtl/dut.compile @@ -0,0 +1,6 @@ + +# pragma uvmf custom dut_compile_info begin +src: + - ./vhdl/vhdl_dut.vhd + - ./verilog/verilog_dut.v +# pragma uvmf custom dut_compile_info end diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/block_1/rtl/verilog/verilog_dut.v b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/block_1/rtl/verilog/verilog_dut.v new file mode 100644 index 00000000..96198441 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/block_1/rtl/verilog/verilog_dut.v @@ -0,0 +1,21 @@ +module verilog_dut(clk, rst, in_signal, out_signal); + +input clk; +input rst; +input in_signal; +output out_signal; + +reg out_signal_o; + +always @(posedge clk) begin + if (rst) begin + out_signal_o <= 0; + end + else begin + out_signal_o <= ~in_signal; + end + end + +assign out_signal = out_signal_o; + +endmodule diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/block_1/rtl/verilog/verilog_dut.vinfo b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/block_1/rtl/verilog/verilog_dut.vinfo new file mode 100644 index 00000000..87e95f36 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/block_1/rtl/verilog/verilog_dut.vinfo @@ -0,0 +1 @@ +verilog_dut.v diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/block_1/rtl/vhdl/vhdl_dut.vhd b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/block_1/rtl/vhdl/vhdl_dut.vhd new file mode 100644 index 00000000..904aa37d --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/block_1/rtl/vhdl/vhdl_dut.vhd @@ -0,0 +1,21 @@ +library ieee; +use ieee.std_logic_1164.all ; + +entity vhdl_dut is + port ( clk : in std_logic ; + rst : in std_logic ; + in_signal : in std_logic ; + out_signal :out std_logic + ); +end vhdl_dut; + +architecture rtl of vhdl_dut is + begin + P1: process + variable out_signal_o : std_logic; + begin + wait until clk'event and clk = '1'; + out_signal_o := in_signal; + out_signal <= out_signal_o; + end process; + end rtl; diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/block_1/sim/Makefile b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/block_1/sim/Makefile new file mode 100644 index 00000000..8bf96331 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/block_1/sim/Makefile @@ -0,0 +1,200 @@ + +# +#---------------------------------------------------------------------- +# +# DESCRIPTION: This makefile includes the shared makefile and contains +# bench level make targets. +# +#---------------------------------------------------------------------- + + +# pragma uvmf custom additional begin +# pragma uvmf custom additional end + +# ********************************************************************************************* +# UVMF library directory: +# This variable points to the UVMF release where uvmf_base_pkg directory resides. +# This variable points to release code that is not user modified. +# This variable allows for UVMF release directories to reside independent of project related verification IP and project bench directories. +# This code below looks "upward" for directory starting with UVMF_* and returns first match for use with the release examples. +UVMF_HOME ?= ___PLEASE_SET_AN_ENVIRONMENT_VARIABLE_NAMED_UVMF_HOME_TO_POINT_TO_THE_UVMF_INSTALLATION___ + +# pragma uvmf custom exports begin +# +# Project(s) specific verification IP library: +# Directory where reusable verification packages for interfaces, environments, utilities, etc. reside. +# This variable allows for your verification IP to reside independent of project bench and UVMF release directories. +# For examples deployed with UVMF this will be $(UVMF_HOME)//verification_ip +export UVMF_VIP_LIBRARY_HOME ?= $(PWD)/../../../verification_ip +# +# Project specific bench: +# Directory where bench specific code is located. +# This variable allows for project_benches to reside independent of verification IP and UVMF release directories. +# For examples deployed with UVMF this will be $(UVMF_HOME)//project_benches/ +export UVMF_PROJECT_DIR ?= $(PWD)/.. +# +# +# pragma uvmf custom exports end +# ********************************************************************************************* + +## Check PATH for required vinfo scripts +PVAL := $(shell command -v make_filelist.py 2> /dev/null) +ifndef PVAL + MFLIST = $(UVMF_HOME)/scripts/make_filelist.py +else + MFLIST = make_filelist.py +endif + + +# Set test case specific Variables +TEST_NAME ?= test_top + +TEST_SEED ?= random +UVM_CLI_ARGS = + +# Usage of Veloce, etc. to be input by the user (subject to defaults) +USE_VELOCE ?= 0 + +# Usage of vinfo flow for generating file list +USE_VINFO ?= 0 + +# Usage of Veloce and Questa profilers +USE_VELOCE_PROFILER ?= 0 +USE_QUESTA_PROFILER ?= 0 + + +# Set project Variables +TEST_PLAN_NAME = block_1_TestPlan +REPORTING_DO_FILE = block_1_reports_script + + +# Include makefile that includes targets for UVM_VIP_Library packages +include $(UVMF_HOME)/scripts/Makefile + + + + +# Include all requisite interface package targets for this bench +include $(UVMF_VIP_LIBRARY_HOME)/interface_packages/apb_m_pkg/Makefile +include $(UVMF_VIP_LIBRARY_HOME)/interface_packages/axi_m_pkg/Makefile +include $(UVMF_VIP_LIBRARY_HOME)/interface_packages/spi_s_pkg/Makefile + +# Include all requisite environment package targets for this bench +include $(UVMF_VIP_LIBRARY_HOME)/environment_packages/block_1_env_pkg/Makefile + + + +# Add to default compile/load/run arguments +VCOM_ARGS += + +# Note: vsim-3009 error can be eliminated by adding -timescale 1ps/1ps to VLOG_ARGS + +VLOG_ARGS += $(UVM_DISABLE_FILE_LINE_CMD) + +VELANALYZE_ARGS += +VELANALYZE_HVL_ARGS += + +BATCH_VOPT_ARGS += +DEBUG_VOPT_ARGS += +EXTRA_VOPT_TOPS += +COMMON_VSIM_ARGS += +COMMON_VSIM_ARGS += + + +BATCH_VSIM_ARGS += #-uvmcontrol=none +DEBUG_VSIM_ARGS += +EXTRA_VSIM_TOPS += + +# pragma uvmf custom additional_args begin +# pragma uvmf custom additional_args end + + +# Project bench package source +block_1_PARAMETERS_PKG ?=\ +$(UVMF_PROJECT_DIR)/tb/parameters/block_1_parameters_pkg.sv + + +block_1_SEQUENCES_PKG ?=\ +$(UVMF_PROJECT_DIR)/tb/sequences/block_1_sequences_pkg.sv + + +block_1_TEST_PKG ?=\ +$(UVMF_PROJECT_DIR)/tb/tests/block_1_tests_pkg.sv + +# pragma uvmf custom dut_files begin +# UVMF_CHANGE_ME : Reference Verilog DUT source. +block_1_VERILOG_DUT ?=\ +$(UVMF_PROJECT_DIR)/rtl/verilog/verilog_dut.v + +# UVMF_CHANGE_ME : Reference VHDL DUT source. +block_1_VHDL_DUT ?=\ +$(UVMF_PROJECT_DIR)/rtl/vhdl/vhdl_dut.vhd +# pragma uvmf custom dut_files end + + +# Project bench package targets +COMP_block_1_PARAMETERS_PKG_TGT_0 = q_comp_block_1_parameters_pkg +COMP_block_1_PARAMETERS_PKG_TGT_1 = v_comp_block_1_parameters_pkg +COMP_block_1_PARAMETERS_PKG_TGT = $(COMP_block_1_PARAMETERS_PKG_TGT_$(USE_VELOCE)) + +comp_block_1_parameters_pkg: $(COMP_block_1_PARAMETERS_PKG_TGT) + +q_comp_block_1_parameters_pkg: + $(HVL_COMP_CMD) +incdir+$(UVMF_PROJECT_DIR)/tb/parameters $(block_1_PARAMETERS_PKG) + +v_comp_block_1_parameters_pkg: q_comp_block_1_parameters_pkg + $(HDL_COMP_CMD) +incdir+$(UVMF_PROJECT_DIR)/tb/parameters $(block_1_PARAMETERS_PKG) + + +comp_block_1_sequence_pkg: + $(HVL_COMP_CMD) +incdir+$(UVMF_PROJECT_DIR)/tb/sequences $(block_1_SEQUENCES_PKG) + +comp_block_1_tests_pkg: + $(HVL_COMP_CMD) +incdir+$(UVMF_PROJECT_DIR)/tb/tests $(block_1_TEST_PKG) + +# pragma uvmf custom dut_compile_make_target begin +# UVMF_CHANGE_ME : Add make target to compile your verilog dut here +comp_block_1_verilog_dut: + echo "Compile your verilog DUT here" + $(HDL_COMP_CMD) $(block_1_VERILOG_DUT) + +# UVMF_CHANGE_ME : Add make target to compile your vhdl dut here +comp_block_1_vhdl_dut: + echo "Compile your vhdl DUT here" + $(HDL_COMP_CMD_VHDL) $(block_1_VHDL_DUT) + +# UVMF_CHANGE_ME : Add make target to compile your dut here +comp_block_1_dut: comp_block_1_vhdl_dut comp_block_1_verilog_dut +# pragma uvmf custom dut_compile_make_target end + + +BUILD_TGT_0 = make_build +BUILD_TGT_1 = vinfo_build +BUILD_TGT = $(BUILD_TGT_$(USE_VINFO)) + + +comp_hvl : comp_hvl_core + + +comp_hvl_core : \ + comp_apb_m_pkg comp_axi_m_pkg comp_spi_s_pkg \ + comp_block_1_env_pkg \ + comp_block_1_parameters_pkg comp_block_1_sequence_pkg comp_block_1_tests_pkg + +comp_uvmf_core : comp_uvm_pkg comp_uvmf_base_pkg + +make_build: comp_block_1_dut comp_uvmf_core comp_hvl comp_test_bench + +hvl_build: q_comp_apb_m_pkg q_comp_axi_m_pkg q_comp_spi_s_pkg comp_block_1_env_pkg comp_block_1_sequence_pkg comp_block_1_tests_pkg hvl_comp_testbench link optimize + + +vinfo_build: comp_block_1_vhdl_dut build_hdl_vinfo build_hvl_vinfo $(VINFO_TGT) + + $(HDL_COMP_CMD) -F hdl.vf + $(VEL_COMP) + +build: $(BUILD_TGT) + +# pragma uvmf custom additional_targets begin +# pragma uvmf custom additional_targets end + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/block_1/sim/bcr_testlist b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/block_1/sim/bcr_testlist new file mode 100644 index 00000000..def2371e --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/block_1/sim/bcr_testlist @@ -0,0 +1,19 @@ + + + +# Test list for use by RMDB file +# File syntax is +# TB_INFO { } { } +# TB ## All subsequent tests will run on this bench until a different "TB" line is seen +# TEST <1st_seed> ... +# If not enough seeds are provided then random seeds are used to pad +# If no repeat count is given, default is 1 +# pragma uvmf custom tb_info begin +TB_INFO block_1 { } { } +# pragma uvmf custom tb_info end +TB block_1 +# pragma uvmf custom regression_suite begin +TEST test_top 3 +# pragma uvmf custom regression_suite end + + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/block_1/sim/bcr_testlist.yaml b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/block_1/sim/bcr_testlist.yaml new file mode 100644 index 00000000..e9f7fa3e --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/block_1/sim/bcr_testlist.yaml @@ -0,0 +1,44 @@ + + + +# YAML test list for use by RMDB file +# File syntax is +# uvmf_testlist: +# testbenches: +# - name: +# extra_build_options: +# extra_run_options: +# - name: +# ... +# - name: +# tests: +# - name: +# uvm_testname: (defaults to test_name) +# testbench: (defaults to last tb name seen) +# repeat: (defaults to 1) +# seeds: [,,...,] (defaults to all random) +# extra_test_options: +# - name: +# ... +# - name: +# include: +# - (relative path reference is to the including YAML file) +# - +# ... +# - + +uvmf_testlist: + testbenches: +# pragma uvmf custom tb_info begin + - name: block_1 + extra_build_options: "" + extra_run_options: "" +# pragma uvmf custom tb_info end + tests: + - testbench: block_1 +# pragma uvmf custom regression_suite begin + - name: test_top + repeat: 3 +# pragma uvmf custom regression_suite end + + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/block_1/sim/compile.do b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/block_1/sim/compile.do new file mode 100644 index 00000000..9f27636d --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/block_1/sim/compile.do @@ -0,0 +1,72 @@ + + +################################################################## +## ENVIRONMENT VARIABLES +################################################################## +quietly set ::env(UVMF_VIP_LIBRARY_HOME) ../../../verification_ip +quietly set ::env(UVMF_PROJECT_DIR) .. + +## Using VRM means that the build is occuring several more directories deeper underneath +## the sim directory, need to prepend some more '..' +if {[info exists ::env(VRM_BUILD)]} { + quietly set ::env(UVMF_VIP_LIBRARY_HOME) "../../../../../$::env(UVMF_VIP_LIBRARY_HOME)" + quietly set ::env(UVMF_PROJECT_DIR) "../../../../../$::env(UVMF_PROJECT_DIR)" +} +quietly set ::env(UVMF_VIP_LIBRARY_HOME) [file normalize $::env(UVMF_VIP_LIBRARY_HOME)] +quietly set ::env(UVMF_PROJECT_DIR) [file normalize $::env(UVMF_PROJECT_DIR)] +quietly echo "UVMF_VIP_LIBRARY_HOME = $::env(UVMF_VIP_LIBRARY_HOME)" +quietly echo "UVMF_PROJECT_DIR = $::env(UVMF_PROJECT_DIR)" + + +################################################################### +## HOUSEKEEPING : DELETE FILES THAT WILL BE REGENERATED +################################################################### +file delete -force *~ *.ucdb vsim.dbg *.vstf *.log work *.mem *.transcript.txt certe_dump.xml *.wlf covhtmlreport VRMDATA +file delete -force design.bin qwave.db dpiheader.h visualizer*.ses +file delete -force veloce.med veloce.wave veloce.map tbxbindings.h edsenv velrunopts.ini +file delete -force sv_connect.* + +################################################################### +## COMPILE DUT SOURCE CODE +################################################################### +vlib work +# pragma uvmf custom dut_compile_dofile_target begin +# UVMF_CHANGE_ME : Add commands to compile your dut here, replacing the default examples +vlog -sv -timescale 1ps/1ps -suppress 2223,2286 $env(UVMF_PROJECT_DIR)/rtl/verilog/verilog_dut.v +vcom $env(UVMF_PROJECT_DIR)/rtl/vhdl/vhdl_dut.vhd +# pragma uvmf custom dut_compile_dofile_target end + +################################################################### +## COMPILE UVMF BASE/COMMON SOURCE CODE +################################################################### +vlog -sv -timescale 1ps/1ps -suppress 2223 -suppress 2286 +incdir+$env(UVMF_HOME)/uvmf_base_pkg -F $env(UVMF_HOME)/uvmf_base_pkg/uvmf_base_pkg_filelist_hdl.f +vlog -sv -timescale 1ps/1ps -suppress 2223 -suppress 2286 +incdir+$env(UVMF_HOME)/uvmf_base_pkg -F $env(UVMF_HOME)/uvmf_base_pkg/uvmf_base_pkg_filelist_hvl.f + + +################################################################### +## UVMF INTERFACE COMPILATION +################################################################### +do $env(UVMF_VIP_LIBRARY_HOME)/interface_packages/apb_m_pkg/compile.do +do $env(UVMF_VIP_LIBRARY_HOME)/interface_packages/axi_m_pkg/compile.do +do $env(UVMF_VIP_LIBRARY_HOME)/interface_packages/spi_s_pkg/compile.do + +################################################################### +## UVMF ENVIRONMENT COMPILATION +################################################################### +do $env(UVMF_VIP_LIBRARY_HOME)/environment_packages/block_1_env_pkg/compile.do + +################################################################### +## UVMF BENCHES COMPILATION +################################################################### +vlog -sv -timescale 1ps/1ps -suppress 2223 -suppress 2286 +incdir+$env(UVMF_PROJECT_DIR)/tb/parameters $env(UVMF_PROJECT_DIR)/tb/parameters/block_1_parameters_pkg.sv +vlog -sv -timescale 1ps/1ps -suppress 2223 -suppress 2286 +incdir+$env(UVMF_PROJECT_DIR)/tb/sequences $env(UVMF_PROJECT_DIR)/tb/sequences/block_1_sequences_pkg.sv +vlog -sv -timescale 1ps/1ps -suppress 2223 -suppress 2286 +incdir+$env(UVMF_PROJECT_DIR)/tb/tests $env(UVMF_PROJECT_DIR)/tb/tests/block_1_tests_pkg.sv + +vlog -sv -timescale 1ps/1ps -suppress 2223 -suppress 2286 +incdir+$env(UVMF_PROJECT_DIR)/tb/testbench -F $env(UVMF_PROJECT_DIR)/tb/testbench/top_filelist_hdl.f +vlog -sv -timescale 1ps/1ps -suppress 2223 -suppress 2286 +incdir+$env(UVMF_PROJECT_DIR)/tb/testbench -F $env(UVMF_PROJECT_DIR)/tb/testbench/top_filelist_hvl.f + +################################################################### +## OPTIMIZATION +################################################################### +vopt hvl_top hdl_top -o optimized_batch_top_tb +vopt +acc hvl_top hdl_top -o optimized_debug_top_tb diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/block_1/sim/hdl.compile b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/block_1/sim/hdl.compile new file mode 100644 index 00000000..8e7bd41a --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/block_1/sim/hdl.compile @@ -0,0 +1,5 @@ +needs: +# pragma uvmf custom dut_compile_info begin + - ../rtl/dut.compile +# pragma uvmf custom dut_compile_info end + - ../tb/testbench/hdl_top.compile diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/block_1/sim/hdl.vinfo b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/block_1/sim/hdl.vinfo new file mode 100644 index 00000000..da27ec77 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/block_1/sim/hdl.vinfo @@ -0,0 +1 @@ +@use $UVMF_PROJECT_DIR/tb/testbench/hdl_top.vinfo diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/block_1/sim/hvl.compile b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/block_1/sim/hvl.compile new file mode 100644 index 00000000..ce952549 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/block_1/sim/hvl.compile @@ -0,0 +1,2 @@ +needs: + - ../tb/testbench/hvl_top.compile diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/block_1/sim/hvl.vinfo b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/block_1/sim/hvl.vinfo new file mode 100644 index 00000000..d22eff33 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/block_1/sim/hvl.vinfo @@ -0,0 +1 @@ +@use $UVMF_PROJECT_DIR/tb/testbench/hvl_top.vinfo diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/block_1/sim/run.do b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/block_1/sim/run.do new file mode 100644 index 00000000..101ddc48 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/block_1/sim/run.do @@ -0,0 +1,21 @@ + + +quietly set svLibs "" +quietly set extra_vsim_args "" + +################################################################### +## Check for additional vsim arguments passed using env var $UVMF_EXTRA_VSIM_ARGS +################################################################### +if {[info exists ::env(UVMF_EXTRA_VSIM_ARGS)]} { + echo "Adding more args to vsim command" + quietly set extra_vsim_args $::env(UVMF_EXTRA_VSIM_ARGS) +} + +################################################################## +## Launch Questa : generate vsim command line and execute +################################################################## +# pragma uvmf custom dut_run_dofile_target begin +# UVMF_CHANGE_ME : Change the UVM_TESTNAME plusarg to run a different test +quietly set cmd [format "vsim -i -sv_seed random +UVM_TESTNAME=test_top +UVM_VERBOSITY=UVM_HIGH -permit_unmatched_virtual_intf +notimingchecks -suppress 8887 %s %s -uvmcontrol=all -msgmode both -classdebug -assertdebug +uvm_set_config_int=*,enable_transaction_viewing,1 -do { set NoQuitOnFinish 1; onbreak {resume}; run 0; do wave.do; set PrefSource(OpenOnBreak) 0; radix hex showbase; } optimized_debug_top_tb" $svLibs $extra_vsim_args] +# pragma uvmf custom dut_run_dofile_target end +eval $cmd diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/block_1/sim/tbx.config b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/block_1/sim/tbx.config new file mode 100644 index 00000000..eec58168 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/block_1/sim/tbx.config @@ -0,0 +1,10 @@ + + + + + +comp -questa +velsyn -D1S +rtlc -allow_4ST + + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/block_1/sim/testlist b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/block_1/sim/testlist new file mode 100644 index 00000000..5ca4f2cc --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/block_1/sim/testlist @@ -0,0 +1,20 @@ + + + + +# Test list for use by RMDB file +# File syntax is +# TB_INFO { } { } +# TB ## All subsequent tests will run on this bench until a different "TB" line is seen +# TEST <1st_seed> ... +# If not enough seeds are provided then random seeds are used to pad +# If no repeat count is given, default is 1 +# pragma uvmf custom tb_info begin +TB_INFO block_1 { UVMF_VIP_LIBRARY_HOME=../../../../../../../../verification_ip UVMF_PROJECT_DIR=../../../../../../../block_1 } { } +# pragma uvmf custom tb_info end +TB block_1 +# pragma uvmf custom regression_suite begin +TEST test_top 3 +# pragma uvmf custom regression_suite end + + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/block_1/sim/testlist.yaml b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/block_1/sim/testlist.yaml new file mode 100644 index 00000000..113ec8a9 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/block_1/sim/testlist.yaml @@ -0,0 +1,44 @@ + + + +# YAML test list for use by RMDB file +# File syntax is +# uvmf_testlist: +# testbenches: +# - name: +# extra_build_options: +# extra_run_options: +# - name: +# ... +# - name: +# tests: +# - name: +# uvm_testname: (defaults to test_name) +# testbench: (defaults to last tb name seen) +# repeat: (defaults to 1) +# seeds: [,,...,] (defaults to all random) +# extra_test_options: +# - name: +# ... +# - name: +# include: +# - (relative path reference is to the including YAML file) +# - +# ... +# - + +uvmf_testlist: + testbenches: +# pragma uvmf custom tb_info begin + - name: block_1 + extra_build_options: "UVMF_VIP_LIBRARY_HOME=../../../../../../../../verification_ip UVMF_PROJECT_DIR=../../../../../../../block_1" + extra_run_options: "" +# pragma uvmf custom tb_info end + tests: + - testbench: block_1 +# pragma uvmf custom regression_suite begin + - name: test_top + repeat: 3 +# pragma uvmf custom regression_suite end + + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/block_1/sim/top.compile b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/block_1/sim/top.compile new file mode 100644 index 00000000..efd51c07 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/block_1/sim/top.compile @@ -0,0 +1,3 @@ +needs: + - hvl.compile + - hdl.compile diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/block_1/sim/veloce.config b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/block_1/sim/veloce.config new file mode 100644 index 00000000..d0975155 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/block_1/sim/veloce.config @@ -0,0 +1,26 @@ + + + + + +# pragma uvmf custom additional begin +comp -num_boards 1 +comp -hvl questa +# Please choose the correct emulator type code for +# comp -platform command or else velcomp will fail +# Available types are: +# - Veloce2 Quattro: D2 +# - Veloce2 Maximus: D2M +# - Veloce Strato TiL, Ti, and Mi: Strato +# - Veloce Strato M and Strato T: StratoM +# - comp -platform +comp -platform Strato + +rtlc -enable_tbx_pragma_checks +rtlc -allow_4ST +rtlc -allow_MDR +rtlc -compile_display +rtlc -xwave_siglist xwaves.sigs +# pragma uvmf custom additional end + + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/block_1/sim/viswave.do b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/block_1/sim/viswave.do new file mode 100644 index 00000000..5e690492 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/block_1/sim/viswave.do @@ -0,0 +1,34 @@ + + +onerror resume +wave tags F0 +wave update off + +wave spacer -backgroundcolor Salmon { apb_master } +wave add uvm_test_top.environment.apb_master.apb_master_monitor.txn_stream -radix string -tag F0 +wave group apb_master_bus +wave add -group apb_master_bus hdl_top.apb_master_bus.* -radix hexadecimal -tag F0 +wave group apb_master_bus -collapse +wave insertion [expr [wave index insertpoint] +1] +wave spacer -backgroundcolor Salmon { axi_master1 } +wave add uvm_test_top.environment.axi_master1.axi_master1_monitor.txn_stream -radix string -tag F0 +wave group axi_master1_bus +wave add -group axi_master1_bus hdl_top.axi_master1_bus.* -radix hexadecimal -tag F0 +wave group axi_master1_bus -collapse +wave insertion [expr [wave index insertpoint] +1] +wave spacer -backgroundcolor Salmon { axi_master2 } +wave add uvm_test_top.environment.axi_master2.axi_master2_monitor.txn_stream -radix string -tag F0 +wave group axi_master2_bus +wave add -group axi_master2_bus hdl_top.axi_master2_bus.* -radix hexadecimal -tag F0 +wave group axi_master2_bus -collapse +wave insertion [expr [wave index insertpoint] +1] +wave spacer -backgroundcolor Salmon { spi_slave } +wave add uvm_test_top.environment.spi_slave.spi_slave_monitor.txn_stream -radix string -tag F0 +wave group spi_slave_bus +wave add -group spi_slave_bus hdl_top.spi_slave_bus.* -radix hexadecimal -tag F0 +wave group spi_slave_bus -collapse +wave insertion [expr [wave index insertpoint] +1] + +wave update on +WaveSetStreamView + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/block_1/sim/wave.do b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/block_1/sim/wave.do new file mode 100644 index 00000000..a290af05 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/block_1/sim/wave.do @@ -0,0 +1,36 @@ + + +onerror {resume} +quietly WaveActivateNextPane {} 0 + +add wave -noupdate -divider apb_master +add wave -noupdate /uvm_root/uvm_test_top/environment/apb_master/apb_master_monitor/txn_stream +add wave -noupdate -group apb_master_bus /hdl_top/apb_master_bus/* +add wave -noupdate -divider axi_master1 +add wave -noupdate /uvm_root/uvm_test_top/environment/axi_master1/axi_master1_monitor/txn_stream +add wave -noupdate -group axi_master1_bus /hdl_top/axi_master1_bus/* +add wave -noupdate -divider axi_master2 +add wave -noupdate /uvm_root/uvm_test_top/environment/axi_master2/axi_master2_monitor/txn_stream +add wave -noupdate -group axi_master2_bus /hdl_top/axi_master2_bus/* +add wave -noupdate -divider spi_slave +add wave -noupdate /uvm_root/uvm_test_top/environment/spi_slave/spi_slave_monitor/txn_stream +add wave -noupdate -group spi_slave_bus /hdl_top/spi_slave_bus/* + +TreeUpdate [SetDefaultTree] +quietly wave cursor active 0 +configure wave -namecolwidth 472 +configure wave -valuecolwidth 100 +configure wave -justifyvalue left +configure wave -signalnamewidth 0 +configure wave -snapdistance 10 +configure wave -datasetprefix 0 +configure wave -rowmargin 4 +configure wave -childrowmargin 2 +configure wave -gridoffset 0 +configure wave -gridperiod 1 +configure wave -griddelta 40 +configure wave -timeline 0 +configure wave -timelineunits ns +update +WaveRestoreZoom {27 ns} {168 ns} + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/block_1/sim/xwaves.sigs b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/block_1/sim/xwaves.sigs new file mode 100644 index 00000000..d75f0a57 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/block_1/sim/xwaves.sigs @@ -0,0 +1,17 @@ + + + + + +# pragma uvmf custom additional begin + +Group All + +#Top level signals +hdl_top.* +#Add additional levels or individual signals as needed +hdl_top.*.* + +# pragma uvmf custom additional end + + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/block_1/tb/parameters/block_1_parameters_pkg.compile b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/block_1/tb/parameters/block_1_parameters_pkg.compile new file mode 100644 index 00000000..e2a26586 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/block_1/tb/parameters/block_1_parameters_pkg.compile @@ -0,0 +1,4 @@ +needs: + - $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg_hdl.compile +src: + - block_1_parameters_pkg.sv diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/block_1/tb/parameters/block_1_parameters_pkg.sv b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/block_1/tb/parameters/block_1_parameters_pkg.sv new file mode 100644 index 00000000..455ee2fb --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/block_1/tb/parameters/block_1_parameters_pkg.sv @@ -0,0 +1,40 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This package contains test level parameters +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// + + +package block_1_parameters_pkg; + + import uvmf_base_pkg_hdl::*; + + // pragma uvmf custom package_imports_additional begin + // pragma uvmf custom package_imports_additional end + + + // These parameters are used to uniquely identify each interface. The monitor_bfm and + // driver_bfm are placed into and retrieved from the uvm_config_db using these string + // names as the field_name. The parameter is also used to enable transaction viewing + // from the command line for selected interfaces using the UVM command line processing. + parameter string apb_master_BFM = "apb_master_BFM"; /* [0] */ + parameter string axi_master1_BFM = "axi_master1_BFM"; /* [1] */ + parameter string axi_master2_BFM = "axi_master2_BFM"; /* [2] */ + parameter string spi_slave_BFM = "spi_slave_BFM"; /* [3] */ + + // pragma uvmf custom package_item_additional begin + // pragma uvmf custom package_item_additional end + +endpackage + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/block_1/tb/parameters/block_1_parameters_pkg.vinfo b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/block_1/tb/parameters/block_1_parameters_pkg.vinfo new file mode 100644 index 00000000..8b0adcd9 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/block_1/tb/parameters/block_1_parameters_pkg.vinfo @@ -0,0 +1,2 @@ +@use $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg_hdl.vinfo +block_1_parameters_pkg.sv diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/block_1/tb/sequences/block_1_sequences_pkg.compile b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/block_1/tb/sequences/block_1_sequences_pkg.compile new file mode 100644 index 00000000..1497180c --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/block_1/tb/sequences/block_1_sequences_pkg.compile @@ -0,0 +1,9 @@ +needs: + - $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg.compile + - ../../../../verification_ip/interface_packages/apb_m_pkg/apb_m.compile + - ../../../../verification_ip/interface_packages/axi_m_pkg/axi_m.compile + - ../../../../verification_ip/interface_packages/spi_s_pkg/spi_s.compile + - ../../../../verification_ip/environment_packages/block_1_env_pkg/block_1_env_pkg.compile + - ../parameters/block_1_parameters_pkg.compile +src: + - block_1_sequences_pkg.sv diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/block_1/tb/sequences/block_1_sequences_pkg.sv b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/block_1/tb/sequences/block_1_sequences_pkg.sv new file mode 100644 index 00000000..983d03ec --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/block_1/tb/sequences/block_1_sequences_pkg.sv @@ -0,0 +1,53 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This package includes all high level sequence classes used +// in the environment. These include utility sequences and top +// level sequences. +// +// CONTAINS: +// - +// - +// +//---------------------------------------------------------------------- +// +//---------------------------------------------------------------------- +// + +package block_1_sequences_pkg; + import uvm_pkg::*; + import uvmf_base_pkg::*; + import apb_m_pkg::*; + import apb_m_pkg_hdl::*; + import axi_m_pkg::*; + import axi_m_pkg_hdl::*; + import spi_s_pkg::*; + import spi_s_pkg_hdl::*; + import block_1_parameters_pkg::*; + import block_1_env_pkg::*; + `include "uvm_macros.svh" + + // pragma uvmf custom package_imports_additional begin + // pragma uvmf custom package_imports_additional end + + `include "src/block_1_bench_sequence_base.svh" + `include "src/register_test_sequence.svh" + `include "src/example_derived_test_sequence.svh" + + // pragma uvmf custom package_item_additional begin + // UVMF_CHANGE_ME : When adding new sequences to the src directory + // be sure to add the sequence file here so that it will be + // compiled as part of the sequence package. Be sure to place + // the new sequence after any base sequences of the new sequence. + // pragma uvmf custom package_item_additional end + +endpackage + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/block_1/tb/sequences/block_1_sequences_pkg.vinfo b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/block_1/tb/sequences/block_1_sequences_pkg.vinfo new file mode 100644 index 00000000..b67a290f --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/block_1/tb/sequences/block_1_sequences_pkg.vinfo @@ -0,0 +1,8 @@ +@use $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg.vinfo +@use $UVMF_VIP_LIBRARY_HOME/interface_packages/apb_m_pkg/apb_m_pkg.vinfo +@use $UVMF_VIP_LIBRARY_HOME/interface_packages/axi_m_pkg/axi_m_pkg.vinfo +@use $UVMF_VIP_LIBRARY_HOME/interface_packages/spi_s_pkg/spi_s_pkg.vinfo +@use $UVMF_VIP_LIBRARY_HOME/environment_packages/block_1_env_pkg/block_1_env_pkg.vinfo +@use $UVMF_PROJECT_DIR/tb/parameters/block_1_parameters_pkg.vinfo ++incdir+@vinfodir +block_1_sequences_pkg.sv diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/block_1/tb/sequences/src/block_1_bench_sequence_base.svh b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/block_1/tb/sequences/src/block_1_bench_sequence_base.svh new file mode 100644 index 00000000..719d0905 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/block_1/tb/sequences/src/block_1_bench_sequence_base.svh @@ -0,0 +1,145 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// Description: This file contains the top level and utility sequences +// used by test_top. It can be extended to create derivative top +// level sequences. +// +//---------------------------------------------------------------------- +// +//---------------------------------------------------------------------- +// + + +typedef block_1_env_configuration block_1_env_configuration_t; + +class block_1_bench_sequence_base extends uvmf_sequence_base #(uvm_sequence_item); + + `uvm_object_utils( block_1_bench_sequence_base ); + + // pragma uvmf custom sequences begin + +typedef block_1_env_sequence_base #( + .CONFIG_T(block_1_env_configuration_t) + ) + block_1_env_sequence_base_t; +rand block_1_env_sequence_base_t block_1_env_seq; + + + + // UVMF_CHANGE_ME : Instantiate, construct, and start sequences as needed to create stimulus scenarios. + // Instantiate sequences here + typedef apb_m_random_sequence apb_master_random_seq_t; + apb_master_random_seq_t apb_master_random_seq; + typedef axi_m_random_sequence axi_master1_random_seq_t; + axi_master1_random_seq_t axi_master1_random_seq; + typedef axi_m_random_sequence axi_master2_random_seq_t; + axi_master2_random_seq_t axi_master2_random_seq; + // pragma uvmf custom sequences end + + // Sequencer handles for each active interface in the environment + typedef apb_m_transaction apb_master_transaction_t; + uvm_sequencer #(apb_master_transaction_t) apb_master_sequencer; + typedef axi_m_transaction axi_master1_transaction_t; + uvm_sequencer #(axi_master1_transaction_t) axi_master1_sequencer; + typedef axi_m_transaction axi_master2_transaction_t; + uvm_sequencer #(axi_master2_transaction_t) axi_master2_sequencer; + + + // Top level environment configuration handle + block_1_env_configuration_t top_configuration; + + // Configuration handles to access interface BFM's + apb_m_configuration apb_master_config; + axi_m_configuration axi_master1_config; + axi_m_configuration axi_master2_config; + spi_s_configuration spi_slave_config; + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + // **************************************************************************** + function new( string name = "" ); + super.new( name ); + // Retrieve the configuration handles from the uvm_config_db + + // Retrieve top level configuration handle + if ( !uvm_config_db#(block_1_env_configuration_t)::get(null,UVMF_CONFIGURATIONS, "TOP_ENV_CONFIG",top_configuration) ) begin + `uvm_info("CFG", "*** FATAL *** uvm_config_db::get can not find TOP_ENV_CONFIG. Are you using an older UVMF release than what was used to generate this bench?",UVM_NONE); + `uvm_fatal("CFG", "uvm_config_db#(block_1_env_configuration_t)::get cannot find resource TOP_ENV_CONFIG"); + end + + // Retrieve config handles for all agents + if( !uvm_config_db #( apb_m_configuration )::get( null , UVMF_CONFIGURATIONS , apb_master_BFM , apb_master_config ) ) + `uvm_fatal("CFG" , "uvm_config_db #( apb_m_configuration )::get cannot find resource apb_master_BFM" ) + if( !uvm_config_db #( axi_m_configuration )::get( null , UVMF_CONFIGURATIONS , axi_master1_BFM , axi_master1_config ) ) + `uvm_fatal("CFG" , "uvm_config_db #( axi_m_configuration )::get cannot find resource axi_master1_BFM" ) + if( !uvm_config_db #( axi_m_configuration )::get( null , UVMF_CONFIGURATIONS , axi_master2_BFM , axi_master2_config ) ) + `uvm_fatal("CFG" , "uvm_config_db #( axi_m_configuration )::get cannot find resource axi_master2_BFM" ) + if( !uvm_config_db #( spi_s_configuration )::get( null , UVMF_CONFIGURATIONS , spi_slave_BFM , spi_slave_config ) ) + `uvm_fatal("CFG" , "uvm_config_db #( spi_s_configuration )::get cannot find resource spi_slave_BFM" ) + + // Assign the sequencer handles from the handles within agent configurations + apb_master_sequencer = apb_master_config.get_sequencer(); + axi_master1_sequencer = axi_master1_config.get_sequencer(); + axi_master2_sequencer = axi_master2_config.get_sequencer(); + + + + // pragma uvmf custom new begin + // pragma uvmf custom new end + + endfunction + + // **************************************************************************** + virtual task body(); + // pragma uvmf custom body begin + + // Construct sequences here + + block_1_env_seq = block_1_env_sequence_base_t::type_id::create("block_1_env_seq"); + + apb_master_random_seq = apb_master_random_seq_t::type_id::create("apb_master_random_seq"); + axi_master1_random_seq = axi_master1_random_seq_t::type_id::create("axi_master1_random_seq"); + axi_master2_random_seq = axi_master2_random_seq_t::type_id::create("axi_master2_random_seq"); + fork + apb_master_config.wait_for_reset(); + axi_master1_config.wait_for_reset(); + axi_master2_config.wait_for_reset(); + spi_slave_config.wait_for_reset(); + join + // Start RESPONDER sequences here + fork + join_none + // Start INITIATOR sequences here + fork + repeat (25) apb_master_random_seq.start(apb_master_sequencer); + repeat (25) axi_master1_random_seq.start(axi_master1_sequencer); + repeat (25) axi_master2_random_seq.start(axi_master2_sequencer); + join + +block_1_env_seq.start(top_configuration.vsqr); + + // UVMF_CHANGE_ME : Extend the simulation XXX number of clocks after + // the last sequence to allow for the last sequence item to flow + // through the design. + fork + apb_master_config.wait_for_num_clocks(400); + axi_master1_config.wait_for_num_clocks(400); + axi_master2_config.wait_for_num_clocks(400); + spi_slave_config.wait_for_num_clocks(400); + join + + // pragma uvmf custom body end + endtask + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/block_1/tb/sequences/src/example_derived_test_sequence.svh b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/block_1/tb/sequences/src/example_derived_test_sequence.svh new file mode 100644 index 00000000..b4127d2f --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/block_1/tb/sequences/src/example_derived_test_sequence.svh @@ -0,0 +1,30 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +// +//---------------------------------------------------------------------- +// +// DESCRIPTION: This file contains the top level sequence used in example_derived_test. +// It is an example of a sequence that is extended from %(benchName)_bench_sequence_base +// and can override %(benchName)_bench_sequence_base. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// + +class example_derived_test_sequence extends block_1_bench_sequence_base; + + `uvm_object_utils( example_derived_test_sequence ); + + function new(string name = "" ); + super.new(name); + endfunction + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/block_1/tb/sequences/src/register_test_sequence.svh b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/block_1/tb/sequences/src/register_test_sequence.svh new file mode 100644 index 00000000..dd9e3574 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/block_1/tb/sequences/src/register_test_sequence.svh @@ -0,0 +1,59 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This file contains the top level sequence used in register_test. +// It uses the UVM built in register test. Specific UVM built-in tests can be +// selected in the body task. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// + +class register_test_sequence extends block_1_bench_sequence_base; + + `uvm_object_utils( register_test_sequence ); + + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + function new(string name = "" ); + super.new(name); + endfunction + + // **************************************************************************** + virtual task body(); + + // Reset the DUT + fork + // pragma uvmf custom register_test_reset begin + // UVMF_CHANGE_ME + // Select the desired wait_for_reset or provide custom mechanism. + // fork-join for this code block may be unnecessary based on your situation. + apb_master_config.wait_for_reset(); + axi_master1_config.wait_for_reset(); + axi_master2_config.wait_for_reset(); + spi_slave_config.wait_for_reset(); + // pragma uvmf custom register_test_reset end + join + + // pragma uvmf custom register_test_setup begin + // UVMF_CHANGE_ME perform potentially necessary operations before running the sequence. + // pragma uvmf custom register_test_setup end + + // pragma uvmf custom register_test_operation begin + // UVMF_CHANGE_ME Perform your custom register test + // pragma uvmf custom register_test_operation end + + endtask + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/block_1/tb/testbench/hdl_top.compile b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/block_1/tb/testbench/hdl_top.compile new file mode 100644 index 00000000..09b570fb --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/block_1/tb/testbench/hdl_top.compile @@ -0,0 +1,11 @@ +incdir: + - ${uvm_path}/src + - . +needs: + - $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg_hdl.compile + - ../parameters/block_1_parameters_pkg.compile + - ../../../../verification_ip/interface_packages/apb_m_pkg/apb_m_hdl.compile + - ../../../../verification_ip/interface_packages/axi_m_pkg/axi_m_hdl.compile + - ../../../../verification_ip/interface_packages/spi_s_pkg/spi_s_hdl.compile +src: + - hdl_top.sv diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/block_1/tb/testbench/hdl_top.sv b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/block_1/tb/testbench/hdl_top.sv new file mode 100644 index 00000000..d8645a94 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/block_1/tb/testbench/hdl_top.sv @@ -0,0 +1,117 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// Description: This top level module instantiates all synthesizable +// static content. This and tb_top.sv are the two top level modules +// of the simulation. +// +// This module instantiates the following: +// DUT: The Design Under Test +// Interfaces: Signal bundles that contain signals connected to DUT +// Driver BFM's: BFM's that actively drive interface signals +// Monitor BFM's: BFM's that passively monitor interface signals +// +//---------------------------------------------------------------------- + +//---------------------------------------------------------------------- +// + +module hdl_top; + +import block_1_parameters_pkg::*; +import uvmf_base_pkg_hdl::*; + + // pragma attribute hdl_top partition_module_xrtl +// pragma uvmf custom clock_generator begin + bit clk; + // Instantiate a clk driver + // tbx clkgen + initial begin + clk = 0; + #9ns; + forever begin + clk = ~clk; + #5ns; + end + end +// pragma uvmf custom clock_generator end + +// pragma uvmf custom reset_generator begin + bit rst; + // Instantiate a rst driver + // tbx clkgen + initial begin + rst = 1; + #200ns; + rst = 0; + end +// pragma uvmf custom reset_generator end + + // pragma uvmf custom module_item_additional begin + // pragma uvmf custom module_item_additional end + + // Instantiate the signal bundle, monitor bfm and driver bfm for each interface. + // The signal bundle, _if, contains signals to be connected to the DUT. + // The monitor, monitor_bfm, observes the bus, _if, and captures transactions. + // The driver, driver_bfm, drives transactions onto the bus, _if. + apb_m_if apb_master_bus( + // pragma uvmf custom apb_master_bus_connections begin + .pclk(clk), .presetn(rst) + // pragma uvmf custom apb_master_bus_connections end + ); + axi_m_if axi_master1_bus( + // pragma uvmf custom axi_master1_bus_connections begin + .axi_clk(clk), .rst(rst) + // pragma uvmf custom axi_master1_bus_connections end + ); + axi_m_if axi_master2_bus( + // pragma uvmf custom axi_master2_bus_connections begin + .axi_clk(clk), .rst(rst) + // pragma uvmf custom axi_master2_bus_connections end + ); + spi_s_if spi_slave_bus( + // pragma uvmf custom spi_slave_bus_connections begin + .sck(clk), .rst(rst) + // pragma uvmf custom spi_slave_bus_connections end + ); + apb_m_monitor_bfm apb_master_mon_bfm(apb_master_bus.monitor_port); + axi_m_monitor_bfm axi_master1_mon_bfm(axi_master1_bus.monitor_port); + axi_m_monitor_bfm axi_master2_mon_bfm(axi_master2_bus.monitor_port); + spi_s_monitor_bfm spi_slave_mon_bfm(spi_slave_bus.monitor_port); + apb_m_driver_bfm apb_master_drv_bfm(apb_master_bus.initiator_port); + axi_m_driver_bfm axi_master1_drv_bfm(axi_master1_bus.initiator_port); + axi_m_driver_bfm axi_master2_drv_bfm(axi_master2_bus.initiator_port); + + // pragma uvmf custom dut_instantiation begin + // UVMF_CHANGE_ME : Add DUT and connect to signals in _bus interfaces listed above + // Instantiate your DUT here + // These DUT's instantiated to show verilog and vhdl instantiation + verilog_dut dut_verilog( .clk(clk), .rst(rst), .in_signal(vhdl_to_verilog_signal), .out_signal(verilog_to_vhdl_signal)); + vhdl_dut dut_vhdl ( .clk(clk), .rst(rst), .in_signal(verilog_to_vhdl_signal), .out_signal(vhdl_to_verilog_signal)); + // pragma uvmf custom dut_instantiation end + + initial begin // tbx vif_binding_block + import uvm_pkg::uvm_config_db; + // The monitor_bfm and driver_bfm for each interface is placed into the uvm_config_db. + // They are placed into the uvm_config_db using the string names defined in the parameters package. + // The string names are passed to the agent configurations by test_top through the top level configuration. + // They are retrieved by the agents configuration class for use by the agent. + uvm_config_db #( virtual apb_m_monitor_bfm )::set( null , UVMF_VIRTUAL_INTERFACES , apb_master_BFM , apb_master_mon_bfm ); + uvm_config_db #( virtual axi_m_monitor_bfm )::set( null , UVMF_VIRTUAL_INTERFACES , axi_master1_BFM , axi_master1_mon_bfm ); + uvm_config_db #( virtual axi_m_monitor_bfm )::set( null , UVMF_VIRTUAL_INTERFACES , axi_master2_BFM , axi_master2_mon_bfm ); + uvm_config_db #( virtual spi_s_monitor_bfm )::set( null , UVMF_VIRTUAL_INTERFACES , spi_slave_BFM , spi_slave_mon_bfm ); + uvm_config_db #( virtual apb_m_driver_bfm )::set( null , UVMF_VIRTUAL_INTERFACES , apb_master_BFM , apb_master_drv_bfm ); + uvm_config_db #( virtual axi_m_driver_bfm )::set( null , UVMF_VIRTUAL_INTERFACES , axi_master1_BFM , axi_master1_drv_bfm ); + uvm_config_db #( virtual axi_m_driver_bfm )::set( null , UVMF_VIRTUAL_INTERFACES , axi_master2_BFM , axi_master2_drv_bfm ); + end + +endmodule + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/block_1/tb/testbench/hdl_top.vinfo b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/block_1/tb/testbench/hdl_top.vinfo new file mode 100644 index 00000000..43c7c76e --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/block_1/tb/testbench/hdl_top.vinfo @@ -0,0 +1,7 @@ +@use $UVMF_PROJECT_DIR/rtl/verilog/verilog_dut.vinfo +@use $UVMF_PROJECT_DIR/tb/parameters/block_1_parameters_pkg.vinfo +@use $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg_hdl.vinfo +@use $UVMF_VIP_LIBRARY_HOME/interface_packages/apb_m_pkg/apb_m_bfm.vinfo +@use $UVMF_VIP_LIBRARY_HOME/interface_packages/axi_m_pkg/axi_m_bfm.vinfo +@use $UVMF_VIP_LIBRARY_HOME/interface_packages/spi_s_pkg/spi_s_bfm.vinfo +hdl_top.sv diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/block_1/tb/testbench/hvl_top.compile b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/block_1/tb/testbench/hvl_top.compile new file mode 100644 index 00000000..d8d273c1 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/block_1/tb/testbench/hvl_top.compile @@ -0,0 +1,7 @@ +incdir: + - ${uvm_path}/src + - . +needs: + - ../tests/block_1_tests_pkg.compile +src: + - hvl_top.sv diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/block_1/tb/testbench/hvl_top.sv b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/block_1/tb/testbench/hvl_top.sv new file mode 100644 index 00000000..89ae61f4 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/block_1/tb/testbench/hvl_top.sv @@ -0,0 +1,33 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +// +//---------------------------------------------------------------------- +// +// DESCRIPTION: This module loads the test package and starts the UVM phases. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// + +module hvl_top; + +import uvm_pkg::*; +import block_1_tests_pkg::*; + + // pragma uvmf custom module_item_additional begin + // pragma uvmf custom module_item_additional end + + initial begin + $timeformat(-9,3,"ns",5); + run_test(); + end + +endmodule + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/block_1/tb/testbench/hvl_top.vinfo b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/block_1/tb/testbench/hvl_top.vinfo new file mode 100644 index 00000000..7bc43d3a --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/block_1/tb/testbench/hvl_top.vinfo @@ -0,0 +1,2 @@ +@use $UVMF_PROJECT_DIR/tb/tests/block_1_tests_pkg.vinfo +hvl_top.sv diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/block_1/tb/testbench/top_filelist_hdl.f b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/block_1/tb/testbench/top_filelist_hdl.f new file mode 100644 index 00000000..1e9dab65 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/block_1/tb/testbench/top_filelist_hdl.f @@ -0,0 +1,3 @@ +$UVMF_PROJECT_DIR/tb/testbench/hdl_top.sv +// pragma uvmf custom additional begin +// pragma uvmf custom additional end diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/block_1/tb/testbench/top_filelist_hvl.f b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/block_1/tb/testbench/top_filelist_hvl.f new file mode 100644 index 00000000..42383ab2 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/block_1/tb/testbench/top_filelist_hvl.f @@ -0,0 +1,3 @@ +$UVMF_PROJECT_DIR/tb/testbench/hvl_top.sv +// pragma uvmf custom additional begin +// pragma uvmf custom additional end diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/block_1/tb/tests/block_1_tests_pkg.compile b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/block_1/tb/tests/block_1_tests_pkg.compile new file mode 100644 index 00000000..ccf235f0 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/block_1/tb/tests/block_1_tests_pkg.compile @@ -0,0 +1,10 @@ +needs: + - $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg.compile + - ../../../../verification_ip/interface_packages/apb_m_pkg/apb_m.compile + - ../../../../verification_ip/interface_packages/axi_m_pkg/axi_m.compile + - ../../../../verification_ip/interface_packages/spi_s_pkg/spi_s.compile + - ../../../../verification_ip/environment_packages/block_1_env_pkg/block_1_env_pkg.compile + - ../parameters/block_1_parameters_pkg.compile + - ../sequences/block_1_sequences_pkg.compile +src: + - block_1_tests_pkg.sv diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/block_1/tb/tests/block_1_tests_pkg.sv b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/block_1/tb/tests/block_1_tests_pkg.sv new file mode 100644 index 00000000..933ace9a --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/block_1/tb/tests/block_1_tests_pkg.sv @@ -0,0 +1,56 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This package contains all tests currently written for +// the simulation project. Once compiled, any test can be selected +// from the vsim command line using +UVM_TESTNAME=yourTestNameHere +// +// CONTAINS: +// - +// - +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// + +package block_1_tests_pkg; + + import uvm_pkg::*; + import uvmf_base_pkg::*; + import block_1_parameters_pkg::*; + import block_1_env_pkg::*; + import block_1_sequences_pkg::*; + import apb_m_pkg::*; + import apb_m_pkg_hdl::*; + import axi_m_pkg::*; + import axi_m_pkg_hdl::*; + import spi_s_pkg::*; + import spi_s_pkg_hdl::*; + + + `include "uvm_macros.svh" + + // pragma uvmf custom package_imports_additional begin + // pragma uvmf custom package_imports_additional end + + `include "src/test_top.svh" + `include "src/register_test.svh" + `include "src/example_derived_test.svh" + + // pragma uvmf custom package_item_additional begin + // UVMF_CHANGE_ME : When adding new tests to the src directory + // be sure to add the test file here so that it will be + // compiled as part of the test package. Be sure to place + // the new test after any base tests of the new test. + // pragma uvmf custom package_item_additional end + +endpackage + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/block_1/tb/tests/block_1_tests_pkg.vinfo b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/block_1/tb/tests/block_1_tests_pkg.vinfo new file mode 100644 index 00000000..9fe7bfbf --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/block_1/tb/tests/block_1_tests_pkg.vinfo @@ -0,0 +1,9 @@ +@use $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg.vinfo +@use $UVMF_VIP_LIBRARY_HOME/interface_packages/apb_m_pkg/apb_m_pkg.vinfo +@use $UVMF_VIP_LIBRARY_HOME/interface_packages/axi_m_pkg/axi_m_pkg.vinfo +@use $UVMF_VIP_LIBRARY_HOME/interface_packages/spi_s_pkg/spi_s_pkg.vinfo +@use $UVMF_VIP_LIBRARY_HOME/environment_packages/block_1_env_pkg/block_1_env_pkg.vinfo +@use $UVMF_PROJECT_DIR/tb/parameters/block_1_parameters_pkg.vinfo +@use $UVMF_PROJECT_DIR/tb/sequences/block_1_sequences_pkg.vinfo ++incdir+@vinfodir +block_1_tests_pkg.sv diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/block_1/tb/tests/src/example_derived_test.svh b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/block_1/tb/tests/src/example_derived_test.svh new file mode 100644 index 00000000..346ac7c4 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/block_1/tb/tests/src/example_derived_test.svh @@ -0,0 +1,43 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This test extends test_top and makes +// changes to test_top using the UVM factory type_override: +// +// Test scenario: +// This is a template test that can be used to create future tests. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// + +class example_derived_test extends test_top; + + `uvm_component_utils( example_derived_test ); + + function new( string name = "", uvm_component parent = null ); + super.new( name, parent ); + endfunction + + virtual function void build_phase(uvm_phase phase); + // The factory override below is an example of how to replace the block_1_bench_sequence_base + // sequence with the example_derived_test_sequence. + block_1_bench_sequence_base::type_id::set_type_override(example_derived_test_sequence::get_type()); + // Execute the build_phase of test_top AFTER all factory overrides have been created. + super.build_phase(phase); + // pragma uvmf custom configuration_settings_post_randomize begin + // UVMF_CHANGE_ME Test specific configuration values can be set here. + // The configuration structure has already been randomized. + // pragma uvmf custom configuration_settings_post_randomize end + endfunction + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/block_1/tb/tests/src/register_test.svh b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/block_1/tb/tests/src/register_test.svh new file mode 100644 index 00000000..ae1d329c --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/block_1/tb/tests/src/register_test.svh @@ -0,0 +1,40 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This test extends test_top and makes +// changes to test_top using the UVM factory type_override: +// +// Test scenario: +// This is a template test that can be used to create future tests. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// + +class register_test extends test_top; + + `uvm_component_utils( register_test ); + + function new( string name = "", uvm_component parent = null ); + super.new( name, parent ); + endfunction + + virtual function void build_phase(uvm_phase phase); + // The factory override below replaces the block_1_bench_sequence_base + // sequence with the register_test_sequence. + block_1_bench_sequence_base::type_id::set_type_override(register_test_sequence::get_type()); + // Execute the build_phase of test_top AFTER all factory overrides have been created. + super.build_phase(phase); + endfunction + + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/block_1/tb/tests/src/test_top.svh b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/block_1/tb/tests/src/test_top.svh new file mode 100644 index 00000000..108d124e --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/block_1/tb/tests/src/test_top.svh @@ -0,0 +1,82 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// Description: This top level UVM test is the base class for all +// future tests created for this project. +// +// This test class contains: +// Configuration: The top level configuration for the project. +// Environment: The top level environment for the project. +// Top_level_sequence: The top level sequence for the project. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// + +typedef block_1_env_configuration block_1_env_configuration_t; +typedef block_1_environment block_1_environment_t; + +class test_top extends uvmf_test_base #(.CONFIG_T(block_1_env_configuration_t), + .ENV_T(block_1_environment_t), + .TOP_LEVEL_SEQ_T(block_1_bench_sequence_base)); + + `uvm_component_utils( test_top ); + + + + string interface_names[] = { + apb_master_BFM /* apb_master [0] */ , + axi_master1_BFM /* axi_master1 [1] */ , + axi_master2_BFM /* axi_master2 [2] */ , + spi_slave_BFM /* spi_slave [3] */ +}; + +uvmf_active_passive_t interface_activities[] = { + ACTIVE /* apb_master [0] */ , + ACTIVE /* axi_master1 [1] */ , + ACTIVE /* axi_master2 [2] */ , + PASSIVE /* spi_slave [3] */ }; + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + // **************************************************************************** + // FUNCTION: new() + // This is the standard systemVerilog constructor. All components are + // constructed in the build_phase to allow factory overriding. + // + function new( string name = "", uvm_component parent = null ); + super.new( name ,parent ); + endfunction + + + + // **************************************************************************** + // FUNCTION: build_phase() + // The construction of the configuration and environment classes is done in + // the build_phase of uvmf_test_base. Once the configuraton and environment + // classes are built then the initialize call is made to perform the + // following: + // Monitor and driver BFM virtual interface handle passing into agents + // Set the active/passive state for each agent + // Once this build_phase completes, the build_phase of the environment is + // executed which builds the agents. + // + virtual function void build_phase(uvm_phase phase); +// pragma uvmf custom build_phase_pre_super begin +// pragma uvmf custom build_phase_pre_super end + super.build_phase(phase); + // pragma uvmf custom configuration_settings_post_randomize begin + // pragma uvmf custom configuration_settings_post_randomize end + configuration.initialize(NA, "uvm_test_top.environment", interface_names, null, interface_activities); + endfunction + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/block_1/yaml/block_1_bench.yaml b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/block_1/yaml/block_1_bench.yaml new file mode 100644 index 00000000..81d1e38d --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/block_1/yaml/block_1_bench.yaml @@ -0,0 +1,21 @@ +uvmf: + benches: + block_1: + active_passive: + - bfm_name: apb_master + value: ACTIVE + - bfm_name: axi_master1 + value: ACTIVE + - bfm_name: axi_master2 + value: ACTIVE + - bfm_name: spi_slave + value: PASSIVE + active_passive_default: ACTIVE + clock_half_period: 5ns + clock_phase_offset: 9ns + existing_library_component: 'True' + interface_params: [] + reset_assertion_level: 'True' + reset_duration: 200ns + top_env: block_1 + use_dpi_link: 'False' diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/block_2/.project b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/block_2/.project new file mode 100644 index 00000000..e070225f --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/block_2/.project @@ -0,0 +1,37 @@ + + + block_2 + + + + + + org.python.pydev.PyDevBuilder + + + + + net.sf.sveditor.core.SVProjectBuilder + + + + + + net.sf.sveditor.core.SVNature + org.python.pydev.pythonNature + + + + verification_ip + 2 + UVMF_VIP_LIBRARY_HOME + + + + + UVMF_VIP_LIBRARY_HOME + $%7BPARENT-2-PROJECT_LOC%7D/verification_ip + + + + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/block_2/.svproject b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/block_2/.svproject new file mode 100644 index 00000000..b5a7f95a --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/block_2/.svproject @@ -0,0 +1,16 @@ + + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/block_2/block_2_sve.F b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/block_2/block_2_sve.F new file mode 100644 index 00000000..83f3e49e --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/block_2/block_2_sve.F @@ -0,0 +1,28 @@ + +// UVM ++incdir+${UVM_HOME}/src +${UVM_HOME}/src/uvm_pkg.sv + +// Common UVMF files +-f ${UVMF_HOME}/common/common_sve.f + +// BFM Files +-F ${UVMF_VIP_LIBRARY_HOME}/interface_packages/spi_m_pkg/spi_m_pkg_sve.F +-F ${UVMF_VIP_LIBRARY_HOME}/interface_packages/wb_s_pkg/wb_s_pkg_sve.F + +// Environment Files +-F ${UVMF_VIP_LIBRARY_HOME}/environment_packages/block_2_env_pkg/block_2_env_pkg_sve.F + +// Bench Files ++incdir+./tb/tests +./tb/tests/block_2_tests_pkg.sv + ++incdir+./tb/sequences +./tb/sequences/block_2_sequences_pkg.sv + ++incdir+./tb/parameters +./tb/parameters/block_2_parameters_pkg.sv + +./tb/testbench/hdl_top.sv +./tb/testbench/hvl_top.sv + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/block_2/docs/interfaces.csv b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/block_2/docs/interfaces.csv new file mode 100644 index 00000000..de1a17a2 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/block_2/docs/interfaces.csv @@ -0,0 +1,14 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// + +, +Interface Description, Interface Type, Interface Transaction, Interface Name, +spi_master, spi_m_driver_bfm spi_m_monitor_bfm, spi_m_transaction, spi_m_pkg_spi_master_BFM, +wb_slave, wb_s_driver_bfm wb_s_monitor_bfm, wb_s_transaction, wb_s_pkg_wb_slave_BFM, + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/block_2/rtl/dut.compile b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/block_2/rtl/dut.compile new file mode 100644 index 00000000..9b0008fc --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/block_2/rtl/dut.compile @@ -0,0 +1,6 @@ + +# pragma uvmf custom dut_compile_info begin +src: + - ./vhdl/vhdl_dut.vhd + - ./verilog/verilog_dut.v +# pragma uvmf custom dut_compile_info end diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/block_2/rtl/verilog/verilog_dut.v b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/block_2/rtl/verilog/verilog_dut.v new file mode 100644 index 00000000..96198441 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/block_2/rtl/verilog/verilog_dut.v @@ -0,0 +1,21 @@ +module verilog_dut(clk, rst, in_signal, out_signal); + +input clk; +input rst; +input in_signal; +output out_signal; + +reg out_signal_o; + +always @(posedge clk) begin + if (rst) begin + out_signal_o <= 0; + end + else begin + out_signal_o <= ~in_signal; + end + end + +assign out_signal = out_signal_o; + +endmodule diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/block_2/rtl/verilog/verilog_dut.vinfo b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/block_2/rtl/verilog/verilog_dut.vinfo new file mode 100644 index 00000000..87e95f36 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/block_2/rtl/verilog/verilog_dut.vinfo @@ -0,0 +1 @@ +verilog_dut.v diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/block_2/rtl/vhdl/vhdl_dut.vhd b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/block_2/rtl/vhdl/vhdl_dut.vhd new file mode 100644 index 00000000..904aa37d --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/block_2/rtl/vhdl/vhdl_dut.vhd @@ -0,0 +1,21 @@ +library ieee; +use ieee.std_logic_1164.all ; + +entity vhdl_dut is + port ( clk : in std_logic ; + rst : in std_logic ; + in_signal : in std_logic ; + out_signal :out std_logic + ); +end vhdl_dut; + +architecture rtl of vhdl_dut is + begin + P1: process + variable out_signal_o : std_logic; + begin + wait until clk'event and clk = '1'; + out_signal_o := in_signal; + out_signal <= out_signal_o; + end process; + end rtl; diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/block_2/sim/Makefile b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/block_2/sim/Makefile new file mode 100644 index 00000000..4bea4673 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/block_2/sim/Makefile @@ -0,0 +1,199 @@ + +# +#---------------------------------------------------------------------- +# +# DESCRIPTION: This makefile includes the shared makefile and contains +# bench level make targets. +# +#---------------------------------------------------------------------- + + +# pragma uvmf custom additional begin +# pragma uvmf custom additional end + +# ********************************************************************************************* +# UVMF library directory: +# This variable points to the UVMF release where uvmf_base_pkg directory resides. +# This variable points to release code that is not user modified. +# This variable allows for UVMF release directories to reside independent of project related verification IP and project bench directories. +# This code below looks "upward" for directory starting with UVMF_* and returns first match for use with the release examples. +UVMF_HOME ?= ___PLEASE_SET_AN_ENVIRONMENT_VARIABLE_NAMED_UVMF_HOME_TO_POINT_TO_THE_UVMF_INSTALLATION___ + +# pragma uvmf custom exports begin +# +# Project(s) specific verification IP library: +# Directory where reusable verification packages for interfaces, environments, utilities, etc. reside. +# This variable allows for your verification IP to reside independent of project bench and UVMF release directories. +# For examples deployed with UVMF this will be $(UVMF_HOME)//verification_ip +export UVMF_VIP_LIBRARY_HOME ?= $(PWD)/../../../verification_ip +# +# Project specific bench: +# Directory where bench specific code is located. +# This variable allows for project_benches to reside independent of verification IP and UVMF release directories. +# For examples deployed with UVMF this will be $(UVMF_HOME)//project_benches/ +export UVMF_PROJECT_DIR ?= $(PWD)/.. +# +# +# pragma uvmf custom exports end +# ********************************************************************************************* + +## Check PATH for required vinfo scripts +PVAL := $(shell command -v make_filelist.py 2> /dev/null) +ifndef PVAL + MFLIST = $(UVMF_HOME)/scripts/make_filelist.py +else + MFLIST = make_filelist.py +endif + + +# Set test case specific Variables +TEST_NAME ?= test_top + +TEST_SEED ?= random +UVM_CLI_ARGS = + +# Usage of Veloce, etc. to be input by the user (subject to defaults) +USE_VELOCE ?= 0 + +# Usage of vinfo flow for generating file list +USE_VINFO ?= 0 + +# Usage of Veloce and Questa profilers +USE_VELOCE_PROFILER ?= 0 +USE_QUESTA_PROFILER ?= 0 + + +# Set project Variables +TEST_PLAN_NAME = block_2_TestPlan +REPORTING_DO_FILE = block_2_reports_script + + +# Include makefile that includes targets for UVM_VIP_Library packages +include $(UVMF_HOME)/scripts/Makefile + + + + +# Include all requisite interface package targets for this bench +include $(UVMF_VIP_LIBRARY_HOME)/interface_packages/spi_m_pkg/Makefile +include $(UVMF_VIP_LIBRARY_HOME)/interface_packages/wb_s_pkg/Makefile + +# Include all requisite environment package targets for this bench +include $(UVMF_VIP_LIBRARY_HOME)/environment_packages/block_2_env_pkg/Makefile + + + +# Add to default compile/load/run arguments +VCOM_ARGS += + +# Note: vsim-3009 error can be eliminated by adding -timescale 1ps/1ps to VLOG_ARGS + +VLOG_ARGS += $(UVM_DISABLE_FILE_LINE_CMD) + +VELANALYZE_ARGS += +VELANALYZE_HVL_ARGS += + +BATCH_VOPT_ARGS += +DEBUG_VOPT_ARGS += +EXTRA_VOPT_TOPS += +COMMON_VSIM_ARGS += +COMMON_VSIM_ARGS += + + +BATCH_VSIM_ARGS += #-uvmcontrol=none +DEBUG_VSIM_ARGS += +EXTRA_VSIM_TOPS += + +# pragma uvmf custom additional_args begin +# pragma uvmf custom additional_args end + + +# Project bench package source +block_2_PARAMETERS_PKG ?=\ +$(UVMF_PROJECT_DIR)/tb/parameters/block_2_parameters_pkg.sv + + +block_2_SEQUENCES_PKG ?=\ +$(UVMF_PROJECT_DIR)/tb/sequences/block_2_sequences_pkg.sv + + +block_2_TEST_PKG ?=\ +$(UVMF_PROJECT_DIR)/tb/tests/block_2_tests_pkg.sv + +# pragma uvmf custom dut_files begin +# UVMF_CHANGE_ME : Reference Verilog DUT source. +block_2_VERILOG_DUT ?=\ +$(UVMF_PROJECT_DIR)/rtl/verilog/verilog_dut.v + +# UVMF_CHANGE_ME : Reference VHDL DUT source. +block_2_VHDL_DUT ?=\ +$(UVMF_PROJECT_DIR)/rtl/vhdl/vhdl_dut.vhd +# pragma uvmf custom dut_files end + + +# Project bench package targets +COMP_block_2_PARAMETERS_PKG_TGT_0 = q_comp_block_2_parameters_pkg +COMP_block_2_PARAMETERS_PKG_TGT_1 = v_comp_block_2_parameters_pkg +COMP_block_2_PARAMETERS_PKG_TGT = $(COMP_block_2_PARAMETERS_PKG_TGT_$(USE_VELOCE)) + +comp_block_2_parameters_pkg: $(COMP_block_2_PARAMETERS_PKG_TGT) + +q_comp_block_2_parameters_pkg: + $(HVL_COMP_CMD) +incdir+$(UVMF_PROJECT_DIR)/tb/parameters $(block_2_PARAMETERS_PKG) + +v_comp_block_2_parameters_pkg: q_comp_block_2_parameters_pkg + $(HDL_COMP_CMD) +incdir+$(UVMF_PROJECT_DIR)/tb/parameters $(block_2_PARAMETERS_PKG) + + +comp_block_2_sequence_pkg: + $(HVL_COMP_CMD) +incdir+$(UVMF_PROJECT_DIR)/tb/sequences $(block_2_SEQUENCES_PKG) + +comp_block_2_tests_pkg: + $(HVL_COMP_CMD) +incdir+$(UVMF_PROJECT_DIR)/tb/tests $(block_2_TEST_PKG) + +# pragma uvmf custom dut_compile_make_target begin +# UVMF_CHANGE_ME : Add make target to compile your verilog dut here +comp_block_2_verilog_dut: + echo "Compile your verilog DUT here" + $(HDL_COMP_CMD) $(block_2_VERILOG_DUT) + +# UVMF_CHANGE_ME : Add make target to compile your vhdl dut here +comp_block_2_vhdl_dut: + echo "Compile your vhdl DUT here" + $(HDL_COMP_CMD_VHDL) $(block_2_VHDL_DUT) + +# UVMF_CHANGE_ME : Add make target to compile your dut here +comp_block_2_dut: comp_block_2_vhdl_dut comp_block_2_verilog_dut +# pragma uvmf custom dut_compile_make_target end + + +BUILD_TGT_0 = make_build +BUILD_TGT_1 = vinfo_build +BUILD_TGT = $(BUILD_TGT_$(USE_VINFO)) + + +comp_hvl : comp_hvl_core + + +comp_hvl_core : \ + comp_spi_m_pkg comp_wb_s_pkg \ + comp_block_2_env_pkg \ + comp_block_2_parameters_pkg comp_block_2_sequence_pkg comp_block_2_tests_pkg + +comp_uvmf_core : comp_uvm_pkg comp_uvmf_base_pkg + +make_build: comp_block_2_dut comp_uvmf_core comp_hvl comp_test_bench + +hvl_build: q_comp_spi_m_pkg q_comp_wb_s_pkg comp_block_2_env_pkg comp_block_2_sequence_pkg comp_block_2_tests_pkg hvl_comp_testbench link optimize + + +vinfo_build: comp_block_2_vhdl_dut build_hdl_vinfo build_hvl_vinfo $(VINFO_TGT) + + $(HDL_COMP_CMD) -F hdl.vf + $(VEL_COMP) + +build: $(BUILD_TGT) + +# pragma uvmf custom additional_targets begin +# pragma uvmf custom additional_targets end + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/block_2/sim/bcr_testlist b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/block_2/sim/bcr_testlist new file mode 100644 index 00000000..5c61ad72 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/block_2/sim/bcr_testlist @@ -0,0 +1,19 @@ + + + +# Test list for use by RMDB file +# File syntax is +# TB_INFO { } { } +# TB ## All subsequent tests will run on this bench until a different "TB" line is seen +# TEST <1st_seed> ... +# If not enough seeds are provided then random seeds are used to pad +# If no repeat count is given, default is 1 +# pragma uvmf custom tb_info begin +TB_INFO block_2 { } { } +# pragma uvmf custom tb_info end +TB block_2 +# pragma uvmf custom regression_suite begin +TEST test_top 3 +# pragma uvmf custom regression_suite end + + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/block_2/sim/bcr_testlist.yaml b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/block_2/sim/bcr_testlist.yaml new file mode 100644 index 00000000..1a81a584 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/block_2/sim/bcr_testlist.yaml @@ -0,0 +1,44 @@ + + + +# YAML test list for use by RMDB file +# File syntax is +# uvmf_testlist: +# testbenches: +# - name: +# extra_build_options: +# extra_run_options: +# - name: +# ... +# - name: +# tests: +# - name: +# uvm_testname: (defaults to test_name) +# testbench: (defaults to last tb name seen) +# repeat: (defaults to 1) +# seeds: [,,...,] (defaults to all random) +# extra_test_options: +# - name: +# ... +# - name: +# include: +# - (relative path reference is to the including YAML file) +# - +# ... +# - + +uvmf_testlist: + testbenches: +# pragma uvmf custom tb_info begin + - name: block_2 + extra_build_options: "" + extra_run_options: "" +# pragma uvmf custom tb_info end + tests: + - testbench: block_2 +# pragma uvmf custom regression_suite begin + - name: test_top + repeat: 3 +# pragma uvmf custom regression_suite end + + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/block_2/sim/compile.do b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/block_2/sim/compile.do new file mode 100644 index 00000000..74950ae6 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/block_2/sim/compile.do @@ -0,0 +1,71 @@ + + +################################################################## +## ENVIRONMENT VARIABLES +################################################################## +quietly set ::env(UVMF_VIP_LIBRARY_HOME) ../../../verification_ip +quietly set ::env(UVMF_PROJECT_DIR) .. + +## Using VRM means that the build is occuring several more directories deeper underneath +## the sim directory, need to prepend some more '..' +if {[info exists ::env(VRM_BUILD)]} { + quietly set ::env(UVMF_VIP_LIBRARY_HOME) "../../../../../$::env(UVMF_VIP_LIBRARY_HOME)" + quietly set ::env(UVMF_PROJECT_DIR) "../../../../../$::env(UVMF_PROJECT_DIR)" +} +quietly set ::env(UVMF_VIP_LIBRARY_HOME) [file normalize $::env(UVMF_VIP_LIBRARY_HOME)] +quietly set ::env(UVMF_PROJECT_DIR) [file normalize $::env(UVMF_PROJECT_DIR)] +quietly echo "UVMF_VIP_LIBRARY_HOME = $::env(UVMF_VIP_LIBRARY_HOME)" +quietly echo "UVMF_PROJECT_DIR = $::env(UVMF_PROJECT_DIR)" + + +################################################################### +## HOUSEKEEPING : DELETE FILES THAT WILL BE REGENERATED +################################################################### +file delete -force *~ *.ucdb vsim.dbg *.vstf *.log work *.mem *.transcript.txt certe_dump.xml *.wlf covhtmlreport VRMDATA +file delete -force design.bin qwave.db dpiheader.h visualizer*.ses +file delete -force veloce.med veloce.wave veloce.map tbxbindings.h edsenv velrunopts.ini +file delete -force sv_connect.* + +################################################################### +## COMPILE DUT SOURCE CODE +################################################################### +vlib work +# pragma uvmf custom dut_compile_dofile_target begin +# UVMF_CHANGE_ME : Add commands to compile your dut here, replacing the default examples +vlog -sv -timescale 1ps/1ps -suppress 2223,2286 $env(UVMF_PROJECT_DIR)/rtl/verilog/verilog_dut.v +vcom $env(UVMF_PROJECT_DIR)/rtl/vhdl/vhdl_dut.vhd +# pragma uvmf custom dut_compile_dofile_target end + +################################################################### +## COMPILE UVMF BASE/COMMON SOURCE CODE +################################################################### +vlog -sv -timescale 1ps/1ps -suppress 2223 -suppress 2286 +incdir+$env(UVMF_HOME)/uvmf_base_pkg -F $env(UVMF_HOME)/uvmf_base_pkg/uvmf_base_pkg_filelist_hdl.f +vlog -sv -timescale 1ps/1ps -suppress 2223 -suppress 2286 +incdir+$env(UVMF_HOME)/uvmf_base_pkg -F $env(UVMF_HOME)/uvmf_base_pkg/uvmf_base_pkg_filelist_hvl.f + + +################################################################### +## UVMF INTERFACE COMPILATION +################################################################### +do $env(UVMF_VIP_LIBRARY_HOME)/interface_packages/spi_m_pkg/compile.do +do $env(UVMF_VIP_LIBRARY_HOME)/interface_packages/wb_s_pkg/compile.do + +################################################################### +## UVMF ENVIRONMENT COMPILATION +################################################################### +do $env(UVMF_VIP_LIBRARY_HOME)/environment_packages/block_2_env_pkg/compile.do + +################################################################### +## UVMF BENCHES COMPILATION +################################################################### +vlog -sv -timescale 1ps/1ps -suppress 2223 -suppress 2286 +incdir+$env(UVMF_PROJECT_DIR)/tb/parameters $env(UVMF_PROJECT_DIR)/tb/parameters/block_2_parameters_pkg.sv +vlog -sv -timescale 1ps/1ps -suppress 2223 -suppress 2286 +incdir+$env(UVMF_PROJECT_DIR)/tb/sequences $env(UVMF_PROJECT_DIR)/tb/sequences/block_2_sequences_pkg.sv +vlog -sv -timescale 1ps/1ps -suppress 2223 -suppress 2286 +incdir+$env(UVMF_PROJECT_DIR)/tb/tests $env(UVMF_PROJECT_DIR)/tb/tests/block_2_tests_pkg.sv + +vlog -sv -timescale 1ps/1ps -suppress 2223 -suppress 2286 +incdir+$env(UVMF_PROJECT_DIR)/tb/testbench -F $env(UVMF_PROJECT_DIR)/tb/testbench/top_filelist_hdl.f +vlog -sv -timescale 1ps/1ps -suppress 2223 -suppress 2286 +incdir+$env(UVMF_PROJECT_DIR)/tb/testbench -F $env(UVMF_PROJECT_DIR)/tb/testbench/top_filelist_hvl.f + +################################################################### +## OPTIMIZATION +################################################################### +vopt hvl_top hdl_top -o optimized_batch_top_tb +vopt +acc hvl_top hdl_top -o optimized_debug_top_tb diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/block_2/sim/hdl.compile b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/block_2/sim/hdl.compile new file mode 100644 index 00000000..8e7bd41a --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/block_2/sim/hdl.compile @@ -0,0 +1,5 @@ +needs: +# pragma uvmf custom dut_compile_info begin + - ../rtl/dut.compile +# pragma uvmf custom dut_compile_info end + - ../tb/testbench/hdl_top.compile diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/block_2/sim/hdl.vinfo b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/block_2/sim/hdl.vinfo new file mode 100644 index 00000000..da27ec77 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/block_2/sim/hdl.vinfo @@ -0,0 +1 @@ +@use $UVMF_PROJECT_DIR/tb/testbench/hdl_top.vinfo diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/block_2/sim/hvl.compile b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/block_2/sim/hvl.compile new file mode 100644 index 00000000..ce952549 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/block_2/sim/hvl.compile @@ -0,0 +1,2 @@ +needs: + - ../tb/testbench/hvl_top.compile diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/block_2/sim/hvl.vinfo b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/block_2/sim/hvl.vinfo new file mode 100644 index 00000000..d22eff33 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/block_2/sim/hvl.vinfo @@ -0,0 +1 @@ +@use $UVMF_PROJECT_DIR/tb/testbench/hvl_top.vinfo diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/block_2/sim/run.do b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/block_2/sim/run.do new file mode 100644 index 00000000..101ddc48 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/block_2/sim/run.do @@ -0,0 +1,21 @@ + + +quietly set svLibs "" +quietly set extra_vsim_args "" + +################################################################### +## Check for additional vsim arguments passed using env var $UVMF_EXTRA_VSIM_ARGS +################################################################### +if {[info exists ::env(UVMF_EXTRA_VSIM_ARGS)]} { + echo "Adding more args to vsim command" + quietly set extra_vsim_args $::env(UVMF_EXTRA_VSIM_ARGS) +} + +################################################################## +## Launch Questa : generate vsim command line and execute +################################################################## +# pragma uvmf custom dut_run_dofile_target begin +# UVMF_CHANGE_ME : Change the UVM_TESTNAME plusarg to run a different test +quietly set cmd [format "vsim -i -sv_seed random +UVM_TESTNAME=test_top +UVM_VERBOSITY=UVM_HIGH -permit_unmatched_virtual_intf +notimingchecks -suppress 8887 %s %s -uvmcontrol=all -msgmode both -classdebug -assertdebug +uvm_set_config_int=*,enable_transaction_viewing,1 -do { set NoQuitOnFinish 1; onbreak {resume}; run 0; do wave.do; set PrefSource(OpenOnBreak) 0; radix hex showbase; } optimized_debug_top_tb" $svLibs $extra_vsim_args] +# pragma uvmf custom dut_run_dofile_target end +eval $cmd diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/block_2/sim/tbx.config b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/block_2/sim/tbx.config new file mode 100644 index 00000000..eec58168 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/block_2/sim/tbx.config @@ -0,0 +1,10 @@ + + + + + +comp -questa +velsyn -D1S +rtlc -allow_4ST + + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/block_2/sim/testlist b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/block_2/sim/testlist new file mode 100644 index 00000000..f92fb15b --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/block_2/sim/testlist @@ -0,0 +1,20 @@ + + + + +# Test list for use by RMDB file +# File syntax is +# TB_INFO { } { } +# TB ## All subsequent tests will run on this bench until a different "TB" line is seen +# TEST <1st_seed> ... +# If not enough seeds are provided then random seeds are used to pad +# If no repeat count is given, default is 1 +# pragma uvmf custom tb_info begin +TB_INFO block_2 { UVMF_VIP_LIBRARY_HOME=../../../../../../../../verification_ip UVMF_PROJECT_DIR=../../../../../../../block_2 } { } +# pragma uvmf custom tb_info end +TB block_2 +# pragma uvmf custom regression_suite begin +TEST test_top 3 +# pragma uvmf custom regression_suite end + + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/block_2/sim/testlist.yaml b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/block_2/sim/testlist.yaml new file mode 100644 index 00000000..f6cabad6 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/block_2/sim/testlist.yaml @@ -0,0 +1,44 @@ + + + +# YAML test list for use by RMDB file +# File syntax is +# uvmf_testlist: +# testbenches: +# - name: +# extra_build_options: +# extra_run_options: +# - name: +# ... +# - name: +# tests: +# - name: +# uvm_testname: (defaults to test_name) +# testbench: (defaults to last tb name seen) +# repeat: (defaults to 1) +# seeds: [,,...,] (defaults to all random) +# extra_test_options: +# - name: +# ... +# - name: +# include: +# - (relative path reference is to the including YAML file) +# - +# ... +# - + +uvmf_testlist: + testbenches: +# pragma uvmf custom tb_info begin + - name: block_2 + extra_build_options: "UVMF_VIP_LIBRARY_HOME=../../../../../../../../verification_ip UVMF_PROJECT_DIR=../../../../../../../block_2" + extra_run_options: "" +# pragma uvmf custom tb_info end + tests: + - testbench: block_2 +# pragma uvmf custom regression_suite begin + - name: test_top + repeat: 3 +# pragma uvmf custom regression_suite end + + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/block_2/sim/top.compile b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/block_2/sim/top.compile new file mode 100644 index 00000000..efd51c07 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/block_2/sim/top.compile @@ -0,0 +1,3 @@ +needs: + - hvl.compile + - hdl.compile diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/block_2/sim/veloce.config b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/block_2/sim/veloce.config new file mode 100644 index 00000000..d0975155 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/block_2/sim/veloce.config @@ -0,0 +1,26 @@ + + + + + +# pragma uvmf custom additional begin +comp -num_boards 1 +comp -hvl questa +# Please choose the correct emulator type code for +# comp -platform command or else velcomp will fail +# Available types are: +# - Veloce2 Quattro: D2 +# - Veloce2 Maximus: D2M +# - Veloce Strato TiL, Ti, and Mi: Strato +# - Veloce Strato M and Strato T: StratoM +# - comp -platform +comp -platform Strato + +rtlc -enable_tbx_pragma_checks +rtlc -allow_4ST +rtlc -allow_MDR +rtlc -compile_display +rtlc -xwave_siglist xwaves.sigs +# pragma uvmf custom additional end + + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/block_2/sim/viswave.do b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/block_2/sim/viswave.do new file mode 100644 index 00000000..e6989769 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/block_2/sim/viswave.do @@ -0,0 +1,22 @@ + + +onerror resume +wave tags F0 +wave update off + +wave spacer -backgroundcolor Salmon { spi_master } +wave add uvm_test_top.environment.spi_master.spi_master_monitor.txn_stream -radix string -tag F0 +wave group spi_master_bus +wave add -group spi_master_bus hdl_top.spi_master_bus.* -radix hexadecimal -tag F0 +wave group spi_master_bus -collapse +wave insertion [expr [wave index insertpoint] +1] +wave spacer -backgroundcolor Salmon { wb_slave } +wave add uvm_test_top.environment.wb_slave.wb_slave_monitor.txn_stream -radix string -tag F0 +wave group wb_slave_bus +wave add -group wb_slave_bus hdl_top.wb_slave_bus.* -radix hexadecimal -tag F0 +wave group wb_slave_bus -collapse +wave insertion [expr [wave index insertpoint] +1] + +wave update on +WaveSetStreamView + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/block_2/sim/wave.do b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/block_2/sim/wave.do new file mode 100644 index 00000000..128637c8 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/block_2/sim/wave.do @@ -0,0 +1,30 @@ + + +onerror {resume} +quietly WaveActivateNextPane {} 0 + +add wave -noupdate -divider spi_master +add wave -noupdate /uvm_root/uvm_test_top/environment/spi_master/spi_master_monitor/txn_stream +add wave -noupdate -group spi_master_bus /hdl_top/spi_master_bus/* +add wave -noupdate -divider wb_slave +add wave -noupdate /uvm_root/uvm_test_top/environment/wb_slave/wb_slave_monitor/txn_stream +add wave -noupdate -group wb_slave_bus /hdl_top/wb_slave_bus/* + +TreeUpdate [SetDefaultTree] +quietly wave cursor active 0 +configure wave -namecolwidth 472 +configure wave -valuecolwidth 100 +configure wave -justifyvalue left +configure wave -signalnamewidth 0 +configure wave -snapdistance 10 +configure wave -datasetprefix 0 +configure wave -rowmargin 4 +configure wave -childrowmargin 2 +configure wave -gridoffset 0 +configure wave -gridperiod 1 +configure wave -griddelta 40 +configure wave -timeline 0 +configure wave -timelineunits ns +update +WaveRestoreZoom {27 ns} {168 ns} + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/block_2/sim/xwaves.sigs b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/block_2/sim/xwaves.sigs new file mode 100644 index 00000000..d75f0a57 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/block_2/sim/xwaves.sigs @@ -0,0 +1,17 @@ + + + + + +# pragma uvmf custom additional begin + +Group All + +#Top level signals +hdl_top.* +#Add additional levels or individual signals as needed +hdl_top.*.* + +# pragma uvmf custom additional end + + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/block_2/tb/parameters/block_2_parameters_pkg.compile b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/block_2/tb/parameters/block_2_parameters_pkg.compile new file mode 100644 index 00000000..1d5f4608 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/block_2/tb/parameters/block_2_parameters_pkg.compile @@ -0,0 +1,4 @@ +needs: + - $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg_hdl.compile +src: + - block_2_parameters_pkg.sv diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/block_2/tb/parameters/block_2_parameters_pkg.sv b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/block_2/tb/parameters/block_2_parameters_pkg.sv new file mode 100644 index 00000000..67f61b95 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/block_2/tb/parameters/block_2_parameters_pkg.sv @@ -0,0 +1,38 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This package contains test level parameters +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// + + +package block_2_parameters_pkg; + + import uvmf_base_pkg_hdl::*; + + // pragma uvmf custom package_imports_additional begin + // pragma uvmf custom package_imports_additional end + + + // These parameters are used to uniquely identify each interface. The monitor_bfm and + // driver_bfm are placed into and retrieved from the uvm_config_db using these string + // names as the field_name. The parameter is also used to enable transaction viewing + // from the command line for selected interfaces using the UVM command line processing. + parameter string spi_master_BFM = "spi_master_BFM"; /* [0] */ + parameter string wb_slave_BFM = "wb_slave_BFM"; /* [1] */ + + // pragma uvmf custom package_item_additional begin + // pragma uvmf custom package_item_additional end + +endpackage + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/block_2/tb/parameters/block_2_parameters_pkg.vinfo b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/block_2/tb/parameters/block_2_parameters_pkg.vinfo new file mode 100644 index 00000000..7d0528cc --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/block_2/tb/parameters/block_2_parameters_pkg.vinfo @@ -0,0 +1,2 @@ +@use $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg_hdl.vinfo +block_2_parameters_pkg.sv diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/block_2/tb/sequences/block_2_sequences_pkg.compile b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/block_2/tb/sequences/block_2_sequences_pkg.compile new file mode 100644 index 00000000..60acb579 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/block_2/tb/sequences/block_2_sequences_pkg.compile @@ -0,0 +1,8 @@ +needs: + - $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg.compile + - ../../../../verification_ip/interface_packages/spi_m_pkg/spi_m.compile + - ../../../../verification_ip/interface_packages/wb_s_pkg/wb_s.compile + - ../../../../verification_ip/environment_packages/block_2_env_pkg/block_2_env_pkg.compile + - ../parameters/block_2_parameters_pkg.compile +src: + - block_2_sequences_pkg.sv diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/block_2/tb/sequences/block_2_sequences_pkg.sv b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/block_2/tb/sequences/block_2_sequences_pkg.sv new file mode 100644 index 00000000..3948b622 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/block_2/tb/sequences/block_2_sequences_pkg.sv @@ -0,0 +1,51 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This package includes all high level sequence classes used +// in the environment. These include utility sequences and top +// level sequences. +// +// CONTAINS: +// - +// - +// +//---------------------------------------------------------------------- +// +//---------------------------------------------------------------------- +// + +package block_2_sequences_pkg; + import uvm_pkg::*; + import uvmf_base_pkg::*; + import spi_m_pkg::*; + import spi_m_pkg_hdl::*; + import wb_s_pkg::*; + import wb_s_pkg_hdl::*; + import block_2_parameters_pkg::*; + import block_2_env_pkg::*; + `include "uvm_macros.svh" + + // pragma uvmf custom package_imports_additional begin + // pragma uvmf custom package_imports_additional end + + `include "src/block_2_bench_sequence_base.svh" + `include "src/register_test_sequence.svh" + `include "src/example_derived_test_sequence.svh" + + // pragma uvmf custom package_item_additional begin + // UVMF_CHANGE_ME : When adding new sequences to the src directory + // be sure to add the sequence file here so that it will be + // compiled as part of the sequence package. Be sure to place + // the new sequence after any base sequences of the new sequence. + // pragma uvmf custom package_item_additional end + +endpackage + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/block_2/tb/sequences/block_2_sequences_pkg.vinfo b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/block_2/tb/sequences/block_2_sequences_pkg.vinfo new file mode 100644 index 00000000..9d82a0e6 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/block_2/tb/sequences/block_2_sequences_pkg.vinfo @@ -0,0 +1,7 @@ +@use $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg.vinfo +@use $UVMF_VIP_LIBRARY_HOME/interface_packages/spi_m_pkg/spi_m_pkg.vinfo +@use $UVMF_VIP_LIBRARY_HOME/interface_packages/wb_s_pkg/wb_s_pkg.vinfo +@use $UVMF_VIP_LIBRARY_HOME/environment_packages/block_2_env_pkg/block_2_env_pkg.vinfo +@use $UVMF_PROJECT_DIR/tb/parameters/block_2_parameters_pkg.vinfo ++incdir+@vinfodir +block_2_sequences_pkg.sv diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/block_2/tb/sequences/src/block_2_bench_sequence_base.svh b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/block_2/tb/sequences/src/block_2_bench_sequence_base.svh new file mode 100644 index 00000000..33b1b8c1 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/block_2/tb/sequences/src/block_2_bench_sequence_base.svh @@ -0,0 +1,121 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// Description: This file contains the top level and utility sequences +// used by test_top. It can be extended to create derivative top +// level sequences. +// +//---------------------------------------------------------------------- +// +//---------------------------------------------------------------------- +// + + +typedef block_2_env_configuration block_2_env_configuration_t; + +class block_2_bench_sequence_base extends uvmf_sequence_base #(uvm_sequence_item); + + `uvm_object_utils( block_2_bench_sequence_base ); + + // pragma uvmf custom sequences begin + +typedef block_2_env_sequence_base #( + .CONFIG_T(block_2_env_configuration_t) + ) + block_2_env_sequence_base_t; +rand block_2_env_sequence_base_t block_2_env_seq; + + + + // UVMF_CHANGE_ME : Instantiate, construct, and start sequences as needed to create stimulus scenarios. + // Instantiate sequences here + typedef spi_m_random_sequence spi_master_random_seq_t; + spi_master_random_seq_t spi_master_random_seq; + // pragma uvmf custom sequences end + + // Sequencer handles for each active interface in the environment + typedef spi_m_transaction spi_master_transaction_t; + uvm_sequencer #(spi_master_transaction_t) spi_master_sequencer; + + + // Top level environment configuration handle + block_2_env_configuration_t top_configuration; + + // Configuration handles to access interface BFM's + spi_m_configuration spi_master_config; + wb_s_configuration wb_slave_config; + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + // **************************************************************************** + function new( string name = "" ); + super.new( name ); + // Retrieve the configuration handles from the uvm_config_db + + // Retrieve top level configuration handle + if ( !uvm_config_db#(block_2_env_configuration_t)::get(null,UVMF_CONFIGURATIONS, "TOP_ENV_CONFIG",top_configuration) ) begin + `uvm_info("CFG", "*** FATAL *** uvm_config_db::get can not find TOP_ENV_CONFIG. Are you using an older UVMF release than what was used to generate this bench?",UVM_NONE); + `uvm_fatal("CFG", "uvm_config_db#(block_2_env_configuration_t)::get cannot find resource TOP_ENV_CONFIG"); + end + + // Retrieve config handles for all agents + if( !uvm_config_db #( spi_m_configuration )::get( null , UVMF_CONFIGURATIONS , spi_master_BFM , spi_master_config ) ) + `uvm_fatal("CFG" , "uvm_config_db #( spi_m_configuration )::get cannot find resource spi_master_BFM" ) + if( !uvm_config_db #( wb_s_configuration )::get( null , UVMF_CONFIGURATIONS , wb_slave_BFM , wb_slave_config ) ) + `uvm_fatal("CFG" , "uvm_config_db #( wb_s_configuration )::get cannot find resource wb_slave_BFM" ) + + // Assign the sequencer handles from the handles within agent configurations + spi_master_sequencer = spi_master_config.get_sequencer(); + + + + // pragma uvmf custom new begin + // pragma uvmf custom new end + + endfunction + + // **************************************************************************** + virtual task body(); + // pragma uvmf custom body begin + + // Construct sequences here + + block_2_env_seq = block_2_env_sequence_base_t::type_id::create("block_2_env_seq"); + + spi_master_random_seq = spi_master_random_seq_t::type_id::create("spi_master_random_seq"); + fork + spi_master_config.wait_for_reset(); + wb_slave_config.wait_for_reset(); + join + // Start RESPONDER sequences here + fork + join_none + // Start INITIATOR sequences here + fork + repeat (25) spi_master_random_seq.start(spi_master_sequencer); + join + +block_2_env_seq.start(top_configuration.vsqr); + + // UVMF_CHANGE_ME : Extend the simulation XXX number of clocks after + // the last sequence to allow for the last sequence item to flow + // through the design. + fork + spi_master_config.wait_for_num_clocks(400); + wb_slave_config.wait_for_num_clocks(400); + join + + // pragma uvmf custom body end + endtask + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/block_2/tb/sequences/src/example_derived_test_sequence.svh b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/block_2/tb/sequences/src/example_derived_test_sequence.svh new file mode 100644 index 00000000..8bd3e555 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/block_2/tb/sequences/src/example_derived_test_sequence.svh @@ -0,0 +1,30 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +// +//---------------------------------------------------------------------- +// +// DESCRIPTION: This file contains the top level sequence used in example_derived_test. +// It is an example of a sequence that is extended from %(benchName)_bench_sequence_base +// and can override %(benchName)_bench_sequence_base. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// + +class example_derived_test_sequence extends block_2_bench_sequence_base; + + `uvm_object_utils( example_derived_test_sequence ); + + function new(string name = "" ); + super.new(name); + endfunction + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/block_2/tb/sequences/src/register_test_sequence.svh b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/block_2/tb/sequences/src/register_test_sequence.svh new file mode 100644 index 00000000..6948b861 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/block_2/tb/sequences/src/register_test_sequence.svh @@ -0,0 +1,57 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This file contains the top level sequence used in register_test. +// It uses the UVM built in register test. Specific UVM built-in tests can be +// selected in the body task. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// + +class register_test_sequence extends block_2_bench_sequence_base; + + `uvm_object_utils( register_test_sequence ); + + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + function new(string name = "" ); + super.new(name); + endfunction + + // **************************************************************************** + virtual task body(); + + // Reset the DUT + fork + // pragma uvmf custom register_test_reset begin + // UVMF_CHANGE_ME + // Select the desired wait_for_reset or provide custom mechanism. + // fork-join for this code block may be unnecessary based on your situation. + spi_master_config.wait_for_reset(); + wb_slave_config.wait_for_reset(); + // pragma uvmf custom register_test_reset end + join + + // pragma uvmf custom register_test_setup begin + // UVMF_CHANGE_ME perform potentially necessary operations before running the sequence. + // pragma uvmf custom register_test_setup end + + // pragma uvmf custom register_test_operation begin + // UVMF_CHANGE_ME Perform your custom register test + // pragma uvmf custom register_test_operation end + + endtask + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/block_2/tb/testbench/hdl_top.compile b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/block_2/tb/testbench/hdl_top.compile new file mode 100644 index 00000000..96a0acc9 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/block_2/tb/testbench/hdl_top.compile @@ -0,0 +1,10 @@ +incdir: + - ${uvm_path}/src + - . +needs: + - $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg_hdl.compile + - ../parameters/block_2_parameters_pkg.compile + - ../../../../verification_ip/interface_packages/spi_m_pkg/spi_m_hdl.compile + - ../../../../verification_ip/interface_packages/wb_s_pkg/wb_s_hdl.compile +src: + - hdl_top.sv diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/block_2/tb/testbench/hdl_top.sv b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/block_2/tb/testbench/hdl_top.sv new file mode 100644 index 00000000..1d30b34f --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/block_2/tb/testbench/hdl_top.sv @@ -0,0 +1,99 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// Description: This top level module instantiates all synthesizable +// static content. This and tb_top.sv are the two top level modules +// of the simulation. +// +// This module instantiates the following: +// DUT: The Design Under Test +// Interfaces: Signal bundles that contain signals connected to DUT +// Driver BFM's: BFM's that actively drive interface signals +// Monitor BFM's: BFM's that passively monitor interface signals +// +//---------------------------------------------------------------------- + +//---------------------------------------------------------------------- +// + +module hdl_top; + +import block_2_parameters_pkg::*; +import uvmf_base_pkg_hdl::*; + + // pragma attribute hdl_top partition_module_xrtl +// pragma uvmf custom clock_generator begin + bit clk; + // Instantiate a clk driver + // tbx clkgen + initial begin + clk = 0; + #9ns; + forever begin + clk = ~clk; + #5ns; + end + end +// pragma uvmf custom clock_generator end + +// pragma uvmf custom reset_generator begin + bit rst; + // Instantiate a rst driver + // tbx clkgen + initial begin + rst = 1; + #200ns; + rst = 0; + end +// pragma uvmf custom reset_generator end + + // pragma uvmf custom module_item_additional begin + // pragma uvmf custom module_item_additional end + + // Instantiate the signal bundle, monitor bfm and driver bfm for each interface. + // The signal bundle, _if, contains signals to be connected to the DUT. + // The monitor, monitor_bfm, observes the bus, _if, and captures transactions. + // The driver, driver_bfm, drives transactions onto the bus, _if. + spi_m_if spi_master_bus( + // pragma uvmf custom spi_master_bus_connections begin + .sck(clk), .rst(rst) + // pragma uvmf custom spi_master_bus_connections end + ); + wb_s_if wb_slave_bus( + // pragma uvmf custom wb_slave_bus_connections begin + .clock(clk), .reset(rst) + // pragma uvmf custom wb_slave_bus_connections end + ); + spi_m_monitor_bfm spi_master_mon_bfm(spi_master_bus.monitor_port); + wb_s_monitor_bfm wb_slave_mon_bfm(wb_slave_bus.monitor_port); + spi_m_driver_bfm spi_master_drv_bfm(spi_master_bus.initiator_port); + + // pragma uvmf custom dut_instantiation begin + // UVMF_CHANGE_ME : Add DUT and connect to signals in _bus interfaces listed above + // Instantiate your DUT here + // These DUT's instantiated to show verilog and vhdl instantiation + verilog_dut dut_verilog( .clk(clk), .rst(rst), .in_signal(vhdl_to_verilog_signal), .out_signal(verilog_to_vhdl_signal)); + vhdl_dut dut_vhdl ( .clk(clk), .rst(rst), .in_signal(verilog_to_vhdl_signal), .out_signal(vhdl_to_verilog_signal)); + // pragma uvmf custom dut_instantiation end + + initial begin // tbx vif_binding_block + import uvm_pkg::uvm_config_db; + // The monitor_bfm and driver_bfm for each interface is placed into the uvm_config_db. + // They are placed into the uvm_config_db using the string names defined in the parameters package. + // The string names are passed to the agent configurations by test_top through the top level configuration. + // They are retrieved by the agents configuration class for use by the agent. + uvm_config_db #( virtual spi_m_monitor_bfm )::set( null , UVMF_VIRTUAL_INTERFACES , spi_master_BFM , spi_master_mon_bfm ); + uvm_config_db #( virtual wb_s_monitor_bfm )::set( null , UVMF_VIRTUAL_INTERFACES , wb_slave_BFM , wb_slave_mon_bfm ); + uvm_config_db #( virtual spi_m_driver_bfm )::set( null , UVMF_VIRTUAL_INTERFACES , spi_master_BFM , spi_master_drv_bfm ); + end + +endmodule + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/block_2/tb/testbench/hdl_top.vinfo b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/block_2/tb/testbench/hdl_top.vinfo new file mode 100644 index 00000000..dce0a508 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/block_2/tb/testbench/hdl_top.vinfo @@ -0,0 +1,6 @@ +@use $UVMF_PROJECT_DIR/rtl/verilog/verilog_dut.vinfo +@use $UVMF_PROJECT_DIR/tb/parameters/block_2_parameters_pkg.vinfo +@use $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg_hdl.vinfo +@use $UVMF_VIP_LIBRARY_HOME/interface_packages/spi_m_pkg/spi_m_bfm.vinfo +@use $UVMF_VIP_LIBRARY_HOME/interface_packages/wb_s_pkg/wb_s_bfm.vinfo +hdl_top.sv diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/block_2/tb/testbench/hvl_top.compile b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/block_2/tb/testbench/hvl_top.compile new file mode 100644 index 00000000..381340b2 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/block_2/tb/testbench/hvl_top.compile @@ -0,0 +1,7 @@ +incdir: + - ${uvm_path}/src + - . +needs: + - ../tests/block_2_tests_pkg.compile +src: + - hvl_top.sv diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/block_2/tb/testbench/hvl_top.sv b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/block_2/tb/testbench/hvl_top.sv new file mode 100644 index 00000000..1cd56838 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/block_2/tb/testbench/hvl_top.sv @@ -0,0 +1,33 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +// +//---------------------------------------------------------------------- +// +// DESCRIPTION: This module loads the test package and starts the UVM phases. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// + +module hvl_top; + +import uvm_pkg::*; +import block_2_tests_pkg::*; + + // pragma uvmf custom module_item_additional begin + // pragma uvmf custom module_item_additional end + + initial begin + $timeformat(-9,3,"ns",5); + run_test(); + end + +endmodule + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/block_2/tb/testbench/hvl_top.vinfo b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/block_2/tb/testbench/hvl_top.vinfo new file mode 100644 index 00000000..fd98547a --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/block_2/tb/testbench/hvl_top.vinfo @@ -0,0 +1,2 @@ +@use $UVMF_PROJECT_DIR/tb/tests/block_2_tests_pkg.vinfo +hvl_top.sv diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/block_2/tb/testbench/top_filelist_hdl.f b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/block_2/tb/testbench/top_filelist_hdl.f new file mode 100644 index 00000000..1e9dab65 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/block_2/tb/testbench/top_filelist_hdl.f @@ -0,0 +1,3 @@ +$UVMF_PROJECT_DIR/tb/testbench/hdl_top.sv +// pragma uvmf custom additional begin +// pragma uvmf custom additional end diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/block_2/tb/testbench/top_filelist_hvl.f b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/block_2/tb/testbench/top_filelist_hvl.f new file mode 100644 index 00000000..42383ab2 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/block_2/tb/testbench/top_filelist_hvl.f @@ -0,0 +1,3 @@ +$UVMF_PROJECT_DIR/tb/testbench/hvl_top.sv +// pragma uvmf custom additional begin +// pragma uvmf custom additional end diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/block_2/tb/tests/block_2_tests_pkg.compile b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/block_2/tb/tests/block_2_tests_pkg.compile new file mode 100644 index 00000000..fcd92c08 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/block_2/tb/tests/block_2_tests_pkg.compile @@ -0,0 +1,9 @@ +needs: + - $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg.compile + - ../../../../verification_ip/interface_packages/spi_m_pkg/spi_m.compile + - ../../../../verification_ip/interface_packages/wb_s_pkg/wb_s.compile + - ../../../../verification_ip/environment_packages/block_2_env_pkg/block_2_env_pkg.compile + - ../parameters/block_2_parameters_pkg.compile + - ../sequences/block_2_sequences_pkg.compile +src: + - block_2_tests_pkg.sv diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/block_2/tb/tests/block_2_tests_pkg.sv b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/block_2/tb/tests/block_2_tests_pkg.sv new file mode 100644 index 00000000..cc8e3ddb --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/block_2/tb/tests/block_2_tests_pkg.sv @@ -0,0 +1,54 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This package contains all tests currently written for +// the simulation project. Once compiled, any test can be selected +// from the vsim command line using +UVM_TESTNAME=yourTestNameHere +// +// CONTAINS: +// - +// - +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// + +package block_2_tests_pkg; + + import uvm_pkg::*; + import uvmf_base_pkg::*; + import block_2_parameters_pkg::*; + import block_2_env_pkg::*; + import block_2_sequences_pkg::*; + import spi_m_pkg::*; + import spi_m_pkg_hdl::*; + import wb_s_pkg::*; + import wb_s_pkg_hdl::*; + + + `include "uvm_macros.svh" + + // pragma uvmf custom package_imports_additional begin + // pragma uvmf custom package_imports_additional end + + `include "src/test_top.svh" + `include "src/register_test.svh" + `include "src/example_derived_test.svh" + + // pragma uvmf custom package_item_additional begin + // UVMF_CHANGE_ME : When adding new tests to the src directory + // be sure to add the test file here so that it will be + // compiled as part of the test package. Be sure to place + // the new test after any base tests of the new test. + // pragma uvmf custom package_item_additional end + +endpackage + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/block_2/tb/tests/block_2_tests_pkg.vinfo b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/block_2/tb/tests/block_2_tests_pkg.vinfo new file mode 100644 index 00000000..9992ff94 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/block_2/tb/tests/block_2_tests_pkg.vinfo @@ -0,0 +1,8 @@ +@use $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg.vinfo +@use $UVMF_VIP_LIBRARY_HOME/interface_packages/spi_m_pkg/spi_m_pkg.vinfo +@use $UVMF_VIP_LIBRARY_HOME/interface_packages/wb_s_pkg/wb_s_pkg.vinfo +@use $UVMF_VIP_LIBRARY_HOME/environment_packages/block_2_env_pkg/block_2_env_pkg.vinfo +@use $UVMF_PROJECT_DIR/tb/parameters/block_2_parameters_pkg.vinfo +@use $UVMF_PROJECT_DIR/tb/sequences/block_2_sequences_pkg.vinfo ++incdir+@vinfodir +block_2_tests_pkg.sv diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/block_2/tb/tests/src/example_derived_test.svh b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/block_2/tb/tests/src/example_derived_test.svh new file mode 100644 index 00000000..24753c75 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/block_2/tb/tests/src/example_derived_test.svh @@ -0,0 +1,43 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This test extends test_top and makes +// changes to test_top using the UVM factory type_override: +// +// Test scenario: +// This is a template test that can be used to create future tests. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// + +class example_derived_test extends test_top; + + `uvm_component_utils( example_derived_test ); + + function new( string name = "", uvm_component parent = null ); + super.new( name, parent ); + endfunction + + virtual function void build_phase(uvm_phase phase); + // The factory override below is an example of how to replace the block_2_bench_sequence_base + // sequence with the example_derived_test_sequence. + block_2_bench_sequence_base::type_id::set_type_override(example_derived_test_sequence::get_type()); + // Execute the build_phase of test_top AFTER all factory overrides have been created. + super.build_phase(phase); + // pragma uvmf custom configuration_settings_post_randomize begin + // UVMF_CHANGE_ME Test specific configuration values can be set here. + // The configuration structure has already been randomized. + // pragma uvmf custom configuration_settings_post_randomize end + endfunction + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/block_2/tb/tests/src/register_test.svh b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/block_2/tb/tests/src/register_test.svh new file mode 100644 index 00000000..2340b0f7 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/block_2/tb/tests/src/register_test.svh @@ -0,0 +1,40 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This test extends test_top and makes +// changes to test_top using the UVM factory type_override: +// +// Test scenario: +// This is a template test that can be used to create future tests. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// + +class register_test extends test_top; + + `uvm_component_utils( register_test ); + + function new( string name = "", uvm_component parent = null ); + super.new( name, parent ); + endfunction + + virtual function void build_phase(uvm_phase phase); + // The factory override below replaces the block_2_bench_sequence_base + // sequence with the register_test_sequence. + block_2_bench_sequence_base::type_id::set_type_override(register_test_sequence::get_type()); + // Execute the build_phase of test_top AFTER all factory overrides have been created. + super.build_phase(phase); + endfunction + + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/block_2/tb/tests/src/test_top.svh b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/block_2/tb/tests/src/test_top.svh new file mode 100644 index 00000000..d177a8dd --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/block_2/tb/tests/src/test_top.svh @@ -0,0 +1,78 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// Description: This top level UVM test is the base class for all +// future tests created for this project. +// +// This test class contains: +// Configuration: The top level configuration for the project. +// Environment: The top level environment for the project. +// Top_level_sequence: The top level sequence for the project. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// + +typedef block_2_env_configuration block_2_env_configuration_t; +typedef block_2_environment block_2_environment_t; + +class test_top extends uvmf_test_base #(.CONFIG_T(block_2_env_configuration_t), + .ENV_T(block_2_environment_t), + .TOP_LEVEL_SEQ_T(block_2_bench_sequence_base)); + + `uvm_component_utils( test_top ); + + + + string interface_names[] = { + spi_master_BFM /* spi_master [0] */ , + wb_slave_BFM /* wb_slave [1] */ +}; + +uvmf_active_passive_t interface_activities[] = { + ACTIVE /* spi_master [0] */ , + PASSIVE /* wb_slave [1] */ }; + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + // **************************************************************************** + // FUNCTION: new() + // This is the standard systemVerilog constructor. All components are + // constructed in the build_phase to allow factory overriding. + // + function new( string name = "", uvm_component parent = null ); + super.new( name ,parent ); + endfunction + + + + // **************************************************************************** + // FUNCTION: build_phase() + // The construction of the configuration and environment classes is done in + // the build_phase of uvmf_test_base. Once the configuraton and environment + // classes are built then the initialize call is made to perform the + // following: + // Monitor and driver BFM virtual interface handle passing into agents + // Set the active/passive state for each agent + // Once this build_phase completes, the build_phase of the environment is + // executed which builds the agents. + // + virtual function void build_phase(uvm_phase phase); +// pragma uvmf custom build_phase_pre_super begin +// pragma uvmf custom build_phase_pre_super end + super.build_phase(phase); + // pragma uvmf custom configuration_settings_post_randomize begin + // pragma uvmf custom configuration_settings_post_randomize end + configuration.initialize(NA, "uvm_test_top.environment", interface_names, null, interface_activities); + endfunction + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/block_2/yaml/block_2_bench.yaml b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/block_2/yaml/block_2_bench.yaml new file mode 100644 index 00000000..abfe0941 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/block_2/yaml/block_2_bench.yaml @@ -0,0 +1,17 @@ +uvmf: + benches: + block_2: + active_passive: + - bfm_name: spi_master + value: ACTIVE + - bfm_name: wb_slave + value: PASSIVE + active_passive_default: ACTIVE + clock_half_period: 5ns + clock_phase_offset: 9ns + existing_library_component: 'True' + interface_params: [] + reset_assertion_level: 'True' + reset_duration: 200ns + top_env: block_2 + use_dpi_link: 'False' diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/.project b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/.project new file mode 100644 index 00000000..99203eb8 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/.project @@ -0,0 +1,37 @@ + + + subsys + + + + + + org.python.pydev.PyDevBuilder + + + + + net.sf.sveditor.core.SVProjectBuilder + + + + + + net.sf.sveditor.core.SVNature + org.python.pydev.pythonNature + + + + verification_ip + 2 + UVMF_VIP_LIBRARY_HOME + + + + + UVMF_VIP_LIBRARY_HOME + $%7BPARENT-2-PROJECT_LOC%7D/verification_ip + + + + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/.svproject b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/.svproject new file mode 100644 index 00000000..62740391 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/.svproject @@ -0,0 +1,16 @@ + + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/docs/interfaces.csv b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/docs/interfaces.csv new file mode 100644 index 00000000..8415ca38 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/docs/interfaces.csv @@ -0,0 +1,18 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// + +, +Interface Description, Interface Type, Interface Transaction, Interface Name, +b1_apb_master, apb_m_driver_bfm apb_m_monitor_bfm, apb_m_transaction, apb_m_pkg_b1_apb_master_BFM, +b1_axi_master1, axi_m_driver_bfm axi_m_monitor_bfm, axi_m_transaction, axi_m_pkg_b1_axi_master1_BFM, +b1_axi_master2, axi_m_driver_bfm axi_m_monitor_bfm, axi_m_transaction, axi_m_pkg_b1_axi_master2_BFM, +b1_spi_slave, spi_s_driver_bfm spi_s_monitor_bfm, spi_s_transaction, spi_s_pkg_b1_spi_slave_BFM, +b2_spi_master, spi_m_driver_bfm spi_m_monitor_bfm, spi_m_transaction, spi_m_pkg_b2_spi_master_BFM, +b2_wb_slave, wb_s_driver_bfm wb_s_monitor_bfm, wb_s_transaction, wb_s_pkg_b2_wb_slave_BFM, + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/rtl/dut.compile b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/rtl/dut.compile new file mode 100644 index 00000000..9b0008fc --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/rtl/dut.compile @@ -0,0 +1,6 @@ + +# pragma uvmf custom dut_compile_info begin +src: + - ./vhdl/vhdl_dut.vhd + - ./verilog/verilog_dut.v +# pragma uvmf custom dut_compile_info end diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/rtl/verilog/verilog_dut.v b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/rtl/verilog/verilog_dut.v new file mode 100644 index 00000000..96198441 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/rtl/verilog/verilog_dut.v @@ -0,0 +1,21 @@ +module verilog_dut(clk, rst, in_signal, out_signal); + +input clk; +input rst; +input in_signal; +output out_signal; + +reg out_signal_o; + +always @(posedge clk) begin + if (rst) begin + out_signal_o <= 0; + end + else begin + out_signal_o <= ~in_signal; + end + end + +assign out_signal = out_signal_o; + +endmodule diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/rtl/verilog/verilog_dut.vinfo b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/rtl/verilog/verilog_dut.vinfo new file mode 100644 index 00000000..87e95f36 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/rtl/verilog/verilog_dut.vinfo @@ -0,0 +1 @@ +verilog_dut.v diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/rtl/vhdl/vhdl_dut.vhd b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/rtl/vhdl/vhdl_dut.vhd new file mode 100644 index 00000000..904aa37d --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/rtl/vhdl/vhdl_dut.vhd @@ -0,0 +1,21 @@ +library ieee; +use ieee.std_logic_1164.all ; + +entity vhdl_dut is + port ( clk : in std_logic ; + rst : in std_logic ; + in_signal : in std_logic ; + out_signal :out std_logic + ); +end vhdl_dut; + +architecture rtl of vhdl_dut is + begin + P1: process + variable out_signal_o : std_logic; + begin + wait until clk'event and clk = '1'; + out_signal_o := in_signal; + out_signal <= out_signal_o; + end process; + end rtl; diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/Makefile b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/Makefile new file mode 100644 index 00000000..554483b2 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/Makefile @@ -0,0 +1,202 @@ + +# +#---------------------------------------------------------------------- +# +# DESCRIPTION: This makefile includes the shared makefile and contains +# bench level make targets. +# +#---------------------------------------------------------------------- + + +# pragma uvmf custom additional begin +# pragma uvmf custom additional end + +# ********************************************************************************************* +# UVMF library directory: +# This variable points to the UVMF release where uvmf_base_pkg directory resides. +# This variable points to release code that is not user modified. +# This variable allows for UVMF release directories to reside independent of project related verification IP and project bench directories. +# This code below looks "upward" for directory starting with UVMF_* and returns first match for use with the release examples. +UVMF_HOME ?= ___PLEASE_SET_AN_ENVIRONMENT_VARIABLE_NAMED_UVMF_HOME_TO_POINT_TO_THE_UVMF_INSTALLATION___ + +# pragma uvmf custom exports begin +# +# Project(s) specific verification IP library: +# Directory where reusable verification packages for interfaces, environments, utilities, etc. reside. +# This variable allows for your verification IP to reside independent of project bench and UVMF release directories. +# For examples deployed with UVMF this will be $(UVMF_HOME)//verification_ip +export UVMF_VIP_LIBRARY_HOME ?= $(PWD)/../../../verification_ip +# +# Project specific bench: +# Directory where bench specific code is located. +# This variable allows for project_benches to reside independent of verification IP and UVMF release directories. +# For examples deployed with UVMF this will be $(UVMF_HOME)//project_benches/ +export UVMF_PROJECT_DIR ?= $(PWD)/.. +# +# +# pragma uvmf custom exports end +# ********************************************************************************************* + +## Check PATH for required vinfo scripts +PVAL := $(shell command -v make_filelist.py 2> /dev/null) +ifndef PVAL + MFLIST = $(UVMF_HOME)/scripts/make_filelist.py +else + MFLIST = make_filelist.py +endif + + +# Set test case specific Variables +TEST_NAME ?= test_top + +TEST_SEED ?= random +UVM_CLI_ARGS = + +# Usage of Veloce, etc. to be input by the user (subject to defaults) +USE_VELOCE ?= 0 + +# Usage of vinfo flow for generating file list +USE_VINFO ?= 0 + +# Usage of Veloce and Questa profilers +USE_VELOCE_PROFILER ?= 0 +USE_QUESTA_PROFILER ?= 0 + + +# Set project Variables +TEST_PLAN_NAME = subsys_TestPlan +REPORTING_DO_FILE = subsys_reports_script + + +# Include makefile that includes targets for UVM_VIP_Library packages +include $(UVMF_HOME)/scripts/Makefile + + + + +# Include all requisite interface package targets for this bench +include $(UVMF_VIP_LIBRARY_HOME)/interface_packages/apb_m_pkg/Makefile +include $(UVMF_VIP_LIBRARY_HOME)/interface_packages/axi_m_pkg/Makefile +include $(UVMF_VIP_LIBRARY_HOME)/interface_packages/spi_s_pkg/Makefile +include $(UVMF_VIP_LIBRARY_HOME)/interface_packages/spi_m_pkg/Makefile +include $(UVMF_VIP_LIBRARY_HOME)/interface_packages/wb_s_pkg/Makefile + +# Include all requisite environment package targets for this bench +include $(UVMF_VIP_LIBRARY_HOME)/environment_packages/subsys_env_pkg/Makefile + + + +# Add to default compile/load/run arguments +VCOM_ARGS += + +# Note: vsim-3009 error can be eliminated by adding -timescale 1ps/1ps to VLOG_ARGS + +VLOG_ARGS += $(UVM_DISABLE_FILE_LINE_CMD) + +VELANALYZE_ARGS += +VELANALYZE_HVL_ARGS += + +BATCH_VOPT_ARGS += +DEBUG_VOPT_ARGS += +EXTRA_VOPT_TOPS += +COMMON_VSIM_ARGS += +COMMON_VSIM_ARGS += + + +BATCH_VSIM_ARGS += #-uvmcontrol=none +DEBUG_VSIM_ARGS += +EXTRA_VSIM_TOPS += + +# pragma uvmf custom additional_args begin +# pragma uvmf custom additional_args end + + +# Project bench package source +subsys_PARAMETERS_PKG ?=\ +$(UVMF_PROJECT_DIR)/tb/parameters/subsys_parameters_pkg.sv + + +subsys_SEQUENCES_PKG ?=\ +$(UVMF_PROJECT_DIR)/tb/sequences/subsys_sequences_pkg.sv + + +subsys_TEST_PKG ?=\ +$(UVMF_PROJECT_DIR)/tb/tests/subsys_tests_pkg.sv + +# pragma uvmf custom dut_files begin +# UVMF_CHANGE_ME : Reference Verilog DUT source. +subsys_VERILOG_DUT ?=\ +$(UVMF_PROJECT_DIR)/rtl/verilog/verilog_dut.v + +# UVMF_CHANGE_ME : Reference VHDL DUT source. +subsys_VHDL_DUT ?=\ +$(UVMF_PROJECT_DIR)/rtl/vhdl/vhdl_dut.vhd +# pragma uvmf custom dut_files end + + +# Project bench package targets +COMP_subsys_PARAMETERS_PKG_TGT_0 = q_comp_subsys_parameters_pkg +COMP_subsys_PARAMETERS_PKG_TGT_1 = v_comp_subsys_parameters_pkg +COMP_subsys_PARAMETERS_PKG_TGT = $(COMP_subsys_PARAMETERS_PKG_TGT_$(USE_VELOCE)) + +comp_subsys_parameters_pkg: $(COMP_subsys_PARAMETERS_PKG_TGT) + +q_comp_subsys_parameters_pkg: + $(HVL_COMP_CMD) +incdir+$(UVMF_PROJECT_DIR)/tb/parameters $(subsys_PARAMETERS_PKG) + +v_comp_subsys_parameters_pkg: q_comp_subsys_parameters_pkg + $(HDL_COMP_CMD) +incdir+$(UVMF_PROJECT_DIR)/tb/parameters $(subsys_PARAMETERS_PKG) + + +comp_subsys_sequence_pkg: + $(HVL_COMP_CMD) +incdir+$(UVMF_PROJECT_DIR)/tb/sequences $(subsys_SEQUENCES_PKG) + +comp_subsys_tests_pkg: + $(HVL_COMP_CMD) +incdir+$(UVMF_PROJECT_DIR)/tb/tests $(subsys_TEST_PKG) + +# pragma uvmf custom dut_compile_make_target begin +# UVMF_CHANGE_ME : Add make target to compile your verilog dut here +comp_subsys_verilog_dut: + echo "Compile your verilog DUT here" + $(HDL_COMP_CMD) $(subsys_VERILOG_DUT) + +# UVMF_CHANGE_ME : Add make target to compile your vhdl dut here +comp_subsys_vhdl_dut: + echo "Compile your vhdl DUT here" + $(HDL_COMP_CMD_VHDL) $(subsys_VHDL_DUT) + +# UVMF_CHANGE_ME : Add make target to compile your dut here +comp_subsys_dut: comp_subsys_vhdl_dut comp_subsys_verilog_dut +# pragma uvmf custom dut_compile_make_target end + + +BUILD_TGT_0 = make_build +BUILD_TGT_1 = vinfo_build +BUILD_TGT = $(BUILD_TGT_$(USE_VINFO)) + + +comp_hvl : comp_hvl_core + + +comp_hvl_core : \ + comp_apb_m_pkg comp_axi_m_pkg comp_spi_s_pkg comp_spi_m_pkg comp_wb_s_pkg \ + comp_subsys_env_pkg \ + comp_subsys_parameters_pkg comp_subsys_sequence_pkg comp_subsys_tests_pkg + +comp_uvmf_core : comp_uvm_pkg comp_uvmf_base_pkg + +make_build: comp_subsys_dut comp_uvmf_core comp_hvl comp_test_bench + +hvl_build: q_comp_apb_m_pkg q_comp_axi_m_pkg q_comp_spi_s_pkg q_comp_spi_m_pkg q_comp_wb_s_pkg comp_subsys_env_pkg comp_subsys_sequence_pkg comp_subsys_tests_pkg hvl_comp_testbench link optimize + + +vinfo_build: comp_subsys_vhdl_dut build_hdl_vinfo build_hvl_vinfo $(VINFO_TGT) + + $(HDL_COMP_CMD) -F hdl.vf + $(VEL_COMP) + +build: $(BUILD_TGT) + +# pragma uvmf custom additional_targets begin +# pragma uvmf custom additional_targets end + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/bcr_testlist b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/bcr_testlist new file mode 100644 index 00000000..a4aae156 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/bcr_testlist @@ -0,0 +1,19 @@ + + + +# Test list for use by RMDB file +# File syntax is +# TB_INFO { } { } +# TB ## All subsequent tests will run on this bench until a different "TB" line is seen +# TEST <1st_seed> ... +# If not enough seeds are provided then random seeds are used to pad +# If no repeat count is given, default is 1 +# pragma uvmf custom tb_info begin +TB_INFO subsys { } { } +# pragma uvmf custom tb_info end +TB subsys +# pragma uvmf custom regression_suite begin +TEST test_top 3 +# pragma uvmf custom regression_suite end + + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/bcr_testlist.yaml b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/bcr_testlist.yaml new file mode 100644 index 00000000..27abcd04 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/bcr_testlist.yaml @@ -0,0 +1,44 @@ + + + +# YAML test list for use by RMDB file +# File syntax is +# uvmf_testlist: +# testbenches: +# - name: +# extra_build_options: +# extra_run_options: +# - name: +# ... +# - name: +# tests: +# - name: +# uvm_testname: (defaults to test_name) +# testbench: (defaults to last tb name seen) +# repeat: (defaults to 1) +# seeds: [,,...,] (defaults to all random) +# extra_test_options: +# - name: +# ... +# - name: +# include: +# - (relative path reference is to the including YAML file) +# - +# ... +# - + +uvmf_testlist: + testbenches: +# pragma uvmf custom tb_info begin + - name: subsys + extra_build_options: "" + extra_run_options: "" +# pragma uvmf custom tb_info end + tests: + - testbench: subsys +# pragma uvmf custom regression_suite begin + - name: test_top + repeat: 3 +# pragma uvmf custom regression_suite end + + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/compile.do b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/compile.do new file mode 100644 index 00000000..489d3e86 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/compile.do @@ -0,0 +1,74 @@ + + +################################################################## +## ENVIRONMENT VARIABLES +################################################################## +quietly set ::env(UVMF_VIP_LIBRARY_HOME) ../../../verification_ip +quietly set ::env(UVMF_PROJECT_DIR) .. + +## Using VRM means that the build is occuring several more directories deeper underneath +## the sim directory, need to prepend some more '..' +if {[info exists ::env(VRM_BUILD)]} { + quietly set ::env(UVMF_VIP_LIBRARY_HOME) "../../../../../$::env(UVMF_VIP_LIBRARY_HOME)" + quietly set ::env(UVMF_PROJECT_DIR) "../../../../../$::env(UVMF_PROJECT_DIR)" +} +quietly set ::env(UVMF_VIP_LIBRARY_HOME) [file normalize $::env(UVMF_VIP_LIBRARY_HOME)] +quietly set ::env(UVMF_PROJECT_DIR) [file normalize $::env(UVMF_PROJECT_DIR)] +quietly echo "UVMF_VIP_LIBRARY_HOME = $::env(UVMF_VIP_LIBRARY_HOME)" +quietly echo "UVMF_PROJECT_DIR = $::env(UVMF_PROJECT_DIR)" + + +################################################################### +## HOUSEKEEPING : DELETE FILES THAT WILL BE REGENERATED +################################################################### +file delete -force *~ *.ucdb vsim.dbg *.vstf *.log work *.mem *.transcript.txt certe_dump.xml *.wlf covhtmlreport VRMDATA +file delete -force design.bin qwave.db dpiheader.h visualizer*.ses +file delete -force veloce.med veloce.wave veloce.map tbxbindings.h edsenv velrunopts.ini +file delete -force sv_connect.* + +################################################################### +## COMPILE DUT SOURCE CODE +################################################################### +vlib work +# pragma uvmf custom dut_compile_dofile_target begin +# UVMF_CHANGE_ME : Add commands to compile your dut here, replacing the default examples +vlog -sv -timescale 1ps/1ps -suppress 2223,2286 $env(UVMF_PROJECT_DIR)/rtl/verilog/verilog_dut.v +vcom $env(UVMF_PROJECT_DIR)/rtl/vhdl/vhdl_dut.vhd +# pragma uvmf custom dut_compile_dofile_target end + +################################################################### +## COMPILE UVMF BASE/COMMON SOURCE CODE +################################################################### +vlog -sv -timescale 1ps/1ps -suppress 2223 -suppress 2286 +incdir+$env(UVMF_HOME)/uvmf_base_pkg -F $env(UVMF_HOME)/uvmf_base_pkg/uvmf_base_pkg_filelist_hdl.f +vlog -sv -timescale 1ps/1ps -suppress 2223 -suppress 2286 +incdir+$env(UVMF_HOME)/uvmf_base_pkg -F $env(UVMF_HOME)/uvmf_base_pkg/uvmf_base_pkg_filelist_hvl.f + + +################################################################### +## UVMF INTERFACE COMPILATION +################################################################### +do $env(UVMF_VIP_LIBRARY_HOME)/interface_packages/apb_m_pkg/compile.do +do $env(UVMF_VIP_LIBRARY_HOME)/interface_packages/axi_m_pkg/compile.do +do $env(UVMF_VIP_LIBRARY_HOME)/interface_packages/spi_s_pkg/compile.do +do $env(UVMF_VIP_LIBRARY_HOME)/interface_packages/spi_m_pkg/compile.do +do $env(UVMF_VIP_LIBRARY_HOME)/interface_packages/wb_s_pkg/compile.do + +################################################################### +## UVMF ENVIRONMENT COMPILATION +################################################################### +do $env(UVMF_VIP_LIBRARY_HOME)/environment_packages/subsys_env_pkg/compile.do + +################################################################### +## UVMF BENCHES COMPILATION +################################################################### +vlog -sv -timescale 1ps/1ps -suppress 2223 -suppress 2286 +incdir+$env(UVMF_PROJECT_DIR)/tb/parameters $env(UVMF_PROJECT_DIR)/tb/parameters/subsys_parameters_pkg.sv +vlog -sv -timescale 1ps/1ps -suppress 2223 -suppress 2286 +incdir+$env(UVMF_PROJECT_DIR)/tb/sequences $env(UVMF_PROJECT_DIR)/tb/sequences/subsys_sequences_pkg.sv +vlog -sv -timescale 1ps/1ps -suppress 2223 -suppress 2286 +incdir+$env(UVMF_PROJECT_DIR)/tb/tests $env(UVMF_PROJECT_DIR)/tb/tests/subsys_tests_pkg.sv + +vlog -sv -timescale 1ps/1ps -suppress 2223 -suppress 2286 +incdir+$env(UVMF_PROJECT_DIR)/tb/testbench -F $env(UVMF_PROJECT_DIR)/tb/testbench/top_filelist_hdl.f +vlog -sv -timescale 1ps/1ps -suppress 2223 -suppress 2286 +incdir+$env(UVMF_PROJECT_DIR)/tb/testbench -F $env(UVMF_PROJECT_DIR)/tb/testbench/top_filelist_hvl.f + +################################################################### +## OPTIMIZATION +################################################################### +vopt hvl_top hdl_top -o optimized_batch_top_tb +vopt +acc hvl_top hdl_top -o optimized_debug_top_tb diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/hdl.compile b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/hdl.compile new file mode 100644 index 00000000..8e7bd41a --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/hdl.compile @@ -0,0 +1,5 @@ +needs: +# pragma uvmf custom dut_compile_info begin + - ../rtl/dut.compile +# pragma uvmf custom dut_compile_info end + - ../tb/testbench/hdl_top.compile diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/hdl.vinfo b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/hdl.vinfo new file mode 100644 index 00000000..da27ec77 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/hdl.vinfo @@ -0,0 +1 @@ +@use $UVMF_PROJECT_DIR/tb/testbench/hdl_top.vinfo diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/hvl.compile b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/hvl.compile new file mode 100644 index 00000000..ce952549 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/hvl.compile @@ -0,0 +1,2 @@ +needs: + - ../tb/testbench/hvl_top.compile diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/hvl.vinfo b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/hvl.vinfo new file mode 100644 index 00000000..d22eff33 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/hvl.vinfo @@ -0,0 +1 @@ +@use $UVMF_PROJECT_DIR/tb/testbench/hvl_top.vinfo diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/run.do b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/run.do new file mode 100644 index 00000000..101ddc48 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/run.do @@ -0,0 +1,21 @@ + + +quietly set svLibs "" +quietly set extra_vsim_args "" + +################################################################### +## Check for additional vsim arguments passed using env var $UVMF_EXTRA_VSIM_ARGS +################################################################### +if {[info exists ::env(UVMF_EXTRA_VSIM_ARGS)]} { + echo "Adding more args to vsim command" + quietly set extra_vsim_args $::env(UVMF_EXTRA_VSIM_ARGS) +} + +################################################################## +## Launch Questa : generate vsim command line and execute +################################################################## +# pragma uvmf custom dut_run_dofile_target begin +# UVMF_CHANGE_ME : Change the UVM_TESTNAME plusarg to run a different test +quietly set cmd [format "vsim -i -sv_seed random +UVM_TESTNAME=test_top +UVM_VERBOSITY=UVM_HIGH -permit_unmatched_virtual_intf +notimingchecks -suppress 8887 %s %s -uvmcontrol=all -msgmode both -classdebug -assertdebug +uvm_set_config_int=*,enable_transaction_viewing,1 -do { set NoQuitOnFinish 1; onbreak {resume}; run 0; do wave.do; set PrefSource(OpenOnBreak) 0; radix hex showbase; } optimized_debug_top_tb" $svLibs $extra_vsim_args] +# pragma uvmf custom dut_run_dofile_target end +eval $cmd diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/tbx.config b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/tbx.config new file mode 100644 index 00000000..eec58168 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/tbx.config @@ -0,0 +1,10 @@ + + + + + +comp -questa +velsyn -D1S +rtlc -allow_4ST + + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/testlist b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/testlist new file mode 100644 index 00000000..81ee4a56 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/testlist @@ -0,0 +1,20 @@ + + + + +# Test list for use by RMDB file +# File syntax is +# TB_INFO { } { } +# TB ## All subsequent tests will run on this bench until a different "TB" line is seen +# TEST <1st_seed> ... +# If not enough seeds are provided then random seeds are used to pad +# If no repeat count is given, default is 1 +# pragma uvmf custom tb_info begin +TB_INFO subsys { UVMF_VIP_LIBRARY_HOME=../../../../../../../../verification_ip UVMF_PROJECT_DIR=../../../../../../../subsys } { } +# pragma uvmf custom tb_info end +TB subsys +# pragma uvmf custom regression_suite begin +TEST test_top 3 +# pragma uvmf custom regression_suite end + + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/testlist.yaml b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/testlist.yaml new file mode 100644 index 00000000..b8b6f60b --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/testlist.yaml @@ -0,0 +1,44 @@ + + + +# YAML test list for use by RMDB file +# File syntax is +# uvmf_testlist: +# testbenches: +# - name: +# extra_build_options: +# extra_run_options: +# - name: +# ... +# - name: +# tests: +# - name: +# uvm_testname: (defaults to test_name) +# testbench: (defaults to last tb name seen) +# repeat: (defaults to 1) +# seeds: [,,...,] (defaults to all random) +# extra_test_options: +# - name: +# ... +# - name: +# include: +# - (relative path reference is to the including YAML file) +# - +# ... +# - + +uvmf_testlist: + testbenches: +# pragma uvmf custom tb_info begin + - name: subsys + extra_build_options: "UVMF_VIP_LIBRARY_HOME=../../../../../../../../verification_ip UVMF_PROJECT_DIR=../../../../../../../subsys" + extra_run_options: "" +# pragma uvmf custom tb_info end + tests: + - testbench: subsys +# pragma uvmf custom regression_suite begin + - name: test_top + repeat: 3 +# pragma uvmf custom regression_suite end + + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/top.compile b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/top.compile new file mode 100644 index 00000000..efd51c07 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/top.compile @@ -0,0 +1,3 @@ +needs: + - hvl.compile + - hdl.compile diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/veloce.config b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/veloce.config new file mode 100644 index 00000000..d0975155 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/veloce.config @@ -0,0 +1,26 @@ + + + + + +# pragma uvmf custom additional begin +comp -num_boards 1 +comp -hvl questa +# Please choose the correct emulator type code for +# comp -platform command or else velcomp will fail +# Available types are: +# - Veloce2 Quattro: D2 +# - Veloce2 Maximus: D2M +# - Veloce Strato TiL, Ti, and Mi: Strato +# - Veloce Strato M and Strato T: StratoM +# - comp -platform +comp -platform Strato + +rtlc -enable_tbx_pragma_checks +rtlc -allow_4ST +rtlc -allow_MDR +rtlc -compile_display +rtlc -xwave_siglist xwaves.sigs +# pragma uvmf custom additional end + + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/viswave.do b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/viswave.do new file mode 100644 index 00000000..18bcb537 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/viswave.do @@ -0,0 +1,46 @@ + + +onerror resume +wave tags F0 +wave update off + +wave spacer -backgroundcolor Salmon { b1_apb_master } +wave add uvm_test_top.environment.b1.apb_master.apb_master_monitor.txn_stream -radix string -tag F0 +wave group b1_apb_master_bus +wave add -group b1_apb_master_bus hdl_top.b1_apb_master_bus.* -radix hexadecimal -tag F0 +wave group b1_apb_master_bus -collapse +wave insertion [expr [wave index insertpoint] +1] +wave spacer -backgroundcolor Salmon { b1_axi_master1 } +wave add uvm_test_top.environment.b1.axi_master1.axi_master1_monitor.txn_stream -radix string -tag F0 +wave group b1_axi_master1_bus +wave add -group b1_axi_master1_bus hdl_top.b1_axi_master1_bus.* -radix hexadecimal -tag F0 +wave group b1_axi_master1_bus -collapse +wave insertion [expr [wave index insertpoint] +1] +wave spacer -backgroundcolor Salmon { b1_axi_master2 } +wave add uvm_test_top.environment.b1.axi_master2.axi_master2_monitor.txn_stream -radix string -tag F0 +wave group b1_axi_master2_bus +wave add -group b1_axi_master2_bus hdl_top.b1_axi_master2_bus.* -radix hexadecimal -tag F0 +wave group b1_axi_master2_bus -collapse +wave insertion [expr [wave index insertpoint] +1] +wave spacer -backgroundcolor Salmon { b1_spi_slave } +wave add uvm_test_top.environment.b1.spi_slave.spi_slave_monitor.txn_stream -radix string -tag F0 +wave group b1_spi_slave_bus +wave add -group b1_spi_slave_bus hdl_top.b1_spi_slave_bus.* -radix hexadecimal -tag F0 +wave group b1_spi_slave_bus -collapse +wave insertion [expr [wave index insertpoint] +1] +wave spacer -backgroundcolor Salmon { b2_spi_master } +wave add uvm_test_top.environment.b2.spi_master.spi_master_monitor.txn_stream -radix string -tag F0 +wave group b2_spi_master_bus +wave add -group b2_spi_master_bus hdl_top.b2_spi_master_bus.* -radix hexadecimal -tag F0 +wave group b2_spi_master_bus -collapse +wave insertion [expr [wave index insertpoint] +1] +wave spacer -backgroundcolor Salmon { b2_wb_slave } +wave add uvm_test_top.environment.b2.wb_slave.wb_slave_monitor.txn_stream -radix string -tag F0 +wave group b2_wb_slave_bus +wave add -group b2_wb_slave_bus hdl_top.b2_wb_slave_bus.* -radix hexadecimal -tag F0 +wave group b2_wb_slave_bus -collapse +wave insertion [expr [wave index insertpoint] +1] + +wave update on +WaveSetStreamView + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/wave.do b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/wave.do new file mode 100644 index 00000000..f76bf238 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/wave.do @@ -0,0 +1,42 @@ + + +onerror {resume} +quietly WaveActivateNextPane {} 0 + +add wave -noupdate -divider b1_apb_master +add wave -noupdate /uvm_root/uvm_test_top/environment.b1/apb_master/apb_master_monitor/txn_stream +add wave -noupdate -group b1_apb_master_bus /hdl_top/b1_apb_master_bus/* +add wave -noupdate -divider b1_axi_master1 +add wave -noupdate /uvm_root/uvm_test_top/environment.b1/axi_master1/axi_master1_monitor/txn_stream +add wave -noupdate -group b1_axi_master1_bus /hdl_top/b1_axi_master1_bus/* +add wave -noupdate -divider b1_axi_master2 +add wave -noupdate /uvm_root/uvm_test_top/environment.b1/axi_master2/axi_master2_monitor/txn_stream +add wave -noupdate -group b1_axi_master2_bus /hdl_top/b1_axi_master2_bus/* +add wave -noupdate -divider b1_spi_slave +add wave -noupdate /uvm_root/uvm_test_top/environment.b1/spi_slave/spi_slave_monitor/txn_stream +add wave -noupdate -group b1_spi_slave_bus /hdl_top/b1_spi_slave_bus/* +add wave -noupdate -divider b2_spi_master +add wave -noupdate /uvm_root/uvm_test_top/environment.b2/spi_master/spi_master_monitor/txn_stream +add wave -noupdate -group b2_spi_master_bus /hdl_top/b2_spi_master_bus/* +add wave -noupdate -divider b2_wb_slave +add wave -noupdate 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@:f16gV]U:n:GLeRg^1No2 +======= +DXx4 work 16 apb_m_if_sv_unit 0 22 ]RkXmHT9^n1V[TNdYaAHF1 +>>>>>>> ceab28f188594b972dededef57152e3a46196cbf +R7 +r1 +!s85 0 +31 +!i10b 1 +!s100 hof1>>>>>> ceab28f188594b972dededef57152e3a46196cbf +r1 +!s85 0 +31 +!i10b 1 +!s100 dTlIN=W0eH8_Wb9T15EeD1 +<<<<<<< HEAD +I@:f16gV]U:n:GLeRg^1No2 +======= +I]RkXmHT9^n1V[TNdYaAHF1 +>>>>>>> ceab28f188594b972dededef57152e3a46196cbf +!i103 1 +S1 +R8 +R9 +R34 +R35 +L0 33 +R25 +R26 +R27 +R28 +!i113 0 +R29 +R30 +R31 +Yapb_m_monitor_bfm +R1 +R2 +R3 +<<<<<<< HEAD +DXx4 work 25 apb_m_monitor_bfm_sv_unit 0 22 FL=8dMh5C69cnI:G6b<;g2 +======= +DXx4 work 25 apb_m_monitor_bfm_sv_unit 0 22 MD8JDZP910^Fz98E]l`kI3 +>>>>>>> ceab28f188594b972dededef57152e3a46196cbf +R4 +R5 +R6 +R7 +r1 +!s85 0 +31 +!i10b 1 +!s100 FP`^a@WG_VbcAFJm6]=Pl1 +<<<<<<< HEAD +II=nPaYoj]IUnWoA>;Y8:]3 +======= +Iie>bU1_>]bo3zdXaZRiW@2 +>>>>>>> ceab28f188594b972dededef57152e3a46196cbf +!s105 apb_m_monitor_bfm_sv_unit +S1 +R8 +R9 +Z37 8/hwetools/work_area/frontend/vineeth_b7/system/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../../../verification_ip/interface_packages/apb_m_pkg/src/apb_m_monitor_bfm.sv +Z38 F/hwetools/work_area/frontend/vineeth_b7/system/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../../../verification_ip/interface_packages/apb_m_pkg/src/apb_m_monitor_bfm.sv +R12 +R13 +R14 +R15 +R16 +R17 +R18 +R19 +R20 +R21 +R22 +R23 +R36 +R25 +R26 +R27 +R28 +!i113 0 +R29 +R30 +R31 +Xapb_m_monitor_bfm_sv_unit +R1 +R2 +R3 +<<<<<<< HEAD +VFL=8dMh5C69cnI:G6b<;g2 +======= +VMD8JDZP910^Fz98E]l`kI3 +>>>>>>> ceab28f188594b972dededef57152e3a46196cbf +r1 +!s85 0 +31 +!i10b 1 +!s100 768KNg5OXno5e0J0 +<<<<<<< HEAD +IFL=8dMh5C69cnI:G6b<;g2 +======= +IMD8JDZP910^Fz98E]l`kI3 +>>>>>>> ceab28f188594b972dededef57152e3a46196cbf +!i103 1 +S1 +R8 +R9 +R37 +R38 +R32 +Z39 L0 31 +R25 +R26 +R27 +R28 +!i113 0 +R29 +R30 +R31 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+F/hwetools/work_area/frontend/vineeth_b7/system/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../../../verification_ip/interface_packages/apb_m_pkg/apb_m_pkg.sv +>>>>>>> ceab28f188594b972dededef57152e3a46196cbf +R12 +R13 +R14 +R15 +R16 +R17 +R18 +R19 +R20 +R21 +R22 +R23 +R32 +F/hwetools/work_area/frontend/vineeth_b7/system/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../../../verification_ip/interface_packages/apb_m_pkg/src/apb_m_typedefs.svh +F/hwetools/work_area/frontend/vineeth_b7/system/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../../../verification_ip/interface_packages/apb_m_pkg/src/apb_m_transaction.svh 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+F/hwetools/work_area/frontend/vineeth_b7/system/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../../../verification_ip/interface_packages/apb_m_pkg/src/apb_m_sequence_base.svh +F/hwetools/work_area/frontend/vineeth_b7/system/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../../../verification_ip/interface_packages/apb_m_pkg/src/apb_m_random_sequence.svh +F/hwetools/work_area/frontend/vineeth_b7/system/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../../../verification_ip/interface_packages/apb_m_pkg/src/apb_m_responder_sequence.svh +F/hwetools/work_area/frontend/vineeth_b7/system/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../../../verification_ip/interface_packages/apb_m_pkg/src/apb_m2reg_adapter.svh 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/hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../../../verification_ip/interface_packages/apb_m_pkg/src/apb_m_agent.svh|/hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../../../verification_ip/interface_packages/apb_m_pkg/src/apb_m2reg_adapter.svh|/hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../../../verification_ip/interface_packages/apb_m_pkg/src/apb_m_responder_sequence.svh|/hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../../../verification_ip/interface_packages/apb_m_pkg/src/apb_m_random_sequence.svh|/hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../../../verification_ip/interface_packages/apb_m_pkg/src/apb_m_sequence_base.svh|/hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../../../verification_ip/interface_packages/apb_m_pkg/src/apb_m_transaction_coverage.svh|/hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../../../verification_ip/interface_packages/apb_m_pkg/src/apb_m_monitor.svh|/hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../../../verification_ip/interface_packages/apb_m_pkg/src/apb_m_driver.svh|/hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../../../verification_ip/interface_packages/apb_m_pkg/src/apb_m_configuration.svh|/hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../../../verification_ip/interface_packages/apb_m_pkg/src/apb_m_transaction.svh|/hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../../../verification_ip/interface_packages/apb_m_pkg/src/apb_m_typedefs.svh|/hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../../../verification_ip/interface_packages/apb_m_pkg/src/apb_m_macros.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/macros/uvm_deprecated_defines.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/macros/uvm_reg_defines.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/macros/uvm_callback_defines.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/macros/uvm_sequence_defines.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/tlm1/uvm_tlm_imps.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/macros/uvm_tlm_defines.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/macros/uvm_printer_defines.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/macros/uvm_object_defines.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/macros/uvm_phase_defines.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/macros/uvm_message_defines.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/macros/uvm_version_defines.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/uvm_macros.svh|/hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../../../verification_ip/interface_packages/apb_m_pkg/apb_m_pkg.sv| +!s90 -sv|-suppress|2223|-suppress|2286|+define+UVM_REPORT_DISABLE_FILE_LINE|+define+UVM_REPORT_DISABLE_FILE_LINE|+incdir+/hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../../../verification_ip/interface_packages/apb_m_pkg|-F|/hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../../../verification_ip/interface_packages/apb_m_pkg/apb_m_filelist_hvl.f| +======= +Z40 !s108 1672027881.000000 +!s107 /hwetools/work_area/frontend/vineeth_b7/system/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../../../verification_ip/interface_packages/apb_m_pkg/src/apb_m_agent.svh|/hwetools/work_area/frontend/vineeth_b7/system/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../../../verification_ip/interface_packages/apb_m_pkg/src/apb_m2reg_adapter.svh|/hwetools/work_area/frontend/vineeth_b7/system/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../../../verification_ip/interface_packages/apb_m_pkg/src/apb_m_responder_sequence.svh|/hwetools/work_area/frontend/vineeth_b7/system/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../../../verification_ip/interface_packages/apb_m_pkg/src/apb_m_random_sequence.svh|/hwetools/work_area/frontend/vineeth_b7/system/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../../../verification_ip/interface_packages/apb_m_pkg/src/apb_m_sequence_base.svh|/hwetools/work_area/frontend/vineeth_b7/system/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../../../verification_ip/interface_packages/apb_m_pkg/src/apb_m_transaction_coverage.svh|/hwetools/work_area/frontend/vineeth_b7/system/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../../../verification_ip/interface_packages/apb_m_pkg/src/apb_m_monitor.svh|/hwetools/work_area/frontend/vineeth_b7/system/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../../../verification_ip/interface_packages/apb_m_pkg/src/apb_m_driver.svh|/hwetools/work_area/frontend/vineeth_b7/system/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../../../verification_ip/interface_packages/apb_m_pkg/src/apb_m_configuration.svh|/hwetools/work_area/frontend/vineeth_b7/system/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../../../verification_ip/interface_packages/apb_m_pkg/src/apb_m_transaction.svh|/hwetools/work_area/frontend/vineeth_b7/system/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../../../verification_ip/interface_packages/apb_m_pkg/src/apb_m_typedefs.svh|/hwetools/work_area/frontend/vineeth_b7/system/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../../../verification_ip/interface_packages/apb_m_pkg/src/apb_m_macros.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/macros/uvm_deprecated_defines.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/macros/uvm_reg_defines.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/macros/uvm_callback_defines.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/macros/uvm_sequence_defines.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/tlm1/uvm_tlm_imps.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/macros/uvm_tlm_defines.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/macros/uvm_printer_defines.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/macros/uvm_object_defines.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/macros/uvm_phase_defines.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/macros/uvm_message_defines.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/macros/uvm_version_defines.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/uvm_macros.svh|/hwetools/work_area/frontend/vineeth_b7/system/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../../../verification_ip/interface_packages/apb_m_pkg/apb_m_pkg.sv| +!s90 -sv|-suppress|2223|-suppress|2286|+define+UVM_REPORT_DISABLE_FILE_LINE|+define+UVM_REPORT_DISABLE_FILE_LINE|+incdir+/hwetools/work_area/frontend/vineeth_b7/system/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../../../verification_ip/interface_packages/apb_m_pkg|-F|/hwetools/work_area/frontend/vineeth_b7/system/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../../../verification_ip/interface_packages/apb_m_pkg/apb_m_filelist_hvl.f| +>>>>>>> ceab28f188594b972dededef57152e3a46196cbf +!i113 0 +R29 +R30 +R31 +Xapb_m_pkg_hdl +R1 +R2 +<<<<<<< HEAD +R39 +!i10b 1 +!s100 aaW93]=>ch6]Zm?aS3dLm3 +IVRQf9z>hS:ooTN4O8oSFC3 +VVRQf9z>hS:ooTN4O8oSFC3 +S1 +R0 +R40 +8/hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../../../verification_ip/interface_packages/apb_m_pkg/apb_m_pkg_hdl.sv +F/hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../../../verification_ip/interface_packages/apb_m_pkg/apb_m_pkg_hdl.sv +F/hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../../../verification_ip/interface_packages/apb_m_pkg/src/apb_m_typedefs_hdl.svh +R31 +Z41 L0 19 +R24 +r1 +!s85 0 +31 +Z42 !s108 1672041466.000000 +!s107 /hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../../../verification_ip/interface_packages/apb_m_pkg/src/apb_m_macros.svh|/hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../../../verification_ip/interface_packages/apb_m_pkg/src/apb_m_typedefs_hdl.svh|/hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../../../verification_ip/interface_packages/apb_m_pkg/apb_m_pkg_hdl.sv| +!s90 -sv|-suppress|2223|-suppress|2286|+define+UVM_REPORT_DISABLE_FILE_LINE|+define+UVM_REPORT_DISABLE_FILE_LINE|+incdir+/hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../../../verification_ip/interface_packages/apb_m_pkg|-F|/hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../../../verification_ip/interface_packages/apb_m_pkg/apb_m_filelist_hdl.f| +======= +Z41 !s110 1672027881 +!i10b 1 +!s100 aaW93]=>ch6]Zm?aS3dLm3 +I:gRkK2he8;9gkhz6;3`cQ0 +V:gRkK2he8;9gkhz6;3`cQ0 +S1 +R8 +R9 +8/hwetools/work_area/frontend/vineeth_b7/system/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../../../verification_ip/interface_packages/apb_m_pkg/apb_m_pkg_hdl.sv +F/hwetools/work_area/frontend/vineeth_b7/system/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../../../verification_ip/interface_packages/apb_m_pkg/apb_m_pkg_hdl.sv +F/hwetools/work_area/frontend/vineeth_b7/system/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../../../verification_ip/interface_packages/apb_m_pkg/src/apb_m_typedefs_hdl.svh +R32 +Z42 L0 19 +R25 +r1 +!s85 0 +31 +R40 +!s107 /hwetools/work_area/frontend/vineeth_b7/system/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../../../verification_ip/interface_packages/apb_m_pkg/src/apb_m_macros.svh|/hwetools/work_area/frontend/vineeth_b7/system/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../../../verification_ip/interface_packages/apb_m_pkg/src/apb_m_typedefs_hdl.svh|/hwetools/work_area/frontend/vineeth_b7/system/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../../../verification_ip/interface_packages/apb_m_pkg/apb_m_pkg_hdl.sv| +!s90 -sv|-suppress|2223|-suppress|2286|+define+UVM_REPORT_DISABLE_FILE_LINE|+define+UVM_REPORT_DISABLE_FILE_LINE|+incdir+/hwetools/work_area/frontend/vineeth_b7/system/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../../../verification_ip/interface_packages/apb_m_pkg|-F|/hwetools/work_area/frontend/vineeth_b7/system/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../../../verification_ip/interface_packages/apb_m_pkg/apb_m_filelist_hdl.f| +>>>>>>> ceab28f188594b972dededef57152e3a46196cbf +!i113 0 +R29 +R30 +R31 +Yaxi_m_driver_bfm +R1 +R2 +<<<<<<< HEAD +Z43 DXx4 work 13 axi_m_pkg_hdl 0 22 me_L3R3SI[>8KC4Rech5:1 +DXx4 work 24 axi_m_driver_bfm_sv_unit 0 22 Se0II?LAVonPB5d]GYGRhmEZ2 +DXx4 work 24 axi_m_driver_bfm_sv_unit 0 22 gmd@3_zXHEO6ZEIhiZP?I0 +R4 +R5 +Z44 DXx4 work 9 axi_m_pkg 0 22 WfkETX_K@CK>iEzYWUH9c3 +>>>>>>> ceab28f188594b972dededef57152e3a46196cbf +R7 +r1 +!s85 0 +31 +!i10b 1 +!s100 T3ZQ1Tm?GV2YHY6FomUm:0 +<<<<<<< HEAD +IG?A;Wj_klb@8AbT]Tz_a11 +!s105 axi_m_driver_bfm_sv_unit +S1 +R0 +Z45 w1672041444 +Z46 8/hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../../../verification_ip/interface_packages/axi_m_pkg/src/axi_m_driver_bfm.sv +Z47 F/hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../../../verification_ip/interface_packages/axi_m_pkg/src/axi_m_driver_bfm.sv +R11 +======= +Iz89`RZSFQnkkl>1Ce_Hn@3 +!s105 axi_m_driver_bfm_sv_unit +S1 +R8 +R9 +Z45 8/hwetools/work_area/frontend/vineeth_b7/system/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../../../verification_ip/interface_packages/axi_m_pkg/src/axi_m_driver_bfm.sv +Z46 F/hwetools/work_area/frontend/vineeth_b7/system/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../../../verification_ip/interface_packages/axi_m_pkg/src/axi_m_driver_bfm.sv +>>>>>>> ceab28f188594b972dededef57152e3a46196cbf +R12 +R13 +R14 +R15 +R16 +R17 +R18 +R19 +R20 +R21 +R22 +R23 +R24 +<<<<<<< HEAD +Z48 !s108 1672041469.000000 +Z49 !s107 /tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/macros/uvm_deprecated_defines.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/macros/uvm_reg_defines.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/macros/uvm_callback_defines.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/macros/uvm_sequence_defines.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/tlm1/uvm_tlm_imps.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/macros/uvm_tlm_defines.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/macros/uvm_printer_defines.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/macros/uvm_object_defines.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/macros/uvm_phase_defines.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/macros/uvm_message_defines.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/macros/uvm_version_defines.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/uvm_macros.svh|/hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../../../verification_ip/interface_packages/axi_m_pkg/src/axi_m_macros.svh|/hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../../../verification_ip/interface_packages/axi_m_pkg/src/axi_m_driver_bfm.sv|/hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../../../verification_ip/interface_packages/axi_m_pkg/src/axi_m_monitor_bfm.sv|/hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../../../verification_ip/interface_packages/axi_m_pkg/src/axi_m_if.sv| +Z50 !s90 -sv|-suppress|2223|-suppress|2286|+define+UVM_REPORT_DISABLE_FILE_LINE|+define+UVM_REPORT_DISABLE_FILE_LINE|+incdir+/hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../../../verification_ip/interface_packages/axi_m_pkg|-F|/hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../../../verification_ip/interface_packages/axi_m_pkg/axi_m_filelist_xrtl.f| +======= +R25 +Z47 !s108 1672027884.000000 +Z48 !s107 /tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/macros/uvm_deprecated_defines.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/macros/uvm_reg_defines.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/macros/uvm_callback_defines.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/macros/uvm_sequence_defines.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/tlm1/uvm_tlm_imps.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/macros/uvm_tlm_defines.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/macros/uvm_printer_defines.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/macros/uvm_object_defines.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/macros/uvm_phase_defines.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/macros/uvm_message_defines.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/macros/uvm_version_defines.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/uvm_macros.svh|/hwetools/work_area/frontend/vineeth_b7/system/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../../../verification_ip/interface_packages/axi_m_pkg/src/axi_m_macros.svh|/hwetools/work_area/frontend/vineeth_b7/system/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../../../verification_ip/interface_packages/axi_m_pkg/src/axi_m_driver_bfm.sv|/hwetools/work_area/frontend/vineeth_b7/system/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../../../verification_ip/interface_packages/axi_m_pkg/src/axi_m_monitor_bfm.sv|/hwetools/work_area/frontend/vineeth_b7/system/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../../../verification_ip/interface_packages/axi_m_pkg/src/axi_m_if.sv| +Z49 !s90 -sv|-suppress|2223|-suppress|2286|+define+UVM_REPORT_DISABLE_FILE_LINE|+define+UVM_REPORT_DISABLE_FILE_LINE|+incdir+/hwetools/work_area/frontend/vineeth_b7/system/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../../../verification_ip/interface_packages/axi_m_pkg|-F|/hwetools/work_area/frontend/vineeth_b7/system/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../../../verification_ip/interface_packages/axi_m_pkg/axi_m_filelist_xrtl.f| +>>>>>>> ceab28f188594b972dededef57152e3a46196cbf +!i113 0 +R29 +Z50 !s92 -suppress 2223 -suppress 2286 -sv +define+UVM_REPORT_DISABLE_FILE_LINE +define+UVM_REPORT_DISABLE_FILE_LINE +incdir+/hwetools/work_area/frontend/vineeth_b7/system/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../../../verification_ip/interface_packages/axi_m_pkg -L mtiAvm -L mtiRnm -L mtiOvm -L mtiUvm -L mtiUPF -L infact +R31 +Xaxi_m_driver_bfm_sv_unit +R1 +R2 +R43 +<<<<<<< HEAD +VSe0II?LAVonPB>>>>>> ceab28f188594b972dededef57152e3a46196cbf +r1 +!s85 0 +31 +!i10b 1 +!s100 ]bccNSdo][n3LZ]m[[Q8P0 +<<<<<<< HEAD +ISe0II?LAVonPB>>>>>> ceab28f188594b972dededef57152e3a46196cbf +!i103 1 +S1 +R8 +R9 +R45 +R46 +Z51 F/hwetools/work_area/frontend/vineeth_b7/system/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../../../verification_ip/interface_packages/axi_m_pkg/src/axi_m_macros.svh +R33 +R25 +R47 +R48 +R49 +!i113 0 +R29 +R50 +R31 +Yaxi_m_if +R1 +R2 +R43 +<<<<<<< HEAD +DXx4 work 16 axi_m_if_sv_unit 0 22 8DdHX332^bbaJ67j06dd72 +======= +DXx4 work 16 axi_m_if_sv_unit 0 22 P_a;;a44B:?W3?j1j;ckX3 +>>>>>>> ceab28f188594b972dededef57152e3a46196cbf +R7 +r1 +!s85 0 +31 +!i10b 1 +!s100 fF61RZX]SD:LLRP0cHHO^3 +I0EU6SFA5ZG^0FG8M;WoL31 +!s105 axi_m_if_sv_unit +S1 +<<<<<<< HEAD +R0 +Z53 w1672041443 +Z54 8/hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../../../verification_ip/interface_packages/axi_m_pkg/src/axi_m_if.sv +Z55 F/hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../../../verification_ip/interface_packages/axi_m_pkg/src/axi_m_if.sv +======= +R8 +R9 +Z52 8/hwetools/work_area/frontend/vineeth_b7/system/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../../../verification_ip/interface_packages/axi_m_pkg/src/axi_m_if.sv +Z53 F/hwetools/work_area/frontend/vineeth_b7/system/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../../../verification_ip/interface_packages/axi_m_pkg/src/axi_m_if.sv +>>>>>>> ceab28f188594b972dededef57152e3a46196cbf +L0 71 +R25 +R47 +R48 +R49 +!i113 0 +R29 +R50 +R31 +Xaxi_m_if_sv_unit +R1 +R2 +R43 +<<<<<<< HEAD +V8DdHX332^bbaJ67j06dd72 +======= +VP_a;;a44B:?W3?j1j;ckX3 +>>>>>>> ceab28f188594b972dededef57152e3a46196cbf +r1 +!s85 0 +31 +!i10b 1 +!s100 jfmMFz6c>L0n=n>[lm>>>>>> ceab28f188594b972dededef57152e3a46196cbf +!i103 1 +S1 +R8 +R9 +R52 +R53 +L0 68 +R25 +R47 +R48 +R49 +!i113 0 +R29 +R50 +R31 +Yaxi_m_monitor_bfm +R1 +R2 +R43 +<<<<<<< HEAD +DXx4 work 25 axi_m_monitor_bfm_sv_unit 0 22 mGae>2k74N:f?<7D995M]2 +======= +DXx4 work 25 axi_m_monitor_bfm_sv_unit 0 22 bUG>S9Wo8PQK3[P]:?>WJ1 +>>>>>>> ceab28f188594b972dededef57152e3a46196cbf +R4 +R5 +R44 +R7 +r1 +!s85 0 +31 +!i10b 1 +!s100 7[;DY^JkESW1fU?4HA?Zh0 +<<<<<<< HEAD +IP[3K:nFgVCm?PN526]ObH0 +======= +I@k`AgLKB@FZA8:>h2T5DN0 +>>>>>>> ceab28f188594b972dededef57152e3a46196cbf +!s105 axi_m_monitor_bfm_sv_unit +S1 +R8 +R9 +Z54 8/hwetools/work_area/frontend/vineeth_b7/system/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../../../verification_ip/interface_packages/axi_m_pkg/src/axi_m_monitor_bfm.sv +Z55 F/hwetools/work_area/frontend/vineeth_b7/system/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../../../verification_ip/interface_packages/axi_m_pkg/src/axi_m_monitor_bfm.sv +R12 +R13 +R14 +R15 +R16 +R17 +R18 +R19 +R20 +R21 +R22 +R23 +R36 +R25 +R47 +R48 +R49 +!i113 0 +R29 +R50 +R31 +Xaxi_m_monitor_bfm_sv_unit +R1 +R2 +R43 +<<<<<<< HEAD +VmGae>2k74N:f?<7D995M]2 +======= +VbUG>S9Wo8PQK3[P]:?>WJ1 +>>>>>>> ceab28f188594b972dededef57152e3a46196cbf +r1 +!s85 0 +31 +!i10b 1 +!s100 oHU@Hodho:f=XeYN[7D]k1 +<<<<<<< HEAD +ImGae>2k74N:f?<7D995M]2 +======= +IbUG>S9Wo8PQK3[P]:?>WJ1 +>>>>>>> ceab28f188594b972dededef57152e3a46196cbf +!i103 1 +S1 +R8 +R9 +R54 +R55 +R51 +R39 +R25 +R47 +R48 +R49 +!i113 0 +R29 +R50 +R31 +Xaxi_m_pkg +!s115 axi_m_monitor_bfm +!s115 axi_m_driver_bfm +R1 +R4 +R2 +R5 +R43 +<<<<<<< HEAD +Z58 !s110 1672041469 +!i10b 1 +!s100 @VCjMH7`lzT5V]]dgTcIL0 +IR:bozX_AjW2QNCb6YZDPg0 +VR:bozX_AjW2QNCb6YZDPg0 +======= +!s110 1672027884 +!i10b 1 +!s100 @VCjMH7`lzT5V]]dgTcIL0 +IWfkETX_K@CK>iEzYWUH9c3 +VWfkETX_K@CK>iEzYWUH9c3 +>>>>>>> ceab28f188594b972dededef57152e3a46196cbf +S1 +R8 +R9 +8/hwetools/work_area/frontend/vineeth_b7/system/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../../../verification_ip/interface_packages/axi_m_pkg/axi_m_pkg.sv +F/hwetools/work_area/frontend/vineeth_b7/system/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../../../verification_ip/interface_packages/axi_m_pkg/axi_m_pkg.sv +R12 +R13 +R14 +R15 +R16 +R17 +R18 +R19 +R20 +R21 +R22 +R23 +R51 +F/hwetools/work_area/frontend/vineeth_b7/system/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../../../verification_ip/interface_packages/axi_m_pkg/src/axi_m_typedefs.svh +F/hwetools/work_area/frontend/vineeth_b7/system/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../../../verification_ip/interface_packages/axi_m_pkg/src/axi_m_transaction.svh +F/hwetools/work_area/frontend/vineeth_b7/system/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../../../verification_ip/interface_packages/axi_m_pkg/src/axi_m_configuration.svh +F/hwetools/work_area/frontend/vineeth_b7/system/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../../../verification_ip/interface_packages/axi_m_pkg/src/axi_m_driver.svh +F/hwetools/work_area/frontend/vineeth_b7/system/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../../../verification_ip/interface_packages/axi_m_pkg/src/axi_m_monitor.svh +F/hwetools/work_area/frontend/vineeth_b7/system/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../../../verification_ip/interface_packages/axi_m_pkg/src/axi_m_transaction_coverage.svh +F/hwetools/work_area/frontend/vineeth_b7/system/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../../../verification_ip/interface_packages/axi_m_pkg/src/axi_m_sequence_base.svh +F/hwetools/work_area/frontend/vineeth_b7/system/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../../../verification_ip/interface_packages/axi_m_pkg/src/axi_m_random_sequence.svh +F/hwetools/work_area/frontend/vineeth_b7/system/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../../../verification_ip/interface_packages/axi_m_pkg/src/axi_m_responder_sequence.svh +F/hwetools/work_area/frontend/vineeth_b7/system/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../../../verification_ip/interface_packages/axi_m_pkg/src/axi_m2reg_adapter.svh +F/hwetools/work_area/frontend/vineeth_b7/system/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../../../verification_ip/interface_packages/axi_m_pkg/src/axi_m_agent.svh +R39 +R25 +r1 +!s85 0 +31 +Z56 !s108 1672027883.000000 +!s107 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-sv|-suppress|2223|-suppress|2286|+define+UVM_REPORT_DISABLE_FILE_LINE|+define+UVM_REPORT_DISABLE_FILE_LINE|+incdir+/hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../../../verification_ip/interface_packages/axi_m_pkg|-F|/hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../../../verification_ip/interface_packages/axi_m_pkg/axi_m_filelist_hdl.f| +======= +!s110 1672027883 +!i10b 1 +!s100 R851jU4Uf>HL2h95OhL1h0 +IMF4H8Y5d]GYGRhmEZ2 +VMF4H8Y5d]GYGRhmEZ2 +S1 +R8 +R9 +8/hwetools/work_area/frontend/vineeth_b7/system/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../../../verification_ip/interface_packages/axi_m_pkg/axi_m_pkg_hdl.sv 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-sv|-suppress|2223|-suppress|2286|+define+UVM_REPORT_DISABLE_FILE_LINE|+define+UVM_REPORT_DISABLE_FILE_LINE|+incdir+/hwetools/work_area/frontend/vineeth_b7/system/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../../../verification_ip/interface_packages/axi_m_pkg|-F|/hwetools/work_area/frontend/vineeth_b7/system/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../../../verification_ip/interface_packages/axi_m_pkg/axi_m_filelist_hdl.f| +>>>>>>> ceab28f188594b972dededef57152e3a46196cbf +!i113 0 +R29 +R50 +R31 +Xblock_1_env_pkg +R1 +R4 +R2 +R5 +R3 +R6 +R43 +R44 +<<<<<<< HEAD +Z59 DXx4 work 13 spi_s_pkg_hdl 0 22 XaEAFYT7hd4>Qb83PJ?`=3 +Z60 DXx4 work 9 spi_s_pkg 0 22 Q0IVY:L17N<[HQK3 +VB8o9;L=BoLgJ>17N<[HQK3 +S1 +R0 +Z61 w1672041447 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+F/hwetools/work_area/frontend/vineeth_b7/system/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../../../verification_ip/environment_packages/block_1_env_pkg/src/block_1_env_configuration.svh +F/hwetools/work_area/frontend/vineeth_b7/system/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../../../verification_ip/environment_packages/block_1_env_pkg/src/block_1_predictor.svh +F/hwetools/work_area/frontend/vineeth_b7/system/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../../../verification_ip/environment_packages/block_1_env_pkg/src/block_1_scoreboard.svh +F/hwetools/work_area/frontend/vineeth_b7/system/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../../../verification_ip/environment_packages/block_1_env_pkg/src/block_1_environment.svh +F/hwetools/work_area/frontend/vineeth_b7/system/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../../../verification_ip/environment_packages/block_1_env_pkg/src/block_1_env_sequence_base.svh +Z59 L0 22 +R25 +r1 +!s85 0 +31 +!s108 1672027891.000000 +!s107 /hwetools/work_area/frontend/vineeth_b7/system/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../../../verification_ip/environment_packages/block_1_env_pkg/src/block_1_env_sequence_base.svh|/hwetools/work_area/frontend/vineeth_b7/system/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../../../verification_ip/environment_packages/block_1_env_pkg/src/block_1_environment.svh|/hwetools/work_area/frontend/vineeth_b7/system/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../../../verification_ip/environment_packages/block_1_env_pkg/src/block_1_scoreboard.svh|/hwetools/work_area/frontend/vineeth_b7/system/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../../../verification_ip/environment_packages/block_1_env_pkg/src/block_1_predictor.svh|/hwetools/work_area/frontend/vineeth_b7/system/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../../../verification_ip/environment_packages/block_1_env_pkg/src/block_1_env_configuration.svh|/hwetools/work_area/frontend/vineeth_b7/system/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../../../verification_ip/environment_packages/block_1_env_pkg/src/block_1_env_typedefs.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/macros/uvm_deprecated_defines.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/macros/uvm_reg_defines.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/macros/uvm_callback_defines.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/macros/uvm_sequence_defines.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/tlm1/uvm_tlm_imps.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/macros/uvm_tlm_defines.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/macros/uvm_printer_defines.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/macros/uvm_object_defines.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/macros/uvm_phase_defines.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/macros/uvm_message_defines.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/macros/uvm_version_defines.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/uvm_macros.svh|/hwetools/work_area/frontend/vineeth_b7/system/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../../../verification_ip/environment_packages/block_1_env_pkg/block_1_env_pkg.sv| +!s90 -sv|-suppress|2223|-suppress|2286|+define+UVM_REPORT_DISABLE_FILE_LINE|+define+UVM_REPORT_DISABLE_FILE_LINE|+incdir+/hwetools/work_area/frontend/vineeth_b7/system/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../../../verification_ip/environment_packages/block_1_env_pkg|/hwetools/work_area/frontend/vineeth_b7/system/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../../../verification_ip/environment_packages/block_1_env_pkg/block_1_env_pkg.sv| +>>>>>>> ceab28f188594b972dededef57152e3a46196cbf +!i113 0 +R29 +!s92 -suppress 2223 -suppress 2286 -sv +define+UVM_REPORT_DISABLE_FILE_LINE +define+UVM_REPORT_DISABLE_FILE_LINE +incdir+/hwetools/work_area/frontend/vineeth_b7/system/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../../../verification_ip/environment_packages/block_1_env_pkg -L mtiAvm -L mtiRnm -L mtiOvm -L mtiUvm -L mtiUPF -L infact +R31 +Xblock_2_env_pkg +R1 +R4 +R2 +R5 +<<<<<<< HEAD +Z63 DXx4 work 13 spi_m_pkg_hdl 0 22 Ym3]FmQA0Q[QQUabY:5R50 +Z64 DXx4 work 9 spi_m_pkg 0 22 I9<[lE1CTn8I9AjUJ;E_Y0 +Z65 DXx4 work 12 wb_s_pkg_hdl 0 22 hCGlXL0=8VkVV8Lzn3hPz0 +Z66 DXx4 work 8 wb_s_pkg 0 22 :J_9lFL]FoGVi5:lShdjn0 +!s110 1672041478 +!i10b 1 +!s100 EoDe4JW]`?]WN6hH7z[DO0 +IQ[?QfR8lN=1Q=I1aAezaI3 +VQ[?QfR8lN=1Q=I1aAezaI3 +S1 +R0 +R61 +8/hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../../../verification_ip/environment_packages/block_2_env_pkg/block_2_env_pkg.sv +F/hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../../../verification_ip/environment_packages/block_2_env_pkg/block_2_env_pkg.sv +R11 +======= +Z60 DXx4 work 13 spi_m_pkg_hdl 0 22 ha;;gQT;AN_CdZ[:g1 +Z62 DXx4 work 12 wb_s_pkg_hdl 0 22 L[62inFI6ZK2d1ndHLnBJ2 +Z63 DXx4 work 8 wb_s_pkg 0 22 IJWOTS7o8dWXB^ZJOzgE?0 +Z64 !s110 1672027893 +!i10b 1 +!s100 EoDe4JW]`?]WN6hH7z[DO0 +I8LDk:n?dkT`WT;F3;^HmG2 +V8LDk:n?dkT`WT;F3;^HmG2 +S1 +R8 +R9 +8/hwetools/work_area/frontend/vineeth_b7/system/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../../../verification_ip/environment_packages/block_2_env_pkg/block_2_env_pkg.sv +F/hwetools/work_area/frontend/vineeth_b7/system/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../../../verification_ip/environment_packages/block_2_env_pkg/block_2_env_pkg.sv +>>>>>>> ceab28f188594b972dededef57152e3a46196cbf +R12 +R13 +R14 +R15 +R16 +R17 +R18 +R19 +R20 +R21 +R22 +<<<<<<< HEAD +F/hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../../../verification_ip/environment_packages/block_2_env_pkg/src/block_2_env_typedefs.svh +F/hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../../../verification_ip/environment_packages/block_2_env_pkg/src/block_2_env_configuration.svh +F/hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../../../verification_ip/environment_packages/block_2_env_pkg/src/block_2_predictor.svh +F/hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../../../verification_ip/environment_packages/block_2_env_pkg/src/block_2_scoreboard.svh +F/hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../../../verification_ip/environment_packages/block_2_env_pkg/src/block_2_environment.svh +F/hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../../../verification_ip/environment_packages/block_2_env_pkg/src/block_2_env_sequence_base.svh +R62 +R24 +r1 +!s85 0 +31 +Z67 !s108 1672041478.000000 +!s107 /hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../../../verification_ip/environment_packages/block_2_env_pkg/src/block_2_env_sequence_base.svh|/hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../../../verification_ip/environment_packages/block_2_env_pkg/src/block_2_environment.svh|/hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../../../verification_ip/environment_packages/block_2_env_pkg/src/block_2_scoreboard.svh|/hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../../../verification_ip/environment_packages/block_2_env_pkg/src/block_2_predictor.svh|/hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../../../verification_ip/environment_packages/block_2_env_pkg/src/block_2_env_configuration.svh|/hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../../../verification_ip/environment_packages/block_2_env_pkg/src/block_2_env_typedefs.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/macros/uvm_deprecated_defines.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/macros/uvm_reg_defines.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/macros/uvm_callback_defines.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/macros/uvm_sequence_defines.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/tlm1/uvm_tlm_imps.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/macros/uvm_tlm_defines.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/macros/uvm_printer_defines.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/macros/uvm_object_defines.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/macros/uvm_phase_defines.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/macros/uvm_message_defines.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/macros/uvm_version_defines.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/uvm_macros.svh|/hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../../../verification_ip/environment_packages/block_2_env_pkg/block_2_env_pkg.sv| +!s90 -sv|-suppress|2223|-suppress|2286|+define+UVM_REPORT_DISABLE_FILE_LINE|+define+UVM_REPORT_DISABLE_FILE_LINE|+incdir+/hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../../../verification_ip/environment_packages/block_2_env_pkg|/hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../../../verification_ip/environment_packages/block_2_env_pkg/block_2_env_pkg.sv| +======= +R23 +F/hwetools/work_area/frontend/vineeth_b7/system/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../../../verification_ip/environment_packages/block_2_env_pkg/src/block_2_env_typedefs.svh +F/hwetools/work_area/frontend/vineeth_b7/system/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../../../verification_ip/environment_packages/block_2_env_pkg/src/block_2_env_configuration.svh +F/hwetools/work_area/frontend/vineeth_b7/system/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../../../verification_ip/environment_packages/block_2_env_pkg/src/block_2_predictor.svh +F/hwetools/work_area/frontend/vineeth_b7/system/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../../../verification_ip/environment_packages/block_2_env_pkg/src/block_2_scoreboard.svh +F/hwetools/work_area/frontend/vineeth_b7/system/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../../../verification_ip/environment_packages/block_2_env_pkg/src/block_2_environment.svh +F/hwetools/work_area/frontend/vineeth_b7/system/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../../../verification_ip/environment_packages/block_2_env_pkg/src/block_2_env_sequence_base.svh +R59 +R25 +r1 +!s85 0 +31 +!s108 1672027892.000000 +!s107 /hwetools/work_area/frontend/vineeth_b7/system/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../../../verification_ip/environment_packages/block_2_env_pkg/src/block_2_env_sequence_base.svh|/hwetools/work_area/frontend/vineeth_b7/system/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../../../verification_ip/environment_packages/block_2_env_pkg/src/block_2_environment.svh|/hwetools/work_area/frontend/vineeth_b7/system/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../../../verification_ip/environment_packages/block_2_env_pkg/src/block_2_scoreboard.svh|/hwetools/work_area/frontend/vineeth_b7/system/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../../../verification_ip/environment_packages/block_2_env_pkg/src/block_2_predictor.svh|/hwetools/work_area/frontend/vineeth_b7/system/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../../../verification_ip/environment_packages/block_2_env_pkg/src/block_2_env_configuration.svh|/hwetools/work_area/frontend/vineeth_b7/system/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../../../verification_ip/environment_packages/block_2_env_pkg/src/block_2_env_typedefs.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/macros/uvm_deprecated_defines.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/macros/uvm_reg_defines.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/macros/uvm_callback_defines.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/macros/uvm_sequence_defines.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/tlm1/uvm_tlm_imps.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/macros/uvm_tlm_defines.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/macros/uvm_printer_defines.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/macros/uvm_object_defines.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/macros/uvm_phase_defines.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/macros/uvm_message_defines.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/macros/uvm_version_defines.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/uvm_macros.svh|/hwetools/work_area/frontend/vineeth_b7/system/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../../../verification_ip/environment_packages/block_2_env_pkg/block_2_env_pkg.sv| +!s90 -sv|-suppress|2223|-suppress|2286|+define+UVM_REPORT_DISABLE_FILE_LINE|+define+UVM_REPORT_DISABLE_FILE_LINE|+incdir+/hwetools/work_area/frontend/vineeth_b7/system/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../../../verification_ip/environment_packages/block_2_env_pkg|/hwetools/work_area/frontend/vineeth_b7/system/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../../../verification_ip/environment_packages/block_2_env_pkg/block_2_env_pkg.sv| +>>>>>>> ceab28f188594b972dededef57152e3a46196cbf +!i113 0 +R29 +!s92 -suppress 2223 -suppress 2286 -sv +define+UVM_REPORT_DISABLE_FILE_LINE +define+UVM_REPORT_DISABLE_FILE_LINE +incdir+/hwetools/work_area/frontend/vineeth_b7/system/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../../../verification_ip/environment_packages/block_2_env_pkg -L mtiAvm -L mtiRnm -L mtiOvm -L mtiUvm -L mtiUPF -L infact +R31 +vhdl_top +R1 +<<<<<<< HEAD +R2 +Z68 DXx4 work 21 subsys_parameters_pkg 0 22 [SPYk8SIoFM1Z6f_7WDSj0 +R4 +Z69 !s110 1672041481 +======= +Z65 DXx4 work 17 uvmf_base_pkg_hdl 0 22 m5olA;]f6dO?R^UD2 +Z66 DXx4 work 21 subsys_parameters_pkg 0 22 0<3O`@6THT^AdIDzUGB9J3 +R4 +Z67 !s110 1672006422 +>>>>>>> ceab28f188594b972dededef57152e3a46196cbf +!i10b 1 +!s100 @Fgl?eDHd0kZ@jz?NF`ih3 +IR6A2`C5WPX>U@QJ7SNmHV1 +R7 +!s105 hdl_top_sv_unit +S1 +R0 +<<<<<<< HEAD +Z70 w1672041448 +======= +Z68 w1672006388 +>>>>>>> ceab28f188594b972dededef57152e3a46196cbf +8/hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../tb/testbench/hdl_top.sv +F/hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../tb/testbench/hdl_top.sv +L0 24 +R25 +r1 +!s85 0 +31 +!s108 1672041481.000000 +!s107 /hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../tb/testbench/hdl_top.sv| +!s90 -sv|-suppress|2223|-suppress|2286|+define+UVM_REPORT_DISABLE_FILE_LINE|+define+UVM_REPORT_DISABLE_FILE_LINE|+incdir+/hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../tb/testbench|-F|/hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../tb/testbench/top_filelist_hdl.f| +!i113 0 +R29 +!s92 -suppress 2223 -suppress 2286 -sv +define+UVM_REPORT_DISABLE_FILE_LINE +define+UVM_REPORT_DISABLE_FILE_LINE +incdir+/hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../tb/testbench -L mtiAvm -L mtiRnm -L mtiOvm -L mtiUvm -L mtiUPF -L infact +R31 +vhvl_top +R1 +R4 +<<<<<<< HEAD +R2 +R5 +R68 +R3 +R6 +R43 +R44 +R59 +R60 +Z71 DXx4 work 15 block_1_env_pkg 0 22 B8o9;L=BoLgJ>17N<[HQK3 +R63 +R64 +======= +>>>>>>> ceab28f188594b972dededef57152e3a46196cbf +R65 +Z69 DXx4 work 13 uvmf_base_pkg 0 22 X9R9lPBnn6SV=>cPHjmcD1 +R66 +<<<<<<< HEAD +Z72 DXx4 work 15 block_2_env_pkg 0 22 Q[?QfR8lN=1Q=I1aAezaI3 +Z73 DXx4 work 14 subsys_env_pkg 0 22 N>?3mAMb@RliZ7kcch=;42 +Z74 DXx4 work 20 subsys_sequences_pkg 0 22 j:gJO;iePWW>^=66oXVk71 +DXx4 work 16 subsys_tests_pkg 0 22 c=8_40UzSQgf6L8QBAz1o3 +R69 +======= +Z70 DXx4 work 13 apb_m_pkg_hdl 0 22 DZlenKN:g2 +Z75 DXx4 work 9 spi_s_pkg 0 22 YCcZ?mNzH7`U8OY@a8kXF0 +Z76 DXx4 work 15 block_1_env_pkg 0 22 kd0Ma8KKO3gEIO5Die[EO2 +Z77 DXx4 work 13 spi_m_pkg_hdl 0 22 D2G5ohi6mlUKKHgfAK?[Z0 +Z78 DXx4 work 9 spi_m_pkg 0 22 oUNQ`J@md[D]?jNbnF3l90 +Z79 DXx4 work 12 wb_s_pkg_hdl 0 22 3[4UY>3IOF?:5RP^dHKWF3 +Z80 DXx4 work 8 wb_s_pkg 0 22 bQhYjd1J?KfS;K3hlmoSb1 +Z81 DXx4 work 15 block_2_env_pkg 0 22 k0m5z^:BBI>D2a]CN`Did1 +Z82 DXx4 work 14 subsys_env_pkg 0 22 a6CW:L2_Dj=6]>L0MI_@c2 +Z83 DXx4 work 20 subsys_sequences_pkg 0 22 mYK49GjCOOPCAmA^_[ERT3 +DXx4 work 16 subsys_tests_pkg 0 22 GNV?d7bm=?czACXf7z3=f3 +R67 +>>>>>>> ceab28f188594b972dededef57152e3a46196cbf +!i10b 1 +!s100 Jo7YVX=0RljLNXRh[^YOa3 +IP:`SHzoJkgm26NQ3DDh]H3 +R7 +!s105 hvl_top_sv_unit +S1 +R0 +<<<<<<< HEAD +R70 +8/hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../tb/testbench/hvl_top.sv +F/hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../tb/testbench/hvl_top.sv +Z75 L0 16 +R24 +======= +R68 +8/hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../tb/testbench/hvl_top.sv +F/hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../tb/testbench/hvl_top.sv +Z84 L0 16 +R25 +>>>>>>> ceab28f188594b972dededef57152e3a46196cbf +r1 +!s85 0 +31 +Z76 !s108 1672041480.000000 +!s107 /hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../tb/testbench/hvl_top.sv| +!s90 -sv|-suppress|2223|-suppress|2286|+define+UVM_REPORT_DISABLE_FILE_LINE|+define+UVM_REPORT_DISABLE_FILE_LINE|+incdir+/questa_mvc_src/sv|+incdir+/hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../tb/testbench|-F|/hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../tb/testbench/top_filelist_hvl.f| +!i113 0 +R29 +!s92 -suppress 2223 -suppress 2286 -sv +define+UVM_REPORT_DISABLE_FILE_LINE +define+UVM_REPORT_DISABLE_FILE_LINE +incdir+/questa_mvc_src/sv +incdir+/hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../tb/testbench -L mtiAvm -L mtiRnm -L mtiOvm -L mtiUvm -L mtiUPF -L infact +R31 +Toptimized_batch_top_tb +<<<<<<< HEAD +!s110 1672041482 +VSJeoz4MC2HEcm;2:Lb8ie3 +Z77 04 7 4 work hvl_top fast 0 +Z78 04 7 4 work hdl_top fast 0 +======= +!s110 1672006423 +VNK]Pm;kPDU4^5gcaa;S@c0 +Z85 04 7 4 work hvl_top fast 0 +Z86 04 7 4 work hdl_top fast 0 +>>>>>>> ceab28f188594b972dededef57152e3a46196cbf +o +R31 +noptimized_batch_top_tb +<<<<<<< HEAD +Z79 OE;O;10.6c;65 +R0 +Toptimized_debug_top_tb +!s110 1672041485 +V6GZ0>jl;LZNb6aj:[fG9P0 +R77 +R78 +======= +Z87 OE;O;10.6c;65 +R0 +Toptimized_debug_top_tb +!s110 1672006426 +ViRNgdNBeH^W_Z9Rl^AmH:1 +R85 +R86 +>>>>>>> ceab28f188594b972dededef57152e3a46196cbf +o+acc +R31 +noptimized_debug_top_tb +<<<<<<< HEAD +R79 +Yspi_m_driver_bfm +R1 +R2 +R63 +DXx4 work 24 spi_m_driver_bfm_sv_unit 0 22 liRHX?KOKOaQA[8fLSO2C1 +======= +R87 +R0 +Yspi_m_driver_bfm +R1 +R2 +R60 +DXx4 work 24 spi_m_driver_bfm_sv_unit 0 22 Bf?UFcghQNEiAg^33NfW93 +>>>>>>> ceab28f188594b972dededef57152e3a46196cbf +R4 +R5 +R61 +R7 +r1 +!s85 0 +31 +!i10b 1 +!s100 EhV6BeBCVCm^9jWBi_@ZZ2 +<<<<<<< HEAD +IP`oDk_:I]d`=>>>>>> ceab28f188594b972dededef57152e3a46196cbf +R12 +R13 +R14 +R15 +R16 +R17 +R18 +R19 +R20 +R21 +R22 +R23 +R24 +<<<<<<< HEAD +Z82 !s108 1672041473.000000 +Z83 !s107 /tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/macros/uvm_deprecated_defines.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/macros/uvm_reg_defines.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/macros/uvm_callback_defines.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/macros/uvm_sequence_defines.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/tlm1/uvm_tlm_imps.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/macros/uvm_tlm_defines.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/macros/uvm_printer_defines.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/macros/uvm_object_defines.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/macros/uvm_phase_defines.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/macros/uvm_message_defines.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/macros/uvm_version_defines.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/uvm_macros.svh|/hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../../../verification_ip/interface_packages/spi_m_pkg/src/spi_m_macros.svh|/hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../../../verification_ip/interface_packages/spi_m_pkg/src/spi_m_driver_bfm.sv|/hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../../../verification_ip/interface_packages/spi_m_pkg/src/spi_m_monitor_bfm.sv|/hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../../../verification_ip/interface_packages/spi_m_pkg/src/spi_m_if.sv| +Z84 !s90 -sv|-suppress|2223|-suppress|2286|+define+UVM_REPORT_DISABLE_FILE_LINE|+define+UVM_REPORT_DISABLE_FILE_LINE|+incdir+/hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../../../verification_ip/interface_packages/spi_m_pkg|-F|/hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../../../verification_ip/interface_packages/spi_m_pkg/spi_m_filelist_xrtl.f| +!i113 0 +R28 +Z85 !s92 -suppress 2223 -suppress 2286 -sv +define+UVM_REPORT_DISABLE_FILE_LINE +define+UVM_REPORT_DISABLE_FILE_LINE +incdir+/hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../../../verification_ip/interface_packages/spi_m_pkg -L mtiAvm -L mtiRnm -L mtiOvm -L mtiUvm -L mtiUPF -L infact +R30 +Xspi_m_driver_bfm_sv_unit +R1 +R2 +R63 +VliRHX?KOKOaQA[8fLSO2C1 +======= +R25 +Z90 !s108 1672027888.000000 +Z91 !s107 /tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/macros/uvm_deprecated_defines.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/macros/uvm_reg_defines.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/macros/uvm_callback_defines.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/macros/uvm_sequence_defines.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/tlm1/uvm_tlm_imps.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/macros/uvm_tlm_defines.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/macros/uvm_printer_defines.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/macros/uvm_object_defines.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/macros/uvm_phase_defines.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/macros/uvm_message_defines.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/macros/uvm_version_defines.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/uvm_macros.svh|/hwetools/work_area/frontend/vineeth_b7/system/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../../../verification_ip/interface_packages/spi_m_pkg/src/spi_m_macros.svh|/hwetools/work_area/frontend/vineeth_b7/system/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../../../verification_ip/interface_packages/spi_m_pkg/src/spi_m_driver_bfm.sv|/hwetools/work_area/frontend/vineeth_b7/system/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../../../verification_ip/interface_packages/spi_m_pkg/src/spi_m_monitor_bfm.sv|/hwetools/work_area/frontend/vineeth_b7/system/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../../../verification_ip/interface_packages/spi_m_pkg/src/spi_m_if.sv| +Z92 !s90 -sv|-suppress|2223|-suppress|2286|+define+UVM_REPORT_DISABLE_FILE_LINE|+define+UVM_REPORT_DISABLE_FILE_LINE|+incdir+/hwetools/work_area/frontend/vineeth_b7/system/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../../../verification_ip/interface_packages/spi_m_pkg|-F|/hwetools/work_area/frontend/vineeth_b7/system/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../../../verification_ip/interface_packages/spi_m_pkg/spi_m_filelist_xrtl.f| +!i113 0 +R29 +Z93 !s92 -suppress 2223 -suppress 2286 -sv +define+UVM_REPORT_DISABLE_FILE_LINE +define+UVM_REPORT_DISABLE_FILE_LINE +incdir+/hwetools/work_area/frontend/vineeth_b7/system/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../../../verification_ip/interface_packages/spi_m_pkg -L mtiAvm -L mtiRnm -L mtiOvm -L mtiUvm -L mtiUPF -L infact +R31 +Xspi_m_driver_bfm_sv_unit +R1 +R2 +R60 +VBf?UFcghQNEiAg^33NfW93 +>>>>>>> ceab28f188594b972dededef57152e3a46196cbf +r1 +!s85 0 +31 +!i10b 1 +!s100 om=fogKFBFb:`m3EELZGE0 +<<<<<<< HEAD +IliRHX?KOKOaQA[8fLSO2C1 +!i103 1 +S1 +R0 +R40 +R80 +R81 +Z86 F/hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../../../verification_ip/interface_packages/spi_m_pkg/src/spi_m_macros.svh +R32 +R24 +R82 +R83 +R84 +!i113 0 +R28 +R85 +R30 +Yspi_m_if +R1 +R2 +R63 +DXx4 work 16 spi_m_if_sv_unit 0 22 8VeDPX?;m]T1L^dm21>R_1 +======= +IBf?UFcghQNEiAg^33NfW93 +!i103 1 +S1 +R8 +R9 +R88 +R89 +Z94 F/hwetools/work_area/frontend/vineeth_b7/system/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../../../verification_ip/interface_packages/spi_m_pkg/src/spi_m_macros.svh +R33 +R25 +R90 +R91 +R92 +!i113 0 +R29 +R93 +R31 +Yspi_m_if +R1 +R2 +R60 +DXx4 work 16 spi_m_if_sv_unit 0 22 kR_3aC4TR=8RUhQ5[PQ9;3 +>>>>>>> ceab28f188594b972dededef57152e3a46196cbf +R7 +r1 +!s85 0 +31 +!i10b 1 +!s100 ONGKTVnNf@BHVO9lJ<35L2 +Io0OXR_1 +======= +R8 +R9 +Z95 8/hwetools/work_area/frontend/vineeth_b7/system/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../../../verification_ip/interface_packages/spi_m_pkg/src/spi_m_if.sv +Z96 F/hwetools/work_area/frontend/vineeth_b7/system/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../../../verification_ip/interface_packages/spi_m_pkg/src/spi_m_if.sv +Z97 L0 30 +R25 +R90 +R91 +R92 +!i113 0 +R29 +R93 +R31 +Xspi_m_if_sv_unit +R1 +R2 +R60 +VkR_3aC4TR=8RUhQ5[PQ9;3 +>>>>>>> ceab28f188594b972dededef57152e3a46196cbf +r1 +!s85 0 +31 +!i10b 1 +!s100 FzQ@RRdj;DGEmaClVXo>93 +<<<<<<< HEAD +I8VeDPX?;m]T1L^dm21>R_1 +!i103 1 +S1 +R0 +R40 +R87 +R88 +Z90 L0 27 +R24 +R82 +R83 +R84 +!i113 0 +R28 +R85 +R30 +Yspi_m_monitor_bfm +R1 +R2 +R63 +DXx4 work 25 spi_m_monitor_bfm_sv_unit 0 22 Ui@Yh3?L;4P5Pdz2 +======= +IkR_3aC4TR=8RUhQ5[PQ9;3 +!i103 1 +S1 +R8 +R9 +R95 +R96 +Z98 L0 27 +R25 +R90 +R91 +R92 +!i113 0 +R29 +R93 +R31 +Yspi_m_monitor_bfm +R1 +R2 +R60 +DXx4 work 25 spi_m_monitor_bfm_sv_unit 0 22 l:TM1b04jcdeiYBFUMMB^1 +>>>>>>> ceab28f188594b972dededef57152e3a46196cbf +R4 +R5 +R61 +R7 +r1 +!s85 0 +31 +!i10b 1 +!s100 XDjIL]C>?]n;oEW=3EY8P3 +<<<<<<< HEAD +I6L>SJ[dgnK[bMkGO^K6;_3 +!s105 spi_m_monitor_bfm_sv_unit +S1 +R0 +R40 +Z91 8/hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../../../verification_ip/interface_packages/spi_m_pkg/src/spi_m_monitor_bfm.sv +Z92 F/hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../../../verification_ip/interface_packages/spi_m_pkg/src/spi_m_monitor_bfm.sv +R11 +======= +IcFEmoJ?1F0b4ZRO?IdF4_3 +!s105 spi_m_monitor_bfm_sv_unit +S1 +R8 +R9 +Z99 8/hwetools/work_area/frontend/vineeth_b7/system/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../../../verification_ip/interface_packages/spi_m_pkg/src/spi_m_monitor_bfm.sv +Z100 F/hwetools/work_area/frontend/vineeth_b7/system/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../../../verification_ip/interface_packages/spi_m_pkg/src/spi_m_monitor_bfm.sv +>>>>>>> ceab28f188594b972dededef57152e3a46196cbf +R12 +R13 +R14 +R15 +R16 +R17 +R18 +R19 +R20 +R21 +R22 +<<<<<<< HEAD +R35 +R24 +R82 +R83 +R84 +!i113 0 +R28 +R85 +R30 +Xspi_m_monitor_bfm_sv_unit +R1 +R2 +R63 +VUi@Yh3?L;4P5Pdz2 +======= +R23 +R36 +R25 +R90 +R91 +R92 +!i113 0 +R29 +R93 +R31 +Xspi_m_monitor_bfm_sv_unit +R1 +R2 +R60 +Vl:TM1b04jcdeiYBFUMMB^1 +>>>>>>> ceab28f188594b972dededef57152e3a46196cbf +r1 +!s85 0 +31 +!i10b 1 +!s100 R86fbRSEA;]?B5Da5ziZ@3 +<<<<<<< HEAD +IUi@Yh3?L;4P5Pdz2 +!i103 1 +S1 +R0 +R40 +R91 +R92 +R86 +R38 +R24 +R82 +R83 +R84 +!i113 0 +R28 +R85 +R30 +======= +Il:TM1b04jcdeiYBFUMMB^1 +!i103 1 +S1 +R8 +R9 +R99 +R100 +R94 +R39 +R25 +R90 +R91 +R92 +!i113 0 +R29 +R93 +R31 +>>>>>>> ceab28f188594b972dededef57152e3a46196cbf +Xspi_m_pkg +!s115 spi_m_monitor_bfm +!s115 spi_m_driver_bfm +R1 +R4 +R2 +R5 +<<<<<<< HEAD +R63 +Z93 !s110 1672041473 +!i10b 1 +!s100 3SV5fSZh6m@WVmX:nGE1E1 +II9<[lE1CTn8I9AjUJ;E_Y0 +VI9<[lE1CTn8I9AjUJ;E_Y0 +S1 +R0 +Z94 w1672041441 +8/hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../../../verification_ip/interface_packages/spi_m_pkg/spi_m_pkg.sv +F/hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../../../verification_ip/interface_packages/spi_m_pkg/spi_m_pkg.sv +R11 +======= +R60 +!s110 1672027888 +!i10b 1 +!s100 3SV5fSZh6m@WVmX:nGE1E1 +IEiYJ`@cXCdZ[:g1 +VEiYJ`@cXCdZ[:g1 +S1 +R8 +Z101 w1671991596 +8/hwetools/work_area/frontend/vineeth_b7/system/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../../../verification_ip/interface_packages/spi_m_pkg/spi_m_pkg.sv +F/hwetools/work_area/frontend/vineeth_b7/system/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../../../verification_ip/interface_packages/spi_m_pkg/spi_m_pkg.sv +>>>>>>> ceab28f188594b972dededef57152e3a46196cbf +R12 +R13 +R14 +R15 +R16 +R17 +R18 +R19 +R20 +R21 +R22 +<<<<<<< HEAD +R86 +F/hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../../../verification_ip/interface_packages/spi_m_pkg/src/spi_m_typedefs.svh +F/hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../../../verification_ip/interface_packages/spi_m_pkg/src/spi_m_transaction.svh +F/hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../../../verification_ip/interface_packages/spi_m_pkg/src/spi_m_configuration.svh +F/hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../../../verification_ip/interface_packages/spi_m_pkg/src/spi_m_driver.svh +F/hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../../../verification_ip/interface_packages/spi_m_pkg/src/spi_m_monitor.svh +F/hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../../../verification_ip/interface_packages/spi_m_pkg/src/spi_m_transaction_coverage.svh +F/hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../../../verification_ip/interface_packages/spi_m_pkg/src/spi_m_sequence_base.svh +F/hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../../../verification_ip/interface_packages/spi_m_pkg/src/spi_m_random_sequence.svh +F/hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../../../verification_ip/interface_packages/spi_m_pkg/src/spi_m_responder_sequence.svh +F/hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../../../verification_ip/interface_packages/spi_m_pkg/src/spi_m2reg_adapter.svh +F/hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../../../verification_ip/interface_packages/spi_m_pkg/src/spi_m_agent.svh +R38 +R24 +r1 +!s85 0 +31 +R82 +!s107 /hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../../../verification_ip/interface_packages/spi_m_pkg/src/spi_m_agent.svh|/hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../../../verification_ip/interface_packages/spi_m_pkg/src/spi_m2reg_adapter.svh|/hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../../../verification_ip/interface_packages/spi_m_pkg/src/spi_m_responder_sequence.svh|/hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../../../verification_ip/interface_packages/spi_m_pkg/src/spi_m_random_sequence.svh|/hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../../../verification_ip/interface_packages/spi_m_pkg/src/spi_m_sequence_base.svh|/hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../../../verification_ip/interface_packages/spi_m_pkg/src/spi_m_transaction_coverage.svh|/hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../../../verification_ip/interface_packages/spi_m_pkg/src/spi_m_monitor.svh|/hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../../../verification_ip/interface_packages/spi_m_pkg/src/spi_m_driver.svh|/hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../../../verification_ip/interface_packages/spi_m_pkg/src/spi_m_configuration.svh|/hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../../../verification_ip/interface_packages/spi_m_pkg/src/spi_m_transaction.svh|/hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../../../verification_ip/interface_packages/spi_m_pkg/src/spi_m_typedefs.svh|/hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../../../verification_ip/interface_packages/spi_m_pkg/src/spi_m_macros.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/macros/uvm_deprecated_defines.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/macros/uvm_reg_defines.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/macros/uvm_callback_defines.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/macros/uvm_sequence_defines.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/tlm1/uvm_tlm_imps.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/macros/uvm_tlm_defines.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/macros/uvm_printer_defines.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/macros/uvm_object_defines.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/macros/uvm_phase_defines.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/macros/uvm_message_defines.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/macros/uvm_version_defines.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/uvm_macros.svh|/hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../../../verification_ip/interface_packages/spi_m_pkg/spi_m_pkg.sv| +!s90 -sv|-suppress|2223|-suppress|2286|+define+UVM_REPORT_DISABLE_FILE_LINE|+define+UVM_REPORT_DISABLE_FILE_LINE|+incdir+/hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../../../verification_ip/interface_packages/spi_m_pkg|-F|/hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../../../verification_ip/interface_packages/spi_m_pkg/spi_m_filelist_hvl.f| +!i113 0 +R28 +R85 +R30 +Xspi_m_pkg_hdl +R1 +R2 +R93 +!i10b 1 +!s100 [LeaZI[OU:Ai@clz9aM:K2 +IYm3]FmQA0Q[QQUabY:5R50 +VYm3]FmQA0Q[QQUabY:5R50 +S1 +R0 +R94 +8/hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../../../verification_ip/interface_packages/spi_m_pkg/spi_m_pkg_hdl.sv +F/hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../../../verification_ip/interface_packages/spi_m_pkg/spi_m_pkg_hdl.sv +F/hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../../../verification_ip/interface_packages/spi_m_pkg/src/spi_m_typedefs_hdl.svh +R86 +R41 +R24 +r1 +!s85 0 +31 +R82 +!s107 /hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../../../verification_ip/interface_packages/spi_m_pkg/src/spi_m_macros.svh|/hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../../../verification_ip/interface_packages/spi_m_pkg/src/spi_m_typedefs_hdl.svh|/hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../../../verification_ip/interface_packages/spi_m_pkg/spi_m_pkg_hdl.sv| +!s90 -sv|-suppress|2223|-suppress|2286|+define+UVM_REPORT_DISABLE_FILE_LINE|+define+UVM_REPORT_DISABLE_FILE_LINE|+incdir+/hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../../../verification_ip/interface_packages/spi_m_pkg|-F|/hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../../../verification_ip/interface_packages/spi_m_pkg/spi_m_filelist_hdl.f| +!i113 0 +R28 +R85 +R30 +Yspi_s_driver_bfm +R1 +R2 +R59 +DXx4 work 24 spi_s_driver_bfm_sv_unit 0 22 :C4BPYUnJM=JnSE>U5LTQ2 +R4 +R5 +R60 +======= +R23 +R94 +F/hwetools/work_area/frontend/vineeth_b7/system/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../../../verification_ip/interface_packages/spi_m_pkg/src/spi_m_typedefs.svh +F/hwetools/work_area/frontend/vineeth_b7/system/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../../../verification_ip/interface_packages/spi_m_pkg/src/spi_m_transaction.svh +F/hwetools/work_area/frontend/vineeth_b7/system/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../../../verification_ip/interface_packages/spi_m_pkg/src/spi_m_configuration.svh +F/hwetools/work_area/frontend/vineeth_b7/system/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../../../verification_ip/interface_packages/spi_m_pkg/src/spi_m_driver.svh +F/hwetools/work_area/frontend/vineeth_b7/system/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../../../verification_ip/interface_packages/spi_m_pkg/src/spi_m_monitor.svh +F/hwetools/work_area/frontend/vineeth_b7/system/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../../../verification_ip/interface_packages/spi_m_pkg/src/spi_m_transaction_coverage.svh +F/hwetools/work_area/frontend/vineeth_b7/system/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../../../verification_ip/interface_packages/spi_m_pkg/src/spi_m_sequence_base.svh +F/hwetools/work_area/frontend/vineeth_b7/system/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../../../verification_ip/interface_packages/spi_m_pkg/src/spi_m_random_sequence.svh +F/hwetools/work_area/frontend/vineeth_b7/system/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../../../verification_ip/interface_packages/spi_m_pkg/src/spi_m_responder_sequence.svh +F/hwetools/work_area/frontend/vineeth_b7/system/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../../../verification_ip/interface_packages/spi_m_pkg/src/spi_m2reg_adapter.svh +F/hwetools/work_area/frontend/vineeth_b7/system/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../../../verification_ip/interface_packages/spi_m_pkg/src/spi_m_agent.svh +R39 +R25 +r1 +!s85 0 +31 +Z102 !s108 1672027887.000000 +!s107 /hwetools/work_area/frontend/vineeth_b7/system/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../../../verification_ip/interface_packages/spi_m_pkg/src/spi_m_agent.svh|/hwetools/work_area/frontend/vineeth_b7/system/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../../../verification_ip/interface_packages/spi_m_pkg/src/spi_m2reg_adapter.svh|/hwetools/work_area/frontend/vineeth_b7/system/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../../../verification_ip/interface_packages/spi_m_pkg/src/spi_m_responder_sequence.svh|/hwetools/work_area/frontend/vineeth_b7/system/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../../../verification_ip/interface_packages/spi_m_pkg/src/spi_m_random_sequence.svh|/hwetools/work_area/frontend/vineeth_b7/system/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../../../verification_ip/interface_packages/spi_m_pkg/src/spi_m_sequence_base.svh|/hwetools/work_area/frontend/vineeth_b7/system/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../../../verification_ip/interface_packages/spi_m_pkg/src/spi_m_transaction_coverage.svh|/hwetools/work_area/frontend/vineeth_b7/system/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../../../verification_ip/interface_packages/spi_m_pkg/src/spi_m_monitor.svh|/hwetools/work_area/frontend/vineeth_b7/system/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../../../verification_ip/interface_packages/spi_m_pkg/src/spi_m_driver.svh|/hwetools/work_area/frontend/vineeth_b7/system/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../../../verification_ip/interface_packages/spi_m_pkg/src/spi_m_configuration.svh|/hwetools/work_area/frontend/vineeth_b7/system/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../../../verification_ip/interface_packages/spi_m_pkg/src/spi_m_transaction.svh|/hwetools/work_area/frontend/vineeth_b7/system/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../../../verification_ip/interface_packages/spi_m_pkg/src/spi_m_typedefs.svh|/hwetools/work_area/frontend/vineeth_b7/system/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../../../verification_ip/interface_packages/spi_m_pkg/src/spi_m_macros.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/macros/uvm_deprecated_defines.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/macros/uvm_reg_defines.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/macros/uvm_callback_defines.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/macros/uvm_sequence_defines.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/tlm1/uvm_tlm_imps.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/macros/uvm_tlm_defines.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/macros/uvm_printer_defines.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/macros/uvm_object_defines.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/macros/uvm_phase_defines.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/macros/uvm_message_defines.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/macros/uvm_version_defines.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/uvm_macros.svh|/hwetools/work_area/frontend/vineeth_b7/system/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../../../verification_ip/interface_packages/spi_m_pkg/spi_m_pkg.sv| +!s90 -sv|-suppress|2223|-suppress|2286|+define+UVM_REPORT_DISABLE_FILE_LINE|+define+UVM_REPORT_DISABLE_FILE_LINE|+incdir+/hwetools/work_area/frontend/vineeth_b7/system/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../../../verification_ip/interface_packages/spi_m_pkg|-F|/hwetools/work_area/frontend/vineeth_b7/system/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../../../verification_ip/interface_packages/spi_m_pkg/spi_m_filelist_hvl.f| +!i113 0 +R29 +R93 +R31 +Xspi_m_pkg_hdl +R1 +R2 +!s110 1672027887 +!i10b 1 +!s100 [LeaZI[OU:Ai@clz9aM:K2 +Iha;;gQT;AN_>>>>>> ceab28f188594b972dededef57152e3a46196cbf +R7 +r1 +!s85 0 +31 +!i10b 1 +!s100 mC@L2T:jkCUPQFIIJ9]i93 +<<<<<<< HEAD +IiBKaeLW_Jm[SngM32NOAb1 +!s105 spi_s_driver_bfm_sv_unit +S1 +R0 +Z95 w1672041445 +Z96 8/hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../../../verification_ip/interface_packages/spi_s_pkg/src/spi_s_driver_bfm.sv +Z97 F/hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../../../verification_ip/interface_packages/spi_s_pkg/src/spi_s_driver_bfm.sv +R11 +======= +IWMSgKhNiPkQkYCQWB9H[=0 +!s105 spi_s_driver_bfm_sv_unit +S1 +R8 +R9 +Z103 8/hwetools/work_area/frontend/vineeth_b7/system/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../../../verification_ip/interface_packages/spi_s_pkg/src/spi_s_driver_bfm.sv +Z104 F/hwetools/work_area/frontend/vineeth_b7/system/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../../../verification_ip/interface_packages/spi_s_pkg/src/spi_s_driver_bfm.sv +>>>>>>> ceab28f188594b972dededef57152e3a46196cbf +R12 +R13 +R14 +R15 +R16 +R17 +R18 +R19 +R20 +R21 +R22 +R23 +R24 +<<<<<<< HEAD +Z98 !s108 1672041471.000000 +Z99 !s107 /tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/macros/uvm_deprecated_defines.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/macros/uvm_reg_defines.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/macros/uvm_callback_defines.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/macros/uvm_sequence_defines.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/tlm1/uvm_tlm_imps.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/macros/uvm_tlm_defines.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/macros/uvm_printer_defines.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/macros/uvm_object_defines.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/macros/uvm_phase_defines.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/macros/uvm_message_defines.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/macros/uvm_version_defines.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/uvm_macros.svh|/hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../../../verification_ip/interface_packages/spi_s_pkg/src/spi_s_macros.svh|/hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../../../verification_ip/interface_packages/spi_s_pkg/src/spi_s_driver_bfm.sv|/hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../../../verification_ip/interface_packages/spi_s_pkg/src/spi_s_monitor_bfm.sv|/hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../../../verification_ip/interface_packages/spi_s_pkg/src/spi_s_if.sv| +Z100 !s90 -sv|-suppress|2223|-suppress|2286|+define+UVM_REPORT_DISABLE_FILE_LINE|+define+UVM_REPORT_DISABLE_FILE_LINE|+incdir+/hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../../../verification_ip/interface_packages/spi_s_pkg|-F|/hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../../../verification_ip/interface_packages/spi_s_pkg/spi_s_filelist_xrtl.f| +!i113 0 +R28 +Z101 !s92 -suppress 2223 -suppress 2286 -sv +define+UVM_REPORT_DISABLE_FILE_LINE +define+UVM_REPORT_DISABLE_FILE_LINE +incdir+/hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../../../verification_ip/interface_packages/spi_s_pkg -L mtiAvm -L mtiRnm -L mtiOvm -L mtiUvm -L mtiUPF -L infact +R30 +Xspi_s_driver_bfm_sv_unit +R1 +R2 +R59 +V:C4BPYUnJM=JnSE>U5LTQ2 +======= +R25 +Z105 !s108 1672027886.000000 +Z106 !s107 /tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/macros/uvm_deprecated_defines.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/macros/uvm_reg_defines.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/macros/uvm_callback_defines.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/macros/uvm_sequence_defines.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/tlm1/uvm_tlm_imps.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/macros/uvm_tlm_defines.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/macros/uvm_printer_defines.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/macros/uvm_object_defines.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/macros/uvm_phase_defines.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/macros/uvm_message_defines.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/macros/uvm_version_defines.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/uvm_macros.svh|/hwetools/work_area/frontend/vineeth_b7/system/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../../../verification_ip/interface_packages/spi_s_pkg/src/spi_s_macros.svh|/hwetools/work_area/frontend/vineeth_b7/system/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../../../verification_ip/interface_packages/spi_s_pkg/src/spi_s_driver_bfm.sv|/hwetools/work_area/frontend/vineeth_b7/system/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../../../verification_ip/interface_packages/spi_s_pkg/src/spi_s_monitor_bfm.sv|/hwetools/work_area/frontend/vineeth_b7/system/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../../../verification_ip/interface_packages/spi_s_pkg/src/spi_s_if.sv| +Z107 !s90 -sv|-suppress|2223|-suppress|2286|+define+UVM_REPORT_DISABLE_FILE_LINE|+define+UVM_REPORT_DISABLE_FILE_LINE|+incdir+/hwetools/work_area/frontend/vineeth_b7/system/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../../../verification_ip/interface_packages/spi_s_pkg|-F|/hwetools/work_area/frontend/vineeth_b7/system/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../../../verification_ip/interface_packages/spi_s_pkg/spi_s_filelist_xrtl.f| +!i113 0 +R29 +Z108 !s92 -suppress 2223 -suppress 2286 -sv +define+UVM_REPORT_DISABLE_FILE_LINE +define+UVM_REPORT_DISABLE_FILE_LINE +incdir+/hwetools/work_area/frontend/vineeth_b7/system/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../../../verification_ip/interface_packages/spi_s_pkg -L mtiAvm -L mtiRnm -L mtiOvm -L mtiUvm -L mtiUPF -L infact +R31 +Xspi_s_driver_bfm_sv_unit +R1 +R2 +R57 +VKQn1z3DhF9QO_MF@2i9^[0 +>>>>>>> ceab28f188594b972dededef57152e3a46196cbf +r1 +!s85 0 +31 +!i10b 1 +!s100 V@G0NOGY0FIk1]j5OcB8;2 +<<<<<<< HEAD +I:C4BPYUnJM=JnSE>U5LTQ2 +!i103 1 +S1 +R0 +R95 +R96 +R97 +Z102 F/hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../../../verification_ip/interface_packages/spi_s_pkg/src/spi_s_macros.svh +R32 +R24 +R98 +R99 +R100 +!i113 0 +R28 +R101 +R30 +Yspi_s_if +R1 +R2 +R59 +DXx4 work 16 spi_s_if_sv_unit 0 22 jn4jiAooz3<:6hn?bd_Uc2 +======= +IKQn1z3DhF9QO_MF@2i9^[0 +!i103 1 +S1 +R8 +R9 +R103 +R104 +Z109 F/hwetools/work_area/frontend/vineeth_b7/system/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../../../verification_ip/interface_packages/spi_s_pkg/src/spi_s_macros.svh +R33 +R25 +R105 +R106 +R107 +!i113 0 +R29 +R108 +R31 +Yspi_s_if +R1 +R2 +R57 +DXx4 work 16 spi_s_if_sv_unit 0 22 mfMO0KGQ>Zk2kL]JGGhoE2 +>>>>>>> ceab28f188594b972dededef57152e3a46196cbf +R7 +r1 +!s85 0 +31 +!i10b 1 +!s100 UXTTfPb>:Wk340=fWlK=fQAlce610;Q0 +!s105 spi_s_if_sv_unit +S1 +<<<<<<< HEAD +R0 +R95 +Z103 8/hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../../../verification_ip/interface_packages/spi_s_pkg/src/spi_s_if.sv +Z104 F/hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../../../verification_ip/interface_packages/spi_s_pkg/src/spi_s_if.sv +R89 +R24 +R98 +R99 +R100 +!i113 0 +R28 +R101 +R30 +Xspi_s_if_sv_unit +R1 +R2 +R59 +Vjn4jiAooz3<:6hn?bd_Uc2 +======= +R8 +R9 +Z110 8/hwetools/work_area/frontend/vineeth_b7/system/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../../../verification_ip/interface_packages/spi_s_pkg/src/spi_s_if.sv +Z111 F/hwetools/work_area/frontend/vineeth_b7/system/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../../../verification_ip/interface_packages/spi_s_pkg/src/spi_s_if.sv +R97 +R25 +R105 +R106 +R107 +!i113 0 +R29 +R108 +R31 +Xspi_s_if_sv_unit +R1 +R2 +R57 +VmfMO0KGQ>Zk2kL]JGGhoE2 +>>>>>>> ceab28f188594b972dededef57152e3a46196cbf +r1 +!s85 0 +31 +!i10b 1 +!s100 f]ccSIJgW:LM0h:NIR=Ag2 +<<<<<<< HEAD +Ijn4jiAooz3<:6hn?bd_Uc2 +!i103 1 +S1 +R0 +R95 +R103 +R104 +R90 +R24 +R98 +R99 +R100 +!i113 0 +R28 +R101 +R30 +Yspi_s_monitor_bfm +R1 +R2 +R59 +DXx4 work 25 spi_s_monitor_bfm_sv_unit 0 22 b^SGS3XbQI_JGYZ3;1<;D0 +R4 +R5 +R60 +======= +ImfMO0KGQ>Zk2kL]JGGhoE2 +!i103 1 +S1 +R8 +R9 +R110 +R111 +R98 +R25 +R105 +R106 +R107 +!i113 0 +R29 +R108 +R31 +Yspi_s_monitor_bfm +R1 +R2 +R57 +DXx4 work 25 spi_s_monitor_bfm_sv_unit 0 22 D:mK<>8OQ_zn`SF@eAcf51 +R4 +R5 +R58 +>>>>>>> ceab28f188594b972dededef57152e3a46196cbf +R7 +r1 +!s85 0 +31 +!i10b 1 +!s100 <_cBm3LV:E12f0cChZk=f3 +<<<<<<< HEAD +IliA7JDAfL3oeZ=9LWm7SX0 +!s105 spi_s_monitor_bfm_sv_unit +S1 +R0 +R95 +Z105 8/hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../../../verification_ip/interface_packages/spi_s_pkg/src/spi_s_monitor_bfm.sv +Z106 F/hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../../../verification_ip/interface_packages/spi_s_pkg/src/spi_s_monitor_bfm.sv +R11 +======= +I1Y:>>>>>> ceab28f188594b972dededef57152e3a46196cbf +R12 +R13 +R14 +R15 +R16 +R17 +R18 +R19 +R20 +R21 +R22 +<<<<<<< HEAD +R35 +R24 +R98 +R99 +R100 +!i113 0 +R28 +R101 +R30 +Xspi_s_monitor_bfm_sv_unit +R1 +R2 +R59 +Vb^SGS3XbQI_JGYZ3;1<;D0 +======= +R23 +R36 +R25 +R105 +R106 +R107 +!i113 0 +R29 +R108 +R31 +Xspi_s_monitor_bfm_sv_unit +R1 +R2 +R57 +VD:mK<>8OQ_zn`SF@eAcf51 +>>>>>>> ceab28f188594b972dededef57152e3a46196cbf +r1 +!s85 0 +31 +!i10b 1 +!s100 lL]1@0PGlTZSPHBF_^NcG3 +<<<<<<< HEAD +Ib^SGS3XbQI_JGYZ3;1<;D0 +!i103 1 +S1 +R0 +R95 +R105 +R106 +R102 +R38 +R24 +R98 +R99 +R100 +!i113 0 +R28 +R101 +R30 +======= +ID:mK<>8OQ_zn`SF@eAcf51 +!i103 1 +S1 +R8 +R9 +R112 +R113 +R109 +R39 +R25 +R105 +R106 +R107 +!i113 0 +R29 +R108 +R31 +>>>>>>> ceab28f188594b972dededef57152e3a46196cbf +Xspi_s_pkg +!s115 spi_s_monitor_bfm +!s115 spi_s_driver_bfm +R1 +R4 +R2 +R5 +<<<<<<< HEAD +R59 +Z107 !s110 1672041471 +!i10b 1 +!s100 H]]g?JJa5zJ@DWCD8n1WW1 +IQ0IVY:L1gK1 +VEngkPf8ab6]S3USEU>1gK1 +S1 +R8 +R101 +8/hwetools/work_area/frontend/vineeth_b7/system/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../../../verification_ip/interface_packages/spi_s_pkg/spi_s_pkg.sv +F/hwetools/work_area/frontend/vineeth_b7/system/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../../../verification_ip/interface_packages/spi_s_pkg/spi_s_pkg.sv +>>>>>>> ceab28f188594b972dededef57152e3a46196cbf +R12 +R13 +R14 +R15 +R16 +R17 +R18 +R19 +R20 +R21 +R22 +<<<<<<< HEAD +R102 +F/hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../../../verification_ip/interface_packages/spi_s_pkg/src/spi_s_typedefs.svh +F/hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../../../verification_ip/interface_packages/spi_s_pkg/src/spi_s_transaction.svh +F/hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../../../verification_ip/interface_packages/spi_s_pkg/src/spi_s_configuration.svh +F/hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../../../verification_ip/interface_packages/spi_s_pkg/src/spi_s_driver.svh +F/hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../../../verification_ip/interface_packages/spi_s_pkg/src/spi_s_monitor.svh +F/hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../../../verification_ip/interface_packages/spi_s_pkg/src/spi_s_transaction_coverage.svh +F/hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../../../verification_ip/interface_packages/spi_s_pkg/src/spi_s_sequence_base.svh +F/hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../../../verification_ip/interface_packages/spi_s_pkg/src/spi_s_random_sequence.svh +F/hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../../../verification_ip/interface_packages/spi_s_pkg/src/spi_s_responder_sequence.svh +F/hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../../../verification_ip/interface_packages/spi_s_pkg/src/spi_s2reg_adapter.svh +F/hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../../../verification_ip/interface_packages/spi_s_pkg/src/spi_s_agent.svh +R38 +R24 +r1 +!s85 0 +31 +R98 +!s107 /hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../../../verification_ip/interface_packages/spi_s_pkg/src/spi_s_agent.svh|/hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../../../verification_ip/interface_packages/spi_s_pkg/src/spi_s2reg_adapter.svh|/hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../../../verification_ip/interface_packages/spi_s_pkg/src/spi_s_responder_sequence.svh|/hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../../../verification_ip/interface_packages/spi_s_pkg/src/spi_s_random_sequence.svh|/hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../../../verification_ip/interface_packages/spi_s_pkg/src/spi_s_sequence_base.svh|/hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../../../verification_ip/interface_packages/spi_s_pkg/src/spi_s_transaction_coverage.svh|/hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../../../verification_ip/interface_packages/spi_s_pkg/src/spi_s_monitor.svh|/hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../../../verification_ip/interface_packages/spi_s_pkg/src/spi_s_driver.svh|/hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../../../verification_ip/interface_packages/spi_s_pkg/src/spi_s_configuration.svh|/hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../../../verification_ip/interface_packages/spi_s_pkg/src/spi_s_transaction.svh|/hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../../../verification_ip/interface_packages/spi_s_pkg/src/spi_s_typedefs.svh|/hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../../../verification_ip/interface_packages/spi_s_pkg/src/spi_s_macros.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/macros/uvm_deprecated_defines.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/macros/uvm_reg_defines.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/macros/uvm_callback_defines.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/macros/uvm_sequence_defines.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/tlm1/uvm_tlm_imps.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/macros/uvm_tlm_defines.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/macros/uvm_printer_defines.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/macros/uvm_object_defines.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/macros/uvm_phase_defines.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/macros/uvm_message_defines.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/macros/uvm_version_defines.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/uvm_macros.svh|/hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../../../verification_ip/interface_packages/spi_s_pkg/spi_s_pkg.sv| +!s90 -sv|-suppress|2223|-suppress|2286|+define+UVM_REPORT_DISABLE_FILE_LINE|+define+UVM_REPORT_DISABLE_FILE_LINE|+incdir+/hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../../../verification_ip/interface_packages/spi_s_pkg|-F|/hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../../../verification_ip/interface_packages/spi_s_pkg/spi_s_filelist_hvl.f| +!i113 0 +R28 +R101 +R30 +Xspi_s_pkg_hdl +R1 +R2 +R107 +!i10b 1 +!s100 Zn16iJIAoJk58UIR?koWB0 +IXaEAFYT7hd4>Qb83PJ?`=3 +VXaEAFYT7hd4>Qb83PJ?`=3 +S1 +R0 +R95 +8/hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../../../verification_ip/interface_packages/spi_s_pkg/spi_s_pkg_hdl.sv +F/hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../../../verification_ip/interface_packages/spi_s_pkg/spi_s_pkg_hdl.sv +F/hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../../../verification_ip/interface_packages/spi_s_pkg/src/spi_s_typedefs_hdl.svh +R102 +R41 +R24 +r1 +!s85 0 +31 +R98 +!s107 /hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../../../verification_ip/interface_packages/spi_s_pkg/src/spi_s_macros.svh|/hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../../../verification_ip/interface_packages/spi_s_pkg/src/spi_s_typedefs_hdl.svh|/hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../../../verification_ip/interface_packages/spi_s_pkg/spi_s_pkg_hdl.sv| +!s90 -sv|-suppress|2223|-suppress|2286|+define+UVM_REPORT_DISABLE_FILE_LINE|+define+UVM_REPORT_DISABLE_FILE_LINE|+incdir+/hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../../../verification_ip/interface_packages/spi_s_pkg|-F|/hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../../../verification_ip/interface_packages/spi_s_pkg/spi_s_filelist_hdl.f| +!i113 0 +R28 +R101 +R30 +======= +R23 +R109 +F/hwetools/work_area/frontend/vineeth_b7/system/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../../../verification_ip/interface_packages/spi_s_pkg/src/spi_s_typedefs.svh +F/hwetools/work_area/frontend/vineeth_b7/system/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../../../verification_ip/interface_packages/spi_s_pkg/src/spi_s_transaction.svh +F/hwetools/work_area/frontend/vineeth_b7/system/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../../../verification_ip/interface_packages/spi_s_pkg/src/spi_s_configuration.svh +F/hwetools/work_area/frontend/vineeth_b7/system/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../../../verification_ip/interface_packages/spi_s_pkg/src/spi_s_driver.svh +F/hwetools/work_area/frontend/vineeth_b7/system/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../../../verification_ip/interface_packages/spi_s_pkg/src/spi_s_monitor.svh +F/hwetools/work_area/frontend/vineeth_b7/system/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../../../verification_ip/interface_packages/spi_s_pkg/src/spi_s_transaction_coverage.svh +F/hwetools/work_area/frontend/vineeth_b7/system/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../../../verification_ip/interface_packages/spi_s_pkg/src/spi_s_sequence_base.svh +F/hwetools/work_area/frontend/vineeth_b7/system/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../../../verification_ip/interface_packages/spi_s_pkg/src/spi_s_random_sequence.svh +F/hwetools/work_area/frontend/vineeth_b7/system/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../../../verification_ip/interface_packages/spi_s_pkg/src/spi_s_responder_sequence.svh +F/hwetools/work_area/frontend/vineeth_b7/system/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../../../verification_ip/interface_packages/spi_s_pkg/src/spi_s2reg_adapter.svh +F/hwetools/work_area/frontend/vineeth_b7/system/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../../../verification_ip/interface_packages/spi_s_pkg/src/spi_s_agent.svh +R39 +R25 +r1 +!s85 0 +31 +Z114 !s108 1672027885.000000 +!s107 /hwetools/work_area/frontend/vineeth_b7/system/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../../../verification_ip/interface_packages/spi_s_pkg/src/spi_s_agent.svh|/hwetools/work_area/frontend/vineeth_b7/system/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../../../verification_ip/interface_packages/spi_s_pkg/src/spi_s2reg_adapter.svh|/hwetools/work_area/frontend/vineeth_b7/system/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../../../verification_ip/interface_packages/spi_s_pkg/src/spi_s_responder_sequence.svh|/hwetools/work_area/frontend/vineeth_b7/system/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../../../verification_ip/interface_packages/spi_s_pkg/src/spi_s_random_sequence.svh|/hwetools/work_area/frontend/vineeth_b7/system/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../../../verification_ip/interface_packages/spi_s_pkg/src/spi_s_sequence_base.svh|/hwetools/work_area/frontend/vineeth_b7/system/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../../../verification_ip/interface_packages/spi_s_pkg/src/spi_s_transaction_coverage.svh|/hwetools/work_area/frontend/vineeth_b7/system/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../../../verification_ip/interface_packages/spi_s_pkg/src/spi_s_monitor.svh|/hwetools/work_area/frontend/vineeth_b7/system/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../../../verification_ip/interface_packages/spi_s_pkg/src/spi_s_driver.svh|/hwetools/work_area/frontend/vineeth_b7/system/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../../../verification_ip/interface_packages/spi_s_pkg/src/spi_s_configuration.svh|/hwetools/work_area/frontend/vineeth_b7/system/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../../../verification_ip/interface_packages/spi_s_pkg/src/spi_s_transaction.svh|/hwetools/work_area/frontend/vineeth_b7/system/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../../../verification_ip/interface_packages/spi_s_pkg/src/spi_s_typedefs.svh|/hwetools/work_area/frontend/vineeth_b7/system/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../../../verification_ip/interface_packages/spi_s_pkg/src/spi_s_macros.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/macros/uvm_deprecated_defines.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/macros/uvm_reg_defines.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/macros/uvm_callback_defines.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/macros/uvm_sequence_defines.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/tlm1/uvm_tlm_imps.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/macros/uvm_tlm_defines.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/macros/uvm_printer_defines.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/macros/uvm_object_defines.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/macros/uvm_phase_defines.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/macros/uvm_message_defines.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/macros/uvm_version_defines.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/uvm_macros.svh|/hwetools/work_area/frontend/vineeth_b7/system/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../../../verification_ip/interface_packages/spi_s_pkg/spi_s_pkg.sv| +!s90 -sv|-suppress|2223|-suppress|2286|+define+UVM_REPORT_DISABLE_FILE_LINE|+define+UVM_REPORT_DISABLE_FILE_LINE|+incdir+/hwetools/work_area/frontend/vineeth_b7/system/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../../../verification_ip/interface_packages/spi_s_pkg|-F|/hwetools/work_area/frontend/vineeth_b7/system/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../../../verification_ip/interface_packages/spi_s_pkg/spi_s_filelist_hvl.f| +!i113 0 +R29 +R108 +R31 +Xspi_s_pkg_hdl +R1 +R2 +!s110 1672027885 +!i10b 1 +!s100 Zn16iJIAoJk58UIR?koWB0 +IYBN14zZ>7o_:a<_^fGoZ?1 +VYBN14zZ>7o_:a<_^fGoZ?1 +S1 +R8 +R101 +8/hwetools/work_area/frontend/vineeth_b7/system/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../../../verification_ip/interface_packages/spi_s_pkg/spi_s_pkg_hdl.sv +F/hwetools/work_area/frontend/vineeth_b7/system/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../../../verification_ip/interface_packages/spi_s_pkg/spi_s_pkg_hdl.sv +F/hwetools/work_area/frontend/vineeth_b7/system/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../../../verification_ip/interface_packages/spi_s_pkg/src/spi_s_typedefs_hdl.svh +R109 +R42 +R25 +r1 +!s85 0 +31 +R114 +!s107 /hwetools/work_area/frontend/vineeth_b7/system/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../../../verification_ip/interface_packages/spi_s_pkg/src/spi_s_macros.svh|/hwetools/work_area/frontend/vineeth_b7/system/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../../../verification_ip/interface_packages/spi_s_pkg/src/spi_s_typedefs_hdl.svh|/hwetools/work_area/frontend/vineeth_b7/system/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../../../verification_ip/interface_packages/spi_s_pkg/spi_s_pkg_hdl.sv| +!s90 -sv|-suppress|2223|-suppress|2286|+define+UVM_REPORT_DISABLE_FILE_LINE|+define+UVM_REPORT_DISABLE_FILE_LINE|+incdir+/hwetools/work_area/frontend/vineeth_b7/system/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../../../verification_ip/interface_packages/spi_s_pkg|-F|/hwetools/work_area/frontend/vineeth_b7/system/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../../../verification_ip/interface_packages/spi_s_pkg/spi_s_filelist_hdl.f| +!i113 0 +R29 +R108 +R31 +>>>>>>> ceab28f188594b972dededef57152e3a46196cbf +Xsubsys_env_pkg +R1 +R4 +R2 +R5 +R3 +R6 +R43 +R44 +<<<<<<< HEAD +R59 +R60 +R71 +======= +R57 +R58 +DXx4 work 15 block_1_env_pkg 0 22 SP9bKSndSUI[nkX?9UKnd3 +R60 +R61 +R62 +>>>>>>> ceab28f188594b972dededef57152e3a46196cbf +R63 +DXx4 work 15 block_2_env_pkg 0 22 8LDk:n?dkT`WT;F3;^HmG2 +R64 +<<<<<<< HEAD +R65 +R66 +R72 +Z108 !s110 1672041479 +!i10b 1 +!s100 l>GD0_8TkAjFF?=cBFW3z0 +IN>?3mAMb@RliZ7kcch=;42 +VN>?3mAMb@RliZ7kcch=;42 +S1 +R0 +w1672041446 +8/hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../../../verification_ip/environment_packages/subsys_env_pkg/subsys_env_pkg.sv +F/hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../../../verification_ip/environment_packages/subsys_env_pkg/subsys_env_pkg.sv +R11 +======= +!i10b 1 +!s100 Q_7@=?A>@dE=Bd3;hMcz;2 +IB9Vm:4J`lXz4K?cnlELR;3 +VB9Vm:4J`lXz4K?cnlELR;3 +S1 +R8 +R9 +8/hwetools/work_area/frontend/vineeth_b7/system/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../../../verification_ip/environment_packages/subsys_env_pkg/subsys_env_pkg.sv +F/hwetools/work_area/frontend/vineeth_b7/system/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../../../verification_ip/environment_packages/subsys_env_pkg/subsys_env_pkg.sv +>>>>>>> ceab28f188594b972dededef57152e3a46196cbf +R12 +R13 +R14 +R15 +R16 +R17 +R18 +R19 +R20 +R21 +R22 +<<<<<<< HEAD +F/hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../../../verification_ip/environment_packages/subsys_env_pkg/src/subsys_env_typedefs.svh +F/hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../../../verification_ip/environment_packages/subsys_env_pkg/src/subsys_env_configuration.svh +F/hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../../../verification_ip/environment_packages/subsys_env_pkg/src/subsys_predictor.svh +F/hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../../../verification_ip/environment_packages/subsys_env_pkg/src/subsys_scoreboard.svh +F/hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../../../verification_ip/environment_packages/subsys_env_pkg/src/subsys_environment.svh +F/hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../../../verification_ip/environment_packages/subsys_env_pkg/src/subsys_env_sequence_base.svh +R62 +R24 +r1 +!s85 0 +31 +R67 +!s107 /hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../../../verification_ip/environment_packages/subsys_env_pkg/src/subsys_env_sequence_base.svh|/hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../../../verification_ip/environment_packages/subsys_env_pkg/src/subsys_environment.svh|/hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../../../verification_ip/environment_packages/subsys_env_pkg/src/subsys_scoreboard.svh|/hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../../../verification_ip/environment_packages/subsys_env_pkg/src/subsys_predictor.svh|/hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../../../verification_ip/environment_packages/subsys_env_pkg/src/subsys_env_configuration.svh|/hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../../../verification_ip/environment_packages/subsys_env_pkg/src/subsys_env_typedefs.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/macros/uvm_deprecated_defines.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/macros/uvm_reg_defines.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/macros/uvm_callback_defines.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/macros/uvm_sequence_defines.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/tlm1/uvm_tlm_imps.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/macros/uvm_tlm_defines.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/macros/uvm_printer_defines.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/macros/uvm_object_defines.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/macros/uvm_phase_defines.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/macros/uvm_message_defines.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/macros/uvm_version_defines.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/uvm_macros.svh|/hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../../../verification_ip/environment_packages/subsys_env_pkg/subsys_env_pkg.sv| +!s90 -sv|-suppress|2223|-suppress|2286|+define+UVM_REPORT_DISABLE_FILE_LINE|+define+UVM_REPORT_DISABLE_FILE_LINE|+incdir+/hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../../../verification_ip/environment_packages/subsys_env_pkg|/hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../../../verification_ip/environment_packages/subsys_env_pkg/subsys_env_pkg.sv| +======= +R23 +F/hwetools/work_area/frontend/vineeth_b7/system/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../../../verification_ip/environment_packages/subsys_env_pkg/src/subsys_env_typedefs.svh +F/hwetools/work_area/frontend/vineeth_b7/system/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../../../verification_ip/environment_packages/subsys_env_pkg/src/subsys_env_configuration.svh +F/hwetools/work_area/frontend/vineeth_b7/system/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../../../verification_ip/environment_packages/subsys_env_pkg/src/subsys_predictor.svh +F/hwetools/work_area/frontend/vineeth_b7/system/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../../../verification_ip/environment_packages/subsys_env_pkg/src/subsys_scoreboard.svh +F/hwetools/work_area/frontend/vineeth_b7/system/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../../../verification_ip/environment_packages/subsys_env_pkg/src/subsys_environment.svh +F/hwetools/work_area/frontend/vineeth_b7/system/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../../../verification_ip/environment_packages/subsys_env_pkg/src/subsys_env_sequence_base.svh +R59 +R25 +r1 +!s85 0 +31 +Z115 !s108 1672027893.000000 +!s107 /hwetools/work_area/frontend/vineeth_b7/system/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../../../verification_ip/environment_packages/subsys_env_pkg/src/subsys_env_sequence_base.svh|/hwetools/work_area/frontend/vineeth_b7/system/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../../../verification_ip/environment_packages/subsys_env_pkg/src/subsys_environment.svh|/hwetools/work_area/frontend/vineeth_b7/system/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../../../verification_ip/environment_packages/subsys_env_pkg/src/subsys_scoreboard.svh|/hwetools/work_area/frontend/vineeth_b7/system/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../../../verification_ip/environment_packages/subsys_env_pkg/src/subsys_predictor.svh|/hwetools/work_area/frontend/vineeth_b7/system/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../../../verification_ip/environment_packages/subsys_env_pkg/src/subsys_env_configuration.svh|/hwetools/work_area/frontend/vineeth_b7/system/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../../../verification_ip/environment_packages/subsys_env_pkg/src/subsys_env_typedefs.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/macros/uvm_deprecated_defines.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/macros/uvm_reg_defines.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/macros/uvm_callback_defines.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/macros/uvm_sequence_defines.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/tlm1/uvm_tlm_imps.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/macros/uvm_tlm_defines.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/macros/uvm_printer_defines.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/macros/uvm_object_defines.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/macros/uvm_phase_defines.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/macros/uvm_message_defines.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/macros/uvm_version_defines.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/uvm_macros.svh|/hwetools/work_area/frontend/vineeth_b7/system/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../../../verification_ip/environment_packages/subsys_env_pkg/subsys_env_pkg.sv| +!s90 -sv|-suppress|2223|-suppress|2286|+define+UVM_REPORT_DISABLE_FILE_LINE|+define+UVM_REPORT_DISABLE_FILE_LINE|+incdir+/hwetools/work_area/frontend/vineeth_b7/system/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../../../verification_ip/environment_packages/subsys_env_pkg|/hwetools/work_area/frontend/vineeth_b7/system/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../../../verification_ip/environment_packages/subsys_env_pkg/subsys_env_pkg.sv| +>>>>>>> ceab28f188594b972dededef57152e3a46196cbf +!i113 0 +R29 +!s92 -suppress 2223 -suppress 2286 -sv +define+UVM_REPORT_DISABLE_FILE_LINE +define+UVM_REPORT_DISABLE_FILE_LINE +incdir+/hwetools/work_area/frontend/vineeth_b7/system/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../../../verification_ip/environment_packages/subsys_env_pkg -L mtiAvm -L mtiRnm -L mtiOvm -L mtiUvm -L mtiUPF -L infact +R31 +Xsubsys_parameters_pkg +R1 +R2 +<<<<<<< HEAD +R108 +!i10b 1 +!s100 3S1a7hRJnQNCj`3n6]:X[3 +I[SPYk8SIoFM1Z6f_7WDSj0 +V[SPYk8SIoFM1Z6f_7WDSj0 +S1 +R0 +R61 +8/hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../tb/parameters/subsys_parameters_pkg.sv +F/hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../tb/parameters/subsys_parameters_pkg.sv +R75 +R24 +r1 +!s85 0 +31 +Z109 !s108 1672041479.000000 +!s107 /hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../tb/parameters/subsys_parameters_pkg.sv| +!s90 -sv|-suppress|2223|-suppress|2286|+define+UVM_REPORT_DISABLE_FILE_LINE|+define+UVM_REPORT_DISABLE_FILE_LINE|+incdir+/hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../tb/parameters|/hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../tb/parameters/subsys_parameters_pkg.sv| +======= +R64 +!i10b 1 +!s100 3S1a7hRJnQNCj`3n6]:X[3 +I0>ba5iBf5=^8izikba5iBf5=^8izik>>>>>> ceab28f188594b972dededef57152e3a46196cbf +!i113 0 +R29 +!s92 -suppress 2223 -suppress 2286 -sv +define+UVM_REPORT_DISABLE_FILE_LINE +define+UVM_REPORT_DISABLE_FILE_LINE +incdir+/hwetools/work_area/frontend/vineeth_b7/system/UVMF/UVM_Framework/UVMF_2022.3/task_3/SUB/project_benches/subsys//tb/parameters -L mtiAvm -L mtiRnm -L mtiOvm -L mtiUvm -L mtiUPF -L infact +R31 +Xsubsys_sequences_pkg +R1 +R4 +<<<<<<< HEAD +R2 +R5 +R3 +R6 +R43 +R44 +R59 +R60 +R63 +R64 +R65 +R66 +R68 +R71 +R72 +R73 +Z110 !s110 1672041480 +======= +R65 +R69 +R70 +R71 +R72 +R73 +R74 +R75 +R77 +R78 +R79 +R80 +R66 +R76 +R81 +R82 +!s110 1672006420 +>>>>>>> ceab28f188594b972dededef57152e3a46196cbf +!i10b 1 +!s100 Oh6`nmTmCGO4OAczR2Jf^0 +Ij:gJO;iePWW>^=66oXVk71 +Vj:gJO;iePWW>^=66oXVk71 +S1 +R0 +<<<<<<< HEAD +R70 +======= +Z117 w1672006389 +>>>>>>> ceab28f188594b972dededef57152e3a46196cbf +8/hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../tb/sequences/subsys_sequences_pkg.sv +F/hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../tb/sequences/subsys_sequences_pkg.sv +R12 +R13 +R14 +R15 +R16 +R17 +R18 +R19 +R20 +R21 +R22 +R23 +F/hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../tb/sequences/src/subsys_bench_sequence_base.svh +F/hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../tb/sequences/src/register_test_sequence.svh +F/hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../tb/sequences/src/example_derived_test_sequence.svh +<<<<<<< HEAD +R62 +R24 +r1 +!s85 0 +31 +R109 +======= +R59 +R25 +r1 +!s85 0 +31 +Z118 !s108 1672006420.000000 +>>>>>>> ceab28f188594b972dededef57152e3a46196cbf +!s107 /hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../tb/sequences/src/example_derived_test_sequence.svh|/hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../tb/sequences/src/register_test_sequence.svh|/hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../tb/sequences/src/subsys_bench_sequence_base.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/macros/uvm_deprecated_defines.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/macros/uvm_reg_defines.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/macros/uvm_callback_defines.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/macros/uvm_sequence_defines.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/tlm1/uvm_tlm_imps.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/macros/uvm_tlm_defines.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/macros/uvm_printer_defines.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/macros/uvm_object_defines.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/macros/uvm_phase_defines.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/macros/uvm_message_defines.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/macros/uvm_version_defines.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/uvm_macros.svh|/hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../tb/sequences/subsys_sequences_pkg.sv| +!s90 -sv|-suppress|2223|-suppress|2286|+define+UVM_REPORT_DISABLE_FILE_LINE|+define+UVM_REPORT_DISABLE_FILE_LINE|+incdir+/hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../tb/sequences|/hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../tb/sequences/subsys_sequences_pkg.sv| +!i113 0 +R29 +!s92 -suppress 2223 -suppress 2286 -sv +define+UVM_REPORT_DISABLE_FILE_LINE +define+UVM_REPORT_DISABLE_FILE_LINE +incdir+/hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../tb/sequences -L mtiAvm -L mtiRnm -L mtiOvm -L mtiUvm -L mtiUPF -L infact +R31 +Xsubsys_tests_pkg +R1 +R4 +<<<<<<< HEAD +R2 +R5 +R68 +R3 +R6 +R43 +R44 +R59 +R60 +R71 +R63 +R64 +======= +>>>>>>> ceab28f188594b972dededef57152e3a46196cbf +R65 +R69 +R66 +<<<<<<< HEAD +R72 +R73 +R74 +R110 +======= +R70 +R71 +R72 +R73 +R74 +R75 +R76 +R77 +R78 +R79 +R80 +R81 +R82 +R83 +!s110 1672006421 +>>>>>>> ceab28f188594b972dededef57152e3a46196cbf +!i10b 1 +!s100 A_8EXB=R2_XEcZnb;=CSY0 +Ic=8_40UzSQgf6L8QBAz1o3 +Vc=8_40UzSQgf6L8QBAz1o3 +S1 +R0 +<<<<<<< HEAD +R70 +======= +R117 +>>>>>>> ceab28f188594b972dededef57152e3a46196cbf +8/hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../tb/tests/subsys_tests_pkg.sv +F/hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../tb/tests/subsys_tests_pkg.sv +R12 +R13 +R14 +R15 +R16 +R17 +R18 +R19 +R20 +R21 +R22 +R23 +F/hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../tb/tests/src/test_top.svh +F/hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../tb/tests/src/register_test.svh +F/hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../tb/tests/src/example_derived_test.svh +L0 21 +R25 +r1 +!s85 0 +31 +<<<<<<< HEAD +R76 +======= +R118 +>>>>>>> ceab28f188594b972dededef57152e3a46196cbf +!s107 /hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../tb/tests/src/example_derived_test.svh|/hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../tb/tests/src/register_test.svh|/hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../tb/tests/src/test_top.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/macros/uvm_deprecated_defines.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/macros/uvm_reg_defines.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/macros/uvm_callback_defines.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/macros/uvm_sequence_defines.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/tlm1/uvm_tlm_imps.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/macros/uvm_tlm_defines.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/macros/uvm_printer_defines.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/macros/uvm_object_defines.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/macros/uvm_phase_defines.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/macros/uvm_message_defines.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/macros/uvm_version_defines.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/uvm_macros.svh|/hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../tb/tests/subsys_tests_pkg.sv| +!s90 -sv|-suppress|2223|-suppress|2286|+define+UVM_REPORT_DISABLE_FILE_LINE|+define+UVM_REPORT_DISABLE_FILE_LINE|+incdir+/hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../tb/tests|/hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../tb/tests/subsys_tests_pkg.sv| +!i113 0 +R29 +!s92 -suppress 2223 -suppress 2286 -sv +define+UVM_REPORT_DISABLE_FILE_LINE +define+UVM_REPORT_DISABLE_FILE_LINE +incdir+/hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../tb/tests -L mtiAvm -L mtiRnm -L mtiOvm -L mtiUvm -L mtiUPF -L infact +R31 +Xuvmf_base_pkg +R1 +R4 +R2 +Z111 !s110 1672041466 +!i10b 1 +!s100 aZaFYJKjJI1f]L:MSl:9<2 +<<<<<<< HEAD +IDi`43ijd2B>d_PV@@j:?c3 +VDi`43ijd2B>d_PV@@j:?c3 +S1 +R0 +Z112 w1671874424 +8/hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3//uvmf_base_pkg/uvmf_base_pkg.sv +F/hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3//uvmf_base_pkg/uvmf_base_pkg.sv +R11 +======= +IH@R@oR_Co_:BkD5VlLbSL0 +VH@R@oR_Co_:BkD5VlLbSL0 +S1 +R8 +Z119 w1671991543 +8/hwetools/work_area/frontend/vineeth_b7/system/UVMF/UVM_Framework/UVMF_2022.3/uvmf_base_pkg/uvmf_base_pkg.sv +F/hwetools/work_area/frontend/vineeth_b7/system/UVMF/UVM_Framework/UVMF_2022.3/uvmf_base_pkg/uvmf_base_pkg.sv +>>>>>>> ceab28f188594b972dededef57152e3a46196cbf +R12 +R13 +R14 +R15 +R16 +R17 +R18 +R19 +R20 +R21 +R22 +<<<<<<< HEAD +F/hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3//uvmf_base_pkg/src/uvmf_version.svh +F/hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3//uvmf_base_pkg/src/uvmf_base_typedefs.svh +F/hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3//uvmf_base_pkg/src/uvmf_transaction_base.svh +F/hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3//uvmf_base_pkg/src/uvmf_sequence_base.svh +F/hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3//uvmf_base_pkg/src/uvmf_scoreboard_base.svh +F/hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3//uvmf_base_pkg/src/uvmf_in_order_scoreboard.svh +F/hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3//uvmf_base_pkg/src/uvmf_in_order_race_scoreboard.svh +F/hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3//uvmf_base_pkg/src/uvmf_in_order_race_scoreboard_array.svh +F/hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3//uvmf_base_pkg/src/uvmf_out_of_order_scoreboard.svh +F/hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3//uvmf_base_pkg/src/uvmf_out_of_order_race_scoreboard.svh +F/hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3//uvmf_base_pkg/src/uvmf_in_order_scoreboard_array.svh +F/hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3//uvmf_base_pkg/src/uvmf_catapult_scoreboard.svh +F/hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3//uvmf_base_pkg/src/uvmf_predictor_base.svh +F/hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3//uvmf_base_pkg/src/uvmf_sorting_predictor_base.svh +F/hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3//uvmf_base_pkg/src/uvmf_parameterized_agent_configuration_base.svh +F/hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3//uvmf_base_pkg/src/uvmf_driver_base.svh +F/hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3//uvmf_base_pkg/src/uvmf_monitor_base.svh +F/hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3//uvmf_base_pkg/src/uvmf_parameterized_agent.svh +F/hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3//uvmf_base_pkg/src/uvmf_virtual_sequencer_base.svh +F/hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3//uvmf_base_pkg/src/uvmf_virtual_sequence_base.svh +F/hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3//uvmf_base_pkg/src/uvmf_environment_configuration_base.svh +F/hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3//uvmf_base_pkg/src/uvmf_environment_base.svh +F/hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3//uvmf_base_pkg/src/uvmf_parameterized_simplex_environment.svh +F/hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3//uvmf_base_pkg/src/uvmf_parameterized_1agent_environment.svh +F/hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3//uvmf_base_pkg/src/uvmf_parameterized_2agent_environment.svh +F/hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3//uvmf_base_pkg/src/uvmf_parameterized_3agent_environment.svh +F/hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3//uvmf_base_pkg/src/uvmf_test_base.svh +======= +R23 +F/hwetools/work_area/frontend/vineeth_b7/system/UVMF/UVM_Framework/UVMF_2022.3/uvmf_base_pkg/src/uvmf_version.svh +F/hwetools/work_area/frontend/vineeth_b7/system/UVMF/UVM_Framework/UVMF_2022.3/uvmf_base_pkg/src/uvmf_base_typedefs.svh +F/hwetools/work_area/frontend/vineeth_b7/system/UVMF/UVM_Framework/UVMF_2022.3/uvmf_base_pkg/src/uvmf_transaction_base.svh +F/hwetools/work_area/frontend/vineeth_b7/system/UVMF/UVM_Framework/UVMF_2022.3/uvmf_base_pkg/src/uvmf_sequence_base.svh +F/hwetools/work_area/frontend/vineeth_b7/system/UVMF/UVM_Framework/UVMF_2022.3/uvmf_base_pkg/src/uvmf_scoreboard_base.svh +F/hwetools/work_area/frontend/vineeth_b7/system/UVMF/UVM_Framework/UVMF_2022.3/uvmf_base_pkg/src/uvmf_in_order_scoreboard.svh +F/hwetools/work_area/frontend/vineeth_b7/system/UVMF/UVM_Framework/UVMF_2022.3/uvmf_base_pkg/src/uvmf_in_order_race_scoreboard.svh +F/hwetools/work_area/frontend/vineeth_b7/system/UVMF/UVM_Framework/UVMF_2022.3/uvmf_base_pkg/src/uvmf_in_order_race_scoreboard_array.svh +F/hwetools/work_area/frontend/vineeth_b7/system/UVMF/UVM_Framework/UVMF_2022.3/uvmf_base_pkg/src/uvmf_out_of_order_scoreboard.svh +F/hwetools/work_area/frontend/vineeth_b7/system/UVMF/UVM_Framework/UVMF_2022.3/uvmf_base_pkg/src/uvmf_out_of_order_race_scoreboard.svh +F/hwetools/work_area/frontend/vineeth_b7/system/UVMF/UVM_Framework/UVMF_2022.3/uvmf_base_pkg/src/uvmf_in_order_scoreboard_array.svh +F/hwetools/work_area/frontend/vineeth_b7/system/UVMF/UVM_Framework/UVMF_2022.3/uvmf_base_pkg/src/uvmf_catapult_scoreboard.svh +F/hwetools/work_area/frontend/vineeth_b7/system/UVMF/UVM_Framework/UVMF_2022.3/uvmf_base_pkg/src/uvmf_predictor_base.svh +F/hwetools/work_area/frontend/vineeth_b7/system/UVMF/UVM_Framework/UVMF_2022.3/uvmf_base_pkg/src/uvmf_sorting_predictor_base.svh +F/hwetools/work_area/frontend/vineeth_b7/system/UVMF/UVM_Framework/UVMF_2022.3/uvmf_base_pkg/src/uvmf_parameterized_agent_configuration_base.svh +F/hwetools/work_area/frontend/vineeth_b7/system/UVMF/UVM_Framework/UVMF_2022.3/uvmf_base_pkg/src/uvmf_driver_base.svh +F/hwetools/work_area/frontend/vineeth_b7/system/UVMF/UVM_Framework/UVMF_2022.3/uvmf_base_pkg/src/uvmf_monitor_base.svh +F/hwetools/work_area/frontend/vineeth_b7/system/UVMF/UVM_Framework/UVMF_2022.3/uvmf_base_pkg/src/uvmf_parameterized_agent.svh +F/hwetools/work_area/frontend/vineeth_b7/system/UVMF/UVM_Framework/UVMF_2022.3/uvmf_base_pkg/src/uvmf_virtual_sequencer_base.svh +F/hwetools/work_area/frontend/vineeth_b7/system/UVMF/UVM_Framework/UVMF_2022.3/uvmf_base_pkg/src/uvmf_virtual_sequence_base.svh +F/hwetools/work_area/frontend/vineeth_b7/system/UVMF/UVM_Framework/UVMF_2022.3/uvmf_base_pkg/src/uvmf_environment_configuration_base.svh +F/hwetools/work_area/frontend/vineeth_b7/system/UVMF/UVM_Framework/UVMF_2022.3/uvmf_base_pkg/src/uvmf_environment_base.svh +F/hwetools/work_area/frontend/vineeth_b7/system/UVMF/UVM_Framework/UVMF_2022.3/uvmf_base_pkg/src/uvmf_parameterized_simplex_environment.svh +F/hwetools/work_area/frontend/vineeth_b7/system/UVMF/UVM_Framework/UVMF_2022.3/uvmf_base_pkg/src/uvmf_parameterized_1agent_environment.svh +F/hwetools/work_area/frontend/vineeth_b7/system/UVMF/UVM_Framework/UVMF_2022.3/uvmf_base_pkg/src/uvmf_parameterized_2agent_environment.svh +F/hwetools/work_area/frontend/vineeth_b7/system/UVMF/UVM_Framework/UVMF_2022.3/uvmf_base_pkg/src/uvmf_parameterized_3agent_environment.svh +F/hwetools/work_area/frontend/vineeth_b7/system/UVMF/UVM_Framework/UVMF_2022.3/uvmf_base_pkg/src/uvmf_test_base.svh +>>>>>>> ceab28f188594b972dededef57152e3a46196cbf +L0 65 +R25 +r1 +!s85 0 +31 +<<<<<<< HEAD +R42 +!s107 /hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3//uvmf_base_pkg/src/uvmf_test_base.svh|/hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3//uvmf_base_pkg/src/uvmf_parameterized_3agent_environment.svh|/hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3//uvmf_base_pkg/src/uvmf_parameterized_2agent_environment.svh|/hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3//uvmf_base_pkg/src/uvmf_parameterized_1agent_environment.svh|/hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3//uvmf_base_pkg/src/uvmf_parameterized_simplex_environment.svh|/hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3//uvmf_base_pkg/src/uvmf_environment_base.svh|/hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3//uvmf_base_pkg/src/uvmf_environment_configuration_base.svh|/hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3//uvmf_base_pkg/src/uvmf_virtual_sequence_base.svh|/hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3//uvmf_base_pkg/src/uvmf_virtual_sequencer_base.svh|/hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3//uvmf_base_pkg/src/uvmf_parameterized_agent.svh|/hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3//uvmf_base_pkg/src/uvmf_monitor_base.svh|/hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3//uvmf_base_pkg/src/uvmf_driver_base.svh|/hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3//uvmf_base_pkg/src/uvmf_parameterized_agent_configuration_base.svh|/hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3//uvmf_base_pkg/src/uvmf_sorting_predictor_base.svh|/hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3//uvmf_base_pkg/src/uvmf_predictor_base.svh|/hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3//uvmf_base_pkg/src/uvmf_catapult_scoreboard.svh|/hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3//uvmf_base_pkg/src/uvmf_in_order_scoreboard_array.svh|/hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3//uvmf_base_pkg/src/uvmf_out_of_order_race_scoreboard.svh|/hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3//uvmf_base_pkg/src/uvmf_out_of_order_scoreboard.svh|/hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3//uvmf_base_pkg/src/uvmf_in_order_race_scoreboard_array.svh|/hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3//uvmf_base_pkg/src/uvmf_in_order_race_scoreboard.svh|/hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3//uvmf_base_pkg/src/uvmf_in_order_scoreboard.svh|/hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3//uvmf_base_pkg/src/uvmf_scoreboard_base.svh|/hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3//uvmf_base_pkg/src/uvmf_sequence_base.svh|/hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3//uvmf_base_pkg/src/uvmf_transaction_base.svh|/hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3//uvmf_base_pkg/src/uvmf_base_typedefs.svh|/hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3//uvmf_base_pkg/src/uvmf_version.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/macros/uvm_deprecated_defines.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/macros/uvm_reg_defines.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/macros/uvm_callback_defines.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/macros/uvm_sequence_defines.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/tlm1/uvm_tlm_imps.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/macros/uvm_tlm_defines.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/macros/uvm_printer_defines.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/macros/uvm_object_defines.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/macros/uvm_phase_defines.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/macros/uvm_message_defines.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/macros/uvm_version_defines.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/uvm_macros.svh|/hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3//uvmf_base_pkg/uvmf_base_pkg.sv| +!s90 -sv|-suppress|2223|-suppress|2286|+define+UVM_REPORT_DISABLE_FILE_LINE|+define+UVM_REPORT_DISABLE_FILE_LINE|+incdir+/hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3//uvmf_base_pkg|-F|/hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3//uvmf_base_pkg/uvmf_base_pkg_filelist_hvl.f| +!i113 0 +R28 +Z113 !s92 -suppress 2223 -suppress 2286 -sv +define+UVM_REPORT_DISABLE_FILE_LINE +define+UVM_REPORT_DISABLE_FILE_LINE +incdir+/hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3//uvmf_base_pkg -L mtiAvm -L mtiRnm -L mtiOvm -L mtiUvm -L mtiUPF -L infact +R30 +Xuvmf_base_pkg_hdl +R1 +R111 +!i10b 1 +!s100 N^6_:OJbG>>>>>> ceab28f188594b972dededef57152e3a46196cbf +L0 38 +R25 +r1 +!s85 0 +31 +<<<<<<< HEAD +R42 +!s107 /hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3//uvmf_base_pkg/src/uvmf_base_typedefs_hdl.svh|/hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3//uvmf_base_pkg/uvmf_base_pkg_hdl.sv| +!s90 -sv|-suppress|2223|-suppress|2286|+define+UVM_REPORT_DISABLE_FILE_LINE|+define+UVM_REPORT_DISABLE_FILE_LINE|+incdir+/hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3//uvmf_base_pkg|-F|/hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3//uvmf_base_pkg/uvmf_base_pkg_filelist_hdl.f| +!i113 0 +R28 +R113 +R30 +vverilog_dut +R1 +R111 +======= +R120 +!s107 /hwetools/work_area/frontend/vineeth_b7/system/UVMF/UVM_Framework/UVMF_2022.3/uvmf_base_pkg/src/uvmf_base_typedefs_hdl.svh|/hwetools/work_area/frontend/vineeth_b7/system/UVMF/UVM_Framework/UVMF_2022.3/uvmf_base_pkg/uvmf_base_pkg_hdl.sv| +!s90 -sv|-suppress|2223|-suppress|2286|+define+UVM_REPORT_DISABLE_FILE_LINE|+define+UVM_REPORT_DISABLE_FILE_LINE|+incdir+/hwetools/work_area/frontend/vineeth_b7/system/UVMF/UVM_Framework/UVMF_2022.3/uvmf_base_pkg|-F|/hwetools/work_area/frontend/vineeth_b7/system/UVMF/UVM_Framework/UVMF_2022.3/uvmf_base_pkg/uvmf_base_pkg_filelist_hdl.f| +!i113 0 +R29 +R121 +R31 +vverilog_dut +R1 +R122 +>>>>>>> ceab28f188594b972dededef57152e3a46196cbf +!i10b 1 +!s100 ^UD9ZTL3>>>>>> ceab28f188594b972dededef57152e3a46196cbf +L0 1 +R25 +r1 +!s85 0 +31 +<<<<<<< HEAD +R42 +!s107 /hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../rtl/verilog/verilog_dut.v| +!s90 -sv|-suppress|2223|-suppress|2286|+define+UVM_REPORT_DISABLE_FILE_LINE|+define+UVM_REPORT_DISABLE_FILE_LINE|/hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../rtl/verilog/verilog_dut.v| +======= +R120 +!s107 /hwetools/work_area/frontend/vineeth_b7/system/UVMF/UVM_Framework/UVMF_2022.3/task_3/SUB/project_benches/subsys//rtl/verilog/verilog_dut.v| +!s90 -sv|-suppress|2223|-suppress|2286|+define+UVM_REPORT_DISABLE_FILE_LINE|+define+UVM_REPORT_DISABLE_FILE_LINE|/hwetools/work_area/frontend/vineeth_b7/system/UVMF/UVM_Framework/UVMF_2022.3/task_3/SUB/project_benches/subsys//rtl/verilog/verilog_dut.v| +>>>>>>> ceab28f188594b972dededef57152e3a46196cbf +!i113 0 +R29 +!s92 -suppress 2223 -suppress 2286 -sv +define+UVM_REPORT_DISABLE_FILE_LINE +define+UVM_REPORT_DISABLE_FILE_LINE -L mtiAvm -L mtiRnm -L mtiOvm -L mtiUvm -L mtiUPF -L infact +R31 +Evhdl_dut +<<<<<<< HEAD +R70 +Z114 DPx3 std 6 textio 0 22 zE1`LPoLg^DX3Oz^4Fj1K3 +Z115 DPx4 ieee 14 std_logic_1164 0 22 eNV`TJ_GofJTzYa?f<@Oe1 +R0 +Z116 8/hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../rtl/vhdl/vhdl_dut.vhd +Z117 F/hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../rtl/vhdl/vhdl_dut.vhd +======= +Z123 w1671991813 +Z124 DPx3 std 6 textio 0 22 zE1`LPoLg^DX3Oz^4Fj1K3 +Z125 DPx4 ieee 14 std_logic_1164 0 22 eNV`TJ_GofJTzYa?f<@Oe1 +R8 +Z126 8/hwetools/work_area/frontend/vineeth_b7/system/UVMF/UVM_Framework/UVMF_2022.3/task_3/SUB/project_benches/subsys//rtl/vhdl/vhdl_dut.vhd +Z127 F/hwetools/work_area/frontend/vineeth_b7/system/UVMF/UVM_Framework/UVMF_2022.3/task_3/SUB/project_benches/subsys//rtl/vhdl/vhdl_dut.vhd +>>>>>>> ceab28f188594b972dededef57152e3a46196cbf +l0 +L4 +V4_]Q6fT]^UP;BkHShHi9j2 +!s100 YHiX09^FS?9c7;MH[92@@2 +<<<<<<< HEAD +Z118 OE;C;10.6c;65 +32 +R111 +!i10b 1 +R42 +Z119 !s90 /hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../rtl/vhdl/vhdl_dut.vhd| +Z120 !s107 /hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../rtl/vhdl/vhdl_dut.vhd| +!i113 0 +Z121 tExplicit 1 CvgOpt 0 +Artl +R114 +R115 +======= +Z128 OE;C;10.6c;65 +32 +R122 +!i10b 1 +R120 +Z129 !s90 /hwetools/work_area/frontend/vineeth_b7/system/UVMF/UVM_Framework/UVMF_2022.3/task_3/SUB/project_benches/subsys//rtl/vhdl/vhdl_dut.vhd| +Z130 !s107 /hwetools/work_area/frontend/vineeth_b7/system/UVMF/UVM_Framework/UVMF_2022.3/task_3/SUB/project_benches/subsys//rtl/vhdl/vhdl_dut.vhd| +!i113 0 +Z131 tExplicit 1 CvgOpt 0 +Artl +R124 +R125 +>>>>>>> ceab28f188594b972dededef57152e3a46196cbf +DEx4 work 8 vhdl_dut 0 22 4_]Q6fT]^UP;BkHShHi9j2 +l13 +L12 +VD8Z[WTM3SDlI>>>>>> ceab28f188594b972dededef57152e3a46196cbf +R4 +R5 +R63 +R7 +r1 +!s85 0 +31 +!i10b 1 +!s100 lTWi^Rlm?kD5?_04zmfm83 +<<<<<<< HEAD +I49aYmE9HzD[GUOG8J@W@h1 +!s105 wb_s_driver_bfm_sv_unit +S1 +R0 +R53 +Z122 8/hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../../../verification_ip/interface_packages/wb_s_pkg/src/wb_s_driver_bfm.sv +Z123 F/hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../../../verification_ip/interface_packages/wb_s_pkg/src/wb_s_driver_bfm.sv +R11 +======= +If;2Pi:l=n7?dIjE>[7WzL2 +!s105 wb_s_driver_bfm_sv_unit +S1 +R8 +R9 +Z132 8/hwetools/work_area/frontend/vineeth_b7/system/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../../../verification_ip/interface_packages/wb_s_pkg/src/wb_s_driver_bfm.sv +Z133 F/hwetools/work_area/frontend/vineeth_b7/system/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../../../verification_ip/interface_packages/wb_s_pkg/src/wb_s_driver_bfm.sv +>>>>>>> ceab28f188594b972dededef57152e3a46196cbf +R12 +R13 +R14 +R15 +R16 +R17 +R18 +R19 +R20 +R21 +R22 +R23 +R24 +<<<<<<< HEAD +Z124 !s108 1672041475.000000 +Z125 !s107 /tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/macros/uvm_deprecated_defines.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/macros/uvm_reg_defines.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/macros/uvm_callback_defines.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/macros/uvm_sequence_defines.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/tlm1/uvm_tlm_imps.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/macros/uvm_tlm_defines.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/macros/uvm_printer_defines.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/macros/uvm_object_defines.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/macros/uvm_phase_defines.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/macros/uvm_message_defines.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/macros/uvm_version_defines.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/uvm_macros.svh|/hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../../../verification_ip/interface_packages/wb_s_pkg/src/wb_s_macros.svh|/hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../../../verification_ip/interface_packages/wb_s_pkg/src/wb_s_driver_bfm.sv|/hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../../../verification_ip/interface_packages/wb_s_pkg/src/wb_s_monitor_bfm.sv|/hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../../../verification_ip/interface_packages/wb_s_pkg/src/wb_s_if.sv| +Z126 !s90 -sv|-suppress|2223|-suppress|2286|+define+UVM_REPORT_DISABLE_FILE_LINE|+define+UVM_REPORT_DISABLE_FILE_LINE|+incdir+/hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../../../verification_ip/interface_packages/wb_s_pkg|-F|/hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../../../verification_ip/interface_packages/wb_s_pkg/wb_s_filelist_xrtl.f| +!i113 0 +R28 +Z127 !s92 -suppress 2223 -suppress 2286 -sv +define+UVM_REPORT_DISABLE_FILE_LINE +define+UVM_REPORT_DISABLE_FILE_LINE +incdir+/hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../../../verification_ip/interface_packages/wb_s_pkg -L mtiAvm -L mtiRnm -L mtiOvm -L mtiUvm -L mtiUPF -L infact +R30 +Xwb_s_driver_bfm_sv_unit +R1 +R2 +R65 +VL=7mYgm5i@:QY7mmBOWH00 +======= +R25 +Z134 !s108 1672027890.000000 +Z135 !s107 /tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/macros/uvm_deprecated_defines.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/macros/uvm_reg_defines.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/macros/uvm_callback_defines.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/macros/uvm_sequence_defines.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/tlm1/uvm_tlm_imps.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/macros/uvm_tlm_defines.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/macros/uvm_printer_defines.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/macros/uvm_object_defines.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/macros/uvm_phase_defines.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/macros/uvm_message_defines.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/macros/uvm_version_defines.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/uvm_macros.svh|/hwetools/work_area/frontend/vineeth_b7/system/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../../../verification_ip/interface_packages/wb_s_pkg/src/wb_s_macros.svh|/hwetools/work_area/frontend/vineeth_b7/system/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../../../verification_ip/interface_packages/wb_s_pkg/src/wb_s_driver_bfm.sv|/hwetools/work_area/frontend/vineeth_b7/system/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../../../verification_ip/interface_packages/wb_s_pkg/src/wb_s_monitor_bfm.sv|/hwetools/work_area/frontend/vineeth_b7/system/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../../../verification_ip/interface_packages/wb_s_pkg/src/wb_s_if.sv| +Z136 !s90 -sv|-suppress|2223|-suppress|2286|+define+UVM_REPORT_DISABLE_FILE_LINE|+define+UVM_REPORT_DISABLE_FILE_LINE|+incdir+/hwetools/work_area/frontend/vineeth_b7/system/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../../../verification_ip/interface_packages/wb_s_pkg|-F|/hwetools/work_area/frontend/vineeth_b7/system/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../../../verification_ip/interface_packages/wb_s_pkg/wb_s_filelist_xrtl.f| +!i113 0 +R29 +Z137 !s92 -suppress 2223 -suppress 2286 -sv +define+UVM_REPORT_DISABLE_FILE_LINE +define+UVM_REPORT_DISABLE_FILE_LINE +incdir+/hwetools/work_area/frontend/vineeth_b7/system/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../../../verification_ip/interface_packages/wb_s_pkg -L mtiAvm -L mtiRnm -L mtiOvm -L mtiUvm -L mtiUPF -L infact +R31 +Xwb_s_driver_bfm_sv_unit +R1 +R2 +R62 +VgMmnm9nfl68Y:QK9oDFZa1 +>>>>>>> ceab28f188594b972dededef57152e3a46196cbf +r1 +!s85 0 +31 +!i10b 1 +!s100 g1ieFI1?jkj4lM18ZmC@U1 +<<<<<<< HEAD +IL=7mYgm5i@:QY7mmBOWH00 +!i103 1 +S1 +R0 +R53 +R122 +R123 +Z128 F/hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../../../verification_ip/interface_packages/wb_s_pkg/src/wb_s_macros.svh +R32 +R24 +R124 +R125 +R126 +!i113 0 +R28 +R127 +R30 +Ywb_s_if +R1 +R2 +R65 +DXx4 work 15 wb_s_if_sv_unit 0 22 83;kY8]9Z^hSCP6BNn=323 +======= +IgMmnm9nfl68Y:QK9oDFZa1 +!i103 1 +S1 +R8 +R9 +R132 +R133 +Z138 F/hwetools/work_area/frontend/vineeth_b7/system/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../../../verification_ip/interface_packages/wb_s_pkg/src/wb_s_macros.svh +R33 +R25 +R134 +R135 +R136 +!i113 0 +R29 +R137 +R31 +Ywb_s_if +R1 +R2 +R62 +DXx4 work 15 wb_s_if_sv_unit 0 22 LKNHZDmlMKjcC5TBiz82C2 +>>>>>>> ceab28f188594b972dededef57152e3a46196cbf +R7 +r1 +!s85 0 +31 +!i10b 1 +!s100 kbP0>d_PE4zdh22n;NhDQ3 +I_8aGBo^gc:NkAVC2G;JBC0 +!s105 wb_s_if_sv_unit +S1 +<<<<<<< HEAD +R0 +Z129 w1672041442 +Z130 8/hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../../../verification_ip/interface_packages/wb_s_pkg/src/wb_s_if.sv +Z131 F/hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../../../verification_ip/interface_packages/wb_s_pkg/src/wb_s_if.sv +L0 37 +R24 +R124 +R125 +R126 +!i113 0 +R28 +R127 +R30 +Xwb_s_if_sv_unit +R1 +R2 +R65 +V83;kY8]9Z^hSCP6BNn=323 +======= +R8 +R9 +Z139 8/hwetools/work_area/frontend/vineeth_b7/system/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../../../verification_ip/interface_packages/wb_s_pkg/src/wb_s_if.sv +Z140 F/hwetools/work_area/frontend/vineeth_b7/system/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../../../verification_ip/interface_packages/wb_s_pkg/src/wb_s_if.sv +L0 37 +R25 +R134 +R135 +R136 +!i113 0 +R29 +R137 +R31 +Xwb_s_if_sv_unit +R1 +R2 +R62 +VLKNHZDmlMKjcC5TBiz82C2 +>>>>>>> ceab28f188594b972dededef57152e3a46196cbf +r1 +!s85 0 +31 +!i10b 1 +!s100 @VchQjBAAY?I54eKPYzMj3 +<<<<<<< HEAD +I83;kY8]9Z^hSCP6BNn=323 +!i103 1 +S1 +R0 +R129 +R130 +R131 +L0 34 +R24 +R124 +R125 +R126 +!i113 0 +R28 +R127 +R30 +Ywb_s_monitor_bfm +R1 +R2 +R65 +DXx4 work 24 wb_s_monitor_bfm_sv_unit 0 22 @Qi=1Y339gO[C09?SaiPZ0 +======= +ILKNHZDmlMKjcC5TBiz82C2 +!i103 1 +S1 +R8 +R9 +R139 +R140 +L0 34 +R25 +R134 +R135 +R136 +!i113 0 +R29 +R137 +R31 +Ywb_s_monitor_bfm +R1 +R2 +R62 +DXx4 work 24 wb_s_monitor_bfm_sv_unit 0 22 aogzCC>R>>>>>> ceab28f188594b972dededef57152e3a46196cbf +R4 +R5 +R63 +R7 +r1 +!s85 0 +31 +!i10b 1 +!s100 Nom@]c9icF<65D;MH[B4k3 +<<<<<<< HEAD +Ii5Mi>>>>>> ceab28f188594b972dededef57152e3a46196cbf +R12 +R13 +R14 +R15 +R16 +R17 +R18 +R19 +R20 +R21 +R22 +<<<<<<< HEAD +R35 +R24 +R124 +R125 +R126 +!i113 0 +R28 +R127 +R30 +Xwb_s_monitor_bfm_sv_unit +R1 +R2 +R65 +V@Qi=1Y339gO[C09?SaiPZ0 +======= +R23 +R36 +R25 +R134 +R135 +R136 +!i113 0 +R29 +R137 +R31 +Xwb_s_monitor_bfm_sv_unit +R1 +R2 +R62 +VaogzCC>R>>>>>> ceab28f188594b972dededef57152e3a46196cbf +r1 +!s85 0 +31 +!i10b 1 +!s100 1=05X5FH@^R>>>>>> ceab28f188594b972dededef57152e3a46196cbf +Xwb_s_pkg +!s115 wb_s_monitor_bfm +!s115 wb_s_driver_bfm +R1 +R4 +R2 +R5 +<<<<<<< HEAD +R65 +Z134 !s110 1672041475 +!i10b 1 +!s100 ]5O_o=8KQ5eLf;1ck1_j;0 +I:J_9lFL]FoGVi5:lShdjn0 +V:J_9lFL]FoGVi5:lShdjn0 +S1 +R0 +R53 +8/hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/../../../verification_ip/interface_packages/wb_s_pkg/wb_s_pkg.sv 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index 00000000..bb70a3ea Binary files /dev/null and b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/work/optimized_debug_top_tb/_lib6_0.qtl differ diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/xwaves.sigs b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/xwaves.sigs new file mode 100644 index 00000000..d75f0a57 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/sim/xwaves.sigs @@ -0,0 +1,17 @@ + + + + + +# pragma uvmf custom additional begin + +Group All + +#Top level signals +hdl_top.* +#Add additional levels or individual signals as needed +hdl_top.*.* + +# pragma uvmf custom additional end + + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/subsys_sve.F b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/subsys_sve.F new file mode 100644 index 00000000..69b29dbd --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/subsys_sve.F @@ -0,0 +1,31 @@ + +// UVM ++incdir+${UVM_HOME}/src +${UVM_HOME}/src/uvm_pkg.sv + +// Common UVMF files +-f ${UVMF_HOME}/common/common_sve.f + +// BFM Files +-F ${UVMF_VIP_LIBRARY_HOME}/interface_packages/apb_m_pkg/apb_m_pkg_sve.F +-F ${UVMF_VIP_LIBRARY_HOME}/interface_packages/axi_m_pkg/axi_m_pkg_sve.F +-F ${UVMF_VIP_LIBRARY_HOME}/interface_packages/spi_s_pkg/spi_s_pkg_sve.F +-F ${UVMF_VIP_LIBRARY_HOME}/interface_packages/spi_m_pkg/spi_m_pkg_sve.F +-F ${UVMF_VIP_LIBRARY_HOME}/interface_packages/wb_s_pkg/wb_s_pkg_sve.F + +// Environment Files +-F ${UVMF_VIP_LIBRARY_HOME}/environment_packages/subsys_env_pkg/subsys_env_pkg_sve.F + +// Bench Files ++incdir+./tb/tests +./tb/tests/subsys_tests_pkg.sv + ++incdir+./tb/sequences +./tb/sequences/subsys_sequences_pkg.sv + ++incdir+./tb/parameters +./tb/parameters/subsys_parameters_pkg.sv + +./tb/testbench/hdl_top.sv +./tb/testbench/hvl_top.sv + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/tb/parameters/subsys_parameters_pkg.compile b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/tb/parameters/subsys_parameters_pkg.compile new file mode 100644 index 00000000..29e4d5fd --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/tb/parameters/subsys_parameters_pkg.compile @@ -0,0 +1,4 @@ +needs: + - $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg_hdl.compile +src: + - subsys_parameters_pkg.sv diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/tb/parameters/subsys_parameters_pkg.sv b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/tb/parameters/subsys_parameters_pkg.sv new file mode 100644 index 00000000..447327c9 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/tb/parameters/subsys_parameters_pkg.sv @@ -0,0 +1,42 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This package contains test level parameters +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// + + +package subsys_parameters_pkg; + + import uvmf_base_pkg_hdl::*; + + // pragma uvmf custom package_imports_additional begin + // pragma uvmf custom package_imports_additional end + + + // These parameters are used to uniquely identify each interface. The monitor_bfm and + // driver_bfm are placed into and retrieved from the uvm_config_db using these string + // names as the field_name. The parameter is also used to enable transaction viewing + // from the command line for selected interfaces using the UVM command line processing. + parameter string b1_apb_master_BFM = "b1_apb_master_BFM"; /* [0] */ + parameter string b1_axi_master1_BFM = "b1_axi_master1_BFM"; /* [1] */ + parameter string b1_axi_master2_BFM = "b1_axi_master2_BFM"; /* [2] */ + parameter string b1_spi_slave_BFM = "b1_spi_slave_BFM"; /* [3] */ + parameter string b2_spi_master_BFM = "b2_spi_master_BFM"; /* [4] */ + parameter string b2_wb_slave_BFM = "b2_wb_slave_BFM"; /* [5] */ + + // pragma uvmf custom package_item_additional begin + // pragma uvmf custom package_item_additional end + +endpackage + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/tb/parameters/subsys_parameters_pkg.vinfo b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/tb/parameters/subsys_parameters_pkg.vinfo new file mode 100644 index 00000000..63c1753f --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/tb/parameters/subsys_parameters_pkg.vinfo @@ -0,0 +1,2 @@ +@use $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg_hdl.vinfo +subsys_parameters_pkg.sv diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/tb/sequences/src/example_derived_test_sequence.svh b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/tb/sequences/src/example_derived_test_sequence.svh new file mode 100644 index 00000000..c690a827 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/tb/sequences/src/example_derived_test_sequence.svh @@ -0,0 +1,30 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +// +//---------------------------------------------------------------------- +// +// DESCRIPTION: This file contains the top level sequence used in example_derived_test. +// It is an example of a sequence that is extended from %(benchName)_bench_sequence_base +// and can override %(benchName)_bench_sequence_base. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// + +class example_derived_test_sequence extends subsys_bench_sequence_base; + + `uvm_object_utils( example_derived_test_sequence ); + + function new(string name = "" ); + super.new(name); + endfunction + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/tb/sequences/src/register_test_sequence.svh b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/tb/sequences/src/register_test_sequence.svh new file mode 100644 index 00000000..270c155d --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/tb/sequences/src/register_test_sequence.svh @@ -0,0 +1,61 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This file contains the top level sequence used in register_test. +// It uses the UVM built in register test. Specific UVM built-in tests can be +// selected in the body task. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// + +class register_test_sequence extends subsys_bench_sequence_base; + + `uvm_object_utils( register_test_sequence ); + + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + function new(string name = "" ); + super.new(name); + endfunction + + // **************************************************************************** + virtual task body(); + + // Reset the DUT + fork + // pragma uvmf custom register_test_reset begin + // UVMF_CHANGE_ME + // Select the desired wait_for_reset or provide custom mechanism. + // fork-join for this code block may be unnecessary based on your situation. + b1_apb_master_config.wait_for_reset(); + b1_axi_master1_config.wait_for_reset(); + b1_axi_master2_config.wait_for_reset(); + b1_spi_slave_config.wait_for_reset(); + b2_spi_master_config.wait_for_reset(); + b2_wb_slave_config.wait_for_reset(); + // pragma uvmf custom register_test_reset end + join + + // pragma uvmf custom register_test_setup begin + // UVMF_CHANGE_ME perform potentially necessary operations before running the sequence. + // pragma uvmf custom register_test_setup end + + // pragma uvmf custom register_test_operation begin + // UVMF_CHANGE_ME Perform your custom register test + // pragma uvmf custom register_test_operation end + + endtask + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/tb/sequences/src/subsys_bench_sequence_base.svh b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/tb/sequences/src/subsys_bench_sequence_base.svh new file mode 100644 index 00000000..5cb75e15 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/tb/sequences/src/subsys_bench_sequence_base.svh @@ -0,0 +1,176 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// Description: This file contains the top level and utility sequences +// used by test_top. It can be extended to create derivative top +// level sequences. +// +//---------------------------------------------------------------------- +// +//---------------------------------------------------------------------- +// + + +typedef subsys_env_configuration subsys_env_configuration_t; + +class subsys_bench_sequence_base extends uvmf_sequence_base #(uvm_sequence_item); + + `uvm_object_utils( subsys_bench_sequence_base ); + + // pragma uvmf custom sequences begin + +typedef subsys_env_sequence_base #( + .CONFIG_T(subsys_env_configuration_t) + ) + subsys_env_sequence_base_t; +rand subsys_env_sequence_base_t subsys_env_seq; + + + + // UVMF_CHANGE_ME : Instantiate, construct, and start sequences as needed to create stimulus scenarios. + // Instantiate sequences here + typedef apb_m_random_sequence b1_apb_master_random_seq_t; + b1_apb_master_random_seq_t b1_apb_master_random_seq; + typedef axi_m_random_sequence b1_axi_master1_random_seq_t; + b1_axi_master1_random_seq_t b1_axi_master1_random_seq; + typedef axi_m_random_sequence b1_axi_master2_random_seq_t; + b1_axi_master2_random_seq_t b1_axi_master2_random_seq; + typedef spi_s_responder_sequence b1_spi_slave_responder_seq_t; + b1_spi_slave_responder_seq_t b1_spi_slave_responder_seq; + typedef spi_m_random_sequence b2_spi_master_random_seq_t; + b2_spi_master_random_seq_t b2_spi_master_random_seq; + typedef wb_s_responder_sequence b2_wb_slave_responder_seq_t; + b2_wb_slave_responder_seq_t b2_wb_slave_responder_seq; + // pragma uvmf custom sequences end + + // Sequencer handles for each active interface in the environment + typedef apb_m_transaction b1_apb_master_transaction_t; + uvm_sequencer #(b1_apb_master_transaction_t) b1_apb_master_sequencer; + typedef axi_m_transaction b1_axi_master1_transaction_t; + uvm_sequencer #(b1_axi_master1_transaction_t) b1_axi_master1_sequencer; + typedef axi_m_transaction b1_axi_master2_transaction_t; + uvm_sequencer #(b1_axi_master2_transaction_t) b1_axi_master2_sequencer; + typedef spi_s_transaction b1_spi_slave_transaction_t; + uvm_sequencer #(b1_spi_slave_transaction_t) b1_spi_slave_sequencer; + typedef spi_m_transaction b2_spi_master_transaction_t; + uvm_sequencer #(b2_spi_master_transaction_t) b2_spi_master_sequencer; + typedef wb_s_transaction b2_wb_slave_transaction_t; + uvm_sequencer #(b2_wb_slave_transaction_t) b2_wb_slave_sequencer; + + + // Top level environment configuration handle + subsys_env_configuration_t top_configuration; + + // Configuration handles to access interface BFM's + apb_m_configuration b1_apb_master_config; + axi_m_configuration b1_axi_master1_config; + axi_m_configuration b1_axi_master2_config; + spi_s_configuration b1_spi_slave_config; + spi_m_configuration b2_spi_master_config; + wb_s_configuration b2_wb_slave_config; + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + // **************************************************************************** + function new( string name = "" ); + super.new( name ); + // Retrieve the configuration handles from the uvm_config_db + + // Retrieve top level configuration handle + if ( !uvm_config_db#(subsys_env_configuration_t)::get(null,UVMF_CONFIGURATIONS, "TOP_ENV_CONFIG",top_configuration) ) begin + `uvm_info("CFG", "*** FATAL *** uvm_config_db::get can not find TOP_ENV_CONFIG. Are you using an older UVMF release than what was used to generate this bench?",UVM_NONE); + `uvm_fatal("CFG", "uvm_config_db#(subsys_env_configuration_t)::get cannot find resource TOP_ENV_CONFIG"); + end + + // Retrieve config handles for all agents + if( !uvm_config_db #( apb_m_configuration )::get( null , UVMF_CONFIGURATIONS , b1_apb_master_BFM , b1_apb_master_config ) ) + `uvm_fatal("CFG" , "uvm_config_db #( apb_m_configuration )::get cannot find resource b1_apb_master_BFM" ) + if( !uvm_config_db #( axi_m_configuration )::get( null , UVMF_CONFIGURATIONS , b1_axi_master1_BFM , b1_axi_master1_config ) ) + `uvm_fatal("CFG" , "uvm_config_db #( axi_m_configuration )::get cannot find resource b1_axi_master1_BFM" ) + if( !uvm_config_db #( axi_m_configuration )::get( null , UVMF_CONFIGURATIONS , b1_axi_master2_BFM , b1_axi_master2_config ) ) + `uvm_fatal("CFG" , "uvm_config_db #( axi_m_configuration )::get cannot find resource b1_axi_master2_BFM" ) + if( !uvm_config_db #( spi_s_configuration )::get( null , UVMF_CONFIGURATIONS , b1_spi_slave_BFM , b1_spi_slave_config ) ) + `uvm_fatal("CFG" , "uvm_config_db #( spi_s_configuration )::get cannot find resource b1_spi_slave_BFM" ) + if( !uvm_config_db #( spi_m_configuration )::get( null , UVMF_CONFIGURATIONS , b2_spi_master_BFM , b2_spi_master_config ) ) + `uvm_fatal("CFG" , "uvm_config_db #( spi_m_configuration )::get cannot find resource b2_spi_master_BFM" ) + if( !uvm_config_db #( wb_s_configuration )::get( null , UVMF_CONFIGURATIONS , b2_wb_slave_BFM , b2_wb_slave_config ) ) + `uvm_fatal("CFG" , "uvm_config_db #( wb_s_configuration )::get cannot find resource b2_wb_slave_BFM" ) + + // Assign the sequencer handles from the handles within agent configurations + b1_apb_master_sequencer = b1_apb_master_config.get_sequencer(); + b1_axi_master1_sequencer = b1_axi_master1_config.get_sequencer(); + b1_axi_master2_sequencer = b1_axi_master2_config.get_sequencer(); + b1_spi_slave_sequencer = b1_spi_slave_config.get_sequencer(); + b2_spi_master_sequencer = b2_spi_master_config.get_sequencer(); + b2_wb_slave_sequencer = b2_wb_slave_config.get_sequencer(); + + + + // pragma uvmf custom new begin + // pragma uvmf custom new end + + endfunction + + // **************************************************************************** + virtual task body(); + // pragma uvmf custom body begin + + // Construct sequences here + + subsys_env_seq = subsys_env_sequence_base_t::type_id::create("subsys_env_seq"); + + b1_apb_master_random_seq = b1_apb_master_random_seq_t::type_id::create("b1_apb_master_random_seq"); + b1_axi_master1_random_seq = b1_axi_master1_random_seq_t::type_id::create("b1_axi_master1_random_seq"); + b1_axi_master2_random_seq = b1_axi_master2_random_seq_t::type_id::create("b1_axi_master2_random_seq"); + b1_spi_slave_responder_seq = b1_spi_slave_responder_seq_t::type_id::create("b1_spi_slave_responder_seq"); + b2_spi_master_random_seq = b2_spi_master_random_seq_t::type_id::create("b2_spi_master_random_seq"); + b2_wb_slave_responder_seq = b2_wb_slave_responder_seq_t::type_id::create("b2_wb_slave_responder_seq"); + fork + b1_apb_master_config.wait_for_reset(); + b1_axi_master1_config.wait_for_reset(); + b1_axi_master2_config.wait_for_reset(); + b1_spi_slave_config.wait_for_reset(); + b2_spi_master_config.wait_for_reset(); + b2_wb_slave_config.wait_for_reset(); + join + // Start RESPONDER sequences here + fork + b1_spi_slave_responder_seq.start(b1_spi_slave_sequencer); + b2_wb_slave_responder_seq.start(b2_wb_slave_sequencer); + join_none + // Start INITIATOR sequences here + fork + repeat (25) b1_apb_master_random_seq.start(b1_apb_master_sequencer); + repeat (25) b1_axi_master1_random_seq.start(b1_axi_master1_sequencer); + repeat (25) b1_axi_master2_random_seq.start(b1_axi_master2_sequencer); + repeat (25) b2_spi_master_random_seq.start(b2_spi_master_sequencer); + join + +subsys_env_seq.start(top_configuration.vsqr); + + // UVMF_CHANGE_ME : Extend the simulation XXX number of clocks after + // the last sequence to allow for the last sequence item to flow + // through the design. + fork + b1_apb_master_config.wait_for_num_clocks(400); + b1_axi_master1_config.wait_for_num_clocks(400); + b1_axi_master2_config.wait_for_num_clocks(400); + b1_spi_slave_config.wait_for_num_clocks(400); + b2_spi_master_config.wait_for_num_clocks(400); + b2_wb_slave_config.wait_for_num_clocks(400); + join + + // pragma uvmf custom body end + endtask + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/tb/sequences/subsys_sequences_pkg.compile b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/tb/sequences/subsys_sequences_pkg.compile new file mode 100644 index 00000000..9e332e90 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/tb/sequences/subsys_sequences_pkg.compile @@ -0,0 +1,11 @@ +needs: + - $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg.compile + - ../../../../verification_ip/interface_packages/apb_m_pkg/apb_m.compile + - ../../../../verification_ip/interface_packages/axi_m_pkg/axi_m.compile + - ../../../../verification_ip/interface_packages/spi_s_pkg/spi_s.compile + - ../../../../verification_ip/interface_packages/spi_m_pkg/spi_m.compile + - ../../../../verification_ip/interface_packages/wb_s_pkg/wb_s.compile + - ../../../../verification_ip/environment_packages/subsys_env_pkg/subsys_env_pkg.compile + - ../parameters/subsys_parameters_pkg.compile +src: + - subsys_sequences_pkg.sv diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/tb/sequences/subsys_sequences_pkg.sv b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/tb/sequences/subsys_sequences_pkg.sv new file mode 100644 index 00000000..2bb1e636 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/tb/sequences/subsys_sequences_pkg.sv @@ -0,0 +1,57 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This package includes all high level sequence classes used +// in the environment. These include utility sequences and top +// level sequences. +// +// CONTAINS: +// - +// - +// +//---------------------------------------------------------------------- +// +//---------------------------------------------------------------------- +// + +package subsys_sequences_pkg; + import uvm_pkg::*; + import uvmf_base_pkg::*; + import apb_m_pkg::*; + import apb_m_pkg_hdl::*; + import axi_m_pkg::*; + import axi_m_pkg_hdl::*; + import spi_s_pkg::*; + import spi_s_pkg_hdl::*; + import spi_m_pkg::*; + import spi_m_pkg_hdl::*; + import wb_s_pkg::*; + import wb_s_pkg_hdl::*; + import subsys_parameters_pkg::*; + import subsys_env_pkg::*; + `include "uvm_macros.svh" + + // pragma uvmf custom package_imports_additional begin + // pragma uvmf custom package_imports_additional end + + `include "src/subsys_bench_sequence_base.svh" + `include "src/register_test_sequence.svh" + `include "src/example_derived_test_sequence.svh" + + // pragma uvmf custom package_item_additional begin + // UVMF_CHANGE_ME : When adding new sequences to the src directory + // be sure to add the sequence file here so that it will be + // compiled as part of the sequence package. Be sure to place + // the new sequence after any base sequences of the new sequence. + // pragma uvmf custom package_item_additional end + +endpackage + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/tb/sequences/subsys_sequences_pkg.vinfo b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/tb/sequences/subsys_sequences_pkg.vinfo new file mode 100644 index 00000000..019ac065 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/tb/sequences/subsys_sequences_pkg.vinfo @@ -0,0 +1,10 @@ +@use $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg.vinfo +@use $UVMF_VIP_LIBRARY_HOME/interface_packages/apb_m_pkg/apb_m_pkg.vinfo +@use $UVMF_VIP_LIBRARY_HOME/interface_packages/axi_m_pkg/axi_m_pkg.vinfo +@use $UVMF_VIP_LIBRARY_HOME/interface_packages/spi_s_pkg/spi_s_pkg.vinfo +@use $UVMF_VIP_LIBRARY_HOME/interface_packages/spi_m_pkg/spi_m_pkg.vinfo +@use $UVMF_VIP_LIBRARY_HOME/interface_packages/wb_s_pkg/wb_s_pkg.vinfo +@use $UVMF_VIP_LIBRARY_HOME/environment_packages/subsys_env_pkg/subsys_env_pkg.vinfo +@use $UVMF_PROJECT_DIR/tb/parameters/subsys_parameters_pkg.vinfo ++incdir+@vinfodir +subsys_sequences_pkg.sv diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/tb/testbench/hdl_top.compile b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/tb/testbench/hdl_top.compile new file mode 100644 index 00000000..15ba4874 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/tb/testbench/hdl_top.compile @@ -0,0 +1,13 @@ +incdir: + - ${uvm_path}/src + - . +needs: + - $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg_hdl.compile + - ../parameters/subsys_parameters_pkg.compile + - ../../../../verification_ip/interface_packages/apb_m_pkg/apb_m_hdl.compile + - ../../../../verification_ip/interface_packages/axi_m_pkg/axi_m_hdl.compile + - ../../../../verification_ip/interface_packages/spi_s_pkg/spi_s_hdl.compile + - ../../../../verification_ip/interface_packages/spi_m_pkg/spi_m_hdl.compile + - ../../../../verification_ip/interface_packages/wb_s_pkg/wb_s_hdl.compile +src: + - hdl_top.sv diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/tb/testbench/hdl_top.sv b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/tb/testbench/hdl_top.sv new file mode 100644 index 00000000..14b291ba --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/tb/testbench/hdl_top.sv @@ -0,0 +1,137 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// Description: This top level module instantiates all synthesizable +// static content. This and tb_top.sv are the two top level modules +// of the simulation. +// +// This module instantiates the following: +// DUT: The Design Under Test +// Interfaces: Signal bundles that contain signals connected to DUT +// Driver BFM's: BFM's that actively drive interface signals +// Monitor BFM's: BFM's that passively monitor interface signals +// +//---------------------------------------------------------------------- + +//---------------------------------------------------------------------- +// + +module hdl_top; + +import subsys_parameters_pkg::*; +import uvmf_base_pkg_hdl::*; + + // pragma attribute hdl_top partition_module_xrtl +// pragma uvmf custom clock_generator begin + bit clk; + // Instantiate a clk driver + // tbx clkgen + initial begin + clk = 0; + #9ns; + forever begin + clk = ~clk; + #5ns; + end + end +// pragma uvmf custom clock_generator end + +// pragma uvmf custom reset_generator begin + bit rst; + // Instantiate a rst driver + // tbx clkgen + initial begin + rst = 0; + #200ns; + rst = 1; + end +// pragma uvmf custom reset_generator end + + // pragma uvmf custom module_item_additional begin + // pragma uvmf custom module_item_additional end + + // Instantiate the signal bundle, monitor bfm and driver bfm for each interface. + // The signal bundle, _if, contains signals to be connected to the DUT. + // The monitor, monitor_bfm, observes the bus, _if, and captures transactions. + // The driver, driver_bfm, drives transactions onto the bus, _if. + apb_m_if b1_apb_master_bus( + // pragma uvmf custom b1_apb_master_bus_connections begin + .pclk(clk), .presetn(rst) + // pragma uvmf custom b1_apb_master_bus_connections end + ); + axi_m_if b1_axi_master1_bus( + // pragma uvmf custom b1_axi_master1_bus_connections begin + .axi_clk(clk), .rst(rst) + // pragma uvmf custom b1_axi_master1_bus_connections end + ); + axi_m_if b1_axi_master2_bus( + // pragma uvmf custom b1_axi_master2_bus_connections begin + .axi_clk(clk), .rst(rst) + // pragma uvmf custom b1_axi_master2_bus_connections end + ); + spi_s_if b1_spi_slave_bus( + // pragma uvmf custom b1_spi_slave_bus_connections begin + .sck(clk), .rst(rst) + // pragma uvmf custom b1_spi_slave_bus_connections end + ); + spi_m_if b2_spi_master_bus( + // pragma uvmf custom b2_spi_master_bus_connections begin + .sck(clk), .rst(rst) + // pragma uvmf custom b2_spi_master_bus_connections end + ); + wb_s_if b2_wb_slave_bus( + // pragma uvmf custom b2_wb_slave_bus_connections begin + .clock(clk), .reset(rst) + // pragma uvmf custom b2_wb_slave_bus_connections end + ); + apb_m_monitor_bfm b1_apb_master_mon_bfm(b1_apb_master_bus.monitor_port); + axi_m_monitor_bfm b1_axi_master1_mon_bfm(b1_axi_master1_bus.monitor_port); + axi_m_monitor_bfm b1_axi_master2_mon_bfm(b1_axi_master2_bus.monitor_port); + spi_s_monitor_bfm b1_spi_slave_mon_bfm(b1_spi_slave_bus.monitor_port); + spi_m_monitor_bfm b2_spi_master_mon_bfm(b2_spi_master_bus.monitor_port); + wb_s_monitor_bfm b2_wb_slave_mon_bfm(b2_wb_slave_bus.monitor_port); + apb_m_driver_bfm b1_apb_master_drv_bfm(b1_apb_master_bus.initiator_port); + axi_m_driver_bfm b1_axi_master1_drv_bfm(b1_axi_master1_bus.initiator_port); + axi_m_driver_bfm b1_axi_master2_drv_bfm(b1_axi_master2_bus.initiator_port); + spi_s_driver_bfm b1_spi_slave_drv_bfm(b1_spi_slave_bus.responder_port); + spi_m_driver_bfm b2_spi_master_drv_bfm(b2_spi_master_bus.initiator_port); + wb_s_driver_bfm b2_wb_slave_drv_bfm(b2_wb_slave_bus.responder_port); + + // pragma uvmf custom dut_instantiation begin + // UVMF_CHANGE_ME : Add DUT and connect to signals in _bus interfaces listed above + // Instantiate your DUT here + // These DUT's instantiated to show verilog and vhdl instantiation + verilog_dut dut_verilog( .clk(clk), .rst(rst), .in_signal(vhdl_to_verilog_signal), .out_signal(verilog_to_vhdl_signal)); + vhdl_dut dut_vhdl ( .clk(clk), .rst(rst), .in_signal(verilog_to_vhdl_signal), .out_signal(vhdl_to_verilog_signal)); + // pragma uvmf custom dut_instantiation end + + initial begin // tbx vif_binding_block + import uvm_pkg::uvm_config_db; + // The monitor_bfm and driver_bfm for each interface is placed into the uvm_config_db. + // They are placed into the uvm_config_db using the string names defined in the parameters package. + // The string names are passed to the agent configurations by test_top through the top level configuration. + // They are retrieved by the agents configuration class for use by the agent. + uvm_config_db #( virtual apb_m_monitor_bfm )::set( null , UVMF_VIRTUAL_INTERFACES , b1_apb_master_BFM , b1_apb_master_mon_bfm ); + uvm_config_db #( virtual axi_m_monitor_bfm )::set( null , UVMF_VIRTUAL_INTERFACES , b1_axi_master1_BFM , b1_axi_master1_mon_bfm ); + uvm_config_db #( virtual axi_m_monitor_bfm )::set( null , UVMF_VIRTUAL_INTERFACES , b1_axi_master2_BFM , b1_axi_master2_mon_bfm ); + uvm_config_db #( virtual spi_s_monitor_bfm )::set( null , UVMF_VIRTUAL_INTERFACES , b1_spi_slave_BFM , b1_spi_slave_mon_bfm ); + uvm_config_db #( virtual spi_m_monitor_bfm )::set( null , UVMF_VIRTUAL_INTERFACES , b2_spi_master_BFM , b2_spi_master_mon_bfm ); + uvm_config_db #( virtual wb_s_monitor_bfm )::set( null , UVMF_VIRTUAL_INTERFACES , b2_wb_slave_BFM , b2_wb_slave_mon_bfm ); + uvm_config_db #( virtual apb_m_driver_bfm )::set( null , UVMF_VIRTUAL_INTERFACES , b1_apb_master_BFM , b1_apb_master_drv_bfm ); + uvm_config_db #( virtual axi_m_driver_bfm )::set( null , UVMF_VIRTUAL_INTERFACES , b1_axi_master1_BFM , b1_axi_master1_drv_bfm ); + uvm_config_db #( virtual axi_m_driver_bfm )::set( null , UVMF_VIRTUAL_INTERFACES , b1_axi_master2_BFM , b1_axi_master2_drv_bfm ); + uvm_config_db #( virtual spi_s_driver_bfm )::set( null , UVMF_VIRTUAL_INTERFACES , b1_spi_slave_BFM , b1_spi_slave_drv_bfm ); + uvm_config_db #( virtual spi_m_driver_bfm )::set( null , UVMF_VIRTUAL_INTERFACES , b2_spi_master_BFM , b2_spi_master_drv_bfm ); + uvm_config_db #( virtual wb_s_driver_bfm )::set( null , UVMF_VIRTUAL_INTERFACES , b2_wb_slave_BFM , b2_wb_slave_drv_bfm ); + end + +endmodule + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/tb/testbench/hdl_top.vinfo b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/tb/testbench/hdl_top.vinfo new file mode 100644 index 00000000..a1a47b9c --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/tb/testbench/hdl_top.vinfo @@ -0,0 +1,9 @@ +@use $UVMF_PROJECT_DIR/rtl/verilog/verilog_dut.vinfo +@use $UVMF_PROJECT_DIR/tb/parameters/subsys_parameters_pkg.vinfo +@use $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg_hdl.vinfo +@use $UVMF_VIP_LIBRARY_HOME/interface_packages/apb_m_pkg/apb_m_bfm.vinfo +@use $UVMF_VIP_LIBRARY_HOME/interface_packages/axi_m_pkg/axi_m_bfm.vinfo +@use $UVMF_VIP_LIBRARY_HOME/interface_packages/spi_s_pkg/spi_s_bfm.vinfo +@use $UVMF_VIP_LIBRARY_HOME/interface_packages/spi_m_pkg/spi_m_bfm.vinfo +@use $UVMF_VIP_LIBRARY_HOME/interface_packages/wb_s_pkg/wb_s_bfm.vinfo +hdl_top.sv diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/tb/testbench/hvl_top.compile b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/tb/testbench/hvl_top.compile new file mode 100644 index 00000000..83c8142f --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/tb/testbench/hvl_top.compile @@ -0,0 +1,7 @@ +incdir: + - ${uvm_path}/src + - . +needs: + - ../tests/subsys_tests_pkg.compile +src: + - hvl_top.sv diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/tb/testbench/hvl_top.sv b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/tb/testbench/hvl_top.sv new file mode 100644 index 00000000..ea97abbc --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/tb/testbench/hvl_top.sv @@ -0,0 +1,33 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +// +//---------------------------------------------------------------------- +// +// DESCRIPTION: This module loads the test package and starts the UVM phases. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// + +module hvl_top; + +import uvm_pkg::*; +import subsys_tests_pkg::*; + + // pragma uvmf custom module_item_additional begin + // pragma uvmf custom module_item_additional end + + initial begin + $timeformat(-9,3,"ns",5); + run_test(); + end + +endmodule + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/tb/testbench/hvl_top.vinfo b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/tb/testbench/hvl_top.vinfo new file mode 100644 index 00000000..2c837f2c --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/tb/testbench/hvl_top.vinfo @@ -0,0 +1,2 @@ +@use $UVMF_PROJECT_DIR/tb/tests/subsys_tests_pkg.vinfo +hvl_top.sv diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/tb/testbench/top_filelist_hdl.f b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/tb/testbench/top_filelist_hdl.f new file mode 100644 index 00000000..1e9dab65 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/tb/testbench/top_filelist_hdl.f @@ -0,0 +1,3 @@ +$UVMF_PROJECT_DIR/tb/testbench/hdl_top.sv +// pragma uvmf custom additional begin +// pragma uvmf custom additional end diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/tb/testbench/top_filelist_hvl.f b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/tb/testbench/top_filelist_hvl.f new file mode 100644 index 00000000..42383ab2 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/tb/testbench/top_filelist_hvl.f @@ -0,0 +1,3 @@ +$UVMF_PROJECT_DIR/tb/testbench/hvl_top.sv +// pragma uvmf custom additional begin +// pragma uvmf custom additional end diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/tb/tests/src/example_derived_test.svh b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/tb/tests/src/example_derived_test.svh new file mode 100644 index 00000000..88999ddc --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/tb/tests/src/example_derived_test.svh @@ -0,0 +1,43 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This test extends test_top and makes +// changes to test_top using the UVM factory type_override: +// +// Test scenario: +// This is a template test that can be used to create future tests. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// + +class example_derived_test extends test_top; + + `uvm_component_utils( example_derived_test ); + + function new( string name = "", uvm_component parent = null ); + super.new( name, parent ); + endfunction + + virtual function void build_phase(uvm_phase phase); + // The factory override below is an example of how to replace the subsys_bench_sequence_base + // sequence with the example_derived_test_sequence. + subsys_bench_sequence_base::type_id::set_type_override(example_derived_test_sequence::get_type()); + // Execute the build_phase of test_top AFTER all factory overrides have been created. + super.build_phase(phase); + // pragma uvmf custom configuration_settings_post_randomize begin + // UVMF_CHANGE_ME Test specific configuration values can be set here. + // The configuration structure has already been randomized. + // pragma uvmf custom configuration_settings_post_randomize end + endfunction + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/tb/tests/src/register_test.svh b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/tb/tests/src/register_test.svh new file mode 100644 index 00000000..f5f98e48 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/tb/tests/src/register_test.svh @@ -0,0 +1,40 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This test extends test_top and makes +// changes to test_top using the UVM factory type_override: +// +// Test scenario: +// This is a template test that can be used to create future tests. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// + +class register_test extends test_top; + + `uvm_component_utils( register_test ); + + function new( string name = "", uvm_component parent = null ); + super.new( name, parent ); + endfunction + + virtual function void build_phase(uvm_phase phase); + // The factory override below replaces the subsys_bench_sequence_base + // sequence with the register_test_sequence. + subsys_bench_sequence_base::type_id::set_type_override(register_test_sequence::get_type()); + // Execute the build_phase of test_top AFTER all factory overrides have been created. + super.build_phase(phase); + endfunction + + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/tb/tests/src/test_top.svh b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/tb/tests/src/test_top.svh new file mode 100644 index 00000000..5096c3b4 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/tb/tests/src/test_top.svh @@ -0,0 +1,86 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// Description: This top level UVM test is the base class for all +// future tests created for this project. +// +// This test class contains: +// Configuration: The top level configuration for the project. +// Environment: The top level environment for the project. +// Top_level_sequence: The top level sequence for the project. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// + +typedef subsys_env_configuration subsys_env_configuration_t; +typedef subsys_environment subsys_environment_t; + +class test_top extends uvmf_test_base #(.CONFIG_T(subsys_env_configuration_t), + .ENV_T(subsys_environment_t), + .TOP_LEVEL_SEQ_T(subsys_bench_sequence_base)); + + `uvm_component_utils( test_top ); + + + + string interface_names[] = { + b1_apb_master_BFM /* b1_apb_master [0] */ , + b1_axi_master1_BFM /* b1_axi_master1 [1] */ , + b1_axi_master2_BFM /* b1_axi_master2 [2] */ , + b1_spi_slave_BFM /* b1_spi_slave [3] */ , + b2_spi_master_BFM /* b2_spi_master [4] */ , + b2_wb_slave_BFM /* b2_wb_slave [5] */ +}; + +uvmf_active_passive_t interface_activities[] = { + ACTIVE /* b1_apb_master [0] */ , + ACTIVE /* b1_axi_master1 [1] */ , + ACTIVE /* b1_axi_master2 [2] */ , + ACTIVE /* b1_spi_slave [3] */ , + ACTIVE /* b2_spi_master [4] */ , + ACTIVE /* b2_wb_slave [5] */ }; + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + // **************************************************************************** + // FUNCTION: new() + // This is the standard systemVerilog constructor. All components are + // constructed in the build_phase to allow factory overriding. + // + function new( string name = "", uvm_component parent = null ); + super.new( name ,parent ); + endfunction + + + + // **************************************************************************** + // FUNCTION: build_phase() + // The construction of the configuration and environment classes is done in + // the build_phase of uvmf_test_base. Once the configuraton and environment + // classes are built then the initialize call is made to perform the + // following: + // Monitor and driver BFM virtual interface handle passing into agents + // Set the active/passive state for each agent + // Once this build_phase completes, the build_phase of the environment is + // executed which builds the agents. + // + virtual function void build_phase(uvm_phase phase); +// pragma uvmf custom build_phase_pre_super begin +// pragma uvmf custom build_phase_pre_super end + super.build_phase(phase); + // pragma uvmf custom configuration_settings_post_randomize begin + // pragma uvmf custom configuration_settings_post_randomize end + configuration.initialize(NA, "uvm_test_top.environment", interface_names, null, interface_activities); + endfunction + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/tb/tests/subsys_tests_pkg.compile b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/tb/tests/subsys_tests_pkg.compile new file mode 100644 index 00000000..106be50e --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/tb/tests/subsys_tests_pkg.compile @@ -0,0 +1,12 @@ +needs: + - $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg.compile + - ../../../../verification_ip/interface_packages/apb_m_pkg/apb_m.compile + - ../../../../verification_ip/interface_packages/axi_m_pkg/axi_m.compile + - ../../../../verification_ip/interface_packages/spi_s_pkg/spi_s.compile + - ../../../../verification_ip/interface_packages/spi_m_pkg/spi_m.compile + - ../../../../verification_ip/interface_packages/wb_s_pkg/wb_s.compile + - ../../../../verification_ip/environment_packages/subsys_env_pkg/subsys_env_pkg.compile + - ../parameters/subsys_parameters_pkg.compile + - ../sequences/subsys_sequences_pkg.compile +src: + - subsys_tests_pkg.sv diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/tb/tests/subsys_tests_pkg.sv b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/tb/tests/subsys_tests_pkg.sv new file mode 100644 index 00000000..8daddb39 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/tb/tests/subsys_tests_pkg.sv @@ -0,0 +1,60 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This package contains all tests currently written for +// the simulation project. Once compiled, any test can be selected +// from the vsim command line using +UVM_TESTNAME=yourTestNameHere +// +// CONTAINS: +// - +// - +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// + +package subsys_tests_pkg; + + import uvm_pkg::*; + import uvmf_base_pkg::*; + import subsys_parameters_pkg::*; + import subsys_env_pkg::*; + import subsys_sequences_pkg::*; + import apb_m_pkg::*; + import apb_m_pkg_hdl::*; + import axi_m_pkg::*; + import axi_m_pkg_hdl::*; + import spi_s_pkg::*; + import spi_s_pkg_hdl::*; + import spi_m_pkg::*; + import spi_m_pkg_hdl::*; + import wb_s_pkg::*; + import wb_s_pkg_hdl::*; + + + `include "uvm_macros.svh" + + // pragma uvmf custom package_imports_additional begin + // pragma uvmf custom package_imports_additional end + + `include "src/test_top.svh" + `include "src/register_test.svh" + `include "src/example_derived_test.svh" + + // pragma uvmf custom package_item_additional begin + // UVMF_CHANGE_ME : When adding new tests to the src directory + // be sure to add the test file here so that it will be + // compiled as part of the test package. Be sure to place + // the new test after any base tests of the new test. + // pragma uvmf custom package_item_additional end + +endpackage + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/tb/tests/subsys_tests_pkg.vinfo b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/tb/tests/subsys_tests_pkg.vinfo new file mode 100644 index 00000000..b50c9a39 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/tb/tests/subsys_tests_pkg.vinfo @@ -0,0 +1,11 @@ +@use $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg.vinfo +@use $UVMF_VIP_LIBRARY_HOME/interface_packages/apb_m_pkg/apb_m_pkg.vinfo +@use $UVMF_VIP_LIBRARY_HOME/interface_packages/axi_m_pkg/axi_m_pkg.vinfo +@use $UVMF_VIP_LIBRARY_HOME/interface_packages/spi_s_pkg/spi_s_pkg.vinfo +@use $UVMF_VIP_LIBRARY_HOME/interface_packages/spi_m_pkg/spi_m_pkg.vinfo +@use $UVMF_VIP_LIBRARY_HOME/interface_packages/wb_s_pkg/wb_s_pkg.vinfo +@use $UVMF_VIP_LIBRARY_HOME/environment_packages/subsys_env_pkg/subsys_env_pkg.vinfo +@use $UVMF_PROJECT_DIR/tb/parameters/subsys_parameters_pkg.vinfo +@use $UVMF_PROJECT_DIR/tb/sequences/subsys_sequences_pkg.vinfo ++incdir+@vinfodir +subsys_tests_pkg.sv diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/yaml/subsys_bench.yaml b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/yaml/subsys_bench.yaml new file mode 100644 index 00000000..528bc098 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/project_benches/subsys/yaml/subsys_bench.yaml @@ -0,0 +1,25 @@ +uvmf: + benches: + subsys: + active_passive: + - bfm_name: b1_apb_master + value: ACTIVE + - bfm_name: b1_axi_master1 + value: ACTIVE + - bfm_name: b1_axi_master2 + value: ACTIVE + - bfm_name: b1_spi_slave + value: ACTIVE + - bfm_name: b2_spi_master + value: ACTIVE + - bfm_name: b2_wb_slave + value: ACTIVE + active_passive_default: ACTIVE + clock_half_period: 5ns + clock_phase_offset: 9ns + existing_library_component: 'True' + interface_params: [] + reset_assertion_level: 'False' + reset_duration: 200ns + top_env: subsys + use_dpi_link: 'False' diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/environment_packages/block_1_env_pkg/.project b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/environment_packages/block_1_env_pkg/.project new file mode 100644 index 00000000..db755a2e --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/environment_packages/block_1_env_pkg/.project @@ -0,0 +1,32 @@ + + + block_1_env_pkg + + + + + + org.python.pydev.PyDevBuilder + + + + + net.sf.sveditor.core.SVProjectBuilder + + + + + + net.sf.sveditor.core.SVNature + org.python.pydev.pythonNature + + + + + + UVMF_VIP_LIBRARY_HOME + $%7BPARENT-2-PROJECT_LOC%7D + + + + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/environment_packages/block_1_env_pkg/.svproject b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/environment_packages/block_1_env_pkg/.svproject new file mode 100644 index 00000000..148d5d69 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/environment_packages/block_1_env_pkg/.svproject @@ -0,0 +1,16 @@ + + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/environment_packages/block_1_env_pkg/Makefile b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/environment_packages/block_1_env_pkg/Makefile new file mode 100644 index 00000000..d0b7efd8 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/environment_packages/block_1_env_pkg/Makefile @@ -0,0 +1,56 @@ +# block_1 environment packages source and make target + +# pragma uvmf custom additional begin +# pragma uvmf custom additional end + +# Include all requisite sub-environment package targets for this bench + +block_1_ENV_PKG =\ + $(UVMF_VIP_LIBRARY_HOME)/environment_packages/block_1_env_pkg/block_1_env_pkg.sv + +COMP_block_1_PKG_TGT_0 = q_comp_block_1_env_pkg +COMP_block_1_PKG_TGT_1 = v_comp_block_1_env_pkg +COMP_block_1_PKG_TGT = $(COMP_block_1_PKG_TGT_$(USE_VELOCE)) + +comp_block_1_env_pkg: $(COMP_block_1_PKG_TGT) + +q_comp_block_1_env_pkg: + $(HVL_COMP_CMD) +incdir+$(UVMF_VIP_LIBRARY_HOME)/environment_packages/block_1_env_pkg $(block_1_ENV_PKG) + +v_comp_block_1_env_pkg: q_comp_block_1_env_pkg + $(VELANALYZE_HVL_CMD) +incdir+$(UVMF_VIP_LIBRARY_HOME)/environment_packages/block_1_env_pkg $(block_1_ENV_PKG) + + + +ifeq ($(MTI_VCO_MODE),64) + GCC_COMP_ARCH = -m64 +else + GCC_COMP_ARCH = -m32 +endif + +export block_1_ENV_DPI_SRC ?= $(UVMF_VIP_LIBRARY_HOME)/environment_packages/block_1_env_pkg/dpi + +C_FILE_COMPILE_LIST_block_1_env_pkg = \ + +O_FILE_COMPILE_LIST_block_1_env_pkg = $(notdir $(C_FILE_COMPILE_LIST_block_1_env_pkg:.c=.o)) + +GCC_COMP_ARGS_block_1_env_pkg += -I$(block_1_ENV_DPI_SRC) \ + -fPIC + +GCC_COMP_ARGS_block_1_env_pkg += $(block_1_ENV_GCC_COMP_ARGUMENTS) + +GCC_LINK_ARGS_block_1_env_pkg += \ + \ + -o .so + +comp_block_1_env_pkg_c_files: + @echo "--------------------------------" + @echo "Compiling Environment C source" + @echo "--------------------------------" + gcc $(GCC_COMP_ARCH) $(GCC_COMP_ARGS_block_1_env_pkg) $(C_FILE_COMPILE_LIST_block_1_env_pkg) + @echo "--------------------------------" + @echo "Linking Environment C objects into a shared object" + @echo "--------------------------------" + gcc $(GCC_COMP_ARCH) $(GCC_LINK_ARGS_block_1_env_pkg) $(O_FILE_COMPILE_LIST_block_1_env_pkg) + @echo "--------------------------------" + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/environment_packages/block_1_env_pkg/block_1_env_pkg.compile b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/environment_packages/block_1_env_pkg/block_1_env_pkg.compile new file mode 100644 index 00000000..4c6f4844 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/environment_packages/block_1_env_pkg/block_1_env_pkg.compile @@ -0,0 +1,9 @@ +needs: + - $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg.compile + - ../../../verification_ip/interface_packages/apb_m_pkg/apb_m_hvl.compile + - ../../../verification_ip/interface_packages/axi_m_pkg/axi_m_hvl.compile + - ../../../verification_ip/interface_packages/spi_s_pkg/spi_s_hvl.compile + +src: + - block_1_env_pkg.sv + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/environment_packages/block_1_env_pkg/block_1_env_pkg.sv b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/environment_packages/block_1_env_pkg/block_1_env_pkg.sv new file mode 100644 index 00000000..490ba8f1 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/environment_packages/block_1_env_pkg/block_1_env_pkg.sv @@ -0,0 +1,63 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// PACKAGE: This file defines all of the files contained in the +// environment package that will run on the host simulator. +// +// CONTAINS: +// - +// - +// - +// - +// - +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +package block_1_env_pkg; + + import uvm_pkg::*; + `include "uvm_macros.svh" + import uvmf_base_pkg::*; + import apb_m_pkg::*; + import apb_m_pkg_hdl::*; + import axi_m_pkg::*; + import axi_m_pkg_hdl::*; + import spi_s_pkg::*; + import spi_s_pkg_hdl::*; + + `uvm_analysis_imp_decl(_axi_2_ae) + `uvm_analysis_imp_decl(_apb_ae) + `uvm_analysis_imp_decl(_axi_1_ae) + `uvm_analysis_imp_decl(_sco_from_pre_ae) + `uvm_analysis_imp_decl(_spi_ae) + + // pragma uvmf custom package_imports_additional begin + // pragma uvmf custom package_imports_additional end + + // Parameters defined as HVL parameters + + `include "src/block_1_env_typedefs.svh" + `include "src/block_1_env_configuration.svh" + `include "src/block_1_predictor.svh" + `include "src/block_1_scoreboard.svh" + `include "src/block_1_environment.svh" + `include "src/block_1_env_sequence_base.svh" + + // pragma uvmf custom package_item_additional begin + // UVMF_CHANGE_ME : When adding new environment level sequences to the src directory + // be sure to add the sequence file here so that it will be + // compiled as part of the environment package. Be sure to place + // the new sequence after any base sequence of the new sequence. + // pragma uvmf custom package_item_additional end + +endpackage + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/environment_packages/block_1_env_pkg/block_1_env_pkg.vinfo b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/environment_packages/block_1_env_pkg/block_1_env_pkg.vinfo new file mode 100644 index 00000000..c2733a14 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/environment_packages/block_1_env_pkg/block_1_env_pkg.vinfo @@ -0,0 +1,6 @@ +@use $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg.vinfo +@use $UVMF_VIP_LIBRARY_HOME/interface_packages/apb_m_pkg/apb_m_pkg.vinfo +@use $UVMF_VIP_LIBRARY_HOME/interface_packages/axi_m_pkg/axi_m_pkg.vinfo +@use $UVMF_VIP_LIBRARY_HOME/interface_packages/spi_s_pkg/spi_s_pkg.vinfo ++incdir+@vinfodir +block_1_env_pkg.sv diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/environment_packages/block_1_env_pkg/block_1_env_pkg_sve.F b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/environment_packages/block_1_env_pkg/block_1_env_pkg_sve.F new file mode 100644 index 00000000..c6edfc2e --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/environment_packages/block_1_env_pkg/block_1_env_pkg_sve.F @@ -0,0 +1,12 @@ + +// UVM ++incdir+${UVM_HOME}/src +${UVM_HOME}/src/uvm_pkg.sv + +// Common UVMF files +-f ${UVMF_HOME}/common/common_sve.f + +// Sub-Environments + ++incdir+. +./block_1_env_pkg.sv diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/environment_packages/block_1_env_pkg/compile.do b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/environment_packages/block_1_env_pkg/compile.do new file mode 100644 index 00000000..bac5463f --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/environment_packages/block_1_env_pkg/compile.do @@ -0,0 +1,12 @@ +# Tcl do file for compile of block_1 interface + +# pragma uvmf custom additional begin +# pragma uvmf custom additional end + + + +quietly set cmd [format "vlog -timescale 1ps/1ps +incdir+%s/environment_packages/block_1_env_pkg" $env(UVMF_VIP_LIBRARY_HOME)] +quietly set cmd [format "%s %s/environment_packages/block_1_env_pkg/block_1_env_pkg.sv" $cmd $env(UVMF_VIP_LIBRARY_HOME)] +eval $cmd + + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/environment_packages/block_1_env_pkg/src/block_1_env_configuration.svh b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/environment_packages/block_1_env_pkg/src/block_1_env_configuration.svh new file mode 100644 index 00000000..56f80daa --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/environment_packages/block_1_env_pkg/src/block_1_env_configuration.svh @@ -0,0 +1,162 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: THis is the configuration for the block_1 environment. +// it contains configuration classes for each agent. It also contains +// environment level configuration variables. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class block_1_env_configuration +extends uvmf_environment_configuration_base; + + `uvm_object_utils( block_1_env_configuration ) + + bit has_scoreboard; + +//Constraints for the configuration variables: + + + covergroup block_1_configuration_cg; + // pragma uvmf custom covergroup begin + option.auto_bin_max=1024; + coverpoint has_scoreboard; + // pragma uvmf custom covergroup end + endgroup + + + typedef apb_m_configuration apb_master_config_t; + rand apb_master_config_t apb_master_config; + + typedef axi_m_configuration axi_master1_config_t; + rand axi_master1_config_t axi_master1_config; + + typedef axi_m_configuration axi_master2_config_t; + rand axi_master2_config_t axi_master2_config; + + typedef spi_s_configuration spi_slave_config_t; + rand spi_slave_config_t spi_slave_config; + + + + + typedef uvmf_virtual_sequencer_base #(.CONFIG_T(block_1_env_configuration)) block_1_vsqr_t; + block_1_vsqr_t vsqr; + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + +// **************************************************************************** +// FUNCTION : new() +// This function is the standard SystemVerilog constructor. +// This function constructs the configuration object for each agent in the environment. +// + function new( string name = "" ); + super.new( name ); + + + apb_master_config = apb_master_config_t::type_id::create("apb_master_config"); + axi_master1_config = axi_master1_config_t::type_id::create("axi_master1_config"); + axi_master2_config = axi_master2_config_t::type_id::create("axi_master2_config"); + spi_slave_config = spi_slave_config_t::type_id::create("spi_slave_config"); + + + block_1_configuration_cg=new; + `uvm_warning("COVERAGE_MODEL_REVIEW", "A covergroup has been constructed which may need review because of either generation or re-generation with merging. Please note that configuration variables added as a result of re-generation and merging are not automatically added to the covergroup. Remove this warning after the covergroup has been reviewed.") + + // pragma uvmf custom new begin + // pragma uvmf custom new end + endfunction + +// **************************************************************************** +// FUNCTION : set_vsqr() +// This function is used to assign the vsqr handle. + virtual function void set_vsqr( block_1_vsqr_t vsqr); + this.vsqr = vsqr; + endfunction : set_vsqr + +// **************************************************************************** +// FUNCTION: post_randomize() +// This function is automatically called after the randomize() function +// is executed. +// + function void post_randomize(); + super.post_randomize(); + // pragma uvmf custom post_randomize begin + // pragma uvmf custom post_randomize end + endfunction + +// **************************************************************************** +// FUNCTION: convert2string() +// This function converts all variables in this class to a single string for +// logfile reporting. This function concatenates the convert2string result for +// each agent configuration in this configuration class. +// + virtual function string convert2string(); + // pragma uvmf custom convert2string begin + return { + $sformatf("has_scoreboard:0x%x ",has_scoreboard), + "\n", apb_master_config.convert2string, + "\n", axi_master1_config.convert2string, + "\n", axi_master2_config.convert2string, + "\n", spi_slave_config.convert2string + + + }; + // pragma uvmf custom convert2string end + endfunction +// **************************************************************************** +// FUNCTION: initialize(); +// This function configures each interface agents configuration class. The +// sim level determines the active/passive state of the agent. The environment_path +// identifies the hierarchy down to and including the instantiation name of the +// environment for this configuration class. Each instance of the environment +// has its own configuration class. The string interface names are used by +// the agent configurations to identify the virtual interface handle to pull from +// the uvm_config_db. +// + function void initialize(uvmf_sim_level_t sim_level, + string environment_path, + string interface_names[], + uvm_reg_block register_model = null, + uvmf_active_passive_t interface_activity[] = {} + ); + + super.initialize(sim_level, environment_path, interface_names, register_model, interface_activity); + + + + // Interface initialization for local agents + apb_master_config.initialize( interface_activity[0], {environment_path,".apb_master"}, interface_names[0]); + apb_master_config.initiator_responder = INITIATOR; + // apb_master_config.has_coverage = 1; + axi_master1_config.initialize( interface_activity[1], {environment_path,".axi_master1"}, interface_names[1]); + axi_master1_config.initiator_responder = INITIATOR; + // axi_master1_config.has_coverage = 1; + axi_master2_config.initialize( interface_activity[2], {environment_path,".axi_master2"}, interface_names[2]); + axi_master2_config.initiator_responder = INITIATOR; + // axi_master2_config.has_coverage = 1; + spi_slave_config.initialize( interface_activity[3], {environment_path,".spi_slave"}, interface_names[3]); + spi_slave_config.initiator_responder = RESPONDER; + // spi_slave_config.has_coverage = 1; + + + + + + // pragma uvmf custom initialize begin + // pragma uvmf custom initialize end + + endfunction + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/environment_packages/block_1_env_pkg/src/block_1_env_sequence_base.svh b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/environment_packages/block_1_env_pkg/src/block_1_env_sequence_base.svh new file mode 100644 index 00000000..949ecd3c --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/environment_packages/block_1_env_pkg/src/block_1_env_sequence_base.svh @@ -0,0 +1,83 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This file contains environment level sequences that will +// be reused from block to top level simulations. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class block_1_env_sequence_base #( + type CONFIG_T + ) extends uvmf_virtual_sequence_base #(.CONFIG_T(CONFIG_T)); + + + `uvm_object_param_utils( block_1_env_sequence_base #( + CONFIG_T + ) ); + + +// This block_1_env_sequence_base contains a handle to a block_1_env_configuration object +// named configuration. This configuration variable contains a handle to each +// sequencer within each agent within this environment and any sub-environments. +// The configuration object handle is automatically assigned in the pre_body in the +// base class of this sequence. The configuration handle is retrieved from the +// virtual sequencer that this sequence is started on. +// Available sequencer handles within the environment configuration: + + // Initiator agent sequencers in block_1_environment: + // configuration.apb_master_config.sequencer + // configuration.axi_master1_config.sequencer + // configuration.axi_master2_config.sequencer + + // Responder agent sequencers in block_1_environment: + // configuration.spi_slave_config.sequencer + + + typedef apb_m_random_sequence apb_master_random_sequence_t; + apb_master_random_sequence_t apb_master_rand_seq; + + typedef axi_m_random_sequence axi_master1_random_sequence_t; + axi_master1_random_sequence_t axi_master1_rand_seq; + + typedef axi_m_random_sequence axi_master2_random_sequence_t; + axi_master2_random_sequence_t axi_master2_rand_seq; + + + + + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + function new(string name = "" ); + super.new(name); + apb_master_rand_seq = apb_master_random_sequence_t::type_id::create("apb_master_rand_seq"); + axi_master1_rand_seq = axi_master1_random_sequence_t::type_id::create("axi_master1_rand_seq"); + axi_master2_rand_seq = axi_master2_random_sequence_t::type_id::create("axi_master2_rand_seq"); + + + endfunction + + virtual task body(); + + if ( configuration.apb_master_config.sequencer != null ) + repeat (25) apb_master_rand_seq.start(configuration.apb_master_config.sequencer); + if ( configuration.axi_master1_config.sequencer != null ) + repeat (25) axi_master1_rand_seq.start(configuration.axi_master1_config.sequencer); + if ( configuration.axi_master2_config.sequencer != null ) + repeat (25) axi_master2_rand_seq.start(configuration.axi_master2_config.sequencer); + + + endtask + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/environment_packages/block_1_env_pkg/src/block_1_env_typedefs.svh b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/environment_packages/block_1_env_pkg/src/block_1_env_typedefs.svh new file mode 100644 index 00000000..9814bd58 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/environment_packages/block_1_env_pkg/src/block_1_env_typedefs.svh @@ -0,0 +1,20 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: +// This file contains defines and typedefs to be compiled for use in +// the environment package. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// + + + // pragma uvmf custom additional begin + // pragma uvmf custom additional end + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/environment_packages/block_1_env_pkg/src/block_1_environment.svh b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/environment_packages/block_1_env_pkg/src/block_1_environment.svh new file mode 100644 index 00000000..f8fc649f --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/environment_packages/block_1_env_pkg/src/block_1_environment.svh @@ -0,0 +1,145 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This environment contains all agents, predictors and +// scoreboards required for the block level design. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// + +class block_1_environment extends uvmf_environment_base #( + .CONFIG_T( block_1_env_configuration + )); + `uvm_component_utils( block_1_environment ) + + + + uvm_analysis_port #(apb_m_transaction) apb_master_ap; + uvm_analysis_port #(axi_m_transaction) axi_master1_ap; + uvm_analysis_port #(axi_m_transaction) axi_master2_ap; + uvm_analysis_port #(spi_s_transaction) spi_slave_ap; + + + typedef apb_m_agent apb_master_t; + apb_master_t apb_master; + + typedef axi_m_agent axi_master1_t; + axi_master1_t axi_master1; + + typedef axi_m_agent axi_master2_t; + axi_master2_t axi_master2; + + typedef spi_s_agent spi_slave_t; + spi_slave_t spi_slave; + + + + + typedef block_1_predictor #( + .CONFIG_T(CONFIG_T) + ) block_1_pred_t; + block_1_pred_t block_1_pred; + typedef block_1_scoreboard #( + .CONFIG_T(CONFIG_T) + ) block_1_sb_t; + block_1_sb_t block_1_sb; + + + + + typedef uvmf_virtual_sequencer_base #(.CONFIG_T(block_1_env_configuration)) block_1_vsqr_t; + block_1_vsqr_t vsqr; + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + +// **************************************************************************** +// FUNCTION : new() +// This function is the standard SystemVerilog constructor. +// + function new( string name = "", uvm_component parent = null ); + super.new( name, parent ); + endfunction + +// **************************************************************************** +// FUNCTION: build_phase() +// This function builds all components within this environment. +// + virtual function void build_phase(uvm_phase phase); +// pragma uvmf custom build_phase_pre_super begin +// pragma uvmf custom build_phase_pre_super end + super.build_phase(phase); + apb_master_ap = new("apb_master_ap",this); + axi_master1_ap = new("axi_master1_ap",this); + axi_master2_ap = new("axi_master2_ap",this); + spi_slave_ap = new("spi_slave_ap",this); + apb_master = apb_master_t::type_id::create("apb_master",this); + apb_master.set_config(configuration.apb_master_config); + axi_master1 = axi_master1_t::type_id::create("axi_master1",this); + axi_master1.set_config(configuration.axi_master1_config); + axi_master2 = axi_master2_t::type_id::create("axi_master2",this); + axi_master2.set_config(configuration.axi_master2_config); + spi_slave = spi_slave_t::type_id::create("spi_slave",this); + spi_slave.set_config(configuration.spi_slave_config); + block_1_pred = block_1_pred_t::type_id::create("block_1_pred",this); + block_1_pred.configuration = configuration; + block_1_sb = block_1_sb_t::type_id::create("block_1_sb",this); + block_1_sb.configuration = configuration; + + vsqr = block_1_vsqr_t::type_id::create("vsqr", this); + vsqr.set_config(configuration); + configuration.set_vsqr(vsqr); + + // pragma uvmf custom build_phase begin + // pragma uvmf custom build_phase end + endfunction + +// **************************************************************************** +// FUNCTION: connect_phase() +// This function makes all connections within this environment. Connections +// typically inclue agent to predictor, predictor to scoreboard and scoreboard +// to agent. +// + virtual function void connect_phase(uvm_phase phase); +// pragma uvmf custom connect_phase_pre_super begin +// pragma uvmf custom connect_phase_pre_super end + super.connect_phase(phase); + spi_slave.monitored_ap.connect(block_1_sb.spi_ae); + apb_master.monitored_ap.connect(block_1_pred.apb_ae); + axi_master1.monitored_ap.connect(block_1_pred.axi_1_ae); + axi_master2.monitored_ap.connect(block_1_pred.axi_2_ae); + block_1_pred.pre_to_sco_ap.connect(block_1_sb.sco_from_pre_ae); + apb_master.monitored_ap.connect(apb_master_ap); + axi_master1.monitored_ap.connect(axi_master1_ap); + axi_master2.monitored_ap.connect(axi_master2_ap); + spi_slave.monitored_ap.connect(spi_slave_ap); + // pragma uvmf custom reg_model_connect_phase begin + // pragma uvmf custom reg_model_connect_phase end + endfunction + +// **************************************************************************** +// FUNCTION: end_of_simulation_phase() +// This function is executed just prior to executing run_phase. This function +// was added to the environment to sample environment configuration settings +// just before the simulation exits time 0. The configuration structure is +// randomized in the build phase before the environment structure is constructed. +// Configuration variables can be customized after randomization in the build_phase +// of the extended test. +// If a sequence modifies values in the configuration structure then the sequence is +// responsible for sampling the covergroup in the configuration if required. +// + virtual function void start_of_simulation_phase(uvm_phase phase); + configuration.block_1_configuration_cg.sample(); + endfunction + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/environment_packages/block_1_env_pkg/src/block_1_predictor.svh b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/environment_packages/block_1_env_pkg/src/block_1_predictor.svh new file mode 100644 index 00000000..c81a2e81 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/environment_packages/block_1_env_pkg/src/block_1_predictor.svh @@ -0,0 +1,176 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +// +//---------------------------------------------------------------------- +// +// DESCRIPTION: This analysis component contains analysis_exports for receiving +// data and analysis_ports for sending data. +// +// This analysis component has the following analysis_exports that receive the +// listed transaction type. +// +// axi_2_ae receives transactions of type axi_m_transaction +// apb_ae receives transactions of type apb_m_transaction +// axi_1_ae receives transactions of type axi_m_transaction +// +// This analysis component has the following analysis_ports that can broadcast +// the listed transaction type. +// +// pre_to_sco_ap broadcasts transactions of type spi_s_transaction +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// + +class block_1_predictor #( + type CONFIG_T, + type BASE_T = uvm_component + ) extends BASE_T; + + // Factory registration of this class + `uvm_component_param_utils( block_1_predictor #( + CONFIG_T, + BASE_T + )) + + + // Instantiate a handle to the configuration of the environment in which this component resides + CONFIG_T configuration; + + + // Instantiate the analysis exports + uvm_analysis_imp_axi_2_ae #(axi_m_transaction, block_1_predictor #( + .CONFIG_T(CONFIG_T), + .BASE_T(BASE_T) + )) axi_2_ae; + uvm_analysis_imp_apb_ae #(apb_m_transaction, block_1_predictor #( + .CONFIG_T(CONFIG_T), + .BASE_T(BASE_T) + )) apb_ae; + uvm_analysis_imp_axi_1_ae #(axi_m_transaction, block_1_predictor #( + .CONFIG_T(CONFIG_T), + .BASE_T(BASE_T) + )) axi_1_ae; + + + // Instantiate the analysis ports + uvm_analysis_port #(spi_s_transaction) pre_to_sco_ap; + + + // Transaction variable for predicted values to be sent out pre_to_sco_ap + // Once a transaction is sent through an analysis_port, another transaction should + // be constructed for the next predicted transaction. + typedef spi_s_transaction pre_to_sco_ap_output_transaction_t; + pre_to_sco_ap_output_transaction_t pre_to_sco_ap_output_transaction; + // Code for sending output transaction out through pre_to_sco_ap + // pre_to_sco_ap.write(pre_to_sco_ap_output_transaction); + + // Define transaction handles for debug visibility + axi_m_transaction axi_2_ae_debug; + apb_m_transaction apb_ae_debug; + axi_m_transaction axi_1_ae_debug; + + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + // FUNCTION: new + function new(string name, uvm_component parent); + super.new(name,parent); + `uvm_warning("PREDICTOR_REVIEW", "This predictor has been created either through generation or re-generation with merging. Remove this warning after the predictor has been reviewed.") + // pragma uvmf custom new begin + // pragma uvmf custom new end + endfunction + + // FUNCTION: build_phase + virtual function void build_phase (uvm_phase phase); + + axi_2_ae = new("axi_2_ae", this); + apb_ae = new("apb_ae", this); + axi_1_ae = new("axi_1_ae", this); + pre_to_sco_ap =new("pre_to_sco_ap", this ); + // pragma uvmf custom build_phase begin + // pragma uvmf custom build_phase end + endfunction + + // FUNCTION: write_axi_2_ae + // Transactions received through axi_2_ae initiate the execution of this function. + // This function performs prediction of DUT output values based on DUT input, configuration and state + virtual function void write_axi_2_ae(axi_m_transaction t); + // pragma uvmf custom axi_2_ae_predictor begin + axi_2_ae_debug = t; + `uvm_info("PRED", "Transaction Received through axi_2_ae", UVM_MEDIUM) + `uvm_info("PRED", {" Data: ",t.convert2string()}, UVM_FULL) + // Construct one of each output transaction type. + pre_to_sco_ap_output_transaction = pre_to_sco_ap_output_transaction_t::type_id::create("pre_to_sco_ap_output_transaction"); + // UVMF_CHANGE_ME: Implement predictor model here. + `uvm_info("UNIMPLEMENTED_PREDICTOR_MODEL", "******************************************************************************************************",UVM_NONE) + `uvm_info("UNIMPLEMENTED_PREDICTOR_MODEL", "UVMF_CHANGE_ME: The block_1_predictor::write_axi_2_ae function needs to be completed with DUT prediction model",UVM_NONE) + `uvm_info("UNIMPLEMENTED_PREDICTOR_MODEL", "******************************************************************************************************",UVM_NONE) + + // Code for sending output transaction out through pre_to_sco_ap + // Please note that each broadcasted transaction should be a different object than previously + // broadcasted transactions. Creation of a different object is done by constructing the transaction + // using either new() or create(). Broadcasting a transaction object more than once to either the + // same subscriber or multiple subscribers will result in unexpected and incorrect behavior. + pre_to_sco_ap.write(pre_to_sco_ap_output_transaction); + // pragma uvmf custom axi_2_ae_predictor end + endfunction + + // FUNCTION: write_apb_ae + // Transactions received through apb_ae initiate the execution of this function. + // This function performs prediction of DUT output values based on DUT input, configuration and state + virtual function void write_apb_ae(apb_m_transaction t); + // pragma uvmf custom apb_ae_predictor begin + apb_ae_debug = t; + `uvm_info("PRED", "Transaction Received through apb_ae", UVM_MEDIUM) + `uvm_info("PRED", {" Data: ",t.convert2string()}, UVM_FULL) + // Construct one of each output transaction type. + pre_to_sco_ap_output_transaction = pre_to_sco_ap_output_transaction_t::type_id::create("pre_to_sco_ap_output_transaction"); + // UVMF_CHANGE_ME: Implement predictor model here. + `uvm_info("UNIMPLEMENTED_PREDICTOR_MODEL", "******************************************************************************************************",UVM_NONE) + `uvm_info("UNIMPLEMENTED_PREDICTOR_MODEL", "UVMF_CHANGE_ME: The block_1_predictor::write_apb_ae function needs to be completed with DUT prediction model",UVM_NONE) + `uvm_info("UNIMPLEMENTED_PREDICTOR_MODEL", "******************************************************************************************************",UVM_NONE) + + // Code for sending output transaction out through pre_to_sco_ap + // Please note that each broadcasted transaction should be a different object than previously + // broadcasted transactions. Creation of a different object is done by constructing the transaction + // using either new() or create(). Broadcasting a transaction object more than once to either the + // same subscriber or multiple subscribers will result in unexpected and incorrect behavior. + pre_to_sco_ap.write(pre_to_sco_ap_output_transaction); + // pragma uvmf custom apb_ae_predictor end + endfunction + + // FUNCTION: write_axi_1_ae + // Transactions received through axi_1_ae initiate the execution of this function. + // This function performs prediction of DUT output values based on DUT input, configuration and state + virtual function void write_axi_1_ae(axi_m_transaction t); + // pragma uvmf custom axi_1_ae_predictor begin + axi_1_ae_debug = t; + `uvm_info("PRED", "Transaction Received through axi_1_ae", UVM_MEDIUM) + `uvm_info("PRED", {" Data: ",t.convert2string()}, UVM_FULL) + // Construct one of each output transaction type. + pre_to_sco_ap_output_transaction = pre_to_sco_ap_output_transaction_t::type_id::create("pre_to_sco_ap_output_transaction"); + // UVMF_CHANGE_ME: Implement predictor model here. + `uvm_info("UNIMPLEMENTED_PREDICTOR_MODEL", "******************************************************************************************************",UVM_NONE) + `uvm_info("UNIMPLEMENTED_PREDICTOR_MODEL", "UVMF_CHANGE_ME: The block_1_predictor::write_axi_1_ae function needs to be completed with DUT prediction model",UVM_NONE) + `uvm_info("UNIMPLEMENTED_PREDICTOR_MODEL", "******************************************************************************************************",UVM_NONE) + + // Code for sending output transaction out through pre_to_sco_ap + // Please note that each broadcasted transaction should be a different object than previously + // broadcasted transactions. Creation of a different object is done by constructing the transaction + // using either new() or create(). Broadcasting a transaction object more than once to either the + // same subscriber or multiple subscribers will result in unexpected and incorrect behavior. + pre_to_sco_ap.write(pre_to_sco_ap_output_transaction); + // pragma uvmf custom axi_1_ae_predictor end + endfunction + + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/environment_packages/block_1_env_pkg/src/block_1_scoreboard.svh b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/environment_packages/block_1_env_pkg/src/block_1_scoreboard.svh new file mode 100644 index 00000000..46ee1bf8 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/environment_packages/block_1_env_pkg/src/block_1_scoreboard.svh @@ -0,0 +1,131 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This analysis component contains analysis_exports for receiving +// data and analysis_ports for sending data. +// +// This analysis component has the following analysis_exports that receive the +// listed transaction type. +// +// sco_from_pre_ae receives transactions of type spi_s_transaction +// spi_ae receives transactions of type spi_s_transaction +// +// This analysis component has the following analysis_ports that can broadcast +// the listed transaction type. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// + + +class block_1_scoreboard #( + type CONFIG_T, + type BASE_T = uvm_component + ) extends BASE_T; + + // Factory registration of this class + `uvm_component_param_utils( block_1_scoreboard #( + CONFIG_T, + BASE_T + )) + + + // Instantiate a handle to the configuration of the environment in which this component resides + CONFIG_T configuration; + + + // Instantiate the analysis exports + uvm_analysis_imp_sco_from_pre_ae #(spi_s_transaction, block_1_scoreboard #( + .CONFIG_T(CONFIG_T), + .BASE_T(BASE_T) + )) sco_from_pre_ae; + uvm_analysis_imp_spi_ae #(spi_s_transaction, block_1_scoreboard #( + .CONFIG_T(CONFIG_T), + .BASE_T(BASE_T) + )) spi_ae; + + + + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + // FUNCTION: new + function new(string name, uvm_component parent); + super.new(name,parent); + // pragma uvmf custom new begin + // pragma uvmf custom new end + endfunction + + // FUNCTION: build_phase + virtual function void build_phase (uvm_phase phase); + + sco_from_pre_ae = new("sco_from_pre_ae", this); + spi_ae = new("spi_ae", this); + // pragma uvmf custom build_phase begin + // pragma uvmf custom build_phase end + endfunction + + // FUNCTION: write_sco_from_pre_ae + // Transactions received through sco_from_pre_ae initiate the execution of this function. + // This function performs prediction of DUT output values based on DUT input, configuration and state + virtual function void write_sco_from_pre_ae(spi_s_transaction t); + // pragma uvmf custom sco_from_pre_ae_scoreboard begin + `uvm_info("PRED", "Transaction Received through sco_from_pre_ae", UVM_MEDIUM) + `uvm_info("PRED", {" Data: ",t.convert2string()}, UVM_FULL) + // UVMF_CHANGE_ME: Implement custom scoreboard here. + `uvm_info("UNIMPLEMENTED_CUSTOM_SCOREBOARD", "******************************************************************************************************",UVM_NONE) + `uvm_info("UNIMPLEMENTED_CUSTOM_SCOREBOARD", "UVMF_CHANGE_ME: The block_1_scoreboard::write_sco_from_pre_ae function needs to be completed with custom scoreboard functionality",UVM_NONE) + `uvm_info("UNIMPLEMENTED_CUSTOM_SCOREBOARD", "******************************************************************************************************",UVM_NONE) + + // pragma uvmf custom sco_from_pre_ae_scoreboard end + endfunction + + // FUNCTION: write_spi_ae + // Transactions received through spi_ae initiate the execution of this function. + // This function performs prediction of DUT output values based on DUT input, configuration and state + virtual function void write_spi_ae(spi_s_transaction t); + // pragma uvmf custom spi_ae_scoreboard begin + `uvm_info("PRED", "Transaction Received through spi_ae", UVM_MEDIUM) + `uvm_info("PRED", {" Data: ",t.convert2string()}, UVM_FULL) + // UVMF_CHANGE_ME: Implement custom scoreboard here. + `uvm_info("UNIMPLEMENTED_CUSTOM_SCOREBOARD", "******************************************************************************************************",UVM_NONE) + `uvm_info("UNIMPLEMENTED_CUSTOM_SCOREBOARD", "UVMF_CHANGE_ME: The block_1_scoreboard::write_spi_ae function needs to be completed with custom scoreboard functionality",UVM_NONE) + `uvm_info("UNIMPLEMENTED_CUSTOM_SCOREBOARD", "******************************************************************************************************",UVM_NONE) + + // pragma uvmf custom spi_ae_scoreboard end + endfunction + + + + // FUNCTION: extract_phase + virtual function void extract_phase(uvm_phase phase); +// pragma uvmf custom extract_phase begin + super.extract_phase(phase); +// pragma uvmf custom extract_phase end + endfunction + + // FUNCTION: check_phase + virtual function void check_phase(uvm_phase phase); +// pragma uvmf custom check_phase begin + super.check_phase(phase); +// pragma uvmf custom check_phase end + endfunction + + // FUNCTION: report_phase + virtual function void report_phase(uvm_phase phase); +// pragma uvmf custom report_phase begin + super.report_phase(phase); +// pragma uvmf custom report_phase end + endfunction + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/environment_packages/block_1_env_pkg/yaml/block_1_environment.yaml b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/environment_packages/block_1_env_pkg/yaml/block_1_environment.yaml new file mode 100644 index 00000000..e13560e8 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/environment_packages/block_1_env_pkg/yaml/block_1_environment.yaml @@ -0,0 +1,67 @@ +uvmf: + environments: + block_1: + agents: + - initiator_responder: INITIATOR + name: apb_master + type: apb_m + - initiator_responder: INITIATOR + name: axi_master1 + type: axi_m + - initiator_responder: INITIATOR + name: axi_master2 + type: axi_m + - initiator_responder: RESPONDER + name: spi_slave + type: spi_s + analysis_components: + - name: block_1_pred + parameters: [] + type: block_1_predictor + - name: block_1_sb + parameters: [] + type: block_1_scoreboard + analysis_exports: [] + analysis_ports: + - connected_to: apb_master.monitored_ap + name: apb_master_ap + trans_type: apb_m_transaction + - connected_to: axi_master1.monitored_ap + name: axi_master1_ap + trans_type: axi_m_transaction + - connected_to: axi_master2.monitored_ap + name: axi_master2_ap + trans_type: axi_m_transaction + - connected_to: spi_slave.monitored_ap + name: spi_slave_ap + trans_type: spi_s_transaction + config_constraints: [] + config_vars: + - comment: '' + isrand: 'False' + name: has_scoreboard + type: bit + value: '' + existing_library_component: 'True' + hvl_pkg_parameters: [] + non_uvmf_components: [] + parameters: [] + qvip_memory_agents: [] + scoreboards: [] + subenvs: [] + tlm_connections: + - driver: spi_slave.monitored_ap + receiver: block_1_sb.spi_ae + validate: 'True' + - driver: apb_master.monitored_ap + receiver: block_1_pred.apb_ae + validate: 'True' + - driver: axi_master1.monitored_ap + receiver: block_1_pred.axi_1_ae + validate: 'True' + - driver: axi_master2.monitored_ap + receiver: block_1_pred.axi_2_ae + validate: 'True' + - driver: block_1_pred.pre_to_sco_ap + receiver: block_1_sb.sco_from_pre_ae + validate: 'True' diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/environment_packages/block_1_env_pkg/yaml/block_1_util_comp_block_1_predictor.yaml b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/environment_packages/block_1_env_pkg/yaml/block_1_util_comp_block_1_predictor.yaml new file mode 100644 index 00000000..ce520abe --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/environment_packages/block_1_env_pkg/yaml/block_1_util_comp_block_1_predictor.yaml @@ -0,0 +1,15 @@ +uvmf: + util_components: + block_1_predictor: + analysis_exports: + - name: axi_2_ae + type: axi_m_transaction + - name: apb_ae + type: apb_m_transaction + - name: axi_1_ae + type: axi_m_transaction + analysis_ports: + - name: pre_to_sco_ap + type: spi_s_transaction + existing_library_component: 'True' + type: predictor diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/environment_packages/block_1_env_pkg/yaml/block_1_util_comp_block_1_scoreboard.yaml b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/environment_packages/block_1_env_pkg/yaml/block_1_util_comp_block_1_scoreboard.yaml new file mode 100644 index 00000000..e1fb20d8 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/environment_packages/block_1_env_pkg/yaml/block_1_util_comp_block_1_scoreboard.yaml @@ -0,0 +1,10 @@ +uvmf: + util_components: + block_1_scoreboard: + analysis_exports: + - name: sco_from_pre_ae + type: spi_s_transaction + - name: spi_ae + type: spi_s_transaction + existing_library_component: 'True' + type: scoreboard diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/environment_packages/block_2_env_pkg/.project b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/environment_packages/block_2_env_pkg/.project new file mode 100644 index 00000000..a03fd98f --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/environment_packages/block_2_env_pkg/.project @@ -0,0 +1,32 @@ + + + block_2_env_pkg + + + + + + org.python.pydev.PyDevBuilder + + + + + net.sf.sveditor.core.SVProjectBuilder + + + + + + net.sf.sveditor.core.SVNature + org.python.pydev.pythonNature + + + + + + UVMF_VIP_LIBRARY_HOME + $%7BPARENT-2-PROJECT_LOC%7D + + + + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/environment_packages/block_2_env_pkg/.svproject b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/environment_packages/block_2_env_pkg/.svproject new file mode 100644 index 00000000..8f384931 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/environment_packages/block_2_env_pkg/.svproject @@ -0,0 +1,16 @@ + + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/environment_packages/block_2_env_pkg/Makefile b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/environment_packages/block_2_env_pkg/Makefile new file mode 100644 index 00000000..68a7f9f1 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/environment_packages/block_2_env_pkg/Makefile @@ -0,0 +1,56 @@ +# block_2 environment packages source and make target + +# pragma uvmf custom additional begin +# pragma uvmf custom additional end + +# Include all requisite sub-environment package targets for this bench + +block_2_ENV_PKG =\ + $(UVMF_VIP_LIBRARY_HOME)/environment_packages/block_2_env_pkg/block_2_env_pkg.sv + +COMP_block_2_PKG_TGT_0 = q_comp_block_2_env_pkg +COMP_block_2_PKG_TGT_1 = v_comp_block_2_env_pkg +COMP_block_2_PKG_TGT = $(COMP_block_2_PKG_TGT_$(USE_VELOCE)) + +comp_block_2_env_pkg: $(COMP_block_2_PKG_TGT) + +q_comp_block_2_env_pkg: + $(HVL_COMP_CMD) +incdir+$(UVMF_VIP_LIBRARY_HOME)/environment_packages/block_2_env_pkg $(block_2_ENV_PKG) + +v_comp_block_2_env_pkg: q_comp_block_2_env_pkg + $(VELANALYZE_HVL_CMD) +incdir+$(UVMF_VIP_LIBRARY_HOME)/environment_packages/block_2_env_pkg $(block_2_ENV_PKG) + + + +ifeq ($(MTI_VCO_MODE),64) + GCC_COMP_ARCH = -m64 +else + GCC_COMP_ARCH = -m32 +endif + +export block_2_ENV_DPI_SRC ?= $(UVMF_VIP_LIBRARY_HOME)/environment_packages/block_2_env_pkg/dpi + +C_FILE_COMPILE_LIST_block_2_env_pkg = \ + +O_FILE_COMPILE_LIST_block_2_env_pkg = $(notdir $(C_FILE_COMPILE_LIST_block_2_env_pkg:.c=.o)) + +GCC_COMP_ARGS_block_2_env_pkg += -I$(block_2_ENV_DPI_SRC) \ + -fPIC + +GCC_COMP_ARGS_block_2_env_pkg += $(block_2_ENV_GCC_COMP_ARGUMENTS) + +GCC_LINK_ARGS_block_2_env_pkg += \ + \ + -o .so + +comp_block_2_env_pkg_c_files: + @echo "--------------------------------" + @echo "Compiling Environment C source" + @echo "--------------------------------" + gcc $(GCC_COMP_ARCH) $(GCC_COMP_ARGS_block_2_env_pkg) $(C_FILE_COMPILE_LIST_block_2_env_pkg) + @echo "--------------------------------" + @echo "Linking Environment C objects into a shared object" + @echo "--------------------------------" + gcc $(GCC_COMP_ARCH) $(GCC_LINK_ARGS_block_2_env_pkg) $(O_FILE_COMPILE_LIST_block_2_env_pkg) + @echo "--------------------------------" + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/environment_packages/block_2_env_pkg/block_2_env_pkg.compile b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/environment_packages/block_2_env_pkg/block_2_env_pkg.compile new file mode 100644 index 00000000..f00e42c6 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/environment_packages/block_2_env_pkg/block_2_env_pkg.compile @@ -0,0 +1,8 @@ +needs: + - $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg.compile + - ../../../verification_ip/interface_packages/spi_m_pkg/spi_m_hvl.compile + - ../../../verification_ip/interface_packages/wb_s_pkg/wb_s_hvl.compile + +src: + - block_2_env_pkg.sv + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/environment_packages/block_2_env_pkg/block_2_env_pkg.sv b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/environment_packages/block_2_env_pkg/block_2_env_pkg.sv new file mode 100644 index 00000000..737c1244 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/environment_packages/block_2_env_pkg/block_2_env_pkg.sv @@ -0,0 +1,59 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// PACKAGE: This file defines all of the files contained in the +// environment package that will run on the host simulator. +// +// CONTAINS: +// - +// - +// - +// - +// - +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +package block_2_env_pkg; + + import uvm_pkg::*; + `include "uvm_macros.svh" + import uvmf_base_pkg::*; + import spi_m_pkg::*; + import spi_m_pkg_hdl::*; + import wb_s_pkg::*; + import wb_s_pkg_hdl::*; + + `uvm_analysis_imp_decl(_spi_ae) + `uvm_analysis_imp_decl(_sco_from_pre_ae) + `uvm_analysis_imp_decl(_wb_ae) + + // pragma uvmf custom package_imports_additional begin + // pragma uvmf custom package_imports_additional end + + // Parameters defined as HVL parameters + + `include "src/block_2_env_typedefs.svh" + `include "src/block_2_env_configuration.svh" + `include "src/block_2_predictor.svh" + `include "src/block_2_scoreboard.svh" + `include "src/block_2_environment.svh" + `include "src/block_2_env_sequence_base.svh" + + // pragma uvmf custom package_item_additional begin + // UVMF_CHANGE_ME : When adding new environment level sequences to the src directory + // be sure to add the sequence file here so that it will be + // compiled as part of the environment package. Be sure to place + // the new sequence after any base sequence of the new sequence. + // pragma uvmf custom package_item_additional end + +endpackage + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/environment_packages/block_2_env_pkg/block_2_env_pkg.vinfo b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/environment_packages/block_2_env_pkg/block_2_env_pkg.vinfo new file mode 100644 index 00000000..edc8f1de --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/environment_packages/block_2_env_pkg/block_2_env_pkg.vinfo @@ -0,0 +1,5 @@ +@use $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg.vinfo +@use $UVMF_VIP_LIBRARY_HOME/interface_packages/spi_m_pkg/spi_m_pkg.vinfo +@use $UVMF_VIP_LIBRARY_HOME/interface_packages/wb_s_pkg/wb_s_pkg.vinfo ++incdir+@vinfodir +block_2_env_pkg.sv diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/environment_packages/block_2_env_pkg/block_2_env_pkg_sve.F b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/environment_packages/block_2_env_pkg/block_2_env_pkg_sve.F new file mode 100644 index 00000000..7c09328b --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/environment_packages/block_2_env_pkg/block_2_env_pkg_sve.F @@ -0,0 +1,12 @@ + +// UVM ++incdir+${UVM_HOME}/src +${UVM_HOME}/src/uvm_pkg.sv + +// Common UVMF files +-f ${UVMF_HOME}/common/common_sve.f + +// Sub-Environments + ++incdir+. +./block_2_env_pkg.sv diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/environment_packages/block_2_env_pkg/compile.do b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/environment_packages/block_2_env_pkg/compile.do new file mode 100644 index 00000000..93c75466 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/environment_packages/block_2_env_pkg/compile.do @@ -0,0 +1,12 @@ +# Tcl do file for compile of block_2 interface + +# pragma uvmf custom additional begin +# pragma uvmf custom additional end + + + +quietly set cmd [format "vlog -timescale 1ps/1ps +incdir+%s/environment_packages/block_2_env_pkg" $env(UVMF_VIP_LIBRARY_HOME)] +quietly set cmd [format "%s %s/environment_packages/block_2_env_pkg/block_2_env_pkg.sv" $cmd $env(UVMF_VIP_LIBRARY_HOME)] +eval $cmd + + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/environment_packages/block_2_env_pkg/src/block_2_env_configuration.svh b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/environment_packages/block_2_env_pkg/src/block_2_env_configuration.svh new file mode 100644 index 00000000..b1d059e5 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/environment_packages/block_2_env_pkg/src/block_2_env_configuration.svh @@ -0,0 +1,146 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: THis is the configuration for the block_2 environment. +// it contains configuration classes for each agent. It also contains +// environment level configuration variables. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class block_2_env_configuration +extends uvmf_environment_configuration_base; + + `uvm_object_utils( block_2_env_configuration ) + + bit has_scoreboard; + +//Constraints for the configuration variables: + + + covergroup block_2_configuration_cg; + // pragma uvmf custom covergroup begin + option.auto_bin_max=1024; + coverpoint has_scoreboard; + // pragma uvmf custom covergroup end + endgroup + + + typedef spi_m_configuration spi_master_config_t; + rand spi_master_config_t spi_master_config; + + typedef wb_s_configuration wb_slave_config_t; + rand wb_slave_config_t wb_slave_config; + + + + + typedef uvmf_virtual_sequencer_base #(.CONFIG_T(block_2_env_configuration)) block_2_vsqr_t; + block_2_vsqr_t vsqr; + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + +// **************************************************************************** +// FUNCTION : new() +// This function is the standard SystemVerilog constructor. +// This function constructs the configuration object for each agent in the environment. +// + function new( string name = "" ); + super.new( name ); + + + spi_master_config = spi_master_config_t::type_id::create("spi_master_config"); + wb_slave_config = wb_slave_config_t::type_id::create("wb_slave_config"); + + + block_2_configuration_cg=new; + `uvm_warning("COVERAGE_MODEL_REVIEW", "A covergroup has been constructed which may need review because of either generation or re-generation with merging. Please note that configuration variables added as a result of re-generation and merging are not automatically added to the covergroup. Remove this warning after the covergroup has been reviewed.") + + // pragma uvmf custom new begin + // pragma uvmf custom new end + endfunction + +// **************************************************************************** +// FUNCTION : set_vsqr() +// This function is used to assign the vsqr handle. + virtual function void set_vsqr( block_2_vsqr_t vsqr); + this.vsqr = vsqr; + endfunction : set_vsqr + +// **************************************************************************** +// FUNCTION: post_randomize() +// This function is automatically called after the randomize() function +// is executed. +// + function void post_randomize(); + super.post_randomize(); + // pragma uvmf custom post_randomize begin + // pragma uvmf custom post_randomize end + endfunction + +// **************************************************************************** +// FUNCTION: convert2string() +// This function converts all variables in this class to a single string for +// logfile reporting. This function concatenates the convert2string result for +// each agent configuration in this configuration class. +// + virtual function string convert2string(); + // pragma uvmf custom convert2string begin + return { + $sformatf("has_scoreboard:0x%x ",has_scoreboard), + "\n", spi_master_config.convert2string, + "\n", wb_slave_config.convert2string + + + }; + // pragma uvmf custom convert2string end + endfunction +// **************************************************************************** +// FUNCTION: initialize(); +// This function configures each interface agents configuration class. The +// sim level determines the active/passive state of the agent. The environment_path +// identifies the hierarchy down to and including the instantiation name of the +// environment for this configuration class. Each instance of the environment +// has its own configuration class. The string interface names are used by +// the agent configurations to identify the virtual interface handle to pull from +// the uvm_config_db. +// + function void initialize(uvmf_sim_level_t sim_level, + string environment_path, + string interface_names[], + uvm_reg_block register_model = null, + uvmf_active_passive_t interface_activity[] = {} + ); + + super.initialize(sim_level, environment_path, interface_names, register_model, interface_activity); + + + + // Interface initialization for local agents + spi_master_config.initialize( interface_activity[0], {environment_path,".spi_master"}, interface_names[0]); + spi_master_config.initiator_responder = INITIATOR; + // spi_master_config.has_coverage = 1; + wb_slave_config.initialize( interface_activity[1], {environment_path,".wb_slave"}, interface_names[1]); + wb_slave_config.initiator_responder = RESPONDER; + // wb_slave_config.has_coverage = 1; + + + + + + // pragma uvmf custom initialize begin + // pragma uvmf custom initialize end + + endfunction + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/environment_packages/block_2_env_pkg/src/block_2_env_sequence_base.svh b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/environment_packages/block_2_env_pkg/src/block_2_env_sequence_base.svh new file mode 100644 index 00000000..809e05e3 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/environment_packages/block_2_env_pkg/src/block_2_env_sequence_base.svh @@ -0,0 +1,69 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This file contains environment level sequences that will +// be reused from block to top level simulations. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class block_2_env_sequence_base #( + type CONFIG_T + ) extends uvmf_virtual_sequence_base #(.CONFIG_T(CONFIG_T)); + + + `uvm_object_param_utils( block_2_env_sequence_base #( + CONFIG_T + ) ); + + +// This block_2_env_sequence_base contains a handle to a block_2_env_configuration object +// named configuration. This configuration variable contains a handle to each +// sequencer within each agent within this environment and any sub-environments. +// The configuration object handle is automatically assigned in the pre_body in the +// base class of this sequence. The configuration handle is retrieved from the +// virtual sequencer that this sequence is started on. +// Available sequencer handles within the environment configuration: + + // Initiator agent sequencers in block_2_environment: + // configuration.spi_master_config.sequencer + + // Responder agent sequencers in block_2_environment: + // configuration.wb_slave_config.sequencer + + + typedef spi_m_random_sequence spi_master_random_sequence_t; + spi_master_random_sequence_t spi_master_rand_seq; + + + + + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + function new(string name = "" ); + super.new(name); + spi_master_rand_seq = spi_master_random_sequence_t::type_id::create("spi_master_rand_seq"); + + + endfunction + + virtual task body(); + + if ( configuration.spi_master_config.sequencer != null ) + repeat (25) spi_master_rand_seq.start(configuration.spi_master_config.sequencer); + + + endtask + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/environment_packages/block_2_env_pkg/src/block_2_env_typedefs.svh b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/environment_packages/block_2_env_pkg/src/block_2_env_typedefs.svh new file mode 100644 index 00000000..9814bd58 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/environment_packages/block_2_env_pkg/src/block_2_env_typedefs.svh @@ -0,0 +1,20 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: +// This file contains defines and typedefs to be compiled for use in +// the environment package. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// + + + // pragma uvmf custom additional begin + // pragma uvmf custom additional end + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/environment_packages/block_2_env_pkg/src/block_2_environment.svh b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/environment_packages/block_2_env_pkg/src/block_2_environment.svh new file mode 100644 index 00000000..b6a94f85 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/environment_packages/block_2_env_pkg/src/block_2_environment.svh @@ -0,0 +1,127 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This environment contains all agents, predictors and +// scoreboards required for the block level design. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// + +class block_2_environment extends uvmf_environment_base #( + .CONFIG_T( block_2_env_configuration + )); + `uvm_component_utils( block_2_environment ) + + + + uvm_analysis_port #(spi_m_transaction) spi_master_ap; + uvm_analysis_port #(wb_s_transaction) wb_slave_ap; + + + typedef spi_m_agent spi_master_t; + spi_master_t spi_master; + + typedef wb_s_agent wb_slave_t; + wb_slave_t wb_slave; + + + + + typedef block_2_predictor #( + .CONFIG_T(CONFIG_T) + ) block_2_pred_t; + block_2_pred_t block_2_pred; + typedef block_2_scoreboard #( + .CONFIG_T(CONFIG_T) + ) block_2_sb_t; + block_2_sb_t block_2_sb; + + + + + typedef uvmf_virtual_sequencer_base #(.CONFIG_T(block_2_env_configuration)) block_2_vsqr_t; + block_2_vsqr_t vsqr; + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + +// **************************************************************************** +// FUNCTION : new() +// This function is the standard SystemVerilog constructor. +// + function new( string name = "", uvm_component parent = null ); + super.new( name, parent ); + endfunction + +// **************************************************************************** +// FUNCTION: build_phase() +// This function builds all components within this environment. +// + virtual function void build_phase(uvm_phase phase); +// pragma uvmf custom build_phase_pre_super begin +// pragma uvmf custom build_phase_pre_super end + super.build_phase(phase); + spi_master_ap = new("spi_master_ap",this); + wb_slave_ap = new("wb_slave_ap",this); + spi_master = spi_master_t::type_id::create("spi_master",this); + spi_master.set_config(configuration.spi_master_config); + wb_slave = wb_slave_t::type_id::create("wb_slave",this); + wb_slave.set_config(configuration.wb_slave_config); + block_2_pred = block_2_pred_t::type_id::create("block_2_pred",this); + block_2_pred.configuration = configuration; + block_2_sb = block_2_sb_t::type_id::create("block_2_sb",this); + block_2_sb.configuration = configuration; + + vsqr = block_2_vsqr_t::type_id::create("vsqr", this); + vsqr.set_config(configuration); + configuration.set_vsqr(vsqr); + + // pragma uvmf custom build_phase begin + // pragma uvmf custom build_phase end + endfunction + +// **************************************************************************** +// FUNCTION: connect_phase() +// This function makes all connections within this environment. Connections +// typically inclue agent to predictor, predictor to scoreboard and scoreboard +// to agent. +// + virtual function void connect_phase(uvm_phase phase); +// pragma uvmf custom connect_phase_pre_super begin +// pragma uvmf custom connect_phase_pre_super end + super.connect_phase(phase); + spi_master.monitored_ap.connect(block_2_pred.spi_ae); + wb_slave.monitored_ap.connect(block_2_sb.wb_ae); + block_2_pred.pre_to_sco_ap.connect(block_2_sb.sco_from_pre_ae); + spi_master.monitored_ap.connect(spi_master_ap); + wb_slave.monitored_ap.connect(wb_slave_ap); + // pragma uvmf custom reg_model_connect_phase begin + // pragma uvmf custom reg_model_connect_phase end + endfunction + +// **************************************************************************** +// FUNCTION: end_of_simulation_phase() +// This function is executed just prior to executing run_phase. This function +// was added to the environment to sample environment configuration settings +// just before the simulation exits time 0. The configuration structure is +// randomized in the build phase before the environment structure is constructed. +// Configuration variables can be customized after randomization in the build_phase +// of the extended test. +// If a sequence modifies values in the configuration structure then the sequence is +// responsible for sampling the covergroup in the configuration if required. +// + virtual function void start_of_simulation_phase(uvm_phase phase); + configuration.block_2_configuration_cg.sample(); + endfunction + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/environment_packages/block_2_env_pkg/src/block_2_predictor.svh b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/environment_packages/block_2_env_pkg/src/block_2_predictor.svh new file mode 100644 index 00000000..6eac733c --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/environment_packages/block_2_env_pkg/src/block_2_predictor.svh @@ -0,0 +1,114 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +// +//---------------------------------------------------------------------- +// +// DESCRIPTION: This analysis component contains analysis_exports for receiving +// data and analysis_ports for sending data. +// +// This analysis component has the following analysis_exports that receive the +// listed transaction type. +// +// spi_ae receives transactions of type spi_m_transaction +// +// This analysis component has the following analysis_ports that can broadcast +// the listed transaction type. +// +// pre_to_sco_ap broadcasts transactions of type wb_s_transaction +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// + +class block_2_predictor #( + type CONFIG_T, + type BASE_T = uvm_component + ) extends BASE_T; + + // Factory registration of this class + `uvm_component_param_utils( block_2_predictor #( + CONFIG_T, + BASE_T + )) + + + // Instantiate a handle to the configuration of the environment in which this component resides + CONFIG_T configuration; + + + // Instantiate the analysis exports + uvm_analysis_imp_spi_ae #(spi_m_transaction, block_2_predictor #( + .CONFIG_T(CONFIG_T), + .BASE_T(BASE_T) + )) spi_ae; + + + // Instantiate the analysis ports + uvm_analysis_port #(wb_s_transaction) pre_to_sco_ap; + + + // Transaction variable for predicted values to be sent out pre_to_sco_ap + // Once a transaction is sent through an analysis_port, another transaction should + // be constructed for the next predicted transaction. + typedef wb_s_transaction pre_to_sco_ap_output_transaction_t; + pre_to_sco_ap_output_transaction_t pre_to_sco_ap_output_transaction; + // Code for sending output transaction out through pre_to_sco_ap + // pre_to_sco_ap.write(pre_to_sco_ap_output_transaction); + + // Define transaction handles for debug visibility + spi_m_transaction spi_ae_debug; + + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + // FUNCTION: new + function new(string name, uvm_component parent); + super.new(name,parent); + `uvm_warning("PREDICTOR_REVIEW", "This predictor has been created either through generation or re-generation with merging. Remove this warning after the predictor has been reviewed.") + // pragma uvmf custom new begin + // pragma uvmf custom new end + endfunction + + // FUNCTION: build_phase + virtual function void build_phase (uvm_phase phase); + + spi_ae = new("spi_ae", this); + pre_to_sco_ap =new("pre_to_sco_ap", this ); + // pragma uvmf custom build_phase begin + // pragma uvmf custom build_phase end + endfunction + + // FUNCTION: write_spi_ae + // Transactions received through spi_ae initiate the execution of this function. + // This function performs prediction of DUT output values based on DUT input, configuration and state + virtual function void write_spi_ae(spi_m_transaction t); + // pragma uvmf custom spi_ae_predictor begin + spi_ae_debug = t; + `uvm_info("PRED", "Transaction Received through spi_ae", UVM_MEDIUM) + `uvm_info("PRED", {" Data: ",t.convert2string()}, UVM_FULL) + // Construct one of each output transaction type. + pre_to_sco_ap_output_transaction = pre_to_sco_ap_output_transaction_t::type_id::create("pre_to_sco_ap_output_transaction"); + // UVMF_CHANGE_ME: Implement predictor model here. + `uvm_info("UNIMPLEMENTED_PREDICTOR_MODEL", "******************************************************************************************************",UVM_NONE) + `uvm_info("UNIMPLEMENTED_PREDICTOR_MODEL", "UVMF_CHANGE_ME: The block_2_predictor::write_spi_ae function needs to be completed with DUT prediction model",UVM_NONE) + `uvm_info("UNIMPLEMENTED_PREDICTOR_MODEL", "******************************************************************************************************",UVM_NONE) + + // Code for sending output transaction out through pre_to_sco_ap + // Please note that each broadcasted transaction should be a different object than previously + // broadcasted transactions. Creation of a different object is done by constructing the transaction + // using either new() or create(). Broadcasting a transaction object more than once to either the + // same subscriber or multiple subscribers will result in unexpected and incorrect behavior. + pre_to_sco_ap.write(pre_to_sco_ap_output_transaction); + // pragma uvmf custom spi_ae_predictor end + endfunction + + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/environment_packages/block_2_env_pkg/src/block_2_scoreboard.svh b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/environment_packages/block_2_env_pkg/src/block_2_scoreboard.svh new file mode 100644 index 00000000..82863e51 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/environment_packages/block_2_env_pkg/src/block_2_scoreboard.svh @@ -0,0 +1,131 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This analysis component contains analysis_exports for receiving +// data and analysis_ports for sending data. +// +// This analysis component has the following analysis_exports that receive the +// listed transaction type. +// +// sco_from_pre_ae receives transactions of type wb_s_transaction +// wb_ae receives transactions of type wb_s_transaction +// +// This analysis component has the following analysis_ports that can broadcast +// the listed transaction type. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// + + +class block_2_scoreboard #( + type CONFIG_T, + type BASE_T = uvm_component + ) extends BASE_T; + + // Factory registration of this class + `uvm_component_param_utils( block_2_scoreboard #( + CONFIG_T, + BASE_T + )) + + + // Instantiate a handle to the configuration of the environment in which this component resides + CONFIG_T configuration; + + + // Instantiate the analysis exports + uvm_analysis_imp_sco_from_pre_ae #(wb_s_transaction, block_2_scoreboard #( + .CONFIG_T(CONFIG_T), + .BASE_T(BASE_T) + )) sco_from_pre_ae; + uvm_analysis_imp_wb_ae #(wb_s_transaction, block_2_scoreboard #( + .CONFIG_T(CONFIG_T), + .BASE_T(BASE_T) + )) wb_ae; + + + + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + // FUNCTION: new + function new(string name, uvm_component parent); + super.new(name,parent); + // pragma uvmf custom new begin + // pragma uvmf custom new end + endfunction + + // FUNCTION: build_phase + virtual function void build_phase (uvm_phase phase); + + sco_from_pre_ae = new("sco_from_pre_ae", this); + wb_ae = new("wb_ae", this); + // pragma uvmf custom build_phase begin + // pragma uvmf custom build_phase end + endfunction + + // FUNCTION: write_sco_from_pre_ae + // Transactions received through sco_from_pre_ae initiate the execution of this function. + // This function performs prediction of DUT output values based on DUT input, configuration and state + virtual function void write_sco_from_pre_ae(wb_s_transaction t); + // pragma uvmf custom sco_from_pre_ae_scoreboard begin + `uvm_info("PRED", "Transaction Received through sco_from_pre_ae", UVM_MEDIUM) + `uvm_info("PRED", {" Data: ",t.convert2string()}, UVM_FULL) + // UVMF_CHANGE_ME: Implement custom scoreboard here. + `uvm_info("UNIMPLEMENTED_CUSTOM_SCOREBOARD", "******************************************************************************************************",UVM_NONE) + `uvm_info("UNIMPLEMENTED_CUSTOM_SCOREBOARD", "UVMF_CHANGE_ME: The block_2_scoreboard::write_sco_from_pre_ae function needs to be completed with custom scoreboard functionality",UVM_NONE) + `uvm_info("UNIMPLEMENTED_CUSTOM_SCOREBOARD", "******************************************************************************************************",UVM_NONE) + + // pragma uvmf custom sco_from_pre_ae_scoreboard end + endfunction + + // FUNCTION: write_wb_ae + // Transactions received through wb_ae initiate the execution of this function. + // This function performs prediction of DUT output values based on DUT input, configuration and state + virtual function void write_wb_ae(wb_s_transaction t); + // pragma uvmf custom wb_ae_scoreboard begin + `uvm_info("PRED", "Transaction Received through wb_ae", UVM_MEDIUM) + `uvm_info("PRED", {" Data: ",t.convert2string()}, UVM_FULL) + // UVMF_CHANGE_ME: Implement custom scoreboard here. + `uvm_info("UNIMPLEMENTED_CUSTOM_SCOREBOARD", "******************************************************************************************************",UVM_NONE) + `uvm_info("UNIMPLEMENTED_CUSTOM_SCOREBOARD", "UVMF_CHANGE_ME: The block_2_scoreboard::write_wb_ae function needs to be completed with custom scoreboard functionality",UVM_NONE) + `uvm_info("UNIMPLEMENTED_CUSTOM_SCOREBOARD", "******************************************************************************************************",UVM_NONE) + + // pragma uvmf custom wb_ae_scoreboard end + endfunction + + + + // FUNCTION: extract_phase + virtual function void extract_phase(uvm_phase phase); +// pragma uvmf custom extract_phase begin + super.extract_phase(phase); +// pragma uvmf custom extract_phase end + endfunction + + // FUNCTION: check_phase + virtual function void check_phase(uvm_phase phase); +// pragma uvmf custom check_phase begin + super.check_phase(phase); +// pragma uvmf custom check_phase end + endfunction + + // FUNCTION: report_phase + virtual function void report_phase(uvm_phase phase); +// pragma uvmf custom report_phase begin + super.report_phase(phase); +// pragma uvmf custom report_phase end + endfunction + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/environment_packages/block_2_env_pkg/yaml/block_2_environment.yaml b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/environment_packages/block_2_env_pkg/yaml/block_2_environment.yaml new file mode 100644 index 00000000..dc04d0c3 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/environment_packages/block_2_env_pkg/yaml/block_2_environment.yaml @@ -0,0 +1,49 @@ +uvmf: + environments: + block_2: + agents: + - initiator_responder: INITIATOR + name: spi_master + type: spi_m + - initiator_responder: RESPONDER + name: wb_slave + type: wb_s + analysis_components: + - name: block_2_pred + parameters: [] + type: block_2_predictor + - name: block_2_sb + parameters: [] + type: block_2_scoreboard + analysis_exports: [] + analysis_ports: + - connected_to: spi_master.monitored_ap + name: spi_master_ap + trans_type: spi_m_transaction + - connected_to: wb_slave.monitored_ap + name: wb_slave_ap + trans_type: wb_s_transaction + config_constraints: [] + config_vars: + - comment: '' + isrand: 'False' + name: has_scoreboard + type: bit + value: '' + existing_library_component: 'True' + hvl_pkg_parameters: [] + non_uvmf_components: [] + parameters: [] + qvip_memory_agents: [] + scoreboards: [] + subenvs: [] + tlm_connections: + - driver: spi_master.monitored_ap + receiver: block_2_pred.spi_ae + validate: 'True' + - driver: wb_slave.monitored_ap + receiver: block_2_sb.wb_ae + validate: 'True' + - driver: block_2_pred.pre_to_sco_ap + receiver: block_2_sb.sco_from_pre_ae + validate: 'True' diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/environment_packages/block_2_env_pkg/yaml/block_2_util_comp_block_2_predictor.yaml b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/environment_packages/block_2_env_pkg/yaml/block_2_util_comp_block_2_predictor.yaml new file mode 100644 index 00000000..c4fe0e50 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/environment_packages/block_2_env_pkg/yaml/block_2_util_comp_block_2_predictor.yaml @@ -0,0 +1,11 @@ +uvmf: + util_components: + block_2_predictor: + analysis_exports: + - name: spi_ae + type: spi_m_transaction + analysis_ports: + - name: pre_to_sco_ap + type: wb_s_transaction + existing_library_component: 'True' + type: predictor diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/environment_packages/block_2_env_pkg/yaml/block_2_util_comp_block_2_scoreboard.yaml b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/environment_packages/block_2_env_pkg/yaml/block_2_util_comp_block_2_scoreboard.yaml new file mode 100644 index 00000000..b0e3bf1a --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/environment_packages/block_2_env_pkg/yaml/block_2_util_comp_block_2_scoreboard.yaml @@ -0,0 +1,10 @@ +uvmf: + util_components: + block_2_scoreboard: + analysis_exports: + - name: sco_from_pre_ae + type: wb_s_transaction + - name: wb_ae + type: wb_s_transaction + existing_library_component: 'True' + type: scoreboard diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/environment_packages/subsys_env_pkg/.project b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/environment_packages/subsys_env_pkg/.project new file mode 100644 index 00000000..d5582aca --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/environment_packages/subsys_env_pkg/.project @@ -0,0 +1,32 @@ + + + subsys_env_pkg + + + + + + org.python.pydev.PyDevBuilder + + + + + net.sf.sveditor.core.SVProjectBuilder + + + + + + net.sf.sveditor.core.SVNature + org.python.pydev.pythonNature + + + + + + UVMF_VIP_LIBRARY_HOME + $%7BPARENT-2-PROJECT_LOC%7D + + + + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/environment_packages/subsys_env_pkg/.svproject b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/environment_packages/subsys_env_pkg/.svproject new file mode 100644 index 00000000..56c4a5ca --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/environment_packages/subsys_env_pkg/.svproject @@ -0,0 +1,16 @@ + + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/environment_packages/subsys_env_pkg/Makefile b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/environment_packages/subsys_env_pkg/Makefile new file mode 100644 index 00000000..5ac49d1d --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/environment_packages/subsys_env_pkg/Makefile @@ -0,0 +1,58 @@ +# subsys environment packages source and make target + +# pragma uvmf custom additional begin +# pragma uvmf custom additional end + +# Include all requisite sub-environment package targets for this bench +include $(UVMF_VIP_LIBRARY_HOME)/environment_packages/block_1_env_pkg/Makefile +include $(UVMF_VIP_LIBRARY_HOME)/environment_packages/block_2_env_pkg/Makefile + +subsys_ENV_PKG =\ + $(UVMF_VIP_LIBRARY_HOME)/environment_packages/subsys_env_pkg/subsys_env_pkg.sv + +COMP_subsys_PKG_TGT_0 = q_comp_subsys_env_pkg +COMP_subsys_PKG_TGT_1 = v_comp_subsys_env_pkg +COMP_subsys_PKG_TGT = $(COMP_subsys_PKG_TGT_$(USE_VELOCE)) + +comp_subsys_env_pkg: $(COMP_subsys_PKG_TGT) + +q_comp_subsys_env_pkg: comp_block_1_env_pkg comp_block_2_env_pkg + $(HVL_COMP_CMD) +incdir+$(UVMF_VIP_LIBRARY_HOME)/environment_packages/subsys_env_pkg $(subsys_ENV_PKG) + +v_comp_subsys_env_pkg: q_comp_subsys_env_pkg + $(VELANALYZE_HVL_CMD) +incdir+$(UVMF_VIP_LIBRARY_HOME)/environment_packages/subsys_env_pkg $(subsys_ENV_PKG) + + + +ifeq ($(MTI_VCO_MODE),64) + GCC_COMP_ARCH = -m64 +else + GCC_COMP_ARCH = -m32 +endif + +export subsys_ENV_DPI_SRC ?= $(UVMF_VIP_LIBRARY_HOME)/environment_packages/subsys_env_pkg/dpi + +C_FILE_COMPILE_LIST_subsys_env_pkg = \ + +O_FILE_COMPILE_LIST_subsys_env_pkg = $(notdir $(C_FILE_COMPILE_LIST_subsys_env_pkg:.c=.o)) + +GCC_COMP_ARGS_subsys_env_pkg += -I$(subsys_ENV_DPI_SRC) \ + -fPIC + +GCC_COMP_ARGS_subsys_env_pkg += $(subsys_ENV_GCC_COMP_ARGUMENTS) + +GCC_LINK_ARGS_subsys_env_pkg += \ + \ + -o .so + +comp_subsys_env_pkg_c_files: + @echo "--------------------------------" + @echo "Compiling Environment C source" + @echo "--------------------------------" + gcc $(GCC_COMP_ARCH) $(GCC_COMP_ARGS_subsys_env_pkg) $(C_FILE_COMPILE_LIST_subsys_env_pkg) + @echo "--------------------------------" + @echo "Linking Environment C objects into a shared object" + @echo "--------------------------------" + gcc $(GCC_COMP_ARCH) $(GCC_LINK_ARGS_subsys_env_pkg) $(O_FILE_COMPILE_LIST_subsys_env_pkg) + @echo "--------------------------------" + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/environment_packages/subsys_env_pkg/compile.do b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/environment_packages/subsys_env_pkg/compile.do new file mode 100644 index 00000000..755d5d0d --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/environment_packages/subsys_env_pkg/compile.do @@ -0,0 +1,18 @@ +# Tcl do file for compile of subsys interface + +# pragma uvmf custom additional begin +# pragma uvmf custom additional end + + +# Include build for sub-environment block_1_env_pkg +quietly set cmd [format "source %s/environment_packages/block_1_env_pkg/compile.do" $env(UVMF_VIP_LIBRARY_HOME)] +eval $cmd +# Include build for sub-environment block_2_env_pkg +quietly set cmd [format "source %s/environment_packages/block_2_env_pkg/compile.do" $env(UVMF_VIP_LIBRARY_HOME)] +eval $cmd + +quietly set cmd [format "vlog -timescale 1ps/1ps +incdir+%s/environment_packages/subsys_env_pkg" $env(UVMF_VIP_LIBRARY_HOME)] +quietly set cmd [format "%s %s/environment_packages/subsys_env_pkg/subsys_env_pkg.sv" $cmd $env(UVMF_VIP_LIBRARY_HOME)] +eval $cmd + + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/environment_packages/subsys_env_pkg/src/subsys_env_configuration.svh b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/environment_packages/subsys_env_pkg/src/subsys_env_configuration.svh new file mode 100644 index 00000000..cfe5403c --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/environment_packages/subsys_env_pkg/src/subsys_env_configuration.svh @@ -0,0 +1,156 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: THis is the configuration for the subsys environment. +// it contains configuration classes for each agent. It also contains +// environment level configuration variables. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class subsys_env_configuration +extends uvmf_environment_configuration_base; + + `uvm_object_utils( subsys_env_configuration ) + + bit has_scoreboard; + +//Constraints for the configuration variables: + + + covergroup subsys_configuration_cg; + // pragma uvmf custom covergroup begin + option.auto_bin_max=1024; + coverpoint has_scoreboard; + // pragma uvmf custom covergroup end + endgroup + +typedef block_1_env_configuration b1_config_t; +rand b1_config_t b1_config; + +typedef block_2_env_configuration b2_config_t; +rand b2_config_t b2_config; + + + + string b1_interface_names[]; + uvmf_active_passive_t b1_interface_activity[]; + string b2_interface_names[]; + uvmf_active_passive_t b2_interface_activity[]; + + + typedef uvmf_virtual_sequencer_base #(.CONFIG_T(subsys_env_configuration)) subsys_vsqr_t; + subsys_vsqr_t vsqr; + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + +// **************************************************************************** +// FUNCTION : new() +// This function is the standard SystemVerilog constructor. +// This function constructs the configuration object for each agent in the environment. +// + function new( string name = "" ); + super.new( name ); + + b1_config = b1_config_t::type_id::create("b1_config"); + b2_config = b2_config_t::type_id::create("b2_config"); + + + + subsys_configuration_cg=new; + `uvm_warning("COVERAGE_MODEL_REVIEW", "A covergroup has been constructed which may need review because of either generation or re-generation with merging. Please note that configuration variables added as a result of re-generation and merging are not automatically added to the covergroup. Remove this warning after the covergroup has been reviewed.") + + // pragma uvmf custom new begin + // pragma uvmf custom new end + endfunction + +// **************************************************************************** +// FUNCTION : set_vsqr() +// This function is used to assign the vsqr handle. + virtual function void set_vsqr( subsys_vsqr_t vsqr); + this.vsqr = vsqr; + endfunction : set_vsqr + +// **************************************************************************** +// FUNCTION: post_randomize() +// This function is automatically called after the randomize() function +// is executed. +// + function void post_randomize(); + super.post_randomize(); + // pragma uvmf custom post_randomize begin + // pragma uvmf custom post_randomize end + endfunction + +// **************************************************************************** +// FUNCTION: convert2string() +// This function converts all variables in this class to a single string for +// logfile reporting. This function concatenates the convert2string result for +// each agent configuration in this configuration class. +// + virtual function string convert2string(); + // pragma uvmf custom convert2string begin + return { + $sformatf("has_scoreboard:0x%x ",has_scoreboard), + + "\n", b1_config.convert2string, + "\n", b2_config.convert2string + + }; + // pragma uvmf custom convert2string end + endfunction +// **************************************************************************** +// FUNCTION: initialize(); +// This function configures each interface agents configuration class. The +// sim level determines the active/passive state of the agent. The environment_path +// identifies the hierarchy down to and including the instantiation name of the +// environment for this configuration class. Each instance of the environment +// has its own configuration class. The string interface names are used by +// the agent configurations to identify the virtual interface handle to pull from +// the uvm_config_db. +// + function void initialize(uvmf_sim_level_t sim_level, + string environment_path, + string interface_names[], + uvm_reg_block register_model = null, + uvmf_active_passive_t interface_activity[] = {} + ); + + super.initialize(sim_level, environment_path, interface_names, register_model, interface_activity); + + // Interface initialization for sub-environments + b1_interface_names = new[4]; + b1_interface_activity = new[4]; + + b1_interface_names = interface_names[0:3]; + b1_interface_activity = interface_activity[0:3]; + b2_interface_names = new[2]; + b2_interface_activity = new[2]; + + b2_interface_names = interface_names[4:5]; + b2_interface_activity = interface_activity[4:5]; + + + + + b1_config.initialize( sim_level, {environment_path,".b1"}, b1_interface_names, null, b1_interface_activity); + b2_config.initialize( sim_level, {environment_path,".b2"}, b2_interface_names, null, b2_interface_activity); + + + + // pragma uvmf custom initialize begin + // pragma uvmf custom initialize end + + endfunction + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/environment_packages/subsys_env_pkg/src/subsys_env_sequence_base.svh b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/environment_packages/subsys_env_pkg/src/subsys_env_sequence_base.svh new file mode 100644 index 00000000..b2ccc409 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/environment_packages/subsys_env_pkg/src/subsys_env_sequence_base.svh @@ -0,0 +1,79 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This file contains environment level sequences that will +// be reused from block to top level simulations. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class subsys_env_sequence_base #( + type CONFIG_T + ) extends uvmf_virtual_sequence_base #(.CONFIG_T(CONFIG_T)); + + + `uvm_object_param_utils( subsys_env_sequence_base #( + CONFIG_T + ) ); + + +// This subsys_env_sequence_base contains a handle to a subsys_env_configuration object +// named configuration. This configuration variable contains a handle to each +// sequencer within each agent within this environment and any sub-environments. +// The configuration object handle is automatically assigned in the pre_body in the +// base class of this sequence. The configuration handle is retrieved from the +// virtual sequencer that this sequence is started on. +// Available sequencer handles within the environment configuration: + + // Initiator agent sequencers in subsys_environment: + + // Responder agent sequencers in subsys_environment: + + // Virtual sequencers in sub-environments located in sub-environment configuration + // configuration.b1_config.vsqr + // configuration.b2_config.vsqr + + +typedef block_1_env_sequence_base #( + .CONFIG_T(block_1_env_configuration) + ) + b1_sequence_base_t; +rand b1_sequence_base_t b1_seq; + +typedef block_2_env_sequence_base #( + .CONFIG_T(block_2_env_configuration) + ) + b2_sequence_base_t; +rand b2_sequence_base_t b2_seq; + + + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + function new(string name = "" ); + super.new(name); + + b1_seq = b1_sequence_base_t::type_id::create("b1_seq"); + b2_seq = b2_sequence_base_t::type_id::create("b2_seq"); + + endfunction + + virtual task body(); + + + b1_seq.start(configuration.b1_config.vsqr); + b2_seq.start(configuration.b2_config.vsqr); + + endtask + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/environment_packages/subsys_env_pkg/src/subsys_env_typedefs.svh b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/environment_packages/subsys_env_pkg/src/subsys_env_typedefs.svh new file mode 100644 index 00000000..9814bd58 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/environment_packages/subsys_env_pkg/src/subsys_env_typedefs.svh @@ -0,0 +1,20 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: +// This file contains defines and typedefs to be compiled for use in +// the environment package. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// + + + // pragma uvmf custom additional begin + // pragma uvmf custom additional end + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/environment_packages/subsys_env_pkg/src/subsys_environment.svh b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/environment_packages/subsys_env_pkg/src/subsys_environment.svh new file mode 100644 index 00000000..721e6178 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/environment_packages/subsys_env_pkg/src/subsys_environment.svh @@ -0,0 +1,135 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This environment contains all agents, predictors and +// scoreboards required for the block level design. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// + +class subsys_environment extends uvmf_environment_base #( + .CONFIG_T( subsys_env_configuration + )); + `uvm_component_utils( subsys_environment ) + + typedef block_1_environment b1_t; + b1_t b1; + + typedef block_2_environment b2_t; + b2_t b2; + + + + uvm_analysis_port #(block_1_environment) block_1_ap1; + uvm_analysis_port #(block_1_environment) block_1_ap2; + uvm_analysis_port #(block_1_environment) block_1_ap3; + uvm_analysis_port #(block_2_environment) block_2_ap1; + + + + + + typedef subsys_predictor #( + .CONFIG_T(CONFIG_T) + ) sub_pred_t; + sub_pred_t sub_pred; + typedef subsys_scoreboard #( + .CONFIG_T(CONFIG_T) + ) sub_sb_t; + sub_sb_t sub_sb; + + + + + typedef uvmf_virtual_sequencer_base #(.CONFIG_T(subsys_env_configuration)) subsys_vsqr_t; + subsys_vsqr_t vsqr; + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + +// **************************************************************************** +// FUNCTION : new() +// This function is the standard SystemVerilog constructor. +// + function new( string name = "", uvm_component parent = null ); + super.new( name, parent ); + endfunction + +// **************************************************************************** +// FUNCTION: build_phase() +// This function builds all components within this environment. +// + virtual function void build_phase(uvm_phase phase); +// pragma uvmf custom build_phase_pre_super begin +// pragma uvmf custom build_phase_pre_super end + super.build_phase(phase); + b1 = b1_t::type_id::create("b1",this); + b1.set_config(configuration.b1_config); + b2 = b2_t::type_id::create("b2",this); + b2.set_config(configuration.b2_config); + block_1_ap1 = new("block_1_ap1",this); + block_1_ap2 = new("block_1_ap2",this); + block_1_ap3 = new("block_1_ap3",this); + block_2_ap1 = new("block_2_ap1",this); + sub_pred = sub_pred_t::type_id::create("sub_pred",this); + sub_pred.configuration = configuration; + sub_sb = sub_sb_t::type_id::create("sub_sb",this); + sub_sb.configuration = configuration; + + vsqr = subsys_vsqr_t::type_id::create("vsqr", this); + vsqr.set_config(configuration); + configuration.set_vsqr(vsqr); + + // pragma uvmf custom build_phase begin + // pragma uvmf custom build_phase end + endfunction + +// **************************************************************************** +// FUNCTION: connect_phase() +// This function makes all connections within this environment. Connections +// typically inclue agent to predictor, predictor to scoreboard and scoreboard +// to agent. +// + virtual function void connect_phase(uvm_phase phase); +// pragma uvmf custom connect_phase_pre_super begin +// pragma uvmf custom connect_phase_pre_super end + super.connect_phase(phase); + b1.apb_master_ap.connect(sub_pred.subsys_apb_ae); + b1.axi_master1_ap.connect(sub_pred.subsys_axi_1_ae); + b1.axi_master2_ap.connect(sub_pred.subsys_axi_2_ae); + sub_pred.subsys_pre_to_sco_ap.connect(sub_sb.subsys_sco_from_pre_ae); + b2.wb_slave_ap.connect(sub_sb.subsys_wb_ae); + b1.apb_master_ap.connect(block_1_ap1); + b1.axi_master1_ap.connect(block_1_ap2); + b1.axi_master2_ap.connect(block_1_ap3); + b2.wb_slave_ap.connect(block_2_ap1); + // pragma uvmf custom reg_model_connect_phase begin + // pragma uvmf custom reg_model_connect_phase end + endfunction + +// **************************************************************************** +// FUNCTION: end_of_simulation_phase() +// This function is executed just prior to executing run_phase. This function +// was added to the environment to sample environment configuration settings +// just before the simulation exits time 0. The configuration structure is +// randomized in the build phase before the environment structure is constructed. +// Configuration variables can be customized after randomization in the build_phase +// of the extended test. +// If a sequence modifies values in the configuration structure then the sequence is +// responsible for sampling the covergroup in the configuration if required. +// + virtual function void start_of_simulation_phase(uvm_phase phase); + configuration.subsys_configuration_cg.sample(); + endfunction + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/environment_packages/subsys_env_pkg/src/subsys_predictor.svh b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/environment_packages/subsys_env_pkg/src/subsys_predictor.svh new file mode 100644 index 00000000..ca687342 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/environment_packages/subsys_env_pkg/src/subsys_predictor.svh @@ -0,0 +1,176 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +// +//---------------------------------------------------------------------- +// +// DESCRIPTION: This analysis component contains analysis_exports for receiving +// data and analysis_ports for sending data. +// +// This analysis component has the following analysis_exports that receive the +// listed transaction type. +// +// subsys_apb_ae receives transactions of type block_1_environment +// subsys_axi_1_ae receives transactions of type block_1_environment +// subsys_axi_2_ae receives transactions of type block_1_environment +// +// This analysis component has the following analysis_ports that can broadcast +// the listed transaction type. +// +// subsys_pre_to_sco_ap broadcasts transactions of type block_2_environment +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// + +class subsys_predictor #( + type CONFIG_T, + type BASE_T = uvm_component + ) extends BASE_T; + + // Factory registration of this class + `uvm_component_param_utils( subsys_predictor #( + CONFIG_T, + BASE_T + )) + + + // Instantiate a handle to the configuration of the environment in which this component resides + CONFIG_T configuration; + + + // Instantiate the analysis exports + uvm_analysis_imp_subsys_apb_ae #(block_1_environment, subsys_predictor #( + .CONFIG_T(CONFIG_T), + .BASE_T(BASE_T) + )) subsys_apb_ae; + uvm_analysis_imp_subsys_axi_1_ae #(block_1_environment, subsys_predictor #( + .CONFIG_T(CONFIG_T), + .BASE_T(BASE_T) + )) subsys_axi_1_ae; + uvm_analysis_imp_subsys_axi_2_ae #(block_1_environment, subsys_predictor #( + .CONFIG_T(CONFIG_T), + .BASE_T(BASE_T) + )) subsys_axi_2_ae; + + + // Instantiate the analysis ports + uvm_analysis_port #(block_2_environment) subsys_pre_to_sco_ap; + + + // Transaction variable for predicted values to be sent out subsys_pre_to_sco_ap + // Once a transaction is sent through an analysis_port, another transaction should + // be constructed for the next predicted transaction. + typedef block_2_environment subsys_pre_to_sco_ap_output_transaction_t; + subsys_pre_to_sco_ap_output_transaction_t subsys_pre_to_sco_ap_output_transaction; + // Code for sending output transaction out through subsys_pre_to_sco_ap + // subsys_pre_to_sco_ap.write(subsys_pre_to_sco_ap_output_transaction); + + // Define transaction handles for debug visibility + block_1_environment subsys_apb_ae_debug; + block_1_environment subsys_axi_1_ae_debug; + block_1_environment subsys_axi_2_ae_debug; + + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + // FUNCTION: new + function new(string name, uvm_component parent); + super.new(name,parent); + `uvm_warning("PREDICTOR_REVIEW", "This predictor has been created either through generation or re-generation with merging. Remove this warning after the predictor has been reviewed.") + // pragma uvmf custom new begin + // pragma uvmf custom new end + endfunction + + // FUNCTION: build_phase + virtual function void build_phase (uvm_phase phase); + + subsys_apb_ae = new("subsys_apb_ae", this); + subsys_axi_1_ae = new("subsys_axi_1_ae", this); + subsys_axi_2_ae = new("subsys_axi_2_ae", this); + subsys_pre_to_sco_ap =new("subsys_pre_to_sco_ap", this ); + // pragma uvmf custom build_phase begin + // pragma uvmf custom build_phase end + endfunction + + // FUNCTION: write_subsys_apb_ae + // Transactions received through subsys_apb_ae initiate the execution of this function. + // This function performs prediction of DUT output values based on DUT input, configuration and state + virtual function void write_subsys_apb_ae(block_1_environment t); + // pragma uvmf custom subsys_apb_ae_predictor begin + subsys_apb_ae_debug = t; + `uvm_info("PRED", "Transaction Received through subsys_apb_ae", UVM_MEDIUM) + `uvm_info("PRED", {" Data: ",t.convert2string()}, UVM_FULL) + // Construct one of each output transaction type. + subsys_pre_to_sco_ap_output_transaction = subsys_pre_to_sco_ap_output_transaction_t::type_id::create("subsys_pre_to_sco_ap_output_transaction"); + // UVMF_CHANGE_ME: Implement predictor model here. + `uvm_info("UNIMPLEMENTED_PREDICTOR_MODEL", "******************************************************************************************************",UVM_NONE) + `uvm_info("UNIMPLEMENTED_PREDICTOR_MODEL", "UVMF_CHANGE_ME: The subsys_predictor::write_subsys_apb_ae function needs to be completed with DUT prediction model",UVM_NONE) + `uvm_info("UNIMPLEMENTED_PREDICTOR_MODEL", "******************************************************************************************************",UVM_NONE) + + // Code for sending output transaction out through subsys_pre_to_sco_ap + // Please note that each broadcasted transaction should be a different object than previously + // broadcasted transactions. Creation of a different object is done by constructing the transaction + // using either new() or create(). Broadcasting a transaction object more than once to either the + // same subscriber or multiple subscribers will result in unexpected and incorrect behavior. + subsys_pre_to_sco_ap.write(subsys_pre_to_sco_ap_output_transaction); + // pragma uvmf custom subsys_apb_ae_predictor end + endfunction + + // FUNCTION: write_subsys_axi_1_ae + // Transactions received through subsys_axi_1_ae initiate the execution of this function. + // This function performs prediction of DUT output values based on DUT input, configuration and state + virtual function void write_subsys_axi_1_ae(block_1_environment t); + // pragma uvmf custom subsys_axi_1_ae_predictor begin + subsys_axi_1_ae_debug = t; + `uvm_info("PRED", "Transaction Received through subsys_axi_1_ae", UVM_MEDIUM) + `uvm_info("PRED", {" Data: ",t.convert2string()}, UVM_FULL) + // Construct one of each output transaction type. + subsys_pre_to_sco_ap_output_transaction = subsys_pre_to_sco_ap_output_transaction_t::type_id::create("subsys_pre_to_sco_ap_output_transaction"); + // UVMF_CHANGE_ME: Implement predictor model here. + `uvm_info("UNIMPLEMENTED_PREDICTOR_MODEL", "******************************************************************************************************",UVM_NONE) + `uvm_info("UNIMPLEMENTED_PREDICTOR_MODEL", "UVMF_CHANGE_ME: The subsys_predictor::write_subsys_axi_1_ae function needs to be completed with DUT prediction model",UVM_NONE) + `uvm_info("UNIMPLEMENTED_PREDICTOR_MODEL", "******************************************************************************************************",UVM_NONE) + + // Code for sending output transaction out through subsys_pre_to_sco_ap + // Please note that each broadcasted transaction should be a different object than previously + // broadcasted transactions. Creation of a different object is done by constructing the transaction + // using either new() or create(). Broadcasting a transaction object more than once to either the + // same subscriber or multiple subscribers will result in unexpected and incorrect behavior. + subsys_pre_to_sco_ap.write(subsys_pre_to_sco_ap_output_transaction); + // pragma uvmf custom subsys_axi_1_ae_predictor end + endfunction + + // FUNCTION: write_subsys_axi_2_ae + // Transactions received through subsys_axi_2_ae initiate the execution of this function. + // This function performs prediction of DUT output values based on DUT input, configuration and state + virtual function void write_subsys_axi_2_ae(block_1_environment t); + // pragma uvmf custom subsys_axi_2_ae_predictor begin + subsys_axi_2_ae_debug = t; + `uvm_info("PRED", "Transaction Received through subsys_axi_2_ae", UVM_MEDIUM) + `uvm_info("PRED", {" Data: ",t.convert2string()}, UVM_FULL) + // Construct one of each output transaction type. + subsys_pre_to_sco_ap_output_transaction = subsys_pre_to_sco_ap_output_transaction_t::type_id::create("subsys_pre_to_sco_ap_output_transaction"); + // UVMF_CHANGE_ME: Implement predictor model here. + `uvm_info("UNIMPLEMENTED_PREDICTOR_MODEL", "******************************************************************************************************",UVM_NONE) + `uvm_info("UNIMPLEMENTED_PREDICTOR_MODEL", "UVMF_CHANGE_ME: The subsys_predictor::write_subsys_axi_2_ae function needs to be completed with DUT prediction model",UVM_NONE) + `uvm_info("UNIMPLEMENTED_PREDICTOR_MODEL", "******************************************************************************************************",UVM_NONE) + + // Code for sending output transaction out through subsys_pre_to_sco_ap + // Please note that each broadcasted transaction should be a different object than previously + // broadcasted transactions. Creation of a different object is done by constructing the transaction + // using either new() or create(). Broadcasting a transaction object more than once to either the + // same subscriber or multiple subscribers will result in unexpected and incorrect behavior. + subsys_pre_to_sco_ap.write(subsys_pre_to_sco_ap_output_transaction); + // pragma uvmf custom subsys_axi_2_ae_predictor end + endfunction + + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/environment_packages/subsys_env_pkg/src/subsys_scoreboard.svh b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/environment_packages/subsys_env_pkg/src/subsys_scoreboard.svh new file mode 100644 index 00000000..93aa6b99 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/environment_packages/subsys_env_pkg/src/subsys_scoreboard.svh @@ -0,0 +1,131 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This analysis component contains analysis_exports for receiving +// data and analysis_ports for sending data. +// +// This analysis component has the following analysis_exports that receive the +// listed transaction type. +// +// subsys_sco_from_pre_ae receives transactions of type block_2_environment +// subsys_wb_ae receives transactions of type block_2_environment +// +// This analysis component has the following analysis_ports that can broadcast +// the listed transaction type. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// + + +class subsys_scoreboard #( + type CONFIG_T, + type BASE_T = uvm_component + ) extends BASE_T; + + // Factory registration of this class + `uvm_component_param_utils( subsys_scoreboard #( + CONFIG_T, + BASE_T + )) + + + // Instantiate a handle to the configuration of the environment in which this component resides + CONFIG_T configuration; + + + // Instantiate the analysis exports + uvm_analysis_imp_subsys_sco_from_pre_ae #(block_2_environment, subsys_scoreboard #( + .CONFIG_T(CONFIG_T), + .BASE_T(BASE_T) + )) subsys_sco_from_pre_ae; + uvm_analysis_imp_subsys_wb_ae #(block_2_environment, subsys_scoreboard #( + .CONFIG_T(CONFIG_T), + .BASE_T(BASE_T) + )) subsys_wb_ae; + + + + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + // FUNCTION: new + function new(string name, uvm_component parent); + super.new(name,parent); + // pragma uvmf custom new begin + // pragma uvmf custom new end + endfunction + + // FUNCTION: build_phase + virtual function void build_phase (uvm_phase phase); + + subsys_sco_from_pre_ae = new("subsys_sco_from_pre_ae", this); + subsys_wb_ae = new("subsys_wb_ae", this); + // pragma uvmf custom build_phase begin + // pragma uvmf custom build_phase end + endfunction + + // FUNCTION: write_subsys_sco_from_pre_ae + // Transactions received through subsys_sco_from_pre_ae initiate the execution of this function. + // This function performs prediction of DUT output values based on DUT input, configuration and state + virtual function void write_subsys_sco_from_pre_ae(block_2_environment t); + // pragma uvmf custom subsys_sco_from_pre_ae_scoreboard begin + `uvm_info("PRED", "Transaction Received through subsys_sco_from_pre_ae", UVM_MEDIUM) + `uvm_info("PRED", {" Data: ",t.convert2string()}, UVM_FULL) + // UVMF_CHANGE_ME: Implement custom scoreboard here. + `uvm_info("UNIMPLEMENTED_CUSTOM_SCOREBOARD", "******************************************************************************************************",UVM_NONE) + `uvm_info("UNIMPLEMENTED_CUSTOM_SCOREBOARD", "UVMF_CHANGE_ME: The subsys_scoreboard::write_subsys_sco_from_pre_ae function needs to be completed with custom scoreboard functionality",UVM_NONE) + `uvm_info("UNIMPLEMENTED_CUSTOM_SCOREBOARD", "******************************************************************************************************",UVM_NONE) + + // pragma uvmf custom subsys_sco_from_pre_ae_scoreboard end + endfunction + + // FUNCTION: write_subsys_wb_ae + // Transactions received through subsys_wb_ae initiate the execution of this function. + // This function performs prediction of DUT output values based on DUT input, configuration and state + virtual function void write_subsys_wb_ae(block_2_environment t); + // pragma uvmf custom subsys_wb_ae_scoreboard begin + `uvm_info("PRED", "Transaction Received through subsys_wb_ae", UVM_MEDIUM) + `uvm_info("PRED", {" Data: ",t.convert2string()}, UVM_FULL) + // UVMF_CHANGE_ME: Implement custom scoreboard here. + `uvm_info("UNIMPLEMENTED_CUSTOM_SCOREBOARD", "******************************************************************************************************",UVM_NONE) + `uvm_info("UNIMPLEMENTED_CUSTOM_SCOREBOARD", "UVMF_CHANGE_ME: The subsys_scoreboard::write_subsys_wb_ae function needs to be completed with custom scoreboard functionality",UVM_NONE) + `uvm_info("UNIMPLEMENTED_CUSTOM_SCOREBOARD", "******************************************************************************************************",UVM_NONE) + + // pragma uvmf custom subsys_wb_ae_scoreboard end + endfunction + + + + // FUNCTION: extract_phase + virtual function void extract_phase(uvm_phase phase); +// pragma uvmf custom extract_phase begin + super.extract_phase(phase); +// pragma uvmf custom extract_phase end + endfunction + + // FUNCTION: check_phase + virtual function void check_phase(uvm_phase phase); +// pragma uvmf custom check_phase begin + super.check_phase(phase); +// pragma uvmf custom check_phase end + endfunction + + // FUNCTION: report_phase + virtual function void report_phase(uvm_phase phase); +// pragma uvmf custom report_phase begin + super.report_phase(phase); +// pragma uvmf custom report_phase end + endfunction + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/environment_packages/subsys_env_pkg/subsys_env_pkg.compile b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/environment_packages/subsys_env_pkg/subsys_env_pkg.compile new file mode 100644 index 00000000..b651f0c9 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/environment_packages/subsys_env_pkg/subsys_env_pkg.compile @@ -0,0 +1,8 @@ +needs: + - $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg.compile + - ../block_1_env_pkg/block_1_env_pkg.compile + - ../block_2_env_pkg/block_2_env_pkg.compile + +src: + - subsys_env_pkg.sv + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/environment_packages/subsys_env_pkg/subsys_env_pkg.sv b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/environment_packages/subsys_env_pkg/subsys_env_pkg.sv new file mode 100644 index 00000000..19448992 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/environment_packages/subsys_env_pkg/subsys_env_pkg.sv @@ -0,0 +1,59 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// PACKAGE: This file defines all of the files contained in the +// environment package that will run on the host simulator. +// +// CONTAINS: +// - +// - +// - +// - +// - +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +package subsys_env_pkg; + + import uvm_pkg::*; + `include "uvm_macros.svh" + import uvmf_base_pkg::*; + import block_1_env_pkg::*; + import block_2_env_pkg::*; + + `uvm_analysis_imp_decl(_subsys_apb_ae) + `uvm_analysis_imp_decl(_subsys_axi_1_ae) + `uvm_analysis_imp_decl(_subsys_axi_2_ae) + `uvm_analysis_imp_decl(_subsys_sco_from_pre_ae) + `uvm_analysis_imp_decl(_subsys_wb_ae) + + // pragma uvmf custom package_imports_additional begin + // pragma uvmf custom package_imports_additional end + + // Parameters defined as HVL parameters + + `include "src/subsys_env_typedefs.svh" + `include "src/subsys_env_configuration.svh" + `include "src/subsys_predictor.svh" + `include "src/subsys_scoreboard.svh" + `include "src/subsys_environment.svh" + `include "src/subsys_env_sequence_base.svh" + + // pragma uvmf custom package_item_additional begin + // UVMF_CHANGE_ME : When adding new environment level sequences to the src directory + // be sure to add the sequence file here so that it will be + // compiled as part of the environment package. Be sure to place + // the new sequence after any base sequence of the new sequence. + // pragma uvmf custom package_item_additional end + +endpackage + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/environment_packages/subsys_env_pkg/subsys_env_pkg.vinfo b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/environment_packages/subsys_env_pkg/subsys_env_pkg.vinfo new file mode 100644 index 00000000..e98bf2e3 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/environment_packages/subsys_env_pkg/subsys_env_pkg.vinfo @@ -0,0 +1,5 @@ +@use $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg.vinfo +@use $UVMF_VIP_LIBRARY_HOME/environment_packages/b1_pkg/b1_pkg.vinfo +@use $UVMF_VIP_LIBRARY_HOME/environment_packages/b2_pkg/b2_pkg.vinfo ++incdir+@vinfodir +subsys_env_pkg.sv diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/environment_packages/subsys_env_pkg/subsys_env_pkg_sve.F b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/environment_packages/subsys_env_pkg/subsys_env_pkg_sve.F new file mode 100644 index 00000000..26dd5cf2 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/environment_packages/subsys_env_pkg/subsys_env_pkg_sve.F @@ -0,0 +1,14 @@ + +// UVM ++incdir+${UVM_HOME}/src +${UVM_HOME}/src/uvm_pkg.sv + +// Common UVMF files +-f ${UVMF_HOME}/common/common_sve.f + +// Sub-Environments +-F ${UVMF_VIP_LIBRARY_HOME}/environment_packages/block_1_env_pkg/block_1_env_pkg_sve.F +-F ${UVMF_VIP_LIBRARY_HOME}/environment_packages/block_2_env_pkg/block_2_env_pkg_sve.F + ++incdir+. +./subsys_env_pkg.sv diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/environment_packages/subsys_env_pkg/yaml/subsys_environment.yaml b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/environment_packages/subsys_env_pkg/yaml/subsys_environment.yaml new file mode 100644 index 00000000..1357ebc4 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/environment_packages/subsys_env_pkg/yaml/subsys_environment.yaml @@ -0,0 +1,61 @@ +uvmf: + environments: + subsys: + agents: [] + analysis_components: + - name: sub_pred + parameters: [] + type: subsys_predictor + - name: sub_sb + parameters: [] + type: subsys_scoreboard + analysis_exports: [] + analysis_ports: + - connected_to: b1.apb_master_ap + name: block_1_ap1 + trans_type: block_1_environment + - connected_to: b1.axi_master1_ap + name: block_1_ap2 + trans_type: block_1_environment + - connected_to: b1.axi_master2_ap + name: block_1_ap3 + trans_type: block_1_environment + - connected_to: b2.wb_slave_ap + name: block_2_ap1 + trans_type: block_2_environment + config_constraints: [] + config_vars: + - comment: '' + isrand: 'False' + name: has_scoreboard + type: bit + value: '' + existing_library_component: 'True' + hvl_pkg_parameters: [] + non_uvmf_components: [] + parameters: [] + qvip_memory_agents: [] + scoreboards: [] + subenvs: + - name: b1 + parameters: [] + type: block_1 + - name: b2 + parameters: [] + type: block_2 + tlm_connections: + - driver: b1.apb_master_ap + receiver: sub_pred.subsys_apb_ae + validate: 'True' + - driver: b1.axi_master1_ap + receiver: sub_pred.subsys_axi_1_ae + validate: 'True' + - driver: b1.axi_master2_ap + receiver: sub_pred.subsys_axi_2_ae + validate: 'True' + - driver: sub_pred.subsys_pre_to_sco_ap + receiver: sub_sb.subsys_sco_from_pre_ae + validate: 'True' + - driver: b2.wb_slave_ap + receiver: sub_sb.subsys_wb_ae + validate: 'True' diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/environment_packages/subsys_env_pkg/yaml/subsys_util_comp_subsys_predictor.yaml b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/environment_packages/subsys_env_pkg/yaml/subsys_util_comp_subsys_predictor.yaml new file mode 100644 index 00000000..8e34a21a --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/environment_packages/subsys_env_pkg/yaml/subsys_util_comp_subsys_predictor.yaml @@ -0,0 +1,15 @@ +uvmf: + util_components: + subsys_predictor: + analysis_exports: + - name: subsys_apb_ae + type: block_1_environment + - name: subsys_axi_1_ae + type: block_1_environment + - name: subsys_axi_2_ae + type: block_1_environment + analysis_ports: + - name: subsys_pre_to_sco_ap + type: block_2_environment + existing_library_component: 'True' + type: predictor diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/environment_packages/subsys_env_pkg/yaml/subsys_util_comp_subsys_scoreboard.yaml b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/environment_packages/subsys_env_pkg/yaml/subsys_util_comp_subsys_scoreboard.yaml new file mode 100644 index 00000000..928c0f6c --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/environment_packages/subsys_env_pkg/yaml/subsys_util_comp_subsys_scoreboard.yaml @@ -0,0 +1,10 @@ +uvmf: + util_components: + subsys_scoreboard: + analysis_exports: + - name: subsys_sco_from_pre_ae + type: block_2_environment + - name: subsys_wb_ae + type: block_2_environment + existing_library_component: 'True' + type: scoreboard diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/apb_m_pkg/.project b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/apb_m_pkg/.project new file mode 100644 index 00000000..6da82621 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/apb_m_pkg/.project @@ -0,0 +1,30 @@ + + + apb_m_pkg + + + + + + org.python.pydev.PyDevBuilder + + + + + net.sf.sveditor.core.SVProjectBuilder + + + + + + net.sf.sveditor.core.SVNature + org.python.pydev.pythonNature + + + + UVMF_VIP_LIBRARY_HOME + $%7BPARENT-2-PROJECT_LOC%7D + + + + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/apb_m_pkg/.svproject b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/apb_m_pkg/.svproject new file mode 100644 index 00000000..e17b552f --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/apb_m_pkg/.svproject @@ -0,0 +1,16 @@ + + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/apb_m_pkg/Makefile b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/apb_m_pkg/Makefile new file mode 100644 index 00000000..eec7d999 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/apb_m_pkg/Makefile @@ -0,0 +1,66 @@ +# apb_m interface packages source +# pragma uvmf custom additional begin +# pragma uvmf custom additional end + +apb_m_PKG = \ + +incdir+$(UVMF_VIP_LIBRARY_HOME)/interface_packages/apb_m_pkg \ + -F $(UVMF_VIP_LIBRARY_HOME)/interface_packages/apb_m_pkg/apb_m_filelist_hvl.f + +apb_m_PKG_HDL = \ + +incdir+$(UVMF_VIP_LIBRARY_HOME)/interface_packages/apb_m_pkg \ + -F $(UVMF_VIP_LIBRARY_HOME)/interface_packages/apb_m_pkg/apb_m_filelist_hdl.f + +apb_m_PKG_XRTL = \ + +incdir+$(UVMF_VIP_LIBRARY_HOME)/interface_packages/apb_m_pkg \ + -F $(UVMF_VIP_LIBRARY_HOME)/interface_packages/apb_m_pkg/apb_m_filelist_xrtl.f + +COMP_apb_m_PKG_TGT_0 = q_comp_apb_m_pkg +COMP_apb_m_PKG_TGT_1 = v_comp_apb_m_pkg +COMP_apb_m_PKG_TGT = $(COMP_apb_m_PKG_TGT_$(USE_VELOCE)) + +comp_apb_m_pkg: $(COMP_apb_m_PKG_TGT) + +q_comp_apb_m_pkg: + $(HDL_COMP_CMD) $(apb_m_PKG_HDL) + $(HVL_COMP_CMD) $(apb_m_PKG) + $(HDL_COMP_CMD) $(apb_m_PKG_XRTL) + +v_comp_apb_m_pkg: + $(HVL_COMP_CMD) $(apb_m_PKG_HDL) + $(HVL_COMP_CMD) $(apb_m_PKG) + $(VELANALYZE_CMD) $(apb_m_PKG_HDL) + $(VELANALYZE_HVL_CMD) $(apb_m_PKG) + $(HDL_COMP_CMD) $(apb_m_PKG_XRTL) + +ifeq ($(MTI_VCO_MODE),64) + GCC_COMP_ARCH = -m64 +else + GCC_COMP_ARCH = -m32 +endif + +export apb_m_IF_DPI_SRC ?= $(UVMF_VIP_LIBRARY_HOME)/interface_packages/apb_m_pkg/dpi + +C_FILE_COMPILE_LIST_apb_m_pkg = \ + +O_FILE_COMPILE_LIST_apb_m_pkg = $(notdir $(C_FILE_COMPILE_LIST_apb_m_pkg:.c=.o)) + +GCC_COMP_ARGS_apb_m_pkg += -I$(apb_m_IF_DPI_SRC) \ + -fPIC + +GCC_COMP_ARGS_apb_m_pkg += $(apb_m_IF_GCC_COMP_ARGUMENTS) + +GCC_LINK_ARGS_apb_m_pkg += \ + \ + -o .so + +comp_apb_m_pkg_c_files: + @echo "--------------------------------" + @echo "Compiling Interface C source" + @echo "--------------------------------" + gcc $(GCC_COMP_ARCH) $(GCC_COMP_ARGS_apb_m_pkg) $(C_FILE_COMPILE_LIST_apb_m_pkg) + @echo "--------------------------------" + @echo "Linking Interface C objects into a shared object" + @echo "--------------------------------" + gcc $(GCC_COMP_ARCH) $(GCC_LINK_ARGS_apb_m_pkg) $(O_FILE_COMPILE_LIST_apb_m_pkg) + @echo "--------------------------------" + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/apb_m_pkg/apb_m.compile b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/apb_m_pkg/apb_m.compile new file mode 100644 index 00000000..d77eb23e --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/apb_m_pkg/apb_m.compile @@ -0,0 +1,3 @@ +needs: + - apb_m_hvl.compile + - apb_m_hdl.compile diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/apb_m_pkg/apb_m_bfm.vinfo b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/apb_m_pkg/apb_m_bfm.vinfo new file mode 100644 index 00000000..8d4b80f9 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/apb_m_pkg/apb_m_bfm.vinfo @@ -0,0 +1,6 @@ +@use $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg_hdl.vinfo +@use apb_m_pkg_hdl.vinfo ++incdir+@vinfodir +src/apb_m_if.sv +src/apb_m_driver_bfm.sv +src/apb_m_monitor_bfm.sv diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/apb_m_pkg/apb_m_common.compile b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/apb_m_pkg/apb_m_common.compile new file mode 100644 index 00000000..26821a84 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/apb_m_pkg/apb_m_common.compile @@ -0,0 +1,7 @@ +needs: + - $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg_hdl.compile +incdir: + - . + - ${uvm_path}/src +src: + - apb_m_pkg_hdl.sv diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/apb_m_pkg/apb_m_filelist_hdl.f b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/apb_m_pkg/apb_m_filelist_hdl.f new file mode 100644 index 00000000..0d2a4c9d --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/apb_m_pkg/apb_m_filelist_hdl.f @@ -0,0 +1 @@ +$UVMF_VIP_LIBRARY_HOME/interface_packages/apb_m_pkg/apb_m_pkg_hdl.sv diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/apb_m_pkg/apb_m_filelist_hvl.f b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/apb_m_pkg/apb_m_filelist_hvl.f new file mode 100644 index 00000000..0d4b8d6b --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/apb_m_pkg/apb_m_filelist_hvl.f @@ -0,0 +1 @@ +$UVMF_VIP_LIBRARY_HOME/interface_packages/apb_m_pkg/apb_m_pkg.sv \ No newline at end of file diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/apb_m_pkg/apb_m_filelist_xrtl.f b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/apb_m_pkg/apb_m_filelist_xrtl.f new file mode 100644 index 00000000..d2cef722 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/apb_m_pkg/apb_m_filelist_xrtl.f @@ -0,0 +1,3 @@ +$UVMF_VIP_LIBRARY_HOME/interface_packages/apb_m_pkg/src/apb_m_if.sv +$UVMF_VIP_LIBRARY_HOME/interface_packages/apb_m_pkg/src/apb_m_monitor_bfm.sv +$UVMF_VIP_LIBRARY_HOME/interface_packages/apb_m_pkg/src/apb_m_driver_bfm.sv diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/apb_m_pkg/apb_m_hdl.compile b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/apb_m_pkg/apb_m_hdl.compile new file mode 100644 index 00000000..83ce2876 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/apb_m_pkg/apb_m_hdl.compile @@ -0,0 +1,9 @@ +needs: + - $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg_hdl.compile + - ./apb_m_common.compile +incdir: + - . +src: + - src/apb_m_if.sv + - src/apb_m_monitor_bfm.sv + - src/apb_m_driver_bfm.sv diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/apb_m_pkg/apb_m_hvl.compile b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/apb_m_pkg/apb_m_hvl.compile new file mode 100644 index 00000000..2b4533f6 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/apb_m_pkg/apb_m_hvl.compile @@ -0,0 +1,7 @@ +needs: + - $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg.compile + - ./apb_m_common.compile +incdir: + - . +src: + - apb_m_pkg.sv diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/apb_m_pkg/apb_m_pkg.sv b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/apb_m_pkg/apb_m_pkg.sv new file mode 100644 index 00000000..453883f5 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/apb_m_pkg/apb_m_pkg.sv @@ -0,0 +1,77 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// PACKAGE: This file defines all of the files contained in the +// interface package that will run on the host simulator. +// +// CONTAINS: +// - +// - +// - + +// - +// - +// - + +// - +// - +// - + +// - +// - +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +package apb_m_pkg; + + import uvm_pkg::*; + import uvmf_base_pkg_hdl::*; + import uvmf_base_pkg::*; + import apb_m_pkg_hdl::*; + + `include "uvm_macros.svh" + + // pragma uvmf custom package_imports_additional begin + // pragma uvmf custom package_imports_additional end + `include "src/apb_m_macros.svh" + + export apb_m_pkg_hdl::*; + + + + // Parameters defined as HVL parameters + + `include "src/apb_m_typedefs.svh" + `include "src/apb_m_transaction.svh" + + `include "src/apb_m_configuration.svh" + `include "src/apb_m_driver.svh" + `include "src/apb_m_monitor.svh" + + `include "src/apb_m_transaction_coverage.svh" + `include "src/apb_m_sequence_base.svh" + `include "src/apb_m_random_sequence.svh" + + `include "src/apb_m_responder_sequence.svh" + `include "src/apb_m2reg_adapter.svh" + + `include "src/apb_m_agent.svh" + + // pragma uvmf custom package_item_additional begin + // UVMF_CHANGE_ME : When adding new interface sequences to the src directory + // be sure to add the sequence file here so that it will be + // compiled as part of the interface package. Be sure to place + // the new sequence after any base sequences of the new sequence. + // pragma uvmf custom package_item_additional end + +endpackage + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/apb_m_pkg/apb_m_pkg.vinfo b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/apb_m_pkg/apb_m_pkg.vinfo new file mode 100644 index 00000000..e6a8b7c1 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/apb_m_pkg/apb_m_pkg.vinfo @@ -0,0 +1,4 @@ +@use $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg.vinfo +@use apb_m_pkg_hdl.vinfo ++incdir+@vinfodir +apb_m_pkg.sv diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/apb_m_pkg/apb_m_pkg_hdl.sv b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/apb_m_pkg/apb_m_pkg_hdl.sv new file mode 100644 index 00000000..b657eb44 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/apb_m_pkg/apb_m_pkg_hdl.sv @@ -0,0 +1,38 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// PACKAGE: This file defines all of the files contained in the +// interface package that needs to be compiled and synthesized +// for running on Veloce. +// +// CONTAINS: +// - +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +package apb_m_pkg_hdl; + + import uvmf_base_pkg_hdl::*; + + // pragma uvmf custom package_imports_additional begin + // pragma uvmf custom package_imports_additional end + + // Parameters defined as HDL parameters + + `include "src/apb_m_typedefs_hdl.svh" + `include "src/apb_m_macros.svh" + + // pragma uvmf custom package_item_additional begin + // pragma uvmf custom package_item_additional end + +endpackage + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/apb_m_pkg/apb_m_pkg_hdl.vinfo b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/apb_m_pkg/apb_m_pkg_hdl.vinfo new file mode 100644 index 00000000..3e5dc166 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/apb_m_pkg/apb_m_pkg_hdl.vinfo @@ -0,0 +1,2 @@ +@use $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg_hdl.vinfo +apb_m_pkg_hdl.sv diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/apb_m_pkg/apb_m_pkg_sve.F b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/apb_m_pkg/apb_m_pkg_sve.F new file mode 100644 index 00000000..b934c1a1 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/apb_m_pkg/apb_m_pkg_sve.F @@ -0,0 +1,10 @@ +// UVM ++incdir+${UVM_HOME}/src +${UVM_HOME}/src/uvm_pkg.sv + +// Common UVMF files +-f ${UVMF_HOME}/common/common_sve.f + ++incdir+. +-f ${UVMF_VIP_LIBRARY_HOME}/interface_packages/apb_m_pkg/apb_m_filelist_hdl.f +-f ${UVMF_VIP_LIBRARY_HOME}/interface_packages/apb_m_pkg/apb_m_filelist_hvl.f diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/apb_m_pkg/compile.do b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/apb_m_pkg/compile.do new file mode 100644 index 00000000..944fd712 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/apb_m_pkg/compile.do @@ -0,0 +1,14 @@ +# Tcl do file for compile of apb_m interface + +# pragma uvmf custom additional begin +# pragma uvmf custom additional end + + +vlog -sv -timescale 1ps/1ps -suppress 2223,2286 +incdir+$env(UVMF_VIP_LIBRARY_HOME)/interface_packages/apb_m_pkg \ + -F $env(UVMF_VIP_LIBRARY_HOME)/interface_packages/apb_m_pkg/apb_m_filelist_hdl.f + +vlog -sv -timescale 1ps/1ps -suppress 2223,2286 +incdir+$env(UVMF_VIP_LIBRARY_HOME)/interface_packages/apb_m_pkg \ + -F $env(UVMF_VIP_LIBRARY_HOME)/interface_packages/apb_m_pkg/apb_m_filelist_hvl.f + +vlog -sv -timescale 1ps/1ps -suppress 2223,2286 +incdir+$env(UVMF_VIP_LIBRARY_HOME)/interface_packages/apb_m_pkg \ + -F $env(UVMF_VIP_LIBRARY_HOME)/interface_packages/apb_m_pkg/apb_m_filelist_xrtl.f \ No newline at end of file diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/apb_m_pkg/src/apb_m2reg_adapter.svh b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/apb_m_pkg/src/apb_m2reg_adapter.svh new file mode 100644 index 00000000..bbbd0c42 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/apb_m_pkg/src/apb_m2reg_adapter.svh @@ -0,0 +1,118 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: +// This file contains the UVM register adapter for the apb_m interface. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class apb_m2reg_adapter #( + int APB_ADDR_WIDTH = 32, + int APB_DATA_WIDTH = 32, + int STRB_LEN = APB_ADDR_WIDTH/8 + ) extends uvm_reg_adapter; + + `uvm_object_param_utils( apb_m2reg_adapter #( + APB_ADDR_WIDTH, + APB_DATA_WIDTH, + STRB_LEN + )) + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + //-------------------------------------------------------------------- + // new + //-------------------------------------------------------------------- + function new (string name = "apb_m2reg_adapter" ); + super.new(name); + // pragma uvmf custom new begin + // UVMF_CHANGE_ME : Configure the adapter regarding byte enables and provides response. + + // Does the protocol the Agent is modeling support byte enables? + // 0 = NO + // 1 = YES + supports_byte_enable = 0; + + // Does the Agent's Driver provide separate response sequence items? + // i.e. Does the driver call seq_item_port.put() + // and do the sequences call get_response()? + // 0 = NO + // 1 = YES + provides_responses = 0; + // pragma uvmf custom new end + + endfunction: new + + //-------------------------------------------------------------------- + // reg2bus + //-------------------------------------------------------------------- + virtual function uvm_sequence_item reg2bus(const ref uvm_reg_bus_op rw); + + apb_m_transaction #( + .APB_ADDR_WIDTH(APB_ADDR_WIDTH), + .APB_DATA_WIDTH(APB_DATA_WIDTH), + .STRB_LEN(STRB_LEN) + ) trans_h = apb_m_transaction #( + .APB_ADDR_WIDTH(APB_ADDR_WIDTH), + .APB_DATA_WIDTH(APB_DATA_WIDTH), + .STRB_LEN(STRB_LEN) + )::type_id::create("trans_h"); + + // pragma uvmf custom reg2bus begin + // UVMF_CHANGE_ME : Fill in the reg2bus adapter mapping registe fields to protocol fields. + + //Adapt the following for your sequence item type + // trans_h.op = (rw.kind == UVM_READ) ? WB_READ : WB_WRITE; + //Copy over address + // trans_h.addr = rw.addr; + //Copy over write data + // trans_h.data = rw.data; + + // pragma uvmf custom reg2bus end + + // Return the adapted transaction + return trans_h; + + endfunction: reg2bus + + //-------------------------------------------------------------------- + // bus2reg + //-------------------------------------------------------------------- + virtual function void bus2reg(uvm_sequence_item bus_item, + ref uvm_reg_bus_op rw); + apb_m_transaction #( + .APB_ADDR_WIDTH(APB_ADDR_WIDTH), + .APB_DATA_WIDTH(APB_DATA_WIDTH), + .STRB_LEN(STRB_LEN) + ) trans_h; + if (!$cast(trans_h, bus_item)) begin + `uvm_fatal("ADAPT","Provided bus_item is not of the correct type") + return; + end + // pragma uvmf custom bus2reg begin + // UVMF_CHANGE_ME : Fill in the bus2reg adapter mapping protocol fields to register fields. + //Adapt the following for your sequence item type + //Copy over instruction type + // rw.kind = (trans_h.op == WB_WRITE) ? UVM_WRITE : UVM_READ; + //Copy over address + // rw.addr = trans_h.addr; + //Copy over read data + // rw.data = trans_h.data; + //Check for errors on the bus and return UVM_NOT_OK if there is an error + // rw.status = UVM_IS_OK; + // pragma uvmf custom bus2reg end + + endfunction: bus2reg + +endclass : apb_m2reg_adapter + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/apb_m_pkg/src/apb_m_agent.svh b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/apb_m_pkg/src/apb_m_agent.svh new file mode 100644 index 00000000..8fbbff4d --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/apb_m_pkg/src/apb_m_agent.svh @@ -0,0 +1,81 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: Protocol specific agent class definition +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class apb_m_agent #( + int APB_ADDR_WIDTH = 32, + int APB_DATA_WIDTH = 32, + int STRB_LEN = APB_ADDR_WIDTH/8 + ) extends uvmf_parameterized_agent #( + .CONFIG_T(apb_m_configuration #( + .APB_ADDR_WIDTH(APB_ADDR_WIDTH), + .APB_DATA_WIDTH(APB_DATA_WIDTH), + .STRB_LEN(STRB_LEN) + )), + .DRIVER_T(apb_m_driver #( + .APB_ADDR_WIDTH(APB_ADDR_WIDTH), + .APB_DATA_WIDTH(APB_DATA_WIDTH), + .STRB_LEN(STRB_LEN) + )), + .MONITOR_T(apb_m_monitor #( + .APB_ADDR_WIDTH(APB_ADDR_WIDTH), + .APB_DATA_WIDTH(APB_DATA_WIDTH), + .STRB_LEN(STRB_LEN) + )), + .COVERAGE_T(apb_m_transaction_coverage #( + .APB_ADDR_WIDTH(APB_ADDR_WIDTH), + .APB_DATA_WIDTH(APB_DATA_WIDTH), + .STRB_LEN(STRB_LEN) + )), + .TRANS_T(apb_m_transaction #( + .APB_ADDR_WIDTH(APB_ADDR_WIDTH), + .APB_DATA_WIDTH(APB_DATA_WIDTH), + .STRB_LEN(STRB_LEN) + )) + ); + + `uvm_component_param_utils( apb_m_agent #( + APB_ADDR_WIDTH, + APB_DATA_WIDTH, + STRB_LEN + )) + +// pragma uvmf custom class_item_additional begin +// pragma uvmf custom class_item_additional end + +// **************************************************************************** +// FUNCTION : new() +// This function is the standard SystemVerilog constructor. +// + function new( string name = "", uvm_component parent = null ); + super.new( name, parent ); + endfunction + +// **************************************************************************** + // FUNCTION: build_phase + virtual function void build_phase(uvm_phase phase); +// pragma uvmf custom build_phase_pre_super begin +// pragma uvmf custom build_phase_pre_super end + super.build_phase(phase); + if (configuration.active_passive == ACTIVE) begin + // Place sequencer handle into configuration object + // so that it may be retrieved from configuration + // rather than using uvm_config_db + configuration.sequencer = this.sequencer; + end + endfunction + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/apb_m_pkg/src/apb_m_configuration.svh b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/apb_m_pkg/src/apb_m_configuration.svh new file mode 100644 index 00000000..e01c8416 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/apb_m_pkg/src/apb_m_configuration.svh @@ -0,0 +1,211 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This class contains all variables and functions used +// to configure the apb_m agent and its bfm's. It gets the +// bfm's from the uvm_config_db for use by the agent. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class apb_m_configuration #( + int APB_ADDR_WIDTH = 32, + int APB_DATA_WIDTH = 32, + int STRB_LEN = APB_ADDR_WIDTH/8 + ) extends uvmf_parameterized_agent_configuration_base #( + .DRIVER_BFM_BIND_T(virtual apb_m_driver_bfm #( + .APB_ADDR_WIDTH(APB_ADDR_WIDTH), + .APB_DATA_WIDTH(APB_DATA_WIDTH), + .STRB_LEN(STRB_LEN) + )), + .MONITOR_BFM_BIND_T( virtual apb_m_monitor_bfm #( + .APB_ADDR_WIDTH(APB_ADDR_WIDTH), + .APB_DATA_WIDTH(APB_DATA_WIDTH), + .STRB_LEN(STRB_LEN) + ))); + + `uvm_object_param_utils( apb_m_configuration #( + APB_ADDR_WIDTH, + APB_DATA_WIDTH, + STRB_LEN + )) + + + // Sequencer handle populated by agent + uvm_sequencer #(apb_m_transaction #( + .APB_ADDR_WIDTH(APB_ADDR_WIDTH), + .APB_DATA_WIDTH(APB_DATA_WIDTH), + .STRB_LEN(STRB_LEN) + ) ) sequencer; + + //Constraints for the configuration variables: + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + covergroup apb_m_configuration_cg; + // pragma uvmf custom covergroup begin + option.auto_bin_max=1024; + // pragma uvmf custom covergroup end + endgroup + + //******************************************************************* + //******************************************************************* + // Structure used to pass configuration variables to monitor and driver BFM's. + // Use to_struct function to pack variables into structure. + // Use from_struct function to unpack variables from structure. + // This structure is defined in apb_m_macros.svh + `apb_m_CONFIGURATION_STRUCT + apb_m_configuration_s apb_m_configuration_struct; + //******************************************************************* + // FUNCTION: to_struct() + // This function packs variables into a apb_m_configuration_s + // structure. The function returns the handle to the apb_m_configuration_struct. + // This function is defined in apb_m_macros.svh + `apb_m_CONFIGURATION_TO_STRUCT_FUNCTION + //******************************************************************* + // FUNCTION: from_struct() + // This function unpacks the struct provided as an argument into + // variables of this class. + // This function is defined in apb_m_macros.svh + `apb_m_CONFIGURATION_FROM_STRUCT_FUNCTION + + // **************************************************************************** + // FUNCTION : new() + // This function is the standard SystemVerilog constructor. + // + function new( string name = "" ); + super.new( name ); + // Construct the covergroup for this configuration class + apb_m_configuration_cg = new; + endfunction + + // **************************************************************************** + // FUNCTION: post_randomize() + // This function is automatically called after the randomize() function + // is executed. + // + function void post_randomize(); + super.post_randomize(); + apb_m_configuration_cg.sample(); + endfunction + + // **************************************************************************** + // FUNCTION: initialize + // This function causes the configuration to retrieve + // its virtual interface handle from the uvm_config_db. + // This function also makes itself available to its + // agent through the uvm_config_db. + // + // ARGUMENTS: + // uvmf_active_passive_t activity: + // This argument identifies the simulation level + // as either BLOCK, CHIP, SIMULATION, etc. + // + // AGENT_PATH: + // This argument identifies the path to this + // configurations agent. This configuration + // makes itself available to the agent specified + // by agent_path by placing itself into the + // uvm_config_db. + // + // INTERFACE_NAME: + // This argument identifies the string name of + // this configurations BFM's. This string + // name is used to retrieve the driver and + // monitor BFM from the uvm_config_db. + // + virtual function void initialize(uvmf_active_passive_t activity, + string agent_path, + string interface_name); + + super.initialize( activity, agent_path, interface_name); + // The covergroup is given the same name as the interface + apb_m_configuration_cg.set_inst_name(interface_name); + + // This configuration places itself into the uvm_config_db for the agent, identified by the agent_path variable, to retrieve. + uvm_config_db #( apb_m_configuration #( + .APB_ADDR_WIDTH(APB_ADDR_WIDTH), + .APB_DATA_WIDTH(APB_DATA_WIDTH), + .STRB_LEN(STRB_LEN) + ) + )::set( null ,agent_path,UVMF_AGENT_CONFIG, this ); + + // This configuration also places itself in the config db using the same identifier used by the interface. This allows users to access + // configuration variables and the interface through the bfm api class rather than directly accessing the BFM. This is useful for + // accessingthe BFM when using Veloce + uvm_config_db #( apb_m_configuration #( + .APB_ADDR_WIDTH(APB_ADDR_WIDTH), + .APB_DATA_WIDTH(APB_DATA_WIDTH), + .STRB_LEN(STRB_LEN) + ) + )::set( null ,UVMF_CONFIGURATIONS, interface_name, this ); + + apb_m_configuration_cg.set_inst_name($sformatf("apb_m_configuration_cg_%s",get_full_name())); + +// This code is to aid in debugging parameter mismatches between the BFM and its corresponding agent. +// Enable this debug by setting UVM_VERBOSITY to UVM_DEBUG +// Setting UVM_VERBOSITY to UVM_DEBUG causes all BFM's and all agents to display their parameter settings. +// All of the messages from this feature have a UVM messaging id value of "CFG" +// The transcript or run.log can be parsed to ensure BFM parameter settings match its corresponding agents parameter settings. + `uvm_info("CFG", + $psprintf("The agent at '%s' is using interface named %s has the following parameters: APB_ADDR_WIDTH=%x APB_DATA_WIDTH=%x STRB_LEN=%x ", agent_path, interface_name, APB_ADDR_WIDTH ,APB_DATA_WIDTH ,STRB_LEN ), + UVM_DEBUG) + + // pragma uvmf custom initialize begin + // This controls whether or not the agent returns a transaction handle in the driver when calling + // item_done() back into the sequencer or not. If set to 1, a transaction is sent back which means + // the sequence on the other end must use the get_response() part of the driver/sequence API. If + // this doesn't occur, there will eventually be response_queue overflow errors during the test. + return_transaction_response = 1'b0; + + // pragma uvmf custom initialize end + + endfunction + + // **************************************************************************** + // TASK: wait_for_reset + // *[Required]* Blocks until reset is released. The wait_for_reset operation is performed + // by a task in the monitor bfm. + virtual task wait_for_reset(); + monitor_bfm.wait_for_reset(); + endtask + + // **************************************************************************** + // TASK: wait_for_num_clocks + // *[Required]* Blocks until specified number of clocks have elapsed. The wait_for_num_clocks + // operation is performed by a task in the monitor bfm. + virtual task wait_for_num_clocks(int clocks); + monitor_bfm.wait_for_num_clocks(clocks); + endtask + + // **************************************************************************** + // FUNCTION : convert2string() + // This function is used to convert variables in this class into a string for log messaging. + // + virtual function string convert2string (); + // pragma uvmf custom convert2string begin + return $sformatf(""); + // pragma uvmf custom convert2string end + endfunction + + // **************************************************************************** + // FUNCTION: get_sequencer + function uvm_sequencer #(apb_m_transaction#( + .APB_ADDR_WIDTH(APB_ADDR_WIDTH), + .APB_DATA_WIDTH(APB_DATA_WIDTH), + .STRB_LEN(STRB_LEN) + )) get_sequencer(); + return sequencer; + endfunction + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/apb_m_pkg/src/apb_m_driver.svh b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/apb_m_pkg/src/apb_m_driver.svh new file mode 100644 index 00000000..0c3b8285 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/apb_m_pkg/src/apb_m_driver.svh @@ -0,0 +1,115 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This class passes transactions between the sequencer +// and the BFM driver interface. It accesses the driver BFM +// through the bfm handle. This driver +// passes transactions to the driver BFM through the access +// task. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class apb_m_driver #( + int APB_ADDR_WIDTH = 32, + int APB_DATA_WIDTH = 32, + int STRB_LEN = APB_ADDR_WIDTH/8 + ) extends uvmf_driver_base #( + .CONFIG_T(apb_m_configuration #( + .APB_ADDR_WIDTH(APB_ADDR_WIDTH), + .APB_DATA_WIDTH(APB_DATA_WIDTH), + .STRB_LEN(STRB_LEN) + ) ), + .BFM_BIND_T(virtual apb_m_driver_bfm #( + .APB_ADDR_WIDTH(APB_ADDR_WIDTH), + .APB_DATA_WIDTH(APB_DATA_WIDTH), + .STRB_LEN(STRB_LEN) + ) ), + .REQ(apb_m_transaction #( + .APB_ADDR_WIDTH(APB_ADDR_WIDTH), + .APB_DATA_WIDTH(APB_DATA_WIDTH), + .STRB_LEN(STRB_LEN) + ) ), + .RSP(apb_m_transaction #( + .APB_ADDR_WIDTH(APB_ADDR_WIDTH), + .APB_DATA_WIDTH(APB_DATA_WIDTH), + .STRB_LEN(STRB_LEN) + ) )); + + `uvm_component_param_utils( apb_m_driver #( + APB_ADDR_WIDTH, + APB_DATA_WIDTH, + STRB_LEN + )) +//******************************************************************* +// Macros that define structs located in apb_m_macros.svh +//******************************************************************* +// Initiator macro used by apb_m_driver and apb_m_driver_bfm +// to communicate initiator driven data to apb_m_driver_bfm. +`apb_m_INITIATOR_STRUCT + apb_m_initiator_s apb_m_initiator_struct; +//******************************************************************* +// Responder macro used by apb_m_driver and apb_m_driver_bfm +// to communicate Responder driven data to apb_m_driver_bfm. +`apb_m_RESPONDER_STRUCT + apb_m_responder_s apb_m_responder_struct; + +// pragma uvmf custom class_item_additional begin +// pragma uvmf custom class_item_additional end + +// **************************************************************************** +// This function is the standard SystemVerilog constructor. +// + function new( string name = "", uvm_component parent=null ); + super.new( name, parent ); + endfunction + +// **************************************************************************** +// This function sends configuration object variables to the driver BFM +// using the configuration struct. +// + virtual function void configure(input CONFIG_T cfg); + bfm.configure( cfg.to_struct() ); + endfunction + +// **************************************************************************** +// This function places a handle to this class in the proxy variable in the +// driver BFM. This allows the driver BFM to call tasks and function within this class. +// + virtual function void set_bfm_proxy_handle(); + bfm.proxy = this; endfunction + +// **************************************************************************** +// This task is called by the run_phase in uvmf_driver_base. + virtual task access( inout REQ txn ); +// pragma uvmf custom access begin + if (configuration.initiator_responder==RESPONDER) begin + // Complete current transfer and wait for next transfer + bfm.respond_and_wait_for_next_transfer( + apb_m_initiator_struct, + txn.to_responder_struct() + ); + // Unpack information about initiated transfer received by this responder + txn.from_initiator_struct(apb_m_initiator_struct); + end else begin + // Initiate a transfer and get response + bfm.initiate_and_get_response( + txn.to_initiator_struct(), + apb_m_responder_struct + ); + // Unpack transfer response information received by this initiator + txn.from_responder_struct(apb_m_responder_struct); + end +// pragma uvmf custom access end + endtask + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/apb_m_pkg/src/apb_m_driver_bfm.sv b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/apb_m_pkg/src/apb_m_driver_bfm.sv new file mode 100644 index 00000000..d4e614a4 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/apb_m_pkg/src/apb_m_driver_bfm.sv @@ -0,0 +1,378 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: +// This interface performs the apb_m signal driving. It is +// accessed by the uvm apb_m driver through a virtual interface +// handle in the apb_m configuration. It drives the singals passed +// in through the port connection named bus of type apb_m_if. +// +// Input signals from the apb_m_if are assigned to an internal input +// signal with a _i suffix. The _i signal should be used for sampling. +// +// The input signal connections are as follows: +// bus.signal -> signal_i +// +// This bfm drives signals with a _o suffix. These signals +// are driven onto signals within apb_m_if based on INITIATOR/RESPONDER and/or +// ARBITRATION/GRANT status. +// +// The output signal connections are as follows: +// signal_o -> bus.signal +// +// +// Interface functions and tasks used by UVM components: +// +// configure: +// This function gets configuration attributes from the +// UVM driver to set any required BFM configuration +// variables such as 'initiator_responder'. +// +// initiate_and_get_response: +// This task is used to perform signaling activity for initiating +// a protocol transfer. The task initiates the transfer, using +// input data from the initiator struct. Then the task captures +// response data, placing the data into the response struct. +// The response struct is returned to the driver class. +// +// respond_and_wait_for_next_transfer: +// This task is used to complete a current transfer as a responder +// and then wait for the initiator to start the next transfer. +// The task uses data in the responder struct to drive protocol +// signals to complete the transfer. The task then waits for +// the next transfer. Once the next transfer begins, data from +// the initiator is placed into the initiator struct and sent +// to the responder sequence for processing to determine +// what data to respond with. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +import uvmf_base_pkg_hdl::*; +import apb_m_pkg_hdl::*; +`include "src/apb_m_macros.svh" + +interface apb_m_driver_bfm #( + int APB_ADDR_WIDTH = 32, + int APB_DATA_WIDTH = 32, + int STRB_LEN = APB_ADDR_WIDTH/8 + ) + (apb_m_if bus); + // The following pragma and additional ones in-lined further below are for running this BFM on Veloce + // pragma attribute apb_m_driver_bfm partition_interface_xif + +`ifndef XRTL +// This code is to aid in debugging parameter mismatches between the BFM and its corresponding agent. +// Enable this debug by setting UVM_VERBOSITY to UVM_DEBUG +// Setting UVM_VERBOSITY to UVM_DEBUG causes all BFM's and all agents to display their parameter settings. +// All of the messages from this feature have a UVM messaging id value of "CFG" +// The transcript or run.log can be parsed to ensure BFM parameter settings match its corresponding agents parameter settings. +import uvm_pkg::*; +`include "uvm_macros.svh" +initial begin : bfm_vs_agent_parameter_debug + `uvm_info("CFG", + $psprintf("The BFM at '%m' has the following parameters: APB_ADDR_WIDTH=%x APB_DATA_WIDTH=%x STRB_LEN=%x ", APB_ADDR_WIDTH,APB_DATA_WIDTH,STRB_LEN), + UVM_DEBUG) +end +`endif + + // Config value to determine if this is an initiator or a responder + uvmf_initiator_responder_t initiator_responder; + // Custom configuration variables. + // These are set using the configure function which is called during the UVM connect_phase + + logic pclk_i; + logic presetn_i; + + // Signal list (all signals are capable of being inputs and outputs for the sake + // of supporting both INITIATOR and RESPONDER mode operation. Expectation is that + // directionality in the config file was from the point-of-view of the INITIATOR + + // INITIATOR mode input signals + tri [APB_DATA_WIDTH-1:0] prdata_i; + reg [APB_DATA_WIDTH-1:0] prdata_o = 'b0; + tri pready_i; + reg pready_o = 0; + tri pslverr_i; + reg pslverr_o = 0; + + // INITIATOR mode output signals + tri [15:0] psel_i; + reg [15:0] psel_o = 'b0; + tri penable_i; + reg penable_o = 'b0; + tri [APB_ADDR_WIDTH-1:0] paddr_i; + reg [APB_ADDR_WIDTH-1:0] paddr_o = 'b0; + tri [APB_DATA_WIDTH-1:0] pwdata_i; + reg [APB_DATA_WIDTH-1:0] pwdata_o = 'b0; + tri pwrite_i; + reg pwrite_o = 'b0; + tri [STRB_LEN-1:0] pstrb_i; + reg [STRB_LEN-1:0] pstrb_o = 'b0; + tri [2:0] pprot_i; + reg [2:0] pprot_o = 'b0; + + // Bi-directional signals + + + assign pclk_i = bus.pclk; + assign presetn_i = bus.presetn; + + // These are signals marked as 'input' by the config file, but the signals will be + // driven by this BFM if put into RESPONDER mode (flipping all signal directions around) + assign prdata_i = bus.prdata; + assign bus.prdata = (initiator_responder == RESPONDER) ? prdata_o : 'bz; + assign pready_i = bus.pready; + assign bus.pready = (initiator_responder == RESPONDER) ? pready_o : 'bz; + assign pslverr_i = bus.pslverr; + assign bus.pslverr = (initiator_responder == RESPONDER) ? pslverr_o : 'bz; + + + // These are signals marked as 'output' by the config file, but the outputs will + // not be driven by this BFM unless placed in INITIATOR mode. + assign bus.psel = (initiator_responder == INITIATOR) ? psel_o : 'bz; + assign psel_i = bus.psel; + assign bus.penable = (initiator_responder == INITIATOR) ? penable_o : 'bz; + assign penable_i = bus.penable; + assign bus.paddr = (initiator_responder == INITIATOR) ? paddr_o : 'bz; + assign paddr_i = bus.paddr; + assign bus.pwdata = (initiator_responder == INITIATOR) ? pwdata_o : 'bz; + assign pwdata_i = bus.pwdata; + assign bus.pwrite = (initiator_responder == INITIATOR) ? pwrite_o : 'bz; + assign pwrite_i = bus.pwrite; + assign bus.pstrb = (initiator_responder == INITIATOR) ? pstrb_o : 'bz; + assign pstrb_i = bus.pstrb; + assign bus.pprot = (initiator_responder == INITIATOR) ? pprot_o : 'bz; + assign pprot_i = bus.pprot; + + // Proxy handle to UVM driver + apb_m_pkg::apb_m_driver #( + .APB_ADDR_WIDTH(APB_ADDR_WIDTH), + .APB_DATA_WIDTH(APB_DATA_WIDTH), + .STRB_LEN(STRB_LEN) + ) proxy; + // pragma tbx oneway proxy.my_function_name_in_uvm_driver + + // **************************************************************************** + // **************************************************************************** + // Macros that define structs located in apb_m_macros.svh + // **************************************************************************** + // Struct for passing configuration data from apb_m_driver to this BFM + // **************************************************************************** + `apb_m_CONFIGURATION_STRUCT + // **************************************************************************** + // Structs for INITIATOR and RESPONDER data flow + //******************************************************************* + // Initiator macro used by apb_m_driver and apb_m_driver_bfm + // to communicate initiator driven data to apb_m_driver_bfm. + `apb_m_INITIATOR_STRUCT + apb_m_initiator_s initiator_struct; + // Responder macro used by apb_m_driver and apb_m_driver_bfm + // to communicate Responder driven data to apb_m_driver_bfm. + `apb_m_RESPONDER_STRUCT + apb_m_responder_s responder_struct; + + // **************************************************************************** +// pragma uvmf custom reset_condition_and_response begin + // Always block used to return signals to reset value upon assertion of reset + always @( negedge presetn_i ) + begin + // RESPONDER mode output signals + prdata_o <= 'b0; + pready_o <= 0; + pslverr_o <= 0; + // INITIATOR mode output signals + psel_o <= 'b0; + penable_o <= 'b0; + paddr_o <= 'b0; + pwdata_o <= 'b0; + pwrite_o <= 'b0; + pstrb_o <= 'b0; + pprot_o <= 'b0; + // Bi-directional signals + + end +// pragma uvmf custom reset_condition_and_response end + + // pragma uvmf custom interface_item_additional begin + // pragma uvmf custom interface_item_additional end + + //****************************************************************** + // The configure() function is used to pass agent configuration + // variables to the driver BFM. It is called by the driver within + // the agent at the beginning of the simulation. It may be called + // during the simulation if agent configuration variables are updated + // and the driver BFM needs to be aware of the new configuration + // variables. + // + + function void configure(apb_m_configuration_s apb_m_configuration_arg); // pragma tbx xtf + initiator_responder = apb_m_configuration_arg.initiator_responder; + // pragma uvmf custom configure begin + // pragma uvmf custom configure end + endfunction + +// pragma uvmf custom initiate_and_get_response begin +// **************************************************************************** +// UVMF_CHANGE_ME +// This task is used by an initator. The task first initiates a transfer then +// waits for the responder to complete the transfer. + task initiate_and_get_response( + // This argument passes transaction variables used by an initiator + // to perform the initial part of a protocol transfer. The values + // come from a sequence item created in a sequence. + input apb_m_initiator_s apb_m_initiator_struct, + // This argument is used to send data received from the responder + // back to the sequence item. The sequence item is returned to the sequence. + output apb_m_responder_s apb_m_responder_struct + );// pragma tbx xtf + // + // Members within the apb_m_initiator_struct: + // bit psel ; + // bit penable ; + // bit [APB_ADDR_WIDTH-1:0] paddr ; + // bit [APB_DATA_WIDTH-1:0] pwdata ; + // bit pwrite ; + // bit [STRB_LEN:0] pstrb ; + // bit [3:0] pprot ; + // bit [APB_DATA_WIDTH-1:0] prdata ; + // bit pready ; + // bit pslverr ; + // Members within the apb_m_responder_struct: + // bit psel ; + // bit penable ; + // bit [APB_ADDR_WIDTH-1:0] paddr ; + // bit [APB_DATA_WIDTH-1:0] pwdata ; + // bit pwrite ; + // bit [STRB_LEN:0] pstrb ; + // bit [3:0] pprot ; + // bit [APB_DATA_WIDTH-1:0] prdata ; + // bit pready ; + // bit pslverr ; + initiator_struct = apb_m_initiator_struct; + // + // Reference code; + // How to wait for signal value + // while (control_signal == 1'b1) @(posedge pclk_i); + // + // How to assign a responder struct member, named xyz, from a signal. + // All available initiator input and inout signals listed. + // Initiator input signals + // apb_m_responder_struct.xyz = prdata_i; // [APB_DATA_WIDTH-1:0] + // apb_m_responder_struct.xyz = pready_i; // + // apb_m_responder_struct.xyz = pslverr_i; // + // Initiator inout signals + // How to assign a signal from an initiator struct member named xyz. + // All available initiator output and inout signals listed. + // Notice the _o. Those are storage variables that allow for procedural assignment. + // Initiator output signals + // psel_o <= apb_m_initiator_struct.xyz; // [15:0] + // penable_o <= apb_m_initiator_struct.xyz; // + // paddr_o <= apb_m_initiator_struct.xyz; // [APB_ADDR_WIDTH-1:0] + // pwdata_o <= apb_m_initiator_struct.xyz; // [APB_DATA_WIDTH-1:0] + // pwrite_o <= apb_m_initiator_struct.xyz; // + // pstrb_o <= apb_m_initiator_struct.xyz; // [STRB_LEN-1:0] + // pprot_o <= apb_m_initiator_struct.xyz; // [2:0] + // Initiator inout signals + // Initiate a transfer using the data received. + @(posedge pclk_i); + @(posedge pclk_i); + // Wait for the responder to complete the transfer then place the responder data into + // apb_m_responder_struct. + @(posedge pclk_i); + @(posedge pclk_i); + responder_struct = apb_m_responder_struct; + endtask +// pragma uvmf custom initiate_and_get_response end + +// pragma uvmf custom respond_and_wait_for_next_transfer begin +// **************************************************************************** +// The first_transfer variable is used to prevent completing a transfer in the +// first call to this task. For the first call to this task, there is not +// current transfer to complete. +bit first_transfer=1; + +// UVMF_CHANGE_ME +// This task is used by a responder. The task first completes the current +// transfer in progress then waits for the initiator to start the next transfer. + task respond_and_wait_for_next_transfer( + // This argument is used to send data received from the initiator + // back to the sequence item. The sequence determines how to respond. + output apb_m_initiator_s apb_m_initiator_struct, + // This argument passes transaction variables used by a responder + // to complete a protocol transfer. The values come from a sequence item. + input apb_m_responder_s apb_m_responder_struct + );// pragma tbx xtf + // Variables within the apb_m_initiator_struct: + // bit psel ; + // bit penable ; + // bit [APB_ADDR_WIDTH-1:0] paddr ; + // bit [APB_DATA_WIDTH-1:0] pwdata ; + // bit pwrite ; + // bit [STRB_LEN:0] pstrb ; + // bit [3:0] pprot ; + // bit [APB_DATA_WIDTH-1:0] prdata ; + // bit pready ; + // bit pslverr ; + // Variables within the apb_m_responder_struct: + // bit psel ; + // bit penable ; + // bit [APB_ADDR_WIDTH-1:0] paddr ; + // bit [APB_DATA_WIDTH-1:0] pwdata ; + // bit pwrite ; + // bit [STRB_LEN:0] pstrb ; + // bit [3:0] pprot ; + // bit [APB_DATA_WIDTH-1:0] prdata ; + // bit pready ; + // bit pslverr ; + // Reference code; + // How to wait for signal value + // while (control_signal == 1'b1) @(posedge pclk_i); + // + // How to assign a responder struct member, named xyz, from a signal. + // All available responder input and inout signals listed. + // Responder input signals + // apb_m_responder_struct.xyz = psel_i; // [15:0] + // apb_m_responder_struct.xyz = penable_i; // + // apb_m_responder_struct.xyz = paddr_i; // [APB_ADDR_WIDTH-1:0] + // apb_m_responder_struct.xyz = pwdata_i; // [APB_DATA_WIDTH-1:0] + // apb_m_responder_struct.xyz = pwrite_i; // + // apb_m_responder_struct.xyz = pstrb_i; // [STRB_LEN-1:0] + // apb_m_responder_struct.xyz = pprot_i; // [2:0] + // Responder inout signals + // How to assign a signal, named xyz, from an initiator struct member. + // All available responder output and inout signals listed. + // Notice the _o. Those are storage variables that allow for procedural assignment. + // Responder output signals + // prdata_o <= apb_m_initiator_struct.xyz; // [APB_DATA_WIDTH-1:0] + // pready_o <= apb_m_initiator_struct.xyz; // + // pslverr_o <= apb_m_initiator_struct.xyz; // + // Responder inout signals + + @(posedge pclk_i); + if (!first_transfer) begin + // Perform transfer response here. + // Reply using data recieved in the apb_m_responder_struct. + @(posedge pclk_i); + // Reply using data recieved in the transaction handle. + @(posedge pclk_i); + end + // Wait for next transfer then gather info from intiator about the transfer. + // Place the data into the apb_m_initiator_struct. + @(posedge pclk_i); + @(posedge pclk_i); + first_transfer = 0; + endtask +// pragma uvmf custom respond_and_wait_for_next_transfer end + + +endinterface + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/apb_m_pkg/src/apb_m_if.sv b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/apb_m_pkg/src/apb_m_if.sv new file mode 100644 index 00000000..6747ba27 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/apb_m_pkg/src/apb_m_if.sv @@ -0,0 +1,113 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This interface contains the apb_m interface signals. +// It is instantiated once per apb_m bus. Bus Functional Models, +// BFM's named apb_m_driver_bfm, are used to drive signals on the bus. +// BFM's named apb_m_monitor_bfm are used to monitor signals on the +// bus. This interface signal bundle is passed in the port list of +// the BFM in order to give the BFM access to the signals in this +// interface. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// This template can be used to connect a DUT to these signals +// +// .dut_signal_port(apb_m_bus.psel), // Agent output +// .dut_signal_port(apb_m_bus.penable), // Agent output +// .dut_signal_port(apb_m_bus.paddr), // Agent output +// .dut_signal_port(apb_m_bus.pwdata), // Agent output +// .dut_signal_port(apb_m_bus.pwrite), // Agent output +// .dut_signal_port(apb_m_bus.pstrb), // Agent output +// .dut_signal_port(apb_m_bus.pprot), // Agent output +// .dut_signal_port(apb_m_bus.prdata), // Agent input +// .dut_signal_port(apb_m_bus.pready), // Agent input +// .dut_signal_port(apb_m_bus.pslverr), // Agent input + +import uvmf_base_pkg_hdl::*; +import apb_m_pkg_hdl::*; + +interface apb_m_if #( + int APB_ADDR_WIDTH = 32, + int APB_DATA_WIDTH = 32, + int STRB_LEN = APB_ADDR_WIDTH/8 + ) + + ( + input logic pclk, + input logic presetn, + output logic [15:0] psel, + output logic penable, + output logic [APB_ADDR_WIDTH-1:0] paddr, + output logic [APB_DATA_WIDTH-1:0] pwdata, + output logic pwrite, + output logic [STRB_LEN-1:0] pstrb, + output logic [2:0] pprot, + input logic [APB_DATA_WIDTH-1:0] prdata, + input logic pready, + input logic pslverr + ); + +modport monitor_port + ( + input pclk, + input presetn, + input psel, + input penable, + input paddr, + input pwdata, + input pwrite, + input pstrb, + input pprot, + input prdata, + input pready, + input pslverr + ); + +modport initiator_port + ( + input pclk, + input presetn, + output psel, + output penable, + output paddr, + output pwdata, + output pwrite, + output pstrb, + output pprot, + input prdata, + input pready, + input pslverr + ); + +modport responder_port + ( + input pclk, + input presetn, + input psel, + input penable, + input paddr, + input pwdata, + input pwrite, + input pstrb, + input pprot, + output prdata, + output pready, + output pslverr + ); + + +// pragma uvmf custom interface_item_additional begin +// pragma uvmf custom interface_item_additional end + +endinterface + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/apb_m_pkg/src/apb_m_infact_coverage_strategy.csv b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/apb_m_pkg/src/apb_m_infact_coverage_strategy.csv new file mode 100644 index 00000000..1c218e14 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/apb_m_pkg/src/apb_m_infact_coverage_strategy.csv @@ -0,0 +1,6 @@ +Global +auto_bin_max, 64 + +Name,Type,Include +rand_fields,coverpoint,=rand *.** + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/apb_m_pkg/src/apb_m_macros.svh b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/apb_m_pkg/src/apb_m_macros.svh new file mode 100644 index 00000000..631c4b12 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/apb_m_pkg/src/apb_m_macros.svh @@ -0,0 +1,202 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This file contains macros used with the apb_m package. +// These macros include packed struct definitions. These structs are +// used to pass data between classes, hvl, and BFM's, hdl. Use of +// structs are more efficient and simpler to modify. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// + +// **************************************************************************** +// When changing the contents of this struct, be sure to update the to_struct +// and from_struct methods defined in the macros below that are used in +// the apb_m_configuration class. +// + `define apb_m_CONFIGURATION_STRUCT \ +typedef struct packed { \ + uvmf_active_passive_t active_passive; \ + uvmf_initiator_responder_t initiator_responder; \ + } apb_m_configuration_s; + + `define apb_m_CONFIGURATION_TO_STRUCT_FUNCTION \ + virtual function apb_m_configuration_s to_struct();\ + apb_m_configuration_struct = \ + {\ + this.active_passive,\ + this.initiator_responder\ + };\ + return ( apb_m_configuration_struct );\ + endfunction + + `define apb_m_CONFIGURATION_FROM_STRUCT_FUNCTION \ + virtual function void from_struct(apb_m_configuration_s apb_m_configuration_struct);\ + {\ + this.active_passive,\ + this.initiator_responder \ + } = apb_m_configuration_struct;\ + endfunction + +// **************************************************************************** +// When changing the contents of this struct, be sure to update the to_monitor_struct +// and from_monitor_struct methods of the apb_m_transaction class. +// + `define apb_m_MONITOR_STRUCT typedef struct packed { \ + bit psel ; \ + bit penable ; \ + bit [APB_ADDR_WIDTH-1:0] paddr ; \ + bit [APB_DATA_WIDTH-1:0] pwdata ; \ + bit pwrite ; \ + bit [STRB_LEN:0] pstrb ; \ + bit [3:0] pprot ; \ + bit [APB_DATA_WIDTH-1:0] prdata ; \ + bit pready ; \ + bit pslverr ; \ + } apb_m_monitor_s; + + `define apb_m_TO_MONITOR_STRUCT_FUNCTION \ + virtual function apb_m_monitor_s to_monitor_struct();\ + apb_m_monitor_struct = \ + { \ + this.psel , \ + this.penable , \ + this.paddr , \ + this.pwdata , \ + this.pwrite , \ + this.pstrb , \ + this.pprot , \ + this.prdata , \ + this.pready , \ + this.pslverr \ + };\ + return ( apb_m_monitor_struct);\ + endfunction\ + + `define apb_m_FROM_MONITOR_STRUCT_FUNCTION \ + virtual function void from_monitor_struct(apb_m_monitor_s apb_m_monitor_struct);\ + {\ + this.psel , \ + this.penable , \ + this.paddr , \ + this.pwdata , \ + this.pwrite , \ + this.pstrb , \ + this.pprot , \ + this.prdata , \ + this.pready , \ + this.pslverr \ + } = apb_m_monitor_struct;\ + endfunction + +// **************************************************************************** +// When changing the contents of this struct, be sure to update the to_initiator_struct +// and from_initiator_struct methods of the apb_m_transaction class. +// Also update the comments in the driver BFM. +// + `define apb_m_INITIATOR_STRUCT typedef struct packed { \ + bit psel ; \ + bit penable ; \ + bit [APB_ADDR_WIDTH-1:0] paddr ; \ + bit [APB_DATA_WIDTH-1:0] pwdata ; \ + bit pwrite ; \ + bit [STRB_LEN:0] pstrb ; \ + bit [3:0] pprot ; \ + bit [APB_DATA_WIDTH-1:0] prdata ; \ + bit pready ; \ + bit pslverr ; \ + } apb_m_initiator_s; + + `define apb_m_TO_INITIATOR_STRUCT_FUNCTION \ + virtual function apb_m_initiator_s to_initiator_struct();\ + apb_m_initiator_struct = \ + {\ + this.psel , \ + this.penable , \ + this.paddr , \ + this.pwdata , \ + this.pwrite , \ + this.pstrb , \ + this.pprot , \ + this.prdata , \ + this.pready , \ + this.pslverr \ + };\ + return ( apb_m_initiator_struct);\ + endfunction + + `define apb_m_FROM_INITIATOR_STRUCT_FUNCTION \ + virtual function void from_initiator_struct(apb_m_initiator_s apb_m_initiator_struct);\ + {\ + this.psel , \ + this.penable , \ + this.paddr , \ + this.pwdata , \ + this.pwrite , \ + this.pstrb , \ + this.pprot , \ + this.prdata , \ + this.pready , \ + this.pslverr \ + } = apb_m_initiator_struct;\ + endfunction + +// **************************************************************************** +// When changing the contents of this struct, be sure to update the to_responder_struct +// and from_responder_struct methods of the apb_m_transaction class. +// Also update the comments in the driver BFM. +// + `define apb_m_RESPONDER_STRUCT typedef struct packed { \ + bit psel ; \ + bit penable ; \ + bit [APB_ADDR_WIDTH-1:0] paddr ; \ + bit [APB_DATA_WIDTH-1:0] pwdata ; \ + bit pwrite ; \ + bit [STRB_LEN:0] pstrb ; \ + bit [3:0] pprot ; \ + bit [APB_DATA_WIDTH-1:0] prdata ; \ + bit pready ; \ + bit pslverr ; \ + } apb_m_responder_s; + + `define apb_m_TO_RESPONDER_STRUCT_FUNCTION \ + virtual function apb_m_responder_s to_responder_struct();\ + apb_m_responder_struct = \ + {\ + this.psel , \ + this.penable , \ + this.paddr , \ + this.pwdata , \ + this.pwrite , \ + this.pstrb , \ + this.pprot , \ + this.prdata , \ + this.pready , \ + this.pslverr \ + };\ + return ( apb_m_responder_struct);\ + endfunction + + `define apb_m_FROM_RESPONDER_STRUCT_FUNCTION \ + virtual function void from_responder_struct(apb_m_responder_s apb_m_responder_struct);\ + {\ + this.psel , \ + this.penable , \ + this.paddr , \ + this.pwdata , \ + this.pwrite , \ + this.pstrb , \ + this.pprot , \ + this.prdata , \ + this.pready , \ + this.pslverr \ + } = apb_m_responder_struct;\ + endfunction +// pragma uvmf custom additional begin +// pragma uvmf custom additional end diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/apb_m_pkg/src/apb_m_monitor.svh b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/apb_m_pkg/src/apb_m_monitor.svh new file mode 100644 index 00000000..7f0c5966 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/apb_m_pkg/src/apb_m_monitor.svh @@ -0,0 +1,107 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This class receives apb_m transactions observed by the +// apb_m monitor BFM and broadcasts them through the analysis port +// on the agent. It accesses the monitor BFM through the monitor +// task. This UVM component captures transactions +// for viewing in the waveform viewer if the +// enable_transaction_viewing flag is set in the configuration. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class apb_m_monitor #( + int APB_ADDR_WIDTH = 32, + int APB_DATA_WIDTH = 32, + int STRB_LEN = APB_ADDR_WIDTH/8 + ) extends uvmf_monitor_base #( + .CONFIG_T(apb_m_configuration #( + .APB_ADDR_WIDTH(APB_ADDR_WIDTH), + .APB_DATA_WIDTH(APB_DATA_WIDTH), + .STRB_LEN(STRB_LEN) + )), + .BFM_BIND_T(virtual apb_m_monitor_bfm #( + .APB_ADDR_WIDTH(APB_ADDR_WIDTH), + .APB_DATA_WIDTH(APB_DATA_WIDTH), + .STRB_LEN(STRB_LEN) + )), + .TRANS_T(apb_m_transaction #( + .APB_ADDR_WIDTH(APB_ADDR_WIDTH), + .APB_DATA_WIDTH(APB_DATA_WIDTH), + .STRB_LEN(STRB_LEN) + ))); + + `uvm_component_param_utils( apb_m_monitor #( + APB_ADDR_WIDTH, + APB_DATA_WIDTH, + STRB_LEN + )) + +// Structure used to pass data from monitor BFM to monitor class in agent. +// Use to_monitor_struct function to pack transaction variables into structure. +// Use from_monitor_struct function to unpack transaction variables from structure. +`apb_m_MONITOR_STRUCT + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + +// **************************************************************************** +// This function is the standard SystemVerilog constructor. +// + function new( string name = "", uvm_component parent = null ); + super.new( name, parent ); + endfunction + +// **************************************************************************** +// This function sends configuration object variables to the monitor BFM +// using the configuration struct. +// + virtual function void configure(input CONFIG_T cfg); + bfm.configure( cfg.to_struct() ); + + endfunction + +// **************************************************************************** +// This function places a handle to this class in the proxy variable in the +// monitor BFM. This allows the monitor BFM to call the notify_transaction +// function within this class. +// + virtual function void set_bfm_proxy_handle(); + bfm.proxy = this; endfunction + +// *************************************************************************** + virtual task run_phase(uvm_phase phase); + // Start monitor BFM thread and don't call super.run() in order to + // override the default monitor proxy 'pull' behavior with the more + // emulation-friendly BFM 'push' approach using the notify_transaction + // function below + bfm.start_monitoring(); + endtask + +// ************************************************************************** + +// This function is called by the monitor BFM. It receives data observed by the +// monitor BFM. Data is passed using the apb_m_monitor_struct. + virtual function void notify_transaction(input apb_m_monitor_s apb_m_monitor_struct); + + + trans = new("trans"); + trans.from_monitor_struct(apb_m_monitor_struct); + trans.start_time = time_stamp; + trans.end_time = $time; + time_stamp = trans.end_time; + + analyze(trans); + endfunction + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/apb_m_pkg/src/apb_m_monitor_bfm.sv b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/apb_m_pkg/src/apb_m_monitor_bfm.sv new file mode 100644 index 00000000..c1f68c5a --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/apb_m_pkg/src/apb_m_monitor_bfm.sv @@ -0,0 +1,218 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This interface performs the apb_m signal monitoring. +// It is accessed by the uvm apb_m monitor through a virtual +// interface handle in the apb_m configuration. It monitors the +// signals passed in through the port connection named bus of +// type apb_m_if. +// +// Input signals from the apb_m_if are assigned to an internal input +// signal with a _i suffix. The _i signal should be used for sampling. +// +// The input signal connections are as follows: +// bus.signal -> signal_i +// +// Interface functions and tasks used by UVM components: +// monitor(inout TRANS_T txn); +// This task receives the transaction, txn, from the +// UVM monitor and then populates variables in txn +// from values observed on bus activity. This task +// blocks until an operation on the apb_m bus is complete. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +import uvmf_base_pkg_hdl::*; +import apb_m_pkg_hdl::*; +`include "src/apb_m_macros.svh" + + +interface apb_m_monitor_bfm #( + int APB_ADDR_WIDTH = 32, + int APB_DATA_WIDTH = 32, + int STRB_LEN = APB_ADDR_WIDTH/8 + ) + ( apb_m_if bus ); + // The pragma below and additional ones in-lined further down are for running this BFM on Veloce + // pragma attribute apb_m_monitor_bfm partition_interface_xif + +`ifndef XRTL +// This code is to aid in debugging parameter mismatches between the BFM and its corresponding agent. +// Enable this debug by setting UVM_VERBOSITY to UVM_DEBUG +// Setting UVM_VERBOSITY to UVM_DEBUG causes all BFM's and all agents to display their parameter settings. +// All of the messages from this feature have a UVM messaging id value of "CFG" +// The transcript or run.log can be parsed to ensure BFM parameter settings match its corresponding agents parameter settings. +import uvm_pkg::*; +`include "uvm_macros.svh" +initial begin : bfm_vs_agent_parameter_debug + `uvm_info("CFG", + $psprintf("The BFM at '%m' has the following parameters: APB_ADDR_WIDTH=%x APB_DATA_WIDTH=%x STRB_LEN=%x ", APB_ADDR_WIDTH,APB_DATA_WIDTH,STRB_LEN), + UVM_DEBUG) +end +`endif + + + // Structure used to pass transaction data from monitor BFM to monitor class in agent. +`apb_m_MONITOR_STRUCT + apb_m_monitor_s apb_m_monitor_struct; + + // Structure used to pass configuration data from monitor class to monitor BFM. + `apb_m_CONFIGURATION_STRUCT + + + // Config value to determine if this is an initiator or a responder + uvmf_initiator_responder_t initiator_responder; + // Custom configuration variables. + // These are set using the configure function which is called during the UVM connect_phase + + logic pclk_i; + logic presetn_i; + tri [15:0] psel_i; + tri penable_i; + tri [APB_ADDR_WIDTH-1:0] paddr_i; + tri [APB_DATA_WIDTH-1:0] pwdata_i; + tri pwrite_i; + tri [STRB_LEN-1:0] pstrb_i; + tri [2:0] pprot_i; + tri [APB_DATA_WIDTH-1:0] prdata_i; + tri pready_i; + tri pslverr_i; + assign pclk_i = bus.pclk; + assign presetn_i = bus.presetn; + assign psel_i = bus.psel; + assign penable_i = bus.penable; + assign paddr_i = bus.paddr; + assign pwdata_i = bus.pwdata; + assign pwrite_i = bus.pwrite; + assign pstrb_i = bus.pstrb; + assign pprot_i = bus.pprot; + assign prdata_i = bus.prdata; + assign pready_i = bus.pready; + assign pslverr_i = bus.pslverr; + + // Proxy handle to UVM monitor + apb_m_pkg::apb_m_monitor #( + .APB_ADDR_WIDTH(APB_ADDR_WIDTH), + .APB_DATA_WIDTH(APB_DATA_WIDTH), + .STRB_LEN(STRB_LEN) + ) proxy; + // pragma tbx oneway proxy.notify_transaction + + // pragma uvmf custom interface_item_additional begin + // pragma uvmf custom interface_item_additional end + + //****************************************************************** + task wait_for_reset();// pragma tbx xtf + @(posedge pclk_i) ; + do_wait_for_reset(); + endtask + + // **************************************************************************** + task do_wait_for_reset(); + // pragma uvmf custom reset_condition begin + wait ( presetn_i === 1 ) ; + @(posedge pclk_i) ; + // pragma uvmf custom reset_condition end + endtask + + //****************************************************************** + + task wait_for_num_clocks(input int unsigned count); // pragma tbx xtf + @(posedge pclk_i); + + repeat (count-1) @(posedge pclk_i); + endtask + + //****************************************************************** + event go; + function void start_monitoring();// pragma tbx xtf + -> go; + endfunction + + // **************************************************************************** + initial begin + @go; + forever begin + @(posedge pclk_i); + do_monitor( apb_m_monitor_struct ); + + + proxy.notify_transaction( apb_m_monitor_struct ); + + end + end + + //****************************************************************** + // The configure() function is used to pass agent configuration + // variables to the monitor BFM. It is called by the monitor within + // the agent at the beginning of the simulation. It may be called + // during the simulation if agent configuration variables are updated + // and the monitor BFM needs to be aware of the new configuration + // variables. + // + function void configure(apb_m_configuration_s apb_m_configuration_arg); // pragma tbx xtf + initiator_responder = apb_m_configuration_arg.initiator_responder; + // pragma uvmf custom configure begin + // pragma uvmf custom configure end + endfunction + + + // **************************************************************************** + + task do_monitor(output apb_m_monitor_s apb_m_monitor_struct); + // + // Available struct members: + // // apb_m_monitor_struct.psel + // // apb_m_monitor_struct.penable + // // apb_m_monitor_struct.paddr + // // apb_m_monitor_struct.pwdata + // // apb_m_monitor_struct.pwrite + // // apb_m_monitor_struct.pstrb + // // apb_m_monitor_struct.pprot + // // apb_m_monitor_struct.prdata + // // apb_m_monitor_struct.pready + // // apb_m_monitor_struct.pslverr + // // + // Reference code; + // How to wait for signal value + // while (control_signal === 1'b1) @(posedge pclk_i); + // + // How to assign a struct member, named xyz, from a signal. + // All available input signals listed. + // apb_m_monitor_struct.xyz = psel_i; // [15:0] + // apb_m_monitor_struct.xyz = penable_i; // + // apb_m_monitor_struct.xyz = paddr_i; // [APB_ADDR_WIDTH-1:0] + // apb_m_monitor_struct.xyz = pwdata_i; // [APB_DATA_WIDTH-1:0] + // apb_m_monitor_struct.xyz = pwrite_i; // + // apb_m_monitor_struct.xyz = pstrb_i; // [STRB_LEN-1:0] + // apb_m_monitor_struct.xyz = pprot_i; // [2:0] + // apb_m_monitor_struct.xyz = prdata_i; // [APB_DATA_WIDTH-1:0] + // apb_m_monitor_struct.xyz = pready_i; // + // apb_m_monitor_struct.xyz = pslverr_i; // + // pragma uvmf custom do_monitor begin + // UVMF_CHANGE_ME : Implement protocol monitoring. The commented reference code + // below are examples of how to capture signal values and assign them to + // structure members. All available input signals are listed. The 'while' + // code example shows how to wait for a synchronous flow control signal. This + // task should return when a complete transfer has been observed. Once this task is + // exited with captured values, it is then called again to wait for and observe + // the next transfer. One clock cycle is consumed between calls to do_monitor. + @(posedge pclk_i); + @(posedge pclk_i); + @(posedge pclk_i); + @(posedge pclk_i); + // pragma uvmf custom do_monitor end + endtask + + +endinterface + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/apb_m_pkg/src/apb_m_random_sequence.svh b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/apb_m_pkg/src/apb_m_random_sequence.svh new file mode 100644 index 00000000..6ad36e08 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/apb_m_pkg/src/apb_m_random_sequence.svh @@ -0,0 +1,69 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: +// This sequences randomizes the apb_m transaction and sends it +// to the UVM driver. +// +// This sequence constructs and randomizes a apb_m_transaction. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class apb_m_random_sequence #( + int APB_ADDR_WIDTH = 32, + int APB_DATA_WIDTH = 32, + int STRB_LEN = APB_ADDR_WIDTH/8 + ) + extends apb_m_sequence_base #( + .APB_ADDR_WIDTH(APB_ADDR_WIDTH), + .APB_DATA_WIDTH(APB_DATA_WIDTH), + .STRB_LEN(STRB_LEN) + ); + + `uvm_object_param_utils( apb_m_random_sequence #( + APB_ADDR_WIDTH, + APB_DATA_WIDTH, + STRB_LEN + )) + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + //***************************************************************** + function new(string name = ""); + super.new(name); + endfunction: new + + // **************************************************************************** + // TASK : body() + // This task is automatically executed when this sequence is started using the + // start(sequencerHandle) task. + // + task body(); + + // Construct the transaction + req=apb_m_transaction#( + .APB_ADDR_WIDTH(APB_ADDR_WIDTH), + .APB_DATA_WIDTH(APB_DATA_WIDTH), + .STRB_LEN(STRB_LEN) + )::type_id::create("req"); + start_item(req); + // Randomize the transaction + if(!req.randomize()) `uvm_fatal("SEQ", "apb_m_random_sequence::body()-apb_m_transaction randomization failed") + // Send the transaction to the apb_m_driver_bfm via the sequencer and apb_m_driver. + finish_item(req); + `uvm_info("SEQ", {"Response:",req.convert2string()},UVM_MEDIUM) + + endtask + +endclass: apb_m_random_sequence + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/apb_m_pkg/src/apb_m_responder_sequence.svh b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/apb_m_pkg/src/apb_m_responder_sequence.svh new file mode 100644 index 00000000..b493b9c2 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/apb_m_pkg/src/apb_m_responder_sequence.svh @@ -0,0 +1,65 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This class can be used to provide stimulus when an interface +// has been configured to run in a responder mode. It +// will never finish by default, always going back to the driver +// and driver BFM for the next transaction with which to respond. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class apb_m_responder_sequence #( + int APB_ADDR_WIDTH = 32, + int APB_DATA_WIDTH = 32, + int STRB_LEN = APB_ADDR_WIDTH/8 + ) + extends apb_m_sequence_base #( + .APB_ADDR_WIDTH(APB_ADDR_WIDTH), + .APB_DATA_WIDTH(APB_DATA_WIDTH), + .STRB_LEN(STRB_LEN) + ); + + `uvm_object_param_utils( apb_m_responder_sequence #( + APB_ADDR_WIDTH, + APB_DATA_WIDTH, + STRB_LEN + )) + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + function new(string name = "apb_m_responder_sequence"); + super.new(name); + endfunction + + task body(); + req=apb_m_transaction#( + .APB_ADDR_WIDTH(APB_ADDR_WIDTH), + .APB_DATA_WIDTH(APB_DATA_WIDTH), + .STRB_LEN(STRB_LEN) + )::type_id::create("req"); + forever begin + start_item(req); + finish_item(req); + // pragma uvmf custom body begin + // UVMF_CHANGE_ME : Do something here with the resulting req item. The + // finish_item() call above will block until the req transaction is ready + // to be handled by the responder sequence. + // If this was an item that required a response, the expectation is + // that the response should be populated within this transaction now. + `uvm_info("SEQ",$sformatf("Processed txn: %s",req.convert2string()),UVM_HIGH) + // pragma uvmf custom body end + end + endtask + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/apb_m_pkg/src/apb_m_sequence_base.svh b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/apb_m_pkg/src/apb_m_sequence_base.svh new file mode 100644 index 00000000..df1d671e --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/apb_m_pkg/src/apb_m_sequence_base.svh @@ -0,0 +1,120 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: +// This file contains the class used as the base class for all sequences +// for this interface. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class apb_m_sequence_base #( + int APB_ADDR_WIDTH = 32, + int APB_DATA_WIDTH = 32, + int STRB_LEN = APB_ADDR_WIDTH/8 + ) extends uvmf_sequence_base #( + .REQ(apb_m_transaction #( + .APB_ADDR_WIDTH(APB_ADDR_WIDTH), + .APB_DATA_WIDTH(APB_DATA_WIDTH), + .STRB_LEN(STRB_LEN) + )), + .RSP(apb_m_transaction #( + .APB_ADDR_WIDTH(APB_ADDR_WIDTH), + .APB_DATA_WIDTH(APB_DATA_WIDTH), + .STRB_LEN(STRB_LEN) + ))); + + `uvm_object_param_utils( apb_m_sequence_base #( + APB_ADDR_WIDTH, + APB_DATA_WIDTH, + STRB_LEN + )) + + // variables + typedef apb_m_transaction #( + .APB_ADDR_WIDTH(APB_ADDR_WIDTH), + .APB_DATA_WIDTH(APB_DATA_WIDTH), + .STRB_LEN(STRB_LEN) + ) apb_m_transaction_req_t; + apb_m_transaction_req_t req; + typedef apb_m_transaction #( + .APB_ADDR_WIDTH(APB_ADDR_WIDTH), + .APB_DATA_WIDTH(APB_DATA_WIDTH), + .STRB_LEN(STRB_LEN) + ) apb_m_transaction_rsp_t; + apb_m_transaction_rsp_t rsp; + + // Event for identifying when a response was received from the sequencer + event new_rsp; + + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + // **************************************************************************** + // TASK : get_responses() + // This task recursively gets sequence item responses from the sequencer. + // + virtual task get_responses(); + fork + begin + // Block until new rsp available + get_response(rsp); + // New rsp received. Indicate to sequence using event. + ->new_rsp; + // Display the received response transaction + `uvm_info("SEQ", {"New response transaction:",rsp.convert2string()}, UVM_MEDIUM) + end + join_none + endtask + + // **************************************************************************** + // TASK : pre_body() + // This task is called automatically when start is called with call_pre_post set to 1 (default). + // By calling get_responses() within pre_body() any derived sequences are automatically + // processing response transactions. Only un-comment this call to get_responses() if you + // have configured the interface driver to utilize the response transaction path by setting + // the configuration variable "return_transaction_response" to 1. Otherwise it is possible + // to impact runtime performance and memory utilization. + // + virtual task pre_body(); + // pragma uvmf custom pre_body begin +// get_responses(); + // pragma uvmf custom pre_body end + endtask + + // **************************************************************************** + // TASK : body() + // This task is called automatically when start is called. This sequence sends + // a req sequence item to the sequencer identified as an argument in the call + // to start. + // + virtual task body(); + // pragma uvmf custom body begin + start_item(req); + finish_item(req); + // pragma uvmf custom body end + endtask + + // **************************************************************************** + // FUNCTION : new() + // This function is the standard SystemVerilog constructor. + // + function new( string name =""); + super.new( name ); + // pragma uvmf custom new begin + req = apb_m_transaction_req_t::type_id::create("req"); + rsp = apb_m_transaction_rsp_t::type_id::create("rsp"); + // pragma uvmf custom new end + endfunction + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/apb_m_pkg/src/apb_m_transaction.svh b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/apb_m_pkg/src/apb_m_transaction.svh new file mode 100644 index 00000000..f254cabe --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/apb_m_pkg/src/apb_m_transaction.svh @@ -0,0 +1,233 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This class defines the variables required for an apb_m +// transaction. Class variables to be displayed in waveform transaction +// viewing are added to the transaction viewing stream in the add_to_wave +// function. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class apb_m_transaction #( + int APB_ADDR_WIDTH = 32, + int APB_DATA_WIDTH = 32, + int STRB_LEN = APB_ADDR_WIDTH/8 + ) extends uvmf_transaction_base; + + `uvm_object_param_utils( apb_m_transaction #( + APB_ADDR_WIDTH, + APB_DATA_WIDTH, + STRB_LEN + )) + + rand bit psel ; + rand bit penable ; + rand bit [APB_ADDR_WIDTH-1:0] paddr ; + rand bit [APB_DATA_WIDTH-1:0] pwdata ; + rand bit pwrite ; + rand bit [STRB_LEN:0] pstrb ; + rand bit [3:0] pprot ; + bit [APB_DATA_WIDTH-1:0] prdata ; + bit pready ; + bit pslverr ; + + //Constraints for the transaction variables: + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + //******************************************************************* + //******************************************************************* + // Macros that define structs and associated functions are + // located in apb_m_macros.svh + + //******************************************************************* + // Monitor macro used by apb_m_monitor and apb_m_monitor_bfm + // This struct is defined in apb_m_macros.svh + `apb_m_MONITOR_STRUCT + apb_m_monitor_s apb_m_monitor_struct; + //******************************************************************* + // FUNCTION: to_monitor_struct() + // This function packs transaction variables into a apb_m_monitor_s + // structure. The function returns the handle to the apb_m_monitor_struct. + // This function is defined in apb_m_macros.svh + `apb_m_TO_MONITOR_STRUCT_FUNCTION + //******************************************************************* + // FUNCTION: from_monitor_struct() + // This function unpacks the struct provided as an argument into transaction + // variables of this class. + // This function is defined in apb_m_macros.svh + `apb_m_FROM_MONITOR_STRUCT_FUNCTION + + //******************************************************************* + // Initiator macro used by apb_m_driver and apb_m_driver_bfm + // to communicate initiator driven data to apb_m_driver_bfm. + // This struct is defined in apb_m_macros.svh + `apb_m_INITIATOR_STRUCT + apb_m_initiator_s apb_m_initiator_struct; + //******************************************************************* + // FUNCTION: to_initiator_struct() + // This function packs transaction variables into a apb_m_initiator_s + // structure. The function returns the handle to the apb_m_initiator_struct. + // This function is defined in apb_m_macros.svh + `apb_m_TO_INITIATOR_STRUCT_FUNCTION + //******************************************************************* + // FUNCTION: from_initiator_struct() + // This function unpacks the struct provided as an argument into transaction + // variables of this class. + // This function is defined in apb_m_macros.svh + `apb_m_FROM_INITIATOR_STRUCT_FUNCTION + + //******************************************************************* + // Responder macro used by apb_m_driver and apb_m_driver_bfm + // to communicate Responder driven data to apb_m_driver_bfm. + // This struct is defined in apb_m_macros.svh + `apb_m_RESPONDER_STRUCT + apb_m_responder_s apb_m_responder_struct; + //******************************************************************* + // FUNCTION: to_responder_struct() + // This function packs transaction variables into a apb_m_responder_s + // structure. The function returns the handle to the apb_m_responder_struct. + // This function is defined in apb_m_macros.svh + `apb_m_TO_RESPONDER_STRUCT_FUNCTION + //******************************************************************* + // FUNCTION: from_responder_struct() + // This function unpacks the struct provided as an argument into transaction + // variables of this class. + // This function is defined in apb_m_macros.svh + `apb_m_FROM_RESPONDER_STRUCT_FUNCTION + // **************************************************************************** + // FUNCTION : new() + // This function is the standard SystemVerilog constructor. + // + function new( string name = "" ); + super.new( name ); + endfunction + + // **************************************************************************** + // FUNCTION: convert2string() + // This function converts all variables in this class to a single string for + // logfile reporting. + // + virtual function string convert2string(); + // pragma uvmf custom convert2string begin + // UVMF_CHANGE_ME : Customize format if desired. + return $sformatf("psel:0x%x penable:0x%x paddr:0x%x pwdata:0x%x pwrite:0x%x pstrb:0x%x pprot:0x%x prdata:0x%x pready:0x%x pslverr:0x%x ",psel,penable,paddr,pwdata,pwrite,pstrb,pprot,prdata,pready,pslverr); + // pragma uvmf custom convert2string end + endfunction + + //******************************************************************* + // FUNCTION: do_print() + // This function is automatically called when the .print() function + // is called on this class. + // + virtual function void do_print(uvm_printer printer); + // pragma uvmf custom do_print begin + // UVMF_CHANGE_ME : Current contents of do_print allows for the use of UVM 1.1d, 1.2 or P1800.2. + // Update based on your own printing preference according to your preferred UVM version + $display(convert2string()); + // pragma uvmf custom do_print end + endfunction + + //******************************************************************* + // FUNCTION: do_compare() + // This function is automatically called when the .compare() function + // is called on this class. + // + virtual function bit do_compare (uvm_object rhs, uvm_comparer comparer); + apb_m_transaction #( + .APB_ADDR_WIDTH(APB_ADDR_WIDTH), + .APB_DATA_WIDTH(APB_DATA_WIDTH), + .STRB_LEN(STRB_LEN) + ) RHS; + if (!$cast(RHS,rhs)) return 0; + // pragma uvmf custom do_compare begin + // UVMF_CHANGE_ME : Eliminate comparison of variables not to be used for compare + return (super.do_compare(rhs,comparer) + &&(this.penable == RHS.penable) + &&(this.paddr == RHS.paddr) + &&(this.pwdata == RHS.pwdata) + &&(this.pwrite == RHS.pwrite) + &&(this.pstrb == RHS.pstrb) + &&(this.pprot == RHS.pprot) + &&(this.prdata == RHS.prdata) + &&(this.pready == RHS.pready) + &&(this.pslverr == RHS.pslverr) + ); + // pragma uvmf custom do_compare end + endfunction + + //******************************************************************* + // FUNCTION: do_copy() + // This function is automatically called when the .copy() function + // is called on this class. + // + virtual function void do_copy (uvm_object rhs); + apb_m_transaction #( + .APB_ADDR_WIDTH(APB_ADDR_WIDTH), + .APB_DATA_WIDTH(APB_DATA_WIDTH), + .STRB_LEN(STRB_LEN) + ) RHS; + assert($cast(RHS,rhs)); + // pragma uvmf custom do_copy begin + super.do_copy(rhs); + this.psel = RHS.psel; + this.penable = RHS.penable; + this.paddr = RHS.paddr; + this.pwdata = RHS.pwdata; + this.pwrite = RHS.pwrite; + this.pstrb = RHS.pstrb; + this.pprot = RHS.pprot; + this.prdata = RHS.prdata; + this.pready = RHS.pready; + this.pslverr = RHS.pslverr; + // pragma uvmf custom do_copy end + endfunction + + // **************************************************************************** + // FUNCTION: add_to_wave() + // This function is used to display variables in this class in the waveform + // viewer. The start_time and end_time variables must be set before this + // function is called. If the start_time and end_time variables are not set + // the transaction will be hidden at 0ns on the waveform display. + // + virtual function void add_to_wave(int transaction_viewing_stream_h); + `ifdef QUESTA + if (transaction_view_h == 0) begin + transaction_view_h = $begin_transaction(transaction_viewing_stream_h,"apb_m_transaction",start_time); + end + super.add_to_wave(transaction_view_h); + // pragma uvmf custom add_to_wave begin + // UVMF_CHANGE_ME : Color can be applied to transaction entries based on content, example below + // case() + // 1 : $add_color(transaction_view_h,"red"); + // default : $add_color(transaction_view_h,"grey"); + // endcase + // UVMF_CHANGE_ME : Eliminate transaction variables not wanted in transaction viewing in the waveform viewer + $add_attribute(transaction_view_h,psel,"psel"); + $add_attribute(transaction_view_h,penable,"penable"); + $add_attribute(transaction_view_h,paddr,"paddr"); + $add_attribute(transaction_view_h,pwdata,"pwdata"); + $add_attribute(transaction_view_h,pwrite,"pwrite"); + $add_attribute(transaction_view_h,pstrb,"pstrb"); + $add_attribute(transaction_view_h,pprot,"pprot"); + $add_attribute(transaction_view_h,prdata,"prdata"); + $add_attribute(transaction_view_h,pready,"pready"); + $add_attribute(transaction_view_h,pslverr,"pslverr"); + // pragma uvmf custom add_to_wave end + $end_transaction(transaction_view_h,end_time); + $free_transaction(transaction_view_h); + `endif // QUESTA + endfunction + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/apb_m_pkg/src/apb_m_transaction_coverage.svh b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/apb_m_pkg/src/apb_m_transaction_coverage.svh new file mode 100644 index 00000000..0d1b9c58 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/apb_m_pkg/src/apb_m_transaction_coverage.svh @@ -0,0 +1,91 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This class records apb_m transaction information using +// a covergroup named apb_m_transaction_cg. An instance of this +// coverage component is instantiated in the uvmf_parameterized_agent +// if the has_coverage flag is set. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class apb_m_transaction_coverage #( + int APB_ADDR_WIDTH = 32, + int APB_DATA_WIDTH = 32, + int STRB_LEN = APB_ADDR_WIDTH/8 + ) extends uvm_subscriber #(.T(apb_m_transaction #( + .APB_ADDR_WIDTH(APB_ADDR_WIDTH), + .APB_DATA_WIDTH(APB_DATA_WIDTH), + .STRB_LEN(STRB_LEN) + ))); + + `uvm_component_param_utils( apb_m_transaction_coverage #( + APB_ADDR_WIDTH, + APB_DATA_WIDTH, + STRB_LEN + )) + + T coverage_trans; + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + // **************************************************************************** + covergroup apb_m_transaction_cg; + // pragma uvmf custom covergroup begin + // UVMF_CHANGE_ME : Add coverage bins, crosses, exclusions, etc. according to coverage needs. + option.auto_bin_max=1024; + option.per_instance=1; + psel: coverpoint coverage_trans.psel; + penable: coverpoint coverage_trans.penable; + paddr: coverpoint coverage_trans.paddr; + pwdata: coverpoint coverage_trans.pwdata; + pwrite: coverpoint coverage_trans.pwrite; + pstrb: coverpoint coverage_trans.pstrb; + pprot: coverpoint coverage_trans.pprot; + prdata: coverpoint coverage_trans.prdata; + pready: coverpoint coverage_trans.pready; + pslverr: coverpoint coverage_trans.pslverr; + // pragma uvmf custom covergroup end + endgroup + + // **************************************************************************** + // FUNCTION : new() + // This function is the standard SystemVerilog constructor. + // + function new(string name="", uvm_component parent=null); + super.new(name,parent); + apb_m_transaction_cg=new; + `uvm_warning("COVERAGE_MODEL_REVIEW", "A covergroup has been constructed which may need review because of either generation or re-generation with merging. Please note that transaction variables added as a result of re-generation and merging are not automatically added to the covergroup. Remove this warning after the covergroup has been reviewed.") + endfunction + + // **************************************************************************** + // FUNCTION : build_phase() + // This function is the standard UVM build_phase. + // + function void build_phase(uvm_phase phase); + apb_m_transaction_cg.set_inst_name($sformatf("apb_m_transaction_cg_%s",get_full_name())); + endfunction + + // **************************************************************************** + // FUNCTION: write (T t) + // This function is automatically executed when a transaction arrives on the + // analysis_export. It copies values from the variables in the transaction + // to local variables used to collect functional coverage. + // + virtual function void write (T t); + `uvm_info("COV","Received transaction",UVM_HIGH); + coverage_trans = t; + apb_m_transaction_cg.sample(); + endfunction + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/apb_m_pkg/src/apb_m_typedefs.svh b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/apb_m_pkg/src/apb_m_typedefs.svh new file mode 100644 index 00000000..43d85640 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/apb_m_pkg/src/apb_m_typedefs.svh @@ -0,0 +1,20 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: +// This file contains defines and typedefs to be compiled for use in +// the simulation running on the host server when using Veloce. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// + + +// pragma uvmf custom additional begin +// pragma uvmf custom additional end + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/apb_m_pkg/src/apb_m_typedefs_hdl.svh b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/apb_m_pkg/src/apb_m_typedefs_hdl.svh new file mode 100644 index 00000000..74738c8c --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/apb_m_pkg/src/apb_m_typedefs_hdl.svh @@ -0,0 +1,21 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: +// This file contains defines and typedefs to be compiled for use in +// the simulation running on the emulator when using Veloce. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// + + + +// pragma uvmf custom additional begin +// pragma uvmf custom additional end + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/apb_m_pkg/yaml/apb_m_interface.yaml b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/apb_m_pkg/yaml/apb_m_interface.yaml new file mode 100644 index 00000000..f49301e8 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/apb_m_pkg/yaml/apb_m_interface.yaml @@ -0,0 +1,128 @@ +uvmf: + interfaces: + apb_m: + clock: pclk + config_constraints: [] + config_vars: [] + existing_library_component: 'True' + gen_inbound_streaming_driver: 'False' + hdl_pkg_parameters: [] + hdl_typedefs: [] + hvl_pkg_parameters: [] + hvl_typedefs: [] + parameters: + - name: APB_ADDR_WIDTH + type: int + value: '32' + - name: APB_DATA_WIDTH + type: int + value: '32' + - name: STRB_LEN + type: int + value: APB_ADDR_WIDTH/8 + ports: + - dir: output + name: psel + reset_value: '''b0' + width: '16' + - dir: output + name: penable + reset_value: '''b0' + width: '1' + - dir: output + name: paddr + reset_value: '''b0' + width: APB_ADDR_WIDTH + - dir: output + name: pwdata + reset_value: '''b0' + width: APB_DATA_WIDTH + - dir: output + name: pwrite + reset_value: '''b0' + width: '1' + - dir: output + name: pstrb + reset_value: '''b0' + width: STRB_LEN + - dir: output + name: pprot + reset_value: '''b0' + width: '3' + - dir: input + name: prdata + reset_value: '''b0' + width: APB_DATA_WIDTH + - dir: input + name: pready + reset_value: '0' + width: '1' + - dir: input + name: pslverr + reset_value: '0' + width: '1' + reset: presetn + reset_assertion_level: 'False' + transaction_constraints: [] + transaction_vars: + - comment: '' + iscompare: 'False' + isrand: 'True' + name: psel + type: bit + unpacked_dimension: '' + - comment: '' + iscompare: 'True' + isrand: 'True' + name: penable + type: bit + unpacked_dimension: '' + - comment: '' + iscompare: 'True' + isrand: 'True' + name: paddr + type: bit [APB_ADDR_WIDTH-1:0] + unpacked_dimension: '' + - comment: '' + iscompare: 'True' + isrand: 'True' + name: pwdata + type: bit [APB_DATA_WIDTH-1:0] + unpacked_dimension: '' + - comment: '' + iscompare: 'True' + isrand: 'True' + name: pwrite + type: bit + unpacked_dimension: '' + - comment: '' + iscompare: 'True' + isrand: 'True' + name: pstrb + type: bit [STRB_LEN:0] + unpacked_dimension: '' + - comment: '' + iscompare: 'True' + isrand: 'True' + name: pprot + type: bit [3:0] + unpacked_dimension: '' + - comment: '' + iscompare: 'True' + isrand: 'False' + name: prdata + type: bit [APB_DATA_WIDTH-1:0] + unpacked_dimension: '' + - comment: '' + iscompare: 'True' + isrand: 'False' + name: pready + type: bit + unpacked_dimension: '' + - comment: '' + iscompare: 'True' + isrand: 'False' + name: pslverr + type: bit + unpacked_dimension: '' + use_dpi_link: 'False' diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/axi_m_pkg/.project b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/axi_m_pkg/.project new file mode 100644 index 00000000..7afbc306 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/axi_m_pkg/.project @@ -0,0 +1,30 @@ + + + axi_m_pkg + + + + + + org.python.pydev.PyDevBuilder + + + + + net.sf.sveditor.core.SVProjectBuilder + + + + + + net.sf.sveditor.core.SVNature + org.python.pydev.pythonNature + + + + UVMF_VIP_LIBRARY_HOME + $%7BPARENT-2-PROJECT_LOC%7D + + + + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/axi_m_pkg/.svproject b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/axi_m_pkg/.svproject new file mode 100644 index 00000000..5c637646 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/axi_m_pkg/.svproject @@ -0,0 +1,16 @@ + + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/axi_m_pkg/Makefile b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/axi_m_pkg/Makefile new file mode 100644 index 00000000..49510a8d --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/axi_m_pkg/Makefile @@ -0,0 +1,66 @@ +# axi_m interface packages source +# pragma uvmf custom additional begin +# pragma uvmf custom additional end + +axi_m_PKG = \ + +incdir+$(UVMF_VIP_LIBRARY_HOME)/interface_packages/axi_m_pkg \ + -F $(UVMF_VIP_LIBRARY_HOME)/interface_packages/axi_m_pkg/axi_m_filelist_hvl.f + +axi_m_PKG_HDL = \ + +incdir+$(UVMF_VIP_LIBRARY_HOME)/interface_packages/axi_m_pkg \ + -F $(UVMF_VIP_LIBRARY_HOME)/interface_packages/axi_m_pkg/axi_m_filelist_hdl.f + +axi_m_PKG_XRTL = \ + +incdir+$(UVMF_VIP_LIBRARY_HOME)/interface_packages/axi_m_pkg \ + -F $(UVMF_VIP_LIBRARY_HOME)/interface_packages/axi_m_pkg/axi_m_filelist_xrtl.f + +COMP_axi_m_PKG_TGT_0 = q_comp_axi_m_pkg +COMP_axi_m_PKG_TGT_1 = v_comp_axi_m_pkg +COMP_axi_m_PKG_TGT = $(COMP_axi_m_PKG_TGT_$(USE_VELOCE)) + +comp_axi_m_pkg: $(COMP_axi_m_PKG_TGT) + +q_comp_axi_m_pkg: + $(HDL_COMP_CMD) $(axi_m_PKG_HDL) + $(HVL_COMP_CMD) $(axi_m_PKG) + $(HDL_COMP_CMD) $(axi_m_PKG_XRTL) + +v_comp_axi_m_pkg: + $(HVL_COMP_CMD) $(axi_m_PKG_HDL) + $(HVL_COMP_CMD) $(axi_m_PKG) + $(VELANALYZE_CMD) $(axi_m_PKG_HDL) + $(VELANALYZE_HVL_CMD) $(axi_m_PKG) + $(HDL_COMP_CMD) $(axi_m_PKG_XRTL) + +ifeq ($(MTI_VCO_MODE),64) + GCC_COMP_ARCH = -m64 +else + GCC_COMP_ARCH = -m32 +endif + +export axi_m_IF_DPI_SRC ?= $(UVMF_VIP_LIBRARY_HOME)/interface_packages/axi_m_pkg/dpi + +C_FILE_COMPILE_LIST_axi_m_pkg = \ + +O_FILE_COMPILE_LIST_axi_m_pkg = $(notdir $(C_FILE_COMPILE_LIST_axi_m_pkg:.c=.o)) + +GCC_COMP_ARGS_axi_m_pkg += -I$(axi_m_IF_DPI_SRC) \ + -fPIC + +GCC_COMP_ARGS_axi_m_pkg += $(axi_m_IF_GCC_COMP_ARGUMENTS) + +GCC_LINK_ARGS_axi_m_pkg += \ + \ + -o .so + +comp_axi_m_pkg_c_files: + @echo "--------------------------------" + @echo "Compiling Interface C source" + @echo "--------------------------------" + gcc $(GCC_COMP_ARCH) $(GCC_COMP_ARGS_axi_m_pkg) $(C_FILE_COMPILE_LIST_axi_m_pkg) + @echo "--------------------------------" + @echo "Linking Interface C objects into a shared object" + @echo "--------------------------------" + gcc $(GCC_COMP_ARCH) $(GCC_LINK_ARGS_axi_m_pkg) $(O_FILE_COMPILE_LIST_axi_m_pkg) + @echo "--------------------------------" + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/axi_m_pkg/axi_m.compile b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/axi_m_pkg/axi_m.compile new file mode 100644 index 00000000..c1de0879 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/axi_m_pkg/axi_m.compile @@ -0,0 +1,3 @@ +needs: + - axi_m_hvl.compile + - axi_m_hdl.compile diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/axi_m_pkg/axi_m_bfm.vinfo b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/axi_m_pkg/axi_m_bfm.vinfo new file mode 100644 index 00000000..69c6a9be --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/axi_m_pkg/axi_m_bfm.vinfo @@ -0,0 +1,6 @@ +@use $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg_hdl.vinfo +@use axi_m_pkg_hdl.vinfo ++incdir+@vinfodir +src/axi_m_if.sv +src/axi_m_driver_bfm.sv +src/axi_m_monitor_bfm.sv diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/axi_m_pkg/axi_m_common.compile b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/axi_m_pkg/axi_m_common.compile new file mode 100644 index 00000000..325f4c25 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/axi_m_pkg/axi_m_common.compile @@ -0,0 +1,7 @@ +needs: + - $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg_hdl.compile +incdir: + - . + - ${uvm_path}/src +src: + - axi_m_pkg_hdl.sv diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/axi_m_pkg/axi_m_filelist_hdl.f b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/axi_m_pkg/axi_m_filelist_hdl.f new file mode 100644 index 00000000..af073f29 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/axi_m_pkg/axi_m_filelist_hdl.f @@ -0,0 +1 @@ +$UVMF_VIP_LIBRARY_HOME/interface_packages/axi_m_pkg/axi_m_pkg_hdl.sv diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/axi_m_pkg/axi_m_filelist_hvl.f b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/axi_m_pkg/axi_m_filelist_hvl.f new file mode 100644 index 00000000..0c583aa9 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/axi_m_pkg/axi_m_filelist_hvl.f @@ -0,0 +1 @@ +$UVMF_VIP_LIBRARY_HOME/interface_packages/axi_m_pkg/axi_m_pkg.sv \ No newline at end of file diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/axi_m_pkg/axi_m_filelist_xrtl.f b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/axi_m_pkg/axi_m_filelist_xrtl.f new file mode 100644 index 00000000..0348c6ae --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/axi_m_pkg/axi_m_filelist_xrtl.f @@ -0,0 +1,3 @@ +$UVMF_VIP_LIBRARY_HOME/interface_packages/axi_m_pkg/src/axi_m_if.sv +$UVMF_VIP_LIBRARY_HOME/interface_packages/axi_m_pkg/src/axi_m_monitor_bfm.sv +$UVMF_VIP_LIBRARY_HOME/interface_packages/axi_m_pkg/src/axi_m_driver_bfm.sv diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/axi_m_pkg/axi_m_hdl.compile b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/axi_m_pkg/axi_m_hdl.compile new file mode 100644 index 00000000..59f061bc --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/axi_m_pkg/axi_m_hdl.compile @@ -0,0 +1,9 @@ +needs: + - $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg_hdl.compile + - ./axi_m_common.compile +incdir: + - . +src: + - src/axi_m_if.sv + - src/axi_m_monitor_bfm.sv + - src/axi_m_driver_bfm.sv diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/axi_m_pkg/axi_m_hvl.compile b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/axi_m_pkg/axi_m_hvl.compile new file mode 100644 index 00000000..b72727cc --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/axi_m_pkg/axi_m_hvl.compile @@ -0,0 +1,7 @@ +needs: + - $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg.compile + - ./axi_m_common.compile +incdir: + - . +src: + - axi_m_pkg.sv diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/axi_m_pkg/axi_m_pkg.sv b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/axi_m_pkg/axi_m_pkg.sv new file mode 100644 index 00000000..4e2e996f --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/axi_m_pkg/axi_m_pkg.sv @@ -0,0 +1,77 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// PACKAGE: This file defines all of the files contained in the +// interface package that will run on the host simulator. +// +// CONTAINS: +// - +// - +// - + +// - +// - +// - + +// - +// - +// - + +// - +// - +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +package axi_m_pkg; + + import uvm_pkg::*; + import uvmf_base_pkg_hdl::*; + import uvmf_base_pkg::*; + import axi_m_pkg_hdl::*; + + `include "uvm_macros.svh" + + // pragma uvmf custom package_imports_additional begin + // pragma uvmf custom package_imports_additional end + `include "src/axi_m_macros.svh" + + export axi_m_pkg_hdl::*; + + + + // Parameters defined as HVL parameters + + `include "src/axi_m_typedefs.svh" + `include "src/axi_m_transaction.svh" + + `include "src/axi_m_configuration.svh" + `include "src/axi_m_driver.svh" + `include "src/axi_m_monitor.svh" + + `include "src/axi_m_transaction_coverage.svh" + `include "src/axi_m_sequence_base.svh" + `include "src/axi_m_random_sequence.svh" + + `include "src/axi_m_responder_sequence.svh" + `include "src/axi_m2reg_adapter.svh" + + `include "src/axi_m_agent.svh" + + // pragma uvmf custom package_item_additional begin + // UVMF_CHANGE_ME : When adding new interface sequences to the src directory + // be sure to add the sequence file here so that it will be + // compiled as part of the interface package. Be sure to place + // the new sequence after any base sequences of the new sequence. + // pragma uvmf custom package_item_additional end + +endpackage + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/axi_m_pkg/axi_m_pkg.vinfo b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/axi_m_pkg/axi_m_pkg.vinfo new file mode 100644 index 00000000..dae51d0c --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/axi_m_pkg/axi_m_pkg.vinfo @@ -0,0 +1,4 @@ +@use $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg.vinfo +@use axi_m_pkg_hdl.vinfo ++incdir+@vinfodir +axi_m_pkg.sv diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/axi_m_pkg/axi_m_pkg_hdl.sv b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/axi_m_pkg/axi_m_pkg_hdl.sv new file mode 100644 index 00000000..37e46870 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/axi_m_pkg/axi_m_pkg_hdl.sv @@ -0,0 +1,38 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// PACKAGE: This file defines all of the files contained in the +// interface package that needs to be compiled and synthesized +// for running on Veloce. +// +// CONTAINS: +// - +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +package axi_m_pkg_hdl; + + import uvmf_base_pkg_hdl::*; + + // pragma uvmf custom package_imports_additional begin + // pragma uvmf custom package_imports_additional end + + // Parameters defined as HDL parameters + + `include "src/axi_m_typedefs_hdl.svh" + `include "src/axi_m_macros.svh" + + // pragma uvmf custom package_item_additional begin + // pragma uvmf custom package_item_additional end + +endpackage + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/axi_m_pkg/axi_m_pkg_hdl.vinfo b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/axi_m_pkg/axi_m_pkg_hdl.vinfo new file mode 100644 index 00000000..4bcea0fb --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/axi_m_pkg/axi_m_pkg_hdl.vinfo @@ -0,0 +1,2 @@ +@use $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg_hdl.vinfo +axi_m_pkg_hdl.sv diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/axi_m_pkg/axi_m_pkg_sve.F b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/axi_m_pkg/axi_m_pkg_sve.F new file mode 100644 index 00000000..fd118edd --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/axi_m_pkg/axi_m_pkg_sve.F @@ -0,0 +1,10 @@ +// UVM ++incdir+${UVM_HOME}/src +${UVM_HOME}/src/uvm_pkg.sv + +// Common UVMF files +-f ${UVMF_HOME}/common/common_sve.f + ++incdir+. +-f ${UVMF_VIP_LIBRARY_HOME}/interface_packages/axi_m_pkg/axi_m_filelist_hdl.f +-f ${UVMF_VIP_LIBRARY_HOME}/interface_packages/axi_m_pkg/axi_m_filelist_hvl.f diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/axi_m_pkg/compile.do b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/axi_m_pkg/compile.do new file mode 100644 index 00000000..ea448b12 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/axi_m_pkg/compile.do @@ -0,0 +1,14 @@ +# Tcl do file for compile of axi_m interface + +# pragma uvmf custom additional begin +# pragma uvmf custom additional end + + +vlog -sv -timescale 1ps/1ps -suppress 2223,2286 +incdir+$env(UVMF_VIP_LIBRARY_HOME)/interface_packages/axi_m_pkg \ + -F $env(UVMF_VIP_LIBRARY_HOME)/interface_packages/axi_m_pkg/axi_m_filelist_hdl.f + +vlog -sv -timescale 1ps/1ps -suppress 2223,2286 +incdir+$env(UVMF_VIP_LIBRARY_HOME)/interface_packages/axi_m_pkg \ + -F $env(UVMF_VIP_LIBRARY_HOME)/interface_packages/axi_m_pkg/axi_m_filelist_hvl.f + +vlog -sv -timescale 1ps/1ps -suppress 2223,2286 +incdir+$env(UVMF_VIP_LIBRARY_HOME)/interface_packages/axi_m_pkg \ + -F $env(UVMF_VIP_LIBRARY_HOME)/interface_packages/axi_m_pkg/axi_m_filelist_xrtl.f \ No newline at end of file diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/axi_m_pkg/src/axi_m2reg_adapter.svh b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/axi_m_pkg/src/axi_m2reg_adapter.svh new file mode 100644 index 00000000..5e9efca8 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/axi_m_pkg/src/axi_m2reg_adapter.svh @@ -0,0 +1,123 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: +// This file contains the UVM register adapter for the axi_m interface. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class axi_m2reg_adapter #( + int AW_WIDTH = 32, + int LEN = 8, + int DATA_WIDTH = 32, + int X = 16 + ) extends uvm_reg_adapter; + + `uvm_object_param_utils( axi_m2reg_adapter #( + AW_WIDTH, + LEN, + DATA_WIDTH, + X + )) + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + //-------------------------------------------------------------------- + // new + //-------------------------------------------------------------------- + function new (string name = "axi_m2reg_adapter" ); + super.new(name); + // pragma uvmf custom new begin + // UVMF_CHANGE_ME : Configure the adapter regarding byte enables and provides response. + + // Does the protocol the Agent is modeling support byte enables? + // 0 = NO + // 1 = YES + supports_byte_enable = 0; + + // Does the Agent's Driver provide separate response sequence items? + // i.e. Does the driver call seq_item_port.put() + // and do the sequences call get_response()? + // 0 = NO + // 1 = YES + provides_responses = 0; + // pragma uvmf custom new end + + endfunction: new + + //-------------------------------------------------------------------- + // reg2bus + //-------------------------------------------------------------------- + virtual function uvm_sequence_item reg2bus(const ref uvm_reg_bus_op rw); + + axi_m_transaction #( + .AW_WIDTH(AW_WIDTH), + .LEN(LEN), + .DATA_WIDTH(DATA_WIDTH), + .X(X) + ) trans_h = axi_m_transaction #( + .AW_WIDTH(AW_WIDTH), + .LEN(LEN), + .DATA_WIDTH(DATA_WIDTH), + .X(X) + )::type_id::create("trans_h"); + + // pragma uvmf custom reg2bus begin + // UVMF_CHANGE_ME : Fill in the reg2bus adapter mapping registe fields to protocol fields. + + //Adapt the following for your sequence item type + // trans_h.op = (rw.kind == UVM_READ) ? WB_READ : WB_WRITE; + //Copy over address + // trans_h.addr = rw.addr; + //Copy over write data + // trans_h.data = rw.data; + + // pragma uvmf custom reg2bus end + + // Return the adapted transaction + return trans_h; + + endfunction: reg2bus + + //-------------------------------------------------------------------- + // bus2reg + //-------------------------------------------------------------------- + virtual function void bus2reg(uvm_sequence_item bus_item, + ref uvm_reg_bus_op rw); + axi_m_transaction #( + .AW_WIDTH(AW_WIDTH), + .LEN(LEN), + .DATA_WIDTH(DATA_WIDTH), + .X(X) + ) trans_h; + if (!$cast(trans_h, bus_item)) begin + `uvm_fatal("ADAPT","Provided bus_item is not of the correct type") + return; + end + // pragma uvmf custom bus2reg begin + // UVMF_CHANGE_ME : Fill in the bus2reg adapter mapping protocol fields to register fields. + //Adapt the following for your sequence item type + //Copy over instruction type + // rw.kind = (trans_h.op == WB_WRITE) ? UVM_WRITE : UVM_READ; + //Copy over address + // rw.addr = trans_h.addr; + //Copy over read data + // rw.data = trans_h.data; + //Check for errors on the bus and return UVM_NOT_OK if there is an error + // rw.status = UVM_IS_OK; + // pragma uvmf custom bus2reg end + + endfunction: bus2reg + +endclass : axi_m2reg_adapter + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/axi_m_pkg/src/axi_m_agent.svh b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/axi_m_pkg/src/axi_m_agent.svh new file mode 100644 index 00000000..6da6dbed --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/axi_m_pkg/src/axi_m_agent.svh @@ -0,0 +1,88 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: Protocol specific agent class definition +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class axi_m_agent #( + int AW_WIDTH = 32, + int LEN = 8, + int DATA_WIDTH = 32, + int X = 16 + ) extends uvmf_parameterized_agent #( + .CONFIG_T(axi_m_configuration #( + .AW_WIDTH(AW_WIDTH), + .LEN(LEN), + .DATA_WIDTH(DATA_WIDTH), + .X(X) + )), + .DRIVER_T(axi_m_driver #( + .AW_WIDTH(AW_WIDTH), + .LEN(LEN), + .DATA_WIDTH(DATA_WIDTH), + .X(X) + )), + .MONITOR_T(axi_m_monitor #( + .AW_WIDTH(AW_WIDTH), + .LEN(LEN), + .DATA_WIDTH(DATA_WIDTH), + .X(X) + )), + .COVERAGE_T(axi_m_transaction_coverage #( + .AW_WIDTH(AW_WIDTH), + .LEN(LEN), + .DATA_WIDTH(DATA_WIDTH), + .X(X) + )), + .TRANS_T(axi_m_transaction #( + .AW_WIDTH(AW_WIDTH), + .LEN(LEN), + .DATA_WIDTH(DATA_WIDTH), + .X(X) + )) + ); + + `uvm_component_param_utils( axi_m_agent #( + AW_WIDTH, + LEN, + DATA_WIDTH, + X + )) + +// pragma uvmf custom class_item_additional begin +// pragma uvmf custom class_item_additional end + +// **************************************************************************** +// FUNCTION : new() +// This function is the standard SystemVerilog constructor. +// + function new( string name = "", uvm_component parent = null ); + super.new( name, parent ); + endfunction + +// **************************************************************************** + // FUNCTION: build_phase + virtual function void build_phase(uvm_phase phase); +// pragma uvmf custom build_phase_pre_super begin +// pragma uvmf custom build_phase_pre_super end + super.build_phase(phase); + if (configuration.active_passive == ACTIVE) begin + // Place sequencer handle into configuration object + // so that it may be retrieved from configuration + // rather than using uvm_config_db + configuration.sequencer = this.sequencer; + end + endfunction + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/axi_m_pkg/src/axi_m_configuration.svh b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/axi_m_pkg/src/axi_m_configuration.svh new file mode 100644 index 00000000..2cecbe25 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/axi_m_pkg/src/axi_m_configuration.svh @@ -0,0 +1,219 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This class contains all variables and functions used +// to configure the axi_m agent and its bfm's. It gets the +// bfm's from the uvm_config_db for use by the agent. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class axi_m_configuration #( + int AW_WIDTH = 32, + int LEN = 8, + int DATA_WIDTH = 32, + int X = 16 + ) extends uvmf_parameterized_agent_configuration_base #( + .DRIVER_BFM_BIND_T(virtual axi_m_driver_bfm #( + .AW_WIDTH(AW_WIDTH), + .LEN(LEN), + .DATA_WIDTH(DATA_WIDTH), + .X(X) + )), + .MONITOR_BFM_BIND_T( virtual axi_m_monitor_bfm #( + .AW_WIDTH(AW_WIDTH), + .LEN(LEN), + .DATA_WIDTH(DATA_WIDTH), + .X(X) + ))); + + `uvm_object_param_utils( axi_m_configuration #( + AW_WIDTH, + LEN, + DATA_WIDTH, + X + )) + + + // Sequencer handle populated by agent + uvm_sequencer #(axi_m_transaction #( + .AW_WIDTH(AW_WIDTH), + .LEN(LEN), + .DATA_WIDTH(DATA_WIDTH), + .X(X) + ) ) sequencer; + + //Constraints for the configuration variables: + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + covergroup axi_m_configuration_cg; + // pragma uvmf custom covergroup begin + option.auto_bin_max=1024; + // pragma uvmf custom covergroup end + endgroup + + //******************************************************************* + //******************************************************************* + // Structure used to pass configuration variables to monitor and driver BFM's. + // Use to_struct function to pack variables into structure. + // Use from_struct function to unpack variables from structure. + // This structure is defined in axi_m_macros.svh + `axi_m_CONFIGURATION_STRUCT + axi_m_configuration_s axi_m_configuration_struct; + //******************************************************************* + // FUNCTION: to_struct() + // This function packs variables into a axi_m_configuration_s + // structure. The function returns the handle to the axi_m_configuration_struct. + // This function is defined in axi_m_macros.svh + `axi_m_CONFIGURATION_TO_STRUCT_FUNCTION + //******************************************************************* + // FUNCTION: from_struct() + // This function unpacks the struct provided as an argument into + // variables of this class. + // This function is defined in axi_m_macros.svh + `axi_m_CONFIGURATION_FROM_STRUCT_FUNCTION + + // **************************************************************************** + // FUNCTION : new() + // This function is the standard SystemVerilog constructor. + // + function new( string name = "" ); + super.new( name ); + // Construct the covergroup for this configuration class + axi_m_configuration_cg = new; + endfunction + + // **************************************************************************** + // FUNCTION: post_randomize() + // This function is automatically called after the randomize() function + // is executed. + // + function void post_randomize(); + super.post_randomize(); + axi_m_configuration_cg.sample(); + endfunction + + // **************************************************************************** + // FUNCTION: initialize + // This function causes the configuration to retrieve + // its virtual interface handle from the uvm_config_db. + // This function also makes itself available to its + // agent through the uvm_config_db. + // + // ARGUMENTS: + // uvmf_active_passive_t activity: + // This argument identifies the simulation level + // as either BLOCK, CHIP, SIMULATION, etc. + // + // AGENT_PATH: + // This argument identifies the path to this + // configurations agent. This configuration + // makes itself available to the agent specified + // by agent_path by placing itself into the + // uvm_config_db. + // + // INTERFACE_NAME: + // This argument identifies the string name of + // this configurations BFM's. This string + // name is used to retrieve the driver and + // monitor BFM from the uvm_config_db. + // + virtual function void initialize(uvmf_active_passive_t activity, + string agent_path, + string interface_name); + + super.initialize( activity, agent_path, interface_name); + // The covergroup is given the same name as the interface + axi_m_configuration_cg.set_inst_name(interface_name); + + // This configuration places itself into the uvm_config_db for the agent, identified by the agent_path variable, to retrieve. + uvm_config_db #( axi_m_configuration #( + .AW_WIDTH(AW_WIDTH), + .LEN(LEN), + .DATA_WIDTH(DATA_WIDTH), + .X(X) + ) + )::set( null ,agent_path,UVMF_AGENT_CONFIG, this ); + + // This configuration also places itself in the config db using the same identifier used by the interface. This allows users to access + // configuration variables and the interface through the bfm api class rather than directly accessing the BFM. This is useful for + // accessingthe BFM when using Veloce + uvm_config_db #( axi_m_configuration #( + .AW_WIDTH(AW_WIDTH), + .LEN(LEN), + .DATA_WIDTH(DATA_WIDTH), + .X(X) + ) + )::set( null ,UVMF_CONFIGURATIONS, interface_name, this ); + + axi_m_configuration_cg.set_inst_name($sformatf("axi_m_configuration_cg_%s",get_full_name())); + +// This code is to aid in debugging parameter mismatches between the BFM and its corresponding agent. +// Enable this debug by setting UVM_VERBOSITY to UVM_DEBUG +// Setting UVM_VERBOSITY to UVM_DEBUG causes all BFM's and all agents to display their parameter settings. +// All of the messages from this feature have a UVM messaging id value of "CFG" +// The transcript or run.log can be parsed to ensure BFM parameter settings match its corresponding agents parameter settings. + `uvm_info("CFG", + $psprintf("The agent at '%s' is using interface named %s has the following parameters: AW_WIDTH=%x LEN=%x DATA_WIDTH=%x X=%x ", agent_path, interface_name, AW_WIDTH ,LEN ,DATA_WIDTH ,X ), + UVM_DEBUG) + + // pragma uvmf custom initialize begin + // This controls whether or not the agent returns a transaction handle in the driver when calling + // item_done() back into the sequencer or not. If set to 1, a transaction is sent back which means + // the sequence on the other end must use the get_response() part of the driver/sequence API. If + // this doesn't occur, there will eventually be response_queue overflow errors during the test. + return_transaction_response = 1'b0; + + // pragma uvmf custom initialize end + + endfunction + + // **************************************************************************** + // TASK: wait_for_reset + // *[Required]* Blocks until reset is released. The wait_for_reset operation is performed + // by a task in the monitor bfm. + virtual task wait_for_reset(); + monitor_bfm.wait_for_reset(); + endtask + + // **************************************************************************** + // TASK: wait_for_num_clocks + // *[Required]* Blocks until specified number of clocks have elapsed. The wait_for_num_clocks + // operation is performed by a task in the monitor bfm. + virtual task wait_for_num_clocks(int clocks); + monitor_bfm.wait_for_num_clocks(clocks); + endtask + + // **************************************************************************** + // FUNCTION : convert2string() + // This function is used to convert variables in this class into a string for log messaging. + // + virtual function string convert2string (); + // pragma uvmf custom convert2string begin + return $sformatf(""); + // pragma uvmf custom convert2string end + endfunction + + // **************************************************************************** + // FUNCTION: get_sequencer + function uvm_sequencer #(axi_m_transaction#( + .AW_WIDTH(AW_WIDTH), + .LEN(LEN), + .DATA_WIDTH(DATA_WIDTH), + .X(X) + )) get_sequencer(); + return sequencer; + endfunction + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/axi_m_pkg/src/axi_m_driver.svh b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/axi_m_pkg/src/axi_m_driver.svh new file mode 100644 index 00000000..aca314e5 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/axi_m_pkg/src/axi_m_driver.svh @@ -0,0 +1,121 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This class passes transactions between the sequencer +// and the BFM driver interface. It accesses the driver BFM +// through the bfm handle. This driver +// passes transactions to the driver BFM through the access +// task. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class axi_m_driver #( + int AW_WIDTH = 32, + int LEN = 8, + int DATA_WIDTH = 32, + int X = 16 + ) extends uvmf_driver_base #( + .CONFIG_T(axi_m_configuration #( + .AW_WIDTH(AW_WIDTH), + .LEN(LEN), + .DATA_WIDTH(DATA_WIDTH), + .X(X) + ) ), + .BFM_BIND_T(virtual axi_m_driver_bfm #( + .AW_WIDTH(AW_WIDTH), + .LEN(LEN), + .DATA_WIDTH(DATA_WIDTH), + .X(X) + ) ), + .REQ(axi_m_transaction #( + .AW_WIDTH(AW_WIDTH), + .LEN(LEN), + .DATA_WIDTH(DATA_WIDTH), + .X(X) + ) ), + .RSP(axi_m_transaction #( + .AW_WIDTH(AW_WIDTH), + .LEN(LEN), + .DATA_WIDTH(DATA_WIDTH), + .X(X) + ) )); + + `uvm_component_param_utils( axi_m_driver #( + AW_WIDTH, + LEN, + DATA_WIDTH, + X + )) +//******************************************************************* +// Macros that define structs located in axi_m_macros.svh +//******************************************************************* +// Initiator macro used by axi_m_driver and axi_m_driver_bfm +// to communicate initiator driven data to axi_m_driver_bfm. +`axi_m_INITIATOR_STRUCT + axi_m_initiator_s axi_m_initiator_struct; +//******************************************************************* +// Responder macro used by axi_m_driver and axi_m_driver_bfm +// to communicate Responder driven data to axi_m_driver_bfm. +`axi_m_RESPONDER_STRUCT + axi_m_responder_s axi_m_responder_struct; + +// pragma uvmf custom class_item_additional begin +// pragma uvmf custom class_item_additional end + +// **************************************************************************** +// This function is the standard SystemVerilog constructor. +// + function new( string name = "", uvm_component parent=null ); + super.new( name, parent ); + endfunction + +// **************************************************************************** +// This function sends configuration object variables to the driver BFM +// using the configuration struct. +// + virtual function void configure(input CONFIG_T cfg); + bfm.configure( cfg.to_struct() ); + endfunction + +// **************************************************************************** +// This function places a handle to this class in the proxy variable in the +// driver BFM. This allows the driver BFM to call tasks and function within this class. +// + virtual function void set_bfm_proxy_handle(); + bfm.proxy = this; endfunction + +// **************************************************************************** +// This task is called by the run_phase in uvmf_driver_base. + virtual task access( inout REQ txn ); +// pragma uvmf custom access begin + if (configuration.initiator_responder==RESPONDER) begin + // Complete current transfer and wait for next transfer + bfm.respond_and_wait_for_next_transfer( + axi_m_initiator_struct, + txn.to_responder_struct() + ); + // Unpack information about initiated transfer received by this responder + txn.from_initiator_struct(axi_m_initiator_struct); + end else begin + // Initiate a transfer and get response + bfm.initiate_and_get_response( + txn.to_initiator_struct(), + axi_m_responder_struct + ); + // Unpack transfer response information received by this initiator + txn.from_responder_struct(axi_m_responder_struct); + end +// pragma uvmf custom access end + endtask + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/axi_m_pkg/src/axi_m_driver_bfm.sv b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/axi_m_pkg/src/axi_m_driver_bfm.sv new file mode 100644 index 00000000..79c5ef38 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/axi_m_pkg/src/axi_m_driver_bfm.sv @@ -0,0 +1,765 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: +// This interface performs the axi_m signal driving. It is +// accessed by the uvm axi_m driver through a virtual interface +// handle in the axi_m configuration. It drives the singals passed +// in through the port connection named bus of type axi_m_if. +// +// Input signals from the axi_m_if are assigned to an internal input +// signal with a _i suffix. The _i signal should be used for sampling. +// +// The input signal connections are as follows: +// bus.signal -> signal_i +// +// This bfm drives signals with a _o suffix. These signals +// are driven onto signals within axi_m_if based on INITIATOR/RESPONDER and/or +// ARBITRATION/GRANT status. +// +// The output signal connections are as follows: +// signal_o -> bus.signal +// +// +// Interface functions and tasks used by UVM components: +// +// configure: +// This function gets configuration attributes from the +// UVM driver to set any required BFM configuration +// variables such as 'initiator_responder'. +// +// initiate_and_get_response: +// This task is used to perform signaling activity for initiating +// a protocol transfer. The task initiates the transfer, using +// input data from the initiator struct. Then the task captures +// response data, placing the data into the response struct. +// The response struct is returned to the driver class. +// +// respond_and_wait_for_next_transfer: +// This task is used to complete a current transfer as a responder +// and then wait for the initiator to start the next transfer. +// The task uses data in the responder struct to drive protocol +// signals to complete the transfer. The task then waits for +// the next transfer. Once the next transfer begins, data from +// the initiator is placed into the initiator struct and sent +// to the responder sequence for processing to determine +// what data to respond with. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +import uvmf_base_pkg_hdl::*; +import axi_m_pkg_hdl::*; +`include "src/axi_m_macros.svh" + +interface axi_m_driver_bfm #( + int AW_WIDTH = 32, + int LEN = 8, + int DATA_WIDTH = 32, + int X = 16 + ) + (axi_m_if bus); + // The following pragma and additional ones in-lined further below are for running this BFM on Veloce + // pragma attribute axi_m_driver_bfm partition_interface_xif + +`ifndef XRTL +// This code is to aid in debugging parameter mismatches between the BFM and its corresponding agent. +// Enable this debug by setting UVM_VERBOSITY to UVM_DEBUG +// Setting UVM_VERBOSITY to UVM_DEBUG causes all BFM's and all agents to display their parameter settings. +// All of the messages from this feature have a UVM messaging id value of "CFG" +// The transcript or run.log can be parsed to ensure BFM parameter settings match its corresponding agents parameter settings. +import uvm_pkg::*; +`include "uvm_macros.svh" +initial begin : bfm_vs_agent_parameter_debug + `uvm_info("CFG", + $psprintf("The BFM at '%m' has the following parameters: AW_WIDTH=%x LEN=%x DATA_WIDTH=%x X=%x ", AW_WIDTH,LEN,DATA_WIDTH,X), + UVM_DEBUG) +end +`endif + + // Config value to determine if this is an initiator or a responder + uvmf_initiator_responder_t initiator_responder; + // Custom configuration variables. + // These are set using the configure function which is called during the UVM connect_phase + + logic axi_clk_i; + logic rst_i; + + // Signal list (all signals are capable of being inputs and outputs for the sake + // of supporting both INITIATOR and RESPONDER mode operation. Expectation is that + // directionality in the config file was from the point-of-view of the INITIATOR + + // INITIATOR mode input signals + tri awready_i; + reg awready_o = 'bz; + tri wready_i; + reg wready_o = 'bz; + tri bwvalid_i; + reg bwvalid_o = 'bz; + tri [1:0] bresp_i; + reg [1:0] bresp_o = 'bz; + tri [X-1:0] bid_i; + reg [X-1:0] bid_o = 'bz; + tri [X-1:0] buser_i; + reg [X-1:0] buser_o = 'bz; + tri aready_i; + reg aready_o = 'bz; + tri rvalid_i; + reg rvalid_o = 'bz; + tri rlast_i; + reg rlast_o = 'bz; + tri [DATA_WIDTH-1:0] rdata_i; + reg [DATA_WIDTH-1:0] rdata_o = 'bz; + tri [X-1:0] rid_i; + reg [X-1:0] rid_o = 'bz; + tri [X-1:0] ruser_i; + reg [X-1:0] ruser_o = 'bz; + tri [1:0] rresp_i; + reg [1:0] rresp_o = 'bz; + + // INITIATOR mode output signals + tri awvalid_i; + reg awvalid_o = 'bz; + tri [AW_WIDTH-1:0] awaddr_i; + reg [AW_WIDTH-1:0] awaddr_o = 'bz; + tri [2:0] awsize_i; + reg [2:0] awsize_o = 'bz; + tri [1:0] awburst_i; + reg [1:0] awburst_o = 'bz; + tri [3:0] awcache_i; + reg [3:0] awcache_o = 'bz; + tri [2:0] awprot_i; + reg [2:0] awprot_o = 'bz; + tri [X-1:0] awid_i; + reg [X-1:0] awid_o = 'bz; + tri [LEN-1:0] awlen_i; + reg [LEN-1:0] awlen_o = 'bz; + tri awlock_i; + reg awlock_o = 'bz; + tri [3:0] awqos_i; + reg [3:0] awqos_o = 'bz; + tri [3:0] awregion_i; + reg [3:0] awregion_o = 'bz; + tri [X-1:0] awuser_i; + reg [X-1:0] awuser_o = 'bz; + tri wvalid_i; + reg wvalid_o = 'bz; + tri wlast_i; + reg wlast_o = 'bz; + tri [DATA_WIDTH-1:0] wdata_i; + reg [DATA_WIDTH-1:0] wdata_o = 'bz; + tri [DATA_WIDTH/8-1:0] wstrb_i; + reg [DATA_WIDTH/8-1:0] wstrb_o = 'bz; + tri [X-1:0] wid_i; + reg [X-1:0] wid_o = 'bz; + tri [X-1:0] wuser_i; + reg [X-1:0] wuser_o = 'bz; + tri bwready_i; + reg bwready_o = 'bz; + tri arvalid_i; + reg arvalid_o = 'bz; + tri [AW_WIDTH-1:0] araddr_i; + reg [AW_WIDTH-1:0] araddr_o = 'bz; + tri [2:0] arsize_i; + reg [2:0] arsize_o = 'bz; + tri [1:0] arburst_i; + reg [1:0] arburst_o = 'bz; + tri [3:0] arcache_i; + reg [3:0] arcache_o = 'bz; + tri [2:0] arprot_i; + reg [2:0] arprot_o = 'bz; + tri [X-1:0] arid_i; + reg [X-1:0] arid_o = 'bz; + tri [LEN-1:0] arlen_i; + reg [LEN-1:0] arlen_o = 'bz; + tri arlock_i; + reg arlock_o = 'bz; + tri [3:0] arqos_i; + reg [3:0] arqos_o = 'bz; + tri [3:0] aregion_i; + reg [3:0] aregion_o = 'bz; + tri [X-1:0] aruser_i; + reg [X-1:0] aruser_o = 'bz; + tri rready_i; + reg rready_o = 'bz; + + // Bi-directional signals + + + assign axi_clk_i = bus.axi_clk; + assign rst_i = bus.rst; + + // These are signals marked as 'input' by the config file, but the signals will be + // driven by this BFM if put into RESPONDER mode (flipping all signal directions around) + assign awready_i = bus.awready; + assign bus.awready = (initiator_responder == RESPONDER) ? awready_o : 'bz; + assign wready_i = bus.wready; + assign bus.wready = (initiator_responder == RESPONDER) ? wready_o : 'bz; + assign bwvalid_i = bus.bwvalid; + assign bus.bwvalid = (initiator_responder == RESPONDER) ? bwvalid_o : 'bz; + assign bresp_i = bus.bresp; + assign bus.bresp = (initiator_responder == RESPONDER) ? bresp_o : 'bz; + assign bid_i = bus.bid; + assign bus.bid = (initiator_responder == RESPONDER) ? bid_o : 'bz; + assign buser_i = bus.buser; + assign bus.buser = (initiator_responder == RESPONDER) ? buser_o : 'bz; + assign aready_i = bus.aready; + assign bus.aready = (initiator_responder == RESPONDER) ? aready_o : 'bz; + assign rvalid_i = bus.rvalid; + assign bus.rvalid = (initiator_responder == RESPONDER) ? rvalid_o : 'bz; + assign rlast_i = bus.rlast; + assign bus.rlast = (initiator_responder == RESPONDER) ? rlast_o : 'bz; + assign rdata_i = bus.rdata; + assign bus.rdata = (initiator_responder == RESPONDER) ? rdata_o : 'bz; + assign rid_i = bus.rid; + assign bus.rid = (initiator_responder == RESPONDER) ? rid_o : 'bz; + assign ruser_i = bus.ruser; + assign bus.ruser = (initiator_responder == RESPONDER) ? ruser_o : 'bz; + assign rresp_i = bus.rresp; + assign bus.rresp = (initiator_responder == RESPONDER) ? rresp_o : 'bz; + + + // These are signals marked as 'output' by the config file, but the outputs will + // not be driven by this BFM unless placed in INITIATOR mode. + assign bus.awvalid = (initiator_responder == INITIATOR) ? awvalid_o : 'bz; + assign awvalid_i = bus.awvalid; + assign bus.awaddr = (initiator_responder == INITIATOR) ? awaddr_o : 'bz; + assign awaddr_i = bus.awaddr; + assign bus.awsize = (initiator_responder == INITIATOR) ? awsize_o : 'bz; + assign awsize_i = bus.awsize; + assign bus.awburst = (initiator_responder == INITIATOR) ? awburst_o : 'bz; + assign awburst_i = bus.awburst; + assign bus.awcache = (initiator_responder == INITIATOR) ? awcache_o : 'bz; + assign awcache_i = bus.awcache; + assign bus.awprot = (initiator_responder == INITIATOR) ? awprot_o : 'bz; + assign awprot_i = bus.awprot; + assign bus.awid = (initiator_responder == INITIATOR) ? awid_o : 'bz; + assign awid_i = bus.awid; + assign bus.awlen = (initiator_responder == INITIATOR) ? awlen_o : 'bz; + assign awlen_i = bus.awlen; + assign bus.awlock = (initiator_responder == INITIATOR) ? awlock_o : 'bz; + assign awlock_i = bus.awlock; + assign bus.awqos = (initiator_responder == INITIATOR) ? awqos_o : 'bz; + assign awqos_i = bus.awqos; + assign bus.awregion = (initiator_responder == INITIATOR) ? awregion_o : 'bz; + assign awregion_i = bus.awregion; + assign bus.awuser = (initiator_responder == INITIATOR) ? awuser_o : 'bz; + assign awuser_i = bus.awuser; + assign bus.wvalid = (initiator_responder == INITIATOR) ? wvalid_o : 'bz; + assign wvalid_i = bus.wvalid; + assign bus.wlast = (initiator_responder == INITIATOR) ? wlast_o : 'bz; + assign wlast_i = bus.wlast; + assign bus.wdata = (initiator_responder == INITIATOR) ? wdata_o : 'bz; + assign wdata_i = bus.wdata; + assign bus.wstrb = (initiator_responder == INITIATOR) ? wstrb_o : 'bz; + assign wstrb_i = bus.wstrb; + assign bus.wid = (initiator_responder == INITIATOR) ? wid_o : 'bz; + assign wid_i = bus.wid; + assign bus.wuser = (initiator_responder == INITIATOR) ? wuser_o : 'bz; + assign wuser_i = bus.wuser; + assign bus.bwready = (initiator_responder == INITIATOR) ? bwready_o : 'bz; + assign bwready_i = bus.bwready; + assign bus.arvalid = (initiator_responder == INITIATOR) ? arvalid_o : 'bz; + assign arvalid_i = bus.arvalid; + assign bus.araddr = (initiator_responder == INITIATOR) ? araddr_o : 'bz; + assign araddr_i = bus.araddr; + assign bus.arsize = (initiator_responder == INITIATOR) ? arsize_o : 'bz; + assign arsize_i = bus.arsize; + assign bus.arburst = (initiator_responder == INITIATOR) ? arburst_o : 'bz; + assign arburst_i = bus.arburst; + assign bus.arcache = (initiator_responder == INITIATOR) ? arcache_o : 'bz; + assign arcache_i = bus.arcache; + assign bus.arprot = (initiator_responder == INITIATOR) ? arprot_o : 'bz; + assign arprot_i = bus.arprot; + assign bus.arid = (initiator_responder == INITIATOR) ? arid_o : 'bz; + assign arid_i = bus.arid; + assign bus.arlen = (initiator_responder == INITIATOR) ? arlen_o : 'bz; + assign arlen_i = bus.arlen; + assign bus.arlock = (initiator_responder == INITIATOR) ? arlock_o : 'bz; + assign arlock_i = bus.arlock; + assign bus.arqos = (initiator_responder == INITIATOR) ? arqos_o : 'bz; + assign arqos_i = bus.arqos; + assign bus.aregion = (initiator_responder == INITIATOR) ? aregion_o : 'bz; + assign aregion_i = bus.aregion; + assign bus.aruser = (initiator_responder == INITIATOR) ? aruser_o : 'bz; + assign aruser_i = bus.aruser; + assign bus.rready = (initiator_responder == INITIATOR) ? rready_o : 'bz; + assign rready_i = bus.rready; + + // Proxy handle to UVM driver + axi_m_pkg::axi_m_driver #( + .AW_WIDTH(AW_WIDTH), + .LEN(LEN), + .DATA_WIDTH(DATA_WIDTH), + .X(X) + ) proxy; + // pragma tbx oneway proxy.my_function_name_in_uvm_driver + + // **************************************************************************** + // **************************************************************************** + // Macros that define structs located in axi_m_macros.svh + // **************************************************************************** + // Struct for passing configuration data from axi_m_driver to this BFM + // **************************************************************************** + `axi_m_CONFIGURATION_STRUCT + // **************************************************************************** + // Structs for INITIATOR and RESPONDER data flow + //******************************************************************* + // Initiator macro used by axi_m_driver and axi_m_driver_bfm + // to communicate initiator driven data to axi_m_driver_bfm. + `axi_m_INITIATOR_STRUCT + axi_m_initiator_s initiator_struct; + // Responder macro used by axi_m_driver and axi_m_driver_bfm + // to communicate Responder driven data to axi_m_driver_bfm. + `axi_m_RESPONDER_STRUCT + axi_m_responder_s responder_struct; + + // **************************************************************************** +// pragma uvmf custom reset_condition_and_response begin + // Always block used to return signals to reset value upon assertion of reset + always @( negedge rst_i ) + begin + // RESPONDER mode output signals + awready_o <= 'bz; + wready_o <= 'bz; + bwvalid_o <= 'bz; + bresp_o <= 'bz; + bid_o <= 'bz; + buser_o <= 'bz; + aready_o <= 'bz; + rvalid_o <= 'bz; + rlast_o <= 'bz; + rdata_o <= 'bz; + rid_o <= 'bz; + ruser_o <= 'bz; + rresp_o <= 'bz; + // INITIATOR mode output signals + awvalid_o <= 'bz; + awaddr_o <= 'bz; + awsize_o <= 'bz; + awburst_o <= 'bz; + awcache_o <= 'bz; + awprot_o <= 'bz; + awid_o <= 'bz; + awlen_o <= 'bz; + awlock_o <= 'bz; + awqos_o <= 'bz; + awregion_o <= 'bz; + awuser_o <= 'bz; + wvalid_o <= 'bz; + wlast_o <= 'bz; + wdata_o <= 'bz; + wstrb_o <= 'bz; + wid_o <= 'bz; + wuser_o <= 'bz; + bwready_o <= 'bz; + arvalid_o <= 'bz; + araddr_o <= 'bz; + arsize_o <= 'bz; + arburst_o <= 'bz; + arcache_o <= 'bz; + arprot_o <= 'bz; + arid_o <= 'bz; + arlen_o <= 'bz; + arlock_o <= 'bz; + arqos_o <= 'bz; + aregion_o <= 'bz; + aruser_o <= 'bz; + rready_o <= 'bz; + // Bi-directional signals + + end +// pragma uvmf custom reset_condition_and_response end + + // pragma uvmf custom interface_item_additional begin + // pragma uvmf custom interface_item_additional end + + //****************************************************************** + // The configure() function is used to pass agent configuration + // variables to the driver BFM. It is called by the driver within + // the agent at the beginning of the simulation. It may be called + // during the simulation if agent configuration variables are updated + // and the driver BFM needs to be aware of the new configuration + // variables. + // + + function void configure(axi_m_configuration_s axi_m_configuration_arg); // pragma tbx xtf + initiator_responder = axi_m_configuration_arg.initiator_responder; + // pragma uvmf custom configure begin + // pragma uvmf custom configure end + endfunction + +// pragma uvmf custom initiate_and_get_response begin +// **************************************************************************** +// UVMF_CHANGE_ME +// This task is used by an initator. The task first initiates a transfer then +// waits for the responder to complete the transfer. + task initiate_and_get_response( + // This argument passes transaction variables used by an initiator + // to perform the initial part of a protocol transfer. The values + // come from a sequence item created in a sequence. + input axi_m_initiator_s axi_m_initiator_struct, + // This argument is used to send data received from the responder + // back to the sequence item. The sequence item is returned to the sequence. + output axi_m_responder_s axi_m_responder_struct + );// pragma tbx xtf + // + // Members within the axi_m_initiator_struct: + // bit awvalid ; + // bit awready ; + // bit [AW_WIDTH-1:0] awaddr ; + // bit awsize ; + // bit awburst ; + // bit awcache ; + // bit awprot ; + // bit [X-1:0] awid ; + // bit [LEN-1:0] awlen ; + // bit awlock ; + // bit awqos ; + // bit awregion ; + // bit [X-1:0] awuser ; + // bit wvalid ; + // bit wready ; + // bit wlast ; + // bit [DATA_WIDTH-1:0] wdata ; + // bit [DATA_WIDTH/8-1:0] wstrb ; + // bit [X-1:0] wid ; + // bit [X-1:0] wuser ; + // bit bwvalid ; + // bit bwready ; + // bit bresp ; + // bit [X-1:0] bid ; + // bit [X-1:0] buser ; + // bit arvalid ; + // bit aready ; + // bit [AW_WIDTH-1:0] araddr ; + // bit arsize ; + // bit arburst ; + // bit arcache ; + // bit arprot ; + // bit [X-1:0] arid ; + // bit [LEN-1:0] arlen ; + // bit arlock ; + // bit arqos ; + // bit aregion ; + // bit [X-1:0] aruser ; + // bit rvalid ; + // bit rready ; + // bit rlast ; + // bit [DATA_WIDTH-1:0] rdata ; + // bit [X-1:0] rid ; + // bit [X-1:0] ruser ; + // bit rresp ; + // Members within the axi_m_responder_struct: + // bit awvalid ; + // bit awready ; + // bit [AW_WIDTH-1:0] awaddr ; + // bit awsize ; + // bit awburst ; + // bit awcache ; + // bit awprot ; + // bit [X-1:0] awid ; + // bit [LEN-1:0] awlen ; + // bit awlock ; + // bit awqos ; + // bit awregion ; + // bit [X-1:0] awuser ; + // bit wvalid ; + // bit wready ; + // bit wlast ; + // bit [DATA_WIDTH-1:0] wdata ; + // bit [DATA_WIDTH/8-1:0] wstrb ; + // bit [X-1:0] wid ; + // bit [X-1:0] wuser ; + // bit bwvalid ; + // bit bwready ; + // bit bresp ; + // bit [X-1:0] bid ; + // bit [X-1:0] buser ; + // bit arvalid ; + // bit aready ; + // bit [AW_WIDTH-1:0] araddr ; + // bit arsize ; + // bit arburst ; + // bit arcache ; + // bit arprot ; + // bit [X-1:0] arid ; + // bit [LEN-1:0] arlen ; + // bit arlock ; + // bit arqos ; + // bit aregion ; + // bit [X-1:0] aruser ; + // bit rvalid ; + // bit rready ; + // bit rlast ; + // bit [DATA_WIDTH-1:0] rdata ; + // bit [X-1:0] rid ; + // bit [X-1:0] ruser ; + // bit rresp ; + initiator_struct = axi_m_initiator_struct; + // + // Reference code; + // How to wait for signal value + // while (control_signal == 1'b1) @(posedge axi_clk_i); + // + // How to assign a responder struct member, named xyz, from a signal. + // All available initiator input and inout signals listed. + // Initiator input signals + // axi_m_responder_struct.xyz = awready_i; // + // axi_m_responder_struct.xyz = wready_i; // + // axi_m_responder_struct.xyz = bwvalid_i; // + // axi_m_responder_struct.xyz = bresp_i; // [1:0] + // axi_m_responder_struct.xyz = bid_i; // [X-1:0] + // axi_m_responder_struct.xyz = buser_i; // [X-1:0] + // axi_m_responder_struct.xyz = aready_i; // + // axi_m_responder_struct.xyz = rvalid_i; // + // axi_m_responder_struct.xyz = rlast_i; // + // axi_m_responder_struct.xyz = rdata_i; // [DATA_WIDTH-1:0] + // axi_m_responder_struct.xyz = rid_i; // [X-1:0] + // axi_m_responder_struct.xyz = ruser_i; // [X-1:0] + // axi_m_responder_struct.xyz = rresp_i; // [1:0] + // Initiator inout signals + // How to assign a signal from an initiator struct member named xyz. + // All available initiator output and inout signals listed. + // Notice the _o. Those are storage variables that allow for procedural assignment. + // Initiator output signals + // awvalid_o <= axi_m_initiator_struct.xyz; // + // awaddr_o <= axi_m_initiator_struct.xyz; // [AW_WIDTH-1:0] + // awsize_o <= axi_m_initiator_struct.xyz; // [2:0] + // awburst_o <= axi_m_initiator_struct.xyz; // [1:0] + // awcache_o <= axi_m_initiator_struct.xyz; // [3:0] + // awprot_o <= axi_m_initiator_struct.xyz; // [2:0] + // awid_o <= axi_m_initiator_struct.xyz; // [X-1:0] + // awlen_o <= axi_m_initiator_struct.xyz; // [LEN-1:0] + // awlock_o <= axi_m_initiator_struct.xyz; // + // awqos_o <= axi_m_initiator_struct.xyz; // [3:0] + // awregion_o <= axi_m_initiator_struct.xyz; // [3:0] + // awuser_o <= axi_m_initiator_struct.xyz; // [X-1:0] + // wvalid_o <= axi_m_initiator_struct.xyz; // + // wlast_o <= axi_m_initiator_struct.xyz; // + // wdata_o <= axi_m_initiator_struct.xyz; // [DATA_WIDTH-1:0] + // wstrb_o <= axi_m_initiator_struct.xyz; // [DATA_WIDTH/8-1:0] + // wid_o <= axi_m_initiator_struct.xyz; // [X-1:0] + // wuser_o <= axi_m_initiator_struct.xyz; // [X-1:0] + // bwready_o <= axi_m_initiator_struct.xyz; // + // arvalid_o <= axi_m_initiator_struct.xyz; // + // araddr_o <= axi_m_initiator_struct.xyz; // [AW_WIDTH-1:0] + // arsize_o <= axi_m_initiator_struct.xyz; // [2:0] + // arburst_o <= axi_m_initiator_struct.xyz; // [1:0] + // arcache_o <= axi_m_initiator_struct.xyz; // [3:0] + // arprot_o <= axi_m_initiator_struct.xyz; // [2:0] + // arid_o <= axi_m_initiator_struct.xyz; // [X-1:0] + // arlen_o <= axi_m_initiator_struct.xyz; // [LEN-1:0] + // arlock_o <= axi_m_initiator_struct.xyz; // + // arqos_o <= axi_m_initiator_struct.xyz; // [3:0] + // aregion_o <= axi_m_initiator_struct.xyz; // [3:0] + // aruser_o <= axi_m_initiator_struct.xyz; // [X-1:0] + // rready_o <= axi_m_initiator_struct.xyz; // + // Initiator inout signals + // Initiate a transfer using the data received. + @(posedge axi_clk_i); + @(posedge axi_clk_i); + // Wait for the responder to complete the transfer then place the responder data into + // axi_m_responder_struct. + @(posedge axi_clk_i); + @(posedge axi_clk_i); + responder_struct = axi_m_responder_struct; + endtask +// pragma uvmf custom initiate_and_get_response end + +// pragma uvmf custom respond_and_wait_for_next_transfer begin +// **************************************************************************** +// The first_transfer variable is used to prevent completing a transfer in the +// first call to this task. For the first call to this task, there is not +// current transfer to complete. +bit first_transfer=1; + +// UVMF_CHANGE_ME +// This task is used by a responder. The task first completes the current +// transfer in progress then waits for the initiator to start the next transfer. + task respond_and_wait_for_next_transfer( + // This argument is used to send data received from the initiator + // back to the sequence item. The sequence determines how to respond. + output axi_m_initiator_s axi_m_initiator_struct, + // This argument passes transaction variables used by a responder + // to complete a protocol transfer. The values come from a sequence item. + input axi_m_responder_s axi_m_responder_struct + );// pragma tbx xtf + // Variables within the axi_m_initiator_struct: + // bit awvalid ; + // bit awready ; + // bit [AW_WIDTH-1:0] awaddr ; + // bit awsize ; + // bit awburst ; + // bit awcache ; + // bit awprot ; + // bit [X-1:0] awid ; + // bit [LEN-1:0] awlen ; + // bit awlock ; + // bit awqos ; + // bit awregion ; + // bit [X-1:0] awuser ; + // bit wvalid ; + // bit wready ; + // bit wlast ; + // bit [DATA_WIDTH-1:0] wdata ; + // bit [DATA_WIDTH/8-1:0] wstrb ; + // bit [X-1:0] wid ; + // bit [X-1:0] wuser ; + // bit bwvalid ; + // bit bwready ; + // bit bresp ; + // bit [X-1:0] bid ; + // bit [X-1:0] buser ; + // bit arvalid ; + // bit aready ; + // bit [AW_WIDTH-1:0] araddr ; + // bit arsize ; + // bit arburst ; + // bit arcache ; + // bit arprot ; + // bit [X-1:0] arid ; + // bit [LEN-1:0] arlen ; + // bit arlock ; + // bit arqos ; + // bit aregion ; + // bit [X-1:0] aruser ; + // bit rvalid ; + // bit rready ; + // bit rlast ; + // bit [DATA_WIDTH-1:0] rdata ; + // bit [X-1:0] rid ; + // bit [X-1:0] ruser ; + // bit rresp ; + // Variables within the axi_m_responder_struct: + // bit awvalid ; + // bit awready ; + // bit [AW_WIDTH-1:0] awaddr ; + // bit awsize ; + // bit awburst ; + // bit awcache ; + // bit awprot ; + // bit [X-1:0] awid ; + // bit [LEN-1:0] awlen ; + // bit awlock ; + // bit awqos ; + // bit awregion ; + // bit [X-1:0] awuser ; + // bit wvalid ; + // bit wready ; + // bit wlast ; + // bit [DATA_WIDTH-1:0] wdata ; + // bit [DATA_WIDTH/8-1:0] wstrb ; + // bit [X-1:0] wid ; + // bit [X-1:0] wuser ; + // bit bwvalid ; + // bit bwready ; + // bit bresp ; + // bit [X-1:0] bid ; + // bit [X-1:0] buser ; + // bit arvalid ; + // bit aready ; + // bit [AW_WIDTH-1:0] araddr ; + // bit arsize ; + // bit arburst ; + // bit arcache ; + // bit arprot ; + // bit [X-1:0] arid ; + // bit [LEN-1:0] arlen ; + // bit arlock ; + // bit arqos ; + // bit aregion ; + // bit [X-1:0] aruser ; + // bit rvalid ; + // bit rready ; + // bit rlast ; + // bit [DATA_WIDTH-1:0] rdata ; + // bit [X-1:0] rid ; + // bit [X-1:0] ruser ; + // bit rresp ; + // Reference code; + // How to wait for signal value + // while (control_signal == 1'b1) @(posedge axi_clk_i); + // + // How to assign a responder struct member, named xyz, from a signal. + // All available responder input and inout signals listed. + // Responder input signals + // axi_m_responder_struct.xyz = awvalid_i; // + // axi_m_responder_struct.xyz = awaddr_i; // [AW_WIDTH-1:0] + // axi_m_responder_struct.xyz = awsize_i; // [2:0] + // axi_m_responder_struct.xyz = awburst_i; // [1:0] + // axi_m_responder_struct.xyz = awcache_i; // [3:0] + // axi_m_responder_struct.xyz = awprot_i; // [2:0] + // axi_m_responder_struct.xyz = awid_i; // [X-1:0] + // axi_m_responder_struct.xyz = awlen_i; // [LEN-1:0] + // axi_m_responder_struct.xyz = awlock_i; // + // axi_m_responder_struct.xyz = awqos_i; // [3:0] + // axi_m_responder_struct.xyz = awregion_i; // [3:0] + // axi_m_responder_struct.xyz = awuser_i; // [X-1:0] + // axi_m_responder_struct.xyz = wvalid_i; // + // axi_m_responder_struct.xyz = wlast_i; // + // axi_m_responder_struct.xyz = wdata_i; // [DATA_WIDTH-1:0] + // axi_m_responder_struct.xyz = wstrb_i; // [DATA_WIDTH/8-1:0] + // axi_m_responder_struct.xyz = wid_i; // [X-1:0] + // axi_m_responder_struct.xyz = wuser_i; // [X-1:0] + // axi_m_responder_struct.xyz = bwready_i; // + // axi_m_responder_struct.xyz = arvalid_i; // + // axi_m_responder_struct.xyz = araddr_i; // [AW_WIDTH-1:0] + // axi_m_responder_struct.xyz = arsize_i; // [2:0] + // axi_m_responder_struct.xyz = arburst_i; // [1:0] + // axi_m_responder_struct.xyz = arcache_i; // [3:0] + // axi_m_responder_struct.xyz = arprot_i; // [2:0] + // axi_m_responder_struct.xyz = arid_i; // [X-1:0] + // axi_m_responder_struct.xyz = arlen_i; // [LEN-1:0] + // axi_m_responder_struct.xyz = arlock_i; // + // axi_m_responder_struct.xyz = arqos_i; // [3:0] + // axi_m_responder_struct.xyz = aregion_i; // [3:0] + // axi_m_responder_struct.xyz = aruser_i; // [X-1:0] + // axi_m_responder_struct.xyz = rready_i; // + // Responder inout signals + // How to assign a signal, named xyz, from an initiator struct member. + // All available responder output and inout signals listed. + // Notice the _o. Those are storage variables that allow for procedural assignment. + // Responder output signals + // awready_o <= axi_m_initiator_struct.xyz; // + // wready_o <= axi_m_initiator_struct.xyz; // + // bwvalid_o <= axi_m_initiator_struct.xyz; // + // bresp_o <= axi_m_initiator_struct.xyz; // [1:0] + // bid_o <= axi_m_initiator_struct.xyz; // [X-1:0] + // buser_o <= axi_m_initiator_struct.xyz; // [X-1:0] + // aready_o <= axi_m_initiator_struct.xyz; // + // rvalid_o <= axi_m_initiator_struct.xyz; // + // rlast_o <= axi_m_initiator_struct.xyz; // + // rdata_o <= axi_m_initiator_struct.xyz; // [DATA_WIDTH-1:0] + // rid_o <= axi_m_initiator_struct.xyz; // [X-1:0] + // ruser_o <= axi_m_initiator_struct.xyz; // [X-1:0] + // rresp_o <= axi_m_initiator_struct.xyz; // [1:0] + // Responder inout signals + + @(posedge axi_clk_i); + if (!first_transfer) begin + // Perform transfer response here. + // Reply using data recieved in the axi_m_responder_struct. + @(posedge axi_clk_i); + // Reply using data recieved in the transaction handle. + @(posedge axi_clk_i); + end + // Wait for next transfer then gather info from intiator about the transfer. + // Place the data into the axi_m_initiator_struct. + @(posedge axi_clk_i); + @(posedge axi_clk_i); + first_transfer = 0; + endtask +// pragma uvmf custom respond_and_wait_for_next_transfer end + + +endinterface + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/axi_m_pkg/src/axi_m_if.sv b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/axi_m_pkg/src/axi_m_if.sv new file mode 100644 index 00000000..90295099 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/axi_m_pkg/src/axi_m_if.sv @@ -0,0 +1,289 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This interface contains the axi_m interface signals. +// It is instantiated once per axi_m bus. Bus Functional Models, +// BFM's named axi_m_driver_bfm, are used to drive signals on the bus. +// BFM's named axi_m_monitor_bfm are used to monitor signals on the +// bus. This interface signal bundle is passed in the port list of +// the BFM in order to give the BFM access to the signals in this +// interface. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// This template can be used to connect a DUT to these signals +// +// .dut_signal_port(axi_m_bus.awvalid), // Agent output +// .dut_signal_port(axi_m_bus.awready), // Agent input +// .dut_signal_port(axi_m_bus.awaddr), // Agent output +// .dut_signal_port(axi_m_bus.awsize), // Agent output +// .dut_signal_port(axi_m_bus.awburst), // Agent output +// .dut_signal_port(axi_m_bus.awcache), // Agent output +// .dut_signal_port(axi_m_bus.awprot), // Agent output +// .dut_signal_port(axi_m_bus.awid), // Agent output +// .dut_signal_port(axi_m_bus.awlen), // Agent output +// .dut_signal_port(axi_m_bus.awlock), // Agent output +// .dut_signal_port(axi_m_bus.awqos), // Agent output +// .dut_signal_port(axi_m_bus.awregion), // Agent output +// .dut_signal_port(axi_m_bus.awuser), // Agent output +// .dut_signal_port(axi_m_bus.wvalid), // Agent output +// .dut_signal_port(axi_m_bus.wready), // Agent input +// .dut_signal_port(axi_m_bus.wlast), // Agent output +// .dut_signal_port(axi_m_bus.wdata), // Agent output +// .dut_signal_port(axi_m_bus.wstrb), // Agent output +// .dut_signal_port(axi_m_bus.wid), // Agent output +// .dut_signal_port(axi_m_bus.wuser), // Agent output +// .dut_signal_port(axi_m_bus.bwvalid), // Agent input +// .dut_signal_port(axi_m_bus.bwready), // Agent output +// .dut_signal_port(axi_m_bus.bresp), // Agent input +// .dut_signal_port(axi_m_bus.bid), // Agent input +// .dut_signal_port(axi_m_bus.buser), // Agent input +// .dut_signal_port(axi_m_bus.arvalid), // Agent output +// .dut_signal_port(axi_m_bus.aready), // Agent input +// .dut_signal_port(axi_m_bus.araddr), // Agent output +// .dut_signal_port(axi_m_bus.arsize), // Agent output +// .dut_signal_port(axi_m_bus.arburst), // Agent output +// .dut_signal_port(axi_m_bus.arcache), // Agent output +// .dut_signal_port(axi_m_bus.arprot), // Agent output +// .dut_signal_port(axi_m_bus.arid), // Agent output +// .dut_signal_port(axi_m_bus.arlen), // Agent output +// .dut_signal_port(axi_m_bus.arlock), // Agent output +// .dut_signal_port(axi_m_bus.arqos), // Agent output +// .dut_signal_port(axi_m_bus.aregion), // Agent output +// .dut_signal_port(axi_m_bus.aruser), // Agent output +// .dut_signal_port(axi_m_bus.rvalid), // Agent input +// .dut_signal_port(axi_m_bus.rready), // Agent output +// .dut_signal_port(axi_m_bus.rlast), // Agent input +// .dut_signal_port(axi_m_bus.rdata), // Agent input +// .dut_signal_port(axi_m_bus.rid), // Agent input +// .dut_signal_port(axi_m_bus.ruser), // Agent input +// .dut_signal_port(axi_m_bus.rresp), // Agent input + +import uvmf_base_pkg_hdl::*; +import axi_m_pkg_hdl::*; + +interface axi_m_if #( + int AW_WIDTH = 32, + int LEN = 8, + int DATA_WIDTH = 32, + int X = 16 + ) + + ( + input logic axi_clk, + input logic rst, + output logic awvalid, + input logic awready, + output logic [AW_WIDTH-1:0] awaddr, + output logic [2:0] awsize, + output logic [1:0] awburst, + output logic [3:0] awcache, + output logic [2:0] awprot, + output logic [X-1:0] awid, + output logic [LEN-1:0] awlen, + output logic awlock, + output logic [3:0] awqos, + output logic [3:0] awregion, + output logic [X-1:0] awuser, + output logic wvalid, + input logic wready, + output logic wlast, + output logic [DATA_WIDTH-1:0] wdata, + output logic [DATA_WIDTH/8-1:0] wstrb, + output logic [X-1:0] wid, + output logic [X-1:0] wuser, + input logic bwvalid, + output logic bwready, + input logic [1:0] bresp, + input logic [X-1:0] bid, + input logic [X-1:0] buser, + output logic arvalid, + input logic aready, + output logic [AW_WIDTH-1:0] araddr, + output logic [2:0] arsize, + output logic [1:0] arburst, + output logic [3:0] arcache, + output logic [2:0] arprot, + output logic [X-1:0] arid, + output logic [LEN-1:0] arlen, + output logic arlock, + output logic [3:0] arqos, + output logic [3:0] aregion, + output logic [X-1:0] aruser, + input logic rvalid, + output logic rready, + input logic rlast, + input logic [DATA_WIDTH-1:0] rdata, + input logic [X-1:0] rid, + input logic [X-1:0] ruser, + input logic [1:0] rresp + ); + +modport monitor_port + ( + input axi_clk, + input rst, + input awvalid, + input awready, + input awaddr, + input awsize, + input awburst, + input awcache, + input awprot, + input awid, + input awlen, + input awlock, + input awqos, + input awregion, + input awuser, + input wvalid, + input wready, + input wlast, + input wdata, + input wstrb, + input wid, + input wuser, + input bwvalid, + input bwready, + input bresp, + input bid, + input buser, + input arvalid, + input aready, + input araddr, + input arsize, + input arburst, + input arcache, + input arprot, + input arid, + input arlen, + input arlock, + input arqos, + input aregion, + input aruser, + input rvalid, + input rready, + input rlast, + input rdata, + input rid, + input ruser, + input rresp + ); + +modport initiator_port + ( + input axi_clk, + input rst, + output awvalid, + input awready, + output awaddr, + output awsize, + output awburst, + output awcache, + output awprot, + output awid, + output awlen, + output awlock, + output awqos, + output awregion, + output awuser, + output wvalid, + input wready, + output wlast, + output wdata, + output wstrb, + output wid, + output wuser, + input bwvalid, + output bwready, + input bresp, + input bid, + input buser, + output arvalid, + input aready, + output araddr, + output arsize, + output arburst, + output arcache, + output arprot, + output arid, + output arlen, + output arlock, + output arqos, + output aregion, + output aruser, + input rvalid, + output rready, + input rlast, + input rdata, + input rid, + input ruser, + input rresp + ); + +modport responder_port + ( + input axi_clk, + input rst, + input awvalid, + output awready, + input awaddr, + input awsize, + input awburst, + input awcache, + input awprot, + input awid, + input awlen, + input awlock, + input awqos, + input awregion, + input awuser, + input wvalid, + output wready, + input wlast, + input wdata, + input wstrb, + input wid, + input wuser, + output bwvalid, + input bwready, + output bresp, + output bid, + output buser, + input arvalid, + output aready, + input araddr, + input arsize, + input arburst, + input arcache, + input arprot, + input arid, + input arlen, + input arlock, + input arqos, + input aregion, + input aruser, + output rvalid, + input rready, + output rlast, + output rdata, + output rid, + output ruser, + output rresp + ); + + +// pragma uvmf custom interface_item_additional begin +// pragma uvmf custom interface_item_additional end + +endinterface + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/axi_m_pkg/src/axi_m_infact_coverage_strategy.csv b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/axi_m_pkg/src/axi_m_infact_coverage_strategy.csv new file mode 100644 index 00000000..1c218e14 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/axi_m_pkg/src/axi_m_infact_coverage_strategy.csv @@ -0,0 +1,6 @@ +Global +auto_bin_max, 64 + +Name,Type,Include +rand_fields,coverpoint,=rand *.** + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/axi_m_pkg/src/axi_m_macros.svh b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/axi_m_pkg/src/axi_m_macros.svh new file mode 100644 index 00000000..f04eaa78 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/axi_m_pkg/src/axi_m_macros.svh @@ -0,0 +1,517 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This file contains macros used with the axi_m package. +// These macros include packed struct definitions. These structs are +// used to pass data between classes, hvl, and BFM's, hdl. Use of +// structs are more efficient and simpler to modify. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// + +// **************************************************************************** +// When changing the contents of this struct, be sure to update the to_struct +// and from_struct methods defined in the macros below that are used in +// the axi_m_configuration class. +// + `define axi_m_CONFIGURATION_STRUCT \ +typedef struct packed { \ + uvmf_active_passive_t active_passive; \ + uvmf_initiator_responder_t initiator_responder; \ + } axi_m_configuration_s; + + `define axi_m_CONFIGURATION_TO_STRUCT_FUNCTION \ + virtual function axi_m_configuration_s to_struct();\ + axi_m_configuration_struct = \ + {\ + this.active_passive,\ + this.initiator_responder\ + };\ + return ( axi_m_configuration_struct );\ + endfunction + + `define axi_m_CONFIGURATION_FROM_STRUCT_FUNCTION \ + virtual function void from_struct(axi_m_configuration_s axi_m_configuration_struct);\ + {\ + this.active_passive,\ + this.initiator_responder \ + } = axi_m_configuration_struct;\ + endfunction + +// **************************************************************************** +// When changing the contents of this struct, be sure to update the to_monitor_struct +// and from_monitor_struct methods of the axi_m_transaction class. +// + `define axi_m_MONITOR_STRUCT typedef struct packed { \ + bit awvalid ; \ + bit awready ; \ + bit [AW_WIDTH-1:0] awaddr ; \ + bit awsize ; \ + bit awburst ; \ + bit awcache ; \ + bit awprot ; \ + bit [X-1:0] awid ; \ + bit [LEN-1:0] awlen ; \ + bit awlock ; \ + bit awqos ; \ + bit awregion ; \ + bit [X-1:0] awuser ; \ + bit wvalid ; \ + bit wready ; \ + bit wlast ; \ + bit [DATA_WIDTH-1:0] wdata ; \ + bit [DATA_WIDTH/8-1:0] wstrb ; \ + bit [X-1:0] wid ; \ + bit [X-1:0] wuser ; \ + bit bwvalid ; \ + bit bwready ; \ + bit bresp ; \ + bit [X-1:0] bid ; \ + bit [X-1:0] buser ; \ + bit arvalid ; \ + bit aready ; \ + bit [AW_WIDTH-1:0] araddr ; \ + bit arsize ; \ + bit arburst ; \ + bit arcache ; \ + bit arprot ; \ + bit [X-1:0] arid ; \ + bit [LEN-1:0] arlen ; \ + bit arlock ; \ + bit arqos ; \ + bit aregion ; \ + bit [X-1:0] aruser ; \ + bit rvalid ; \ + bit rready ; \ + bit rlast ; \ + bit [DATA_WIDTH-1:0] rdata ; \ + bit [X-1:0] rid ; \ + bit [X-1:0] ruser ; \ + bit rresp ; \ + } axi_m_monitor_s; + + `define axi_m_TO_MONITOR_STRUCT_FUNCTION \ + virtual function axi_m_monitor_s to_monitor_struct();\ + axi_m_monitor_struct = \ + { \ + this.awvalid , \ + this.awready , \ + this.awaddr , \ + this.awsize , \ + this.awburst , \ + this.awcache , \ + this.awprot , \ + this.awid , \ + this.awlen , \ + this.awlock , \ + this.awqos , \ + this.awregion , \ + this.awuser , \ + this.wvalid , \ + this.wready , \ + this.wlast , \ + this.wdata , \ + this.wstrb , \ + this.wid , \ + this.wuser , \ + this.bwvalid , \ + this.bwready , \ + this.bresp , \ + this.bid , \ + this.buser , \ + this.arvalid , \ + this.aready , \ + this.araddr , \ + this.arsize , \ + this.arburst , \ + this.arcache , \ + this.arprot , \ + this.arid , \ + this.arlen , \ + this.arlock , \ + this.arqos , \ + this.aregion , \ + this.aruser , \ + this.rvalid , \ + this.rready , \ + this.rlast , \ + this.rdata , \ + this.rid , \ + this.ruser , \ + this.rresp \ + };\ + return ( axi_m_monitor_struct);\ + endfunction\ + + `define axi_m_FROM_MONITOR_STRUCT_FUNCTION \ + virtual function void from_monitor_struct(axi_m_monitor_s axi_m_monitor_struct);\ + {\ + this.awvalid , \ + this.awready , \ + this.awaddr , \ + this.awsize , \ + this.awburst , \ + this.awcache , \ + this.awprot , \ + this.awid , \ + this.awlen , \ + this.awlock , \ + this.awqos , \ + this.awregion , \ + this.awuser , \ + this.wvalid , \ + this.wready , \ + this.wlast , \ + this.wdata , \ + this.wstrb , \ + this.wid , \ + this.wuser , \ + this.bwvalid , \ + this.bwready , \ + this.bresp , \ + this.bid , \ + this.buser , \ + this.arvalid , \ + this.aready , \ + this.araddr , \ + this.arsize , \ + this.arburst , \ + this.arcache , \ + this.arprot , \ + this.arid , \ + this.arlen , \ + this.arlock , \ + this.arqos , \ + this.aregion , \ + this.aruser , \ + this.rvalid , \ + this.rready , \ + this.rlast , \ + this.rdata , \ + this.rid , \ + this.ruser , \ + this.rresp \ + } = axi_m_monitor_struct;\ + endfunction + +// **************************************************************************** +// When changing the contents of this struct, be sure to update the to_initiator_struct +// and from_initiator_struct methods of the axi_m_transaction class. +// Also update the comments in the driver BFM. +// + `define axi_m_INITIATOR_STRUCT typedef struct packed { \ + bit awvalid ; \ + bit awready ; \ + bit [AW_WIDTH-1:0] awaddr ; \ + bit awsize ; \ + bit awburst ; \ + bit awcache ; \ + bit awprot ; \ + bit [X-1:0] awid ; \ + bit [LEN-1:0] awlen ; \ + bit awlock ; \ + bit awqos ; \ + bit awregion ; \ + bit [X-1:0] awuser ; \ + bit wvalid ; \ + bit wready ; \ + bit wlast ; \ + bit [DATA_WIDTH-1:0] wdata ; \ + bit [DATA_WIDTH/8-1:0] wstrb ; \ + bit [X-1:0] wid ; \ + bit [X-1:0] wuser ; \ + bit bwvalid ; \ + bit bwready ; \ + bit bresp ; \ + bit [X-1:0] bid ; \ + bit [X-1:0] buser ; \ + bit arvalid ; \ + bit aready ; \ + bit [AW_WIDTH-1:0] araddr ; \ + bit arsize ; \ + bit arburst ; \ + bit arcache ; \ + bit arprot ; \ + bit [X-1:0] arid ; \ + bit [LEN-1:0] arlen ; \ + bit arlock ; \ + bit arqos ; \ + bit aregion ; \ + bit [X-1:0] aruser ; \ + bit rvalid ; \ + bit rready ; \ + bit rlast ; \ + bit [DATA_WIDTH-1:0] rdata ; \ + bit [X-1:0] rid ; \ + bit [X-1:0] ruser ; \ + bit rresp ; \ + } axi_m_initiator_s; + + `define axi_m_TO_INITIATOR_STRUCT_FUNCTION \ + virtual function axi_m_initiator_s to_initiator_struct();\ + axi_m_initiator_struct = \ + {\ + this.awvalid , \ + this.awready , \ + this.awaddr , \ + this.awsize , \ + this.awburst , \ + this.awcache , \ + this.awprot , \ + this.awid , \ + this.awlen , \ + this.awlock , \ + this.awqos , \ + this.awregion , \ + this.awuser , \ + this.wvalid , \ + this.wready , \ + this.wlast , \ + this.wdata , \ + this.wstrb , \ + this.wid , \ + this.wuser , \ + this.bwvalid , \ + this.bwready , \ + this.bresp , \ + this.bid , \ + this.buser , \ + this.arvalid , \ + this.aready , \ + this.araddr , \ + this.arsize , \ + this.arburst , \ + this.arcache , \ + this.arprot , \ + this.arid , \ + this.arlen , \ + this.arlock , \ + this.arqos , \ + this.aregion , \ + this.aruser , \ + this.rvalid , \ + this.rready , \ + this.rlast , \ + this.rdata , \ + this.rid , \ + this.ruser , \ + this.rresp \ + };\ + return ( axi_m_initiator_struct);\ + endfunction + + `define axi_m_FROM_INITIATOR_STRUCT_FUNCTION \ + virtual function void from_initiator_struct(axi_m_initiator_s axi_m_initiator_struct);\ + {\ + this.awvalid , \ + this.awready , \ + this.awaddr , \ + this.awsize , \ + this.awburst , \ + this.awcache , \ + this.awprot , \ + this.awid , \ + this.awlen , \ + this.awlock , \ + this.awqos , \ + this.awregion , \ + this.awuser , \ + this.wvalid , \ + this.wready , \ + this.wlast , \ + this.wdata , \ + this.wstrb , \ + this.wid , \ + this.wuser , \ + this.bwvalid , \ + this.bwready , \ + this.bresp , \ + this.bid , \ + this.buser , \ + this.arvalid , \ + this.aready , \ + this.araddr , \ + this.arsize , \ + this.arburst , \ + this.arcache , \ + this.arprot , \ + this.arid , \ + this.arlen , \ + this.arlock , \ + this.arqos , \ + this.aregion , \ + this.aruser , \ + this.rvalid , \ + this.rready , \ + this.rlast , \ + this.rdata , \ + this.rid , \ + this.ruser , \ + this.rresp \ + } = axi_m_initiator_struct;\ + endfunction + +// **************************************************************************** +// When changing the contents of this struct, be sure to update the to_responder_struct +// and from_responder_struct methods of the axi_m_transaction class. +// Also update the comments in the driver BFM. +// + `define axi_m_RESPONDER_STRUCT typedef struct packed { \ + bit awvalid ; \ + bit awready ; \ + bit [AW_WIDTH-1:0] awaddr ; \ + bit awsize ; \ + bit awburst ; \ + bit awcache ; \ + bit awprot ; \ + bit [X-1:0] awid ; \ + bit [LEN-1:0] awlen ; \ + bit awlock ; \ + bit awqos ; \ + bit awregion ; \ + bit [X-1:0] awuser ; \ + bit wvalid ; \ + bit wready ; \ + bit wlast ; \ + bit [DATA_WIDTH-1:0] wdata ; \ + bit [DATA_WIDTH/8-1:0] wstrb ; \ + bit [X-1:0] wid ; \ + bit [X-1:0] wuser ; \ + bit bwvalid ; \ + bit bwready ; \ + bit bresp ; \ + bit [X-1:0] bid ; \ + bit [X-1:0] buser ; \ + bit arvalid ; \ + bit aready ; \ + bit [AW_WIDTH-1:0] araddr ; \ + bit arsize ; \ + bit arburst ; \ + bit arcache ; \ + bit arprot ; \ + bit [X-1:0] arid ; \ + bit [LEN-1:0] arlen ; \ + bit arlock ; \ + bit arqos ; \ + bit aregion ; \ + bit [X-1:0] aruser ; \ + bit rvalid ; \ + bit rready ; \ + bit rlast ; \ + bit [DATA_WIDTH-1:0] rdata ; \ + bit [X-1:0] rid ; \ + bit [X-1:0] ruser ; \ + bit rresp ; \ + } axi_m_responder_s; + + `define axi_m_TO_RESPONDER_STRUCT_FUNCTION \ + virtual function axi_m_responder_s to_responder_struct();\ + axi_m_responder_struct = \ + {\ + this.awvalid , \ + this.awready , \ + this.awaddr , \ + this.awsize , \ + this.awburst , \ + this.awcache , \ + this.awprot , \ + this.awid , \ + this.awlen , \ + this.awlock , \ + this.awqos , \ + this.awregion , \ + this.awuser , \ + this.wvalid , \ + this.wready , \ + this.wlast , \ + this.wdata , \ + this.wstrb , \ + this.wid , \ + this.wuser , \ + this.bwvalid , \ + this.bwready , \ + this.bresp , \ + this.bid , \ + this.buser , \ + this.arvalid , \ + this.aready , \ + this.araddr , \ + this.arsize , \ + this.arburst , \ + this.arcache , \ + this.arprot , \ + this.arid , \ + this.arlen , \ + this.arlock , \ + this.arqos , \ + this.aregion , \ + this.aruser , \ + this.rvalid , \ + this.rready , \ + this.rlast , \ + this.rdata , \ + this.rid , \ + this.ruser , \ + this.rresp \ + };\ + return ( axi_m_responder_struct);\ + endfunction + + `define axi_m_FROM_RESPONDER_STRUCT_FUNCTION \ + virtual function void from_responder_struct(axi_m_responder_s axi_m_responder_struct);\ + {\ + this.awvalid , \ + this.awready , \ + this.awaddr , \ + this.awsize , \ + this.awburst , \ + this.awcache , \ + this.awprot , \ + this.awid , \ + this.awlen , \ + this.awlock , \ + this.awqos , \ + this.awregion , \ + this.awuser , \ + this.wvalid , \ + this.wready , \ + this.wlast , \ + this.wdata , \ + this.wstrb , \ + this.wid , \ + this.wuser , \ + this.bwvalid , \ + this.bwready , \ + this.bresp , \ + this.bid , \ + this.buser , \ + this.arvalid , \ + this.aready , \ + this.araddr , \ + this.arsize , \ + this.arburst , \ + this.arcache , \ + this.arprot , \ + this.arid , \ + this.arlen , \ + this.arlock , \ + this.arqos , \ + this.aregion , \ + this.aruser , \ + this.rvalid , \ + this.rready , \ + this.rlast , \ + this.rdata , \ + this.rid , \ + this.ruser , \ + this.rresp \ + } = axi_m_responder_struct;\ + endfunction +// pragma uvmf custom additional begin +// pragma uvmf custom additional end diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/axi_m_pkg/src/axi_m_monitor.svh b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/axi_m_pkg/src/axi_m_monitor.svh new file mode 100644 index 00000000..c5f4c0df --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/axi_m_pkg/src/axi_m_monitor.svh @@ -0,0 +1,112 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This class receives axi_m transactions observed by the +// axi_m monitor BFM and broadcasts them through the analysis port +// on the agent. It accesses the monitor BFM through the monitor +// task. This UVM component captures transactions +// for viewing in the waveform viewer if the +// enable_transaction_viewing flag is set in the configuration. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class axi_m_monitor #( + int AW_WIDTH = 32, + int LEN = 8, + int DATA_WIDTH = 32, + int X = 16 + ) extends uvmf_monitor_base #( + .CONFIG_T(axi_m_configuration #( + .AW_WIDTH(AW_WIDTH), + .LEN(LEN), + .DATA_WIDTH(DATA_WIDTH), + .X(X) + )), + .BFM_BIND_T(virtual axi_m_monitor_bfm #( + .AW_WIDTH(AW_WIDTH), + .LEN(LEN), + .DATA_WIDTH(DATA_WIDTH), + .X(X) + )), + .TRANS_T(axi_m_transaction #( + .AW_WIDTH(AW_WIDTH), + .LEN(LEN), + .DATA_WIDTH(DATA_WIDTH), + .X(X) + ))); + + `uvm_component_param_utils( axi_m_monitor #( + AW_WIDTH, + LEN, + DATA_WIDTH, + X + )) + +// Structure used to pass data from monitor BFM to monitor class in agent. +// Use to_monitor_struct function to pack transaction variables into structure. +// Use from_monitor_struct function to unpack transaction variables from structure. +`axi_m_MONITOR_STRUCT + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + +// **************************************************************************** +// This function is the standard SystemVerilog constructor. +// + function new( string name = "", uvm_component parent = null ); + super.new( name, parent ); + endfunction + +// **************************************************************************** +// This function sends configuration object variables to the monitor BFM +// using the configuration struct. +// + virtual function void configure(input CONFIG_T cfg); + bfm.configure( cfg.to_struct() ); + + endfunction + +// **************************************************************************** +// This function places a handle to this class in the proxy variable in the +// monitor BFM. This allows the monitor BFM to call the notify_transaction +// function within this class. +// + virtual function void set_bfm_proxy_handle(); + bfm.proxy = this; endfunction + +// *************************************************************************** + virtual task run_phase(uvm_phase phase); + // Start monitor BFM thread and don't call super.run() in order to + // override the default monitor proxy 'pull' behavior with the more + // emulation-friendly BFM 'push' approach using the notify_transaction + // function below + bfm.start_monitoring(); + endtask + +// ************************************************************************** + +// This function is called by the monitor BFM. It receives data observed by the +// monitor BFM. Data is passed using the axi_m_monitor_struct. + virtual function void notify_transaction(input axi_m_monitor_s axi_m_monitor_struct); + + + trans = new("trans"); + trans.from_monitor_struct(axi_m_monitor_struct); + trans.start_time = time_stamp; + trans.end_time = $time; + time_stamp = trans.end_time; + + analyze(trans); + endfunction + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/axi_m_pkg/src/axi_m_monitor_bfm.sv b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/axi_m_pkg/src/axi_m_monitor_bfm.sv new file mode 100644 index 00000000..649ee7d6 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/axi_m_pkg/src/axi_m_monitor_bfm.sv @@ -0,0 +1,360 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This interface performs the axi_m signal monitoring. +// It is accessed by the uvm axi_m monitor through a virtual +// interface handle in the axi_m configuration. It monitors the +// signals passed in through the port connection named bus of +// type axi_m_if. +// +// Input signals from the axi_m_if are assigned to an internal input +// signal with a _i suffix. The _i signal should be used for sampling. +// +// The input signal connections are as follows: +// bus.signal -> signal_i +// +// Interface functions and tasks used by UVM components: +// monitor(inout TRANS_T txn); +// This task receives the transaction, txn, from the +// UVM monitor and then populates variables in txn +// from values observed on bus activity. This task +// blocks until an operation on the axi_m bus is complete. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +import uvmf_base_pkg_hdl::*; +import axi_m_pkg_hdl::*; +`include "src/axi_m_macros.svh" + + +interface axi_m_monitor_bfm #( + int AW_WIDTH = 32, + int LEN = 8, + int DATA_WIDTH = 32, + int X = 16 + ) + ( axi_m_if bus ); + // The pragma below and additional ones in-lined further down are for running this BFM on Veloce + // pragma attribute axi_m_monitor_bfm partition_interface_xif + +`ifndef XRTL +// This code is to aid in debugging parameter mismatches between the BFM and its corresponding agent. +// Enable this debug by setting UVM_VERBOSITY to UVM_DEBUG +// Setting UVM_VERBOSITY to UVM_DEBUG causes all BFM's and all agents to display their parameter settings. +// All of the messages from this feature have a UVM messaging id value of "CFG" +// The transcript or run.log can be parsed to ensure BFM parameter settings match its corresponding agents parameter settings. +import uvm_pkg::*; +`include "uvm_macros.svh" +initial begin : bfm_vs_agent_parameter_debug + `uvm_info("CFG", + $psprintf("The BFM at '%m' has the following parameters: AW_WIDTH=%x LEN=%x DATA_WIDTH=%x X=%x ", AW_WIDTH,LEN,DATA_WIDTH,X), + UVM_DEBUG) +end +`endif + + + // Structure used to pass transaction data from monitor BFM to monitor class in agent. +`axi_m_MONITOR_STRUCT + axi_m_monitor_s axi_m_monitor_struct; + + // Structure used to pass configuration data from monitor class to monitor BFM. + `axi_m_CONFIGURATION_STRUCT + + + // Config value to determine if this is an initiator or a responder + uvmf_initiator_responder_t initiator_responder; + // Custom configuration variables. + // These are set using the configure function which is called during the UVM connect_phase + + logic axi_clk_i; + logic rst_i; + tri awvalid_i; + tri awready_i; + tri [AW_WIDTH-1:0] awaddr_i; + tri [2:0] awsize_i; + tri [1:0] awburst_i; + tri [3:0] awcache_i; + tri [2:0] awprot_i; + tri [X-1:0] awid_i; + tri [LEN-1:0] awlen_i; + tri awlock_i; + tri [3:0] awqos_i; + tri [3:0] awregion_i; + tri [X-1:0] awuser_i; + tri wvalid_i; + tri wready_i; + tri wlast_i; + tri [DATA_WIDTH-1:0] wdata_i; + tri [DATA_WIDTH/8-1:0] wstrb_i; + tri [X-1:0] wid_i; + tri [X-1:0] wuser_i; + tri bwvalid_i; + tri bwready_i; + tri [1:0] bresp_i; + tri [X-1:0] bid_i; + tri [X-1:0] buser_i; + tri arvalid_i; + tri aready_i; + tri [AW_WIDTH-1:0] araddr_i; + tri [2:0] arsize_i; + tri [1:0] arburst_i; + tri [3:0] arcache_i; + tri [2:0] arprot_i; + tri [X-1:0] arid_i; + tri [LEN-1:0] arlen_i; + tri arlock_i; + tri [3:0] arqos_i; + tri [3:0] aregion_i; + tri [X-1:0] aruser_i; + tri rvalid_i; + tri rready_i; + tri rlast_i; + tri [DATA_WIDTH-1:0] rdata_i; + tri [X-1:0] rid_i; + tri [X-1:0] ruser_i; + tri [1:0] rresp_i; + assign axi_clk_i = bus.axi_clk; + assign rst_i = bus.rst; + assign awvalid_i = bus.awvalid; + assign awready_i = bus.awready; + assign awaddr_i = bus.awaddr; + assign awsize_i = bus.awsize; + assign awburst_i = bus.awburst; + assign awcache_i = bus.awcache; + assign awprot_i = bus.awprot; + assign awid_i = bus.awid; + assign awlen_i = bus.awlen; + assign awlock_i = bus.awlock; + assign awqos_i = bus.awqos; + assign awregion_i = bus.awregion; + assign awuser_i = bus.awuser; + assign wvalid_i = bus.wvalid; + assign wready_i = bus.wready; + assign wlast_i = bus.wlast; + assign wdata_i = bus.wdata; + assign wstrb_i = bus.wstrb; + assign wid_i = bus.wid; + assign wuser_i = bus.wuser; + assign bwvalid_i = bus.bwvalid; + assign bwready_i = bus.bwready; + assign bresp_i = bus.bresp; + assign bid_i = bus.bid; + assign buser_i = bus.buser; + assign arvalid_i = bus.arvalid; + assign aready_i = bus.aready; + assign araddr_i = bus.araddr; + assign arsize_i = bus.arsize; + assign arburst_i = bus.arburst; + assign arcache_i = bus.arcache; + assign arprot_i = bus.arprot; + assign arid_i = bus.arid; + assign arlen_i = bus.arlen; + assign arlock_i = bus.arlock; + assign arqos_i = bus.arqos; + assign aregion_i = bus.aregion; + assign aruser_i = bus.aruser; + assign rvalid_i = bus.rvalid; + assign rready_i = bus.rready; + assign rlast_i = bus.rlast; + assign rdata_i = bus.rdata; + assign rid_i = bus.rid; + assign ruser_i = bus.ruser; + assign rresp_i = bus.rresp; + + // Proxy handle to UVM monitor + axi_m_pkg::axi_m_monitor #( + .AW_WIDTH(AW_WIDTH), + .LEN(LEN), + .DATA_WIDTH(DATA_WIDTH), + .X(X) + ) proxy; + // pragma tbx oneway proxy.notify_transaction + + // pragma uvmf custom interface_item_additional begin + // pragma uvmf custom interface_item_additional end + + //****************************************************************** + task wait_for_reset();// pragma tbx xtf + @(posedge axi_clk_i) ; + do_wait_for_reset(); + endtask + + // **************************************************************************** + task do_wait_for_reset(); + // pragma uvmf custom reset_condition begin + wait ( rst_i === 1 ) ; + @(posedge axi_clk_i) ; + // pragma uvmf custom reset_condition end + endtask + + //****************************************************************** + + task wait_for_num_clocks(input int unsigned count); // pragma tbx xtf + @(posedge axi_clk_i); + + repeat (count-1) @(posedge axi_clk_i); + endtask + + //****************************************************************** + event go; + function void start_monitoring();// pragma tbx xtf + -> go; + endfunction + + // **************************************************************************** + initial begin + @go; + forever begin + @(posedge axi_clk_i); + do_monitor( axi_m_monitor_struct ); + + + proxy.notify_transaction( axi_m_monitor_struct ); + + end + end + + //****************************************************************** + // The configure() function is used to pass agent configuration + // variables to the monitor BFM. It is called by the monitor within + // the agent at the beginning of the simulation. It may be called + // during the simulation if agent configuration variables are updated + // and the monitor BFM needs to be aware of the new configuration + // variables. + // + function void configure(axi_m_configuration_s axi_m_configuration_arg); // pragma tbx xtf + initiator_responder = axi_m_configuration_arg.initiator_responder; + // pragma uvmf custom configure begin + // pragma uvmf custom configure end + endfunction + + + // **************************************************************************** + + task do_monitor(output axi_m_monitor_s axi_m_monitor_struct); + // + // Available struct members: + // // axi_m_monitor_struct.awvalid + // // axi_m_monitor_struct.awready + // // axi_m_monitor_struct.awaddr + // // axi_m_monitor_struct.awsize + // // axi_m_monitor_struct.awburst + // // axi_m_monitor_struct.awcache + // // axi_m_monitor_struct.awprot + // // axi_m_monitor_struct.awid + // // axi_m_monitor_struct.awlen + // // axi_m_monitor_struct.awlock + // // axi_m_monitor_struct.awqos + // // axi_m_monitor_struct.awregion + // // axi_m_monitor_struct.awuser + // // axi_m_monitor_struct.wvalid + // // axi_m_monitor_struct.wready + // // axi_m_monitor_struct.wlast + // // axi_m_monitor_struct.wdata + // // axi_m_monitor_struct.wstrb + // // axi_m_monitor_struct.wid + // // axi_m_monitor_struct.wuser + // // axi_m_monitor_struct.bwvalid + // // axi_m_monitor_struct.bwready + // // axi_m_monitor_struct.bresp + // // axi_m_monitor_struct.bid + // // axi_m_monitor_struct.buser + // // axi_m_monitor_struct.arvalid + // // axi_m_monitor_struct.aready + // // axi_m_monitor_struct.araddr + // // axi_m_monitor_struct.arsize + // // axi_m_monitor_struct.arburst + // // axi_m_monitor_struct.arcache + // // axi_m_monitor_struct.arprot + // // axi_m_monitor_struct.arid + // // axi_m_monitor_struct.arlen + // // axi_m_monitor_struct.arlock + // // axi_m_monitor_struct.arqos + // // axi_m_monitor_struct.aregion + // // axi_m_monitor_struct.aruser + // // axi_m_monitor_struct.rvalid + // // axi_m_monitor_struct.rready + // // axi_m_monitor_struct.rlast + // // axi_m_monitor_struct.rdata + // // axi_m_monitor_struct.rid + // // axi_m_monitor_struct.ruser + // // axi_m_monitor_struct.rresp + // // + // Reference code; + // How to wait for signal value + // while (control_signal === 1'b1) @(posedge axi_clk_i); + // + // How to assign a struct member, named xyz, from a signal. + // All available input signals listed. + // axi_m_monitor_struct.xyz = awvalid_i; // + // axi_m_monitor_struct.xyz = awready_i; // + // axi_m_monitor_struct.xyz = awaddr_i; // [AW_WIDTH-1:0] + // axi_m_monitor_struct.xyz = awsize_i; // [2:0] + // axi_m_monitor_struct.xyz = awburst_i; // [1:0] + // axi_m_monitor_struct.xyz = awcache_i; // [3:0] + // axi_m_monitor_struct.xyz = awprot_i; // [2:0] + // axi_m_monitor_struct.xyz = awid_i; // [X-1:0] + // axi_m_monitor_struct.xyz = awlen_i; // [LEN-1:0] + // axi_m_monitor_struct.xyz = awlock_i; // + // axi_m_monitor_struct.xyz = awqos_i; // [3:0] + // axi_m_monitor_struct.xyz = awregion_i; // [3:0] + // axi_m_monitor_struct.xyz = awuser_i; // [X-1:0] + // axi_m_monitor_struct.xyz = wvalid_i; // + // axi_m_monitor_struct.xyz = wready_i; // + // axi_m_monitor_struct.xyz = wlast_i; // + // axi_m_monitor_struct.xyz = wdata_i; // [DATA_WIDTH-1:0] + // axi_m_monitor_struct.xyz = wstrb_i; // [DATA_WIDTH/8-1:0] + // axi_m_monitor_struct.xyz = wid_i; // [X-1:0] + // axi_m_monitor_struct.xyz = wuser_i; // [X-1:0] + // axi_m_monitor_struct.xyz = bwvalid_i; // + // axi_m_monitor_struct.xyz = bwready_i; // + // axi_m_monitor_struct.xyz = bresp_i; // [1:0] + // axi_m_monitor_struct.xyz = bid_i; // [X-1:0] + // axi_m_monitor_struct.xyz = buser_i; // [X-1:0] + // axi_m_monitor_struct.xyz = arvalid_i; // + // axi_m_monitor_struct.xyz = aready_i; // + // axi_m_monitor_struct.xyz = araddr_i; // [AW_WIDTH-1:0] + // axi_m_monitor_struct.xyz = arsize_i; // [2:0] + // axi_m_monitor_struct.xyz = arburst_i; // [1:0] + // axi_m_monitor_struct.xyz = arcache_i; // [3:0] + // axi_m_monitor_struct.xyz = arprot_i; // [2:0] + // axi_m_monitor_struct.xyz = arid_i; // [X-1:0] + // axi_m_monitor_struct.xyz = arlen_i; // [LEN-1:0] + // axi_m_monitor_struct.xyz = arlock_i; // + // axi_m_monitor_struct.xyz = arqos_i; // [3:0] + // axi_m_monitor_struct.xyz = aregion_i; // [3:0] + // axi_m_monitor_struct.xyz = aruser_i; // [X-1:0] + // axi_m_monitor_struct.xyz = rvalid_i; // + // axi_m_monitor_struct.xyz = rready_i; // + // axi_m_monitor_struct.xyz = rlast_i; // + // axi_m_monitor_struct.xyz = rdata_i; // [DATA_WIDTH-1:0] + // axi_m_monitor_struct.xyz = rid_i; // [X-1:0] + // axi_m_monitor_struct.xyz = ruser_i; // [X-1:0] + // axi_m_monitor_struct.xyz = rresp_i; // [1:0] + // pragma uvmf custom do_monitor begin + // UVMF_CHANGE_ME : Implement protocol monitoring. The commented reference code + // below are examples of how to capture signal values and assign them to + // structure members. All available input signals are listed. The 'while' + // code example shows how to wait for a synchronous flow control signal. This + // task should return when a complete transfer has been observed. Once this task is + // exited with captured values, it is then called again to wait for and observe + // the next transfer. One clock cycle is consumed between calls to do_monitor. + @(posedge axi_clk_i); + @(posedge axi_clk_i); + @(posedge axi_clk_i); + @(posedge axi_clk_i); + // pragma uvmf custom do_monitor end + endtask + + +endinterface + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/axi_m_pkg/src/axi_m_random_sequence.svh b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/axi_m_pkg/src/axi_m_random_sequence.svh new file mode 100644 index 00000000..06a95ce8 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/axi_m_pkg/src/axi_m_random_sequence.svh @@ -0,0 +1,73 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: +// This sequences randomizes the axi_m transaction and sends it +// to the UVM driver. +// +// This sequence constructs and randomizes a axi_m_transaction. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class axi_m_random_sequence #( + int AW_WIDTH = 32, + int LEN = 8, + int DATA_WIDTH = 32, + int X = 16 + ) + extends axi_m_sequence_base #( + .AW_WIDTH(AW_WIDTH), + .LEN(LEN), + .DATA_WIDTH(DATA_WIDTH), + .X(X) + ); + + `uvm_object_param_utils( axi_m_random_sequence #( + AW_WIDTH, + LEN, + DATA_WIDTH, + X + )) + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + //***************************************************************** + function new(string name = ""); + super.new(name); + endfunction: new + + // **************************************************************************** + // TASK : body() + // This task is automatically executed when this sequence is started using the + // start(sequencerHandle) task. + // + task body(); + + // Construct the transaction + req=axi_m_transaction#( + .AW_WIDTH(AW_WIDTH), + .LEN(LEN), + .DATA_WIDTH(DATA_WIDTH), + .X(X) + )::type_id::create("req"); + start_item(req); + // Randomize the transaction + if(!req.randomize()) `uvm_fatal("SEQ", "axi_m_random_sequence::body()-axi_m_transaction randomization failed") + // Send the transaction to the axi_m_driver_bfm via the sequencer and axi_m_driver. + finish_item(req); + `uvm_info("SEQ", {"Response:",req.convert2string()},UVM_MEDIUM) + + endtask + +endclass: axi_m_random_sequence + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/axi_m_pkg/src/axi_m_responder_sequence.svh b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/axi_m_pkg/src/axi_m_responder_sequence.svh new file mode 100644 index 00000000..caf31664 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/axi_m_pkg/src/axi_m_responder_sequence.svh @@ -0,0 +1,69 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This class can be used to provide stimulus when an interface +// has been configured to run in a responder mode. It +// will never finish by default, always going back to the driver +// and driver BFM for the next transaction with which to respond. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class axi_m_responder_sequence #( + int AW_WIDTH = 32, + int LEN = 8, + int DATA_WIDTH = 32, + int X = 16 + ) + extends axi_m_sequence_base #( + .AW_WIDTH(AW_WIDTH), + .LEN(LEN), + .DATA_WIDTH(DATA_WIDTH), + .X(X) + ); + + `uvm_object_param_utils( axi_m_responder_sequence #( + AW_WIDTH, + LEN, + DATA_WIDTH, + X + )) + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + function new(string name = "axi_m_responder_sequence"); + super.new(name); + endfunction + + task body(); + req=axi_m_transaction#( + .AW_WIDTH(AW_WIDTH), + .LEN(LEN), + .DATA_WIDTH(DATA_WIDTH), + .X(X) + )::type_id::create("req"); + forever begin + start_item(req); + finish_item(req); + // pragma uvmf custom body begin + // UVMF_CHANGE_ME : Do something here with the resulting req item. The + // finish_item() call above will block until the req transaction is ready + // to be handled by the responder sequence. + // If this was an item that required a response, the expectation is + // that the response should be populated within this transaction now. + `uvm_info("SEQ",$sformatf("Processed txn: %s",req.convert2string()),UVM_HIGH) + // pragma uvmf custom body end + end + endtask + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/axi_m_pkg/src/axi_m_sequence_base.svh b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/axi_m_pkg/src/axi_m_sequence_base.svh new file mode 100644 index 00000000..3924f333 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/axi_m_pkg/src/axi_m_sequence_base.svh @@ -0,0 +1,126 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: +// This file contains the class used as the base class for all sequences +// for this interface. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class axi_m_sequence_base #( + int AW_WIDTH = 32, + int LEN = 8, + int DATA_WIDTH = 32, + int X = 16 + ) extends uvmf_sequence_base #( + .REQ(axi_m_transaction #( + .AW_WIDTH(AW_WIDTH), + .LEN(LEN), + .DATA_WIDTH(DATA_WIDTH), + .X(X) + )), + .RSP(axi_m_transaction #( + .AW_WIDTH(AW_WIDTH), + .LEN(LEN), + .DATA_WIDTH(DATA_WIDTH), + .X(X) + ))); + + `uvm_object_param_utils( axi_m_sequence_base #( + AW_WIDTH, + LEN, + DATA_WIDTH, + X + )) + + // variables + typedef axi_m_transaction #( + .AW_WIDTH(AW_WIDTH), + .LEN(LEN), + .DATA_WIDTH(DATA_WIDTH), + .X(X) + ) axi_m_transaction_req_t; + axi_m_transaction_req_t req; + typedef axi_m_transaction #( + .AW_WIDTH(AW_WIDTH), + .LEN(LEN), + .DATA_WIDTH(DATA_WIDTH), + .X(X) + ) axi_m_transaction_rsp_t; + axi_m_transaction_rsp_t rsp; + + // Event for identifying when a response was received from the sequencer + event new_rsp; + + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + // **************************************************************************** + // TASK : get_responses() + // This task recursively gets sequence item responses from the sequencer. + // + virtual task get_responses(); + fork + begin + // Block until new rsp available + get_response(rsp); + // New rsp received. Indicate to sequence using event. + ->new_rsp; + // Display the received response transaction + `uvm_info("SEQ", {"New response transaction:",rsp.convert2string()}, UVM_MEDIUM) + end + join_none + endtask + + // **************************************************************************** + // TASK : pre_body() + // This task is called automatically when start is called with call_pre_post set to 1 (default). + // By calling get_responses() within pre_body() any derived sequences are automatically + // processing response transactions. Only un-comment this call to get_responses() if you + // have configured the interface driver to utilize the response transaction path by setting + // the configuration variable "return_transaction_response" to 1. Otherwise it is possible + // to impact runtime performance and memory utilization. + // + virtual task pre_body(); + // pragma uvmf custom pre_body begin +// get_responses(); + // pragma uvmf custom pre_body end + endtask + + // **************************************************************************** + // TASK : body() + // This task is called automatically when start is called. This sequence sends + // a req sequence item to the sequencer identified as an argument in the call + // to start. + // + virtual task body(); + // pragma uvmf custom body begin + start_item(req); + finish_item(req); + // pragma uvmf custom body end + endtask + + // **************************************************************************** + // FUNCTION : new() + // This function is the standard SystemVerilog constructor. + // + function new( string name =""); + super.new( name ); + // pragma uvmf custom new begin + req = axi_m_transaction_req_t::type_id::create("req"); + rsp = axi_m_transaction_rsp_t::type_id::create("rsp"); + // pragma uvmf custom new end + endfunction + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/axi_m_pkg/src/axi_m_transaction.svh b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/axi_m_pkg/src/axi_m_transaction.svh new file mode 100644 index 00000000..18c07970 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/axi_m_pkg/src/axi_m_transaction.svh @@ -0,0 +1,333 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This class defines the variables required for an axi_m +// transaction. Class variables to be displayed in waveform transaction +// viewing are added to the transaction viewing stream in the add_to_wave +// function. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class axi_m_transaction #( + int AW_WIDTH = 32, + int LEN = 8, + int DATA_WIDTH = 32, + int X = 16 + ) extends uvmf_transaction_base; + + `uvm_object_param_utils( axi_m_transaction #( + AW_WIDTH, + LEN, + DATA_WIDTH, + X + )) + + bit awvalid ; + bit awready ; + rand bit [AW_WIDTH-1:0] awaddr ; + rand bit awsize ; + rand bit awburst ; + rand bit awcache ; + rand bit awprot ; + rand bit [X-1:0] awid ; + rand bit [LEN-1:0] awlen ; + rand bit awlock ; + rand bit awqos ; + rand bit awregion ; + rand bit [X-1:0] awuser ; + bit wvalid ; + bit wready ; + bit wlast ; + rand bit [DATA_WIDTH-1:0] wdata ; + rand bit [DATA_WIDTH/8-1:0] wstrb ; + bit [X-1:0] wid ; + rand bit [X-1:0] wuser ; + bit bwvalid ; + bit bwready ; + rand bit bresp ; + bit [X-1:0] bid ; + rand bit [X-1:0] buser ; + bit arvalid ; + bit aready ; + rand bit [AW_WIDTH-1:0] araddr ; + rand bit arsize ; + rand bit arburst ; + rand bit arcache ; + rand bit arprot ; + rand bit [X-1:0] arid ; + rand bit [LEN-1:0] arlen ; + rand bit arlock ; + rand bit arqos ; + rand bit aregion ; + rand bit [X-1:0] aruser ; + bit rvalid ; + bit rready ; + bit rlast ; + rand bit [DATA_WIDTH-1:0] rdata ; + rand bit [X-1:0] rid ; + rand bit [X-1:0] ruser ; + rand bit rresp ; + + //Constraints for the transaction variables: + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + //******************************************************************* + //******************************************************************* + // Macros that define structs and associated functions are + // located in axi_m_macros.svh + + //******************************************************************* + // Monitor macro used by axi_m_monitor and axi_m_monitor_bfm + // This struct is defined in axi_m_macros.svh + `axi_m_MONITOR_STRUCT + axi_m_monitor_s axi_m_monitor_struct; + //******************************************************************* + // FUNCTION: to_monitor_struct() + // This function packs transaction variables into a axi_m_monitor_s + // structure. The function returns the handle to the axi_m_monitor_struct. + // This function is defined in axi_m_macros.svh + `axi_m_TO_MONITOR_STRUCT_FUNCTION + //******************************************************************* + // FUNCTION: from_monitor_struct() + // This function unpacks the struct provided as an argument into transaction + // variables of this class. + // This function is defined in axi_m_macros.svh + `axi_m_FROM_MONITOR_STRUCT_FUNCTION + + //******************************************************************* + // Initiator macro used by axi_m_driver and axi_m_driver_bfm + // to communicate initiator driven data to axi_m_driver_bfm. + // This struct is defined in axi_m_macros.svh + `axi_m_INITIATOR_STRUCT + axi_m_initiator_s axi_m_initiator_struct; + //******************************************************************* + // FUNCTION: to_initiator_struct() + // This function packs transaction variables into a axi_m_initiator_s + // structure. The function returns the handle to the axi_m_initiator_struct. + // This function is defined in axi_m_macros.svh + `axi_m_TO_INITIATOR_STRUCT_FUNCTION + //******************************************************************* + // FUNCTION: from_initiator_struct() + // This function unpacks the struct provided as an argument into transaction + // variables of this class. + // This function is defined in axi_m_macros.svh + `axi_m_FROM_INITIATOR_STRUCT_FUNCTION + + //******************************************************************* + // Responder macro used by axi_m_driver and axi_m_driver_bfm + // to communicate Responder driven data to axi_m_driver_bfm. + // This struct is defined in axi_m_macros.svh + `axi_m_RESPONDER_STRUCT + axi_m_responder_s axi_m_responder_struct; + //******************************************************************* + // FUNCTION: to_responder_struct() + // This function packs transaction variables into a axi_m_responder_s + // structure. The function returns the handle to the axi_m_responder_struct. + // This function is defined in axi_m_macros.svh + `axi_m_TO_RESPONDER_STRUCT_FUNCTION + //******************************************************************* + // FUNCTION: from_responder_struct() + // This function unpacks the struct provided as an argument into transaction + // variables of this class. + // This function is defined in axi_m_macros.svh + `axi_m_FROM_RESPONDER_STRUCT_FUNCTION + // **************************************************************************** + // FUNCTION : new() + // This function is the standard SystemVerilog constructor. + // + function new( string name = "" ); + super.new( name ); + endfunction + + // **************************************************************************** + // FUNCTION: convert2string() + // This function converts all variables in this class to a single string for + // logfile reporting. + // + virtual function string convert2string(); + // pragma uvmf custom convert2string begin + // UVMF_CHANGE_ME : Customize format if desired. + return $sformatf("awvalid:0x%x awready:0x%x awaddr:0x%x awsize:0x%x awburst:0x%x awcache:0x%x awprot:0x%x awid:0x%x awlen:0x%x awlock:0x%x awqos:0x%x awregion:0x%x awuser:0x%x wvalid:0x%x wready:0x%x wlast:0x%x wdata:0x%x wstrb:0x%x wid:0x%x wuser:0x%x bwvalid:0x%x bwready:0x%x bresp:0x%x bid:0x%x buser:0x%x arvalid:0x%x aready:0x%x araddr:0x%x arsize:0x%x arburst:0x%x arcache:0x%x arprot:0x%x arid:0x%x arlen:0x%x arlock:0x%x arqos:0x%x aregion:0x%x aruser:0x%x rvalid:0x%x rready:0x%x rlast:0x%x rdata:0x%x rid:0x%x ruser:0x%x rresp:0x%x ",awvalid,awready,awaddr,awsize,awburst,awcache,awprot,awid,awlen,awlock,awqos,awregion,awuser,wvalid,wready,wlast,wdata,wstrb,wid,wuser,bwvalid,bwready,bresp,bid,buser,arvalid,aready,araddr,arsize,arburst,arcache,arprot,arid,arlen,arlock,arqos,aregion,aruser,rvalid,rready,rlast,rdata,rid,ruser,rresp); + // pragma uvmf custom convert2string end + endfunction + + //******************************************************************* + // FUNCTION: do_print() + // This function is automatically called when the .print() function + // is called on this class. + // + virtual function void do_print(uvm_printer printer); + // pragma uvmf custom do_print begin + // UVMF_CHANGE_ME : Current contents of do_print allows for the use of UVM 1.1d, 1.2 or P1800.2. + // Update based on your own printing preference according to your preferred UVM version + $display(convert2string()); + // pragma uvmf custom do_print end + endfunction + + //******************************************************************* + // FUNCTION: do_compare() + // This function is automatically called when the .compare() function + // is called on this class. + // + virtual function bit do_compare (uvm_object rhs, uvm_comparer comparer); + axi_m_transaction #( + .AW_WIDTH(AW_WIDTH), + .LEN(LEN), + .DATA_WIDTH(DATA_WIDTH), + .X(X) + ) RHS; + if (!$cast(RHS,rhs)) return 0; + // pragma uvmf custom do_compare begin + // UVMF_CHANGE_ME : Eliminate comparison of variables not to be used for compare + return (super.do_compare(rhs,comparer) + ); + // pragma uvmf custom do_compare end + endfunction + + //******************************************************************* + // FUNCTION: do_copy() + // This function is automatically called when the .copy() function + // is called on this class. + // + virtual function void do_copy (uvm_object rhs); + axi_m_transaction #( + .AW_WIDTH(AW_WIDTH), + .LEN(LEN), + .DATA_WIDTH(DATA_WIDTH), + .X(X) + ) RHS; + assert($cast(RHS,rhs)); + // pragma uvmf custom do_copy begin + super.do_copy(rhs); + this.awvalid = RHS.awvalid; + this.awready = RHS.awready; + this.awaddr = RHS.awaddr; + this.awsize = RHS.awsize; + this.awburst = RHS.awburst; + this.awcache = RHS.awcache; + this.awprot = RHS.awprot; + this.awid = RHS.awid; + this.awlen = RHS.awlen; + this.awlock = RHS.awlock; + this.awqos = RHS.awqos; + this.awregion = RHS.awregion; + this.awuser = RHS.awuser; + this.wvalid = RHS.wvalid; + this.wready = RHS.wready; + this.wlast = RHS.wlast; + this.wdata = RHS.wdata; + this.wstrb = RHS.wstrb; + this.wid = RHS.wid; + this.wuser = RHS.wuser; + this.bwvalid = RHS.bwvalid; + this.bwready = RHS.bwready; + this.bresp = RHS.bresp; + this.bid = RHS.bid; + this.buser = RHS.buser; + this.arvalid = RHS.arvalid; + this.aready = RHS.aready; + this.araddr = RHS.araddr; + this.arsize = RHS.arsize; + this.arburst = RHS.arburst; + this.arcache = RHS.arcache; + this.arprot = RHS.arprot; + this.arid = RHS.arid; + this.arlen = RHS.arlen; + this.arlock = RHS.arlock; + this.arqos = RHS.arqos; + this.aregion = RHS.aregion; + this.aruser = RHS.aruser; + this.rvalid = RHS.rvalid; + this.rready = RHS.rready; + this.rlast = RHS.rlast; + this.rdata = RHS.rdata; + this.rid = RHS.rid; + this.ruser = RHS.ruser; + this.rresp = RHS.rresp; + // pragma uvmf custom do_copy end + endfunction + + // **************************************************************************** + // FUNCTION: add_to_wave() + // This function is used to display variables in this class in the waveform + // viewer. The start_time and end_time variables must be set before this + // function is called. If the start_time and end_time variables are not set + // the transaction will be hidden at 0ns on the waveform display. + // + virtual function void add_to_wave(int transaction_viewing_stream_h); + `ifdef QUESTA + if (transaction_view_h == 0) begin + transaction_view_h = $begin_transaction(transaction_viewing_stream_h,"axi_m_transaction",start_time); + end + super.add_to_wave(transaction_view_h); + // pragma uvmf custom add_to_wave begin + // UVMF_CHANGE_ME : Color can be applied to transaction entries based on content, example below + // case() + // 1 : $add_color(transaction_view_h,"red"); + // default : $add_color(transaction_view_h,"grey"); + // endcase + // UVMF_CHANGE_ME : Eliminate transaction variables not wanted in transaction viewing in the waveform viewer + $add_attribute(transaction_view_h,awvalid,"awvalid"); + $add_attribute(transaction_view_h,awready,"awready"); + $add_attribute(transaction_view_h,awaddr,"awaddr"); + $add_attribute(transaction_view_h,awsize,"awsize"); + $add_attribute(transaction_view_h,awburst,"awburst"); + $add_attribute(transaction_view_h,awcache,"awcache"); + $add_attribute(transaction_view_h,awprot,"awprot"); + $add_attribute(transaction_view_h,awid,"awid"); + $add_attribute(transaction_view_h,awlen,"awlen"); + $add_attribute(transaction_view_h,awlock,"awlock"); + $add_attribute(transaction_view_h,awqos,"awqos"); + $add_attribute(transaction_view_h,awregion,"awregion"); + $add_attribute(transaction_view_h,awuser,"awuser"); + $add_attribute(transaction_view_h,wvalid,"wvalid"); + $add_attribute(transaction_view_h,wready,"wready"); + $add_attribute(transaction_view_h,wlast,"wlast"); + $add_attribute(transaction_view_h,wdata,"wdata"); + $add_attribute(transaction_view_h,wstrb,"wstrb"); + $add_attribute(transaction_view_h,wid,"wid"); + $add_attribute(transaction_view_h,wuser,"wuser"); + $add_attribute(transaction_view_h,bwvalid,"bwvalid"); + $add_attribute(transaction_view_h,bwready,"bwready"); + $add_attribute(transaction_view_h,bresp,"bresp"); + $add_attribute(transaction_view_h,bid,"bid"); + $add_attribute(transaction_view_h,buser,"buser"); + $add_attribute(transaction_view_h,arvalid,"arvalid"); + $add_attribute(transaction_view_h,aready,"aready"); + $add_attribute(transaction_view_h,araddr,"araddr"); + $add_attribute(transaction_view_h,arsize,"arsize"); + $add_attribute(transaction_view_h,arburst,"arburst"); + $add_attribute(transaction_view_h,arcache,"arcache"); + $add_attribute(transaction_view_h,arprot,"arprot"); + $add_attribute(transaction_view_h,arid,"arid"); + $add_attribute(transaction_view_h,arlen,"arlen"); + $add_attribute(transaction_view_h,arlock,"arlock"); + $add_attribute(transaction_view_h,arqos,"arqos"); + $add_attribute(transaction_view_h,aregion,"aregion"); + $add_attribute(transaction_view_h,aruser,"aruser"); + $add_attribute(transaction_view_h,rvalid,"rvalid"); + $add_attribute(transaction_view_h,rready,"rready"); + $add_attribute(transaction_view_h,rlast,"rlast"); + $add_attribute(transaction_view_h,rdata,"rdata"); + $add_attribute(transaction_view_h,rid,"rid"); + $add_attribute(transaction_view_h,ruser,"ruser"); + $add_attribute(transaction_view_h,rresp,"rresp"); + // pragma uvmf custom add_to_wave end + $end_transaction(transaction_view_h,end_time); + $free_transaction(transaction_view_h); + `endif // QUESTA + endfunction + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/axi_m_pkg/src/axi_m_transaction_coverage.svh b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/axi_m_pkg/src/axi_m_transaction_coverage.svh new file mode 100644 index 00000000..088ea2eb --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/axi_m_pkg/src/axi_m_transaction_coverage.svh @@ -0,0 +1,129 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This class records axi_m transaction information using +// a covergroup named axi_m_transaction_cg. An instance of this +// coverage component is instantiated in the uvmf_parameterized_agent +// if the has_coverage flag is set. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class axi_m_transaction_coverage #( + int AW_WIDTH = 32, + int LEN = 8, + int DATA_WIDTH = 32, + int X = 16 + ) extends uvm_subscriber #(.T(axi_m_transaction #( + .AW_WIDTH(AW_WIDTH), + .LEN(LEN), + .DATA_WIDTH(DATA_WIDTH), + .X(X) + ))); + + `uvm_component_param_utils( axi_m_transaction_coverage #( + AW_WIDTH, + LEN, + DATA_WIDTH, + X + )) + + T coverage_trans; + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + // **************************************************************************** + covergroup axi_m_transaction_cg; + // pragma uvmf custom covergroup begin + // UVMF_CHANGE_ME : Add coverage bins, crosses, exclusions, etc. according to coverage needs. + option.auto_bin_max=1024; + option.per_instance=1; + awvalid: coverpoint coverage_trans.awvalid; + awready: coverpoint coverage_trans.awready; + awaddr: coverpoint coverage_trans.awaddr; + awsize: coverpoint coverage_trans.awsize; + awburst: coverpoint coverage_trans.awburst; + awcache: coverpoint coverage_trans.awcache; + awprot: coverpoint coverage_trans.awprot; + awid: coverpoint coverage_trans.awid; + awlen: coverpoint coverage_trans.awlen; + awlock: coverpoint coverage_trans.awlock; + awqos: coverpoint coverage_trans.awqos; + awregion: coverpoint coverage_trans.awregion; + awuser: coverpoint coverage_trans.awuser; + wvalid: coverpoint coverage_trans.wvalid; + wready: coverpoint coverage_trans.wready; + wlast: coverpoint coverage_trans.wlast; + wdata: coverpoint coverage_trans.wdata; + wstrb: coverpoint coverage_trans.wstrb; + wid: coverpoint coverage_trans.wid; + wuser: coverpoint coverage_trans.wuser; + bwvalid: coverpoint coverage_trans.bwvalid; + bwready: coverpoint coverage_trans.bwready; + bresp: coverpoint coverage_trans.bresp; + bid: coverpoint coverage_trans.bid; + buser: coverpoint coverage_trans.buser; + arvalid: coverpoint coverage_trans.arvalid; + aready: coverpoint coverage_trans.aready; + araddr: coverpoint coverage_trans.araddr; + arsize: coverpoint coverage_trans.arsize; + arburst: coverpoint coverage_trans.arburst; + arcache: coverpoint coverage_trans.arcache; + arprot: coverpoint coverage_trans.arprot; + arid: coverpoint coverage_trans.arid; + arlen: coverpoint coverage_trans.arlen; + arlock: coverpoint coverage_trans.arlock; + arqos: coverpoint coverage_trans.arqos; + aregion: coverpoint coverage_trans.aregion; + aruser: coverpoint coverage_trans.aruser; + rvalid: coverpoint coverage_trans.rvalid; + rready: coverpoint coverage_trans.rready; + rlast: coverpoint coverage_trans.rlast; + rdata: coverpoint coverage_trans.rdata; + rid: coverpoint coverage_trans.rid; + ruser: coverpoint coverage_trans.ruser; + rresp: coverpoint coverage_trans.rresp; + // pragma uvmf custom covergroup end + endgroup + + // **************************************************************************** + // FUNCTION : new() + // This function is the standard SystemVerilog constructor. + // + function new(string name="", uvm_component parent=null); + super.new(name,parent); + axi_m_transaction_cg=new; + `uvm_warning("COVERAGE_MODEL_REVIEW", "A covergroup has been constructed which may need review because of either generation or re-generation with merging. Please note that transaction variables added as a result of re-generation and merging are not automatically added to the covergroup. Remove this warning after the covergroup has been reviewed.") + endfunction + + // **************************************************************************** + // FUNCTION : build_phase() + // This function is the standard UVM build_phase. + // + function void build_phase(uvm_phase phase); + axi_m_transaction_cg.set_inst_name($sformatf("axi_m_transaction_cg_%s",get_full_name())); + endfunction + + // **************************************************************************** + // FUNCTION: write (T t) + // This function is automatically executed when a transaction arrives on the + // analysis_export. It copies values from the variables in the transaction + // to local variables used to collect functional coverage. + // + virtual function void write (T t); + `uvm_info("COV","Received transaction",UVM_HIGH); + coverage_trans = t; + axi_m_transaction_cg.sample(); + endfunction + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/axi_m_pkg/src/axi_m_typedefs.svh b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/axi_m_pkg/src/axi_m_typedefs.svh new file mode 100644 index 00000000..43d85640 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/axi_m_pkg/src/axi_m_typedefs.svh @@ -0,0 +1,20 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: +// This file contains defines and typedefs to be compiled for use in +// the simulation running on the host server when using Veloce. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// + + +// pragma uvmf custom additional begin +// pragma uvmf custom additional end + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/axi_m_pkg/src/axi_m_typedefs_hdl.svh b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/axi_m_pkg/src/axi_m_typedefs_hdl.svh new file mode 100644 index 00000000..74738c8c --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/axi_m_pkg/src/axi_m_typedefs_hdl.svh @@ -0,0 +1,21 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: +// This file contains defines and typedefs to be compiled for use in +// the simulation running on the emulator when using Veloce. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// + + + +// pragma uvmf custom additional begin +// pragma uvmf custom additional end + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/axi_m_pkg/yaml/axi_m_interface.yaml b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/axi_m_pkg/yaml/axi_m_interface.yaml new file mode 100644 index 00000000..98e0bca3 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/axi_m_pkg/yaml/axi_m_interface.yaml @@ -0,0 +1,481 @@ +uvmf: + interfaces: + axi_m: + clock: axi_clk + config_constraints: [] + config_vars: [] + existing_library_component: 'True' + gen_inbound_streaming_driver: 'False' + hdl_pkg_parameters: [] + hdl_typedefs: [] + hvl_pkg_parameters: [] + hvl_typedefs: [] + parameters: + - name: AW_WIDTH + type: int + value: '32' + - name: LEN + type: int + value: '8' + - name: DATA_WIDTH + type: int + value: '32' + - name: X + type: int + value: '16' + ports: + - dir: output + name: awvalid + reset_value: '''bz' + width: '1' + - dir: input + name: awready + reset_value: '''bz' + width: '1' + - dir: output + name: awaddr + reset_value: '''bz' + width: AW_WIDTH + - dir: output + name: awsize + reset_value: '''bz' + width: '3' + - dir: output + name: awburst + reset_value: '''bz' + width: '2' + - dir: output + name: awcache + reset_value: '''bz' + width: '4' + - dir: output + name: awprot + reset_value: '''bz' + width: '3' + - dir: output + name: awid + reset_value: '''bz' + width: X + - dir: output + name: awlen + reset_value: '''bz' + width: LEN + - dir: output + name: awlock + reset_value: '''bz' + width: '1' + - dir: output + name: awqos + reset_value: '''bz' + width: '4' + - dir: output + name: awregion + reset_value: '''bz' + width: '4' + - dir: output + name: awuser + reset_value: '''bz' + width: X + - dir: output + name: wvalid + reset_value: '''bz' + width: '1' + - dir: input + name: wready + reset_value: '''bz' + width: '1' + - dir: output + name: wlast + reset_value: '''bz' + width: '1' + - dir: output + name: wdata + reset_value: '''bz' + width: DATA_WIDTH + - dir: output + name: wstrb + reset_value: '''bz' + width: DATA_WIDTH/8 + - dir: output + name: wid + reset_value: '''bz' + width: X + - dir: output + name: wuser + reset_value: '''bz' + width: X + - dir: input + name: bwvalid + reset_value: '''bz' + width: '1' + - dir: output + name: bwready + reset_value: '''bz' + width: '1' + - dir: input + name: bresp + reset_value: '''bz' + width: '2' + - dir: input + name: bid + reset_value: '''bz' + width: X + - dir: input + name: buser + reset_value: '''bz' + width: X + - dir: output + name: arvalid + reset_value: '''bz' + width: '1' + - dir: input + name: aready + reset_value: '''bz' + width: '1' + - dir: output + name: araddr + reset_value: '''bz' + width: AW_WIDTH + - dir: output + name: arsize + reset_value: '''bz' + width: '3' + - dir: output + name: arburst + reset_value: '''bz' + width: '2' + - dir: output + name: arcache + reset_value: '''bz' + width: '4' + - dir: output + name: arprot + reset_value: '''bz' + width: '3' + - dir: output + name: arid + reset_value: '''bz' + width: X + - dir: output + name: arlen + reset_value: '''bz' + width: LEN + - dir: output + name: arlock + reset_value: '''bz' + width: '1' + - dir: output + name: arqos + reset_value: '''bz' + width: '4' + - dir: output + name: aregion + reset_value: '''bz' + width: '4' + - dir: output + name: aruser + reset_value: '''bz' + width: X + - dir: input + name: rvalid + reset_value: '''bz' + width: '1' + - dir: output + name: rready + reset_value: '''bz' + width: '1' + - dir: input + name: rlast + reset_value: '''bz' + width: '1' + - dir: input + name: rdata + reset_value: '''bz' + width: DATA_WIDTH + - dir: input + name: rid + reset_value: '''bz' + width: X + - dir: input + name: ruser + reset_value: '''bz' + width: X + - dir: input + name: rresp + reset_value: '''bz' + width: '2' + reset: rst + reset_assertion_level: 'False' + transaction_constraints: [] + transaction_vars: + - comment: '' + iscompare: 'False' + isrand: 'False' + name: awvalid + type: bit + unpacked_dimension: '' + - comment: '' + iscompare: 'False' + isrand: 'False' + name: awready + type: bit + unpacked_dimension: '' + - comment: '' + iscompare: 'False' + isrand: 'True' + name: awaddr + type: bit [AW_WIDTH-1:0] + unpacked_dimension: '' + - comment: '' + iscompare: 'False' + isrand: 'True' + name: awsize + type: bit + unpacked_dimension: '' + - comment: '' + iscompare: 'False' + isrand: 'True' + name: awburst + type: bit + unpacked_dimension: '' + - comment: '' + iscompare: 'False' + isrand: 'True' + name: awcache + type: bit + unpacked_dimension: '' + - comment: '' + iscompare: 'False' + isrand: 'True' + name: awprot + type: bit + unpacked_dimension: '' + - comment: '' + iscompare: 'False' + isrand: 'True' + name: awid + type: bit [X-1:0] + unpacked_dimension: '' + - comment: '' + iscompare: 'False' + isrand: 'True' + name: awlen + type: bit [LEN-1:0] + unpacked_dimension: '' + - comment: '' + iscompare: 'False' + isrand: 'True' + name: awlock + type: bit + unpacked_dimension: '' + - comment: '' + iscompare: 'False' + isrand: 'True' + name: awqos + type: bit + unpacked_dimension: '' + - comment: '' + iscompare: 'False' + isrand: 'True' + name: awregion + type: bit + unpacked_dimension: '' + - comment: '' + iscompare: 'False' + isrand: 'True' + name: awuser + type: bit [X-1:0] + unpacked_dimension: '' + - comment: '' + iscompare: 'False' + isrand: 'False' + name: wvalid + type: bit + unpacked_dimension: '' + - comment: '' + iscompare: 'False' + isrand: 'False' + name: wready + type: bit + unpacked_dimension: '' + - comment: '' + iscompare: 'False' + isrand: 'False' + name: wlast + type: bit + unpacked_dimension: '' + - comment: '' + iscompare: 'False' + isrand: 'True' + name: wdata + type: bit [DATA_WIDTH-1:0] + unpacked_dimension: '' + - comment: '' + iscompare: 'False' + isrand: 'True' + name: wstrb + type: bit [DATA_WIDTH/8-1:0] + unpacked_dimension: '' + - comment: '' + iscompare: 'False' + isrand: 'False' + name: wid + type: bit [X-1:0] + unpacked_dimension: '' + - comment: '' + iscompare: 'False' + isrand: 'True' + name: wuser + type: bit [X-1:0] + unpacked_dimension: '' + - comment: '' + iscompare: 'False' + isrand: 'False' + name: bwvalid + type: bit + unpacked_dimension: '' + - comment: '' + iscompare: 'False' + isrand: 'False' + name: bwready + type: bit + unpacked_dimension: '' + - comment: '' + iscompare: 'False' + isrand: 'True' + name: bresp + type: bit + unpacked_dimension: '' + - comment: '' + iscompare: 'False' + isrand: 'False' + name: bid + type: bit [X-1:0] + unpacked_dimension: '' + - comment: '' + iscompare: 'False' + isrand: 'True' + name: buser + type: bit [X-1:0] + unpacked_dimension: '' + - comment: '' + iscompare: 'False' + isrand: 'False' + name: arvalid + type: bit + unpacked_dimension: '' + - comment: '' + iscompare: 'False' + isrand: 'False' + name: aready + type: bit + unpacked_dimension: '' + - comment: '' + iscompare: 'False' + isrand: 'True' + name: araddr + type: bit [AW_WIDTH-1:0] + unpacked_dimension: '' + - comment: '' + iscompare: 'False' + isrand: 'True' + name: arsize + type: bit + unpacked_dimension: '' + - comment: '' + iscompare: 'False' + isrand: 'True' + name: arburst + type: bit + unpacked_dimension: '' + - comment: '' + iscompare: 'False' + isrand: 'True' + name: arcache + type: bit + unpacked_dimension: '' + - comment: '' + iscompare: 'False' + isrand: 'True' + name: arprot + type: bit + unpacked_dimension: '' + - comment: '' + iscompare: 'False' + isrand: 'True' + name: arid + type: bit [X-1:0] + unpacked_dimension: '' + - comment: '' + iscompare: 'False' + isrand: 'True' + name: arlen + type: bit [LEN-1:0] + unpacked_dimension: '' + - comment: '' + iscompare: 'False' + isrand: 'True' + name: arlock + type: bit + unpacked_dimension: '' + - comment: '' + iscompare: 'False' + isrand: 'True' + name: arqos + type: bit + unpacked_dimension: '' + - comment: '' + iscompare: 'False' + isrand: 'True' + name: aregion + type: bit + unpacked_dimension: '' + - comment: '' + iscompare: 'False' + isrand: 'True' + name: aruser + type: bit [X-1:0] + unpacked_dimension: '' + - comment: '' + iscompare: 'False' + isrand: 'False' + name: rvalid + type: bit + unpacked_dimension: '' + - comment: '' + iscompare: 'False' + isrand: 'False' + name: rready + type: bit + unpacked_dimension: '' + - comment: '' + iscompare: 'False' + isrand: 'False' + name: rlast + type: bit + unpacked_dimension: '' + - comment: '' + iscompare: 'False' + isrand: 'True' + name: rdata + type: bit [DATA_WIDTH-1:0] + unpacked_dimension: '' + - comment: '' + iscompare: 'False' + isrand: 'True' + name: rid + type: bit [X-1:0] + unpacked_dimension: '' + - comment: '' + iscompare: 'False' + isrand: 'True' + name: ruser + type: bit [X-1:0] + unpacked_dimension: '' + - comment: '' + iscompare: 'False' + isrand: 'True' + name: rresp + type: bit + unpacked_dimension: '' + use_dpi_link: 'False' diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/axi_s_pkg/.project b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/axi_s_pkg/.project new file mode 100644 index 00000000..009c04fc --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/axi_s_pkg/.project @@ -0,0 +1,30 @@ + + + axi_s_pkg + + + + + + org.python.pydev.PyDevBuilder + + + + + net.sf.sveditor.core.SVProjectBuilder + + + + + + net.sf.sveditor.core.SVNature + org.python.pydev.pythonNature + + + + UVMF_VIP_LIBRARY_HOME + $%7BPARENT-2-PROJECT_LOC%7D + + + + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/axi_s_pkg/.svproject b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/axi_s_pkg/.svproject new file mode 100644 index 00000000..2f7c662b --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/axi_s_pkg/.svproject @@ -0,0 +1,16 @@ + + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/axi_s_pkg/Makefile b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/axi_s_pkg/Makefile new file mode 100644 index 00000000..63d28f13 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/axi_s_pkg/Makefile @@ -0,0 +1,66 @@ +# axi_s interface packages source +# pragma uvmf custom additional begin +# pragma uvmf custom additional end + +axi_s_PKG = \ + +incdir+$(UVMF_VIP_LIBRARY_HOME)/interface_packages/axi_s_pkg \ + -F $(UVMF_VIP_LIBRARY_HOME)/interface_packages/axi_s_pkg/axi_s_filelist_hvl.f + +axi_s_PKG_HDL = \ + +incdir+$(UVMF_VIP_LIBRARY_HOME)/interface_packages/axi_s_pkg \ + -F $(UVMF_VIP_LIBRARY_HOME)/interface_packages/axi_s_pkg/axi_s_filelist_hdl.f + +axi_s_PKG_XRTL = \ + +incdir+$(UVMF_VIP_LIBRARY_HOME)/interface_packages/axi_s_pkg \ + -F $(UVMF_VIP_LIBRARY_HOME)/interface_packages/axi_s_pkg/axi_s_filelist_xrtl.f + +COMP_axi_s_PKG_TGT_0 = q_comp_axi_s_pkg +COMP_axi_s_PKG_TGT_1 = v_comp_axi_s_pkg +COMP_axi_s_PKG_TGT = $(COMP_axi_s_PKG_TGT_$(USE_VELOCE)) + +comp_axi_s_pkg: $(COMP_axi_s_PKG_TGT) + +q_comp_axi_s_pkg: + $(HDL_COMP_CMD) $(axi_s_PKG_HDL) + $(HVL_COMP_CMD) $(axi_s_PKG) + $(HDL_COMP_CMD) $(axi_s_PKG_XRTL) + +v_comp_axi_s_pkg: + $(HVL_COMP_CMD) $(axi_s_PKG_HDL) + $(HVL_COMP_CMD) $(axi_s_PKG) + $(VELANALYZE_CMD) $(axi_s_PKG_HDL) + $(VELANALYZE_HVL_CMD) $(axi_s_PKG) + $(HDL_COMP_CMD) $(axi_s_PKG_XRTL) + +ifeq ($(MTI_VCO_MODE),64) + GCC_COMP_ARCH = -m64 +else + GCC_COMP_ARCH = -m32 +endif + +export axi_s_IF_DPI_SRC ?= $(UVMF_VIP_LIBRARY_HOME)/interface_packages/axi_s_pkg/dpi + +C_FILE_COMPILE_LIST_axi_s_pkg = \ + +O_FILE_COMPILE_LIST_axi_s_pkg = $(notdir $(C_FILE_COMPILE_LIST_axi_s_pkg:.c=.o)) + +GCC_COMP_ARGS_axi_s_pkg += -I$(axi_s_IF_DPI_SRC) \ + -fPIC + +GCC_COMP_ARGS_axi_s_pkg += $(axi_s_IF_GCC_COMP_ARGUMENTS) + +GCC_LINK_ARGS_axi_s_pkg += \ + \ + -o .so + +comp_axi_s_pkg_c_files: + @echo "--------------------------------" + @echo "Compiling Interface C source" + @echo "--------------------------------" + gcc $(GCC_COMP_ARCH) $(GCC_COMP_ARGS_axi_s_pkg) $(C_FILE_COMPILE_LIST_axi_s_pkg) + @echo "--------------------------------" + @echo "Linking Interface C objects into a shared object" + @echo "--------------------------------" + gcc $(GCC_COMP_ARCH) $(GCC_LINK_ARGS_axi_s_pkg) $(O_FILE_COMPILE_LIST_axi_s_pkg) + @echo "--------------------------------" + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/axi_s_pkg/axi_s.compile b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/axi_s_pkg/axi_s.compile new file mode 100644 index 00000000..96602b5a --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/axi_s_pkg/axi_s.compile @@ -0,0 +1,3 @@ +needs: + - axi_s_hvl.compile + - axi_s_hdl.compile diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/axi_s_pkg/axi_s_bfm.vinfo b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/axi_s_pkg/axi_s_bfm.vinfo new file mode 100644 index 00000000..dc6f9acc --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/axi_s_pkg/axi_s_bfm.vinfo @@ -0,0 +1,6 @@ +@use $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg_hdl.vinfo +@use axi_s_pkg_hdl.vinfo ++incdir+@vinfodir +src/axi_s_if.sv +src/axi_s_driver_bfm.sv +src/axi_s_monitor_bfm.sv diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/axi_s_pkg/axi_s_common.compile b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/axi_s_pkg/axi_s_common.compile new file mode 100644 index 00000000..cb7464be --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/axi_s_pkg/axi_s_common.compile @@ -0,0 +1,7 @@ +needs: + - $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg_hdl.compile +incdir: + - . + - ${uvm_path}/src +src: + - axi_s_pkg_hdl.sv diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/axi_s_pkg/axi_s_filelist_hdl.f b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/axi_s_pkg/axi_s_filelist_hdl.f new file mode 100644 index 00000000..99d98e31 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/axi_s_pkg/axi_s_filelist_hdl.f @@ -0,0 +1 @@ +$UVMF_VIP_LIBRARY_HOME/interface_packages/axi_s_pkg/axi_s_pkg_hdl.sv diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/axi_s_pkg/axi_s_filelist_hvl.f b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/axi_s_pkg/axi_s_filelist_hvl.f new file mode 100644 index 00000000..40ec1992 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/axi_s_pkg/axi_s_filelist_hvl.f @@ -0,0 +1 @@ +$UVMF_VIP_LIBRARY_HOME/interface_packages/axi_s_pkg/axi_s_pkg.sv \ No newline at end of file diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/axi_s_pkg/axi_s_filelist_xrtl.f b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/axi_s_pkg/axi_s_filelist_xrtl.f new file mode 100644 index 00000000..d329ce6c --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/axi_s_pkg/axi_s_filelist_xrtl.f @@ -0,0 +1,3 @@ +$UVMF_VIP_LIBRARY_HOME/interface_packages/axi_s_pkg/src/axi_s_if.sv +$UVMF_VIP_LIBRARY_HOME/interface_packages/axi_s_pkg/src/axi_s_monitor_bfm.sv +$UVMF_VIP_LIBRARY_HOME/interface_packages/axi_s_pkg/src/axi_s_driver_bfm.sv diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/axi_s_pkg/axi_s_hdl.compile b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/axi_s_pkg/axi_s_hdl.compile new file mode 100644 index 00000000..f5769a4f --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/axi_s_pkg/axi_s_hdl.compile @@ -0,0 +1,9 @@ +needs: + - $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg_hdl.compile + - ./axi_s_common.compile +incdir: + - . +src: + - src/axi_s_if.sv + - src/axi_s_monitor_bfm.sv + - src/axi_s_driver_bfm.sv diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/axi_s_pkg/axi_s_hvl.compile b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/axi_s_pkg/axi_s_hvl.compile new file mode 100644 index 00000000..d65e6473 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/axi_s_pkg/axi_s_hvl.compile @@ -0,0 +1,7 @@ +needs: + - $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg.compile + - ./axi_s_common.compile +incdir: + - . +src: + - axi_s_pkg.sv diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/axi_s_pkg/axi_s_pkg.sv b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/axi_s_pkg/axi_s_pkg.sv new file mode 100644 index 00000000..b699cccd --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/axi_s_pkg/axi_s_pkg.sv @@ -0,0 +1,77 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// PACKAGE: This file defines all of the files contained in the +// interface package that will run on the host simulator. +// +// CONTAINS: +// - +// - +// - + +// - +// - +// - + +// - +// - +// - + +// - +// - +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +package axi_s_pkg; + + import uvm_pkg::*; + import uvmf_base_pkg_hdl::*; + import uvmf_base_pkg::*; + import axi_s_pkg_hdl::*; + + `include "uvm_macros.svh" + + // pragma uvmf custom package_imports_additional begin + // pragma uvmf custom package_imports_additional end + `include "src/axi_s_macros.svh" + + export axi_s_pkg_hdl::*; + + + + // Parameters defined as HVL parameters + + `include "src/axi_s_typedefs.svh" + `include "src/axi_s_transaction.svh" + + `include "src/axi_s_configuration.svh" + `include "src/axi_s_driver.svh" + `include "src/axi_s_monitor.svh" + + `include "src/axi_s_transaction_coverage.svh" + `include "src/axi_s_sequence_base.svh" + `include "src/axi_s_random_sequence.svh" + + `include "src/axi_s_responder_sequence.svh" + `include "src/axi_s2reg_adapter.svh" + + `include "src/axi_s_agent.svh" + + // pragma uvmf custom package_item_additional begin + // UVMF_CHANGE_ME : When adding new interface sequences to the src directory + // be sure to add the sequence file here so that it will be + // compiled as part of the interface package. Be sure to place + // the new sequence after any base sequences of the new sequence. + // pragma uvmf custom package_item_additional end + +endpackage + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/axi_s_pkg/axi_s_pkg.vinfo b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/axi_s_pkg/axi_s_pkg.vinfo new file mode 100644 index 00000000..4f79b005 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/axi_s_pkg/axi_s_pkg.vinfo @@ -0,0 +1,4 @@ +@use $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg.vinfo +@use axi_s_pkg_hdl.vinfo ++incdir+@vinfodir +axi_s_pkg.sv diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/axi_s_pkg/axi_s_pkg_hdl.sv b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/axi_s_pkg/axi_s_pkg_hdl.sv new file mode 100644 index 00000000..67e47049 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/axi_s_pkg/axi_s_pkg_hdl.sv @@ -0,0 +1,38 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// PACKAGE: This file defines all of the files contained in the +// interface package that needs to be compiled and synthesized +// for running on Veloce. +// +// CONTAINS: +// - +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +package axi_s_pkg_hdl; + + import uvmf_base_pkg_hdl::*; + + // pragma uvmf custom package_imports_additional begin + // pragma uvmf custom package_imports_additional end + + // Parameters defined as HDL parameters + + `include "src/axi_s_typedefs_hdl.svh" + `include "src/axi_s_macros.svh" + + // pragma uvmf custom package_item_additional begin + // pragma uvmf custom package_item_additional end + +endpackage + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/axi_s_pkg/axi_s_pkg_hdl.vinfo b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/axi_s_pkg/axi_s_pkg_hdl.vinfo new file mode 100644 index 00000000..62905353 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/axi_s_pkg/axi_s_pkg_hdl.vinfo @@ -0,0 +1,2 @@ +@use $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg_hdl.vinfo +axi_s_pkg_hdl.sv diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/axi_s_pkg/axi_s_pkg_sve.F b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/axi_s_pkg/axi_s_pkg_sve.F new file mode 100644 index 00000000..13538815 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/axi_s_pkg/axi_s_pkg_sve.F @@ -0,0 +1,10 @@ +// UVM ++incdir+${UVM_HOME}/src +${UVM_HOME}/src/uvm_pkg.sv + +// Common UVMF files +-f ${UVMF_HOME}/common/common_sve.f + ++incdir+. +-f ${UVMF_VIP_LIBRARY_HOME}/interface_packages/axi_s_pkg/axi_s_filelist_hdl.f +-f ${UVMF_VIP_LIBRARY_HOME}/interface_packages/axi_s_pkg/axi_s_filelist_hvl.f diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/axi_s_pkg/compile.do b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/axi_s_pkg/compile.do new file mode 100644 index 00000000..6a9b5a78 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/axi_s_pkg/compile.do @@ -0,0 +1,14 @@ +# Tcl do file for compile of axi_s interface + +# pragma uvmf custom additional begin +# pragma uvmf custom additional end + + +vlog -sv -timescale 1ps/1ps -suppress 2223,2286 +incdir+$env(UVMF_VIP_LIBRARY_HOME)/interface_packages/axi_s_pkg \ + -F $env(UVMF_VIP_LIBRARY_HOME)/interface_packages/axi_s_pkg/axi_s_filelist_hdl.f + +vlog -sv -timescale 1ps/1ps -suppress 2223,2286 +incdir+$env(UVMF_VIP_LIBRARY_HOME)/interface_packages/axi_s_pkg \ + -F $env(UVMF_VIP_LIBRARY_HOME)/interface_packages/axi_s_pkg/axi_s_filelist_hvl.f + +vlog -sv -timescale 1ps/1ps -suppress 2223,2286 +incdir+$env(UVMF_VIP_LIBRARY_HOME)/interface_packages/axi_s_pkg \ + -F $env(UVMF_VIP_LIBRARY_HOME)/interface_packages/axi_s_pkg/axi_s_filelist_xrtl.f \ No newline at end of file diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/axi_s_pkg/src/axi_s2reg_adapter.svh b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/axi_s_pkg/src/axi_s2reg_adapter.svh new file mode 100644 index 00000000..fc6ac9bf --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/axi_s_pkg/src/axi_s2reg_adapter.svh @@ -0,0 +1,123 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: +// This file contains the UVM register adapter for the axi_s interface. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class axi_s2reg_adapter #( + int AW_WIDTH = 32, + int LEN = 8, + int DATA_WIDTH = 32, + int X = 16 + ) extends uvm_reg_adapter; + + `uvm_object_param_utils( axi_s2reg_adapter #( + AW_WIDTH, + LEN, + DATA_WIDTH, + X + )) + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + //-------------------------------------------------------------------- + // new + //-------------------------------------------------------------------- + function new (string name = "axi_s2reg_adapter" ); + super.new(name); + // pragma uvmf custom new begin + // UVMF_CHANGE_ME : Configure the adapter regarding byte enables and provides response. + + // Does the protocol the Agent is modeling support byte enables? + // 0 = NO + // 1 = YES + supports_byte_enable = 0; + + // Does the Agent's Driver provide separate response sequence items? + // i.e. Does the driver call seq_item_port.put() + // and do the sequences call get_response()? + // 0 = NO + // 1 = YES + provides_responses = 0; + // pragma uvmf custom new end + + endfunction: new + + //-------------------------------------------------------------------- + // reg2bus + //-------------------------------------------------------------------- + virtual function uvm_sequence_item reg2bus(const ref uvm_reg_bus_op rw); + + axi_s_transaction #( + .AW_WIDTH(AW_WIDTH), + .LEN(LEN), + .DATA_WIDTH(DATA_WIDTH), + .X(X) + ) trans_h = axi_s_transaction #( + .AW_WIDTH(AW_WIDTH), + .LEN(LEN), + .DATA_WIDTH(DATA_WIDTH), + .X(X) + )::type_id::create("trans_h"); + + // pragma uvmf custom reg2bus begin + // UVMF_CHANGE_ME : Fill in the reg2bus adapter mapping registe fields to protocol fields. + + //Adapt the following for your sequence item type + // trans_h.op = (rw.kind == UVM_READ) ? WB_READ : WB_WRITE; + //Copy over address + // trans_h.addr = rw.addr; + //Copy over write data + // trans_h.data = rw.data; + + // pragma uvmf custom reg2bus end + + // Return the adapted transaction + return trans_h; + + endfunction: reg2bus + + //-------------------------------------------------------------------- + // bus2reg + //-------------------------------------------------------------------- + virtual function void bus2reg(uvm_sequence_item bus_item, + ref uvm_reg_bus_op rw); + axi_s_transaction #( + .AW_WIDTH(AW_WIDTH), + .LEN(LEN), + .DATA_WIDTH(DATA_WIDTH), + .X(X) + ) trans_h; + if (!$cast(trans_h, bus_item)) begin + `uvm_fatal("ADAPT","Provided bus_item is not of the correct type") + return; + end + // pragma uvmf custom bus2reg begin + // UVMF_CHANGE_ME : Fill in the bus2reg adapter mapping protocol fields to register fields. + //Adapt the following for your sequence item type + //Copy over instruction type + // rw.kind = (trans_h.op == WB_WRITE) ? UVM_WRITE : UVM_READ; + //Copy over address + // rw.addr = trans_h.addr; + //Copy over read data + // rw.data = trans_h.data; + //Check for errors on the bus and return UVM_NOT_OK if there is an error + // rw.status = UVM_IS_OK; + // pragma uvmf custom bus2reg end + + endfunction: bus2reg + +endclass : axi_s2reg_adapter + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/axi_s_pkg/src/axi_s_agent.svh b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/axi_s_pkg/src/axi_s_agent.svh new file mode 100644 index 00000000..faf4da95 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/axi_s_pkg/src/axi_s_agent.svh @@ -0,0 +1,88 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: Protocol specific agent class definition +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class axi_s_agent #( + int AW_WIDTH = 32, + int LEN = 8, + int DATA_WIDTH = 32, + int X = 16 + ) extends uvmf_parameterized_agent #( + .CONFIG_T(axi_s_configuration #( + .AW_WIDTH(AW_WIDTH), + .LEN(LEN), + .DATA_WIDTH(DATA_WIDTH), + .X(X) + )), + .DRIVER_T(axi_s_driver #( + .AW_WIDTH(AW_WIDTH), + .LEN(LEN), + .DATA_WIDTH(DATA_WIDTH), + .X(X) + )), + .MONITOR_T(axi_s_monitor #( + .AW_WIDTH(AW_WIDTH), + .LEN(LEN), + .DATA_WIDTH(DATA_WIDTH), + .X(X) + )), + .COVERAGE_T(axi_s_transaction_coverage #( + .AW_WIDTH(AW_WIDTH), + .LEN(LEN), + .DATA_WIDTH(DATA_WIDTH), + .X(X) + )), + .TRANS_T(axi_s_transaction #( + .AW_WIDTH(AW_WIDTH), + .LEN(LEN), + .DATA_WIDTH(DATA_WIDTH), + .X(X) + )) + ); + + `uvm_component_param_utils( axi_s_agent #( + AW_WIDTH, + LEN, + DATA_WIDTH, + X + )) + +// pragma uvmf custom class_item_additional begin +// pragma uvmf custom class_item_additional end + +// **************************************************************************** +// FUNCTION : new() +// This function is the standard SystemVerilog constructor. +// + function new( string name = "", uvm_component parent = null ); + super.new( name, parent ); + endfunction + +// **************************************************************************** + // FUNCTION: build_phase + virtual function void build_phase(uvm_phase phase); +// pragma uvmf custom build_phase_pre_super begin +// pragma uvmf custom build_phase_pre_super end + super.build_phase(phase); + if (configuration.active_passive == ACTIVE) begin + // Place sequencer handle into configuration object + // so that it may be retrieved from configuration + // rather than using uvm_config_db + configuration.sequencer = this.sequencer; + end + endfunction + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/axi_s_pkg/src/axi_s_configuration.svh b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/axi_s_pkg/src/axi_s_configuration.svh new file mode 100644 index 00000000..2bbcfc4a --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/axi_s_pkg/src/axi_s_configuration.svh @@ -0,0 +1,219 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This class contains all variables and functions used +// to configure the axi_s agent and its bfm's. It gets the +// bfm's from the uvm_config_db for use by the agent. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class axi_s_configuration #( + int AW_WIDTH = 32, + int LEN = 8, + int DATA_WIDTH = 32, + int X = 16 + ) extends uvmf_parameterized_agent_configuration_base #( + .DRIVER_BFM_BIND_T(virtual axi_s_driver_bfm #( + .AW_WIDTH(AW_WIDTH), + .LEN(LEN), + .DATA_WIDTH(DATA_WIDTH), + .X(X) + )), + .MONITOR_BFM_BIND_T( virtual axi_s_monitor_bfm #( + .AW_WIDTH(AW_WIDTH), + .LEN(LEN), + .DATA_WIDTH(DATA_WIDTH), + .X(X) + ))); + + `uvm_object_param_utils( axi_s_configuration #( + AW_WIDTH, + LEN, + DATA_WIDTH, + X + )) + + + // Sequencer handle populated by agent + uvm_sequencer #(axi_s_transaction #( + .AW_WIDTH(AW_WIDTH), + .LEN(LEN), + .DATA_WIDTH(DATA_WIDTH), + .X(X) + ) ) sequencer; + + //Constraints for the configuration variables: + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + covergroup axi_s_configuration_cg; + // pragma uvmf custom covergroup begin + option.auto_bin_max=1024; + // pragma uvmf custom covergroup end + endgroup + + //******************************************************************* + //******************************************************************* + // Structure used to pass configuration variables to monitor and driver BFM's. + // Use to_struct function to pack variables into structure. + // Use from_struct function to unpack variables from structure. + // This structure is defined in axi_s_macros.svh + `axi_s_CONFIGURATION_STRUCT + axi_s_configuration_s axi_s_configuration_struct; + //******************************************************************* + // FUNCTION: to_struct() + // This function packs variables into a axi_s_configuration_s + // structure. The function returns the handle to the axi_s_configuration_struct. + // This function is defined in axi_s_macros.svh + `axi_s_CONFIGURATION_TO_STRUCT_FUNCTION + //******************************************************************* + // FUNCTION: from_struct() + // This function unpacks the struct provided as an argument into + // variables of this class. + // This function is defined in axi_s_macros.svh + `axi_s_CONFIGURATION_FROM_STRUCT_FUNCTION + + // **************************************************************************** + // FUNCTION : new() + // This function is the standard SystemVerilog constructor. + // + function new( string name = "" ); + super.new( name ); + // Construct the covergroup for this configuration class + axi_s_configuration_cg = new; + endfunction + + // **************************************************************************** + // FUNCTION: post_randomize() + // This function is automatically called after the randomize() function + // is executed. + // + function void post_randomize(); + super.post_randomize(); + axi_s_configuration_cg.sample(); + endfunction + + // **************************************************************************** + // FUNCTION: initialize + // This function causes the configuration to retrieve + // its virtual interface handle from the uvm_config_db. + // This function also makes itself available to its + // agent through the uvm_config_db. + // + // ARGUMENTS: + // uvmf_active_passive_t activity: + // This argument identifies the simulation level + // as either BLOCK, CHIP, SIMULATION, etc. + // + // AGENT_PATH: + // This argument identifies the path to this + // configurations agent. This configuration + // makes itself available to the agent specified + // by agent_path by placing itself into the + // uvm_config_db. + // + // INTERFACE_NAME: + // This argument identifies the string name of + // this configurations BFM's. This string + // name is used to retrieve the driver and + // monitor BFM from the uvm_config_db. + // + virtual function void initialize(uvmf_active_passive_t activity, + string agent_path, + string interface_name); + + super.initialize( activity, agent_path, interface_name); + // The covergroup is given the same name as the interface + axi_s_configuration_cg.set_inst_name(interface_name); + + // This configuration places itself into the uvm_config_db for the agent, identified by the agent_path variable, to retrieve. + uvm_config_db #( axi_s_configuration #( + .AW_WIDTH(AW_WIDTH), + .LEN(LEN), + .DATA_WIDTH(DATA_WIDTH), + .X(X) + ) + )::set( null ,agent_path,UVMF_AGENT_CONFIG, this ); + + // This configuration also places itself in the config db using the same identifier used by the interface. This allows users to access + // configuration variables and the interface through the bfm api class rather than directly accessing the BFM. This is useful for + // accessingthe BFM when using Veloce + uvm_config_db #( axi_s_configuration #( + .AW_WIDTH(AW_WIDTH), + .LEN(LEN), + .DATA_WIDTH(DATA_WIDTH), + .X(X) + ) + )::set( null ,UVMF_CONFIGURATIONS, interface_name, this ); + + axi_s_configuration_cg.set_inst_name($sformatf("axi_s_configuration_cg_%s",get_full_name())); + +// This code is to aid in debugging parameter mismatches between the BFM and its corresponding agent. +// Enable this debug by setting UVM_VERBOSITY to UVM_DEBUG +// Setting UVM_VERBOSITY to UVM_DEBUG causes all BFM's and all agents to display their parameter settings. +// All of the messages from this feature have a UVM messaging id value of "CFG" +// The transcript or run.log can be parsed to ensure BFM parameter settings match its corresponding agents parameter settings. + `uvm_info("CFG", + $psprintf("The agent at '%s' is using interface named %s has the following parameters: AW_WIDTH=%x LEN=%x DATA_WIDTH=%x X=%x ", agent_path, interface_name, AW_WIDTH ,LEN ,DATA_WIDTH ,X ), + UVM_DEBUG) + + // pragma uvmf custom initialize begin + // This controls whether or not the agent returns a transaction handle in the driver when calling + // item_done() back into the sequencer or not. If set to 1, a transaction is sent back which means + // the sequence on the other end must use the get_response() part of the driver/sequence API. If + // this doesn't occur, there will eventually be response_queue overflow errors during the test. + return_transaction_response = 1'b0; + + // pragma uvmf custom initialize end + + endfunction + + // **************************************************************************** + // TASK: wait_for_reset + // *[Required]* Blocks until reset is released. The wait_for_reset operation is performed + // by a task in the monitor bfm. + virtual task wait_for_reset(); + monitor_bfm.wait_for_reset(); + endtask + + // **************************************************************************** + // TASK: wait_for_num_clocks + // *[Required]* Blocks until specified number of clocks have elapsed. The wait_for_num_clocks + // operation is performed by a task in the monitor bfm. + virtual task wait_for_num_clocks(int clocks); + monitor_bfm.wait_for_num_clocks(clocks); + endtask + + // **************************************************************************** + // FUNCTION : convert2string() + // This function is used to convert variables in this class into a string for log messaging. + // + virtual function string convert2string (); + // pragma uvmf custom convert2string begin + return $sformatf(""); + // pragma uvmf custom convert2string end + endfunction + + // **************************************************************************** + // FUNCTION: get_sequencer + function uvm_sequencer #(axi_s_transaction#( + .AW_WIDTH(AW_WIDTH), + .LEN(LEN), + .DATA_WIDTH(DATA_WIDTH), + .X(X) + )) get_sequencer(); + return sequencer; + endfunction + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/axi_s_pkg/src/axi_s_driver.svh b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/axi_s_pkg/src/axi_s_driver.svh new file mode 100644 index 00000000..7b6765cf --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/axi_s_pkg/src/axi_s_driver.svh @@ -0,0 +1,121 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This class passes transactions between the sequencer +// and the BFM driver interface. It accesses the driver BFM +// through the bfm handle. This driver +// passes transactions to the driver BFM through the access +// task. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class axi_s_driver #( + int AW_WIDTH = 32, + int LEN = 8, + int DATA_WIDTH = 32, + int X = 16 + ) extends uvmf_driver_base #( + .CONFIG_T(axi_s_configuration #( + .AW_WIDTH(AW_WIDTH), + .LEN(LEN), + .DATA_WIDTH(DATA_WIDTH), + .X(X) + ) ), + .BFM_BIND_T(virtual axi_s_driver_bfm #( + .AW_WIDTH(AW_WIDTH), + .LEN(LEN), + .DATA_WIDTH(DATA_WIDTH), + .X(X) + ) ), + .REQ(axi_s_transaction #( + .AW_WIDTH(AW_WIDTH), + .LEN(LEN), + .DATA_WIDTH(DATA_WIDTH), + .X(X) + ) ), + .RSP(axi_s_transaction #( + .AW_WIDTH(AW_WIDTH), + .LEN(LEN), + .DATA_WIDTH(DATA_WIDTH), + .X(X) + ) )); + + `uvm_component_param_utils( axi_s_driver #( + AW_WIDTH, + LEN, + DATA_WIDTH, + X + )) +//******************************************************************* +// Macros that define structs located in axi_s_macros.svh +//******************************************************************* +// Initiator macro used by axi_s_driver and axi_s_driver_bfm +// to communicate initiator driven data to axi_s_driver_bfm. +`axi_s_INITIATOR_STRUCT + axi_s_initiator_s axi_s_initiator_struct; +//******************************************************************* +// Responder macro used by axi_s_driver and axi_s_driver_bfm +// to communicate Responder driven data to axi_s_driver_bfm. +`axi_s_RESPONDER_STRUCT + axi_s_responder_s axi_s_responder_struct; + +// pragma uvmf custom class_item_additional begin +// pragma uvmf custom class_item_additional end + +// **************************************************************************** +// This function is the standard SystemVerilog constructor. +// + function new( string name = "", uvm_component parent=null ); + super.new( name, parent ); + endfunction + +// **************************************************************************** +// This function sends configuration object variables to the driver BFM +// using the configuration struct. +// + virtual function void configure(input CONFIG_T cfg); + bfm.configure( cfg.to_struct() ); + endfunction + +// **************************************************************************** +// This function places a handle to this class in the proxy variable in the +// driver BFM. This allows the driver BFM to call tasks and function within this class. +// + virtual function void set_bfm_proxy_handle(); + bfm.proxy = this; endfunction + +// **************************************************************************** +// This task is called by the run_phase in uvmf_driver_base. + virtual task access( inout REQ txn ); +// pragma uvmf custom access begin + if (configuration.initiator_responder==RESPONDER) begin + // Complete current transfer and wait for next transfer + bfm.respond_and_wait_for_next_transfer( + axi_s_initiator_struct, + txn.to_responder_struct() + ); + // Unpack information about initiated transfer received by this responder + txn.from_initiator_struct(axi_s_initiator_struct); + end else begin + // Initiate a transfer and get response + bfm.initiate_and_get_response( + txn.to_initiator_struct(), + axi_s_responder_struct + ); + // Unpack transfer response information received by this initiator + txn.from_responder_struct(axi_s_responder_struct); + end +// pragma uvmf custom access end + endtask + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/axi_s_pkg/src/axi_s_driver_bfm.sv b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/axi_s_pkg/src/axi_s_driver_bfm.sv new file mode 100644 index 00000000..c2f44c62 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/axi_s_pkg/src/axi_s_driver_bfm.sv @@ -0,0 +1,765 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: +// This interface performs the axi_s signal driving. It is +// accessed by the uvm axi_s driver through a virtual interface +// handle in the axi_s configuration. It drives the singals passed +// in through the port connection named bus of type axi_s_if. +// +// Input signals from the axi_s_if are assigned to an internal input +// signal with a _i suffix. The _i signal should be used for sampling. +// +// The input signal connections are as follows: +// bus.signal -> signal_i +// +// This bfm drives signals with a _o suffix. These signals +// are driven onto signals within axi_s_if based on INITIATOR/RESPONDER and/or +// ARBITRATION/GRANT status. +// +// The output signal connections are as follows: +// signal_o -> bus.signal +// +// +// Interface functions and tasks used by UVM components: +// +// configure: +// This function gets configuration attributes from the +// UVM driver to set any required BFM configuration +// variables such as 'initiator_responder'. +// +// initiate_and_get_response: +// This task is used to perform signaling activity for initiating +// a protocol transfer. The task initiates the transfer, using +// input data from the initiator struct. Then the task captures +// response data, placing the data into the response struct. +// The response struct is returned to the driver class. +// +// respond_and_wait_for_next_transfer: +// This task is used to complete a current transfer as a responder +// and then wait for the initiator to start the next transfer. +// The task uses data in the responder struct to drive protocol +// signals to complete the transfer. The task then waits for +// the next transfer. Once the next transfer begins, data from +// the initiator is placed into the initiator struct and sent +// to the responder sequence for processing to determine +// what data to respond with. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +import uvmf_base_pkg_hdl::*; +import axi_s_pkg_hdl::*; +`include "src/axi_s_macros.svh" + +interface axi_s_driver_bfm #( + int AW_WIDTH = 32, + int LEN = 8, + int DATA_WIDTH = 32, + int X = 16 + ) + (axi_s_if bus); + // The following pragma and additional ones in-lined further below are for running this BFM on Veloce + // pragma attribute axi_s_driver_bfm partition_interface_xif + +`ifndef XRTL +// This code is to aid in debugging parameter mismatches between the BFM and its corresponding agent. +// Enable this debug by setting UVM_VERBOSITY to UVM_DEBUG +// Setting UVM_VERBOSITY to UVM_DEBUG causes all BFM's and all agents to display their parameter settings. +// All of the messages from this feature have a UVM messaging id value of "CFG" +// The transcript or run.log can be parsed to ensure BFM parameter settings match its corresponding agents parameter settings. +import uvm_pkg::*; +`include "uvm_macros.svh" +initial begin : bfm_vs_agent_parameter_debug + `uvm_info("CFG", + $psprintf("The BFM at '%m' has the following parameters: AW_WIDTH=%x LEN=%x DATA_WIDTH=%x X=%x ", AW_WIDTH,LEN,DATA_WIDTH,X), + UVM_DEBUG) +end +`endif + + // Config value to determine if this is an initiator or a responder + uvmf_initiator_responder_t initiator_responder; + // Custom configuration variables. + // These are set using the configure function which is called during the UVM connect_phase + + logic axi_clk_i; + logic rst_i; + + // Signal list (all signals are capable of being inputs and outputs for the sake + // of supporting both INITIATOR and RESPONDER mode operation. Expectation is that + // directionality in the config file was from the point-of-view of the INITIATOR + + // INITIATOR mode input signals + tri awvalid_i; + reg awvalid_o = 'bz; + tri [AW_WIDTH-1:0] awaddr_i; + reg [AW_WIDTH-1:0] awaddr_o = 'bz; + tri [2:0] awsize_i; + reg [2:0] awsize_o = 'bz; + tri [1:0] awburst_i; + reg [1:0] awburst_o = 'bz; + tri [3:0] awcache_i; + reg [3:0] awcache_o = 'bz; + tri [2:0] awprot_i; + reg [2:0] awprot_o = 'bz; + tri [X-1:0] awid_i; + reg [X-1:0] awid_o = 'bz; + tri [LEN-1:0] awlen_i; + reg [LEN-1:0] awlen_o = 'bz; + tri awlock_i; + reg awlock_o = 'bz; + tri [3:0] awqos_i; + reg [3:0] awqos_o = 'bz; + tri [3:0] awregion_i; + reg [3:0] awregion_o = 'bz; + tri [X-1:0] awuser_i; + reg [X-1:0] awuser_o = 'bz; + tri wvalid_i; + reg wvalid_o = 'bz; + tri wlast_i; + reg wlast_o = 'bz; + tri [DATA_WIDTH-1:0] wdata_i; + reg [DATA_WIDTH-1:0] wdata_o = 'bz; + tri [DATA_WIDTH/8-1:0] wstrb_i; + reg [DATA_WIDTH/8-1:0] wstrb_o = 'bz; + tri [X-1:0] wid_i; + reg [X-1:0] wid_o = 'bz; + tri [X-1:0] wuser_i; + reg [X-1:0] wuser_o = 'bz; + tri [1:0] bresp_i; + reg [1:0] bresp_o = 'bz; + tri arvalid_i; + reg arvalid_o = 'bz; + tri [AW_WIDTH-1:0] araddr_i; + reg [AW_WIDTH-1:0] araddr_o = 'bz; + tri [2:0] arsize_i; + reg [2:0] arsize_o = 'bz; + tri [1:0] arburst_i; + reg [1:0] arburst_o = 'bz; + tri [3:0] arcache_i; + reg [3:0] arcache_o = 'bz; + tri [2:0] arprot_i; + reg [2:0] arprot_o = 'bz; + tri [X-1:0] arid_i; + reg [X-1:0] arid_o = 'bz; + tri [LEN-1:0] arlen_i; + reg [LEN-1:0] arlen_o = 'bz; + tri arlock_i; + reg arlock_o = 'bz; + tri [3:0] arqos_i; + reg [3:0] arqos_o = 'bz; + tri [3:0] aregion_i; + reg [3:0] aregion_o = 'bz; + tri [X-1:0] aruser_i; + reg [X-1:0] aruser_o = 'bz; + tri rready_i; + reg rready_o = 'bz; + + // INITIATOR mode output signals + tri awready_i; + reg awready_o = 'bz; + tri wready_i; + reg wready_o = 'bz; + tri bwvalid_i; + reg bwvalid_o = 'bz; + tri bwready_i; + reg bwready_o = 'bz; + tri [X-1:0] bid_i; + reg [X-1:0] bid_o = 'bz; + tri [X-1:0] buser_i; + reg [X-1:0] buser_o = 'bz; + tri aready_i; + reg aready_o = 'bz; + tri rvalid_i; + reg rvalid_o = 'bz; + tri rlast_i; + reg rlast_o = 'bz; + tri [DATA_WIDTH-1:0] rdata_i; + reg [DATA_WIDTH-1:0] rdata_o = 'bz; + tri [X-1:0] rid_i; + reg [X-1:0] rid_o = 'bz; + tri [X-1:0] ruser_i; + reg [X-1:0] ruser_o = 'bz; + tri [1:0] rresp_i; + reg [1:0] rresp_o = 'bz; + + // Bi-directional signals + + + assign axi_clk_i = bus.axi_clk; + assign rst_i = bus.rst; + + // These are signals marked as 'input' by the config file, but the signals will be + // driven by this BFM if put into RESPONDER mode (flipping all signal directions around) + assign awvalid_i = bus.awvalid; + assign bus.awvalid = (initiator_responder == RESPONDER) ? awvalid_o : 'bz; + assign awaddr_i = bus.awaddr; + assign bus.awaddr = (initiator_responder == RESPONDER) ? awaddr_o : 'bz; + assign awsize_i = bus.awsize; + assign bus.awsize = (initiator_responder == RESPONDER) ? awsize_o : 'bz; + assign awburst_i = bus.awburst; + assign bus.awburst = (initiator_responder == RESPONDER) ? awburst_o : 'bz; + assign awcache_i = bus.awcache; + assign bus.awcache = (initiator_responder == RESPONDER) ? awcache_o : 'bz; + assign awprot_i = bus.awprot; + assign bus.awprot = (initiator_responder == RESPONDER) ? awprot_o : 'bz; + assign awid_i = bus.awid; + assign bus.awid = (initiator_responder == RESPONDER) ? awid_o : 'bz; + assign awlen_i = bus.awlen; + assign bus.awlen = (initiator_responder == RESPONDER) ? awlen_o : 'bz; + assign awlock_i = bus.awlock; + assign bus.awlock = (initiator_responder == RESPONDER) ? awlock_o : 'bz; + assign awqos_i = bus.awqos; + assign bus.awqos = (initiator_responder == RESPONDER) ? awqos_o : 'bz; + assign awregion_i = bus.awregion; + assign bus.awregion = (initiator_responder == RESPONDER) ? awregion_o : 'bz; + assign awuser_i = bus.awuser; + assign bus.awuser = (initiator_responder == RESPONDER) ? awuser_o : 'bz; + assign wvalid_i = bus.wvalid; + assign bus.wvalid = (initiator_responder == RESPONDER) ? wvalid_o : 'bz; + assign wlast_i = bus.wlast; + assign bus.wlast = (initiator_responder == RESPONDER) ? wlast_o : 'bz; + assign wdata_i = bus.wdata; + assign bus.wdata = (initiator_responder == RESPONDER) ? wdata_o : 'bz; + assign wstrb_i = bus.wstrb; + assign bus.wstrb = (initiator_responder == RESPONDER) ? wstrb_o : 'bz; + assign wid_i = bus.wid; + assign bus.wid = (initiator_responder == RESPONDER) ? wid_o : 'bz; + assign wuser_i = bus.wuser; + assign bus.wuser = (initiator_responder == RESPONDER) ? wuser_o : 'bz; + assign bresp_i = bus.bresp; + assign bus.bresp = (initiator_responder == RESPONDER) ? bresp_o : 'bz; + assign arvalid_i = bus.arvalid; + assign bus.arvalid = (initiator_responder == RESPONDER) ? arvalid_o : 'bz; + assign araddr_i = bus.araddr; + assign bus.araddr = (initiator_responder == RESPONDER) ? araddr_o : 'bz; + assign arsize_i = bus.arsize; + assign bus.arsize = (initiator_responder == RESPONDER) ? arsize_o : 'bz; + assign arburst_i = bus.arburst; + assign bus.arburst = (initiator_responder == RESPONDER) ? arburst_o : 'bz; + assign arcache_i = bus.arcache; + assign bus.arcache = (initiator_responder == RESPONDER) ? arcache_o : 'bz; + assign arprot_i = bus.arprot; + assign bus.arprot = (initiator_responder == RESPONDER) ? arprot_o : 'bz; + assign arid_i = bus.arid; + assign bus.arid = (initiator_responder == RESPONDER) ? arid_o : 'bz; + assign arlen_i = bus.arlen; + assign bus.arlen = (initiator_responder == RESPONDER) ? arlen_o : 'bz; + assign arlock_i = bus.arlock; + assign bus.arlock = (initiator_responder == RESPONDER) ? arlock_o : 'bz; + assign arqos_i = bus.arqos; + assign bus.arqos = (initiator_responder == RESPONDER) ? arqos_o : 'bz; + assign aregion_i = bus.aregion; + assign bus.aregion = (initiator_responder == RESPONDER) ? aregion_o : 'bz; + assign aruser_i = bus.aruser; + assign bus.aruser = (initiator_responder == RESPONDER) ? aruser_o : 'bz; + assign rready_i = bus.rready; + assign bus.rready = (initiator_responder == RESPONDER) ? rready_o : 'bz; + + + // These are signals marked as 'output' by the config file, but the outputs will + // not be driven by this BFM unless placed in INITIATOR mode. + assign bus.awready = (initiator_responder == INITIATOR) ? awready_o : 'bz; + assign awready_i = bus.awready; + assign bus.wready = (initiator_responder == INITIATOR) ? wready_o : 'bz; + assign wready_i = bus.wready; + assign bus.bwvalid = (initiator_responder == INITIATOR) ? bwvalid_o : 'bz; + assign bwvalid_i = bus.bwvalid; + assign bus.bwready = (initiator_responder == INITIATOR) ? bwready_o : 'bz; + assign bwready_i = bus.bwready; + assign bus.bid = (initiator_responder == INITIATOR) ? bid_o : 'bz; + assign bid_i = bus.bid; + assign bus.buser = (initiator_responder == INITIATOR) ? buser_o : 'bz; + assign buser_i = bus.buser; + assign bus.aready = (initiator_responder == INITIATOR) ? aready_o : 'bz; + assign aready_i = bus.aready; + assign bus.rvalid = (initiator_responder == INITIATOR) ? rvalid_o : 'bz; + assign rvalid_i = bus.rvalid; + assign bus.rlast = (initiator_responder == INITIATOR) ? rlast_o : 'bz; + assign rlast_i = bus.rlast; + assign bus.rdata = (initiator_responder == INITIATOR) ? rdata_o : 'bz; + assign rdata_i = bus.rdata; + assign bus.rid = (initiator_responder == INITIATOR) ? rid_o : 'bz; + assign rid_i = bus.rid; + assign bus.ruser = (initiator_responder == INITIATOR) ? ruser_o : 'bz; + assign ruser_i = bus.ruser; + assign bus.rresp = (initiator_responder == INITIATOR) ? rresp_o : 'bz; + assign rresp_i = bus.rresp; + + // Proxy handle to UVM driver + axi_s_pkg::axi_s_driver #( + .AW_WIDTH(AW_WIDTH), + .LEN(LEN), + .DATA_WIDTH(DATA_WIDTH), + .X(X) + ) proxy; + // pragma tbx oneway proxy.my_function_name_in_uvm_driver + + // **************************************************************************** + // **************************************************************************** + // Macros that define structs located in axi_s_macros.svh + // **************************************************************************** + // Struct for passing configuration data from axi_s_driver to this BFM + // **************************************************************************** + `axi_s_CONFIGURATION_STRUCT + // **************************************************************************** + // Structs for INITIATOR and RESPONDER data flow + //******************************************************************* + // Initiator macro used by axi_s_driver and axi_s_driver_bfm + // to communicate initiator driven data to axi_s_driver_bfm. + `axi_s_INITIATOR_STRUCT + axi_s_initiator_s initiator_struct; + // Responder macro used by axi_s_driver and axi_s_driver_bfm + // to communicate Responder driven data to axi_s_driver_bfm. + `axi_s_RESPONDER_STRUCT + axi_s_responder_s responder_struct; + + // **************************************************************************** +// pragma uvmf custom reset_condition_and_response begin + // Always block used to return signals to reset value upon assertion of reset + always @( negedge rst_i ) + begin + // RESPONDER mode output signals + awvalid_o <= 'bz; + awaddr_o <= 'bz; + awsize_o <= 'bz; + awburst_o <= 'bz; + awcache_o <= 'bz; + awprot_o <= 'bz; + awid_o <= 'bz; + awlen_o <= 'bz; + awlock_o <= 'bz; + awqos_o <= 'bz; + awregion_o <= 'bz; + awuser_o <= 'bz; + wvalid_o <= 'bz; + wlast_o <= 'bz; + wdata_o <= 'bz; + wstrb_o <= 'bz; + wid_o <= 'bz; + wuser_o <= 'bz; + bresp_o <= 'bz; + arvalid_o <= 'bz; + araddr_o <= 'bz; + arsize_o <= 'bz; + arburst_o <= 'bz; + arcache_o <= 'bz; + arprot_o <= 'bz; + arid_o <= 'bz; + arlen_o <= 'bz; + arlock_o <= 'bz; + arqos_o <= 'bz; + aregion_o <= 'bz; + aruser_o <= 'bz; + rready_o <= 'bz; + // INITIATOR mode output signals + awready_o <= 'bz; + wready_o <= 'bz; + bwvalid_o <= 'bz; + bwready_o <= 'bz; + bid_o <= 'bz; + buser_o <= 'bz; + aready_o <= 'bz; + rvalid_o <= 'bz; + rlast_o <= 'bz; + rdata_o <= 'bz; + rid_o <= 'bz; + ruser_o <= 'bz; + rresp_o <= 'bz; + // Bi-directional signals + + end +// pragma uvmf custom reset_condition_and_response end + + // pragma uvmf custom interface_item_additional begin + // pragma uvmf custom interface_item_additional end + + //****************************************************************** + // The configure() function is used to pass agent configuration + // variables to the driver BFM. It is called by the driver within + // the agent at the beginning of the simulation. It may be called + // during the simulation if agent configuration variables are updated + // and the driver BFM needs to be aware of the new configuration + // variables. + // + + function void configure(axi_s_configuration_s axi_s_configuration_arg); // pragma tbx xtf + initiator_responder = axi_s_configuration_arg.initiator_responder; + // pragma uvmf custom configure begin + // pragma uvmf custom configure end + endfunction + +// pragma uvmf custom initiate_and_get_response begin +// **************************************************************************** +// UVMF_CHANGE_ME +// This task is used by an initator. The task first initiates a transfer then +// waits for the responder to complete the transfer. + task initiate_and_get_response( + // This argument passes transaction variables used by an initiator + // to perform the initial part of a protocol transfer. The values + // come from a sequence item created in a sequence. + input axi_s_initiator_s axi_s_initiator_struct, + // This argument is used to send data received from the responder + // back to the sequence item. The sequence item is returned to the sequence. + output axi_s_responder_s axi_s_responder_struct + );// pragma tbx xtf + // + // Members within the axi_s_initiator_struct: + // bit awvalid ; + // bit awready ; + // bit [AW_WIDTH-1:0] awaddr ; + // bit awsize ; + // bit awburst ; + // bit awcache ; + // bit awprot ; + // bit [X-1:0] awid ; + // bit [LEN-1:0] awlen ; + // bit awlock ; + // bit awqos ; + // bit awregion ; + // bit [X-1:0] awuser ; + // bit wvalid ; + // bit wready ; + // bit wlast ; + // bit [DATA_WIDTH-1:0] wdata ; + // bit [DATA_WIDTH/8-1:0] wstrb ; + // bit [X-1:0] wid ; + // bit [X-1:0] wuser ; + // bit bwvalid ; + // bit bwready ; + // bit bresp ; + // bit [X-1:0] bid ; + // bit [X-1:0] buser ; + // bit arvalid ; + // bit aready ; + // bit [AW_WIDTH-1:0] araddr ; + // bit arsize ; + // bit arburst ; + // bit arcache ; + // bit arprot ; + // bit [X-1:0] arid ; + // bit [LEN-1:0] arlen ; + // bit arlock ; + // bit arqos ; + // bit aregion ; + // bit [X-1:0] aruser ; + // bit rvalid ; + // bit rready ; + // bit rlast ; + // bit [DATA_WIDTH-1:0] rdata ; + // bit [X-1:0] rid ; + // bit [X-1:0] ruser ; + // bit rresp ; + // Members within the axi_s_responder_struct: + // bit awvalid ; + // bit awready ; + // bit [AW_WIDTH-1:0] awaddr ; + // bit awsize ; + // bit awburst ; + // bit awcache ; + // bit awprot ; + // bit [X-1:0] awid ; + // bit [LEN-1:0] awlen ; + // bit awlock ; + // bit awqos ; + // bit awregion ; + // bit [X-1:0] awuser ; + // bit wvalid ; + // bit wready ; + // bit wlast ; + // bit [DATA_WIDTH-1:0] wdata ; + // bit [DATA_WIDTH/8-1:0] wstrb ; + // bit [X-1:0] wid ; + // bit [X-1:0] wuser ; + // bit bwvalid ; + // bit bwready ; + // bit bresp ; + // bit [X-1:0] bid ; + // bit [X-1:0] buser ; + // bit arvalid ; + // bit aready ; + // bit [AW_WIDTH-1:0] araddr ; + // bit arsize ; + // bit arburst ; + // bit arcache ; + // bit arprot ; + // bit [X-1:0] arid ; + // bit [LEN-1:0] arlen ; + // bit arlock ; + // bit arqos ; + // bit aregion ; + // bit [X-1:0] aruser ; + // bit rvalid ; + // bit rready ; + // bit rlast ; + // bit [DATA_WIDTH-1:0] rdata ; + // bit [X-1:0] rid ; + // bit [X-1:0] ruser ; + // bit rresp ; + initiator_struct = axi_s_initiator_struct; + // + // Reference code; + // How to wait for signal value + // while (control_signal == 1'b1) @(posedge axi_clk_i); + // + // How to assign a responder struct member, named xyz, from a signal. + // All available initiator input and inout signals listed. + // Initiator input signals + // axi_s_responder_struct.xyz = awvalid_i; // + // axi_s_responder_struct.xyz = awaddr_i; // [AW_WIDTH-1:0] + // axi_s_responder_struct.xyz = awsize_i; // [2:0] + // axi_s_responder_struct.xyz = awburst_i; // [1:0] + // axi_s_responder_struct.xyz = awcache_i; // [3:0] + // axi_s_responder_struct.xyz = awprot_i; // [2:0] + // axi_s_responder_struct.xyz = awid_i; // [X-1:0] + // axi_s_responder_struct.xyz = awlen_i; // [LEN-1:0] + // axi_s_responder_struct.xyz = awlock_i; // + // axi_s_responder_struct.xyz = awqos_i; // [3:0] + // axi_s_responder_struct.xyz = awregion_i; // [3:0] + // axi_s_responder_struct.xyz = awuser_i; // [X-1:0] + // axi_s_responder_struct.xyz = wvalid_i; // + // axi_s_responder_struct.xyz = wlast_i; // + // axi_s_responder_struct.xyz = wdata_i; // [DATA_WIDTH-1:0] + // axi_s_responder_struct.xyz = wstrb_i; // [DATA_WIDTH/8-1:0] + // axi_s_responder_struct.xyz = wid_i; // [X-1:0] + // axi_s_responder_struct.xyz = wuser_i; // [X-1:0] + // axi_s_responder_struct.xyz = bresp_i; // [1:0] + // axi_s_responder_struct.xyz = arvalid_i; // + // axi_s_responder_struct.xyz = araddr_i; // [AW_WIDTH-1:0] + // axi_s_responder_struct.xyz = arsize_i; // [2:0] + // axi_s_responder_struct.xyz = arburst_i; // [1:0] + // axi_s_responder_struct.xyz = arcache_i; // [3:0] + // axi_s_responder_struct.xyz = arprot_i; // [2:0] + // axi_s_responder_struct.xyz = arid_i; // [X-1:0] + // axi_s_responder_struct.xyz = arlen_i; // [LEN-1:0] + // axi_s_responder_struct.xyz = arlock_i; // + // axi_s_responder_struct.xyz = arqos_i; // [3:0] + // axi_s_responder_struct.xyz = aregion_i; // [3:0] + // axi_s_responder_struct.xyz = aruser_i; // [X-1:0] + // axi_s_responder_struct.xyz = rready_i; // + // Initiator inout signals + // How to assign a signal from an initiator struct member named xyz. + // All available initiator output and inout signals listed. + // Notice the _o. Those are storage variables that allow for procedural assignment. + // Initiator output signals + // awready_o <= axi_s_initiator_struct.xyz; // + // wready_o <= axi_s_initiator_struct.xyz; // + // bwvalid_o <= axi_s_initiator_struct.xyz; // + // bwready_o <= axi_s_initiator_struct.xyz; // + // bid_o <= axi_s_initiator_struct.xyz; // [X-1:0] + // buser_o <= axi_s_initiator_struct.xyz; // [X-1:0] + // aready_o <= axi_s_initiator_struct.xyz; // + // rvalid_o <= axi_s_initiator_struct.xyz; // + // rlast_o <= axi_s_initiator_struct.xyz; // + // rdata_o <= axi_s_initiator_struct.xyz; // [DATA_WIDTH-1:0] + // rid_o <= axi_s_initiator_struct.xyz; // [X-1:0] + // ruser_o <= axi_s_initiator_struct.xyz; // [X-1:0] + // rresp_o <= axi_s_initiator_struct.xyz; // [1:0] + // Initiator inout signals + // Initiate a transfer using the data received. + @(posedge axi_clk_i); + @(posedge axi_clk_i); + // Wait for the responder to complete the transfer then place the responder data into + // axi_s_responder_struct. + @(posedge axi_clk_i); + @(posedge axi_clk_i); + responder_struct = axi_s_responder_struct; + endtask +// pragma uvmf custom initiate_and_get_response end + +// pragma uvmf custom respond_and_wait_for_next_transfer begin +// **************************************************************************** +// The first_transfer variable is used to prevent completing a transfer in the +// first call to this task. For the first call to this task, there is not +// current transfer to complete. +bit first_transfer=1; + +// UVMF_CHANGE_ME +// This task is used by a responder. The task first completes the current +// transfer in progress then waits for the initiator to start the next transfer. + task respond_and_wait_for_next_transfer( + // This argument is used to send data received from the initiator + // back to the sequence item. The sequence determines how to respond. + output axi_s_initiator_s axi_s_initiator_struct, + // This argument passes transaction variables used by a responder + // to complete a protocol transfer. The values come from a sequence item. + input axi_s_responder_s axi_s_responder_struct + );// pragma tbx xtf + // Variables within the axi_s_initiator_struct: + // bit awvalid ; + // bit awready ; + // bit [AW_WIDTH-1:0] awaddr ; + // bit awsize ; + // bit awburst ; + // bit awcache ; + // bit awprot ; + // bit [X-1:0] awid ; + // bit [LEN-1:0] awlen ; + // bit awlock ; + // bit awqos ; + // bit awregion ; + // bit [X-1:0] awuser ; + // bit wvalid ; + // bit wready ; + // bit wlast ; + // bit [DATA_WIDTH-1:0] wdata ; + // bit [DATA_WIDTH/8-1:0] wstrb ; + // bit [X-1:0] wid ; + // bit [X-1:0] wuser ; + // bit bwvalid ; + // bit bwready ; + // bit bresp ; + // bit [X-1:0] bid ; + // bit [X-1:0] buser ; + // bit arvalid ; + // bit aready ; + // bit [AW_WIDTH-1:0] araddr ; + // bit arsize ; + // bit arburst ; + // bit arcache ; + // bit arprot ; + // bit [X-1:0] arid ; + // bit [LEN-1:0] arlen ; + // bit arlock ; + // bit arqos ; + // bit aregion ; + // bit [X-1:0] aruser ; + // bit rvalid ; + // bit rready ; + // bit rlast ; + // bit [DATA_WIDTH-1:0] rdata ; + // bit [X-1:0] rid ; + // bit [X-1:0] ruser ; + // bit rresp ; + // Variables within the axi_s_responder_struct: + // bit awvalid ; + // bit awready ; + // bit [AW_WIDTH-1:0] awaddr ; + // bit awsize ; + // bit awburst ; + // bit awcache ; + // bit awprot ; + // bit [X-1:0] awid ; + // bit [LEN-1:0] awlen ; + // bit awlock ; + // bit awqos ; + // bit awregion ; + // bit [X-1:0] awuser ; + // bit wvalid ; + // bit wready ; + // bit wlast ; + // bit [DATA_WIDTH-1:0] wdata ; + // bit [DATA_WIDTH/8-1:0] wstrb ; + // bit [X-1:0] wid ; + // bit [X-1:0] wuser ; + // bit bwvalid ; + // bit bwready ; + // bit bresp ; + // bit [X-1:0] bid ; + // bit [X-1:0] buser ; + // bit arvalid ; + // bit aready ; + // bit [AW_WIDTH-1:0] araddr ; + // bit arsize ; + // bit arburst ; + // bit arcache ; + // bit arprot ; + // bit [X-1:0] arid ; + // bit [LEN-1:0] arlen ; + // bit arlock ; + // bit arqos ; + // bit aregion ; + // bit [X-1:0] aruser ; + // bit rvalid ; + // bit rready ; + // bit rlast ; + // bit [DATA_WIDTH-1:0] rdata ; + // bit [X-1:0] rid ; + // bit [X-1:0] ruser ; + // bit rresp ; + // Reference code; + // How to wait for signal value + // while (control_signal == 1'b1) @(posedge axi_clk_i); + // + // How to assign a responder struct member, named xyz, from a signal. + // All available responder input and inout signals listed. + // Responder input signals + // axi_s_responder_struct.xyz = awready_i; // + // axi_s_responder_struct.xyz = wready_i; // + // axi_s_responder_struct.xyz = bwvalid_i; // + // axi_s_responder_struct.xyz = bwready_i; // + // axi_s_responder_struct.xyz = bid_i; // [X-1:0] + // axi_s_responder_struct.xyz = buser_i; // [X-1:0] + // axi_s_responder_struct.xyz = aready_i; // + // axi_s_responder_struct.xyz = rvalid_i; // + // axi_s_responder_struct.xyz = rlast_i; // + // axi_s_responder_struct.xyz = rdata_i; // [DATA_WIDTH-1:0] + // axi_s_responder_struct.xyz = rid_i; // [X-1:0] + // axi_s_responder_struct.xyz = ruser_i; // [X-1:0] + // axi_s_responder_struct.xyz = rresp_i; // [1:0] + // Responder inout signals + // How to assign a signal, named xyz, from an initiator struct member. + // All available responder output and inout signals listed. + // Notice the _o. Those are storage variables that allow for procedural assignment. + // Responder output signals + // awvalid_o <= axi_s_initiator_struct.xyz; // + // awaddr_o <= axi_s_initiator_struct.xyz; // [AW_WIDTH-1:0] + // awsize_o <= axi_s_initiator_struct.xyz; // [2:0] + // awburst_o <= axi_s_initiator_struct.xyz; // [1:0] + // awcache_o <= axi_s_initiator_struct.xyz; // [3:0] + // awprot_o <= axi_s_initiator_struct.xyz; // [2:0] + // awid_o <= axi_s_initiator_struct.xyz; // [X-1:0] + // awlen_o <= axi_s_initiator_struct.xyz; // [LEN-1:0] + // awlock_o <= axi_s_initiator_struct.xyz; // + // awqos_o <= axi_s_initiator_struct.xyz; // [3:0] + // awregion_o <= axi_s_initiator_struct.xyz; // [3:0] + // awuser_o <= axi_s_initiator_struct.xyz; // [X-1:0] + // wvalid_o <= axi_s_initiator_struct.xyz; // + // wlast_o <= axi_s_initiator_struct.xyz; // + // wdata_o <= axi_s_initiator_struct.xyz; // [DATA_WIDTH-1:0] + // wstrb_o <= axi_s_initiator_struct.xyz; // [DATA_WIDTH/8-1:0] + // wid_o <= axi_s_initiator_struct.xyz; // [X-1:0] + // wuser_o <= axi_s_initiator_struct.xyz; // [X-1:0] + // bresp_o <= axi_s_initiator_struct.xyz; // [1:0] + // arvalid_o <= axi_s_initiator_struct.xyz; // + // araddr_o <= axi_s_initiator_struct.xyz; // [AW_WIDTH-1:0] + // arsize_o <= axi_s_initiator_struct.xyz; // [2:0] + // arburst_o <= axi_s_initiator_struct.xyz; // [1:0] + // arcache_o <= axi_s_initiator_struct.xyz; // [3:0] + // arprot_o <= axi_s_initiator_struct.xyz; // [2:0] + // arid_o <= axi_s_initiator_struct.xyz; // [X-1:0] + // arlen_o <= axi_s_initiator_struct.xyz; // [LEN-1:0] + // arlock_o <= axi_s_initiator_struct.xyz; // + // arqos_o <= axi_s_initiator_struct.xyz; // [3:0] + // aregion_o <= axi_s_initiator_struct.xyz; // [3:0] + // aruser_o <= axi_s_initiator_struct.xyz; // [X-1:0] + // rready_o <= axi_s_initiator_struct.xyz; // + // Responder inout signals + + @(posedge axi_clk_i); + if (!first_transfer) begin + // Perform transfer response here. + // Reply using data recieved in the axi_s_responder_struct. + @(posedge axi_clk_i); + // Reply using data recieved in the transaction handle. + @(posedge axi_clk_i); + end + // Wait for next transfer then gather info from intiator about the transfer. + // Place the data into the axi_s_initiator_struct. + @(posedge axi_clk_i); + @(posedge axi_clk_i); + first_transfer = 0; + endtask +// pragma uvmf custom respond_and_wait_for_next_transfer end + + +endinterface + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/axi_s_pkg/src/axi_s_if.sv b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/axi_s_pkg/src/axi_s_if.sv new file mode 100644 index 00000000..fcd5d49b --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/axi_s_pkg/src/axi_s_if.sv @@ -0,0 +1,289 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This interface contains the axi_s interface signals. +// It is instantiated once per axi_s bus. Bus Functional Models, +// BFM's named axi_s_driver_bfm, are used to drive signals on the bus. +// BFM's named axi_s_monitor_bfm are used to monitor signals on the +// bus. This interface signal bundle is passed in the port list of +// the BFM in order to give the BFM access to the signals in this +// interface. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// This template can be used to connect a DUT to these signals +// +// .dut_signal_port(axi_s_bus.awvalid), // Agent input +// .dut_signal_port(axi_s_bus.awready), // Agent output +// .dut_signal_port(axi_s_bus.awaddr), // Agent input +// .dut_signal_port(axi_s_bus.awsize), // Agent input +// .dut_signal_port(axi_s_bus.awburst), // Agent input +// .dut_signal_port(axi_s_bus.awcache), // Agent input +// .dut_signal_port(axi_s_bus.awprot), // Agent input +// .dut_signal_port(axi_s_bus.awid), // Agent input +// .dut_signal_port(axi_s_bus.awlen), // Agent input +// .dut_signal_port(axi_s_bus.awlock), // Agent input +// .dut_signal_port(axi_s_bus.awqos), // Agent input +// .dut_signal_port(axi_s_bus.awregion), // Agent input +// .dut_signal_port(axi_s_bus.awuser), // Agent input +// .dut_signal_port(axi_s_bus.wvalid), // Agent input +// .dut_signal_port(axi_s_bus.wready), // Agent output +// .dut_signal_port(axi_s_bus.wlast), // Agent input +// .dut_signal_port(axi_s_bus.wdata), // Agent input +// .dut_signal_port(axi_s_bus.wstrb), // Agent input +// .dut_signal_port(axi_s_bus.wid), // Agent input +// .dut_signal_port(axi_s_bus.wuser), // Agent input +// .dut_signal_port(axi_s_bus.bwvalid), // Agent output +// .dut_signal_port(axi_s_bus.bwready), // Agent output +// .dut_signal_port(axi_s_bus.bresp), // Agent input +// .dut_signal_port(axi_s_bus.bid), // Agent output +// .dut_signal_port(axi_s_bus.buser), // Agent output +// .dut_signal_port(axi_s_bus.arvalid), // Agent input +// .dut_signal_port(axi_s_bus.aready), // Agent output +// .dut_signal_port(axi_s_bus.araddr), // Agent input +// .dut_signal_port(axi_s_bus.arsize), // Agent input +// .dut_signal_port(axi_s_bus.arburst), // Agent input +// .dut_signal_port(axi_s_bus.arcache), // Agent input +// .dut_signal_port(axi_s_bus.arprot), // Agent input +// .dut_signal_port(axi_s_bus.arid), // Agent input +// .dut_signal_port(axi_s_bus.arlen), // Agent input +// .dut_signal_port(axi_s_bus.arlock), // Agent input +// .dut_signal_port(axi_s_bus.arqos), // Agent input +// .dut_signal_port(axi_s_bus.aregion), // Agent input +// .dut_signal_port(axi_s_bus.aruser), // Agent input +// .dut_signal_port(axi_s_bus.rvalid), // Agent output +// .dut_signal_port(axi_s_bus.rready), // Agent input +// .dut_signal_port(axi_s_bus.rlast), // Agent output +// .dut_signal_port(axi_s_bus.rdata), // Agent output +// .dut_signal_port(axi_s_bus.rid), // Agent output +// .dut_signal_port(axi_s_bus.ruser), // Agent output +// .dut_signal_port(axi_s_bus.rresp), // Agent output + +import uvmf_base_pkg_hdl::*; +import axi_s_pkg_hdl::*; + +interface axi_s_if #( + int AW_WIDTH = 32, + int LEN = 8, + int DATA_WIDTH = 32, + int X = 16 + ) + + ( + input logic axi_clk, + input logic rst, + input logic awvalid, + output logic awready, + input logic [AW_WIDTH-1:0] awaddr, + input logic [2:0] awsize, + input logic [1:0] awburst, + input logic [3:0] awcache, + input logic [2:0] awprot, + input logic [X-1:0] awid, + input logic [LEN-1:0] awlen, + input logic awlock, + input logic [3:0] awqos, + input logic [3:0] awregion, + input logic [X-1:0] awuser, + input logic wvalid, + output logic wready, + input logic wlast, + input logic [DATA_WIDTH-1:0] wdata, + input logic [DATA_WIDTH/8-1:0] wstrb, + input logic [X-1:0] wid, + input logic [X-1:0] wuser, + output logic bwvalid, + output logic bwready, + input logic [1:0] bresp, + output logic [X-1:0] bid, + output logic [X-1:0] buser, + input logic arvalid, + output logic aready, + input logic [AW_WIDTH-1:0] araddr, + input logic [2:0] arsize, + input logic [1:0] arburst, + input logic [3:0] arcache, + input logic [2:0] arprot, + input logic [X-1:0] arid, + input logic [LEN-1:0] arlen, + input logic arlock, + input logic [3:0] arqos, + input logic [3:0] aregion, + input logic [X-1:0] aruser, + output logic rvalid, + input logic rready, + output logic rlast, + output logic [DATA_WIDTH-1:0] rdata, + output logic [X-1:0] rid, + output logic [X-1:0] ruser, + output logic [1:0] rresp + ); + +modport monitor_port + ( + input axi_clk, + input rst, + input awvalid, + input awready, + input awaddr, + input awsize, + input awburst, + input awcache, + input awprot, + input awid, + input awlen, + input awlock, + input awqos, + input awregion, + input awuser, + input wvalid, + input wready, + input wlast, + input wdata, + input wstrb, + input wid, + input wuser, + input bwvalid, + input bwready, + input bresp, + input bid, + input buser, + input arvalid, + input aready, + input araddr, + input arsize, + input arburst, + input arcache, + input arprot, + input arid, + input arlen, + input arlock, + input arqos, + input aregion, + input aruser, + input rvalid, + input rready, + input rlast, + input rdata, + input rid, + input ruser, + input rresp + ); + +modport initiator_port + ( + input axi_clk, + input rst, + input awvalid, + output awready, + input awaddr, + input awsize, + input awburst, + input awcache, + input awprot, + input awid, + input awlen, + input awlock, + input awqos, + input awregion, + input awuser, + input wvalid, + output wready, + input wlast, + input wdata, + input wstrb, + input wid, + input wuser, + output bwvalid, + output bwready, + input bresp, + output bid, + output buser, + input arvalid, + output aready, + input araddr, + input arsize, + input arburst, + input arcache, + input arprot, + input arid, + input arlen, + input arlock, + input arqos, + input aregion, + input aruser, + output rvalid, + input rready, + output rlast, + output rdata, + output rid, + output ruser, + output rresp + ); + +modport responder_port + ( + input axi_clk, + input rst, + output awvalid, + input awready, + output awaddr, + output awsize, + output awburst, + output awcache, + output awprot, + output awid, + output awlen, + output awlock, + output awqos, + output awregion, + output awuser, + output wvalid, + input wready, + output wlast, + output wdata, + output wstrb, + output wid, + output wuser, + input bwvalid, + input bwready, + output bresp, + input bid, + input buser, + output arvalid, + input aready, + output araddr, + output arsize, + output arburst, + output arcache, + output arprot, + output arid, + output arlen, + output arlock, + output arqos, + output aregion, + output aruser, + input rvalid, + output rready, + input rlast, + input rdata, + input rid, + input ruser, + input rresp + ); + + +// pragma uvmf custom interface_item_additional begin +// pragma uvmf custom interface_item_additional end + +endinterface + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/axi_s_pkg/src/axi_s_infact_coverage_strategy.csv b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/axi_s_pkg/src/axi_s_infact_coverage_strategy.csv new file mode 100644 index 00000000..1c218e14 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/axi_s_pkg/src/axi_s_infact_coverage_strategy.csv @@ -0,0 +1,6 @@ +Global +auto_bin_max, 64 + +Name,Type,Include +rand_fields,coverpoint,=rand *.** + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/axi_s_pkg/src/axi_s_macros.svh b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/axi_s_pkg/src/axi_s_macros.svh new file mode 100644 index 00000000..84dc9f36 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/axi_s_pkg/src/axi_s_macros.svh @@ -0,0 +1,517 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This file contains macros used with the axi_s package. +// These macros include packed struct definitions. These structs are +// used to pass data between classes, hvl, and BFM's, hdl. Use of +// structs are more efficient and simpler to modify. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// + +// **************************************************************************** +// When changing the contents of this struct, be sure to update the to_struct +// and from_struct methods defined in the macros below that are used in +// the axi_s_configuration class. +// + `define axi_s_CONFIGURATION_STRUCT \ +typedef struct packed { \ + uvmf_active_passive_t active_passive; \ + uvmf_initiator_responder_t initiator_responder; \ + } axi_s_configuration_s; + + `define axi_s_CONFIGURATION_TO_STRUCT_FUNCTION \ + virtual function axi_s_configuration_s to_struct();\ + axi_s_configuration_struct = \ + {\ + this.active_passive,\ + this.initiator_responder\ + };\ + return ( axi_s_configuration_struct );\ + endfunction + + `define axi_s_CONFIGURATION_FROM_STRUCT_FUNCTION \ + virtual function void from_struct(axi_s_configuration_s axi_s_configuration_struct);\ + {\ + this.active_passive,\ + this.initiator_responder \ + } = axi_s_configuration_struct;\ + endfunction + +// **************************************************************************** +// When changing the contents of this struct, be sure to update the to_monitor_struct +// and from_monitor_struct methods of the axi_s_transaction class. +// + `define axi_s_MONITOR_STRUCT typedef struct packed { \ + bit awvalid ; \ + bit awready ; \ + bit [AW_WIDTH-1:0] awaddr ; \ + bit awsize ; \ + bit awburst ; \ + bit awcache ; \ + bit awprot ; \ + bit [X-1:0] awid ; \ + bit [LEN-1:0] awlen ; \ + bit awlock ; \ + bit awqos ; \ + bit awregion ; \ + bit [X-1:0] awuser ; \ + bit wvalid ; \ + bit wready ; \ + bit wlast ; \ + bit [DATA_WIDTH-1:0] wdata ; \ + bit [DATA_WIDTH/8-1:0] wstrb ; \ + bit [X-1:0] wid ; \ + bit [X-1:0] wuser ; \ + bit bwvalid ; \ + bit bwready ; \ + bit bresp ; \ + bit [X-1:0] bid ; \ + bit [X-1:0] buser ; \ + bit arvalid ; \ + bit aready ; \ + bit [AW_WIDTH-1:0] araddr ; \ + bit arsize ; \ + bit arburst ; \ + bit arcache ; \ + bit arprot ; \ + bit [X-1:0] arid ; \ + bit [LEN-1:0] arlen ; \ + bit arlock ; \ + bit arqos ; \ + bit aregion ; \ + bit [X-1:0] aruser ; \ + bit rvalid ; \ + bit rready ; \ + bit rlast ; \ + bit [DATA_WIDTH-1:0] rdata ; \ + bit [X-1:0] rid ; \ + bit [X-1:0] ruser ; \ + bit rresp ; \ + } axi_s_monitor_s; + + `define axi_s_TO_MONITOR_STRUCT_FUNCTION \ + virtual function axi_s_monitor_s to_monitor_struct();\ + axi_s_monitor_struct = \ + { \ + this.awvalid , \ + this.awready , \ + this.awaddr , \ + this.awsize , \ + this.awburst , \ + this.awcache , \ + this.awprot , \ + this.awid , \ + this.awlen , \ + this.awlock , \ + this.awqos , \ + this.awregion , \ + this.awuser , \ + this.wvalid , \ + this.wready , \ + this.wlast , \ + this.wdata , \ + this.wstrb , \ + this.wid , \ + this.wuser , \ + this.bwvalid , \ + this.bwready , \ + this.bresp , \ + this.bid , \ + this.buser , \ + this.arvalid , \ + this.aready , \ + this.araddr , \ + this.arsize , \ + this.arburst , \ + this.arcache , \ + this.arprot , \ + this.arid , \ + this.arlen , \ + this.arlock , \ + this.arqos , \ + this.aregion , \ + this.aruser , \ + this.rvalid , \ + this.rready , \ + this.rlast , \ + this.rdata , \ + this.rid , \ + this.ruser , \ + this.rresp \ + };\ + return ( axi_s_monitor_struct);\ + endfunction\ + + `define axi_s_FROM_MONITOR_STRUCT_FUNCTION \ + virtual function void from_monitor_struct(axi_s_monitor_s axi_s_monitor_struct);\ + {\ + this.awvalid , \ + this.awready , \ + this.awaddr , \ + this.awsize , \ + this.awburst , \ + this.awcache , \ + this.awprot , \ + this.awid , \ + this.awlen , \ + this.awlock , \ + this.awqos , \ + this.awregion , \ + this.awuser , \ + this.wvalid , \ + this.wready , \ + this.wlast , \ + this.wdata , \ + this.wstrb , \ + this.wid , \ + this.wuser , \ + this.bwvalid , \ + this.bwready , \ + this.bresp , \ + this.bid , \ + this.buser , \ + this.arvalid , \ + this.aready , \ + this.araddr , \ + this.arsize , \ + this.arburst , \ + this.arcache , \ + this.arprot , \ + this.arid , \ + this.arlen , \ + this.arlock , \ + this.arqos , \ + this.aregion , \ + this.aruser , \ + this.rvalid , \ + this.rready , \ + this.rlast , \ + this.rdata , \ + this.rid , \ + this.ruser , \ + this.rresp \ + } = axi_s_monitor_struct;\ + endfunction + +// **************************************************************************** +// When changing the contents of this struct, be sure to update the to_initiator_struct +// and from_initiator_struct methods of the axi_s_transaction class. +// Also update the comments in the driver BFM. +// + `define axi_s_INITIATOR_STRUCT typedef struct packed { \ + bit awvalid ; \ + bit awready ; \ + bit [AW_WIDTH-1:0] awaddr ; \ + bit awsize ; \ + bit awburst ; \ + bit awcache ; \ + bit awprot ; \ + bit [X-1:0] awid ; \ + bit [LEN-1:0] awlen ; \ + bit awlock ; \ + bit awqos ; \ + bit awregion ; \ + bit [X-1:0] awuser ; \ + bit wvalid ; \ + bit wready ; \ + bit wlast ; \ + bit [DATA_WIDTH-1:0] wdata ; \ + bit [DATA_WIDTH/8-1:0] wstrb ; \ + bit [X-1:0] wid ; \ + bit [X-1:0] wuser ; \ + bit bwvalid ; \ + bit bwready ; \ + bit bresp ; \ + bit [X-1:0] bid ; \ + bit [X-1:0] buser ; \ + bit arvalid ; \ + bit aready ; \ + bit [AW_WIDTH-1:0] araddr ; \ + bit arsize ; \ + bit arburst ; \ + bit arcache ; \ + bit arprot ; \ + bit [X-1:0] arid ; \ + bit [LEN-1:0] arlen ; \ + bit arlock ; \ + bit arqos ; \ + bit aregion ; \ + bit [X-1:0] aruser ; \ + bit rvalid ; \ + bit rready ; \ + bit rlast ; \ + bit [DATA_WIDTH-1:0] rdata ; \ + bit [X-1:0] rid ; \ + bit [X-1:0] ruser ; \ + bit rresp ; \ + } axi_s_initiator_s; + + `define axi_s_TO_INITIATOR_STRUCT_FUNCTION \ + virtual function axi_s_initiator_s to_initiator_struct();\ + axi_s_initiator_struct = \ + {\ + this.awvalid , \ + this.awready , \ + this.awaddr , \ + this.awsize , \ + this.awburst , \ + this.awcache , \ + this.awprot , \ + this.awid , \ + this.awlen , \ + this.awlock , \ + this.awqos , \ + this.awregion , \ + this.awuser , \ + this.wvalid , \ + this.wready , \ + this.wlast , \ + this.wdata , \ + this.wstrb , \ + this.wid , \ + this.wuser , \ + this.bwvalid , \ + this.bwready , \ + this.bresp , \ + this.bid , \ + this.buser , \ + this.arvalid , \ + this.aready , \ + this.araddr , \ + this.arsize , \ + this.arburst , \ + this.arcache , \ + this.arprot , \ + this.arid , \ + this.arlen , \ + this.arlock , \ + this.arqos , \ + this.aregion , \ + this.aruser , \ + this.rvalid , \ + this.rready , \ + this.rlast , \ + this.rdata , \ + this.rid , \ + this.ruser , \ + this.rresp \ + };\ + return ( axi_s_initiator_struct);\ + endfunction + + `define axi_s_FROM_INITIATOR_STRUCT_FUNCTION \ + virtual function void from_initiator_struct(axi_s_initiator_s axi_s_initiator_struct);\ + {\ + this.awvalid , \ + this.awready , \ + this.awaddr , \ + this.awsize , \ + this.awburst , \ + this.awcache , \ + this.awprot , \ + this.awid , \ + this.awlen , \ + this.awlock , \ + this.awqos , \ + this.awregion , \ + this.awuser , \ + this.wvalid , \ + this.wready , \ + this.wlast , \ + this.wdata , \ + this.wstrb , \ + this.wid , \ + this.wuser , \ + this.bwvalid , \ + this.bwready , \ + this.bresp , \ + this.bid , \ + this.buser , \ + this.arvalid , \ + this.aready , \ + this.araddr , \ + this.arsize , \ + this.arburst , \ + this.arcache , \ + this.arprot , \ + this.arid , \ + this.arlen , \ + this.arlock , \ + this.arqos , \ + this.aregion , \ + this.aruser , \ + this.rvalid , \ + this.rready , \ + this.rlast , \ + this.rdata , \ + this.rid , \ + this.ruser , \ + this.rresp \ + } = axi_s_initiator_struct;\ + endfunction + +// **************************************************************************** +// When changing the contents of this struct, be sure to update the to_responder_struct +// and from_responder_struct methods of the axi_s_transaction class. +// Also update the comments in the driver BFM. +// + `define axi_s_RESPONDER_STRUCT typedef struct packed { \ + bit awvalid ; \ + bit awready ; \ + bit [AW_WIDTH-1:0] awaddr ; \ + bit awsize ; \ + bit awburst ; \ + bit awcache ; \ + bit awprot ; \ + bit [X-1:0] awid ; \ + bit [LEN-1:0] awlen ; \ + bit awlock ; \ + bit awqos ; \ + bit awregion ; \ + bit [X-1:0] awuser ; \ + bit wvalid ; \ + bit wready ; \ + bit wlast ; \ + bit [DATA_WIDTH-1:0] wdata ; \ + bit [DATA_WIDTH/8-1:0] wstrb ; \ + bit [X-1:0] wid ; \ + bit [X-1:0] wuser ; \ + bit bwvalid ; \ + bit bwready ; \ + bit bresp ; \ + bit [X-1:0] bid ; \ + bit [X-1:0] buser ; \ + bit arvalid ; \ + bit aready ; \ + bit [AW_WIDTH-1:0] araddr ; \ + bit arsize ; \ + bit arburst ; \ + bit arcache ; \ + bit arprot ; \ + bit [X-1:0] arid ; \ + bit [LEN-1:0] arlen ; \ + bit arlock ; \ + bit arqos ; \ + bit aregion ; \ + bit [X-1:0] aruser ; \ + bit rvalid ; \ + bit rready ; \ + bit rlast ; \ + bit [DATA_WIDTH-1:0] rdata ; \ + bit [X-1:0] rid ; \ + bit [X-1:0] ruser ; \ + bit rresp ; \ + } axi_s_responder_s; + + `define axi_s_TO_RESPONDER_STRUCT_FUNCTION \ + virtual function axi_s_responder_s to_responder_struct();\ + axi_s_responder_struct = \ + {\ + this.awvalid , \ + this.awready , \ + this.awaddr , \ + this.awsize , \ + this.awburst , \ + this.awcache , \ + this.awprot , \ + this.awid , \ + this.awlen , \ + this.awlock , \ + this.awqos , \ + this.awregion , \ + this.awuser , \ + this.wvalid , \ + this.wready , \ + this.wlast , \ + this.wdata , \ + this.wstrb , \ + this.wid , \ + this.wuser , \ + this.bwvalid , \ + this.bwready , \ + this.bresp , \ + this.bid , \ + this.buser , \ + this.arvalid , \ + this.aready , \ + this.araddr , \ + this.arsize , \ + this.arburst , \ + this.arcache , \ + this.arprot , \ + this.arid , \ + this.arlen , \ + this.arlock , \ + this.arqos , \ + this.aregion , \ + this.aruser , \ + this.rvalid , \ + this.rready , \ + this.rlast , \ + this.rdata , \ + this.rid , \ + this.ruser , \ + this.rresp \ + };\ + return ( axi_s_responder_struct);\ + endfunction + + `define axi_s_FROM_RESPONDER_STRUCT_FUNCTION \ + virtual function void from_responder_struct(axi_s_responder_s axi_s_responder_struct);\ + {\ + this.awvalid , \ + this.awready , \ + this.awaddr , \ + this.awsize , \ + this.awburst , \ + this.awcache , \ + this.awprot , \ + this.awid , \ + this.awlen , \ + this.awlock , \ + this.awqos , \ + this.awregion , \ + this.awuser , \ + this.wvalid , \ + this.wready , \ + this.wlast , \ + this.wdata , \ + this.wstrb , \ + this.wid , \ + this.wuser , \ + this.bwvalid , \ + this.bwready , \ + this.bresp , \ + this.bid , \ + this.buser , \ + this.arvalid , \ + this.aready , \ + this.araddr , \ + this.arsize , \ + this.arburst , \ + this.arcache , \ + this.arprot , \ + this.arid , \ + this.arlen , \ + this.arlock , \ + this.arqos , \ + this.aregion , \ + this.aruser , \ + this.rvalid , \ + this.rready , \ + this.rlast , \ + this.rdata , \ + this.rid , \ + this.ruser , \ + this.rresp \ + } = axi_s_responder_struct;\ + endfunction +// pragma uvmf custom additional begin +// pragma uvmf custom additional end diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/axi_s_pkg/src/axi_s_monitor.svh b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/axi_s_pkg/src/axi_s_monitor.svh new file mode 100644 index 00000000..63bc38e6 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/axi_s_pkg/src/axi_s_monitor.svh @@ -0,0 +1,112 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This class receives axi_s transactions observed by the +// axi_s monitor BFM and broadcasts them through the analysis port +// on the agent. It accesses the monitor BFM through the monitor +// task. This UVM component captures transactions +// for viewing in the waveform viewer if the +// enable_transaction_viewing flag is set in the configuration. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class axi_s_monitor #( + int AW_WIDTH = 32, + int LEN = 8, + int DATA_WIDTH = 32, + int X = 16 + ) extends uvmf_monitor_base #( + .CONFIG_T(axi_s_configuration #( + .AW_WIDTH(AW_WIDTH), + .LEN(LEN), + .DATA_WIDTH(DATA_WIDTH), + .X(X) + )), + .BFM_BIND_T(virtual axi_s_monitor_bfm #( + .AW_WIDTH(AW_WIDTH), + .LEN(LEN), + .DATA_WIDTH(DATA_WIDTH), + .X(X) + )), + .TRANS_T(axi_s_transaction #( + .AW_WIDTH(AW_WIDTH), + .LEN(LEN), + .DATA_WIDTH(DATA_WIDTH), + .X(X) + ))); + + `uvm_component_param_utils( axi_s_monitor #( + AW_WIDTH, + LEN, + DATA_WIDTH, + X + )) + +// Structure used to pass data from monitor BFM to monitor class in agent. +// Use to_monitor_struct function to pack transaction variables into structure. +// Use from_monitor_struct function to unpack transaction variables from structure. +`axi_s_MONITOR_STRUCT + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + +// **************************************************************************** +// This function is the standard SystemVerilog constructor. +// + function new( string name = "", uvm_component parent = null ); + super.new( name, parent ); + endfunction + +// **************************************************************************** +// This function sends configuration object variables to the monitor BFM +// using the configuration struct. +// + virtual function void configure(input CONFIG_T cfg); + bfm.configure( cfg.to_struct() ); + + endfunction + +// **************************************************************************** +// This function places a handle to this class in the proxy variable in the +// monitor BFM. This allows the monitor BFM to call the notify_transaction +// function within this class. +// + virtual function void set_bfm_proxy_handle(); + bfm.proxy = this; endfunction + +// *************************************************************************** + virtual task run_phase(uvm_phase phase); + // Start monitor BFM thread and don't call super.run() in order to + // override the default monitor proxy 'pull' behavior with the more + // emulation-friendly BFM 'push' approach using the notify_transaction + // function below + bfm.start_monitoring(); + endtask + +// ************************************************************************** + +// This function is called by the monitor BFM. It receives data observed by the +// monitor BFM. Data is passed using the axi_s_monitor_struct. + virtual function void notify_transaction(input axi_s_monitor_s axi_s_monitor_struct); + + + trans = new("trans"); + trans.from_monitor_struct(axi_s_monitor_struct); + trans.start_time = time_stamp; + trans.end_time = $time; + time_stamp = trans.end_time; + + analyze(trans); + endfunction + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/axi_s_pkg/src/axi_s_monitor_bfm.sv b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/axi_s_pkg/src/axi_s_monitor_bfm.sv new file mode 100644 index 00000000..d8a65d39 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/axi_s_pkg/src/axi_s_monitor_bfm.sv @@ -0,0 +1,360 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This interface performs the axi_s signal monitoring. +// It is accessed by the uvm axi_s monitor through a virtual +// interface handle in the axi_s configuration. It monitors the +// signals passed in through the port connection named bus of +// type axi_s_if. +// +// Input signals from the axi_s_if are assigned to an internal input +// signal with a _i suffix. The _i signal should be used for sampling. +// +// The input signal connections are as follows: +// bus.signal -> signal_i +// +// Interface functions and tasks used by UVM components: +// monitor(inout TRANS_T txn); +// This task receives the transaction, txn, from the +// UVM monitor and then populates variables in txn +// from values observed on bus activity. This task +// blocks until an operation on the axi_s bus is complete. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +import uvmf_base_pkg_hdl::*; +import axi_s_pkg_hdl::*; +`include "src/axi_s_macros.svh" + + +interface axi_s_monitor_bfm #( + int AW_WIDTH = 32, + int LEN = 8, + int DATA_WIDTH = 32, + int X = 16 + ) + ( axi_s_if bus ); + // The pragma below and additional ones in-lined further down are for running this BFM on Veloce + // pragma attribute axi_s_monitor_bfm partition_interface_xif + +`ifndef XRTL +// This code is to aid in debugging parameter mismatches between the BFM and its corresponding agent. +// Enable this debug by setting UVM_VERBOSITY to UVM_DEBUG +// Setting UVM_VERBOSITY to UVM_DEBUG causes all BFM's and all agents to display their parameter settings. +// All of the messages from this feature have a UVM messaging id value of "CFG" +// The transcript or run.log can be parsed to ensure BFM parameter settings match its corresponding agents parameter settings. +import uvm_pkg::*; +`include "uvm_macros.svh" +initial begin : bfm_vs_agent_parameter_debug + `uvm_info("CFG", + $psprintf("The BFM at '%m' has the following parameters: AW_WIDTH=%x LEN=%x DATA_WIDTH=%x X=%x ", AW_WIDTH,LEN,DATA_WIDTH,X), + UVM_DEBUG) +end +`endif + + + // Structure used to pass transaction data from monitor BFM to monitor class in agent. +`axi_s_MONITOR_STRUCT + axi_s_monitor_s axi_s_monitor_struct; + + // Structure used to pass configuration data from monitor class to monitor BFM. + `axi_s_CONFIGURATION_STRUCT + + + // Config value to determine if this is an initiator or a responder + uvmf_initiator_responder_t initiator_responder; + // Custom configuration variables. + // These are set using the configure function which is called during the UVM connect_phase + + logic axi_clk_i; + logic rst_i; + tri awvalid_i; + tri awready_i; + tri [AW_WIDTH-1:0] awaddr_i; + tri [2:0] awsize_i; + tri [1:0] awburst_i; + tri [3:0] awcache_i; + tri [2:0] awprot_i; + tri [X-1:0] awid_i; + tri [LEN-1:0] awlen_i; + tri awlock_i; + tri [3:0] awqos_i; + tri [3:0] awregion_i; + tri [X-1:0] awuser_i; + tri wvalid_i; + tri wready_i; + tri wlast_i; + tri [DATA_WIDTH-1:0] wdata_i; + tri [DATA_WIDTH/8-1:0] wstrb_i; + tri [X-1:0] wid_i; + tri [X-1:0] wuser_i; + tri bwvalid_i; + tri bwready_i; + tri [1:0] bresp_i; + tri [X-1:0] bid_i; + tri [X-1:0] buser_i; + tri arvalid_i; + tri aready_i; + tri [AW_WIDTH-1:0] araddr_i; + tri [2:0] arsize_i; + tri [1:0] arburst_i; + tri [3:0] arcache_i; + tri [2:0] arprot_i; + tri [X-1:0] arid_i; + tri [LEN-1:0] arlen_i; + tri arlock_i; + tri [3:0] arqos_i; + tri [3:0] aregion_i; + tri [X-1:0] aruser_i; + tri rvalid_i; + tri rready_i; + tri rlast_i; + tri [DATA_WIDTH-1:0] rdata_i; + tri [X-1:0] rid_i; + tri [X-1:0] ruser_i; + tri [1:0] rresp_i; + assign axi_clk_i = bus.axi_clk; + assign rst_i = bus.rst; + assign awvalid_i = bus.awvalid; + assign awready_i = bus.awready; + assign awaddr_i = bus.awaddr; + assign awsize_i = bus.awsize; + assign awburst_i = bus.awburst; + assign awcache_i = bus.awcache; + assign awprot_i = bus.awprot; + assign awid_i = bus.awid; + assign awlen_i = bus.awlen; + assign awlock_i = bus.awlock; + assign awqos_i = bus.awqos; + assign awregion_i = bus.awregion; + assign awuser_i = bus.awuser; + assign wvalid_i = bus.wvalid; + assign wready_i = bus.wready; + assign wlast_i = bus.wlast; + assign wdata_i = bus.wdata; + assign wstrb_i = bus.wstrb; + assign wid_i = bus.wid; + assign wuser_i = bus.wuser; + assign bwvalid_i = bus.bwvalid; + assign bwready_i = bus.bwready; + assign bresp_i = bus.bresp; + assign bid_i = bus.bid; + assign buser_i = bus.buser; + assign arvalid_i = bus.arvalid; + assign aready_i = bus.aready; + assign araddr_i = bus.araddr; + assign arsize_i = bus.arsize; + assign arburst_i = bus.arburst; + assign arcache_i = bus.arcache; + assign arprot_i = bus.arprot; + assign arid_i = bus.arid; + assign arlen_i = bus.arlen; + assign arlock_i = bus.arlock; + assign arqos_i = bus.arqos; + assign aregion_i = bus.aregion; + assign aruser_i = bus.aruser; + assign rvalid_i = bus.rvalid; + assign rready_i = bus.rready; + assign rlast_i = bus.rlast; + assign rdata_i = bus.rdata; + assign rid_i = bus.rid; + assign ruser_i = bus.ruser; + assign rresp_i = bus.rresp; + + // Proxy handle to UVM monitor + axi_s_pkg::axi_s_monitor #( + .AW_WIDTH(AW_WIDTH), + .LEN(LEN), + .DATA_WIDTH(DATA_WIDTH), + .X(X) + ) proxy; + // pragma tbx oneway proxy.notify_transaction + + // pragma uvmf custom interface_item_additional begin + // pragma uvmf custom interface_item_additional end + + //****************************************************************** + task wait_for_reset();// pragma tbx xtf + @(posedge axi_clk_i) ; + do_wait_for_reset(); + endtask + + // **************************************************************************** + task do_wait_for_reset(); + // pragma uvmf custom reset_condition begin + wait ( rst_i === 1 ) ; + @(posedge axi_clk_i) ; + // pragma uvmf custom reset_condition end + endtask + + //****************************************************************** + + task wait_for_num_clocks(input int unsigned count); // pragma tbx xtf + @(posedge axi_clk_i); + + repeat (count-1) @(posedge axi_clk_i); + endtask + + //****************************************************************** + event go; + function void start_monitoring();// pragma tbx xtf + -> go; + endfunction + + // **************************************************************************** + initial begin + @go; + forever begin + @(posedge axi_clk_i); + do_monitor( axi_s_monitor_struct ); + + + proxy.notify_transaction( axi_s_monitor_struct ); + + end + end + + //****************************************************************** + // The configure() function is used to pass agent configuration + // variables to the monitor BFM. It is called by the monitor within + // the agent at the beginning of the simulation. It may be called + // during the simulation if agent configuration variables are updated + // and the monitor BFM needs to be aware of the new configuration + // variables. + // + function void configure(axi_s_configuration_s axi_s_configuration_arg); // pragma tbx xtf + initiator_responder = axi_s_configuration_arg.initiator_responder; + // pragma uvmf custom configure begin + // pragma uvmf custom configure end + endfunction + + + // **************************************************************************** + + task do_monitor(output axi_s_monitor_s axi_s_monitor_struct); + // + // Available struct members: + // // axi_s_monitor_struct.awvalid + // // axi_s_monitor_struct.awready + // // axi_s_monitor_struct.awaddr + // // axi_s_monitor_struct.awsize + // // axi_s_monitor_struct.awburst + // // axi_s_monitor_struct.awcache + // // axi_s_monitor_struct.awprot + // // axi_s_monitor_struct.awid + // // axi_s_monitor_struct.awlen + // // axi_s_monitor_struct.awlock + // // axi_s_monitor_struct.awqos + // // axi_s_monitor_struct.awregion + // // axi_s_monitor_struct.awuser + // // axi_s_monitor_struct.wvalid + // // axi_s_monitor_struct.wready + // // axi_s_monitor_struct.wlast + // // axi_s_monitor_struct.wdata + // // axi_s_monitor_struct.wstrb + // // axi_s_monitor_struct.wid + // // axi_s_monitor_struct.wuser + // // axi_s_monitor_struct.bwvalid + // // axi_s_monitor_struct.bwready + // // axi_s_monitor_struct.bresp + // // axi_s_monitor_struct.bid + // // axi_s_monitor_struct.buser + // // axi_s_monitor_struct.arvalid + // // axi_s_monitor_struct.aready + // // axi_s_monitor_struct.araddr + // // axi_s_monitor_struct.arsize + // // axi_s_monitor_struct.arburst + // // axi_s_monitor_struct.arcache + // // axi_s_monitor_struct.arprot + // // axi_s_monitor_struct.arid + // // axi_s_monitor_struct.arlen + // // axi_s_monitor_struct.arlock + // // axi_s_monitor_struct.arqos + // // axi_s_monitor_struct.aregion + // // axi_s_monitor_struct.aruser + // // axi_s_monitor_struct.rvalid + // // axi_s_monitor_struct.rready + // // axi_s_monitor_struct.rlast + // // axi_s_monitor_struct.rdata + // // axi_s_monitor_struct.rid + // // axi_s_monitor_struct.ruser + // // axi_s_monitor_struct.rresp + // // + // Reference code; + // How to wait for signal value + // while (control_signal === 1'b1) @(posedge axi_clk_i); + // + // How to assign a struct member, named xyz, from a signal. + // All available input signals listed. + // axi_s_monitor_struct.xyz = awvalid_i; // + // axi_s_monitor_struct.xyz = awready_i; // + // axi_s_monitor_struct.xyz = awaddr_i; // [AW_WIDTH-1:0] + // axi_s_monitor_struct.xyz = awsize_i; // [2:0] + // axi_s_monitor_struct.xyz = awburst_i; // [1:0] + // axi_s_monitor_struct.xyz = awcache_i; // [3:0] + // axi_s_monitor_struct.xyz = awprot_i; // [2:0] + // axi_s_monitor_struct.xyz = awid_i; // [X-1:0] + // axi_s_monitor_struct.xyz = awlen_i; // [LEN-1:0] + // axi_s_monitor_struct.xyz = awlock_i; // + // axi_s_monitor_struct.xyz = awqos_i; // [3:0] + // axi_s_monitor_struct.xyz = awregion_i; // [3:0] + // axi_s_monitor_struct.xyz = awuser_i; // [X-1:0] + // axi_s_monitor_struct.xyz = wvalid_i; // + // axi_s_monitor_struct.xyz = wready_i; // + // axi_s_monitor_struct.xyz = wlast_i; // + // axi_s_monitor_struct.xyz = wdata_i; // [DATA_WIDTH-1:0] + // axi_s_monitor_struct.xyz = wstrb_i; // [DATA_WIDTH/8-1:0] + // axi_s_monitor_struct.xyz = wid_i; // [X-1:0] + // axi_s_monitor_struct.xyz = wuser_i; // [X-1:0] + // axi_s_monitor_struct.xyz = bwvalid_i; // + // axi_s_monitor_struct.xyz = bwready_i; // + // axi_s_monitor_struct.xyz = bresp_i; // [1:0] + // axi_s_monitor_struct.xyz = bid_i; // [X-1:0] + // axi_s_monitor_struct.xyz = buser_i; // [X-1:0] + // axi_s_monitor_struct.xyz = arvalid_i; // + // axi_s_monitor_struct.xyz = aready_i; // + // axi_s_monitor_struct.xyz = araddr_i; // [AW_WIDTH-1:0] + // axi_s_monitor_struct.xyz = arsize_i; // [2:0] + // axi_s_monitor_struct.xyz = arburst_i; // [1:0] + // axi_s_monitor_struct.xyz = arcache_i; // [3:0] + // axi_s_monitor_struct.xyz = arprot_i; // [2:0] + // axi_s_monitor_struct.xyz = arid_i; // [X-1:0] + // axi_s_monitor_struct.xyz = arlen_i; // [LEN-1:0] + // axi_s_monitor_struct.xyz = arlock_i; // + // axi_s_monitor_struct.xyz = arqos_i; // [3:0] + // axi_s_monitor_struct.xyz = aregion_i; // [3:0] + // axi_s_monitor_struct.xyz = aruser_i; // [X-1:0] + // axi_s_monitor_struct.xyz = rvalid_i; // + // axi_s_monitor_struct.xyz = rready_i; // + // axi_s_monitor_struct.xyz = rlast_i; // + // axi_s_monitor_struct.xyz = rdata_i; // [DATA_WIDTH-1:0] + // axi_s_monitor_struct.xyz = rid_i; // [X-1:0] + // axi_s_monitor_struct.xyz = ruser_i; // [X-1:0] + // axi_s_monitor_struct.xyz = rresp_i; // [1:0] + // pragma uvmf custom do_monitor begin + // UVMF_CHANGE_ME : Implement protocol monitoring. The commented reference code + // below are examples of how to capture signal values and assign them to + // structure members. All available input signals are listed. The 'while' + // code example shows how to wait for a synchronous flow control signal. This + // task should return when a complete transfer has been observed. Once this task is + // exited with captured values, it is then called again to wait for and observe + // the next transfer. One clock cycle is consumed between calls to do_monitor. + @(posedge axi_clk_i); + @(posedge axi_clk_i); + @(posedge axi_clk_i); + @(posedge axi_clk_i); + // pragma uvmf custom do_monitor end + endtask + + +endinterface + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/axi_s_pkg/src/axi_s_random_sequence.svh b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/axi_s_pkg/src/axi_s_random_sequence.svh new file mode 100644 index 00000000..3eed0e3c --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/axi_s_pkg/src/axi_s_random_sequence.svh @@ -0,0 +1,73 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: +// This sequences randomizes the axi_s transaction and sends it +// to the UVM driver. +// +// This sequence constructs and randomizes a axi_s_transaction. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class axi_s_random_sequence #( + int AW_WIDTH = 32, + int LEN = 8, + int DATA_WIDTH = 32, + int X = 16 + ) + extends axi_s_sequence_base #( + .AW_WIDTH(AW_WIDTH), + .LEN(LEN), + .DATA_WIDTH(DATA_WIDTH), + .X(X) + ); + + `uvm_object_param_utils( axi_s_random_sequence #( + AW_WIDTH, + LEN, + DATA_WIDTH, + X + )) + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + //***************************************************************** + function new(string name = ""); + super.new(name); + endfunction: new + + // **************************************************************************** + // TASK : body() + // This task is automatically executed when this sequence is started using the + // start(sequencerHandle) task. + // + task body(); + + // Construct the transaction + req=axi_s_transaction#( + .AW_WIDTH(AW_WIDTH), + .LEN(LEN), + .DATA_WIDTH(DATA_WIDTH), + .X(X) + )::type_id::create("req"); + start_item(req); + // Randomize the transaction + if(!req.randomize()) `uvm_fatal("SEQ", "axi_s_random_sequence::body()-axi_s_transaction randomization failed") + // Send the transaction to the axi_s_driver_bfm via the sequencer and axi_s_driver. + finish_item(req); + `uvm_info("SEQ", {"Response:",req.convert2string()},UVM_MEDIUM) + + endtask + +endclass: axi_s_random_sequence + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/axi_s_pkg/src/axi_s_responder_sequence.svh b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/axi_s_pkg/src/axi_s_responder_sequence.svh new file mode 100644 index 00000000..bf30907b --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/axi_s_pkg/src/axi_s_responder_sequence.svh @@ -0,0 +1,69 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This class can be used to provide stimulus when an interface +// has been configured to run in a responder mode. It +// will never finish by default, always going back to the driver +// and driver BFM for the next transaction with which to respond. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class axi_s_responder_sequence #( + int AW_WIDTH = 32, + int LEN = 8, + int DATA_WIDTH = 32, + int X = 16 + ) + extends axi_s_sequence_base #( + .AW_WIDTH(AW_WIDTH), + .LEN(LEN), + .DATA_WIDTH(DATA_WIDTH), + .X(X) + ); + + `uvm_object_param_utils( axi_s_responder_sequence #( + AW_WIDTH, + LEN, + DATA_WIDTH, + X + )) + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + function new(string name = "axi_s_responder_sequence"); + super.new(name); + endfunction + + task body(); + req=axi_s_transaction#( + .AW_WIDTH(AW_WIDTH), + .LEN(LEN), + .DATA_WIDTH(DATA_WIDTH), + .X(X) + )::type_id::create("req"); + forever begin + start_item(req); + finish_item(req); + // pragma uvmf custom body begin + // UVMF_CHANGE_ME : Do something here with the resulting req item. The + // finish_item() call above will block until the req transaction is ready + // to be handled by the responder sequence. + // If this was an item that required a response, the expectation is + // that the response should be populated within this transaction now. + `uvm_info("SEQ",$sformatf("Processed txn: %s",req.convert2string()),UVM_HIGH) + // pragma uvmf custom body end + end + endtask + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/axi_s_pkg/src/axi_s_sequence_base.svh b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/axi_s_pkg/src/axi_s_sequence_base.svh new file mode 100644 index 00000000..1a75be44 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/axi_s_pkg/src/axi_s_sequence_base.svh @@ -0,0 +1,126 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: +// This file contains the class used as the base class for all sequences +// for this interface. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class axi_s_sequence_base #( + int AW_WIDTH = 32, + int LEN = 8, + int DATA_WIDTH = 32, + int X = 16 + ) extends uvmf_sequence_base #( + .REQ(axi_s_transaction #( + .AW_WIDTH(AW_WIDTH), + .LEN(LEN), + .DATA_WIDTH(DATA_WIDTH), + .X(X) + )), + .RSP(axi_s_transaction #( + .AW_WIDTH(AW_WIDTH), + .LEN(LEN), + .DATA_WIDTH(DATA_WIDTH), + .X(X) + ))); + + `uvm_object_param_utils( axi_s_sequence_base #( + AW_WIDTH, + LEN, + DATA_WIDTH, + X + )) + + // variables + typedef axi_s_transaction #( + .AW_WIDTH(AW_WIDTH), + .LEN(LEN), + .DATA_WIDTH(DATA_WIDTH), + .X(X) + ) axi_s_transaction_req_t; + axi_s_transaction_req_t req; + typedef axi_s_transaction #( + .AW_WIDTH(AW_WIDTH), + .LEN(LEN), + .DATA_WIDTH(DATA_WIDTH), + .X(X) + ) axi_s_transaction_rsp_t; + axi_s_transaction_rsp_t rsp; + + // Event for identifying when a response was received from the sequencer + event new_rsp; + + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + // **************************************************************************** + // TASK : get_responses() + // This task recursively gets sequence item responses from the sequencer. + // + virtual task get_responses(); + fork + begin + // Block until new rsp available + get_response(rsp); + // New rsp received. Indicate to sequence using event. + ->new_rsp; + // Display the received response transaction + `uvm_info("SEQ", {"New response transaction:",rsp.convert2string()}, UVM_MEDIUM) + end + join_none + endtask + + // **************************************************************************** + // TASK : pre_body() + // This task is called automatically when start is called with call_pre_post set to 1 (default). + // By calling get_responses() within pre_body() any derived sequences are automatically + // processing response transactions. Only un-comment this call to get_responses() if you + // have configured the interface driver to utilize the response transaction path by setting + // the configuration variable "return_transaction_response" to 1. Otherwise it is possible + // to impact runtime performance and memory utilization. + // + virtual task pre_body(); + // pragma uvmf custom pre_body begin +// get_responses(); + // pragma uvmf custom pre_body end + endtask + + // **************************************************************************** + // TASK : body() + // This task is called automatically when start is called. This sequence sends + // a req sequence item to the sequencer identified as an argument in the call + // to start. + // + virtual task body(); + // pragma uvmf custom body begin + start_item(req); + finish_item(req); + // pragma uvmf custom body end + endtask + + // **************************************************************************** + // FUNCTION : new() + // This function is the standard SystemVerilog constructor. + // + function new( string name =""); + super.new( name ); + // pragma uvmf custom new begin + req = axi_s_transaction_req_t::type_id::create("req"); + rsp = axi_s_transaction_rsp_t::type_id::create("rsp"); + // pragma uvmf custom new end + endfunction + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/axi_s_pkg/src/axi_s_transaction.svh b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/axi_s_pkg/src/axi_s_transaction.svh new file mode 100644 index 00000000..f8776dc6 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/axi_s_pkg/src/axi_s_transaction.svh @@ -0,0 +1,333 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This class defines the variables required for an axi_s +// transaction. Class variables to be displayed in waveform transaction +// viewing are added to the transaction viewing stream in the add_to_wave +// function. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class axi_s_transaction #( + int AW_WIDTH = 32, + int LEN = 8, + int DATA_WIDTH = 32, + int X = 16 + ) extends uvmf_transaction_base; + + `uvm_object_param_utils( axi_s_transaction #( + AW_WIDTH, + LEN, + DATA_WIDTH, + X + )) + + bit awvalid ; + bit awready ; + bit [AW_WIDTH-1:0] awaddr ; + bit awsize ; + bit awburst ; + bit awcache ; + bit awprot ; + bit [X-1:0] awid ; + bit [LEN-1:0] awlen ; + bit awlock ; + bit awqos ; + bit awregion ; + bit [X-1:0] awuser ; + bit wvalid ; + bit wready ; + bit wlast ; + bit [DATA_WIDTH-1:0] wdata ; + bit [DATA_WIDTH/8-1:0] wstrb ; + bit [X-1:0] wid ; + bit [X-1:0] wuser ; + bit bwvalid ; + bit bwready ; + rand bit bresp ; + bit [X-1:0] bid ; + rand bit [X-1:0] buser ; + bit arvalid ; + bit aready ; + rand bit [AW_WIDTH-1:0] araddr ; + rand bit arsize ; + rand bit arburst ; + rand bit arcache ; + rand bit arprot ; + rand bit [X-1:0] arid ; + rand bit [LEN-1:0] arlen ; + rand bit arlock ; + rand bit arqos ; + bit aregion ; + bit [X-1:0] aruser ; + bit rvalid ; + bit rready ; + bit rlast ; + rand bit [DATA_WIDTH-1:0] rdata ; + rand bit [X-1:0] rid ; + rand bit [X-1:0] ruser ; + rand bit rresp ; + + //Constraints for the transaction variables: + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + //******************************************************************* + //******************************************************************* + // Macros that define structs and associated functions are + // located in axi_s_macros.svh + + //******************************************************************* + // Monitor macro used by axi_s_monitor and axi_s_monitor_bfm + // This struct is defined in axi_s_macros.svh + `axi_s_MONITOR_STRUCT + axi_s_monitor_s axi_s_monitor_struct; + //******************************************************************* + // FUNCTION: to_monitor_struct() + // This function packs transaction variables into a axi_s_monitor_s + // structure. The function returns the handle to the axi_s_monitor_struct. + // This function is defined in axi_s_macros.svh + `axi_s_TO_MONITOR_STRUCT_FUNCTION + //******************************************************************* + // FUNCTION: from_monitor_struct() + // This function unpacks the struct provided as an argument into transaction + // variables of this class. + // This function is defined in axi_s_macros.svh + `axi_s_FROM_MONITOR_STRUCT_FUNCTION + + //******************************************************************* + // Initiator macro used by axi_s_driver and axi_s_driver_bfm + // to communicate initiator driven data to axi_s_driver_bfm. + // This struct is defined in axi_s_macros.svh + `axi_s_INITIATOR_STRUCT + axi_s_initiator_s axi_s_initiator_struct; + //******************************************************************* + // FUNCTION: to_initiator_struct() + // This function packs transaction variables into a axi_s_initiator_s + // structure. The function returns the handle to the axi_s_initiator_struct. + // This function is defined in axi_s_macros.svh + `axi_s_TO_INITIATOR_STRUCT_FUNCTION + //******************************************************************* + // FUNCTION: from_initiator_struct() + // This function unpacks the struct provided as an argument into transaction + // variables of this class. + // This function is defined in axi_s_macros.svh + `axi_s_FROM_INITIATOR_STRUCT_FUNCTION + + //******************************************************************* + // Responder macro used by axi_s_driver and axi_s_driver_bfm + // to communicate Responder driven data to axi_s_driver_bfm. + // This struct is defined in axi_s_macros.svh + `axi_s_RESPONDER_STRUCT + axi_s_responder_s axi_s_responder_struct; + //******************************************************************* + // FUNCTION: to_responder_struct() + // This function packs transaction variables into a axi_s_responder_s + // structure. The function returns the handle to the axi_s_responder_struct. + // This function is defined in axi_s_macros.svh + `axi_s_TO_RESPONDER_STRUCT_FUNCTION + //******************************************************************* + // FUNCTION: from_responder_struct() + // This function unpacks the struct provided as an argument into transaction + // variables of this class. + // This function is defined in axi_s_macros.svh + `axi_s_FROM_RESPONDER_STRUCT_FUNCTION + // **************************************************************************** + // FUNCTION : new() + // This function is the standard SystemVerilog constructor. + // + function new( string name = "" ); + super.new( name ); + endfunction + + // **************************************************************************** + // FUNCTION: convert2string() + // This function converts all variables in this class to a single string for + // logfile reporting. + // + virtual function string convert2string(); + // pragma uvmf custom convert2string begin + // UVMF_CHANGE_ME : Customize format if desired. + return $sformatf("awvalid:0x%x awready:0x%x awaddr:0x%x awsize:0x%x awburst:0x%x awcache:0x%x awprot:0x%x awid:0x%x awlen:0x%x awlock:0x%x awqos:0x%x awregion:0x%x awuser:0x%x wvalid:0x%x wready:0x%x wlast:0x%x wdata:0x%x wstrb:0x%x wid:0x%x wuser:0x%x bwvalid:0x%x bwready:0x%x bresp:0x%x bid:0x%x buser:0x%x arvalid:0x%x aready:0x%x araddr:0x%x arsize:0x%x arburst:0x%x arcache:0x%x arprot:0x%x arid:0x%x arlen:0x%x arlock:0x%x arqos:0x%x aregion:0x%x aruser:0x%x rvalid:0x%x rready:0x%x rlast:0x%x rdata:0x%x rid:0x%x ruser:0x%x rresp:0x%x ",awvalid,awready,awaddr,awsize,awburst,awcache,awprot,awid,awlen,awlock,awqos,awregion,awuser,wvalid,wready,wlast,wdata,wstrb,wid,wuser,bwvalid,bwready,bresp,bid,buser,arvalid,aready,araddr,arsize,arburst,arcache,arprot,arid,arlen,arlock,arqos,aregion,aruser,rvalid,rready,rlast,rdata,rid,ruser,rresp); + // pragma uvmf custom convert2string end + endfunction + + //******************************************************************* + // FUNCTION: do_print() + // This function is automatically called when the .print() function + // is called on this class. + // + virtual function void do_print(uvm_printer printer); + // pragma uvmf custom do_print begin + // UVMF_CHANGE_ME : Current contents of do_print allows for the use of UVM 1.1d, 1.2 or P1800.2. + // Update based on your own printing preference according to your preferred UVM version + $display(convert2string()); + // pragma uvmf custom do_print end + endfunction + + //******************************************************************* + // FUNCTION: do_compare() + // This function is automatically called when the .compare() function + // is called on this class. + // + virtual function bit do_compare (uvm_object rhs, uvm_comparer comparer); + axi_s_transaction #( + .AW_WIDTH(AW_WIDTH), + .LEN(LEN), + .DATA_WIDTH(DATA_WIDTH), + .X(X) + ) RHS; + if (!$cast(RHS,rhs)) return 0; + // pragma uvmf custom do_compare begin + // UVMF_CHANGE_ME : Eliminate comparison of variables not to be used for compare + return (super.do_compare(rhs,comparer) + ); + // pragma uvmf custom do_compare end + endfunction + + //******************************************************************* + // FUNCTION: do_copy() + // This function is automatically called when the .copy() function + // is called on this class. + // + virtual function void do_copy (uvm_object rhs); + axi_s_transaction #( + .AW_WIDTH(AW_WIDTH), + .LEN(LEN), + .DATA_WIDTH(DATA_WIDTH), + .X(X) + ) RHS; + assert($cast(RHS,rhs)); + // pragma uvmf custom do_copy begin + super.do_copy(rhs); + this.awvalid = RHS.awvalid; + this.awready = RHS.awready; + this.awaddr = RHS.awaddr; + this.awsize = RHS.awsize; + this.awburst = RHS.awburst; + this.awcache = RHS.awcache; + this.awprot = RHS.awprot; + this.awid = RHS.awid; + this.awlen = RHS.awlen; + this.awlock = RHS.awlock; + this.awqos = RHS.awqos; + this.awregion = RHS.awregion; + this.awuser = RHS.awuser; + this.wvalid = RHS.wvalid; + this.wready = RHS.wready; + this.wlast = RHS.wlast; + this.wdata = RHS.wdata; + this.wstrb = RHS.wstrb; + this.wid = RHS.wid; + this.wuser = RHS.wuser; + this.bwvalid = RHS.bwvalid; + this.bwready = RHS.bwready; + this.bresp = RHS.bresp; + this.bid = RHS.bid; + this.buser = RHS.buser; + this.arvalid = RHS.arvalid; + this.aready = RHS.aready; + this.araddr = RHS.araddr; + this.arsize = RHS.arsize; + this.arburst = RHS.arburst; + this.arcache = RHS.arcache; + this.arprot = RHS.arprot; + this.arid = RHS.arid; + this.arlen = RHS.arlen; + this.arlock = RHS.arlock; + this.arqos = RHS.arqos; + this.aregion = RHS.aregion; + this.aruser = RHS.aruser; + this.rvalid = RHS.rvalid; + this.rready = RHS.rready; + this.rlast = RHS.rlast; + this.rdata = RHS.rdata; + this.rid = RHS.rid; + this.ruser = RHS.ruser; + this.rresp = RHS.rresp; + // pragma uvmf custom do_copy end + endfunction + + // **************************************************************************** + // FUNCTION: add_to_wave() + // This function is used to display variables in this class in the waveform + // viewer. The start_time and end_time variables must be set before this + // function is called. If the start_time and end_time variables are not set + // the transaction will be hidden at 0ns on the waveform display. + // + virtual function void add_to_wave(int transaction_viewing_stream_h); + `ifdef QUESTA + if (transaction_view_h == 0) begin + transaction_view_h = $begin_transaction(transaction_viewing_stream_h,"axi_s_transaction",start_time); + end + super.add_to_wave(transaction_view_h); + // pragma uvmf custom add_to_wave begin + // UVMF_CHANGE_ME : Color can be applied to transaction entries based on content, example below + // case() + // 1 : $add_color(transaction_view_h,"red"); + // default : $add_color(transaction_view_h,"grey"); + // endcase + // UVMF_CHANGE_ME : Eliminate transaction variables not wanted in transaction viewing in the waveform viewer + $add_attribute(transaction_view_h,awvalid,"awvalid"); + $add_attribute(transaction_view_h,awready,"awready"); + $add_attribute(transaction_view_h,awaddr,"awaddr"); + $add_attribute(transaction_view_h,awsize,"awsize"); + $add_attribute(transaction_view_h,awburst,"awburst"); + $add_attribute(transaction_view_h,awcache,"awcache"); + $add_attribute(transaction_view_h,awprot,"awprot"); + $add_attribute(transaction_view_h,awid,"awid"); + $add_attribute(transaction_view_h,awlen,"awlen"); + $add_attribute(transaction_view_h,awlock,"awlock"); + $add_attribute(transaction_view_h,awqos,"awqos"); + $add_attribute(transaction_view_h,awregion,"awregion"); + $add_attribute(transaction_view_h,awuser,"awuser"); + $add_attribute(transaction_view_h,wvalid,"wvalid"); + $add_attribute(transaction_view_h,wready,"wready"); + $add_attribute(transaction_view_h,wlast,"wlast"); + $add_attribute(transaction_view_h,wdata,"wdata"); + $add_attribute(transaction_view_h,wstrb,"wstrb"); + $add_attribute(transaction_view_h,wid,"wid"); + $add_attribute(transaction_view_h,wuser,"wuser"); + $add_attribute(transaction_view_h,bwvalid,"bwvalid"); + $add_attribute(transaction_view_h,bwready,"bwready"); + $add_attribute(transaction_view_h,bresp,"bresp"); + $add_attribute(transaction_view_h,bid,"bid"); + $add_attribute(transaction_view_h,buser,"buser"); + $add_attribute(transaction_view_h,arvalid,"arvalid"); + $add_attribute(transaction_view_h,aready,"aready"); + $add_attribute(transaction_view_h,araddr,"araddr"); + $add_attribute(transaction_view_h,arsize,"arsize"); + $add_attribute(transaction_view_h,arburst,"arburst"); + $add_attribute(transaction_view_h,arcache,"arcache"); + $add_attribute(transaction_view_h,arprot,"arprot"); + $add_attribute(transaction_view_h,arid,"arid"); + $add_attribute(transaction_view_h,arlen,"arlen"); + $add_attribute(transaction_view_h,arlock,"arlock"); + $add_attribute(transaction_view_h,arqos,"arqos"); + $add_attribute(transaction_view_h,aregion,"aregion"); + $add_attribute(transaction_view_h,aruser,"aruser"); + $add_attribute(transaction_view_h,rvalid,"rvalid"); + $add_attribute(transaction_view_h,rready,"rready"); + $add_attribute(transaction_view_h,rlast,"rlast"); + $add_attribute(transaction_view_h,rdata,"rdata"); + $add_attribute(transaction_view_h,rid,"rid"); + $add_attribute(transaction_view_h,ruser,"ruser"); + $add_attribute(transaction_view_h,rresp,"rresp"); + // pragma uvmf custom add_to_wave end + $end_transaction(transaction_view_h,end_time); + $free_transaction(transaction_view_h); + `endif // QUESTA + endfunction + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/axi_s_pkg/src/axi_s_transaction_coverage.svh b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/axi_s_pkg/src/axi_s_transaction_coverage.svh new file mode 100644 index 00000000..03e4a490 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/axi_s_pkg/src/axi_s_transaction_coverage.svh @@ -0,0 +1,129 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This class records axi_s transaction information using +// a covergroup named axi_s_transaction_cg. An instance of this +// coverage component is instantiated in the uvmf_parameterized_agent +// if the has_coverage flag is set. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class axi_s_transaction_coverage #( + int AW_WIDTH = 32, + int LEN = 8, + int DATA_WIDTH = 32, + int X = 16 + ) extends uvm_subscriber #(.T(axi_s_transaction #( + .AW_WIDTH(AW_WIDTH), + .LEN(LEN), + .DATA_WIDTH(DATA_WIDTH), + .X(X) + ))); + + `uvm_component_param_utils( axi_s_transaction_coverage #( + AW_WIDTH, + LEN, + DATA_WIDTH, + X + )) + + T coverage_trans; + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + // **************************************************************************** + covergroup axi_s_transaction_cg; + // pragma uvmf custom covergroup begin + // UVMF_CHANGE_ME : Add coverage bins, crosses, exclusions, etc. according to coverage needs. + option.auto_bin_max=1024; + option.per_instance=1; + awvalid: coverpoint coverage_trans.awvalid; + awready: coverpoint coverage_trans.awready; + awaddr: coverpoint coverage_trans.awaddr; + awsize: coverpoint coverage_trans.awsize; + awburst: coverpoint coverage_trans.awburst; + awcache: coverpoint coverage_trans.awcache; + awprot: coverpoint coverage_trans.awprot; + awid: coverpoint coverage_trans.awid; + awlen: coverpoint coverage_trans.awlen; + awlock: coverpoint coverage_trans.awlock; + awqos: coverpoint coverage_trans.awqos; + awregion: coverpoint coverage_trans.awregion; + awuser: coverpoint coverage_trans.awuser; + wvalid: coverpoint coverage_trans.wvalid; + wready: coverpoint coverage_trans.wready; + wlast: coverpoint coverage_trans.wlast; + wdata: coverpoint coverage_trans.wdata; + wstrb: coverpoint coverage_trans.wstrb; + wid: coverpoint coverage_trans.wid; + wuser: coverpoint coverage_trans.wuser; + bwvalid: coverpoint coverage_trans.bwvalid; + bwready: coverpoint coverage_trans.bwready; + bresp: coverpoint coverage_trans.bresp; + bid: coverpoint coverage_trans.bid; + buser: coverpoint coverage_trans.buser; + arvalid: coverpoint coverage_trans.arvalid; + aready: coverpoint coverage_trans.aready; + araddr: coverpoint coverage_trans.araddr; + arsize: coverpoint coverage_trans.arsize; + arburst: coverpoint coverage_trans.arburst; + arcache: coverpoint coverage_trans.arcache; + arprot: coverpoint coverage_trans.arprot; + arid: coverpoint coverage_trans.arid; + arlen: coverpoint coverage_trans.arlen; + arlock: coverpoint coverage_trans.arlock; + arqos: coverpoint coverage_trans.arqos; + aregion: coverpoint coverage_trans.aregion; + aruser: coverpoint coverage_trans.aruser; + rvalid: coverpoint coverage_trans.rvalid; + rready: coverpoint coverage_trans.rready; + rlast: coverpoint coverage_trans.rlast; + rdata: coverpoint coverage_trans.rdata; + rid: coverpoint coverage_trans.rid; + ruser: coverpoint coverage_trans.ruser; + rresp: coverpoint coverage_trans.rresp; + // pragma uvmf custom covergroup end + endgroup + + // **************************************************************************** + // FUNCTION : new() + // This function is the standard SystemVerilog constructor. + // + function new(string name="", uvm_component parent=null); + super.new(name,parent); + axi_s_transaction_cg=new; + `uvm_warning("COVERAGE_MODEL_REVIEW", "A covergroup has been constructed which may need review because of either generation or re-generation with merging. Please note that transaction variables added as a result of re-generation and merging are not automatically added to the covergroup. Remove this warning after the covergroup has been reviewed.") + endfunction + + // **************************************************************************** + // FUNCTION : build_phase() + // This function is the standard UVM build_phase. + // + function void build_phase(uvm_phase phase); + axi_s_transaction_cg.set_inst_name($sformatf("axi_s_transaction_cg_%s",get_full_name())); + endfunction + + // **************************************************************************** + // FUNCTION: write (T t) + // This function is automatically executed when a transaction arrives on the + // analysis_export. It copies values from the variables in the transaction + // to local variables used to collect functional coverage. + // + virtual function void write (T t); + `uvm_info("COV","Received transaction",UVM_HIGH); + coverage_trans = t; + axi_s_transaction_cg.sample(); + endfunction + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/axi_s_pkg/src/axi_s_typedefs.svh b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/axi_s_pkg/src/axi_s_typedefs.svh new file mode 100644 index 00000000..43d85640 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/axi_s_pkg/src/axi_s_typedefs.svh @@ -0,0 +1,20 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: +// This file contains defines and typedefs to be compiled for use in +// the simulation running on the host server when using Veloce. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// + + +// pragma uvmf custom additional begin +// pragma uvmf custom additional end + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/axi_s_pkg/src/axi_s_typedefs_hdl.svh b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/axi_s_pkg/src/axi_s_typedefs_hdl.svh new file mode 100644 index 00000000..74738c8c --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/axi_s_pkg/src/axi_s_typedefs_hdl.svh @@ -0,0 +1,21 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: +// This file contains defines and typedefs to be compiled for use in +// the simulation running on the emulator when using Veloce. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// + + + +// pragma uvmf custom additional begin +// pragma uvmf custom additional end + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/axi_s_pkg/yaml/axi_s_interface.yaml b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/axi_s_pkg/yaml/axi_s_interface.yaml new file mode 100644 index 00000000..5f0bb407 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/axi_s_pkg/yaml/axi_s_interface.yaml @@ -0,0 +1,481 @@ +uvmf: + interfaces: + axi_s: + clock: axi_clk + config_constraints: [] + config_vars: [] + existing_library_component: 'True' + gen_inbound_streaming_driver: 'False' + hdl_pkg_parameters: [] + hdl_typedefs: [] + hvl_pkg_parameters: [] + hvl_typedefs: [] + parameters: + - name: AW_WIDTH + type: int + value: '32' + - name: LEN + type: int + value: '8' + - name: DATA_WIDTH + type: int + value: '32' + - name: X + type: int + value: '16' + ports: + - dir: input + name: awvalid + reset_value: '''bz' + width: '1' + - dir: output + name: awready + reset_value: '''bz' + width: '1' + - dir: input + name: awaddr + reset_value: '''bz' + width: AW_WIDTH + - dir: input + name: awsize + reset_value: '''bz' + width: '3' + - dir: input + name: awburst + reset_value: '''bz' + width: '2' + - dir: input + name: awcache + reset_value: '''bz' + width: '4' + - dir: input + name: awprot + reset_value: '''bz' + width: '3' + - dir: input + name: awid + reset_value: '''bz' + width: X + - dir: input + name: awlen + reset_value: '''bz' + width: LEN + - dir: input + name: awlock + reset_value: '''bz' + width: '1' + - dir: input + name: awqos + reset_value: '''bz' + width: '4' + - dir: input + name: awregion + reset_value: '''bz' + width: '4' + - dir: input + name: awuser + reset_value: '''bz' + width: X + - dir: input + name: wvalid + reset_value: '''bz' + width: '1' + - dir: output + name: wready + reset_value: '''bz' + width: '1' + - dir: input + name: wlast + reset_value: '''bz' + width: '1' + - dir: input + name: wdata + reset_value: '''bz' + width: DATA_WIDTH + - dir: input + name: wstrb + reset_value: '''bz' + width: DATA_WIDTH/8 + - dir: input + name: wid + reset_value: '''bz' + width: X + - dir: input + name: wuser + reset_value: '''bz' + width: X + - dir: output + name: bwvalid + reset_value: '''bz' + width: '1' + - dir: output + name: bwready + reset_value: '''bz' + width: '1' + - dir: input + name: bresp + reset_value: '''bz' + width: '2' + - dir: output + name: bid + reset_value: '''bz' + width: X + - dir: output + name: buser + reset_value: '''bz' + width: X + - dir: input + name: arvalid + reset_value: '''bz' + width: '1' + - dir: output + name: aready + reset_value: '''bz' + width: '1' + - dir: input + name: araddr + reset_value: '''bz' + width: AW_WIDTH + - dir: input + name: arsize + reset_value: '''bz' + width: '3' + - dir: input + name: arburst + reset_value: '''bz' + width: '2' + - dir: input + name: arcache + reset_value: '''bz' + width: '4' + - dir: input + name: arprot + reset_value: '''bz' + width: '3' + - dir: input + name: arid + reset_value: '''bz' + width: X + - dir: input + name: arlen + reset_value: '''bz' + width: LEN + - dir: input + name: arlock + reset_value: '''bz' + width: '1' + - dir: input + name: arqos + reset_value: '''bz' + width: '4' + - dir: input + name: aregion + reset_value: '''bz' + width: '4' + - dir: input + name: aruser + reset_value: '''bz' + width: X + - dir: output + name: rvalid + reset_value: '''bz' + width: '1' + - dir: input + name: rready + reset_value: '''bz' + width: '1' + - dir: output + name: rlast + reset_value: '''bz' + width: '1' + - dir: output + name: rdata + reset_value: '''bz' + width: DATA_WIDTH + - dir: output + name: rid + reset_value: '''bz' + width: X + - dir: output + name: ruser + reset_value: '''bz' + width: X + - dir: output + name: rresp + reset_value: '''bz' + width: '2' + reset: rst + reset_assertion_level: 'False' + transaction_constraints: [] + transaction_vars: + - comment: '' + iscompare: 'False' + isrand: 'False' + name: awvalid + type: bit + unpacked_dimension: '' + - comment: '' + iscompare: 'False' + isrand: 'False' + name: awready + type: bit + unpacked_dimension: '' + - comment: '' + iscompare: 'False' + isrand: 'False' + name: awaddr + type: bit [AW_WIDTH-1:0] + unpacked_dimension: '' + - comment: '' + iscompare: 'False' + isrand: 'False' + name: awsize + type: bit + unpacked_dimension: '' + - comment: '' + iscompare: 'False' + isrand: 'False' + name: awburst + type: bit + unpacked_dimension: '' + - comment: '' + iscompare: 'False' + isrand: 'False' + name: awcache + type: bit + unpacked_dimension: '' + - comment: '' + iscompare: 'False' + isrand: 'False' + name: awprot + type: bit + unpacked_dimension: '' + - comment: '' + iscompare: 'False' + isrand: 'False' + name: awid + type: bit [X-1:0] + unpacked_dimension: '' + - comment: '' + iscompare: 'False' + isrand: 'False' + name: awlen + type: bit [LEN-1:0] + unpacked_dimension: '' + - comment: '' + iscompare: 'False' + isrand: 'False' + name: awlock + type: bit + unpacked_dimension: '' + - comment: '' + iscompare: 'False' + isrand: 'False' + name: awqos + type: bit + unpacked_dimension: '' + - comment: '' + iscompare: 'False' + isrand: 'False' + name: awregion + type: bit + unpacked_dimension: '' + - comment: '' + iscompare: 'False' + isrand: 'False' + name: awuser + type: bit [X-1:0] + unpacked_dimension: '' + - comment: '' + iscompare: 'False' + isrand: 'False' + name: wvalid + type: bit + unpacked_dimension: '' + - comment: '' + iscompare: 'False' + isrand: 'False' + name: wready + type: bit + unpacked_dimension: '' + - comment: '' + iscompare: 'False' + isrand: 'False' + name: wlast + type: bit + unpacked_dimension: '' + - comment: '' + iscompare: 'False' + isrand: 'False' + name: wdata + type: bit [DATA_WIDTH-1:0] + unpacked_dimension: '' + - comment: '' + iscompare: 'False' + isrand: 'False' + name: wstrb + type: bit [DATA_WIDTH/8-1:0] + unpacked_dimension: '' + - comment: '' + iscompare: 'False' + isrand: 'False' + name: wid + type: bit [X-1:0] + unpacked_dimension: '' + - comment: '' + iscompare: 'False' + isrand: 'False' + name: wuser + type: bit [X-1:0] + unpacked_dimension: '' + - comment: '' + iscompare: 'False' + isrand: 'False' + name: bwvalid + type: bit + unpacked_dimension: '' + - comment: '' + iscompare: 'False' + isrand: 'False' + name: bwready + type: bit + unpacked_dimension: '' + - comment: '' + iscompare: 'False' + isrand: 'True' + name: bresp + type: bit + unpacked_dimension: '' + - comment: '' + iscompare: 'False' + isrand: 'False' + name: bid + type: bit [X-1:0] + unpacked_dimension: '' + - comment: '' + iscompare: 'False' + isrand: 'True' + name: buser + type: bit [X-1:0] + unpacked_dimension: '' + - comment: '' + iscompare: 'False' + isrand: 'False' + name: arvalid + type: bit + unpacked_dimension: '' + - comment: '' + iscompare: 'False' + isrand: 'False' + name: aready + type: bit + unpacked_dimension: '' + - comment: '' + iscompare: 'False' + isrand: 'True' + name: araddr + type: bit [AW_WIDTH-1:0] + unpacked_dimension: '' + - comment: '' + iscompare: 'False' + isrand: 'True' + name: arsize + type: bit + unpacked_dimension: '' + - comment: '' + iscompare: 'False' + isrand: 'True' + name: arburst + type: bit + unpacked_dimension: '' + - comment: '' + iscompare: 'False' + isrand: 'True' + name: arcache + type: bit + unpacked_dimension: '' + - comment: '' + iscompare: 'False' + isrand: 'True' + name: arprot + type: bit + unpacked_dimension: '' + - comment: '' + iscompare: 'False' + isrand: 'True' + name: arid + type: bit [X-1:0] + unpacked_dimension: '' + - comment: '' + iscompare: 'False' + isrand: 'True' + name: arlen + type: bit [LEN-1:0] + unpacked_dimension: '' + - comment: '' + iscompare: 'False' + isrand: 'True' + name: arlock + type: bit + unpacked_dimension: '' + - comment: '' + iscompare: 'False' + isrand: 'True' + name: arqos + type: bit + unpacked_dimension: '' + - comment: '' + iscompare: 'False' + isrand: 'False' + name: aregion + type: bit + unpacked_dimension: '' + - comment: '' + iscompare: 'False' + isrand: 'False' + name: aruser + type: bit [X-1:0] + unpacked_dimension: '' + - comment: '' + iscompare: 'False' + isrand: 'False' + name: rvalid + type: bit + unpacked_dimension: '' + - comment: '' + iscompare: 'False' + isrand: 'False' + name: rready + type: bit + unpacked_dimension: '' + - comment: '' + iscompare: 'False' + isrand: 'False' + name: rlast + type: bit + unpacked_dimension: '' + - comment: '' + iscompare: 'False' + isrand: 'True' + name: rdata + type: bit [DATA_WIDTH-1:0] + unpacked_dimension: '' + - comment: '' + iscompare: 'False' + isrand: 'True' + name: rid + type: bit [X-1:0] + unpacked_dimension: '' + - comment: '' + iscompare: 'False' + isrand: 'True' + name: ruser + type: bit [X-1:0] + unpacked_dimension: '' + - comment: '' + iscompare: 'False' + isrand: 'True' + name: rresp + type: bit + unpacked_dimension: '' + use_dpi_link: 'False' diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/spi_m_pkg/.project b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/spi_m_pkg/.project new file mode 100644 index 00000000..712c4d7d --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/spi_m_pkg/.project @@ -0,0 +1,30 @@ + + + spi_m_pkg + + + + + + org.python.pydev.PyDevBuilder + + + + + net.sf.sveditor.core.SVProjectBuilder + + + + + + net.sf.sveditor.core.SVNature + org.python.pydev.pythonNature + + + + UVMF_VIP_LIBRARY_HOME + $%7BPARENT-2-PROJECT_LOC%7D + + + + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/spi_m_pkg/.svproject b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/spi_m_pkg/.svproject new file mode 100644 index 00000000..df5b00f1 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/spi_m_pkg/.svproject @@ -0,0 +1,16 @@ + + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/spi_m_pkg/Makefile b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/spi_m_pkg/Makefile new file mode 100644 index 00000000..1dd05009 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/spi_m_pkg/Makefile @@ -0,0 +1,66 @@ +# spi_m interface packages source +# pragma uvmf custom additional begin +# pragma uvmf custom additional end + +spi_m_PKG = \ + +incdir+$(UVMF_VIP_LIBRARY_HOME)/interface_packages/spi_m_pkg \ + -F $(UVMF_VIP_LIBRARY_HOME)/interface_packages/spi_m_pkg/spi_m_filelist_hvl.f + +spi_m_PKG_HDL = \ + +incdir+$(UVMF_VIP_LIBRARY_HOME)/interface_packages/spi_m_pkg \ + -F $(UVMF_VIP_LIBRARY_HOME)/interface_packages/spi_m_pkg/spi_m_filelist_hdl.f + +spi_m_PKG_XRTL = \ + +incdir+$(UVMF_VIP_LIBRARY_HOME)/interface_packages/spi_m_pkg \ + -F $(UVMF_VIP_LIBRARY_HOME)/interface_packages/spi_m_pkg/spi_m_filelist_xrtl.f + +COMP_spi_m_PKG_TGT_0 = q_comp_spi_m_pkg +COMP_spi_m_PKG_TGT_1 = v_comp_spi_m_pkg +COMP_spi_m_PKG_TGT = $(COMP_spi_m_PKG_TGT_$(USE_VELOCE)) + +comp_spi_m_pkg: $(COMP_spi_m_PKG_TGT) + +q_comp_spi_m_pkg: + $(HDL_COMP_CMD) $(spi_m_PKG_HDL) + $(HVL_COMP_CMD) $(spi_m_PKG) + $(HDL_COMP_CMD) $(spi_m_PKG_XRTL) + +v_comp_spi_m_pkg: + $(HVL_COMP_CMD) $(spi_m_PKG_HDL) + $(HVL_COMP_CMD) $(spi_m_PKG) + $(VELANALYZE_CMD) $(spi_m_PKG_HDL) + $(VELANALYZE_HVL_CMD) $(spi_m_PKG) + $(HDL_COMP_CMD) $(spi_m_PKG_XRTL) + +ifeq ($(MTI_VCO_MODE),64) + GCC_COMP_ARCH = -m64 +else + GCC_COMP_ARCH = -m32 +endif + +export spi_m_IF_DPI_SRC ?= $(UVMF_VIP_LIBRARY_HOME)/interface_packages/spi_m_pkg/dpi + +C_FILE_COMPILE_LIST_spi_m_pkg = \ + +O_FILE_COMPILE_LIST_spi_m_pkg = $(notdir $(C_FILE_COMPILE_LIST_spi_m_pkg:.c=.o)) + +GCC_COMP_ARGS_spi_m_pkg += -I$(spi_m_IF_DPI_SRC) \ + -fPIC + +GCC_COMP_ARGS_spi_m_pkg += $(spi_m_IF_GCC_COMP_ARGUMENTS) + +GCC_LINK_ARGS_spi_m_pkg += \ + \ + -o .so + +comp_spi_m_pkg_c_files: + @echo "--------------------------------" + @echo "Compiling Interface C source" + @echo "--------------------------------" + gcc $(GCC_COMP_ARCH) $(GCC_COMP_ARGS_spi_m_pkg) $(C_FILE_COMPILE_LIST_spi_m_pkg) + @echo "--------------------------------" + @echo "Linking Interface C objects into a shared object" + @echo "--------------------------------" + gcc $(GCC_COMP_ARCH) $(GCC_LINK_ARGS_spi_m_pkg) $(O_FILE_COMPILE_LIST_spi_m_pkg) + @echo "--------------------------------" + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/spi_m_pkg/compile.do b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/spi_m_pkg/compile.do new file mode 100644 index 00000000..13f6b813 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/spi_m_pkg/compile.do @@ -0,0 +1,14 @@ +# Tcl do file for compile of spi_m interface + +# pragma uvmf custom additional begin +# pragma uvmf custom additional end + + +vlog -sv -timescale 1ps/1ps -suppress 2223,2286 +incdir+$env(UVMF_VIP_LIBRARY_HOME)/interface_packages/spi_m_pkg \ + -F $env(UVMF_VIP_LIBRARY_HOME)/interface_packages/spi_m_pkg/spi_m_filelist_hdl.f + +vlog -sv -timescale 1ps/1ps -suppress 2223,2286 +incdir+$env(UVMF_VIP_LIBRARY_HOME)/interface_packages/spi_m_pkg \ + -F $env(UVMF_VIP_LIBRARY_HOME)/interface_packages/spi_m_pkg/spi_m_filelist_hvl.f + +vlog -sv -timescale 1ps/1ps -suppress 2223,2286 +incdir+$env(UVMF_VIP_LIBRARY_HOME)/interface_packages/spi_m_pkg \ + -F $env(UVMF_VIP_LIBRARY_HOME)/interface_packages/spi_m_pkg/spi_m_filelist_xrtl.f \ No newline at end of file diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/spi_m_pkg/spi_m.compile b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/spi_m_pkg/spi_m.compile new file mode 100644 index 00000000..6cfb1a16 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/spi_m_pkg/spi_m.compile @@ -0,0 +1,3 @@ +needs: + - spi_m_hvl.compile + - spi_m_hdl.compile diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/spi_m_pkg/spi_m_bfm.vinfo b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/spi_m_pkg/spi_m_bfm.vinfo new file mode 100644 index 00000000..054f46b2 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/spi_m_pkg/spi_m_bfm.vinfo @@ -0,0 +1,6 @@ +@use $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg_hdl.vinfo +@use spi_m_pkg_hdl.vinfo ++incdir+@vinfodir +src/spi_m_if.sv +src/spi_m_driver_bfm.sv +src/spi_m_monitor_bfm.sv diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/spi_m_pkg/spi_m_common.compile b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/spi_m_pkg/spi_m_common.compile new file mode 100644 index 00000000..31a2c1bc --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/spi_m_pkg/spi_m_common.compile @@ -0,0 +1,7 @@ +needs: + - $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg_hdl.compile +incdir: + - . + - ${uvm_path}/src +src: + - spi_m_pkg_hdl.sv diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/spi_m_pkg/spi_m_filelist_hdl.f b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/spi_m_pkg/spi_m_filelist_hdl.f new file mode 100644 index 00000000..952ce3e3 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/spi_m_pkg/spi_m_filelist_hdl.f @@ -0,0 +1 @@ +$UVMF_VIP_LIBRARY_HOME/interface_packages/spi_m_pkg/spi_m_pkg_hdl.sv diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/spi_m_pkg/spi_m_filelist_hvl.f b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/spi_m_pkg/spi_m_filelist_hvl.f new file mode 100644 index 00000000..f7b45778 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/spi_m_pkg/spi_m_filelist_hvl.f @@ -0,0 +1 @@ +$UVMF_VIP_LIBRARY_HOME/interface_packages/spi_m_pkg/spi_m_pkg.sv \ No newline at end of file diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/spi_m_pkg/spi_m_filelist_xrtl.f b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/spi_m_pkg/spi_m_filelist_xrtl.f new file mode 100644 index 00000000..996b7bf9 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/spi_m_pkg/spi_m_filelist_xrtl.f @@ -0,0 +1,3 @@ +$UVMF_VIP_LIBRARY_HOME/interface_packages/spi_m_pkg/src/spi_m_if.sv +$UVMF_VIP_LIBRARY_HOME/interface_packages/spi_m_pkg/src/spi_m_monitor_bfm.sv +$UVMF_VIP_LIBRARY_HOME/interface_packages/spi_m_pkg/src/spi_m_driver_bfm.sv diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/spi_m_pkg/spi_m_hdl.compile b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/spi_m_pkg/spi_m_hdl.compile new file mode 100644 index 00000000..e0606ef0 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/spi_m_pkg/spi_m_hdl.compile @@ -0,0 +1,9 @@ +needs: + - $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg_hdl.compile + - ./spi_m_common.compile +incdir: + - . +src: + - src/spi_m_if.sv + - src/spi_m_monitor_bfm.sv + - src/spi_m_driver_bfm.sv diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/spi_m_pkg/spi_m_hvl.compile b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/spi_m_pkg/spi_m_hvl.compile new file mode 100644 index 00000000..ef56d81f --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/spi_m_pkg/spi_m_hvl.compile @@ -0,0 +1,7 @@ +needs: + - $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg.compile + - ./spi_m_common.compile +incdir: + - . +src: + - spi_m_pkg.sv diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/spi_m_pkg/spi_m_pkg.sv b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/spi_m_pkg/spi_m_pkg.sv new file mode 100644 index 00000000..326e87d4 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/spi_m_pkg/spi_m_pkg.sv @@ -0,0 +1,77 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// PACKAGE: This file defines all of the files contained in the +// interface package that will run on the host simulator. +// +// CONTAINS: +// - +// - +// - + +// - +// - +// - + +// - +// - +// - + +// - +// - +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +package spi_m_pkg; + + import uvm_pkg::*; + import uvmf_base_pkg_hdl::*; + import uvmf_base_pkg::*; + import spi_m_pkg_hdl::*; + + `include "uvm_macros.svh" + + // pragma uvmf custom package_imports_additional begin + // pragma uvmf custom package_imports_additional end + `include "src/spi_m_macros.svh" + + export spi_m_pkg_hdl::*; + + + + // Parameters defined as HVL parameters + + `include "src/spi_m_typedefs.svh" + `include "src/spi_m_transaction.svh" + + `include "src/spi_m_configuration.svh" + `include "src/spi_m_driver.svh" + `include "src/spi_m_monitor.svh" + + `include "src/spi_m_transaction_coverage.svh" + `include "src/spi_m_sequence_base.svh" + `include "src/spi_m_random_sequence.svh" + + `include "src/spi_m_responder_sequence.svh" + `include "src/spi_m2reg_adapter.svh" + + `include "src/spi_m_agent.svh" + + // pragma uvmf custom package_item_additional begin + // UVMF_CHANGE_ME : When adding new interface sequences to the src directory + // be sure to add the sequence file here so that it will be + // compiled as part of the interface package. Be sure to place + // the new sequence after any base sequences of the new sequence. + // pragma uvmf custom package_item_additional end + +endpackage + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/spi_m_pkg/spi_m_pkg.vinfo b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/spi_m_pkg/spi_m_pkg.vinfo new file mode 100644 index 00000000..a05007a1 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/spi_m_pkg/spi_m_pkg.vinfo @@ -0,0 +1,4 @@ +@use $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg.vinfo +@use spi_m_pkg_hdl.vinfo ++incdir+@vinfodir +spi_m_pkg.sv diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/spi_m_pkg/spi_m_pkg_hdl.sv b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/spi_m_pkg/spi_m_pkg_hdl.sv new file mode 100644 index 00000000..632e6786 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/spi_m_pkg/spi_m_pkg_hdl.sv @@ -0,0 +1,38 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// PACKAGE: This file defines all of the files contained in the +// interface package that needs to be compiled and synthesized +// for running on Veloce. +// +// CONTAINS: +// - +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +package spi_m_pkg_hdl; + + import uvmf_base_pkg_hdl::*; + + // pragma uvmf custom package_imports_additional begin + // pragma uvmf custom package_imports_additional end + + // Parameters defined as HDL parameters + + `include "src/spi_m_typedefs_hdl.svh" + `include "src/spi_m_macros.svh" + + // pragma uvmf custom package_item_additional begin + // pragma uvmf custom package_item_additional end + +endpackage + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/spi_m_pkg/spi_m_pkg_hdl.vinfo b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/spi_m_pkg/spi_m_pkg_hdl.vinfo new file mode 100644 index 00000000..ed83921b --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/spi_m_pkg/spi_m_pkg_hdl.vinfo @@ -0,0 +1,2 @@ +@use $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg_hdl.vinfo +spi_m_pkg_hdl.sv diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/spi_m_pkg/spi_m_pkg_sve.F b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/spi_m_pkg/spi_m_pkg_sve.F new file mode 100644 index 00000000..b48ecf8c --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/spi_m_pkg/spi_m_pkg_sve.F @@ -0,0 +1,10 @@ +// UVM ++incdir+${UVM_HOME}/src +${UVM_HOME}/src/uvm_pkg.sv + +// Common UVMF files +-f ${UVMF_HOME}/common/common_sve.f + ++incdir+. +-f ${UVMF_VIP_LIBRARY_HOME}/interface_packages/spi_m_pkg/spi_m_filelist_hdl.f +-f ${UVMF_VIP_LIBRARY_HOME}/interface_packages/spi_m_pkg/spi_m_filelist_hvl.f diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/spi_m_pkg/src/spi_m2reg_adapter.svh b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/spi_m_pkg/src/spi_m2reg_adapter.svh new file mode 100644 index 00000000..800ec5da --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/spi_m_pkg/src/spi_m2reg_adapter.svh @@ -0,0 +1,98 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: +// This file contains the UVM register adapter for the spi_m interface. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class spi_m2reg_adapter extends uvm_reg_adapter; + + `uvm_object_utils( spi_m2reg_adapter ) + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + //-------------------------------------------------------------------- + // new + //-------------------------------------------------------------------- + function new (string name = "spi_m2reg_adapter" ); + super.new(name); + // pragma uvmf custom new begin + // UVMF_CHANGE_ME : Configure the adapter regarding byte enables and provides response. + + // Does the protocol the Agent is modeling support byte enables? + // 0 = NO + // 1 = YES + supports_byte_enable = 0; + + // Does the Agent's Driver provide separate response sequence items? + // i.e. Does the driver call seq_item_port.put() + // and do the sequences call get_response()? + // 0 = NO + // 1 = YES + provides_responses = 0; + // pragma uvmf custom new end + + endfunction: new + + //-------------------------------------------------------------------- + // reg2bus + //-------------------------------------------------------------------- + virtual function uvm_sequence_item reg2bus(const ref uvm_reg_bus_op rw); + + spi_m_transaction trans_h = spi_m_transaction ::type_id::create("trans_h"); + + // pragma uvmf custom reg2bus begin + // UVMF_CHANGE_ME : Fill in the reg2bus adapter mapping registe fields to protocol fields. + + //Adapt the following for your sequence item type + // trans_h.op = (rw.kind == UVM_READ) ? WB_READ : WB_WRITE; + //Copy over address + // trans_h.addr = rw.addr; + //Copy over write data + // trans_h.data = rw.data; + + // pragma uvmf custom reg2bus end + + // Return the adapted transaction + return trans_h; + + endfunction: reg2bus + + //-------------------------------------------------------------------- + // bus2reg + //-------------------------------------------------------------------- + virtual function void bus2reg(uvm_sequence_item bus_item, + ref uvm_reg_bus_op rw); + spi_m_transaction trans_h; + if (!$cast(trans_h, bus_item)) begin + `uvm_fatal("ADAPT","Provided bus_item is not of the correct type") + return; + end + // pragma uvmf custom bus2reg begin + // UVMF_CHANGE_ME : Fill in the bus2reg adapter mapping protocol fields to register fields. + //Adapt the following for your sequence item type + //Copy over instruction type + // rw.kind = (trans_h.op == WB_WRITE) ? UVM_WRITE : UVM_READ; + //Copy over address + // rw.addr = trans_h.addr; + //Copy over read data + // rw.data = trans_h.data; + //Check for errors on the bus and return UVM_NOT_OK if there is an error + // rw.status = UVM_IS_OK; + // pragma uvmf custom bus2reg end + + endfunction: bus2reg + +endclass : spi_m2reg_adapter + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/spi_m_pkg/src/spi_m_agent.svh b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/spi_m_pkg/src/spi_m_agent.svh new file mode 100644 index 00000000..99c5d200 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/spi_m_pkg/src/spi_m_agent.svh @@ -0,0 +1,53 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: Protocol specific agent class definition +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class spi_m_agent extends uvmf_parameterized_agent #( + .CONFIG_T(spi_m_configuration ), + .DRIVER_T(spi_m_driver ), + .MONITOR_T(spi_m_monitor ), + .COVERAGE_T(spi_m_transaction_coverage ), + .TRANS_T(spi_m_transaction ) + ); + + `uvm_component_utils( spi_m_agent ) + +// pragma uvmf custom class_item_additional begin +// pragma uvmf custom class_item_additional end + +// **************************************************************************** +// FUNCTION : new() +// This function is the standard SystemVerilog constructor. +// + function new( string name = "", uvm_component parent = null ); + super.new( name, parent ); + endfunction + +// **************************************************************************** + // FUNCTION: build_phase + virtual function void build_phase(uvm_phase phase); +// pragma uvmf custom build_phase_pre_super begin +// pragma uvmf custom build_phase_pre_super end + super.build_phase(phase); + if (configuration.active_passive == ACTIVE) begin + // Place sequencer handle into configuration object + // so that it may be retrieved from configuration + // rather than using uvm_config_db + configuration.sequencer = this.sequencer; + end + endfunction + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/spi_m_pkg/src/spi_m_configuration.svh b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/spi_m_pkg/src/spi_m_configuration.svh new file mode 100644 index 00000000..9c71a8ea --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/spi_m_pkg/src/spi_m_configuration.svh @@ -0,0 +1,179 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This class contains all variables and functions used +// to configure the spi_m agent and its bfm's. It gets the +// bfm's from the uvm_config_db for use by the agent. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class spi_m_configuration extends uvmf_parameterized_agent_configuration_base #( + .DRIVER_BFM_BIND_T(virtual spi_m_driver_bfm ), + .MONITOR_BFM_BIND_T( virtual spi_m_monitor_bfm )); + + `uvm_object_utils( spi_m_configuration ) + + + // Sequencer handle populated by agent + uvm_sequencer #(spi_m_transaction ) sequencer; + + //Constraints for the configuration variables: + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + covergroup spi_m_configuration_cg; + // pragma uvmf custom covergroup begin + option.auto_bin_max=1024; + // pragma uvmf custom covergroup end + endgroup + + //******************************************************************* + //******************************************************************* + // Structure used to pass configuration variables to monitor and driver BFM's. + // Use to_struct function to pack variables into structure. + // Use from_struct function to unpack variables from structure. + // This structure is defined in spi_m_macros.svh + `spi_m_CONFIGURATION_STRUCT + spi_m_configuration_s spi_m_configuration_struct; + //******************************************************************* + // FUNCTION: to_struct() + // This function packs variables into a spi_m_configuration_s + // structure. The function returns the handle to the spi_m_configuration_struct. + // This function is defined in spi_m_macros.svh + `spi_m_CONFIGURATION_TO_STRUCT_FUNCTION + //******************************************************************* + // FUNCTION: from_struct() + // This function unpacks the struct provided as an argument into + // variables of this class. + // This function is defined in spi_m_macros.svh + `spi_m_CONFIGURATION_FROM_STRUCT_FUNCTION + + // **************************************************************************** + // FUNCTION : new() + // This function is the standard SystemVerilog constructor. + // + function new( string name = "" ); + super.new( name ); + // Construct the covergroup for this configuration class + spi_m_configuration_cg = new; + endfunction + + // **************************************************************************** + // FUNCTION: post_randomize() + // This function is automatically called after the randomize() function + // is executed. + // + function void post_randomize(); + super.post_randomize(); + spi_m_configuration_cg.sample(); + endfunction + + // **************************************************************************** + // FUNCTION: initialize + // This function causes the configuration to retrieve + // its virtual interface handle from the uvm_config_db. + // This function also makes itself available to its + // agent through the uvm_config_db. + // + // ARGUMENTS: + // uvmf_active_passive_t activity: + // This argument identifies the simulation level + // as either BLOCK, CHIP, SIMULATION, etc. + // + // AGENT_PATH: + // This argument identifies the path to this + // configurations agent. This configuration + // makes itself available to the agent specified + // by agent_path by placing itself into the + // uvm_config_db. + // + // INTERFACE_NAME: + // This argument identifies the string name of + // this configurations BFM's. This string + // name is used to retrieve the driver and + // monitor BFM from the uvm_config_db. + // + virtual function void initialize(uvmf_active_passive_t activity, + string agent_path, + string interface_name); + + super.initialize( activity, agent_path, interface_name); + // The covergroup is given the same name as the interface + spi_m_configuration_cg.set_inst_name(interface_name); + + // This configuration places itself into the uvm_config_db for the agent, identified by the agent_path variable, to retrieve. + uvm_config_db #( spi_m_configuration + )::set( null ,agent_path,UVMF_AGENT_CONFIG, this ); + + // This configuration also places itself in the config db using the same identifier used by the interface. This allows users to access + // configuration variables and the interface through the bfm api class rather than directly accessing the BFM. This is useful for + // accessingthe BFM when using Veloce + uvm_config_db #( spi_m_configuration + )::set( null ,UVMF_CONFIGURATIONS, interface_name, this ); + + spi_m_configuration_cg.set_inst_name($sformatf("spi_m_configuration_cg_%s",get_full_name())); + +// This code is to aid in debugging parameter mismatches between the BFM and its corresponding agent. +// Enable this debug by setting UVM_VERBOSITY to UVM_DEBUG +// Setting UVM_VERBOSITY to UVM_DEBUG causes all BFM's and all agents to display their parameter settings. +// All of the messages from this feature have a UVM messaging id value of "CFG" +// The transcript or run.log can be parsed to ensure BFM parameter settings match its corresponding agents parameter settings. + `uvm_info("CFG", + $psprintf("The agent at '%s' is using interface named %s has the following parameters: ", agent_path, interface_name, ), + UVM_DEBUG) + + // pragma uvmf custom initialize begin + // This controls whether or not the agent returns a transaction handle in the driver when calling + // item_done() back into the sequencer or not. If set to 1, a transaction is sent back which means + // the sequence on the other end must use the get_response() part of the driver/sequence API. If + // this doesn't occur, there will eventually be response_queue overflow errors during the test. + return_transaction_response = 1'b0; + + // pragma uvmf custom initialize end + + endfunction + + // **************************************************************************** + // TASK: wait_for_reset + // *[Required]* Blocks until reset is released. The wait_for_reset operation is performed + // by a task in the monitor bfm. + virtual task wait_for_reset(); + monitor_bfm.wait_for_reset(); + endtask + + // **************************************************************************** + // TASK: wait_for_num_clocks + // *[Required]* Blocks until specified number of clocks have elapsed. The wait_for_num_clocks + // operation is performed by a task in the monitor bfm. + virtual task wait_for_num_clocks(int clocks); + monitor_bfm.wait_for_num_clocks(clocks); + endtask + + // **************************************************************************** + // FUNCTION : convert2string() + // This function is used to convert variables in this class into a string for log messaging. + // + virtual function string convert2string (); + // pragma uvmf custom convert2string begin + return $sformatf(""); + // pragma uvmf custom convert2string end + endfunction + + // **************************************************************************** + // FUNCTION: get_sequencer + function uvm_sequencer #(spi_m_transaction) get_sequencer(); + return sequencer; + endfunction + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/spi_m_pkg/src/spi_m_driver.svh b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/spi_m_pkg/src/spi_m_driver.svh new file mode 100644 index 00000000..89417864 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/spi_m_pkg/src/spi_m_driver.svh @@ -0,0 +1,91 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This class passes transactions between the sequencer +// and the BFM driver interface. It accesses the driver BFM +// through the bfm handle. This driver +// passes transactions to the driver BFM through the access +// task. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class spi_m_driver extends uvmf_driver_base #( + .CONFIG_T(spi_m_configuration ), + .BFM_BIND_T(virtual spi_m_driver_bfm ), + .REQ(spi_m_transaction ), + .RSP(spi_m_transaction )); + + `uvm_component_utils( spi_m_driver ) +//******************************************************************* +// Macros that define structs located in spi_m_macros.svh +//******************************************************************* +// Initiator macro used by spi_m_driver and spi_m_driver_bfm +// to communicate initiator driven data to spi_m_driver_bfm. +`spi_m_INITIATOR_STRUCT + spi_m_initiator_s spi_m_initiator_struct; +//******************************************************************* +// Responder macro used by spi_m_driver and spi_m_driver_bfm +// to communicate Responder driven data to spi_m_driver_bfm. +`spi_m_RESPONDER_STRUCT + spi_m_responder_s spi_m_responder_struct; + +// pragma uvmf custom class_item_additional begin +// pragma uvmf custom class_item_additional end + +// **************************************************************************** +// This function is the standard SystemVerilog constructor. +// + function new( string name = "", uvm_component parent=null ); + super.new( name, parent ); + endfunction + +// **************************************************************************** +// This function sends configuration object variables to the driver BFM +// using the configuration struct. +// + virtual function void configure(input CONFIG_T cfg); + bfm.configure( cfg.to_struct() ); + endfunction + +// **************************************************************************** +// This function places a handle to this class in the proxy variable in the +// driver BFM. This allows the driver BFM to call tasks and function within this class. +// + virtual function void set_bfm_proxy_handle(); + bfm.proxy = this; endfunction + +// **************************************************************************** +// This task is called by the run_phase in uvmf_driver_base. + virtual task access( inout REQ txn ); +// pragma uvmf custom access begin + if (configuration.initiator_responder==RESPONDER) begin + // Complete current transfer and wait for next transfer + bfm.respond_and_wait_for_next_transfer( + spi_m_initiator_struct, + txn.to_responder_struct() + ); + // Unpack information about initiated transfer received by this responder + txn.from_initiator_struct(spi_m_initiator_struct); + end else begin + // Initiate a transfer and get response + bfm.initiate_and_get_response( + txn.to_initiator_struct(), + spi_m_responder_struct + ); + // Unpack transfer response information received by this initiator + txn.from_responder_struct(spi_m_responder_struct); + end +// pragma uvmf custom access end + endtask + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/spi_m_pkg/src/spi_m_driver_bfm.sv b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/spi_m_pkg/src/spi_m_driver_bfm.sv new file mode 100644 index 00000000..7b70757a --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/spi_m_pkg/src/spi_m_driver_bfm.sv @@ -0,0 +1,300 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: +// This interface performs the spi_m signal driving. It is +// accessed by the uvm spi_m driver through a virtual interface +// handle in the spi_m configuration. It drives the singals passed +// in through the port connection named bus of type spi_m_if. +// +// Input signals from the spi_m_if are assigned to an internal input +// signal with a _i suffix. The _i signal should be used for sampling. +// +// The input signal connections are as follows: +// bus.signal -> signal_i +// +// This bfm drives signals with a _o suffix. These signals +// are driven onto signals within spi_m_if based on INITIATOR/RESPONDER and/or +// ARBITRATION/GRANT status. +// +// The output signal connections are as follows: +// signal_o -> bus.signal +// +// +// Interface functions and tasks used by UVM components: +// +// configure: +// This function gets configuration attributes from the +// UVM driver to set any required BFM configuration +// variables such as 'initiator_responder'. +// +// initiate_and_get_response: +// This task is used to perform signaling activity for initiating +// a protocol transfer. The task initiates the transfer, using +// input data from the initiator struct. Then the task captures +// response data, placing the data into the response struct. +// The response struct is returned to the driver class. +// +// respond_and_wait_for_next_transfer: +// This task is used to complete a current transfer as a responder +// and then wait for the initiator to start the next transfer. +// The task uses data in the responder struct to drive protocol +// signals to complete the transfer. The task then waits for +// the next transfer. Once the next transfer begins, data from +// the initiator is placed into the initiator struct and sent +// to the responder sequence for processing to determine +// what data to respond with. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +import uvmf_base_pkg_hdl::*; +import spi_m_pkg_hdl::*; +`include "src/spi_m_macros.svh" + +interface spi_m_driver_bfm + (spi_m_if bus); + // The following pragma and additional ones in-lined further below are for running this BFM on Veloce + // pragma attribute spi_m_driver_bfm partition_interface_xif + +`ifndef XRTL +// This code is to aid in debugging parameter mismatches between the BFM and its corresponding agent. +// Enable this debug by setting UVM_VERBOSITY to UVM_DEBUG +// Setting UVM_VERBOSITY to UVM_DEBUG causes all BFM's and all agents to display their parameter settings. +// All of the messages from this feature have a UVM messaging id value of "CFG" +// The transcript or run.log can be parsed to ensure BFM parameter settings match its corresponding agents parameter settings. +import uvm_pkg::*; +`include "uvm_macros.svh" +initial begin : bfm_vs_agent_parameter_debug + `uvm_info("CFG", + $psprintf("The BFM at '%m' has the following parameters: ", ), + UVM_DEBUG) +end +`endif + + // Config value to determine if this is an initiator or a responder + uvmf_initiator_responder_t initiator_responder; + // Custom configuration variables. + // These are set using the configure function which is called during the UVM connect_phase + + logic sck_i; + logic rst_i; + + // Signal list (all signals are capable of being inputs and outputs for the sake + // of supporting both INITIATOR and RESPONDER mode operation. Expectation is that + // directionality in the config file was from the point-of-view of the INITIATOR + + // INITIATOR mode input signals + tri [7:0] miso_i; + reg [7:0] miso_o = 'b0; + + // INITIATOR mode output signals + tri sclk_i; + reg sclk_o = 'b0; + tri ss_i; + reg ss_o = 'b0; + tri [7:0] mosi_i; + reg [7:0] mosi_o = 'b0; + + // Bi-directional signals + + + assign sck_i = bus.sck; + assign rst_i = bus.rst; + + // These are signals marked as 'input' by the config file, but the signals will be + // driven by this BFM if put into RESPONDER mode (flipping all signal directions around) + assign miso_i = bus.miso; + assign bus.miso = (initiator_responder == RESPONDER) ? miso_o : 'bz; + + + // These are signals marked as 'output' by the config file, but the outputs will + // not be driven by this BFM unless placed in INITIATOR mode. + assign bus.sclk = (initiator_responder == INITIATOR) ? sclk_o : 'bz; + assign sclk_i = bus.sclk; + assign bus.ss = (initiator_responder == INITIATOR) ? ss_o : 'bz; + assign ss_i = bus.ss; + assign bus.mosi = (initiator_responder == INITIATOR) ? mosi_o : 'bz; + assign mosi_i = bus.mosi; + + // Proxy handle to UVM driver + spi_m_pkg::spi_m_driver proxy; + // pragma tbx oneway proxy.my_function_name_in_uvm_driver + + // **************************************************************************** + // **************************************************************************** + // Macros that define structs located in spi_m_macros.svh + // **************************************************************************** + // Struct for passing configuration data from spi_m_driver to this BFM + // **************************************************************************** + `spi_m_CONFIGURATION_STRUCT + // **************************************************************************** + // Structs for INITIATOR and RESPONDER data flow + //******************************************************************* + // Initiator macro used by spi_m_driver and spi_m_driver_bfm + // to communicate initiator driven data to spi_m_driver_bfm. + `spi_m_INITIATOR_STRUCT + spi_m_initiator_s initiator_struct; + // Responder macro used by spi_m_driver and spi_m_driver_bfm + // to communicate Responder driven data to spi_m_driver_bfm. + `spi_m_RESPONDER_STRUCT + spi_m_responder_s responder_struct; + + // **************************************************************************** +// pragma uvmf custom reset_condition_and_response begin + // Always block used to return signals to reset value upon assertion of reset + always @( posedge rst_i ) + begin + // RESPONDER mode output signals + miso_o <= 'b0; + // INITIATOR mode output signals + sclk_o <= 'b0; + ss_o <= 'b0; + mosi_o <= 'b0; + // Bi-directional signals + + end +// pragma uvmf custom reset_condition_and_response end + + // pragma uvmf custom interface_item_additional begin + // pragma uvmf custom interface_item_additional end + + //****************************************************************** + // The configure() function is used to pass agent configuration + // variables to the driver BFM. It is called by the driver within + // the agent at the beginning of the simulation. It may be called + // during the simulation if agent configuration variables are updated + // and the driver BFM needs to be aware of the new configuration + // variables. + // + + function void configure(spi_m_configuration_s spi_m_configuration_arg); // pragma tbx xtf + initiator_responder = spi_m_configuration_arg.initiator_responder; + // pragma uvmf custom configure begin + // pragma uvmf custom configure end + endfunction + +// pragma uvmf custom initiate_and_get_response begin +// **************************************************************************** +// UVMF_CHANGE_ME +// This task is used by an initator. The task first initiates a transfer then +// waits for the responder to complete the transfer. + task initiate_and_get_response( + // This argument passes transaction variables used by an initiator + // to perform the initial part of a protocol transfer. The values + // come from a sequence item created in a sequence. + input spi_m_initiator_s spi_m_initiator_struct, + // This argument is used to send data received from the responder + // back to the sequence item. The sequence item is returned to the sequence. + output spi_m_responder_s spi_m_responder_struct + );// pragma tbx xtf + // + // Members within the spi_m_initiator_struct: + // bit ssel ; + // bit [7:0] mosi ; + // bit [7:0] miso ; + // Members within the spi_m_responder_struct: + // bit ssel ; + // bit [7:0] mosi ; + // bit [7:0] miso ; + initiator_struct = spi_m_initiator_struct; + // + // Reference code; + // How to wait for signal value + // while (control_signal == 1'b1) @(posedge sck_i); + // + // How to assign a responder struct member, named xyz, from a signal. + // All available initiator input and inout signals listed. + // Initiator input signals + // spi_m_responder_struct.xyz = miso_i; // [7:0] + // Initiator inout signals + // How to assign a signal from an initiator struct member named xyz. + // All available initiator output and inout signals listed. + // Notice the _o. Those are storage variables that allow for procedural assignment. + // Initiator output signals + // sclk_o <= spi_m_initiator_struct.xyz; // + // ss_o <= spi_m_initiator_struct.xyz; // + // mosi_o <= spi_m_initiator_struct.xyz; // [7:0] + // Initiator inout signals + // Initiate a transfer using the data received. + @(posedge sck_i); + @(posedge sck_i); + // Wait for the responder to complete the transfer then place the responder data into + // spi_m_responder_struct. + @(posedge sck_i); + @(posedge sck_i); + responder_struct = spi_m_responder_struct; + endtask +// pragma uvmf custom initiate_and_get_response end + +// pragma uvmf custom respond_and_wait_for_next_transfer begin +// **************************************************************************** +// The first_transfer variable is used to prevent completing a transfer in the +// first call to this task. For the first call to this task, there is not +// current transfer to complete. +bit first_transfer=1; + +// UVMF_CHANGE_ME +// This task is used by a responder. The task first completes the current +// transfer in progress then waits for the initiator to start the next transfer. + task respond_and_wait_for_next_transfer( + // This argument is used to send data received from the initiator + // back to the sequence item. The sequence determines how to respond. + output spi_m_initiator_s spi_m_initiator_struct, + // This argument passes transaction variables used by a responder + // to complete a protocol transfer. The values come from a sequence item. + input spi_m_responder_s spi_m_responder_struct + );// pragma tbx xtf + // Variables within the spi_m_initiator_struct: + // bit ssel ; + // bit [7:0] mosi ; + // bit [7:0] miso ; + // Variables within the spi_m_responder_struct: + // bit ssel ; + // bit [7:0] mosi ; + // bit [7:0] miso ; + // Reference code; + // How to wait for signal value + // while (control_signal == 1'b1) @(posedge sck_i); + // + // How to assign a responder struct member, named xyz, from a signal. + // All available responder input and inout signals listed. + // Responder input signals + // spi_m_responder_struct.xyz = sclk_i; // + // spi_m_responder_struct.xyz = ss_i; // + // spi_m_responder_struct.xyz = mosi_i; // [7:0] + // Responder inout signals + // How to assign a signal, named xyz, from an initiator struct member. + // All available responder output and inout signals listed. + // Notice the _o. Those are storage variables that allow for procedural assignment. + // Responder output signals + // miso_o <= spi_m_initiator_struct.xyz; // [7:0] + // Responder inout signals + + @(posedge sck_i); + if (!first_transfer) begin + // Perform transfer response here. + // Reply using data recieved in the spi_m_responder_struct. + @(posedge sck_i); + // Reply using data recieved in the transaction handle. + @(posedge sck_i); + end + // Wait for next transfer then gather info from intiator about the transfer. + // Place the data into the spi_m_initiator_struct. + @(posedge sck_i); + @(posedge sck_i); + first_transfer = 0; + endtask +// pragma uvmf custom respond_and_wait_for_next_transfer end + + +endinterface + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/spi_m_pkg/src/spi_m_if.sv b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/spi_m_pkg/src/spi_m_if.sv new file mode 100644 index 00000000..3f88074f --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/spi_m_pkg/src/spi_m_if.sv @@ -0,0 +1,79 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This interface contains the spi_m interface signals. +// It is instantiated once per spi_m bus. Bus Functional Models, +// BFM's named spi_m_driver_bfm, are used to drive signals on the bus. +// BFM's named spi_m_monitor_bfm are used to monitor signals on the +// bus. This interface signal bundle is passed in the port list of +// the BFM in order to give the BFM access to the signals in this +// interface. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// This template can be used to connect a DUT to these signals +// +// .dut_signal_port(spi_m_bus.sclk), // Agent output +// .dut_signal_port(spi_m_bus.ss), // Agent output +// .dut_signal_port(spi_m_bus.mosi), // Agent output +// .dut_signal_port(spi_m_bus.miso), // Agent input + +import uvmf_base_pkg_hdl::*; +import spi_m_pkg_hdl::*; + +interface spi_m_if + + ( + input logic sck, + input logic rst, + output logic sclk, + output logic ss, + output logic [7:0] mosi, + input logic [7:0] miso + ); + +modport monitor_port + ( + input sck, + input rst, + input sclk, + input ss, + input mosi, + input miso + ); + +modport initiator_port + ( + input sck, + input rst, + output sclk, + output ss, + output mosi, + input miso + ); + +modport responder_port + ( + input sck, + input rst, + input sclk, + input ss, + input mosi, + output miso + ); + + +// pragma uvmf custom interface_item_additional begin +// pragma uvmf custom interface_item_additional end + +endinterface + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/spi_m_pkg/src/spi_m_infact_coverage_strategy.csv b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/spi_m_pkg/src/spi_m_infact_coverage_strategy.csv new file mode 100644 index 00000000..1c218e14 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/spi_m_pkg/src/spi_m_infact_coverage_strategy.csv @@ -0,0 +1,6 @@ +Global +auto_bin_max, 64 + +Name,Type,Include +rand_fields,coverpoint,=rand *.** + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/spi_m_pkg/src/spi_m_macros.svh b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/spi_m_pkg/src/spi_m_macros.svh new file mode 100644 index 00000000..a67d1c47 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/spi_m_pkg/src/spi_m_macros.svh @@ -0,0 +1,139 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This file contains macros used with the spi_m package. +// These macros include packed struct definitions. These structs are +// used to pass data between classes, hvl, and BFM's, hdl. Use of +// structs are more efficient and simpler to modify. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// + +// **************************************************************************** +// When changing the contents of this struct, be sure to update the to_struct +// and from_struct methods defined in the macros below that are used in +// the spi_m_configuration class. +// + `define spi_m_CONFIGURATION_STRUCT \ +typedef struct packed { \ + uvmf_active_passive_t active_passive; \ + uvmf_initiator_responder_t initiator_responder; \ + } spi_m_configuration_s; + + `define spi_m_CONFIGURATION_TO_STRUCT_FUNCTION \ + virtual function spi_m_configuration_s to_struct();\ + spi_m_configuration_struct = \ + {\ + this.active_passive,\ + this.initiator_responder\ + };\ + return ( spi_m_configuration_struct );\ + endfunction + + `define spi_m_CONFIGURATION_FROM_STRUCT_FUNCTION \ + virtual function void from_struct(spi_m_configuration_s spi_m_configuration_struct);\ + {\ + this.active_passive,\ + this.initiator_responder \ + } = spi_m_configuration_struct;\ + endfunction + +// **************************************************************************** +// When changing the contents of this struct, be sure to update the to_monitor_struct +// and from_monitor_struct methods of the spi_m_transaction class. +// + `define spi_m_MONITOR_STRUCT typedef struct packed { \ + bit ssel ; \ + bit [7:0] mosi ; \ + bit [7:0] miso ; \ + } spi_m_monitor_s; + + `define spi_m_TO_MONITOR_STRUCT_FUNCTION \ + virtual function spi_m_monitor_s to_monitor_struct();\ + spi_m_monitor_struct = \ + { \ + this.ssel , \ + this.mosi , \ + this.miso \ + };\ + return ( spi_m_monitor_struct);\ + endfunction\ + + `define spi_m_FROM_MONITOR_STRUCT_FUNCTION \ + virtual function void from_monitor_struct(spi_m_monitor_s spi_m_monitor_struct);\ + {\ + this.ssel , \ + this.mosi , \ + this.miso \ + } = spi_m_monitor_struct;\ + endfunction + +// **************************************************************************** +// When changing the contents of this struct, be sure to update the to_initiator_struct +// and from_initiator_struct methods of the spi_m_transaction class. +// Also update the comments in the driver BFM. +// + `define spi_m_INITIATOR_STRUCT typedef struct packed { \ + bit ssel ; \ + bit [7:0] mosi ; \ + bit [7:0] miso ; \ + } spi_m_initiator_s; + + `define spi_m_TO_INITIATOR_STRUCT_FUNCTION \ + virtual function spi_m_initiator_s to_initiator_struct();\ + spi_m_initiator_struct = \ + {\ + this.ssel , \ + this.mosi , \ + this.miso \ + };\ + return ( spi_m_initiator_struct);\ + endfunction + + `define spi_m_FROM_INITIATOR_STRUCT_FUNCTION \ + virtual function void from_initiator_struct(spi_m_initiator_s spi_m_initiator_struct);\ + {\ + this.ssel , \ + this.mosi , \ + this.miso \ + } = spi_m_initiator_struct;\ + endfunction + +// **************************************************************************** +// When changing the contents of this struct, be sure to update the to_responder_struct +// and from_responder_struct methods of the spi_m_transaction class. +// Also update the comments in the driver BFM. +// + `define spi_m_RESPONDER_STRUCT typedef struct packed { \ + bit ssel ; \ + bit [7:0] mosi ; \ + bit [7:0] miso ; \ + } spi_m_responder_s; + + `define spi_m_TO_RESPONDER_STRUCT_FUNCTION \ + virtual function spi_m_responder_s to_responder_struct();\ + spi_m_responder_struct = \ + {\ + this.ssel , \ + this.mosi , \ + this.miso \ + };\ + return ( spi_m_responder_struct);\ + endfunction + + `define spi_m_FROM_RESPONDER_STRUCT_FUNCTION \ + virtual function void from_responder_struct(spi_m_responder_s spi_m_responder_struct);\ + {\ + this.ssel , \ + this.mosi , \ + this.miso \ + } = spi_m_responder_struct;\ + endfunction +// pragma uvmf custom additional begin +// pragma uvmf custom additional end diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/spi_m_pkg/src/spi_m_monitor.svh b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/spi_m_pkg/src/spi_m_monitor.svh new file mode 100644 index 00000000..594666de --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/spi_m_pkg/src/spi_m_monitor.svh @@ -0,0 +1,87 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This class receives spi_m transactions observed by the +// spi_m monitor BFM and broadcasts them through the analysis port +// on the agent. It accesses the monitor BFM through the monitor +// task. This UVM component captures transactions +// for viewing in the waveform viewer if the +// enable_transaction_viewing flag is set in the configuration. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class spi_m_monitor extends uvmf_monitor_base #( + .CONFIG_T(spi_m_configuration ), + .BFM_BIND_T(virtual spi_m_monitor_bfm ), + .TRANS_T(spi_m_transaction )); + + `uvm_component_utils( spi_m_monitor ) + +// Structure used to pass data from monitor BFM to monitor class in agent. +// Use to_monitor_struct function to pack transaction variables into structure. +// Use from_monitor_struct function to unpack transaction variables from structure. +`spi_m_MONITOR_STRUCT + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + +// **************************************************************************** +// This function is the standard SystemVerilog constructor. +// + function new( string name = "", uvm_component parent = null ); + super.new( name, parent ); + endfunction + +// **************************************************************************** +// This function sends configuration object variables to the monitor BFM +// using the configuration struct. +// + virtual function void configure(input CONFIG_T cfg); + bfm.configure( cfg.to_struct() ); + + endfunction + +// **************************************************************************** +// This function places a handle to this class in the proxy variable in the +// monitor BFM. This allows the monitor BFM to call the notify_transaction +// function within this class. +// + virtual function void set_bfm_proxy_handle(); + bfm.proxy = this; endfunction + +// *************************************************************************** + virtual task run_phase(uvm_phase phase); + // Start monitor BFM thread and don't call super.run() in order to + // override the default monitor proxy 'pull' behavior with the more + // emulation-friendly BFM 'push' approach using the notify_transaction + // function below + bfm.start_monitoring(); + endtask + +// ************************************************************************** + +// This function is called by the monitor BFM. It receives data observed by the +// monitor BFM. Data is passed using the spi_m_monitor_struct. + virtual function void notify_transaction(input spi_m_monitor_s spi_m_monitor_struct); + + + trans = new("trans"); + trans.from_monitor_struct(spi_m_monitor_struct); + trans.start_time = time_stamp; + trans.end_time = $time; + time_stamp = trans.end_time; + + analyze(trans); + endfunction + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/spi_m_pkg/src/spi_m_monitor_bfm.sv b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/spi_m_pkg/src/spi_m_monitor_bfm.sv new file mode 100644 index 00000000..c727952e --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/spi_m_pkg/src/spi_m_monitor_bfm.sv @@ -0,0 +1,185 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This interface performs the spi_m signal monitoring. +// It is accessed by the uvm spi_m monitor through a virtual +// interface handle in the spi_m configuration. It monitors the +// signals passed in through the port connection named bus of +// type spi_m_if. +// +// Input signals from the spi_m_if are assigned to an internal input +// signal with a _i suffix. The _i signal should be used for sampling. +// +// The input signal connections are as follows: +// bus.signal -> signal_i +// +// Interface functions and tasks used by UVM components: +// monitor(inout TRANS_T txn); +// This task receives the transaction, txn, from the +// UVM monitor and then populates variables in txn +// from values observed on bus activity. This task +// blocks until an operation on the spi_m bus is complete. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +import uvmf_base_pkg_hdl::*; +import spi_m_pkg_hdl::*; +`include "src/spi_m_macros.svh" + + +interface spi_m_monitor_bfm + ( spi_m_if bus ); + // The pragma below and additional ones in-lined further down are for running this BFM on Veloce + // pragma attribute spi_m_monitor_bfm partition_interface_xif + +`ifndef XRTL +// This code is to aid in debugging parameter mismatches between the BFM and its corresponding agent. +// Enable this debug by setting UVM_VERBOSITY to UVM_DEBUG +// Setting UVM_VERBOSITY to UVM_DEBUG causes all BFM's and all agents to display their parameter settings. +// All of the messages from this feature have a UVM messaging id value of "CFG" +// The transcript or run.log can be parsed to ensure BFM parameter settings match its corresponding agents parameter settings. +import uvm_pkg::*; +`include "uvm_macros.svh" +initial begin : bfm_vs_agent_parameter_debug + `uvm_info("CFG", + $psprintf("The BFM at '%m' has the following parameters: ", ), + UVM_DEBUG) +end +`endif + + + // Structure used to pass transaction data from monitor BFM to monitor class in agent. +`spi_m_MONITOR_STRUCT + spi_m_monitor_s spi_m_monitor_struct; + + // Structure used to pass configuration data from monitor class to monitor BFM. + `spi_m_CONFIGURATION_STRUCT + + + // Config value to determine if this is an initiator or a responder + uvmf_initiator_responder_t initiator_responder; + // Custom configuration variables. + // These are set using the configure function which is called during the UVM connect_phase + + logic sck_i; + logic rst_i; + tri sclk_i; + tri ss_i; + tri [7:0] mosi_i; + tri [7:0] miso_i; + assign sck_i = bus.sck; + assign rst_i = bus.rst; + assign sclk_i = bus.sclk; + assign ss_i = bus.ss; + assign mosi_i = bus.mosi; + assign miso_i = bus.miso; + + // Proxy handle to UVM monitor + spi_m_pkg::spi_m_monitor proxy; + // pragma tbx oneway proxy.notify_transaction + + // pragma uvmf custom interface_item_additional begin + // pragma uvmf custom interface_item_additional end + + //****************************************************************** + task wait_for_reset();// pragma tbx xtf + @(posedge sck_i) ; + do_wait_for_reset(); + endtask + + // **************************************************************************** + task do_wait_for_reset(); + // pragma uvmf custom reset_condition begin + wait ( rst_i === 0 ) ; + @(posedge sck_i) ; + // pragma uvmf custom reset_condition end + endtask + + //****************************************************************** + + task wait_for_num_clocks(input int unsigned count); // pragma tbx xtf + @(posedge sck_i); + + repeat (count-1) @(posedge sck_i); + endtask + + //****************************************************************** + event go; + function void start_monitoring();// pragma tbx xtf + -> go; + endfunction + + // **************************************************************************** + initial begin + @go; + forever begin + @(posedge sck_i); + do_monitor( spi_m_monitor_struct ); + + + proxy.notify_transaction( spi_m_monitor_struct ); + + end + end + + //****************************************************************** + // The configure() function is used to pass agent configuration + // variables to the monitor BFM. It is called by the monitor within + // the agent at the beginning of the simulation. It may be called + // during the simulation if agent configuration variables are updated + // and the monitor BFM needs to be aware of the new configuration + // variables. + // + function void configure(spi_m_configuration_s spi_m_configuration_arg); // pragma tbx xtf + initiator_responder = spi_m_configuration_arg.initiator_responder; + // pragma uvmf custom configure begin + // pragma uvmf custom configure end + endfunction + + + // **************************************************************************** + + task do_monitor(output spi_m_monitor_s spi_m_monitor_struct); + // + // Available struct members: + // // spi_m_monitor_struct.ssel + // // spi_m_monitor_struct.mosi + // // spi_m_monitor_struct.miso + // // + // Reference code; + // How to wait for signal value + // while (control_signal === 1'b1) @(posedge sck_i); + // + // How to assign a struct member, named xyz, from a signal. + // All available input signals listed. + // spi_m_monitor_struct.xyz = sclk_i; // + // spi_m_monitor_struct.xyz = ss_i; // + // spi_m_monitor_struct.xyz = mosi_i; // [7:0] + // spi_m_monitor_struct.xyz = miso_i; // [7:0] + // pragma uvmf custom do_monitor begin + // UVMF_CHANGE_ME : Implement protocol monitoring. The commented reference code + // below are examples of how to capture signal values and assign them to + // structure members. All available input signals are listed. The 'while' + // code example shows how to wait for a synchronous flow control signal. This + // task should return when a complete transfer has been observed. Once this task is + // exited with captured values, it is then called again to wait for and observe + // the next transfer. One clock cycle is consumed between calls to do_monitor. + @(posedge sck_i); + @(posedge sck_i); + @(posedge sck_i); + @(posedge sck_i); + // pragma uvmf custom do_monitor end + endtask + + +endinterface + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/spi_m_pkg/src/spi_m_random_sequence.svh b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/spi_m_pkg/src/spi_m_random_sequence.svh new file mode 100644 index 00000000..53962025 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/spi_m_pkg/src/spi_m_random_sequence.svh @@ -0,0 +1,53 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: +// This sequences randomizes the spi_m transaction and sends it +// to the UVM driver. +// +// This sequence constructs and randomizes a spi_m_transaction. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class spi_m_random_sequence + extends spi_m_sequence_base ; + + `uvm_object_utils( spi_m_random_sequence ) + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + //***************************************************************** + function new(string name = ""); + super.new(name); + endfunction: new + + // **************************************************************************** + // TASK : body() + // This task is automatically executed when this sequence is started using the + // start(sequencerHandle) task. + // + task body(); + + // Construct the transaction + req=spi_m_transaction::type_id::create("req"); + start_item(req); + // Randomize the transaction + if(!req.randomize()) `uvm_fatal("SEQ", "spi_m_random_sequence::body()-spi_m_transaction randomization failed") + // Send the transaction to the spi_m_driver_bfm via the sequencer and spi_m_driver. + finish_item(req); + `uvm_info("SEQ", {"Response:",req.convert2string()},UVM_MEDIUM) + + endtask + +endclass: spi_m_random_sequence + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/spi_m_pkg/src/spi_m_responder_sequence.svh b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/spi_m_pkg/src/spi_m_responder_sequence.svh new file mode 100644 index 00000000..ee97f025 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/spi_m_pkg/src/spi_m_responder_sequence.svh @@ -0,0 +1,49 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This class can be used to provide stimulus when an interface +// has been configured to run in a responder mode. It +// will never finish by default, always going back to the driver +// and driver BFM for the next transaction with which to respond. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class spi_m_responder_sequence + extends spi_m_sequence_base ; + + `uvm_object_utils( spi_m_responder_sequence ) + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + function new(string name = "spi_m_responder_sequence"); + super.new(name); + endfunction + + task body(); + req=spi_m_transaction::type_id::create("req"); + forever begin + start_item(req); + finish_item(req); + // pragma uvmf custom body begin + // UVMF_CHANGE_ME : Do something here with the resulting req item. The + // finish_item() call above will block until the req transaction is ready + // to be handled by the responder sequence. + // If this was an item that required a response, the expectation is + // that the response should be populated within this transaction now. + `uvm_info("SEQ",$sformatf("Processed txn: %s",req.convert2string()),UVM_HIGH) + // pragma uvmf custom body end + end + endtask + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/spi_m_pkg/src/spi_m_sequence_base.svh b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/spi_m_pkg/src/spi_m_sequence_base.svh new file mode 100644 index 00000000..d603b978 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/spi_m_pkg/src/spi_m_sequence_base.svh @@ -0,0 +1,96 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: +// This file contains the class used as the base class for all sequences +// for this interface. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class spi_m_sequence_base extends uvmf_sequence_base #( + .REQ(spi_m_transaction ), + .RSP(spi_m_transaction )); + + `uvm_object_utils( spi_m_sequence_base ) + + // variables + typedef spi_m_transaction spi_m_transaction_req_t; + spi_m_transaction_req_t req; + typedef spi_m_transaction spi_m_transaction_rsp_t; + spi_m_transaction_rsp_t rsp; + + // Event for identifying when a response was received from the sequencer + event new_rsp; + + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + // **************************************************************************** + // TASK : get_responses() + // This task recursively gets sequence item responses from the sequencer. + // + virtual task get_responses(); + fork + begin + // Block until new rsp available + get_response(rsp); + // New rsp received. Indicate to sequence using event. + ->new_rsp; + // Display the received response transaction + `uvm_info("SEQ", {"New response transaction:",rsp.convert2string()}, UVM_MEDIUM) + end + join_none + endtask + + // **************************************************************************** + // TASK : pre_body() + // This task is called automatically when start is called with call_pre_post set to 1 (default). + // By calling get_responses() within pre_body() any derived sequences are automatically + // processing response transactions. Only un-comment this call to get_responses() if you + // have configured the interface driver to utilize the response transaction path by setting + // the configuration variable "return_transaction_response" to 1. Otherwise it is possible + // to impact runtime performance and memory utilization. + // + virtual task pre_body(); + // pragma uvmf custom pre_body begin +// get_responses(); + // pragma uvmf custom pre_body end + endtask + + // **************************************************************************** + // TASK : body() + // This task is called automatically when start is called. This sequence sends + // a req sequence item to the sequencer identified as an argument in the call + // to start. + // + virtual task body(); + // pragma uvmf custom body begin + start_item(req); + finish_item(req); + // pragma uvmf custom body end + endtask + + // **************************************************************************** + // FUNCTION : new() + // This function is the standard SystemVerilog constructor. + // + function new( string name =""); + super.new( name ); + // pragma uvmf custom new begin + req = spi_m_transaction_req_t::type_id::create("req"); + rsp = spi_m_transaction_rsp_t::type_id::create("rsp"); + // pragma uvmf custom new end + endfunction + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/spi_m_pkg/src/spi_m_transaction.svh b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/spi_m_pkg/src/spi_m_transaction.svh new file mode 100644 index 00000000..99a7fd1c --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/spi_m_pkg/src/spi_m_transaction.svh @@ -0,0 +1,190 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This class defines the variables required for an spi_m +// transaction. Class variables to be displayed in waveform transaction +// viewing are added to the transaction viewing stream in the add_to_wave +// function. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class spi_m_transaction extends uvmf_transaction_base; + + `uvm_object_utils( spi_m_transaction ) + + rand bit ssel ; + rand bit [7:0] mosi ; + bit [7:0] miso ; + + //Constraints for the transaction variables: + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + //******************************************************************* + //******************************************************************* + // Macros that define structs and associated functions are + // located in spi_m_macros.svh + + //******************************************************************* + // Monitor macro used by spi_m_monitor and spi_m_monitor_bfm + // This struct is defined in spi_m_macros.svh + `spi_m_MONITOR_STRUCT + spi_m_monitor_s spi_m_monitor_struct; + //******************************************************************* + // FUNCTION: to_monitor_struct() + // This function packs transaction variables into a spi_m_monitor_s + // structure. The function returns the handle to the spi_m_monitor_struct. + // This function is defined in spi_m_macros.svh + `spi_m_TO_MONITOR_STRUCT_FUNCTION + //******************************************************************* + // FUNCTION: from_monitor_struct() + // This function unpacks the struct provided as an argument into transaction + // variables of this class. + // This function is defined in spi_m_macros.svh + `spi_m_FROM_MONITOR_STRUCT_FUNCTION + + //******************************************************************* + // Initiator macro used by spi_m_driver and spi_m_driver_bfm + // to communicate initiator driven data to spi_m_driver_bfm. + // This struct is defined in spi_m_macros.svh + `spi_m_INITIATOR_STRUCT + spi_m_initiator_s spi_m_initiator_struct; + //******************************************************************* + // FUNCTION: to_initiator_struct() + // This function packs transaction variables into a spi_m_initiator_s + // structure. The function returns the handle to the spi_m_initiator_struct. + // This function is defined in spi_m_macros.svh + `spi_m_TO_INITIATOR_STRUCT_FUNCTION + //******************************************************************* + // FUNCTION: from_initiator_struct() + // This function unpacks the struct provided as an argument into transaction + // variables of this class. + // This function is defined in spi_m_macros.svh + `spi_m_FROM_INITIATOR_STRUCT_FUNCTION + + //******************************************************************* + // Responder macro used by spi_m_driver and spi_m_driver_bfm + // to communicate Responder driven data to spi_m_driver_bfm. + // This struct is defined in spi_m_macros.svh + `spi_m_RESPONDER_STRUCT + spi_m_responder_s spi_m_responder_struct; + //******************************************************************* + // FUNCTION: to_responder_struct() + // This function packs transaction variables into a spi_m_responder_s + // structure. The function returns the handle to the spi_m_responder_struct. + // This function is defined in spi_m_macros.svh + `spi_m_TO_RESPONDER_STRUCT_FUNCTION + //******************************************************************* + // FUNCTION: from_responder_struct() + // This function unpacks the struct provided as an argument into transaction + // variables of this class. + // This function is defined in spi_m_macros.svh + `spi_m_FROM_RESPONDER_STRUCT_FUNCTION + // **************************************************************************** + // FUNCTION : new() + // This function is the standard SystemVerilog constructor. + // + function new( string name = "" ); + super.new( name ); + endfunction + + // **************************************************************************** + // FUNCTION: convert2string() + // This function converts all variables in this class to a single string for + // logfile reporting. + // + virtual function string convert2string(); + // pragma uvmf custom convert2string begin + // UVMF_CHANGE_ME : Customize format if desired. + return $sformatf("ssel:0x%x mosi:0x%x miso:0x%x ",ssel,mosi,miso); + // pragma uvmf custom convert2string end + endfunction + + //******************************************************************* + // FUNCTION: do_print() + // This function is automatically called when the .print() function + // is called on this class. + // + virtual function void do_print(uvm_printer printer); + // pragma uvmf custom do_print begin + // UVMF_CHANGE_ME : Current contents of do_print allows for the use of UVM 1.1d, 1.2 or P1800.2. + // Update based on your own printing preference according to your preferred UVM version + $display(convert2string()); + // pragma uvmf custom do_print end + endfunction + + //******************************************************************* + // FUNCTION: do_compare() + // This function is automatically called when the .compare() function + // is called on this class. + // + virtual function bit do_compare (uvm_object rhs, uvm_comparer comparer); + spi_m_transaction RHS; + if (!$cast(RHS,rhs)) return 0; + // pragma uvmf custom do_compare begin + // UVMF_CHANGE_ME : Eliminate comparison of variables not to be used for compare + return (super.do_compare(rhs,comparer) + &&(this.ssel == RHS.ssel) + &&(this.mosi == RHS.mosi) + &&(this.miso == RHS.miso) + ); + // pragma uvmf custom do_compare end + endfunction + + //******************************************************************* + // FUNCTION: do_copy() + // This function is automatically called when the .copy() function + // is called on this class. + // + virtual function void do_copy (uvm_object rhs); + spi_m_transaction RHS; + assert($cast(RHS,rhs)); + // pragma uvmf custom do_copy begin + super.do_copy(rhs); + this.ssel = RHS.ssel; + this.mosi = RHS.mosi; + this.miso = RHS.miso; + // pragma uvmf custom do_copy end + endfunction + + // **************************************************************************** + // FUNCTION: add_to_wave() + // This function is used to display variables in this class in the waveform + // viewer. The start_time and end_time variables must be set before this + // function is called. If the start_time and end_time variables are not set + // the transaction will be hidden at 0ns on the waveform display. + // + virtual function void add_to_wave(int transaction_viewing_stream_h); + `ifdef QUESTA + if (transaction_view_h == 0) begin + transaction_view_h = $begin_transaction(transaction_viewing_stream_h,"spi_m_transaction",start_time); + end + super.add_to_wave(transaction_view_h); + // pragma uvmf custom add_to_wave begin + // UVMF_CHANGE_ME : Color can be applied to transaction entries based on content, example below + // case() + // 1 : $add_color(transaction_view_h,"red"); + // default : $add_color(transaction_view_h,"grey"); + // endcase + // UVMF_CHANGE_ME : Eliminate transaction variables not wanted in transaction viewing in the waveform viewer + $add_attribute(transaction_view_h,ssel,"ssel"); + $add_attribute(transaction_view_h,mosi,"mosi"); + $add_attribute(transaction_view_h,miso,"miso"); + // pragma uvmf custom add_to_wave end + $end_transaction(transaction_view_h,end_time); + $free_transaction(transaction_view_h); + `endif // QUESTA + endfunction + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/spi_m_pkg/src/spi_m_transaction_coverage.svh b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/spi_m_pkg/src/spi_m_transaction_coverage.svh new file mode 100644 index 00000000..95cda794 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/spi_m_pkg/src/spi_m_transaction_coverage.svh @@ -0,0 +1,72 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This class records spi_m transaction information using +// a covergroup named spi_m_transaction_cg. An instance of this +// coverage component is instantiated in the uvmf_parameterized_agent +// if the has_coverage flag is set. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class spi_m_transaction_coverage extends uvm_subscriber #(.T(spi_m_transaction )); + + `uvm_component_utils( spi_m_transaction_coverage ) + + T coverage_trans; + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + // **************************************************************************** + covergroup spi_m_transaction_cg; + // pragma uvmf custom covergroup begin + // UVMF_CHANGE_ME : Add coverage bins, crosses, exclusions, etc. according to coverage needs. + option.auto_bin_max=1024; + option.per_instance=1; + ssel: coverpoint coverage_trans.ssel; + mosi: coverpoint coverage_trans.mosi; + miso: coverpoint coverage_trans.miso; + // pragma uvmf custom covergroup end + endgroup + + // **************************************************************************** + // FUNCTION : new() + // This function is the standard SystemVerilog constructor. + // + function new(string name="", uvm_component parent=null); + super.new(name,parent); + spi_m_transaction_cg=new; + `uvm_warning("COVERAGE_MODEL_REVIEW", "A covergroup has been constructed which may need review because of either generation or re-generation with merging. Please note that transaction variables added as a result of re-generation and merging are not automatically added to the covergroup. Remove this warning after the covergroup has been reviewed.") + endfunction + + // **************************************************************************** + // FUNCTION : build_phase() + // This function is the standard UVM build_phase. + // + function void build_phase(uvm_phase phase); + spi_m_transaction_cg.set_inst_name($sformatf("spi_m_transaction_cg_%s",get_full_name())); + endfunction + + // **************************************************************************** + // FUNCTION: write (T t) + // This function is automatically executed when a transaction arrives on the + // analysis_export. It copies values from the variables in the transaction + // to local variables used to collect functional coverage. + // + virtual function void write (T t); + `uvm_info("COV","Received transaction",UVM_HIGH); + coverage_trans = t; + spi_m_transaction_cg.sample(); + endfunction + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/spi_m_pkg/src/spi_m_typedefs.svh b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/spi_m_pkg/src/spi_m_typedefs.svh new file mode 100644 index 00000000..43d85640 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/spi_m_pkg/src/spi_m_typedefs.svh @@ -0,0 +1,20 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: +// This file contains defines and typedefs to be compiled for use in +// the simulation running on the host server when using Veloce. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// + + +// pragma uvmf custom additional begin +// pragma uvmf custom additional end + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/spi_m_pkg/src/spi_m_typedefs_hdl.svh b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/spi_m_pkg/src/spi_m_typedefs_hdl.svh new file mode 100644 index 00000000..74738c8c --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/spi_m_pkg/src/spi_m_typedefs_hdl.svh @@ -0,0 +1,21 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: +// This file contains defines and typedefs to be compiled for use in +// the simulation running on the emulator when using Veloce. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// + + + +// pragma uvmf custom additional begin +// pragma uvmf custom additional end + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/spi_m_pkg/yaml/spi_m_interface.yaml b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/spi_m_pkg/yaml/spi_m_interface.yaml new file mode 100644 index 00000000..1eca4f64 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/spi_m_pkg/yaml/spi_m_interface.yaml @@ -0,0 +1,53 @@ +uvmf: + interfaces: + spi_m: + clock: sck + config_constraints: [] + config_vars: [] + existing_library_component: 'True' + gen_inbound_streaming_driver: 'False' + hdl_pkg_parameters: [] + hdl_typedefs: [] + hvl_pkg_parameters: [] + hvl_typedefs: [] + parameters: [] + ports: + - dir: output + name: sclk + reset_value: '''b0' + width: '1' + - dir: output + name: ss + reset_value: '''b0' + width: '1' + - dir: output + name: mosi + reset_value: '''b0' + width: '8' + - dir: input + name: miso + reset_value: '''b0' + width: '8' + reset: rst + reset_assertion_level: 'True' + transaction_constraints: [] + transaction_vars: + - comment: '' + iscompare: 'True' + isrand: 'True' + name: ssel + type: bit + unpacked_dimension: '' + - comment: '' + iscompare: 'True' + isrand: 'True' + name: mosi + type: bit [7:0] + unpacked_dimension: '' + - comment: '' + iscompare: 'True' + isrand: 'False' + name: miso + type: bit [7:0] + unpacked_dimension: '' + use_dpi_link: 'False' diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/spi_s_pkg/.project b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/spi_s_pkg/.project new file mode 100644 index 00000000..548e937e --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/spi_s_pkg/.project @@ -0,0 +1,30 @@ + + + spi_s_pkg + + + + + + org.python.pydev.PyDevBuilder + + + + + net.sf.sveditor.core.SVProjectBuilder + + + + + + net.sf.sveditor.core.SVNature + org.python.pydev.pythonNature + + + + UVMF_VIP_LIBRARY_HOME + $%7BPARENT-2-PROJECT_LOC%7D + + + + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/spi_s_pkg/.svproject b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/spi_s_pkg/.svproject new file mode 100644 index 00000000..dbc66e83 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/spi_s_pkg/.svproject @@ -0,0 +1,16 @@ + + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/spi_s_pkg/Makefile b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/spi_s_pkg/Makefile new file mode 100644 index 00000000..d4c678b7 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/spi_s_pkg/Makefile @@ -0,0 +1,66 @@ +# spi_s interface packages source +# pragma uvmf custom additional begin +# pragma uvmf custom additional end + +spi_s_PKG = \ + +incdir+$(UVMF_VIP_LIBRARY_HOME)/interface_packages/spi_s_pkg \ + -F $(UVMF_VIP_LIBRARY_HOME)/interface_packages/spi_s_pkg/spi_s_filelist_hvl.f + +spi_s_PKG_HDL = \ + +incdir+$(UVMF_VIP_LIBRARY_HOME)/interface_packages/spi_s_pkg \ + -F $(UVMF_VIP_LIBRARY_HOME)/interface_packages/spi_s_pkg/spi_s_filelist_hdl.f + +spi_s_PKG_XRTL = \ + +incdir+$(UVMF_VIP_LIBRARY_HOME)/interface_packages/spi_s_pkg \ + -F $(UVMF_VIP_LIBRARY_HOME)/interface_packages/spi_s_pkg/spi_s_filelist_xrtl.f + +COMP_spi_s_PKG_TGT_0 = q_comp_spi_s_pkg +COMP_spi_s_PKG_TGT_1 = v_comp_spi_s_pkg +COMP_spi_s_PKG_TGT = $(COMP_spi_s_PKG_TGT_$(USE_VELOCE)) + +comp_spi_s_pkg: $(COMP_spi_s_PKG_TGT) + +q_comp_spi_s_pkg: + $(HDL_COMP_CMD) $(spi_s_PKG_HDL) + $(HVL_COMP_CMD) $(spi_s_PKG) + $(HDL_COMP_CMD) $(spi_s_PKG_XRTL) + +v_comp_spi_s_pkg: + $(HVL_COMP_CMD) $(spi_s_PKG_HDL) + $(HVL_COMP_CMD) $(spi_s_PKG) + $(VELANALYZE_CMD) $(spi_s_PKG_HDL) + $(VELANALYZE_HVL_CMD) $(spi_s_PKG) + $(HDL_COMP_CMD) $(spi_s_PKG_XRTL) + +ifeq ($(MTI_VCO_MODE),64) + GCC_COMP_ARCH = -m64 +else + GCC_COMP_ARCH = -m32 +endif + +export spi_s_IF_DPI_SRC ?= $(UVMF_VIP_LIBRARY_HOME)/interface_packages/spi_s_pkg/dpi + +C_FILE_COMPILE_LIST_spi_s_pkg = \ + +O_FILE_COMPILE_LIST_spi_s_pkg = $(notdir $(C_FILE_COMPILE_LIST_spi_s_pkg:.c=.o)) + +GCC_COMP_ARGS_spi_s_pkg += -I$(spi_s_IF_DPI_SRC) \ + -fPIC + +GCC_COMP_ARGS_spi_s_pkg += $(spi_s_IF_GCC_COMP_ARGUMENTS) + +GCC_LINK_ARGS_spi_s_pkg += \ + \ + -o .so + +comp_spi_s_pkg_c_files: + @echo "--------------------------------" + @echo "Compiling Interface C source" + @echo "--------------------------------" + gcc $(GCC_COMP_ARCH) $(GCC_COMP_ARGS_spi_s_pkg) $(C_FILE_COMPILE_LIST_spi_s_pkg) + @echo "--------------------------------" + @echo "Linking Interface C objects into a shared object" + @echo "--------------------------------" + gcc $(GCC_COMP_ARCH) $(GCC_LINK_ARGS_spi_s_pkg) $(O_FILE_COMPILE_LIST_spi_s_pkg) + @echo "--------------------------------" + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/spi_s_pkg/compile.do b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/spi_s_pkg/compile.do new file mode 100644 index 00000000..303c17b2 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/spi_s_pkg/compile.do @@ -0,0 +1,14 @@ +# Tcl do file for compile of spi_s interface + +# pragma uvmf custom additional begin +# pragma uvmf custom additional end + + +vlog -sv -timescale 1ps/1ps -suppress 2223,2286 +incdir+$env(UVMF_VIP_LIBRARY_HOME)/interface_packages/spi_s_pkg \ + -F $env(UVMF_VIP_LIBRARY_HOME)/interface_packages/spi_s_pkg/spi_s_filelist_hdl.f + +vlog -sv -timescale 1ps/1ps -suppress 2223,2286 +incdir+$env(UVMF_VIP_LIBRARY_HOME)/interface_packages/spi_s_pkg \ + -F $env(UVMF_VIP_LIBRARY_HOME)/interface_packages/spi_s_pkg/spi_s_filelist_hvl.f + +vlog -sv -timescale 1ps/1ps -suppress 2223,2286 +incdir+$env(UVMF_VIP_LIBRARY_HOME)/interface_packages/spi_s_pkg \ + -F $env(UVMF_VIP_LIBRARY_HOME)/interface_packages/spi_s_pkg/spi_s_filelist_xrtl.f \ No newline at end of file diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/spi_s_pkg/spi_s.compile b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/spi_s_pkg/spi_s.compile new file mode 100644 index 00000000..8b8aa6e2 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/spi_s_pkg/spi_s.compile @@ -0,0 +1,3 @@ +needs: + - spi_s_hvl.compile + - spi_s_hdl.compile diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/spi_s_pkg/spi_s_bfm.vinfo b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/spi_s_pkg/spi_s_bfm.vinfo new file mode 100644 index 00000000..0f12baaf --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/spi_s_pkg/spi_s_bfm.vinfo @@ -0,0 +1,6 @@ +@use $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg_hdl.vinfo +@use spi_s_pkg_hdl.vinfo ++incdir+@vinfodir +src/spi_s_if.sv +src/spi_s_driver_bfm.sv +src/spi_s_monitor_bfm.sv diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/spi_s_pkg/spi_s_common.compile b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/spi_s_pkg/spi_s_common.compile new file mode 100644 index 00000000..08bd125f --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/spi_s_pkg/spi_s_common.compile @@ -0,0 +1,7 @@ +needs: + - $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg_hdl.compile +incdir: + - . + - ${uvm_path}/src +src: + - spi_s_pkg_hdl.sv diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/spi_s_pkg/spi_s_filelist_hdl.f b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/spi_s_pkg/spi_s_filelist_hdl.f new file mode 100644 index 00000000..d7724020 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/spi_s_pkg/spi_s_filelist_hdl.f @@ -0,0 +1 @@ +$UVMF_VIP_LIBRARY_HOME/interface_packages/spi_s_pkg/spi_s_pkg_hdl.sv diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/spi_s_pkg/spi_s_filelist_hvl.f b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/spi_s_pkg/spi_s_filelist_hvl.f new file mode 100644 index 00000000..cbc4a9ef --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/spi_s_pkg/spi_s_filelist_hvl.f @@ -0,0 +1 @@ +$UVMF_VIP_LIBRARY_HOME/interface_packages/spi_s_pkg/spi_s_pkg.sv \ No newline at end of file diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/spi_s_pkg/spi_s_filelist_xrtl.f b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/spi_s_pkg/spi_s_filelist_xrtl.f new file mode 100644 index 00000000..175919ef --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/spi_s_pkg/spi_s_filelist_xrtl.f @@ -0,0 +1,3 @@ +$UVMF_VIP_LIBRARY_HOME/interface_packages/spi_s_pkg/src/spi_s_if.sv +$UVMF_VIP_LIBRARY_HOME/interface_packages/spi_s_pkg/src/spi_s_monitor_bfm.sv +$UVMF_VIP_LIBRARY_HOME/interface_packages/spi_s_pkg/src/spi_s_driver_bfm.sv diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/spi_s_pkg/spi_s_hdl.compile b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/spi_s_pkg/spi_s_hdl.compile new file mode 100644 index 00000000..e63a6a97 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/spi_s_pkg/spi_s_hdl.compile @@ -0,0 +1,9 @@ +needs: + - $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg_hdl.compile + - ./spi_s_common.compile +incdir: + - . +src: + - src/spi_s_if.sv + - src/spi_s_monitor_bfm.sv + - src/spi_s_driver_bfm.sv diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/spi_s_pkg/spi_s_hvl.compile b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/spi_s_pkg/spi_s_hvl.compile new file mode 100644 index 00000000..569dc399 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/spi_s_pkg/spi_s_hvl.compile @@ -0,0 +1,7 @@ +needs: + - $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg.compile + - ./spi_s_common.compile +incdir: + - . +src: + - spi_s_pkg.sv diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/spi_s_pkg/spi_s_pkg.sv b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/spi_s_pkg/spi_s_pkg.sv new file mode 100644 index 00000000..90ad9fe1 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/spi_s_pkg/spi_s_pkg.sv @@ -0,0 +1,77 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// PACKAGE: This file defines all of the files contained in the +// interface package that will run on the host simulator. +// +// CONTAINS: +// - +// - +// - + +// - +// - +// - + +// - +// - +// - + +// - +// - +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +package spi_s_pkg; + + import uvm_pkg::*; + import uvmf_base_pkg_hdl::*; + import uvmf_base_pkg::*; + import spi_s_pkg_hdl::*; + + `include "uvm_macros.svh" + + // pragma uvmf custom package_imports_additional begin + // pragma uvmf custom package_imports_additional end + `include "src/spi_s_macros.svh" + + export spi_s_pkg_hdl::*; + + + + // Parameters defined as HVL parameters + + `include "src/spi_s_typedefs.svh" + `include "src/spi_s_transaction.svh" + + `include "src/spi_s_configuration.svh" + `include "src/spi_s_driver.svh" + `include "src/spi_s_monitor.svh" + + `include "src/spi_s_transaction_coverage.svh" + `include "src/spi_s_sequence_base.svh" + `include "src/spi_s_random_sequence.svh" + + `include "src/spi_s_responder_sequence.svh" + `include "src/spi_s2reg_adapter.svh" + + `include "src/spi_s_agent.svh" + + // pragma uvmf custom package_item_additional begin + // UVMF_CHANGE_ME : When adding new interface sequences to the src directory + // be sure to add the sequence file here so that it will be + // compiled as part of the interface package. Be sure to place + // the new sequence after any base sequences of the new sequence. + // pragma uvmf custom package_item_additional end + +endpackage + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/spi_s_pkg/spi_s_pkg.vinfo b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/spi_s_pkg/spi_s_pkg.vinfo new file mode 100644 index 00000000..b849145a --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/spi_s_pkg/spi_s_pkg.vinfo @@ -0,0 +1,4 @@ +@use $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg.vinfo +@use spi_s_pkg_hdl.vinfo ++incdir+@vinfodir +spi_s_pkg.sv diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/spi_s_pkg/spi_s_pkg_hdl.sv b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/spi_s_pkg/spi_s_pkg_hdl.sv new file mode 100644 index 00000000..d2773bc0 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/spi_s_pkg/spi_s_pkg_hdl.sv @@ -0,0 +1,38 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// PACKAGE: This file defines all of the files contained in the +// interface package that needs to be compiled and synthesized +// for running on Veloce. +// +// CONTAINS: +// - +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +package spi_s_pkg_hdl; + + import uvmf_base_pkg_hdl::*; + + // pragma uvmf custom package_imports_additional begin + // pragma uvmf custom package_imports_additional end + + // Parameters defined as HDL parameters + + `include "src/spi_s_typedefs_hdl.svh" + `include "src/spi_s_macros.svh" + + // pragma uvmf custom package_item_additional begin + // pragma uvmf custom package_item_additional end + +endpackage + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/spi_s_pkg/spi_s_pkg_hdl.vinfo b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/spi_s_pkg/spi_s_pkg_hdl.vinfo new file mode 100644 index 00000000..969589c7 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/spi_s_pkg/spi_s_pkg_hdl.vinfo @@ -0,0 +1,2 @@ +@use $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg_hdl.vinfo +spi_s_pkg_hdl.sv diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/spi_s_pkg/spi_s_pkg_sve.F b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/spi_s_pkg/spi_s_pkg_sve.F new file mode 100644 index 00000000..13508e71 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/spi_s_pkg/spi_s_pkg_sve.F @@ -0,0 +1,10 @@ +// UVM ++incdir+${UVM_HOME}/src +${UVM_HOME}/src/uvm_pkg.sv + +// Common UVMF files +-f ${UVMF_HOME}/common/common_sve.f + ++incdir+. +-f ${UVMF_VIP_LIBRARY_HOME}/interface_packages/spi_s_pkg/spi_s_filelist_hdl.f +-f ${UVMF_VIP_LIBRARY_HOME}/interface_packages/spi_s_pkg/spi_s_filelist_hvl.f diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/spi_s_pkg/src/spi_s2reg_adapter.svh b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/spi_s_pkg/src/spi_s2reg_adapter.svh new file mode 100644 index 00000000..f6ce4828 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/spi_s_pkg/src/spi_s2reg_adapter.svh @@ -0,0 +1,98 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: +// This file contains the UVM register adapter for the spi_s interface. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class spi_s2reg_adapter extends uvm_reg_adapter; + + `uvm_object_utils( spi_s2reg_adapter ) + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + //-------------------------------------------------------------------- + // new + //-------------------------------------------------------------------- + function new (string name = "spi_s2reg_adapter" ); + super.new(name); + // pragma uvmf custom new begin + // UVMF_CHANGE_ME : Configure the adapter regarding byte enables and provides response. + + // Does the protocol the Agent is modeling support byte enables? + // 0 = NO + // 1 = YES + supports_byte_enable = 0; + + // Does the Agent's Driver provide separate response sequence items? + // i.e. Does the driver call seq_item_port.put() + // and do the sequences call get_response()? + // 0 = NO + // 1 = YES + provides_responses = 0; + // pragma uvmf custom new end + + endfunction: new + + //-------------------------------------------------------------------- + // reg2bus + //-------------------------------------------------------------------- + virtual function uvm_sequence_item reg2bus(const ref uvm_reg_bus_op rw); + + spi_s_transaction trans_h = spi_s_transaction ::type_id::create("trans_h"); + + // pragma uvmf custom reg2bus begin + // UVMF_CHANGE_ME : Fill in the reg2bus adapter mapping registe fields to protocol fields. + + //Adapt the following for your sequence item type + // trans_h.op = (rw.kind == UVM_READ) ? WB_READ : WB_WRITE; + //Copy over address + // trans_h.addr = rw.addr; + //Copy over write data + // trans_h.data = rw.data; + + // pragma uvmf custom reg2bus end + + // Return the adapted transaction + return trans_h; + + endfunction: reg2bus + + //-------------------------------------------------------------------- + // bus2reg + //-------------------------------------------------------------------- + virtual function void bus2reg(uvm_sequence_item bus_item, + ref uvm_reg_bus_op rw); + spi_s_transaction trans_h; + if (!$cast(trans_h, bus_item)) begin + `uvm_fatal("ADAPT","Provided bus_item is not of the correct type") + return; + end + // pragma uvmf custom bus2reg begin + // UVMF_CHANGE_ME : Fill in the bus2reg adapter mapping protocol fields to register fields. + //Adapt the following for your sequence item type + //Copy over instruction type + // rw.kind = (trans_h.op == WB_WRITE) ? UVM_WRITE : UVM_READ; + //Copy over address + // rw.addr = trans_h.addr; + //Copy over read data + // rw.data = trans_h.data; + //Check for errors on the bus and return UVM_NOT_OK if there is an error + // rw.status = UVM_IS_OK; + // pragma uvmf custom bus2reg end + + endfunction: bus2reg + +endclass : spi_s2reg_adapter + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/spi_s_pkg/src/spi_s_agent.svh b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/spi_s_pkg/src/spi_s_agent.svh new file mode 100644 index 00000000..9a9a24d8 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/spi_s_pkg/src/spi_s_agent.svh @@ -0,0 +1,53 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: Protocol specific agent class definition +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class spi_s_agent extends uvmf_parameterized_agent #( + .CONFIG_T(spi_s_configuration ), + .DRIVER_T(spi_s_driver ), + .MONITOR_T(spi_s_monitor ), + .COVERAGE_T(spi_s_transaction_coverage ), + .TRANS_T(spi_s_transaction ) + ); + + `uvm_component_utils( spi_s_agent ) + +// pragma uvmf custom class_item_additional begin +// pragma uvmf custom class_item_additional end + +// **************************************************************************** +// FUNCTION : new() +// This function is the standard SystemVerilog constructor. +// + function new( string name = "", uvm_component parent = null ); + super.new( name, parent ); + endfunction + +// **************************************************************************** + // FUNCTION: build_phase + virtual function void build_phase(uvm_phase phase); +// pragma uvmf custom build_phase_pre_super begin +// pragma uvmf custom build_phase_pre_super end + super.build_phase(phase); + if (configuration.active_passive == ACTIVE) begin + // Place sequencer handle into configuration object + // so that it may be retrieved from configuration + // rather than using uvm_config_db + configuration.sequencer = this.sequencer; + end + endfunction + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/spi_s_pkg/src/spi_s_configuration.svh b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/spi_s_pkg/src/spi_s_configuration.svh new file mode 100644 index 00000000..14c2735b --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/spi_s_pkg/src/spi_s_configuration.svh @@ -0,0 +1,179 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This class contains all variables and functions used +// to configure the spi_s agent and its bfm's. It gets the +// bfm's from the uvm_config_db for use by the agent. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class spi_s_configuration extends uvmf_parameterized_agent_configuration_base #( + .DRIVER_BFM_BIND_T(virtual spi_s_driver_bfm ), + .MONITOR_BFM_BIND_T( virtual spi_s_monitor_bfm )); + + `uvm_object_utils( spi_s_configuration ) + + + // Sequencer handle populated by agent + uvm_sequencer #(spi_s_transaction ) sequencer; + + //Constraints for the configuration variables: + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + covergroup spi_s_configuration_cg; + // pragma uvmf custom covergroup begin + option.auto_bin_max=1024; + // pragma uvmf custom covergroup end + endgroup + + //******************************************************************* + //******************************************************************* + // Structure used to pass configuration variables to monitor and driver BFM's. + // Use to_struct function to pack variables into structure. + // Use from_struct function to unpack variables from structure. + // This structure is defined in spi_s_macros.svh + `spi_s_CONFIGURATION_STRUCT + spi_s_configuration_s spi_s_configuration_struct; + //******************************************************************* + // FUNCTION: to_struct() + // This function packs variables into a spi_s_configuration_s + // structure. The function returns the handle to the spi_s_configuration_struct. + // This function is defined in spi_s_macros.svh + `spi_s_CONFIGURATION_TO_STRUCT_FUNCTION + //******************************************************************* + // FUNCTION: from_struct() + // This function unpacks the struct provided as an argument into + // variables of this class. + // This function is defined in spi_s_macros.svh + `spi_s_CONFIGURATION_FROM_STRUCT_FUNCTION + + // **************************************************************************** + // FUNCTION : new() + // This function is the standard SystemVerilog constructor. + // + function new( string name = "" ); + super.new( name ); + // Construct the covergroup for this configuration class + spi_s_configuration_cg = new; + endfunction + + // **************************************************************************** + // FUNCTION: post_randomize() + // This function is automatically called after the randomize() function + // is executed. + // + function void post_randomize(); + super.post_randomize(); + spi_s_configuration_cg.sample(); + endfunction + + // **************************************************************************** + // FUNCTION: initialize + // This function causes the configuration to retrieve + // its virtual interface handle from the uvm_config_db. + // This function also makes itself available to its + // agent through the uvm_config_db. + // + // ARGUMENTS: + // uvmf_active_passive_t activity: + // This argument identifies the simulation level + // as either BLOCK, CHIP, SIMULATION, etc. + // + // AGENT_PATH: + // This argument identifies the path to this + // configurations agent. This configuration + // makes itself available to the agent specified + // by agent_path by placing itself into the + // uvm_config_db. + // + // INTERFACE_NAME: + // This argument identifies the string name of + // this configurations BFM's. This string + // name is used to retrieve the driver and + // monitor BFM from the uvm_config_db. + // + virtual function void initialize(uvmf_active_passive_t activity, + string agent_path, + string interface_name); + + super.initialize( activity, agent_path, interface_name); + // The covergroup is given the same name as the interface + spi_s_configuration_cg.set_inst_name(interface_name); + + // This configuration places itself into the uvm_config_db for the agent, identified by the agent_path variable, to retrieve. + uvm_config_db #( spi_s_configuration + )::set( null ,agent_path,UVMF_AGENT_CONFIG, this ); + + // This configuration also places itself in the config db using the same identifier used by the interface. This allows users to access + // configuration variables and the interface through the bfm api class rather than directly accessing the BFM. This is useful for + // accessingthe BFM when using Veloce + uvm_config_db #( spi_s_configuration + )::set( null ,UVMF_CONFIGURATIONS, interface_name, this ); + + spi_s_configuration_cg.set_inst_name($sformatf("spi_s_configuration_cg_%s",get_full_name())); + +// This code is to aid in debugging parameter mismatches between the BFM and its corresponding agent. +// Enable this debug by setting UVM_VERBOSITY to UVM_DEBUG +// Setting UVM_VERBOSITY to UVM_DEBUG causes all BFM's and all agents to display their parameter settings. +// All of the messages from this feature have a UVM messaging id value of "CFG" +// The transcript or run.log can be parsed to ensure BFM parameter settings match its corresponding agents parameter settings. + `uvm_info("CFG", + $psprintf("The agent at '%s' is using interface named %s has the following parameters: ", agent_path, interface_name, ), + UVM_DEBUG) + + // pragma uvmf custom initialize begin + // This controls whether or not the agent returns a transaction handle in the driver when calling + // item_done() back into the sequencer or not. If set to 1, a transaction is sent back which means + // the sequence on the other end must use the get_response() part of the driver/sequence API. If + // this doesn't occur, there will eventually be response_queue overflow errors during the test. + return_transaction_response = 1'b0; + + // pragma uvmf custom initialize end + + endfunction + + // **************************************************************************** + // TASK: wait_for_reset + // *[Required]* Blocks until reset is released. The wait_for_reset operation is performed + // by a task in the monitor bfm. + virtual task wait_for_reset(); + monitor_bfm.wait_for_reset(); + endtask + + // **************************************************************************** + // TASK: wait_for_num_clocks + // *[Required]* Blocks until specified number of clocks have elapsed. The wait_for_num_clocks + // operation is performed by a task in the monitor bfm. + virtual task wait_for_num_clocks(int clocks); + monitor_bfm.wait_for_num_clocks(clocks); + endtask + + // **************************************************************************** + // FUNCTION : convert2string() + // This function is used to convert variables in this class into a string for log messaging. + // + virtual function string convert2string (); + // pragma uvmf custom convert2string begin + return $sformatf(""); + // pragma uvmf custom convert2string end + endfunction + + // **************************************************************************** + // FUNCTION: get_sequencer + function uvm_sequencer #(spi_s_transaction) get_sequencer(); + return sequencer; + endfunction + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/spi_s_pkg/src/spi_s_driver.svh b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/spi_s_pkg/src/spi_s_driver.svh new file mode 100644 index 00000000..2ef57307 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/spi_s_pkg/src/spi_s_driver.svh @@ -0,0 +1,91 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This class passes transactions between the sequencer +// and the BFM driver interface. It accesses the driver BFM +// through the bfm handle. This driver +// passes transactions to the driver BFM through the access +// task. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class spi_s_driver extends uvmf_driver_base #( + .CONFIG_T(spi_s_configuration ), + .BFM_BIND_T(virtual spi_s_driver_bfm ), + .REQ(spi_s_transaction ), + .RSP(spi_s_transaction )); + + `uvm_component_utils( spi_s_driver ) +//******************************************************************* +// Macros that define structs located in spi_s_macros.svh +//******************************************************************* +// Initiator macro used by spi_s_driver and spi_s_driver_bfm +// to communicate initiator driven data to spi_s_driver_bfm. +`spi_s_INITIATOR_STRUCT + spi_s_initiator_s spi_s_initiator_struct; +//******************************************************************* +// Responder macro used by spi_s_driver and spi_s_driver_bfm +// to communicate Responder driven data to spi_s_driver_bfm. +`spi_s_RESPONDER_STRUCT + spi_s_responder_s spi_s_responder_struct; + +// pragma uvmf custom class_item_additional begin +// pragma uvmf custom class_item_additional end + +// **************************************************************************** +// This function is the standard SystemVerilog constructor. +// + function new( string name = "", uvm_component parent=null ); + super.new( name, parent ); + endfunction + +// **************************************************************************** +// This function sends configuration object variables to the driver BFM +// using the configuration struct. +// + virtual function void configure(input CONFIG_T cfg); + bfm.configure( cfg.to_struct() ); + endfunction + +// **************************************************************************** +// This function places a handle to this class in the proxy variable in the +// driver BFM. This allows the driver BFM to call tasks and function within this class. +// + virtual function void set_bfm_proxy_handle(); + bfm.proxy = this; endfunction + +// **************************************************************************** +// This task is called by the run_phase in uvmf_driver_base. + virtual task access( inout REQ txn ); +// pragma uvmf custom access begin + if (configuration.initiator_responder==RESPONDER) begin + // Complete current transfer and wait for next transfer + bfm.respond_and_wait_for_next_transfer( + spi_s_initiator_struct, + txn.to_responder_struct() + ); + // Unpack information about initiated transfer received by this responder + txn.from_initiator_struct(spi_s_initiator_struct); + end else begin + // Initiate a transfer and get response + bfm.initiate_and_get_response( + txn.to_initiator_struct(), + spi_s_responder_struct + ); + // Unpack transfer response information received by this initiator + txn.from_responder_struct(spi_s_responder_struct); + end +// pragma uvmf custom access end + endtask + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/spi_s_pkg/src/spi_s_driver_bfm.sv b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/spi_s_pkg/src/spi_s_driver_bfm.sv new file mode 100644 index 00000000..fe0026ab --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/spi_s_pkg/src/spi_s_driver_bfm.sv @@ -0,0 +1,300 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: +// This interface performs the spi_s signal driving. It is +// accessed by the uvm spi_s driver through a virtual interface +// handle in the spi_s configuration. It drives the singals passed +// in through the port connection named bus of type spi_s_if. +// +// Input signals from the spi_s_if are assigned to an internal input +// signal with a _i suffix. The _i signal should be used for sampling. +// +// The input signal connections are as follows: +// bus.signal -> signal_i +// +// This bfm drives signals with a _o suffix. These signals +// are driven onto signals within spi_s_if based on INITIATOR/RESPONDER and/or +// ARBITRATION/GRANT status. +// +// The output signal connections are as follows: +// signal_o -> bus.signal +// +// +// Interface functions and tasks used by UVM components: +// +// configure: +// This function gets configuration attributes from the +// UVM driver to set any required BFM configuration +// variables such as 'initiator_responder'. +// +// initiate_and_get_response: +// This task is used to perform signaling activity for initiating +// a protocol transfer. The task initiates the transfer, using +// input data from the initiator struct. Then the task captures +// response data, placing the data into the response struct. +// The response struct is returned to the driver class. +// +// respond_and_wait_for_next_transfer: +// This task is used to complete a current transfer as a responder +// and then wait for the initiator to start the next transfer. +// The task uses data in the responder struct to drive protocol +// signals to complete the transfer. The task then waits for +// the next transfer. Once the next transfer begins, data from +// the initiator is placed into the initiator struct and sent +// to the responder sequence for processing to determine +// what data to respond with. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +import uvmf_base_pkg_hdl::*; +import spi_s_pkg_hdl::*; +`include "src/spi_s_macros.svh" + +interface spi_s_driver_bfm + (spi_s_if bus); + // The following pragma and additional ones in-lined further below are for running this BFM on Veloce + // pragma attribute spi_s_driver_bfm partition_interface_xif + +`ifndef XRTL +// This code is to aid in debugging parameter mismatches between the BFM and its corresponding agent. +// Enable this debug by setting UVM_VERBOSITY to UVM_DEBUG +// Setting UVM_VERBOSITY to UVM_DEBUG causes all BFM's and all agents to display their parameter settings. +// All of the messages from this feature have a UVM messaging id value of "CFG" +// The transcript or run.log can be parsed to ensure BFM parameter settings match its corresponding agents parameter settings. +import uvm_pkg::*; +`include "uvm_macros.svh" +initial begin : bfm_vs_agent_parameter_debug + `uvm_info("CFG", + $psprintf("The BFM at '%m' has the following parameters: ", ), + UVM_DEBUG) +end +`endif + + // Config value to determine if this is an initiator or a responder + uvmf_initiator_responder_t initiator_responder; + // Custom configuration variables. + // These are set using the configure function which is called during the UVM connect_phase + + logic sck_i; + logic rst_i; + + // Signal list (all signals are capable of being inputs and outputs for the sake + // of supporting both INITIATOR and RESPONDER mode operation. Expectation is that + // directionality in the config file was from the point-of-view of the INITIATOR + + // INITIATOR mode input signals + tri sclk_i; + reg sclk_o = 'b0; + tri ss_i; + reg ss_o = 'b0; + tri [7:0] mosi_i; + reg [7:0] mosi_o = 'b0; + + // INITIATOR mode output signals + tri [7:0] miso_i; + reg [7:0] miso_o = 'b0; + + // Bi-directional signals + + + assign sck_i = bus.sck; + assign rst_i = bus.rst; + + // These are signals marked as 'input' by the config file, but the signals will be + // driven by this BFM if put into RESPONDER mode (flipping all signal directions around) + assign sclk_i = bus.sclk; + assign bus.sclk = (initiator_responder == RESPONDER) ? sclk_o : 'bz; + assign ss_i = bus.ss; + assign bus.ss = (initiator_responder == RESPONDER) ? ss_o : 'bz; + assign mosi_i = bus.mosi; + assign bus.mosi = (initiator_responder == RESPONDER) ? mosi_o : 'bz; + + + // These are signals marked as 'output' by the config file, but the outputs will + // not be driven by this BFM unless placed in INITIATOR mode. + assign bus.miso = (initiator_responder == INITIATOR) ? miso_o : 'bz; + assign miso_i = bus.miso; + + // Proxy handle to UVM driver + spi_s_pkg::spi_s_driver proxy; + // pragma tbx oneway proxy.my_function_name_in_uvm_driver + + // **************************************************************************** + // **************************************************************************** + // Macros that define structs located in spi_s_macros.svh + // **************************************************************************** + // Struct for passing configuration data from spi_s_driver to this BFM + // **************************************************************************** + `spi_s_CONFIGURATION_STRUCT + // **************************************************************************** + // Structs for INITIATOR and RESPONDER data flow + //******************************************************************* + // Initiator macro used by spi_s_driver and spi_s_driver_bfm + // to communicate initiator driven data to spi_s_driver_bfm. + `spi_s_INITIATOR_STRUCT + spi_s_initiator_s initiator_struct; + // Responder macro used by spi_s_driver and spi_s_driver_bfm + // to communicate Responder driven data to spi_s_driver_bfm. + `spi_s_RESPONDER_STRUCT + spi_s_responder_s responder_struct; + + // **************************************************************************** +// pragma uvmf custom reset_condition_and_response begin + // Always block used to return signals to reset value upon assertion of reset + always @( posedge rst_i ) + begin + // RESPONDER mode output signals + sclk_o <= 'b0; + ss_o <= 'b0; + mosi_o <= 'b0; + // INITIATOR mode output signals + miso_o <= 'b0; + // Bi-directional signals + + end +// pragma uvmf custom reset_condition_and_response end + + // pragma uvmf custom interface_item_additional begin + // pragma uvmf custom interface_item_additional end + + //****************************************************************** + // The configure() function is used to pass agent configuration + // variables to the driver BFM. It is called by the driver within + // the agent at the beginning of the simulation. It may be called + // during the simulation if agent configuration variables are updated + // and the driver BFM needs to be aware of the new configuration + // variables. + // + + function void configure(spi_s_configuration_s spi_s_configuration_arg); // pragma tbx xtf + initiator_responder = spi_s_configuration_arg.initiator_responder; + // pragma uvmf custom configure begin + // pragma uvmf custom configure end + endfunction + +// pragma uvmf custom initiate_and_get_response begin +// **************************************************************************** +// UVMF_CHANGE_ME +// This task is used by an initator. The task first initiates a transfer then +// waits for the responder to complete the transfer. + task initiate_and_get_response( + // This argument passes transaction variables used by an initiator + // to perform the initial part of a protocol transfer. The values + // come from a sequence item created in a sequence. + input spi_s_initiator_s spi_s_initiator_struct, + // This argument is used to send data received from the responder + // back to the sequence item. The sequence item is returned to the sequence. + output spi_s_responder_s spi_s_responder_struct + );// pragma tbx xtf + // + // Members within the spi_s_initiator_struct: + // bit ssel ; + // bit [7:0] mosi ; + // bit [7:0] miso ; + // Members within the spi_s_responder_struct: + // bit ssel ; + // bit [7:0] mosi ; + // bit [7:0] miso ; + initiator_struct = spi_s_initiator_struct; + // + // Reference code; + // How to wait for signal value + // while (control_signal == 1'b1) @(posedge sck_i); + // + // How to assign a responder struct member, named xyz, from a signal. + // All available initiator input and inout signals listed. + // Initiator input signals + // spi_s_responder_struct.xyz = sclk_i; // + // spi_s_responder_struct.xyz = ss_i; // + // spi_s_responder_struct.xyz = mosi_i; // [7:0] + // Initiator inout signals + // How to assign a signal from an initiator struct member named xyz. + // All available initiator output and inout signals listed. + // Notice the _o. Those are storage variables that allow for procedural assignment. + // Initiator output signals + // miso_o <= spi_s_initiator_struct.xyz; // [7:0] + // Initiator inout signals + // Initiate a transfer using the data received. + @(posedge sck_i); + @(posedge sck_i); + // Wait for the responder to complete the transfer then place the responder data into + // spi_s_responder_struct. + @(posedge sck_i); + @(posedge sck_i); + responder_struct = spi_s_responder_struct; + endtask +// pragma uvmf custom initiate_and_get_response end + +// pragma uvmf custom respond_and_wait_for_next_transfer begin +// **************************************************************************** +// The first_transfer variable is used to prevent completing a transfer in the +// first call to this task. For the first call to this task, there is not +// current transfer to complete. +bit first_transfer=1; + +// UVMF_CHANGE_ME +// This task is used by a responder. The task first completes the current +// transfer in progress then waits for the initiator to start the next transfer. + task respond_and_wait_for_next_transfer( + // This argument is used to send data received from the initiator + // back to the sequence item. The sequence determines how to respond. + output spi_s_initiator_s spi_s_initiator_struct, + // This argument passes transaction variables used by a responder + // to complete a protocol transfer. The values come from a sequence item. + input spi_s_responder_s spi_s_responder_struct + );// pragma tbx xtf + // Variables within the spi_s_initiator_struct: + // bit ssel ; + // bit [7:0] mosi ; + // bit [7:0] miso ; + // Variables within the spi_s_responder_struct: + // bit ssel ; + // bit [7:0] mosi ; + // bit [7:0] miso ; + // Reference code; + // How to wait for signal value + // while (control_signal == 1'b1) @(posedge sck_i); + // + // How to assign a responder struct member, named xyz, from a signal. + // All available responder input and inout signals listed. + // Responder input signals + // spi_s_responder_struct.xyz = miso_i; // [7:0] + // Responder inout signals + // How to assign a signal, named xyz, from an initiator struct member. + // All available responder output and inout signals listed. + // Notice the _o. Those are storage variables that allow for procedural assignment. + // Responder output signals + // sclk_o <= spi_s_initiator_struct.xyz; // + // ss_o <= spi_s_initiator_struct.xyz; // + // mosi_o <= spi_s_initiator_struct.xyz; // [7:0] + // Responder inout signals + + @(posedge sck_i); + if (!first_transfer) begin + // Perform transfer response here. + // Reply using data recieved in the spi_s_responder_struct. + @(posedge sck_i); + // Reply using data recieved in the transaction handle. + @(posedge sck_i); + end + // Wait for next transfer then gather info from intiator about the transfer. + // Place the data into the spi_s_initiator_struct. + @(posedge sck_i); + @(posedge sck_i); + first_transfer = 0; + endtask +// pragma uvmf custom respond_and_wait_for_next_transfer end + + +endinterface + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/spi_s_pkg/src/spi_s_if.sv b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/spi_s_pkg/src/spi_s_if.sv new file mode 100644 index 00000000..47150e10 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/spi_s_pkg/src/spi_s_if.sv @@ -0,0 +1,79 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This interface contains the spi_s interface signals. +// It is instantiated once per spi_s bus. Bus Functional Models, +// BFM's named spi_s_driver_bfm, are used to drive signals on the bus. +// BFM's named spi_s_monitor_bfm are used to monitor signals on the +// bus. This interface signal bundle is passed in the port list of +// the BFM in order to give the BFM access to the signals in this +// interface. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// This template can be used to connect a DUT to these signals +// +// .dut_signal_port(spi_s_bus.sclk), // Agent input +// .dut_signal_port(spi_s_bus.ss), // Agent input +// .dut_signal_port(spi_s_bus.mosi), // Agent input +// .dut_signal_port(spi_s_bus.miso), // Agent output + +import uvmf_base_pkg_hdl::*; +import spi_s_pkg_hdl::*; + +interface spi_s_if + + ( + input logic sck, + input logic rst, + input logic sclk, + input logic ss, + input logic [7:0] mosi, + output logic [7:0] miso + ); + +modport monitor_port + ( + input sck, + input rst, + input sclk, + input ss, + input mosi, + input miso + ); + +modport initiator_port + ( + input sck, + input rst, + input sclk, + input ss, + input mosi, + output miso + ); + +modport responder_port + ( + input sck, + input rst, + output sclk, + output ss, + output mosi, + input miso + ); + + +// pragma uvmf custom interface_item_additional begin +// pragma uvmf custom interface_item_additional end + +endinterface + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/spi_s_pkg/src/spi_s_infact_coverage_strategy.csv b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/spi_s_pkg/src/spi_s_infact_coverage_strategy.csv new file mode 100644 index 00000000..1c218e14 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/spi_s_pkg/src/spi_s_infact_coverage_strategy.csv @@ -0,0 +1,6 @@ +Global +auto_bin_max, 64 + +Name,Type,Include +rand_fields,coverpoint,=rand *.** + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/spi_s_pkg/src/spi_s_macros.svh b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/spi_s_pkg/src/spi_s_macros.svh new file mode 100644 index 00000000..cbf12ff6 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/spi_s_pkg/src/spi_s_macros.svh @@ -0,0 +1,139 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This file contains macros used with the spi_s package. +// These macros include packed struct definitions. These structs are +// used to pass data between classes, hvl, and BFM's, hdl. Use of +// structs are more efficient and simpler to modify. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// + +// **************************************************************************** +// When changing the contents of this struct, be sure to update the to_struct +// and from_struct methods defined in the macros below that are used in +// the spi_s_configuration class. +// + `define spi_s_CONFIGURATION_STRUCT \ +typedef struct packed { \ + uvmf_active_passive_t active_passive; \ + uvmf_initiator_responder_t initiator_responder; \ + } spi_s_configuration_s; + + `define spi_s_CONFIGURATION_TO_STRUCT_FUNCTION \ + virtual function spi_s_configuration_s to_struct();\ + spi_s_configuration_struct = \ + {\ + this.active_passive,\ + this.initiator_responder\ + };\ + return ( spi_s_configuration_struct );\ + endfunction + + `define spi_s_CONFIGURATION_FROM_STRUCT_FUNCTION \ + virtual function void from_struct(spi_s_configuration_s spi_s_configuration_struct);\ + {\ + this.active_passive,\ + this.initiator_responder \ + } = spi_s_configuration_struct;\ + endfunction + +// **************************************************************************** +// When changing the contents of this struct, be sure to update the to_monitor_struct +// and from_monitor_struct methods of the spi_s_transaction class. +// + `define spi_s_MONITOR_STRUCT typedef struct packed { \ + bit ssel ; \ + bit [7:0] mosi ; \ + bit [7:0] miso ; \ + } spi_s_monitor_s; + + `define spi_s_TO_MONITOR_STRUCT_FUNCTION \ + virtual function spi_s_monitor_s to_monitor_struct();\ + spi_s_monitor_struct = \ + { \ + this.ssel , \ + this.mosi , \ + this.miso \ + };\ + return ( spi_s_monitor_struct);\ + endfunction\ + + `define spi_s_FROM_MONITOR_STRUCT_FUNCTION \ + virtual function void from_monitor_struct(spi_s_monitor_s spi_s_monitor_struct);\ + {\ + this.ssel , \ + this.mosi , \ + this.miso \ + } = spi_s_monitor_struct;\ + endfunction + +// **************************************************************************** +// When changing the contents of this struct, be sure to update the to_initiator_struct +// and from_initiator_struct methods of the spi_s_transaction class. +// Also update the comments in the driver BFM. +// + `define spi_s_INITIATOR_STRUCT typedef struct packed { \ + bit ssel ; \ + bit [7:0] mosi ; \ + bit [7:0] miso ; \ + } spi_s_initiator_s; + + `define spi_s_TO_INITIATOR_STRUCT_FUNCTION \ + virtual function spi_s_initiator_s to_initiator_struct();\ + spi_s_initiator_struct = \ + {\ + this.ssel , \ + this.mosi , \ + this.miso \ + };\ + return ( spi_s_initiator_struct);\ + endfunction + + `define spi_s_FROM_INITIATOR_STRUCT_FUNCTION \ + virtual function void from_initiator_struct(spi_s_initiator_s spi_s_initiator_struct);\ + {\ + this.ssel , \ + this.mosi , \ + this.miso \ + } = spi_s_initiator_struct;\ + endfunction + +// **************************************************************************** +// When changing the contents of this struct, be sure to update the to_responder_struct +// and from_responder_struct methods of the spi_s_transaction class. +// Also update the comments in the driver BFM. +// + `define spi_s_RESPONDER_STRUCT typedef struct packed { \ + bit ssel ; \ + bit [7:0] mosi ; \ + bit [7:0] miso ; \ + } spi_s_responder_s; + + `define spi_s_TO_RESPONDER_STRUCT_FUNCTION \ + virtual function spi_s_responder_s to_responder_struct();\ + spi_s_responder_struct = \ + {\ + this.ssel , \ + this.mosi , \ + this.miso \ + };\ + return ( spi_s_responder_struct);\ + endfunction + + `define spi_s_FROM_RESPONDER_STRUCT_FUNCTION \ + virtual function void from_responder_struct(spi_s_responder_s spi_s_responder_struct);\ + {\ + this.ssel , \ + this.mosi , \ + this.miso \ + } = spi_s_responder_struct;\ + endfunction +// pragma uvmf custom additional begin +// pragma uvmf custom additional end diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/spi_s_pkg/src/spi_s_monitor.svh b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/spi_s_pkg/src/spi_s_monitor.svh new file mode 100644 index 00000000..31289dd6 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/spi_s_pkg/src/spi_s_monitor.svh @@ -0,0 +1,87 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This class receives spi_s transactions observed by the +// spi_s monitor BFM and broadcasts them through the analysis port +// on the agent. It accesses the monitor BFM through the monitor +// task. This UVM component captures transactions +// for viewing in the waveform viewer if the +// enable_transaction_viewing flag is set in the configuration. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class spi_s_monitor extends uvmf_monitor_base #( + .CONFIG_T(spi_s_configuration ), + .BFM_BIND_T(virtual spi_s_monitor_bfm ), + .TRANS_T(spi_s_transaction )); + + `uvm_component_utils( spi_s_monitor ) + +// Structure used to pass data from monitor BFM to monitor class in agent. +// Use to_monitor_struct function to pack transaction variables into structure. +// Use from_monitor_struct function to unpack transaction variables from structure. +`spi_s_MONITOR_STRUCT + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + +// **************************************************************************** +// This function is the standard SystemVerilog constructor. +// + function new( string name = "", uvm_component parent = null ); + super.new( name, parent ); + endfunction + +// **************************************************************************** +// This function sends configuration object variables to the monitor BFM +// using the configuration struct. +// + virtual function void configure(input CONFIG_T cfg); + bfm.configure( cfg.to_struct() ); + + endfunction + +// **************************************************************************** +// This function places a handle to this class in the proxy variable in the +// monitor BFM. This allows the monitor BFM to call the notify_transaction +// function within this class. +// + virtual function void set_bfm_proxy_handle(); + bfm.proxy = this; endfunction + +// *************************************************************************** + virtual task run_phase(uvm_phase phase); + // Start monitor BFM thread and don't call super.run() in order to + // override the default monitor proxy 'pull' behavior with the more + // emulation-friendly BFM 'push' approach using the notify_transaction + // function below + bfm.start_monitoring(); + endtask + +// ************************************************************************** + +// This function is called by the monitor BFM. It receives data observed by the +// monitor BFM. Data is passed using the spi_s_monitor_struct. + virtual function void notify_transaction(input spi_s_monitor_s spi_s_monitor_struct); + + + trans = new("trans"); + trans.from_monitor_struct(spi_s_monitor_struct); + trans.start_time = time_stamp; + trans.end_time = $time; + time_stamp = trans.end_time; + + analyze(trans); + endfunction + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/spi_s_pkg/src/spi_s_monitor_bfm.sv b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/spi_s_pkg/src/spi_s_monitor_bfm.sv new file mode 100644 index 00000000..68438155 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/spi_s_pkg/src/spi_s_monitor_bfm.sv @@ -0,0 +1,185 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This interface performs the spi_s signal monitoring. +// It is accessed by the uvm spi_s monitor through a virtual +// interface handle in the spi_s configuration. It monitors the +// signals passed in through the port connection named bus of +// type spi_s_if. +// +// Input signals from the spi_s_if are assigned to an internal input +// signal with a _i suffix. The _i signal should be used for sampling. +// +// The input signal connections are as follows: +// bus.signal -> signal_i +// +// Interface functions and tasks used by UVM components: +// monitor(inout TRANS_T txn); +// This task receives the transaction, txn, from the +// UVM monitor and then populates variables in txn +// from values observed on bus activity. This task +// blocks until an operation on the spi_s bus is complete. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +import uvmf_base_pkg_hdl::*; +import spi_s_pkg_hdl::*; +`include "src/spi_s_macros.svh" + + +interface spi_s_monitor_bfm + ( spi_s_if bus ); + // The pragma below and additional ones in-lined further down are for running this BFM on Veloce + // pragma attribute spi_s_monitor_bfm partition_interface_xif + +`ifndef XRTL +// This code is to aid in debugging parameter mismatches between the BFM and its corresponding agent. +// Enable this debug by setting UVM_VERBOSITY to UVM_DEBUG +// Setting UVM_VERBOSITY to UVM_DEBUG causes all BFM's and all agents to display their parameter settings. +// All of the messages from this feature have a UVM messaging id value of "CFG" +// The transcript or run.log can be parsed to ensure BFM parameter settings match its corresponding agents parameter settings. +import uvm_pkg::*; +`include "uvm_macros.svh" +initial begin : bfm_vs_agent_parameter_debug + `uvm_info("CFG", + $psprintf("The BFM at '%m' has the following parameters: ", ), + UVM_DEBUG) +end +`endif + + + // Structure used to pass transaction data from monitor BFM to monitor class in agent. +`spi_s_MONITOR_STRUCT + spi_s_monitor_s spi_s_monitor_struct; + + // Structure used to pass configuration data from monitor class to monitor BFM. + `spi_s_CONFIGURATION_STRUCT + + + // Config value to determine if this is an initiator or a responder + uvmf_initiator_responder_t initiator_responder; + // Custom configuration variables. + // These are set using the configure function which is called during the UVM connect_phase + + logic sck_i; + logic rst_i; + tri sclk_i; + tri ss_i; + tri [7:0] mosi_i; + tri [7:0] miso_i; + assign sck_i = bus.sck; + assign rst_i = bus.rst; + assign sclk_i = bus.sclk; + assign ss_i = bus.ss; + assign mosi_i = bus.mosi; + assign miso_i = bus.miso; + + // Proxy handle to UVM monitor + spi_s_pkg::spi_s_monitor proxy; + // pragma tbx oneway proxy.notify_transaction + + // pragma uvmf custom interface_item_additional begin + // pragma uvmf custom interface_item_additional end + + //****************************************************************** + task wait_for_reset();// pragma tbx xtf + @(posedge sck_i) ; + do_wait_for_reset(); + endtask + + // **************************************************************************** + task do_wait_for_reset(); + // pragma uvmf custom reset_condition begin + wait ( rst_i === 0 ) ; + @(posedge sck_i) ; + // pragma uvmf custom reset_condition end + endtask + + //****************************************************************** + + task wait_for_num_clocks(input int unsigned count); // pragma tbx xtf + @(posedge sck_i); + + repeat (count-1) @(posedge sck_i); + endtask + + //****************************************************************** + event go; + function void start_monitoring();// pragma tbx xtf + -> go; + endfunction + + // **************************************************************************** + initial begin + @go; + forever begin + @(posedge sck_i); + do_monitor( spi_s_monitor_struct ); + + + proxy.notify_transaction( spi_s_monitor_struct ); + + end + end + + //****************************************************************** + // The configure() function is used to pass agent configuration + // variables to the monitor BFM. It is called by the monitor within + // the agent at the beginning of the simulation. It may be called + // during the simulation if agent configuration variables are updated + // and the monitor BFM needs to be aware of the new configuration + // variables. + // + function void configure(spi_s_configuration_s spi_s_configuration_arg); // pragma tbx xtf + initiator_responder = spi_s_configuration_arg.initiator_responder; + // pragma uvmf custom configure begin + // pragma uvmf custom configure end + endfunction + + + // **************************************************************************** + + task do_monitor(output spi_s_monitor_s spi_s_monitor_struct); + // + // Available struct members: + // // spi_s_monitor_struct.ssel + // // spi_s_monitor_struct.mosi + // // spi_s_monitor_struct.miso + // // + // Reference code; + // How to wait for signal value + // while (control_signal === 1'b1) @(posedge sck_i); + // + // How to assign a struct member, named xyz, from a signal. + // All available input signals listed. + // spi_s_monitor_struct.xyz = sclk_i; // + // spi_s_monitor_struct.xyz = ss_i; // + // spi_s_monitor_struct.xyz = mosi_i; // [7:0] + // spi_s_monitor_struct.xyz = miso_i; // [7:0] + // pragma uvmf custom do_monitor begin + // UVMF_CHANGE_ME : Implement protocol monitoring. The commented reference code + // below are examples of how to capture signal values and assign them to + // structure members. All available input signals are listed. The 'while' + // code example shows how to wait for a synchronous flow control signal. This + // task should return when a complete transfer has been observed. Once this task is + // exited with captured values, it is then called again to wait for and observe + // the next transfer. One clock cycle is consumed between calls to do_monitor. + @(posedge sck_i); + @(posedge sck_i); + @(posedge sck_i); + @(posedge sck_i); + // pragma uvmf custom do_monitor end + endtask + + +endinterface + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/spi_s_pkg/src/spi_s_random_sequence.svh b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/spi_s_pkg/src/spi_s_random_sequence.svh new file mode 100644 index 00000000..799ca4ff --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/spi_s_pkg/src/spi_s_random_sequence.svh @@ -0,0 +1,53 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: +// This sequences randomizes the spi_s transaction and sends it +// to the UVM driver. +// +// This sequence constructs and randomizes a spi_s_transaction. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class spi_s_random_sequence + extends spi_s_sequence_base ; + + `uvm_object_utils( spi_s_random_sequence ) + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + //***************************************************************** + function new(string name = ""); + super.new(name); + endfunction: new + + // **************************************************************************** + // TASK : body() + // This task is automatically executed when this sequence is started using the + // start(sequencerHandle) task. + // + task body(); + + // Construct the transaction + req=spi_s_transaction::type_id::create("req"); + start_item(req); + // Randomize the transaction + if(!req.randomize()) `uvm_fatal("SEQ", "spi_s_random_sequence::body()-spi_s_transaction randomization failed") + // Send the transaction to the spi_s_driver_bfm via the sequencer and spi_s_driver. + finish_item(req); + `uvm_info("SEQ", {"Response:",req.convert2string()},UVM_MEDIUM) + + endtask + +endclass: spi_s_random_sequence + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/spi_s_pkg/src/spi_s_responder_sequence.svh b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/spi_s_pkg/src/spi_s_responder_sequence.svh new file mode 100644 index 00000000..f7a9964e --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/spi_s_pkg/src/spi_s_responder_sequence.svh @@ -0,0 +1,49 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This class can be used to provide stimulus when an interface +// has been configured to run in a responder mode. It +// will never finish by default, always going back to the driver +// and driver BFM for the next transaction with which to respond. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class spi_s_responder_sequence + extends spi_s_sequence_base ; + + `uvm_object_utils( spi_s_responder_sequence ) + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + function new(string name = "spi_s_responder_sequence"); + super.new(name); + endfunction + + task body(); + req=spi_s_transaction::type_id::create("req"); + forever begin + start_item(req); + finish_item(req); + // pragma uvmf custom body begin + // UVMF_CHANGE_ME : Do something here with the resulting req item. The + // finish_item() call above will block until the req transaction is ready + // to be handled by the responder sequence. + // If this was an item that required a response, the expectation is + // that the response should be populated within this transaction now. + `uvm_info("SEQ",$sformatf("Processed txn: %s",req.convert2string()),UVM_HIGH) + // pragma uvmf custom body end + end + endtask + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/spi_s_pkg/src/spi_s_sequence_base.svh b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/spi_s_pkg/src/spi_s_sequence_base.svh new file mode 100644 index 00000000..fca6ae59 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/spi_s_pkg/src/spi_s_sequence_base.svh @@ -0,0 +1,96 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: +// This file contains the class used as the base class for all sequences +// for this interface. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class spi_s_sequence_base extends uvmf_sequence_base #( + .REQ(spi_s_transaction ), + .RSP(spi_s_transaction )); + + `uvm_object_utils( spi_s_sequence_base ) + + // variables + typedef spi_s_transaction spi_s_transaction_req_t; + spi_s_transaction_req_t req; + typedef spi_s_transaction spi_s_transaction_rsp_t; + spi_s_transaction_rsp_t rsp; + + // Event for identifying when a response was received from the sequencer + event new_rsp; + + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + // **************************************************************************** + // TASK : get_responses() + // This task recursively gets sequence item responses from the sequencer. + // + virtual task get_responses(); + fork + begin + // Block until new rsp available + get_response(rsp); + // New rsp received. Indicate to sequence using event. + ->new_rsp; + // Display the received response transaction + `uvm_info("SEQ", {"New response transaction:",rsp.convert2string()}, UVM_MEDIUM) + end + join_none + endtask + + // **************************************************************************** + // TASK : pre_body() + // This task is called automatically when start is called with call_pre_post set to 1 (default). + // By calling get_responses() within pre_body() any derived sequences are automatically + // processing response transactions. Only un-comment this call to get_responses() if you + // have configured the interface driver to utilize the response transaction path by setting + // the configuration variable "return_transaction_response" to 1. Otherwise it is possible + // to impact runtime performance and memory utilization. + // + virtual task pre_body(); + // pragma uvmf custom pre_body begin +// get_responses(); + // pragma uvmf custom pre_body end + endtask + + // **************************************************************************** + // TASK : body() + // This task is called automatically when start is called. This sequence sends + // a req sequence item to the sequencer identified as an argument in the call + // to start. + // + virtual task body(); + // pragma uvmf custom body begin + start_item(req); + finish_item(req); + // pragma uvmf custom body end + endtask + + // **************************************************************************** + // FUNCTION : new() + // This function is the standard SystemVerilog constructor. + // + function new( string name =""); + super.new( name ); + // pragma uvmf custom new begin + req = spi_s_transaction_req_t::type_id::create("req"); + rsp = spi_s_transaction_rsp_t::type_id::create("rsp"); + // pragma uvmf custom new end + endfunction + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/spi_s_pkg/src/spi_s_transaction.svh b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/spi_s_pkg/src/spi_s_transaction.svh new file mode 100644 index 00000000..7edd633c --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/spi_s_pkg/src/spi_s_transaction.svh @@ -0,0 +1,190 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This class defines the variables required for an spi_s +// transaction. Class variables to be displayed in waveform transaction +// viewing are added to the transaction viewing stream in the add_to_wave +// function. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class spi_s_transaction extends uvmf_transaction_base; + + `uvm_object_utils( spi_s_transaction ) + + bit ssel ; + bit [7:0] mosi ; + rand bit [7:0] miso ; + + //Constraints for the transaction variables: + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + //******************************************************************* + //******************************************************************* + // Macros that define structs and associated functions are + // located in spi_s_macros.svh + + //******************************************************************* + // Monitor macro used by spi_s_monitor and spi_s_monitor_bfm + // This struct is defined in spi_s_macros.svh + `spi_s_MONITOR_STRUCT + spi_s_monitor_s spi_s_monitor_struct; + //******************************************************************* + // FUNCTION: to_monitor_struct() + // This function packs transaction variables into a spi_s_monitor_s + // structure. The function returns the handle to the spi_s_monitor_struct. + // This function is defined in spi_s_macros.svh + `spi_s_TO_MONITOR_STRUCT_FUNCTION + //******************************************************************* + // FUNCTION: from_monitor_struct() + // This function unpacks the struct provided as an argument into transaction + // variables of this class. + // This function is defined in spi_s_macros.svh + `spi_s_FROM_MONITOR_STRUCT_FUNCTION + + //******************************************************************* + // Initiator macro used by spi_s_driver and spi_s_driver_bfm + // to communicate initiator driven data to spi_s_driver_bfm. + // This struct is defined in spi_s_macros.svh + `spi_s_INITIATOR_STRUCT + spi_s_initiator_s spi_s_initiator_struct; + //******************************************************************* + // FUNCTION: to_initiator_struct() + // This function packs transaction variables into a spi_s_initiator_s + // structure. The function returns the handle to the spi_s_initiator_struct. + // This function is defined in spi_s_macros.svh + `spi_s_TO_INITIATOR_STRUCT_FUNCTION + //******************************************************************* + // FUNCTION: from_initiator_struct() + // This function unpacks the struct provided as an argument into transaction + // variables of this class. + // This function is defined in spi_s_macros.svh + `spi_s_FROM_INITIATOR_STRUCT_FUNCTION + + //******************************************************************* + // Responder macro used by spi_s_driver and spi_s_driver_bfm + // to communicate Responder driven data to spi_s_driver_bfm. + // This struct is defined in spi_s_macros.svh + `spi_s_RESPONDER_STRUCT + spi_s_responder_s spi_s_responder_struct; + //******************************************************************* + // FUNCTION: to_responder_struct() + // This function packs transaction variables into a spi_s_responder_s + // structure. The function returns the handle to the spi_s_responder_struct. + // This function is defined in spi_s_macros.svh + `spi_s_TO_RESPONDER_STRUCT_FUNCTION + //******************************************************************* + // FUNCTION: from_responder_struct() + // This function unpacks the struct provided as an argument into transaction + // variables of this class. + // This function is defined in spi_s_macros.svh + `spi_s_FROM_RESPONDER_STRUCT_FUNCTION + // **************************************************************************** + // FUNCTION : new() + // This function is the standard SystemVerilog constructor. + // + function new( string name = "" ); + super.new( name ); + endfunction + + // **************************************************************************** + // FUNCTION: convert2string() + // This function converts all variables in this class to a single string for + // logfile reporting. + // + virtual function string convert2string(); + // pragma uvmf custom convert2string begin + // UVMF_CHANGE_ME : Customize format if desired. + return $sformatf("ssel:0x%x mosi:0x%x miso:0x%x ",ssel,mosi,miso); + // pragma uvmf custom convert2string end + endfunction + + //******************************************************************* + // FUNCTION: do_print() + // This function is automatically called when the .print() function + // is called on this class. + // + virtual function void do_print(uvm_printer printer); + // pragma uvmf custom do_print begin + // UVMF_CHANGE_ME : Current contents of do_print allows for the use of UVM 1.1d, 1.2 or P1800.2. + // Update based on your own printing preference according to your preferred UVM version + $display(convert2string()); + // pragma uvmf custom do_print end + endfunction + + //******************************************************************* + // FUNCTION: do_compare() + // This function is automatically called when the .compare() function + // is called on this class. + // + virtual function bit do_compare (uvm_object rhs, uvm_comparer comparer); + spi_s_transaction RHS; + if (!$cast(RHS,rhs)) return 0; + // pragma uvmf custom do_compare begin + // UVMF_CHANGE_ME : Eliminate comparison of variables not to be used for compare + return (super.do_compare(rhs,comparer) + &&(this.ssel == RHS.ssel) + &&(this.mosi == RHS.mosi) + &&(this.miso == RHS.miso) + ); + // pragma uvmf custom do_compare end + endfunction + + //******************************************************************* + // FUNCTION: do_copy() + // This function is automatically called when the .copy() function + // is called on this class. + // + virtual function void do_copy (uvm_object rhs); + spi_s_transaction RHS; + assert($cast(RHS,rhs)); + // pragma uvmf custom do_copy begin + super.do_copy(rhs); + this.ssel = RHS.ssel; + this.mosi = RHS.mosi; + this.miso = RHS.miso; + // pragma uvmf custom do_copy end + endfunction + + // **************************************************************************** + // FUNCTION: add_to_wave() + // This function is used to display variables in this class in the waveform + // viewer. The start_time and end_time variables must be set before this + // function is called. If the start_time and end_time variables are not set + // the transaction will be hidden at 0ns on the waveform display. + // + virtual function void add_to_wave(int transaction_viewing_stream_h); + `ifdef QUESTA + if (transaction_view_h == 0) begin + transaction_view_h = $begin_transaction(transaction_viewing_stream_h,"spi_s_transaction",start_time); + end + super.add_to_wave(transaction_view_h); + // pragma uvmf custom add_to_wave begin + // UVMF_CHANGE_ME : Color can be applied to transaction entries based on content, example below + // case() + // 1 : $add_color(transaction_view_h,"red"); + // default : $add_color(transaction_view_h,"grey"); + // endcase + // UVMF_CHANGE_ME : Eliminate transaction variables not wanted in transaction viewing in the waveform viewer + $add_attribute(transaction_view_h,ssel,"ssel"); + $add_attribute(transaction_view_h,mosi,"mosi"); + $add_attribute(transaction_view_h,miso,"miso"); + // pragma uvmf custom add_to_wave end + $end_transaction(transaction_view_h,end_time); + $free_transaction(transaction_view_h); + `endif // QUESTA + endfunction + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/spi_s_pkg/src/spi_s_transaction_coverage.svh b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/spi_s_pkg/src/spi_s_transaction_coverage.svh new file mode 100644 index 00000000..cbde0275 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/spi_s_pkg/src/spi_s_transaction_coverage.svh @@ -0,0 +1,72 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This class records spi_s transaction information using +// a covergroup named spi_s_transaction_cg. An instance of this +// coverage component is instantiated in the uvmf_parameterized_agent +// if the has_coverage flag is set. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class spi_s_transaction_coverage extends uvm_subscriber #(.T(spi_s_transaction )); + + `uvm_component_utils( spi_s_transaction_coverage ) + + T coverage_trans; + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + // **************************************************************************** + covergroup spi_s_transaction_cg; + // pragma uvmf custom covergroup begin + // UVMF_CHANGE_ME : Add coverage bins, crosses, exclusions, etc. according to coverage needs. + option.auto_bin_max=1024; + option.per_instance=1; + ssel: coverpoint coverage_trans.ssel; + mosi: coverpoint coverage_trans.mosi; + miso: coverpoint coverage_trans.miso; + // pragma uvmf custom covergroup end + endgroup + + // **************************************************************************** + // FUNCTION : new() + // This function is the standard SystemVerilog constructor. + // + function new(string name="", uvm_component parent=null); + super.new(name,parent); + spi_s_transaction_cg=new; + `uvm_warning("COVERAGE_MODEL_REVIEW", "A covergroup has been constructed which may need review because of either generation or re-generation with merging. Please note that transaction variables added as a result of re-generation and merging are not automatically added to the covergroup. Remove this warning after the covergroup has been reviewed.") + endfunction + + // **************************************************************************** + // FUNCTION : build_phase() + // This function is the standard UVM build_phase. + // + function void build_phase(uvm_phase phase); + spi_s_transaction_cg.set_inst_name($sformatf("spi_s_transaction_cg_%s",get_full_name())); + endfunction + + // **************************************************************************** + // FUNCTION: write (T t) + // This function is automatically executed when a transaction arrives on the + // analysis_export. It copies values from the variables in the transaction + // to local variables used to collect functional coverage. + // + virtual function void write (T t); + `uvm_info("COV","Received transaction",UVM_HIGH); + coverage_trans = t; + spi_s_transaction_cg.sample(); + endfunction + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/spi_s_pkg/src/spi_s_typedefs.svh b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/spi_s_pkg/src/spi_s_typedefs.svh new file mode 100644 index 00000000..43d85640 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/spi_s_pkg/src/spi_s_typedefs.svh @@ -0,0 +1,20 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: +// This file contains defines and typedefs to be compiled for use in +// the simulation running on the host server when using Veloce. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// + + +// pragma uvmf custom additional begin +// pragma uvmf custom additional end + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/spi_s_pkg/src/spi_s_typedefs_hdl.svh b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/spi_s_pkg/src/spi_s_typedefs_hdl.svh new file mode 100644 index 00000000..74738c8c --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/spi_s_pkg/src/spi_s_typedefs_hdl.svh @@ -0,0 +1,21 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: +// This file contains defines and typedefs to be compiled for use in +// the simulation running on the emulator when using Veloce. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// + + + +// pragma uvmf custom additional begin +// pragma uvmf custom additional end + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/spi_s_pkg/yaml/spi_s_interface.yaml b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/spi_s_pkg/yaml/spi_s_interface.yaml new file mode 100644 index 00000000..b00c98ca --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/spi_s_pkg/yaml/spi_s_interface.yaml @@ -0,0 +1,53 @@ +uvmf: + interfaces: + spi_s: + clock: sck + config_constraints: [] + config_vars: [] + existing_library_component: 'True' + gen_inbound_streaming_driver: 'False' + hdl_pkg_parameters: [] + hdl_typedefs: [] + hvl_pkg_parameters: [] + hvl_typedefs: [] + parameters: [] + ports: + - dir: input + name: sclk + reset_value: '''b0' + width: '1' + - dir: input + name: ss + reset_value: '''b0' + width: '1' + - dir: input + name: mosi + reset_value: '''b0' + width: '8' + - dir: output + name: miso + reset_value: '''b0' + width: '8' + reset: rst + reset_assertion_level: 'True' + transaction_constraints: [] + transaction_vars: + - comment: '' + iscompare: 'True' + isrand: 'False' + name: ssel + type: bit + unpacked_dimension: '' + - comment: '' + iscompare: 'True' + isrand: 'False' + name: mosi + type: bit [7:0] + unpacked_dimension: '' + - comment: '' + iscompare: 'True' + isrand: 'True' + name: miso + type: bit [7:0] + unpacked_dimension: '' + use_dpi_link: 'False' diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/wb_s_pkg/.project b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/wb_s_pkg/.project new file mode 100644 index 00000000..d9963c6a --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/wb_s_pkg/.project @@ -0,0 +1,30 @@ + + + wb_s_pkg + + + + + + org.python.pydev.PyDevBuilder + + + + + net.sf.sveditor.core.SVProjectBuilder + + + + + + net.sf.sveditor.core.SVNature + org.python.pydev.pythonNature + + + + UVMF_VIP_LIBRARY_HOME + $%7BPARENT-2-PROJECT_LOC%7D + + + + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/wb_s_pkg/.svproject b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/wb_s_pkg/.svproject new file mode 100644 index 00000000..0edf84a9 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/wb_s_pkg/.svproject @@ -0,0 +1,16 @@ + + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/wb_s_pkg/Makefile b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/wb_s_pkg/Makefile new file mode 100644 index 00000000..2ccf8e80 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/wb_s_pkg/Makefile @@ -0,0 +1,66 @@ +# wb_s interface packages source +# pragma uvmf custom additional begin +# pragma uvmf custom additional end + +wb_s_PKG = \ + +incdir+$(UVMF_VIP_LIBRARY_HOME)/interface_packages/wb_s_pkg \ + -F $(UVMF_VIP_LIBRARY_HOME)/interface_packages/wb_s_pkg/wb_s_filelist_hvl.f + +wb_s_PKG_HDL = \ + +incdir+$(UVMF_VIP_LIBRARY_HOME)/interface_packages/wb_s_pkg \ + -F $(UVMF_VIP_LIBRARY_HOME)/interface_packages/wb_s_pkg/wb_s_filelist_hdl.f + +wb_s_PKG_XRTL = \ + +incdir+$(UVMF_VIP_LIBRARY_HOME)/interface_packages/wb_s_pkg \ + -F $(UVMF_VIP_LIBRARY_HOME)/interface_packages/wb_s_pkg/wb_s_filelist_xrtl.f + +COMP_wb_s_PKG_TGT_0 = q_comp_wb_s_pkg +COMP_wb_s_PKG_TGT_1 = v_comp_wb_s_pkg +COMP_wb_s_PKG_TGT = $(COMP_wb_s_PKG_TGT_$(USE_VELOCE)) + +comp_wb_s_pkg: $(COMP_wb_s_PKG_TGT) + +q_comp_wb_s_pkg: + $(HDL_COMP_CMD) $(wb_s_PKG_HDL) + $(HVL_COMP_CMD) $(wb_s_PKG) + $(HDL_COMP_CMD) $(wb_s_PKG_XRTL) + +v_comp_wb_s_pkg: + $(HVL_COMP_CMD) $(wb_s_PKG_HDL) + $(HVL_COMP_CMD) $(wb_s_PKG) + $(VELANALYZE_CMD) $(wb_s_PKG_HDL) + $(VELANALYZE_HVL_CMD) $(wb_s_PKG) + $(HDL_COMP_CMD) $(wb_s_PKG_XRTL) + +ifeq ($(MTI_VCO_MODE),64) + GCC_COMP_ARCH = -m64 +else + GCC_COMP_ARCH = -m32 +endif + +export wb_s_IF_DPI_SRC ?= $(UVMF_VIP_LIBRARY_HOME)/interface_packages/wb_s_pkg/dpi + +C_FILE_COMPILE_LIST_wb_s_pkg = \ + +O_FILE_COMPILE_LIST_wb_s_pkg = $(notdir $(C_FILE_COMPILE_LIST_wb_s_pkg:.c=.o)) + +GCC_COMP_ARGS_wb_s_pkg += -I$(wb_s_IF_DPI_SRC) \ + -fPIC + +GCC_COMP_ARGS_wb_s_pkg += $(wb_s_IF_GCC_COMP_ARGUMENTS) + +GCC_LINK_ARGS_wb_s_pkg += \ + \ + -o .so + +comp_wb_s_pkg_c_files: + @echo "--------------------------------" + @echo "Compiling Interface C source" + @echo "--------------------------------" + gcc $(GCC_COMP_ARCH) $(GCC_COMP_ARGS_wb_s_pkg) $(C_FILE_COMPILE_LIST_wb_s_pkg) + @echo "--------------------------------" + @echo "Linking Interface C objects into a shared object" + @echo "--------------------------------" + gcc $(GCC_COMP_ARCH) $(GCC_LINK_ARGS_wb_s_pkg) $(O_FILE_COMPILE_LIST_wb_s_pkg) + @echo "--------------------------------" + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/wb_s_pkg/compile.do b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/wb_s_pkg/compile.do new file mode 100644 index 00000000..55cf9dcd --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/wb_s_pkg/compile.do @@ -0,0 +1,14 @@ +# Tcl do file for compile of wb_s interface + +# pragma uvmf custom additional begin +# pragma uvmf custom additional end + + +vlog -sv -timescale 1ps/1ps -suppress 2223,2286 +incdir+$env(UVMF_VIP_LIBRARY_HOME)/interface_packages/wb_s_pkg \ + -F $env(UVMF_VIP_LIBRARY_HOME)/interface_packages/wb_s_pkg/wb_s_filelist_hdl.f + +vlog -sv -timescale 1ps/1ps -suppress 2223,2286 +incdir+$env(UVMF_VIP_LIBRARY_HOME)/interface_packages/wb_s_pkg \ + -F $env(UVMF_VIP_LIBRARY_HOME)/interface_packages/wb_s_pkg/wb_s_filelist_hvl.f + +vlog -sv -timescale 1ps/1ps -suppress 2223,2286 +incdir+$env(UVMF_VIP_LIBRARY_HOME)/interface_packages/wb_s_pkg \ + -F $env(UVMF_VIP_LIBRARY_HOME)/interface_packages/wb_s_pkg/wb_s_filelist_xrtl.f \ No newline at end of file diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/wb_s_pkg/src/wb_s2reg_adapter.svh b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/wb_s_pkg/src/wb_s2reg_adapter.svh new file mode 100644 index 00000000..b8230f45 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/wb_s_pkg/src/wb_s2reg_adapter.svh @@ -0,0 +1,113 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: +// This file contains the UVM register adapter for the wb_s interface. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class wb_s2reg_adapter #( + int WB_ADDR_WIDTH = 32, + int WB_DATA_WIDTH = 16 + ) extends uvm_reg_adapter; + + `uvm_object_param_utils( wb_s2reg_adapter #( + WB_ADDR_WIDTH, + WB_DATA_WIDTH + )) + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + //-------------------------------------------------------------------- + // new + //-------------------------------------------------------------------- + function new (string name = "wb_s2reg_adapter" ); + super.new(name); + // pragma uvmf custom new begin + // UVMF_CHANGE_ME : Configure the adapter regarding byte enables and provides response. + + // Does the protocol the Agent is modeling support byte enables? + // 0 = NO + // 1 = YES + supports_byte_enable = 0; + + // Does the Agent's Driver provide separate response sequence items? + // i.e. Does the driver call seq_item_port.put() + // and do the sequences call get_response()? + // 0 = NO + // 1 = YES + provides_responses = 0; + // pragma uvmf custom new end + + endfunction: new + + //-------------------------------------------------------------------- + // reg2bus + //-------------------------------------------------------------------- + virtual function uvm_sequence_item reg2bus(const ref uvm_reg_bus_op rw); + + wb_s_transaction #( + .WB_ADDR_WIDTH(WB_ADDR_WIDTH), + .WB_DATA_WIDTH(WB_DATA_WIDTH) + ) trans_h = wb_s_transaction #( + .WB_ADDR_WIDTH(WB_ADDR_WIDTH), + .WB_DATA_WIDTH(WB_DATA_WIDTH) + )::type_id::create("trans_h"); + + // pragma uvmf custom reg2bus begin + // UVMF_CHANGE_ME : Fill in the reg2bus adapter mapping registe fields to protocol fields. + + //Adapt the following for your sequence item type + // trans_h.op = (rw.kind == UVM_READ) ? WB_READ : WB_WRITE; + //Copy over address + // trans_h.addr = rw.addr; + //Copy over write data + // trans_h.data = rw.data; + + // pragma uvmf custom reg2bus end + + // Return the adapted transaction + return trans_h; + + endfunction: reg2bus + + //-------------------------------------------------------------------- + // bus2reg + //-------------------------------------------------------------------- + virtual function void bus2reg(uvm_sequence_item bus_item, + ref uvm_reg_bus_op rw); + wb_s_transaction #( + .WB_ADDR_WIDTH(WB_ADDR_WIDTH), + .WB_DATA_WIDTH(WB_DATA_WIDTH) + ) trans_h; + if (!$cast(trans_h, bus_item)) begin + `uvm_fatal("ADAPT","Provided bus_item is not of the correct type") + return; + end + // pragma uvmf custom bus2reg begin + // UVMF_CHANGE_ME : Fill in the bus2reg adapter mapping protocol fields to register fields. + //Adapt the following for your sequence item type + //Copy over instruction type + // rw.kind = (trans_h.op == WB_WRITE) ? UVM_WRITE : UVM_READ; + //Copy over address + // rw.addr = trans_h.addr; + //Copy over read data + // rw.data = trans_h.data; + //Check for errors on the bus and return UVM_NOT_OK if there is an error + // rw.status = UVM_IS_OK; + // pragma uvmf custom bus2reg end + + endfunction: bus2reg + +endclass : wb_s2reg_adapter + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/wb_s_pkg/src/wb_s_agent.svh b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/wb_s_pkg/src/wb_s_agent.svh new file mode 100644 index 00000000..de099f9c --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/wb_s_pkg/src/wb_s_agent.svh @@ -0,0 +1,74 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: Protocol specific agent class definition +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class wb_s_agent #( + int WB_ADDR_WIDTH = 32, + int WB_DATA_WIDTH = 16 + ) extends uvmf_parameterized_agent #( + .CONFIG_T(wb_s_configuration #( + .WB_ADDR_WIDTH(WB_ADDR_WIDTH), + .WB_DATA_WIDTH(WB_DATA_WIDTH) + )), + .DRIVER_T(wb_s_driver #( + .WB_ADDR_WIDTH(WB_ADDR_WIDTH), + .WB_DATA_WIDTH(WB_DATA_WIDTH) + )), + .MONITOR_T(wb_s_monitor #( + .WB_ADDR_WIDTH(WB_ADDR_WIDTH), + .WB_DATA_WIDTH(WB_DATA_WIDTH) + )), + .COVERAGE_T(wb_s_transaction_coverage #( + .WB_ADDR_WIDTH(WB_ADDR_WIDTH), + .WB_DATA_WIDTH(WB_DATA_WIDTH) + )), + .TRANS_T(wb_s_transaction #( + .WB_ADDR_WIDTH(WB_ADDR_WIDTH), + .WB_DATA_WIDTH(WB_DATA_WIDTH) + )) + ); + + `uvm_component_param_utils( wb_s_agent #( + WB_ADDR_WIDTH, + WB_DATA_WIDTH + )) + +// pragma uvmf custom class_item_additional begin +// pragma uvmf custom class_item_additional end + +// **************************************************************************** +// FUNCTION : new() +// This function is the standard SystemVerilog constructor. +// + function new( string name = "", uvm_component parent = null ); + super.new( name, parent ); + endfunction + +// **************************************************************************** + // FUNCTION: build_phase + virtual function void build_phase(uvm_phase phase); +// pragma uvmf custom build_phase_pre_super begin +// pragma uvmf custom build_phase_pre_super end + super.build_phase(phase); + if (configuration.active_passive == ACTIVE) begin + // Place sequencer handle into configuration object + // so that it may be retrieved from configuration + // rather than using uvm_config_db + configuration.sequencer = this.sequencer; + end + endfunction + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/wb_s_pkg/src/wb_s_configuration.svh b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/wb_s_pkg/src/wb_s_configuration.svh new file mode 100644 index 00000000..bb3d38e1 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/wb_s_pkg/src/wb_s_configuration.svh @@ -0,0 +1,203 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This class contains all variables and functions used +// to configure the wb_s agent and its bfm's. It gets the +// bfm's from the uvm_config_db for use by the agent. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class wb_s_configuration #( + int WB_ADDR_WIDTH = 32, + int WB_DATA_WIDTH = 16 + ) extends uvmf_parameterized_agent_configuration_base #( + .DRIVER_BFM_BIND_T(virtual wb_s_driver_bfm #( + .WB_ADDR_WIDTH(WB_ADDR_WIDTH), + .WB_DATA_WIDTH(WB_DATA_WIDTH) + )), + .MONITOR_BFM_BIND_T( virtual wb_s_monitor_bfm #( + .WB_ADDR_WIDTH(WB_ADDR_WIDTH), + .WB_DATA_WIDTH(WB_DATA_WIDTH) + ))); + + `uvm_object_param_utils( wb_s_configuration #( + WB_ADDR_WIDTH, + WB_DATA_WIDTH + )) + + + // Sequencer handle populated by agent + uvm_sequencer #(wb_s_transaction #( + .WB_ADDR_WIDTH(WB_ADDR_WIDTH), + .WB_DATA_WIDTH(WB_DATA_WIDTH) + ) ) sequencer; + + //Constraints for the configuration variables: + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + covergroup wb_s_configuration_cg; + // pragma uvmf custom covergroup begin + option.auto_bin_max=1024; + // pragma uvmf custom covergroup end + endgroup + + //******************************************************************* + //******************************************************************* + // Structure used to pass configuration variables to monitor and driver BFM's. + // Use to_struct function to pack variables into structure. + // Use from_struct function to unpack variables from structure. + // This structure is defined in wb_s_macros.svh + `wb_s_CONFIGURATION_STRUCT + wb_s_configuration_s wb_s_configuration_struct; + //******************************************************************* + // FUNCTION: to_struct() + // This function packs variables into a wb_s_configuration_s + // structure. The function returns the handle to the wb_s_configuration_struct. + // This function is defined in wb_s_macros.svh + `wb_s_CONFIGURATION_TO_STRUCT_FUNCTION + //******************************************************************* + // FUNCTION: from_struct() + // This function unpacks the struct provided as an argument into + // variables of this class. + // This function is defined in wb_s_macros.svh + `wb_s_CONFIGURATION_FROM_STRUCT_FUNCTION + + // **************************************************************************** + // FUNCTION : new() + // This function is the standard SystemVerilog constructor. + // + function new( string name = "" ); + super.new( name ); + // Construct the covergroup for this configuration class + wb_s_configuration_cg = new; + endfunction + + // **************************************************************************** + // FUNCTION: post_randomize() + // This function is automatically called after the randomize() function + // is executed. + // + function void post_randomize(); + super.post_randomize(); + wb_s_configuration_cg.sample(); + endfunction + + // **************************************************************************** + // FUNCTION: initialize + // This function causes the configuration to retrieve + // its virtual interface handle from the uvm_config_db. + // This function also makes itself available to its + // agent through the uvm_config_db. + // + // ARGUMENTS: + // uvmf_active_passive_t activity: + // This argument identifies the simulation level + // as either BLOCK, CHIP, SIMULATION, etc. + // + // AGENT_PATH: + // This argument identifies the path to this + // configurations agent. This configuration + // makes itself available to the agent specified + // by agent_path by placing itself into the + // uvm_config_db. + // + // INTERFACE_NAME: + // This argument identifies the string name of + // this configurations BFM's. This string + // name is used to retrieve the driver and + // monitor BFM from the uvm_config_db. + // + virtual function void initialize(uvmf_active_passive_t activity, + string agent_path, + string interface_name); + + super.initialize( activity, agent_path, interface_name); + // The covergroup is given the same name as the interface + wb_s_configuration_cg.set_inst_name(interface_name); + + // This configuration places itself into the uvm_config_db for the agent, identified by the agent_path variable, to retrieve. + uvm_config_db #( wb_s_configuration #( + .WB_ADDR_WIDTH(WB_ADDR_WIDTH), + .WB_DATA_WIDTH(WB_DATA_WIDTH) + ) + )::set( null ,agent_path,UVMF_AGENT_CONFIG, this ); + + // This configuration also places itself in the config db using the same identifier used by the interface. This allows users to access + // configuration variables and the interface through the bfm api class rather than directly accessing the BFM. This is useful for + // accessingthe BFM when using Veloce + uvm_config_db #( wb_s_configuration #( + .WB_ADDR_WIDTH(WB_ADDR_WIDTH), + .WB_DATA_WIDTH(WB_DATA_WIDTH) + ) + )::set( null ,UVMF_CONFIGURATIONS, interface_name, this ); + + wb_s_configuration_cg.set_inst_name($sformatf("wb_s_configuration_cg_%s",get_full_name())); + +// This code is to aid in debugging parameter mismatches between the BFM and its corresponding agent. +// Enable this debug by setting UVM_VERBOSITY to UVM_DEBUG +// Setting UVM_VERBOSITY to UVM_DEBUG causes all BFM's and all agents to display their parameter settings. +// All of the messages from this feature have a UVM messaging id value of "CFG" +// The transcript or run.log can be parsed to ensure BFM parameter settings match its corresponding agents parameter settings. + `uvm_info("CFG", + $psprintf("The agent at '%s' is using interface named %s has the following parameters: WB_ADDR_WIDTH=%x WB_DATA_WIDTH=%x ", agent_path, interface_name, WB_ADDR_WIDTH ,WB_DATA_WIDTH ), + UVM_DEBUG) + + // pragma uvmf custom initialize begin + // This controls whether or not the agent returns a transaction handle in the driver when calling + // item_done() back into the sequencer or not. If set to 1, a transaction is sent back which means + // the sequence on the other end must use the get_response() part of the driver/sequence API. If + // this doesn't occur, there will eventually be response_queue overflow errors during the test. + return_transaction_response = 1'b0; + + // pragma uvmf custom initialize end + + endfunction + + // **************************************************************************** + // TASK: wait_for_reset + // *[Required]* Blocks until reset is released. The wait_for_reset operation is performed + // by a task in the monitor bfm. + virtual task wait_for_reset(); + monitor_bfm.wait_for_reset(); + endtask + + // **************************************************************************** + // TASK: wait_for_num_clocks + // *[Required]* Blocks until specified number of clocks have elapsed. The wait_for_num_clocks + // operation is performed by a task in the monitor bfm. + virtual task wait_for_num_clocks(int clocks); + monitor_bfm.wait_for_num_clocks(clocks); + endtask + + // **************************************************************************** + // FUNCTION : convert2string() + // This function is used to convert variables in this class into a string for log messaging. + // + virtual function string convert2string (); + // pragma uvmf custom convert2string begin + return $sformatf(""); + // pragma uvmf custom convert2string end + endfunction + + // **************************************************************************** + // FUNCTION: get_sequencer + function uvm_sequencer #(wb_s_transaction#( + .WB_ADDR_WIDTH(WB_ADDR_WIDTH), + .WB_DATA_WIDTH(WB_DATA_WIDTH) + )) get_sequencer(); + return sequencer; + endfunction + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/wb_s_pkg/src/wb_s_driver.svh b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/wb_s_pkg/src/wb_s_driver.svh new file mode 100644 index 00000000..af5bd8e1 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/wb_s_pkg/src/wb_s_driver.svh @@ -0,0 +1,109 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This class passes transactions between the sequencer +// and the BFM driver interface. It accesses the driver BFM +// through the bfm handle. This driver +// passes transactions to the driver BFM through the access +// task. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class wb_s_driver #( + int WB_ADDR_WIDTH = 32, + int WB_DATA_WIDTH = 16 + ) extends uvmf_driver_base #( + .CONFIG_T(wb_s_configuration #( + .WB_ADDR_WIDTH(WB_ADDR_WIDTH), + .WB_DATA_WIDTH(WB_DATA_WIDTH) + ) ), + .BFM_BIND_T(virtual wb_s_driver_bfm #( + .WB_ADDR_WIDTH(WB_ADDR_WIDTH), + .WB_DATA_WIDTH(WB_DATA_WIDTH) + ) ), + .REQ(wb_s_transaction #( + .WB_ADDR_WIDTH(WB_ADDR_WIDTH), + .WB_DATA_WIDTH(WB_DATA_WIDTH) + ) ), + .RSP(wb_s_transaction #( + .WB_ADDR_WIDTH(WB_ADDR_WIDTH), + .WB_DATA_WIDTH(WB_DATA_WIDTH) + ) )); + + `uvm_component_param_utils( wb_s_driver #( + WB_ADDR_WIDTH, + WB_DATA_WIDTH + )) +//******************************************************************* +// Macros that define structs located in wb_s_macros.svh +//******************************************************************* +// Initiator macro used by wb_s_driver and wb_s_driver_bfm +// to communicate initiator driven data to wb_s_driver_bfm. +`wb_s_INITIATOR_STRUCT + wb_s_initiator_s wb_s_initiator_struct; +//******************************************************************* +// Responder macro used by wb_s_driver and wb_s_driver_bfm +// to communicate Responder driven data to wb_s_driver_bfm. +`wb_s_RESPONDER_STRUCT + wb_s_responder_s wb_s_responder_struct; + +// pragma uvmf custom class_item_additional begin +// pragma uvmf custom class_item_additional end + +// **************************************************************************** +// This function is the standard SystemVerilog constructor. +// + function new( string name = "", uvm_component parent=null ); + super.new( name, parent ); + endfunction + +// **************************************************************************** +// This function sends configuration object variables to the driver BFM +// using the configuration struct. +// + virtual function void configure(input CONFIG_T cfg); + bfm.configure( cfg.to_struct() ); + endfunction + +// **************************************************************************** +// This function places a handle to this class in the proxy variable in the +// driver BFM. This allows the driver BFM to call tasks and function within this class. +// + virtual function void set_bfm_proxy_handle(); + bfm.proxy = this; endfunction + +// **************************************************************************** +// This task is called by the run_phase in uvmf_driver_base. + virtual task access( inout REQ txn ); +// pragma uvmf custom access begin + if (configuration.initiator_responder==RESPONDER) begin + // Complete current transfer and wait for next transfer + bfm.respond_and_wait_for_next_transfer( + wb_s_initiator_struct, + txn.to_responder_struct() + ); + // Unpack information about initiated transfer received by this responder + txn.from_initiator_struct(wb_s_initiator_struct); + end else begin + // Initiate a transfer and get response + bfm.initiate_and_get_response( + txn.to_initiator_struct(), + wb_s_responder_struct + ); + // Unpack transfer response information received by this initiator + txn.from_responder_struct(wb_s_responder_struct); + end +// pragma uvmf custom access end + endtask + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/wb_s_pkg/src/wb_s_driver_bfm.sv b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/wb_s_pkg/src/wb_s_driver_bfm.sv new file mode 100644 index 00000000..4acfa6a7 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/wb_s_pkg/src/wb_s_driver_bfm.sv @@ -0,0 +1,347 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: +// This interface performs the wb_s signal driving. It is +// accessed by the uvm wb_s driver through a virtual interface +// handle in the wb_s configuration. It drives the singals passed +// in through the port connection named bus of type wb_s_if. +// +// Input signals from the wb_s_if are assigned to an internal input +// signal with a _i suffix. The _i signal should be used for sampling. +// +// The input signal connections are as follows: +// bus.signal -> signal_i +// +// This bfm drives signals with a _o suffix. These signals +// are driven onto signals within wb_s_if based on INITIATOR/RESPONDER and/or +// ARBITRATION/GRANT status. +// +// The output signal connections are as follows: +// signal_o -> bus.signal +// +// +// Interface functions and tasks used by UVM components: +// +// configure: +// This function gets configuration attributes from the +// UVM driver to set any required BFM configuration +// variables such as 'initiator_responder'. +// +// initiate_and_get_response: +// This task is used to perform signaling activity for initiating +// a protocol transfer. The task initiates the transfer, using +// input data from the initiator struct. Then the task captures +// response data, placing the data into the response struct. +// The response struct is returned to the driver class. +// +// respond_and_wait_for_next_transfer: +// This task is used to complete a current transfer as a responder +// and then wait for the initiator to start the next transfer. +// The task uses data in the responder struct to drive protocol +// signals to complete the transfer. The task then waits for +// the next transfer. Once the next transfer begins, data from +// the initiator is placed into the initiator struct and sent +// to the responder sequence for processing to determine +// what data to respond with. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +import uvmf_base_pkg_hdl::*; +import wb_s_pkg_hdl::*; +`include "src/wb_s_macros.svh" + +interface wb_s_driver_bfm #( + int WB_ADDR_WIDTH = 32, + int WB_DATA_WIDTH = 16 + ) + (wb_s_if bus); + // The following pragma and additional ones in-lined further below are for running this BFM on Veloce + // pragma attribute wb_s_driver_bfm partition_interface_xif + +`ifndef XRTL +// This code is to aid in debugging parameter mismatches between the BFM and its corresponding agent. +// Enable this debug by setting UVM_VERBOSITY to UVM_DEBUG +// Setting UVM_VERBOSITY to UVM_DEBUG causes all BFM's and all agents to display their parameter settings. +// All of the messages from this feature have a UVM messaging id value of "CFG" +// The transcript or run.log can be parsed to ensure BFM parameter settings match its corresponding agents parameter settings. +import uvm_pkg::*; +`include "uvm_macros.svh" +initial begin : bfm_vs_agent_parameter_debug + `uvm_info("CFG", + $psprintf("The BFM at '%m' has the following parameters: WB_ADDR_WIDTH=%x WB_DATA_WIDTH=%x ", WB_ADDR_WIDTH,WB_DATA_WIDTH), + UVM_DEBUG) +end +`endif + + // Config value to determine if this is an initiator or a responder + uvmf_initiator_responder_t initiator_responder; + // Custom configuration variables. + // These are set using the configure function which is called during the UVM connect_phase + + logic clock_i; + logic reset_i; + + // Signal list (all signals are capable of being inputs and outputs for the sake + // of supporting both INITIATOR and RESPONDER mode operation. Expectation is that + // directionality in the config file was from the point-of-view of the INITIATOR + + // INITIATOR mode input signals + tri [WB_DATA_WIDTH-1:0] din_i; + reg [WB_DATA_WIDTH-1:0] din_o = 'b0; + tri [WB_DATA_WIDTH-1:0] TGD_I_i; + reg [WB_DATA_WIDTH-1:0] TGD_I_o = 'bz; + tri [WB_ADDR_WIDTH-1:0] adr_i; + reg [WB_ADDR_WIDTH-1:0] adr_o = 'b0; + tri cyc_i; + reg cyc_o = 0; + tri we_i; + reg we_o = 0; + tri stb_i; + reg stb_o = 0; + tri [WB_DATA_WIDTH/8-1:0] sel_i; + reg [WB_DATA_WIDTH/8-1:0] sel_o = 'b0; + + // INITIATOR mode output signals + tri [WB_DATA_WIDTH-1:0] dout_i; + reg [WB_DATA_WIDTH-1:0] dout_o = 'b0; + tri [WB_DATA_WIDTH-1:0] TGD_O_i; + reg [WB_DATA_WIDTH-1:0] TGD_O_o = 'bz; + tri ack_i; + reg ack_o = 'b0; + tri err_i; + reg err_o = 'b0; + + // Bi-directional signals + + + assign clock_i = bus.clock; + assign reset_i = bus.reset; + + // These are signals marked as 'input' by the config file, but the signals will be + // driven by this BFM if put into RESPONDER mode (flipping all signal directions around) + assign din_i = bus.din; + assign bus.din = (initiator_responder == RESPONDER) ? din_o : 'bz; + assign TGD_I_i = bus.TGD_I; + assign bus.TGD_I = (initiator_responder == RESPONDER) ? TGD_I_o : 'bz; + assign adr_i = bus.adr; + assign bus.adr = (initiator_responder == RESPONDER) ? adr_o : 'bz; + assign cyc_i = bus.cyc; + assign bus.cyc = (initiator_responder == RESPONDER) ? cyc_o : 'bz; + assign we_i = bus.we; + assign bus.we = (initiator_responder == RESPONDER) ? we_o : 'bz; + assign stb_i = bus.stb; + assign bus.stb = (initiator_responder == RESPONDER) ? stb_o : 'bz; + assign sel_i = bus.sel; + assign bus.sel = (initiator_responder == RESPONDER) ? sel_o : 'bz; + + + // These are signals marked as 'output' by the config file, but the outputs will + // not be driven by this BFM unless placed in INITIATOR mode. + assign bus.dout = (initiator_responder == INITIATOR) ? dout_o : 'bz; + assign dout_i = bus.dout; + assign bus.TGD_O = (initiator_responder == INITIATOR) ? TGD_O_o : 'bz; + assign TGD_O_i = bus.TGD_O; + assign bus.ack = (initiator_responder == INITIATOR) ? ack_o : 'bz; + assign ack_i = bus.ack; + assign bus.err = (initiator_responder == INITIATOR) ? err_o : 'bz; + assign err_i = bus.err; + + // Proxy handle to UVM driver + wb_s_pkg::wb_s_driver #( + .WB_ADDR_WIDTH(WB_ADDR_WIDTH), + .WB_DATA_WIDTH(WB_DATA_WIDTH) + ) proxy; + // pragma tbx oneway proxy.my_function_name_in_uvm_driver + + // **************************************************************************** + // **************************************************************************** + // Macros that define structs located in wb_s_macros.svh + // **************************************************************************** + // Struct for passing configuration data from wb_s_driver to this BFM + // **************************************************************************** + `wb_s_CONFIGURATION_STRUCT + // **************************************************************************** + // Structs for INITIATOR and RESPONDER data flow + //******************************************************************* + // Initiator macro used by wb_s_driver and wb_s_driver_bfm + // to communicate initiator driven data to wb_s_driver_bfm. + `wb_s_INITIATOR_STRUCT + wb_s_initiator_s initiator_struct; + // Responder macro used by wb_s_driver and wb_s_driver_bfm + // to communicate Responder driven data to wb_s_driver_bfm. + `wb_s_RESPONDER_STRUCT + wb_s_responder_s responder_struct; + + // **************************************************************************** +// pragma uvmf custom reset_condition_and_response begin + // Always block used to return signals to reset value upon assertion of reset + always @( posedge reset_i ) + begin + // RESPONDER mode output signals + din_o <= 'b0; + TGD_I_o <= 'bz; + adr_o <= 'b0; + cyc_o <= 0; + we_o <= 0; + stb_o <= 0; + sel_o <= 'b0; + // INITIATOR mode output signals + dout_o <= 'b0; + TGD_O_o <= 'bz; + ack_o <= 'b0; + err_o <= 'b0; + // Bi-directional signals + + end +// pragma uvmf custom reset_condition_and_response end + + // pragma uvmf custom interface_item_additional begin + // pragma uvmf custom interface_item_additional end + + //****************************************************************** + // The configure() function is used to pass agent configuration + // variables to the driver BFM. It is called by the driver within + // the agent at the beginning of the simulation. It may be called + // during the simulation if agent configuration variables are updated + // and the driver BFM needs to be aware of the new configuration + // variables. + // + + function void configure(wb_s_configuration_s wb_s_configuration_arg); // pragma tbx xtf + initiator_responder = wb_s_configuration_arg.initiator_responder; + // pragma uvmf custom configure begin + // pragma uvmf custom configure end + endfunction + +// pragma uvmf custom initiate_and_get_response begin +// **************************************************************************** +// UVMF_CHANGE_ME +// This task is used by an initator. The task first initiates a transfer then +// waits for the responder to complete the transfer. + task initiate_and_get_response( + // This argument passes transaction variables used by an initiator + // to perform the initial part of a protocol transfer. The values + // come from a sequence item created in a sequence. + input wb_s_initiator_s wb_s_initiator_struct, + // This argument is used to send data received from the responder + // back to the sequence item. The sequence item is returned to the sequence. + output wb_s_responder_s wb_s_responder_struct + );// pragma tbx xtf + // + // Members within the wb_s_initiator_struct: + // bit [WB_DATA_WIDTH-1:0] data ; + // Members within the wb_s_responder_struct: + // bit [WB_DATA_WIDTH-1:0] data ; + initiator_struct = wb_s_initiator_struct; + // + // Reference code; + // How to wait for signal value + // while (control_signal == 1'b1) @(posedge clock_i); + // + // How to assign a responder struct member, named xyz, from a signal. + // All available initiator input and inout signals listed. + // Initiator input signals + // wb_s_responder_struct.xyz = din_i; // [WB_DATA_WIDTH-1:0] + // wb_s_responder_struct.xyz = TGD_I_i; // [WB_DATA_WIDTH-1:0] + // wb_s_responder_struct.xyz = adr_i; // [WB_ADDR_WIDTH-1:0] + // wb_s_responder_struct.xyz = cyc_i; // + // wb_s_responder_struct.xyz = we_i; // + // wb_s_responder_struct.xyz = stb_i; // + // wb_s_responder_struct.xyz = sel_i; // [WB_DATA_WIDTH/8-1:0] + // Initiator inout signals + // How to assign a signal from an initiator struct member named xyz. + // All available initiator output and inout signals listed. + // Notice the _o. Those are storage variables that allow for procedural assignment. + // Initiator output signals + // dout_o <= wb_s_initiator_struct.xyz; // [WB_DATA_WIDTH-1:0] + // TGD_O_o <= wb_s_initiator_struct.xyz; // [WB_DATA_WIDTH-1:0] + // ack_o <= wb_s_initiator_struct.xyz; // + // err_o <= wb_s_initiator_struct.xyz; // + // Initiator inout signals + // Initiate a transfer using the data received. + @(posedge clock_i); + @(posedge clock_i); + // Wait for the responder to complete the transfer then place the responder data into + // wb_s_responder_struct. + @(posedge clock_i); + @(posedge clock_i); + responder_struct = wb_s_responder_struct; + endtask +// pragma uvmf custom initiate_and_get_response end + +// pragma uvmf custom respond_and_wait_for_next_transfer begin +// **************************************************************************** +// The first_transfer variable is used to prevent completing a transfer in the +// first call to this task. For the first call to this task, there is not +// current transfer to complete. +bit first_transfer=1; + +// UVMF_CHANGE_ME +// This task is used by a responder. The task first completes the current +// transfer in progress then waits for the initiator to start the next transfer. + task respond_and_wait_for_next_transfer( + // This argument is used to send data received from the initiator + // back to the sequence item. The sequence determines how to respond. + output wb_s_initiator_s wb_s_initiator_struct, + // This argument passes transaction variables used by a responder + // to complete a protocol transfer. The values come from a sequence item. + input wb_s_responder_s wb_s_responder_struct + );// pragma tbx xtf + // Variables within the wb_s_initiator_struct: + // bit [WB_DATA_WIDTH-1:0] data ; + // Variables within the wb_s_responder_struct: + // bit [WB_DATA_WIDTH-1:0] data ; + // Reference code; + // How to wait for signal value + // while (control_signal == 1'b1) @(posedge clock_i); + // + // How to assign a responder struct member, named xyz, from a signal. + // All available responder input and inout signals listed. + // Responder input signals + // wb_s_responder_struct.xyz = dout_i; // [WB_DATA_WIDTH-1:0] + // wb_s_responder_struct.xyz = TGD_O_i; // [WB_DATA_WIDTH-1:0] + // wb_s_responder_struct.xyz = ack_i; // + // wb_s_responder_struct.xyz = err_i; // + // Responder inout signals + // How to assign a signal, named xyz, from an initiator struct member. + // All available responder output and inout signals listed. + // Notice the _o. Those are storage variables that allow for procedural assignment. + // Responder output signals + // din_o <= wb_s_initiator_struct.xyz; // [WB_DATA_WIDTH-1:0] + // TGD_I_o <= wb_s_initiator_struct.xyz; // [WB_DATA_WIDTH-1:0] + // adr_o <= wb_s_initiator_struct.xyz; // [WB_ADDR_WIDTH-1:0] + // cyc_o <= wb_s_initiator_struct.xyz; // + // we_o <= wb_s_initiator_struct.xyz; // + // stb_o <= wb_s_initiator_struct.xyz; // + // sel_o <= wb_s_initiator_struct.xyz; // [WB_DATA_WIDTH/8-1:0] + // Responder inout signals + + @(posedge clock_i); + if (!first_transfer) begin + // Perform transfer response here. + // Reply using data recieved in the wb_s_responder_struct. + @(posedge clock_i); + // Reply using data recieved in the transaction handle. + @(posedge clock_i); + end + // Wait for next transfer then gather info from intiator about the transfer. + // Place the data into the wb_s_initiator_struct. + @(posedge clock_i); + @(posedge clock_i); + first_transfer = 0; + endtask +// pragma uvmf custom respond_and_wait_for_next_transfer end + + +endinterface + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/wb_s_pkg/src/wb_s_if.sv b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/wb_s_pkg/src/wb_s_if.sv new file mode 100644 index 00000000..98000bcc --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/wb_s_pkg/src/wb_s_if.sv @@ -0,0 +1,117 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This interface contains the wb_s interface signals. +// It is instantiated once per wb_s bus. Bus Functional Models, +// BFM's named wb_s_driver_bfm, are used to drive signals on the bus. +// BFM's named wb_s_monitor_bfm are used to monitor signals on the +// bus. This interface signal bundle is passed in the port list of +// the BFM in order to give the BFM access to the signals in this +// interface. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// This template can be used to connect a DUT to these signals +// +// .dut_signal_port(wb_s_bus.din), // Agent input +// .dut_signal_port(wb_s_bus.dout), // Agent output +// .dut_signal_port(wb_s_bus.TGD_I), // Agent input +// .dut_signal_port(wb_s_bus.TGD_O), // Agent output +// .dut_signal_port(wb_s_bus.ack), // Agent output +// .dut_signal_port(wb_s_bus.adr), // Agent input +// .dut_signal_port(wb_s_bus.cyc), // Agent input +// .dut_signal_port(wb_s_bus.err), // Agent output +// .dut_signal_port(wb_s_bus.we), // Agent input +// .dut_signal_port(wb_s_bus.stb), // Agent input +// .dut_signal_port(wb_s_bus.sel), // Agent input + +import uvmf_base_pkg_hdl::*; +import wb_s_pkg_hdl::*; + +interface wb_s_if #( + int WB_ADDR_WIDTH = 32, + int WB_DATA_WIDTH = 16 + ) + + ( + input logic clock, + input logic reset, + input logic [WB_DATA_WIDTH-1:0] din, + output logic [WB_DATA_WIDTH-1:0] dout, + input logic [WB_DATA_WIDTH-1:0] TGD_I, + output logic [WB_DATA_WIDTH-1:0] TGD_O, + output logic ack, + input logic [WB_ADDR_WIDTH-1:0] adr, + input logic cyc, + output logic err, + input logic we, + input logic stb, + input logic [WB_DATA_WIDTH/8-1:0] sel + ); + +modport monitor_port + ( + input clock, + input reset, + input din, + input dout, + input TGD_I, + input TGD_O, + input ack, + input adr, + input cyc, + input err, + input we, + input stb, + input sel + ); + +modport initiator_port + ( + input clock, + input reset, + input din, + output dout, + input TGD_I, + output TGD_O, + output ack, + input adr, + input cyc, + output err, + input we, + input stb, + input sel + ); + +modport responder_port + ( + input clock, + input reset, + output din, + input dout, + output TGD_I, + input TGD_O, + input ack, + output adr, + output cyc, + input err, + output we, + output stb, + output sel + ); + + +// pragma uvmf custom interface_item_additional begin +// pragma uvmf custom interface_item_additional end + +endinterface + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/wb_s_pkg/src/wb_s_infact_coverage_strategy.csv b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/wb_s_pkg/src/wb_s_infact_coverage_strategy.csv new file mode 100644 index 00000000..1c218e14 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/wb_s_pkg/src/wb_s_infact_coverage_strategy.csv @@ -0,0 +1,6 @@ +Global +auto_bin_max, 64 + +Name,Type,Include +rand_fields,coverpoint,=rand *.** + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/wb_s_pkg/src/wb_s_macros.svh b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/wb_s_pkg/src/wb_s_macros.svh new file mode 100644 index 00000000..5758385f --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/wb_s_pkg/src/wb_s_macros.svh @@ -0,0 +1,121 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This file contains macros used with the wb_s package. +// These macros include packed struct definitions. These structs are +// used to pass data between classes, hvl, and BFM's, hdl. Use of +// structs are more efficient and simpler to modify. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// + +// **************************************************************************** +// When changing the contents of this struct, be sure to update the to_struct +// and from_struct methods defined in the macros below that are used in +// the wb_s_configuration class. +// + `define wb_s_CONFIGURATION_STRUCT \ +typedef struct packed { \ + uvmf_active_passive_t active_passive; \ + uvmf_initiator_responder_t initiator_responder; \ + } wb_s_configuration_s; + + `define wb_s_CONFIGURATION_TO_STRUCT_FUNCTION \ + virtual function wb_s_configuration_s to_struct();\ + wb_s_configuration_struct = \ + {\ + this.active_passive,\ + this.initiator_responder\ + };\ + return ( wb_s_configuration_struct );\ + endfunction + + `define wb_s_CONFIGURATION_FROM_STRUCT_FUNCTION \ + virtual function void from_struct(wb_s_configuration_s wb_s_configuration_struct);\ + {\ + this.active_passive,\ + this.initiator_responder \ + } = wb_s_configuration_struct;\ + endfunction + +// **************************************************************************** +// When changing the contents of this struct, be sure to update the to_monitor_struct +// and from_monitor_struct methods of the wb_s_transaction class. +// + `define wb_s_MONITOR_STRUCT typedef struct packed { \ + bit [WB_DATA_WIDTH-1:0] data ; \ + } wb_s_monitor_s; + + `define wb_s_TO_MONITOR_STRUCT_FUNCTION \ + virtual function wb_s_monitor_s to_monitor_struct();\ + wb_s_monitor_struct = \ + { \ + this.data \ + };\ + return ( wb_s_monitor_struct);\ + endfunction\ + + `define wb_s_FROM_MONITOR_STRUCT_FUNCTION \ + virtual function void from_monitor_struct(wb_s_monitor_s wb_s_monitor_struct);\ + {\ + this.data \ + } = wb_s_monitor_struct;\ + endfunction + +// **************************************************************************** +// When changing the contents of this struct, be sure to update the to_initiator_struct +// and from_initiator_struct methods of the wb_s_transaction class. +// Also update the comments in the driver BFM. +// + `define wb_s_INITIATOR_STRUCT typedef struct packed { \ + bit [WB_DATA_WIDTH-1:0] data ; \ + } wb_s_initiator_s; + + `define wb_s_TO_INITIATOR_STRUCT_FUNCTION \ + virtual function wb_s_initiator_s to_initiator_struct();\ + wb_s_initiator_struct = \ + {\ + this.data \ + };\ + return ( wb_s_initiator_struct);\ + endfunction + + `define wb_s_FROM_INITIATOR_STRUCT_FUNCTION \ + virtual function void from_initiator_struct(wb_s_initiator_s wb_s_initiator_struct);\ + {\ + this.data \ + } = wb_s_initiator_struct;\ + endfunction + +// **************************************************************************** +// When changing the contents of this struct, be sure to update the to_responder_struct +// and from_responder_struct methods of the wb_s_transaction class. +// Also update the comments in the driver BFM. +// + `define wb_s_RESPONDER_STRUCT typedef struct packed { \ + bit [WB_DATA_WIDTH-1:0] data ; \ + } wb_s_responder_s; + + `define wb_s_TO_RESPONDER_STRUCT_FUNCTION \ + virtual function wb_s_responder_s to_responder_struct();\ + wb_s_responder_struct = \ + {\ + this.data \ + };\ + return ( wb_s_responder_struct);\ + endfunction + + `define wb_s_FROM_RESPONDER_STRUCT_FUNCTION \ + virtual function void from_responder_struct(wb_s_responder_s wb_s_responder_struct);\ + {\ + this.data \ + } = wb_s_responder_struct;\ + endfunction +// pragma uvmf custom additional begin +// pragma uvmf custom additional end diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/wb_s_pkg/src/wb_s_monitor.svh b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/wb_s_pkg/src/wb_s_monitor.svh new file mode 100644 index 00000000..904d0a5b --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/wb_s_pkg/src/wb_s_monitor.svh @@ -0,0 +1,102 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This class receives wb_s transactions observed by the +// wb_s monitor BFM and broadcasts them through the analysis port +// on the agent. It accesses the monitor BFM through the monitor +// task. This UVM component captures transactions +// for viewing in the waveform viewer if the +// enable_transaction_viewing flag is set in the configuration. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class wb_s_monitor #( + int WB_ADDR_WIDTH = 32, + int WB_DATA_WIDTH = 16 + ) extends uvmf_monitor_base #( + .CONFIG_T(wb_s_configuration #( + .WB_ADDR_WIDTH(WB_ADDR_WIDTH), + .WB_DATA_WIDTH(WB_DATA_WIDTH) + )), + .BFM_BIND_T(virtual wb_s_monitor_bfm #( + .WB_ADDR_WIDTH(WB_ADDR_WIDTH), + .WB_DATA_WIDTH(WB_DATA_WIDTH) + )), + .TRANS_T(wb_s_transaction #( + .WB_ADDR_WIDTH(WB_ADDR_WIDTH), + .WB_DATA_WIDTH(WB_DATA_WIDTH) + ))); + + `uvm_component_param_utils( wb_s_monitor #( + WB_ADDR_WIDTH, + WB_DATA_WIDTH + )) + +// Structure used to pass data from monitor BFM to monitor class in agent. +// Use to_monitor_struct function to pack transaction variables into structure. +// Use from_monitor_struct function to unpack transaction variables from structure. +`wb_s_MONITOR_STRUCT + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + +// **************************************************************************** +// This function is the standard SystemVerilog constructor. +// + function new( string name = "", uvm_component parent = null ); + super.new( name, parent ); + endfunction + +// **************************************************************************** +// This function sends configuration object variables to the monitor BFM +// using the configuration struct. +// + virtual function void configure(input CONFIG_T cfg); + bfm.configure( cfg.to_struct() ); + + endfunction + +// **************************************************************************** +// This function places a handle to this class in the proxy variable in the +// monitor BFM. This allows the monitor BFM to call the notify_transaction +// function within this class. +// + virtual function void set_bfm_proxy_handle(); + bfm.proxy = this; endfunction + +// *************************************************************************** + virtual task run_phase(uvm_phase phase); + // Start monitor BFM thread and don't call super.run() in order to + // override the default monitor proxy 'pull' behavior with the more + // emulation-friendly BFM 'push' approach using the notify_transaction + // function below + bfm.start_monitoring(); + endtask + +// ************************************************************************** + +// This function is called by the monitor BFM. It receives data observed by the +// monitor BFM. Data is passed using the wb_s_monitor_struct. + virtual function void notify_transaction(input wb_s_monitor_s wb_s_monitor_struct); + + + trans = new("trans"); + trans.from_monitor_struct(wb_s_monitor_struct); + trans.start_time = time_stamp; + trans.end_time = $time; + time_stamp = trans.end_time; + + analyze(trans); + endfunction + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/wb_s_pkg/src/wb_s_monitor_bfm.sv b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/wb_s_pkg/src/wb_s_monitor_bfm.sv new file mode 100644 index 00000000..fa19c337 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/wb_s_pkg/src/wb_s_monitor_bfm.sv @@ -0,0 +1,210 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This interface performs the wb_s signal monitoring. +// It is accessed by the uvm wb_s monitor through a virtual +// interface handle in the wb_s configuration. It monitors the +// signals passed in through the port connection named bus of +// type wb_s_if. +// +// Input signals from the wb_s_if are assigned to an internal input +// signal with a _i suffix. The _i signal should be used for sampling. +// +// The input signal connections are as follows: +// bus.signal -> signal_i +// +// Interface functions and tasks used by UVM components: +// monitor(inout TRANS_T txn); +// This task receives the transaction, txn, from the +// UVM monitor and then populates variables in txn +// from values observed on bus activity. This task +// blocks until an operation on the wb_s bus is complete. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +import uvmf_base_pkg_hdl::*; +import wb_s_pkg_hdl::*; +`include "src/wb_s_macros.svh" + + +interface wb_s_monitor_bfm #( + int WB_ADDR_WIDTH = 32, + int WB_DATA_WIDTH = 16 + ) + ( wb_s_if bus ); + // The pragma below and additional ones in-lined further down are for running this BFM on Veloce + // pragma attribute wb_s_monitor_bfm partition_interface_xif + +`ifndef XRTL +// This code is to aid in debugging parameter mismatches between the BFM and its corresponding agent. +// Enable this debug by setting UVM_VERBOSITY to UVM_DEBUG +// Setting UVM_VERBOSITY to UVM_DEBUG causes all BFM's and all agents to display their parameter settings. +// All of the messages from this feature have a UVM messaging id value of "CFG" +// The transcript or run.log can be parsed to ensure BFM parameter settings match its corresponding agents parameter settings. +import uvm_pkg::*; +`include "uvm_macros.svh" +initial begin : bfm_vs_agent_parameter_debug + `uvm_info("CFG", + $psprintf("The BFM at '%m' has the following parameters: WB_ADDR_WIDTH=%x WB_DATA_WIDTH=%x ", WB_ADDR_WIDTH,WB_DATA_WIDTH), + UVM_DEBUG) +end +`endif + + + // Structure used to pass transaction data from monitor BFM to monitor class in agent. +`wb_s_MONITOR_STRUCT + wb_s_monitor_s wb_s_monitor_struct; + + // Structure used to pass configuration data from monitor class to monitor BFM. + `wb_s_CONFIGURATION_STRUCT + + + // Config value to determine if this is an initiator or a responder + uvmf_initiator_responder_t initiator_responder; + // Custom configuration variables. + // These are set using the configure function which is called during the UVM connect_phase + + logic clock_i; + logic reset_i; + tri [WB_DATA_WIDTH-1:0] din_i; + tri [WB_DATA_WIDTH-1:0] dout_i; + tri [WB_DATA_WIDTH-1:0] TGD_I_i; + tri [WB_DATA_WIDTH-1:0] TGD_O_i; + tri ack_i; + tri [WB_ADDR_WIDTH-1:0] adr_i; + tri cyc_i; + tri err_i; + tri we_i; + tri stb_i; + tri [WB_DATA_WIDTH/8-1:0] sel_i; + assign clock_i = bus.clock; + assign reset_i = bus.reset; + assign din_i = bus.din; + assign dout_i = bus.dout; + assign TGD_I_i = bus.TGD_I; + assign TGD_O_i = bus.TGD_O; + assign ack_i = bus.ack; + assign adr_i = bus.adr; + assign cyc_i = bus.cyc; + assign err_i = bus.err; + assign we_i = bus.we; + assign stb_i = bus.stb; + assign sel_i = bus.sel; + + // Proxy handle to UVM monitor + wb_s_pkg::wb_s_monitor #( + .WB_ADDR_WIDTH(WB_ADDR_WIDTH), + .WB_DATA_WIDTH(WB_DATA_WIDTH) + ) proxy; + // pragma tbx oneway proxy.notify_transaction + + // pragma uvmf custom interface_item_additional begin + // pragma uvmf custom interface_item_additional end + + //****************************************************************** + task wait_for_reset();// pragma tbx xtf + @(posedge clock_i) ; + do_wait_for_reset(); + endtask + + // **************************************************************************** + task do_wait_for_reset(); + // pragma uvmf custom reset_condition begin + wait ( reset_i === 0 ) ; + @(posedge clock_i) ; + // pragma uvmf custom reset_condition end + endtask + + //****************************************************************** + + task wait_for_num_clocks(input int unsigned count); // pragma tbx xtf + @(posedge clock_i); + + repeat (count-1) @(posedge clock_i); + endtask + + //****************************************************************** + event go; + function void start_monitoring();// pragma tbx xtf + -> go; + endfunction + + // **************************************************************************** + initial begin + @go; + forever begin + @(posedge clock_i); + do_monitor( wb_s_monitor_struct ); + + + proxy.notify_transaction( wb_s_monitor_struct ); + + end + end + + //****************************************************************** + // The configure() function is used to pass agent configuration + // variables to the monitor BFM. It is called by the monitor within + // the agent at the beginning of the simulation. It may be called + // during the simulation if agent configuration variables are updated + // and the monitor BFM needs to be aware of the new configuration + // variables. + // + function void configure(wb_s_configuration_s wb_s_configuration_arg); // pragma tbx xtf + initiator_responder = wb_s_configuration_arg.initiator_responder; + // pragma uvmf custom configure begin + // pragma uvmf custom configure end + endfunction + + + // **************************************************************************** + + task do_monitor(output wb_s_monitor_s wb_s_monitor_struct); + // + // Available struct members: + // // wb_s_monitor_struct.data + // // + // Reference code; + // How to wait for signal value + // while (control_signal === 1'b1) @(posedge clock_i); + // + // How to assign a struct member, named xyz, from a signal. + // All available input signals listed. + // wb_s_monitor_struct.xyz = din_i; // [WB_DATA_WIDTH-1:0] + // wb_s_monitor_struct.xyz = dout_i; // [WB_DATA_WIDTH-1:0] + // wb_s_monitor_struct.xyz = TGD_I_i; // [WB_DATA_WIDTH-1:0] + // wb_s_monitor_struct.xyz = TGD_O_i; // [WB_DATA_WIDTH-1:0] + // wb_s_monitor_struct.xyz = ack_i; // + // wb_s_monitor_struct.xyz = adr_i; // [WB_ADDR_WIDTH-1:0] + // wb_s_monitor_struct.xyz = cyc_i; // + // wb_s_monitor_struct.xyz = err_i; // + // wb_s_monitor_struct.xyz = we_i; // + // wb_s_monitor_struct.xyz = stb_i; // + // wb_s_monitor_struct.xyz = sel_i; // [WB_DATA_WIDTH/8-1:0] + // pragma uvmf custom do_monitor begin + // UVMF_CHANGE_ME : Implement protocol monitoring. The commented reference code + // below are examples of how to capture signal values and assign them to + // structure members. All available input signals are listed. The 'while' + // code example shows how to wait for a synchronous flow control signal. This + // task should return when a complete transfer has been observed. Once this task is + // exited with captured values, it is then called again to wait for and observe + // the next transfer. One clock cycle is consumed between calls to do_monitor. + @(posedge clock_i); + @(posedge clock_i); + @(posedge clock_i); + @(posedge clock_i); + // pragma uvmf custom do_monitor end + endtask + + +endinterface + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/wb_s_pkg/src/wb_s_random_sequence.svh b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/wb_s_pkg/src/wb_s_random_sequence.svh new file mode 100644 index 00000000..92df7b61 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/wb_s_pkg/src/wb_s_random_sequence.svh @@ -0,0 +1,65 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: +// This sequences randomizes the wb_s transaction and sends it +// to the UVM driver. +// +// This sequence constructs and randomizes a wb_s_transaction. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class wb_s_random_sequence #( + int WB_ADDR_WIDTH = 32, + int WB_DATA_WIDTH = 16 + ) + extends wb_s_sequence_base #( + .WB_ADDR_WIDTH(WB_ADDR_WIDTH), + .WB_DATA_WIDTH(WB_DATA_WIDTH) + ); + + `uvm_object_param_utils( wb_s_random_sequence #( + WB_ADDR_WIDTH, + WB_DATA_WIDTH + )) + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + //***************************************************************** + function new(string name = ""); + super.new(name); + endfunction: new + + // **************************************************************************** + // TASK : body() + // This task is automatically executed when this sequence is started using the + // start(sequencerHandle) task. + // + task body(); + + // Construct the transaction + req=wb_s_transaction#( + .WB_ADDR_WIDTH(WB_ADDR_WIDTH), + .WB_DATA_WIDTH(WB_DATA_WIDTH) + )::type_id::create("req"); + start_item(req); + // Randomize the transaction + if(!req.randomize()) `uvm_fatal("SEQ", "wb_s_random_sequence::body()-wb_s_transaction randomization failed") + // Send the transaction to the wb_s_driver_bfm via the sequencer and wb_s_driver. + finish_item(req); + `uvm_info("SEQ", {"Response:",req.convert2string()},UVM_MEDIUM) + + endtask + +endclass: wb_s_random_sequence + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/wb_s_pkg/src/wb_s_responder_sequence.svh b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/wb_s_pkg/src/wb_s_responder_sequence.svh new file mode 100644 index 00000000..730ec16e --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/wb_s_pkg/src/wb_s_responder_sequence.svh @@ -0,0 +1,61 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This class can be used to provide stimulus when an interface +// has been configured to run in a responder mode. It +// will never finish by default, always going back to the driver +// and driver BFM for the next transaction with which to respond. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class wb_s_responder_sequence #( + int WB_ADDR_WIDTH = 32, + int WB_DATA_WIDTH = 16 + ) + extends wb_s_sequence_base #( + .WB_ADDR_WIDTH(WB_ADDR_WIDTH), + .WB_DATA_WIDTH(WB_DATA_WIDTH) + ); + + `uvm_object_param_utils( wb_s_responder_sequence #( + WB_ADDR_WIDTH, + WB_DATA_WIDTH + )) + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + function new(string name = "wb_s_responder_sequence"); + super.new(name); + endfunction + + task body(); + req=wb_s_transaction#( + .WB_ADDR_WIDTH(WB_ADDR_WIDTH), + .WB_DATA_WIDTH(WB_DATA_WIDTH) + )::type_id::create("req"); + forever begin + start_item(req); + finish_item(req); + // pragma uvmf custom body begin + // UVMF_CHANGE_ME : Do something here with the resulting req item. The + // finish_item() call above will block until the req transaction is ready + // to be handled by the responder sequence. + // If this was an item that required a response, the expectation is + // that the response should be populated within this transaction now. + `uvm_info("SEQ",$sformatf("Processed txn: %s",req.convert2string()),UVM_HIGH) + // pragma uvmf custom body end + end + endtask + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/wb_s_pkg/src/wb_s_sequence_base.svh b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/wb_s_pkg/src/wb_s_sequence_base.svh new file mode 100644 index 00000000..78d29786 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/wb_s_pkg/src/wb_s_sequence_base.svh @@ -0,0 +1,114 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: +// This file contains the class used as the base class for all sequences +// for this interface. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class wb_s_sequence_base #( + int WB_ADDR_WIDTH = 32, + int WB_DATA_WIDTH = 16 + ) extends uvmf_sequence_base #( + .REQ(wb_s_transaction #( + .WB_ADDR_WIDTH(WB_ADDR_WIDTH), + .WB_DATA_WIDTH(WB_DATA_WIDTH) + )), + .RSP(wb_s_transaction #( + .WB_ADDR_WIDTH(WB_ADDR_WIDTH), + .WB_DATA_WIDTH(WB_DATA_WIDTH) + ))); + + `uvm_object_param_utils( wb_s_sequence_base #( + WB_ADDR_WIDTH, + WB_DATA_WIDTH + )) + + // variables + typedef wb_s_transaction #( + .WB_ADDR_WIDTH(WB_ADDR_WIDTH), + .WB_DATA_WIDTH(WB_DATA_WIDTH) + ) wb_s_transaction_req_t; + wb_s_transaction_req_t req; + typedef wb_s_transaction #( + .WB_ADDR_WIDTH(WB_ADDR_WIDTH), + .WB_DATA_WIDTH(WB_DATA_WIDTH) + ) wb_s_transaction_rsp_t; + wb_s_transaction_rsp_t rsp; + + // Event for identifying when a response was received from the sequencer + event new_rsp; + + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + // **************************************************************************** + // TASK : get_responses() + // This task recursively gets sequence item responses from the sequencer. + // + virtual task get_responses(); + fork + begin + // Block until new rsp available + get_response(rsp); + // New rsp received. Indicate to sequence using event. + ->new_rsp; + // Display the received response transaction + `uvm_info("SEQ", {"New response transaction:",rsp.convert2string()}, UVM_MEDIUM) + end + join_none + endtask + + // **************************************************************************** + // TASK : pre_body() + // This task is called automatically when start is called with call_pre_post set to 1 (default). + // By calling get_responses() within pre_body() any derived sequences are automatically + // processing response transactions. Only un-comment this call to get_responses() if you + // have configured the interface driver to utilize the response transaction path by setting + // the configuration variable "return_transaction_response" to 1. Otherwise it is possible + // to impact runtime performance and memory utilization. + // + virtual task pre_body(); + // pragma uvmf custom pre_body begin +// get_responses(); + // pragma uvmf custom pre_body end + endtask + + // **************************************************************************** + // TASK : body() + // This task is called automatically when start is called. This sequence sends + // a req sequence item to the sequencer identified as an argument in the call + // to start. + // + virtual task body(); + // pragma uvmf custom body begin + start_item(req); + finish_item(req); + // pragma uvmf custom body end + endtask + + // **************************************************************************** + // FUNCTION : new() + // This function is the standard SystemVerilog constructor. + // + function new( string name =""); + super.new( name ); + // pragma uvmf custom new begin + req = wb_s_transaction_req_t::type_id::create("req"); + rsp = wb_s_transaction_rsp_t::type_id::create("rsp"); + // pragma uvmf custom new end + endfunction + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/wb_s_pkg/src/wb_s_transaction.svh b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/wb_s_pkg/src/wb_s_transaction.svh new file mode 100644 index 00000000..7548f786 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/wb_s_pkg/src/wb_s_transaction.svh @@ -0,0 +1,194 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This class defines the variables required for an wb_s +// transaction. Class variables to be displayed in waveform transaction +// viewing are added to the transaction viewing stream in the add_to_wave +// function. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class wb_s_transaction #( + int WB_ADDR_WIDTH = 32, + int WB_DATA_WIDTH = 16 + ) extends uvmf_transaction_base; + + `uvm_object_param_utils( wb_s_transaction #( + WB_ADDR_WIDTH, + WB_DATA_WIDTH + )) + + rand bit [WB_DATA_WIDTH-1:0] data ; + + //Constraints for the transaction variables: + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + //******************************************************************* + //******************************************************************* + // Macros that define structs and associated functions are + // located in wb_s_macros.svh + + //******************************************************************* + // Monitor macro used by wb_s_monitor and wb_s_monitor_bfm + // This struct is defined in wb_s_macros.svh + `wb_s_MONITOR_STRUCT + wb_s_monitor_s wb_s_monitor_struct; + //******************************************************************* + // FUNCTION: to_monitor_struct() + // This function packs transaction variables into a wb_s_monitor_s + // structure. The function returns the handle to the wb_s_monitor_struct. + // This function is defined in wb_s_macros.svh + `wb_s_TO_MONITOR_STRUCT_FUNCTION + //******************************************************************* + // FUNCTION: from_monitor_struct() + // This function unpacks the struct provided as an argument into transaction + // variables of this class. + // This function is defined in wb_s_macros.svh + `wb_s_FROM_MONITOR_STRUCT_FUNCTION + + //******************************************************************* + // Initiator macro used by wb_s_driver and wb_s_driver_bfm + // to communicate initiator driven data to wb_s_driver_bfm. + // This struct is defined in wb_s_macros.svh + `wb_s_INITIATOR_STRUCT + wb_s_initiator_s wb_s_initiator_struct; + //******************************************************************* + // FUNCTION: to_initiator_struct() + // This function packs transaction variables into a wb_s_initiator_s + // structure. The function returns the handle to the wb_s_initiator_struct. + // This function is defined in wb_s_macros.svh + `wb_s_TO_INITIATOR_STRUCT_FUNCTION + //******************************************************************* + // FUNCTION: from_initiator_struct() + // This function unpacks the struct provided as an argument into transaction + // variables of this class. + // This function is defined in wb_s_macros.svh + `wb_s_FROM_INITIATOR_STRUCT_FUNCTION + + //******************************************************************* + // Responder macro used by wb_s_driver and wb_s_driver_bfm + // to communicate Responder driven data to wb_s_driver_bfm. + // This struct is defined in wb_s_macros.svh + `wb_s_RESPONDER_STRUCT + wb_s_responder_s wb_s_responder_struct; + //******************************************************************* + // FUNCTION: to_responder_struct() + // This function packs transaction variables into a wb_s_responder_s + // structure. The function returns the handle to the wb_s_responder_struct. + // This function is defined in wb_s_macros.svh + `wb_s_TO_RESPONDER_STRUCT_FUNCTION + //******************************************************************* + // FUNCTION: from_responder_struct() + // This function unpacks the struct provided as an argument into transaction + // variables of this class. + // This function is defined in wb_s_macros.svh + `wb_s_FROM_RESPONDER_STRUCT_FUNCTION + // **************************************************************************** + // FUNCTION : new() + // This function is the standard SystemVerilog constructor. + // + function new( string name = "" ); + super.new( name ); + endfunction + + // **************************************************************************** + // FUNCTION: convert2string() + // This function converts all variables in this class to a single string for + // logfile reporting. + // + virtual function string convert2string(); + // pragma uvmf custom convert2string begin + // UVMF_CHANGE_ME : Customize format if desired. + return $sformatf("data:0x%x ",data); + // pragma uvmf custom convert2string end + endfunction + + //******************************************************************* + // FUNCTION: do_print() + // This function is automatically called when the .print() function + // is called on this class. + // + virtual function void do_print(uvm_printer printer); + // pragma uvmf custom do_print begin + // UVMF_CHANGE_ME : Current contents of do_print allows for the use of UVM 1.1d, 1.2 or P1800.2. + // Update based on your own printing preference according to your preferred UVM version + $display(convert2string()); + // pragma uvmf custom do_print end + endfunction + + //******************************************************************* + // FUNCTION: do_compare() + // This function is automatically called when the .compare() function + // is called on this class. + // + virtual function bit do_compare (uvm_object rhs, uvm_comparer comparer); + wb_s_transaction #( + .WB_ADDR_WIDTH(WB_ADDR_WIDTH), + .WB_DATA_WIDTH(WB_DATA_WIDTH) + ) RHS; + if (!$cast(RHS,rhs)) return 0; + // pragma uvmf custom do_compare begin + // UVMF_CHANGE_ME : Eliminate comparison of variables not to be used for compare + return (super.do_compare(rhs,comparer) + &&(this.data == RHS.data) + ); + // pragma uvmf custom do_compare end + endfunction + + //******************************************************************* + // FUNCTION: do_copy() + // This function is automatically called when the .copy() function + // is called on this class. + // + virtual function void do_copy (uvm_object rhs); + wb_s_transaction #( + .WB_ADDR_WIDTH(WB_ADDR_WIDTH), + .WB_DATA_WIDTH(WB_DATA_WIDTH) + ) RHS; + assert($cast(RHS,rhs)); + // pragma uvmf custom do_copy begin + super.do_copy(rhs); + this.data = RHS.data; + // pragma uvmf custom do_copy end + endfunction + + // **************************************************************************** + // FUNCTION: add_to_wave() + // This function is used to display variables in this class in the waveform + // viewer. The start_time and end_time variables must be set before this + // function is called. If the start_time and end_time variables are not set + // the transaction will be hidden at 0ns on the waveform display. + // + virtual function void add_to_wave(int transaction_viewing_stream_h); + `ifdef QUESTA + if (transaction_view_h == 0) begin + transaction_view_h = $begin_transaction(transaction_viewing_stream_h,"wb_s_transaction",start_time); + end + super.add_to_wave(transaction_view_h); + // pragma uvmf custom add_to_wave begin + // UVMF_CHANGE_ME : Color can be applied to transaction entries based on content, example below + // case() + // 1 : $add_color(transaction_view_h,"red"); + // default : $add_color(transaction_view_h,"grey"); + // endcase + // UVMF_CHANGE_ME : Eliminate transaction variables not wanted in transaction viewing in the waveform viewer + $add_attribute(transaction_view_h,data,"data"); + // pragma uvmf custom add_to_wave end + $end_transaction(transaction_view_h,end_time); + $free_transaction(transaction_view_h); + `endif // QUESTA + endfunction + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/wb_s_pkg/src/wb_s_transaction_coverage.svh b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/wb_s_pkg/src/wb_s_transaction_coverage.svh new file mode 100644 index 00000000..01295fc0 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/wb_s_pkg/src/wb_s_transaction_coverage.svh @@ -0,0 +1,79 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This class records wb_s transaction information using +// a covergroup named wb_s_transaction_cg. An instance of this +// coverage component is instantiated in the uvmf_parameterized_agent +// if the has_coverage flag is set. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class wb_s_transaction_coverage #( + int WB_ADDR_WIDTH = 32, + int WB_DATA_WIDTH = 16 + ) extends uvm_subscriber #(.T(wb_s_transaction #( + .WB_ADDR_WIDTH(WB_ADDR_WIDTH), + .WB_DATA_WIDTH(WB_DATA_WIDTH) + ))); + + `uvm_component_param_utils( wb_s_transaction_coverage #( + WB_ADDR_WIDTH, + WB_DATA_WIDTH + )) + + T coverage_trans; + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + // **************************************************************************** + covergroup wb_s_transaction_cg; + // pragma uvmf custom covergroup begin + // UVMF_CHANGE_ME : Add coverage bins, crosses, exclusions, etc. according to coverage needs. + option.auto_bin_max=1024; + option.per_instance=1; + data: coverpoint coverage_trans.data; + // pragma uvmf custom covergroup end + endgroup + + // **************************************************************************** + // FUNCTION : new() + // This function is the standard SystemVerilog constructor. + // + function new(string name="", uvm_component parent=null); + super.new(name,parent); + wb_s_transaction_cg=new; + `uvm_warning("COVERAGE_MODEL_REVIEW", "A covergroup has been constructed which may need review because of either generation or re-generation with merging. Please note that transaction variables added as a result of re-generation and merging are not automatically added to the covergroup. Remove this warning after the covergroup has been reviewed.") + endfunction + + // **************************************************************************** + // FUNCTION : build_phase() + // This function is the standard UVM build_phase. + // + function void build_phase(uvm_phase phase); + wb_s_transaction_cg.set_inst_name($sformatf("wb_s_transaction_cg_%s",get_full_name())); + endfunction + + // **************************************************************************** + // FUNCTION: write (T t) + // This function is automatically executed when a transaction arrives on the + // analysis_export. It copies values from the variables in the transaction + // to local variables used to collect functional coverage. + // + virtual function void write (T t); + `uvm_info("COV","Received transaction",UVM_HIGH); + coverage_trans = t; + wb_s_transaction_cg.sample(); + endfunction + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/wb_s_pkg/src/wb_s_typedefs.svh b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/wb_s_pkg/src/wb_s_typedefs.svh new file mode 100644 index 00000000..43d85640 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/wb_s_pkg/src/wb_s_typedefs.svh @@ -0,0 +1,20 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: +// This file contains defines and typedefs to be compiled for use in +// the simulation running on the host server when using Veloce. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// + + +// pragma uvmf custom additional begin +// pragma uvmf custom additional end + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/wb_s_pkg/src/wb_s_typedefs_hdl.svh b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/wb_s_pkg/src/wb_s_typedefs_hdl.svh new file mode 100644 index 00000000..74738c8c --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/wb_s_pkg/src/wb_s_typedefs_hdl.svh @@ -0,0 +1,21 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: +// This file contains defines and typedefs to be compiled for use in +// the simulation running on the emulator when using Veloce. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// + + + +// pragma uvmf custom additional begin +// pragma uvmf custom additional end + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/wb_s_pkg/wb_s.compile b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/wb_s_pkg/wb_s.compile new file mode 100644 index 00000000..177c6693 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/wb_s_pkg/wb_s.compile @@ -0,0 +1,3 @@ +needs: + - wb_s_hvl.compile + - wb_s_hdl.compile diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/wb_s_pkg/wb_s_bfm.vinfo b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/wb_s_pkg/wb_s_bfm.vinfo new file mode 100644 index 00000000..712d86d9 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/wb_s_pkg/wb_s_bfm.vinfo @@ -0,0 +1,6 @@ +@use $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg_hdl.vinfo +@use wb_s_pkg_hdl.vinfo ++incdir+@vinfodir +src/wb_s_if.sv +src/wb_s_driver_bfm.sv +src/wb_s_monitor_bfm.sv diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/wb_s_pkg/wb_s_common.compile b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/wb_s_pkg/wb_s_common.compile new file mode 100644 index 00000000..cab218ee --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/wb_s_pkg/wb_s_common.compile @@ -0,0 +1,7 @@ +needs: + - $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg_hdl.compile +incdir: + - . + - ${uvm_path}/src +src: + - wb_s_pkg_hdl.sv diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/wb_s_pkg/wb_s_filelist_hdl.f b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/wb_s_pkg/wb_s_filelist_hdl.f new file mode 100644 index 00000000..569bcef6 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/wb_s_pkg/wb_s_filelist_hdl.f @@ -0,0 +1 @@ +$UVMF_VIP_LIBRARY_HOME/interface_packages/wb_s_pkg/wb_s_pkg_hdl.sv diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/wb_s_pkg/wb_s_filelist_hvl.f b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/wb_s_pkg/wb_s_filelist_hvl.f new file mode 100644 index 00000000..6c9a363f --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/wb_s_pkg/wb_s_filelist_hvl.f @@ -0,0 +1 @@ +$UVMF_VIP_LIBRARY_HOME/interface_packages/wb_s_pkg/wb_s_pkg.sv \ No newline at end of file diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/wb_s_pkg/wb_s_filelist_xrtl.f b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/wb_s_pkg/wb_s_filelist_xrtl.f new file mode 100644 index 00000000..23f4bc76 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/wb_s_pkg/wb_s_filelist_xrtl.f @@ -0,0 +1,3 @@ +$UVMF_VIP_LIBRARY_HOME/interface_packages/wb_s_pkg/src/wb_s_if.sv +$UVMF_VIP_LIBRARY_HOME/interface_packages/wb_s_pkg/src/wb_s_monitor_bfm.sv +$UVMF_VIP_LIBRARY_HOME/interface_packages/wb_s_pkg/src/wb_s_driver_bfm.sv diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/wb_s_pkg/wb_s_hdl.compile b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/wb_s_pkg/wb_s_hdl.compile new file mode 100644 index 00000000..4f4110eb --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/wb_s_pkg/wb_s_hdl.compile @@ -0,0 +1,9 @@ +needs: + - $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg_hdl.compile + - ./wb_s_common.compile +incdir: + - . +src: + - src/wb_s_if.sv + - src/wb_s_monitor_bfm.sv + - src/wb_s_driver_bfm.sv diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/wb_s_pkg/wb_s_hvl.compile b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/wb_s_pkg/wb_s_hvl.compile new file mode 100644 index 00000000..e94eaf9b --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/wb_s_pkg/wb_s_hvl.compile @@ -0,0 +1,7 @@ +needs: + - $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg.compile + - ./wb_s_common.compile +incdir: + - . +src: + - wb_s_pkg.sv diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/wb_s_pkg/wb_s_pkg.sv b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/wb_s_pkg/wb_s_pkg.sv new file mode 100644 index 00000000..64813566 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/wb_s_pkg/wb_s_pkg.sv @@ -0,0 +1,77 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// PACKAGE: This file defines all of the files contained in the +// interface package that will run on the host simulator. +// +// CONTAINS: +// - +// - +// - + +// - +// - +// - + +// - +// - +// - + +// - +// - +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +package wb_s_pkg; + + import uvm_pkg::*; + import uvmf_base_pkg_hdl::*; + import uvmf_base_pkg::*; + import wb_s_pkg_hdl::*; + + `include "uvm_macros.svh" + + // pragma uvmf custom package_imports_additional begin + // pragma uvmf custom package_imports_additional end + `include "src/wb_s_macros.svh" + + export wb_s_pkg_hdl::*; + + + + // Parameters defined as HVL parameters + + `include "src/wb_s_typedefs.svh" + `include "src/wb_s_transaction.svh" + + `include "src/wb_s_configuration.svh" + `include "src/wb_s_driver.svh" + `include "src/wb_s_monitor.svh" + + `include "src/wb_s_transaction_coverage.svh" + `include "src/wb_s_sequence_base.svh" + `include "src/wb_s_random_sequence.svh" + + `include "src/wb_s_responder_sequence.svh" + `include "src/wb_s2reg_adapter.svh" + + `include "src/wb_s_agent.svh" + + // pragma uvmf custom package_item_additional begin + // UVMF_CHANGE_ME : When adding new interface sequences to the src directory + // be sure to add the sequence file here so that it will be + // compiled as part of the interface package. Be sure to place + // the new sequence after any base sequences of the new sequence. + // pragma uvmf custom package_item_additional end + +endpackage + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/wb_s_pkg/wb_s_pkg.vinfo b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/wb_s_pkg/wb_s_pkg.vinfo new file mode 100644 index 00000000..617cce78 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/wb_s_pkg/wb_s_pkg.vinfo @@ -0,0 +1,4 @@ +@use $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg.vinfo +@use wb_s_pkg_hdl.vinfo ++incdir+@vinfodir +wb_s_pkg.sv diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/wb_s_pkg/wb_s_pkg_hdl.sv b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/wb_s_pkg/wb_s_pkg_hdl.sv new file mode 100644 index 00000000..49908ae3 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/wb_s_pkg/wb_s_pkg_hdl.sv @@ -0,0 +1,38 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// PACKAGE: This file defines all of the files contained in the +// interface package that needs to be compiled and synthesized +// for running on Veloce. +// +// CONTAINS: +// - +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +package wb_s_pkg_hdl; + + import uvmf_base_pkg_hdl::*; + + // pragma uvmf custom package_imports_additional begin + // pragma uvmf custom package_imports_additional end + + // Parameters defined as HDL parameters + + `include "src/wb_s_typedefs_hdl.svh" + `include "src/wb_s_macros.svh" + + // pragma uvmf custom package_item_additional begin + // pragma uvmf custom package_item_additional end + +endpackage + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/wb_s_pkg/wb_s_pkg_hdl.vinfo b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/wb_s_pkg/wb_s_pkg_hdl.vinfo new file mode 100644 index 00000000..51a2e086 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/wb_s_pkg/wb_s_pkg_hdl.vinfo @@ -0,0 +1,2 @@ +@use $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg_hdl.vinfo +wb_s_pkg_hdl.sv diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/wb_s_pkg/wb_s_pkg_sve.F b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/wb_s_pkg/wb_s_pkg_sve.F new file mode 100644 index 00000000..75e70906 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/wb_s_pkg/wb_s_pkg_sve.F @@ -0,0 +1,10 @@ +// UVM ++incdir+${UVM_HOME}/src +${UVM_HOME}/src/uvm_pkg.sv + +// Common UVMF files +-f ${UVMF_HOME}/common/common_sve.f + ++incdir+. +-f ${UVMF_VIP_LIBRARY_HOME}/interface_packages/wb_s_pkg/wb_s_filelist_hdl.f +-f ${UVMF_VIP_LIBRARY_HOME}/interface_packages/wb_s_pkg/wb_s_filelist_hvl.f diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/wb_s_pkg/yaml/wb_s_interface.yaml b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/wb_s_pkg/yaml/wb_s_interface.yaml new file mode 100644 index 00000000..f37041fc --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/subsystem/uvmf_template_output/verification_ip/interface_packages/wb_s_pkg/yaml/wb_s_interface.yaml @@ -0,0 +1,75 @@ +uvmf: + interfaces: + wb_s: + clock: clock + config_constraints: [] + config_vars: [] + existing_library_component: 'True' + gen_inbound_streaming_driver: 'False' + hdl_pkg_parameters: [] + hdl_typedefs: [] + hvl_pkg_parameters: [] + hvl_typedefs: [] + parameters: + - name: WB_ADDR_WIDTH + type: int + value: '32' + - name: WB_DATA_WIDTH + type: int + value: '16' + ports: + - dir: input + name: din + reset_value: '''b0' + width: WB_DATA_WIDTH + - dir: output + name: dout + reset_value: '''b0' + width: WB_DATA_WIDTH + - dir: input + name: TGD_I + reset_value: '''bz' + width: WB_DATA_WIDTH + - dir: output + name: TGD_O + reset_value: '''bz' + width: WB_DATA_WIDTH + - dir: output + name: ack + reset_value: '''b0' + width: '1' + - dir: input + name: adr + reset_value: '''b0' + width: WB_ADDR_WIDTH + - dir: input + name: cyc + reset_value: '0' + width: '1' + - dir: output + name: err + reset_value: '''b0' + width: '1' + - dir: input + name: we + reset_value: '0' + width: '1' + - dir: input + name: stb + reset_value: '0' + width: '1' + - dir: input + name: sel + reset_value: '''b0' + width: WB_DATA_WIDTH/8 + reset: reset + reset_assertion_level: 'True' + transaction_constraints: [] + transaction_vars: + - comment: '' + iscompare: 'True' + isrand: 'True' + name: data + type: bit [WB_DATA_WIDTH-1:0] + unpacked_dimension: '' + use_dpi_link: 'False' diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_1/.project b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_1/.project new file mode 100644 index 00000000..f8d875b5 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_1/.project @@ -0,0 +1,37 @@ + + + block_1 + + + + + + org.python.pydev.PyDevBuilder + + + + + net.sf.sveditor.core.SVProjectBuilder + + + + + + net.sf.sveditor.core.SVNature + org.python.pydev.pythonNature + + + + verification_ip + 2 + UVMF_VIP_LIBRARY_HOME + + + + + UVMF_VIP_LIBRARY_HOME + $%7BPARENT-2-PROJECT_LOC%7D/verification_ip + + + + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_1/.svproject b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_1/.svproject new file mode 100644 index 00000000..2bcfbf34 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_1/.svproject @@ -0,0 +1,16 @@ + + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_1/block_1_sve.F b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_1/block_1_sve.F new file mode 100644 index 00000000..08e278c3 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_1/block_1_sve.F @@ -0,0 +1,29 @@ + +// UVM ++incdir+${UVM_HOME}/src +${UVM_HOME}/src/uvm_pkg.sv + +// Common UVMF files +-f ${UVMF_HOME}/common/common_sve.f + +// BFM Files +-F ${UVMF_VIP_LIBRARY_HOME}/interface_packages/apb_m_pkg/apb_m_pkg_sve.F +-F ${UVMF_VIP_LIBRARY_HOME}/interface_packages/axi_m_pkg/axi_m_pkg_sve.F +-F ${UVMF_VIP_LIBRARY_HOME}/interface_packages/spi_s_pkg/spi_s_pkg_sve.F + +// Environment Files +-F ${UVMF_VIP_LIBRARY_HOME}/environment_packages/block_1_env_pkg/block_1_env_pkg_sve.F + +// Bench Files ++incdir+./tb/tests +./tb/tests/block_1_tests_pkg.sv + ++incdir+./tb/sequences +./tb/sequences/block_1_sequences_pkg.sv + ++incdir+./tb/parameters +./tb/parameters/block_1_parameters_pkg.sv + +./tb/testbench/hdl_top.sv +./tb/testbench/hvl_top.sv + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_1/docs/interfaces.csv b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_1/docs/interfaces.csv new file mode 100644 index 00000000..784f480a --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_1/docs/interfaces.csv @@ -0,0 +1,16 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// + +, +Interface Description, Interface Type, Interface Transaction, Interface Name, +apb_master, apb_m_driver_bfm apb_m_monitor_bfm, apb_m_transaction, apb_m_pkg_apb_master_BFM, +axi_master1, axi_m_driver_bfm axi_m_monitor_bfm, axi_m_transaction, axi_m_pkg_axi_master1_BFM, +axi_master2, axi_m_driver_bfm axi_m_monitor_bfm, axi_m_transaction, axi_m_pkg_axi_master2_BFM, +spi_slave, spi_s_driver_bfm spi_s_monitor_bfm, spi_s_transaction, spi_s_pkg_spi_slave_BFM, + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_1/rtl/dut.compile b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_1/rtl/dut.compile new file mode 100644 index 00000000..9b0008fc --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_1/rtl/dut.compile @@ -0,0 +1,6 @@ + +# pragma uvmf custom dut_compile_info begin +src: + - ./vhdl/vhdl_dut.vhd + - ./verilog/verilog_dut.v +# pragma uvmf custom dut_compile_info end diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_1/rtl/verilog/verilog_dut.v b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_1/rtl/verilog/verilog_dut.v new file mode 100644 index 00000000..96198441 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_1/rtl/verilog/verilog_dut.v @@ -0,0 +1,21 @@ +module verilog_dut(clk, rst, in_signal, out_signal); + +input clk; +input rst; +input in_signal; +output out_signal; + +reg out_signal_o; + +always @(posedge clk) begin + if (rst) begin + out_signal_o <= 0; + end + else begin + out_signal_o <= ~in_signal; + end + end + +assign out_signal = out_signal_o; + +endmodule diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_1/rtl/verilog/verilog_dut.vinfo b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_1/rtl/verilog/verilog_dut.vinfo new file mode 100644 index 00000000..87e95f36 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_1/rtl/verilog/verilog_dut.vinfo @@ -0,0 +1 @@ +verilog_dut.v diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_1/rtl/vhdl/vhdl_dut.vhd b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_1/rtl/vhdl/vhdl_dut.vhd new file mode 100644 index 00000000..904aa37d --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_1/rtl/vhdl/vhdl_dut.vhd @@ -0,0 +1,21 @@ +library ieee; +use ieee.std_logic_1164.all ; + +entity vhdl_dut is + port ( clk : in std_logic ; + rst : in std_logic ; + in_signal : in std_logic ; + out_signal :out std_logic + ); +end vhdl_dut; + +architecture rtl of vhdl_dut is + begin + P1: process + variable out_signal_o : std_logic; + begin + wait until clk'event and clk = '1'; + out_signal_o := in_signal; + out_signal <= out_signal_o; + end process; + end rtl; diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_1/sim/Makefile b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_1/sim/Makefile new file mode 100644 index 00000000..8bf96331 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_1/sim/Makefile @@ -0,0 +1,200 @@ + +# +#---------------------------------------------------------------------- +# +# DESCRIPTION: This makefile includes the shared makefile and contains +# bench level make targets. +# +#---------------------------------------------------------------------- + + +# pragma uvmf custom additional begin +# pragma uvmf custom additional end + +# ********************************************************************************************* +# UVMF library directory: +# This variable points to the UVMF release where uvmf_base_pkg directory resides. +# This variable points to release code that is not user modified. +# This variable allows for UVMF release directories to reside independent of project related verification IP and project bench directories. +# This code below looks "upward" for directory starting with UVMF_* and returns first match for use with the release examples. +UVMF_HOME ?= ___PLEASE_SET_AN_ENVIRONMENT_VARIABLE_NAMED_UVMF_HOME_TO_POINT_TO_THE_UVMF_INSTALLATION___ + +# pragma uvmf custom exports begin +# +# Project(s) specific verification IP library: +# Directory where reusable verification packages for interfaces, environments, utilities, etc. reside. +# This variable allows for your verification IP to reside independent of project bench and UVMF release directories. +# For examples deployed with UVMF this will be $(UVMF_HOME)//verification_ip +export UVMF_VIP_LIBRARY_HOME ?= $(PWD)/../../../verification_ip +# +# Project specific bench: +# Directory where bench specific code is located. +# This variable allows for project_benches to reside independent of verification IP and UVMF release directories. +# For examples deployed with UVMF this will be $(UVMF_HOME)//project_benches/ +export UVMF_PROJECT_DIR ?= $(PWD)/.. +# +# +# pragma uvmf custom exports end +# ********************************************************************************************* + +## Check PATH for required vinfo scripts +PVAL := $(shell command -v make_filelist.py 2> /dev/null) +ifndef PVAL + MFLIST = $(UVMF_HOME)/scripts/make_filelist.py +else + MFLIST = make_filelist.py +endif + + +# Set test case specific Variables +TEST_NAME ?= test_top + +TEST_SEED ?= random +UVM_CLI_ARGS = + +# Usage of Veloce, etc. to be input by the user (subject to defaults) +USE_VELOCE ?= 0 + +# Usage of vinfo flow for generating file list +USE_VINFO ?= 0 + +# Usage of Veloce and Questa profilers +USE_VELOCE_PROFILER ?= 0 +USE_QUESTA_PROFILER ?= 0 + + +# Set project Variables +TEST_PLAN_NAME = block_1_TestPlan +REPORTING_DO_FILE = block_1_reports_script + + +# Include makefile that includes targets for UVM_VIP_Library packages +include $(UVMF_HOME)/scripts/Makefile + + + + +# Include all requisite interface package targets for this bench +include $(UVMF_VIP_LIBRARY_HOME)/interface_packages/apb_m_pkg/Makefile +include $(UVMF_VIP_LIBRARY_HOME)/interface_packages/axi_m_pkg/Makefile +include $(UVMF_VIP_LIBRARY_HOME)/interface_packages/spi_s_pkg/Makefile + +# Include all requisite environment package targets for this bench +include $(UVMF_VIP_LIBRARY_HOME)/environment_packages/block_1_env_pkg/Makefile + + + +# Add to default compile/load/run arguments +VCOM_ARGS += + +# Note: vsim-3009 error can be eliminated by adding -timescale 1ps/1ps to VLOG_ARGS + +VLOG_ARGS += $(UVM_DISABLE_FILE_LINE_CMD) + +VELANALYZE_ARGS += +VELANALYZE_HVL_ARGS += + +BATCH_VOPT_ARGS += +DEBUG_VOPT_ARGS += +EXTRA_VOPT_TOPS += +COMMON_VSIM_ARGS += +COMMON_VSIM_ARGS += + + +BATCH_VSIM_ARGS += #-uvmcontrol=none +DEBUG_VSIM_ARGS += +EXTRA_VSIM_TOPS += + +# pragma uvmf custom additional_args begin +# pragma uvmf custom additional_args end + + +# Project bench package source +block_1_PARAMETERS_PKG ?=\ +$(UVMF_PROJECT_DIR)/tb/parameters/block_1_parameters_pkg.sv + + +block_1_SEQUENCES_PKG ?=\ +$(UVMF_PROJECT_DIR)/tb/sequences/block_1_sequences_pkg.sv + + +block_1_TEST_PKG ?=\ +$(UVMF_PROJECT_DIR)/tb/tests/block_1_tests_pkg.sv + +# pragma uvmf custom dut_files begin +# UVMF_CHANGE_ME : Reference Verilog DUT source. +block_1_VERILOG_DUT ?=\ +$(UVMF_PROJECT_DIR)/rtl/verilog/verilog_dut.v + +# UVMF_CHANGE_ME : Reference VHDL DUT source. +block_1_VHDL_DUT ?=\ +$(UVMF_PROJECT_DIR)/rtl/vhdl/vhdl_dut.vhd +# pragma uvmf custom dut_files end + + +# Project bench package targets +COMP_block_1_PARAMETERS_PKG_TGT_0 = q_comp_block_1_parameters_pkg +COMP_block_1_PARAMETERS_PKG_TGT_1 = v_comp_block_1_parameters_pkg +COMP_block_1_PARAMETERS_PKG_TGT = $(COMP_block_1_PARAMETERS_PKG_TGT_$(USE_VELOCE)) + +comp_block_1_parameters_pkg: $(COMP_block_1_PARAMETERS_PKG_TGT) + +q_comp_block_1_parameters_pkg: + $(HVL_COMP_CMD) +incdir+$(UVMF_PROJECT_DIR)/tb/parameters $(block_1_PARAMETERS_PKG) + +v_comp_block_1_parameters_pkg: q_comp_block_1_parameters_pkg + $(HDL_COMP_CMD) +incdir+$(UVMF_PROJECT_DIR)/tb/parameters $(block_1_PARAMETERS_PKG) + + +comp_block_1_sequence_pkg: + $(HVL_COMP_CMD) +incdir+$(UVMF_PROJECT_DIR)/tb/sequences $(block_1_SEQUENCES_PKG) + +comp_block_1_tests_pkg: + $(HVL_COMP_CMD) +incdir+$(UVMF_PROJECT_DIR)/tb/tests $(block_1_TEST_PKG) + +# pragma uvmf custom dut_compile_make_target begin +# UVMF_CHANGE_ME : Add make target to compile your verilog dut here +comp_block_1_verilog_dut: + echo "Compile your verilog DUT here" + $(HDL_COMP_CMD) $(block_1_VERILOG_DUT) + +# UVMF_CHANGE_ME : Add make target to compile your vhdl dut here +comp_block_1_vhdl_dut: + echo "Compile your vhdl DUT here" + $(HDL_COMP_CMD_VHDL) $(block_1_VHDL_DUT) + +# UVMF_CHANGE_ME : Add make target to compile your dut here +comp_block_1_dut: comp_block_1_vhdl_dut comp_block_1_verilog_dut +# pragma uvmf custom dut_compile_make_target end + + +BUILD_TGT_0 = make_build +BUILD_TGT_1 = vinfo_build +BUILD_TGT = $(BUILD_TGT_$(USE_VINFO)) + + +comp_hvl : comp_hvl_core + + +comp_hvl_core : \ + comp_apb_m_pkg comp_axi_m_pkg comp_spi_s_pkg \ + comp_block_1_env_pkg \ + comp_block_1_parameters_pkg comp_block_1_sequence_pkg comp_block_1_tests_pkg + +comp_uvmf_core : comp_uvm_pkg comp_uvmf_base_pkg + +make_build: comp_block_1_dut comp_uvmf_core comp_hvl comp_test_bench + +hvl_build: q_comp_apb_m_pkg q_comp_axi_m_pkg q_comp_spi_s_pkg comp_block_1_env_pkg comp_block_1_sequence_pkg comp_block_1_tests_pkg hvl_comp_testbench link optimize + + +vinfo_build: comp_block_1_vhdl_dut build_hdl_vinfo build_hvl_vinfo $(VINFO_TGT) + + $(HDL_COMP_CMD) -F hdl.vf + $(VEL_COMP) + +build: $(BUILD_TGT) + +# pragma uvmf custom additional_targets begin +# pragma uvmf custom additional_targets end + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_1/sim/bcr_testlist b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_1/sim/bcr_testlist new file mode 100644 index 00000000..def2371e --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_1/sim/bcr_testlist @@ -0,0 +1,19 @@ + + + +# Test list for use by RMDB file +# File syntax is +# TB_INFO { } { } +# TB ## All subsequent tests will run on this bench until a different "TB" line is seen +# TEST <1st_seed> ... +# If not enough seeds are provided then random seeds are used to pad +# If no repeat count is given, default is 1 +# pragma uvmf custom tb_info begin +TB_INFO block_1 { } { } +# pragma uvmf custom tb_info end +TB block_1 +# pragma uvmf custom regression_suite begin +TEST test_top 3 +# pragma uvmf custom regression_suite end + + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_1/sim/bcr_testlist.yaml b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_1/sim/bcr_testlist.yaml new file mode 100644 index 00000000..e9f7fa3e --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_1/sim/bcr_testlist.yaml @@ -0,0 +1,44 @@ + + + +# YAML test list for use by RMDB file +# File syntax is +# uvmf_testlist: +# testbenches: +# - name: +# extra_build_options: +# extra_run_options: +# - name: +# ... +# - name: +# tests: +# - name: +# uvm_testname: (defaults to test_name) +# testbench: (defaults to last tb name seen) +# repeat: (defaults to 1) +# seeds: [,,...,] (defaults to all random) +# extra_test_options: +# - name: +# ... +# - name: +# include: +# - (relative path reference is to the including YAML file) +# - +# ... +# - + +uvmf_testlist: + testbenches: +# pragma uvmf custom tb_info begin + - name: block_1 + extra_build_options: "" + extra_run_options: "" +# pragma uvmf custom tb_info end + tests: + - testbench: block_1 +# pragma uvmf custom regression_suite begin + - name: test_top + repeat: 3 +# pragma uvmf custom regression_suite end + + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_1/sim/compile.do b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_1/sim/compile.do new file mode 100644 index 00000000..9f27636d --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_1/sim/compile.do @@ -0,0 +1,72 @@ + + +################################################################## +## ENVIRONMENT VARIABLES +################################################################## +quietly set ::env(UVMF_VIP_LIBRARY_HOME) ../../../verification_ip +quietly set ::env(UVMF_PROJECT_DIR) .. + +## Using VRM means that the build is occuring several more directories deeper underneath +## the sim directory, need to prepend some more '..' +if {[info exists ::env(VRM_BUILD)]} { + quietly set ::env(UVMF_VIP_LIBRARY_HOME) "../../../../../$::env(UVMF_VIP_LIBRARY_HOME)" + quietly set ::env(UVMF_PROJECT_DIR) "../../../../../$::env(UVMF_PROJECT_DIR)" +} +quietly set ::env(UVMF_VIP_LIBRARY_HOME) [file normalize $::env(UVMF_VIP_LIBRARY_HOME)] +quietly set ::env(UVMF_PROJECT_DIR) [file normalize $::env(UVMF_PROJECT_DIR)] +quietly echo "UVMF_VIP_LIBRARY_HOME = $::env(UVMF_VIP_LIBRARY_HOME)" +quietly echo "UVMF_PROJECT_DIR = $::env(UVMF_PROJECT_DIR)" + + +################################################################### +## HOUSEKEEPING : DELETE FILES THAT WILL BE REGENERATED +################################################################### +file delete -force *~ *.ucdb vsim.dbg *.vstf *.log work *.mem *.transcript.txt certe_dump.xml *.wlf covhtmlreport VRMDATA +file delete -force design.bin qwave.db dpiheader.h visualizer*.ses +file delete -force veloce.med veloce.wave veloce.map tbxbindings.h edsenv velrunopts.ini +file delete -force sv_connect.* + +################################################################### +## COMPILE DUT SOURCE CODE +################################################################### +vlib work +# pragma uvmf custom dut_compile_dofile_target begin +# UVMF_CHANGE_ME : Add commands to compile your dut here, replacing the default examples +vlog -sv -timescale 1ps/1ps -suppress 2223,2286 $env(UVMF_PROJECT_DIR)/rtl/verilog/verilog_dut.v +vcom $env(UVMF_PROJECT_DIR)/rtl/vhdl/vhdl_dut.vhd +# pragma uvmf custom dut_compile_dofile_target end + +################################################################### +## COMPILE UVMF BASE/COMMON SOURCE CODE +################################################################### +vlog -sv -timescale 1ps/1ps -suppress 2223 -suppress 2286 +incdir+$env(UVMF_HOME)/uvmf_base_pkg -F $env(UVMF_HOME)/uvmf_base_pkg/uvmf_base_pkg_filelist_hdl.f +vlog -sv -timescale 1ps/1ps -suppress 2223 -suppress 2286 +incdir+$env(UVMF_HOME)/uvmf_base_pkg -F $env(UVMF_HOME)/uvmf_base_pkg/uvmf_base_pkg_filelist_hvl.f + + +################################################################### +## UVMF INTERFACE COMPILATION +################################################################### +do $env(UVMF_VIP_LIBRARY_HOME)/interface_packages/apb_m_pkg/compile.do +do $env(UVMF_VIP_LIBRARY_HOME)/interface_packages/axi_m_pkg/compile.do +do $env(UVMF_VIP_LIBRARY_HOME)/interface_packages/spi_s_pkg/compile.do + +################################################################### +## UVMF ENVIRONMENT COMPILATION +################################################################### +do $env(UVMF_VIP_LIBRARY_HOME)/environment_packages/block_1_env_pkg/compile.do + +################################################################### +## UVMF BENCHES COMPILATION +################################################################### +vlog -sv -timescale 1ps/1ps -suppress 2223 -suppress 2286 +incdir+$env(UVMF_PROJECT_DIR)/tb/parameters $env(UVMF_PROJECT_DIR)/tb/parameters/block_1_parameters_pkg.sv +vlog -sv -timescale 1ps/1ps -suppress 2223 -suppress 2286 +incdir+$env(UVMF_PROJECT_DIR)/tb/sequences $env(UVMF_PROJECT_DIR)/tb/sequences/block_1_sequences_pkg.sv +vlog -sv -timescale 1ps/1ps -suppress 2223 -suppress 2286 +incdir+$env(UVMF_PROJECT_DIR)/tb/tests $env(UVMF_PROJECT_DIR)/tb/tests/block_1_tests_pkg.sv + +vlog -sv -timescale 1ps/1ps -suppress 2223 -suppress 2286 +incdir+$env(UVMF_PROJECT_DIR)/tb/testbench -F $env(UVMF_PROJECT_DIR)/tb/testbench/top_filelist_hdl.f +vlog -sv -timescale 1ps/1ps -suppress 2223 -suppress 2286 +incdir+$env(UVMF_PROJECT_DIR)/tb/testbench -F $env(UVMF_PROJECT_DIR)/tb/testbench/top_filelist_hvl.f + +################################################################### +## OPTIMIZATION +################################################################### +vopt hvl_top hdl_top -o optimized_batch_top_tb +vopt +acc hvl_top hdl_top -o optimized_debug_top_tb diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_1/sim/hdl.compile b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_1/sim/hdl.compile new file mode 100644 index 00000000..8e7bd41a --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_1/sim/hdl.compile @@ -0,0 +1,5 @@ +needs: +# pragma uvmf custom dut_compile_info begin + - ../rtl/dut.compile +# pragma uvmf custom dut_compile_info end + - ../tb/testbench/hdl_top.compile diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_1/sim/hdl.vinfo b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_1/sim/hdl.vinfo new file mode 100644 index 00000000..da27ec77 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_1/sim/hdl.vinfo @@ -0,0 +1 @@ +@use $UVMF_PROJECT_DIR/tb/testbench/hdl_top.vinfo diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_1/sim/hvl.compile b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_1/sim/hvl.compile new file mode 100644 index 00000000..ce952549 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_1/sim/hvl.compile @@ -0,0 +1,2 @@ +needs: + - ../tb/testbench/hvl_top.compile diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_1/sim/hvl.vinfo b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_1/sim/hvl.vinfo new file mode 100644 index 00000000..d22eff33 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_1/sim/hvl.vinfo @@ -0,0 +1 @@ +@use $UVMF_PROJECT_DIR/tb/testbench/hvl_top.vinfo diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_1/sim/run.do b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_1/sim/run.do new file mode 100644 index 00000000..101ddc48 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_1/sim/run.do @@ -0,0 +1,21 @@ + + +quietly set svLibs "" +quietly set extra_vsim_args "" + +################################################################### +## Check for additional vsim arguments passed using env var $UVMF_EXTRA_VSIM_ARGS +################################################################### +if {[info exists ::env(UVMF_EXTRA_VSIM_ARGS)]} { + echo "Adding more args to vsim command" + quietly set extra_vsim_args $::env(UVMF_EXTRA_VSIM_ARGS) +} + +################################################################## +## Launch Questa : generate vsim command line and execute +################################################################## +# pragma uvmf custom dut_run_dofile_target begin +# UVMF_CHANGE_ME : Change the UVM_TESTNAME plusarg to run a different test +quietly set cmd [format "vsim -i -sv_seed random +UVM_TESTNAME=test_top +UVM_VERBOSITY=UVM_HIGH -permit_unmatched_virtual_intf +notimingchecks -suppress 8887 %s %s -uvmcontrol=all -msgmode both -classdebug -assertdebug +uvm_set_config_int=*,enable_transaction_viewing,1 -do { set NoQuitOnFinish 1; onbreak {resume}; run 0; do wave.do; set PrefSource(OpenOnBreak) 0; radix hex showbase; } optimized_debug_top_tb" $svLibs $extra_vsim_args] +# pragma uvmf custom dut_run_dofile_target end +eval $cmd diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_1/sim/tbx.config b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_1/sim/tbx.config new file mode 100644 index 00000000..eec58168 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_1/sim/tbx.config @@ -0,0 +1,10 @@ + + + + + +comp -questa +velsyn -D1S +rtlc -allow_4ST + + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_1/sim/testlist b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_1/sim/testlist new file mode 100644 index 00000000..5ca4f2cc --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_1/sim/testlist @@ -0,0 +1,20 @@ + + + + +# Test list for use by RMDB file +# File syntax is +# TB_INFO { } { } +# TB ## All subsequent tests will run on this bench until a different "TB" line is seen +# TEST <1st_seed> ... +# If not enough seeds are provided then random seeds are used to pad +# If no repeat count is given, default is 1 +# pragma uvmf custom tb_info begin +TB_INFO block_1 { UVMF_VIP_LIBRARY_HOME=../../../../../../../../verification_ip UVMF_PROJECT_DIR=../../../../../../../block_1 } { } +# pragma uvmf custom tb_info end +TB block_1 +# pragma uvmf custom regression_suite begin +TEST test_top 3 +# pragma uvmf custom regression_suite end + + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_1/sim/testlist.yaml b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_1/sim/testlist.yaml new file mode 100644 index 00000000..113ec8a9 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_1/sim/testlist.yaml @@ -0,0 +1,44 @@ + + + +# YAML test list for use by RMDB file +# File syntax is +# uvmf_testlist: +# testbenches: +# - name: +# extra_build_options: +# extra_run_options: +# - name: +# ... +# - name: +# tests: +# - name: +# uvm_testname: (defaults to test_name) +# testbench: (defaults to last tb name seen) +# repeat: (defaults to 1) +# seeds: [,,...,] (defaults to all random) +# extra_test_options: +# - name: +# ... +# - name: +# include: +# - (relative path reference is to the including YAML file) +# - +# ... +# - + +uvmf_testlist: + testbenches: +# pragma uvmf custom tb_info begin + - name: block_1 + extra_build_options: "UVMF_VIP_LIBRARY_HOME=../../../../../../../../verification_ip UVMF_PROJECT_DIR=../../../../../../../block_1" + extra_run_options: "" +# pragma uvmf custom tb_info end + tests: + - testbench: block_1 +# pragma uvmf custom regression_suite begin + - name: test_top + repeat: 3 +# pragma uvmf custom regression_suite end + + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_1/sim/top.compile b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_1/sim/top.compile new file mode 100644 index 00000000..efd51c07 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_1/sim/top.compile @@ -0,0 +1,3 @@ +needs: + - hvl.compile + - hdl.compile diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_1/sim/veloce.config b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_1/sim/veloce.config new file mode 100644 index 00000000..d0975155 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_1/sim/veloce.config @@ -0,0 +1,26 @@ + + + + + +# pragma uvmf custom additional begin +comp -num_boards 1 +comp -hvl questa +# Please choose the correct emulator type code for +# comp -platform command or else velcomp will fail +# Available types are: +# - Veloce2 Quattro: D2 +# - Veloce2 Maximus: D2M +# - Veloce Strato TiL, Ti, and Mi: Strato +# - Veloce Strato M and Strato T: StratoM +# - comp -platform +comp -platform Strato + +rtlc -enable_tbx_pragma_checks +rtlc -allow_4ST +rtlc -allow_MDR +rtlc -compile_display +rtlc -xwave_siglist xwaves.sigs +# pragma uvmf custom additional end + + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_1/sim/viswave.do b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_1/sim/viswave.do new file mode 100644 index 00000000..5e690492 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_1/sim/viswave.do @@ -0,0 +1,34 @@ + + +onerror resume +wave tags F0 +wave update off + +wave spacer -backgroundcolor Salmon { apb_master } +wave add uvm_test_top.environment.apb_master.apb_master_monitor.txn_stream -radix string -tag F0 +wave group apb_master_bus +wave add -group apb_master_bus hdl_top.apb_master_bus.* -radix hexadecimal -tag F0 +wave group apb_master_bus -collapse +wave insertion [expr [wave index insertpoint] +1] +wave spacer -backgroundcolor Salmon { axi_master1 } +wave add uvm_test_top.environment.axi_master1.axi_master1_monitor.txn_stream -radix string -tag F0 +wave group axi_master1_bus +wave add -group axi_master1_bus hdl_top.axi_master1_bus.* -radix hexadecimal -tag F0 +wave group axi_master1_bus -collapse +wave insertion [expr [wave index insertpoint] +1] +wave spacer -backgroundcolor Salmon { axi_master2 } +wave add uvm_test_top.environment.axi_master2.axi_master2_monitor.txn_stream -radix string -tag F0 +wave group axi_master2_bus +wave add -group axi_master2_bus hdl_top.axi_master2_bus.* -radix hexadecimal -tag F0 +wave group axi_master2_bus -collapse +wave insertion [expr [wave index insertpoint] +1] +wave spacer -backgroundcolor Salmon { spi_slave } +wave add uvm_test_top.environment.spi_slave.spi_slave_monitor.txn_stream -radix string -tag F0 +wave group spi_slave_bus +wave add -group spi_slave_bus hdl_top.spi_slave_bus.* -radix hexadecimal -tag F0 +wave group spi_slave_bus -collapse +wave insertion [expr [wave index insertpoint] +1] + +wave update on +WaveSetStreamView + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_1/sim/wave.do b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_1/sim/wave.do new file mode 100644 index 00000000..a290af05 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_1/sim/wave.do @@ -0,0 +1,36 @@ + + +onerror {resume} +quietly WaveActivateNextPane {} 0 + +add wave -noupdate -divider apb_master +add wave -noupdate /uvm_root/uvm_test_top/environment/apb_master/apb_master_monitor/txn_stream +add wave -noupdate -group apb_master_bus /hdl_top/apb_master_bus/* +add wave -noupdate -divider axi_master1 +add wave -noupdate /uvm_root/uvm_test_top/environment/axi_master1/axi_master1_monitor/txn_stream +add wave -noupdate -group axi_master1_bus /hdl_top/axi_master1_bus/* +add wave -noupdate -divider axi_master2 +add wave -noupdate /uvm_root/uvm_test_top/environment/axi_master2/axi_master2_monitor/txn_stream +add wave -noupdate -group axi_master2_bus /hdl_top/axi_master2_bus/* +add wave -noupdate -divider spi_slave +add wave -noupdate /uvm_root/uvm_test_top/environment/spi_slave/spi_slave_monitor/txn_stream +add wave -noupdate -group spi_slave_bus /hdl_top/spi_slave_bus/* + +TreeUpdate [SetDefaultTree] +quietly wave cursor active 0 +configure wave -namecolwidth 472 +configure wave -valuecolwidth 100 +configure wave -justifyvalue left +configure wave -signalnamewidth 0 +configure wave -snapdistance 10 +configure wave -datasetprefix 0 +configure wave -rowmargin 4 +configure wave -childrowmargin 2 +configure wave -gridoffset 0 +configure wave -gridperiod 1 +configure wave -griddelta 40 +configure wave -timeline 0 +configure wave -timelineunits ns +update +WaveRestoreZoom {27 ns} {168 ns} + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_1/sim/xwaves.sigs b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_1/sim/xwaves.sigs new file mode 100644 index 00000000..d75f0a57 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_1/sim/xwaves.sigs @@ -0,0 +1,17 @@ + + + + + +# pragma uvmf custom additional begin + +Group All + +#Top level signals +hdl_top.* +#Add additional levels or individual signals as needed +hdl_top.*.* + +# pragma uvmf custom additional end + + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_1/tb/parameters/block_1_parameters_pkg.compile b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_1/tb/parameters/block_1_parameters_pkg.compile new file mode 100644 index 00000000..e2a26586 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_1/tb/parameters/block_1_parameters_pkg.compile @@ -0,0 +1,4 @@ +needs: + - $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg_hdl.compile +src: + - block_1_parameters_pkg.sv diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_1/tb/parameters/block_1_parameters_pkg.sv b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_1/tb/parameters/block_1_parameters_pkg.sv new file mode 100644 index 00000000..c78c1374 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_1/tb/parameters/block_1_parameters_pkg.sv @@ -0,0 +1,41 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This package contains test level parameters +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +`ifndef BLOCK_1_PARAMETERS_PKG_BENCH +`define BLOCK_1_PARAMETERS_PKG_BENCH + +package block_1_parameters_pkg; + + import uvmf_base_pkg_hdl::*; + + // pragma uvmf custom package_imports_additional begin + // pragma uvmf custom package_imports_additional end + + + // These parameters are used to uniquely identify each interface. The monitor_bfm and + // driver_bfm are placed into and retrieved from the uvm_config_db using these string + // names as the field_name. The parameter is also used to enable transaction viewing + // from the command line for selected interfaces using the UVM command line processing. + parameter string apb_master_BFM = "apb_master_BFM"; /* [0] */ + parameter string axi_master1_BFM = "axi_master1_BFM"; /* [1] */ + parameter string axi_master2_BFM = "axi_master2_BFM"; /* [2] */ + parameter string spi_slave_BFM = "spi_slave_BFM"; /* [3] */ + + // pragma uvmf custom package_item_additional begin + // pragma uvmf custom package_item_additional end + +endpackage + +// pragma uvmf custom external begin +// pragma uvmf custom external end +`endif diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_1/tb/parameters/block_1_parameters_pkg.vinfo b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_1/tb/parameters/block_1_parameters_pkg.vinfo new file mode 100644 index 00000000..8b0adcd9 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_1/tb/parameters/block_1_parameters_pkg.vinfo @@ -0,0 +1,2 @@ +@use $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg_hdl.vinfo +block_1_parameters_pkg.sv diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_1/tb/sequences/block_1_sequences_pkg.compile b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_1/tb/sequences/block_1_sequences_pkg.compile new file mode 100644 index 00000000..1497180c --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_1/tb/sequences/block_1_sequences_pkg.compile @@ -0,0 +1,9 @@ +needs: + - $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg.compile + - ../../../../verification_ip/interface_packages/apb_m_pkg/apb_m.compile + - ../../../../verification_ip/interface_packages/axi_m_pkg/axi_m.compile + - ../../../../verification_ip/interface_packages/spi_s_pkg/spi_s.compile + - ../../../../verification_ip/environment_packages/block_1_env_pkg/block_1_env_pkg.compile + - ../parameters/block_1_parameters_pkg.compile +src: + - block_1_sequences_pkg.sv diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_1/tb/sequences/block_1_sequences_pkg.sv b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_1/tb/sequences/block_1_sequences_pkg.sv new file mode 100644 index 00000000..b93a63f9 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_1/tb/sequences/block_1_sequences_pkg.sv @@ -0,0 +1,54 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This package includes all high level sequence classes used +// in the environment. These include utility sequences and top +// level sequences. +// +// CONTAINS: +// - +// - +// +//---------------------------------------------------------------------- +// +//---------------------------------------------------------------------- +// +`ifndef BLOCK_1_SEQUENCES_PKG_BENCH +`define BLOCK_1_SEQUENCES_PKG_BENCH +package block_1_sequences_pkg; + import uvm_pkg::*; + import uvmf_base_pkg::*; + import apb_m_pkg::*; + import apb_m_pkg_hdl::*; + import axi_m_pkg::*; + import axi_m_pkg_hdl::*; + import spi_s_pkg::*; + import spi_s_pkg_hdl::*; + import block_1_parameters_pkg::*; + import block_1_env_pkg::*; + `include "uvm_macros.svh" + + // pragma uvmf custom package_imports_additional begin + // pragma uvmf custom package_imports_additional end + + `include "src/block_1_bench_sequence_base.svh" + `include "src/register_test_sequence.svh" + `include "src/example_derived_test_sequence.svh" + + // pragma uvmf custom package_item_additional begin + // UVMF_CHANGE_ME : When adding new sequences to the src directory + // be sure to add the sequence file here so that it will be + // compiled as part of the sequence package. Be sure to place + // the new sequence after any base sequences of the new sequence. + // pragma uvmf custom package_item_additional end + +endpackage + +// pragma uvmf custom external begin +// pragma uvmf custom external end +`endif diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_1/tb/sequences/block_1_sequences_pkg.vinfo b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_1/tb/sequences/block_1_sequences_pkg.vinfo new file mode 100644 index 00000000..b67a290f --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_1/tb/sequences/block_1_sequences_pkg.vinfo @@ -0,0 +1,8 @@ +@use $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg.vinfo +@use $UVMF_VIP_LIBRARY_HOME/interface_packages/apb_m_pkg/apb_m_pkg.vinfo +@use $UVMF_VIP_LIBRARY_HOME/interface_packages/axi_m_pkg/axi_m_pkg.vinfo +@use $UVMF_VIP_LIBRARY_HOME/interface_packages/spi_s_pkg/spi_s_pkg.vinfo +@use $UVMF_VIP_LIBRARY_HOME/environment_packages/block_1_env_pkg/block_1_env_pkg.vinfo +@use $UVMF_PROJECT_DIR/tb/parameters/block_1_parameters_pkg.vinfo ++incdir+@vinfodir +block_1_sequences_pkg.sv diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_1/tb/sequences/src/block_1_bench_sequence_base.svh b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_1/tb/sequences/src/block_1_bench_sequence_base.svh new file mode 100644 index 00000000..e8490ea3 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_1/tb/sequences/src/block_1_bench_sequence_base.svh @@ -0,0 +1,146 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// Description: This file contains the top level and utility sequences +// used by test_top. It can be extended to create derivative top +// level sequences. +// +//---------------------------------------------------------------------- +// +//---------------------------------------------------------------------- +// +`ifndef BLOCK_1_BENCH_SEQUENCE_BASE +`define BLOCK_1_BENCH_SEQUENCE_BASE + +typedef block_1_env_configuration block_1_env_configuration_t; + +class block_1_bench_sequence_base extends uvmf_sequence_base #(uvm_sequence_item); + + `uvm_object_utils( block_1_bench_sequence_base ); + + // pragma uvmf custom sequences begin + +typedef block_1_env_sequence_base #( + .CONFIG_T(block_1_env_configuration_t) + ) + block_1_env_sequence_base_t; +rand block_1_env_sequence_base_t block_1_env_seq; + + + + // UVMF_CHANGE_ME : Instantiate, construct, and start sequences as needed to create stimulus scenarios. + // Instantiate sequences here + typedef apb_m_random_sequence apb_master_random_seq_t; + apb_master_random_seq_t apb_master_random_seq; + typedef axi_m_random_sequence axi_master1_random_seq_t; + axi_master1_random_seq_t axi_master1_random_seq; + typedef axi_m_random_sequence axi_master2_random_seq_t; + axi_master2_random_seq_t axi_master2_random_seq; + // pragma uvmf custom sequences end + + // Sequencer handles for each active interface in the environment + typedef apb_m_transaction apb_master_transaction_t; + uvm_sequencer #(apb_master_transaction_t) apb_master_sequencer; + typedef axi_m_transaction axi_master1_transaction_t; + uvm_sequencer #(axi_master1_transaction_t) axi_master1_sequencer; + typedef axi_m_transaction axi_master2_transaction_t; + uvm_sequencer #(axi_master2_transaction_t) axi_master2_sequencer; + + + // Top level environment configuration handle + block_1_env_configuration_t top_configuration; + + // Configuration handles to access interface BFM's + apb_m_configuration apb_master_config; + axi_m_configuration axi_master1_config; + axi_m_configuration axi_master2_config; + spi_s_configuration spi_slave_config; + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + // **************************************************************************** + function new( string name = "" ); + super.new( name ); + // Retrieve the configuration handles from the uvm_config_db + + // Retrieve top level configuration handle + if ( !uvm_config_db#(block_1_env_configuration_t)::get(null,UVMF_CONFIGURATIONS, "TOP_ENV_CONFIG",top_configuration) ) begin + `uvm_info("CFG", "*** FATAL *** uvm_config_db::get can not find TOP_ENV_CONFIG. Are you using an older UVMF release than what was used to generate this bench?",UVM_NONE); + `uvm_fatal("CFG", "uvm_config_db#(block_1_env_configuration_t)::get cannot find resource TOP_ENV_CONFIG"); + end + + // Retrieve config handles for all agents + if( !uvm_config_db #( apb_m_configuration )::get( null , UVMF_CONFIGURATIONS , apb_master_BFM , apb_master_config ) ) + `uvm_fatal("CFG" , "uvm_config_db #( apb_m_configuration )::get cannot find resource apb_master_BFM" ) + if( !uvm_config_db #( axi_m_configuration )::get( null , UVMF_CONFIGURATIONS , axi_master1_BFM , axi_master1_config ) ) + `uvm_fatal("CFG" , "uvm_config_db #( axi_m_configuration )::get cannot find resource axi_master1_BFM" ) + if( !uvm_config_db #( axi_m_configuration )::get( null , UVMF_CONFIGURATIONS , axi_master2_BFM , axi_master2_config ) ) + `uvm_fatal("CFG" , "uvm_config_db #( axi_m_configuration )::get cannot find resource axi_master2_BFM" ) + if( !uvm_config_db #( spi_s_configuration )::get( null , UVMF_CONFIGURATIONS , spi_slave_BFM , spi_slave_config ) ) + `uvm_fatal("CFG" , "uvm_config_db #( spi_s_configuration )::get cannot find resource spi_slave_BFM" ) + + // Assign the sequencer handles from the handles within agent configurations + apb_master_sequencer = apb_master_config.get_sequencer(); + axi_master1_sequencer = axi_master1_config.get_sequencer(); + axi_master2_sequencer = axi_master2_config.get_sequencer(); + + + + // pragma uvmf custom new begin + // pragma uvmf custom new end + + endfunction + + // **************************************************************************** + virtual task body(); + // pragma uvmf custom body begin + + // Construct sequences here + + block_1_env_seq = block_1_env_sequence_base_t::type_id::create("block_1_env_seq"); + + apb_master_random_seq = apb_master_random_seq_t::type_id::create("apb_master_random_seq"); + axi_master1_random_seq = axi_master1_random_seq_t::type_id::create("axi_master1_random_seq"); + axi_master2_random_seq = axi_master2_random_seq_t::type_id::create("axi_master2_random_seq"); + fork + apb_master_config.wait_for_reset(); + axi_master1_config.wait_for_reset(); + axi_master2_config.wait_for_reset(); + spi_slave_config.wait_for_reset(); + join + // Start RESPONDER sequences here + fork + join_none + // Start INITIATOR sequences here + fork + repeat (25) apb_master_random_seq.start(apb_master_sequencer); + repeat (25) axi_master1_random_seq.start(axi_master1_sequencer); + repeat (25) axi_master2_random_seq.start(axi_master2_sequencer); + join + +block_1_env_seq.start(top_configuration.vsqr); + + // UVMF_CHANGE_ME : Extend the simulation XXX number of clocks after + // the last sequence to allow for the last sequence item to flow + // through the design. + fork + apb_master_config.wait_for_num_clocks(400); + axi_master1_config.wait_for_num_clocks(400); + axi_master2_config.wait_for_num_clocks(400); + spi_slave_config.wait_for_num_clocks(400); + join + + // pragma uvmf custom body end + endtask + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end +`endif diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_1/tb/sequences/src/example_derived_test_sequence.svh b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_1/tb/sequences/src/example_derived_test_sequence.svh new file mode 100644 index 00000000..ee68cd86 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_1/tb/sequences/src/example_derived_test_sequence.svh @@ -0,0 +1,31 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +// +//---------------------------------------------------------------------- +// +// DESCRIPTION: This file contains the top level sequence used in example_derived_test. +// It is an example of a sequence that is extended from %(benchName)_bench_sequence_base +// and can override %(benchName)_bench_sequence_base. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +`ifndef EXAMPLE_DERIVED_TEST_SEQUENCE +`define EXAMPLE_DERIVED_TEST_SEQUENCE +class example_derived_test_sequence extends block_1_bench_sequence_base; + + `uvm_object_utils( example_derived_test_sequence ); + + function new(string name = "" ); + super.new(name); + endfunction + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end +`endif diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_1/tb/sequences/src/register_test_sequence.svh b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_1/tb/sequences/src/register_test_sequence.svh new file mode 100644 index 00000000..3751ac29 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_1/tb/sequences/src/register_test_sequence.svh @@ -0,0 +1,60 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This file contains the top level sequence used in register_test. +// It uses the UVM built in register test. Specific UVM built-in tests can be +// selected in the body task. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +`ifndef REGISTER_TEST_SEQUENCE +`define REGISTER_TEST_SEQUENCE +class register_test_sequence extends block_1_bench_sequence_base; + + `uvm_object_utils( register_test_sequence ); + + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + function new(string name = "" ); + super.new(name); + endfunction + + // **************************************************************************** + virtual task body(); + + // Reset the DUT + fork + // pragma uvmf custom register_test_reset begin + // UVMF_CHANGE_ME + // Select the desired wait_for_reset or provide custom mechanism. + // fork-join for this code block may be unnecessary based on your situation. + apb_master_config.wait_for_reset(); + axi_master1_config.wait_for_reset(); + axi_master2_config.wait_for_reset(); + spi_slave_config.wait_for_reset(); + // pragma uvmf custom register_test_reset end + join + + // pragma uvmf custom register_test_setup begin + // UVMF_CHANGE_ME perform potentially necessary operations before running the sequence. + // pragma uvmf custom register_test_setup end + + // pragma uvmf custom register_test_operation begin + // UVMF_CHANGE_ME Perform your custom register test + // pragma uvmf custom register_test_operation end + + endtask + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end +`endif diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_1/tb/testbench/hdl_top.compile b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_1/tb/testbench/hdl_top.compile new file mode 100644 index 00000000..09b570fb --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_1/tb/testbench/hdl_top.compile @@ -0,0 +1,11 @@ +incdir: + - ${uvm_path}/src + - . +needs: + - $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg_hdl.compile + - ../parameters/block_1_parameters_pkg.compile + - ../../../../verification_ip/interface_packages/apb_m_pkg/apb_m_hdl.compile + - ../../../../verification_ip/interface_packages/axi_m_pkg/axi_m_hdl.compile + - ../../../../verification_ip/interface_packages/spi_s_pkg/spi_s_hdl.compile +src: + - hdl_top.sv diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_1/tb/testbench/hdl_top.sv b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_1/tb/testbench/hdl_top.sv new file mode 100644 index 00000000..d8645a94 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_1/tb/testbench/hdl_top.sv @@ -0,0 +1,117 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// Description: This top level module instantiates all synthesizable +// static content. This and tb_top.sv are the two top level modules +// of the simulation. +// +// This module instantiates the following: +// DUT: The Design Under Test +// Interfaces: Signal bundles that contain signals connected to DUT +// Driver BFM's: BFM's that actively drive interface signals +// Monitor BFM's: BFM's that passively monitor interface signals +// +//---------------------------------------------------------------------- + +//---------------------------------------------------------------------- +// + +module hdl_top; + +import block_1_parameters_pkg::*; +import uvmf_base_pkg_hdl::*; + + // pragma attribute hdl_top partition_module_xrtl +// pragma uvmf custom clock_generator begin + bit clk; + // Instantiate a clk driver + // tbx clkgen + initial begin + clk = 0; + #9ns; + forever begin + clk = ~clk; + #5ns; + end + end +// pragma uvmf custom clock_generator end + +// pragma uvmf custom reset_generator begin + bit rst; + // Instantiate a rst driver + // tbx clkgen + initial begin + rst = 1; + #200ns; + rst = 0; + end +// pragma uvmf custom reset_generator end + + // pragma uvmf custom module_item_additional begin + // pragma uvmf custom module_item_additional end + + // Instantiate the signal bundle, monitor bfm and driver bfm for each interface. + // The signal bundle, _if, contains signals to be connected to the DUT. + // The monitor, monitor_bfm, observes the bus, _if, and captures transactions. + // The driver, driver_bfm, drives transactions onto the bus, _if. + apb_m_if apb_master_bus( + // pragma uvmf custom apb_master_bus_connections begin + .pclk(clk), .presetn(rst) + // pragma uvmf custom apb_master_bus_connections end + ); + axi_m_if axi_master1_bus( + // pragma uvmf custom axi_master1_bus_connections begin + .axi_clk(clk), .rst(rst) + // pragma uvmf custom axi_master1_bus_connections end + ); + axi_m_if axi_master2_bus( + // pragma uvmf custom axi_master2_bus_connections begin + .axi_clk(clk), .rst(rst) + // pragma uvmf custom axi_master2_bus_connections end + ); + spi_s_if spi_slave_bus( + // pragma uvmf custom spi_slave_bus_connections begin + .sck(clk), .rst(rst) + // pragma uvmf custom spi_slave_bus_connections end + ); + apb_m_monitor_bfm apb_master_mon_bfm(apb_master_bus.monitor_port); + axi_m_monitor_bfm axi_master1_mon_bfm(axi_master1_bus.monitor_port); + axi_m_monitor_bfm axi_master2_mon_bfm(axi_master2_bus.monitor_port); + spi_s_monitor_bfm spi_slave_mon_bfm(spi_slave_bus.monitor_port); + apb_m_driver_bfm apb_master_drv_bfm(apb_master_bus.initiator_port); + axi_m_driver_bfm axi_master1_drv_bfm(axi_master1_bus.initiator_port); + axi_m_driver_bfm axi_master2_drv_bfm(axi_master2_bus.initiator_port); + + // pragma uvmf custom dut_instantiation begin + // UVMF_CHANGE_ME : Add DUT and connect to signals in _bus interfaces listed above + // Instantiate your DUT here + // These DUT's instantiated to show verilog and vhdl instantiation + verilog_dut dut_verilog( .clk(clk), .rst(rst), .in_signal(vhdl_to_verilog_signal), .out_signal(verilog_to_vhdl_signal)); + vhdl_dut dut_vhdl ( .clk(clk), .rst(rst), .in_signal(verilog_to_vhdl_signal), .out_signal(vhdl_to_verilog_signal)); + // pragma uvmf custom dut_instantiation end + + initial begin // tbx vif_binding_block + import uvm_pkg::uvm_config_db; + // The monitor_bfm and driver_bfm for each interface is placed into the uvm_config_db. + // They are placed into the uvm_config_db using the string names defined in the parameters package. + // The string names are passed to the agent configurations by test_top through the top level configuration. + // They are retrieved by the agents configuration class for use by the agent. + uvm_config_db #( virtual apb_m_monitor_bfm )::set( null , UVMF_VIRTUAL_INTERFACES , apb_master_BFM , apb_master_mon_bfm ); + uvm_config_db #( virtual axi_m_monitor_bfm )::set( null , UVMF_VIRTUAL_INTERFACES , axi_master1_BFM , axi_master1_mon_bfm ); + uvm_config_db #( virtual axi_m_monitor_bfm )::set( null , UVMF_VIRTUAL_INTERFACES , axi_master2_BFM , axi_master2_mon_bfm ); + uvm_config_db #( virtual spi_s_monitor_bfm )::set( null , UVMF_VIRTUAL_INTERFACES , spi_slave_BFM , spi_slave_mon_bfm ); + uvm_config_db #( virtual apb_m_driver_bfm )::set( null , UVMF_VIRTUAL_INTERFACES , apb_master_BFM , apb_master_drv_bfm ); + uvm_config_db #( virtual axi_m_driver_bfm )::set( null , UVMF_VIRTUAL_INTERFACES , axi_master1_BFM , axi_master1_drv_bfm ); + uvm_config_db #( virtual axi_m_driver_bfm )::set( null , UVMF_VIRTUAL_INTERFACES , axi_master2_BFM , axi_master2_drv_bfm ); + end + +endmodule + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_1/tb/testbench/hdl_top.vinfo b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_1/tb/testbench/hdl_top.vinfo new file mode 100644 index 00000000..43c7c76e --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_1/tb/testbench/hdl_top.vinfo @@ -0,0 +1,7 @@ +@use $UVMF_PROJECT_DIR/rtl/verilog/verilog_dut.vinfo +@use $UVMF_PROJECT_DIR/tb/parameters/block_1_parameters_pkg.vinfo +@use $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg_hdl.vinfo +@use $UVMF_VIP_LIBRARY_HOME/interface_packages/apb_m_pkg/apb_m_bfm.vinfo +@use $UVMF_VIP_LIBRARY_HOME/interface_packages/axi_m_pkg/axi_m_bfm.vinfo +@use $UVMF_VIP_LIBRARY_HOME/interface_packages/spi_s_pkg/spi_s_bfm.vinfo +hdl_top.sv diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_1/tb/testbench/hvl_top.compile b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_1/tb/testbench/hvl_top.compile new file mode 100644 index 00000000..d8d273c1 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_1/tb/testbench/hvl_top.compile @@ -0,0 +1,7 @@ +incdir: + - ${uvm_path}/src + - . +needs: + - ../tests/block_1_tests_pkg.compile +src: + - hvl_top.sv diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_1/tb/testbench/hvl_top.sv b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_1/tb/testbench/hvl_top.sv new file mode 100644 index 00000000..89ae61f4 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_1/tb/testbench/hvl_top.sv @@ -0,0 +1,33 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +// +//---------------------------------------------------------------------- +// +// DESCRIPTION: This module loads the test package and starts the UVM phases. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// + +module hvl_top; + +import uvm_pkg::*; +import block_1_tests_pkg::*; + + // pragma uvmf custom module_item_additional begin + // pragma uvmf custom module_item_additional end + + initial begin + $timeformat(-9,3,"ns",5); + run_test(); + end + +endmodule + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_1/tb/testbench/hvl_top.vinfo b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_1/tb/testbench/hvl_top.vinfo new file mode 100644 index 00000000..7bc43d3a --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_1/tb/testbench/hvl_top.vinfo @@ -0,0 +1,2 @@ +@use $UVMF_PROJECT_DIR/tb/tests/block_1_tests_pkg.vinfo +hvl_top.sv diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_1/tb/testbench/top_filelist_hdl.f b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_1/tb/testbench/top_filelist_hdl.f new file mode 100644 index 00000000..1e9dab65 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_1/tb/testbench/top_filelist_hdl.f @@ -0,0 +1,3 @@ +$UVMF_PROJECT_DIR/tb/testbench/hdl_top.sv +// pragma uvmf custom additional begin +// pragma uvmf custom additional end diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_1/tb/testbench/top_filelist_hvl.f b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_1/tb/testbench/top_filelist_hvl.f new file mode 100644 index 00000000..42383ab2 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_1/tb/testbench/top_filelist_hvl.f @@ -0,0 +1,3 @@ +$UVMF_PROJECT_DIR/tb/testbench/hvl_top.sv +// pragma uvmf custom additional begin +// pragma uvmf custom additional end diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_1/tb/tests/block_1_tests_pkg.compile b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_1/tb/tests/block_1_tests_pkg.compile new file mode 100644 index 00000000..ccf235f0 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_1/tb/tests/block_1_tests_pkg.compile @@ -0,0 +1,10 @@ +needs: + - $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg.compile + - ../../../../verification_ip/interface_packages/apb_m_pkg/apb_m.compile + - ../../../../verification_ip/interface_packages/axi_m_pkg/axi_m.compile + - ../../../../verification_ip/interface_packages/spi_s_pkg/spi_s.compile + - ../../../../verification_ip/environment_packages/block_1_env_pkg/block_1_env_pkg.compile + - ../parameters/block_1_parameters_pkg.compile + - ../sequences/block_1_sequences_pkg.compile +src: + - block_1_tests_pkg.sv diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_1/tb/tests/block_1_tests_pkg.sv b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_1/tb/tests/block_1_tests_pkg.sv new file mode 100644 index 00000000..282f65ba --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_1/tb/tests/block_1_tests_pkg.sv @@ -0,0 +1,57 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This package contains all tests currently written for +// the simulation project. Once compiled, any test can be selected +// from the vsim command line using +UVM_TESTNAME=yourTestNameHere +// +// CONTAINS: +// - +// - +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +`ifndef BLOCK_1_TESTS_PKG +`define BLOCK_1_TESTS_PKG +package block_1_tests_pkg; + + import uvm_pkg::*; + import uvmf_base_pkg::*; + import block_1_parameters_pkg::*; + import block_1_env_pkg::*; + import block_1_sequences_pkg::*; + import apb_m_pkg::*; + import apb_m_pkg_hdl::*; + import axi_m_pkg::*; + import axi_m_pkg_hdl::*; + import spi_s_pkg::*; + import spi_s_pkg_hdl::*; + + + `include "uvm_macros.svh" + + // pragma uvmf custom package_imports_additional begin + // pragma uvmf custom package_imports_additional end + + `include "src/test_top.svh" + `include "src/register_test.svh" + `include "src/example_derived_test.svh" + + // pragma uvmf custom package_item_additional begin + // UVMF_CHANGE_ME : When adding new tests to the src directory + // be sure to add the test file here so that it will be + // compiled as part of the test package. Be sure to place + // the new test after any base tests of the new test. + // pragma uvmf custom package_item_additional end + +endpackage + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_1/tb/tests/block_1_tests_pkg.vinfo b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_1/tb/tests/block_1_tests_pkg.vinfo new file mode 100644 index 00000000..9fe7bfbf --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_1/tb/tests/block_1_tests_pkg.vinfo @@ -0,0 +1,9 @@ +@use $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg.vinfo +@use $UVMF_VIP_LIBRARY_HOME/interface_packages/apb_m_pkg/apb_m_pkg.vinfo +@use $UVMF_VIP_LIBRARY_HOME/interface_packages/axi_m_pkg/axi_m_pkg.vinfo +@use $UVMF_VIP_LIBRARY_HOME/interface_packages/spi_s_pkg/spi_s_pkg.vinfo +@use $UVMF_VIP_LIBRARY_HOME/environment_packages/block_1_env_pkg/block_1_env_pkg.vinfo +@use $UVMF_PROJECT_DIR/tb/parameters/block_1_parameters_pkg.vinfo +@use $UVMF_PROJECT_DIR/tb/sequences/block_1_sequences_pkg.vinfo ++incdir+@vinfodir +block_1_tests_pkg.sv diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_1/tb/tests/src/example_derived_test.svh b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_1/tb/tests/src/example_derived_test.svh new file mode 100644 index 00000000..3284fba2 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_1/tb/tests/src/example_derived_test.svh @@ -0,0 +1,44 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This test extends test_top and makes +// changes to test_top using the UVM factory type_override: +// +// Test scenario: +// This is a template test that can be used to create future tests. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +`ifndef EXAMPLE_DERIVED_TEST +`define EXAMPLE_DERIVED_TEST +class example_derived_test extends test_top; + + `uvm_component_utils( example_derived_test ); + + function new( string name = "", uvm_component parent = null ); + super.new( name, parent ); + endfunction + + virtual function void build_phase(uvm_phase phase); + // The factory override below is an example of how to replace the block_1_bench_sequence_base + // sequence with the example_derived_test_sequence. + block_1_bench_sequence_base::type_id::set_type_override(example_derived_test_sequence::get_type()); + // Execute the build_phase of test_top AFTER all factory overrides have been created. + super.build_phase(phase); + // pragma uvmf custom configuration_settings_post_randomize begin + // UVMF_CHANGE_ME Test specific configuration values can be set here. + // The configuration structure has already been randomized. + // pragma uvmf custom configuration_settings_post_randomize end + endfunction + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end +`endif diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_1/tb/tests/src/register_test.svh b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_1/tb/tests/src/register_test.svh new file mode 100644 index 00000000..09a76da4 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_1/tb/tests/src/register_test.svh @@ -0,0 +1,41 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This test extends test_top and makes +// changes to test_top using the UVM factory type_override: +// +// Test scenario: +// This is a template test that can be used to create future tests. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +`ifndef REGISTER_TEST +`define REGISTER_TEST +class register_test extends test_top; + + `uvm_component_utils( register_test ); + + function new( string name = "", uvm_component parent = null ); + super.new( name, parent ); + endfunction + + virtual function void build_phase(uvm_phase phase); + // The factory override below replaces the block_1_bench_sequence_base + // sequence with the register_test_sequence. + block_1_bench_sequence_base::type_id::set_type_override(register_test_sequence::get_type()); + // Execute the build_phase of test_top AFTER all factory overrides have been created. + super.build_phase(phase); + endfunction + + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end +`endif diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_1/tb/tests/src/test_top.svh b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_1/tb/tests/src/test_top.svh new file mode 100644 index 00000000..4bcecee7 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_1/tb/tests/src/test_top.svh @@ -0,0 +1,83 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// Description: This top level UVM test is the base class for all +// future tests created for this project. +// +// This test class contains: +// Configuration: The top level configuration for the project. +// Environment: The top level environment for the project. +// Top_level_sequence: The top level sequence for the project. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// + +typedef block_1_env_configuration block_1_env_configuration_t; +typedef block_1_environment block_1_environment_t; +`ifndef TEST_TOP +`define TEST_TOP +class test_top extends uvmf_test_base #(.CONFIG_T(block_1_env_configuration_t), + .ENV_T(block_1_environment_t), + .TOP_LEVEL_SEQ_T(block_1_bench_sequence_base)); + + `uvm_component_utils( test_top ); + + + + string interface_names[] = { + apb_master_BFM /* apb_master [0] */ , + axi_master1_BFM /* axi_master1 [1] */ , + axi_master2_BFM /* axi_master2 [2] */ , + spi_slave_BFM /* spi_slave [3] */ +}; + +uvmf_active_passive_t interface_activities[] = { + ACTIVE /* apb_master [0] */ , + ACTIVE /* axi_master1 [1] */ , + ACTIVE /* axi_master2 [2] */ , + PASSIVE /* spi_slave [3] */ }; + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + // **************************************************************************** + // FUNCTION: new() + // This is the standard systemVerilog constructor. All components are + // constructed in the build_phase to allow factory overriding. + // + function new( string name = "", uvm_component parent = null ); + super.new( name ,parent ); + endfunction + + + + // **************************************************************************** + // FUNCTION: build_phase() + // The construction of the configuration and environment classes is done in + // the build_phase of uvmf_test_base. Once the configuraton and environment + // classes are built then the initialize call is made to perform the + // following: + // Monitor and driver BFM virtual interface handle passing into agents + // Set the active/passive state for each agent + // Once this build_phase completes, the build_phase of the environment is + // executed which builds the agents. + // + virtual function void build_phase(uvm_phase phase); +// pragma uvmf custom build_phase_pre_super begin +// pragma uvmf custom build_phase_pre_super end + super.build_phase(phase); + // pragma uvmf custom configuration_settings_post_randomize begin + // pragma uvmf custom configuration_settings_post_randomize end + configuration.initialize(NA, "uvm_test_top.environment", interface_names, null, interface_activities); + endfunction + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end +`endif diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_1/yaml/block_1_bench.yaml b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_1/yaml/block_1_bench.yaml new file mode 100644 index 00000000..81d1e38d --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_1/yaml/block_1_bench.yaml @@ -0,0 +1,21 @@ +uvmf: + benches: + block_1: + active_passive: + - bfm_name: apb_master + value: ACTIVE + - bfm_name: axi_master1 + value: ACTIVE + - bfm_name: axi_master2 + value: ACTIVE + - bfm_name: spi_slave + value: PASSIVE + active_passive_default: ACTIVE + clock_half_period: 5ns + clock_phase_offset: 9ns + existing_library_component: 'True' + interface_params: [] + reset_assertion_level: 'True' + reset_duration: 200ns + top_env: block_1 + use_dpi_link: 'False' diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_2/.project b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_2/.project new file mode 100644 index 00000000..e070225f --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_2/.project @@ -0,0 +1,37 @@ + + + block_2 + + + + + + org.python.pydev.PyDevBuilder + + + + + net.sf.sveditor.core.SVProjectBuilder + + + + + + net.sf.sveditor.core.SVNature + org.python.pydev.pythonNature + + + + verification_ip + 2 + UVMF_VIP_LIBRARY_HOME + + + + + UVMF_VIP_LIBRARY_HOME + $%7BPARENT-2-PROJECT_LOC%7D/verification_ip + + + + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_2/.svproject b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_2/.svproject new file mode 100644 index 00000000..b5a7f95a --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_2/.svproject @@ -0,0 +1,16 @@ + + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_2/block_2_sve.F b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_2/block_2_sve.F new file mode 100644 index 00000000..83f3e49e --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_2/block_2_sve.F @@ -0,0 +1,28 @@ + +// UVM ++incdir+${UVM_HOME}/src +${UVM_HOME}/src/uvm_pkg.sv + +// Common UVMF files +-f ${UVMF_HOME}/common/common_sve.f + +// BFM Files +-F ${UVMF_VIP_LIBRARY_HOME}/interface_packages/spi_m_pkg/spi_m_pkg_sve.F +-F ${UVMF_VIP_LIBRARY_HOME}/interface_packages/wb_s_pkg/wb_s_pkg_sve.F + +// Environment Files +-F ${UVMF_VIP_LIBRARY_HOME}/environment_packages/block_2_env_pkg/block_2_env_pkg_sve.F + +// Bench Files ++incdir+./tb/tests +./tb/tests/block_2_tests_pkg.sv + ++incdir+./tb/sequences +./tb/sequences/block_2_sequences_pkg.sv + ++incdir+./tb/parameters +./tb/parameters/block_2_parameters_pkg.sv + +./tb/testbench/hdl_top.sv +./tb/testbench/hvl_top.sv + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_2/docs/interfaces.csv b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_2/docs/interfaces.csv new file mode 100644 index 00000000..de1a17a2 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_2/docs/interfaces.csv @@ -0,0 +1,14 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// + +, +Interface Description, Interface Type, Interface Transaction, Interface Name, +spi_master, spi_m_driver_bfm spi_m_monitor_bfm, spi_m_transaction, spi_m_pkg_spi_master_BFM, +wb_slave, wb_s_driver_bfm wb_s_monitor_bfm, wb_s_transaction, wb_s_pkg_wb_slave_BFM, + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_2/rtl/dut.compile b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_2/rtl/dut.compile new file mode 100644 index 00000000..9b0008fc --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_2/rtl/dut.compile @@ -0,0 +1,6 @@ + +# pragma uvmf custom dut_compile_info begin +src: + - ./vhdl/vhdl_dut.vhd + - ./verilog/verilog_dut.v +# pragma uvmf custom dut_compile_info end diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_2/rtl/verilog/verilog_dut.v b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_2/rtl/verilog/verilog_dut.v new file mode 100644 index 00000000..96198441 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_2/rtl/verilog/verilog_dut.v @@ -0,0 +1,21 @@ +module verilog_dut(clk, rst, in_signal, out_signal); + +input clk; +input rst; +input in_signal; +output out_signal; + +reg out_signal_o; + +always @(posedge clk) begin + if (rst) begin + out_signal_o <= 0; + end + else begin + out_signal_o <= ~in_signal; + end + end + +assign out_signal = out_signal_o; + +endmodule diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_2/rtl/verilog/verilog_dut.vinfo b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_2/rtl/verilog/verilog_dut.vinfo new file mode 100644 index 00000000..87e95f36 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_2/rtl/verilog/verilog_dut.vinfo @@ -0,0 +1 @@ +verilog_dut.v diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_2/rtl/vhdl/vhdl_dut.vhd b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_2/rtl/vhdl/vhdl_dut.vhd new file mode 100644 index 00000000..904aa37d --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_2/rtl/vhdl/vhdl_dut.vhd @@ -0,0 +1,21 @@ +library ieee; +use ieee.std_logic_1164.all ; + +entity vhdl_dut is + port ( clk : in std_logic ; + rst : in std_logic ; + in_signal : in std_logic ; + out_signal :out std_logic + ); +end vhdl_dut; + +architecture rtl of vhdl_dut is + begin + P1: process + variable out_signal_o : std_logic; + begin + wait until clk'event and clk = '1'; + out_signal_o := in_signal; + out_signal <= out_signal_o; + end process; + end rtl; diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_2/sim/Makefile b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_2/sim/Makefile new file mode 100644 index 00000000..4bea4673 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_2/sim/Makefile @@ -0,0 +1,199 @@ + +# +#---------------------------------------------------------------------- +# +# DESCRIPTION: This makefile includes the shared makefile and contains +# bench level make targets. +# +#---------------------------------------------------------------------- + + +# pragma uvmf custom additional begin +# pragma uvmf custom additional end + +# ********************************************************************************************* +# UVMF library directory: +# This variable points to the UVMF release where uvmf_base_pkg directory resides. +# This variable points to release code that is not user modified. +# This variable allows for UVMF release directories to reside independent of project related verification IP and project bench directories. +# This code below looks "upward" for directory starting with UVMF_* and returns first match for use with the release examples. +UVMF_HOME ?= ___PLEASE_SET_AN_ENVIRONMENT_VARIABLE_NAMED_UVMF_HOME_TO_POINT_TO_THE_UVMF_INSTALLATION___ + +# pragma uvmf custom exports begin +# +# Project(s) specific verification IP library: +# Directory where reusable verification packages for interfaces, environments, utilities, etc. reside. +# This variable allows for your verification IP to reside independent of project bench and UVMF release directories. +# For examples deployed with UVMF this will be $(UVMF_HOME)//verification_ip +export UVMF_VIP_LIBRARY_HOME ?= $(PWD)/../../../verification_ip +# +# Project specific bench: +# Directory where bench specific code is located. +# This variable allows for project_benches to reside independent of verification IP and UVMF release directories. +# For examples deployed with UVMF this will be $(UVMF_HOME)//project_benches/ +export UVMF_PROJECT_DIR ?= $(PWD)/.. +# +# +# pragma uvmf custom exports end +# ********************************************************************************************* + +## Check PATH for required vinfo scripts +PVAL := $(shell command -v make_filelist.py 2> /dev/null) +ifndef PVAL + MFLIST = $(UVMF_HOME)/scripts/make_filelist.py +else + MFLIST = make_filelist.py +endif + + +# Set test case specific Variables +TEST_NAME ?= test_top + +TEST_SEED ?= random +UVM_CLI_ARGS = + +# Usage of Veloce, etc. to be input by the user (subject to defaults) +USE_VELOCE ?= 0 + +# Usage of vinfo flow for generating file list +USE_VINFO ?= 0 + +# Usage of Veloce and Questa profilers +USE_VELOCE_PROFILER ?= 0 +USE_QUESTA_PROFILER ?= 0 + + +# Set project Variables +TEST_PLAN_NAME = block_2_TestPlan +REPORTING_DO_FILE = block_2_reports_script + + +# Include makefile that includes targets for UVM_VIP_Library packages +include $(UVMF_HOME)/scripts/Makefile + + + + +# Include all requisite interface package targets for this bench +include $(UVMF_VIP_LIBRARY_HOME)/interface_packages/spi_m_pkg/Makefile +include $(UVMF_VIP_LIBRARY_HOME)/interface_packages/wb_s_pkg/Makefile + +# Include all requisite environment package targets for this bench +include $(UVMF_VIP_LIBRARY_HOME)/environment_packages/block_2_env_pkg/Makefile + + + +# Add to default compile/load/run arguments +VCOM_ARGS += + +# Note: vsim-3009 error can be eliminated by adding -timescale 1ps/1ps to VLOG_ARGS + +VLOG_ARGS += $(UVM_DISABLE_FILE_LINE_CMD) + +VELANALYZE_ARGS += +VELANALYZE_HVL_ARGS += + +BATCH_VOPT_ARGS += +DEBUG_VOPT_ARGS += +EXTRA_VOPT_TOPS += +COMMON_VSIM_ARGS += +COMMON_VSIM_ARGS += + + +BATCH_VSIM_ARGS += #-uvmcontrol=none +DEBUG_VSIM_ARGS += +EXTRA_VSIM_TOPS += + +# pragma uvmf custom additional_args begin +# pragma uvmf custom additional_args end + + +# Project bench package source +block_2_PARAMETERS_PKG ?=\ +$(UVMF_PROJECT_DIR)/tb/parameters/block_2_parameters_pkg.sv + + +block_2_SEQUENCES_PKG ?=\ +$(UVMF_PROJECT_DIR)/tb/sequences/block_2_sequences_pkg.sv + + +block_2_TEST_PKG ?=\ +$(UVMF_PROJECT_DIR)/tb/tests/block_2_tests_pkg.sv + +# pragma uvmf custom dut_files begin +# UVMF_CHANGE_ME : Reference Verilog DUT source. +block_2_VERILOG_DUT ?=\ +$(UVMF_PROJECT_DIR)/rtl/verilog/verilog_dut.v + +# UVMF_CHANGE_ME : Reference VHDL DUT source. +block_2_VHDL_DUT ?=\ +$(UVMF_PROJECT_DIR)/rtl/vhdl/vhdl_dut.vhd +# pragma uvmf custom dut_files end + + +# Project bench package targets +COMP_block_2_PARAMETERS_PKG_TGT_0 = q_comp_block_2_parameters_pkg +COMP_block_2_PARAMETERS_PKG_TGT_1 = v_comp_block_2_parameters_pkg +COMP_block_2_PARAMETERS_PKG_TGT = $(COMP_block_2_PARAMETERS_PKG_TGT_$(USE_VELOCE)) + +comp_block_2_parameters_pkg: $(COMP_block_2_PARAMETERS_PKG_TGT) + +q_comp_block_2_parameters_pkg: + $(HVL_COMP_CMD) +incdir+$(UVMF_PROJECT_DIR)/tb/parameters $(block_2_PARAMETERS_PKG) + +v_comp_block_2_parameters_pkg: q_comp_block_2_parameters_pkg + $(HDL_COMP_CMD) +incdir+$(UVMF_PROJECT_DIR)/tb/parameters $(block_2_PARAMETERS_PKG) + + +comp_block_2_sequence_pkg: + $(HVL_COMP_CMD) +incdir+$(UVMF_PROJECT_DIR)/tb/sequences $(block_2_SEQUENCES_PKG) + +comp_block_2_tests_pkg: + $(HVL_COMP_CMD) +incdir+$(UVMF_PROJECT_DIR)/tb/tests $(block_2_TEST_PKG) + +# pragma uvmf custom dut_compile_make_target begin +# UVMF_CHANGE_ME : Add make target to compile your verilog dut here +comp_block_2_verilog_dut: + echo "Compile your verilog DUT here" + $(HDL_COMP_CMD) $(block_2_VERILOG_DUT) + +# UVMF_CHANGE_ME : Add make target to compile your vhdl dut here +comp_block_2_vhdl_dut: + echo "Compile your vhdl DUT here" + $(HDL_COMP_CMD_VHDL) $(block_2_VHDL_DUT) + +# UVMF_CHANGE_ME : Add make target to compile your dut here +comp_block_2_dut: comp_block_2_vhdl_dut comp_block_2_verilog_dut +# pragma uvmf custom dut_compile_make_target end + + +BUILD_TGT_0 = make_build +BUILD_TGT_1 = vinfo_build +BUILD_TGT = $(BUILD_TGT_$(USE_VINFO)) + + +comp_hvl : comp_hvl_core + + +comp_hvl_core : \ + comp_spi_m_pkg comp_wb_s_pkg \ + comp_block_2_env_pkg \ + comp_block_2_parameters_pkg comp_block_2_sequence_pkg comp_block_2_tests_pkg + +comp_uvmf_core : comp_uvm_pkg comp_uvmf_base_pkg + +make_build: comp_block_2_dut comp_uvmf_core comp_hvl comp_test_bench + +hvl_build: q_comp_spi_m_pkg q_comp_wb_s_pkg comp_block_2_env_pkg comp_block_2_sequence_pkg comp_block_2_tests_pkg hvl_comp_testbench link optimize + + +vinfo_build: comp_block_2_vhdl_dut build_hdl_vinfo build_hvl_vinfo $(VINFO_TGT) + + $(HDL_COMP_CMD) -F hdl.vf + $(VEL_COMP) + +build: $(BUILD_TGT) + +# pragma uvmf custom additional_targets begin +# pragma uvmf custom additional_targets end + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_2/sim/bcr_testlist b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_2/sim/bcr_testlist new file mode 100644 index 00000000..5c61ad72 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_2/sim/bcr_testlist @@ -0,0 +1,19 @@ + + + +# Test list for use by RMDB file +# File syntax is +# TB_INFO { } { } +# TB ## All subsequent tests will run on this bench until a different "TB" line is seen +# TEST <1st_seed> ... +# If not enough seeds are provided then random seeds are used to pad +# If no repeat count is given, default is 1 +# pragma uvmf custom tb_info begin +TB_INFO block_2 { } { } +# pragma uvmf custom tb_info end +TB block_2 +# pragma uvmf custom regression_suite begin +TEST test_top 3 +# pragma uvmf custom regression_suite end + + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_2/sim/bcr_testlist.yaml b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_2/sim/bcr_testlist.yaml new file mode 100644 index 00000000..1a81a584 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_2/sim/bcr_testlist.yaml @@ -0,0 +1,44 @@ + + + +# YAML test list for use by RMDB file +# File syntax is +# uvmf_testlist: +# testbenches: +# - name: +# extra_build_options: +# extra_run_options: +# - name: +# ... +# - name: +# tests: +# - name: +# uvm_testname: (defaults to test_name) +# testbench: (defaults to last tb name seen) +# repeat: (defaults to 1) +# seeds: [,,...,] (defaults to all random) +# extra_test_options: +# - name: +# ... +# - name: +# include: +# - (relative path reference is to the including YAML file) +# - +# ... +# - + +uvmf_testlist: + testbenches: +# pragma uvmf custom tb_info begin + - name: block_2 + extra_build_options: "" + extra_run_options: "" +# pragma uvmf custom tb_info end + tests: + - testbench: block_2 +# pragma uvmf custom regression_suite begin + - name: test_top + repeat: 3 +# pragma uvmf custom regression_suite end + + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_2/sim/compile.do b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_2/sim/compile.do new file mode 100644 index 00000000..74950ae6 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_2/sim/compile.do @@ -0,0 +1,71 @@ + + +################################################################## +## ENVIRONMENT VARIABLES +################################################################## +quietly set ::env(UVMF_VIP_LIBRARY_HOME) ../../../verification_ip +quietly set ::env(UVMF_PROJECT_DIR) .. + +## Using VRM means that the build is occuring several more directories deeper underneath +## the sim directory, need to prepend some more '..' +if {[info exists ::env(VRM_BUILD)]} { + quietly set ::env(UVMF_VIP_LIBRARY_HOME) "../../../../../$::env(UVMF_VIP_LIBRARY_HOME)" + quietly set ::env(UVMF_PROJECT_DIR) "../../../../../$::env(UVMF_PROJECT_DIR)" +} +quietly set ::env(UVMF_VIP_LIBRARY_HOME) [file normalize $::env(UVMF_VIP_LIBRARY_HOME)] +quietly set ::env(UVMF_PROJECT_DIR) [file normalize $::env(UVMF_PROJECT_DIR)] +quietly echo "UVMF_VIP_LIBRARY_HOME = $::env(UVMF_VIP_LIBRARY_HOME)" +quietly echo "UVMF_PROJECT_DIR = $::env(UVMF_PROJECT_DIR)" + + +################################################################### +## HOUSEKEEPING : DELETE FILES THAT WILL BE REGENERATED +################################################################### +file delete -force *~ *.ucdb vsim.dbg *.vstf *.log work *.mem *.transcript.txt certe_dump.xml *.wlf covhtmlreport VRMDATA +file delete -force design.bin qwave.db dpiheader.h visualizer*.ses +file delete -force veloce.med veloce.wave veloce.map tbxbindings.h edsenv velrunopts.ini +file delete -force sv_connect.* + +################################################################### +## COMPILE DUT SOURCE CODE +################################################################### +vlib work +# pragma uvmf custom dut_compile_dofile_target begin +# UVMF_CHANGE_ME : Add commands to compile your dut here, replacing the default examples +vlog -sv -timescale 1ps/1ps -suppress 2223,2286 $env(UVMF_PROJECT_DIR)/rtl/verilog/verilog_dut.v +vcom $env(UVMF_PROJECT_DIR)/rtl/vhdl/vhdl_dut.vhd +# pragma uvmf custom dut_compile_dofile_target end + +################################################################### +## COMPILE UVMF BASE/COMMON SOURCE CODE +################################################################### +vlog -sv -timescale 1ps/1ps -suppress 2223 -suppress 2286 +incdir+$env(UVMF_HOME)/uvmf_base_pkg -F $env(UVMF_HOME)/uvmf_base_pkg/uvmf_base_pkg_filelist_hdl.f +vlog -sv -timescale 1ps/1ps -suppress 2223 -suppress 2286 +incdir+$env(UVMF_HOME)/uvmf_base_pkg -F $env(UVMF_HOME)/uvmf_base_pkg/uvmf_base_pkg_filelist_hvl.f + + +################################################################### +## UVMF INTERFACE COMPILATION +################################################################### +do $env(UVMF_VIP_LIBRARY_HOME)/interface_packages/spi_m_pkg/compile.do +do $env(UVMF_VIP_LIBRARY_HOME)/interface_packages/wb_s_pkg/compile.do + +################################################################### +## UVMF ENVIRONMENT COMPILATION +################################################################### +do $env(UVMF_VIP_LIBRARY_HOME)/environment_packages/block_2_env_pkg/compile.do + +################################################################### +## UVMF BENCHES COMPILATION +################################################################### +vlog -sv -timescale 1ps/1ps -suppress 2223 -suppress 2286 +incdir+$env(UVMF_PROJECT_DIR)/tb/parameters $env(UVMF_PROJECT_DIR)/tb/parameters/block_2_parameters_pkg.sv +vlog -sv -timescale 1ps/1ps -suppress 2223 -suppress 2286 +incdir+$env(UVMF_PROJECT_DIR)/tb/sequences $env(UVMF_PROJECT_DIR)/tb/sequences/block_2_sequences_pkg.sv +vlog -sv -timescale 1ps/1ps -suppress 2223 -suppress 2286 +incdir+$env(UVMF_PROJECT_DIR)/tb/tests $env(UVMF_PROJECT_DIR)/tb/tests/block_2_tests_pkg.sv + +vlog -sv -timescale 1ps/1ps -suppress 2223 -suppress 2286 +incdir+$env(UVMF_PROJECT_DIR)/tb/testbench -F $env(UVMF_PROJECT_DIR)/tb/testbench/top_filelist_hdl.f +vlog -sv -timescale 1ps/1ps -suppress 2223 -suppress 2286 +incdir+$env(UVMF_PROJECT_DIR)/tb/testbench -F $env(UVMF_PROJECT_DIR)/tb/testbench/top_filelist_hvl.f + +################################################################### +## OPTIMIZATION +################################################################### +vopt hvl_top hdl_top -o optimized_batch_top_tb +vopt +acc hvl_top hdl_top -o optimized_debug_top_tb diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_2/sim/hdl.compile b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_2/sim/hdl.compile new file mode 100644 index 00000000..8e7bd41a --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_2/sim/hdl.compile @@ -0,0 +1,5 @@ +needs: +# pragma uvmf custom dut_compile_info begin + - ../rtl/dut.compile +# pragma uvmf custom dut_compile_info end + - ../tb/testbench/hdl_top.compile diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_2/sim/hdl.vinfo b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_2/sim/hdl.vinfo new file mode 100644 index 00000000..da27ec77 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_2/sim/hdl.vinfo @@ -0,0 +1 @@ +@use $UVMF_PROJECT_DIR/tb/testbench/hdl_top.vinfo diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_2/sim/hvl.compile b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_2/sim/hvl.compile new file mode 100644 index 00000000..ce952549 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_2/sim/hvl.compile @@ -0,0 +1,2 @@ +needs: + - ../tb/testbench/hvl_top.compile diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_2/sim/hvl.vinfo b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_2/sim/hvl.vinfo new file mode 100644 index 00000000..d22eff33 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_2/sim/hvl.vinfo @@ -0,0 +1 @@ +@use $UVMF_PROJECT_DIR/tb/testbench/hvl_top.vinfo diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_2/sim/run.do b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_2/sim/run.do new file mode 100644 index 00000000..101ddc48 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_2/sim/run.do @@ -0,0 +1,21 @@ + + +quietly set svLibs "" +quietly set extra_vsim_args "" + +################################################################### +## Check for additional vsim arguments passed using env var $UVMF_EXTRA_VSIM_ARGS +################################################################### +if {[info exists ::env(UVMF_EXTRA_VSIM_ARGS)]} { + echo "Adding more args to vsim command" + quietly set extra_vsim_args $::env(UVMF_EXTRA_VSIM_ARGS) +} + +################################################################## +## Launch Questa : generate vsim command line and execute +################################################################## +# pragma uvmf custom dut_run_dofile_target begin +# UVMF_CHANGE_ME : Change the UVM_TESTNAME plusarg to run a different test +quietly set cmd [format "vsim -i -sv_seed random +UVM_TESTNAME=test_top +UVM_VERBOSITY=UVM_HIGH -permit_unmatched_virtual_intf +notimingchecks -suppress 8887 %s %s -uvmcontrol=all -msgmode both -classdebug -assertdebug +uvm_set_config_int=*,enable_transaction_viewing,1 -do { set NoQuitOnFinish 1; onbreak {resume}; run 0; do wave.do; set PrefSource(OpenOnBreak) 0; radix hex showbase; } optimized_debug_top_tb" $svLibs $extra_vsim_args] +# pragma uvmf custom dut_run_dofile_target end +eval $cmd diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_2/sim/tbx.config b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_2/sim/tbx.config new file mode 100644 index 00000000..eec58168 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_2/sim/tbx.config @@ -0,0 +1,10 @@ + + + + + +comp -questa +velsyn -D1S +rtlc -allow_4ST + + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_2/sim/testlist b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_2/sim/testlist new file mode 100644 index 00000000..f92fb15b --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_2/sim/testlist @@ -0,0 +1,20 @@ + + + + +# Test list for use by RMDB file +# File syntax is +# TB_INFO { } { } +# TB ## All subsequent tests will run on this bench until a different "TB" line is seen +# TEST <1st_seed> ... +# If not enough seeds are provided then random seeds are used to pad +# If no repeat count is given, default is 1 +# pragma uvmf custom tb_info begin +TB_INFO block_2 { UVMF_VIP_LIBRARY_HOME=../../../../../../../../verification_ip UVMF_PROJECT_DIR=../../../../../../../block_2 } { } +# pragma uvmf custom tb_info end +TB block_2 +# pragma uvmf custom regression_suite begin +TEST test_top 3 +# pragma uvmf custom regression_suite end + + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_2/sim/testlist.yaml b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_2/sim/testlist.yaml new file mode 100644 index 00000000..f6cabad6 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_2/sim/testlist.yaml @@ -0,0 +1,44 @@ + + + +# YAML test list for use by RMDB file +# File syntax is +# uvmf_testlist: +# testbenches: +# - name: +# extra_build_options: +# extra_run_options: +# - name: +# ... +# - name: +# tests: +# - name: +# uvm_testname: (defaults to test_name) +# testbench: (defaults to last tb name seen) +# repeat: (defaults to 1) +# seeds: [,,...,] (defaults to all random) +# extra_test_options: +# - name: +# ... +# - name: +# include: +# - (relative path reference is to the including YAML file) +# - +# ... +# - + +uvmf_testlist: + testbenches: +# pragma uvmf custom tb_info begin + - name: block_2 + extra_build_options: "UVMF_VIP_LIBRARY_HOME=../../../../../../../../verification_ip UVMF_PROJECT_DIR=../../../../../../../block_2" + extra_run_options: "" +# pragma uvmf custom tb_info end + tests: + - testbench: block_2 +# pragma uvmf custom regression_suite begin + - name: test_top + repeat: 3 +# pragma uvmf custom regression_suite end + + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_2/sim/top.compile b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_2/sim/top.compile new file mode 100644 index 00000000..efd51c07 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_2/sim/top.compile @@ -0,0 +1,3 @@ +needs: + - hvl.compile + - hdl.compile diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_2/sim/veloce.config b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_2/sim/veloce.config new file mode 100644 index 00000000..d0975155 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_2/sim/veloce.config @@ -0,0 +1,26 @@ + + + + + +# pragma uvmf custom additional begin +comp -num_boards 1 +comp -hvl questa +# Please choose the correct emulator type code for +# comp -platform command or else velcomp will fail +# Available types are: +# - Veloce2 Quattro: D2 +# - Veloce2 Maximus: D2M +# - Veloce Strato TiL, Ti, and Mi: Strato +# - Veloce Strato M and Strato T: StratoM +# - comp -platform +comp -platform Strato + +rtlc -enable_tbx_pragma_checks +rtlc -allow_4ST +rtlc -allow_MDR +rtlc -compile_display +rtlc -xwave_siglist xwaves.sigs +# pragma uvmf custom additional end + + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_2/sim/viswave.do b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_2/sim/viswave.do new file mode 100644 index 00000000..e6989769 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_2/sim/viswave.do @@ -0,0 +1,22 @@ + + +onerror resume +wave tags F0 +wave update off + +wave spacer -backgroundcolor Salmon { spi_master } +wave add uvm_test_top.environment.spi_master.spi_master_monitor.txn_stream -radix string -tag F0 +wave group spi_master_bus +wave add -group spi_master_bus hdl_top.spi_master_bus.* -radix hexadecimal -tag F0 +wave group spi_master_bus -collapse +wave insertion [expr [wave index insertpoint] +1] +wave spacer -backgroundcolor Salmon { wb_slave } +wave add uvm_test_top.environment.wb_slave.wb_slave_monitor.txn_stream -radix string -tag F0 +wave group wb_slave_bus +wave add -group wb_slave_bus hdl_top.wb_slave_bus.* -radix hexadecimal -tag F0 +wave group wb_slave_bus -collapse +wave insertion [expr [wave index insertpoint] +1] + +wave update on +WaveSetStreamView + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_2/sim/wave.do b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_2/sim/wave.do new file mode 100644 index 00000000..128637c8 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_2/sim/wave.do @@ -0,0 +1,30 @@ + + +onerror {resume} +quietly WaveActivateNextPane {} 0 + +add wave -noupdate -divider spi_master +add wave -noupdate /uvm_root/uvm_test_top/environment/spi_master/spi_master_monitor/txn_stream +add wave -noupdate -group spi_master_bus /hdl_top/spi_master_bus/* +add wave -noupdate -divider wb_slave +add wave -noupdate /uvm_root/uvm_test_top/environment/wb_slave/wb_slave_monitor/txn_stream +add wave -noupdate -group wb_slave_bus /hdl_top/wb_slave_bus/* + +TreeUpdate [SetDefaultTree] +quietly wave cursor active 0 +configure wave -namecolwidth 472 +configure wave -valuecolwidth 100 +configure wave -justifyvalue left +configure wave -signalnamewidth 0 +configure wave -snapdistance 10 +configure wave -datasetprefix 0 +configure wave -rowmargin 4 +configure wave -childrowmargin 2 +configure wave -gridoffset 0 +configure wave -gridperiod 1 +configure wave -griddelta 40 +configure wave -timeline 0 +configure wave -timelineunits ns +update +WaveRestoreZoom {27 ns} {168 ns} + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_2/sim/xwaves.sigs b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_2/sim/xwaves.sigs new file mode 100644 index 00000000..d75f0a57 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_2/sim/xwaves.sigs @@ -0,0 +1,17 @@ + + + + + +# pragma uvmf custom additional begin + +Group All + +#Top level signals +hdl_top.* +#Add additional levels or individual signals as needed +hdl_top.*.* + +# pragma uvmf custom additional end + + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_2/tb/parameters/block_2_parameters_pkg.compile b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_2/tb/parameters/block_2_parameters_pkg.compile new file mode 100644 index 00000000..1d5f4608 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_2/tb/parameters/block_2_parameters_pkg.compile @@ -0,0 +1,4 @@ +needs: + - $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg_hdl.compile +src: + - block_2_parameters_pkg.sv diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_2/tb/parameters/block_2_parameters_pkg.sv b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_2/tb/parameters/block_2_parameters_pkg.sv new file mode 100644 index 00000000..f01793fd --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_2/tb/parameters/block_2_parameters_pkg.sv @@ -0,0 +1,39 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This package contains test level parameters +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +`ifndef BLOCK_2_PARAMETERS_PKG_BENCH +`define BLOCK_2_PARAMETERS_PKG_BENCH + +package block_2_parameters_pkg; + + import uvmf_base_pkg_hdl::*; + + // pragma uvmf custom package_imports_additional begin + // pragma uvmf custom package_imports_additional end + + + // These parameters are used to uniquely identify each interface. The monitor_bfm and + // driver_bfm are placed into and retrieved from the uvm_config_db using these string + // names as the field_name. The parameter is also used to enable transaction viewing + // from the command line for selected interfaces using the UVM command line processing. + parameter string spi_master_BFM = "spi_master_BFM"; /* [0] */ + parameter string wb_slave_BFM = "wb_slave_BFM"; /* [1] */ + + // pragma uvmf custom package_item_additional begin + // pragma uvmf custom package_item_additional end + +endpackage + +// pragma uvmf custom external begin +// pragma uvmf custom external end +`endif diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_2/tb/parameters/block_2_parameters_pkg.vinfo b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_2/tb/parameters/block_2_parameters_pkg.vinfo new file mode 100644 index 00000000..7d0528cc --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_2/tb/parameters/block_2_parameters_pkg.vinfo @@ -0,0 +1,2 @@ +@use $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg_hdl.vinfo +block_2_parameters_pkg.sv diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_2/tb/sequences/block_2_sequences_pkg.compile b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_2/tb/sequences/block_2_sequences_pkg.compile new file mode 100644 index 00000000..60acb579 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_2/tb/sequences/block_2_sequences_pkg.compile @@ -0,0 +1,8 @@ +needs: + - $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg.compile + - ../../../../verification_ip/interface_packages/spi_m_pkg/spi_m.compile + - ../../../../verification_ip/interface_packages/wb_s_pkg/wb_s.compile + - ../../../../verification_ip/environment_packages/block_2_env_pkg/block_2_env_pkg.compile + - ../parameters/block_2_parameters_pkg.compile +src: + - block_2_sequences_pkg.sv diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_2/tb/sequences/block_2_sequences_pkg.sv b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_2/tb/sequences/block_2_sequences_pkg.sv new file mode 100644 index 00000000..dd290407 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_2/tb/sequences/block_2_sequences_pkg.sv @@ -0,0 +1,52 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This package includes all high level sequence classes used +// in the environment. These include utility sequences and top +// level sequences. +// +// CONTAINS: +// - +// - +// +//---------------------------------------------------------------------- +// +//---------------------------------------------------------------------- +// +`ifndef BLOCK_2_SEQUENCES_PKG_BENCH +`define BLOCK_2_SEQUENCES_PKG_BENCH +package block_2_sequences_pkg; + import uvm_pkg::*; + import uvmf_base_pkg::*; + import spi_m_pkg::*; + import spi_m_pkg_hdl::*; + import wb_s_pkg::*; + import wb_s_pkg_hdl::*; + import block_2_parameters_pkg::*; + import block_2_env_pkg::*; + `include "uvm_macros.svh" + + // pragma uvmf custom package_imports_additional begin + // pragma uvmf custom package_imports_additional end + + `include "src/block_2_bench_sequence_base.svh" + `include "src/register_test_sequence.svh" + `include "src/example_derived_test_sequence.svh" + + // pragma uvmf custom package_item_additional begin + // UVMF_CHANGE_ME : When adding new sequences to the src directory + // be sure to add the sequence file here so that it will be + // compiled as part of the sequence package. Be sure to place + // the new sequence after any base sequences of the new sequence. + // pragma uvmf custom package_item_additional end + +endpackage + +// pragma uvmf custom external begin +// pragma uvmf custom external end +`endif diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_2/tb/sequences/block_2_sequences_pkg.vinfo b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_2/tb/sequences/block_2_sequences_pkg.vinfo new file mode 100644 index 00000000..9d82a0e6 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_2/tb/sequences/block_2_sequences_pkg.vinfo @@ -0,0 +1,7 @@ +@use $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg.vinfo +@use $UVMF_VIP_LIBRARY_HOME/interface_packages/spi_m_pkg/spi_m_pkg.vinfo +@use $UVMF_VIP_LIBRARY_HOME/interface_packages/wb_s_pkg/wb_s_pkg.vinfo +@use $UVMF_VIP_LIBRARY_HOME/environment_packages/block_2_env_pkg/block_2_env_pkg.vinfo +@use $UVMF_PROJECT_DIR/tb/parameters/block_2_parameters_pkg.vinfo ++incdir+@vinfodir +block_2_sequences_pkg.sv diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_2/tb/sequences/src/block_2_bench_sequence_base.svh b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_2/tb/sequences/src/block_2_bench_sequence_base.svh new file mode 100644 index 00000000..663bf27d --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_2/tb/sequences/src/block_2_bench_sequence_base.svh @@ -0,0 +1,122 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// Description: This file contains the top level and utility sequences +// used by test_top. It can be extended to create derivative top +// level sequences. +// +//---------------------------------------------------------------------- +// +//---------------------------------------------------------------------- +// +`ifndef BLOCK_2_BENCH_SEQUENCE_BASE +`define BLOCK_2_BENCH_SEQUENCE_BASE + +typedef block_2_env_configuration block_2_env_configuration_t; + +class block_2_bench_sequence_base extends uvmf_sequence_base #(uvm_sequence_item); + + `uvm_object_utils( block_2_bench_sequence_base ); + + // pragma uvmf custom sequences begin + +typedef block_2_env_sequence_base #( + .CONFIG_T(block_2_env_configuration_t) + ) + block_2_env_sequence_base_t; +rand block_2_env_sequence_base_t block_2_env_seq; + + + + // UVMF_CHANGE_ME : Instantiate, construct, and start sequences as needed to create stimulus scenarios. + // Instantiate sequences here + typedef spi_m_random_sequence spi_master_random_seq_t; + spi_master_random_seq_t spi_master_random_seq; + // pragma uvmf custom sequences end + + // Sequencer handles for each active interface in the environment + typedef spi_m_transaction spi_master_transaction_t; + uvm_sequencer #(spi_master_transaction_t) spi_master_sequencer; + + + // Top level environment configuration handle + block_2_env_configuration_t top_configuration; + + // Configuration handles to access interface BFM's + spi_m_configuration spi_master_config; + wb_s_configuration wb_slave_config; + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + // **************************************************************************** + function new( string name = "" ); + super.new( name ); + // Retrieve the configuration handles from the uvm_config_db + + // Retrieve top level configuration handle + if ( !uvm_config_db#(block_2_env_configuration_t)::get(null,UVMF_CONFIGURATIONS, "TOP_ENV_CONFIG",top_configuration) ) begin + `uvm_info("CFG", "*** FATAL *** uvm_config_db::get can not find TOP_ENV_CONFIG. Are you using an older UVMF release than what was used to generate this bench?",UVM_NONE); + `uvm_fatal("CFG", "uvm_config_db#(block_2_env_configuration_t)::get cannot find resource TOP_ENV_CONFIG"); + end + + // Retrieve config handles for all agents + if( !uvm_config_db #( spi_m_configuration )::get( null , UVMF_CONFIGURATIONS , spi_master_BFM , spi_master_config ) ) + `uvm_fatal("CFG" , "uvm_config_db #( spi_m_configuration )::get cannot find resource spi_master_BFM" ) + if( !uvm_config_db #( wb_s_configuration )::get( null , UVMF_CONFIGURATIONS , wb_slave_BFM , wb_slave_config ) ) + `uvm_fatal("CFG" , "uvm_config_db #( wb_s_configuration )::get cannot find resource wb_slave_BFM" ) + + // Assign the sequencer handles from the handles within agent configurations + spi_master_sequencer = spi_master_config.get_sequencer(); + + + + // pragma uvmf custom new begin + // pragma uvmf custom new end + + endfunction + + // **************************************************************************** + virtual task body(); + // pragma uvmf custom body begin + + // Construct sequences here + + block_2_env_seq = block_2_env_sequence_base_t::type_id::create("block_2_env_seq"); + + spi_master_random_seq = spi_master_random_seq_t::type_id::create("spi_master_random_seq"); + fork + spi_master_config.wait_for_reset(); + wb_slave_config.wait_for_reset(); + join + // Start RESPONDER sequences here + fork + join_none + // Start INITIATOR sequences here + fork + repeat (25) spi_master_random_seq.start(spi_master_sequencer); + join + +block_2_env_seq.start(top_configuration.vsqr); + + // UVMF_CHANGE_ME : Extend the simulation XXX number of clocks after + // the last sequence to allow for the last sequence item to flow + // through the design. + fork + spi_master_config.wait_for_num_clocks(400); + wb_slave_config.wait_for_num_clocks(400); + join + + // pragma uvmf custom body end + endtask + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end +`endif diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_2/tb/sequences/src/example_derived_test_sequence.svh b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_2/tb/sequences/src/example_derived_test_sequence.svh new file mode 100644 index 00000000..b76f0eda --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_2/tb/sequences/src/example_derived_test_sequence.svh @@ -0,0 +1,31 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +// +//---------------------------------------------------------------------- +// +// DESCRIPTION: This file contains the top level sequence used in example_derived_test. +// It is an example of a sequence that is extended from %(benchName)_bench_sequence_base +// and can override %(benchName)_bench_sequence_base. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +`ifndef EXAMPLE_DERIVED_TEST_SEQUENCE +`define EXAMPLE_DERIVED_TEST_SEQUENCE +class example_derived_test_sequence extends block_2_bench_sequence_base; + + `uvm_object_utils( example_derived_test_sequence ); + + function new(string name = "" ); + super.new(name); + endfunction + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end +`endif diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_2/tb/sequences/src/register_test_sequence.svh b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_2/tb/sequences/src/register_test_sequence.svh new file mode 100644 index 00000000..869cbb63 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_2/tb/sequences/src/register_test_sequence.svh @@ -0,0 +1,58 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This file contains the top level sequence used in register_test. +// It uses the UVM built in register test. Specific UVM built-in tests can be +// selected in the body task. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +`ifndef REGISTER_TEST_SEQUENCE +`define REGISTER_TEST_SEQUENCE +class register_test_sequence extends block_2_bench_sequence_base; + + `uvm_object_utils( register_test_sequence ); + + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + function new(string name = "" ); + super.new(name); + endfunction + + // **************************************************************************** + virtual task body(); + + // Reset the DUT + fork + // pragma uvmf custom register_test_reset begin + // UVMF_CHANGE_ME + // Select the desired wait_for_reset or provide custom mechanism. + // fork-join for this code block may be unnecessary based on your situation. + spi_master_config.wait_for_reset(); + wb_slave_config.wait_for_reset(); + // pragma uvmf custom register_test_reset end + join + + // pragma uvmf custom register_test_setup begin + // UVMF_CHANGE_ME perform potentially necessary operations before running the sequence. + // pragma uvmf custom register_test_setup end + + // pragma uvmf custom register_test_operation begin + // UVMF_CHANGE_ME Perform your custom register test + // pragma uvmf custom register_test_operation end + + endtask + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end +`endif diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_2/tb/testbench/hdl_top.compile b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_2/tb/testbench/hdl_top.compile new file mode 100644 index 00000000..96a0acc9 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_2/tb/testbench/hdl_top.compile @@ -0,0 +1,10 @@ +incdir: + - ${uvm_path}/src + - . +needs: + - $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg_hdl.compile + - ../parameters/block_2_parameters_pkg.compile + - ../../../../verification_ip/interface_packages/spi_m_pkg/spi_m_hdl.compile + - ../../../../verification_ip/interface_packages/wb_s_pkg/wb_s_hdl.compile +src: + - hdl_top.sv diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_2/tb/testbench/hdl_top.sv b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_2/tb/testbench/hdl_top.sv new file mode 100644 index 00000000..1d30b34f --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_2/tb/testbench/hdl_top.sv @@ -0,0 +1,99 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// Description: This top level module instantiates all synthesizable +// static content. This and tb_top.sv are the two top level modules +// of the simulation. +// +// This module instantiates the following: +// DUT: The Design Under Test +// Interfaces: Signal bundles that contain signals connected to DUT +// Driver BFM's: BFM's that actively drive interface signals +// Monitor BFM's: BFM's that passively monitor interface signals +// +//---------------------------------------------------------------------- + +//---------------------------------------------------------------------- +// + +module hdl_top; + +import block_2_parameters_pkg::*; +import uvmf_base_pkg_hdl::*; + + // pragma attribute hdl_top partition_module_xrtl +// pragma uvmf custom clock_generator begin + bit clk; + // Instantiate a clk driver + // tbx clkgen + initial begin + clk = 0; + #9ns; + forever begin + clk = ~clk; + #5ns; + end + end +// pragma uvmf custom clock_generator end + +// pragma uvmf custom reset_generator begin + bit rst; + // Instantiate a rst driver + // tbx clkgen + initial begin + rst = 1; + #200ns; + rst = 0; + end +// pragma uvmf custom reset_generator end + + // pragma uvmf custom module_item_additional begin + // pragma uvmf custom module_item_additional end + + // Instantiate the signal bundle, monitor bfm and driver bfm for each interface. + // The signal bundle, _if, contains signals to be connected to the DUT. + // The monitor, monitor_bfm, observes the bus, _if, and captures transactions. + // The driver, driver_bfm, drives transactions onto the bus, _if. + spi_m_if spi_master_bus( + // pragma uvmf custom spi_master_bus_connections begin + .sck(clk), .rst(rst) + // pragma uvmf custom spi_master_bus_connections end + ); + wb_s_if wb_slave_bus( + // pragma uvmf custom wb_slave_bus_connections begin + .clock(clk), .reset(rst) + // pragma uvmf custom wb_slave_bus_connections end + ); + spi_m_monitor_bfm spi_master_mon_bfm(spi_master_bus.monitor_port); + wb_s_monitor_bfm wb_slave_mon_bfm(wb_slave_bus.monitor_port); + spi_m_driver_bfm spi_master_drv_bfm(spi_master_bus.initiator_port); + + // pragma uvmf custom dut_instantiation begin + // UVMF_CHANGE_ME : Add DUT and connect to signals in _bus interfaces listed above + // Instantiate your DUT here + // These DUT's instantiated to show verilog and vhdl instantiation + verilog_dut dut_verilog( .clk(clk), .rst(rst), .in_signal(vhdl_to_verilog_signal), .out_signal(verilog_to_vhdl_signal)); + vhdl_dut dut_vhdl ( .clk(clk), .rst(rst), .in_signal(verilog_to_vhdl_signal), .out_signal(vhdl_to_verilog_signal)); + // pragma uvmf custom dut_instantiation end + + initial begin // tbx vif_binding_block + import uvm_pkg::uvm_config_db; + // The monitor_bfm and driver_bfm for each interface is placed into the uvm_config_db. + // They are placed into the uvm_config_db using the string names defined in the parameters package. + // The string names are passed to the agent configurations by test_top through the top level configuration. + // They are retrieved by the agents configuration class for use by the agent. + uvm_config_db #( virtual spi_m_monitor_bfm )::set( null , UVMF_VIRTUAL_INTERFACES , spi_master_BFM , spi_master_mon_bfm ); + uvm_config_db #( virtual wb_s_monitor_bfm )::set( null , UVMF_VIRTUAL_INTERFACES , wb_slave_BFM , wb_slave_mon_bfm ); + uvm_config_db #( virtual spi_m_driver_bfm )::set( null , UVMF_VIRTUAL_INTERFACES , spi_master_BFM , spi_master_drv_bfm ); + end + +endmodule + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_2/tb/testbench/hdl_top.vinfo b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_2/tb/testbench/hdl_top.vinfo new file mode 100644 index 00000000..dce0a508 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_2/tb/testbench/hdl_top.vinfo @@ -0,0 +1,6 @@ +@use $UVMF_PROJECT_DIR/rtl/verilog/verilog_dut.vinfo +@use $UVMF_PROJECT_DIR/tb/parameters/block_2_parameters_pkg.vinfo +@use $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg_hdl.vinfo +@use $UVMF_VIP_LIBRARY_HOME/interface_packages/spi_m_pkg/spi_m_bfm.vinfo +@use $UVMF_VIP_LIBRARY_HOME/interface_packages/wb_s_pkg/wb_s_bfm.vinfo +hdl_top.sv diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_2/tb/testbench/hvl_top.compile b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_2/tb/testbench/hvl_top.compile new file mode 100644 index 00000000..381340b2 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_2/tb/testbench/hvl_top.compile @@ -0,0 +1,7 @@ +incdir: + - ${uvm_path}/src + - . +needs: + - ../tests/block_2_tests_pkg.compile +src: + - hvl_top.sv diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_2/tb/testbench/hvl_top.sv b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_2/tb/testbench/hvl_top.sv new file mode 100644 index 00000000..1cd56838 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_2/tb/testbench/hvl_top.sv @@ -0,0 +1,33 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +// +//---------------------------------------------------------------------- +// +// DESCRIPTION: This module loads the test package and starts the UVM phases. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// + +module hvl_top; + +import uvm_pkg::*; +import block_2_tests_pkg::*; + + // pragma uvmf custom module_item_additional begin + // pragma uvmf custom module_item_additional end + + initial begin + $timeformat(-9,3,"ns",5); + run_test(); + end + +endmodule + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_2/tb/testbench/hvl_top.vinfo b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_2/tb/testbench/hvl_top.vinfo new file mode 100644 index 00000000..fd98547a --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_2/tb/testbench/hvl_top.vinfo @@ -0,0 +1,2 @@ +@use $UVMF_PROJECT_DIR/tb/tests/block_2_tests_pkg.vinfo +hvl_top.sv diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_2/tb/testbench/top_filelist_hdl.f b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_2/tb/testbench/top_filelist_hdl.f new file mode 100644 index 00000000..1e9dab65 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_2/tb/testbench/top_filelist_hdl.f @@ -0,0 +1,3 @@ +$UVMF_PROJECT_DIR/tb/testbench/hdl_top.sv +// pragma uvmf custom additional begin +// pragma uvmf custom additional end diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_2/tb/testbench/top_filelist_hvl.f b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_2/tb/testbench/top_filelist_hvl.f new file mode 100644 index 00000000..42383ab2 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_2/tb/testbench/top_filelist_hvl.f @@ -0,0 +1,3 @@ +$UVMF_PROJECT_DIR/tb/testbench/hvl_top.sv +// pragma uvmf custom additional begin +// pragma uvmf custom additional end diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_2/tb/tests/block_2_tests_pkg.compile b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_2/tb/tests/block_2_tests_pkg.compile new file mode 100644 index 00000000..fcd92c08 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_2/tb/tests/block_2_tests_pkg.compile @@ -0,0 +1,9 @@ +needs: + - $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg.compile + - ../../../../verification_ip/interface_packages/spi_m_pkg/spi_m.compile + - ../../../../verification_ip/interface_packages/wb_s_pkg/wb_s.compile + - ../../../../verification_ip/environment_packages/block_2_env_pkg/block_2_env_pkg.compile + - ../parameters/block_2_parameters_pkg.compile + - ../sequences/block_2_sequences_pkg.compile +src: + - block_2_tests_pkg.sv diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_2/tb/tests/block_2_tests_pkg.sv b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_2/tb/tests/block_2_tests_pkg.sv new file mode 100644 index 00000000..b740c091 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_2/tb/tests/block_2_tests_pkg.sv @@ -0,0 +1,55 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This package contains all tests currently written for +// the simulation project. Once compiled, any test can be selected +// from the vsim command line using +UVM_TESTNAME=yourTestNameHere +// +// CONTAINS: +// - +// - +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +`ifndef BLOCK_2_TESTS_PKG +`define BLOCK_2_TESTS_PKG +package block_2_tests_pkg; + + import uvm_pkg::*; + import uvmf_base_pkg::*; + import block_2_parameters_pkg::*; + import block_2_env_pkg::*; + import block_2_sequences_pkg::*; + import spi_m_pkg::*; + import spi_m_pkg_hdl::*; + import wb_s_pkg::*; + import wb_s_pkg_hdl::*; + + + `include "uvm_macros.svh" + + // pragma uvmf custom package_imports_additional begin + // pragma uvmf custom package_imports_additional end + + `include "src/test_top.svh" + `include "src/register_test.svh" + `include "src/example_derived_test.svh" + + // pragma uvmf custom package_item_additional begin + // UVMF_CHANGE_ME : When adding new tests to the src directory + // be sure to add the test file here so that it will be + // compiled as part of the test package. Be sure to place + // the new test after any base tests of the new test. + // pragma uvmf custom package_item_additional end + +endpackage + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_2/tb/tests/block_2_tests_pkg.vinfo b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_2/tb/tests/block_2_tests_pkg.vinfo new file mode 100644 index 00000000..9992ff94 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_2/tb/tests/block_2_tests_pkg.vinfo @@ -0,0 +1,8 @@ +@use $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg.vinfo +@use $UVMF_VIP_LIBRARY_HOME/interface_packages/spi_m_pkg/spi_m_pkg.vinfo +@use $UVMF_VIP_LIBRARY_HOME/interface_packages/wb_s_pkg/wb_s_pkg.vinfo +@use $UVMF_VIP_LIBRARY_HOME/environment_packages/block_2_env_pkg/block_2_env_pkg.vinfo +@use $UVMF_PROJECT_DIR/tb/parameters/block_2_parameters_pkg.vinfo +@use $UVMF_PROJECT_DIR/tb/sequences/block_2_sequences_pkg.vinfo ++incdir+@vinfodir +block_2_tests_pkg.sv diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_2/tb/tests/src/example_derived_test.svh b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_2/tb/tests/src/example_derived_test.svh new file mode 100644 index 00000000..4422213f --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_2/tb/tests/src/example_derived_test.svh @@ -0,0 +1,44 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This test extends test_top and makes +// changes to test_top using the UVM factory type_override: +// +// Test scenario: +// This is a template test that can be used to create future tests. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +`ifndef EXAMPLE_DERIVED_TEST +`define EXAMPLE_DERIVED_TEST +class example_derived_test extends test_top; + + `uvm_component_utils( example_derived_test ); + + function new( string name = "", uvm_component parent = null ); + super.new( name, parent ); + endfunction + + virtual function void build_phase(uvm_phase phase); + // The factory override below is an example of how to replace the block_2_bench_sequence_base + // sequence with the example_derived_test_sequence. + block_2_bench_sequence_base::type_id::set_type_override(example_derived_test_sequence::get_type()); + // Execute the build_phase of test_top AFTER all factory overrides have been created. + super.build_phase(phase); + // pragma uvmf custom configuration_settings_post_randomize begin + // UVMF_CHANGE_ME Test specific configuration values can be set here. + // The configuration structure has already been randomized. + // pragma uvmf custom configuration_settings_post_randomize end + endfunction + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end +`endif diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_2/tb/tests/src/register_test.svh b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_2/tb/tests/src/register_test.svh new file mode 100644 index 00000000..93cb3385 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_2/tb/tests/src/register_test.svh @@ -0,0 +1,41 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This test extends test_top and makes +// changes to test_top using the UVM factory type_override: +// +// Test scenario: +// This is a template test that can be used to create future tests. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +`ifndef REGISTER_TEST +`define REGISTER_TEST +class register_test extends test_top; + + `uvm_component_utils( register_test ); + + function new( string name = "", uvm_component parent = null ); + super.new( name, parent ); + endfunction + + virtual function void build_phase(uvm_phase phase); + // The factory override below replaces the block_2_bench_sequence_base + // sequence with the register_test_sequence. + block_2_bench_sequence_base::type_id::set_type_override(register_test_sequence::get_type()); + // Execute the build_phase of test_top AFTER all factory overrides have been created. + super.build_phase(phase); + endfunction + + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end +`endif diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_2/tb/tests/src/test_top.svh b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_2/tb/tests/src/test_top.svh new file mode 100644 index 00000000..160bfe82 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_2/tb/tests/src/test_top.svh @@ -0,0 +1,79 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// Description: This top level UVM test is the base class for all +// future tests created for this project. +// +// This test class contains: +// Configuration: The top level configuration for the project. +// Environment: The top level environment for the project. +// Top_level_sequence: The top level sequence for the project. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// + +typedef block_2_env_configuration block_2_env_configuration_t; +typedef block_2_environment block_2_environment_t; +`ifndef TEST_TOP +`define TEST_TOP +class test_top extends uvmf_test_base #(.CONFIG_T(block_2_env_configuration_t), + .ENV_T(block_2_environment_t), + .TOP_LEVEL_SEQ_T(block_2_bench_sequence_base)); + + `uvm_component_utils( test_top ); + + + + string interface_names[] = { + spi_master_BFM /* spi_master [0] */ , + wb_slave_BFM /* wb_slave [1] */ +}; + +uvmf_active_passive_t interface_activities[] = { + ACTIVE /* spi_master [0] */ , + PASSIVE /* wb_slave [1] */ }; + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + // **************************************************************************** + // FUNCTION: new() + // This is the standard systemVerilog constructor. All components are + // constructed in the build_phase to allow factory overriding. + // + function new( string name = "", uvm_component parent = null ); + super.new( name ,parent ); + endfunction + + + + // **************************************************************************** + // FUNCTION: build_phase() + // The construction of the configuration and environment classes is done in + // the build_phase of uvmf_test_base. Once the configuraton and environment + // classes are built then the initialize call is made to perform the + // following: + // Monitor and driver BFM virtual interface handle passing into agents + // Set the active/passive state for each agent + // Once this build_phase completes, the build_phase of the environment is + // executed which builds the agents. + // + virtual function void build_phase(uvm_phase phase); +// pragma uvmf custom build_phase_pre_super begin +// pragma uvmf custom build_phase_pre_super end + super.build_phase(phase); + // pragma uvmf custom configuration_settings_post_randomize begin + // pragma uvmf custom configuration_settings_post_randomize end + configuration.initialize(NA, "uvm_test_top.environment", interface_names, null, interface_activities); + endfunction + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end +`endif diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_2/yaml/block_2_bench.yaml b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_2/yaml/block_2_bench.yaml new file mode 100644 index 00000000..abfe0941 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_2/yaml/block_2_bench.yaml @@ -0,0 +1,17 @@ +uvmf: + benches: + block_2: + active_passive: + - bfm_name: spi_master + value: ACTIVE + - bfm_name: wb_slave + value: PASSIVE + active_passive_default: ACTIVE + clock_half_period: 5ns + clock_phase_offset: 9ns + existing_library_component: 'True' + interface_params: [] + reset_assertion_level: 'True' + reset_duration: 200ns + top_env: block_2 + use_dpi_link: 'False' diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_3/.project b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_3/.project new file mode 100644 index 00000000..ba9cab02 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_3/.project @@ -0,0 +1,37 @@ + + + block_3 + + + + + + org.python.pydev.PyDevBuilder + + + + + net.sf.sveditor.core.SVProjectBuilder + + + + + + net.sf.sveditor.core.SVNature + org.python.pydev.pythonNature + + + + verification_ip + 2 + UVMF_VIP_LIBRARY_HOME + + + + + UVMF_VIP_LIBRARY_HOME + $%7BPARENT-2-PROJECT_LOC%7D/verification_ip + + + + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_3/.svproject b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_3/.svproject new file mode 100644 index 00000000..e998cea7 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_3/.svproject @@ -0,0 +1,16 @@ + + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_3/block_3_sve.F b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_3/block_3_sve.F new file mode 100644 index 00000000..0c6abe1a --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_3/block_3_sve.F @@ -0,0 +1,28 @@ + +// UVM ++incdir+${UVM_HOME}/src +${UVM_HOME}/src/uvm_pkg.sv + +// Common UVMF files +-f ${UVMF_HOME}/common/common_sve.f + +// BFM Files +-F ${UVMF_VIP_LIBRARY_HOME}/interface_packages/wb_m_pkg/wb_m_pkg_sve.F +-F ${UVMF_VIP_LIBRARY_HOME}/interface_packages/axi_s_pkg/axi_s_pkg_sve.F + +// Environment Files +-F ${UVMF_VIP_LIBRARY_HOME}/environment_packages/block_3_env_pkg/block_3_env_pkg_sve.F + +// Bench Files ++incdir+./tb/tests +./tb/tests/block_3_tests_pkg.sv + ++incdir+./tb/sequences +./tb/sequences/block_3_sequences_pkg.sv + ++incdir+./tb/parameters +./tb/parameters/block_3_parameters_pkg.sv + +./tb/testbench/hdl_top.sv +./tb/testbench/hvl_top.sv + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_3/docs/interfaces.csv b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_3/docs/interfaces.csv new file mode 100644 index 00000000..82c2e9d0 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_3/docs/interfaces.csv @@ -0,0 +1,14 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// + +, +Interface Description, Interface Type, Interface Transaction, Interface Name, +wb_master, wb_m_driver_bfm wb_m_monitor_bfm, wb_m_transaction, wb_m_pkg_wb_master_BFM, +axi_slave, axi_s_driver_bfm axi_s_monitor_bfm, axi_s_transaction, axi_s_pkg_axi_slave_BFM, + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_3/rtl/dut.compile b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_3/rtl/dut.compile new file mode 100644 index 00000000..9b0008fc --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_3/rtl/dut.compile @@ -0,0 +1,6 @@ + +# pragma uvmf custom dut_compile_info begin +src: + - ./vhdl/vhdl_dut.vhd + - ./verilog/verilog_dut.v +# pragma uvmf custom dut_compile_info end diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_3/rtl/verilog/verilog_dut.v b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_3/rtl/verilog/verilog_dut.v new file mode 100644 index 00000000..96198441 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_3/rtl/verilog/verilog_dut.v @@ -0,0 +1,21 @@ +module verilog_dut(clk, rst, in_signal, out_signal); + +input clk; +input rst; +input in_signal; +output out_signal; + +reg out_signal_o; + +always @(posedge clk) begin + if (rst) begin + out_signal_o <= 0; + end + else begin + out_signal_o <= ~in_signal; + end + end + +assign out_signal = out_signal_o; + +endmodule diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_3/rtl/verilog/verilog_dut.vinfo b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_3/rtl/verilog/verilog_dut.vinfo new file mode 100644 index 00000000..87e95f36 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_3/rtl/verilog/verilog_dut.vinfo @@ -0,0 +1 @@ +verilog_dut.v diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_3/rtl/vhdl/vhdl_dut.vhd b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_3/rtl/vhdl/vhdl_dut.vhd new file mode 100644 index 00000000..904aa37d --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_3/rtl/vhdl/vhdl_dut.vhd @@ -0,0 +1,21 @@ +library ieee; +use ieee.std_logic_1164.all ; + +entity vhdl_dut is + port ( clk : in std_logic ; + rst : in std_logic ; + in_signal : in std_logic ; + out_signal :out std_logic + ); +end vhdl_dut; + +architecture rtl of vhdl_dut is + begin + P1: process + variable out_signal_o : std_logic; + begin + wait until clk'event and clk = '1'; + out_signal_o := in_signal; + out_signal <= out_signal_o; + end process; + end rtl; diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_3/sim/Makefile b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_3/sim/Makefile new file mode 100644 index 00000000..3866116c --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_3/sim/Makefile @@ -0,0 +1,199 @@ + +# +#---------------------------------------------------------------------- +# +# DESCRIPTION: This makefile includes the shared makefile and contains +# bench level make targets. +# +#---------------------------------------------------------------------- + + +# pragma uvmf custom additional begin +# pragma uvmf custom additional end + +# ********************************************************************************************* +# UVMF library directory: +# This variable points to the UVMF release where uvmf_base_pkg directory resides. +# This variable points to release code that is not user modified. +# This variable allows for UVMF release directories to reside independent of project related verification IP and project bench directories. +# This code below looks "upward" for directory starting with UVMF_* and returns first match for use with the release examples. +UVMF_HOME ?= ___PLEASE_SET_AN_ENVIRONMENT_VARIABLE_NAMED_UVMF_HOME_TO_POINT_TO_THE_UVMF_INSTALLATION___ + +# pragma uvmf custom exports begin +# +# Project(s) specific verification IP library: +# Directory where reusable verification packages for interfaces, environments, utilities, etc. reside. +# This variable allows for your verification IP to reside independent of project bench and UVMF release directories. +# For examples deployed with UVMF this will be $(UVMF_HOME)//verification_ip +export UVMF_VIP_LIBRARY_HOME ?= $(PWD)/../../../verification_ip +# +# Project specific bench: +# Directory where bench specific code is located. +# This variable allows for project_benches to reside independent of verification IP and UVMF release directories. +# For examples deployed with UVMF this will be $(UVMF_HOME)//project_benches/ +export UVMF_PROJECT_DIR ?= $(PWD)/.. +# +# +# pragma uvmf custom exports end +# ********************************************************************************************* + +## Check PATH for required vinfo scripts +PVAL := $(shell command -v make_filelist.py 2> /dev/null) +ifndef PVAL + MFLIST = $(UVMF_HOME)/scripts/make_filelist.py +else + MFLIST = make_filelist.py +endif + + +# Set test case specific Variables +TEST_NAME ?= test_top + +TEST_SEED ?= random +UVM_CLI_ARGS = + +# Usage of Veloce, etc. to be input by the user (subject to defaults) +USE_VELOCE ?= 0 + +# Usage of vinfo flow for generating file list +USE_VINFO ?= 0 + +# Usage of Veloce and Questa profilers +USE_VELOCE_PROFILER ?= 0 +USE_QUESTA_PROFILER ?= 0 + + +# Set project Variables +TEST_PLAN_NAME = block_3_TestPlan +REPORTING_DO_FILE = block_3_reports_script + + +# Include makefile that includes targets for UVM_VIP_Library packages +include $(UVMF_HOME)/scripts/Makefile + + + + +# Include all requisite interface package targets for this bench +include $(UVMF_VIP_LIBRARY_HOME)/interface_packages/wb_m_pkg/Makefile +include $(UVMF_VIP_LIBRARY_HOME)/interface_packages/axi_s_pkg/Makefile + +# Include all requisite environment package targets for this bench +include $(UVMF_VIP_LIBRARY_HOME)/environment_packages/block_3_env_pkg/Makefile + + + +# Add to default compile/load/run arguments +VCOM_ARGS += + +# Note: vsim-3009 error can be eliminated by adding -timescale 1ps/1ps to VLOG_ARGS + +VLOG_ARGS += $(UVM_DISABLE_FILE_LINE_CMD) + +VELANALYZE_ARGS += +VELANALYZE_HVL_ARGS += + +BATCH_VOPT_ARGS += +DEBUG_VOPT_ARGS += +EXTRA_VOPT_TOPS += +COMMON_VSIM_ARGS += +COMMON_VSIM_ARGS += + + +BATCH_VSIM_ARGS += #-uvmcontrol=none +DEBUG_VSIM_ARGS += +EXTRA_VSIM_TOPS += + +# pragma uvmf custom additional_args begin +# pragma uvmf custom additional_args end + + +# Project bench package source +block_3_PARAMETERS_PKG ?=\ +$(UVMF_PROJECT_DIR)/tb/parameters/block_3_parameters_pkg.sv + + +block_3_SEQUENCES_PKG ?=\ +$(UVMF_PROJECT_DIR)/tb/sequences/block_3_sequences_pkg.sv + + +block_3_TEST_PKG ?=\ +$(UVMF_PROJECT_DIR)/tb/tests/block_3_tests_pkg.sv + +# pragma uvmf custom dut_files begin +# UVMF_CHANGE_ME : Reference Verilog DUT source. +block_3_VERILOG_DUT ?=\ +$(UVMF_PROJECT_DIR)/rtl/verilog/verilog_dut.v + +# UVMF_CHANGE_ME : Reference VHDL DUT source. +block_3_VHDL_DUT ?=\ +$(UVMF_PROJECT_DIR)/rtl/vhdl/vhdl_dut.vhd +# pragma uvmf custom dut_files end + + +# Project bench package targets +COMP_block_3_PARAMETERS_PKG_TGT_0 = q_comp_block_3_parameters_pkg +COMP_block_3_PARAMETERS_PKG_TGT_1 = v_comp_block_3_parameters_pkg +COMP_block_3_PARAMETERS_PKG_TGT = $(COMP_block_3_PARAMETERS_PKG_TGT_$(USE_VELOCE)) + +comp_block_3_parameters_pkg: $(COMP_block_3_PARAMETERS_PKG_TGT) + +q_comp_block_3_parameters_pkg: + $(HVL_COMP_CMD) +incdir+$(UVMF_PROJECT_DIR)/tb/parameters $(block_3_PARAMETERS_PKG) + +v_comp_block_3_parameters_pkg: q_comp_block_3_parameters_pkg + $(HDL_COMP_CMD) +incdir+$(UVMF_PROJECT_DIR)/tb/parameters $(block_3_PARAMETERS_PKG) + + +comp_block_3_sequence_pkg: + $(HVL_COMP_CMD) +incdir+$(UVMF_PROJECT_DIR)/tb/sequences $(block_3_SEQUENCES_PKG) + +comp_block_3_tests_pkg: + $(HVL_COMP_CMD) +incdir+$(UVMF_PROJECT_DIR)/tb/tests $(block_3_TEST_PKG) + +# pragma uvmf custom dut_compile_make_target begin +# UVMF_CHANGE_ME : Add make target to compile your verilog dut here +comp_block_3_verilog_dut: + echo "Compile your verilog DUT here" + $(HDL_COMP_CMD) $(block_3_VERILOG_DUT) + +# UVMF_CHANGE_ME : Add make target to compile your vhdl dut here +comp_block_3_vhdl_dut: + echo "Compile your vhdl DUT here" + $(HDL_COMP_CMD_VHDL) $(block_3_VHDL_DUT) + +# UVMF_CHANGE_ME : Add make target to compile your dut here +comp_block_3_dut: comp_block_3_vhdl_dut comp_block_3_verilog_dut +# pragma uvmf custom dut_compile_make_target end + + +BUILD_TGT_0 = make_build +BUILD_TGT_1 = vinfo_build +BUILD_TGT = $(BUILD_TGT_$(USE_VINFO)) + + +comp_hvl : comp_hvl_core + + +comp_hvl_core : \ + comp_wb_m_pkg comp_axi_s_pkg \ + comp_block_3_env_pkg \ + comp_block_3_parameters_pkg comp_block_3_sequence_pkg comp_block_3_tests_pkg + +comp_uvmf_core : comp_uvm_pkg comp_uvmf_base_pkg + +make_build: comp_block_3_dut comp_uvmf_core comp_hvl comp_test_bench + +hvl_build: q_comp_wb_m_pkg q_comp_axi_s_pkg comp_block_3_env_pkg comp_block_3_sequence_pkg comp_block_3_tests_pkg hvl_comp_testbench link optimize + + +vinfo_build: comp_block_3_vhdl_dut build_hdl_vinfo build_hvl_vinfo $(VINFO_TGT) + + $(HDL_COMP_CMD) -F hdl.vf + $(VEL_COMP) + +build: $(BUILD_TGT) + +# pragma uvmf custom additional_targets begin +# pragma uvmf custom additional_targets end + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_3/sim/bcr_testlist b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_3/sim/bcr_testlist new file mode 100644 index 00000000..482f01fc --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_3/sim/bcr_testlist @@ -0,0 +1,19 @@ + + + +# Test list for use by RMDB file +# File syntax is +# TB_INFO { } { } +# TB ## All subsequent tests will run on this bench until a different "TB" line is seen +# TEST <1st_seed> ... +# If not enough seeds are provided then random seeds are used to pad +# If no repeat count is given, default is 1 +# pragma uvmf custom tb_info begin +TB_INFO block_3 { } { } +# pragma uvmf custom tb_info end +TB block_3 +# pragma uvmf custom regression_suite begin +TEST test_top 3 +# pragma uvmf custom regression_suite end + + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_3/sim/bcr_testlist.yaml b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_3/sim/bcr_testlist.yaml new file mode 100644 index 00000000..ac85d606 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_3/sim/bcr_testlist.yaml @@ -0,0 +1,44 @@ + + + +# YAML test list for use by RMDB file +# File syntax is +# uvmf_testlist: +# testbenches: +# - name: +# extra_build_options: +# extra_run_options: +# - name: +# ... +# - name: +# tests: +# - name: +# uvm_testname: (defaults to test_name) +# testbench: (defaults to last tb name seen) +# repeat: (defaults to 1) +# seeds: [,,...,] (defaults to all random) +# extra_test_options: +# - name: +# ... +# - name: +# include: +# - (relative path reference is to the including YAML file) +# - +# ... +# - + +uvmf_testlist: + testbenches: +# pragma uvmf custom tb_info begin + - name: block_3 + extra_build_options: "" + extra_run_options: "" +# pragma uvmf custom tb_info end + tests: + - testbench: block_3 +# pragma uvmf custom regression_suite begin + - name: test_top + repeat: 3 +# pragma uvmf custom regression_suite end + + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_3/sim/compile.do b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_3/sim/compile.do new file mode 100644 index 00000000..dba7d6f1 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_3/sim/compile.do @@ -0,0 +1,71 @@ + + +################################################################## +## ENVIRONMENT VARIABLES +################################################################## +quietly set ::env(UVMF_VIP_LIBRARY_HOME) ../../../verification_ip +quietly set ::env(UVMF_PROJECT_DIR) .. + +## Using VRM means that the build is occuring several more directories deeper underneath +## the sim directory, need to prepend some more '..' +if {[info exists ::env(VRM_BUILD)]} { + quietly set ::env(UVMF_VIP_LIBRARY_HOME) "../../../../../$::env(UVMF_VIP_LIBRARY_HOME)" + quietly set ::env(UVMF_PROJECT_DIR) "../../../../../$::env(UVMF_PROJECT_DIR)" +} +quietly set ::env(UVMF_VIP_LIBRARY_HOME) [file normalize $::env(UVMF_VIP_LIBRARY_HOME)] +quietly set ::env(UVMF_PROJECT_DIR) [file normalize $::env(UVMF_PROJECT_DIR)] +quietly echo "UVMF_VIP_LIBRARY_HOME = $::env(UVMF_VIP_LIBRARY_HOME)" +quietly echo "UVMF_PROJECT_DIR = $::env(UVMF_PROJECT_DIR)" + + +################################################################### +## HOUSEKEEPING : DELETE FILES THAT WILL BE REGENERATED +################################################################### +file delete -force *~ *.ucdb vsim.dbg *.vstf *.log work *.mem *.transcript.txt certe_dump.xml *.wlf covhtmlreport VRMDATA +file delete -force design.bin qwave.db dpiheader.h visualizer*.ses +file delete -force veloce.med veloce.wave veloce.map tbxbindings.h edsenv velrunopts.ini +file delete -force sv_connect.* + +################################################################### +## COMPILE DUT SOURCE CODE +################################################################### +vlib work +# pragma uvmf custom dut_compile_dofile_target begin +# UVMF_CHANGE_ME : Add commands to compile your dut here, replacing the default examples +vlog -sv -timescale 1ps/1ps -suppress 2223,2286 $env(UVMF_PROJECT_DIR)/rtl/verilog/verilog_dut.v +vcom $env(UVMF_PROJECT_DIR)/rtl/vhdl/vhdl_dut.vhd +# pragma uvmf custom dut_compile_dofile_target end + +################################################################### +## COMPILE UVMF BASE/COMMON SOURCE CODE +################################################################### +vlog -sv -timescale 1ps/1ps -suppress 2223 -suppress 2286 +incdir+$env(UVMF_HOME)/uvmf_base_pkg -F $env(UVMF_HOME)/uvmf_base_pkg/uvmf_base_pkg_filelist_hdl.f +vlog -sv -timescale 1ps/1ps -suppress 2223 -suppress 2286 +incdir+$env(UVMF_HOME)/uvmf_base_pkg -F $env(UVMF_HOME)/uvmf_base_pkg/uvmf_base_pkg_filelist_hvl.f + + +################################################################### +## UVMF INTERFACE COMPILATION +################################################################### +do $env(UVMF_VIP_LIBRARY_HOME)/interface_packages/wb_m_pkg/compile.do +do $env(UVMF_VIP_LIBRARY_HOME)/interface_packages/axi_s_pkg/compile.do + +################################################################### +## UVMF ENVIRONMENT COMPILATION +################################################################### +do $env(UVMF_VIP_LIBRARY_HOME)/environment_packages/block_3_env_pkg/compile.do + +################################################################### +## UVMF BENCHES COMPILATION +################################################################### +vlog -sv -timescale 1ps/1ps -suppress 2223 -suppress 2286 +incdir+$env(UVMF_PROJECT_DIR)/tb/parameters $env(UVMF_PROJECT_DIR)/tb/parameters/block_3_parameters_pkg.sv +vlog -sv -timescale 1ps/1ps -suppress 2223 -suppress 2286 +incdir+$env(UVMF_PROJECT_DIR)/tb/sequences $env(UVMF_PROJECT_DIR)/tb/sequences/block_3_sequences_pkg.sv +vlog -sv -timescale 1ps/1ps -suppress 2223 -suppress 2286 +incdir+$env(UVMF_PROJECT_DIR)/tb/tests $env(UVMF_PROJECT_DIR)/tb/tests/block_3_tests_pkg.sv + +vlog -sv -timescale 1ps/1ps -suppress 2223 -suppress 2286 +incdir+$env(UVMF_PROJECT_DIR)/tb/testbench -F $env(UVMF_PROJECT_DIR)/tb/testbench/top_filelist_hdl.f +vlog -sv -timescale 1ps/1ps -suppress 2223 -suppress 2286 +incdir+$env(UVMF_PROJECT_DIR)/tb/testbench -F $env(UVMF_PROJECT_DIR)/tb/testbench/top_filelist_hvl.f + +################################################################### +## OPTIMIZATION +################################################################### +vopt hvl_top hdl_top -o optimized_batch_top_tb +vopt +acc hvl_top hdl_top -o optimized_debug_top_tb diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_3/sim/hdl.compile b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_3/sim/hdl.compile new file mode 100644 index 00000000..8e7bd41a --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_3/sim/hdl.compile @@ -0,0 +1,5 @@ +needs: +# pragma uvmf custom dut_compile_info begin + - ../rtl/dut.compile +# pragma uvmf custom dut_compile_info end + - ../tb/testbench/hdl_top.compile diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_3/sim/hdl.vinfo b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_3/sim/hdl.vinfo new file mode 100644 index 00000000..da27ec77 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_3/sim/hdl.vinfo @@ -0,0 +1 @@ +@use $UVMF_PROJECT_DIR/tb/testbench/hdl_top.vinfo diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_3/sim/hvl.compile b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_3/sim/hvl.compile new file mode 100644 index 00000000..ce952549 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_3/sim/hvl.compile @@ -0,0 +1,2 @@ +needs: + - ../tb/testbench/hvl_top.compile diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_3/sim/hvl.vinfo b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_3/sim/hvl.vinfo new file mode 100644 index 00000000..d22eff33 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_3/sim/hvl.vinfo @@ -0,0 +1 @@ +@use $UVMF_PROJECT_DIR/tb/testbench/hvl_top.vinfo diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_3/sim/run.do b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_3/sim/run.do new file mode 100644 index 00000000..101ddc48 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_3/sim/run.do @@ -0,0 +1,21 @@ + + +quietly set svLibs "" +quietly set extra_vsim_args "" + +################################################################### +## Check for additional vsim arguments passed using env var $UVMF_EXTRA_VSIM_ARGS +################################################################### +if {[info exists ::env(UVMF_EXTRA_VSIM_ARGS)]} { + echo "Adding more args to vsim command" + quietly set extra_vsim_args $::env(UVMF_EXTRA_VSIM_ARGS) +} + +################################################################## +## Launch Questa : generate vsim command line and execute +################################################################## +# pragma uvmf custom dut_run_dofile_target begin +# UVMF_CHANGE_ME : Change the UVM_TESTNAME plusarg to run a different test +quietly set cmd [format "vsim -i -sv_seed random +UVM_TESTNAME=test_top +UVM_VERBOSITY=UVM_HIGH -permit_unmatched_virtual_intf +notimingchecks -suppress 8887 %s %s -uvmcontrol=all -msgmode both -classdebug -assertdebug +uvm_set_config_int=*,enable_transaction_viewing,1 -do { set NoQuitOnFinish 1; onbreak {resume}; run 0; do wave.do; set PrefSource(OpenOnBreak) 0; radix hex showbase; } optimized_debug_top_tb" $svLibs $extra_vsim_args] +# pragma uvmf custom dut_run_dofile_target end +eval $cmd diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_3/sim/tbx.config b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_3/sim/tbx.config new file mode 100644 index 00000000..eec58168 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_3/sim/tbx.config @@ -0,0 +1,10 @@ + + + + + +comp -questa +velsyn -D1S +rtlc -allow_4ST + + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_3/sim/testlist b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_3/sim/testlist new file mode 100644 index 00000000..c770870e --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_3/sim/testlist @@ -0,0 +1,20 @@ + + + + +# Test list for use by RMDB file +# File syntax is +# TB_INFO { } { } +# TB ## All subsequent tests will run on this bench until a different "TB" line is seen +# TEST <1st_seed> ... +# If not enough seeds are provided then random seeds are used to pad +# If no repeat count is given, default is 1 +# pragma uvmf custom tb_info begin +TB_INFO block_3 { UVMF_VIP_LIBRARY_HOME=../../../../../../../../verification_ip UVMF_PROJECT_DIR=../../../../../../../block_3 } { } +# pragma uvmf custom tb_info end +TB block_3 +# pragma uvmf custom regression_suite begin +TEST test_top 3 +# pragma uvmf custom regression_suite end + + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_3/sim/testlist.yaml b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_3/sim/testlist.yaml new file mode 100644 index 00000000..2eb1c8dc --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_3/sim/testlist.yaml @@ -0,0 +1,44 @@ + + + +# YAML test list for use by RMDB file +# File syntax is +# uvmf_testlist: +# testbenches: +# - name: +# extra_build_options: +# extra_run_options: +# - name: +# ... +# - name: +# tests: +# - name: +# uvm_testname: (defaults to test_name) +# testbench: (defaults to last tb name seen) +# repeat: (defaults to 1) +# seeds: [,,...,] (defaults to all random) +# extra_test_options: +# - name: +# ... +# - name: +# include: +# - (relative path reference is to the including YAML file) +# - +# ... +# - + +uvmf_testlist: + testbenches: +# pragma uvmf custom tb_info begin + - name: block_3 + extra_build_options: "UVMF_VIP_LIBRARY_HOME=../../../../../../../../verification_ip UVMF_PROJECT_DIR=../../../../../../../block_3" + extra_run_options: "" +# pragma uvmf custom tb_info end + tests: + - testbench: block_3 +# pragma uvmf custom regression_suite begin + - name: test_top + repeat: 3 +# pragma uvmf custom regression_suite end + + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_3/sim/top.compile b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_3/sim/top.compile new file mode 100644 index 00000000..efd51c07 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_3/sim/top.compile @@ -0,0 +1,3 @@ +needs: + - hvl.compile + - hdl.compile diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_3/sim/veloce.config b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_3/sim/veloce.config new file mode 100644 index 00000000..d0975155 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_3/sim/veloce.config @@ -0,0 +1,26 @@ + + + + + +# pragma uvmf custom additional begin +comp -num_boards 1 +comp -hvl questa +# Please choose the correct emulator type code for +# comp -platform command or else velcomp will fail +# Available types are: +# - Veloce2 Quattro: D2 +# - Veloce2 Maximus: D2M +# - Veloce Strato TiL, Ti, and Mi: Strato +# - Veloce Strato M and Strato T: StratoM +# - comp -platform +comp -platform Strato + +rtlc -enable_tbx_pragma_checks +rtlc -allow_4ST +rtlc -allow_MDR +rtlc -compile_display +rtlc -xwave_siglist xwaves.sigs +# pragma uvmf custom additional end + + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_3/sim/viswave.do b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_3/sim/viswave.do new file mode 100644 index 00000000..6b69c9ea --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_3/sim/viswave.do @@ -0,0 +1,22 @@ + + +onerror resume +wave tags F0 +wave update off + +wave spacer -backgroundcolor Salmon { wb_master } +wave add uvm_test_top.environment.wb_master.wb_master_monitor.txn_stream -radix string -tag F0 +wave group wb_master_bus +wave add -group wb_master_bus hdl_top.wb_master_bus.* -radix hexadecimal -tag F0 +wave group wb_master_bus -collapse +wave insertion [expr [wave index insertpoint] +1] +wave spacer -backgroundcolor Salmon { axi_slave } +wave add uvm_test_top.environment.axi_slave.axi_slave_monitor.txn_stream -radix string -tag F0 +wave group axi_slave_bus +wave add -group axi_slave_bus hdl_top.axi_slave_bus.* -radix hexadecimal -tag F0 +wave group axi_slave_bus -collapse +wave insertion [expr [wave index insertpoint] +1] + +wave update on +WaveSetStreamView + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_3/sim/wave.do b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_3/sim/wave.do new file mode 100644 index 00000000..ad8536c6 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_3/sim/wave.do @@ -0,0 +1,30 @@ + + +onerror {resume} +quietly WaveActivateNextPane {} 0 + +add wave -noupdate -divider wb_master +add wave -noupdate /uvm_root/uvm_test_top/environment/wb_master/wb_master_monitor/txn_stream +add wave -noupdate -group wb_master_bus /hdl_top/wb_master_bus/* +add wave -noupdate -divider axi_slave +add wave -noupdate /uvm_root/uvm_test_top/environment/axi_slave/axi_slave_monitor/txn_stream +add wave -noupdate -group axi_slave_bus /hdl_top/axi_slave_bus/* + +TreeUpdate [SetDefaultTree] +quietly wave cursor active 0 +configure wave -namecolwidth 472 +configure wave -valuecolwidth 100 +configure wave -justifyvalue left +configure wave -signalnamewidth 0 +configure wave -snapdistance 10 +configure wave -datasetprefix 0 +configure wave -rowmargin 4 +configure wave -childrowmargin 2 +configure wave -gridoffset 0 +configure wave -gridperiod 1 +configure wave -griddelta 40 +configure wave -timeline 0 +configure wave -timelineunits ns +update +WaveRestoreZoom {27 ns} {168 ns} + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_3/sim/xwaves.sigs b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_3/sim/xwaves.sigs new file mode 100644 index 00000000..d75f0a57 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_3/sim/xwaves.sigs @@ -0,0 +1,17 @@ + + + + + +# pragma uvmf custom additional begin + +Group All + +#Top level signals +hdl_top.* +#Add additional levels or individual signals as needed +hdl_top.*.* + +# pragma uvmf custom additional end + + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_3/tb/parameters/block_3_parameters_pkg.compile b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_3/tb/parameters/block_3_parameters_pkg.compile new file mode 100644 index 00000000..5315773a --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_3/tb/parameters/block_3_parameters_pkg.compile @@ -0,0 +1,4 @@ +needs: + - $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg_hdl.compile +src: + - block_3_parameters_pkg.sv diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_3/tb/parameters/block_3_parameters_pkg.sv b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_3/tb/parameters/block_3_parameters_pkg.sv new file mode 100644 index 00000000..f20beb1c --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_3/tb/parameters/block_3_parameters_pkg.sv @@ -0,0 +1,39 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This package contains test level parameters +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +`ifndef BLOCK_3_PARAMETERS_PKG_BENCH +`define BLOCK_3_PARAMETERS_PKG_BENCH + +package block_3_parameters_pkg; + + import uvmf_base_pkg_hdl::*; + + // pragma uvmf custom package_imports_additional begin + // pragma uvmf custom package_imports_additional end + + + // These parameters are used to uniquely identify each interface. The monitor_bfm and + // driver_bfm are placed into and retrieved from the uvm_config_db using these string + // names as the field_name. The parameter is also used to enable transaction viewing + // from the command line for selected interfaces using the UVM command line processing. + parameter string wb_master_BFM = "wb_master_BFM"; /* [0] */ + parameter string axi_slave_BFM = "axi_slave_BFM"; /* [1] */ + + // pragma uvmf custom package_item_additional begin + // pragma uvmf custom package_item_additional end + +endpackage + +// pragma uvmf custom external begin +// pragma uvmf custom external end +`endif diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_3/tb/parameters/block_3_parameters_pkg.vinfo b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_3/tb/parameters/block_3_parameters_pkg.vinfo new file mode 100644 index 00000000..2e4b56d0 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_3/tb/parameters/block_3_parameters_pkg.vinfo @@ -0,0 +1,2 @@ +@use $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg_hdl.vinfo +block_3_parameters_pkg.sv diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_3/tb/sequences/block_3_sequences_pkg.compile b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_3/tb/sequences/block_3_sequences_pkg.compile new file mode 100644 index 00000000..bb608184 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_3/tb/sequences/block_3_sequences_pkg.compile @@ -0,0 +1,8 @@ +needs: + - $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg.compile + - ../../../../verification_ip/interface_packages/wb_m_pkg/wb_m.compile + - ../../../../verification_ip/interface_packages/axi_s_pkg/axi_s.compile + - ../../../../verification_ip/environment_packages/block_3_env_pkg/block_3_env_pkg.compile + - ../parameters/block_3_parameters_pkg.compile +src: + - block_3_sequences_pkg.sv diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_3/tb/sequences/block_3_sequences_pkg.sv b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_3/tb/sequences/block_3_sequences_pkg.sv new file mode 100644 index 00000000..b7ce57cf --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_3/tb/sequences/block_3_sequences_pkg.sv @@ -0,0 +1,52 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This package includes all high level sequence classes used +// in the environment. These include utility sequences and top +// level sequences. +// +// CONTAINS: +// - +// - +// +//---------------------------------------------------------------------- +// +//---------------------------------------------------------------------- +// +`ifndef BLOCK_3_SEQUENCES_PKG_BENCH +`define BLOCK_3_SEQUENCES_PKG_BENCH +package block_3_sequences_pkg; + import uvm_pkg::*; + import uvmf_base_pkg::*; + import wb_m_pkg::*; + import wb_m_pkg_hdl::*; + import axi_s_pkg::*; + import axi_s_pkg_hdl::*; + import block_3_parameters_pkg::*; + import block_3_env_pkg::*; + `include "uvm_macros.svh" + + // pragma uvmf custom package_imports_additional begin + // pragma uvmf custom package_imports_additional end + + `include "src/block_3_bench_sequence_base.svh" + `include "src/register_test_sequence.svh" + `include "src/example_derived_test_sequence.svh" + + // pragma uvmf custom package_item_additional begin + // UVMF_CHANGE_ME : When adding new sequences to the src directory + // be sure to add the sequence file here so that it will be + // compiled as part of the sequence package. Be sure to place + // the new sequence after any base sequences of the new sequence. + // pragma uvmf custom package_item_additional end + +endpackage + +// pragma uvmf custom external begin +// pragma uvmf custom external end +`endif diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_3/tb/sequences/block_3_sequences_pkg.vinfo b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_3/tb/sequences/block_3_sequences_pkg.vinfo new file mode 100644 index 00000000..1e7146b0 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_3/tb/sequences/block_3_sequences_pkg.vinfo @@ -0,0 +1,7 @@ +@use $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg.vinfo +@use $UVMF_VIP_LIBRARY_HOME/interface_packages/wb_m_pkg/wb_m_pkg.vinfo +@use $UVMF_VIP_LIBRARY_HOME/interface_packages/axi_s_pkg/axi_s_pkg.vinfo +@use $UVMF_VIP_LIBRARY_HOME/environment_packages/block_3_env_pkg/block_3_env_pkg.vinfo +@use $UVMF_PROJECT_DIR/tb/parameters/block_3_parameters_pkg.vinfo ++incdir+@vinfodir +block_3_sequences_pkg.sv diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_3/tb/sequences/src/block_3_bench_sequence_base.svh b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_3/tb/sequences/src/block_3_bench_sequence_base.svh new file mode 100644 index 00000000..80bcbaf4 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_3/tb/sequences/src/block_3_bench_sequence_base.svh @@ -0,0 +1,129 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// Description: This file contains the top level and utility sequences +// used by test_top. It can be extended to create derivative top +// level sequences. +// +//---------------------------------------------------------------------- +// +//---------------------------------------------------------------------- +// +`ifndef BLOCK_3_BENCH_SEQUENCE_BASE +`define BLOCK_3_BENCH_SEQUENCE_BASE + +typedef block_3_env_configuration block_3_env_configuration_t; + +class block_3_bench_sequence_base extends uvmf_sequence_base #(uvm_sequence_item); + + `uvm_object_utils( block_3_bench_sequence_base ); + + // pragma uvmf custom sequences begin + +typedef block_3_env_sequence_base #( + .CONFIG_T(block_3_env_configuration_t) + ) + block_3_env_sequence_base_t; +rand block_3_env_sequence_base_t block_3_env_seq; + + + + // UVMF_CHANGE_ME : Instantiate, construct, and start sequences as needed to create stimulus scenarios. + // Instantiate sequences here + typedef wb_m_random_sequence wb_master_random_seq_t; + wb_master_random_seq_t wb_master_random_seq; + typedef axi_s_responder_sequence axi_slave_responder_seq_t; + axi_slave_responder_seq_t axi_slave_responder_seq; + // pragma uvmf custom sequences end + + // Sequencer handles for each active interface in the environment + typedef wb_m_transaction wb_master_transaction_t; + uvm_sequencer #(wb_master_transaction_t) wb_master_sequencer; + typedef axi_s_transaction axi_slave_transaction_t; + uvm_sequencer #(axi_slave_transaction_t) axi_slave_sequencer; + + + // Top level environment configuration handle + block_3_env_configuration_t top_configuration; + + // Configuration handles to access interface BFM's + wb_m_configuration wb_master_config; + axi_s_configuration axi_slave_config; + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + // **************************************************************************** + function new( string name = "" ); + super.new( name ); + // Retrieve the configuration handles from the uvm_config_db + + // Retrieve top level configuration handle + if ( !uvm_config_db#(block_3_env_configuration_t)::get(null,UVMF_CONFIGURATIONS, "TOP_ENV_CONFIG",top_configuration) ) begin + `uvm_info("CFG", "*** FATAL *** uvm_config_db::get can not find TOP_ENV_CONFIG. Are you using an older UVMF release than what was used to generate this bench?",UVM_NONE); + `uvm_fatal("CFG", "uvm_config_db#(block_3_env_configuration_t)::get cannot find resource TOP_ENV_CONFIG"); + end + + // Retrieve config handles for all agents + if( !uvm_config_db #( wb_m_configuration )::get( null , UVMF_CONFIGURATIONS , wb_master_BFM , wb_master_config ) ) + `uvm_fatal("CFG" , "uvm_config_db #( wb_m_configuration )::get cannot find resource wb_master_BFM" ) + if( !uvm_config_db #( axi_s_configuration )::get( null , UVMF_CONFIGURATIONS , axi_slave_BFM , axi_slave_config ) ) + `uvm_fatal("CFG" , "uvm_config_db #( axi_s_configuration )::get cannot find resource axi_slave_BFM" ) + + // Assign the sequencer handles from the handles within agent configurations + wb_master_sequencer = wb_master_config.get_sequencer(); + axi_slave_sequencer = axi_slave_config.get_sequencer(); + + + + // pragma uvmf custom new begin + // pragma uvmf custom new end + + endfunction + + // **************************************************************************** + virtual task body(); + // pragma uvmf custom body begin + + // Construct sequences here + + block_3_env_seq = block_3_env_sequence_base_t::type_id::create("block_3_env_seq"); + + wb_master_random_seq = wb_master_random_seq_t::type_id::create("wb_master_random_seq"); + axi_slave_responder_seq = axi_slave_responder_seq_t::type_id::create("axi_slave_responder_seq"); + fork + wb_master_config.wait_for_reset(); + axi_slave_config.wait_for_reset(); + join + // Start RESPONDER sequences here + fork + axi_slave_responder_seq.start(axi_slave_sequencer); + join_none + // Start INITIATOR sequences here + fork + repeat (25) wb_master_random_seq.start(wb_master_sequencer); + join + +block_3_env_seq.start(top_configuration.vsqr); + + // UVMF_CHANGE_ME : Extend the simulation XXX number of clocks after + // the last sequence to allow for the last sequence item to flow + // through the design. + fork + wb_master_config.wait_for_num_clocks(400); + axi_slave_config.wait_for_num_clocks(400); + join + + // pragma uvmf custom body end + endtask + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end +`endif diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_3/tb/sequences/src/example_derived_test_sequence.svh b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_3/tb/sequences/src/example_derived_test_sequence.svh new file mode 100644 index 00000000..d98bb84d --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_3/tb/sequences/src/example_derived_test_sequence.svh @@ -0,0 +1,31 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +// +//---------------------------------------------------------------------- +// +// DESCRIPTION: This file contains the top level sequence used in example_derived_test. +// It is an example of a sequence that is extended from %(benchName)_bench_sequence_base +// and can override %(benchName)_bench_sequence_base. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +`ifndef EXAMPLE_DERIVED_TEST_SEQUENCE +`define EXAMPLE_DERIVED_TEST_SEQUENCE +class example_derived_test_sequence extends block_3_bench_sequence_base; + + `uvm_object_utils( example_derived_test_sequence ); + + function new(string name = "" ); + super.new(name); + endfunction + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end +`endif diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_3/tb/sequences/src/register_test_sequence.svh b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_3/tb/sequences/src/register_test_sequence.svh new file mode 100644 index 00000000..621db148 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_3/tb/sequences/src/register_test_sequence.svh @@ -0,0 +1,58 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This file contains the top level sequence used in register_test. +// It uses the UVM built in register test. Specific UVM built-in tests can be +// selected in the body task. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +`ifndef REGISTER_TEST_SEQUENCE +`define REGISTER_TEST_SEQUENCE +class register_test_sequence extends block_3_bench_sequence_base; + + `uvm_object_utils( register_test_sequence ); + + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + function new(string name = "" ); + super.new(name); + endfunction + + // **************************************************************************** + virtual task body(); + + // Reset the DUT + fork + // pragma uvmf custom register_test_reset begin + // UVMF_CHANGE_ME + // Select the desired wait_for_reset or provide custom mechanism. + // fork-join for this code block may be unnecessary based on your situation. + wb_master_config.wait_for_reset(); + axi_slave_config.wait_for_reset(); + // pragma uvmf custom register_test_reset end + join + + // pragma uvmf custom register_test_setup begin + // UVMF_CHANGE_ME perform potentially necessary operations before running the sequence. + // pragma uvmf custom register_test_setup end + + // pragma uvmf custom register_test_operation begin + // UVMF_CHANGE_ME Perform your custom register test + // pragma uvmf custom register_test_operation end + + endtask + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end +`endif diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_3/tb/testbench/hdl_top.compile b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_3/tb/testbench/hdl_top.compile new file mode 100644 index 00000000..e5040eb0 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_3/tb/testbench/hdl_top.compile @@ -0,0 +1,10 @@ +incdir: + - ${uvm_path}/src + - . +needs: + - $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg_hdl.compile + - ../parameters/block_3_parameters_pkg.compile + - ../../../../verification_ip/interface_packages/wb_m_pkg/wb_m_hdl.compile + - ../../../../verification_ip/interface_packages/axi_s_pkg/axi_s_hdl.compile +src: + - hdl_top.sv diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_3/tb/testbench/hdl_top.sv b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_3/tb/testbench/hdl_top.sv new file mode 100644 index 00000000..1f2599cb --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_3/tb/testbench/hdl_top.sv @@ -0,0 +1,101 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// Description: This top level module instantiates all synthesizable +// static content. This and tb_top.sv are the two top level modules +// of the simulation. +// +// This module instantiates the following: +// DUT: The Design Under Test +// Interfaces: Signal bundles that contain signals connected to DUT +// Driver BFM's: BFM's that actively drive interface signals +// Monitor BFM's: BFM's that passively monitor interface signals +// +//---------------------------------------------------------------------- + +//---------------------------------------------------------------------- +// + +module hdl_top; + +import block_3_parameters_pkg::*; +import uvmf_base_pkg_hdl::*; + + // pragma attribute hdl_top partition_module_xrtl +// pragma uvmf custom clock_generator begin + bit clk; + // Instantiate a clk driver + // tbx clkgen + initial begin + clk = 0; + #9ns; + forever begin + clk = ~clk; + #5ns; + end + end +// pragma uvmf custom clock_generator end + +// pragma uvmf custom reset_generator begin + bit rst; + // Instantiate a rst driver + // tbx clkgen + initial begin + rst = 1; + #200ns; + rst = 0; + end +// pragma uvmf custom reset_generator end + + // pragma uvmf custom module_item_additional begin + // pragma uvmf custom module_item_additional end + + // Instantiate the signal bundle, monitor bfm and driver bfm for each interface. + // The signal bundle, _if, contains signals to be connected to the DUT. + // The monitor, monitor_bfm, observes the bus, _if, and captures transactions. + // The driver, driver_bfm, drives transactions onto the bus, _if. + wb_m_if wb_master_bus( + // pragma uvmf custom wb_master_bus_connections begin + .clock(clk), .reset(rst) + // pragma uvmf custom wb_master_bus_connections end + ); + axi_s_if axi_slave_bus( + // pragma uvmf custom axi_slave_bus_connections begin + .axi_clk(clk), .rst(rst) + // pragma uvmf custom axi_slave_bus_connections end + ); + wb_m_monitor_bfm wb_master_mon_bfm(wb_master_bus.monitor_port); + axi_s_monitor_bfm axi_slave_mon_bfm(axi_slave_bus.monitor_port); + wb_m_driver_bfm wb_master_drv_bfm(wb_master_bus.initiator_port); + axi_s_driver_bfm axi_slave_drv_bfm(axi_slave_bus.responder_port); + + // pragma uvmf custom dut_instantiation begin + // UVMF_CHANGE_ME : Add DUT and connect to signals in _bus interfaces listed above + // Instantiate your DUT here + // These DUT's instantiated to show verilog and vhdl instantiation + verilog_dut dut_verilog( .clk(clk), .rst(rst), .in_signal(vhdl_to_verilog_signal), .out_signal(verilog_to_vhdl_signal)); + vhdl_dut dut_vhdl ( .clk(clk), .rst(rst), .in_signal(verilog_to_vhdl_signal), .out_signal(vhdl_to_verilog_signal)); + // pragma uvmf custom dut_instantiation end + + initial begin // tbx vif_binding_block + import uvm_pkg::uvm_config_db; + // The monitor_bfm and driver_bfm for each interface is placed into the uvm_config_db. + // They are placed into the uvm_config_db using the string names defined in the parameters package. + // The string names are passed to the agent configurations by test_top through the top level configuration. + // They are retrieved by the agents configuration class for use by the agent. + uvm_config_db #( virtual wb_m_monitor_bfm )::set( null , UVMF_VIRTUAL_INTERFACES , wb_master_BFM , wb_master_mon_bfm ); + uvm_config_db #( virtual axi_s_monitor_bfm )::set( null , UVMF_VIRTUAL_INTERFACES , axi_slave_BFM , axi_slave_mon_bfm ); + uvm_config_db #( virtual wb_m_driver_bfm )::set( null , UVMF_VIRTUAL_INTERFACES , wb_master_BFM , wb_master_drv_bfm ); + uvm_config_db #( virtual axi_s_driver_bfm )::set( null , UVMF_VIRTUAL_INTERFACES , axi_slave_BFM , axi_slave_drv_bfm ); + end + +endmodule + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_3/tb/testbench/hdl_top.vinfo b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_3/tb/testbench/hdl_top.vinfo new file mode 100644 index 00000000..881203b6 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_3/tb/testbench/hdl_top.vinfo @@ -0,0 +1,6 @@ +@use $UVMF_PROJECT_DIR/rtl/verilog/verilog_dut.vinfo +@use $UVMF_PROJECT_DIR/tb/parameters/block_3_parameters_pkg.vinfo +@use $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg_hdl.vinfo +@use $UVMF_VIP_LIBRARY_HOME/interface_packages/wb_m_pkg/wb_m_bfm.vinfo +@use $UVMF_VIP_LIBRARY_HOME/interface_packages/axi_s_pkg/axi_s_bfm.vinfo +hdl_top.sv diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_3/tb/testbench/hvl_top.compile b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_3/tb/testbench/hvl_top.compile new file mode 100644 index 00000000..d9bfbc86 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_3/tb/testbench/hvl_top.compile @@ -0,0 +1,7 @@ +incdir: + - ${uvm_path}/src + - . +needs: + - ../tests/block_3_tests_pkg.compile +src: + - hvl_top.sv diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_3/tb/testbench/hvl_top.sv b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_3/tb/testbench/hvl_top.sv new file mode 100644 index 00000000..785b6f37 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_3/tb/testbench/hvl_top.sv @@ -0,0 +1,33 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +// +//---------------------------------------------------------------------- +// +// DESCRIPTION: This module loads the test package and starts the UVM phases. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// + +module hvl_top; + +import uvm_pkg::*; +import block_3_tests_pkg::*; + + // pragma uvmf custom module_item_additional begin + // pragma uvmf custom module_item_additional end + + initial begin + $timeformat(-9,3,"ns",5); + run_test(); + end + +endmodule + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_3/tb/testbench/hvl_top.vinfo b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_3/tb/testbench/hvl_top.vinfo new file mode 100644 index 00000000..fe43bc9c --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_3/tb/testbench/hvl_top.vinfo @@ -0,0 +1,2 @@ +@use $UVMF_PROJECT_DIR/tb/tests/block_3_tests_pkg.vinfo +hvl_top.sv diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_3/tb/testbench/top_filelist_hdl.f b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_3/tb/testbench/top_filelist_hdl.f new file mode 100644 index 00000000..1e9dab65 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_3/tb/testbench/top_filelist_hdl.f @@ -0,0 +1,3 @@ +$UVMF_PROJECT_DIR/tb/testbench/hdl_top.sv +// pragma uvmf custom additional begin +// pragma uvmf custom additional end diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_3/tb/testbench/top_filelist_hvl.f b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_3/tb/testbench/top_filelist_hvl.f new file mode 100644 index 00000000..42383ab2 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_3/tb/testbench/top_filelist_hvl.f @@ -0,0 +1,3 @@ +$UVMF_PROJECT_DIR/tb/testbench/hvl_top.sv +// pragma uvmf custom additional begin +// pragma uvmf custom additional end diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_3/tb/tests/block_3_tests_pkg.compile b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_3/tb/tests/block_3_tests_pkg.compile new file mode 100644 index 00000000..344eca11 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_3/tb/tests/block_3_tests_pkg.compile @@ -0,0 +1,9 @@ +needs: + - $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg.compile + - ../../../../verification_ip/interface_packages/wb_m_pkg/wb_m.compile + - ../../../../verification_ip/interface_packages/axi_s_pkg/axi_s.compile + - ../../../../verification_ip/environment_packages/block_3_env_pkg/block_3_env_pkg.compile + - ../parameters/block_3_parameters_pkg.compile + - ../sequences/block_3_sequences_pkg.compile +src: + - block_3_tests_pkg.sv diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_3/tb/tests/block_3_tests_pkg.sv b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_3/tb/tests/block_3_tests_pkg.sv new file mode 100644 index 00000000..8267af0a --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_3/tb/tests/block_3_tests_pkg.sv @@ -0,0 +1,55 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This package contains all tests currently written for +// the simulation project. Once compiled, any test can be selected +// from the vsim command line using +UVM_TESTNAME=yourTestNameHere +// +// CONTAINS: +// - +// - +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +`ifndef BLOCK_3_TESTS_PKG +`define BLOCK_3_TESTS_PKG +package block_3_tests_pkg; + + import uvm_pkg::*; + import uvmf_base_pkg::*; + import block_3_parameters_pkg::*; + import block_3_env_pkg::*; + import block_3_sequences_pkg::*; + import wb_m_pkg::*; + import wb_m_pkg_hdl::*; + import axi_s_pkg::*; + import axi_s_pkg_hdl::*; + + + `include "uvm_macros.svh" + + // pragma uvmf custom package_imports_additional begin + // pragma uvmf custom package_imports_additional end + + `include "src/test_top.svh" + `include "src/register_test.svh" + `include "src/example_derived_test.svh" + + // pragma uvmf custom package_item_additional begin + // UVMF_CHANGE_ME : When adding new tests to the src directory + // be sure to add the test file here so that it will be + // compiled as part of the test package. Be sure to place + // the new test after any base tests of the new test. + // pragma uvmf custom package_item_additional end + +endpackage + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_3/tb/tests/block_3_tests_pkg.vinfo b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_3/tb/tests/block_3_tests_pkg.vinfo new file mode 100644 index 00000000..2fb6da4d --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_3/tb/tests/block_3_tests_pkg.vinfo @@ -0,0 +1,8 @@ +@use $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg.vinfo +@use $UVMF_VIP_LIBRARY_HOME/interface_packages/wb_m_pkg/wb_m_pkg.vinfo +@use $UVMF_VIP_LIBRARY_HOME/interface_packages/axi_s_pkg/axi_s_pkg.vinfo +@use $UVMF_VIP_LIBRARY_HOME/environment_packages/block_3_env_pkg/block_3_env_pkg.vinfo +@use $UVMF_PROJECT_DIR/tb/parameters/block_3_parameters_pkg.vinfo +@use $UVMF_PROJECT_DIR/tb/sequences/block_3_sequences_pkg.vinfo ++incdir+@vinfodir +block_3_tests_pkg.sv diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_3/tb/tests/src/example_derived_test.svh b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_3/tb/tests/src/example_derived_test.svh new file mode 100644 index 00000000..0b09dc83 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_3/tb/tests/src/example_derived_test.svh @@ -0,0 +1,44 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This test extends test_top and makes +// changes to test_top using the UVM factory type_override: +// +// Test scenario: +// This is a template test that can be used to create future tests. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +`ifndef EXAMPLE_DERIVED_TEST +`define EXAMPLE_DERIVED_TEST +class example_derived_test extends test_top; + + `uvm_component_utils( example_derived_test ); + + function new( string name = "", uvm_component parent = null ); + super.new( name, parent ); + endfunction + + virtual function void build_phase(uvm_phase phase); + // The factory override below is an example of how to replace the block_3_bench_sequence_base + // sequence with the example_derived_test_sequence. + block_3_bench_sequence_base::type_id::set_type_override(example_derived_test_sequence::get_type()); + // Execute the build_phase of test_top AFTER all factory overrides have been created. + super.build_phase(phase); + // pragma uvmf custom configuration_settings_post_randomize begin + // UVMF_CHANGE_ME Test specific configuration values can be set here. + // The configuration structure has already been randomized. + // pragma uvmf custom configuration_settings_post_randomize end + endfunction + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end +`endif diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_3/tb/tests/src/register_test.svh b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_3/tb/tests/src/register_test.svh new file mode 100644 index 00000000..0ff08048 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_3/tb/tests/src/register_test.svh @@ -0,0 +1,41 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This test extends test_top and makes +// changes to test_top using the UVM factory type_override: +// +// Test scenario: +// This is a template test that can be used to create future tests. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +`ifndef REGISTER_TEST +`define REGISTER_TEST +class register_test extends test_top; + + `uvm_component_utils( register_test ); + + function new( string name = "", uvm_component parent = null ); + super.new( name, parent ); + endfunction + + virtual function void build_phase(uvm_phase phase); + // The factory override below replaces the block_3_bench_sequence_base + // sequence with the register_test_sequence. + block_3_bench_sequence_base::type_id::set_type_override(register_test_sequence::get_type()); + // Execute the build_phase of test_top AFTER all factory overrides have been created. + super.build_phase(phase); + endfunction + + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end +`endif diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_3/tb/tests/src/test_top.svh b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_3/tb/tests/src/test_top.svh new file mode 100644 index 00000000..da9db550 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_3/tb/tests/src/test_top.svh @@ -0,0 +1,79 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// Description: This top level UVM test is the base class for all +// future tests created for this project. +// +// This test class contains: +// Configuration: The top level configuration for the project. +// Environment: The top level environment for the project. +// Top_level_sequence: The top level sequence for the project. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// + +typedef block_3_env_configuration block_3_env_configuration_t; +typedef block_3_environment block_3_environment_t; +`ifndef TEST_TOP +`define TEST_TOP +class test_top extends uvmf_test_base #(.CONFIG_T(block_3_env_configuration_t), + .ENV_T(block_3_environment_t), + .TOP_LEVEL_SEQ_T(block_3_bench_sequence_base)); + + `uvm_component_utils( test_top ); + + + + string interface_names[] = { + wb_master_BFM /* wb_master [0] */ , + axi_slave_BFM /* axi_slave [1] */ +}; + +uvmf_active_passive_t interface_activities[] = { + ACTIVE /* wb_master [0] */ , + ACTIVE /* axi_slave [1] */ }; + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + // **************************************************************************** + // FUNCTION: new() + // This is the standard systemVerilog constructor. All components are + // constructed in the build_phase to allow factory overriding. + // + function new( string name = "", uvm_component parent = null ); + super.new( name ,parent ); + endfunction + + + + // **************************************************************************** + // FUNCTION: build_phase() + // The construction of the configuration and environment classes is done in + // the build_phase of uvmf_test_base. Once the configuraton and environment + // classes are built then the initialize call is made to perform the + // following: + // Monitor and driver BFM virtual interface handle passing into agents + // Set the active/passive state for each agent + // Once this build_phase completes, the build_phase of the environment is + // executed which builds the agents. + // + virtual function void build_phase(uvm_phase phase); +// pragma uvmf custom build_phase_pre_super begin +// pragma uvmf custom build_phase_pre_super end + super.build_phase(phase); + // pragma uvmf custom configuration_settings_post_randomize begin + // pragma uvmf custom configuration_settings_post_randomize end + configuration.initialize(NA, "uvm_test_top.environment", interface_names, null, interface_activities); + endfunction + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end +`endif diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_3/yaml/block_3_bench.yaml b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_3/yaml/block_3_bench.yaml new file mode 100644 index 00000000..385d405c --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/block_3/yaml/block_3_bench.yaml @@ -0,0 +1,17 @@ +uvmf: + benches: + block_3: + active_passive: + - bfm_name: wb_master + value: ACTIVE + - bfm_name: axi_slave + value: ACTIVE + active_passive_default: ACTIVE + clock_half_period: 5ns + clock_phase_offset: 9ns + existing_library_component: 'True' + interface_params: [] + reset_assertion_level: 'True' + reset_duration: 200ns + top_env: block_3 + use_dpi_link: 'False' diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/subsys/.project b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/subsys/.project new file mode 100644 index 00000000..99203eb8 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/subsys/.project @@ -0,0 +1,37 @@ + + + subsys + + + + + + org.python.pydev.PyDevBuilder + + + + + net.sf.sveditor.core.SVProjectBuilder + + + + + + net.sf.sveditor.core.SVNature + org.python.pydev.pythonNature + + + + verification_ip + 2 + UVMF_VIP_LIBRARY_HOME + + + + + UVMF_VIP_LIBRARY_HOME + $%7BPARENT-2-PROJECT_LOC%7D/verification_ip + + + + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/subsys/.svproject b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/subsys/.svproject new file mode 100644 index 00000000..62740391 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/subsys/.svproject @@ -0,0 +1,16 @@ + + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/subsys/docs/interfaces.csv b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/subsys/docs/interfaces.csv new file mode 100644 index 00000000..8415ca38 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/subsys/docs/interfaces.csv @@ -0,0 +1,18 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// + +, +Interface Description, Interface Type, Interface Transaction, Interface Name, +b1_apb_master, apb_m_driver_bfm apb_m_monitor_bfm, apb_m_transaction, apb_m_pkg_b1_apb_master_BFM, +b1_axi_master1, axi_m_driver_bfm axi_m_monitor_bfm, axi_m_transaction, axi_m_pkg_b1_axi_master1_BFM, +b1_axi_master2, axi_m_driver_bfm axi_m_monitor_bfm, axi_m_transaction, axi_m_pkg_b1_axi_master2_BFM, +b1_spi_slave, spi_s_driver_bfm spi_s_monitor_bfm, spi_s_transaction, spi_s_pkg_b1_spi_slave_BFM, +b2_spi_master, spi_m_driver_bfm spi_m_monitor_bfm, spi_m_transaction, spi_m_pkg_b2_spi_master_BFM, +b2_wb_slave, wb_s_driver_bfm wb_s_monitor_bfm, wb_s_transaction, wb_s_pkg_b2_wb_slave_BFM, + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/subsys/rtl/dut.compile b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/subsys/rtl/dut.compile new file mode 100644 index 00000000..9b0008fc --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/subsys/rtl/dut.compile @@ -0,0 +1,6 @@ + +# pragma uvmf custom dut_compile_info begin +src: + - ./vhdl/vhdl_dut.vhd + - ./verilog/verilog_dut.v +# pragma uvmf custom dut_compile_info end diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/subsys/rtl/verilog/verilog_dut.v b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/subsys/rtl/verilog/verilog_dut.v new file mode 100644 index 00000000..96198441 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/subsys/rtl/verilog/verilog_dut.v @@ -0,0 +1,21 @@ +module verilog_dut(clk, rst, in_signal, out_signal); + +input clk; +input rst; +input in_signal; +output out_signal; + +reg out_signal_o; + +always @(posedge clk) begin + if (rst) begin + out_signal_o <= 0; + end + else begin + out_signal_o <= ~in_signal; + end + end + +assign out_signal = out_signal_o; + +endmodule diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/subsys/rtl/verilog/verilog_dut.vinfo b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/subsys/rtl/verilog/verilog_dut.vinfo new file mode 100644 index 00000000..87e95f36 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/subsys/rtl/verilog/verilog_dut.vinfo @@ -0,0 +1 @@ +verilog_dut.v diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/subsys/rtl/vhdl/vhdl_dut.vhd b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/subsys/rtl/vhdl/vhdl_dut.vhd new file mode 100644 index 00000000..904aa37d --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/subsys/rtl/vhdl/vhdl_dut.vhd @@ -0,0 +1,21 @@ +library ieee; +use ieee.std_logic_1164.all ; + +entity vhdl_dut is + port ( clk : in std_logic ; + rst : in std_logic ; + in_signal : in std_logic ; + out_signal :out std_logic + ); +end vhdl_dut; + +architecture rtl of vhdl_dut is + begin + P1: process + variable out_signal_o : std_logic; + begin + wait until clk'event and clk = '1'; + out_signal_o := in_signal; + out_signal <= out_signal_o; + end process; + end rtl; diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/subsys/sim/Makefile b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/subsys/sim/Makefile new file mode 100644 index 00000000..554483b2 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/subsys/sim/Makefile @@ -0,0 +1,202 @@ + +# +#---------------------------------------------------------------------- +# +# DESCRIPTION: This makefile includes the shared makefile and contains +# bench level make targets. +# +#---------------------------------------------------------------------- + + +# pragma uvmf custom additional begin +# pragma uvmf custom additional end + +# ********************************************************************************************* +# UVMF library directory: +# This variable points to the UVMF release where uvmf_base_pkg directory resides. +# This variable points to release code that is not user modified. +# This variable allows for UVMF release directories to reside independent of project related verification IP and project bench directories. +# This code below looks "upward" for directory starting with UVMF_* and returns first match for use with the release examples. +UVMF_HOME ?= ___PLEASE_SET_AN_ENVIRONMENT_VARIABLE_NAMED_UVMF_HOME_TO_POINT_TO_THE_UVMF_INSTALLATION___ + +# pragma uvmf custom exports begin +# +# Project(s) specific verification IP library: +# Directory where reusable verification packages for interfaces, environments, utilities, etc. reside. +# This variable allows for your verification IP to reside independent of project bench and UVMF release directories. +# For examples deployed with UVMF this will be $(UVMF_HOME)//verification_ip +export UVMF_VIP_LIBRARY_HOME ?= $(PWD)/../../../verification_ip +# +# Project specific bench: +# Directory where bench specific code is located. +# This variable allows for project_benches to reside independent of verification IP and UVMF release directories. +# For examples deployed with UVMF this will be $(UVMF_HOME)//project_benches/ +export UVMF_PROJECT_DIR ?= $(PWD)/.. +# +# +# pragma uvmf custom exports end +# ********************************************************************************************* + +## Check PATH for required vinfo scripts +PVAL := $(shell command -v make_filelist.py 2> /dev/null) +ifndef PVAL + MFLIST = $(UVMF_HOME)/scripts/make_filelist.py +else + MFLIST = make_filelist.py +endif + + +# Set test case specific Variables +TEST_NAME ?= test_top + +TEST_SEED ?= random +UVM_CLI_ARGS = + +# Usage of Veloce, etc. to be input by the user (subject to defaults) +USE_VELOCE ?= 0 + +# Usage of vinfo flow for generating file list +USE_VINFO ?= 0 + +# Usage of Veloce and Questa profilers +USE_VELOCE_PROFILER ?= 0 +USE_QUESTA_PROFILER ?= 0 + + +# Set project Variables +TEST_PLAN_NAME = subsys_TestPlan +REPORTING_DO_FILE = subsys_reports_script + + +# Include makefile that includes targets for UVM_VIP_Library packages +include $(UVMF_HOME)/scripts/Makefile + + + + +# Include all requisite interface package targets for this bench +include $(UVMF_VIP_LIBRARY_HOME)/interface_packages/apb_m_pkg/Makefile +include $(UVMF_VIP_LIBRARY_HOME)/interface_packages/axi_m_pkg/Makefile +include $(UVMF_VIP_LIBRARY_HOME)/interface_packages/spi_s_pkg/Makefile +include $(UVMF_VIP_LIBRARY_HOME)/interface_packages/spi_m_pkg/Makefile +include $(UVMF_VIP_LIBRARY_HOME)/interface_packages/wb_s_pkg/Makefile + +# Include all requisite environment package targets for this bench +include $(UVMF_VIP_LIBRARY_HOME)/environment_packages/subsys_env_pkg/Makefile + + + +# Add to default compile/load/run arguments +VCOM_ARGS += + +# Note: vsim-3009 error can be eliminated by adding -timescale 1ps/1ps to VLOG_ARGS + +VLOG_ARGS += $(UVM_DISABLE_FILE_LINE_CMD) + +VELANALYZE_ARGS += +VELANALYZE_HVL_ARGS += + +BATCH_VOPT_ARGS += +DEBUG_VOPT_ARGS += +EXTRA_VOPT_TOPS += +COMMON_VSIM_ARGS += +COMMON_VSIM_ARGS += + + +BATCH_VSIM_ARGS += #-uvmcontrol=none +DEBUG_VSIM_ARGS += +EXTRA_VSIM_TOPS += + +# pragma uvmf custom additional_args begin +# pragma uvmf custom additional_args end + + +# Project bench package source +subsys_PARAMETERS_PKG ?=\ +$(UVMF_PROJECT_DIR)/tb/parameters/subsys_parameters_pkg.sv + + +subsys_SEQUENCES_PKG ?=\ +$(UVMF_PROJECT_DIR)/tb/sequences/subsys_sequences_pkg.sv + + +subsys_TEST_PKG ?=\ +$(UVMF_PROJECT_DIR)/tb/tests/subsys_tests_pkg.sv + +# pragma uvmf custom dut_files begin +# UVMF_CHANGE_ME : Reference Verilog DUT source. +subsys_VERILOG_DUT ?=\ +$(UVMF_PROJECT_DIR)/rtl/verilog/verilog_dut.v + +# UVMF_CHANGE_ME : Reference VHDL DUT source. +subsys_VHDL_DUT ?=\ +$(UVMF_PROJECT_DIR)/rtl/vhdl/vhdl_dut.vhd +# pragma uvmf custom dut_files end + + +# Project bench package targets +COMP_subsys_PARAMETERS_PKG_TGT_0 = q_comp_subsys_parameters_pkg +COMP_subsys_PARAMETERS_PKG_TGT_1 = v_comp_subsys_parameters_pkg +COMP_subsys_PARAMETERS_PKG_TGT = $(COMP_subsys_PARAMETERS_PKG_TGT_$(USE_VELOCE)) + +comp_subsys_parameters_pkg: $(COMP_subsys_PARAMETERS_PKG_TGT) + +q_comp_subsys_parameters_pkg: + $(HVL_COMP_CMD) +incdir+$(UVMF_PROJECT_DIR)/tb/parameters $(subsys_PARAMETERS_PKG) + +v_comp_subsys_parameters_pkg: q_comp_subsys_parameters_pkg + $(HDL_COMP_CMD) +incdir+$(UVMF_PROJECT_DIR)/tb/parameters $(subsys_PARAMETERS_PKG) + + +comp_subsys_sequence_pkg: + $(HVL_COMP_CMD) +incdir+$(UVMF_PROJECT_DIR)/tb/sequences $(subsys_SEQUENCES_PKG) + +comp_subsys_tests_pkg: + $(HVL_COMP_CMD) +incdir+$(UVMF_PROJECT_DIR)/tb/tests $(subsys_TEST_PKG) + +# pragma uvmf custom dut_compile_make_target begin +# UVMF_CHANGE_ME : Add make target to compile your verilog dut here +comp_subsys_verilog_dut: + echo "Compile your verilog DUT here" + $(HDL_COMP_CMD) $(subsys_VERILOG_DUT) + +# UVMF_CHANGE_ME : Add make target to compile your vhdl dut here +comp_subsys_vhdl_dut: + echo "Compile your vhdl DUT here" + $(HDL_COMP_CMD_VHDL) $(subsys_VHDL_DUT) + +# UVMF_CHANGE_ME : Add make target to compile your dut here +comp_subsys_dut: comp_subsys_vhdl_dut comp_subsys_verilog_dut +# pragma uvmf custom dut_compile_make_target end + + +BUILD_TGT_0 = make_build +BUILD_TGT_1 = vinfo_build +BUILD_TGT = $(BUILD_TGT_$(USE_VINFO)) + + +comp_hvl : comp_hvl_core + + +comp_hvl_core : \ + comp_apb_m_pkg comp_axi_m_pkg comp_spi_s_pkg comp_spi_m_pkg comp_wb_s_pkg \ + comp_subsys_env_pkg \ + comp_subsys_parameters_pkg comp_subsys_sequence_pkg comp_subsys_tests_pkg + +comp_uvmf_core : comp_uvm_pkg comp_uvmf_base_pkg + +make_build: comp_subsys_dut comp_uvmf_core comp_hvl comp_test_bench + +hvl_build: q_comp_apb_m_pkg q_comp_axi_m_pkg q_comp_spi_s_pkg q_comp_spi_m_pkg q_comp_wb_s_pkg comp_subsys_env_pkg comp_subsys_sequence_pkg comp_subsys_tests_pkg hvl_comp_testbench link optimize + + +vinfo_build: comp_subsys_vhdl_dut build_hdl_vinfo build_hvl_vinfo $(VINFO_TGT) + + $(HDL_COMP_CMD) -F hdl.vf + $(VEL_COMP) + +build: $(BUILD_TGT) + +# pragma uvmf custom additional_targets begin +# pragma uvmf custom additional_targets end + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/subsys/sim/bcr_testlist b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/subsys/sim/bcr_testlist new file mode 100644 index 00000000..a4aae156 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/subsys/sim/bcr_testlist @@ -0,0 +1,19 @@ + + + +# Test list for use by RMDB file +# File syntax is +# TB_INFO { } { } +# TB ## All subsequent tests will run on this bench until a different "TB" line is seen +# TEST <1st_seed> ... +# If not enough seeds are provided then random seeds are used to pad +# If no repeat count is given, default is 1 +# pragma uvmf custom tb_info begin +TB_INFO subsys { } { } +# pragma uvmf custom tb_info end +TB subsys +# pragma uvmf custom regression_suite begin +TEST test_top 3 +# pragma uvmf custom regression_suite end + + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/subsys/sim/bcr_testlist.yaml b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/subsys/sim/bcr_testlist.yaml new file mode 100644 index 00000000..27abcd04 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/subsys/sim/bcr_testlist.yaml @@ -0,0 +1,44 @@ + + + +# YAML test list for use by RMDB file +# File syntax is +# uvmf_testlist: +# testbenches: +# - name: +# extra_build_options: +# extra_run_options: +# - name: +# ... +# - name: +# tests: +# - name: +# uvm_testname: (defaults to test_name) +# testbench: (defaults to last tb name seen) +# repeat: (defaults to 1) +# seeds: [,,...,] (defaults to all random) +# extra_test_options: +# - name: +# ... +# - name: +# include: +# - (relative path reference is to the including YAML file) +# - +# ... +# - + +uvmf_testlist: + testbenches: +# pragma uvmf custom tb_info begin + - name: subsys + extra_build_options: "" + extra_run_options: "" +# pragma uvmf custom tb_info end + tests: + - testbench: subsys +# pragma uvmf custom regression_suite begin + - name: test_top + repeat: 3 +# pragma uvmf custom regression_suite end + + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/subsys/sim/compile.do b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/subsys/sim/compile.do new file mode 100644 index 00000000..489d3e86 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/subsys/sim/compile.do @@ -0,0 +1,74 @@ + + +################################################################## +## ENVIRONMENT VARIABLES +################################################################## +quietly set ::env(UVMF_VIP_LIBRARY_HOME) ../../../verification_ip +quietly set ::env(UVMF_PROJECT_DIR) .. + +## Using VRM means that the build is occuring several more directories deeper underneath +## the sim directory, need to prepend some more '..' +if {[info exists ::env(VRM_BUILD)]} { + quietly set ::env(UVMF_VIP_LIBRARY_HOME) "../../../../../$::env(UVMF_VIP_LIBRARY_HOME)" + quietly set ::env(UVMF_PROJECT_DIR) "../../../../../$::env(UVMF_PROJECT_DIR)" +} +quietly set ::env(UVMF_VIP_LIBRARY_HOME) [file normalize $::env(UVMF_VIP_LIBRARY_HOME)] +quietly set ::env(UVMF_PROJECT_DIR) [file normalize $::env(UVMF_PROJECT_DIR)] +quietly echo "UVMF_VIP_LIBRARY_HOME = $::env(UVMF_VIP_LIBRARY_HOME)" +quietly echo "UVMF_PROJECT_DIR = $::env(UVMF_PROJECT_DIR)" + + +################################################################### +## HOUSEKEEPING : DELETE FILES THAT WILL BE REGENERATED +################################################################### +file delete -force *~ *.ucdb vsim.dbg *.vstf *.log work *.mem *.transcript.txt certe_dump.xml *.wlf covhtmlreport VRMDATA +file delete -force design.bin qwave.db dpiheader.h visualizer*.ses +file delete -force veloce.med veloce.wave veloce.map tbxbindings.h edsenv velrunopts.ini +file delete -force sv_connect.* + +################################################################### +## COMPILE DUT SOURCE CODE +################################################################### +vlib work +# pragma uvmf custom dut_compile_dofile_target begin +# UVMF_CHANGE_ME : Add commands to compile your dut here, replacing the default examples +vlog -sv -timescale 1ps/1ps -suppress 2223,2286 $env(UVMF_PROJECT_DIR)/rtl/verilog/verilog_dut.v +vcom $env(UVMF_PROJECT_DIR)/rtl/vhdl/vhdl_dut.vhd +# pragma uvmf custom dut_compile_dofile_target end + +################################################################### +## COMPILE UVMF BASE/COMMON SOURCE CODE +################################################################### +vlog -sv -timescale 1ps/1ps -suppress 2223 -suppress 2286 +incdir+$env(UVMF_HOME)/uvmf_base_pkg -F $env(UVMF_HOME)/uvmf_base_pkg/uvmf_base_pkg_filelist_hdl.f +vlog -sv -timescale 1ps/1ps -suppress 2223 -suppress 2286 +incdir+$env(UVMF_HOME)/uvmf_base_pkg -F $env(UVMF_HOME)/uvmf_base_pkg/uvmf_base_pkg_filelist_hvl.f + + +################################################################### +## UVMF INTERFACE COMPILATION +################################################################### +do $env(UVMF_VIP_LIBRARY_HOME)/interface_packages/apb_m_pkg/compile.do +do $env(UVMF_VIP_LIBRARY_HOME)/interface_packages/axi_m_pkg/compile.do +do $env(UVMF_VIP_LIBRARY_HOME)/interface_packages/spi_s_pkg/compile.do +do $env(UVMF_VIP_LIBRARY_HOME)/interface_packages/spi_m_pkg/compile.do +do $env(UVMF_VIP_LIBRARY_HOME)/interface_packages/wb_s_pkg/compile.do + +################################################################### +## UVMF ENVIRONMENT COMPILATION +################################################################### +do $env(UVMF_VIP_LIBRARY_HOME)/environment_packages/subsys_env_pkg/compile.do + +################################################################### +## UVMF BENCHES COMPILATION +################################################################### +vlog -sv -timescale 1ps/1ps -suppress 2223 -suppress 2286 +incdir+$env(UVMF_PROJECT_DIR)/tb/parameters $env(UVMF_PROJECT_DIR)/tb/parameters/subsys_parameters_pkg.sv +vlog -sv -timescale 1ps/1ps -suppress 2223 -suppress 2286 +incdir+$env(UVMF_PROJECT_DIR)/tb/sequences $env(UVMF_PROJECT_DIR)/tb/sequences/subsys_sequences_pkg.sv +vlog -sv -timescale 1ps/1ps -suppress 2223 -suppress 2286 +incdir+$env(UVMF_PROJECT_DIR)/tb/tests $env(UVMF_PROJECT_DIR)/tb/tests/subsys_tests_pkg.sv + +vlog -sv -timescale 1ps/1ps -suppress 2223 -suppress 2286 +incdir+$env(UVMF_PROJECT_DIR)/tb/testbench -F $env(UVMF_PROJECT_DIR)/tb/testbench/top_filelist_hdl.f +vlog -sv -timescale 1ps/1ps -suppress 2223 -suppress 2286 +incdir+$env(UVMF_PROJECT_DIR)/tb/testbench -F $env(UVMF_PROJECT_DIR)/tb/testbench/top_filelist_hvl.f + +################################################################### +## OPTIMIZATION +################################################################### +vopt hvl_top hdl_top -o optimized_batch_top_tb +vopt +acc hvl_top hdl_top -o optimized_debug_top_tb diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/subsys/sim/hdl.compile b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/subsys/sim/hdl.compile new file mode 100644 index 00000000..8e7bd41a --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/subsys/sim/hdl.compile @@ -0,0 +1,5 @@ +needs: +# pragma uvmf custom dut_compile_info begin + - ../rtl/dut.compile +# pragma uvmf custom dut_compile_info end + - ../tb/testbench/hdl_top.compile diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/subsys/sim/hdl.vinfo b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/subsys/sim/hdl.vinfo new file mode 100644 index 00000000..da27ec77 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/subsys/sim/hdl.vinfo @@ -0,0 +1 @@ +@use $UVMF_PROJECT_DIR/tb/testbench/hdl_top.vinfo diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/subsys/sim/hvl.compile b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/subsys/sim/hvl.compile new file mode 100644 index 00000000..ce952549 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/subsys/sim/hvl.compile @@ -0,0 +1,2 @@ +needs: + - ../tb/testbench/hvl_top.compile diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/subsys/sim/hvl.vinfo b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/subsys/sim/hvl.vinfo new file mode 100644 index 00000000..d22eff33 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/subsys/sim/hvl.vinfo @@ -0,0 +1 @@ +@use $UVMF_PROJECT_DIR/tb/testbench/hvl_top.vinfo diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/subsys/sim/run.do b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/subsys/sim/run.do new file mode 100644 index 00000000..101ddc48 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/subsys/sim/run.do @@ -0,0 +1,21 @@ + + +quietly set svLibs "" +quietly set extra_vsim_args "" + +################################################################### +## Check for additional vsim arguments passed using env var $UVMF_EXTRA_VSIM_ARGS +################################################################### +if {[info exists ::env(UVMF_EXTRA_VSIM_ARGS)]} { + echo "Adding more args to vsim command" + quietly set extra_vsim_args $::env(UVMF_EXTRA_VSIM_ARGS) +} + +################################################################## +## Launch Questa : generate vsim command line and execute +################################################################## +# pragma uvmf custom dut_run_dofile_target begin +# UVMF_CHANGE_ME : Change the UVM_TESTNAME plusarg to run a different test +quietly set cmd [format "vsim -i -sv_seed random +UVM_TESTNAME=test_top +UVM_VERBOSITY=UVM_HIGH -permit_unmatched_virtual_intf +notimingchecks -suppress 8887 %s %s -uvmcontrol=all -msgmode both -classdebug -assertdebug +uvm_set_config_int=*,enable_transaction_viewing,1 -do { set NoQuitOnFinish 1; onbreak {resume}; run 0; do wave.do; set PrefSource(OpenOnBreak) 0; radix hex showbase; } optimized_debug_top_tb" $svLibs $extra_vsim_args] +# pragma uvmf custom dut_run_dofile_target end +eval $cmd diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/subsys/sim/tbx.config b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/subsys/sim/tbx.config new file mode 100644 index 00000000..eec58168 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/subsys/sim/tbx.config @@ -0,0 +1,10 @@ + + + + + +comp -questa +velsyn -D1S +rtlc -allow_4ST + + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/subsys/sim/testlist b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/subsys/sim/testlist new file mode 100644 index 00000000..81ee4a56 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/subsys/sim/testlist @@ -0,0 +1,20 @@ + + + + +# Test list for use by RMDB file +# File syntax is +# TB_INFO { } { } +# TB ## All subsequent tests will run on this bench until a different "TB" line is seen +# TEST <1st_seed> ... +# If not enough seeds are provided then random seeds are used to pad +# If no repeat count is given, default is 1 +# pragma uvmf custom tb_info begin +TB_INFO subsys { UVMF_VIP_LIBRARY_HOME=../../../../../../../../verification_ip UVMF_PROJECT_DIR=../../../../../../../subsys } { } +# pragma uvmf custom tb_info end +TB subsys +# pragma uvmf custom regression_suite begin +TEST test_top 3 +# pragma uvmf custom regression_suite end + + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/subsys/sim/testlist.yaml b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/subsys/sim/testlist.yaml new file mode 100644 index 00000000..b8b6f60b --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/subsys/sim/testlist.yaml @@ -0,0 +1,44 @@ + + + +# YAML test list for use by RMDB file +# File syntax is +# uvmf_testlist: +# testbenches: +# - name: +# extra_build_options: +# extra_run_options: +# - name: +# ... +# - name: +# tests: +# - name: +# uvm_testname: (defaults to test_name) +# testbench: (defaults to last tb name seen) +# repeat: (defaults to 1) +# seeds: [,,...,] (defaults to all random) +# extra_test_options: +# - name: +# ... +# - name: +# include: +# - (relative path reference is to the including YAML file) +# - +# ... +# - + +uvmf_testlist: + testbenches: +# pragma uvmf custom tb_info begin + - name: subsys + extra_build_options: "UVMF_VIP_LIBRARY_HOME=../../../../../../../../verification_ip UVMF_PROJECT_DIR=../../../../../../../subsys" + extra_run_options: "" +# pragma uvmf custom tb_info end + tests: + - testbench: subsys +# pragma uvmf custom regression_suite begin + - name: test_top + repeat: 3 +# pragma uvmf custom regression_suite end + + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/subsys/sim/top.compile b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/subsys/sim/top.compile new file mode 100644 index 00000000..efd51c07 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/subsys/sim/top.compile @@ -0,0 +1,3 @@ +needs: + - hvl.compile + - hdl.compile diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/subsys/sim/veloce.config b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/subsys/sim/veloce.config new file mode 100644 index 00000000..d0975155 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/subsys/sim/veloce.config @@ -0,0 +1,26 @@ + + + + + +# pragma uvmf custom additional begin +comp -num_boards 1 +comp -hvl questa +# Please choose the correct emulator type code for +# comp -platform command or else velcomp will fail +# Available types are: +# - Veloce2 Quattro: D2 +# - Veloce2 Maximus: D2M +# - Veloce Strato TiL, Ti, and Mi: Strato +# - Veloce Strato M and Strato T: StratoM +# - comp -platform +comp -platform Strato + +rtlc -enable_tbx_pragma_checks +rtlc -allow_4ST +rtlc -allow_MDR +rtlc -compile_display +rtlc -xwave_siglist xwaves.sigs +# pragma uvmf custom additional end + + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/subsys/sim/viswave.do b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/subsys/sim/viswave.do new file mode 100644 index 00000000..18bcb537 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/subsys/sim/viswave.do @@ -0,0 +1,46 @@ + + +onerror resume +wave tags F0 +wave update off + +wave spacer -backgroundcolor Salmon { b1_apb_master } +wave add uvm_test_top.environment.b1.apb_master.apb_master_monitor.txn_stream -radix string -tag F0 +wave group b1_apb_master_bus +wave add -group b1_apb_master_bus hdl_top.b1_apb_master_bus.* -radix hexadecimal -tag F0 +wave group b1_apb_master_bus -collapse +wave insertion [expr [wave index insertpoint] +1] +wave spacer -backgroundcolor Salmon { b1_axi_master1 } +wave add uvm_test_top.environment.b1.axi_master1.axi_master1_monitor.txn_stream -radix string -tag F0 +wave group b1_axi_master1_bus +wave add -group b1_axi_master1_bus hdl_top.b1_axi_master1_bus.* -radix hexadecimal -tag F0 +wave group b1_axi_master1_bus -collapse +wave insertion [expr [wave index insertpoint] +1] +wave spacer -backgroundcolor Salmon { b1_axi_master2 } +wave add uvm_test_top.environment.b1.axi_master2.axi_master2_monitor.txn_stream -radix string -tag F0 +wave group b1_axi_master2_bus +wave add -group b1_axi_master2_bus hdl_top.b1_axi_master2_bus.* -radix hexadecimal -tag F0 +wave group b1_axi_master2_bus -collapse +wave insertion [expr [wave index insertpoint] +1] +wave spacer -backgroundcolor Salmon { b1_spi_slave } +wave add uvm_test_top.environment.b1.spi_slave.spi_slave_monitor.txn_stream -radix string -tag F0 +wave group b1_spi_slave_bus +wave add -group b1_spi_slave_bus hdl_top.b1_spi_slave_bus.* -radix hexadecimal -tag F0 +wave group b1_spi_slave_bus -collapse +wave insertion [expr [wave index insertpoint] +1] +wave spacer -backgroundcolor Salmon { b2_spi_master } +wave add uvm_test_top.environment.b2.spi_master.spi_master_monitor.txn_stream -radix string -tag F0 +wave group b2_spi_master_bus +wave add -group b2_spi_master_bus hdl_top.b2_spi_master_bus.* -radix hexadecimal -tag F0 +wave group b2_spi_master_bus -collapse +wave insertion [expr [wave index insertpoint] +1] +wave spacer -backgroundcolor Salmon { b2_wb_slave } +wave add uvm_test_top.environment.b2.wb_slave.wb_slave_monitor.txn_stream -radix string -tag F0 +wave group b2_wb_slave_bus +wave add -group b2_wb_slave_bus hdl_top.b2_wb_slave_bus.* -radix hexadecimal -tag F0 +wave group b2_wb_slave_bus -collapse +wave insertion [expr [wave index insertpoint] +1] + +wave update on +WaveSetStreamView + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/subsys/sim/wave.do b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/subsys/sim/wave.do new file mode 100644 index 00000000..f76bf238 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/subsys/sim/wave.do @@ -0,0 +1,42 @@ + + +onerror {resume} +quietly WaveActivateNextPane {} 0 + +add wave -noupdate -divider b1_apb_master +add wave -noupdate /uvm_root/uvm_test_top/environment.b1/apb_master/apb_master_monitor/txn_stream +add wave -noupdate -group b1_apb_master_bus /hdl_top/b1_apb_master_bus/* +add wave -noupdate -divider b1_axi_master1 +add wave -noupdate /uvm_root/uvm_test_top/environment.b1/axi_master1/axi_master1_monitor/txn_stream +add wave -noupdate -group b1_axi_master1_bus /hdl_top/b1_axi_master1_bus/* +add wave -noupdate -divider b1_axi_master2 +add wave -noupdate /uvm_root/uvm_test_top/environment.b1/axi_master2/axi_master2_monitor/txn_stream +add wave -noupdate -group b1_axi_master2_bus /hdl_top/b1_axi_master2_bus/* +add wave -noupdate -divider b1_spi_slave +add wave -noupdate /uvm_root/uvm_test_top/environment.b1/spi_slave/spi_slave_monitor/txn_stream +add wave -noupdate -group b1_spi_slave_bus /hdl_top/b1_spi_slave_bus/* +add wave -noupdate -divider b2_spi_master +add wave -noupdate /uvm_root/uvm_test_top/environment.b2/spi_master/spi_master_monitor/txn_stream +add wave -noupdate -group b2_spi_master_bus /hdl_top/b2_spi_master_bus/* +add wave -noupdate -divider b2_wb_slave +add wave -noupdate /uvm_root/uvm_test_top/environment.b2/wb_slave/wb_slave_monitor/txn_stream +add wave -noupdate -group b2_wb_slave_bus /hdl_top/b2_wb_slave_bus/* + +TreeUpdate [SetDefaultTree] +quietly wave cursor active 0 +configure wave -namecolwidth 472 +configure wave -valuecolwidth 100 +configure wave -justifyvalue left +configure wave -signalnamewidth 0 +configure wave -snapdistance 10 +configure wave -datasetprefix 0 +configure wave -rowmargin 4 +configure wave -childrowmargin 2 +configure wave -gridoffset 0 +configure wave -gridperiod 1 +configure wave -griddelta 40 +configure wave -timeline 0 +configure wave -timelineunits ns +update +WaveRestoreZoom {27 ns} {168 ns} + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/subsys/sim/xwaves.sigs b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/subsys/sim/xwaves.sigs new file mode 100644 index 00000000..d75f0a57 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/subsys/sim/xwaves.sigs @@ -0,0 +1,17 @@ + + + + + +# pragma uvmf custom additional begin + +Group All + +#Top level signals +hdl_top.* +#Add additional levels or individual signals as needed +hdl_top.*.* + +# pragma uvmf custom additional end + + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/subsys/subsys_sve.F b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/subsys/subsys_sve.F new file mode 100644 index 00000000..69b29dbd --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/subsys/subsys_sve.F @@ -0,0 +1,31 @@ + +// UVM ++incdir+${UVM_HOME}/src +${UVM_HOME}/src/uvm_pkg.sv + +// Common UVMF files +-f ${UVMF_HOME}/common/common_sve.f + +// BFM Files +-F ${UVMF_VIP_LIBRARY_HOME}/interface_packages/apb_m_pkg/apb_m_pkg_sve.F +-F ${UVMF_VIP_LIBRARY_HOME}/interface_packages/axi_m_pkg/axi_m_pkg_sve.F +-F ${UVMF_VIP_LIBRARY_HOME}/interface_packages/spi_s_pkg/spi_s_pkg_sve.F +-F ${UVMF_VIP_LIBRARY_HOME}/interface_packages/spi_m_pkg/spi_m_pkg_sve.F +-F ${UVMF_VIP_LIBRARY_HOME}/interface_packages/wb_s_pkg/wb_s_pkg_sve.F + +// Environment Files +-F ${UVMF_VIP_LIBRARY_HOME}/environment_packages/subsys_env_pkg/subsys_env_pkg_sve.F + +// Bench Files ++incdir+./tb/tests +./tb/tests/subsys_tests_pkg.sv + ++incdir+./tb/sequences +./tb/sequences/subsys_sequences_pkg.sv + ++incdir+./tb/parameters +./tb/parameters/subsys_parameters_pkg.sv + +./tb/testbench/hdl_top.sv +./tb/testbench/hvl_top.sv + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/subsys/tb/parameters/subsys_parameters_pkg.compile b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/subsys/tb/parameters/subsys_parameters_pkg.compile new file mode 100644 index 00000000..29e4d5fd --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/subsys/tb/parameters/subsys_parameters_pkg.compile @@ -0,0 +1,4 @@ +needs: + - $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg_hdl.compile +src: + - subsys_parameters_pkg.sv diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/subsys/tb/parameters/subsys_parameters_pkg.sv b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/subsys/tb/parameters/subsys_parameters_pkg.sv new file mode 100644 index 00000000..e32fff9f --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/subsys/tb/parameters/subsys_parameters_pkg.sv @@ -0,0 +1,43 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This package contains test level parameters +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +`ifndef SUBSYS_PARAMETERS_PKG_BENCH +`define SUBSYS_PARAMETERS_PKG_BENCH + +package subsys_parameters_pkg; + + import uvmf_base_pkg_hdl::*; + + // pragma uvmf custom package_imports_additional begin + // pragma uvmf custom package_imports_additional end + + + // These parameters are used to uniquely identify each interface. The monitor_bfm and + // driver_bfm are placed into and retrieved from the uvm_config_db using these string + // names as the field_name. The parameter is also used to enable transaction viewing + // from the command line for selected interfaces using the UVM command line processing. + parameter string b1_apb_master_BFM = "b1_apb_master_BFM"; /* [0] */ + parameter string b1_axi_master1_BFM = "b1_axi_master1_BFM"; /* [1] */ + parameter string b1_axi_master2_BFM = "b1_axi_master2_BFM"; /* [2] */ + parameter string b1_spi_slave_BFM = "b1_spi_slave_BFM"; /* [3] */ + parameter string b2_spi_master_BFM = "b2_spi_master_BFM"; /* [4] */ + parameter string b2_wb_slave_BFM = "b2_wb_slave_BFM"; /* [5] */ + + // pragma uvmf custom package_item_additional begin + // pragma uvmf custom package_item_additional end + +endpackage + +// pragma uvmf custom external begin +// pragma uvmf custom external end +`endif diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/subsys/tb/parameters/subsys_parameters_pkg.vinfo b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/subsys/tb/parameters/subsys_parameters_pkg.vinfo new file mode 100644 index 00000000..63c1753f --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/subsys/tb/parameters/subsys_parameters_pkg.vinfo @@ -0,0 +1,2 @@ +@use $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg_hdl.vinfo +subsys_parameters_pkg.sv diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/subsys/tb/sequences/src/example_derived_test_sequence.svh b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/subsys/tb/sequences/src/example_derived_test_sequence.svh new file mode 100644 index 00000000..dbc06aee --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/subsys/tb/sequences/src/example_derived_test_sequence.svh @@ -0,0 +1,31 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +// +//---------------------------------------------------------------------- +// +// DESCRIPTION: This file contains the top level sequence used in example_derived_test. +// It is an example of a sequence that is extended from %(benchName)_bench_sequence_base +// and can override %(benchName)_bench_sequence_base. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +`ifndef EXAMPLE_DERIVED_TEST_SEQUENCE +`define EXAMPLE_DERIVED_TEST_SEQUENCE +class example_derived_test_sequence extends subsys_bench_sequence_base; + + `uvm_object_utils( example_derived_test_sequence ); + + function new(string name = "" ); + super.new(name); + endfunction + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end +`endif diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/subsys/tb/sequences/src/register_test_sequence.svh b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/subsys/tb/sequences/src/register_test_sequence.svh new file mode 100644 index 00000000..c1cc1bcf --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/subsys/tb/sequences/src/register_test_sequence.svh @@ -0,0 +1,62 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This file contains the top level sequence used in register_test. +// It uses the UVM built in register test. Specific UVM built-in tests can be +// selected in the body task. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +`ifndef REGISTER_TEST_SEQUENCE +`define REGISTER_TEST_SEQUENCE +class register_test_sequence extends subsys_bench_sequence_base; + + `uvm_object_utils( register_test_sequence ); + + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + function new(string name = "" ); + super.new(name); + endfunction + + // **************************************************************************** + virtual task body(); + + // Reset the DUT + fork + // pragma uvmf custom register_test_reset begin + // UVMF_CHANGE_ME + // Select the desired wait_for_reset or provide custom mechanism. + // fork-join for this code block may be unnecessary based on your situation. + b1_apb_master_config.wait_for_reset(); + b1_axi_master1_config.wait_for_reset(); + b1_axi_master2_config.wait_for_reset(); + b1_spi_slave_config.wait_for_reset(); + b2_spi_master_config.wait_for_reset(); + b2_wb_slave_config.wait_for_reset(); + // pragma uvmf custom register_test_reset end + join + + // pragma uvmf custom register_test_setup begin + // UVMF_CHANGE_ME perform potentially necessary operations before running the sequence. + // pragma uvmf custom register_test_setup end + + // pragma uvmf custom register_test_operation begin + // UVMF_CHANGE_ME Perform your custom register test + // pragma uvmf custom register_test_operation end + + endtask + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end +`endif diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/subsys/tb/sequences/src/subsys_bench_sequence_base.svh b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/subsys/tb/sequences/src/subsys_bench_sequence_base.svh new file mode 100644 index 00000000..ca7dddd8 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/subsys/tb/sequences/src/subsys_bench_sequence_base.svh @@ -0,0 +1,163 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// Description: This file contains the top level and utility sequences +// used by test_top. It can be extended to create derivative top +// level sequences. +// +//---------------------------------------------------------------------- +// +//---------------------------------------------------------------------- +// +`ifndef SUBSYS_BENCH_SEQUENCE_BASE +`define SUBSYS_BENCH_SEQUENCE_BASE + +typedef subsys_env_configuration subsys_env_configuration_t; + +class subsys_bench_sequence_base extends uvmf_sequence_base #(uvm_sequence_item); + + `uvm_object_utils( subsys_bench_sequence_base ); + + // pragma uvmf custom sequences begin + +typedef subsys_env_sequence_base #( + .CONFIG_T(subsys_env_configuration_t) + ) + subsys_env_sequence_base_t; +rand subsys_env_sequence_base_t subsys_env_seq; + + + + // UVMF_CHANGE_ME : Instantiate, construct, and start sequences as needed to create stimulus scenarios. + // Instantiate sequences here + typedef apb_m_random_sequence b1_apb_master_random_seq_t; + b1_apb_master_random_seq_t b1_apb_master_random_seq; + typedef axi_m_random_sequence b1_axi_master1_random_seq_t; + b1_axi_master1_random_seq_t b1_axi_master1_random_seq; + typedef axi_m_random_sequence b1_axi_master2_random_seq_t; + b1_axi_master2_random_seq_t b1_axi_master2_random_seq; + typedef wb_s_responder_sequence b2_wb_slave_responder_seq_t; + b2_wb_slave_responder_seq_t b2_wb_slave_responder_seq; + // pragma uvmf custom sequences end + + // Sequencer handles for each active interface in the environment + typedef apb_m_transaction b1_apb_master_transaction_t; + uvm_sequencer #(b1_apb_master_transaction_t) b1_apb_master_sequencer; + typedef axi_m_transaction b1_axi_master1_transaction_t; + uvm_sequencer #(b1_axi_master1_transaction_t) b1_axi_master1_sequencer; + typedef axi_m_transaction b1_axi_master2_transaction_t; + uvm_sequencer #(b1_axi_master2_transaction_t) b1_axi_master2_sequencer; + typedef wb_s_transaction b2_wb_slave_transaction_t; + uvm_sequencer #(b2_wb_slave_transaction_t) b2_wb_slave_sequencer; + + + // Top level environment configuration handle + subsys_env_configuration_t top_configuration; + + // Configuration handles to access interface BFM's + apb_m_configuration b1_apb_master_config; + axi_m_configuration b1_axi_master1_config; + axi_m_configuration b1_axi_master2_config; + spi_s_configuration b1_spi_slave_config; + spi_m_configuration b2_spi_master_config; + wb_s_configuration b2_wb_slave_config; + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + // **************************************************************************** + function new( string name = "" ); + super.new( name ); + // Retrieve the configuration handles from the uvm_config_db + + // Retrieve top level configuration handle + if ( !uvm_config_db#(subsys_env_configuration_t)::get(null,UVMF_CONFIGURATIONS, "TOP_ENV_CONFIG",top_configuration) ) begin + `uvm_info("CFG", "*** FATAL *** uvm_config_db::get can not find TOP_ENV_CONFIG. Are you using an older UVMF release than what was used to generate this bench?",UVM_NONE); + `uvm_fatal("CFG", "uvm_config_db#(subsys_env_configuration_t)::get cannot find resource TOP_ENV_CONFIG"); + end + + // Retrieve config handles for all agents + if( !uvm_config_db #( apb_m_configuration )::get( null , UVMF_CONFIGURATIONS , b1_apb_master_BFM , b1_apb_master_config ) ) + `uvm_fatal("CFG" , "uvm_config_db #( apb_m_configuration )::get cannot find resource b1_apb_master_BFM" ) + if( !uvm_config_db #( axi_m_configuration )::get( null , UVMF_CONFIGURATIONS , b1_axi_master1_BFM , b1_axi_master1_config ) ) + `uvm_fatal("CFG" , "uvm_config_db #( axi_m_configuration )::get cannot find resource b1_axi_master1_BFM" ) + if( !uvm_config_db #( axi_m_configuration )::get( null , UVMF_CONFIGURATIONS , b1_axi_master2_BFM , b1_axi_master2_config ) ) + `uvm_fatal("CFG" , "uvm_config_db #( axi_m_configuration )::get cannot find resource b1_axi_master2_BFM" ) + if( !uvm_config_db #( spi_s_configuration )::get( null , UVMF_CONFIGURATIONS , b1_spi_slave_BFM , b1_spi_slave_config ) ) + `uvm_fatal("CFG" , "uvm_config_db #( spi_s_configuration )::get cannot find resource b1_spi_slave_BFM" ) + if( !uvm_config_db #( spi_m_configuration )::get( null , UVMF_CONFIGURATIONS , b2_spi_master_BFM , b2_spi_master_config ) ) + `uvm_fatal("CFG" , "uvm_config_db #( spi_m_configuration )::get cannot find resource b2_spi_master_BFM" ) + if( !uvm_config_db #( wb_s_configuration )::get( null , UVMF_CONFIGURATIONS , b2_wb_slave_BFM , b2_wb_slave_config ) ) + `uvm_fatal("CFG" , "uvm_config_db #( wb_s_configuration )::get cannot find resource b2_wb_slave_BFM" ) + + // Assign the sequencer handles from the handles within agent configurations + b1_apb_master_sequencer = b1_apb_master_config.get_sequencer(); + b1_axi_master1_sequencer = b1_axi_master1_config.get_sequencer(); + b1_axi_master2_sequencer = b1_axi_master2_config.get_sequencer(); + b2_wb_slave_sequencer = b2_wb_slave_config.get_sequencer(); + + + + // pragma uvmf custom new begin + // pragma uvmf custom new end + + endfunction + + // **************************************************************************** + virtual task body(); + // pragma uvmf custom body begin + + // Construct sequences here + + subsys_env_seq = subsys_env_sequence_base_t::type_id::create("subsys_env_seq"); + + b1_apb_master_random_seq = b1_apb_master_random_seq_t::type_id::create("b1_apb_master_random_seq"); + b1_axi_master1_random_seq = b1_axi_master1_random_seq_t::type_id::create("b1_axi_master1_random_seq"); + b1_axi_master2_random_seq = b1_axi_master2_random_seq_t::type_id::create("b1_axi_master2_random_seq"); + b2_wb_slave_responder_seq = b2_wb_slave_responder_seq_t::type_id::create("b2_wb_slave_responder_seq"); + fork + b1_apb_master_config.wait_for_reset(); + b1_axi_master1_config.wait_for_reset(); + b1_axi_master2_config.wait_for_reset(); + b1_spi_slave_config.wait_for_reset(); + b2_spi_master_config.wait_for_reset(); + b2_wb_slave_config.wait_for_reset(); + join + // Start RESPONDER sequences here + fork + b2_wb_slave_responder_seq.start(b2_wb_slave_sequencer); + join_none + // Start INITIATOR sequences here + fork + repeat (25) b1_apb_master_random_seq.start(b1_apb_master_sequencer); + repeat (25) b1_axi_master1_random_seq.start(b1_axi_master1_sequencer); + repeat (25) b1_axi_master2_random_seq.start(b1_axi_master2_sequencer); + join + +subsys_env_seq.start(top_configuration.vsqr); + + // UVMF_CHANGE_ME : Extend the simulation XXX number of clocks after + // the last sequence to allow for the last sequence item to flow + // through the design. + fork + b1_apb_master_config.wait_for_num_clocks(400); + b1_axi_master1_config.wait_for_num_clocks(400); + b1_axi_master2_config.wait_for_num_clocks(400); + b1_spi_slave_config.wait_for_num_clocks(400); + b2_spi_master_config.wait_for_num_clocks(400); + b2_wb_slave_config.wait_for_num_clocks(400); + join + + // pragma uvmf custom body end + endtask + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end +`endif diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/subsys/tb/sequences/subsys_sequences_pkg.compile b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/subsys/tb/sequences/subsys_sequences_pkg.compile new file mode 100644 index 00000000..9e332e90 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/subsys/tb/sequences/subsys_sequences_pkg.compile @@ -0,0 +1,11 @@ +needs: + - $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg.compile + - ../../../../verification_ip/interface_packages/apb_m_pkg/apb_m.compile + - ../../../../verification_ip/interface_packages/axi_m_pkg/axi_m.compile + - ../../../../verification_ip/interface_packages/spi_s_pkg/spi_s.compile + - ../../../../verification_ip/interface_packages/spi_m_pkg/spi_m.compile + - ../../../../verification_ip/interface_packages/wb_s_pkg/wb_s.compile + - ../../../../verification_ip/environment_packages/subsys_env_pkg/subsys_env_pkg.compile + - ../parameters/subsys_parameters_pkg.compile +src: + - subsys_sequences_pkg.sv diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/subsys/tb/sequences/subsys_sequences_pkg.sv b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/subsys/tb/sequences/subsys_sequences_pkg.sv new file mode 100644 index 00000000..cb3a5e76 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/subsys/tb/sequences/subsys_sequences_pkg.sv @@ -0,0 +1,58 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This package includes all high level sequence classes used +// in the environment. These include utility sequences and top +// level sequences. +// +// CONTAINS: +// - +// - +// +//---------------------------------------------------------------------- +// +//---------------------------------------------------------------------- +// +`ifndef SUBSYS_SEQUENCES_PKG_BENCH +`define SUBSYS_SEQUENCES_PKG_BENCH +package subsys_sequences_pkg; + import uvm_pkg::*; + import uvmf_base_pkg::*; + import apb_m_pkg::*; + import apb_m_pkg_hdl::*; + import axi_m_pkg::*; + import axi_m_pkg_hdl::*; + import spi_s_pkg::*; + import spi_s_pkg_hdl::*; + import spi_m_pkg::*; + import spi_m_pkg_hdl::*; + import wb_s_pkg::*; + import wb_s_pkg_hdl::*; + import subsys_parameters_pkg::*; + import subsys_env_pkg::*; + `include "uvm_macros.svh" + + // pragma uvmf custom package_imports_additional begin + // pragma uvmf custom package_imports_additional end + + `include "src/subsys_bench_sequence_base.svh" + `include "src/register_test_sequence.svh" + `include "src/example_derived_test_sequence.svh" + + // pragma uvmf custom package_item_additional begin + // UVMF_CHANGE_ME : When adding new sequences to the src directory + // be sure to add the sequence file here so that it will be + // compiled as part of the sequence package. Be sure to place + // the new sequence after any base sequences of the new sequence. + // pragma uvmf custom package_item_additional end + +endpackage + +// pragma uvmf custom external begin +// pragma uvmf custom external end +`endif diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/subsys/tb/sequences/subsys_sequences_pkg.vinfo b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/subsys/tb/sequences/subsys_sequences_pkg.vinfo new file mode 100644 index 00000000..019ac065 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/subsys/tb/sequences/subsys_sequences_pkg.vinfo @@ -0,0 +1,10 @@ +@use $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg.vinfo +@use $UVMF_VIP_LIBRARY_HOME/interface_packages/apb_m_pkg/apb_m_pkg.vinfo +@use $UVMF_VIP_LIBRARY_HOME/interface_packages/axi_m_pkg/axi_m_pkg.vinfo +@use $UVMF_VIP_LIBRARY_HOME/interface_packages/spi_s_pkg/spi_s_pkg.vinfo +@use $UVMF_VIP_LIBRARY_HOME/interface_packages/spi_m_pkg/spi_m_pkg.vinfo +@use $UVMF_VIP_LIBRARY_HOME/interface_packages/wb_s_pkg/wb_s_pkg.vinfo +@use $UVMF_VIP_LIBRARY_HOME/environment_packages/subsys_env_pkg/subsys_env_pkg.vinfo +@use $UVMF_PROJECT_DIR/tb/parameters/subsys_parameters_pkg.vinfo ++incdir+@vinfodir +subsys_sequences_pkg.sv diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/subsys/tb/testbench/hdl_top.compile b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/subsys/tb/testbench/hdl_top.compile new file mode 100644 index 00000000..15ba4874 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/subsys/tb/testbench/hdl_top.compile @@ -0,0 +1,13 @@ +incdir: + - ${uvm_path}/src + - . +needs: + - $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg_hdl.compile + - ../parameters/subsys_parameters_pkg.compile + - ../../../../verification_ip/interface_packages/apb_m_pkg/apb_m_hdl.compile + - ../../../../verification_ip/interface_packages/axi_m_pkg/axi_m_hdl.compile + - ../../../../verification_ip/interface_packages/spi_s_pkg/spi_s_hdl.compile + - ../../../../verification_ip/interface_packages/spi_m_pkg/spi_m_hdl.compile + - ../../../../verification_ip/interface_packages/wb_s_pkg/wb_s_hdl.compile +src: + - hdl_top.sv diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/subsys/tb/testbench/hdl_top.sv b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/subsys/tb/testbench/hdl_top.sv new file mode 100644 index 00000000..d00f22ab --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/subsys/tb/testbench/hdl_top.sv @@ -0,0 +1,133 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// Description: This top level module instantiates all synthesizable +// static content. This and tb_top.sv are the two top level modules +// of the simulation. +// +// This module instantiates the following: +// DUT: The Design Under Test +// Interfaces: Signal bundles that contain signals connected to DUT +// Driver BFM's: BFM's that actively drive interface signals +// Monitor BFM's: BFM's that passively monitor interface signals +// +//---------------------------------------------------------------------- + +//---------------------------------------------------------------------- +// + +module hdl_top; + +import subsys_parameters_pkg::*; +import uvmf_base_pkg_hdl::*; + + // pragma attribute hdl_top partition_module_xrtl +// pragma uvmf custom clock_generator begin + bit clk; + // Instantiate a clk driver + // tbx clkgen + initial begin + clk = 0; + #9ns; + forever begin + clk = ~clk; + #5ns; + end + end +// pragma uvmf custom clock_generator end + +// pragma uvmf custom reset_generator begin + bit rst; + // Instantiate a rst driver + // tbx clkgen + initial begin + rst = 1; + #200ns; + rst = 0; + end +// pragma uvmf custom reset_generator end + + // pragma uvmf custom module_item_additional begin + // pragma uvmf custom module_item_additional end + + // Instantiate the signal bundle, monitor bfm and driver bfm for each interface. + // The signal bundle, _if, contains signals to be connected to the DUT. + // The monitor, monitor_bfm, observes the bus, _if, and captures transactions. + // The driver, driver_bfm, drives transactions onto the bus, _if. + apb_m_if b1_apb_master_bus( + // pragma uvmf custom b1_apb_master_bus_connections begin + .pclk(clk), .presetn(rst) + // pragma uvmf custom b1_apb_master_bus_connections end + ); + axi_m_if b1_axi_master1_bus( + // pragma uvmf custom b1_axi_master1_bus_connections begin + .axi_clk(clk), .rst(rst) + // pragma uvmf custom b1_axi_master1_bus_connections end + ); + axi_m_if b1_axi_master2_bus( + // pragma uvmf custom b1_axi_master2_bus_connections begin + .axi_clk(clk), .rst(rst) + // pragma uvmf custom b1_axi_master2_bus_connections end + ); + spi_s_if b1_spi_slave_bus( + // pragma uvmf custom b1_spi_slave_bus_connections begin + .sck(clk), .rst(rst) + // pragma uvmf custom b1_spi_slave_bus_connections end + ); + spi_m_if b2_spi_master_bus( + // pragma uvmf custom b2_spi_master_bus_connections begin + .sck(clk), .rst(rst) + // pragma uvmf custom b2_spi_master_bus_connections end + ); + wb_s_if b2_wb_slave_bus( + // pragma uvmf custom b2_wb_slave_bus_connections begin + .clock(clk), .reset(rst) + // pragma uvmf custom b2_wb_slave_bus_connections end + ); + apb_m_monitor_bfm b1_apb_master_mon_bfm(b1_apb_master_bus.monitor_port); + axi_m_monitor_bfm b1_axi_master1_mon_bfm(b1_axi_master1_bus.monitor_port); + axi_m_monitor_bfm b1_axi_master2_mon_bfm(b1_axi_master2_bus.monitor_port); + spi_s_monitor_bfm b1_spi_slave_mon_bfm(b1_spi_slave_bus.monitor_port); + spi_m_monitor_bfm b2_spi_master_mon_bfm(b2_spi_master_bus.monitor_port); + wb_s_monitor_bfm b2_wb_slave_mon_bfm(b2_wb_slave_bus.monitor_port); + apb_m_driver_bfm b1_apb_master_drv_bfm(b1_apb_master_bus.initiator_port); + axi_m_driver_bfm b1_axi_master1_drv_bfm(b1_axi_master1_bus.initiator_port); + axi_m_driver_bfm b1_axi_master2_drv_bfm(b1_axi_master2_bus.initiator_port); + wb_s_driver_bfm b2_wb_slave_drv_bfm(b2_wb_slave_bus.responder_port); + + // pragma uvmf custom dut_instantiation begin + // UVMF_CHANGE_ME : Add DUT and connect to signals in _bus interfaces listed above + // Instantiate your DUT here + // These DUT's instantiated to show verilog and vhdl instantiation + verilog_dut dut_verilog( .clk(clk), .rst(rst), .in_signal(vhdl_to_verilog_signal), .out_signal(verilog_to_vhdl_signal)); + vhdl_dut dut_vhdl ( .clk(clk), .rst(rst), .in_signal(verilog_to_vhdl_signal), .out_signal(vhdl_to_verilog_signal)); + // pragma uvmf custom dut_instantiation end + + initial begin // tbx vif_binding_block + import uvm_pkg::uvm_config_db; + // The monitor_bfm and driver_bfm for each interface is placed into the uvm_config_db. + // They are placed into the uvm_config_db using the string names defined in the parameters package. + // The string names are passed to the agent configurations by test_top through the top level configuration. + // They are retrieved by the agents configuration class for use by the agent. + uvm_config_db #( virtual apb_m_monitor_bfm )::set( null , UVMF_VIRTUAL_INTERFACES , b1_apb_master_BFM , b1_apb_master_mon_bfm ); + uvm_config_db #( virtual axi_m_monitor_bfm )::set( null , UVMF_VIRTUAL_INTERFACES , b1_axi_master1_BFM , b1_axi_master1_mon_bfm ); + uvm_config_db #( virtual axi_m_monitor_bfm )::set( null , UVMF_VIRTUAL_INTERFACES , b1_axi_master2_BFM , b1_axi_master2_mon_bfm ); + uvm_config_db #( virtual spi_s_monitor_bfm )::set( null , UVMF_VIRTUAL_INTERFACES , b1_spi_slave_BFM , b1_spi_slave_mon_bfm ); + uvm_config_db #( virtual spi_m_monitor_bfm )::set( null , UVMF_VIRTUAL_INTERFACES , b2_spi_master_BFM , b2_spi_master_mon_bfm ); + uvm_config_db #( virtual wb_s_monitor_bfm )::set( null , UVMF_VIRTUAL_INTERFACES , b2_wb_slave_BFM , b2_wb_slave_mon_bfm ); + uvm_config_db #( virtual apb_m_driver_bfm )::set( null , UVMF_VIRTUAL_INTERFACES , b1_apb_master_BFM , b1_apb_master_drv_bfm ); + uvm_config_db #( virtual axi_m_driver_bfm )::set( null , UVMF_VIRTUAL_INTERFACES , b1_axi_master1_BFM , b1_axi_master1_drv_bfm ); + uvm_config_db #( virtual axi_m_driver_bfm )::set( null , UVMF_VIRTUAL_INTERFACES , b1_axi_master2_BFM , b1_axi_master2_drv_bfm ); + uvm_config_db #( virtual wb_s_driver_bfm )::set( null , UVMF_VIRTUAL_INTERFACES , b2_wb_slave_BFM , b2_wb_slave_drv_bfm ); + end + +endmodule + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/subsys/tb/testbench/hdl_top.vinfo b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/subsys/tb/testbench/hdl_top.vinfo new file mode 100644 index 00000000..a1a47b9c --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/subsys/tb/testbench/hdl_top.vinfo @@ -0,0 +1,9 @@ +@use $UVMF_PROJECT_DIR/rtl/verilog/verilog_dut.vinfo +@use $UVMF_PROJECT_DIR/tb/parameters/subsys_parameters_pkg.vinfo +@use $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg_hdl.vinfo +@use $UVMF_VIP_LIBRARY_HOME/interface_packages/apb_m_pkg/apb_m_bfm.vinfo +@use $UVMF_VIP_LIBRARY_HOME/interface_packages/axi_m_pkg/axi_m_bfm.vinfo +@use $UVMF_VIP_LIBRARY_HOME/interface_packages/spi_s_pkg/spi_s_bfm.vinfo +@use $UVMF_VIP_LIBRARY_HOME/interface_packages/spi_m_pkg/spi_m_bfm.vinfo +@use $UVMF_VIP_LIBRARY_HOME/interface_packages/wb_s_pkg/wb_s_bfm.vinfo +hdl_top.sv diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/subsys/tb/testbench/hvl_top.compile b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/subsys/tb/testbench/hvl_top.compile new file mode 100644 index 00000000..83c8142f --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/subsys/tb/testbench/hvl_top.compile @@ -0,0 +1,7 @@ +incdir: + - ${uvm_path}/src + - . +needs: + - ../tests/subsys_tests_pkg.compile +src: + - hvl_top.sv diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/subsys/tb/testbench/hvl_top.sv b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/subsys/tb/testbench/hvl_top.sv new file mode 100644 index 00000000..ea97abbc --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/subsys/tb/testbench/hvl_top.sv @@ -0,0 +1,33 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +// +//---------------------------------------------------------------------- +// +// DESCRIPTION: This module loads the test package and starts the UVM phases. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// + +module hvl_top; + +import uvm_pkg::*; +import subsys_tests_pkg::*; + + // pragma uvmf custom module_item_additional begin + // pragma uvmf custom module_item_additional end + + initial begin + $timeformat(-9,3,"ns",5); + run_test(); + end + +endmodule + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/subsys/tb/testbench/hvl_top.vinfo b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/subsys/tb/testbench/hvl_top.vinfo new file mode 100644 index 00000000..2c837f2c --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/subsys/tb/testbench/hvl_top.vinfo @@ -0,0 +1,2 @@ +@use $UVMF_PROJECT_DIR/tb/tests/subsys_tests_pkg.vinfo +hvl_top.sv diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/subsys/tb/testbench/top_filelist_hdl.f b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/subsys/tb/testbench/top_filelist_hdl.f new file mode 100644 index 00000000..1e9dab65 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/subsys/tb/testbench/top_filelist_hdl.f @@ -0,0 +1,3 @@ +$UVMF_PROJECT_DIR/tb/testbench/hdl_top.sv +// pragma uvmf custom additional begin +// pragma uvmf custom additional end diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/subsys/tb/testbench/top_filelist_hvl.f b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/subsys/tb/testbench/top_filelist_hvl.f new file mode 100644 index 00000000..42383ab2 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/subsys/tb/testbench/top_filelist_hvl.f @@ -0,0 +1,3 @@ +$UVMF_PROJECT_DIR/tb/testbench/hvl_top.sv +// pragma uvmf custom additional begin +// pragma uvmf custom additional end diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/subsys/tb/tests/src/example_derived_test.svh b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/subsys/tb/tests/src/example_derived_test.svh new file mode 100644 index 00000000..94204d40 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/subsys/tb/tests/src/example_derived_test.svh @@ -0,0 +1,44 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This test extends test_top and makes +// changes to test_top using the UVM factory type_override: +// +// Test scenario: +// This is a template test that can be used to create future tests. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +`ifndef EXAMPLE_DERIVED_TEST +`define EXAMPLE_DERIVED_TEST +class example_derived_test extends test_top; + + `uvm_component_utils( example_derived_test ); + + function new( string name = "", uvm_component parent = null ); + super.new( name, parent ); + endfunction + + virtual function void build_phase(uvm_phase phase); + // The factory override below is an example of how to replace the subsys_bench_sequence_base + // sequence with the example_derived_test_sequence. + subsys_bench_sequence_base::type_id::set_type_override(example_derived_test_sequence::get_type()); + // Execute the build_phase of test_top AFTER all factory overrides have been created. + super.build_phase(phase); + // pragma uvmf custom configuration_settings_post_randomize begin + // UVMF_CHANGE_ME Test specific configuration values can be set here. + // The configuration structure has already been randomized. + // pragma uvmf custom configuration_settings_post_randomize end + endfunction + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end +`endif diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/subsys/tb/tests/src/register_test.svh b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/subsys/tb/tests/src/register_test.svh new file mode 100644 index 00000000..9894343c --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/subsys/tb/tests/src/register_test.svh @@ -0,0 +1,41 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This test extends test_top and makes +// changes to test_top using the UVM factory type_override: +// +// Test scenario: +// This is a template test that can be used to create future tests. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +`ifndef REGISTER_TEST +`define REGISTER_TEST +class register_test extends test_top; + + `uvm_component_utils( register_test ); + + function new( string name = "", uvm_component parent = null ); + super.new( name, parent ); + endfunction + + virtual function void build_phase(uvm_phase phase); + // The factory override below replaces the subsys_bench_sequence_base + // sequence with the register_test_sequence. + subsys_bench_sequence_base::type_id::set_type_override(register_test_sequence::get_type()); + // Execute the build_phase of test_top AFTER all factory overrides have been created. + super.build_phase(phase); + endfunction + + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end +`endif diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/subsys/tb/tests/src/test_top.svh b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/subsys/tb/tests/src/test_top.svh new file mode 100644 index 00000000..c09ca366 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/subsys/tb/tests/src/test_top.svh @@ -0,0 +1,87 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// Description: This top level UVM test is the base class for all +// future tests created for this project. +// +// This test class contains: +// Configuration: The top level configuration for the project. +// Environment: The top level environment for the project. +// Top_level_sequence: The top level sequence for the project. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// + +typedef subsys_env_configuration subsys_env_configuration_t; +typedef subsys_environment subsys_environment_t; +`ifndef TEST_TOP +`define TEST_TOP +class test_top extends uvmf_test_base #(.CONFIG_T(subsys_env_configuration_t), + .ENV_T(subsys_environment_t), + .TOP_LEVEL_SEQ_T(subsys_bench_sequence_base)); + + `uvm_component_utils( test_top ); + + + + string interface_names[] = { + b1_apb_master_BFM /* b1_apb_master [0] */ , + b1_axi_master1_BFM /* b1_axi_master1 [1] */ , + b1_axi_master2_BFM /* b1_axi_master2 [2] */ , + b1_spi_slave_BFM /* b1_spi_slave [3] */ , + b2_spi_master_BFM /* b2_spi_master [4] */ , + b2_wb_slave_BFM /* b2_wb_slave [5] */ +}; + +uvmf_active_passive_t interface_activities[] = { + ACTIVE /* b1_apb_master [0] */ , + ACTIVE /* b1_axi_master1 [1] */ , + ACTIVE /* b1_axi_master2 [2] */ , + PASSIVE /* b1_spi_slave [3] */ , + PASSIVE /* b2_spi_master [4] */ , + ACTIVE /* b2_wb_slave [5] */ }; + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + // **************************************************************************** + // FUNCTION: new() + // This is the standard systemVerilog constructor. All components are + // constructed in the build_phase to allow factory overriding. + // + function new( string name = "", uvm_component parent = null ); + super.new( name ,parent ); + endfunction + + + + // **************************************************************************** + // FUNCTION: build_phase() + // The construction of the configuration and environment classes is done in + // the build_phase of uvmf_test_base. Once the configuraton and environment + // classes are built then the initialize call is made to perform the + // following: + // Monitor and driver BFM virtual interface handle passing into agents + // Set the active/passive state for each agent + // Once this build_phase completes, the build_phase of the environment is + // executed which builds the agents. + // + virtual function void build_phase(uvm_phase phase); +// pragma uvmf custom build_phase_pre_super begin +// pragma uvmf custom build_phase_pre_super end + super.build_phase(phase); + // pragma uvmf custom configuration_settings_post_randomize begin + // pragma uvmf custom configuration_settings_post_randomize end + configuration.initialize(NA, "uvm_test_top.environment", interface_names, null, interface_activities); + endfunction + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end +`endif diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/subsys/tb/tests/subsys_tests_pkg.compile b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/subsys/tb/tests/subsys_tests_pkg.compile new file mode 100644 index 00000000..106be50e --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/subsys/tb/tests/subsys_tests_pkg.compile @@ -0,0 +1,12 @@ +needs: + - $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg.compile + - ../../../../verification_ip/interface_packages/apb_m_pkg/apb_m.compile + - ../../../../verification_ip/interface_packages/axi_m_pkg/axi_m.compile + - ../../../../verification_ip/interface_packages/spi_s_pkg/spi_s.compile + - ../../../../verification_ip/interface_packages/spi_m_pkg/spi_m.compile + - ../../../../verification_ip/interface_packages/wb_s_pkg/wb_s.compile + - ../../../../verification_ip/environment_packages/subsys_env_pkg/subsys_env_pkg.compile + - ../parameters/subsys_parameters_pkg.compile + - ../sequences/subsys_sequences_pkg.compile +src: + - subsys_tests_pkg.sv diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/subsys/tb/tests/subsys_tests_pkg.sv b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/subsys/tb/tests/subsys_tests_pkg.sv new file mode 100644 index 00000000..1947ca1e --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/subsys/tb/tests/subsys_tests_pkg.sv @@ -0,0 +1,61 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This package contains all tests currently written for +// the simulation project. Once compiled, any test can be selected +// from the vsim command line using +UVM_TESTNAME=yourTestNameHere +// +// CONTAINS: +// - +// - +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +`ifndef SUBSYS_TESTS_PKG +`define SUBSYS_TESTS_PKG +package subsys_tests_pkg; + + import uvm_pkg::*; + import uvmf_base_pkg::*; + import subsys_parameters_pkg::*; + import subsys_env_pkg::*; + import subsys_sequences_pkg::*; + import apb_m_pkg::*; + import apb_m_pkg_hdl::*; + import axi_m_pkg::*; + import axi_m_pkg_hdl::*; + import spi_s_pkg::*; + import spi_s_pkg_hdl::*; + import spi_m_pkg::*; + import spi_m_pkg_hdl::*; + import wb_s_pkg::*; + import wb_s_pkg_hdl::*; + + + `include "uvm_macros.svh" + + // pragma uvmf custom package_imports_additional begin + // pragma uvmf custom package_imports_additional end + + `include "src/test_top.svh" + `include "src/register_test.svh" + `include "src/example_derived_test.svh" + + // pragma uvmf custom package_item_additional begin + // UVMF_CHANGE_ME : When adding new tests to the src directory + // be sure to add the test file here so that it will be + // compiled as part of the test package. Be sure to place + // the new test after any base tests of the new test. + // pragma uvmf custom package_item_additional end + +endpackage + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/subsys/tb/tests/subsys_tests_pkg.vinfo b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/subsys/tb/tests/subsys_tests_pkg.vinfo new file mode 100644 index 00000000..b50c9a39 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/subsys/tb/tests/subsys_tests_pkg.vinfo @@ -0,0 +1,11 @@ +@use $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg.vinfo +@use $UVMF_VIP_LIBRARY_HOME/interface_packages/apb_m_pkg/apb_m_pkg.vinfo +@use $UVMF_VIP_LIBRARY_HOME/interface_packages/axi_m_pkg/axi_m_pkg.vinfo +@use $UVMF_VIP_LIBRARY_HOME/interface_packages/spi_s_pkg/spi_s_pkg.vinfo +@use $UVMF_VIP_LIBRARY_HOME/interface_packages/spi_m_pkg/spi_m_pkg.vinfo +@use $UVMF_VIP_LIBRARY_HOME/interface_packages/wb_s_pkg/wb_s_pkg.vinfo +@use $UVMF_VIP_LIBRARY_HOME/environment_packages/subsys_env_pkg/subsys_env_pkg.vinfo +@use $UVMF_PROJECT_DIR/tb/parameters/subsys_parameters_pkg.vinfo +@use $UVMF_PROJECT_DIR/tb/sequences/subsys_sequences_pkg.vinfo ++incdir+@vinfodir +subsys_tests_pkg.sv diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/subsys/yaml/subsys_bench.yaml b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/subsys/yaml/subsys_bench.yaml new file mode 100644 index 00000000..bea949dd --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/subsys/yaml/subsys_bench.yaml @@ -0,0 +1,25 @@ +uvmf: + benches: + subsys: + active_passive: + - bfm_name: b1_apb_master + value: ACTIVE + - bfm_name: b1_axi_master1 + value: ACTIVE + - bfm_name: b1_axi_master2 + value: ACTIVE + - bfm_name: b1_spi_slave + value: PASSIVE + - bfm_name: b2_spi_master + value: PASSIVE + - bfm_name: b2_wb_slave + value: ACTIVE + active_passive_default: ACTIVE + clock_half_period: 5ns + clock_phase_offset: 9ns + existing_library_component: 'True' + interface_params: [] + reset_assertion_level: 'True' + reset_duration: 200ns + top_env: subsys + use_dpi_link: 'False' diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/system/.project b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/system/.project new file mode 100644 index 00000000..d9a56710 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/system/.project @@ -0,0 +1,37 @@ + + + system + + + + + + org.python.pydev.PyDevBuilder + + + + + net.sf.sveditor.core.SVProjectBuilder + + + + + + net.sf.sveditor.core.SVNature + org.python.pydev.pythonNature + + + + verification_ip + 2 + UVMF_VIP_LIBRARY_HOME + + + + + UVMF_VIP_LIBRARY_HOME + $%7BPARENT-2-PROJECT_LOC%7D/verification_ip + + + + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/system/.svproject b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/system/.svproject new file mode 100644 index 00000000..2604503d --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/system/.svproject @@ -0,0 +1,16 @@ + + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/system/docs/interfaces.csv b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/system/docs/interfaces.csv new file mode 100644 index 00000000..6676d63d --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/system/docs/interfaces.csv @@ -0,0 +1,20 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// + +, +Interface Description, Interface Type, Interface Transaction, Interface Name, +s1_b1_apb_master, apb_m_driver_bfm apb_m_monitor_bfm, apb_m_transaction, apb_m_pkg_s1_b1_apb_master_BFM, +s1_b1_axi_master1, axi_m_driver_bfm axi_m_monitor_bfm, axi_m_transaction, axi_m_pkg_s1_b1_axi_master1_BFM, +s1_b1_axi_master2, axi_m_driver_bfm axi_m_monitor_bfm, axi_m_transaction, axi_m_pkg_s1_b1_axi_master2_BFM, +s1_b1_spi_slave, spi_s_driver_bfm spi_s_monitor_bfm, spi_s_transaction, spi_s_pkg_s1_b1_spi_slave_BFM, +s1_b2_spi_master, spi_m_driver_bfm spi_m_monitor_bfm, spi_m_transaction, spi_m_pkg_s1_b2_spi_master_BFM, +s1_b2_wb_slave, wb_s_driver_bfm wb_s_monitor_bfm, wb_s_transaction, wb_s_pkg_s1_b2_wb_slave_BFM, +b3_wb_master, wb_m_driver_bfm wb_m_monitor_bfm, wb_m_transaction, wb_m_pkg_b3_wb_master_BFM, +b3_axi_slave, axi_s_driver_bfm axi_s_monitor_bfm, axi_s_transaction, axi_s_pkg_b3_axi_slave_BFM, + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/system/rtl/dut.compile b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/system/rtl/dut.compile new file mode 100644 index 00000000..9b0008fc --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/system/rtl/dut.compile @@ -0,0 +1,6 @@ + +# pragma uvmf custom dut_compile_info begin +src: + - ./vhdl/vhdl_dut.vhd + - ./verilog/verilog_dut.v +# pragma uvmf custom dut_compile_info end diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/system/rtl/verilog/verilog_dut.v b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/system/rtl/verilog/verilog_dut.v new file mode 100644 index 00000000..96198441 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/system/rtl/verilog/verilog_dut.v @@ -0,0 +1,21 @@ +module verilog_dut(clk, rst, in_signal, out_signal); + +input clk; +input rst; +input in_signal; +output out_signal; + +reg out_signal_o; + +always @(posedge clk) begin + if (rst) begin + out_signal_o <= 0; + end + else begin + out_signal_o <= ~in_signal; + end + end + +assign out_signal = out_signal_o; + +endmodule diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/system/rtl/verilog/verilog_dut.vinfo b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/system/rtl/verilog/verilog_dut.vinfo new file mode 100644 index 00000000..87e95f36 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/system/rtl/verilog/verilog_dut.vinfo @@ -0,0 +1 @@ +verilog_dut.v diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/system/rtl/vhdl/vhdl_dut.vhd b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/system/rtl/vhdl/vhdl_dut.vhd new file mode 100644 index 00000000..904aa37d --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/system/rtl/vhdl/vhdl_dut.vhd @@ -0,0 +1,21 @@ +library ieee; +use ieee.std_logic_1164.all ; + +entity vhdl_dut is + port ( clk : in std_logic ; + rst : in std_logic ; + in_signal : in std_logic ; + out_signal :out std_logic + ); +end vhdl_dut; + +architecture rtl of vhdl_dut is + begin + P1: process + variable out_signal_o : std_logic; + begin + wait until clk'event and clk = '1'; + out_signal_o := in_signal; + out_signal <= out_signal_o; + end process; + end rtl; diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/system/sim/Makefile b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/system/sim/Makefile new file mode 100644 index 00000000..5700c289 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/system/sim/Makefile @@ -0,0 +1,204 @@ + +# +#---------------------------------------------------------------------- +# +# DESCRIPTION: This makefile includes the shared makefile and contains +# bench level make targets. +# +#---------------------------------------------------------------------- + + +# pragma uvmf custom additional begin +# pragma uvmf custom additional end + +# ********************************************************************************************* +# UVMF library directory: +# This variable points to the UVMF release where uvmf_base_pkg directory resides. +# This variable points to release code that is not user modified. +# This variable allows for UVMF release directories to reside independent of project related verification IP and project bench directories. +# This code below looks "upward" for directory starting with UVMF_* and returns first match for use with the release examples. +UVMF_HOME ?= ___PLEASE_SET_AN_ENVIRONMENT_VARIABLE_NAMED_UVMF_HOME_TO_POINT_TO_THE_UVMF_INSTALLATION___ + +# pragma uvmf custom exports begin +# +# Project(s) specific verification IP library: +# Directory where reusable verification packages for interfaces, environments, utilities, etc. reside. +# This variable allows for your verification IP to reside independent of project bench and UVMF release directories. +# For examples deployed with UVMF this will be $(UVMF_HOME)//verification_ip +export UVMF_VIP_LIBRARY_HOME ?= $(PWD)/../../../verification_ip +# +# Project specific bench: +# Directory where bench specific code is located. +# This variable allows for project_benches to reside independent of verification IP and UVMF release directories. +# For examples deployed with UVMF this will be $(UVMF_HOME)//project_benches/ +export UVMF_PROJECT_DIR ?= $(PWD)/.. +# +# +# pragma uvmf custom exports end +# ********************************************************************************************* + +## Check PATH for required vinfo scripts +PVAL := $(shell command -v make_filelist.py 2> /dev/null) +ifndef PVAL + MFLIST = $(UVMF_HOME)/scripts/make_filelist.py +else + MFLIST = make_filelist.py +endif + + +# Set test case specific Variables +TEST_NAME ?= test_top + +TEST_SEED ?= random +UVM_CLI_ARGS = + +# Usage of Veloce, etc. to be input by the user (subject to defaults) +USE_VELOCE ?= 0 + +# Usage of vinfo flow for generating file list +USE_VINFO ?= 0 + +# Usage of Veloce and Questa profilers +USE_VELOCE_PROFILER ?= 0 +USE_QUESTA_PROFILER ?= 0 + + +# Set project Variables +TEST_PLAN_NAME = system_TestPlan +REPORTING_DO_FILE = system_reports_script + + +# Include makefile that includes targets for UVM_VIP_Library packages +include $(UVMF_HOME)/scripts/Makefile + + + + +# Include all requisite interface package targets for this bench +include $(UVMF_VIP_LIBRARY_HOME)/interface_packages/apb_m_pkg/Makefile +include $(UVMF_VIP_LIBRARY_HOME)/interface_packages/axi_m_pkg/Makefile +include $(UVMF_VIP_LIBRARY_HOME)/interface_packages/spi_s_pkg/Makefile +include $(UVMF_VIP_LIBRARY_HOME)/interface_packages/spi_m_pkg/Makefile +include $(UVMF_VIP_LIBRARY_HOME)/interface_packages/wb_s_pkg/Makefile +include $(UVMF_VIP_LIBRARY_HOME)/interface_packages/wb_m_pkg/Makefile +include $(UVMF_VIP_LIBRARY_HOME)/interface_packages/axi_s_pkg/Makefile + +# Include all requisite environment package targets for this bench +include $(UVMF_VIP_LIBRARY_HOME)/environment_packages/system_env_pkg/Makefile + + + +# Add to default compile/load/run arguments +VCOM_ARGS += + +# Note: vsim-3009 error can be eliminated by adding -timescale 1ps/1ps to VLOG_ARGS + +VLOG_ARGS += $(UVM_DISABLE_FILE_LINE_CMD) + +VELANALYZE_ARGS += +VELANALYZE_HVL_ARGS += + +BATCH_VOPT_ARGS += +DEBUG_VOPT_ARGS += +EXTRA_VOPT_TOPS += +COMMON_VSIM_ARGS += +COMMON_VSIM_ARGS += + + +BATCH_VSIM_ARGS += #-uvmcontrol=none +DEBUG_VSIM_ARGS += +EXTRA_VSIM_TOPS += + +# pragma uvmf custom additional_args begin +# pragma uvmf custom additional_args end + + +# Project bench package source +system_PARAMETERS_PKG ?=\ +$(UVMF_PROJECT_DIR)/tb/parameters/system_parameters_pkg.sv + + +system_SEQUENCES_PKG ?=\ +$(UVMF_PROJECT_DIR)/tb/sequences/system_sequences_pkg.sv + + +system_TEST_PKG ?=\ +$(UVMF_PROJECT_DIR)/tb/tests/system_tests_pkg.sv + +# pragma uvmf custom dut_files begin +# UVMF_CHANGE_ME : Reference Verilog DUT source. +system_VERILOG_DUT ?=\ +$(UVMF_PROJECT_DIR)/rtl/verilog/verilog_dut.v + +# UVMF_CHANGE_ME : Reference VHDL DUT source. +system_VHDL_DUT ?=\ +$(UVMF_PROJECT_DIR)/rtl/vhdl/vhdl_dut.vhd +# pragma uvmf custom dut_files end + + +# Project bench package targets +COMP_system_PARAMETERS_PKG_TGT_0 = q_comp_system_parameters_pkg +COMP_system_PARAMETERS_PKG_TGT_1 = v_comp_system_parameters_pkg +COMP_system_PARAMETERS_PKG_TGT = $(COMP_system_PARAMETERS_PKG_TGT_$(USE_VELOCE)) + +comp_system_parameters_pkg: $(COMP_system_PARAMETERS_PKG_TGT) + +q_comp_system_parameters_pkg: + $(HVL_COMP_CMD) +incdir+$(UVMF_PROJECT_DIR)/tb/parameters $(system_PARAMETERS_PKG) + +v_comp_system_parameters_pkg: q_comp_system_parameters_pkg + $(HDL_COMP_CMD) +incdir+$(UVMF_PROJECT_DIR)/tb/parameters $(system_PARAMETERS_PKG) + + +comp_system_sequence_pkg: + $(HVL_COMP_CMD) +incdir+$(UVMF_PROJECT_DIR)/tb/sequences $(system_SEQUENCES_PKG) + +comp_system_tests_pkg: + $(HVL_COMP_CMD) +incdir+$(UVMF_PROJECT_DIR)/tb/tests $(system_TEST_PKG) + +# pragma uvmf custom dut_compile_make_target begin +# UVMF_CHANGE_ME : Add make target to compile your verilog dut here +comp_system_verilog_dut: + echo "Compile your verilog DUT here" + $(HDL_COMP_CMD) $(system_VERILOG_DUT) + +# UVMF_CHANGE_ME : Add make target to compile your vhdl dut here +comp_system_vhdl_dut: + echo "Compile your vhdl DUT here" + $(HDL_COMP_CMD_VHDL) $(system_VHDL_DUT) + +# UVMF_CHANGE_ME : Add make target to compile your dut here +comp_system_dut: comp_system_vhdl_dut comp_system_verilog_dut +# pragma uvmf custom dut_compile_make_target end + + +BUILD_TGT_0 = make_build +BUILD_TGT_1 = vinfo_build +BUILD_TGT = $(BUILD_TGT_$(USE_VINFO)) + + +comp_hvl : comp_hvl_core + + +comp_hvl_core : \ + comp_apb_m_pkg comp_axi_m_pkg comp_spi_s_pkg comp_spi_m_pkg comp_wb_s_pkg comp_wb_m_pkg comp_axi_s_pkg \ + comp_system_env_pkg \ + comp_system_parameters_pkg comp_system_sequence_pkg comp_system_tests_pkg + +comp_uvmf_core : comp_uvm_pkg comp_uvmf_base_pkg + +make_build: comp_system_dut comp_uvmf_core comp_hvl comp_test_bench + +hvl_build: q_comp_apb_m_pkg q_comp_axi_m_pkg q_comp_spi_s_pkg q_comp_spi_m_pkg q_comp_wb_s_pkg q_comp_wb_m_pkg q_comp_axi_s_pkg comp_system_env_pkg comp_system_sequence_pkg comp_system_tests_pkg hvl_comp_testbench link optimize + + +vinfo_build: comp_system_vhdl_dut build_hdl_vinfo build_hvl_vinfo $(VINFO_TGT) + + $(HDL_COMP_CMD) -F hdl.vf + $(VEL_COMP) + +build: $(BUILD_TGT) + +# pragma uvmf custom additional_targets begin +# pragma uvmf custom additional_targets end + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/system/sim/bcr_testlist b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/system/sim/bcr_testlist new file mode 100644 index 00000000..2bb25c0e --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/system/sim/bcr_testlist @@ -0,0 +1,19 @@ + + + +# Test list for use by RMDB file +# File syntax is +# TB_INFO { } { } +# TB ## All subsequent tests will run on this bench until a different "TB" line is seen +# TEST <1st_seed> ... +# If not enough seeds are provided then random seeds are used to pad +# If no repeat count is given, default is 1 +# pragma uvmf custom tb_info begin +TB_INFO system { } { } +# pragma uvmf custom tb_info end +TB system +# pragma uvmf custom regression_suite begin +TEST test_top 3 +# pragma uvmf custom regression_suite end + + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/system/sim/bcr_testlist.yaml b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/system/sim/bcr_testlist.yaml new file mode 100644 index 00000000..4f661bb2 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/system/sim/bcr_testlist.yaml @@ -0,0 +1,44 @@ + + + +# YAML test list for use by RMDB file +# File syntax is +# uvmf_testlist: +# testbenches: +# - name: +# extra_build_options: +# extra_run_options: +# - name: +# ... +# - name: +# tests: +# - name: +# uvm_testname: (defaults to test_name) +# testbench: (defaults to last tb name seen) +# repeat: (defaults to 1) +# seeds: [,,...,] (defaults to all random) +# extra_test_options: +# - name: +# ... +# - name: +# include: +# - (relative path reference is to the including YAML file) +# - +# ... +# - + +uvmf_testlist: + testbenches: +# pragma uvmf custom tb_info begin + - name: system + extra_build_options: "" + extra_run_options: "" +# pragma uvmf custom tb_info end + tests: + - testbench: system +# pragma uvmf custom regression_suite begin + - name: test_top + repeat: 3 +# pragma uvmf custom regression_suite end + + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/system/sim/compile.do b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/system/sim/compile.do new file mode 100644 index 00000000..72f475cb --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/system/sim/compile.do @@ -0,0 +1,76 @@ + + +################################################################## +## ENVIRONMENT VARIABLES +################################################################## +quietly set ::env(UVMF_VIP_LIBRARY_HOME) ../../../verification_ip +quietly set ::env(UVMF_PROJECT_DIR) .. + +## Using VRM means that the build is occuring several more directories deeper underneath +## the sim directory, need to prepend some more '..' +if {[info exists ::env(VRM_BUILD)]} { + quietly set ::env(UVMF_VIP_LIBRARY_HOME) "../../../../../$::env(UVMF_VIP_LIBRARY_HOME)" + quietly set ::env(UVMF_PROJECT_DIR) "../../../../../$::env(UVMF_PROJECT_DIR)" +} +quietly set ::env(UVMF_VIP_LIBRARY_HOME) [file normalize $::env(UVMF_VIP_LIBRARY_HOME)] +quietly set ::env(UVMF_PROJECT_DIR) [file normalize $::env(UVMF_PROJECT_DIR)] +quietly echo "UVMF_VIP_LIBRARY_HOME = $::env(UVMF_VIP_LIBRARY_HOME)" +quietly echo "UVMF_PROJECT_DIR = $::env(UVMF_PROJECT_DIR)" + + +################################################################### +## HOUSEKEEPING : DELETE FILES THAT WILL BE REGENERATED +################################################################### +file delete -force *~ *.ucdb vsim.dbg *.vstf *.log work *.mem *.transcript.txt certe_dump.xml *.wlf covhtmlreport VRMDATA +file delete -force design.bin qwave.db dpiheader.h visualizer*.ses +file delete -force veloce.med veloce.wave veloce.map tbxbindings.h edsenv velrunopts.ini +file delete -force sv_connect.* + +################################################################### +## COMPILE DUT SOURCE CODE +################################################################### +vlib work +# pragma uvmf custom dut_compile_dofile_target begin +# UVMF_CHANGE_ME : Add commands to compile your dut here, replacing the default examples +vlog -sv -timescale 1ps/1ps -suppress 2223,2286 $env(UVMF_PROJECT_DIR)/rtl/verilog/verilog_dut.v +vcom $env(UVMF_PROJECT_DIR)/rtl/vhdl/vhdl_dut.vhd +# pragma uvmf custom dut_compile_dofile_target end + +################################################################### +## COMPILE UVMF BASE/COMMON SOURCE CODE +################################################################### +vlog -sv -timescale 1ps/1ps -suppress 2223 -suppress 2286 +incdir+$env(UVMF_HOME)/uvmf_base_pkg -F $env(UVMF_HOME)/uvmf_base_pkg/uvmf_base_pkg_filelist_hdl.f +vlog -sv -timescale 1ps/1ps -suppress 2223 -suppress 2286 +incdir+$env(UVMF_HOME)/uvmf_base_pkg -F $env(UVMF_HOME)/uvmf_base_pkg/uvmf_base_pkg_filelist_hvl.f + + +################################################################### +## UVMF INTERFACE COMPILATION +################################################################### +do $env(UVMF_VIP_LIBRARY_HOME)/interface_packages/apb_m_pkg/compile.do +do $env(UVMF_VIP_LIBRARY_HOME)/interface_packages/axi_m_pkg/compile.do +do $env(UVMF_VIP_LIBRARY_HOME)/interface_packages/spi_s_pkg/compile.do +do $env(UVMF_VIP_LIBRARY_HOME)/interface_packages/spi_m_pkg/compile.do +do $env(UVMF_VIP_LIBRARY_HOME)/interface_packages/wb_s_pkg/compile.do +do $env(UVMF_VIP_LIBRARY_HOME)/interface_packages/wb_m_pkg/compile.do +do $env(UVMF_VIP_LIBRARY_HOME)/interface_packages/axi_s_pkg/compile.do + +################################################################### +## UVMF ENVIRONMENT COMPILATION +################################################################### +do $env(UVMF_VIP_LIBRARY_HOME)/environment_packages/system_env_pkg/compile.do + +################################################################### +## UVMF BENCHES COMPILATION +################################################################### +vlog -sv -timescale 1ps/1ps -suppress 2223 -suppress 2286 +incdir+$env(UVMF_PROJECT_DIR)/tb/parameters $env(UVMF_PROJECT_DIR)/tb/parameters/system_parameters_pkg.sv +vlog -sv -timescale 1ps/1ps -suppress 2223 -suppress 2286 +incdir+$env(UVMF_PROJECT_DIR)/tb/sequences $env(UVMF_PROJECT_DIR)/tb/sequences/system_sequences_pkg.sv +vlog -sv -timescale 1ps/1ps -suppress 2223 -suppress 2286 +incdir+$env(UVMF_PROJECT_DIR)/tb/tests $env(UVMF_PROJECT_DIR)/tb/tests/system_tests_pkg.sv + +vlog -sv -timescale 1ps/1ps -suppress 2223 -suppress 2286 +incdir+$env(UVMF_PROJECT_DIR)/tb/testbench -F $env(UVMF_PROJECT_DIR)/tb/testbench/top_filelist_hdl.f +vlog -sv -timescale 1ps/1ps -suppress 2223 -suppress 2286 +incdir+$env(UVMF_PROJECT_DIR)/tb/testbench -F $env(UVMF_PROJECT_DIR)/tb/testbench/top_filelist_hvl.f + +################################################################### +## OPTIMIZATION +################################################################### +vopt hvl_top hdl_top -o optimized_batch_top_tb +vopt +acc hvl_top hdl_top -o optimized_debug_top_tb diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/system/sim/hdl.compile b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/system/sim/hdl.compile new file mode 100644 index 00000000..8e7bd41a --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/system/sim/hdl.compile @@ -0,0 +1,5 @@ +needs: +# pragma uvmf custom dut_compile_info begin + - ../rtl/dut.compile +# pragma uvmf custom dut_compile_info end + - ../tb/testbench/hdl_top.compile diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/system/sim/hdl.vinfo b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/system/sim/hdl.vinfo new file mode 100644 index 00000000..da27ec77 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/system/sim/hdl.vinfo @@ -0,0 +1 @@ +@use $UVMF_PROJECT_DIR/tb/testbench/hdl_top.vinfo diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/system/sim/hvl.compile b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/system/sim/hvl.compile new file mode 100644 index 00000000..ce952549 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/system/sim/hvl.compile @@ -0,0 +1,2 @@ +needs: + - ../tb/testbench/hvl_top.compile diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/system/sim/hvl.vinfo b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/system/sim/hvl.vinfo new file mode 100644 index 00000000..d22eff33 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/system/sim/hvl.vinfo @@ -0,0 +1 @@ +@use $UVMF_PROJECT_DIR/tb/testbench/hvl_top.vinfo diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/system/sim/run.do b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/system/sim/run.do new file mode 100644 index 00000000..101ddc48 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/system/sim/run.do @@ -0,0 +1,21 @@ + + +quietly set svLibs "" +quietly set extra_vsim_args "" + +################################################################### +## Check for additional vsim arguments passed using env var $UVMF_EXTRA_VSIM_ARGS +################################################################### +if {[info exists ::env(UVMF_EXTRA_VSIM_ARGS)]} { + echo "Adding more args to vsim command" + quietly set extra_vsim_args $::env(UVMF_EXTRA_VSIM_ARGS) +} + +################################################################## +## Launch Questa : generate vsim command line and execute +################################################################## +# pragma uvmf custom dut_run_dofile_target begin +# UVMF_CHANGE_ME : Change the UVM_TESTNAME plusarg to run a different test +quietly set cmd [format "vsim -i -sv_seed random +UVM_TESTNAME=test_top +UVM_VERBOSITY=UVM_HIGH -permit_unmatched_virtual_intf +notimingchecks -suppress 8887 %s %s -uvmcontrol=all -msgmode both -classdebug -assertdebug +uvm_set_config_int=*,enable_transaction_viewing,1 -do { set NoQuitOnFinish 1; onbreak {resume}; run 0; do wave.do; set PrefSource(OpenOnBreak) 0; radix hex showbase; } optimized_debug_top_tb" $svLibs $extra_vsim_args] +# pragma uvmf custom dut_run_dofile_target end +eval $cmd diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/system/sim/tbx.config b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/system/sim/tbx.config new file mode 100644 index 00000000..eec58168 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/system/sim/tbx.config @@ -0,0 +1,10 @@ + + + + + +comp -questa +velsyn -D1S +rtlc -allow_4ST + + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/system/sim/testlist b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/system/sim/testlist new file mode 100644 index 00000000..a8df97de --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/system/sim/testlist @@ -0,0 +1,20 @@ + + + + +# Test list for use by RMDB file +# File syntax is +# TB_INFO { } { } +# TB ## All subsequent tests will run on this bench until a different "TB" line is seen +# TEST <1st_seed> ... +# If not enough seeds are provided then random seeds are used to pad +# If no repeat count is given, default is 1 +# pragma uvmf custom tb_info begin +TB_INFO system { UVMF_VIP_LIBRARY_HOME=../../../../../../../../verification_ip UVMF_PROJECT_DIR=../../../../../../../system } { } +# pragma uvmf custom tb_info end +TB system +# pragma uvmf custom regression_suite begin +TEST test_top 3 +# pragma uvmf custom regression_suite end + + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/system/sim/testlist.yaml b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/system/sim/testlist.yaml new file mode 100644 index 00000000..4e7ac236 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/system/sim/testlist.yaml @@ -0,0 +1,44 @@ + + + +# YAML test list for use by RMDB file +# File syntax is +# uvmf_testlist: +# testbenches: +# - name: +# extra_build_options: +# extra_run_options: +# - name: +# ... +# - name: +# tests: +# - name: +# uvm_testname: (defaults to test_name) +# testbench: (defaults to last tb name seen) +# repeat: (defaults to 1) +# seeds: [,,...,] (defaults to all random) +# extra_test_options: +# - name: +# ... +# - name: +# include: +# - (relative path reference is to the including YAML file) +# - +# ... +# - + +uvmf_testlist: + testbenches: +# pragma uvmf custom tb_info begin + - name: system + extra_build_options: "UVMF_VIP_LIBRARY_HOME=../../../../../../../../verification_ip UVMF_PROJECT_DIR=../../../../../../../system" + extra_run_options: "" +# pragma uvmf custom tb_info end + tests: + - testbench: system +# pragma uvmf custom regression_suite begin + - name: test_top + repeat: 3 +# pragma uvmf custom regression_suite end + + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/system/sim/top.compile b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/system/sim/top.compile new file mode 100644 index 00000000..efd51c07 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/system/sim/top.compile @@ -0,0 +1,3 @@ +needs: + - hvl.compile + - hdl.compile diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/system/sim/veloce.config b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/system/sim/veloce.config new file mode 100644 index 00000000..d0975155 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/system/sim/veloce.config @@ -0,0 +1,26 @@ + + + + + +# pragma uvmf custom additional begin +comp -num_boards 1 +comp -hvl questa +# Please choose the correct emulator type code for +# comp -platform command or else velcomp will fail +# Available types are: +# - Veloce2 Quattro: D2 +# - Veloce2 Maximus: D2M +# - Veloce Strato TiL, Ti, and Mi: Strato +# - Veloce Strato M and Strato T: StratoM +# - comp -platform +comp -platform Strato + +rtlc -enable_tbx_pragma_checks +rtlc -allow_4ST +rtlc -allow_MDR +rtlc -compile_display +rtlc -xwave_siglist xwaves.sigs +# pragma uvmf custom additional end + + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/system/sim/viswave.do b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/system/sim/viswave.do new file mode 100644 index 00000000..76a96341 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/system/sim/viswave.do @@ -0,0 +1,58 @@ + + +onerror resume +wave tags F0 +wave update off + +wave spacer -backgroundcolor Salmon { s1_b1_apb_master } +wave add uvm_test_top.environment.s1.b1.apb_master.apb_master_monitor.txn_stream -radix string -tag F0 +wave group s1_b1_apb_master_bus +wave add -group s1_b1_apb_master_bus hdl_top.s1_b1_apb_master_bus.* -radix hexadecimal -tag F0 +wave group s1_b1_apb_master_bus -collapse +wave insertion [expr [wave index insertpoint] +1] +wave spacer -backgroundcolor Salmon { s1_b1_axi_master1 } +wave add uvm_test_top.environment.s1.b1.axi_master1.axi_master1_monitor.txn_stream -radix string -tag F0 +wave group s1_b1_axi_master1_bus +wave add -group s1_b1_axi_master1_bus hdl_top.s1_b1_axi_master1_bus.* -radix hexadecimal -tag F0 +wave group s1_b1_axi_master1_bus -collapse +wave insertion [expr [wave index insertpoint] +1] +wave spacer -backgroundcolor Salmon { s1_b1_axi_master2 } +wave add uvm_test_top.environment.s1.b1.axi_master2.axi_master2_monitor.txn_stream -radix string -tag F0 +wave group s1_b1_axi_master2_bus +wave add -group s1_b1_axi_master2_bus hdl_top.s1_b1_axi_master2_bus.* -radix hexadecimal -tag F0 +wave group s1_b1_axi_master2_bus -collapse +wave insertion [expr [wave index insertpoint] +1] +wave spacer -backgroundcolor Salmon { s1_b1_spi_slave } +wave add uvm_test_top.environment.s1.b1.spi_slave.spi_slave_monitor.txn_stream -radix string -tag F0 +wave group s1_b1_spi_slave_bus +wave add -group s1_b1_spi_slave_bus hdl_top.s1_b1_spi_slave_bus.* -radix hexadecimal -tag F0 +wave group s1_b1_spi_slave_bus -collapse +wave insertion [expr [wave index insertpoint] +1] +wave spacer -backgroundcolor Salmon { s1_b2_spi_master } +wave add uvm_test_top.environment.s1.b2.spi_master.spi_master_monitor.txn_stream -radix string -tag F0 +wave group s1_b2_spi_master_bus +wave add -group s1_b2_spi_master_bus hdl_top.s1_b2_spi_master_bus.* -radix hexadecimal -tag F0 +wave group s1_b2_spi_master_bus -collapse +wave insertion [expr [wave index insertpoint] +1] +wave spacer -backgroundcolor Salmon { s1_b2_wb_slave } +wave add uvm_test_top.environment.s1.b2.wb_slave.wb_slave_monitor.txn_stream -radix string -tag F0 +wave group s1_b2_wb_slave_bus +wave add -group s1_b2_wb_slave_bus hdl_top.s1_b2_wb_slave_bus.* -radix hexadecimal -tag F0 +wave group s1_b2_wb_slave_bus -collapse +wave insertion [expr [wave index insertpoint] +1] +wave spacer -backgroundcolor Salmon { b3_wb_master } +wave add uvm_test_top.environment.b3.wb_master.wb_master_monitor.txn_stream -radix string -tag F0 +wave group b3_wb_master_bus +wave add -group b3_wb_master_bus hdl_top.b3_wb_master_bus.* -radix hexadecimal -tag F0 +wave group b3_wb_master_bus -collapse +wave insertion [expr [wave index insertpoint] +1] +wave spacer -backgroundcolor Salmon { b3_axi_slave } +wave add uvm_test_top.environment.b3.axi_slave.axi_slave_monitor.txn_stream -radix string -tag F0 +wave group b3_axi_slave_bus +wave add -group b3_axi_slave_bus hdl_top.b3_axi_slave_bus.* -radix hexadecimal -tag F0 +wave group b3_axi_slave_bus -collapse +wave insertion [expr [wave index insertpoint] +1] + +wave update on +WaveSetStreamView + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/system/sim/wave.do b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/system/sim/wave.do new file mode 100644 index 00000000..f89f9b18 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/system/sim/wave.do @@ -0,0 +1,48 @@ + + +onerror {resume} +quietly WaveActivateNextPane {} 0 + +add wave -noupdate -divider s1_b1_apb_master +add wave -noupdate /uvm_root/uvm_test_top/environment.s1.b1/apb_master/apb_master_monitor/txn_stream +add wave -noupdate -group s1_b1_apb_master_bus /hdl_top/s1_b1_apb_master_bus/* +add wave -noupdate -divider s1_b1_axi_master1 +add wave -noupdate /uvm_root/uvm_test_top/environment.s1.b1/axi_master1/axi_master1_monitor/txn_stream +add wave -noupdate -group s1_b1_axi_master1_bus /hdl_top/s1_b1_axi_master1_bus/* +add wave -noupdate -divider s1_b1_axi_master2 +add wave -noupdate /uvm_root/uvm_test_top/environment.s1.b1/axi_master2/axi_master2_monitor/txn_stream +add wave -noupdate -group s1_b1_axi_master2_bus /hdl_top/s1_b1_axi_master2_bus/* +add wave -noupdate -divider s1_b1_spi_slave +add wave -noupdate /uvm_root/uvm_test_top/environment.s1.b1/spi_slave/spi_slave_monitor/txn_stream +add wave -noupdate -group s1_b1_spi_slave_bus /hdl_top/s1_b1_spi_slave_bus/* +add wave -noupdate -divider s1_b2_spi_master +add wave -noupdate /uvm_root/uvm_test_top/environment.s1.b2/spi_master/spi_master_monitor/txn_stream +add wave -noupdate -group s1_b2_spi_master_bus /hdl_top/s1_b2_spi_master_bus/* +add wave -noupdate -divider s1_b2_wb_slave +add wave -noupdate /uvm_root/uvm_test_top/environment.s1.b2/wb_slave/wb_slave_monitor/txn_stream +add wave -noupdate -group s1_b2_wb_slave_bus /hdl_top/s1_b2_wb_slave_bus/* +add wave -noupdate -divider b3_wb_master +add wave -noupdate /uvm_root/uvm_test_top/environment.b3/wb_master/wb_master_monitor/txn_stream +add wave -noupdate -group b3_wb_master_bus /hdl_top/b3_wb_master_bus/* +add wave -noupdate -divider b3_axi_slave +add wave -noupdate /uvm_root/uvm_test_top/environment.b3/axi_slave/axi_slave_monitor/txn_stream +add wave -noupdate -group b3_axi_slave_bus /hdl_top/b3_axi_slave_bus/* + +TreeUpdate [SetDefaultTree] +quietly wave cursor active 0 +configure wave -namecolwidth 472 +configure wave -valuecolwidth 100 +configure wave -justifyvalue left +configure wave -signalnamewidth 0 +configure wave -snapdistance 10 +configure wave -datasetprefix 0 +configure wave -rowmargin 4 +configure wave -childrowmargin 2 +configure wave -gridoffset 0 +configure wave -gridperiod 1 +configure wave -griddelta 40 +configure wave -timeline 0 +configure wave -timelineunits ns +update +WaveRestoreZoom {27 ns} {168 ns} + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/system/sim/xwaves.sigs b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/system/sim/xwaves.sigs new file mode 100644 index 00000000..d75f0a57 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/system/sim/xwaves.sigs @@ -0,0 +1,17 @@ + + + + + +# pragma uvmf custom additional begin + +Group All + +#Top level signals +hdl_top.* +#Add additional levels or individual signals as needed +hdl_top.*.* + +# pragma uvmf custom additional end + + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/system/system_sve.F b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/system/system_sve.F new file mode 100644 index 00000000..e7f53136 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/system/system_sve.F @@ -0,0 +1,33 @@ + +// UVM ++incdir+${UVM_HOME}/src +${UVM_HOME}/src/uvm_pkg.sv + +// Common UVMF files +-f ${UVMF_HOME}/common/common_sve.f + +// BFM Files +-F ${UVMF_VIP_LIBRARY_HOME}/interface_packages/apb_m_pkg/apb_m_pkg_sve.F +-F ${UVMF_VIP_LIBRARY_HOME}/interface_packages/axi_m_pkg/axi_m_pkg_sve.F +-F ${UVMF_VIP_LIBRARY_HOME}/interface_packages/spi_s_pkg/spi_s_pkg_sve.F +-F ${UVMF_VIP_LIBRARY_HOME}/interface_packages/spi_m_pkg/spi_m_pkg_sve.F +-F ${UVMF_VIP_LIBRARY_HOME}/interface_packages/wb_s_pkg/wb_s_pkg_sve.F +-F ${UVMF_VIP_LIBRARY_HOME}/interface_packages/wb_m_pkg/wb_m_pkg_sve.F +-F ${UVMF_VIP_LIBRARY_HOME}/interface_packages/axi_s_pkg/axi_s_pkg_sve.F + +// Environment Files +-F ${UVMF_VIP_LIBRARY_HOME}/environment_packages/system_env_pkg/system_env_pkg_sve.F + +// Bench Files ++incdir+./tb/tests +./tb/tests/system_tests_pkg.sv + ++incdir+./tb/sequences +./tb/sequences/system_sequences_pkg.sv + ++incdir+./tb/parameters +./tb/parameters/system_parameters_pkg.sv + +./tb/testbench/hdl_top.sv +./tb/testbench/hvl_top.sv + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/system/tb/parameters/system_parameters_pkg.compile b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/system/tb/parameters/system_parameters_pkg.compile new file mode 100644 index 00000000..38160fab --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/system/tb/parameters/system_parameters_pkg.compile @@ -0,0 +1,4 @@ +needs: + - $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg_hdl.compile +src: + - system_parameters_pkg.sv diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/system/tb/parameters/system_parameters_pkg.sv b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/system/tb/parameters/system_parameters_pkg.sv new file mode 100644 index 00000000..784ce7c2 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/system/tb/parameters/system_parameters_pkg.sv @@ -0,0 +1,45 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This package contains test level parameters +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +`ifndef SYSTEM_PARAMETERS_PKG_BENCH +`define SYSTEM_PARAMETERS_PKG_BENCH + +package system_parameters_pkg; + + import uvmf_base_pkg_hdl::*; + + // pragma uvmf custom package_imports_additional begin + // pragma uvmf custom package_imports_additional end + + + // These parameters are used to uniquely identify each interface. The monitor_bfm and + // driver_bfm are placed into and retrieved from the uvm_config_db using these string + // names as the field_name. The parameter is also used to enable transaction viewing + // from the command line for selected interfaces using the UVM command line processing. + parameter string s1_b1_apb_master_BFM = "s1_b1_apb_master_BFM"; /* [0] */ + parameter string s1_b1_axi_master1_BFM = "s1_b1_axi_master1_BFM"; /* [1] */ + parameter string s1_b1_axi_master2_BFM = "s1_b1_axi_master2_BFM"; /* [2] */ + parameter string s1_b1_spi_slave_BFM = "s1_b1_spi_slave_BFM"; /* [3] */ + parameter string s1_b2_spi_master_BFM = "s1_b2_spi_master_BFM"; /* [4] */ + parameter string s1_b2_wb_slave_BFM = "s1_b2_wb_slave_BFM"; /* [5] */ + parameter string b3_wb_master_BFM = "b3_wb_master_BFM"; /* [6] */ + parameter string b3_axi_slave_BFM = "b3_axi_slave_BFM"; /* [7] */ + + // pragma uvmf custom package_item_additional begin + // pragma uvmf custom package_item_additional end + +endpackage + +// pragma uvmf custom external begin +// pragma uvmf custom external end +`endif diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/system/tb/parameters/system_parameters_pkg.vinfo b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/system/tb/parameters/system_parameters_pkg.vinfo new file mode 100644 index 00000000..701cc373 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/system/tb/parameters/system_parameters_pkg.vinfo @@ -0,0 +1,2 @@ +@use $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg_hdl.vinfo +system_parameters_pkg.sv diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/system/tb/sequences/src/example_derived_test_sequence.svh b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/system/tb/sequences/src/example_derived_test_sequence.svh new file mode 100644 index 00000000..83e44d9d --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/system/tb/sequences/src/example_derived_test_sequence.svh @@ -0,0 +1,31 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +// +//---------------------------------------------------------------------- +// +// DESCRIPTION: This file contains the top level sequence used in example_derived_test. +// It is an example of a sequence that is extended from %(benchName)_bench_sequence_base +// and can override %(benchName)_bench_sequence_base. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +`ifndef EXAMPLE_DERIVED_TEST_SEQUENCE +`define EXAMPLE_DERIVED_TEST_SEQUENCE +class example_derived_test_sequence extends system_bench_sequence_base; + + `uvm_object_utils( example_derived_test_sequence ); + + function new(string name = "" ); + super.new(name); + endfunction + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end +`endif diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/system/tb/sequences/src/register_test_sequence.svh b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/system/tb/sequences/src/register_test_sequence.svh new file mode 100644 index 00000000..86478f19 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/system/tb/sequences/src/register_test_sequence.svh @@ -0,0 +1,64 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This file contains the top level sequence used in register_test. +// It uses the UVM built in register test. Specific UVM built-in tests can be +// selected in the body task. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +`ifndef REGISTER_TEST_SEQUENCE +`define REGISTER_TEST_SEQUENCE +class register_test_sequence extends system_bench_sequence_base; + + `uvm_object_utils( register_test_sequence ); + + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + function new(string name = "" ); + super.new(name); + endfunction + + // **************************************************************************** + virtual task body(); + + // Reset the DUT + fork + // pragma uvmf custom register_test_reset begin + // UVMF_CHANGE_ME + // Select the desired wait_for_reset or provide custom mechanism. + // fork-join for this code block may be unnecessary based on your situation. + s1_b1_apb_master_config.wait_for_reset(); + s1_b1_axi_master1_config.wait_for_reset(); + s1_b1_axi_master2_config.wait_for_reset(); + s1_b1_spi_slave_config.wait_for_reset(); + s1_b2_spi_master_config.wait_for_reset(); + s1_b2_wb_slave_config.wait_for_reset(); + b3_wb_master_config.wait_for_reset(); + b3_axi_slave_config.wait_for_reset(); + // pragma uvmf custom register_test_reset end + join + + // pragma uvmf custom register_test_setup begin + // UVMF_CHANGE_ME perform potentially necessary operations before running the sequence. + // pragma uvmf custom register_test_setup end + + // pragma uvmf custom register_test_operation begin + // UVMF_CHANGE_ME Perform your custom register test + // pragma uvmf custom register_test_operation end + + endtask + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end +`endif diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/system/tb/sequences/src/system_bench_sequence_base.svh b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/system/tb/sequences/src/system_bench_sequence_base.svh new file mode 100644 index 00000000..5f9342e4 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/system/tb/sequences/src/system_bench_sequence_base.svh @@ -0,0 +1,201 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// Description: This file contains the top level and utility sequences +// used by test_top. It can be extended to create derivative top +// level sequences. +// +//---------------------------------------------------------------------- +// +//---------------------------------------------------------------------- +// +`ifndef SYSTEM_BENCH_SEQUENCE_BASE +`define SYSTEM_BENCH_SEQUENCE_BASE + +typedef system_env_configuration system_env_configuration_t; + +class system_bench_sequence_base extends uvmf_sequence_base #(uvm_sequence_item); + + `uvm_object_utils( system_bench_sequence_base ); + + // pragma uvmf custom sequences begin + +typedef system_env_sequence_base #( + .CONFIG_T(system_env_configuration_t) + ) + system_env_sequence_base_t; +rand system_env_sequence_base_t system_env_seq; + + + + // UVMF_CHANGE_ME : Instantiate, construct, and start sequences as needed to create stimulus scenarios. + // Instantiate sequences here + typedef apb_m_random_sequence s1_b1_apb_master_random_seq_t; + s1_b1_apb_master_random_seq_t s1_b1_apb_master_random_seq; + typedef axi_m_random_sequence s1_b1_axi_master1_random_seq_t; + s1_b1_axi_master1_random_seq_t s1_b1_axi_master1_random_seq; + typedef axi_m_random_sequence s1_b1_axi_master2_random_seq_t; + s1_b1_axi_master2_random_seq_t s1_b1_axi_master2_random_seq; + typedef spi_s_responder_sequence s1_b1_spi_slave_responder_seq_t; + s1_b1_spi_slave_responder_seq_t s1_b1_spi_slave_responder_seq; + typedef spi_m_random_sequence s1_b2_spi_master_random_seq_t; + s1_b2_spi_master_random_seq_t s1_b2_spi_master_random_seq; + typedef wb_s_responder_sequence s1_b2_wb_slave_responder_seq_t; + s1_b2_wb_slave_responder_seq_t s1_b2_wb_slave_responder_seq; + typedef wb_m_random_sequence b3_wb_master_random_seq_t; + b3_wb_master_random_seq_t b3_wb_master_random_seq; + typedef axi_s_responder_sequence b3_axi_slave_responder_seq_t; + b3_axi_slave_responder_seq_t b3_axi_slave_responder_seq; + // pragma uvmf custom sequences end + + // Sequencer handles for each active interface in the environment + typedef apb_m_transaction s1_b1_apb_master_transaction_t; + uvm_sequencer #(s1_b1_apb_master_transaction_t) s1_b1_apb_master_sequencer; + typedef axi_m_transaction s1_b1_axi_master1_transaction_t; + uvm_sequencer #(s1_b1_axi_master1_transaction_t) s1_b1_axi_master1_sequencer; + typedef axi_m_transaction s1_b1_axi_master2_transaction_t; + uvm_sequencer #(s1_b1_axi_master2_transaction_t) s1_b1_axi_master2_sequencer; + typedef spi_s_transaction s1_b1_spi_slave_transaction_t; + uvm_sequencer #(s1_b1_spi_slave_transaction_t) s1_b1_spi_slave_sequencer; + typedef spi_m_transaction s1_b2_spi_master_transaction_t; + uvm_sequencer #(s1_b2_spi_master_transaction_t) s1_b2_spi_master_sequencer; + typedef wb_s_transaction s1_b2_wb_slave_transaction_t; + uvm_sequencer #(s1_b2_wb_slave_transaction_t) s1_b2_wb_slave_sequencer; + typedef wb_m_transaction b3_wb_master_transaction_t; + uvm_sequencer #(b3_wb_master_transaction_t) b3_wb_master_sequencer; + typedef axi_s_transaction b3_axi_slave_transaction_t; + uvm_sequencer #(b3_axi_slave_transaction_t) b3_axi_slave_sequencer; + + + // Top level environment configuration handle + system_env_configuration_t top_configuration; + + // Configuration handles to access interface BFM's + apb_m_configuration s1_b1_apb_master_config; + axi_m_configuration s1_b1_axi_master1_config; + axi_m_configuration s1_b1_axi_master2_config; + spi_s_configuration s1_b1_spi_slave_config; + spi_m_configuration s1_b2_spi_master_config; + wb_s_configuration s1_b2_wb_slave_config; + wb_m_configuration b3_wb_master_config; + axi_s_configuration b3_axi_slave_config; + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + // **************************************************************************** + function new( string name = "" ); + super.new( name ); + // Retrieve the configuration handles from the uvm_config_db + + // Retrieve top level configuration handle + if ( !uvm_config_db#(system_env_configuration_t)::get(null,UVMF_CONFIGURATIONS, "TOP_ENV_CONFIG",top_configuration) ) begin + `uvm_info("CFG", "*** FATAL *** uvm_config_db::get can not find TOP_ENV_CONFIG. Are you using an older UVMF release than what was used to generate this bench?",UVM_NONE); + `uvm_fatal("CFG", "uvm_config_db#(system_env_configuration_t)::get cannot find resource TOP_ENV_CONFIG"); + end + + // Retrieve config handles for all agents + if( !uvm_config_db #( apb_m_configuration )::get( null , UVMF_CONFIGURATIONS , s1_b1_apb_master_BFM , s1_b1_apb_master_config ) ) + `uvm_fatal("CFG" , "uvm_config_db #( apb_m_configuration )::get cannot find resource s1_b1_apb_master_BFM" ) + if( !uvm_config_db #( axi_m_configuration )::get( null , UVMF_CONFIGURATIONS , s1_b1_axi_master1_BFM , s1_b1_axi_master1_config ) ) + `uvm_fatal("CFG" , "uvm_config_db #( axi_m_configuration )::get cannot find resource s1_b1_axi_master1_BFM" ) + if( !uvm_config_db #( axi_m_configuration )::get( null , UVMF_CONFIGURATIONS , s1_b1_axi_master2_BFM , s1_b1_axi_master2_config ) ) + `uvm_fatal("CFG" , "uvm_config_db #( axi_m_configuration )::get cannot find resource s1_b1_axi_master2_BFM" ) + if( !uvm_config_db #( spi_s_configuration )::get( null , UVMF_CONFIGURATIONS , s1_b1_spi_slave_BFM , s1_b1_spi_slave_config ) ) + `uvm_fatal("CFG" , "uvm_config_db #( spi_s_configuration )::get cannot find resource s1_b1_spi_slave_BFM" ) + if( !uvm_config_db #( spi_m_configuration )::get( null , UVMF_CONFIGURATIONS , s1_b2_spi_master_BFM , s1_b2_spi_master_config ) ) + `uvm_fatal("CFG" , "uvm_config_db #( spi_m_configuration )::get cannot find resource s1_b2_spi_master_BFM" ) + if( !uvm_config_db #( wb_s_configuration )::get( null , UVMF_CONFIGURATIONS , s1_b2_wb_slave_BFM , s1_b2_wb_slave_config ) ) + `uvm_fatal("CFG" , "uvm_config_db #( wb_s_configuration )::get cannot find resource s1_b2_wb_slave_BFM" ) + if( !uvm_config_db #( wb_m_configuration )::get( null , UVMF_CONFIGURATIONS , b3_wb_master_BFM , b3_wb_master_config ) ) + `uvm_fatal("CFG" , "uvm_config_db #( wb_m_configuration )::get cannot find resource b3_wb_master_BFM" ) + if( !uvm_config_db #( axi_s_configuration )::get( null , UVMF_CONFIGURATIONS , b3_axi_slave_BFM , b3_axi_slave_config ) ) + `uvm_fatal("CFG" , "uvm_config_db #( axi_s_configuration )::get cannot find resource b3_axi_slave_BFM" ) + + // Assign the sequencer handles from the handles within agent configurations + s1_b1_apb_master_sequencer = s1_b1_apb_master_config.get_sequencer(); + s1_b1_axi_master1_sequencer = s1_b1_axi_master1_config.get_sequencer(); + s1_b1_axi_master2_sequencer = s1_b1_axi_master2_config.get_sequencer(); + s1_b1_spi_slave_sequencer = s1_b1_spi_slave_config.get_sequencer(); + s1_b2_spi_master_sequencer = s1_b2_spi_master_config.get_sequencer(); + s1_b2_wb_slave_sequencer = s1_b2_wb_slave_config.get_sequencer(); + b3_wb_master_sequencer = b3_wb_master_config.get_sequencer(); + b3_axi_slave_sequencer = b3_axi_slave_config.get_sequencer(); + + + + // pragma uvmf custom new begin + // pragma uvmf custom new end + + endfunction + + // **************************************************************************** + virtual task body(); + // pragma uvmf custom body begin + + // Construct sequences here + + system_env_seq = system_env_sequence_base_t::type_id::create("system_env_seq"); + + s1_b1_apb_master_random_seq = s1_b1_apb_master_random_seq_t::type_id::create("s1_b1_apb_master_random_seq"); + s1_b1_axi_master1_random_seq = s1_b1_axi_master1_random_seq_t::type_id::create("s1_b1_axi_master1_random_seq"); + s1_b1_axi_master2_random_seq = s1_b1_axi_master2_random_seq_t::type_id::create("s1_b1_axi_master2_random_seq"); + s1_b1_spi_slave_responder_seq = s1_b1_spi_slave_responder_seq_t::type_id::create("s1_b1_spi_slave_responder_seq"); + s1_b2_spi_master_random_seq = s1_b2_spi_master_random_seq_t::type_id::create("s1_b2_spi_master_random_seq"); + s1_b2_wb_slave_responder_seq = s1_b2_wb_slave_responder_seq_t::type_id::create("s1_b2_wb_slave_responder_seq"); + b3_wb_master_random_seq = b3_wb_master_random_seq_t::type_id::create("b3_wb_master_random_seq"); + b3_axi_slave_responder_seq = b3_axi_slave_responder_seq_t::type_id::create("b3_axi_slave_responder_seq"); + fork + s1_b1_apb_master_config.wait_for_reset(); + s1_b1_axi_master1_config.wait_for_reset(); + s1_b1_axi_master2_config.wait_for_reset(); + s1_b1_spi_slave_config.wait_for_reset(); + s1_b2_spi_master_config.wait_for_reset(); + s1_b2_wb_slave_config.wait_for_reset(); + b3_wb_master_config.wait_for_reset(); + b3_axi_slave_config.wait_for_reset(); + join + // Start RESPONDER sequences here + fork + s1_b1_spi_slave_responder_seq.start(s1_b1_spi_slave_sequencer); + s1_b2_wb_slave_responder_seq.start(s1_b2_wb_slave_sequencer); + b3_axi_slave_responder_seq.start(b3_axi_slave_sequencer); + join_none + // Start INITIATOR sequences here + fork + repeat (25) s1_b1_apb_master_random_seq.start(s1_b1_apb_master_sequencer); + repeat (25) s1_b1_axi_master1_random_seq.start(s1_b1_axi_master1_sequencer); + repeat (25) s1_b1_axi_master2_random_seq.start(s1_b1_axi_master2_sequencer); + repeat (25) s1_b2_spi_master_random_seq.start(s1_b2_spi_master_sequencer); + repeat (25) b3_wb_master_random_seq.start(b3_wb_master_sequencer); + join + +system_env_seq.start(top_configuration.vsqr); + + // UVMF_CHANGE_ME : Extend the simulation XXX number of clocks after + // the last sequence to allow for the last sequence item to flow + // through the design. + fork + s1_b1_apb_master_config.wait_for_num_clocks(400); + s1_b1_axi_master1_config.wait_for_num_clocks(400); + s1_b1_axi_master2_config.wait_for_num_clocks(400); + s1_b1_spi_slave_config.wait_for_num_clocks(400); + s1_b2_spi_master_config.wait_for_num_clocks(400); + s1_b2_wb_slave_config.wait_for_num_clocks(400); + b3_wb_master_config.wait_for_num_clocks(400); + b3_axi_slave_config.wait_for_num_clocks(400); + join + + // pragma uvmf custom body end + endtask + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end +`endif diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/system/tb/sequences/system_sequences_pkg.compile b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/system/tb/sequences/system_sequences_pkg.compile new file mode 100644 index 00000000..d4e06aec --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/system/tb/sequences/system_sequences_pkg.compile @@ -0,0 +1,13 @@ +needs: + - $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg.compile + - ../../../../verification_ip/interface_packages/apb_m_pkg/apb_m.compile + - ../../../../verification_ip/interface_packages/axi_m_pkg/axi_m.compile + - ../../../../verification_ip/interface_packages/spi_s_pkg/spi_s.compile + - ../../../../verification_ip/interface_packages/spi_m_pkg/spi_m.compile + - ../../../../verification_ip/interface_packages/wb_s_pkg/wb_s.compile + - ../../../../verification_ip/interface_packages/wb_m_pkg/wb_m.compile + - ../../../../verification_ip/interface_packages/axi_s_pkg/axi_s.compile + - ../../../../verification_ip/environment_packages/system_env_pkg/system_env_pkg.compile + - ../parameters/system_parameters_pkg.compile +src: + - system_sequences_pkg.sv diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/system/tb/sequences/system_sequences_pkg.sv b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/system/tb/sequences/system_sequences_pkg.sv new file mode 100644 index 00000000..ee4d09cb --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/system/tb/sequences/system_sequences_pkg.sv @@ -0,0 +1,62 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This package includes all high level sequence classes used +// in the environment. These include utility sequences and top +// level sequences. +// +// CONTAINS: +// - +// - +// +//---------------------------------------------------------------------- +// +//---------------------------------------------------------------------- +// +`ifndef SYSTEM_SEQUENCES_PKG_BENCH +`define SYSTEM_SEQUENCES_PKG_BENCH +package system_sequences_pkg; + import uvm_pkg::*; + import uvmf_base_pkg::*; + import apb_m_pkg::*; + import apb_m_pkg_hdl::*; + import axi_m_pkg::*; + import axi_m_pkg_hdl::*; + import spi_s_pkg::*; + import spi_s_pkg_hdl::*; + import spi_m_pkg::*; + import spi_m_pkg_hdl::*; + import wb_s_pkg::*; + import wb_s_pkg_hdl::*; + import wb_m_pkg::*; + import wb_m_pkg_hdl::*; + import axi_s_pkg::*; + import axi_s_pkg_hdl::*; + import system_parameters_pkg::*; + import system_env_pkg::*; + `include "uvm_macros.svh" + + // pragma uvmf custom package_imports_additional begin + // pragma uvmf custom package_imports_additional end + + `include "src/system_bench_sequence_base.svh" + `include "src/register_test_sequence.svh" + `include "src/example_derived_test_sequence.svh" + + // pragma uvmf custom package_item_additional begin + // UVMF_CHANGE_ME : When adding new sequences to the src directory + // be sure to add the sequence file here so that it will be + // compiled as part of the sequence package. Be sure to place + // the new sequence after any base sequences of the new sequence. + // pragma uvmf custom package_item_additional end + +endpackage + +// pragma uvmf custom external begin +// pragma uvmf custom external end +`endif diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/system/tb/sequences/system_sequences_pkg.vinfo b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/system/tb/sequences/system_sequences_pkg.vinfo new file mode 100644 index 00000000..a5e2494b --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/system/tb/sequences/system_sequences_pkg.vinfo @@ -0,0 +1,12 @@ +@use $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg.vinfo +@use $UVMF_VIP_LIBRARY_HOME/interface_packages/apb_m_pkg/apb_m_pkg.vinfo +@use $UVMF_VIP_LIBRARY_HOME/interface_packages/axi_m_pkg/axi_m_pkg.vinfo +@use $UVMF_VIP_LIBRARY_HOME/interface_packages/spi_s_pkg/spi_s_pkg.vinfo +@use $UVMF_VIP_LIBRARY_HOME/interface_packages/spi_m_pkg/spi_m_pkg.vinfo +@use $UVMF_VIP_LIBRARY_HOME/interface_packages/wb_s_pkg/wb_s_pkg.vinfo +@use $UVMF_VIP_LIBRARY_HOME/interface_packages/wb_m_pkg/wb_m_pkg.vinfo +@use $UVMF_VIP_LIBRARY_HOME/interface_packages/axi_s_pkg/axi_s_pkg.vinfo +@use $UVMF_VIP_LIBRARY_HOME/environment_packages/system_env_pkg/system_env_pkg.vinfo +@use $UVMF_PROJECT_DIR/tb/parameters/system_parameters_pkg.vinfo ++incdir+@vinfodir +system_sequences_pkg.sv diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/system/tb/testbench/hdl_top.compile b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/system/tb/testbench/hdl_top.compile new file mode 100644 index 00000000..90ec858a --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/system/tb/testbench/hdl_top.compile @@ -0,0 +1,15 @@ +incdir: + - ${uvm_path}/src + - . +needs: + - $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg_hdl.compile + - ../parameters/system_parameters_pkg.compile + - ../../../../verification_ip/interface_packages/apb_m_pkg/apb_m_hdl.compile + - ../../../../verification_ip/interface_packages/axi_m_pkg/axi_m_hdl.compile + - ../../../../verification_ip/interface_packages/spi_s_pkg/spi_s_hdl.compile + - ../../../../verification_ip/interface_packages/spi_m_pkg/spi_m_hdl.compile + - ../../../../verification_ip/interface_packages/wb_s_pkg/wb_s_hdl.compile + - ../../../../verification_ip/interface_packages/wb_m_pkg/wb_m_hdl.compile + - ../../../../verification_ip/interface_packages/axi_s_pkg/axi_s_hdl.compile +src: + - hdl_top.sv diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/system/tb/testbench/hdl_top.sv b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/system/tb/testbench/hdl_top.sv new file mode 100644 index 00000000..2eea24a6 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/system/tb/testbench/hdl_top.sv @@ -0,0 +1,155 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// Description: This top level module instantiates all synthesizable +// static content. This and tb_top.sv are the two top level modules +// of the simulation. +// +// This module instantiates the following: +// DUT: The Design Under Test +// Interfaces: Signal bundles that contain signals connected to DUT +// Driver BFM's: BFM's that actively drive interface signals +// Monitor BFM's: BFM's that passively monitor interface signals +// +//---------------------------------------------------------------------- + +//---------------------------------------------------------------------- +// + +module hdl_top; + +import system_parameters_pkg::*; +import uvmf_base_pkg_hdl::*; + + // pragma attribute hdl_top partition_module_xrtl +// pragma uvmf custom clock_generator begin + bit clk; + // Instantiate a clk driver + // tbx clkgen + initial begin + clk = 0; + #9ns; + forever begin + clk = ~clk; + #5ns; + end + end +// pragma uvmf custom clock_generator end + +// pragma uvmf custom reset_generator begin + bit rst; + // Instantiate a rst driver + // tbx clkgen + initial begin + rst = 0; + #200ns; + rst = 1; + end +// pragma uvmf custom reset_generator end + + // pragma uvmf custom module_item_additional begin + // pragma uvmf custom module_item_additional end + + // Instantiate the signal bundle, monitor bfm and driver bfm for each interface. + // The signal bundle, _if, contains signals to be connected to the DUT. + // The monitor, monitor_bfm, observes the bus, _if, and captures transactions. + // The driver, driver_bfm, drives transactions onto the bus, _if. + apb_m_if s1_b1_apb_master_bus( + // pragma uvmf custom s1_b1_apb_master_bus_connections begin + .pclk(clk), .presetn(rst) + // pragma uvmf custom s1_b1_apb_master_bus_connections end + ); + axi_m_if s1_b1_axi_master1_bus( + // pragma uvmf custom s1_b1_axi_master1_bus_connections begin + .axi_clk(clk), .rst(rst) + // pragma uvmf custom s1_b1_axi_master1_bus_connections end + ); + axi_m_if s1_b1_axi_master2_bus( + // pragma uvmf custom s1_b1_axi_master2_bus_connections begin + .axi_clk(clk), .rst(rst) + // pragma uvmf custom s1_b1_axi_master2_bus_connections end + ); + spi_s_if s1_b1_spi_slave_bus( + // pragma uvmf custom s1_b1_spi_slave_bus_connections begin + .sck(clk), .rst(rst) + // pragma uvmf custom s1_b1_spi_slave_bus_connections end + ); + spi_m_if s1_b2_spi_master_bus( + // pragma uvmf custom s1_b2_spi_master_bus_connections begin + .sck(clk), .rst(rst) + // pragma uvmf custom s1_b2_spi_master_bus_connections end + ); + wb_s_if s1_b2_wb_slave_bus( + // pragma uvmf custom s1_b2_wb_slave_bus_connections begin + .clock(clk), .reset(rst) + // pragma uvmf custom s1_b2_wb_slave_bus_connections end + ); + wb_m_if b3_wb_master_bus( + // pragma uvmf custom b3_wb_master_bus_connections begin + .clock(clk), .reset(rst) + // pragma uvmf custom b3_wb_master_bus_connections end + ); + axi_s_if b3_axi_slave_bus( + // pragma uvmf custom b3_axi_slave_bus_connections begin + .axi_clk(clk), .rst(rst) + // pragma uvmf custom b3_axi_slave_bus_connections end + ); + apb_m_monitor_bfm s1_b1_apb_master_mon_bfm(s1_b1_apb_master_bus.monitor_port); + axi_m_monitor_bfm s1_b1_axi_master1_mon_bfm(s1_b1_axi_master1_bus.monitor_port); + axi_m_monitor_bfm s1_b1_axi_master2_mon_bfm(s1_b1_axi_master2_bus.monitor_port); + spi_s_monitor_bfm s1_b1_spi_slave_mon_bfm(s1_b1_spi_slave_bus.monitor_port); + spi_m_monitor_bfm s1_b2_spi_master_mon_bfm(s1_b2_spi_master_bus.monitor_port); + wb_s_monitor_bfm s1_b2_wb_slave_mon_bfm(s1_b2_wb_slave_bus.monitor_port); + wb_m_monitor_bfm b3_wb_master_mon_bfm(b3_wb_master_bus.monitor_port); + axi_s_monitor_bfm b3_axi_slave_mon_bfm(b3_axi_slave_bus.monitor_port); + apb_m_driver_bfm s1_b1_apb_master_drv_bfm(s1_b1_apb_master_bus.initiator_port); + axi_m_driver_bfm s1_b1_axi_master1_drv_bfm(s1_b1_axi_master1_bus.initiator_port); + axi_m_driver_bfm s1_b1_axi_master2_drv_bfm(s1_b1_axi_master2_bus.initiator_port); + spi_s_driver_bfm s1_b1_spi_slave_drv_bfm(s1_b1_spi_slave_bus.responder_port); + spi_m_driver_bfm s1_b2_spi_master_drv_bfm(s1_b2_spi_master_bus.initiator_port); + wb_s_driver_bfm s1_b2_wb_slave_drv_bfm(s1_b2_wb_slave_bus.responder_port); + wb_m_driver_bfm b3_wb_master_drv_bfm(b3_wb_master_bus.initiator_port); + axi_s_driver_bfm b3_axi_slave_drv_bfm(b3_axi_slave_bus.responder_port); + + // pragma uvmf custom dut_instantiation begin + // UVMF_CHANGE_ME : Add DUT and connect to signals in _bus interfaces listed above + // Instantiate your DUT here + // These DUT's instantiated to show verilog and vhdl instantiation + verilog_dut dut_verilog( .clk(clk), .rst(rst), .in_signal(vhdl_to_verilog_signal), .out_signal(verilog_to_vhdl_signal)); + vhdl_dut dut_vhdl ( .clk(clk), .rst(rst), .in_signal(verilog_to_vhdl_signal), .out_signal(vhdl_to_verilog_signal)); + // pragma uvmf custom dut_instantiation end + + initial begin // tbx vif_binding_block + import uvm_pkg::uvm_config_db; + // The monitor_bfm and driver_bfm for each interface is placed into the uvm_config_db. + // They are placed into the uvm_config_db using the string names defined in the parameters package. + // The string names are passed to the agent configurations by test_top through the top level configuration. + // They are retrieved by the agents configuration class for use by the agent. + uvm_config_db #( virtual apb_m_monitor_bfm )::set( null , UVMF_VIRTUAL_INTERFACES , s1_b1_apb_master_BFM , s1_b1_apb_master_mon_bfm ); + uvm_config_db #( virtual axi_m_monitor_bfm )::set( null , UVMF_VIRTUAL_INTERFACES , s1_b1_axi_master1_BFM , s1_b1_axi_master1_mon_bfm ); + uvm_config_db #( virtual axi_m_monitor_bfm )::set( null , UVMF_VIRTUAL_INTERFACES , s1_b1_axi_master2_BFM , s1_b1_axi_master2_mon_bfm ); + uvm_config_db #( virtual spi_s_monitor_bfm )::set( null , UVMF_VIRTUAL_INTERFACES , s1_b1_spi_slave_BFM , s1_b1_spi_slave_mon_bfm ); + uvm_config_db #( virtual spi_m_monitor_bfm )::set( null , UVMF_VIRTUAL_INTERFACES , s1_b2_spi_master_BFM , s1_b2_spi_master_mon_bfm ); + uvm_config_db #( virtual wb_s_monitor_bfm )::set( null , UVMF_VIRTUAL_INTERFACES , s1_b2_wb_slave_BFM , s1_b2_wb_slave_mon_bfm ); + uvm_config_db #( virtual wb_m_monitor_bfm )::set( null , UVMF_VIRTUAL_INTERFACES , b3_wb_master_BFM , b3_wb_master_mon_bfm ); + uvm_config_db #( virtual axi_s_monitor_bfm )::set( null , UVMF_VIRTUAL_INTERFACES , b3_axi_slave_BFM , b3_axi_slave_mon_bfm ); + uvm_config_db #( virtual apb_m_driver_bfm )::set( null , UVMF_VIRTUAL_INTERFACES , s1_b1_apb_master_BFM , s1_b1_apb_master_drv_bfm ); + uvm_config_db #( virtual axi_m_driver_bfm )::set( null , UVMF_VIRTUAL_INTERFACES , s1_b1_axi_master1_BFM , s1_b1_axi_master1_drv_bfm ); + uvm_config_db #( virtual axi_m_driver_bfm )::set( null , UVMF_VIRTUAL_INTERFACES , s1_b1_axi_master2_BFM , s1_b1_axi_master2_drv_bfm ); + uvm_config_db #( virtual spi_s_driver_bfm )::set( null , UVMF_VIRTUAL_INTERFACES , s1_b1_spi_slave_BFM , s1_b1_spi_slave_drv_bfm ); + uvm_config_db #( virtual spi_m_driver_bfm )::set( null , UVMF_VIRTUAL_INTERFACES , s1_b2_spi_master_BFM , s1_b2_spi_master_drv_bfm ); + uvm_config_db #( virtual wb_s_driver_bfm )::set( null , UVMF_VIRTUAL_INTERFACES , s1_b2_wb_slave_BFM , s1_b2_wb_slave_drv_bfm ); + uvm_config_db #( virtual wb_m_driver_bfm )::set( null , UVMF_VIRTUAL_INTERFACES , b3_wb_master_BFM , b3_wb_master_drv_bfm ); + uvm_config_db #( virtual axi_s_driver_bfm )::set( null , UVMF_VIRTUAL_INTERFACES , b3_axi_slave_BFM , b3_axi_slave_drv_bfm ); + end + +endmodule + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/system/tb/testbench/hdl_top.vinfo b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/system/tb/testbench/hdl_top.vinfo new file mode 100644 index 00000000..c9ec2444 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/system/tb/testbench/hdl_top.vinfo @@ -0,0 +1,11 @@ +@use $UVMF_PROJECT_DIR/rtl/verilog/verilog_dut.vinfo +@use $UVMF_PROJECT_DIR/tb/parameters/system_parameters_pkg.vinfo +@use $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg_hdl.vinfo +@use $UVMF_VIP_LIBRARY_HOME/interface_packages/apb_m_pkg/apb_m_bfm.vinfo +@use $UVMF_VIP_LIBRARY_HOME/interface_packages/axi_m_pkg/axi_m_bfm.vinfo +@use $UVMF_VIP_LIBRARY_HOME/interface_packages/spi_s_pkg/spi_s_bfm.vinfo +@use $UVMF_VIP_LIBRARY_HOME/interface_packages/spi_m_pkg/spi_m_bfm.vinfo +@use $UVMF_VIP_LIBRARY_HOME/interface_packages/wb_s_pkg/wb_s_bfm.vinfo +@use $UVMF_VIP_LIBRARY_HOME/interface_packages/wb_m_pkg/wb_m_bfm.vinfo +@use $UVMF_VIP_LIBRARY_HOME/interface_packages/axi_s_pkg/axi_s_bfm.vinfo +hdl_top.sv diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/system/tb/testbench/hvl_top.compile b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/system/tb/testbench/hvl_top.compile new file mode 100644 index 00000000..b1439fe4 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/system/tb/testbench/hvl_top.compile @@ -0,0 +1,7 @@ +incdir: + - ${uvm_path}/src + - . +needs: + - ../tests/system_tests_pkg.compile +src: + - hvl_top.sv diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/system/tb/testbench/hvl_top.sv b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/system/tb/testbench/hvl_top.sv new file mode 100644 index 00000000..5757d249 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/system/tb/testbench/hvl_top.sv @@ -0,0 +1,33 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +// +//---------------------------------------------------------------------- +// +// DESCRIPTION: This module loads the test package and starts the UVM phases. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// + +module hvl_top; + +import uvm_pkg::*; +import system_tests_pkg::*; + + // pragma uvmf custom module_item_additional begin + // pragma uvmf custom module_item_additional end + + initial begin + $timeformat(-9,3,"ns",5); + run_test(); + end + +endmodule + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/system/tb/testbench/hvl_top.vinfo b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/system/tb/testbench/hvl_top.vinfo new file mode 100644 index 00000000..7e3e46e0 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/system/tb/testbench/hvl_top.vinfo @@ -0,0 +1,2 @@ +@use $UVMF_PROJECT_DIR/tb/tests/system_tests_pkg.vinfo +hvl_top.sv diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/system/tb/testbench/top_filelist_hdl.f b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/system/tb/testbench/top_filelist_hdl.f new file mode 100644 index 00000000..1e9dab65 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/system/tb/testbench/top_filelist_hdl.f @@ -0,0 +1,3 @@ +$UVMF_PROJECT_DIR/tb/testbench/hdl_top.sv +// pragma uvmf custom additional begin +// pragma uvmf custom additional end diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/system/tb/testbench/top_filelist_hvl.f b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/system/tb/testbench/top_filelist_hvl.f new file mode 100644 index 00000000..42383ab2 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/system/tb/testbench/top_filelist_hvl.f @@ -0,0 +1,3 @@ +$UVMF_PROJECT_DIR/tb/testbench/hvl_top.sv +// pragma uvmf custom additional begin +// pragma uvmf custom additional end diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/system/tb/tests/src/example_derived_test.svh b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/system/tb/tests/src/example_derived_test.svh new file mode 100644 index 00000000..26b1db58 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/system/tb/tests/src/example_derived_test.svh @@ -0,0 +1,44 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This test extends test_top and makes +// changes to test_top using the UVM factory type_override: +// +// Test scenario: +// This is a template test that can be used to create future tests. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +`ifndef EXAMPLE_DERIVED_TEST +`define EXAMPLE_DERIVED_TEST +class example_derived_test extends test_top; + + `uvm_component_utils( example_derived_test ); + + function new( string name = "", uvm_component parent = null ); + super.new( name, parent ); + endfunction + + virtual function void build_phase(uvm_phase phase); + // The factory override below is an example of how to replace the system_bench_sequence_base + // sequence with the example_derived_test_sequence. + system_bench_sequence_base::type_id::set_type_override(example_derived_test_sequence::get_type()); + // Execute the build_phase of test_top AFTER all factory overrides have been created. + super.build_phase(phase); + // pragma uvmf custom configuration_settings_post_randomize begin + // UVMF_CHANGE_ME Test specific configuration values can be set here. + // The configuration structure has already been randomized. + // pragma uvmf custom configuration_settings_post_randomize end + endfunction + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end +`endif diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/system/tb/tests/src/register_test.svh b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/system/tb/tests/src/register_test.svh new file mode 100644 index 00000000..00ce2f48 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/system/tb/tests/src/register_test.svh @@ -0,0 +1,41 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This test extends test_top and makes +// changes to test_top using the UVM factory type_override: +// +// Test scenario: +// This is a template test that can be used to create future tests. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +`ifndef REGISTER_TEST +`define REGISTER_TEST +class register_test extends test_top; + + `uvm_component_utils( register_test ); + + function new( string name = "", uvm_component parent = null ); + super.new( name, parent ); + endfunction + + virtual function void build_phase(uvm_phase phase); + // The factory override below replaces the system_bench_sequence_base + // sequence with the register_test_sequence. + system_bench_sequence_base::type_id::set_type_override(register_test_sequence::get_type()); + // Execute the build_phase of test_top AFTER all factory overrides have been created. + super.build_phase(phase); + endfunction + + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end +`endif diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/system/tb/tests/src/test_top.svh b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/system/tb/tests/src/test_top.svh new file mode 100644 index 00000000..2ad06615 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/system/tb/tests/src/test_top.svh @@ -0,0 +1,91 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// Description: This top level UVM test is the base class for all +// future tests created for this project. +// +// This test class contains: +// Configuration: The top level configuration for the project. +// Environment: The top level environment for the project. +// Top_level_sequence: The top level sequence for the project. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// + +typedef system_env_configuration system_env_configuration_t; +typedef system_environment system_environment_t; +`ifndef TEST_TOP +`define TEST_TOP +class test_top extends uvmf_test_base #(.CONFIG_T(system_env_configuration_t), + .ENV_T(system_environment_t), + .TOP_LEVEL_SEQ_T(system_bench_sequence_base)); + + `uvm_component_utils( test_top ); + + + + string interface_names[] = { + s1_b1_apb_master_BFM /* s1_b1_apb_master [0] */ , + s1_b1_axi_master1_BFM /* s1_b1_axi_master1 [1] */ , + s1_b1_axi_master2_BFM /* s1_b1_axi_master2 [2] */ , + s1_b1_spi_slave_BFM /* s1_b1_spi_slave [3] */ , + s1_b2_spi_master_BFM /* s1_b2_spi_master [4] */ , + s1_b2_wb_slave_BFM /* s1_b2_wb_slave [5] */ , + b3_wb_master_BFM /* b3_wb_master [6] */ , + b3_axi_slave_BFM /* b3_axi_slave [7] */ +}; + +uvmf_active_passive_t interface_activities[] = { + ACTIVE /* s1_b1_apb_master [0] */ , + ACTIVE /* s1_b1_axi_master1 [1] */ , + ACTIVE /* s1_b1_axi_master2 [2] */ , + ACTIVE /* s1_b1_spi_slave [3] */ , + ACTIVE /* s1_b2_spi_master [4] */ , + ACTIVE /* s1_b2_wb_slave [5] */ , + ACTIVE /* b3_wb_master [6] */ , + ACTIVE /* b3_axi_slave [7] */ }; + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + // **************************************************************************** + // FUNCTION: new() + // This is the standard systemVerilog constructor. All components are + // constructed in the build_phase to allow factory overriding. + // + function new( string name = "", uvm_component parent = null ); + super.new( name ,parent ); + endfunction + + + + // **************************************************************************** + // FUNCTION: build_phase() + // The construction of the configuration and environment classes is done in + // the build_phase of uvmf_test_base. Once the configuraton and environment + // classes are built then the initialize call is made to perform the + // following: + // Monitor and driver BFM virtual interface handle passing into agents + // Set the active/passive state for each agent + // Once this build_phase completes, the build_phase of the environment is + // executed which builds the agents. + // + virtual function void build_phase(uvm_phase phase); +// pragma uvmf custom build_phase_pre_super begin +// pragma uvmf custom build_phase_pre_super end + super.build_phase(phase); + // pragma uvmf custom configuration_settings_post_randomize begin + // pragma uvmf custom configuration_settings_post_randomize end + configuration.initialize(NA, "uvm_test_top.environment", interface_names, null, interface_activities); + endfunction + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end +`endif diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/system/tb/tests/system_tests_pkg.compile b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/system/tb/tests/system_tests_pkg.compile new file mode 100644 index 00000000..5a1d5a5a --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/system/tb/tests/system_tests_pkg.compile @@ -0,0 +1,14 @@ +needs: + - $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg.compile + - ../../../../verification_ip/interface_packages/apb_m_pkg/apb_m.compile + - ../../../../verification_ip/interface_packages/axi_m_pkg/axi_m.compile + - ../../../../verification_ip/interface_packages/spi_s_pkg/spi_s.compile + - ../../../../verification_ip/interface_packages/spi_m_pkg/spi_m.compile + - ../../../../verification_ip/interface_packages/wb_s_pkg/wb_s.compile + - ../../../../verification_ip/interface_packages/wb_m_pkg/wb_m.compile + - ../../../../verification_ip/interface_packages/axi_s_pkg/axi_s.compile + - ../../../../verification_ip/environment_packages/system_env_pkg/system_env_pkg.compile + - ../parameters/system_parameters_pkg.compile + - ../sequences/system_sequences_pkg.compile +src: + - system_tests_pkg.sv diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/system/tb/tests/system_tests_pkg.sv b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/system/tb/tests/system_tests_pkg.sv new file mode 100644 index 00000000..3dcfa477 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/system/tb/tests/system_tests_pkg.sv @@ -0,0 +1,65 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This package contains all tests currently written for +// the simulation project. Once compiled, any test can be selected +// from the vsim command line using +UVM_TESTNAME=yourTestNameHere +// +// CONTAINS: +// - +// - +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +`ifndef SYSTEM_TESTS_PKG +`define SYSTEM_TESTS_PKG +package system_tests_pkg; + + import uvm_pkg::*; + import uvmf_base_pkg::*; + import system_parameters_pkg::*; + import system_env_pkg::*; + import system_sequences_pkg::*; + import apb_m_pkg::*; + import apb_m_pkg_hdl::*; + import axi_m_pkg::*; + import axi_m_pkg_hdl::*; + import spi_s_pkg::*; + import spi_s_pkg_hdl::*; + import spi_m_pkg::*; + import spi_m_pkg_hdl::*; + import wb_s_pkg::*; + import wb_s_pkg_hdl::*; + import wb_m_pkg::*; + import wb_m_pkg_hdl::*; + import axi_s_pkg::*; + import axi_s_pkg_hdl::*; + + + `include "uvm_macros.svh" + + // pragma uvmf custom package_imports_additional begin + // pragma uvmf custom package_imports_additional end + + `include "src/test_top.svh" + `include "src/register_test.svh" + `include "src/example_derived_test.svh" + + // pragma uvmf custom package_item_additional begin + // UVMF_CHANGE_ME : When adding new tests to the src directory + // be sure to add the test file here so that it will be + // compiled as part of the test package. Be sure to place + // the new test after any base tests of the new test. + // pragma uvmf custom package_item_additional end + +endpackage + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/system/tb/tests/system_tests_pkg.vinfo b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/system/tb/tests/system_tests_pkg.vinfo new file mode 100644 index 00000000..e00b60f3 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/system/tb/tests/system_tests_pkg.vinfo @@ -0,0 +1,13 @@ +@use $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg.vinfo +@use $UVMF_VIP_LIBRARY_HOME/interface_packages/apb_m_pkg/apb_m_pkg.vinfo +@use $UVMF_VIP_LIBRARY_HOME/interface_packages/axi_m_pkg/axi_m_pkg.vinfo +@use $UVMF_VIP_LIBRARY_HOME/interface_packages/spi_s_pkg/spi_s_pkg.vinfo +@use $UVMF_VIP_LIBRARY_HOME/interface_packages/spi_m_pkg/spi_m_pkg.vinfo +@use $UVMF_VIP_LIBRARY_HOME/interface_packages/wb_s_pkg/wb_s_pkg.vinfo +@use $UVMF_VIP_LIBRARY_HOME/interface_packages/wb_m_pkg/wb_m_pkg.vinfo +@use $UVMF_VIP_LIBRARY_HOME/interface_packages/axi_s_pkg/axi_s_pkg.vinfo +@use $UVMF_VIP_LIBRARY_HOME/environment_packages/system_env_pkg/system_env_pkg.vinfo +@use $UVMF_PROJECT_DIR/tb/parameters/system_parameters_pkg.vinfo +@use $UVMF_PROJECT_DIR/tb/sequences/system_sequences_pkg.vinfo ++incdir+@vinfodir +system_tests_pkg.sv diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/system/yaml/system_bench.yaml b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/system/yaml/system_bench.yaml new file mode 100644 index 00000000..24d295b4 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/project_benches/system/yaml/system_bench.yaml @@ -0,0 +1,29 @@ +uvmf: + benches: + system: + active_passive: + - bfm_name: s1_b1_apb_master + value: ACTIVE + - bfm_name: s1_b1_axi_master1 + value: ACTIVE + - bfm_name: s1_b1_axi_master2 + value: ACTIVE + - bfm_name: s1_b1_spi_slave + value: ACTIVE + - bfm_name: s1_b2_spi_master + value: ACTIVE + - bfm_name: s1_b2_wb_slave + value: ACTIVE + - bfm_name: b3_wb_master + value: ACTIVE + - bfm_name: b3_axi_slave + value: ACTIVE + active_passive_default: ACTIVE + clock_half_period: 5ns + clock_phase_offset: 9ns + existing_library_component: 'True' + interface_params: [] + reset_assertion_level: 'False' + reset_duration: 200ns + top_env: system + use_dpi_link: 'False' diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/environment_packages/block_1_env_pkg/.project b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/environment_packages/block_1_env_pkg/.project new file mode 100644 index 00000000..db755a2e --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/environment_packages/block_1_env_pkg/.project @@ -0,0 +1,32 @@ + + + block_1_env_pkg + + + + + + org.python.pydev.PyDevBuilder + + + + + net.sf.sveditor.core.SVProjectBuilder + + + + + + net.sf.sveditor.core.SVNature + org.python.pydev.pythonNature + + + + + + UVMF_VIP_LIBRARY_HOME + $%7BPARENT-2-PROJECT_LOC%7D + + + + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/environment_packages/block_1_env_pkg/.svproject b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/environment_packages/block_1_env_pkg/.svproject new file mode 100644 index 00000000..148d5d69 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/environment_packages/block_1_env_pkg/.svproject @@ -0,0 +1,16 @@ + + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/environment_packages/block_1_env_pkg/Makefile b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/environment_packages/block_1_env_pkg/Makefile new file mode 100644 index 00000000..d0b7efd8 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/environment_packages/block_1_env_pkg/Makefile @@ -0,0 +1,56 @@ +# block_1 environment packages source and make target + +# pragma uvmf custom additional begin +# pragma uvmf custom additional end + +# Include all requisite sub-environment package targets for this bench + +block_1_ENV_PKG =\ + $(UVMF_VIP_LIBRARY_HOME)/environment_packages/block_1_env_pkg/block_1_env_pkg.sv + +COMP_block_1_PKG_TGT_0 = q_comp_block_1_env_pkg +COMP_block_1_PKG_TGT_1 = v_comp_block_1_env_pkg +COMP_block_1_PKG_TGT = $(COMP_block_1_PKG_TGT_$(USE_VELOCE)) + +comp_block_1_env_pkg: $(COMP_block_1_PKG_TGT) + +q_comp_block_1_env_pkg: + $(HVL_COMP_CMD) +incdir+$(UVMF_VIP_LIBRARY_HOME)/environment_packages/block_1_env_pkg $(block_1_ENV_PKG) + +v_comp_block_1_env_pkg: q_comp_block_1_env_pkg + $(VELANALYZE_HVL_CMD) +incdir+$(UVMF_VIP_LIBRARY_HOME)/environment_packages/block_1_env_pkg $(block_1_ENV_PKG) + + + +ifeq ($(MTI_VCO_MODE),64) + GCC_COMP_ARCH = -m64 +else + GCC_COMP_ARCH = -m32 +endif + +export block_1_ENV_DPI_SRC ?= $(UVMF_VIP_LIBRARY_HOME)/environment_packages/block_1_env_pkg/dpi + +C_FILE_COMPILE_LIST_block_1_env_pkg = \ + +O_FILE_COMPILE_LIST_block_1_env_pkg = $(notdir $(C_FILE_COMPILE_LIST_block_1_env_pkg:.c=.o)) + +GCC_COMP_ARGS_block_1_env_pkg += -I$(block_1_ENV_DPI_SRC) \ + -fPIC + +GCC_COMP_ARGS_block_1_env_pkg += $(block_1_ENV_GCC_COMP_ARGUMENTS) + +GCC_LINK_ARGS_block_1_env_pkg += \ + \ + -o .so + +comp_block_1_env_pkg_c_files: + @echo "--------------------------------" + @echo "Compiling Environment C source" + @echo "--------------------------------" + gcc $(GCC_COMP_ARCH) $(GCC_COMP_ARGS_block_1_env_pkg) $(C_FILE_COMPILE_LIST_block_1_env_pkg) + @echo "--------------------------------" + @echo "Linking Environment C objects into a shared object" + @echo "--------------------------------" + gcc $(GCC_COMP_ARCH) $(GCC_LINK_ARGS_block_1_env_pkg) $(O_FILE_COMPILE_LIST_block_1_env_pkg) + @echo "--------------------------------" + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/environment_packages/block_1_env_pkg/block_1_env_pkg.compile b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/environment_packages/block_1_env_pkg/block_1_env_pkg.compile new file mode 100644 index 00000000..4c6f4844 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/environment_packages/block_1_env_pkg/block_1_env_pkg.compile @@ -0,0 +1,9 @@ +needs: + - $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg.compile + - ../../../verification_ip/interface_packages/apb_m_pkg/apb_m_hvl.compile + - ../../../verification_ip/interface_packages/axi_m_pkg/axi_m_hvl.compile + - ../../../verification_ip/interface_packages/spi_s_pkg/spi_s_hvl.compile + +src: + - block_1_env_pkg.sv + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/environment_packages/block_1_env_pkg/block_1_env_pkg.sv b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/environment_packages/block_1_env_pkg/block_1_env_pkg.sv new file mode 100644 index 00000000..490ba8f1 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/environment_packages/block_1_env_pkg/block_1_env_pkg.sv @@ -0,0 +1,63 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// PACKAGE: This file defines all of the files contained in the +// environment package that will run on the host simulator. +// +// CONTAINS: +// - +// - +// - +// - +// - +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +package block_1_env_pkg; + + import uvm_pkg::*; + `include "uvm_macros.svh" + import uvmf_base_pkg::*; + import apb_m_pkg::*; + import apb_m_pkg_hdl::*; + import axi_m_pkg::*; + import axi_m_pkg_hdl::*; + import spi_s_pkg::*; + import spi_s_pkg_hdl::*; + + `uvm_analysis_imp_decl(_axi_2_ae) + `uvm_analysis_imp_decl(_apb_ae) + `uvm_analysis_imp_decl(_axi_1_ae) + `uvm_analysis_imp_decl(_sco_from_pre_ae) + `uvm_analysis_imp_decl(_spi_ae) + + // pragma uvmf custom package_imports_additional begin + // pragma uvmf custom package_imports_additional end + + // Parameters defined as HVL parameters + + `include "src/block_1_env_typedefs.svh" + `include "src/block_1_env_configuration.svh" + `include "src/block_1_predictor.svh" + `include "src/block_1_scoreboard.svh" + `include "src/block_1_environment.svh" + `include "src/block_1_env_sequence_base.svh" + + // pragma uvmf custom package_item_additional begin + // UVMF_CHANGE_ME : When adding new environment level sequences to the src directory + // be sure to add the sequence file here so that it will be + // compiled as part of the environment package. Be sure to place + // the new sequence after any base sequence of the new sequence. + // pragma uvmf custom package_item_additional end + +endpackage + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/environment_packages/block_1_env_pkg/block_1_env_pkg.vinfo b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/environment_packages/block_1_env_pkg/block_1_env_pkg.vinfo new file mode 100644 index 00000000..c2733a14 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/environment_packages/block_1_env_pkg/block_1_env_pkg.vinfo @@ -0,0 +1,6 @@ +@use $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg.vinfo +@use $UVMF_VIP_LIBRARY_HOME/interface_packages/apb_m_pkg/apb_m_pkg.vinfo +@use $UVMF_VIP_LIBRARY_HOME/interface_packages/axi_m_pkg/axi_m_pkg.vinfo +@use $UVMF_VIP_LIBRARY_HOME/interface_packages/spi_s_pkg/spi_s_pkg.vinfo ++incdir+@vinfodir +block_1_env_pkg.sv diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/environment_packages/block_1_env_pkg/block_1_env_pkg_sve.F b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/environment_packages/block_1_env_pkg/block_1_env_pkg_sve.F new file mode 100644 index 00000000..c6edfc2e --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/environment_packages/block_1_env_pkg/block_1_env_pkg_sve.F @@ -0,0 +1,12 @@ + +// UVM ++incdir+${UVM_HOME}/src +${UVM_HOME}/src/uvm_pkg.sv + +// Common UVMF files +-f ${UVMF_HOME}/common/common_sve.f + +// Sub-Environments + ++incdir+. +./block_1_env_pkg.sv diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/environment_packages/block_1_env_pkg/compile.do b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/environment_packages/block_1_env_pkg/compile.do new file mode 100644 index 00000000..bac5463f --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/environment_packages/block_1_env_pkg/compile.do @@ -0,0 +1,12 @@ +# Tcl do file for compile of block_1 interface + +# pragma uvmf custom additional begin +# pragma uvmf custom additional end + + + +quietly set cmd [format "vlog -timescale 1ps/1ps +incdir+%s/environment_packages/block_1_env_pkg" $env(UVMF_VIP_LIBRARY_HOME)] +quietly set cmd [format "%s %s/environment_packages/block_1_env_pkg/block_1_env_pkg.sv" $cmd $env(UVMF_VIP_LIBRARY_HOME)] +eval $cmd + + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/environment_packages/block_1_env_pkg/src/block_1_env_configuration.svh b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/environment_packages/block_1_env_pkg/src/block_1_env_configuration.svh new file mode 100644 index 00000000..885cbdff --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/environment_packages/block_1_env_pkg/src/block_1_env_configuration.svh @@ -0,0 +1,166 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: THis is the configuration for the block_1 environment. +// it contains configuration classes for each agent. It also contains +// environment level configuration variables. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +`ifndef BLOCK_1_ENV_CONFIGURATION +`define BLOCK_1_ENV_CONFIGURATION + +class block_1_env_configuration +extends uvmf_environment_configuration_base; + + `uvm_object_utils( block_1_env_configuration ) + + bit has_scoreboard; + +//Constraints for the configuration variables: + + + covergroup block_1_configuration_cg; + // pragma uvmf custom covergroup begin + option.auto_bin_max=1024; + coverpoint has_scoreboard; + // pragma uvmf custom covergroup end + endgroup + + + typedef apb_m_configuration apb_master_config_t; + rand apb_master_config_t apb_master_config; + + typedef axi_m_configuration axi_master1_config_t; + rand axi_master1_config_t axi_master1_config; + + typedef axi_m_configuration axi_master2_config_t; + rand axi_master2_config_t axi_master2_config; + + typedef spi_s_configuration spi_slave_config_t; + rand spi_slave_config_t spi_slave_config; + + + + + typedef uvmf_virtual_sequencer_base #(.CONFIG_T(block_1_env_configuration)) block_1_vsqr_t; + block_1_vsqr_t vsqr; + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + +// **************************************************************************** +// FUNCTION : new() +// This function is the standard SystemVerilog constructor. +// This function constructs the configuration object for each agent in the environment. +// + function new( string name = "" ); + super.new( name ); + + + apb_master_config = apb_master_config_t::type_id::create("apb_master_config"); + axi_master1_config = axi_master1_config_t::type_id::create("axi_master1_config"); + axi_master2_config = axi_master2_config_t::type_id::create("axi_master2_config"); + spi_slave_config = spi_slave_config_t::type_id::create("spi_slave_config"); + + + block_1_configuration_cg=new; + `uvm_warning("COVERAGE_MODEL_REVIEW", "A covergroup has been constructed which may need review because of either generation or re-generation with merging. Please note that configuration variables added as a result of re-generation and merging are not automatically added to the covergroup. Remove this warning after the covergroup has been reviewed.") + + // pragma uvmf custom new begin + // pragma uvmf custom new end + endfunction + +// **************************************************************************** +// FUNCTION : set_vsqr() +// This function is used to assign the vsqr handle. + virtual function void set_vsqr( block_1_vsqr_t vsqr); + this.vsqr = vsqr; + endfunction : set_vsqr + +// **************************************************************************** +// FUNCTION: post_randomize() +// This function is automatically called after the randomize() function +// is executed. +// + function void post_randomize(); + super.post_randomize(); + // pragma uvmf custom post_randomize begin + // pragma uvmf custom post_randomize end + endfunction + +// **************************************************************************** +// FUNCTION: convert2string() +// This function converts all variables in this class to a single string for +// logfile reporting. This function concatenates the convert2string result for +// each agent configuration in this configuration class. +// + virtual function string convert2string(); + // pragma uvmf custom convert2string begin + return { + $sformatf("has_scoreboard:0x%x ",has_scoreboard), + "\n", apb_master_config.convert2string, + "\n", axi_master1_config.convert2string, + "\n", axi_master2_config.convert2string, + "\n", spi_slave_config.convert2string + + + }; + // pragma uvmf custom convert2string end + endfunction +// **************************************************************************** +// FUNCTION: initialize(); +// This function configures each interface agents configuration class. The +// sim level determines the active/passive state of the agent. The environment_path +// identifies the hierarchy down to and including the instantiation name of the +// environment for this configuration class. Each instance of the environment +// has its own configuration class. The string interface names are used by +// the agent configurations to identify the virtual interface handle to pull from +// the uvm_config_db. +// + function void initialize(uvmf_sim_level_t sim_level, + string environment_path, + string interface_names[], + uvm_reg_block register_model = null, + uvmf_active_passive_t interface_activity[] = {} + ); + + super.initialize(sim_level, environment_path, interface_names, register_model, interface_activity); + + + + // Interface initialization for local agents + apb_master_config.initialize( interface_activity[0], {environment_path,".apb_master"}, interface_names[0]); + apb_master_config.initiator_responder = INITIATOR; + // apb_master_config.has_coverage = 1; + axi_master1_config.initialize( interface_activity[1], {environment_path,".axi_master1"}, interface_names[1]); + axi_master1_config.initiator_responder = INITIATOR; + // axi_master1_config.has_coverage = 1; + axi_master2_config.initialize( interface_activity[2], {environment_path,".axi_master2"}, interface_names[2]); + axi_master2_config.initiator_responder = INITIATOR; + // axi_master2_config.has_coverage = 1; + spi_slave_config.initialize( interface_activity[3], {environment_path,".spi_slave"}, interface_names[3]); + spi_slave_config.initiator_responder = RESPONDER; + // spi_slave_config.has_coverage = 1; + + + + + + // pragma uvmf custom initialize begin + // pragma uvmf custom initialize end + + endfunction + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end +`endif + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/environment_packages/block_1_env_pkg/src/block_1_env_sequence_base.svh b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/environment_packages/block_1_env_pkg/src/block_1_env_sequence_base.svh new file mode 100644 index 00000000..25444e45 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/environment_packages/block_1_env_pkg/src/block_1_env_sequence_base.svh @@ -0,0 +1,86 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This file contains environment level sequences that will +// be reused from block to top level simulations. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +`ifndef BLOCK_1_ENV_SEQUENCE_BASE +`define BLOCK_1_ENV_SEQUENCE_BASE + +class block_1_env_sequence_base #( + type CONFIG_T + ) extends uvmf_virtual_sequence_base #(.CONFIG_T(CONFIG_T)); + + + `uvm_object_param_utils( block_1_env_sequence_base #( + CONFIG_T + ) ); + + +// This block_1_env_sequence_base contains a handle to a block_1_env_configuration object +// named configuration. This configuration variable contains a handle to each +// sequencer within each agent within this environment and any sub-environments. +// The configuration object handle is automatically assigned in the pre_body in the +// base class of this sequence. The configuration handle is retrieved from the +// virtual sequencer that this sequence is started on. +// Available sequencer handles within the environment configuration: + + // Initiator agent sequencers in block_1_environment: + // configuration.apb_master_config.sequencer + // configuration.axi_master1_config.sequencer + // configuration.axi_master2_config.sequencer + + // Responder agent sequencers in block_1_environment: + // configuration.spi_slave_config.sequencer + + + typedef apb_m_random_sequence apb_master_random_sequence_t; + apb_master_random_sequence_t apb_master_rand_seq; + + typedef axi_m_random_sequence axi_master1_random_sequence_t; + axi_master1_random_sequence_t axi_master1_rand_seq; + + typedef axi_m_random_sequence axi_master2_random_sequence_t; + axi_master2_random_sequence_t axi_master2_rand_seq; + + + + + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + function new(string name = "" ); + super.new(name); + apb_master_rand_seq = apb_master_random_sequence_t::type_id::create("apb_master_rand_seq"); + axi_master1_rand_seq = axi_master1_random_sequence_t::type_id::create("axi_master1_rand_seq"); + axi_master2_rand_seq = axi_master2_random_sequence_t::type_id::create("axi_master2_rand_seq"); + + + endfunction + + virtual task body(); + + if ( configuration.apb_master_config.sequencer != null ) + repeat (25) apb_master_rand_seq.start(configuration.apb_master_config.sequencer); + if ( configuration.axi_master1_config.sequencer != null ) + repeat (25) axi_master1_rand_seq.start(configuration.axi_master1_config.sequencer); + if ( configuration.axi_master2_config.sequencer != null ) + repeat (25) axi_master2_rand_seq.start(configuration.axi_master2_config.sequencer); + + + endtask + +endclass +// pragma uvmf custom external begin +// pragma uvmf custom external end + +`endif diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/environment_packages/block_1_env_pkg/src/block_1_env_typedefs.svh b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/environment_packages/block_1_env_pkg/src/block_1_env_typedefs.svh new file mode 100644 index 00000000..9814bd58 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/environment_packages/block_1_env_pkg/src/block_1_env_typedefs.svh @@ -0,0 +1,20 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: +// This file contains defines and typedefs to be compiled for use in +// the environment package. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// + + + // pragma uvmf custom additional begin + // pragma uvmf custom additional end + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/environment_packages/block_1_env_pkg/src/block_1_environment.svh b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/environment_packages/block_1_env_pkg/src/block_1_environment.svh new file mode 100644 index 00000000..0744df61 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/environment_packages/block_1_env_pkg/src/block_1_environment.svh @@ -0,0 +1,147 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This environment contains all agents, predictors and +// scoreboards required for the block level design. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +`ifndef BLOCK_1_ENVIRONMENT +`define BLOCK_1_ENVIRONMENT + +class block_1_environment extends uvmf_environment_base #( + .CONFIG_T( block_1_env_configuration + )); + `uvm_component_utils( block_1_environment ) + + + + uvm_analysis_port #(apb_m_transaction) apb_master_ap; + uvm_analysis_port #(axi_m_transaction) axi_master1_ap; + uvm_analysis_port #(axi_m_transaction) axi_master2_ap; + uvm_analysis_port #(spi_s_transaction) spi_slave_ap; + + + typedef apb_m_agent apb_master_t; + apb_master_t apb_master; + + typedef axi_m_agent axi_master1_t; + axi_master1_t axi_master1; + + typedef axi_m_agent axi_master2_t; + axi_master2_t axi_master2; + + typedef spi_s_agent spi_slave_t; + spi_slave_t spi_slave; + + + + + typedef block_1_predictor #( + .CONFIG_T(CONFIG_T) + ) block_1_pred_t; + block_1_pred_t block_1_pred; + typedef block_1_scoreboard #( + .CONFIG_T(CONFIG_T) + ) block_1_sb_t; + block_1_sb_t block_1_sb; + + + + + typedef uvmf_virtual_sequencer_base #(.CONFIG_T(block_1_env_configuration)) block_1_vsqr_t; + block_1_vsqr_t vsqr; + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + +// **************************************************************************** +// FUNCTION : new() +// This function is the standard SystemVerilog constructor. +// + function new( string name = "", uvm_component parent = null ); + super.new( name, parent ); + endfunction + +// **************************************************************************** +// FUNCTION: build_phase() +// This function builds all components within this environment. +// + virtual function void build_phase(uvm_phase phase); +// pragma uvmf custom build_phase_pre_super begin +// pragma uvmf custom build_phase_pre_super end + super.build_phase(phase); + apb_master_ap = new("apb_master_ap",this); + axi_master1_ap = new("axi_master1_ap",this); + axi_master2_ap = new("axi_master2_ap",this); + spi_slave_ap = new("spi_slave_ap",this); + apb_master = apb_master_t::type_id::create("apb_master",this); + apb_master.set_config(configuration.apb_master_config); + axi_master1 = axi_master1_t::type_id::create("axi_master1",this); + axi_master1.set_config(configuration.axi_master1_config); + axi_master2 = axi_master2_t::type_id::create("axi_master2",this); + axi_master2.set_config(configuration.axi_master2_config); + spi_slave = spi_slave_t::type_id::create("spi_slave",this); + spi_slave.set_config(configuration.spi_slave_config); + block_1_pred = block_1_pred_t::type_id::create("block_1_pred",this); + block_1_pred.configuration = configuration; + block_1_sb = block_1_sb_t::type_id::create("block_1_sb",this); + block_1_sb.configuration = configuration; + + vsqr = block_1_vsqr_t::type_id::create("vsqr", this); + vsqr.set_config(configuration); + configuration.set_vsqr(vsqr); + + // pragma uvmf custom build_phase begin + // pragma uvmf custom build_phase end + endfunction + +// **************************************************************************** +// FUNCTION: connect_phase() +// This function makes all connections within this environment. Connections +// typically inclue agent to predictor, predictor to scoreboard and scoreboard +// to agent. +// + virtual function void connect_phase(uvm_phase phase); +// pragma uvmf custom connect_phase_pre_super begin +// pragma uvmf custom connect_phase_pre_super end + super.connect_phase(phase); + spi_slave.monitored_ap.connect(block_1_sb.spi_ae); + apb_master.monitored_ap.connect(block_1_pred.apb_ae); + axi_master1.monitored_ap.connect(block_1_pred.axi_1_ae); + axi_master2.monitored_ap.connect(block_1_pred.axi_2_ae); + block_1_pred.pre_to_sco_ap.connect(block_1_sb.sco_from_pre_ae); + apb_master.monitored_ap.connect(apb_master_ap); + axi_master1.monitored_ap.connect(axi_master1_ap); + axi_master2.monitored_ap.connect(axi_master2_ap); + spi_slave.monitored_ap.connect(spi_slave_ap); + // pragma uvmf custom reg_model_connect_phase begin + // pragma uvmf custom reg_model_connect_phase end + endfunction + +// **************************************************************************** +// FUNCTION: end_of_simulation_phase() +// This function is executed just prior to executing run_phase. This function +// was added to the environment to sample environment configuration settings +// just before the simulation exits time 0. The configuration structure is +// randomized in the build phase before the environment structure is constructed. +// Configuration variables can be customized after randomization in the build_phase +// of the extended test. +// If a sequence modifies values in the configuration structure then the sequence is +// responsible for sampling the covergroup in the configuration if required. +// + virtual function void start_of_simulation_phase(uvm_phase phase); + configuration.block_1_configuration_cg.sample(); + endfunction + +endclass +// pragma uvmf custom external begin +// pragma uvmf custom external end + +`endif diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/environment_packages/block_1_env_pkg/src/block_1_predictor.svh b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/environment_packages/block_1_env_pkg/src/block_1_predictor.svh new file mode 100644 index 00000000..0f611ca5 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/environment_packages/block_1_env_pkg/src/block_1_predictor.svh @@ -0,0 +1,179 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +// +//---------------------------------------------------------------------- +// +// DESCRIPTION: This analysis component contains analysis_exports for receiving +// data and analysis_ports for sending data. +// +// This analysis component has the following analysis_exports that receive the +// listed transaction type. +// +// axi_2_ae receives transactions of type axi_m_transaction +// apb_ae receives transactions of type apb_m_transaction +// axi_1_ae receives transactions of type axi_m_transaction +// +// This analysis component has the following analysis_ports that can broadcast +// the listed transaction type. +// +// pre_to_sco_ap broadcasts transactions of type spi_s_transaction +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +`ifndef BLOCK_1_PREDICTOR +`define BLOCK_1_PREDICTOR + +class block_1_predictor #( + type CONFIG_T, + type BASE_T = uvm_component + ) extends BASE_T; + + // Factory registration of this class + `uvm_component_param_utils( block_1_predictor #( + CONFIG_T, + BASE_T + )) + + + // Instantiate a handle to the configuration of the environment in which this component resides + CONFIG_T configuration; + + + // Instantiate the analysis exports + uvm_analysis_imp_axi_2_ae #(axi_m_transaction, block_1_predictor #( + .CONFIG_T(CONFIG_T), + .BASE_T(BASE_T) + )) axi_2_ae; + uvm_analysis_imp_apb_ae #(apb_m_transaction, block_1_predictor #( + .CONFIG_T(CONFIG_T), + .BASE_T(BASE_T) + )) apb_ae; + uvm_analysis_imp_axi_1_ae #(axi_m_transaction, block_1_predictor #( + .CONFIG_T(CONFIG_T), + .BASE_T(BASE_T) + )) axi_1_ae; + + + // Instantiate the analysis ports + uvm_analysis_port #(spi_s_transaction) pre_to_sco_ap; + + + // Transaction variable for predicted values to be sent out pre_to_sco_ap + // Once a transaction is sent through an analysis_port, another transaction should + // be constructed for the next predicted transaction. + typedef spi_s_transaction pre_to_sco_ap_output_transaction_t; + pre_to_sco_ap_output_transaction_t pre_to_sco_ap_output_transaction; + // Code for sending output transaction out through pre_to_sco_ap + // pre_to_sco_ap.write(pre_to_sco_ap_output_transaction); + + // Define transaction handles for debug visibility + axi_m_transaction axi_2_ae_debug; + apb_m_transaction apb_ae_debug; + axi_m_transaction axi_1_ae_debug; + + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + // FUNCTION: new + function new(string name, uvm_component parent); + super.new(name,parent); + `uvm_warning("PREDICTOR_REVIEW", "This predictor has been created either through generation or re-generation with merging. Remove this warning after the predictor has been reviewed.") + // pragma uvmf custom new begin + // pragma uvmf custom new end + endfunction + + // FUNCTION: build_phase + virtual function void build_phase (uvm_phase phase); + + axi_2_ae = new("axi_2_ae", this); + apb_ae = new("apb_ae", this); + axi_1_ae = new("axi_1_ae", this); + pre_to_sco_ap =new("pre_to_sco_ap", this ); + // pragma uvmf custom build_phase begin + // pragma uvmf custom build_phase end + endfunction + + // FUNCTION: write_axi_2_ae + // Transactions received through axi_2_ae initiate the execution of this function. + // This function performs prediction of DUT output values based on DUT input, configuration and state + virtual function void write_axi_2_ae(axi_m_transaction t); + // pragma uvmf custom axi_2_ae_predictor begin + axi_2_ae_debug = t; + `uvm_info("PRED", "Transaction Received through axi_2_ae", UVM_MEDIUM) + `uvm_info("PRED", {" Data: ",t.convert2string()}, UVM_FULL) + // Construct one of each output transaction type. + pre_to_sco_ap_output_transaction = pre_to_sco_ap_output_transaction_t::type_id::create("pre_to_sco_ap_output_transaction"); + // UVMF_CHANGE_ME: Implement predictor model here. + `uvm_info("UNIMPLEMENTED_PREDICTOR_MODEL", "******************************************************************************************************",UVM_NONE) + `uvm_info("UNIMPLEMENTED_PREDICTOR_MODEL", "UVMF_CHANGE_ME: The block_1_predictor::write_axi_2_ae function needs to be completed with DUT prediction model",UVM_NONE) + `uvm_info("UNIMPLEMENTED_PREDICTOR_MODEL", "******************************************************************************************************",UVM_NONE) + + // Code for sending output transaction out through pre_to_sco_ap + // Please note that each broadcasted transaction should be a different object than previously + // broadcasted transactions. Creation of a different object is done by constructing the transaction + // using either new() or create(). Broadcasting a transaction object more than once to either the + // same subscriber or multiple subscribers will result in unexpected and incorrect behavior. + pre_to_sco_ap.write(pre_to_sco_ap_output_transaction); + // pragma uvmf custom axi_2_ae_predictor end + endfunction + + // FUNCTION: write_apb_ae + // Transactions received through apb_ae initiate the execution of this function. + // This function performs prediction of DUT output values based on DUT input, configuration and state + virtual function void write_apb_ae(apb_m_transaction t); + // pragma uvmf custom apb_ae_predictor begin + apb_ae_debug = t; + `uvm_info("PRED", "Transaction Received through apb_ae", UVM_MEDIUM) + `uvm_info("PRED", {" Data: ",t.convert2string()}, UVM_FULL) + // Construct one of each output transaction type. + pre_to_sco_ap_output_transaction = pre_to_sco_ap_output_transaction_t::type_id::create("pre_to_sco_ap_output_transaction"); + // UVMF_CHANGE_ME: Implement predictor model here. + `uvm_info("UNIMPLEMENTED_PREDICTOR_MODEL", "******************************************************************************************************",UVM_NONE) + `uvm_info("UNIMPLEMENTED_PREDICTOR_MODEL", "UVMF_CHANGE_ME: The block_1_predictor::write_apb_ae function needs to be completed with DUT prediction model",UVM_NONE) + `uvm_info("UNIMPLEMENTED_PREDICTOR_MODEL", "******************************************************************************************************",UVM_NONE) + + // Code for sending output transaction out through pre_to_sco_ap + // Please note that each broadcasted transaction should be a different object than previously + // broadcasted transactions. Creation of a different object is done by constructing the transaction + // using either new() or create(). Broadcasting a transaction object more than once to either the + // same subscriber or multiple subscribers will result in unexpected and incorrect behavior. + pre_to_sco_ap.write(pre_to_sco_ap_output_transaction); + // pragma uvmf custom apb_ae_predictor end + endfunction + + // FUNCTION: write_axi_1_ae + // Transactions received through axi_1_ae initiate the execution of this function. + // This function performs prediction of DUT output values based on DUT input, configuration and state + virtual function void write_axi_1_ae(axi_m_transaction t); + // pragma uvmf custom axi_1_ae_predictor begin + axi_1_ae_debug = t; + `uvm_info("PRED", "Transaction Received through axi_1_ae", UVM_MEDIUM) + `uvm_info("PRED", {" Data: ",t.convert2string()}, UVM_FULL) + // Construct one of each output transaction type. + pre_to_sco_ap_output_transaction = pre_to_sco_ap_output_transaction_t::type_id::create("pre_to_sco_ap_output_transaction"); + // UVMF_CHANGE_ME: Implement predictor model here. + `uvm_info("UNIMPLEMENTED_PREDICTOR_MODEL", "******************************************************************************************************",UVM_NONE) + `uvm_info("UNIMPLEMENTED_PREDICTOR_MODEL", "UVMF_CHANGE_ME: The block_1_predictor::write_axi_1_ae function needs to be completed with DUT prediction model",UVM_NONE) + `uvm_info("UNIMPLEMENTED_PREDICTOR_MODEL", "******************************************************************************************************",UVM_NONE) + + // Code for sending output transaction out through pre_to_sco_ap + // Please note that each broadcasted transaction should be a different object than previously + // broadcasted transactions. Creation of a different object is done by constructing the transaction + // using either new() or create(). Broadcasting a transaction object more than once to either the + // same subscriber or multiple subscribers will result in unexpected and incorrect behavior. + pre_to_sco_ap.write(pre_to_sco_ap_output_transaction); + // pragma uvmf custom axi_1_ae_predictor end + endfunction + + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + +`endif diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/environment_packages/block_1_env_pkg/src/block_1_scoreboard.svh b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/environment_packages/block_1_env_pkg/src/block_1_scoreboard.svh new file mode 100644 index 00000000..ddb28880 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/environment_packages/block_1_env_pkg/src/block_1_scoreboard.svh @@ -0,0 +1,132 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This analysis component contains analysis_exports for receiving +// data and analysis_ports for sending data. +// +// This analysis component has the following analysis_exports that receive the +// listed transaction type. +// +// sco_from_pre_ae receives transactions of type spi_s_transaction +// spi_ae receives transactions of type spi_s_transaction +// +// This analysis component has the following analysis_ports that can broadcast +// the listed transaction type. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +`ifndef BLOCK_1_SCOREBOARD +`define BLOCK_1_SCOREBOARD + +class block_1_scoreboard #( + type CONFIG_T, + type BASE_T = uvm_component + ) extends BASE_T; + + // Factory registration of this class + `uvm_component_param_utils( block_1_scoreboard #( + CONFIG_T, + BASE_T + )) + + + // Instantiate a handle to the configuration of the environment in which this component resides + CONFIG_T configuration; + + + // Instantiate the analysis exports + uvm_analysis_imp_sco_from_pre_ae #(spi_s_transaction, block_1_scoreboard #( + .CONFIG_T(CONFIG_T), + .BASE_T(BASE_T) + )) sco_from_pre_ae; + uvm_analysis_imp_spi_ae #(spi_s_transaction, block_1_scoreboard #( + .CONFIG_T(CONFIG_T), + .BASE_T(BASE_T) + )) spi_ae; + + + + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + // FUNCTION: new + function new(string name, uvm_component parent); + super.new(name,parent); + // pragma uvmf custom new begin + // pragma uvmf custom new end + endfunction + + // FUNCTION: build_phase + virtual function void build_phase (uvm_phase phase); + + sco_from_pre_ae = new("sco_from_pre_ae", this); + spi_ae = new("spi_ae", this); + // pragma uvmf custom build_phase begin + // pragma uvmf custom build_phase end + endfunction + + // FUNCTION: write_sco_from_pre_ae + // Transactions received through sco_from_pre_ae initiate the execution of this function. + // This function performs prediction of DUT output values based on DUT input, configuration and state + virtual function void write_sco_from_pre_ae(spi_s_transaction t); + // pragma uvmf custom sco_from_pre_ae_scoreboard begin + `uvm_info("PRED", "Transaction Received through sco_from_pre_ae", UVM_MEDIUM) + `uvm_info("PRED", {" Data: ",t.convert2string()}, UVM_FULL) + // UVMF_CHANGE_ME: Implement custom scoreboard here. + `uvm_info("UNIMPLEMENTED_CUSTOM_SCOREBOARD", "******************************************************************************************************",UVM_NONE) + `uvm_info("UNIMPLEMENTED_CUSTOM_SCOREBOARD", "UVMF_CHANGE_ME: The block_1_scoreboard::write_sco_from_pre_ae function needs to be completed with custom scoreboard functionality",UVM_NONE) + `uvm_info("UNIMPLEMENTED_CUSTOM_SCOREBOARD", "******************************************************************************************************",UVM_NONE) + + // pragma uvmf custom sco_from_pre_ae_scoreboard end + endfunction + + // FUNCTION: write_spi_ae + // Transactions received through spi_ae initiate the execution of this function. + // This function performs prediction of DUT output values based on DUT input, configuration and state + virtual function void write_spi_ae(spi_s_transaction t); + // pragma uvmf custom spi_ae_scoreboard begin + `uvm_info("PRED", "Transaction Received through spi_ae", UVM_MEDIUM) + `uvm_info("PRED", {" Data: ",t.convert2string()}, UVM_FULL) + // UVMF_CHANGE_ME: Implement custom scoreboard here. + `uvm_info("UNIMPLEMENTED_CUSTOM_SCOREBOARD", "******************************************************************************************************",UVM_NONE) + `uvm_info("UNIMPLEMENTED_CUSTOM_SCOREBOARD", "UVMF_CHANGE_ME: The block_1_scoreboard::write_spi_ae function needs to be completed with custom scoreboard functionality",UVM_NONE) + `uvm_info("UNIMPLEMENTED_CUSTOM_SCOREBOARD", "******************************************************************************************************",UVM_NONE) + + // pragma uvmf custom spi_ae_scoreboard end + endfunction + + + + // FUNCTION: extract_phase + virtual function void extract_phase(uvm_phase phase); +// pragma uvmf custom extract_phase begin + super.extract_phase(phase); +// pragma uvmf custom extract_phase end + endfunction + + // FUNCTION: check_phase + virtual function void check_phase(uvm_phase phase); +// pragma uvmf custom check_phase begin + super.check_phase(phase); +// pragma uvmf custom check_phase end + endfunction + + // FUNCTION: report_phase + virtual function void report_phase(uvm_phase phase); +// pragma uvmf custom report_phase begin + super.report_phase(phase); +// pragma uvmf custom report_phase end + endfunction + +endclass +// pragma uvmf custom external begin +// pragma uvmf custom external end + +`endif diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/environment_packages/block_1_env_pkg/yaml/block_1_environment.yaml b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/environment_packages/block_1_env_pkg/yaml/block_1_environment.yaml new file mode 100644 index 00000000..e13560e8 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/environment_packages/block_1_env_pkg/yaml/block_1_environment.yaml @@ -0,0 +1,67 @@ +uvmf: + environments: + block_1: + agents: + - initiator_responder: INITIATOR + name: apb_master + type: apb_m + - initiator_responder: INITIATOR + name: axi_master1 + type: axi_m + - initiator_responder: INITIATOR + name: axi_master2 + type: axi_m + - initiator_responder: RESPONDER + name: spi_slave + type: spi_s + analysis_components: + - name: block_1_pred + parameters: [] + type: block_1_predictor + - name: block_1_sb + parameters: [] + type: block_1_scoreboard + analysis_exports: [] + analysis_ports: + - connected_to: apb_master.monitored_ap + name: apb_master_ap + trans_type: apb_m_transaction + - connected_to: axi_master1.monitored_ap + name: axi_master1_ap + trans_type: axi_m_transaction + - connected_to: axi_master2.monitored_ap + name: axi_master2_ap + trans_type: axi_m_transaction + - connected_to: spi_slave.monitored_ap + name: spi_slave_ap + trans_type: spi_s_transaction + config_constraints: [] + config_vars: + - comment: '' + isrand: 'False' + name: has_scoreboard + type: bit + value: '' + existing_library_component: 'True' + hvl_pkg_parameters: [] + non_uvmf_components: [] + parameters: [] + qvip_memory_agents: [] + scoreboards: [] + subenvs: [] + tlm_connections: + - driver: spi_slave.monitored_ap + receiver: block_1_sb.spi_ae + validate: 'True' + - driver: apb_master.monitored_ap + receiver: block_1_pred.apb_ae + validate: 'True' + - driver: axi_master1.monitored_ap + receiver: block_1_pred.axi_1_ae + validate: 'True' + - driver: axi_master2.monitored_ap + receiver: block_1_pred.axi_2_ae + validate: 'True' + - driver: block_1_pred.pre_to_sco_ap + receiver: block_1_sb.sco_from_pre_ae + validate: 'True' diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/environment_packages/block_1_env_pkg/yaml/block_1_util_comp_block_1_predictor.yaml b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/environment_packages/block_1_env_pkg/yaml/block_1_util_comp_block_1_predictor.yaml new file mode 100644 index 00000000..ce520abe --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/environment_packages/block_1_env_pkg/yaml/block_1_util_comp_block_1_predictor.yaml @@ -0,0 +1,15 @@ +uvmf: + util_components: + block_1_predictor: + analysis_exports: + - name: axi_2_ae + type: axi_m_transaction + - name: apb_ae + type: apb_m_transaction + - name: axi_1_ae + type: axi_m_transaction + analysis_ports: + - name: pre_to_sco_ap + type: spi_s_transaction + existing_library_component: 'True' + type: predictor diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/environment_packages/block_1_env_pkg/yaml/block_1_util_comp_block_1_scoreboard.yaml b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/environment_packages/block_1_env_pkg/yaml/block_1_util_comp_block_1_scoreboard.yaml new file mode 100644 index 00000000..e1fb20d8 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/environment_packages/block_1_env_pkg/yaml/block_1_util_comp_block_1_scoreboard.yaml @@ -0,0 +1,10 @@ +uvmf: + util_components: + block_1_scoreboard: + analysis_exports: + - name: sco_from_pre_ae + type: spi_s_transaction + - name: spi_ae + type: spi_s_transaction + existing_library_component: 'True' + type: scoreboard diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/environment_packages/block_2_env_pkg/.project b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/environment_packages/block_2_env_pkg/.project new file mode 100644 index 00000000..a03fd98f --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/environment_packages/block_2_env_pkg/.project @@ -0,0 +1,32 @@ + + + block_2_env_pkg + + + + + + org.python.pydev.PyDevBuilder + + + + + net.sf.sveditor.core.SVProjectBuilder + + + + + + net.sf.sveditor.core.SVNature + org.python.pydev.pythonNature + + + + + + UVMF_VIP_LIBRARY_HOME + $%7BPARENT-2-PROJECT_LOC%7D + + + + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/environment_packages/block_2_env_pkg/.svproject b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/environment_packages/block_2_env_pkg/.svproject new file mode 100644 index 00000000..8f384931 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/environment_packages/block_2_env_pkg/.svproject @@ -0,0 +1,16 @@ + + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/environment_packages/block_2_env_pkg/Makefile b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/environment_packages/block_2_env_pkg/Makefile new file mode 100644 index 00000000..68a7f9f1 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/environment_packages/block_2_env_pkg/Makefile @@ -0,0 +1,56 @@ +# block_2 environment packages source and make target + +# pragma uvmf custom additional begin +# pragma uvmf custom additional end + +# Include all requisite sub-environment package targets for this bench + +block_2_ENV_PKG =\ + $(UVMF_VIP_LIBRARY_HOME)/environment_packages/block_2_env_pkg/block_2_env_pkg.sv + +COMP_block_2_PKG_TGT_0 = q_comp_block_2_env_pkg +COMP_block_2_PKG_TGT_1 = v_comp_block_2_env_pkg +COMP_block_2_PKG_TGT = $(COMP_block_2_PKG_TGT_$(USE_VELOCE)) + +comp_block_2_env_pkg: $(COMP_block_2_PKG_TGT) + +q_comp_block_2_env_pkg: + $(HVL_COMP_CMD) +incdir+$(UVMF_VIP_LIBRARY_HOME)/environment_packages/block_2_env_pkg $(block_2_ENV_PKG) + +v_comp_block_2_env_pkg: q_comp_block_2_env_pkg + $(VELANALYZE_HVL_CMD) +incdir+$(UVMF_VIP_LIBRARY_HOME)/environment_packages/block_2_env_pkg $(block_2_ENV_PKG) + + + +ifeq ($(MTI_VCO_MODE),64) + GCC_COMP_ARCH = -m64 +else + GCC_COMP_ARCH = -m32 +endif + +export block_2_ENV_DPI_SRC ?= $(UVMF_VIP_LIBRARY_HOME)/environment_packages/block_2_env_pkg/dpi + +C_FILE_COMPILE_LIST_block_2_env_pkg = \ + +O_FILE_COMPILE_LIST_block_2_env_pkg = $(notdir $(C_FILE_COMPILE_LIST_block_2_env_pkg:.c=.o)) + +GCC_COMP_ARGS_block_2_env_pkg += -I$(block_2_ENV_DPI_SRC) \ + -fPIC + +GCC_COMP_ARGS_block_2_env_pkg += $(block_2_ENV_GCC_COMP_ARGUMENTS) + +GCC_LINK_ARGS_block_2_env_pkg += \ + \ + -o .so + +comp_block_2_env_pkg_c_files: + @echo "--------------------------------" + @echo "Compiling Environment C source" + @echo "--------------------------------" + gcc $(GCC_COMP_ARCH) $(GCC_COMP_ARGS_block_2_env_pkg) $(C_FILE_COMPILE_LIST_block_2_env_pkg) + @echo "--------------------------------" + @echo "Linking Environment C objects into a shared object" + @echo "--------------------------------" + gcc $(GCC_COMP_ARCH) $(GCC_LINK_ARGS_block_2_env_pkg) $(O_FILE_COMPILE_LIST_block_2_env_pkg) + @echo "--------------------------------" + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/environment_packages/block_2_env_pkg/block_2_env_pkg.compile b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/environment_packages/block_2_env_pkg/block_2_env_pkg.compile new file mode 100644 index 00000000..f00e42c6 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/environment_packages/block_2_env_pkg/block_2_env_pkg.compile @@ -0,0 +1,8 @@ +needs: + - $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg.compile + - ../../../verification_ip/interface_packages/spi_m_pkg/spi_m_hvl.compile + - ../../../verification_ip/interface_packages/wb_s_pkg/wb_s_hvl.compile + +src: + - block_2_env_pkg.sv + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/environment_packages/block_2_env_pkg/block_2_env_pkg.sv b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/environment_packages/block_2_env_pkg/block_2_env_pkg.sv new file mode 100644 index 00000000..737c1244 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/environment_packages/block_2_env_pkg/block_2_env_pkg.sv @@ -0,0 +1,59 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// PACKAGE: This file defines all of the files contained in the +// environment package that will run on the host simulator. +// +// CONTAINS: +// - +// - +// - +// - +// - +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +package block_2_env_pkg; + + import uvm_pkg::*; + `include "uvm_macros.svh" + import uvmf_base_pkg::*; + import spi_m_pkg::*; + import spi_m_pkg_hdl::*; + import wb_s_pkg::*; + import wb_s_pkg_hdl::*; + + `uvm_analysis_imp_decl(_spi_ae) + `uvm_analysis_imp_decl(_sco_from_pre_ae) + `uvm_analysis_imp_decl(_wb_ae) + + // pragma uvmf custom package_imports_additional begin + // pragma uvmf custom package_imports_additional end + + // Parameters defined as HVL parameters + + `include "src/block_2_env_typedefs.svh" + `include "src/block_2_env_configuration.svh" + `include "src/block_2_predictor.svh" + `include "src/block_2_scoreboard.svh" + `include "src/block_2_environment.svh" + `include "src/block_2_env_sequence_base.svh" + + // pragma uvmf custom package_item_additional begin + // UVMF_CHANGE_ME : When adding new environment level sequences to the src directory + // be sure to add the sequence file here so that it will be + // compiled as part of the environment package. Be sure to place + // the new sequence after any base sequence of the new sequence. + // pragma uvmf custom package_item_additional end + +endpackage + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/environment_packages/block_2_env_pkg/block_2_env_pkg.vinfo b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/environment_packages/block_2_env_pkg/block_2_env_pkg.vinfo new file mode 100644 index 00000000..edc8f1de --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/environment_packages/block_2_env_pkg/block_2_env_pkg.vinfo @@ -0,0 +1,5 @@ +@use $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg.vinfo +@use $UVMF_VIP_LIBRARY_HOME/interface_packages/spi_m_pkg/spi_m_pkg.vinfo +@use $UVMF_VIP_LIBRARY_HOME/interface_packages/wb_s_pkg/wb_s_pkg.vinfo ++incdir+@vinfodir +block_2_env_pkg.sv diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/environment_packages/block_2_env_pkg/block_2_env_pkg_sve.F b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/environment_packages/block_2_env_pkg/block_2_env_pkg_sve.F new file mode 100644 index 00000000..7c09328b --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/environment_packages/block_2_env_pkg/block_2_env_pkg_sve.F @@ -0,0 +1,12 @@ + +// UVM ++incdir+${UVM_HOME}/src +${UVM_HOME}/src/uvm_pkg.sv + +// Common UVMF files +-f ${UVMF_HOME}/common/common_sve.f + +// Sub-Environments + ++incdir+. +./block_2_env_pkg.sv diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/environment_packages/block_2_env_pkg/compile.do b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/environment_packages/block_2_env_pkg/compile.do new file mode 100644 index 00000000..93c75466 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/environment_packages/block_2_env_pkg/compile.do @@ -0,0 +1,12 @@ +# Tcl do file for compile of block_2 interface + +# pragma uvmf custom additional begin +# pragma uvmf custom additional end + + + +quietly set cmd [format "vlog -timescale 1ps/1ps +incdir+%s/environment_packages/block_2_env_pkg" $env(UVMF_VIP_LIBRARY_HOME)] +quietly set cmd [format "%s %s/environment_packages/block_2_env_pkg/block_2_env_pkg.sv" $cmd $env(UVMF_VIP_LIBRARY_HOME)] +eval $cmd + + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/environment_packages/block_2_env_pkg/src/block_2_env_configuration.svh b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/environment_packages/block_2_env_pkg/src/block_2_env_configuration.svh new file mode 100644 index 00000000..05f32f39 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/environment_packages/block_2_env_pkg/src/block_2_env_configuration.svh @@ -0,0 +1,150 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: THis is the configuration for the block_2 environment. +// it contains configuration classes for each agent. It also contains +// environment level configuration variables. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +`ifndef BLOCK_2_ENV_CONFIGURATION +`define BLOCK_2_ENV_CONFIGURATION + +class block_2_env_configuration +extends uvmf_environment_configuration_base; + + `uvm_object_utils( block_2_env_configuration ) + + bit has_scoreboard; + +//Constraints for the configuration variables: + + + covergroup block_2_configuration_cg; + // pragma uvmf custom covergroup begin + option.auto_bin_max=1024; + coverpoint has_scoreboard; + // pragma uvmf custom covergroup end + endgroup + + + typedef spi_m_configuration spi_master_config_t; + rand spi_master_config_t spi_master_config; + + typedef wb_s_configuration wb_slave_config_t; + rand wb_slave_config_t wb_slave_config; + + + + + typedef uvmf_virtual_sequencer_base #(.CONFIG_T(block_2_env_configuration)) block_2_vsqr_t; + block_2_vsqr_t vsqr; + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + +// **************************************************************************** +// FUNCTION : new() +// This function is the standard SystemVerilog constructor. +// This function constructs the configuration object for each agent in the environment. +// + function new( string name = "" ); + super.new( name ); + + + spi_master_config = spi_master_config_t::type_id::create("spi_master_config"); + wb_slave_config = wb_slave_config_t::type_id::create("wb_slave_config"); + + + block_2_configuration_cg=new; + `uvm_warning("COVERAGE_MODEL_REVIEW", "A covergroup has been constructed which may need review because of either generation or re-generation with merging. Please note that configuration variables added as a result of re-generation and merging are not automatically added to the covergroup. Remove this warning after the covergroup has been reviewed.") + + // pragma uvmf custom new begin + // pragma uvmf custom new end + endfunction + +// **************************************************************************** +// FUNCTION : set_vsqr() +// This function is used to assign the vsqr handle. + virtual function void set_vsqr( block_2_vsqr_t vsqr); + this.vsqr = vsqr; + endfunction : set_vsqr + +// **************************************************************************** +// FUNCTION: post_randomize() +// This function is automatically called after the randomize() function +// is executed. +// + function void post_randomize(); + super.post_randomize(); + // pragma uvmf custom post_randomize begin + // pragma uvmf custom post_randomize end + endfunction + +// **************************************************************************** +// FUNCTION: convert2string() +// This function converts all variables in this class to a single string for +// logfile reporting. This function concatenates the convert2string result for +// each agent configuration in this configuration class. +// + virtual function string convert2string(); + // pragma uvmf custom convert2string begin + return { + $sformatf("has_scoreboard:0x%x ",has_scoreboard), + "\n", spi_master_config.convert2string, + "\n", wb_slave_config.convert2string + + + }; + // pragma uvmf custom convert2string end + endfunction +// **************************************************************************** +// FUNCTION: initialize(); +// This function configures each interface agents configuration class. The +// sim level determines the active/passive state of the agent. The environment_path +// identifies the hierarchy down to and including the instantiation name of the +// environment for this configuration class. Each instance of the environment +// has its own configuration class. The string interface names are used by +// the agent configurations to identify the virtual interface handle to pull from +// the uvm_config_db. +// + function void initialize(uvmf_sim_level_t sim_level, + string environment_path, + string interface_names[], + uvm_reg_block register_model = null, + uvmf_active_passive_t interface_activity[] = {} + ); + + super.initialize(sim_level, environment_path, interface_names, register_model, interface_activity); + + + + // Interface initialization for local agents + spi_master_config.initialize( interface_activity[0], {environment_path,".spi_master"}, interface_names[0]); + spi_master_config.initiator_responder = INITIATOR; + // spi_master_config.has_coverage = 1; + wb_slave_config.initialize( interface_activity[1], {environment_path,".wb_slave"}, interface_names[1]); + wb_slave_config.initiator_responder = RESPONDER; + // wb_slave_config.has_coverage = 1; + + + + + + // pragma uvmf custom initialize begin + // pragma uvmf custom initialize end + + endfunction + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end +`endif + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/environment_packages/block_2_env_pkg/src/block_2_env_sequence_base.svh b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/environment_packages/block_2_env_pkg/src/block_2_env_sequence_base.svh new file mode 100644 index 00000000..e3139765 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/environment_packages/block_2_env_pkg/src/block_2_env_sequence_base.svh @@ -0,0 +1,72 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This file contains environment level sequences that will +// be reused from block to top level simulations. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +`ifndef BLOCK_2_ENV_SEQUENCE_BASE +`define BLOCK_2_ENV_SEQUENCE_BASE + +class block_2_env_sequence_base #( + type CONFIG_T + ) extends uvmf_virtual_sequence_base #(.CONFIG_T(CONFIG_T)); + + + `uvm_object_param_utils( block_2_env_sequence_base #( + CONFIG_T + ) ); + + +// This block_2_env_sequence_base contains a handle to a block_2_env_configuration object +// named configuration. This configuration variable contains a handle to each +// sequencer within each agent within this environment and any sub-environments. +// The configuration object handle is automatically assigned in the pre_body in the +// base class of this sequence. The configuration handle is retrieved from the +// virtual sequencer that this sequence is started on. +// Available sequencer handles within the environment configuration: + + // Initiator agent sequencers in block_2_environment: + // configuration.spi_master_config.sequencer + + // Responder agent sequencers in block_2_environment: + // configuration.wb_slave_config.sequencer + + + typedef spi_m_random_sequence spi_master_random_sequence_t; + spi_master_random_sequence_t spi_master_rand_seq; + + + + + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + function new(string name = "" ); + super.new(name); + spi_master_rand_seq = spi_master_random_sequence_t::type_id::create("spi_master_rand_seq"); + + + endfunction + + virtual task body(); + + if ( configuration.spi_master_config.sequencer != null ) + repeat (25) spi_master_rand_seq.start(configuration.spi_master_config.sequencer); + + + endtask + +endclass +// pragma uvmf custom external begin +// pragma uvmf custom external end + +`endif diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/environment_packages/block_2_env_pkg/src/block_2_env_typedefs.svh b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/environment_packages/block_2_env_pkg/src/block_2_env_typedefs.svh new file mode 100644 index 00000000..9814bd58 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/environment_packages/block_2_env_pkg/src/block_2_env_typedefs.svh @@ -0,0 +1,20 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: +// This file contains defines and typedefs to be compiled for use in +// the environment package. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// + + + // pragma uvmf custom additional begin + // pragma uvmf custom additional end + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/environment_packages/block_2_env_pkg/src/block_2_environment.svh b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/environment_packages/block_2_env_pkg/src/block_2_environment.svh new file mode 100644 index 00000000..e4cc6af8 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/environment_packages/block_2_env_pkg/src/block_2_environment.svh @@ -0,0 +1,129 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This environment contains all agents, predictors and +// scoreboards required for the block level design. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +`ifndef BLOCK_2_ENVIRONMENT +`define BLOCK_2_ENVIRONMENT + +class block_2_environment extends uvmf_environment_base #( + .CONFIG_T( block_2_env_configuration + )); + `uvm_component_utils( block_2_environment ) + + + + uvm_analysis_port #(spi_m_transaction) spi_master_ap; + uvm_analysis_port #(wb_s_transaction) wb_slave_ap; + + + typedef spi_m_agent spi_master_t; + spi_master_t spi_master; + + typedef wb_s_agent wb_slave_t; + wb_slave_t wb_slave; + + + + + typedef block_2_predictor #( + .CONFIG_T(CONFIG_T) + ) block_2_pred_t; + block_2_pred_t block_2_pred; + typedef block_2_scoreboard #( + .CONFIG_T(CONFIG_T) + ) block_2_sb_t; + block_2_sb_t block_2_sb; + + + + + typedef uvmf_virtual_sequencer_base #(.CONFIG_T(block_2_env_configuration)) block_2_vsqr_t; + block_2_vsqr_t vsqr; + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + +// **************************************************************************** +// FUNCTION : new() +// This function is the standard SystemVerilog constructor. +// + function new( string name = "", uvm_component parent = null ); + super.new( name, parent ); + endfunction + +// **************************************************************************** +// FUNCTION: build_phase() +// This function builds all components within this environment. +// + virtual function void build_phase(uvm_phase phase); +// pragma uvmf custom build_phase_pre_super begin +// pragma uvmf custom build_phase_pre_super end + super.build_phase(phase); + spi_master_ap = new("spi_master_ap",this); + wb_slave_ap = new("wb_slave_ap",this); + spi_master = spi_master_t::type_id::create("spi_master",this); + spi_master.set_config(configuration.spi_master_config); + wb_slave = wb_slave_t::type_id::create("wb_slave",this); + wb_slave.set_config(configuration.wb_slave_config); + block_2_pred = block_2_pred_t::type_id::create("block_2_pred",this); + block_2_pred.configuration = configuration; + block_2_sb = block_2_sb_t::type_id::create("block_2_sb",this); + block_2_sb.configuration = configuration; + + vsqr = block_2_vsqr_t::type_id::create("vsqr", this); + vsqr.set_config(configuration); + configuration.set_vsqr(vsqr); + + // pragma uvmf custom build_phase begin + // pragma uvmf custom build_phase end + endfunction + +// **************************************************************************** +// FUNCTION: connect_phase() +// This function makes all connections within this environment. Connections +// typically inclue agent to predictor, predictor to scoreboard and scoreboard +// to agent. +// + virtual function void connect_phase(uvm_phase phase); +// pragma uvmf custom connect_phase_pre_super begin +// pragma uvmf custom connect_phase_pre_super end + super.connect_phase(phase); + spi_master.monitored_ap.connect(block_2_pred.spi_ae); + wb_slave.monitored_ap.connect(block_2_sb.wb_ae); + block_2_pred.pre_to_sco_ap.connect(block_2_sb.sco_from_pre_ae); + spi_master.monitored_ap.connect(spi_master_ap); + wb_slave.monitored_ap.connect(wb_slave_ap); + // pragma uvmf custom reg_model_connect_phase begin + // pragma uvmf custom reg_model_connect_phase end + endfunction + +// **************************************************************************** +// FUNCTION: end_of_simulation_phase() +// This function is executed just prior to executing run_phase. This function +// was added to the environment to sample environment configuration settings +// just before the simulation exits time 0. The configuration structure is +// randomized in the build phase before the environment structure is constructed. +// Configuration variables can be customized after randomization in the build_phase +// of the extended test. +// If a sequence modifies values in the configuration structure then the sequence is +// responsible for sampling the covergroup in the configuration if required. +// + virtual function void start_of_simulation_phase(uvm_phase phase); + configuration.block_2_configuration_cg.sample(); + endfunction + +endclass +// pragma uvmf custom external begin +// pragma uvmf custom external end + +`endif diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/environment_packages/block_2_env_pkg/src/block_2_predictor.svh b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/environment_packages/block_2_env_pkg/src/block_2_predictor.svh new file mode 100644 index 00000000..3a93c19c --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/environment_packages/block_2_env_pkg/src/block_2_predictor.svh @@ -0,0 +1,117 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +// +//---------------------------------------------------------------------- +// +// DESCRIPTION: This analysis component contains analysis_exports for receiving +// data and analysis_ports for sending data. +// +// This analysis component has the following analysis_exports that receive the +// listed transaction type. +// +// spi_ae receives transactions of type spi_m_transaction +// +// This analysis component has the following analysis_ports that can broadcast +// the listed transaction type. +// +// pre_to_sco_ap broadcasts transactions of type wb_s_transaction +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +`ifndef BLOCK_2_PREDICTOR +`define BLOCK_2_PREDICTOR + +class block_2_predictor #( + type CONFIG_T, + type BASE_T = uvm_component + ) extends BASE_T; + + // Factory registration of this class + `uvm_component_param_utils( block_2_predictor #( + CONFIG_T, + BASE_T + )) + + + // Instantiate a handle to the configuration of the environment in which this component resides + CONFIG_T configuration; + + + // Instantiate the analysis exports + uvm_analysis_imp_spi_ae #(spi_m_transaction, block_2_predictor #( + .CONFIG_T(CONFIG_T), + .BASE_T(BASE_T) + )) spi_ae; + + + // Instantiate the analysis ports + uvm_analysis_port #(wb_s_transaction) pre_to_sco_ap; + + + // Transaction variable for predicted values to be sent out pre_to_sco_ap + // Once a transaction is sent through an analysis_port, another transaction should + // be constructed for the next predicted transaction. + typedef wb_s_transaction pre_to_sco_ap_output_transaction_t; + pre_to_sco_ap_output_transaction_t pre_to_sco_ap_output_transaction; + // Code for sending output transaction out through pre_to_sco_ap + // pre_to_sco_ap.write(pre_to_sco_ap_output_transaction); + + // Define transaction handles for debug visibility + spi_m_transaction spi_ae_debug; + + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + // FUNCTION: new + function new(string name, uvm_component parent); + super.new(name,parent); + `uvm_warning("PREDICTOR_REVIEW", "This predictor has been created either through generation or re-generation with merging. Remove this warning after the predictor has been reviewed.") + // pragma uvmf custom new begin + // pragma uvmf custom new end + endfunction + + // FUNCTION: build_phase + virtual function void build_phase (uvm_phase phase); + + spi_ae = new("spi_ae", this); + pre_to_sco_ap =new("pre_to_sco_ap", this ); + // pragma uvmf custom build_phase begin + // pragma uvmf custom build_phase end + endfunction + + // FUNCTION: write_spi_ae + // Transactions received through spi_ae initiate the execution of this function. + // This function performs prediction of DUT output values based on DUT input, configuration and state + virtual function void write_spi_ae(spi_m_transaction t); + // pragma uvmf custom spi_ae_predictor begin + spi_ae_debug = t; + `uvm_info("PRED", "Transaction Received through spi_ae", UVM_MEDIUM) + `uvm_info("PRED", {" Data: ",t.convert2string()}, UVM_FULL) + // Construct one of each output transaction type. + pre_to_sco_ap_output_transaction = pre_to_sco_ap_output_transaction_t::type_id::create("pre_to_sco_ap_output_transaction"); + // UVMF_CHANGE_ME: Implement predictor model here. + `uvm_info("UNIMPLEMENTED_PREDICTOR_MODEL", "******************************************************************************************************",UVM_NONE) + `uvm_info("UNIMPLEMENTED_PREDICTOR_MODEL", "UVMF_CHANGE_ME: The block_2_predictor::write_spi_ae function needs to be completed with DUT prediction model",UVM_NONE) + `uvm_info("UNIMPLEMENTED_PREDICTOR_MODEL", "******************************************************************************************************",UVM_NONE) + + // Code for sending output transaction out through pre_to_sco_ap + // Please note that each broadcasted transaction should be a different object than previously + // broadcasted transactions. Creation of a different object is done by constructing the transaction + // using either new() or create(). Broadcasting a transaction object more than once to either the + // same subscriber or multiple subscribers will result in unexpected and incorrect behavior. + pre_to_sco_ap.write(pre_to_sco_ap_output_transaction); + // pragma uvmf custom spi_ae_predictor end + endfunction + + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + +`endif diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/environment_packages/block_2_env_pkg/src/block_2_scoreboard.svh b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/environment_packages/block_2_env_pkg/src/block_2_scoreboard.svh new file mode 100644 index 00000000..766944b1 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/environment_packages/block_2_env_pkg/src/block_2_scoreboard.svh @@ -0,0 +1,132 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This analysis component contains analysis_exports for receiving +// data and analysis_ports for sending data. +// +// This analysis component has the following analysis_exports that receive the +// listed transaction type. +// +// sco_from_pre_ae receives transactions of type wb_s_transaction +// wb_ae receives transactions of type wb_s_transaction +// +// This analysis component has the following analysis_ports that can broadcast +// the listed transaction type. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +`ifndef BLOCK_2_SCOREBOARD +`define BLOCK_2_SCOREBOARD + +class block_2_scoreboard #( + type CONFIG_T, + type BASE_T = uvm_component + ) extends BASE_T; + + // Factory registration of this class + `uvm_component_param_utils( block_2_scoreboard #( + CONFIG_T, + BASE_T + )) + + + // Instantiate a handle to the configuration of the environment in which this component resides + CONFIG_T configuration; + + + // Instantiate the analysis exports + uvm_analysis_imp_sco_from_pre_ae #(wb_s_transaction, block_2_scoreboard #( + .CONFIG_T(CONFIG_T), + .BASE_T(BASE_T) + )) sco_from_pre_ae; + uvm_analysis_imp_wb_ae #(wb_s_transaction, block_2_scoreboard #( + .CONFIG_T(CONFIG_T), + .BASE_T(BASE_T) + )) wb_ae; + + + + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + // FUNCTION: new + function new(string name, uvm_component parent); + super.new(name,parent); + // pragma uvmf custom new begin + // pragma uvmf custom new end + endfunction + + // FUNCTION: build_phase + virtual function void build_phase (uvm_phase phase); + + sco_from_pre_ae = new("sco_from_pre_ae", this); + wb_ae = new("wb_ae", this); + // pragma uvmf custom build_phase begin + // pragma uvmf custom build_phase end + endfunction + + // FUNCTION: write_sco_from_pre_ae + // Transactions received through sco_from_pre_ae initiate the execution of this function. + // This function performs prediction of DUT output values based on DUT input, configuration and state + virtual function void write_sco_from_pre_ae(wb_s_transaction t); + // pragma uvmf custom sco_from_pre_ae_scoreboard begin + `uvm_info("PRED", "Transaction Received through sco_from_pre_ae", UVM_MEDIUM) + `uvm_info("PRED", {" Data: ",t.convert2string()}, UVM_FULL) + // UVMF_CHANGE_ME: Implement custom scoreboard here. + `uvm_info("UNIMPLEMENTED_CUSTOM_SCOREBOARD", "******************************************************************************************************",UVM_NONE) + `uvm_info("UNIMPLEMENTED_CUSTOM_SCOREBOARD", "UVMF_CHANGE_ME: The block_2_scoreboard::write_sco_from_pre_ae function needs to be completed with custom scoreboard functionality",UVM_NONE) + `uvm_info("UNIMPLEMENTED_CUSTOM_SCOREBOARD", "******************************************************************************************************",UVM_NONE) + + // pragma uvmf custom sco_from_pre_ae_scoreboard end + endfunction + + // FUNCTION: write_wb_ae + // Transactions received through wb_ae initiate the execution of this function. + // This function performs prediction of DUT output values based on DUT input, configuration and state + virtual function void write_wb_ae(wb_s_transaction t); + // pragma uvmf custom wb_ae_scoreboard begin + `uvm_info("PRED", "Transaction Received through wb_ae", UVM_MEDIUM) + `uvm_info("PRED", {" Data: ",t.convert2string()}, UVM_FULL) + // UVMF_CHANGE_ME: Implement custom scoreboard here. + `uvm_info("UNIMPLEMENTED_CUSTOM_SCOREBOARD", "******************************************************************************************************",UVM_NONE) + `uvm_info("UNIMPLEMENTED_CUSTOM_SCOREBOARD", "UVMF_CHANGE_ME: The block_2_scoreboard::write_wb_ae function needs to be completed with custom scoreboard functionality",UVM_NONE) + `uvm_info("UNIMPLEMENTED_CUSTOM_SCOREBOARD", "******************************************************************************************************",UVM_NONE) + + // pragma uvmf custom wb_ae_scoreboard end + endfunction + + + + // FUNCTION: extract_phase + virtual function void extract_phase(uvm_phase phase); +// pragma uvmf custom extract_phase begin + super.extract_phase(phase); +// pragma uvmf custom extract_phase end + endfunction + + // FUNCTION: check_phase + virtual function void check_phase(uvm_phase phase); +// pragma uvmf custom check_phase begin + super.check_phase(phase); +// pragma uvmf custom check_phase end + endfunction + + // FUNCTION: report_phase + virtual function void report_phase(uvm_phase phase); +// pragma uvmf custom report_phase begin + super.report_phase(phase); +// pragma uvmf custom report_phase end + endfunction + +endclass +// pragma uvmf custom external begin +// pragma uvmf custom external end + +`endif diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/environment_packages/block_2_env_pkg/yaml/block_2_environment.yaml b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/environment_packages/block_2_env_pkg/yaml/block_2_environment.yaml new file mode 100644 index 00000000..dc04d0c3 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/environment_packages/block_2_env_pkg/yaml/block_2_environment.yaml @@ -0,0 +1,49 @@ +uvmf: + environments: + block_2: + agents: + - initiator_responder: INITIATOR + name: spi_master + type: spi_m + - initiator_responder: RESPONDER + name: wb_slave + type: wb_s + analysis_components: + - name: block_2_pred + parameters: [] + type: block_2_predictor + - name: block_2_sb + parameters: [] + type: block_2_scoreboard + analysis_exports: [] + analysis_ports: + - connected_to: spi_master.monitored_ap + name: spi_master_ap + trans_type: spi_m_transaction + - connected_to: wb_slave.monitored_ap + name: wb_slave_ap + trans_type: wb_s_transaction + config_constraints: [] + config_vars: + - comment: '' + isrand: 'False' + name: has_scoreboard + type: bit + value: '' + existing_library_component: 'True' + hvl_pkg_parameters: [] + non_uvmf_components: [] + parameters: [] + qvip_memory_agents: [] + scoreboards: [] + subenvs: [] + tlm_connections: + - driver: spi_master.monitored_ap + receiver: block_2_pred.spi_ae + validate: 'True' + - driver: wb_slave.monitored_ap + receiver: block_2_sb.wb_ae + validate: 'True' + - driver: block_2_pred.pre_to_sco_ap + receiver: block_2_sb.sco_from_pre_ae + validate: 'True' diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/environment_packages/block_2_env_pkg/yaml/block_2_util_comp_block_2_predictor.yaml b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/environment_packages/block_2_env_pkg/yaml/block_2_util_comp_block_2_predictor.yaml new file mode 100644 index 00000000..c4fe0e50 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/environment_packages/block_2_env_pkg/yaml/block_2_util_comp_block_2_predictor.yaml @@ -0,0 +1,11 @@ +uvmf: + util_components: + block_2_predictor: + analysis_exports: + - name: spi_ae + type: spi_m_transaction + analysis_ports: + - name: pre_to_sco_ap + type: wb_s_transaction + existing_library_component: 'True' + type: predictor diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/environment_packages/block_2_env_pkg/yaml/block_2_util_comp_block_2_scoreboard.yaml b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/environment_packages/block_2_env_pkg/yaml/block_2_util_comp_block_2_scoreboard.yaml new file mode 100644 index 00000000..b0e3bf1a --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/environment_packages/block_2_env_pkg/yaml/block_2_util_comp_block_2_scoreboard.yaml @@ -0,0 +1,10 @@ +uvmf: + util_components: + block_2_scoreboard: + analysis_exports: + - name: sco_from_pre_ae + type: wb_s_transaction + - name: wb_ae + type: wb_s_transaction + existing_library_component: 'True' + type: scoreboard diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/environment_packages/block_3_env_pkg/.project b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/environment_packages/block_3_env_pkg/.project new file mode 100644 index 00000000..2bda5dd2 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/environment_packages/block_3_env_pkg/.project @@ -0,0 +1,32 @@ + + + block_3_env_pkg + + + + + + org.python.pydev.PyDevBuilder + + + + + net.sf.sveditor.core.SVProjectBuilder + + + + + + net.sf.sveditor.core.SVNature + org.python.pydev.pythonNature + + + + + + UVMF_VIP_LIBRARY_HOME + $%7BPARENT-2-PROJECT_LOC%7D + + + + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/environment_packages/block_3_env_pkg/.svproject b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/environment_packages/block_3_env_pkg/.svproject new file mode 100644 index 00000000..62b5e4b4 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/environment_packages/block_3_env_pkg/.svproject @@ -0,0 +1,16 @@ + + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/environment_packages/block_3_env_pkg/Makefile b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/environment_packages/block_3_env_pkg/Makefile new file mode 100644 index 00000000..945868c5 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/environment_packages/block_3_env_pkg/Makefile @@ -0,0 +1,56 @@ +# block_3 environment packages source and make target + +# pragma uvmf custom additional begin +# pragma uvmf custom additional end + +# Include all requisite sub-environment package targets for this bench + +block_3_ENV_PKG =\ + $(UVMF_VIP_LIBRARY_HOME)/environment_packages/block_3_env_pkg/block_3_env_pkg.sv + +COMP_block_3_PKG_TGT_0 = q_comp_block_3_env_pkg +COMP_block_3_PKG_TGT_1 = v_comp_block_3_env_pkg +COMP_block_3_PKG_TGT = $(COMP_block_3_PKG_TGT_$(USE_VELOCE)) + +comp_block_3_env_pkg: $(COMP_block_3_PKG_TGT) + +q_comp_block_3_env_pkg: + $(HVL_COMP_CMD) +incdir+$(UVMF_VIP_LIBRARY_HOME)/environment_packages/block_3_env_pkg $(block_3_ENV_PKG) + +v_comp_block_3_env_pkg: q_comp_block_3_env_pkg + $(VELANALYZE_HVL_CMD) +incdir+$(UVMF_VIP_LIBRARY_HOME)/environment_packages/block_3_env_pkg $(block_3_ENV_PKG) + + + +ifeq ($(MTI_VCO_MODE),64) + GCC_COMP_ARCH = -m64 +else + GCC_COMP_ARCH = -m32 +endif + +export block_3_ENV_DPI_SRC ?= $(UVMF_VIP_LIBRARY_HOME)/environment_packages/block_3_env_pkg/dpi + +C_FILE_COMPILE_LIST_block_3_env_pkg = \ + +O_FILE_COMPILE_LIST_block_3_env_pkg = $(notdir $(C_FILE_COMPILE_LIST_block_3_env_pkg:.c=.o)) + +GCC_COMP_ARGS_block_3_env_pkg += -I$(block_3_ENV_DPI_SRC) \ + -fPIC + +GCC_COMP_ARGS_block_3_env_pkg += $(block_3_ENV_GCC_COMP_ARGUMENTS) + +GCC_LINK_ARGS_block_3_env_pkg += \ + \ + -o .so + +comp_block_3_env_pkg_c_files: + @echo "--------------------------------" + @echo "Compiling Environment C source" + @echo "--------------------------------" + gcc $(GCC_COMP_ARCH) $(GCC_COMP_ARGS_block_3_env_pkg) $(C_FILE_COMPILE_LIST_block_3_env_pkg) + @echo "--------------------------------" + @echo "Linking Environment C objects into a shared object" + @echo "--------------------------------" + gcc $(GCC_COMP_ARCH) $(GCC_LINK_ARGS_block_3_env_pkg) $(O_FILE_COMPILE_LIST_block_3_env_pkg) + @echo "--------------------------------" + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/environment_packages/block_3_env_pkg/block_3_env_pkg.compile b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/environment_packages/block_3_env_pkg/block_3_env_pkg.compile new file mode 100644 index 00000000..67f11230 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/environment_packages/block_3_env_pkg/block_3_env_pkg.compile @@ -0,0 +1,8 @@ +needs: + - $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg.compile + - ../../../verification_ip/interface_packages/wb_m_pkg/wb_m_hvl.compile + - ../../../verification_ip/interface_packages/axi_s_pkg/axi_s_hvl.compile + +src: + - block_3_env_pkg.sv + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/environment_packages/block_3_env_pkg/block_3_env_pkg.sv b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/environment_packages/block_3_env_pkg/block_3_env_pkg.sv new file mode 100644 index 00000000..e4200aaf --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/environment_packages/block_3_env_pkg/block_3_env_pkg.sv @@ -0,0 +1,59 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// PACKAGE: This file defines all of the files contained in the +// environment package that will run on the host simulator. +// +// CONTAINS: +// - +// - +// - +// - +// - +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +package block_3_env_pkg; + + import uvm_pkg::*; + `include "uvm_macros.svh" + import uvmf_base_pkg::*; + import wb_m_pkg::*; + import wb_m_pkg_hdl::*; + import axi_s_pkg::*; + import axi_s_pkg_hdl::*; + + `uvm_analysis_imp_decl(_wb_ae) + `uvm_analysis_imp_decl(_sco_from_pre_ae) + `uvm_analysis_imp_decl(_axi_ae) + + // pragma uvmf custom package_imports_additional begin + // pragma uvmf custom package_imports_additional end + + // Parameters defined as HVL parameters + + `include "src/block_3_env_typedefs.svh" + `include "src/block_3_env_configuration.svh" + `include "src/block_3_predictor.svh" + `include "src/block_3_scoreboard.svh" + `include "src/block_3_environment.svh" + `include "src/block_3_env_sequence_base.svh" + + // pragma uvmf custom package_item_additional begin + // UVMF_CHANGE_ME : When adding new environment level sequences to the src directory + // be sure to add the sequence file here so that it will be + // compiled as part of the environment package. Be sure to place + // the new sequence after any base sequence of the new sequence. + // pragma uvmf custom package_item_additional end + +endpackage + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/environment_packages/block_3_env_pkg/block_3_env_pkg.vinfo b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/environment_packages/block_3_env_pkg/block_3_env_pkg.vinfo new file mode 100644 index 00000000..ac8db6f3 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/environment_packages/block_3_env_pkg/block_3_env_pkg.vinfo @@ -0,0 +1,5 @@ +@use $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg.vinfo +@use $UVMF_VIP_LIBRARY_HOME/interface_packages/wb_m_pkg/wb_m_pkg.vinfo +@use $UVMF_VIP_LIBRARY_HOME/interface_packages/axi_s_pkg/axi_s_pkg.vinfo ++incdir+@vinfodir +block_3_env_pkg.sv diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/environment_packages/block_3_env_pkg/block_3_env_pkg_sve.F b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/environment_packages/block_3_env_pkg/block_3_env_pkg_sve.F new file mode 100644 index 00000000..01f8db54 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/environment_packages/block_3_env_pkg/block_3_env_pkg_sve.F @@ -0,0 +1,12 @@ + +// UVM ++incdir+${UVM_HOME}/src +${UVM_HOME}/src/uvm_pkg.sv + +// Common UVMF files +-f ${UVMF_HOME}/common/common_sve.f + +// Sub-Environments + ++incdir+. +./block_3_env_pkg.sv diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/environment_packages/block_3_env_pkg/compile.do b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/environment_packages/block_3_env_pkg/compile.do new file mode 100644 index 00000000..a35e5e59 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/environment_packages/block_3_env_pkg/compile.do @@ -0,0 +1,12 @@ +# Tcl do file for compile of block_3 interface + +# pragma uvmf custom additional begin +# pragma uvmf custom additional end + + + +quietly set cmd [format "vlog -timescale 1ps/1ps +incdir+%s/environment_packages/block_3_env_pkg" $env(UVMF_VIP_LIBRARY_HOME)] +quietly set cmd [format "%s %s/environment_packages/block_3_env_pkg/block_3_env_pkg.sv" $cmd $env(UVMF_VIP_LIBRARY_HOME)] +eval $cmd + + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/environment_packages/block_3_env_pkg/src/block_3_env_configuration.svh b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/environment_packages/block_3_env_pkg/src/block_3_env_configuration.svh new file mode 100644 index 00000000..8a504871 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/environment_packages/block_3_env_pkg/src/block_3_env_configuration.svh @@ -0,0 +1,150 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: THis is the configuration for the block_3 environment. +// it contains configuration classes for each agent. It also contains +// environment level configuration variables. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +`ifndef BLOCK_3_ENV_CONFIGURATION +`define BLOCK_3_ENV_CONFIGURATION + +class block_3_env_configuration +extends uvmf_environment_configuration_base; + + `uvm_object_utils( block_3_env_configuration ) + + bit has_scoreboard; + +//Constraints for the configuration variables: + + + covergroup block_3_configuration_cg; + // pragma uvmf custom covergroup begin + option.auto_bin_max=1024; + coverpoint has_scoreboard; + // pragma uvmf custom covergroup end + endgroup + + + typedef wb_m_configuration wb_master_config_t; + rand wb_master_config_t wb_master_config; + + typedef axi_s_configuration axi_slave_config_t; + rand axi_slave_config_t axi_slave_config; + + + + + typedef uvmf_virtual_sequencer_base #(.CONFIG_T(block_3_env_configuration)) block_3_vsqr_t; + block_3_vsqr_t vsqr; + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + +// **************************************************************************** +// FUNCTION : new() +// This function is the standard SystemVerilog constructor. +// This function constructs the configuration object for each agent in the environment. +// + function new( string name = "" ); + super.new( name ); + + + wb_master_config = wb_master_config_t::type_id::create("wb_master_config"); + axi_slave_config = axi_slave_config_t::type_id::create("axi_slave_config"); + + + block_3_configuration_cg=new; + `uvm_warning("COVERAGE_MODEL_REVIEW", "A covergroup has been constructed which may need review because of either generation or re-generation with merging. Please note that configuration variables added as a result of re-generation and merging are not automatically added to the covergroup. Remove this warning after the covergroup has been reviewed.") + + // pragma uvmf custom new begin + // pragma uvmf custom new end + endfunction + +// **************************************************************************** +// FUNCTION : set_vsqr() +// This function is used to assign the vsqr handle. + virtual function void set_vsqr( block_3_vsqr_t vsqr); + this.vsqr = vsqr; + endfunction : set_vsqr + +// **************************************************************************** +// FUNCTION: post_randomize() +// This function is automatically called after the randomize() function +// is executed. +// + function void post_randomize(); + super.post_randomize(); + // pragma uvmf custom post_randomize begin + // pragma uvmf custom post_randomize end + endfunction + +// **************************************************************************** +// FUNCTION: convert2string() +// This function converts all variables in this class to a single string for +// logfile reporting. This function concatenates the convert2string result for +// each agent configuration in this configuration class. +// + virtual function string convert2string(); + // pragma uvmf custom convert2string begin + return { + $sformatf("has_scoreboard:0x%x ",has_scoreboard), + "\n", wb_master_config.convert2string, + "\n", axi_slave_config.convert2string + + + }; + // pragma uvmf custom convert2string end + endfunction +// **************************************************************************** +// FUNCTION: initialize(); +// This function configures each interface agents configuration class. The +// sim level determines the active/passive state of the agent. The environment_path +// identifies the hierarchy down to and including the instantiation name of the +// environment for this configuration class. Each instance of the environment +// has its own configuration class. The string interface names are used by +// the agent configurations to identify the virtual interface handle to pull from +// the uvm_config_db. +// + function void initialize(uvmf_sim_level_t sim_level, + string environment_path, + string interface_names[], + uvm_reg_block register_model = null, + uvmf_active_passive_t interface_activity[] = {} + ); + + super.initialize(sim_level, environment_path, interface_names, register_model, interface_activity); + + + + // Interface initialization for local agents + wb_master_config.initialize( interface_activity[0], {environment_path,".wb_master"}, interface_names[0]); + wb_master_config.initiator_responder = INITIATOR; + // wb_master_config.has_coverage = 1; + axi_slave_config.initialize( interface_activity[1], {environment_path,".axi_slave"}, interface_names[1]); + axi_slave_config.initiator_responder = RESPONDER; + // axi_slave_config.has_coverage = 1; + + + + + + // pragma uvmf custom initialize begin + // pragma uvmf custom initialize end + + endfunction + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end +`endif + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/environment_packages/block_3_env_pkg/src/block_3_env_sequence_base.svh b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/environment_packages/block_3_env_pkg/src/block_3_env_sequence_base.svh new file mode 100644 index 00000000..8aa76975 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/environment_packages/block_3_env_pkg/src/block_3_env_sequence_base.svh @@ -0,0 +1,72 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This file contains environment level sequences that will +// be reused from block to top level simulations. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +`ifndef BLOCK_3_ENV_SEQUENCE_BASE +`define BLOCK_3_ENV_SEQUENCE_BASE + +class block_3_env_sequence_base #( + type CONFIG_T + ) extends uvmf_virtual_sequence_base #(.CONFIG_T(CONFIG_T)); + + + `uvm_object_param_utils( block_3_env_sequence_base #( + CONFIG_T + ) ); + + +// This block_3_env_sequence_base contains a handle to a block_3_env_configuration object +// named configuration. This configuration variable contains a handle to each +// sequencer within each agent within this environment and any sub-environments. +// The configuration object handle is automatically assigned in the pre_body in the +// base class of this sequence. The configuration handle is retrieved from the +// virtual sequencer that this sequence is started on. +// Available sequencer handles within the environment configuration: + + // Initiator agent sequencers in block_3_environment: + // configuration.wb_master_config.sequencer + + // Responder agent sequencers in block_3_environment: + // configuration.axi_slave_config.sequencer + + + typedef wb_m_random_sequence wb_master_random_sequence_t; + wb_master_random_sequence_t wb_master_rand_seq; + + + + + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + function new(string name = "" ); + super.new(name); + wb_master_rand_seq = wb_master_random_sequence_t::type_id::create("wb_master_rand_seq"); + + + endfunction + + virtual task body(); + + if ( configuration.wb_master_config.sequencer != null ) + repeat (25) wb_master_rand_seq.start(configuration.wb_master_config.sequencer); + + + endtask + +endclass +// pragma uvmf custom external begin +// pragma uvmf custom external end + +`endif diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/environment_packages/block_3_env_pkg/src/block_3_env_typedefs.svh b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/environment_packages/block_3_env_pkg/src/block_3_env_typedefs.svh new file mode 100644 index 00000000..9814bd58 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/environment_packages/block_3_env_pkg/src/block_3_env_typedefs.svh @@ -0,0 +1,20 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: +// This file contains defines and typedefs to be compiled for use in +// the environment package. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// + + + // pragma uvmf custom additional begin + // pragma uvmf custom additional end + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/environment_packages/block_3_env_pkg/src/block_3_environment.svh b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/environment_packages/block_3_env_pkg/src/block_3_environment.svh new file mode 100644 index 00000000..c5da2112 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/environment_packages/block_3_env_pkg/src/block_3_environment.svh @@ -0,0 +1,129 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This environment contains all agents, predictors and +// scoreboards required for the block level design. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +`ifndef BLOCK_3_ENVIRONMENT +`define BLOCK_3_ENVIRONMENT + +class block_3_environment extends uvmf_environment_base #( + .CONFIG_T( block_3_env_configuration + )); + `uvm_component_utils( block_3_environment ) + + + + uvm_analysis_port #(wb_m_transaction) wb_master_ap; + uvm_analysis_port #(axi_s_transaction) axi_slave_ap; + + + typedef wb_m_agent wb_master_t; + wb_master_t wb_master; + + typedef axi_s_agent axi_slave_t; + axi_slave_t axi_slave; + + + + + typedef block_3_predictor #( + .CONFIG_T(CONFIG_T) + ) block_3_pred_t; + block_3_pred_t block_3_pred; + typedef block_3_scoreboard #( + .CONFIG_T(CONFIG_T) + ) block_3_sb_t; + block_3_sb_t block_3_sb; + + + + + typedef uvmf_virtual_sequencer_base #(.CONFIG_T(block_3_env_configuration)) block_3_vsqr_t; + block_3_vsqr_t vsqr; + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + +// **************************************************************************** +// FUNCTION : new() +// This function is the standard SystemVerilog constructor. +// + function new( string name = "", uvm_component parent = null ); + super.new( name, parent ); + endfunction + +// **************************************************************************** +// FUNCTION: build_phase() +// This function builds all components within this environment. +// + virtual function void build_phase(uvm_phase phase); +// pragma uvmf custom build_phase_pre_super begin +// pragma uvmf custom build_phase_pre_super end + super.build_phase(phase); + wb_master_ap = new("wb_master_ap",this); + axi_slave_ap = new("axi_slave_ap",this); + wb_master = wb_master_t::type_id::create("wb_master",this); + wb_master.set_config(configuration.wb_master_config); + axi_slave = axi_slave_t::type_id::create("axi_slave",this); + axi_slave.set_config(configuration.axi_slave_config); + block_3_pred = block_3_pred_t::type_id::create("block_3_pred",this); + block_3_pred.configuration = configuration; + block_3_sb = block_3_sb_t::type_id::create("block_3_sb",this); + block_3_sb.configuration = configuration; + + vsqr = block_3_vsqr_t::type_id::create("vsqr", this); + vsqr.set_config(configuration); + configuration.set_vsqr(vsqr); + + // pragma uvmf custom build_phase begin + // pragma uvmf custom build_phase end + endfunction + +// **************************************************************************** +// FUNCTION: connect_phase() +// This function makes all connections within this environment. Connections +// typically inclue agent to predictor, predictor to scoreboard and scoreboard +// to agent. +// + virtual function void connect_phase(uvm_phase phase); +// pragma uvmf custom connect_phase_pre_super begin +// pragma uvmf custom connect_phase_pre_super end + super.connect_phase(phase); + wb_master.monitored_ap.connect(block_3_pred.wb_ae); + axi_slave.monitored_ap.connect(block_3_sb.axi_ae); + block_3_pred.pre_to_sco_ap.connect(block_3_sb.sco_from_pre_ae); + wb_master.monitored_ap.connect(wb_master_ap); + axi_slave.monitored_ap.connect(axi_slave_ap); + // pragma uvmf custom reg_model_connect_phase begin + // pragma uvmf custom reg_model_connect_phase end + endfunction + +// **************************************************************************** +// FUNCTION: end_of_simulation_phase() +// This function is executed just prior to executing run_phase. This function +// was added to the environment to sample environment configuration settings +// just before the simulation exits time 0. The configuration structure is +// randomized in the build phase before the environment structure is constructed. +// Configuration variables can be customized after randomization in the build_phase +// of the extended test. +// If a sequence modifies values in the configuration structure then the sequence is +// responsible for sampling the covergroup in the configuration if required. +// + virtual function void start_of_simulation_phase(uvm_phase phase); + configuration.block_3_configuration_cg.sample(); + endfunction + +endclass +// pragma uvmf custom external begin +// pragma uvmf custom external end + +`endif diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/environment_packages/block_3_env_pkg/src/block_3_predictor.svh b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/environment_packages/block_3_env_pkg/src/block_3_predictor.svh new file mode 100644 index 00000000..bcd32457 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/environment_packages/block_3_env_pkg/src/block_3_predictor.svh @@ -0,0 +1,117 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +// +//---------------------------------------------------------------------- +// +// DESCRIPTION: This analysis component contains analysis_exports for receiving +// data and analysis_ports for sending data. +// +// This analysis component has the following analysis_exports that receive the +// listed transaction type. +// +// wb_ae receives transactions of type wb_m_transaction +// +// This analysis component has the following analysis_ports that can broadcast +// the listed transaction type. +// +// pre_to_sco_ap broadcasts transactions of type axi_s_transaction +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +`ifndef BLOCK_3_PREDICTOR +`define BLOCK_3_PREDICTOR + +class block_3_predictor #( + type CONFIG_T, + type BASE_T = uvm_component + ) extends BASE_T; + + // Factory registration of this class + `uvm_component_param_utils( block_3_predictor #( + CONFIG_T, + BASE_T + )) + + + // Instantiate a handle to the configuration of the environment in which this component resides + CONFIG_T configuration; + + + // Instantiate the analysis exports + uvm_analysis_imp_wb_ae #(wb_m_transaction, block_3_predictor #( + .CONFIG_T(CONFIG_T), + .BASE_T(BASE_T) + )) wb_ae; + + + // Instantiate the analysis ports + uvm_analysis_port #(axi_s_transaction) pre_to_sco_ap; + + + // Transaction variable for predicted values to be sent out pre_to_sco_ap + // Once a transaction is sent through an analysis_port, another transaction should + // be constructed for the next predicted transaction. + typedef axi_s_transaction pre_to_sco_ap_output_transaction_t; + pre_to_sco_ap_output_transaction_t pre_to_sco_ap_output_transaction; + // Code for sending output transaction out through pre_to_sco_ap + // pre_to_sco_ap.write(pre_to_sco_ap_output_transaction); + + // Define transaction handles for debug visibility + wb_m_transaction wb_ae_debug; + + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + // FUNCTION: new + function new(string name, uvm_component parent); + super.new(name,parent); + `uvm_warning("PREDICTOR_REVIEW", "This predictor has been created either through generation or re-generation with merging. Remove this warning after the predictor has been reviewed.") + // pragma uvmf custom new begin + // pragma uvmf custom new end + endfunction + + // FUNCTION: build_phase + virtual function void build_phase (uvm_phase phase); + + wb_ae = new("wb_ae", this); + pre_to_sco_ap =new("pre_to_sco_ap", this ); + // pragma uvmf custom build_phase begin + // pragma uvmf custom build_phase end + endfunction + + // FUNCTION: write_wb_ae + // Transactions received through wb_ae initiate the execution of this function. + // This function performs prediction of DUT output values based on DUT input, configuration and state + virtual function void write_wb_ae(wb_m_transaction t); + // pragma uvmf custom wb_ae_predictor begin + wb_ae_debug = t; + `uvm_info("PRED", "Transaction Received through wb_ae", UVM_MEDIUM) + `uvm_info("PRED", {" Data: ",t.convert2string()}, UVM_FULL) + // Construct one of each output transaction type. + pre_to_sco_ap_output_transaction = pre_to_sco_ap_output_transaction_t::type_id::create("pre_to_sco_ap_output_transaction"); + // UVMF_CHANGE_ME: Implement predictor model here. + `uvm_info("UNIMPLEMENTED_PREDICTOR_MODEL", "******************************************************************************************************",UVM_NONE) + `uvm_info("UNIMPLEMENTED_PREDICTOR_MODEL", "UVMF_CHANGE_ME: The block_3_predictor::write_wb_ae function needs to be completed with DUT prediction model",UVM_NONE) + `uvm_info("UNIMPLEMENTED_PREDICTOR_MODEL", "******************************************************************************************************",UVM_NONE) + + // Code for sending output transaction out through pre_to_sco_ap + // Please note that each broadcasted transaction should be a different object than previously + // broadcasted transactions. Creation of a different object is done by constructing the transaction + // using either new() or create(). Broadcasting a transaction object more than once to either the + // same subscriber or multiple subscribers will result in unexpected and incorrect behavior. + pre_to_sco_ap.write(pre_to_sco_ap_output_transaction); + // pragma uvmf custom wb_ae_predictor end + endfunction + + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + +`endif diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/environment_packages/block_3_env_pkg/src/block_3_scoreboard.svh b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/environment_packages/block_3_env_pkg/src/block_3_scoreboard.svh new file mode 100644 index 00000000..62513a79 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/environment_packages/block_3_env_pkg/src/block_3_scoreboard.svh @@ -0,0 +1,132 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This analysis component contains analysis_exports for receiving +// data and analysis_ports for sending data. +// +// This analysis component has the following analysis_exports that receive the +// listed transaction type. +// +// sco_from_pre_ae receives transactions of type axi_s_transaction +// axi_ae receives transactions of type axi_s_transaction +// +// This analysis component has the following analysis_ports that can broadcast +// the listed transaction type. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +`ifndef BLOCK_3_SCOREBOARD +`define BLOCK_3_SCOREBOARD + +class block_3_scoreboard #( + type CONFIG_T, + type BASE_T = uvm_component + ) extends BASE_T; + + // Factory registration of this class + `uvm_component_param_utils( block_3_scoreboard #( + CONFIG_T, + BASE_T + )) + + + // Instantiate a handle to the configuration of the environment in which this component resides + CONFIG_T configuration; + + + // Instantiate the analysis exports + uvm_analysis_imp_sco_from_pre_ae #(axi_s_transaction, block_3_scoreboard #( + .CONFIG_T(CONFIG_T), + .BASE_T(BASE_T) + )) sco_from_pre_ae; + uvm_analysis_imp_axi_ae #(axi_s_transaction, block_3_scoreboard #( + .CONFIG_T(CONFIG_T), + .BASE_T(BASE_T) + )) axi_ae; + + + + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + // FUNCTION: new + function new(string name, uvm_component parent); + super.new(name,parent); + // pragma uvmf custom new begin + // pragma uvmf custom new end + endfunction + + // FUNCTION: build_phase + virtual function void build_phase (uvm_phase phase); + + sco_from_pre_ae = new("sco_from_pre_ae", this); + axi_ae = new("axi_ae", this); + // pragma uvmf custom build_phase begin + // pragma uvmf custom build_phase end + endfunction + + // FUNCTION: write_sco_from_pre_ae + // Transactions received through sco_from_pre_ae initiate the execution of this function. + // This function performs prediction of DUT output values based on DUT input, configuration and state + virtual function void write_sco_from_pre_ae(axi_s_transaction t); + // pragma uvmf custom sco_from_pre_ae_scoreboard begin + `uvm_info("PRED", "Transaction Received through sco_from_pre_ae", UVM_MEDIUM) + `uvm_info("PRED", {" Data: ",t.convert2string()}, UVM_FULL) + // UVMF_CHANGE_ME: Implement custom scoreboard here. + `uvm_info("UNIMPLEMENTED_CUSTOM_SCOREBOARD", "******************************************************************************************************",UVM_NONE) + `uvm_info("UNIMPLEMENTED_CUSTOM_SCOREBOARD", "UVMF_CHANGE_ME: The block_3_scoreboard::write_sco_from_pre_ae function needs to be completed with custom scoreboard functionality",UVM_NONE) + `uvm_info("UNIMPLEMENTED_CUSTOM_SCOREBOARD", "******************************************************************************************************",UVM_NONE) + + // pragma uvmf custom sco_from_pre_ae_scoreboard end + endfunction + + // FUNCTION: write_axi_ae + // Transactions received through axi_ae initiate the execution of this function. + // This function performs prediction of DUT output values based on DUT input, configuration and state + virtual function void write_axi_ae(axi_s_transaction t); + // pragma uvmf custom axi_ae_scoreboard begin + `uvm_info("PRED", "Transaction Received through axi_ae", UVM_MEDIUM) + `uvm_info("PRED", {" Data: ",t.convert2string()}, UVM_FULL) + // UVMF_CHANGE_ME: Implement custom scoreboard here. + `uvm_info("UNIMPLEMENTED_CUSTOM_SCOREBOARD", "******************************************************************************************************",UVM_NONE) + `uvm_info("UNIMPLEMENTED_CUSTOM_SCOREBOARD", "UVMF_CHANGE_ME: The block_3_scoreboard::write_axi_ae function needs to be completed with custom scoreboard functionality",UVM_NONE) + `uvm_info("UNIMPLEMENTED_CUSTOM_SCOREBOARD", "******************************************************************************************************",UVM_NONE) + + // pragma uvmf custom axi_ae_scoreboard end + endfunction + + + + // FUNCTION: extract_phase + virtual function void extract_phase(uvm_phase phase); +// pragma uvmf custom extract_phase begin + super.extract_phase(phase); +// pragma uvmf custom extract_phase end + endfunction + + // FUNCTION: check_phase + virtual function void check_phase(uvm_phase phase); +// pragma uvmf custom check_phase begin + super.check_phase(phase); +// pragma uvmf custom check_phase end + endfunction + + // FUNCTION: report_phase + virtual function void report_phase(uvm_phase phase); +// pragma uvmf custom report_phase begin + super.report_phase(phase); +// pragma uvmf custom report_phase end + endfunction + +endclass +// pragma uvmf custom external begin +// pragma uvmf custom external end + +`endif diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/environment_packages/block_3_env_pkg/yaml/block_3_environment.yaml b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/environment_packages/block_3_env_pkg/yaml/block_3_environment.yaml new file mode 100644 index 00000000..9bb7bd0d --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/environment_packages/block_3_env_pkg/yaml/block_3_environment.yaml @@ -0,0 +1,49 @@ +uvmf: + environments: + block_3: + agents: + - initiator_responder: INITIATOR + name: wb_master + type: wb_m + - initiator_responder: RESPONDER + name: axi_slave + type: axi_s + analysis_components: + - name: block_3_pred + parameters: [] + type: block_3_predictor + - name: block_3_sb + parameters: [] + type: block_3_scoreboard + analysis_exports: [] + analysis_ports: + - connected_to: wb_master.monitored_ap + name: wb_master_ap + trans_type: wb_m_transaction + - connected_to: axi_slave.monitored_ap + name: axi_slave_ap + trans_type: axi_s_transaction + config_constraints: [] + config_vars: + - comment: '' + isrand: 'False' + name: has_scoreboard + type: bit + value: '' + existing_library_component: 'True' + hvl_pkg_parameters: [] + non_uvmf_components: [] + parameters: [] + qvip_memory_agents: [] + scoreboards: [] + subenvs: [] + tlm_connections: + - driver: wb_master.monitored_ap + receiver: block_3_pred.wb_ae + validate: 'True' + - driver: axi_slave.monitored_ap + receiver: block_3_sb.axi_ae + validate: 'True' + - driver: block_3_pred.pre_to_sco_ap + receiver: block_3_sb.sco_from_pre_ae + validate: 'True' diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/environment_packages/block_3_env_pkg/yaml/block_3_util_comp_block_3_predictor.yaml b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/environment_packages/block_3_env_pkg/yaml/block_3_util_comp_block_3_predictor.yaml new file mode 100644 index 00000000..f521bd67 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/environment_packages/block_3_env_pkg/yaml/block_3_util_comp_block_3_predictor.yaml @@ -0,0 +1,11 @@ +uvmf: + util_components: + block_3_predictor: + analysis_exports: + - name: wb_ae + type: wb_m_transaction + analysis_ports: + - name: pre_to_sco_ap + type: axi_s_transaction + existing_library_component: 'True' + type: predictor diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/environment_packages/block_3_env_pkg/yaml/block_3_util_comp_block_3_scoreboard.yaml b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/environment_packages/block_3_env_pkg/yaml/block_3_util_comp_block_3_scoreboard.yaml new file mode 100644 index 00000000..79d8d7d2 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/environment_packages/block_3_env_pkg/yaml/block_3_util_comp_block_3_scoreboard.yaml @@ -0,0 +1,10 @@ +uvmf: + util_components: + block_3_scoreboard: + analysis_exports: + - name: sco_from_pre_ae + type: axi_s_transaction + - name: axi_ae + type: axi_s_transaction + existing_library_component: 'True' + type: scoreboard diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/environment_packages/subsys_env_pkg/.project b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/environment_packages/subsys_env_pkg/.project new file mode 100644 index 00000000..d5582aca --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/environment_packages/subsys_env_pkg/.project @@ -0,0 +1,32 @@ + + + subsys_env_pkg + + + + + + org.python.pydev.PyDevBuilder + + + + + net.sf.sveditor.core.SVProjectBuilder + + + + + + net.sf.sveditor.core.SVNature + org.python.pydev.pythonNature + + + + + + UVMF_VIP_LIBRARY_HOME + $%7BPARENT-2-PROJECT_LOC%7D + + + + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/environment_packages/subsys_env_pkg/.svproject b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/environment_packages/subsys_env_pkg/.svproject new file mode 100644 index 00000000..56c4a5ca --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/environment_packages/subsys_env_pkg/.svproject @@ -0,0 +1,16 @@ + + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/environment_packages/subsys_env_pkg/Makefile b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/environment_packages/subsys_env_pkg/Makefile new file mode 100644 index 00000000..5ac49d1d --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/environment_packages/subsys_env_pkg/Makefile @@ -0,0 +1,58 @@ +# subsys environment packages source and make target + +# pragma uvmf custom additional begin +# pragma uvmf custom additional end + +# Include all requisite sub-environment package targets for this bench +include $(UVMF_VIP_LIBRARY_HOME)/environment_packages/block_1_env_pkg/Makefile +include $(UVMF_VIP_LIBRARY_HOME)/environment_packages/block_2_env_pkg/Makefile + +subsys_ENV_PKG =\ + $(UVMF_VIP_LIBRARY_HOME)/environment_packages/subsys_env_pkg/subsys_env_pkg.sv + +COMP_subsys_PKG_TGT_0 = q_comp_subsys_env_pkg +COMP_subsys_PKG_TGT_1 = v_comp_subsys_env_pkg +COMP_subsys_PKG_TGT = $(COMP_subsys_PKG_TGT_$(USE_VELOCE)) + +comp_subsys_env_pkg: $(COMP_subsys_PKG_TGT) + +q_comp_subsys_env_pkg: comp_block_1_env_pkg comp_block_2_env_pkg + $(HVL_COMP_CMD) +incdir+$(UVMF_VIP_LIBRARY_HOME)/environment_packages/subsys_env_pkg $(subsys_ENV_PKG) + +v_comp_subsys_env_pkg: q_comp_subsys_env_pkg + $(VELANALYZE_HVL_CMD) +incdir+$(UVMF_VIP_LIBRARY_HOME)/environment_packages/subsys_env_pkg $(subsys_ENV_PKG) + + + +ifeq ($(MTI_VCO_MODE),64) + GCC_COMP_ARCH = -m64 +else + GCC_COMP_ARCH = -m32 +endif + +export subsys_ENV_DPI_SRC ?= $(UVMF_VIP_LIBRARY_HOME)/environment_packages/subsys_env_pkg/dpi + +C_FILE_COMPILE_LIST_subsys_env_pkg = \ + +O_FILE_COMPILE_LIST_subsys_env_pkg = $(notdir $(C_FILE_COMPILE_LIST_subsys_env_pkg:.c=.o)) + +GCC_COMP_ARGS_subsys_env_pkg += -I$(subsys_ENV_DPI_SRC) \ + -fPIC + +GCC_COMP_ARGS_subsys_env_pkg += $(subsys_ENV_GCC_COMP_ARGUMENTS) + +GCC_LINK_ARGS_subsys_env_pkg += \ + \ + -o .so + +comp_subsys_env_pkg_c_files: + @echo "--------------------------------" + @echo "Compiling Environment C source" + @echo "--------------------------------" + gcc $(GCC_COMP_ARCH) $(GCC_COMP_ARGS_subsys_env_pkg) $(C_FILE_COMPILE_LIST_subsys_env_pkg) + @echo "--------------------------------" + @echo "Linking Environment C objects into a shared object" + @echo "--------------------------------" + gcc $(GCC_COMP_ARCH) $(GCC_LINK_ARGS_subsys_env_pkg) $(O_FILE_COMPILE_LIST_subsys_env_pkg) + @echo "--------------------------------" + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/environment_packages/subsys_env_pkg/compile.do b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/environment_packages/subsys_env_pkg/compile.do new file mode 100644 index 00000000..755d5d0d --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/environment_packages/subsys_env_pkg/compile.do @@ -0,0 +1,18 @@ +# Tcl do file for compile of subsys interface + +# pragma uvmf custom additional begin +# pragma uvmf custom additional end + + +# Include build for sub-environment block_1_env_pkg +quietly set cmd [format "source %s/environment_packages/block_1_env_pkg/compile.do" $env(UVMF_VIP_LIBRARY_HOME)] +eval $cmd +# Include build for sub-environment block_2_env_pkg +quietly set cmd [format "source %s/environment_packages/block_2_env_pkg/compile.do" $env(UVMF_VIP_LIBRARY_HOME)] +eval $cmd + +quietly set cmd [format "vlog -timescale 1ps/1ps +incdir+%s/environment_packages/subsys_env_pkg" $env(UVMF_VIP_LIBRARY_HOME)] +quietly set cmd [format "%s %s/environment_packages/subsys_env_pkg/subsys_env_pkg.sv" $cmd $env(UVMF_VIP_LIBRARY_HOME)] +eval $cmd + + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/environment_packages/subsys_env_pkg/src/subsys_env_configuration.svh b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/environment_packages/subsys_env_pkg/src/subsys_env_configuration.svh new file mode 100644 index 00000000..e837f8ba --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/environment_packages/subsys_env_pkg/src/subsys_env_configuration.svh @@ -0,0 +1,160 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: THis is the configuration for the subsys environment. +// it contains configuration classes for each agent. It also contains +// environment level configuration variables. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +`ifndef SUBSYS_ENV_CONFIGURATION +`define SUBSYS_ENV_CONFIGURATION + +class subsys_env_configuration +extends uvmf_environment_configuration_base; + + `uvm_object_utils( subsys_env_configuration ) + + bit has_scoreboard; + +//Constraints for the configuration variables: + + + covergroup subsys_configuration_cg; + // pragma uvmf custom covergroup begin + option.auto_bin_max=1024; + coverpoint has_scoreboard; + // pragma uvmf custom covergroup end + endgroup + +typedef block_1_env_configuration b1_config_t; +rand b1_config_t b1_config; + +typedef block_2_env_configuration b2_config_t; +rand b2_config_t b2_config; + + + + string b1_interface_names[]; + uvmf_active_passive_t b1_interface_activity[]; + string b2_interface_names[]; + uvmf_active_passive_t b2_interface_activity[]; + + + typedef uvmf_virtual_sequencer_base #(.CONFIG_T(subsys_env_configuration)) subsys_vsqr_t; + subsys_vsqr_t vsqr; + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + +// **************************************************************************** +// FUNCTION : new() +// This function is the standard SystemVerilog constructor. +// This function constructs the configuration object for each agent in the environment. +// + function new( string name = "" ); + super.new( name ); + + b1_config = b1_config_t::type_id::create("b1_config"); + b2_config = b2_config_t::type_id::create("b2_config"); + + + + subsys_configuration_cg=new; + `uvm_warning("COVERAGE_MODEL_REVIEW", "A covergroup has been constructed which may need review because of either generation or re-generation with merging. Please note that configuration variables added as a result of re-generation and merging are not automatically added to the covergroup. Remove this warning after the covergroup has been reviewed.") + + // pragma uvmf custom new begin + // pragma uvmf custom new end + endfunction + +// **************************************************************************** +// FUNCTION : set_vsqr() +// This function is used to assign the vsqr handle. + virtual function void set_vsqr( subsys_vsqr_t vsqr); + this.vsqr = vsqr; + endfunction : set_vsqr + +// **************************************************************************** +// FUNCTION: post_randomize() +// This function is automatically called after the randomize() function +// is executed. +// + function void post_randomize(); + super.post_randomize(); + // pragma uvmf custom post_randomize begin + // pragma uvmf custom post_randomize end + endfunction + +// **************************************************************************** +// FUNCTION: convert2string() +// This function converts all variables in this class to a single string for +// logfile reporting. This function concatenates the convert2string result for +// each agent configuration in this configuration class. +// + virtual function string convert2string(); + // pragma uvmf custom convert2string begin + return { + $sformatf("has_scoreboard:0x%x ",has_scoreboard), + + "\n", b1_config.convert2string, + "\n", b2_config.convert2string + + }; + // pragma uvmf custom convert2string end + endfunction +// **************************************************************************** +// FUNCTION: initialize(); +// This function configures each interface agents configuration class. The +// sim level determines the active/passive state of the agent. The environment_path +// identifies the hierarchy down to and including the instantiation name of the +// environment for this configuration class. Each instance of the environment +// has its own configuration class. The string interface names are used by +// the agent configurations to identify the virtual interface handle to pull from +// the uvm_config_db. +// + function void initialize(uvmf_sim_level_t sim_level, + string environment_path, + string interface_names[], + uvm_reg_block register_model = null, + uvmf_active_passive_t interface_activity[] = {} + ); + + super.initialize(sim_level, environment_path, interface_names, register_model, interface_activity); + + // Interface initialization for sub-environments + b1_interface_names = new[4]; + b1_interface_activity = new[4]; + + b1_interface_names = interface_names[0:3]; + b1_interface_activity = interface_activity[0:3]; + b2_interface_names = new[2]; + b2_interface_activity = new[2]; + + b2_interface_names = interface_names[4:5]; + b2_interface_activity = interface_activity[4:5]; + + + + + b1_config.initialize( sim_level, {environment_path,".b1"}, b1_interface_names, null, b1_interface_activity); + b2_config.initialize( sim_level, {environment_path,".b2"}, b2_interface_names, null, b2_interface_activity); + + + + // pragma uvmf custom initialize begin + // pragma uvmf custom initialize end + + endfunction + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end +`endif + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/environment_packages/subsys_env_pkg/src/subsys_env_sequence_base.svh b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/environment_packages/subsys_env_pkg/src/subsys_env_sequence_base.svh new file mode 100644 index 00000000..8dee7a25 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/environment_packages/subsys_env_pkg/src/subsys_env_sequence_base.svh @@ -0,0 +1,82 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This file contains environment level sequences that will +// be reused from block to top level simulations. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +`ifndef SUBSYS_ENV_SEQUENCE_BASE +`define SUBSYS_ENV_SEQUENCE_BASE + +class subsys_env_sequence_base #( + type CONFIG_T + ) extends uvmf_virtual_sequence_base #(.CONFIG_T(CONFIG_T)); + + + `uvm_object_param_utils( subsys_env_sequence_base #( + CONFIG_T + ) ); + + +// This subsys_env_sequence_base contains a handle to a subsys_env_configuration object +// named configuration. This configuration variable contains a handle to each +// sequencer within each agent within this environment and any sub-environments. +// The configuration object handle is automatically assigned in the pre_body in the +// base class of this sequence. The configuration handle is retrieved from the +// virtual sequencer that this sequence is started on. +// Available sequencer handles within the environment configuration: + + // Initiator agent sequencers in subsys_environment: + + // Responder agent sequencers in subsys_environment: + + // Virtual sequencers in sub-environments located in sub-environment configuration + // configuration.b1_config.vsqr + // configuration.b2_config.vsqr + + +typedef block_1_env_sequence_base #( + .CONFIG_T(block_1_env_configuration) + ) + b1_sequence_base_t; +rand b1_sequence_base_t b1_seq; + +typedef block_2_env_sequence_base #( + .CONFIG_T(block_2_env_configuration) + ) + b2_sequence_base_t; +rand b2_sequence_base_t b2_seq; + + + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + function new(string name = "" ); + super.new(name); + + b1_seq = b1_sequence_base_t::type_id::create("b1_seq"); + b2_seq = b2_sequence_base_t::type_id::create("b2_seq"); + + endfunction + + virtual task body(); + + + b1_seq.start(configuration.b1_config.vsqr); + b2_seq.start(configuration.b2_config.vsqr); + + endtask + +endclass +// pragma uvmf custom external begin +// pragma uvmf custom external end + +`endif diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/environment_packages/subsys_env_pkg/src/subsys_env_typedefs.svh b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/environment_packages/subsys_env_pkg/src/subsys_env_typedefs.svh new file mode 100644 index 00000000..9814bd58 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/environment_packages/subsys_env_pkg/src/subsys_env_typedefs.svh @@ -0,0 +1,20 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: +// This file contains defines and typedefs to be compiled for use in +// the environment package. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// + + + // pragma uvmf custom additional begin + // pragma uvmf custom additional end + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/environment_packages/subsys_env_pkg/src/subsys_environment.svh b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/environment_packages/subsys_env_pkg/src/subsys_environment.svh new file mode 100644 index 00000000..2d21197e --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/environment_packages/subsys_env_pkg/src/subsys_environment.svh @@ -0,0 +1,137 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This environment contains all agents, predictors and +// scoreboards required for the block level design. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +`ifndef SUBSYS_ENVIRONMENT +`define SUBSYS_ENVIRONMENT + +class subsys_environment extends uvmf_environment_base #( + .CONFIG_T( subsys_env_configuration + )); + `uvm_component_utils( subsys_environment ) + + typedef block_1_environment b1_t; + b1_t b1; + + typedef block_2_environment b2_t; + b2_t b2; + + + + uvm_analysis_port #(apb_m_transaction) block_1_ap1; + uvm_analysis_port #(axi_m_transaction) block_1_ap2; + uvm_analysis_port #(axi_m_transaction) block_1_ap3; + uvm_analysis_port #(wb_s_transaction) block_2_ap1; + + + + + + typedef subsys_predictor #( + .CONFIG_T(CONFIG_T) + ) sub_pred_t; + sub_pred_t sub_pred; + typedef subsys_scoreboard #( + .CONFIG_T(CONFIG_T) + ) sub_sb_t; + sub_sb_t sub_sb; + + + + + typedef uvmf_virtual_sequencer_base #(.CONFIG_T(subsys_env_configuration)) subsys_vsqr_t; + subsys_vsqr_t vsqr; + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + +// **************************************************************************** +// FUNCTION : new() +// This function is the standard SystemVerilog constructor. +// + function new( string name = "", uvm_component parent = null ); + super.new( name, parent ); + endfunction + +// **************************************************************************** +// FUNCTION: build_phase() +// This function builds all components within this environment. +// + virtual function void build_phase(uvm_phase phase); +// pragma uvmf custom build_phase_pre_super begin +// pragma uvmf custom build_phase_pre_super end + super.build_phase(phase); + b1 = b1_t::type_id::create("b1",this); + b1.set_config(configuration.b1_config); + b2 = b2_t::type_id::create("b2",this); + b2.set_config(configuration.b2_config); + block_1_ap1 = new("block_1_ap1",this); + block_1_ap2 = new("block_1_ap2",this); + block_1_ap3 = new("block_1_ap3",this); + block_2_ap1 = new("block_2_ap1",this); + sub_pred = sub_pred_t::type_id::create("sub_pred",this); + sub_pred.configuration = configuration; + sub_sb = sub_sb_t::type_id::create("sub_sb",this); + sub_sb.configuration = configuration; + + vsqr = subsys_vsqr_t::type_id::create("vsqr", this); + vsqr.set_config(configuration); + configuration.set_vsqr(vsqr); + + // pragma uvmf custom build_phase begin + // pragma uvmf custom build_phase end + endfunction + +// **************************************************************************** +// FUNCTION: connect_phase() +// This function makes all connections within this environment. Connections +// typically inclue agent to predictor, predictor to scoreboard and scoreboard +// to agent. +// + virtual function void connect_phase(uvm_phase phase); +// pragma uvmf custom connect_phase_pre_super begin +// pragma uvmf custom connect_phase_pre_super end + super.connect_phase(phase); + b1.apb_master_ap.connect(sub_pred.subsys_apb_ae); + b1.axi_master1_ap.connect(sub_pred.subsys_axi_1_ae); + b1.axi_master2_ap.connect(sub_pred.subsys_axi_2_ae); + sub_pred.subsys_pre_to_sco_ap.connect(sub_sb.subsys_sco_from_pre_ae); + b2.wb_slave_ap.connect(sub_sb.subsys_wb_ae); + b1.apb_master_ap.connect(block_1_ap1); + b1.axi_master1_ap.connect(block_1_ap2); + b1.axi_master2_ap.connect(block_1_ap3); + b2.wb_slave_ap.connect(block_2_ap1); + // pragma uvmf custom reg_model_connect_phase begin + // pragma uvmf custom reg_model_connect_phase end + endfunction + +// **************************************************************************** +// FUNCTION: end_of_simulation_phase() +// This function is executed just prior to executing run_phase. This function +// was added to the environment to sample environment configuration settings +// just before the simulation exits time 0. The configuration structure is +// randomized in the build phase before the environment structure is constructed. +// Configuration variables can be customized after randomization in the build_phase +// of the extended test. +// If a sequence modifies values in the configuration structure then the sequence is +// responsible for sampling the covergroup in the configuration if required. +// + virtual function void start_of_simulation_phase(uvm_phase phase); + configuration.subsys_configuration_cg.sample(); + endfunction + +endclass +// pragma uvmf custom external begin +// pragma uvmf custom external end + +`endif diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/environment_packages/subsys_env_pkg/src/subsys_predictor.svh b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/environment_packages/subsys_env_pkg/src/subsys_predictor.svh new file mode 100644 index 00000000..c7ccbc25 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/environment_packages/subsys_env_pkg/src/subsys_predictor.svh @@ -0,0 +1,179 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +// +//---------------------------------------------------------------------- +// +// DESCRIPTION: This analysis component contains analysis_exports for receiving +// data and analysis_ports for sending data. +// +// This analysis component has the following analysis_exports that receive the +// listed transaction type. +// +// subsys_apb_ae receives transactions of type apb_m_transaction +// subsys_axi_1_ae receives transactions of type axi_m_transaction +// subsys_axi_2_ae receives transactions of type axi_m_transaction +// +// This analysis component has the following analysis_ports that can broadcast +// the listed transaction type. +// +// subsys_pre_to_sco_ap broadcasts transactions of type wb_s_transaction +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +`ifndef SUBSYS_PREDICTOR +`define SUBSYS_PREDICTOR + +class subsys_predictor #( + type CONFIG_T, + type BASE_T = uvm_component + ) extends BASE_T; + + // Factory registration of this class + `uvm_component_param_utils( subsys_predictor #( + CONFIG_T, + BASE_T + )) + + + // Instantiate a handle to the configuration of the environment in which this component resides + CONFIG_T configuration; + + + // Instantiate the analysis exports + uvm_analysis_imp_subsys_apb_ae #(apb_m_transaction, subsys_predictor #( + .CONFIG_T(CONFIG_T), + .BASE_T(BASE_T) + )) subsys_apb_ae; + uvm_analysis_imp_subsys_axi_1_ae #(axi_m_transaction, subsys_predictor #( + .CONFIG_T(CONFIG_T), + .BASE_T(BASE_T) + )) subsys_axi_1_ae; + uvm_analysis_imp_subsys_axi_2_ae #(axi_m_transaction, subsys_predictor #( + .CONFIG_T(CONFIG_T), + .BASE_T(BASE_T) + )) subsys_axi_2_ae; + + + // Instantiate the analysis ports + uvm_analysis_port #(wb_s_transaction) subsys_pre_to_sco_ap; + + + // Transaction variable for predicted values to be sent out subsys_pre_to_sco_ap + // Once a transaction is sent through an analysis_port, another transaction should + // be constructed for the next predicted transaction. + typedef wb_s_transaction subsys_pre_to_sco_ap_output_transaction_t; + subsys_pre_to_sco_ap_output_transaction_t subsys_pre_to_sco_ap_output_transaction; + // Code for sending output transaction out through subsys_pre_to_sco_ap + // subsys_pre_to_sco_ap.write(subsys_pre_to_sco_ap_output_transaction); + + // Define transaction handles for debug visibility + apb_m_transaction subsys_apb_ae_debug; + axi_m_transaction subsys_axi_1_ae_debug; + axi_m_transaction subsys_axi_2_ae_debug; + + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + // FUNCTION: new + function new(string name, uvm_component parent); + super.new(name,parent); + `uvm_warning("PREDICTOR_REVIEW", "This predictor has been created either through generation or re-generation with merging. Remove this warning after the predictor has been reviewed.") + // pragma uvmf custom new begin + // pragma uvmf custom new end + endfunction + + // FUNCTION: build_phase + virtual function void build_phase (uvm_phase phase); + + subsys_apb_ae = new("subsys_apb_ae", this); + subsys_axi_1_ae = new("subsys_axi_1_ae", this); + subsys_axi_2_ae = new("subsys_axi_2_ae", this); + subsys_pre_to_sco_ap =new("subsys_pre_to_sco_ap", this ); + // pragma uvmf custom build_phase begin + // pragma uvmf custom build_phase end + endfunction + + // FUNCTION: write_subsys_apb_ae + // Transactions received through subsys_apb_ae initiate the execution of this function. + // This function performs prediction of DUT output values based on DUT input, configuration and state + virtual function void write_subsys_apb_ae(apb_m_transaction t); + // pragma uvmf custom subsys_apb_ae_predictor begin + subsys_apb_ae_debug = t; + `uvm_info("PRED", "Transaction Received through subsys_apb_ae", UVM_MEDIUM) + `uvm_info("PRED", {" Data: ",t.convert2string()}, UVM_FULL) + // Construct one of each output transaction type. + subsys_pre_to_sco_ap_output_transaction = subsys_pre_to_sco_ap_output_transaction_t::type_id::create("subsys_pre_to_sco_ap_output_transaction"); + // UVMF_CHANGE_ME: Implement predictor model here. + `uvm_info("UNIMPLEMENTED_PREDICTOR_MODEL", "******************************************************************************************************",UVM_NONE) + `uvm_info("UNIMPLEMENTED_PREDICTOR_MODEL", "UVMF_CHANGE_ME: The subsys_predictor::write_subsys_apb_ae function needs to be completed with DUT prediction model",UVM_NONE) + `uvm_info("UNIMPLEMENTED_PREDICTOR_MODEL", "******************************************************************************************************",UVM_NONE) + + // Code for sending output transaction out through subsys_pre_to_sco_ap + // Please note that each broadcasted transaction should be a different object than previously + // broadcasted transactions. Creation of a different object is done by constructing the transaction + // using either new() or create(). Broadcasting a transaction object more than once to either the + // same subscriber or multiple subscribers will result in unexpected and incorrect behavior. + subsys_pre_to_sco_ap.write(subsys_pre_to_sco_ap_output_transaction); + // pragma uvmf custom subsys_apb_ae_predictor end + endfunction + + // FUNCTION: write_subsys_axi_1_ae + // Transactions received through subsys_axi_1_ae initiate the execution of this function. + // This function performs prediction of DUT output values based on DUT input, configuration and state + virtual function void write_subsys_axi_1_ae(axi_m_transaction t); + // pragma uvmf custom subsys_axi_1_ae_predictor begin + subsys_axi_1_ae_debug = t; + `uvm_info("PRED", "Transaction Received through subsys_axi_1_ae", UVM_MEDIUM) + `uvm_info("PRED", {" Data: ",t.convert2string()}, UVM_FULL) + // Construct one of each output transaction type. + subsys_pre_to_sco_ap_output_transaction = subsys_pre_to_sco_ap_output_transaction_t::type_id::create("subsys_pre_to_sco_ap_output_transaction"); + // UVMF_CHANGE_ME: Implement predictor model here. + `uvm_info("UNIMPLEMENTED_PREDICTOR_MODEL", "******************************************************************************************************",UVM_NONE) + `uvm_info("UNIMPLEMENTED_PREDICTOR_MODEL", "UVMF_CHANGE_ME: The subsys_predictor::write_subsys_axi_1_ae function needs to be completed with DUT prediction model",UVM_NONE) + `uvm_info("UNIMPLEMENTED_PREDICTOR_MODEL", "******************************************************************************************************",UVM_NONE) + + // Code for sending output transaction out through subsys_pre_to_sco_ap + // Please note that each broadcasted transaction should be a different object than previously + // broadcasted transactions. Creation of a different object is done by constructing the transaction + // using either new() or create(). Broadcasting a transaction object more than once to either the + // same subscriber or multiple subscribers will result in unexpected and incorrect behavior. + subsys_pre_to_sco_ap.write(subsys_pre_to_sco_ap_output_transaction); + // pragma uvmf custom subsys_axi_1_ae_predictor end + endfunction + + // FUNCTION: write_subsys_axi_2_ae + // Transactions received through subsys_axi_2_ae initiate the execution of this function. + // This function performs prediction of DUT output values based on DUT input, configuration and state + virtual function void write_subsys_axi_2_ae(axi_m_transaction t); + // pragma uvmf custom subsys_axi_2_ae_predictor begin + subsys_axi_2_ae_debug = t; + `uvm_info("PRED", "Transaction Received through subsys_axi_2_ae", UVM_MEDIUM) + `uvm_info("PRED", {" Data: ",t.convert2string()}, UVM_FULL) + // Construct one of each output transaction type. + subsys_pre_to_sco_ap_output_transaction = subsys_pre_to_sco_ap_output_transaction_t::type_id::create("subsys_pre_to_sco_ap_output_transaction"); + // UVMF_CHANGE_ME: Implement predictor model here. + `uvm_info("UNIMPLEMENTED_PREDICTOR_MODEL", "******************************************************************************************************",UVM_NONE) + `uvm_info("UNIMPLEMENTED_PREDICTOR_MODEL", "UVMF_CHANGE_ME: The subsys_predictor::write_subsys_axi_2_ae function needs to be completed with DUT prediction model",UVM_NONE) + `uvm_info("UNIMPLEMENTED_PREDICTOR_MODEL", "******************************************************************************************************",UVM_NONE) + + // Code for sending output transaction out through subsys_pre_to_sco_ap + // Please note that each broadcasted transaction should be a different object than previously + // broadcasted transactions. Creation of a different object is done by constructing the transaction + // using either new() or create(). Broadcasting a transaction object more than once to either the + // same subscriber or multiple subscribers will result in unexpected and incorrect behavior. + subsys_pre_to_sco_ap.write(subsys_pre_to_sco_ap_output_transaction); + // pragma uvmf custom subsys_axi_2_ae_predictor end + endfunction + + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + +`endif diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/environment_packages/subsys_env_pkg/src/subsys_scoreboard.svh b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/environment_packages/subsys_env_pkg/src/subsys_scoreboard.svh new file mode 100644 index 00000000..ef78c471 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/environment_packages/subsys_env_pkg/src/subsys_scoreboard.svh @@ -0,0 +1,132 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This analysis component contains analysis_exports for receiving +// data and analysis_ports for sending data. +// +// This analysis component has the following analysis_exports that receive the +// listed transaction type. +// +// subsys_sco_from_pre_ae receives transactions of type wb_s_transaction +// subsys_wb_ae receives transactions of type wb_s_transaction +// +// This analysis component has the following analysis_ports that can broadcast +// the listed transaction type. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +`ifndef SUBSYS_SCOREBOARD +`define SUBSYS_SCOREBOARD + +class subsys_scoreboard #( + type CONFIG_T, + type BASE_T = uvm_component + ) extends BASE_T; + + // Factory registration of this class + `uvm_component_param_utils( subsys_scoreboard #( + CONFIG_T, + BASE_T + )) + + + // Instantiate a handle to the configuration of the environment in which this component resides + CONFIG_T configuration; + + + // Instantiate the analysis exports + uvm_analysis_imp_subsys_sco_from_pre_ae #(wb_s_transaction, subsys_scoreboard #( + .CONFIG_T(CONFIG_T), + .BASE_T(BASE_T) + )) subsys_sco_from_pre_ae; + uvm_analysis_imp_subsys_wb_ae #(wb_s_transaction, subsys_scoreboard #( + .CONFIG_T(CONFIG_T), + .BASE_T(BASE_T) + )) subsys_wb_ae; + + + + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + // FUNCTION: new + function new(string name, uvm_component parent); + super.new(name,parent); + // pragma uvmf custom new begin + // pragma uvmf custom new end + endfunction + + // FUNCTION: build_phase + virtual function void build_phase (uvm_phase phase); + + subsys_sco_from_pre_ae = new("subsys_sco_from_pre_ae", this); + subsys_wb_ae = new("subsys_wb_ae", this); + // pragma uvmf custom build_phase begin + // pragma uvmf custom build_phase end + endfunction + + // FUNCTION: write_subsys_sco_from_pre_ae + // Transactions received through subsys_sco_from_pre_ae initiate the execution of this function. + // This function performs prediction of DUT output values based on DUT input, configuration and state + virtual function void write_subsys_sco_from_pre_ae(wb_s_transaction t); + // pragma uvmf custom subsys_sco_from_pre_ae_scoreboard begin + `uvm_info("PRED", "Transaction Received through subsys_sco_from_pre_ae", UVM_MEDIUM) + `uvm_info("PRED", {" Data: ",t.convert2string()}, UVM_FULL) + // UVMF_CHANGE_ME: Implement custom scoreboard here. + `uvm_info("UNIMPLEMENTED_CUSTOM_SCOREBOARD", "******************************************************************************************************",UVM_NONE) + `uvm_info("UNIMPLEMENTED_CUSTOM_SCOREBOARD", "UVMF_CHANGE_ME: The subsys_scoreboard::write_subsys_sco_from_pre_ae function needs to be completed with custom scoreboard functionality",UVM_NONE) + `uvm_info("UNIMPLEMENTED_CUSTOM_SCOREBOARD", "******************************************************************************************************",UVM_NONE) + + // pragma uvmf custom subsys_sco_from_pre_ae_scoreboard end + endfunction + + // FUNCTION: write_subsys_wb_ae + // Transactions received through subsys_wb_ae initiate the execution of this function. + // This function performs prediction of DUT output values based on DUT input, configuration and state + virtual function void write_subsys_wb_ae(wb_s_transaction t); + // pragma uvmf custom subsys_wb_ae_scoreboard begin + `uvm_info("PRED", "Transaction Received through subsys_wb_ae", UVM_MEDIUM) + `uvm_info("PRED", {" Data: ",t.convert2string()}, UVM_FULL) + // UVMF_CHANGE_ME: Implement custom scoreboard here. + `uvm_info("UNIMPLEMENTED_CUSTOM_SCOREBOARD", "******************************************************************************************************",UVM_NONE) + `uvm_info("UNIMPLEMENTED_CUSTOM_SCOREBOARD", "UVMF_CHANGE_ME: The subsys_scoreboard::write_subsys_wb_ae function needs to be completed with custom scoreboard functionality",UVM_NONE) + `uvm_info("UNIMPLEMENTED_CUSTOM_SCOREBOARD", "******************************************************************************************************",UVM_NONE) + + // pragma uvmf custom subsys_wb_ae_scoreboard end + endfunction + + + + // FUNCTION: extract_phase + virtual function void extract_phase(uvm_phase phase); +// pragma uvmf custom extract_phase begin + super.extract_phase(phase); +// pragma uvmf custom extract_phase end + endfunction + + // FUNCTION: check_phase + virtual function void check_phase(uvm_phase phase); +// pragma uvmf custom check_phase begin + super.check_phase(phase); +// pragma uvmf custom check_phase end + endfunction + + // FUNCTION: report_phase + virtual function void report_phase(uvm_phase phase); +// pragma uvmf custom report_phase begin + super.report_phase(phase); +// pragma uvmf custom report_phase end + endfunction + +endclass +// pragma uvmf custom external begin +// pragma uvmf custom external end + +`endif diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/environment_packages/subsys_env_pkg/subsys_env_pkg.compile b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/environment_packages/subsys_env_pkg/subsys_env_pkg.compile new file mode 100644 index 00000000..b651f0c9 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/environment_packages/subsys_env_pkg/subsys_env_pkg.compile @@ -0,0 +1,8 @@ +needs: + - $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg.compile + - ../block_1_env_pkg/block_1_env_pkg.compile + - ../block_2_env_pkg/block_2_env_pkg.compile + +src: + - subsys_env_pkg.sv + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/environment_packages/subsys_env_pkg/subsys_env_pkg.sv b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/environment_packages/subsys_env_pkg/subsys_env_pkg.sv new file mode 100644 index 00000000..29b15242 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/environment_packages/subsys_env_pkg/subsys_env_pkg.sv @@ -0,0 +1,62 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// PACKAGE: This file defines all of the files contained in the +// environment package that will run on the host simulator. +// +// CONTAINS: +// - +// - +// - +// - +// - +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +package subsys_env_pkg; + + import uvm_pkg::*; + `include "uvm_macros.svh" + import uvmf_base_pkg::*; + import apb_m_pkg::*; + import axi_m_pkg::*; + import wb_s_pkg::*; + import block_1_env_pkg::*; + import block_2_env_pkg::*; + + `uvm_analysis_imp_decl(_subsys_apb_ae) + `uvm_analysis_imp_decl(_subsys_axi_1_ae) + `uvm_analysis_imp_decl(_subsys_axi_2_ae) + `uvm_analysis_imp_decl(_subsys_sco_from_pre_ae) + `uvm_analysis_imp_decl(_subsys_wb_ae) + + // pragma uvmf custom package_imports_additional begin + // pragma uvmf custom package_imports_additional end + + // Parameters defined as HVL parameters + + `include "src/subsys_env_typedefs.svh" + `include "src/subsys_env_configuration.svh" + `include "src/subsys_predictor.svh" + `include "src/subsys_scoreboard.svh" + `include "src/subsys_environment.svh" + `include "src/subsys_env_sequence_base.svh" + + // pragma uvmf custom package_item_additional begin + // UVMF_CHANGE_ME : When adding new environment level sequences to the src directory + // be sure to add the sequence file here so that it will be + // compiled as part of the environment package. Be sure to place + // the new sequence after any base sequence of the new sequence. + // pragma uvmf custom package_item_additional end + +endpackage + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/environment_packages/subsys_env_pkg/subsys_env_pkg.vinfo b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/environment_packages/subsys_env_pkg/subsys_env_pkg.vinfo new file mode 100644 index 00000000..e98bf2e3 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/environment_packages/subsys_env_pkg/subsys_env_pkg.vinfo @@ -0,0 +1,5 @@ +@use $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg.vinfo +@use $UVMF_VIP_LIBRARY_HOME/environment_packages/b1_pkg/b1_pkg.vinfo +@use $UVMF_VIP_LIBRARY_HOME/environment_packages/b2_pkg/b2_pkg.vinfo ++incdir+@vinfodir +subsys_env_pkg.sv diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/environment_packages/subsys_env_pkg/subsys_env_pkg_sve.F b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/environment_packages/subsys_env_pkg/subsys_env_pkg_sve.F new file mode 100644 index 00000000..26dd5cf2 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/environment_packages/subsys_env_pkg/subsys_env_pkg_sve.F @@ -0,0 +1,14 @@ + +// UVM ++incdir+${UVM_HOME}/src +${UVM_HOME}/src/uvm_pkg.sv + +// Common UVMF files +-f ${UVMF_HOME}/common/common_sve.f + +// Sub-Environments +-F ${UVMF_VIP_LIBRARY_HOME}/environment_packages/block_1_env_pkg/block_1_env_pkg_sve.F +-F ${UVMF_VIP_LIBRARY_HOME}/environment_packages/block_2_env_pkg/block_2_env_pkg_sve.F + ++incdir+. +./subsys_env_pkg.sv diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/environment_packages/subsys_env_pkg/yaml/subsys_environment.yaml b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/environment_packages/subsys_env_pkg/yaml/subsys_environment.yaml new file mode 100644 index 00000000..5365c0a3 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/environment_packages/subsys_env_pkg/yaml/subsys_environment.yaml @@ -0,0 +1,65 @@ +uvmf: + environments: + subsys: + agents: [] + analysis_components: + - name: sub_pred + parameters: [] + type: subsys_predictor + - name: sub_sb + parameters: [] + type: subsys_scoreboard + analysis_exports: [] + analysis_ports: + - connected_to: b1.apb_master_ap + name: block_1_ap1 + trans_type: apb_m_transaction + - connected_to: b1.axi_master1_ap + name: block_1_ap2 + trans_type: axi_m_transaction + - connected_to: b1.axi_master2_ap + name: block_1_ap3 + trans_type: axi_m_transaction + - connected_to: b2.wb_slave_ap + name: block_2_ap1 + trans_type: wb_s_transaction + config_constraints: [] + config_vars: + - comment: '' + isrand: 'False' + name: has_scoreboard + type: bit + value: '' + existing_library_component: 'True' + hvl_pkg_parameters: [] + imports: + - name: apb_m_pkg + - name: axi_m_pkg + - name: wb_s_pkg + non_uvmf_components: [] + parameters: [] + qvip_memory_agents: [] + scoreboards: [] + subenvs: + - name: b1 + parameters: [] + type: block_1 + - name: b2 + parameters: [] + type: block_2 + tlm_connections: + - driver: b1.apb_master_ap + receiver: sub_pred.subsys_apb_ae + validate: 'True' + - driver: b1.axi_master1_ap + receiver: sub_pred.subsys_axi_1_ae + validate: 'True' + - driver: b1.axi_master2_ap + receiver: sub_pred.subsys_axi_2_ae + validate: 'True' + - driver: sub_pred.subsys_pre_to_sco_ap + receiver: sub_sb.subsys_sco_from_pre_ae + validate: 'True' + - driver: b2.wb_slave_ap + receiver: sub_sb.subsys_wb_ae + validate: 'True' diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/environment_packages/subsys_env_pkg/yaml/subsys_util_comp_subsys_predictor.yaml b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/environment_packages/subsys_env_pkg/yaml/subsys_util_comp_subsys_predictor.yaml new file mode 100644 index 00000000..7570a2d3 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/environment_packages/subsys_env_pkg/yaml/subsys_util_comp_subsys_predictor.yaml @@ -0,0 +1,15 @@ +uvmf: + util_components: + subsys_predictor: + analysis_exports: + - name: subsys_apb_ae + type: apb_m_transaction + - name: subsys_axi_1_ae + type: axi_m_transaction + - name: subsys_axi_2_ae + type: axi_m_transaction + analysis_ports: + - name: subsys_pre_to_sco_ap + type: wb_s_transaction + existing_library_component: 'True' + type: predictor diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/environment_packages/subsys_env_pkg/yaml/subsys_util_comp_subsys_scoreboard.yaml b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/environment_packages/subsys_env_pkg/yaml/subsys_util_comp_subsys_scoreboard.yaml new file mode 100644 index 00000000..ea3069cd --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/environment_packages/subsys_env_pkg/yaml/subsys_util_comp_subsys_scoreboard.yaml @@ -0,0 +1,10 @@ +uvmf: + util_components: + subsys_scoreboard: + analysis_exports: + - name: subsys_sco_from_pre_ae + type: wb_s_transaction + - name: subsys_wb_ae + type: wb_s_transaction + existing_library_component: 'True' + type: scoreboard diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/environment_packages/system_env_pkg/.project b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/environment_packages/system_env_pkg/.project new file mode 100644 index 00000000..c5328a19 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/environment_packages/system_env_pkg/.project @@ -0,0 +1,32 @@ + + + system_env_pkg + + + + + + org.python.pydev.PyDevBuilder + + + + + net.sf.sveditor.core.SVProjectBuilder + + + + + + net.sf.sveditor.core.SVNature + org.python.pydev.pythonNature + + + + + + UVMF_VIP_LIBRARY_HOME + $%7BPARENT-2-PROJECT_LOC%7D + + + + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/environment_packages/system_env_pkg/.svproject b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/environment_packages/system_env_pkg/.svproject new file mode 100644 index 00000000..2c6c041c --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/environment_packages/system_env_pkg/.svproject @@ -0,0 +1,16 @@ + + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/environment_packages/system_env_pkg/Makefile b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/environment_packages/system_env_pkg/Makefile new file mode 100644 index 00000000..25f0dbbf --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/environment_packages/system_env_pkg/Makefile @@ -0,0 +1,58 @@ +# system environment packages source and make target + +# pragma uvmf custom additional begin +# pragma uvmf custom additional end + +# Include all requisite sub-environment package targets for this bench +include $(UVMF_VIP_LIBRARY_HOME)/environment_packages/subsys_env_pkg/Makefile +include $(UVMF_VIP_LIBRARY_HOME)/environment_packages/block_3_env_pkg/Makefile + +system_ENV_PKG =\ + $(UVMF_VIP_LIBRARY_HOME)/environment_packages/system_env_pkg/system_env_pkg.sv + +COMP_system_PKG_TGT_0 = q_comp_system_env_pkg +COMP_system_PKG_TGT_1 = v_comp_system_env_pkg +COMP_system_PKG_TGT = $(COMP_system_PKG_TGT_$(USE_VELOCE)) + +comp_system_env_pkg: $(COMP_system_PKG_TGT) + +q_comp_system_env_pkg: comp_subsys_env_pkg comp_block_3_env_pkg + $(HVL_COMP_CMD) +incdir+$(UVMF_VIP_LIBRARY_HOME)/environment_packages/system_env_pkg $(system_ENV_PKG) + +v_comp_system_env_pkg: q_comp_system_env_pkg + $(VELANALYZE_HVL_CMD) +incdir+$(UVMF_VIP_LIBRARY_HOME)/environment_packages/system_env_pkg $(system_ENV_PKG) + + + +ifeq ($(MTI_VCO_MODE),64) + GCC_COMP_ARCH = -m64 +else + GCC_COMP_ARCH = -m32 +endif + +export system_ENV_DPI_SRC ?= $(UVMF_VIP_LIBRARY_HOME)/environment_packages/system_env_pkg/dpi + +C_FILE_COMPILE_LIST_system_env_pkg = \ + +O_FILE_COMPILE_LIST_system_env_pkg = $(notdir $(C_FILE_COMPILE_LIST_system_env_pkg:.c=.o)) + +GCC_COMP_ARGS_system_env_pkg += -I$(system_ENV_DPI_SRC) \ + -fPIC + +GCC_COMP_ARGS_system_env_pkg += $(system_ENV_GCC_COMP_ARGUMENTS) + +GCC_LINK_ARGS_system_env_pkg += \ + \ + -o .so + +comp_system_env_pkg_c_files: + @echo "--------------------------------" + @echo "Compiling Environment C source" + @echo "--------------------------------" + gcc $(GCC_COMP_ARCH) $(GCC_COMP_ARGS_system_env_pkg) $(C_FILE_COMPILE_LIST_system_env_pkg) + @echo "--------------------------------" + @echo "Linking Environment C objects into a shared object" + @echo "--------------------------------" + gcc $(GCC_COMP_ARCH) $(GCC_LINK_ARGS_system_env_pkg) $(O_FILE_COMPILE_LIST_system_env_pkg) + @echo "--------------------------------" + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/environment_packages/system_env_pkg/compile.do b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/environment_packages/system_env_pkg/compile.do new file mode 100644 index 00000000..05f00889 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/environment_packages/system_env_pkg/compile.do @@ -0,0 +1,18 @@ +# Tcl do file for compile of system interface + +# pragma uvmf custom additional begin +# pragma uvmf custom additional end + + +# Include build for sub-environment subsys_env_pkg +quietly set cmd [format "source %s/environment_packages/subsys_env_pkg/compile.do" $env(UVMF_VIP_LIBRARY_HOME)] +eval $cmd +# Include build for sub-environment block_3_env_pkg +quietly set cmd [format "source %s/environment_packages/block_3_env_pkg/compile.do" $env(UVMF_VIP_LIBRARY_HOME)] +eval $cmd + +quietly set cmd [format "vlog -timescale 1ps/1ps +incdir+%s/environment_packages/system_env_pkg" $env(UVMF_VIP_LIBRARY_HOME)] +quietly set cmd [format "%s %s/environment_packages/system_env_pkg/system_env_pkg.sv" $cmd $env(UVMF_VIP_LIBRARY_HOME)] +eval $cmd + + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/environment_packages/system_env_pkg/src/sys_predictor.svh b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/environment_packages/system_env_pkg/src/sys_predictor.svh new file mode 100644 index 00000000..7375b47e --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/environment_packages/system_env_pkg/src/sys_predictor.svh @@ -0,0 +1,179 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +// +//---------------------------------------------------------------------- +// +// DESCRIPTION: This analysis component contains analysis_exports for receiving +// data and analysis_ports for sending data. +// +// This analysis component has the following analysis_exports that receive the +// listed transaction type. +// +// sys_apb_ae receives transactions of type apb_m_transaction +// sys_axi_2_ae receives transactions of type axi_m_transaction +// sys_axi_1_ae receives transactions of type axi_m_transaction +// +// This analysis component has the following analysis_ports that can broadcast +// the listed transaction type. +// +// sys_pre_to_sco_ap broadcasts transactions of type axi_s_transaction +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +`ifndef SYS_PREDICTOR +`define SYS_PREDICTOR + +class sys_predictor #( + type CONFIG_T, + type BASE_T = uvm_component + ) extends BASE_T; + + // Factory registration of this class + `uvm_component_param_utils( sys_predictor #( + CONFIG_T, + BASE_T + )) + + + // Instantiate a handle to the configuration of the environment in which this component resides + CONFIG_T configuration; + + + // Instantiate the analysis exports + uvm_analysis_imp_sys_apb_ae #(apb_m_transaction, sys_predictor #( + .CONFIG_T(CONFIG_T), + .BASE_T(BASE_T) + )) sys_apb_ae; + uvm_analysis_imp_sys_axi_2_ae #(axi_m_transaction, sys_predictor #( + .CONFIG_T(CONFIG_T), + .BASE_T(BASE_T) + )) sys_axi_2_ae; + uvm_analysis_imp_sys_axi_1_ae #(axi_m_transaction, sys_predictor #( + .CONFIG_T(CONFIG_T), + .BASE_T(BASE_T) + )) sys_axi_1_ae; + + + // Instantiate the analysis ports + uvm_analysis_port #(axi_s_transaction) sys_pre_to_sco_ap; + + + // Transaction variable for predicted values to be sent out sys_pre_to_sco_ap + // Once a transaction is sent through an analysis_port, another transaction should + // be constructed for the next predicted transaction. + typedef axi_s_transaction sys_pre_to_sco_ap_output_transaction_t; + sys_pre_to_sco_ap_output_transaction_t sys_pre_to_sco_ap_output_transaction; + // Code for sending output transaction out through sys_pre_to_sco_ap + // sys_pre_to_sco_ap.write(sys_pre_to_sco_ap_output_transaction); + + // Define transaction handles for debug visibility + apb_m_transaction sys_apb_ae_debug; + axi_m_transaction sys_axi_2_ae_debug; + axi_m_transaction sys_axi_1_ae_debug; + + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + // FUNCTION: new + function new(string name, uvm_component parent); + super.new(name,parent); + `uvm_warning("PREDICTOR_REVIEW", "This predictor has been created either through generation or re-generation with merging. Remove this warning after the predictor has been reviewed.") + // pragma uvmf custom new begin + // pragma uvmf custom new end + endfunction + + // FUNCTION: build_phase + virtual function void build_phase (uvm_phase phase); + + sys_apb_ae = new("sys_apb_ae", this); + sys_axi_2_ae = new("sys_axi_2_ae", this); + sys_axi_1_ae = new("sys_axi_1_ae", this); + sys_pre_to_sco_ap =new("sys_pre_to_sco_ap", this ); + // pragma uvmf custom build_phase begin + // pragma uvmf custom build_phase end + endfunction + + // FUNCTION: write_sys_apb_ae + // Transactions received through sys_apb_ae initiate the execution of this function. + // This function performs prediction of DUT output values based on DUT input, configuration and state + virtual function void write_sys_apb_ae(apb_m_transaction t); + // pragma uvmf custom sys_apb_ae_predictor begin + sys_apb_ae_debug = t; + `uvm_info("PRED", "Transaction Received through sys_apb_ae", UVM_MEDIUM) + `uvm_info("PRED", {" Data: ",t.convert2string()}, UVM_FULL) + // Construct one of each output transaction type. + sys_pre_to_sco_ap_output_transaction = sys_pre_to_sco_ap_output_transaction_t::type_id::create("sys_pre_to_sco_ap_output_transaction"); + // UVMF_CHANGE_ME: Implement predictor model here. + `uvm_info("UNIMPLEMENTED_PREDICTOR_MODEL", "******************************************************************************************************",UVM_NONE) + `uvm_info("UNIMPLEMENTED_PREDICTOR_MODEL", "UVMF_CHANGE_ME: The sys_predictor::write_sys_apb_ae function needs to be completed with DUT prediction model",UVM_NONE) + `uvm_info("UNIMPLEMENTED_PREDICTOR_MODEL", "******************************************************************************************************",UVM_NONE) + + // Code for sending output transaction out through sys_pre_to_sco_ap + // Please note that each broadcasted transaction should be a different object than previously + // broadcasted transactions. Creation of a different object is done by constructing the transaction + // using either new() or create(). Broadcasting a transaction object more than once to either the + // same subscriber or multiple subscribers will result in unexpected and incorrect behavior. + sys_pre_to_sco_ap.write(sys_pre_to_sco_ap_output_transaction); + // pragma uvmf custom sys_apb_ae_predictor end + endfunction + + // FUNCTION: write_sys_axi_2_ae + // Transactions received through sys_axi_2_ae initiate the execution of this function. + // This function performs prediction of DUT output values based on DUT input, configuration and state + virtual function void write_sys_axi_2_ae(axi_m_transaction t); + // pragma uvmf custom sys_axi_2_ae_predictor begin + sys_axi_2_ae_debug = t; + `uvm_info("PRED", "Transaction Received through sys_axi_2_ae", UVM_MEDIUM) + `uvm_info("PRED", {" Data: ",t.convert2string()}, UVM_FULL) + // Construct one of each output transaction type. + sys_pre_to_sco_ap_output_transaction = sys_pre_to_sco_ap_output_transaction_t::type_id::create("sys_pre_to_sco_ap_output_transaction"); + // UVMF_CHANGE_ME: Implement predictor model here. + `uvm_info("UNIMPLEMENTED_PREDICTOR_MODEL", "******************************************************************************************************",UVM_NONE) + `uvm_info("UNIMPLEMENTED_PREDICTOR_MODEL", "UVMF_CHANGE_ME: The sys_predictor::write_sys_axi_2_ae function needs to be completed with DUT prediction model",UVM_NONE) + `uvm_info("UNIMPLEMENTED_PREDICTOR_MODEL", "******************************************************************************************************",UVM_NONE) + + // Code for sending output transaction out through sys_pre_to_sco_ap + // Please note that each broadcasted transaction should be a different object than previously + // broadcasted transactions. Creation of a different object is done by constructing the transaction + // using either new() or create(). Broadcasting a transaction object more than once to either the + // same subscriber or multiple subscribers will result in unexpected and incorrect behavior. + sys_pre_to_sco_ap.write(sys_pre_to_sco_ap_output_transaction); + // pragma uvmf custom sys_axi_2_ae_predictor end + endfunction + + // FUNCTION: write_sys_axi_1_ae + // Transactions received through sys_axi_1_ae initiate the execution of this function. + // This function performs prediction of DUT output values based on DUT input, configuration and state + virtual function void write_sys_axi_1_ae(axi_m_transaction t); + // pragma uvmf custom sys_axi_1_ae_predictor begin + sys_axi_1_ae_debug = t; + `uvm_info("PRED", "Transaction Received through sys_axi_1_ae", UVM_MEDIUM) + `uvm_info("PRED", {" Data: ",t.convert2string()}, UVM_FULL) + // Construct one of each output transaction type. + sys_pre_to_sco_ap_output_transaction = sys_pre_to_sco_ap_output_transaction_t::type_id::create("sys_pre_to_sco_ap_output_transaction"); + // UVMF_CHANGE_ME: Implement predictor model here. + `uvm_info("UNIMPLEMENTED_PREDICTOR_MODEL", "******************************************************************************************************",UVM_NONE) + `uvm_info("UNIMPLEMENTED_PREDICTOR_MODEL", "UVMF_CHANGE_ME: The sys_predictor::write_sys_axi_1_ae function needs to be completed with DUT prediction model",UVM_NONE) + `uvm_info("UNIMPLEMENTED_PREDICTOR_MODEL", "******************************************************************************************************",UVM_NONE) + + // Code for sending output transaction out through sys_pre_to_sco_ap + // Please note that each broadcasted transaction should be a different object than previously + // broadcasted transactions. Creation of a different object is done by constructing the transaction + // using either new() or create(). Broadcasting a transaction object more than once to either the + // same subscriber or multiple subscribers will result in unexpected and incorrect behavior. + sys_pre_to_sco_ap.write(sys_pre_to_sco_ap_output_transaction); + // pragma uvmf custom sys_axi_1_ae_predictor end + endfunction + + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + +`endif diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/environment_packages/system_env_pkg/src/sys_scoreboard.svh b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/environment_packages/system_env_pkg/src/sys_scoreboard.svh new file mode 100644 index 00000000..e09ecb62 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/environment_packages/system_env_pkg/src/sys_scoreboard.svh @@ -0,0 +1,132 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This analysis component contains analysis_exports for receiving +// data and analysis_ports for sending data. +// +// This analysis component has the following analysis_exports that receive the +// listed transaction type. +// +// sys_axi_ae receives transactions of type axi_s_transaction +// sys_sco_from_pre_ae receives transactions of type axi_s_transaction +// +// This analysis component has the following analysis_ports that can broadcast +// the listed transaction type. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +`ifndef SYS_SCOREBOARD +`define SYS_SCOREBOARD + +class sys_scoreboard #( + type CONFIG_T, + type BASE_T = uvm_component + ) extends BASE_T; + + // Factory registration of this class + `uvm_component_param_utils( sys_scoreboard #( + CONFIG_T, + BASE_T + )) + + + // Instantiate a handle to the configuration of the environment in which this component resides + CONFIG_T configuration; + + + // Instantiate the analysis exports + uvm_analysis_imp_sys_axi_ae #(axi_s_transaction, sys_scoreboard #( + .CONFIG_T(CONFIG_T), + .BASE_T(BASE_T) + )) sys_axi_ae; + uvm_analysis_imp_sys_sco_from_pre_ae #(axi_s_transaction, sys_scoreboard #( + .CONFIG_T(CONFIG_T), + .BASE_T(BASE_T) + )) sys_sco_from_pre_ae; + + + + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + // FUNCTION: new + function new(string name, uvm_component parent); + super.new(name,parent); + // pragma uvmf custom new begin + // pragma uvmf custom new end + endfunction + + // FUNCTION: build_phase + virtual function void build_phase (uvm_phase phase); + + sys_axi_ae = new("sys_axi_ae", this); + sys_sco_from_pre_ae = new("sys_sco_from_pre_ae", this); + // pragma uvmf custom build_phase begin + // pragma uvmf custom build_phase end + endfunction + + // FUNCTION: write_sys_axi_ae + // Transactions received through sys_axi_ae initiate the execution of this function. + // This function performs prediction of DUT output values based on DUT input, configuration and state + virtual function void write_sys_axi_ae(axi_s_transaction t); + // pragma uvmf custom sys_axi_ae_scoreboard begin + `uvm_info("PRED", "Transaction Received through sys_axi_ae", UVM_MEDIUM) + `uvm_info("PRED", {" Data: ",t.convert2string()}, UVM_FULL) + // UVMF_CHANGE_ME: Implement custom scoreboard here. + `uvm_info("UNIMPLEMENTED_CUSTOM_SCOREBOARD", "******************************************************************************************************",UVM_NONE) + `uvm_info("UNIMPLEMENTED_CUSTOM_SCOREBOARD", "UVMF_CHANGE_ME: The sys_scoreboard::write_sys_axi_ae function needs to be completed with custom scoreboard functionality",UVM_NONE) + `uvm_info("UNIMPLEMENTED_CUSTOM_SCOREBOARD", "******************************************************************************************************",UVM_NONE) + + // pragma uvmf custom sys_axi_ae_scoreboard end + endfunction + + // FUNCTION: write_sys_sco_from_pre_ae + // Transactions received through sys_sco_from_pre_ae initiate the execution of this function. + // This function performs prediction of DUT output values based on DUT input, configuration and state + virtual function void write_sys_sco_from_pre_ae(axi_s_transaction t); + // pragma uvmf custom sys_sco_from_pre_ae_scoreboard begin + `uvm_info("PRED", "Transaction Received through sys_sco_from_pre_ae", UVM_MEDIUM) + `uvm_info("PRED", {" Data: ",t.convert2string()}, UVM_FULL) + // UVMF_CHANGE_ME: Implement custom scoreboard here. + `uvm_info("UNIMPLEMENTED_CUSTOM_SCOREBOARD", "******************************************************************************************************",UVM_NONE) + `uvm_info("UNIMPLEMENTED_CUSTOM_SCOREBOARD", "UVMF_CHANGE_ME: The sys_scoreboard::write_sys_sco_from_pre_ae function needs to be completed with custom scoreboard functionality",UVM_NONE) + `uvm_info("UNIMPLEMENTED_CUSTOM_SCOREBOARD", "******************************************************************************************************",UVM_NONE) + + // pragma uvmf custom sys_sco_from_pre_ae_scoreboard end + endfunction + + + + // FUNCTION: extract_phase + virtual function void extract_phase(uvm_phase phase); +// pragma uvmf custom extract_phase begin + super.extract_phase(phase); +// pragma uvmf custom extract_phase end + endfunction + + // FUNCTION: check_phase + virtual function void check_phase(uvm_phase phase); +// pragma uvmf custom check_phase begin + super.check_phase(phase); +// pragma uvmf custom check_phase end + endfunction + + // FUNCTION: report_phase + virtual function void report_phase(uvm_phase phase); +// pragma uvmf custom report_phase begin + super.report_phase(phase); +// pragma uvmf custom report_phase end + endfunction + +endclass +// pragma uvmf custom external begin +// pragma uvmf custom external end + +`endif diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/environment_packages/system_env_pkg/src/system_env_configuration.svh b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/environment_packages/system_env_pkg/src/system_env_configuration.svh new file mode 100644 index 00000000..ef03a3bb --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/environment_packages/system_env_pkg/src/system_env_configuration.svh @@ -0,0 +1,160 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: THis is the configuration for the system environment. +// it contains configuration classes for each agent. It also contains +// environment level configuration variables. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +`ifndef SYSTEM_ENV_CONFIGURATION +`define SYSTEM_ENV_CONFIGURATION + +class system_env_configuration +extends uvmf_environment_configuration_base; + + `uvm_object_utils( system_env_configuration ) + + bit has_scoreboard; + +//Constraints for the configuration variables: + + + covergroup system_configuration_cg; + // pragma uvmf custom covergroup begin + option.auto_bin_max=1024; + coverpoint has_scoreboard; + // pragma uvmf custom covergroup end + endgroup + +typedef subsys_env_configuration s1_config_t; +rand s1_config_t s1_config; + +typedef block_3_env_configuration b3_config_t; +rand b3_config_t b3_config; + + + + string s1_interface_names[]; + uvmf_active_passive_t s1_interface_activity[]; + string b3_interface_names[]; + uvmf_active_passive_t b3_interface_activity[]; + + + typedef uvmf_virtual_sequencer_base #(.CONFIG_T(system_env_configuration)) system_vsqr_t; + system_vsqr_t vsqr; + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + +// **************************************************************************** +// FUNCTION : new() +// This function is the standard SystemVerilog constructor. +// This function constructs the configuration object for each agent in the environment. +// + function new( string name = "" ); + super.new( name ); + + s1_config = s1_config_t::type_id::create("s1_config"); + b3_config = b3_config_t::type_id::create("b3_config"); + + + + system_configuration_cg=new; + `uvm_warning("COVERAGE_MODEL_REVIEW", "A covergroup has been constructed which may need review because of either generation or re-generation with merging. Please note that configuration variables added as a result of re-generation and merging are not automatically added to the covergroup. Remove this warning after the covergroup has been reviewed.") + + // pragma uvmf custom new begin + // pragma uvmf custom new end + endfunction + +// **************************************************************************** +// FUNCTION : set_vsqr() +// This function is used to assign the vsqr handle. + virtual function void set_vsqr( system_vsqr_t vsqr); + this.vsqr = vsqr; + endfunction : set_vsqr + +// **************************************************************************** +// FUNCTION: post_randomize() +// This function is automatically called after the randomize() function +// is executed. +// + function void post_randomize(); + super.post_randomize(); + // pragma uvmf custom post_randomize begin + // pragma uvmf custom post_randomize end + endfunction + +// **************************************************************************** +// FUNCTION: convert2string() +// This function converts all variables in this class to a single string for +// logfile reporting. This function concatenates the convert2string result for +// each agent configuration in this configuration class. +// + virtual function string convert2string(); + // pragma uvmf custom convert2string begin + return { + $sformatf("has_scoreboard:0x%x ",has_scoreboard), + + "\n", s1_config.convert2string, + "\n", b3_config.convert2string + + }; + // pragma uvmf custom convert2string end + endfunction +// **************************************************************************** +// FUNCTION: initialize(); +// This function configures each interface agents configuration class. The +// sim level determines the active/passive state of the agent. The environment_path +// identifies the hierarchy down to and including the instantiation name of the +// environment for this configuration class. Each instance of the environment +// has its own configuration class. The string interface names are used by +// the agent configurations to identify the virtual interface handle to pull from +// the uvm_config_db. +// + function void initialize(uvmf_sim_level_t sim_level, + string environment_path, + string interface_names[], + uvm_reg_block register_model = null, + uvmf_active_passive_t interface_activity[] = {} + ); + + super.initialize(sim_level, environment_path, interface_names, register_model, interface_activity); + + // Interface initialization for sub-environments + s1_interface_names = new[6]; + s1_interface_activity = new[6]; + + s1_interface_names = interface_names[0:5]; + s1_interface_activity = interface_activity[0:5]; + b3_interface_names = new[2]; + b3_interface_activity = new[2]; + + b3_interface_names = interface_names[6:7]; + b3_interface_activity = interface_activity[6:7]; + + + + + s1_config.initialize( sim_level, {environment_path,".s1"}, s1_interface_names, null, s1_interface_activity); + b3_config.initialize( sim_level, {environment_path,".b3"}, b3_interface_names, null, b3_interface_activity); + + + + // pragma uvmf custom initialize begin + // pragma uvmf custom initialize end + + endfunction + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end +`endif + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/environment_packages/system_env_pkg/src/system_env_sequence_base.svh b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/environment_packages/system_env_pkg/src/system_env_sequence_base.svh new file mode 100644 index 00000000..925e4f9b --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/environment_packages/system_env_pkg/src/system_env_sequence_base.svh @@ -0,0 +1,82 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This file contains environment level sequences that will +// be reused from block to top level simulations. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +`ifndef SYSTEM_ENV_SEQUENCE_BASE +`define SYSTEM_ENV_SEQUENCE_BASE + +class system_env_sequence_base #( + type CONFIG_T + ) extends uvmf_virtual_sequence_base #(.CONFIG_T(CONFIG_T)); + + + `uvm_object_param_utils( system_env_sequence_base #( + CONFIG_T + ) ); + + +// This system_env_sequence_base contains a handle to a system_env_configuration object +// named configuration. This configuration variable contains a handle to each +// sequencer within each agent within this environment and any sub-environments. +// The configuration object handle is automatically assigned in the pre_body in the +// base class of this sequence. The configuration handle is retrieved from the +// virtual sequencer that this sequence is started on. +// Available sequencer handles within the environment configuration: + + // Initiator agent sequencers in system_environment: + + // Responder agent sequencers in system_environment: + + // Virtual sequencers in sub-environments located in sub-environment configuration + // configuration.s1_config.vsqr + // configuration.b3_config.vsqr + + +typedef subsys_env_sequence_base #( + .CONFIG_T(subsys_env_configuration) + ) + s1_sequence_base_t; +rand s1_sequence_base_t s1_seq; + +typedef block_3_env_sequence_base #( + .CONFIG_T(block_3_env_configuration) + ) + b3_sequence_base_t; +rand b3_sequence_base_t b3_seq; + + + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + function new(string name = "" ); + super.new(name); + + s1_seq = s1_sequence_base_t::type_id::create("s1_seq"); + b3_seq = b3_sequence_base_t::type_id::create("b3_seq"); + + endfunction + + virtual task body(); + + + s1_seq.start(configuration.s1_config.vsqr); + b3_seq.start(configuration.b3_config.vsqr); + + endtask + +endclass +// pragma uvmf custom external begin +// pragma uvmf custom external end + +`endif diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/environment_packages/system_env_pkg/src/system_env_typedefs.svh b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/environment_packages/system_env_pkg/src/system_env_typedefs.svh new file mode 100644 index 00000000..9814bd58 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/environment_packages/system_env_pkg/src/system_env_typedefs.svh @@ -0,0 +1,20 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: +// This file contains defines and typedefs to be compiled for use in +// the environment package. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// + + + // pragma uvmf custom additional begin + // pragma uvmf custom additional end + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/environment_packages/system_env_pkg/src/system_environment.svh b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/environment_packages/system_env_pkg/src/system_environment.svh new file mode 100644 index 00000000..d822cf45 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/environment_packages/system_env_pkg/src/system_environment.svh @@ -0,0 +1,125 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This environment contains all agents, predictors and +// scoreboards required for the block level design. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +`ifndef SYSTEM_ENVIRONMENT +`define SYSTEM_ENVIRONMENT + +class system_environment extends uvmf_environment_base #( + .CONFIG_T( system_env_configuration + )); + `uvm_component_utils( system_environment ) + + typedef subsys_environment s1_t; + s1_t s1; + + typedef block_3_environment b3_t; + b3_t b3; + + + + + + + + + typedef sys_predictor #( + .CONFIG_T(CONFIG_T) + ) sys_pred_t; + sys_pred_t sys_pred; + typedef sys_scoreboard #( + .CONFIG_T(CONFIG_T) + ) sys_sb_t; + sys_sb_t sys_sb; + + + + + typedef uvmf_virtual_sequencer_base #(.CONFIG_T(system_env_configuration)) system_vsqr_t; + system_vsqr_t vsqr; + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + +// **************************************************************************** +// FUNCTION : new() +// This function is the standard SystemVerilog constructor. +// + function new( string name = "", uvm_component parent = null ); + super.new( name, parent ); + endfunction + +// **************************************************************************** +// FUNCTION: build_phase() +// This function builds all components within this environment. +// + virtual function void build_phase(uvm_phase phase); +// pragma uvmf custom build_phase_pre_super begin +// pragma uvmf custom build_phase_pre_super end + super.build_phase(phase); + s1 = s1_t::type_id::create("s1",this); + s1.set_config(configuration.s1_config); + b3 = b3_t::type_id::create("b3",this); + b3.set_config(configuration.b3_config); + sys_pred = sys_pred_t::type_id::create("sys_pred",this); + sys_pred.configuration = configuration; + sys_sb = sys_sb_t::type_id::create("sys_sb",this); + sys_sb.configuration = configuration; + + vsqr = system_vsqr_t::type_id::create("vsqr", this); + vsqr.set_config(configuration); + configuration.set_vsqr(vsqr); + + // pragma uvmf custom build_phase begin + // pragma uvmf custom build_phase end + endfunction + +// **************************************************************************** +// FUNCTION: connect_phase() +// This function makes all connections within this environment. Connections +// typically inclue agent to predictor, predictor to scoreboard and scoreboard +// to agent. +// + virtual function void connect_phase(uvm_phase phase); +// pragma uvmf custom connect_phase_pre_super begin +// pragma uvmf custom connect_phase_pre_super end + super.connect_phase(phase); + s1.block_1_ap1.connect(sys_pred.sys_apb_ae); + s1.block_1_ap2.connect(sys_pred.sys_axi_1_ae); + s1.block_1_ap3.connect(sys_pred.sys_axi_2_ae); + sys_pred.sys_pre_to_sco_ap.connect(sys_sb.sys_sco_from_pre_ae); + b3.axi_slave_ap.connect(sys_sb.sys_axi_ae); + // pragma uvmf custom reg_model_connect_phase begin + // pragma uvmf custom reg_model_connect_phase end + endfunction + +// **************************************************************************** +// FUNCTION: end_of_simulation_phase() +// This function is executed just prior to executing run_phase. This function +// was added to the environment to sample environment configuration settings +// just before the simulation exits time 0. The configuration structure is +// randomized in the build phase before the environment structure is constructed. +// Configuration variables can be customized after randomization in the build_phase +// of the extended test. +// If a sequence modifies values in the configuration structure then the sequence is +// responsible for sampling the covergroup in the configuration if required. +// + virtual function void start_of_simulation_phase(uvm_phase phase); + configuration.system_configuration_cg.sample(); + endfunction + +endclass +// pragma uvmf custom external begin +// pragma uvmf custom external end + +`endif diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/environment_packages/system_env_pkg/system_env_pkg.compile b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/environment_packages/system_env_pkg/system_env_pkg.compile new file mode 100644 index 00000000..ddbd4836 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/environment_packages/system_env_pkg/system_env_pkg.compile @@ -0,0 +1,8 @@ +needs: + - $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg.compile + - ../subsys_env_pkg/subsys_env_pkg.compile + - ../block_3_env_pkg/block_3_env_pkg.compile + +src: + - system_env_pkg.sv + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/environment_packages/system_env_pkg/system_env_pkg.sv b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/environment_packages/system_env_pkg/system_env_pkg.sv new file mode 100644 index 00000000..db9d74d3 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/environment_packages/system_env_pkg/system_env_pkg.sv @@ -0,0 +1,64 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// PACKAGE: This file defines all of the files contained in the +// environment package that will run on the host simulator. +// +// CONTAINS: +// - +// - +// - +// - +// - +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +package system_env_pkg; + + import uvm_pkg::*; + `include "uvm_macros.svh" + import uvmf_base_pkg::*; + import apb_m_pkg::*; + import axi_m_pkg::*; + import axi_s_pkg::*; + import block_1_env_pkg::*; + import block_2_env_pkg::*; + import subsys_env_pkg::*; + import block_3_env_pkg::*; + + `uvm_analysis_imp_decl(_sys_apb_ae) + `uvm_analysis_imp_decl(_sys_axi_2_ae) + `uvm_analysis_imp_decl(_sys_axi_1_ae) + `uvm_analysis_imp_decl(_sys_axi_ae) + `uvm_analysis_imp_decl(_sys_sco_from_pre_ae) + + // pragma uvmf custom package_imports_additional begin + // pragma uvmf custom package_imports_additional end + + // Parameters defined as HVL parameters + + `include "src/system_env_typedefs.svh" + `include "src/system_env_configuration.svh" + `include "src/sys_predictor.svh" + `include "src/sys_scoreboard.svh" + `include "src/system_environment.svh" + `include "src/system_env_sequence_base.svh" + + // pragma uvmf custom package_item_additional begin + // UVMF_CHANGE_ME : When adding new environment level sequences to the src directory + // be sure to add the sequence file here so that it will be + // compiled as part of the environment package. Be sure to place + // the new sequence after any base sequence of the new sequence. + // pragma uvmf custom package_item_additional end + +endpackage + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/environment_packages/system_env_pkg/system_env_pkg.vinfo b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/environment_packages/system_env_pkg/system_env_pkg.vinfo new file mode 100644 index 00000000..86e05312 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/environment_packages/system_env_pkg/system_env_pkg.vinfo @@ -0,0 +1,5 @@ +@use $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg.vinfo +@use $UVMF_VIP_LIBRARY_HOME/environment_packages/s1_pkg/s1_pkg.vinfo +@use $UVMF_VIP_LIBRARY_HOME/environment_packages/b3_pkg/b3_pkg.vinfo ++incdir+@vinfodir +system_env_pkg.sv diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/environment_packages/system_env_pkg/system_env_pkg_sve.F b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/environment_packages/system_env_pkg/system_env_pkg_sve.F new file mode 100644 index 00000000..a4177b61 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/environment_packages/system_env_pkg/system_env_pkg_sve.F @@ -0,0 +1,14 @@ + +// UVM ++incdir+${UVM_HOME}/src +${UVM_HOME}/src/uvm_pkg.sv + +// Common UVMF files +-f ${UVMF_HOME}/common/common_sve.f + +// Sub-Environments +-F ${UVMF_VIP_LIBRARY_HOME}/environment_packages/subsys_env_pkg/subsys_env_pkg_sve.F +-F ${UVMF_VIP_LIBRARY_HOME}/environment_packages/block_3_env_pkg/block_3_env_pkg_sve.F + ++incdir+. +./system_env_pkg.sv diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/environment_packages/system_env_pkg/yaml/system_environment.yaml b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/environment_packages/system_env_pkg/yaml/system_environment.yaml new file mode 100644 index 00000000..c4c2dc78 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/environment_packages/system_env_pkg/yaml/system_environment.yaml @@ -0,0 +1,55 @@ +uvmf: + environments: + system: + agents: [] + analysis_components: + - name: sys_pred + parameters: [] + type: sys_predictor + - name: sys_sb + parameters: [] + type: sys_scoreboard + analysis_exports: [] + analysis_ports: [] + config_constraints: [] + config_vars: + - comment: '' + isrand: 'False' + name: has_scoreboard + type: bit + value: '' + existing_library_component: 'True' + hvl_pkg_parameters: [] + imports: + - name: apb_m_pkg + - name: axi_m_pkg + - name: axi_s_pkg + - name: block_1_env_pkg + - name: block_2_env_pkg + non_uvmf_components: [] + parameters: [] + qvip_memory_agents: [] + scoreboards: [] + subenvs: + - name: s1 + parameters: [] + type: subsys + - name: b3 + parameters: [] + type: block_3 + tlm_connections: + - driver: s1.block_1_ap1 + receiver: sys_pred.sys_apb_ae + validate: 'True' + - driver: s1.block_1_ap2 + receiver: sys_pred.sys_axi_1_ae + validate: 'True' + - driver: s1.block_1_ap3 + receiver: sys_pred.sys_axi_2_ae + validate: 'True' + - driver: sys_pred.sys_pre_to_sco_ap + receiver: sys_sb.sys_sco_from_pre_ae + validate: 'True' + - driver: b3.axi_slave_ap + receiver: sys_sb.sys_axi_ae + validate: 'True' diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/environment_packages/system_env_pkg/yaml/system_util_comp_sys_predictor.yaml b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/environment_packages/system_env_pkg/yaml/system_util_comp_sys_predictor.yaml new file mode 100644 index 00000000..f4d56616 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/environment_packages/system_env_pkg/yaml/system_util_comp_sys_predictor.yaml @@ -0,0 +1,15 @@ +uvmf: + util_components: + sys_predictor: + analysis_exports: + - name: sys_apb_ae + type: apb_m_transaction + - name: sys_axi_2_ae + type: axi_m_transaction + - name: sys_axi_1_ae + type: axi_m_transaction + analysis_ports: + - name: sys_pre_to_sco_ap + type: axi_s_transaction + existing_library_component: 'True' + type: predictor diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/environment_packages/system_env_pkg/yaml/system_util_comp_sys_scoreboard.yaml b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/environment_packages/system_env_pkg/yaml/system_util_comp_sys_scoreboard.yaml new file mode 100644 index 00000000..e6d4c20f --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/environment_packages/system_env_pkg/yaml/system_util_comp_sys_scoreboard.yaml @@ -0,0 +1,10 @@ +uvmf: + util_components: + sys_scoreboard: + analysis_exports: + - name: sys_axi_ae + type: axi_s_transaction + - name: sys_sco_from_pre_ae + type: axi_s_transaction + existing_library_component: 'True' + type: scoreboard diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/apb_m_pkg/.project b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/apb_m_pkg/.project new file mode 100644 index 00000000..6da82621 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/apb_m_pkg/.project @@ -0,0 +1,30 @@ + + + apb_m_pkg + + + + + + org.python.pydev.PyDevBuilder + + + + + net.sf.sveditor.core.SVProjectBuilder + + + + + + net.sf.sveditor.core.SVNature + org.python.pydev.pythonNature + + + + UVMF_VIP_LIBRARY_HOME + $%7BPARENT-2-PROJECT_LOC%7D + + + + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/apb_m_pkg/.svproject b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/apb_m_pkg/.svproject new file mode 100644 index 00000000..e17b552f --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/apb_m_pkg/.svproject @@ -0,0 +1,16 @@ + + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/apb_m_pkg/Makefile b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/apb_m_pkg/Makefile new file mode 100644 index 00000000..eec7d999 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/apb_m_pkg/Makefile @@ -0,0 +1,66 @@ +# apb_m interface packages source +# pragma uvmf custom additional begin +# pragma uvmf custom additional end + +apb_m_PKG = \ + +incdir+$(UVMF_VIP_LIBRARY_HOME)/interface_packages/apb_m_pkg \ + -F $(UVMF_VIP_LIBRARY_HOME)/interface_packages/apb_m_pkg/apb_m_filelist_hvl.f + +apb_m_PKG_HDL = \ + +incdir+$(UVMF_VIP_LIBRARY_HOME)/interface_packages/apb_m_pkg \ + -F $(UVMF_VIP_LIBRARY_HOME)/interface_packages/apb_m_pkg/apb_m_filelist_hdl.f + +apb_m_PKG_XRTL = \ + +incdir+$(UVMF_VIP_LIBRARY_HOME)/interface_packages/apb_m_pkg \ + -F $(UVMF_VIP_LIBRARY_HOME)/interface_packages/apb_m_pkg/apb_m_filelist_xrtl.f + +COMP_apb_m_PKG_TGT_0 = q_comp_apb_m_pkg +COMP_apb_m_PKG_TGT_1 = v_comp_apb_m_pkg +COMP_apb_m_PKG_TGT = $(COMP_apb_m_PKG_TGT_$(USE_VELOCE)) + +comp_apb_m_pkg: $(COMP_apb_m_PKG_TGT) + +q_comp_apb_m_pkg: + $(HDL_COMP_CMD) $(apb_m_PKG_HDL) + $(HVL_COMP_CMD) $(apb_m_PKG) + $(HDL_COMP_CMD) $(apb_m_PKG_XRTL) + +v_comp_apb_m_pkg: + $(HVL_COMP_CMD) $(apb_m_PKG_HDL) + $(HVL_COMP_CMD) $(apb_m_PKG) + $(VELANALYZE_CMD) $(apb_m_PKG_HDL) + $(VELANALYZE_HVL_CMD) $(apb_m_PKG) + $(HDL_COMP_CMD) $(apb_m_PKG_XRTL) + +ifeq ($(MTI_VCO_MODE),64) + GCC_COMP_ARCH = -m64 +else + GCC_COMP_ARCH = -m32 +endif + +export apb_m_IF_DPI_SRC ?= $(UVMF_VIP_LIBRARY_HOME)/interface_packages/apb_m_pkg/dpi + +C_FILE_COMPILE_LIST_apb_m_pkg = \ + +O_FILE_COMPILE_LIST_apb_m_pkg = $(notdir $(C_FILE_COMPILE_LIST_apb_m_pkg:.c=.o)) + +GCC_COMP_ARGS_apb_m_pkg += -I$(apb_m_IF_DPI_SRC) \ + -fPIC + +GCC_COMP_ARGS_apb_m_pkg += $(apb_m_IF_GCC_COMP_ARGUMENTS) + +GCC_LINK_ARGS_apb_m_pkg += \ + \ + -o .so + +comp_apb_m_pkg_c_files: + @echo "--------------------------------" + @echo "Compiling Interface C source" + @echo "--------------------------------" + gcc $(GCC_COMP_ARCH) $(GCC_COMP_ARGS_apb_m_pkg) $(C_FILE_COMPILE_LIST_apb_m_pkg) + @echo "--------------------------------" + @echo "Linking Interface C objects into a shared object" + @echo "--------------------------------" + gcc $(GCC_COMP_ARCH) $(GCC_LINK_ARGS_apb_m_pkg) $(O_FILE_COMPILE_LIST_apb_m_pkg) + @echo "--------------------------------" + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/apb_m_pkg/apb_m.compile b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/apb_m_pkg/apb_m.compile new file mode 100644 index 00000000..d77eb23e --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/apb_m_pkg/apb_m.compile @@ -0,0 +1,3 @@ +needs: + - apb_m_hvl.compile + - apb_m_hdl.compile diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/apb_m_pkg/apb_m_bfm.vinfo b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/apb_m_pkg/apb_m_bfm.vinfo new file mode 100644 index 00000000..8d4b80f9 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/apb_m_pkg/apb_m_bfm.vinfo @@ -0,0 +1,6 @@ +@use $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg_hdl.vinfo +@use apb_m_pkg_hdl.vinfo ++incdir+@vinfodir +src/apb_m_if.sv +src/apb_m_driver_bfm.sv +src/apb_m_monitor_bfm.sv diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/apb_m_pkg/apb_m_common.compile b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/apb_m_pkg/apb_m_common.compile new file mode 100644 index 00000000..26821a84 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/apb_m_pkg/apb_m_common.compile @@ -0,0 +1,7 @@ +needs: + - $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg_hdl.compile +incdir: + - . + - ${uvm_path}/src +src: + - apb_m_pkg_hdl.sv diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/apb_m_pkg/apb_m_filelist_hdl.f b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/apb_m_pkg/apb_m_filelist_hdl.f new file mode 100644 index 00000000..0d2a4c9d --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/apb_m_pkg/apb_m_filelist_hdl.f @@ -0,0 +1 @@ +$UVMF_VIP_LIBRARY_HOME/interface_packages/apb_m_pkg/apb_m_pkg_hdl.sv diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/apb_m_pkg/apb_m_filelist_hvl.f b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/apb_m_pkg/apb_m_filelist_hvl.f new file mode 100644 index 00000000..0d4b8d6b --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/apb_m_pkg/apb_m_filelist_hvl.f @@ -0,0 +1 @@ +$UVMF_VIP_LIBRARY_HOME/interface_packages/apb_m_pkg/apb_m_pkg.sv \ No newline at end of file diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/apb_m_pkg/apb_m_filelist_xrtl.f b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/apb_m_pkg/apb_m_filelist_xrtl.f new file mode 100644 index 00000000..d2cef722 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/apb_m_pkg/apb_m_filelist_xrtl.f @@ -0,0 +1,3 @@ +$UVMF_VIP_LIBRARY_HOME/interface_packages/apb_m_pkg/src/apb_m_if.sv +$UVMF_VIP_LIBRARY_HOME/interface_packages/apb_m_pkg/src/apb_m_monitor_bfm.sv +$UVMF_VIP_LIBRARY_HOME/interface_packages/apb_m_pkg/src/apb_m_driver_bfm.sv diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/apb_m_pkg/apb_m_hdl.compile b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/apb_m_pkg/apb_m_hdl.compile new file mode 100644 index 00000000..83ce2876 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/apb_m_pkg/apb_m_hdl.compile @@ -0,0 +1,9 @@ +needs: + - $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg_hdl.compile + - ./apb_m_common.compile +incdir: + - . +src: + - src/apb_m_if.sv + - src/apb_m_monitor_bfm.sv + - src/apb_m_driver_bfm.sv diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/apb_m_pkg/apb_m_hvl.compile b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/apb_m_pkg/apb_m_hvl.compile new file mode 100644 index 00000000..2b4533f6 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/apb_m_pkg/apb_m_hvl.compile @@ -0,0 +1,7 @@ +needs: + - $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg.compile + - ./apb_m_common.compile +incdir: + - . +src: + - apb_m_pkg.sv diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/apb_m_pkg/apb_m_pkg.sv b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/apb_m_pkg/apb_m_pkg.sv new file mode 100644 index 00000000..8f8672c0 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/apb_m_pkg/apb_m_pkg.sv @@ -0,0 +1,79 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// PACKAGE: This file defines all of the files contained in the +// interface package that will run on the host simulator. +// +// CONTAINS: +// - +// - +// - + +// - +// - +// - + +// - +// - +// - + +// - +// - +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +`ifndef APB_M_PKG +`define APB_M_PKG +package apb_m_pkg; + + import uvm_pkg::*; + import uvmf_base_pkg_hdl::*; + import uvmf_base_pkg::*; + import apb_m_pkg_hdl::*; + + `include "uvm_macros.svh" + + // pragma uvmf custom package_imports_additional begin + // pragma uvmf custom package_imports_additional end + `include "src/apb_m_macros.svh" + + export apb_m_pkg_hdl::*; + + + + // Parameters defined as HVL parameters + + `include "src/apb_m_typedefs.svh" + `include "src/apb_m_transaction.svh" + + `include "src/apb_m_configuration.svh" + `include "src/apb_m_driver.svh" + `include "src/apb_m_monitor.svh" + + `include "src/apb_m_transaction_coverage.svh" + `include "src/apb_m_sequence_base.svh" + `include "src/apb_m_random_sequence.svh" + + `include "src/apb_m_responder_sequence.svh" + `include "src/apb_m2reg_adapter.svh" + + `include "src/apb_m_agent.svh" + + // pragma uvmf custom package_item_additional begin + // UVMF_CHANGE_ME : When adding new interface sequences to the src directory + // be sure to add the sequence file here so that it will be + // compiled as part of the interface package. Be sure to place + // the new sequence after any base sequences of the new sequence. + // pragma uvmf custom package_item_additional end + +endpackage + +// pragma uvmf custom external begin +// pragma uvmf custom external end +`endif diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/apb_m_pkg/apb_m_pkg.vinfo b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/apb_m_pkg/apb_m_pkg.vinfo new file mode 100644 index 00000000..e6a8b7c1 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/apb_m_pkg/apb_m_pkg.vinfo @@ -0,0 +1,4 @@ +@use $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg.vinfo +@use apb_m_pkg_hdl.vinfo ++incdir+@vinfodir +apb_m_pkg.sv diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/apb_m_pkg/apb_m_pkg_hdl.sv b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/apb_m_pkg/apb_m_pkg_hdl.sv new file mode 100644 index 00000000..0159159c --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/apb_m_pkg/apb_m_pkg_hdl.sv @@ -0,0 +1,40 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// PACKAGE: This file defines all of the files contained in the +// interface package that needs to be compiled and synthesized +// for running on Veloce. +// +// CONTAINS: +// - +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +`ifndef APB_M_PKG_HDL +`define APB_M_PKG_HDL +package apb_m_pkg_hdl; + + import uvmf_base_pkg_hdl::*; + + // pragma uvmf custom package_imports_additional begin + // pragma uvmf custom package_imports_additional end + + // Parameters defined as HDL parameters + + `include "src/apb_m_typedefs_hdl.svh" + `include "src/apb_m_macros.svh" + + // pragma uvmf custom package_item_additional begin + // pragma uvmf custom package_item_additional end + +endpackage + +// pragma uvmf custom external begin +// pragma uvmf custom external end +`endif diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/apb_m_pkg/apb_m_pkg_hdl.vinfo b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/apb_m_pkg/apb_m_pkg_hdl.vinfo new file mode 100644 index 00000000..3e5dc166 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/apb_m_pkg/apb_m_pkg_hdl.vinfo @@ -0,0 +1,2 @@ +@use $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg_hdl.vinfo +apb_m_pkg_hdl.sv diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/apb_m_pkg/apb_m_pkg_sve.F b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/apb_m_pkg/apb_m_pkg_sve.F new file mode 100644 index 00000000..b934c1a1 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/apb_m_pkg/apb_m_pkg_sve.F @@ -0,0 +1,10 @@ +// UVM ++incdir+${UVM_HOME}/src +${UVM_HOME}/src/uvm_pkg.sv + +// Common UVMF files +-f ${UVMF_HOME}/common/common_sve.f + ++incdir+. +-f ${UVMF_VIP_LIBRARY_HOME}/interface_packages/apb_m_pkg/apb_m_filelist_hdl.f +-f ${UVMF_VIP_LIBRARY_HOME}/interface_packages/apb_m_pkg/apb_m_filelist_hvl.f diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/apb_m_pkg/compile.do b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/apb_m_pkg/compile.do new file mode 100644 index 00000000..944fd712 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/apb_m_pkg/compile.do @@ -0,0 +1,14 @@ +# Tcl do file for compile of apb_m interface + +# pragma uvmf custom additional begin +# pragma uvmf custom additional end + + +vlog -sv -timescale 1ps/1ps -suppress 2223,2286 +incdir+$env(UVMF_VIP_LIBRARY_HOME)/interface_packages/apb_m_pkg \ + -F $env(UVMF_VIP_LIBRARY_HOME)/interface_packages/apb_m_pkg/apb_m_filelist_hdl.f + +vlog -sv -timescale 1ps/1ps -suppress 2223,2286 +incdir+$env(UVMF_VIP_LIBRARY_HOME)/interface_packages/apb_m_pkg \ + -F $env(UVMF_VIP_LIBRARY_HOME)/interface_packages/apb_m_pkg/apb_m_filelist_hvl.f + +vlog -sv -timescale 1ps/1ps -suppress 2223,2286 +incdir+$env(UVMF_VIP_LIBRARY_HOME)/interface_packages/apb_m_pkg \ + -F $env(UVMF_VIP_LIBRARY_HOME)/interface_packages/apb_m_pkg/apb_m_filelist_xrtl.f \ No newline at end of file diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/apb_m_pkg/src/apb_m2reg_adapter.svh b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/apb_m_pkg/src/apb_m2reg_adapter.svh new file mode 100644 index 00000000..e82ede66 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/apb_m_pkg/src/apb_m2reg_adapter.svh @@ -0,0 +1,120 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: +// This file contains the UVM register adapter for the apb_m interface. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +`ifndef APB_M2REG_ADAPTER +`define APB_M2REG_ADAPTER +class apb_m2reg_adapter #( + int APB_ADDR_WIDTH = 32, + int APB_DATA_WIDTH = 32, + int STRB_LEN = APB_ADDR_WIDTH/8 + ) extends uvm_reg_adapter; + + `uvm_object_param_utils( apb_m2reg_adapter #( + APB_ADDR_WIDTH, + APB_DATA_WIDTH, + STRB_LEN + )) + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + //-------------------------------------------------------------------- + // new + //-------------------------------------------------------------------- + function new (string name = "apb_m2reg_adapter" ); + super.new(name); + // pragma uvmf custom new begin + // UVMF_CHANGE_ME : Configure the adapter regarding byte enables and provides response. + + // Does the protocol the Agent is modeling support byte enables? + // 0 = NO + // 1 = YES + supports_byte_enable = 0; + + // Does the Agent's Driver provide separate response sequence items? + // i.e. Does the driver call seq_item_port.put() + // and do the sequences call get_response()? + // 0 = NO + // 1 = YES + provides_responses = 0; + // pragma uvmf custom new end + + endfunction: new + + //-------------------------------------------------------------------- + // reg2bus + //-------------------------------------------------------------------- + virtual function uvm_sequence_item reg2bus(const ref uvm_reg_bus_op rw); + + apb_m_transaction #( + .APB_ADDR_WIDTH(APB_ADDR_WIDTH), + .APB_DATA_WIDTH(APB_DATA_WIDTH), + .STRB_LEN(STRB_LEN) + ) trans_h = apb_m_transaction #( + .APB_ADDR_WIDTH(APB_ADDR_WIDTH), + .APB_DATA_WIDTH(APB_DATA_WIDTH), + .STRB_LEN(STRB_LEN) + )::type_id::create("trans_h"); + + // pragma uvmf custom reg2bus begin + // UVMF_CHANGE_ME : Fill in the reg2bus adapter mapping registe fields to protocol fields. + + //Adapt the following for your sequence item type + // trans_h.op = (rw.kind == UVM_READ) ? WB_READ : WB_WRITE; + //Copy over address + // trans_h.addr = rw.addr; + //Copy over write data + // trans_h.data = rw.data; + + // pragma uvmf custom reg2bus end + + // Return the adapted transaction + return trans_h; + + endfunction: reg2bus + + //-------------------------------------------------------------------- + // bus2reg + //-------------------------------------------------------------------- + virtual function void bus2reg(uvm_sequence_item bus_item, + ref uvm_reg_bus_op rw); + apb_m_transaction #( + .APB_ADDR_WIDTH(APB_ADDR_WIDTH), + .APB_DATA_WIDTH(APB_DATA_WIDTH), + .STRB_LEN(STRB_LEN) + ) trans_h; + if (!$cast(trans_h, bus_item)) begin + `uvm_fatal("ADAPT","Provided bus_item is not of the correct type") + return; + end + // pragma uvmf custom bus2reg begin + // UVMF_CHANGE_ME : Fill in the bus2reg adapter mapping protocol fields to register fields. + //Adapt the following for your sequence item type + //Copy over instruction type + // rw.kind = (trans_h.op == WB_WRITE) ? UVM_WRITE : UVM_READ; + //Copy over address + // rw.addr = trans_h.addr; + //Copy over read data + // rw.data = trans_h.data; + //Check for errors on the bus and return UVM_NOT_OK if there is an error + // rw.status = UVM_IS_OK; + // pragma uvmf custom bus2reg end + + endfunction: bus2reg + +endclass : apb_m2reg_adapter + +// pragma uvmf custom external begin +// pragma uvmf custom external end +`endif diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/apb_m_pkg/src/apb_m_agent.svh b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/apb_m_pkg/src/apb_m_agent.svh new file mode 100644 index 00000000..9907f8f3 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/apb_m_pkg/src/apb_m_agent.svh @@ -0,0 +1,86 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: Protocol specific agent class definition +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// + +`ifndef APB_M_AGENT +`define APB_M_AGENT + +class apb_m_agent #( + int APB_ADDR_WIDTH = 32, + int APB_DATA_WIDTH = 32, + int STRB_LEN = APB_ADDR_WIDTH/8 + ) extends uvmf_parameterized_agent #( + .CONFIG_T(apb_m_configuration #( + .APB_ADDR_WIDTH(APB_ADDR_WIDTH), + .APB_DATA_WIDTH(APB_DATA_WIDTH), + .STRB_LEN(STRB_LEN) + )), + .DRIVER_T(apb_m_driver #( + .APB_ADDR_WIDTH(APB_ADDR_WIDTH), + .APB_DATA_WIDTH(APB_DATA_WIDTH), + .STRB_LEN(STRB_LEN) + )), + .MONITOR_T(apb_m_monitor #( + .APB_ADDR_WIDTH(APB_ADDR_WIDTH), + .APB_DATA_WIDTH(APB_DATA_WIDTH), + .STRB_LEN(STRB_LEN) + )), + .COVERAGE_T(apb_m_transaction_coverage #( + .APB_ADDR_WIDTH(APB_ADDR_WIDTH), + .APB_DATA_WIDTH(APB_DATA_WIDTH), + .STRB_LEN(STRB_LEN) + )), + .TRANS_T(apb_m_transaction #( + .APB_ADDR_WIDTH(APB_ADDR_WIDTH), + .APB_DATA_WIDTH(APB_DATA_WIDTH), + .STRB_LEN(STRB_LEN) + )) + ); + + `uvm_component_param_utils( apb_m_agent #( + APB_ADDR_WIDTH, + APB_DATA_WIDTH, + STRB_LEN + )) + +// pragma uvmf custom class_item_additional begin +// pragma uvmf custom class_item_additional end + +// **************************************************************************** +// FUNCTION : new() +// This function is the standard SystemVerilog constructor. +// + function new( string name = "", uvm_component parent = null ); + super.new( name, parent ); + endfunction + +// **************************************************************************** + // FUNCTION: build_phase + virtual function void build_phase(uvm_phase phase); +// pragma uvmf custom build_phase_pre_super begin +// pragma uvmf custom build_phase_pre_super end + super.build_phase(phase); + if (configuration.active_passive == ACTIVE) begin + // Place sequencer handle into configuration object + // so that it may be retrieved from configuration + // rather than using uvm_config_db + configuration.sequencer = this.sequencer; + end + endfunction + +endclass + + +// pragma uvmf custom external begin +// pragma uvmf custom external end +`endif diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/apb_m_pkg/src/apb_m_configuration.svh b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/apb_m_pkg/src/apb_m_configuration.svh new file mode 100644 index 00000000..86a11324 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/apb_m_pkg/src/apb_m_configuration.svh @@ -0,0 +1,214 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This class contains all variables and functions used +// to configure the apb_m agent and its bfm's. It gets the +// bfm's from the uvm_config_db for use by the agent. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// + +`ifndef APB_M_CONFIGURATION +`define APB_M_CONFIGURATION +class apb_m_configuration #( + int APB_ADDR_WIDTH = 32, + int APB_DATA_WIDTH = 32, + int STRB_LEN = APB_ADDR_WIDTH/8 + ) extends uvmf_parameterized_agent_configuration_base #( + .DRIVER_BFM_BIND_T(virtual apb_m_driver_bfm #( + .APB_ADDR_WIDTH(APB_ADDR_WIDTH), + .APB_DATA_WIDTH(APB_DATA_WIDTH), + .STRB_LEN(STRB_LEN) + )), + .MONITOR_BFM_BIND_T( virtual apb_m_monitor_bfm #( + .APB_ADDR_WIDTH(APB_ADDR_WIDTH), + .APB_DATA_WIDTH(APB_DATA_WIDTH), + .STRB_LEN(STRB_LEN) + ))); + + `uvm_object_param_utils( apb_m_configuration #( + APB_ADDR_WIDTH, + APB_DATA_WIDTH, + STRB_LEN + )) + + + // Sequencer handle populated by agent + uvm_sequencer #(apb_m_transaction #( + .APB_ADDR_WIDTH(APB_ADDR_WIDTH), + .APB_DATA_WIDTH(APB_DATA_WIDTH), + .STRB_LEN(STRB_LEN) + ) ) sequencer; + + //Constraints for the configuration variables: + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + covergroup apb_m_configuration_cg; + // pragma uvmf custom covergroup begin + option.auto_bin_max=1024; + // pragma uvmf custom covergroup end + endgroup + + //******************************************************************* + //******************************************************************* + // Structure used to pass configuration variables to monitor and driver BFM's. + // Use to_struct function to pack variables into structure. + // Use from_struct function to unpack variables from structure. + // This structure is defined in apb_m_macros.svh + `apb_m_CONFIGURATION_STRUCT + apb_m_configuration_s apb_m_configuration_struct; + //******************************************************************* + // FUNCTION: to_struct() + // This function packs variables into a apb_m_configuration_s + // structure. The function returns the handle to the apb_m_configuration_struct. + // This function is defined in apb_m_macros.svh + `apb_m_CONFIGURATION_TO_STRUCT_FUNCTION + //******************************************************************* + // FUNCTION: from_struct() + // This function unpacks the struct provided as an argument into + // variables of this class. + // This function is defined in apb_m_macros.svh + `apb_m_CONFIGURATION_FROM_STRUCT_FUNCTION + + // **************************************************************************** + // FUNCTION : new() + // This function is the standard SystemVerilog constructor. + // + function new( string name = "" ); + super.new( name ); + // Construct the covergroup for this configuration class + apb_m_configuration_cg = new; + endfunction + + // **************************************************************************** + // FUNCTION: post_randomize() + // This function is automatically called after the randomize() function + // is executed. + // + function void post_randomize(); + super.post_randomize(); + apb_m_configuration_cg.sample(); + endfunction + + // **************************************************************************** + // FUNCTION: initialize + // This function causes the configuration to retrieve + // its virtual interface handle from the uvm_config_db. + // This function also makes itself available to its + // agent through the uvm_config_db. + // + // ARGUMENTS: + // uvmf_active_passive_t activity: + // This argument identifies the simulation level + // as either BLOCK, CHIP, SIMULATION, etc. + // + // AGENT_PATH: + // This argument identifies the path to this + // configurations agent. This configuration + // makes itself available to the agent specified + // by agent_path by placing itself into the + // uvm_config_db. + // + // INTERFACE_NAME: + // This argument identifies the string name of + // this configurations BFM's. This string + // name is used to retrieve the driver and + // monitor BFM from the uvm_config_db. + // + virtual function void initialize(uvmf_active_passive_t activity, + string agent_path, + string interface_name); + + super.initialize( activity, agent_path, interface_name); + // The covergroup is given the same name as the interface + apb_m_configuration_cg.set_inst_name(interface_name); + + // This configuration places itself into the uvm_config_db for the agent, identified by the agent_path variable, to retrieve. + uvm_config_db #( apb_m_configuration #( + .APB_ADDR_WIDTH(APB_ADDR_WIDTH), + .APB_DATA_WIDTH(APB_DATA_WIDTH), + .STRB_LEN(STRB_LEN) + ) + )::set( null ,agent_path,UVMF_AGENT_CONFIG, this ); + + // This configuration also places itself in the config db using the same identifier used by the interface. This allows users to access + // configuration variables and the interface through the bfm api class rather than directly accessing the BFM. This is useful for + // accessingthe BFM when using Veloce + uvm_config_db #( apb_m_configuration #( + .APB_ADDR_WIDTH(APB_ADDR_WIDTH), + .APB_DATA_WIDTH(APB_DATA_WIDTH), + .STRB_LEN(STRB_LEN) + ) + )::set( null ,UVMF_CONFIGURATIONS, interface_name, this ); + + apb_m_configuration_cg.set_inst_name($sformatf("apb_m_configuration_cg_%s",get_full_name())); + +// This code is to aid in debugging parameter mismatches between the BFM and its corresponding agent. +// Enable this debug by setting UVM_VERBOSITY to UVM_DEBUG +// Setting UVM_VERBOSITY to UVM_DEBUG causes all BFM's and all agents to display their parameter settings. +// All of the messages from this feature have a UVM messaging id value of "CFG" +// The transcript or run.log can be parsed to ensure BFM parameter settings match its corresponding agents parameter settings. + `uvm_info("CFG", + $psprintf("The agent at '%s' is using interface named %s has the following parameters: APB_ADDR_WIDTH=%x APB_DATA_WIDTH=%x STRB_LEN=%x ", agent_path, interface_name, APB_ADDR_WIDTH ,APB_DATA_WIDTH ,STRB_LEN ), + UVM_DEBUG) + + // pragma uvmf custom initialize begin + // This controls whether or not the agent returns a transaction handle in the driver when calling + // item_done() back into the sequencer or not. If set to 1, a transaction is sent back which means + // the sequence on the other end must use the get_response() part of the driver/sequence API. If + // this doesn't occur, there will eventually be response_queue overflow errors during the test. + return_transaction_response = 1'b0; + + // pragma uvmf custom initialize end + + endfunction + + // **************************************************************************** + // TASK: wait_for_reset + // *[Required]* Blocks until reset is released. The wait_for_reset operation is performed + // by a task in the monitor bfm. + virtual task wait_for_reset(); + monitor_bfm.wait_for_reset(); + endtask + + // **************************************************************************** + // TASK: wait_for_num_clocks + // *[Required]* Blocks until specified number of clocks have elapsed. The wait_for_num_clocks + // operation is performed by a task in the monitor bfm. + virtual task wait_for_num_clocks(int clocks); + monitor_bfm.wait_for_num_clocks(clocks); + endtask + + // **************************************************************************** + // FUNCTION : convert2string() + // This function is used to convert variables in this class into a string for log messaging. + // + virtual function string convert2string (); + // pragma uvmf custom convert2string begin + return $sformatf(""); + // pragma uvmf custom convert2string end + endfunction + + // **************************************************************************** + // FUNCTION: get_sequencer + function uvm_sequencer #(apb_m_transaction#( + .APB_ADDR_WIDTH(APB_ADDR_WIDTH), + .APB_DATA_WIDTH(APB_DATA_WIDTH), + .STRB_LEN(STRB_LEN) + )) get_sequencer(); + return sequencer; + endfunction + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end +`endif diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/apb_m_pkg/src/apb_m_driver.svh b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/apb_m_pkg/src/apb_m_driver.svh new file mode 100644 index 00000000..5753586f --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/apb_m_pkg/src/apb_m_driver.svh @@ -0,0 +1,117 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This class passes transactions between the sequencer +// and the BFM driver interface. It accesses the driver BFM +// through the bfm handle. This driver +// passes transactions to the driver BFM through the access +// task. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +`ifndef APB_M_DRIVER +`define APB_M_DRIVER +class apb_m_driver #( + int APB_ADDR_WIDTH = 32, + int APB_DATA_WIDTH = 32, + int STRB_LEN = APB_ADDR_WIDTH/8 + ) extends uvmf_driver_base #( + .CONFIG_T(apb_m_configuration #( + .APB_ADDR_WIDTH(APB_ADDR_WIDTH), + .APB_DATA_WIDTH(APB_DATA_WIDTH), + .STRB_LEN(STRB_LEN) + ) ), + .BFM_BIND_T(virtual apb_m_driver_bfm #( + .APB_ADDR_WIDTH(APB_ADDR_WIDTH), + .APB_DATA_WIDTH(APB_DATA_WIDTH), + .STRB_LEN(STRB_LEN) + ) ), + .REQ(apb_m_transaction #( + .APB_ADDR_WIDTH(APB_ADDR_WIDTH), + .APB_DATA_WIDTH(APB_DATA_WIDTH), + .STRB_LEN(STRB_LEN) + ) ), + .RSP(apb_m_transaction #( + .APB_ADDR_WIDTH(APB_ADDR_WIDTH), + .APB_DATA_WIDTH(APB_DATA_WIDTH), + .STRB_LEN(STRB_LEN) + ) )); + + `uvm_component_param_utils( apb_m_driver #( + APB_ADDR_WIDTH, + APB_DATA_WIDTH, + STRB_LEN + )) +//******************************************************************* +// Macros that define structs located in apb_m_macros.svh +//******************************************************************* +// Initiator macro used by apb_m_driver and apb_m_driver_bfm +// to communicate initiator driven data to apb_m_driver_bfm. +`apb_m_INITIATOR_STRUCT + apb_m_initiator_s apb_m_initiator_struct; +//******************************************************************* +// Responder macro used by apb_m_driver and apb_m_driver_bfm +// to communicate Responder driven data to apb_m_driver_bfm. +`apb_m_RESPONDER_STRUCT + apb_m_responder_s apb_m_responder_struct; + +// pragma uvmf custom class_item_additional begin +// pragma uvmf custom class_item_additional end + +// **************************************************************************** +// This function is the standard SystemVerilog constructor. +// + function new( string name = "", uvm_component parent=null ); + super.new( name, parent ); + endfunction + +// **************************************************************************** +// This function sends configuration object variables to the driver BFM +// using the configuration struct. +// + virtual function void configure(input CONFIG_T cfg); + bfm.configure( cfg.to_struct() ); + endfunction + +// **************************************************************************** +// This function places a handle to this class in the proxy variable in the +// driver BFM. This allows the driver BFM to call tasks and function within this class. +// + virtual function void set_bfm_proxy_handle(); + bfm.proxy = this; endfunction + +// **************************************************************************** +// This task is called by the run_phase in uvmf_driver_base. + virtual task access( inout REQ txn ); +// pragma uvmf custom access begin + if (configuration.initiator_responder==RESPONDER) begin + // Complete current transfer and wait for next transfer + bfm.respond_and_wait_for_next_transfer( + apb_m_initiator_struct, + txn.to_responder_struct() + ); + // Unpack information about initiated transfer received by this responder + txn.from_initiator_struct(apb_m_initiator_struct); + end else begin + // Initiate a transfer and get response + bfm.initiate_and_get_response( + txn.to_initiator_struct(), + apb_m_responder_struct + ); + // Unpack transfer response information received by this initiator + txn.from_responder_struct(apb_m_responder_struct); + end +// pragma uvmf custom access end + endtask + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end +`endif diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/apb_m_pkg/src/apb_m_driver_bfm.sv b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/apb_m_pkg/src/apb_m_driver_bfm.sv new file mode 100644 index 00000000..8a8926e6 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/apb_m_pkg/src/apb_m_driver_bfm.sv @@ -0,0 +1,378 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: +// This interface performs the apb_m signal driving. It is +// accessed by the uvm apb_m driver through a virtual interface +// handle in the apb_m configuration. It drives the singals passed +// in through the port connection named bus of type apb_m_if. +// +// Input signals from the apb_m_if are assigned to an internal input +// signal with a _i suffix. The _i signal should be used for sampling. +// +// The input signal connections are as follows: +// bus.signal -> signal_i +// +// This bfm drives signals with a _o suffix. These signals +// are driven onto signals within apb_m_if based on INITIATOR/RESPONDER and/or +// ARBITRATION/GRANT status. +// +// The output signal connections are as follows: +// signal_o -> bus.signal +// +// +// Interface functions and tasks used by UVM components: +// +// configure: +// This function gets configuration attributes from the +// UVM driver to set any required BFM configuration +// variables such as 'initiator_responder'. +// +// initiate_and_get_response: +// This task is used to perform signaling activity for initiating +// a protocol transfer. The task initiates the transfer, using +// input data from the initiator struct. Then the task captures +// response data, placing the data into the response struct. +// The response struct is returned to the driver class. +// +// respond_and_wait_for_next_transfer: +// This task is used to complete a current transfer as a responder +// and then wait for the initiator to start the next transfer. +// The task uses data in the responder struct to drive protocol +// signals to complete the transfer. The task then waits for +// the next transfer. Once the next transfer begins, data from +// the initiator is placed into the initiator struct and sent +// to the responder sequence for processing to determine +// what data to respond with. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +import uvmf_base_pkg_hdl::*; +import apb_m_pkg_hdl::*; +`include "src/apb_m_macros.svh" + +interface apb_m_driver_bfm #( + int APB_ADDR_WIDTH = 32, + int APB_DATA_WIDTH = 32, + int STRB_LEN = APB_ADDR_WIDTH/8 + ) + (apb_m_if bus); + // The following pragma and additional ones in-lined further below are for running this BFM on Veloce + // pragma attribute apb_m_driver_bfm partition_interface_xif + +`ifndef XRTL +// This code is to aid in debugging parameter mismatches between the BFM and its corresponding agent. +// Enable this debug by setting UVM_VERBOSITY to UVM_DEBUG +// Setting UVM_VERBOSITY to UVM_DEBUG causes all BFM's and all agents to display their parameter settings. +// All of the messages from this feature have a UVM messaging id value of "CFG" +// The transcript or run.log can be parsed to ensure BFM parameter settings match its corresponding agents parameter settings. +import uvm_pkg::*; +`include "uvm_macros.svh" +initial begin : bfm_vs_agent_parameter_debug + `uvm_info("CFG", + $psprintf("The BFM at '%m' has the following parameters: APB_ADDR_WIDTH=%x APB_DATA_WIDTH=%x STRB_LEN=%x ", APB_ADDR_WIDTH,APB_DATA_WIDTH,STRB_LEN), + UVM_DEBUG) +end +`endif + + // Config value to determine if this is an initiator or a responder + uvmf_initiator_responder_t initiator_responder; + // Custom configuration variables. + // These are set using the configure function which is called during the UVM connect_phase + + logic pclk_i; + logic presetn_i; + + // Signal list (all signals are capable of being inputs and outputs for the sake + // of supporting both INITIATOR and RESPONDER mode operation. Expectation is that + // directionality in the config file was from the point-of-view of the INITIATOR + + // INITIATOR mode input signals + tri [APB_DATA_WIDTH-1:0] prdata_i; + reg [APB_DATA_WIDTH-1:0] prdata_o = 'b0; + tri pready_i; + reg pready_o = 0; + tri pslverr_i; + reg pslverr_o = 0; + + // INITIATOR mode output signals + tri [15:0] psel_i; + reg [15:0] psel_o = 'b0; + tri penable_i; + reg penable_o = 'b0; + tri [APB_ADDR_WIDTH-1:0] paddr_i; + reg [APB_ADDR_WIDTH-1:0] paddr_o = 'b0; + tri [APB_DATA_WIDTH-1:0] pwdata_i; + reg [APB_DATA_WIDTH-1:0] pwdata_o = 'b0; + tri pwrite_i; + reg pwrite_o = 'b0; + tri [STRB_LEN-1:0] pstrb_i; + reg [STRB_LEN-1:0] pstrb_o = 'b0; + tri [2:0] pprot_i; + reg [2:0] pprot_o = 'b0; + + // Bi-directional signals + + + assign pclk_i = bus.pclk; + assign presetn_i = bus.presetn; + + // These are signals marked as 'input' by the config file, but the signals will be + // driven by this BFM if put into RESPONDER mode (flipping all signal directions around) + assign prdata_i = bus.prdata; + assign bus.prdata = (initiator_responder == RESPONDER) ? prdata_o : 'bz; + assign pready_i = bus.pready; + assign bus.pready = (initiator_responder == RESPONDER) ? pready_o : 'bz; + assign pslverr_i = bus.pslverr; + assign bus.pslverr = (initiator_responder == RESPONDER) ? pslverr_o : 'bz; + + + // These are signals marked as 'output' by the config file, but the outputs will + // not be driven by this BFM unless placed in INITIATOR mode. + assign bus.psel = (initiator_responder == INITIATOR) ? psel_o : 'bz; + assign psel_i = bus.psel; + assign bus.penable = (initiator_responder == INITIATOR) ? penable_o : 'bz; + assign penable_i = bus.penable; + assign bus.paddr = (initiator_responder == INITIATOR) ? paddr_o : 'bz; + assign paddr_i = bus.paddr; + assign bus.pwdata = (initiator_responder == INITIATOR) ? pwdata_o : 'bz; + assign pwdata_i = bus.pwdata; + assign bus.pwrite = (initiator_responder == INITIATOR) ? pwrite_o : 'bz; + assign pwrite_i = bus.pwrite; + assign bus.pstrb = (initiator_responder == INITIATOR) ? pstrb_o : 'bz; + assign pstrb_i = bus.pstrb; + assign bus.pprot = (initiator_responder == INITIATOR) ? pprot_o : 'bz; + assign pprot_i = bus.pprot; + + // Proxy handle to UVM driver + apb_m_pkg::apb_m_driver #( + .APB_ADDR_WIDTH(APB_ADDR_WIDTH), + .APB_DATA_WIDTH(APB_DATA_WIDTH), + .STRB_LEN(STRB_LEN) + ) proxy; + // pragma tbx oneway proxy.my_function_name_in_uvm_driver + + // **************************************************************************** + // **************************************************************************** + // Macros that define structs located in apb_m_macros.svh + // **************************************************************************** + // Struct for passing configuration data from apb_m_driver to this BFM + // **************************************************************************** + `apb_m_CONFIGURATION_STRUCT + // **************************************************************************** + // Structs for INITIATOR and RESPONDER data flow + //******************************************************************* + // Initiator macro used by apb_m_driver and apb_m_driver_bfm + // to communicate initiator driven data to apb_m_driver_bfm. + `apb_m_INITIATOR_STRUCT + apb_m_initiator_s initiator_struct; + // Responder macro used by apb_m_driver and apb_m_driver_bfm + // to communicate Responder driven data to apb_m_driver_bfm. + `apb_m_RESPONDER_STRUCT + apb_m_responder_s responder_struct; + + // **************************************************************************** +// pragma uvmf custom reset_condition_and_response begin + // Always block used to return signals to reset value upon assertion of reset + always @( negedge presetn_i ) + begin + // RESPONDER mode output signals + prdata_o <= 'b0; + pready_o <= 0; + pslverr_o <= 0; + // INITIATOR mode output signals + psel_o <= 'b0; + penable_o <= 'b0; + paddr_o <= 'b0; + pwdata_o <= 'b0; + pwrite_o <= 'b0; + pstrb_o <= 'b0; + pprot_o <= 'b0; + // Bi-directional signals + + end +// pragma uvmf custom reset_condition_and_response end + + // pragma uvmf custom interface_item_additional begin + // pragma uvmf custom interface_item_additional end + + //****************************************************************** + // The configure() function is used to pass agent configuration + // variables to the driver BFM. It is called by the driver within + // the agent at the beginning of the simulation. It may be called + // during the simulation if agent configuration variables are updated + // and the driver BFM needs to be aware of the new configuration + // variables. + // + + function void configure(apb_m_configuration_s apb_m_configuration_arg); // pragma tbx xtf + initiator_responder = apb_m_configuration_arg.initiator_responder; + // pragma uvmf custom configure begin + // pragma uvmf custom configure end + endfunction + +// pragma uvmf custom initiate_and_get_response begin +// **************************************************************************** +// UVMF_CHANGE_ME +// This task is used by an initator. The task first initiates a transfer then +// waits for the responder to complete the transfer. + task initiate_and_get_response( + // This argument passes transaction variables used by an initiator + // to perform the initial part of a protocol transfer. The values + // come from a sequence item created in a sequence. + input apb_m_initiator_s apb_m_initiator_struct, + // This argument is used to send data received from the responder + // back to the sequence item. The sequence item is returned to the sequence. + output apb_m_responder_s apb_m_responder_struct + );// pragma tbx xtf + // + // Members within the apb_m_initiator_struct: + // bit psel ; + // bit penable ; + // bit [APB_ADDR_WIDTH-1:0] paddr ; + // bit [APB_DATA_WIDTH-1:0] pwdata ; + // bit pwrite ; + // bit [STRB_LEN:0] pstrb ; + // bit [3:0] pprot ; + // bit [APB_DATA_WIDTH-1:0] prdata ; + // bit pready ; + // bit pslverr ; + // Members within the apb_m_responder_struct: + // bit psel ; + // bit penable ; + // bit [APB_ADDR_WIDTH-1:0] paddr ; + // bit [APB_DATA_WIDTH-1:0] pwdata ; + // bit pwrite ; + // bit [STRB_LEN:0] pstrb ; + // bit [3:0] pprot ; + // bit [APB_DATA_WIDTH-1:0] prdata ; + // bit pready ; + // bit pslverr ; + initiator_struct = apb_m_initiator_struct; + // + // Reference code; + // How to wait for signal value + // while (control_signal == 1'b1) @(posedge pclk_i); + // + // How to assign a responder struct member, named xyz, from a signal. + // All available initiator input and inout signals listed. + // Initiator input signals + // apb_m_responder_struct.xyz = prdata_i; // [APB_DATA_WIDTH-1:0] + // apb_m_responder_struct.xyz = pready_i; // + // apb_m_responder_struct.xyz = pslverr_i; // + // Initiator inout signals + // How to assign a signal from an initiator struct member named xyz. + // All available initiator output and inout signals listed. + // Notice the _o. Those are storage variables that allow for procedural assignment. + // Initiator output signals + // psel_o <= apb_m_initiator_struct.xyz; // [15:0] + // penable_o <= apb_m_initiator_struct.xyz; // + // paddr_o <= apb_m_initiator_struct.xyz; // [APB_ADDR_WIDTH-1:0] + // pwdata_o <= apb_m_initiator_struct.xyz; // [APB_DATA_WIDTH-1:0] + // pwrite_o <= apb_m_initiator_struct.xyz; // + // pstrb_o <= apb_m_initiator_struct.xyz; // [STRB_LEN-1:0] + // pprot_o <= apb_m_initiator_struct.xyz; // [2:0] + // Initiator inout signals + // Initiate a transfer using the data received. + @(posedge pclk_i); + @(posedge pclk_i); + // Wait for the responder to complete the transfer then place the responder data into + // apb_m_responder_struct. + @(posedge pclk_i); + @(posedge pclk_i); + responder_struct = apb_m_responder_struct; + endtask +// pragma uvmf custom initiate_and_get_response end + +// pragma uvmf custom respond_and_wait_for_next_transfer begin +// **************************************************************************** +// The first_transfer variable is used to prevent completing a transfer in the +// first call to this task. For the first call to this task, there is not +// current transfer to complete. +bit first_transfer=1; + +// UVMF_CHANGE_ME +// This task is used by a responder. The task first completes the current +// transfer in progress then waits for the initiator to start the next transfer. + task respond_and_wait_for_next_transfer( + // This argument is used to send data received from the initiator + // back to the sequence item. The sequence determines how to respond. + output apb_m_initiator_s apb_m_initiator_struct, + // This argument passes transaction variables used by a responder + // to complete a protocol transfer. The values come from a sequence item. + input apb_m_responder_s apb_m_responder_struct + );// pragma tbx xtf + // Variables within the apb_m_initiator_struct: + // bit psel ; + // bit penable ; + // bit [APB_ADDR_WIDTH-1:0] paddr ; + // bit [APB_DATA_WIDTH-1:0] pwdata ; + // bit pwrite ; + // bit [STRB_LEN:0] pstrb ; + // bit [3:0] pprot ; + // bit [APB_DATA_WIDTH-1:0] prdata ; + // bit pready ; + // bit pslverr ; + // Variables within the apb_m_responder_struct: + // bit psel ; + // bit penable ; + // bit [APB_ADDR_WIDTH-1:0] paddr ; + // bit [APB_DATA_WIDTH-1:0] pwdata ; + // bit pwrite ; + // bit [STRB_LEN:0] pstrb ; + // bit [3:0] pprot ; + // bit [APB_DATA_WIDTH-1:0] prdata ; + // bit pready ; + // bit pslverr ; + // Reference code; + // How to wait for signal value + // while (control_signal == 1'b1) @(posedge pclk_i); + // + // How to assign a responder struct member, named xyz, from a signal. + // All available responder input and inout signals listed. + // Responder input signals + // apb_m_responder_struct.xyz = psel_i; // [15:0] + // apb_m_responder_struct.xyz = penable_i; // + // apb_m_responder_struct.xyz = paddr_i; // [APB_ADDR_WIDTH-1:0] + // apb_m_responder_struct.xyz = pwdata_i; // [APB_DATA_WIDTH-1:0] + // apb_m_responder_struct.xyz = pwrite_i; // + // apb_m_responder_struct.xyz = pstrb_i; // [STRB_LEN-1:0] + // apb_m_responder_struct.xyz = pprot_i; // [2:0] + // Responder inout signals + // How to assign a signal, named xyz, from an initiator struct member. + // All available responder output and inout signals listed. + // Notice the _o. Those are storage variables that allow for procedural assignment. + // Responder output signals + // prdata_o <= apb_m_initiator_struct.xyz; // [APB_DATA_WIDTH-1:0] + // pready_o <= apb_m_initiator_struct.xyz; // + // pslverr_o <= apb_m_initiator_struct.xyz; // + // Responder inout signals + + @(posedge pclk_i); + if (!first_transfer) begin + // Perform transfer response here. + // Reply using data recieved in the apb_m_responder_struct. + @(posedge pclk_i); + // Reply using data recieved in the transaction handle. + @(posedge pclk_i); + end + // Wait for next transfer then gather info from intiator about the transfer. + // Place the data into the apb_m_initiator_struct. + @(posedge pclk_i); + @(posedge pclk_i); + first_transfer = 0; + endtask +// pragma uvmf custom respond_and_wait_for_next_transfer end + + +endinterface + +// pragma uvmf custom external begin +// pragma uvmf custom external end +`endif diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/apb_m_pkg/src/apb_m_if.sv b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/apb_m_pkg/src/apb_m_if.sv new file mode 100644 index 00000000..73bb7f1a --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/apb_m_pkg/src/apb_m_if.sv @@ -0,0 +1,115 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This interface contains the apb_m interface signals. +// It is instantiated once per apb_m bus. Bus Functional Models, +// BFM's named apb_m_driver_bfm, are used to drive signals on the bus. +// BFM's named apb_m_monitor_bfm are used to monitor signals on the +// bus. This interface signal bundle is passed in the port list of +// the BFM in order to give the BFM access to the signals in this +// interface. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +`ifndef APB_M_IF +`define APB_M_IF +// This template can be used to connect a DUT to these signals +// +// .dut_signal_port(apb_m_bus.psel), // Agent output +// .dut_signal_port(apb_m_bus.penable), // Agent output +// .dut_signal_port(apb_m_bus.paddr), // Agent output +// .dut_signal_port(apb_m_bus.pwdata), // Agent output +// .dut_signal_port(apb_m_bus.pwrite), // Agent output +// .dut_signal_port(apb_m_bus.pstrb), // Agent output +// .dut_signal_port(apb_m_bus.pprot), // Agent output +// .dut_signal_port(apb_m_bus.prdata), // Agent input +// .dut_signal_port(apb_m_bus.pready), // Agent input +// .dut_signal_port(apb_m_bus.pslverr), // Agent input + +import uvmf_base_pkg_hdl::*; +import apb_m_pkg_hdl::*; + +interface apb_m_if #( + int APB_ADDR_WIDTH = 32, + int APB_DATA_WIDTH = 32, + int STRB_LEN = APB_ADDR_WIDTH/8 + ) + + ( + input logic pclk, + input logic presetn, + output logic [15:0] psel, + output logic penable, + output logic [APB_ADDR_WIDTH-1:0] paddr, + output logic [APB_DATA_WIDTH-1:0] pwdata, + output logic pwrite, + output logic [STRB_LEN-1:0] pstrb, + output logic [2:0] pprot, + input logic [APB_DATA_WIDTH-1:0] prdata, + input logic pready, + input logic pslverr + ); + +modport monitor_port + ( + input pclk, + input presetn, + input psel, + input penable, + input paddr, + input pwdata, + input pwrite, + input pstrb, + input pprot, + input prdata, + input pready, + input pslverr + ); + +modport initiator_port + ( + input pclk, + input presetn, + output psel, + output penable, + output paddr, + output pwdata, + output pwrite, + output pstrb, + output pprot, + input prdata, + input pready, + input pslverr + ); + +modport responder_port + ( + input pclk, + input presetn, + input psel, + input penable, + input paddr, + input pwdata, + input pwrite, + input pstrb, + input pprot, + output prdata, + output pready, + output pslverr + ); + + +// pragma uvmf custom interface_item_additional begin +// pragma uvmf custom interface_item_additional end + +endinterface + +// pragma uvmf custom external begin +// pragma uvmf custom external end +`endif diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/apb_m_pkg/src/apb_m_infact_coverage_strategy.csv b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/apb_m_pkg/src/apb_m_infact_coverage_strategy.csv new file mode 100644 index 00000000..1c218e14 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/apb_m_pkg/src/apb_m_infact_coverage_strategy.csv @@ -0,0 +1,6 @@ +Global +auto_bin_max, 64 + +Name,Type,Include +rand_fields,coverpoint,=rand *.** + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/apb_m_pkg/src/apb_m_macros.svh b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/apb_m_pkg/src/apb_m_macros.svh new file mode 100644 index 00000000..631c4b12 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/apb_m_pkg/src/apb_m_macros.svh @@ -0,0 +1,202 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This file contains macros used with the apb_m package. +// These macros include packed struct definitions. These structs are +// used to pass data between classes, hvl, and BFM's, hdl. Use of +// structs are more efficient and simpler to modify. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// + +// **************************************************************************** +// When changing the contents of this struct, be sure to update the to_struct +// and from_struct methods defined in the macros below that are used in +// the apb_m_configuration class. +// + `define apb_m_CONFIGURATION_STRUCT \ +typedef struct packed { \ + uvmf_active_passive_t active_passive; \ + uvmf_initiator_responder_t initiator_responder; \ + } apb_m_configuration_s; + + `define apb_m_CONFIGURATION_TO_STRUCT_FUNCTION \ + virtual function apb_m_configuration_s to_struct();\ + apb_m_configuration_struct = \ + {\ + this.active_passive,\ + this.initiator_responder\ + };\ + return ( apb_m_configuration_struct );\ + endfunction + + `define apb_m_CONFIGURATION_FROM_STRUCT_FUNCTION \ + virtual function void from_struct(apb_m_configuration_s apb_m_configuration_struct);\ + {\ + this.active_passive,\ + this.initiator_responder \ + } = apb_m_configuration_struct;\ + endfunction + +// **************************************************************************** +// When changing the contents of this struct, be sure to update the to_monitor_struct +// and from_monitor_struct methods of the apb_m_transaction class. +// + `define apb_m_MONITOR_STRUCT typedef struct packed { \ + bit psel ; \ + bit penable ; \ + bit [APB_ADDR_WIDTH-1:0] paddr ; \ + bit [APB_DATA_WIDTH-1:0] pwdata ; \ + bit pwrite ; \ + bit [STRB_LEN:0] pstrb ; \ + bit [3:0] pprot ; \ + bit [APB_DATA_WIDTH-1:0] prdata ; \ + bit pready ; \ + bit pslverr ; \ + } apb_m_monitor_s; + + `define apb_m_TO_MONITOR_STRUCT_FUNCTION \ + virtual function apb_m_monitor_s to_monitor_struct();\ + apb_m_monitor_struct = \ + { \ + this.psel , \ + this.penable , \ + this.paddr , \ + this.pwdata , \ + this.pwrite , \ + this.pstrb , \ + this.pprot , \ + this.prdata , \ + this.pready , \ + this.pslverr \ + };\ + return ( apb_m_monitor_struct);\ + endfunction\ + + `define apb_m_FROM_MONITOR_STRUCT_FUNCTION \ + virtual function void from_monitor_struct(apb_m_monitor_s apb_m_monitor_struct);\ + {\ + this.psel , \ + this.penable , \ + this.paddr , \ + this.pwdata , \ + this.pwrite , \ + this.pstrb , \ + this.pprot , \ + this.prdata , \ + this.pready , \ + this.pslverr \ + } = apb_m_monitor_struct;\ + endfunction + +// **************************************************************************** +// When changing the contents of this struct, be sure to update the to_initiator_struct +// and from_initiator_struct methods of the apb_m_transaction class. +// Also update the comments in the driver BFM. +// + `define apb_m_INITIATOR_STRUCT typedef struct packed { \ + bit psel ; \ + bit penable ; \ + bit [APB_ADDR_WIDTH-1:0] paddr ; \ + bit [APB_DATA_WIDTH-1:0] pwdata ; \ + bit pwrite ; \ + bit [STRB_LEN:0] pstrb ; \ + bit [3:0] pprot ; \ + bit [APB_DATA_WIDTH-1:0] prdata ; \ + bit pready ; \ + bit pslverr ; \ + } apb_m_initiator_s; + + `define apb_m_TO_INITIATOR_STRUCT_FUNCTION \ + virtual function apb_m_initiator_s to_initiator_struct();\ + apb_m_initiator_struct = \ + {\ + this.psel , \ + this.penable , \ + this.paddr , \ + this.pwdata , \ + this.pwrite , \ + this.pstrb , \ + this.pprot , \ + this.prdata , \ + this.pready , \ + this.pslverr \ + };\ + return ( apb_m_initiator_struct);\ + endfunction + + `define apb_m_FROM_INITIATOR_STRUCT_FUNCTION \ + virtual function void from_initiator_struct(apb_m_initiator_s apb_m_initiator_struct);\ + {\ + this.psel , \ + this.penable , \ + this.paddr , \ + this.pwdata , \ + this.pwrite , \ + this.pstrb , \ + this.pprot , \ + this.prdata , \ + this.pready , \ + this.pslverr \ + } = apb_m_initiator_struct;\ + endfunction + +// **************************************************************************** +// When changing the contents of this struct, be sure to update the to_responder_struct +// and from_responder_struct methods of the apb_m_transaction class. +// Also update the comments in the driver BFM. +// + `define apb_m_RESPONDER_STRUCT typedef struct packed { \ + bit psel ; \ + bit penable ; \ + bit [APB_ADDR_WIDTH-1:0] paddr ; \ + bit [APB_DATA_WIDTH-1:0] pwdata ; \ + bit pwrite ; \ + bit [STRB_LEN:0] pstrb ; \ + bit [3:0] pprot ; \ + bit [APB_DATA_WIDTH-1:0] prdata ; \ + bit pready ; \ + bit pslverr ; \ + } apb_m_responder_s; + + `define apb_m_TO_RESPONDER_STRUCT_FUNCTION \ + virtual function apb_m_responder_s to_responder_struct();\ + apb_m_responder_struct = \ + {\ + this.psel , \ + this.penable , \ + this.paddr , \ + this.pwdata , \ + this.pwrite , \ + this.pstrb , \ + this.pprot , \ + this.prdata , \ + this.pready , \ + this.pslverr \ + };\ + return ( apb_m_responder_struct);\ + endfunction + + `define apb_m_FROM_RESPONDER_STRUCT_FUNCTION \ + virtual function void from_responder_struct(apb_m_responder_s apb_m_responder_struct);\ + {\ + this.psel , \ + this.penable , \ + this.paddr , \ + this.pwdata , \ + this.pwrite , \ + this.pstrb , \ + this.pprot , \ + this.prdata , \ + this.pready , \ + this.pslverr \ + } = apb_m_responder_struct;\ + endfunction +// pragma uvmf custom additional begin +// pragma uvmf custom additional end diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/apb_m_pkg/src/apb_m_monitor.svh b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/apb_m_pkg/src/apb_m_monitor.svh new file mode 100644 index 00000000..34c10bc9 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/apb_m_pkg/src/apb_m_monitor.svh @@ -0,0 +1,109 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This class receives apb_m transactions observed by the +// apb_m monitor BFM and broadcasts them through the analysis port +// on the agent. It accesses the monitor BFM through the monitor +// task. This UVM component captures transactions +// for viewing in the waveform viewer if the +// enable_transaction_viewing flag is set in the configuration. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +`ifndef APB_M_MONITOR +`define APB_M_MONITOR +class apb_m_monitor #( + int APB_ADDR_WIDTH = 32, + int APB_DATA_WIDTH = 32, + int STRB_LEN = APB_ADDR_WIDTH/8 + ) extends uvmf_monitor_base #( + .CONFIG_T(apb_m_configuration #( + .APB_ADDR_WIDTH(APB_ADDR_WIDTH), + .APB_DATA_WIDTH(APB_DATA_WIDTH), + .STRB_LEN(STRB_LEN) + )), + .BFM_BIND_T(virtual apb_m_monitor_bfm #( + .APB_ADDR_WIDTH(APB_ADDR_WIDTH), + .APB_DATA_WIDTH(APB_DATA_WIDTH), + .STRB_LEN(STRB_LEN) + )), + .TRANS_T(apb_m_transaction #( + .APB_ADDR_WIDTH(APB_ADDR_WIDTH), + .APB_DATA_WIDTH(APB_DATA_WIDTH), + .STRB_LEN(STRB_LEN) + ))); + + `uvm_component_param_utils( apb_m_monitor #( + APB_ADDR_WIDTH, + APB_DATA_WIDTH, + STRB_LEN + )) + +// Structure used to pass data from monitor BFM to monitor class in agent. +// Use to_monitor_struct function to pack transaction variables into structure. +// Use from_monitor_struct function to unpack transaction variables from structure. +`apb_m_MONITOR_STRUCT + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + +// **************************************************************************** +// This function is the standard SystemVerilog constructor. +// + function new( string name = "", uvm_component parent = null ); + super.new( name, parent ); + endfunction + +// **************************************************************************** +// This function sends configuration object variables to the monitor BFM +// using the configuration struct. +// + virtual function void configure(input CONFIG_T cfg); + bfm.configure( cfg.to_struct() ); + + endfunction + +// **************************************************************************** +// This function places a handle to this class in the proxy variable in the +// monitor BFM. This allows the monitor BFM to call the notify_transaction +// function within this class. +// + virtual function void set_bfm_proxy_handle(); + bfm.proxy = this; endfunction + +// *************************************************************************** + virtual task run_phase(uvm_phase phase); + // Start monitor BFM thread and don't call super.run() in order to + // override the default monitor proxy 'pull' behavior with the more + // emulation-friendly BFM 'push' approach using the notify_transaction + // function below + bfm.start_monitoring(); + endtask + +// ************************************************************************** + +// This function is called by the monitor BFM. It receives data observed by the +// monitor BFM. Data is passed using the apb_m_monitor_struct. + virtual function void notify_transaction(input apb_m_monitor_s apb_m_monitor_struct); + + + trans = new("trans"); + trans.from_monitor_struct(apb_m_monitor_struct); + trans.start_time = time_stamp; + trans.end_time = $time; + time_stamp = trans.end_time; + + analyze(trans); + endfunction + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end +`endif diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/apb_m_pkg/src/apb_m_monitor_bfm.sv b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/apb_m_pkg/src/apb_m_monitor_bfm.sv new file mode 100644 index 00000000..14d98dba --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/apb_m_pkg/src/apb_m_monitor_bfm.sv @@ -0,0 +1,220 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This interface performs the apb_m signal monitoring. +// It is accessed by the uvm apb_m monitor through a virtual +// interface handle in the apb_m configuration. It monitors the +// signals passed in through the port connection named bus of +// type apb_m_if. +// +// Input signals from the apb_m_if are assigned to an internal input +// signal with a _i suffix. The _i signal should be used for sampling. +// +// The input signal connections are as follows: +// bus.signal -> signal_i +// +// Interface functions and tasks used by UVM components: +// monitor(inout TRANS_T txn); +// This task receives the transaction, txn, from the +// UVM monitor and then populates variables in txn +// from values observed on bus activity. This task +// blocks until an operation on the apb_m bus is complete. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +`ifndef APB_M_MONITOR_BFM +`define APB_M_MONITOR_BFM +import uvmf_base_pkg_hdl::*; +import apb_m_pkg_hdl::*; +`include "src/apb_m_macros.svh" + + +interface apb_m_monitor_bfm #( + int APB_ADDR_WIDTH = 32, + int APB_DATA_WIDTH = 32, + int STRB_LEN = APB_ADDR_WIDTH/8 + ) + ( apb_m_if bus ); + // The pragma below and additional ones in-lined further down are for running this BFM on Veloce + // pragma attribute apb_m_monitor_bfm partition_interface_xif + +`ifndef XRTL +// This code is to aid in debugging parameter mismatches between the BFM and its corresponding agent. +// Enable this debug by setting UVM_VERBOSITY to UVM_DEBUG +// Setting UVM_VERBOSITY to UVM_DEBUG causes all BFM's and all agents to display their parameter settings. +// All of the messages from this feature have a UVM messaging id value of "CFG" +// The transcript or run.log can be parsed to ensure BFM parameter settings match its corresponding agents parameter settings. +import uvm_pkg::*; +`include "uvm_macros.svh" +initial begin : bfm_vs_agent_parameter_debug + `uvm_info("CFG", + $psprintf("The BFM at '%m' has the following parameters: APB_ADDR_WIDTH=%x APB_DATA_WIDTH=%x STRB_LEN=%x ", APB_ADDR_WIDTH,APB_DATA_WIDTH,STRB_LEN), + UVM_DEBUG) +end +`endif + + + // Structure used to pass transaction data from monitor BFM to monitor class in agent. +`apb_m_MONITOR_STRUCT + apb_m_monitor_s apb_m_monitor_struct; + + // Structure used to pass configuration data from monitor class to monitor BFM. + `apb_m_CONFIGURATION_STRUCT + + + // Config value to determine if this is an initiator or a responder + uvmf_initiator_responder_t initiator_responder; + // Custom configuration variables. + // These are set using the configure function which is called during the UVM connect_phase + + logic pclk_i; + logic presetn_i; + tri [15:0] psel_i; + tri penable_i; + tri [APB_ADDR_WIDTH-1:0] paddr_i; + tri [APB_DATA_WIDTH-1:0] pwdata_i; + tri pwrite_i; + tri [STRB_LEN-1:0] pstrb_i; + tri [2:0] pprot_i; + tri [APB_DATA_WIDTH-1:0] prdata_i; + tri pready_i; + tri pslverr_i; + assign pclk_i = bus.pclk; + assign presetn_i = bus.presetn; + assign psel_i = bus.psel; + assign penable_i = bus.penable; + assign paddr_i = bus.paddr; + assign pwdata_i = bus.pwdata; + assign pwrite_i = bus.pwrite; + assign pstrb_i = bus.pstrb; + assign pprot_i = bus.pprot; + assign prdata_i = bus.prdata; + assign pready_i = bus.pready; + assign pslverr_i = bus.pslverr; + + // Proxy handle to UVM monitor + apb_m_pkg::apb_m_monitor #( + .APB_ADDR_WIDTH(APB_ADDR_WIDTH), + .APB_DATA_WIDTH(APB_DATA_WIDTH), + .STRB_LEN(STRB_LEN) + ) proxy; + // pragma tbx oneway proxy.notify_transaction + + // pragma uvmf custom interface_item_additional begin + // pragma uvmf custom interface_item_additional end + + //****************************************************************** + task wait_for_reset();// pragma tbx xtf + @(posedge pclk_i) ; + do_wait_for_reset(); + endtask + + // **************************************************************************** + task do_wait_for_reset(); + // pragma uvmf custom reset_condition begin + wait ( presetn_i === 1 ) ; + @(posedge pclk_i) ; + // pragma uvmf custom reset_condition end + endtask + + //****************************************************************** + + task wait_for_num_clocks(input int unsigned count); // pragma tbx xtf + @(posedge pclk_i); + + repeat (count-1) @(posedge pclk_i); + endtask + + //****************************************************************** + event go; + function void start_monitoring();// pragma tbx xtf + -> go; + endfunction + + // **************************************************************************** + initial begin + @go; + forever begin + @(posedge pclk_i); + do_monitor( apb_m_monitor_struct ); + + + proxy.notify_transaction( apb_m_monitor_struct ); + + end + end + + //****************************************************************** + // The configure() function is used to pass agent configuration + // variables to the monitor BFM. It is called by the monitor within + // the agent at the beginning of the simulation. It may be called + // during the simulation if agent configuration variables are updated + // and the monitor BFM needs to be aware of the new configuration + // variables. + // + function void configure(apb_m_configuration_s apb_m_configuration_arg); // pragma tbx xtf + initiator_responder = apb_m_configuration_arg.initiator_responder; + // pragma uvmf custom configure begin + // pragma uvmf custom configure end + endfunction + + + // **************************************************************************** + + task do_monitor(output apb_m_monitor_s apb_m_monitor_struct); + // + // Available struct members: + // // apb_m_monitor_struct.psel + // // apb_m_monitor_struct.penable + // // apb_m_monitor_struct.paddr + // // apb_m_monitor_struct.pwdata + // // apb_m_monitor_struct.pwrite + // // apb_m_monitor_struct.pstrb + // // apb_m_monitor_struct.pprot + // // apb_m_monitor_struct.prdata + // // apb_m_monitor_struct.pready + // // apb_m_monitor_struct.pslverr + // // + // Reference code; + // How to wait for signal value + // while (control_signal === 1'b1) @(posedge pclk_i); + // + // How to assign a struct member, named xyz, from a signal. + // All available input signals listed. + // apb_m_monitor_struct.xyz = psel_i; // [15:0] + // apb_m_monitor_struct.xyz = penable_i; // + // apb_m_monitor_struct.xyz = paddr_i; // [APB_ADDR_WIDTH-1:0] + // apb_m_monitor_struct.xyz = pwdata_i; // [APB_DATA_WIDTH-1:0] + // apb_m_monitor_struct.xyz = pwrite_i; // + // apb_m_monitor_struct.xyz = pstrb_i; // [STRB_LEN-1:0] + // apb_m_monitor_struct.xyz = pprot_i; // [2:0] + // apb_m_monitor_struct.xyz = prdata_i; // [APB_DATA_WIDTH-1:0] + // apb_m_monitor_struct.xyz = pready_i; // + // apb_m_monitor_struct.xyz = pslverr_i; // + // pragma uvmf custom do_monitor begin + // UVMF_CHANGE_ME : Implement protocol monitoring. The commented reference code + // below are examples of how to capture signal values and assign them to + // structure members. All available input signals are listed. The 'while' + // code example shows how to wait for a synchronous flow control signal. This + // task should return when a complete transfer has been observed. Once this task is + // exited with captured values, it is then called again to wait for and observe + // the next transfer. One clock cycle is consumed between calls to do_monitor. + @(posedge pclk_i); + @(posedge pclk_i); + @(posedge pclk_i); + @(posedge pclk_i); + // pragma uvmf custom do_monitor end + endtask + + +endinterface + +// pragma uvmf custom external begin +// pragma uvmf custom external end +`endif diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/apb_m_pkg/src/apb_m_random_sequence.svh b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/apb_m_pkg/src/apb_m_random_sequence.svh new file mode 100644 index 00000000..952caae6 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/apb_m_pkg/src/apb_m_random_sequence.svh @@ -0,0 +1,71 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: +// This sequences randomizes the apb_m transaction and sends it +// to the UVM driver. +// +// This sequence constructs and randomizes a apb_m_transaction. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +`ifndef APB_M_RANDOM_SEQUENCE +`define APB_M_RANDOM_SEQUENCE +class apb_m_random_sequence #( + int APB_ADDR_WIDTH = 32, + int APB_DATA_WIDTH = 32, + int STRB_LEN = APB_ADDR_WIDTH/8 + ) + extends apb_m_sequence_base #( + .APB_ADDR_WIDTH(APB_ADDR_WIDTH), + .APB_DATA_WIDTH(APB_DATA_WIDTH), + .STRB_LEN(STRB_LEN) + ); + + `uvm_object_param_utils( apb_m_random_sequence #( + APB_ADDR_WIDTH, + APB_DATA_WIDTH, + STRB_LEN + )) + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + //***************************************************************** + function new(string name = ""); + super.new(name); + endfunction: new + + // **************************************************************************** + // TASK : body() + // This task is automatically executed when this sequence is started using the + // start(sequencerHandle) task. + // + task body(); + + // Construct the transaction + req=apb_m_transaction#( + .APB_ADDR_WIDTH(APB_ADDR_WIDTH), + .APB_DATA_WIDTH(APB_DATA_WIDTH), + .STRB_LEN(STRB_LEN) + )::type_id::create("req"); + start_item(req); + // Randomize the transaction + if(!req.randomize()) `uvm_fatal("SEQ", "apb_m_random_sequence::body()-apb_m_transaction randomization failed") + // Send the transaction to the apb_m_driver_bfm via the sequencer and apb_m_driver. + finish_item(req); + `uvm_info("SEQ", {"Response:",req.convert2string()},UVM_MEDIUM) + + endtask + +endclass: apb_m_random_sequence + +// pragma uvmf custom external begin +// pragma uvmf custom external end +`endif diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/apb_m_pkg/src/apb_m_responder_sequence.svh b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/apb_m_pkg/src/apb_m_responder_sequence.svh new file mode 100644 index 00000000..fe00375b --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/apb_m_pkg/src/apb_m_responder_sequence.svh @@ -0,0 +1,67 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This class can be used to provide stimulus when an interface +// has been configured to run in a responder mode. It +// will never finish by default, always going back to the driver +// and driver BFM for the next transaction with which to respond. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +`ifndef APB_M_RESPONDER_SEQUENCE +`define APB_M_RESPONDER_SEQUENCE +class apb_m_responder_sequence #( + int APB_ADDR_WIDTH = 32, + int APB_DATA_WIDTH = 32, + int STRB_LEN = APB_ADDR_WIDTH/8 + ) + extends apb_m_sequence_base #( + .APB_ADDR_WIDTH(APB_ADDR_WIDTH), + .APB_DATA_WIDTH(APB_DATA_WIDTH), + .STRB_LEN(STRB_LEN) + ); + + `uvm_object_param_utils( apb_m_responder_sequence #( + APB_ADDR_WIDTH, + APB_DATA_WIDTH, + STRB_LEN + )) + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + function new(string name = "apb_m_responder_sequence"); + super.new(name); + endfunction + + task body(); + req=apb_m_transaction#( + .APB_ADDR_WIDTH(APB_ADDR_WIDTH), + .APB_DATA_WIDTH(APB_DATA_WIDTH), + .STRB_LEN(STRB_LEN) + )::type_id::create("req"); + forever begin + start_item(req); + finish_item(req); + // pragma uvmf custom body begin + // UVMF_CHANGE_ME : Do something here with the resulting req item. The + // finish_item() call above will block until the req transaction is ready + // to be handled by the responder sequence. + // If this was an item that required a response, the expectation is + // that the response should be populated within this transaction now. + `uvm_info("SEQ",$sformatf("Processed txn: %s",req.convert2string()),UVM_HIGH) + // pragma uvmf custom body end + end + endtask + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end +`endif diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/apb_m_pkg/src/apb_m_sequence_base.svh b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/apb_m_pkg/src/apb_m_sequence_base.svh new file mode 100644 index 00000000..16023c3e --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/apb_m_pkg/src/apb_m_sequence_base.svh @@ -0,0 +1,122 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: +// This file contains the class used as the base class for all sequences +// for this interface. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +`ifndef APB_M_SEQUENCE_BASE +`define APB_M_SEQUENCE_BASE +class apb_m_sequence_base #( + int APB_ADDR_WIDTH = 32, + int APB_DATA_WIDTH = 32, + int STRB_LEN = APB_ADDR_WIDTH/8 + ) extends uvmf_sequence_base #( + .REQ(apb_m_transaction #( + .APB_ADDR_WIDTH(APB_ADDR_WIDTH), + .APB_DATA_WIDTH(APB_DATA_WIDTH), + .STRB_LEN(STRB_LEN) + )), + .RSP(apb_m_transaction #( + .APB_ADDR_WIDTH(APB_ADDR_WIDTH), + .APB_DATA_WIDTH(APB_DATA_WIDTH), + .STRB_LEN(STRB_LEN) + ))); + + `uvm_object_param_utils( apb_m_sequence_base #( + APB_ADDR_WIDTH, + APB_DATA_WIDTH, + STRB_LEN + )) + + // variables + typedef apb_m_transaction #( + .APB_ADDR_WIDTH(APB_ADDR_WIDTH), + .APB_DATA_WIDTH(APB_DATA_WIDTH), + .STRB_LEN(STRB_LEN) + ) apb_m_transaction_req_t; + apb_m_transaction_req_t req; + typedef apb_m_transaction #( + .APB_ADDR_WIDTH(APB_ADDR_WIDTH), + .APB_DATA_WIDTH(APB_DATA_WIDTH), + .STRB_LEN(STRB_LEN) + ) apb_m_transaction_rsp_t; + apb_m_transaction_rsp_t rsp; + + // Event for identifying when a response was received from the sequencer + event new_rsp; + + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + // **************************************************************************** + // TASK : get_responses() + // This task recursively gets sequence item responses from the sequencer. + // + virtual task get_responses(); + fork + begin + // Block until new rsp available + get_response(rsp); + // New rsp received. Indicate to sequence using event. + ->new_rsp; + // Display the received response transaction + `uvm_info("SEQ", {"New response transaction:",rsp.convert2string()}, UVM_MEDIUM) + end + join_none + endtask + + // **************************************************************************** + // TASK : pre_body() + // This task is called automatically when start is called with call_pre_post set to 1 (default). + // By calling get_responses() within pre_body() any derived sequences are automatically + // processing response transactions. Only un-comment this call to get_responses() if you + // have configured the interface driver to utilize the response transaction path by setting + // the configuration variable "return_transaction_response" to 1. Otherwise it is possible + // to impact runtime performance and memory utilization. + // + virtual task pre_body(); + // pragma uvmf custom pre_body begin +// get_responses(); + // pragma uvmf custom pre_body end + endtask + + // **************************************************************************** + // TASK : body() + // This task is called automatically when start is called. This sequence sends + // a req sequence item to the sequencer identified as an argument in the call + // to start. + // + virtual task body(); + // pragma uvmf custom body begin + start_item(req); + finish_item(req); + // pragma uvmf custom body end + endtask + + // **************************************************************************** + // FUNCTION : new() + // This function is the standard SystemVerilog constructor. + // + function new( string name =""); + super.new( name ); + // pragma uvmf custom new begin + req = apb_m_transaction_req_t::type_id::create("req"); + rsp = apb_m_transaction_rsp_t::type_id::create("rsp"); + // pragma uvmf custom new end + endfunction + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end +`endif diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/apb_m_pkg/src/apb_m_transaction.svh b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/apb_m_pkg/src/apb_m_transaction.svh new file mode 100644 index 00000000..84640d6a --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/apb_m_pkg/src/apb_m_transaction.svh @@ -0,0 +1,235 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This class defines the variables required for an apb_m +// transaction. Class variables to be displayed in waveform transaction +// viewing are added to the transaction viewing stream in the add_to_wave +// function. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +`ifndef APB_M_TRANSACTION +`define APB_M_TRANSACTION +class apb_m_transaction #( + int APB_ADDR_WIDTH = 32, + int APB_DATA_WIDTH = 32, + int STRB_LEN = APB_ADDR_WIDTH/8 + ) extends uvmf_transaction_base; + + `uvm_object_param_utils( apb_m_transaction #( + APB_ADDR_WIDTH, + APB_DATA_WIDTH, + STRB_LEN + )) + + rand bit psel ; + rand bit penable ; + rand bit [APB_ADDR_WIDTH-1:0] paddr ; + rand bit [APB_DATA_WIDTH-1:0] pwdata ; + rand bit pwrite ; + rand bit [STRB_LEN:0] pstrb ; + rand bit [3:0] pprot ; + bit [APB_DATA_WIDTH-1:0] prdata ; + bit pready ; + bit pslverr ; + + //Constraints for the transaction variables: + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + //******************************************************************* + //******************************************************************* + // Macros that define structs and associated functions are + // located in apb_m_macros.svh + + //******************************************************************* + // Monitor macro used by apb_m_monitor and apb_m_monitor_bfm + // This struct is defined in apb_m_macros.svh + `apb_m_MONITOR_STRUCT + apb_m_monitor_s apb_m_monitor_struct; + //******************************************************************* + // FUNCTION: to_monitor_struct() + // This function packs transaction variables into a apb_m_monitor_s + // structure. The function returns the handle to the apb_m_monitor_struct. + // This function is defined in apb_m_macros.svh + `apb_m_TO_MONITOR_STRUCT_FUNCTION + //******************************************************************* + // FUNCTION: from_monitor_struct() + // This function unpacks the struct provided as an argument into transaction + // variables of this class. + // This function is defined in apb_m_macros.svh + `apb_m_FROM_MONITOR_STRUCT_FUNCTION + + //******************************************************************* + // Initiator macro used by apb_m_driver and apb_m_driver_bfm + // to communicate initiator driven data to apb_m_driver_bfm. + // This struct is defined in apb_m_macros.svh + `apb_m_INITIATOR_STRUCT + apb_m_initiator_s apb_m_initiator_struct; + //******************************************************************* + // FUNCTION: to_initiator_struct() + // This function packs transaction variables into a apb_m_initiator_s + // structure. The function returns the handle to the apb_m_initiator_struct. + // This function is defined in apb_m_macros.svh + `apb_m_TO_INITIATOR_STRUCT_FUNCTION + //******************************************************************* + // FUNCTION: from_initiator_struct() + // This function unpacks the struct provided as an argument into transaction + // variables of this class. + // This function is defined in apb_m_macros.svh + `apb_m_FROM_INITIATOR_STRUCT_FUNCTION + + //******************************************************************* + // Responder macro used by apb_m_driver and apb_m_driver_bfm + // to communicate Responder driven data to apb_m_driver_bfm. + // This struct is defined in apb_m_macros.svh + `apb_m_RESPONDER_STRUCT + apb_m_responder_s apb_m_responder_struct; + //******************************************************************* + // FUNCTION: to_responder_struct() + // This function packs transaction variables into a apb_m_responder_s + // structure. The function returns the handle to the apb_m_responder_struct. + // This function is defined in apb_m_macros.svh + `apb_m_TO_RESPONDER_STRUCT_FUNCTION + //******************************************************************* + // FUNCTION: from_responder_struct() + // This function unpacks the struct provided as an argument into transaction + // variables of this class. + // This function is defined in apb_m_macros.svh + `apb_m_FROM_RESPONDER_STRUCT_FUNCTION + // **************************************************************************** + // FUNCTION : new() + // This function is the standard SystemVerilog constructor. + // + function new( string name = "" ); + super.new( name ); + endfunction + + // **************************************************************************** + // FUNCTION: convert2string() + // This function converts all variables in this class to a single string for + // logfile reporting. + // + virtual function string convert2string(); + // pragma uvmf custom convert2string begin + // UVMF_CHANGE_ME : Customize format if desired. + return $sformatf("psel:0x%x penable:0x%x paddr:0x%x pwdata:0x%x pwrite:0x%x pstrb:0x%x pprot:0x%x prdata:0x%x pready:0x%x pslverr:0x%x ",psel,penable,paddr,pwdata,pwrite,pstrb,pprot,prdata,pready,pslverr); + // pragma uvmf custom convert2string end + endfunction + + //******************************************************************* + // FUNCTION: do_print() + // This function is automatically called when the .print() function + // is called on this class. + // + virtual function void do_print(uvm_printer printer); + // pragma uvmf custom do_print begin + // UVMF_CHANGE_ME : Current contents of do_print allows for the use of UVM 1.1d, 1.2 or P1800.2. + // Update based on your own printing preference according to your preferred UVM version + $display(convert2string()); + // pragma uvmf custom do_print end + endfunction + + //******************************************************************* + // FUNCTION: do_compare() + // This function is automatically called when the .compare() function + // is called on this class. + // + virtual function bit do_compare (uvm_object rhs, uvm_comparer comparer); + apb_m_transaction #( + .APB_ADDR_WIDTH(APB_ADDR_WIDTH), + .APB_DATA_WIDTH(APB_DATA_WIDTH), + .STRB_LEN(STRB_LEN) + ) RHS; + if (!$cast(RHS,rhs)) return 0; + // pragma uvmf custom do_compare begin + // UVMF_CHANGE_ME : Eliminate comparison of variables not to be used for compare + return (super.do_compare(rhs,comparer) + &&(this.penable == RHS.penable) + &&(this.paddr == RHS.paddr) + &&(this.pwdata == RHS.pwdata) + &&(this.pwrite == RHS.pwrite) + &&(this.pstrb == RHS.pstrb) + &&(this.pprot == RHS.pprot) + &&(this.prdata == RHS.prdata) + &&(this.pready == RHS.pready) + &&(this.pslverr == RHS.pslverr) + ); + // pragma uvmf custom do_compare end + endfunction + + //******************************************************************* + // FUNCTION: do_copy() + // This function is automatically called when the .copy() function + // is called on this class. + // + virtual function void do_copy (uvm_object rhs); + apb_m_transaction #( + .APB_ADDR_WIDTH(APB_ADDR_WIDTH), + .APB_DATA_WIDTH(APB_DATA_WIDTH), + .STRB_LEN(STRB_LEN) + ) RHS; + assert($cast(RHS,rhs)); + // pragma uvmf custom do_copy begin + super.do_copy(rhs); + this.psel = RHS.psel; + this.penable = RHS.penable; + this.paddr = RHS.paddr; + this.pwdata = RHS.pwdata; + this.pwrite = RHS.pwrite; + this.pstrb = RHS.pstrb; + this.pprot = RHS.pprot; + this.prdata = RHS.prdata; + this.pready = RHS.pready; + this.pslverr = RHS.pslverr; + // pragma uvmf custom do_copy end + endfunction + + // **************************************************************************** + // FUNCTION: add_to_wave() + // This function is used to display variables in this class in the waveform + // viewer. The start_time and end_time variables must be set before this + // function is called. If the start_time and end_time variables are not set + // the transaction will be hidden at 0ns on the waveform display. + // + virtual function void add_to_wave(int transaction_viewing_stream_h); + `ifdef QUESTA + if (transaction_view_h == 0) begin + transaction_view_h = $begin_transaction(transaction_viewing_stream_h,"apb_m_transaction",start_time); + end + super.add_to_wave(transaction_view_h); + // pragma uvmf custom add_to_wave begin + // UVMF_CHANGE_ME : Color can be applied to transaction entries based on content, example below + // case() + // 1 : $add_color(transaction_view_h,"red"); + // default : $add_color(transaction_view_h,"grey"); + // endcase + // UVMF_CHANGE_ME : Eliminate transaction variables not wanted in transaction viewing in the waveform viewer + $add_attribute(transaction_view_h,psel,"psel"); + $add_attribute(transaction_view_h,penable,"penable"); + $add_attribute(transaction_view_h,paddr,"paddr"); + $add_attribute(transaction_view_h,pwdata,"pwdata"); + $add_attribute(transaction_view_h,pwrite,"pwrite"); + $add_attribute(transaction_view_h,pstrb,"pstrb"); + $add_attribute(transaction_view_h,pprot,"pprot"); + $add_attribute(transaction_view_h,prdata,"prdata"); + $add_attribute(transaction_view_h,pready,"pready"); + $add_attribute(transaction_view_h,pslverr,"pslverr"); + // pragma uvmf custom add_to_wave end + $end_transaction(transaction_view_h,end_time); + $free_transaction(transaction_view_h); + `endif // QUESTA + endfunction + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end +`endif diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/apb_m_pkg/src/apb_m_transaction_coverage.svh b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/apb_m_pkg/src/apb_m_transaction_coverage.svh new file mode 100644 index 00000000..2759cc07 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/apb_m_pkg/src/apb_m_transaction_coverage.svh @@ -0,0 +1,94 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This class records apb_m transaction information using +// a covergroup named apb_m_transaction_cg. An instance of this +// coverage component is instantiated in the uvmf_parameterized_agent +// if the has_coverage flag is set. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +`ifndef APB_M_TRANSACTION_COVERAGE +`define APB_M_TRANSACTION_COVERAGE +class apb_m_transaction_coverage #( + int APB_ADDR_WIDTH = 32, + int APB_DATA_WIDTH = 32, + int STRB_LEN = APB_ADDR_WIDTH/8 + ) extends uvm_subscriber #(.T(apb_m_transaction #( + .APB_ADDR_WIDTH(APB_ADDR_WIDTH), + .APB_DATA_WIDTH(APB_DATA_WIDTH), + .STRB_LEN(STRB_LEN) + ))); + + `uvm_component_param_utils( apb_m_transaction_coverage #( + APB_ADDR_WIDTH, + APB_DATA_WIDTH, + STRB_LEN + )) + + T coverage_trans; + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + // **************************************************************************** + covergroup apb_m_transaction_cg; + // pragma uvmf custom covergroup begin + // UVMF_CHANGE_ME : Add coverage bins, crosses, exclusions, etc. according to coverage needs. + option.auto_bin_max=1024; + option.per_instance=1; + psel: coverpoint coverage_trans.psel; + penable: coverpoint coverage_trans.penable; + paddr: coverpoint coverage_trans.paddr; + pwdata: coverpoint coverage_trans.pwdata; + pwrite: coverpoint coverage_trans.pwrite; + pstrb: coverpoint coverage_trans.pstrb; + pprot: coverpoint coverage_trans.pprot; + prdata: coverpoint coverage_trans.prdata; + pready: coverpoint coverage_trans.pready; + pslverr: coverpoint coverage_trans.pslverr; + // pragma uvmf custom covergroup end + endgroup + + // **************************************************************************** + // FUNCTION : new() + // This function is the standard SystemVerilog constructor. + // + function new(string name="", uvm_component parent=null); + super.new(name,parent); + apb_m_transaction_cg=new; + `uvm_warning("COVERAGE_MODEL_REVIEW", "A covergroup has been constructed which may need review because of either generation or re-generation with merging. Please note that transaction variables added as a result of re-generation and merging are not automatically added to the covergroup. Remove this warning after the covergroup has been reviewed.") + endfunction + + // **************************************************************************** + // FUNCTION : build_phase() + // This function is the standard UVM build_phase. + // + function void build_phase(uvm_phase phase); + apb_m_transaction_cg.set_inst_name($sformatf("apb_m_transaction_cg_%s",get_full_name())); + endfunction + + // **************************************************************************** + // FUNCTION: write (T t) + // This function is automatically executed when a transaction arrives on the + // analysis_export. It copies values from the variables in the transaction + // to local variables used to collect functional coverage. + // + virtual function void write (T t); + `uvm_info("COV","Received transaction",UVM_HIGH); + coverage_trans = t; + apb_m_transaction_cg.sample(); + endfunction + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + +`endif diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/apb_m_pkg/src/apb_m_typedefs.svh b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/apb_m_pkg/src/apb_m_typedefs.svh new file mode 100644 index 00000000..91e77a1c --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/apb_m_pkg/src/apb_m_typedefs.svh @@ -0,0 +1,21 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: +// This file contains defines and typedefs to be compiled for use in +// the simulation running on the host server when using Veloce. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +`ifndef TYPEDEFS_HVL +`definr TYPEDEFS_HVL + +// pragma uvmf custom additional begin +// pragma uvmf custom additional end +`endif diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/apb_m_pkg/src/apb_m_typedefs_hdl.svh b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/apb_m_pkg/src/apb_m_typedefs_hdl.svh new file mode 100644 index 00000000..bd6b6f41 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/apb_m_pkg/src/apb_m_typedefs_hdl.svh @@ -0,0 +1,23 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: +// This file contains defines and typedefs to be compiled for use in +// the simulation running on the emulator when using Veloce. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// + +`ifndef TYPEDEFS_HVL +`definr TYPEDEFS_HVL + + +// pragma uvmf custom additional begin +// pragma uvmf custom additional end +`endif diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/apb_m_pkg/yaml/apb_m_interface.yaml b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/apb_m_pkg/yaml/apb_m_interface.yaml new file mode 100644 index 00000000..f49301e8 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/apb_m_pkg/yaml/apb_m_interface.yaml @@ -0,0 +1,128 @@ +uvmf: + interfaces: + apb_m: + clock: pclk + config_constraints: [] + config_vars: [] + existing_library_component: 'True' + gen_inbound_streaming_driver: 'False' + hdl_pkg_parameters: [] + hdl_typedefs: [] + hvl_pkg_parameters: [] + hvl_typedefs: [] + parameters: + - name: APB_ADDR_WIDTH + type: int + value: '32' + - name: APB_DATA_WIDTH + type: int + value: '32' + - name: STRB_LEN + type: int + value: APB_ADDR_WIDTH/8 + ports: + - dir: output + name: psel + reset_value: '''b0' + width: '16' + - dir: output + name: penable + reset_value: '''b0' + width: '1' + - dir: output + name: paddr + reset_value: '''b0' + width: APB_ADDR_WIDTH + - dir: output + name: pwdata + reset_value: '''b0' + width: APB_DATA_WIDTH + - dir: output + name: pwrite + reset_value: '''b0' + width: '1' + - dir: output + name: pstrb + reset_value: '''b0' + width: STRB_LEN + - dir: output + name: pprot + reset_value: '''b0' + width: '3' + - dir: input + name: prdata + reset_value: '''b0' + width: APB_DATA_WIDTH + - dir: input + name: pready + reset_value: '0' + width: '1' + - dir: input + name: pslverr + reset_value: '0' + width: '1' + reset: presetn + reset_assertion_level: 'False' + transaction_constraints: [] + transaction_vars: + - comment: '' + iscompare: 'False' + isrand: 'True' + name: psel + type: bit + unpacked_dimension: '' + - comment: '' + iscompare: 'True' + isrand: 'True' + name: penable + type: bit + unpacked_dimension: '' + - comment: '' + iscompare: 'True' + isrand: 'True' + name: paddr + type: bit [APB_ADDR_WIDTH-1:0] + unpacked_dimension: '' + - comment: '' + iscompare: 'True' + isrand: 'True' + name: pwdata + type: bit [APB_DATA_WIDTH-1:0] + unpacked_dimension: '' + - comment: '' + iscompare: 'True' + isrand: 'True' + name: pwrite + type: bit + unpacked_dimension: '' + - comment: '' + iscompare: 'True' + isrand: 'True' + name: pstrb + type: bit [STRB_LEN:0] + unpacked_dimension: '' + - comment: '' + iscompare: 'True' + isrand: 'True' + name: pprot + type: bit [3:0] + unpacked_dimension: '' + - comment: '' + iscompare: 'True' + isrand: 'False' + name: prdata + type: bit [APB_DATA_WIDTH-1:0] + unpacked_dimension: '' + - comment: '' + iscompare: 'True' + isrand: 'False' + name: pready + type: bit + unpacked_dimension: '' + - comment: '' + iscompare: 'True' + isrand: 'False' + name: pslverr + type: bit + unpacked_dimension: '' + use_dpi_link: 'False' diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/axi_m_pkg/.project b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/axi_m_pkg/.project new file mode 100644 index 00000000..7afbc306 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/axi_m_pkg/.project @@ -0,0 +1,30 @@ + + + axi_m_pkg + + + + + + org.python.pydev.PyDevBuilder + + + + + net.sf.sveditor.core.SVProjectBuilder + + + + + + net.sf.sveditor.core.SVNature + org.python.pydev.pythonNature + + + + UVMF_VIP_LIBRARY_HOME + $%7BPARENT-2-PROJECT_LOC%7D + + + + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/axi_m_pkg/.svproject b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/axi_m_pkg/.svproject new file mode 100644 index 00000000..5c637646 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/axi_m_pkg/.svproject @@ -0,0 +1,16 @@ + + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/axi_m_pkg/Makefile b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/axi_m_pkg/Makefile new file mode 100644 index 00000000..49510a8d --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/axi_m_pkg/Makefile @@ -0,0 +1,66 @@ +# axi_m interface packages source +# pragma uvmf custom additional begin +# pragma uvmf custom additional end + +axi_m_PKG = \ + +incdir+$(UVMF_VIP_LIBRARY_HOME)/interface_packages/axi_m_pkg \ + -F $(UVMF_VIP_LIBRARY_HOME)/interface_packages/axi_m_pkg/axi_m_filelist_hvl.f + +axi_m_PKG_HDL = \ + +incdir+$(UVMF_VIP_LIBRARY_HOME)/interface_packages/axi_m_pkg \ + -F $(UVMF_VIP_LIBRARY_HOME)/interface_packages/axi_m_pkg/axi_m_filelist_hdl.f + +axi_m_PKG_XRTL = \ + +incdir+$(UVMF_VIP_LIBRARY_HOME)/interface_packages/axi_m_pkg \ + -F $(UVMF_VIP_LIBRARY_HOME)/interface_packages/axi_m_pkg/axi_m_filelist_xrtl.f + +COMP_axi_m_PKG_TGT_0 = q_comp_axi_m_pkg +COMP_axi_m_PKG_TGT_1 = v_comp_axi_m_pkg +COMP_axi_m_PKG_TGT = $(COMP_axi_m_PKG_TGT_$(USE_VELOCE)) + +comp_axi_m_pkg: $(COMP_axi_m_PKG_TGT) + +q_comp_axi_m_pkg: + $(HDL_COMP_CMD) $(axi_m_PKG_HDL) + $(HVL_COMP_CMD) $(axi_m_PKG) + $(HDL_COMP_CMD) $(axi_m_PKG_XRTL) + +v_comp_axi_m_pkg: + $(HVL_COMP_CMD) $(axi_m_PKG_HDL) + $(HVL_COMP_CMD) $(axi_m_PKG) + $(VELANALYZE_CMD) $(axi_m_PKG_HDL) + $(VELANALYZE_HVL_CMD) $(axi_m_PKG) + $(HDL_COMP_CMD) $(axi_m_PKG_XRTL) + +ifeq ($(MTI_VCO_MODE),64) + GCC_COMP_ARCH = -m64 +else + GCC_COMP_ARCH = -m32 +endif + +export axi_m_IF_DPI_SRC ?= $(UVMF_VIP_LIBRARY_HOME)/interface_packages/axi_m_pkg/dpi + +C_FILE_COMPILE_LIST_axi_m_pkg = \ + +O_FILE_COMPILE_LIST_axi_m_pkg = $(notdir $(C_FILE_COMPILE_LIST_axi_m_pkg:.c=.o)) + +GCC_COMP_ARGS_axi_m_pkg += -I$(axi_m_IF_DPI_SRC) \ + -fPIC + +GCC_COMP_ARGS_axi_m_pkg += $(axi_m_IF_GCC_COMP_ARGUMENTS) + +GCC_LINK_ARGS_axi_m_pkg += \ + \ + -o .so + +comp_axi_m_pkg_c_files: + @echo "--------------------------------" + @echo "Compiling Interface C source" + @echo "--------------------------------" + gcc $(GCC_COMP_ARCH) $(GCC_COMP_ARGS_axi_m_pkg) $(C_FILE_COMPILE_LIST_axi_m_pkg) + @echo "--------------------------------" + @echo "Linking Interface C objects into a shared object" + @echo "--------------------------------" + gcc $(GCC_COMP_ARCH) $(GCC_LINK_ARGS_axi_m_pkg) $(O_FILE_COMPILE_LIST_axi_m_pkg) + @echo "--------------------------------" + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/axi_m_pkg/axi_m.compile b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/axi_m_pkg/axi_m.compile new file mode 100644 index 00000000..c1de0879 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/axi_m_pkg/axi_m.compile @@ -0,0 +1,3 @@ +needs: + - axi_m_hvl.compile + - axi_m_hdl.compile diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/axi_m_pkg/axi_m_bfm.vinfo b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/axi_m_pkg/axi_m_bfm.vinfo new file mode 100644 index 00000000..69c6a9be --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/axi_m_pkg/axi_m_bfm.vinfo @@ -0,0 +1,6 @@ +@use $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg_hdl.vinfo +@use axi_m_pkg_hdl.vinfo ++incdir+@vinfodir +src/axi_m_if.sv +src/axi_m_driver_bfm.sv +src/axi_m_monitor_bfm.sv diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/axi_m_pkg/axi_m_common.compile b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/axi_m_pkg/axi_m_common.compile new file mode 100644 index 00000000..325f4c25 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/axi_m_pkg/axi_m_common.compile @@ -0,0 +1,7 @@ +needs: + - $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg_hdl.compile +incdir: + - . + - ${uvm_path}/src +src: + - axi_m_pkg_hdl.sv diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/axi_m_pkg/axi_m_filelist_hdl.f b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/axi_m_pkg/axi_m_filelist_hdl.f new file mode 100644 index 00000000..af073f29 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/axi_m_pkg/axi_m_filelist_hdl.f @@ -0,0 +1 @@ +$UVMF_VIP_LIBRARY_HOME/interface_packages/axi_m_pkg/axi_m_pkg_hdl.sv diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/axi_m_pkg/axi_m_filelist_hvl.f b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/axi_m_pkg/axi_m_filelist_hvl.f new file mode 100644 index 00000000..0c583aa9 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/axi_m_pkg/axi_m_filelist_hvl.f @@ -0,0 +1 @@ +$UVMF_VIP_LIBRARY_HOME/interface_packages/axi_m_pkg/axi_m_pkg.sv \ No newline at end of file diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/axi_m_pkg/axi_m_filelist_xrtl.f b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/axi_m_pkg/axi_m_filelist_xrtl.f new file mode 100644 index 00000000..0348c6ae --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/axi_m_pkg/axi_m_filelist_xrtl.f @@ -0,0 +1,3 @@ +$UVMF_VIP_LIBRARY_HOME/interface_packages/axi_m_pkg/src/axi_m_if.sv +$UVMF_VIP_LIBRARY_HOME/interface_packages/axi_m_pkg/src/axi_m_monitor_bfm.sv +$UVMF_VIP_LIBRARY_HOME/interface_packages/axi_m_pkg/src/axi_m_driver_bfm.sv diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/axi_m_pkg/axi_m_hdl.compile b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/axi_m_pkg/axi_m_hdl.compile new file mode 100644 index 00000000..59f061bc --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/axi_m_pkg/axi_m_hdl.compile @@ -0,0 +1,9 @@ +needs: + - $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg_hdl.compile + - ./axi_m_common.compile +incdir: + - . +src: + - src/axi_m_if.sv + - src/axi_m_monitor_bfm.sv + - src/axi_m_driver_bfm.sv diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/axi_m_pkg/axi_m_hvl.compile b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/axi_m_pkg/axi_m_hvl.compile new file mode 100644 index 00000000..b72727cc --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/axi_m_pkg/axi_m_hvl.compile @@ -0,0 +1,7 @@ +needs: + - $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg.compile + - ./axi_m_common.compile +incdir: + - . +src: + - axi_m_pkg.sv diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/axi_m_pkg/axi_m_pkg.sv b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/axi_m_pkg/axi_m_pkg.sv new file mode 100644 index 00000000..d265c7ac --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/axi_m_pkg/axi_m_pkg.sv @@ -0,0 +1,79 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// PACKAGE: This file defines all of the files contained in the +// interface package that will run on the host simulator. +// +// CONTAINS: +// - +// - +// - + +// - +// - +// - + +// - +// - +// - + +// - +// - +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +`ifndef AXI_M_PKG +`define AXI_M_PKG +package axi_m_pkg; + + import uvm_pkg::*; + import uvmf_base_pkg_hdl::*; + import uvmf_base_pkg::*; + import axi_m_pkg_hdl::*; + + `include "uvm_macros.svh" + + // pragma uvmf custom package_imports_additional begin + // pragma uvmf custom package_imports_additional end + `include "src/axi_m_macros.svh" + + export axi_m_pkg_hdl::*; + + + + // Parameters defined as HVL parameters + + `include "src/axi_m_typedefs.svh" + `include "src/axi_m_transaction.svh" + + `include "src/axi_m_configuration.svh" + `include "src/axi_m_driver.svh" + `include "src/axi_m_monitor.svh" + + `include "src/axi_m_transaction_coverage.svh" + `include "src/axi_m_sequence_base.svh" + `include "src/axi_m_random_sequence.svh" + + `include "src/axi_m_responder_sequence.svh" + `include "src/axi_m2reg_adapter.svh" + + `include "src/axi_m_agent.svh" + + // pragma uvmf custom package_item_additional begin + // UVMF_CHANGE_ME : When adding new interface sequences to the src directory + // be sure to add the sequence file here so that it will be + // compiled as part of the interface package. Be sure to place + // the new sequence after any base sequences of the new sequence. + // pragma uvmf custom package_item_additional end + +endpackage + +// pragma uvmf custom external begin +// pragma uvmf custom external end +`endif diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/axi_m_pkg/axi_m_pkg.vinfo b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/axi_m_pkg/axi_m_pkg.vinfo new file mode 100644 index 00000000..dae51d0c --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/axi_m_pkg/axi_m_pkg.vinfo @@ -0,0 +1,4 @@ +@use $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg.vinfo +@use axi_m_pkg_hdl.vinfo ++incdir+@vinfodir +axi_m_pkg.sv diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/axi_m_pkg/axi_m_pkg_hdl.sv b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/axi_m_pkg/axi_m_pkg_hdl.sv new file mode 100644 index 00000000..6727b95a --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/axi_m_pkg/axi_m_pkg_hdl.sv @@ -0,0 +1,40 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// PACKAGE: This file defines all of the files contained in the +// interface package that needs to be compiled and synthesized +// for running on Veloce. +// +// CONTAINS: +// - +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +`ifndef AXI_M_PKG_HDL +`define AXI_M_PKG_HDL +package axi_m_pkg_hdl; + + import uvmf_base_pkg_hdl::*; + + // pragma uvmf custom package_imports_additional begin + // pragma uvmf custom package_imports_additional end + + // Parameters defined as HDL parameters + + `include "src/axi_m_typedefs_hdl.svh" + `include "src/axi_m_macros.svh" + + // pragma uvmf custom package_item_additional begin + // pragma uvmf custom package_item_additional end + +endpackage + +// pragma uvmf custom external begin +// pragma uvmf custom external end +`endif diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/axi_m_pkg/axi_m_pkg_hdl.vinfo b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/axi_m_pkg/axi_m_pkg_hdl.vinfo new file mode 100644 index 00000000..4bcea0fb --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/axi_m_pkg/axi_m_pkg_hdl.vinfo @@ -0,0 +1,2 @@ +@use $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg_hdl.vinfo +axi_m_pkg_hdl.sv diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/axi_m_pkg/axi_m_pkg_sve.F b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/axi_m_pkg/axi_m_pkg_sve.F new file mode 100644 index 00000000..fd118edd --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/axi_m_pkg/axi_m_pkg_sve.F @@ -0,0 +1,10 @@ +// UVM ++incdir+${UVM_HOME}/src +${UVM_HOME}/src/uvm_pkg.sv + +// Common UVMF files +-f ${UVMF_HOME}/common/common_sve.f + ++incdir+. +-f ${UVMF_VIP_LIBRARY_HOME}/interface_packages/axi_m_pkg/axi_m_filelist_hdl.f +-f ${UVMF_VIP_LIBRARY_HOME}/interface_packages/axi_m_pkg/axi_m_filelist_hvl.f diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/axi_m_pkg/compile.do b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/axi_m_pkg/compile.do new file mode 100644 index 00000000..ea448b12 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/axi_m_pkg/compile.do @@ -0,0 +1,14 @@ +# Tcl do file for compile of axi_m interface + +# pragma uvmf custom additional begin +# pragma uvmf custom additional end + + +vlog -sv -timescale 1ps/1ps -suppress 2223,2286 +incdir+$env(UVMF_VIP_LIBRARY_HOME)/interface_packages/axi_m_pkg \ + -F $env(UVMF_VIP_LIBRARY_HOME)/interface_packages/axi_m_pkg/axi_m_filelist_hdl.f + +vlog -sv -timescale 1ps/1ps -suppress 2223,2286 +incdir+$env(UVMF_VIP_LIBRARY_HOME)/interface_packages/axi_m_pkg \ + -F $env(UVMF_VIP_LIBRARY_HOME)/interface_packages/axi_m_pkg/axi_m_filelist_hvl.f + +vlog -sv -timescale 1ps/1ps -suppress 2223,2286 +incdir+$env(UVMF_VIP_LIBRARY_HOME)/interface_packages/axi_m_pkg \ + -F $env(UVMF_VIP_LIBRARY_HOME)/interface_packages/axi_m_pkg/axi_m_filelist_xrtl.f \ No newline at end of file diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/axi_m_pkg/src/axi_m2reg_adapter.svh b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/axi_m_pkg/src/axi_m2reg_adapter.svh new file mode 100644 index 00000000..dde89e79 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/axi_m_pkg/src/axi_m2reg_adapter.svh @@ -0,0 +1,125 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: +// This file contains the UVM register adapter for the axi_m interface. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +`ifndef AXI_M2REG_ADAPTER +`define AXI_M2REG_ADAPTER +class axi_m2reg_adapter #( + int AW_WIDTH = 32, + int LEN = 8, + int DATA_WIDTH = 32, + int X = 16 + ) extends uvm_reg_adapter; + + `uvm_object_param_utils( axi_m2reg_adapter #( + AW_WIDTH, + LEN, + DATA_WIDTH, + X + )) + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + //-------------------------------------------------------------------- + // new + //-------------------------------------------------------------------- + function new (string name = "axi_m2reg_adapter" ); + super.new(name); + // pragma uvmf custom new begin + // UVMF_CHANGE_ME : Configure the adapter regarding byte enables and provides response. + + // Does the protocol the Agent is modeling support byte enables? + // 0 = NO + // 1 = YES + supports_byte_enable = 0; + + // Does the Agent's Driver provide separate response sequence items? + // i.e. Does the driver call seq_item_port.put() + // and do the sequences call get_response()? + // 0 = NO + // 1 = YES + provides_responses = 0; + // pragma uvmf custom new end + + endfunction: new + + //-------------------------------------------------------------------- + // reg2bus + //-------------------------------------------------------------------- + virtual function uvm_sequence_item reg2bus(const ref uvm_reg_bus_op rw); + + axi_m_transaction #( + .AW_WIDTH(AW_WIDTH), + .LEN(LEN), + .DATA_WIDTH(DATA_WIDTH), + .X(X) + ) trans_h = axi_m_transaction #( + .AW_WIDTH(AW_WIDTH), + .LEN(LEN), + .DATA_WIDTH(DATA_WIDTH), + .X(X) + )::type_id::create("trans_h"); + + // pragma uvmf custom reg2bus begin + // UVMF_CHANGE_ME : Fill in the reg2bus adapter mapping registe fields to protocol fields. + + //Adapt the following for your sequence item type + // trans_h.op = (rw.kind == UVM_READ) ? WB_READ : WB_WRITE; + //Copy over address + // trans_h.addr = rw.addr; + //Copy over write data + // trans_h.data = rw.data; + + // pragma uvmf custom reg2bus end + + // Return the adapted transaction + return trans_h; + + endfunction: reg2bus + + //-------------------------------------------------------------------- + // bus2reg + //-------------------------------------------------------------------- + virtual function void bus2reg(uvm_sequence_item bus_item, + ref uvm_reg_bus_op rw); + axi_m_transaction #( + .AW_WIDTH(AW_WIDTH), + .LEN(LEN), + .DATA_WIDTH(DATA_WIDTH), + .X(X) + ) trans_h; + if (!$cast(trans_h, bus_item)) begin + `uvm_fatal("ADAPT","Provided bus_item is not of the correct type") + return; + end + // pragma uvmf custom bus2reg begin + // UVMF_CHANGE_ME : Fill in the bus2reg adapter mapping protocol fields to register fields. + //Adapt the following for your sequence item type + //Copy over instruction type + // rw.kind = (trans_h.op == WB_WRITE) ? UVM_WRITE : UVM_READ; + //Copy over address + // rw.addr = trans_h.addr; + //Copy over read data + // rw.data = trans_h.data; + //Check for errors on the bus and return UVM_NOT_OK if there is an error + // rw.status = UVM_IS_OK; + // pragma uvmf custom bus2reg end + + endfunction: bus2reg + +endclass : axi_m2reg_adapter + +// pragma uvmf custom external begin +// pragma uvmf custom external end +`endif diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/axi_m_pkg/src/axi_m_agent.svh b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/axi_m_pkg/src/axi_m_agent.svh new file mode 100644 index 00000000..9f526a05 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/axi_m_pkg/src/axi_m_agent.svh @@ -0,0 +1,93 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: Protocol specific agent class definition +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// + +`ifndef AXI_M_AGENT +`define AXI_M_AGENT + +class axi_m_agent #( + int AW_WIDTH = 32, + int LEN = 8, + int DATA_WIDTH = 32, + int X = 16 + ) extends uvmf_parameterized_agent #( + .CONFIG_T(axi_m_configuration #( + .AW_WIDTH(AW_WIDTH), + .LEN(LEN), + .DATA_WIDTH(DATA_WIDTH), + .X(X) + )), + .DRIVER_T(axi_m_driver #( + .AW_WIDTH(AW_WIDTH), + .LEN(LEN), + .DATA_WIDTH(DATA_WIDTH), + .X(X) + )), + .MONITOR_T(axi_m_monitor #( + .AW_WIDTH(AW_WIDTH), + .LEN(LEN), + .DATA_WIDTH(DATA_WIDTH), + .X(X) + )), + .COVERAGE_T(axi_m_transaction_coverage #( + .AW_WIDTH(AW_WIDTH), + .LEN(LEN), + .DATA_WIDTH(DATA_WIDTH), + .X(X) + )), + .TRANS_T(axi_m_transaction #( + .AW_WIDTH(AW_WIDTH), + .LEN(LEN), + .DATA_WIDTH(DATA_WIDTH), + .X(X) + )) + ); + + `uvm_component_param_utils( axi_m_agent #( + AW_WIDTH, + LEN, + DATA_WIDTH, + X + )) + +// pragma uvmf custom class_item_additional begin +// pragma uvmf custom class_item_additional end + +// **************************************************************************** +// FUNCTION : new() +// This function is the standard SystemVerilog constructor. +// + function new( string name = "", uvm_component parent = null ); + super.new( name, parent ); + endfunction + +// **************************************************************************** + // FUNCTION: build_phase + virtual function void build_phase(uvm_phase phase); +// pragma uvmf custom build_phase_pre_super begin +// pragma uvmf custom build_phase_pre_super end + super.build_phase(phase); + if (configuration.active_passive == ACTIVE) begin + // Place sequencer handle into configuration object + // so that it may be retrieved from configuration + // rather than using uvm_config_db + configuration.sequencer = this.sequencer; + end + endfunction + +endclass + + +// pragma uvmf custom external begin +// pragma uvmf custom external end +`endif diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/axi_m_pkg/src/axi_m_configuration.svh b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/axi_m_pkg/src/axi_m_configuration.svh new file mode 100644 index 00000000..2807bbf4 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/axi_m_pkg/src/axi_m_configuration.svh @@ -0,0 +1,222 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This class contains all variables and functions used +// to configure the axi_m agent and its bfm's. It gets the +// bfm's from the uvm_config_db for use by the agent. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// + +`ifndef AXI_M_CONFIGURATION +`define AXI_M_CONFIGURATION +class axi_m_configuration #( + int AW_WIDTH = 32, + int LEN = 8, + int DATA_WIDTH = 32, + int X = 16 + ) extends uvmf_parameterized_agent_configuration_base #( + .DRIVER_BFM_BIND_T(virtual axi_m_driver_bfm #( + .AW_WIDTH(AW_WIDTH), + .LEN(LEN), + .DATA_WIDTH(DATA_WIDTH), + .X(X) + )), + .MONITOR_BFM_BIND_T( virtual axi_m_monitor_bfm #( + .AW_WIDTH(AW_WIDTH), + .LEN(LEN), + .DATA_WIDTH(DATA_WIDTH), + .X(X) + ))); + + `uvm_object_param_utils( axi_m_configuration #( + AW_WIDTH, + LEN, + DATA_WIDTH, + X + )) + + + // Sequencer handle populated by agent + uvm_sequencer #(axi_m_transaction #( + .AW_WIDTH(AW_WIDTH), + .LEN(LEN), + .DATA_WIDTH(DATA_WIDTH), + .X(X) + ) ) sequencer; + + //Constraints for the configuration variables: + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + covergroup axi_m_configuration_cg; + // pragma uvmf custom covergroup begin + option.auto_bin_max=1024; + // pragma uvmf custom covergroup end + endgroup + + //******************************************************************* + //******************************************************************* + // Structure used to pass configuration variables to monitor and driver BFM's. + // Use to_struct function to pack variables into structure. + // Use from_struct function to unpack variables from structure. + // This structure is defined in axi_m_macros.svh + `axi_m_CONFIGURATION_STRUCT + axi_m_configuration_s axi_m_configuration_struct; + //******************************************************************* + // FUNCTION: to_struct() + // This function packs variables into a axi_m_configuration_s + // structure. The function returns the handle to the axi_m_configuration_struct. + // This function is defined in axi_m_macros.svh + `axi_m_CONFIGURATION_TO_STRUCT_FUNCTION + //******************************************************************* + // FUNCTION: from_struct() + // This function unpacks the struct provided as an argument into + // variables of this class. + // This function is defined in axi_m_macros.svh + `axi_m_CONFIGURATION_FROM_STRUCT_FUNCTION + + // **************************************************************************** + // FUNCTION : new() + // This function is the standard SystemVerilog constructor. + // + function new( string name = "" ); + super.new( name ); + // Construct the covergroup for this configuration class + axi_m_configuration_cg = new; + endfunction + + // **************************************************************************** + // FUNCTION: post_randomize() + // This function is automatically called after the randomize() function + // is executed. + // + function void post_randomize(); + super.post_randomize(); + axi_m_configuration_cg.sample(); + endfunction + + // **************************************************************************** + // FUNCTION: initialize + // This function causes the configuration to retrieve + // its virtual interface handle from the uvm_config_db. + // This function also makes itself available to its + // agent through the uvm_config_db. + // + // ARGUMENTS: + // uvmf_active_passive_t activity: + // This argument identifies the simulation level + // as either BLOCK, CHIP, SIMULATION, etc. + // + // AGENT_PATH: + // This argument identifies the path to this + // configurations agent. This configuration + // makes itself available to the agent specified + // by agent_path by placing itself into the + // uvm_config_db. + // + // INTERFACE_NAME: + // This argument identifies the string name of + // this configurations BFM's. This string + // name is used to retrieve the driver and + // monitor BFM from the uvm_config_db. + // + virtual function void initialize(uvmf_active_passive_t activity, + string agent_path, + string interface_name); + + super.initialize( activity, agent_path, interface_name); + // The covergroup is given the same name as the interface + axi_m_configuration_cg.set_inst_name(interface_name); + + // This configuration places itself into the uvm_config_db for the agent, identified by the agent_path variable, to retrieve. + uvm_config_db #( axi_m_configuration #( + .AW_WIDTH(AW_WIDTH), + .LEN(LEN), + .DATA_WIDTH(DATA_WIDTH), + .X(X) + ) + )::set( null ,agent_path,UVMF_AGENT_CONFIG, this ); + + // This configuration also places itself in the config db using the same identifier used by the interface. This allows users to access + // configuration variables and the interface through the bfm api class rather than directly accessing the BFM. This is useful for + // accessingthe BFM when using Veloce + uvm_config_db #( axi_m_configuration #( + .AW_WIDTH(AW_WIDTH), + .LEN(LEN), + .DATA_WIDTH(DATA_WIDTH), + .X(X) + ) + )::set( null ,UVMF_CONFIGURATIONS, interface_name, this ); + + axi_m_configuration_cg.set_inst_name($sformatf("axi_m_configuration_cg_%s",get_full_name())); + +// This code is to aid in debugging parameter mismatches between the BFM and its corresponding agent. +// Enable this debug by setting UVM_VERBOSITY to UVM_DEBUG +// Setting UVM_VERBOSITY to UVM_DEBUG causes all BFM's and all agents to display their parameter settings. +// All of the messages from this feature have a UVM messaging id value of "CFG" +// The transcript or run.log can be parsed to ensure BFM parameter settings match its corresponding agents parameter settings. + `uvm_info("CFG", + $psprintf("The agent at '%s' is using interface named %s has the following parameters: AW_WIDTH=%x LEN=%x DATA_WIDTH=%x X=%x ", agent_path, interface_name, AW_WIDTH ,LEN ,DATA_WIDTH ,X ), + UVM_DEBUG) + + // pragma uvmf custom initialize begin + // This controls whether or not the agent returns a transaction handle in the driver when calling + // item_done() back into the sequencer or not. If set to 1, a transaction is sent back which means + // the sequence on the other end must use the get_response() part of the driver/sequence API. If + // this doesn't occur, there will eventually be response_queue overflow errors during the test. + return_transaction_response = 1'b0; + + // pragma uvmf custom initialize end + + endfunction + + // **************************************************************************** + // TASK: wait_for_reset + // *[Required]* Blocks until reset is released. The wait_for_reset operation is performed + // by a task in the monitor bfm. + virtual task wait_for_reset(); + monitor_bfm.wait_for_reset(); + endtask + + // **************************************************************************** + // TASK: wait_for_num_clocks + // *[Required]* Blocks until specified number of clocks have elapsed. The wait_for_num_clocks + // operation is performed by a task in the monitor bfm. + virtual task wait_for_num_clocks(int clocks); + monitor_bfm.wait_for_num_clocks(clocks); + endtask + + // **************************************************************************** + // FUNCTION : convert2string() + // This function is used to convert variables in this class into a string for log messaging. + // + virtual function string convert2string (); + // pragma uvmf custom convert2string begin + return $sformatf(""); + // pragma uvmf custom convert2string end + endfunction + + // **************************************************************************** + // FUNCTION: get_sequencer + function uvm_sequencer #(axi_m_transaction#( + .AW_WIDTH(AW_WIDTH), + .LEN(LEN), + .DATA_WIDTH(DATA_WIDTH), + .X(X) + )) get_sequencer(); + return sequencer; + endfunction + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end +`endif diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/axi_m_pkg/src/axi_m_driver.svh b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/axi_m_pkg/src/axi_m_driver.svh new file mode 100644 index 00000000..bd53a86f --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/axi_m_pkg/src/axi_m_driver.svh @@ -0,0 +1,123 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This class passes transactions between the sequencer +// and the BFM driver interface. It accesses the driver BFM +// through the bfm handle. This driver +// passes transactions to the driver BFM through the access +// task. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +`ifndef AXI_M_DRIVER +`define AXI_M_DRIVER +class axi_m_driver #( + int AW_WIDTH = 32, + int LEN = 8, + int DATA_WIDTH = 32, + int X = 16 + ) extends uvmf_driver_base #( + .CONFIG_T(axi_m_configuration #( + .AW_WIDTH(AW_WIDTH), + .LEN(LEN), + .DATA_WIDTH(DATA_WIDTH), + .X(X) + ) ), + .BFM_BIND_T(virtual axi_m_driver_bfm #( + .AW_WIDTH(AW_WIDTH), + .LEN(LEN), + .DATA_WIDTH(DATA_WIDTH), + .X(X) + ) ), + .REQ(axi_m_transaction #( + .AW_WIDTH(AW_WIDTH), + .LEN(LEN), + .DATA_WIDTH(DATA_WIDTH), + .X(X) + ) ), + .RSP(axi_m_transaction #( + .AW_WIDTH(AW_WIDTH), + .LEN(LEN), + .DATA_WIDTH(DATA_WIDTH), + .X(X) + ) )); + + `uvm_component_param_utils( axi_m_driver #( + AW_WIDTH, + LEN, + DATA_WIDTH, + X + )) +//******************************************************************* +// Macros that define structs located in axi_m_macros.svh +//******************************************************************* +// Initiator macro used by axi_m_driver and axi_m_driver_bfm +// to communicate initiator driven data to axi_m_driver_bfm. +`axi_m_INITIATOR_STRUCT + axi_m_initiator_s axi_m_initiator_struct; +//******************************************************************* +// Responder macro used by axi_m_driver and axi_m_driver_bfm +// to communicate Responder driven data to axi_m_driver_bfm. +`axi_m_RESPONDER_STRUCT + axi_m_responder_s axi_m_responder_struct; + +// pragma uvmf custom class_item_additional begin +// pragma uvmf custom class_item_additional end + +// **************************************************************************** +// This function is the standard SystemVerilog constructor. +// + function new( string name = "", uvm_component parent=null ); + super.new( name, parent ); + endfunction + +// **************************************************************************** +// This function sends configuration object variables to the driver BFM +// using the configuration struct. +// + virtual function void configure(input CONFIG_T cfg); + bfm.configure( cfg.to_struct() ); + endfunction + +// **************************************************************************** +// This function places a handle to this class in the proxy variable in the +// driver BFM. This allows the driver BFM to call tasks and function within this class. +// + virtual function void set_bfm_proxy_handle(); + bfm.proxy = this; endfunction + +// **************************************************************************** +// This task is called by the run_phase in uvmf_driver_base. + virtual task access( inout REQ txn ); +// pragma uvmf custom access begin + if (configuration.initiator_responder==RESPONDER) begin + // Complete current transfer and wait for next transfer + bfm.respond_and_wait_for_next_transfer( + axi_m_initiator_struct, + txn.to_responder_struct() + ); + // Unpack information about initiated transfer received by this responder + txn.from_initiator_struct(axi_m_initiator_struct); + end else begin + // Initiate a transfer and get response + bfm.initiate_and_get_response( + txn.to_initiator_struct(), + axi_m_responder_struct + ); + // Unpack transfer response information received by this initiator + txn.from_responder_struct(axi_m_responder_struct); + end +// pragma uvmf custom access end + endtask + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end +`endif diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/axi_m_pkg/src/axi_m_driver_bfm.sv b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/axi_m_pkg/src/axi_m_driver_bfm.sv new file mode 100644 index 00000000..e26f0af6 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/axi_m_pkg/src/axi_m_driver_bfm.sv @@ -0,0 +1,765 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: +// This interface performs the axi_m signal driving. It is +// accessed by the uvm axi_m driver through a virtual interface +// handle in the axi_m configuration. It drives the singals passed +// in through the port connection named bus of type axi_m_if. +// +// Input signals from the axi_m_if are assigned to an internal input +// signal with a _i suffix. The _i signal should be used for sampling. +// +// The input signal connections are as follows: +// bus.signal -> signal_i +// +// This bfm drives signals with a _o suffix. These signals +// are driven onto signals within axi_m_if based on INITIATOR/RESPONDER and/or +// ARBITRATION/GRANT status. +// +// The output signal connections are as follows: +// signal_o -> bus.signal +// +// +// Interface functions and tasks used by UVM components: +// +// configure: +// This function gets configuration attributes from the +// UVM driver to set any required BFM configuration +// variables such as 'initiator_responder'. +// +// initiate_and_get_response: +// This task is used to perform signaling activity for initiating +// a protocol transfer. The task initiates the transfer, using +// input data from the initiator struct. Then the task captures +// response data, placing the data into the response struct. +// The response struct is returned to the driver class. +// +// respond_and_wait_for_next_transfer: +// This task is used to complete a current transfer as a responder +// and then wait for the initiator to start the next transfer. +// The task uses data in the responder struct to drive protocol +// signals to complete the transfer. The task then waits for +// the next transfer. Once the next transfer begins, data from +// the initiator is placed into the initiator struct and sent +// to the responder sequence for processing to determine +// what data to respond with. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +import uvmf_base_pkg_hdl::*; +import axi_m_pkg_hdl::*; +`include "src/axi_m_macros.svh" + +interface axi_m_driver_bfm #( + int AW_WIDTH = 32, + int LEN = 8, + int DATA_WIDTH = 32, + int X = 16 + ) + (axi_m_if bus); + // The following pragma and additional ones in-lined further below are for running this BFM on Veloce + // pragma attribute axi_m_driver_bfm partition_interface_xif + +`ifndef XRTL +// This code is to aid in debugging parameter mismatches between the BFM and its corresponding agent. +// Enable this debug by setting UVM_VERBOSITY to UVM_DEBUG +// Setting UVM_VERBOSITY to UVM_DEBUG causes all BFM's and all agents to display their parameter settings. +// All of the messages from this feature have a UVM messaging id value of "CFG" +// The transcript or run.log can be parsed to ensure BFM parameter settings match its corresponding agents parameter settings. +import uvm_pkg::*; +`include "uvm_macros.svh" +initial begin : bfm_vs_agent_parameter_debug + `uvm_info("CFG", + $psprintf("The BFM at '%m' has the following parameters: AW_WIDTH=%x LEN=%x DATA_WIDTH=%x X=%x ", AW_WIDTH,LEN,DATA_WIDTH,X), + UVM_DEBUG) +end +`endif + + // Config value to determine if this is an initiator or a responder + uvmf_initiator_responder_t initiator_responder; + // Custom configuration variables. + // These are set using the configure function which is called during the UVM connect_phase + + logic axi_clk_i; + logic rst_i; + + // Signal list (all signals are capable of being inputs and outputs for the sake + // of supporting both INITIATOR and RESPONDER mode operation. Expectation is that + // directionality in the config file was from the point-of-view of the INITIATOR + + // INITIATOR mode input signals + tri awready_i; + reg awready_o = 'bz; + tri wready_i; + reg wready_o = 'bz; + tri bwvalid_i; + reg bwvalid_o = 'bz; + tri [1:0] bresp_i; + reg [1:0] bresp_o = 'bz; + tri [X-1:0] bid_i; + reg [X-1:0] bid_o = 'bz; + tri [X-1:0] buser_i; + reg [X-1:0] buser_o = 'bz; + tri aready_i; + reg aready_o = 'bz; + tri rvalid_i; + reg rvalid_o = 'bz; + tri rlast_i; + reg rlast_o = 'bz; + tri [DATA_WIDTH-1:0] rdata_i; + reg [DATA_WIDTH-1:0] rdata_o = 'bz; + tri [X-1:0] rid_i; + reg [X-1:0] rid_o = 'bz; + tri [X-1:0] ruser_i; + reg [X-1:0] ruser_o = 'bz; + tri [1:0] rresp_i; + reg [1:0] rresp_o = 'bz; + + // INITIATOR mode output signals + tri awvalid_i; + reg awvalid_o = 'bz; + tri [AW_WIDTH-1:0] awaddr_i; + reg [AW_WIDTH-1:0] awaddr_o = 'bz; + tri [2:0] awsize_i; + reg [2:0] awsize_o = 'bz; + tri [1:0] awburst_i; + reg [1:0] awburst_o = 'bz; + tri [3:0] awcache_i; + reg [3:0] awcache_o = 'bz; + tri [2:0] awprot_i; + reg [2:0] awprot_o = 'bz; + tri [X-1:0] awid_i; + reg [X-1:0] awid_o = 'bz; + tri [LEN-1:0] awlen_i; + reg [LEN-1:0] awlen_o = 'bz; + tri awlock_i; + reg awlock_o = 'bz; + tri [3:0] awqos_i; + reg [3:0] awqos_o = 'bz; + tri [3:0] awregion_i; + reg [3:0] awregion_o = 'bz; + tri [X-1:0] awuser_i; + reg [X-1:0] awuser_o = 'bz; + tri wvalid_i; + reg wvalid_o = 'bz; + tri wlast_i; + reg wlast_o = 'bz; + tri [DATA_WIDTH-1:0] wdata_i; + reg [DATA_WIDTH-1:0] wdata_o = 'bz; + tri [DATA_WIDTH/8-1:0] wstrb_i; + reg [DATA_WIDTH/8-1:0] wstrb_o = 'bz; + tri [X-1:0] wid_i; + reg [X-1:0] wid_o = 'bz; + tri [X-1:0] wuser_i; + reg [X-1:0] wuser_o = 'bz; + tri bwready_i; + reg bwready_o = 'bz; + tri arvalid_i; + reg arvalid_o = 'bz; + tri [AW_WIDTH-1:0] araddr_i; + reg [AW_WIDTH-1:0] araddr_o = 'bz; + tri [2:0] arsize_i; + reg [2:0] arsize_o = 'bz; + tri [1:0] arburst_i; + reg [1:0] arburst_o = 'bz; + tri [3:0] arcache_i; + reg [3:0] arcache_o = 'bz; + tri [2:0] arprot_i; + reg [2:0] arprot_o = 'bz; + tri [X-1:0] arid_i; + reg [X-1:0] arid_o = 'bz; + tri [LEN-1:0] arlen_i; + reg [LEN-1:0] arlen_o = 'bz; + tri arlock_i; + reg arlock_o = 'bz; + tri [3:0] arqos_i; + reg [3:0] arqos_o = 'bz; + tri [3:0] aregion_i; + reg [3:0] aregion_o = 'bz; + tri [X-1:0] aruser_i; + reg [X-1:0] aruser_o = 'bz; + tri rready_i; + reg rready_o = 'bz; + + // Bi-directional signals + + + assign axi_clk_i = bus.axi_clk; + assign rst_i = bus.rst; + + // These are signals marked as 'input' by the config file, but the signals will be + // driven by this BFM if put into RESPONDER mode (flipping all signal directions around) + assign awready_i = bus.awready; + assign bus.awready = (initiator_responder == RESPONDER) ? awready_o : 'bz; + assign wready_i = bus.wready; + assign bus.wready = (initiator_responder == RESPONDER) ? wready_o : 'bz; + assign bwvalid_i = bus.bwvalid; + assign bus.bwvalid = (initiator_responder == RESPONDER) ? bwvalid_o : 'bz; + assign bresp_i = bus.bresp; + assign bus.bresp = (initiator_responder == RESPONDER) ? bresp_o : 'bz; + assign bid_i = bus.bid; + assign bus.bid = (initiator_responder == RESPONDER) ? bid_o : 'bz; + assign buser_i = bus.buser; + assign bus.buser = (initiator_responder == RESPONDER) ? buser_o : 'bz; + assign aready_i = bus.aready; + assign bus.aready = (initiator_responder == RESPONDER) ? aready_o : 'bz; + assign rvalid_i = bus.rvalid; + assign bus.rvalid = (initiator_responder == RESPONDER) ? rvalid_o : 'bz; + assign rlast_i = bus.rlast; + assign bus.rlast = (initiator_responder == RESPONDER) ? rlast_o : 'bz; + assign rdata_i = bus.rdata; + assign bus.rdata = (initiator_responder == RESPONDER) ? rdata_o : 'bz; + assign rid_i = bus.rid; + assign bus.rid = (initiator_responder == RESPONDER) ? rid_o : 'bz; + assign ruser_i = bus.ruser; + assign bus.ruser = (initiator_responder == RESPONDER) ? ruser_o : 'bz; + assign rresp_i = bus.rresp; + assign bus.rresp = (initiator_responder == RESPONDER) ? rresp_o : 'bz; + + + // These are signals marked as 'output' by the config file, but the outputs will + // not be driven by this BFM unless placed in INITIATOR mode. + assign bus.awvalid = (initiator_responder == INITIATOR) ? awvalid_o : 'bz; + assign awvalid_i = bus.awvalid; + assign bus.awaddr = (initiator_responder == INITIATOR) ? awaddr_o : 'bz; + assign awaddr_i = bus.awaddr; + assign bus.awsize = (initiator_responder == INITIATOR) ? awsize_o : 'bz; + assign awsize_i = bus.awsize; + assign bus.awburst = (initiator_responder == INITIATOR) ? awburst_o : 'bz; + assign awburst_i = bus.awburst; + assign bus.awcache = (initiator_responder == INITIATOR) ? awcache_o : 'bz; + assign awcache_i = bus.awcache; + assign bus.awprot = (initiator_responder == INITIATOR) ? awprot_o : 'bz; + assign awprot_i = bus.awprot; + assign bus.awid = (initiator_responder == INITIATOR) ? awid_o : 'bz; + assign awid_i = bus.awid; + assign bus.awlen = (initiator_responder == INITIATOR) ? awlen_o : 'bz; + assign awlen_i = bus.awlen; + assign bus.awlock = (initiator_responder == INITIATOR) ? awlock_o : 'bz; + assign awlock_i = bus.awlock; + assign bus.awqos = (initiator_responder == INITIATOR) ? awqos_o : 'bz; + assign awqos_i = bus.awqos; + assign bus.awregion = (initiator_responder == INITIATOR) ? awregion_o : 'bz; + assign awregion_i = bus.awregion; + assign bus.awuser = (initiator_responder == INITIATOR) ? awuser_o : 'bz; + assign awuser_i = bus.awuser; + assign bus.wvalid = (initiator_responder == INITIATOR) ? wvalid_o : 'bz; + assign wvalid_i = bus.wvalid; + assign bus.wlast = (initiator_responder == INITIATOR) ? wlast_o : 'bz; + assign wlast_i = bus.wlast; + assign bus.wdata = (initiator_responder == INITIATOR) ? wdata_o : 'bz; + assign wdata_i = bus.wdata; + assign bus.wstrb = (initiator_responder == INITIATOR) ? wstrb_o : 'bz; + assign wstrb_i = bus.wstrb; + assign bus.wid = (initiator_responder == INITIATOR) ? wid_o : 'bz; + assign wid_i = bus.wid; + assign bus.wuser = (initiator_responder == INITIATOR) ? wuser_o : 'bz; + assign wuser_i = bus.wuser; + assign bus.bwready = (initiator_responder == INITIATOR) ? bwready_o : 'bz; + assign bwready_i = bus.bwready; + assign bus.arvalid = (initiator_responder == INITIATOR) ? arvalid_o : 'bz; + assign arvalid_i = bus.arvalid; + assign bus.araddr = (initiator_responder == INITIATOR) ? araddr_o : 'bz; + assign araddr_i = bus.araddr; + assign bus.arsize = (initiator_responder == INITIATOR) ? arsize_o : 'bz; + assign arsize_i = bus.arsize; + assign bus.arburst = (initiator_responder == INITIATOR) ? arburst_o : 'bz; + assign arburst_i = bus.arburst; + assign bus.arcache = (initiator_responder == INITIATOR) ? arcache_o : 'bz; + assign arcache_i = bus.arcache; + assign bus.arprot = (initiator_responder == INITIATOR) ? arprot_o : 'bz; + assign arprot_i = bus.arprot; + assign bus.arid = (initiator_responder == INITIATOR) ? arid_o : 'bz; + assign arid_i = bus.arid; + assign bus.arlen = (initiator_responder == INITIATOR) ? arlen_o : 'bz; + assign arlen_i = bus.arlen; + assign bus.arlock = (initiator_responder == INITIATOR) ? arlock_o : 'bz; + assign arlock_i = bus.arlock; + assign bus.arqos = (initiator_responder == INITIATOR) ? arqos_o : 'bz; + assign arqos_i = bus.arqos; + assign bus.aregion = (initiator_responder == INITIATOR) ? aregion_o : 'bz; + assign aregion_i = bus.aregion; + assign bus.aruser = (initiator_responder == INITIATOR) ? aruser_o : 'bz; + assign aruser_i = bus.aruser; + assign bus.rready = (initiator_responder == INITIATOR) ? rready_o : 'bz; + assign rready_i = bus.rready; + + // Proxy handle to UVM driver + axi_m_pkg::axi_m_driver #( + .AW_WIDTH(AW_WIDTH), + .LEN(LEN), + .DATA_WIDTH(DATA_WIDTH), + .X(X) + ) proxy; + // pragma tbx oneway proxy.my_function_name_in_uvm_driver + + // **************************************************************************** + // **************************************************************************** + // Macros that define structs located in axi_m_macros.svh + // **************************************************************************** + // Struct for passing configuration data from axi_m_driver to this BFM + // **************************************************************************** + `axi_m_CONFIGURATION_STRUCT + // **************************************************************************** + // Structs for INITIATOR and RESPONDER data flow + //******************************************************************* + // Initiator macro used by axi_m_driver and axi_m_driver_bfm + // to communicate initiator driven data to axi_m_driver_bfm. + `axi_m_INITIATOR_STRUCT + axi_m_initiator_s initiator_struct; + // Responder macro used by axi_m_driver and axi_m_driver_bfm + // to communicate Responder driven data to axi_m_driver_bfm. + `axi_m_RESPONDER_STRUCT + axi_m_responder_s responder_struct; + + // **************************************************************************** +// pragma uvmf custom reset_condition_and_response begin + // Always block used to return signals to reset value upon assertion of reset + always @( negedge rst_i ) + begin + // RESPONDER mode output signals + awready_o <= 'bz; + wready_o <= 'bz; + bwvalid_o <= 'bz; + bresp_o <= 'bz; + bid_o <= 'bz; + buser_o <= 'bz; + aready_o <= 'bz; + rvalid_o <= 'bz; + rlast_o <= 'bz; + rdata_o <= 'bz; + rid_o <= 'bz; + ruser_o <= 'bz; + rresp_o <= 'bz; + // INITIATOR mode output signals + awvalid_o <= 'bz; + awaddr_o <= 'bz; + awsize_o <= 'bz; + awburst_o <= 'bz; + awcache_o <= 'bz; + awprot_o <= 'bz; + awid_o <= 'bz; + awlen_o <= 'bz; + awlock_o <= 'bz; + awqos_o <= 'bz; + awregion_o <= 'bz; + awuser_o <= 'bz; + wvalid_o <= 'bz; + wlast_o <= 'bz; + wdata_o <= 'bz; + wstrb_o <= 'bz; + wid_o <= 'bz; + wuser_o <= 'bz; + bwready_o <= 'bz; + arvalid_o <= 'bz; + araddr_o <= 'bz; + arsize_o <= 'bz; + arburst_o <= 'bz; + arcache_o <= 'bz; + arprot_o <= 'bz; + arid_o <= 'bz; + arlen_o <= 'bz; + arlock_o <= 'bz; + arqos_o <= 'bz; + aregion_o <= 'bz; + aruser_o <= 'bz; + rready_o <= 'bz; + // Bi-directional signals + + end +// pragma uvmf custom reset_condition_and_response end + + // pragma uvmf custom interface_item_additional begin + // pragma uvmf custom interface_item_additional end + + //****************************************************************** + // The configure() function is used to pass agent configuration + // variables to the driver BFM. It is called by the driver within + // the agent at the beginning of the simulation. It may be called + // during the simulation if agent configuration variables are updated + // and the driver BFM needs to be aware of the new configuration + // variables. + // + + function void configure(axi_m_configuration_s axi_m_configuration_arg); // pragma tbx xtf + initiator_responder = axi_m_configuration_arg.initiator_responder; + // pragma uvmf custom configure begin + // pragma uvmf custom configure end + endfunction + +// pragma uvmf custom initiate_and_get_response begin +// **************************************************************************** +// UVMF_CHANGE_ME +// This task is used by an initator. The task first initiates a transfer then +// waits for the responder to complete the transfer. + task initiate_and_get_response( + // This argument passes transaction variables used by an initiator + // to perform the initial part of a protocol transfer. The values + // come from a sequence item created in a sequence. + input axi_m_initiator_s axi_m_initiator_struct, + // This argument is used to send data received from the responder + // back to the sequence item. The sequence item is returned to the sequence. + output axi_m_responder_s axi_m_responder_struct + );// pragma tbx xtf + // + // Members within the axi_m_initiator_struct: + // bit awvalid ; + // bit awready ; + // bit [AW_WIDTH-1:0] awaddr ; + // bit awsize ; + // bit awburst ; + // bit awcache ; + // bit awprot ; + // bit [X-1:0] awid ; + // bit [LEN-1:0] awlen ; + // bit awlock ; + // bit awqos ; + // bit awregion ; + // bit [X-1:0] awuser ; + // bit wvalid ; + // bit wready ; + // bit wlast ; + // bit [DATA_WIDTH-1:0] wdata ; + // bit [DATA_WIDTH/8-1:0] wstrb ; + // bit [X-1:0] wid ; + // bit [X-1:0] wuser ; + // bit bwvalid ; + // bit bwready ; + // bit bresp ; + // bit [X-1:0] bid ; + // bit [X-1:0] buser ; + // bit arvalid ; + // bit aready ; + // bit [AW_WIDTH-1:0] araddr ; + // bit arsize ; + // bit arburst ; + // bit arcache ; + // bit arprot ; + // bit [X-1:0] arid ; + // bit [LEN-1:0] arlen ; + // bit arlock ; + // bit arqos ; + // bit aregion ; + // bit [X-1:0] aruser ; + // bit rvalid ; + // bit rready ; + // bit rlast ; + // bit [DATA_WIDTH-1:0] rdata ; + // bit [X-1:0] rid ; + // bit [X-1:0] ruser ; + // bit rresp ; + // Members within the axi_m_responder_struct: + // bit awvalid ; + // bit awready ; + // bit [AW_WIDTH-1:0] awaddr ; + // bit awsize ; + // bit awburst ; + // bit awcache ; + // bit awprot ; + // bit [X-1:0] awid ; + // bit [LEN-1:0] awlen ; + // bit awlock ; + // bit awqos ; + // bit awregion ; + // bit [X-1:0] awuser ; + // bit wvalid ; + // bit wready ; + // bit wlast ; + // bit [DATA_WIDTH-1:0] wdata ; + // bit [DATA_WIDTH/8-1:0] wstrb ; + // bit [X-1:0] wid ; + // bit [X-1:0] wuser ; + // bit bwvalid ; + // bit bwready ; + // bit bresp ; + // bit [X-1:0] bid ; + // bit [X-1:0] buser ; + // bit arvalid ; + // bit aready ; + // bit [AW_WIDTH-1:0] araddr ; + // bit arsize ; + // bit arburst ; + // bit arcache ; + // bit arprot ; + // bit [X-1:0] arid ; + // bit [LEN-1:0] arlen ; + // bit arlock ; + // bit arqos ; + // bit aregion ; + // bit [X-1:0] aruser ; + // bit rvalid ; + // bit rready ; + // bit rlast ; + // bit [DATA_WIDTH-1:0] rdata ; + // bit [X-1:0] rid ; + // bit [X-1:0] ruser ; + // bit rresp ; + initiator_struct = axi_m_initiator_struct; + // + // Reference code; + // How to wait for signal value + // while (control_signal == 1'b1) @(posedge axi_clk_i); + // + // How to assign a responder struct member, named xyz, from a signal. + // All available initiator input and inout signals listed. + // Initiator input signals + // axi_m_responder_struct.xyz = awready_i; // + // axi_m_responder_struct.xyz = wready_i; // + // axi_m_responder_struct.xyz = bwvalid_i; // + // axi_m_responder_struct.xyz = bresp_i; // [1:0] + // axi_m_responder_struct.xyz = bid_i; // [X-1:0] + // axi_m_responder_struct.xyz = buser_i; // [X-1:0] + // axi_m_responder_struct.xyz = aready_i; // + // axi_m_responder_struct.xyz = rvalid_i; // + // axi_m_responder_struct.xyz = rlast_i; // + // axi_m_responder_struct.xyz = rdata_i; // [DATA_WIDTH-1:0] + // axi_m_responder_struct.xyz = rid_i; // [X-1:0] + // axi_m_responder_struct.xyz = ruser_i; // [X-1:0] + // axi_m_responder_struct.xyz = rresp_i; // [1:0] + // Initiator inout signals + // How to assign a signal from an initiator struct member named xyz. + // All available initiator output and inout signals listed. + // Notice the _o. Those are storage variables that allow for procedural assignment. + // Initiator output signals + // awvalid_o <= axi_m_initiator_struct.xyz; // + // awaddr_o <= axi_m_initiator_struct.xyz; // [AW_WIDTH-1:0] + // awsize_o <= axi_m_initiator_struct.xyz; // [2:0] + // awburst_o <= axi_m_initiator_struct.xyz; // [1:0] + // awcache_o <= axi_m_initiator_struct.xyz; // [3:0] + // awprot_o <= axi_m_initiator_struct.xyz; // [2:0] + // awid_o <= axi_m_initiator_struct.xyz; // [X-1:0] + // awlen_o <= axi_m_initiator_struct.xyz; // [LEN-1:0] + // awlock_o <= axi_m_initiator_struct.xyz; // + // awqos_o <= axi_m_initiator_struct.xyz; // [3:0] + // awregion_o <= axi_m_initiator_struct.xyz; // [3:0] + // awuser_o <= axi_m_initiator_struct.xyz; // [X-1:0] + // wvalid_o <= axi_m_initiator_struct.xyz; // + // wlast_o <= axi_m_initiator_struct.xyz; // + // wdata_o <= axi_m_initiator_struct.xyz; // [DATA_WIDTH-1:0] + // wstrb_o <= axi_m_initiator_struct.xyz; // [DATA_WIDTH/8-1:0] + // wid_o <= axi_m_initiator_struct.xyz; // [X-1:0] + // wuser_o <= axi_m_initiator_struct.xyz; // [X-1:0] + // bwready_o <= axi_m_initiator_struct.xyz; // + // arvalid_o <= axi_m_initiator_struct.xyz; // + // araddr_o <= axi_m_initiator_struct.xyz; // [AW_WIDTH-1:0] + // arsize_o <= axi_m_initiator_struct.xyz; // [2:0] + // arburst_o <= axi_m_initiator_struct.xyz; // [1:0] + // arcache_o <= axi_m_initiator_struct.xyz; // [3:0] + // arprot_o <= axi_m_initiator_struct.xyz; // [2:0] + // arid_o <= axi_m_initiator_struct.xyz; // [X-1:0] + // arlen_o <= axi_m_initiator_struct.xyz; // [LEN-1:0] + // arlock_o <= axi_m_initiator_struct.xyz; // + // arqos_o <= axi_m_initiator_struct.xyz; // [3:0] + // aregion_o <= axi_m_initiator_struct.xyz; // [3:0] + // aruser_o <= axi_m_initiator_struct.xyz; // [X-1:0] + // rready_o <= axi_m_initiator_struct.xyz; // + // Initiator inout signals + // Initiate a transfer using the data received. + @(posedge axi_clk_i); + @(posedge axi_clk_i); + // Wait for the responder to complete the transfer then place the responder data into + // axi_m_responder_struct. + @(posedge axi_clk_i); + @(posedge axi_clk_i); + responder_struct = axi_m_responder_struct; + endtask +// pragma uvmf custom initiate_and_get_response end + +// pragma uvmf custom respond_and_wait_for_next_transfer begin +// **************************************************************************** +// The first_transfer variable is used to prevent completing a transfer in the +// first call to this task. For the first call to this task, there is not +// current transfer to complete. +bit first_transfer=1; + +// UVMF_CHANGE_ME +// This task is used by a responder. The task first completes the current +// transfer in progress then waits for the initiator to start the next transfer. + task respond_and_wait_for_next_transfer( + // This argument is used to send data received from the initiator + // back to the sequence item. The sequence determines how to respond. + output axi_m_initiator_s axi_m_initiator_struct, + // This argument passes transaction variables used by a responder + // to complete a protocol transfer. The values come from a sequence item. + input axi_m_responder_s axi_m_responder_struct + );// pragma tbx xtf + // Variables within the axi_m_initiator_struct: + // bit awvalid ; + // bit awready ; + // bit [AW_WIDTH-1:0] awaddr ; + // bit awsize ; + // bit awburst ; + // bit awcache ; + // bit awprot ; + // bit [X-1:0] awid ; + // bit [LEN-1:0] awlen ; + // bit awlock ; + // bit awqos ; + // bit awregion ; + // bit [X-1:0] awuser ; + // bit wvalid ; + // bit wready ; + // bit wlast ; + // bit [DATA_WIDTH-1:0] wdata ; + // bit [DATA_WIDTH/8-1:0] wstrb ; + // bit [X-1:0] wid ; + // bit [X-1:0] wuser ; + // bit bwvalid ; + // bit bwready ; + // bit bresp ; + // bit [X-1:0] bid ; + // bit [X-1:0] buser ; + // bit arvalid ; + // bit aready ; + // bit [AW_WIDTH-1:0] araddr ; + // bit arsize ; + // bit arburst ; + // bit arcache ; + // bit arprot ; + // bit [X-1:0] arid ; + // bit [LEN-1:0] arlen ; + // bit arlock ; + // bit arqos ; + // bit aregion ; + // bit [X-1:0] aruser ; + // bit rvalid ; + // bit rready ; + // bit rlast ; + // bit [DATA_WIDTH-1:0] rdata ; + // bit [X-1:0] rid ; + // bit [X-1:0] ruser ; + // bit rresp ; + // Variables within the axi_m_responder_struct: + // bit awvalid ; + // bit awready ; + // bit [AW_WIDTH-1:0] awaddr ; + // bit awsize ; + // bit awburst ; + // bit awcache ; + // bit awprot ; + // bit [X-1:0] awid ; + // bit [LEN-1:0] awlen ; + // bit awlock ; + // bit awqos ; + // bit awregion ; + // bit [X-1:0] awuser ; + // bit wvalid ; + // bit wready ; + // bit wlast ; + // bit [DATA_WIDTH-1:0] wdata ; + // bit [DATA_WIDTH/8-1:0] wstrb ; + // bit [X-1:0] wid ; + // bit [X-1:0] wuser ; + // bit bwvalid ; + // bit bwready ; + // bit bresp ; + // bit [X-1:0] bid ; + // bit [X-1:0] buser ; + // bit arvalid ; + // bit aready ; + // bit [AW_WIDTH-1:0] araddr ; + // bit arsize ; + // bit arburst ; + // bit arcache ; + // bit arprot ; + // bit [X-1:0] arid ; + // bit [LEN-1:0] arlen ; + // bit arlock ; + // bit arqos ; + // bit aregion ; + // bit [X-1:0] aruser ; + // bit rvalid ; + // bit rready ; + // bit rlast ; + // bit [DATA_WIDTH-1:0] rdata ; + // bit [X-1:0] rid ; + // bit [X-1:0] ruser ; + // bit rresp ; + // Reference code; + // How to wait for signal value + // while (control_signal == 1'b1) @(posedge axi_clk_i); + // + // How to assign a responder struct member, named xyz, from a signal. + // All available responder input and inout signals listed. + // Responder input signals + // axi_m_responder_struct.xyz = awvalid_i; // + // axi_m_responder_struct.xyz = awaddr_i; // [AW_WIDTH-1:0] + // axi_m_responder_struct.xyz = awsize_i; // [2:0] + // axi_m_responder_struct.xyz = awburst_i; // [1:0] + // axi_m_responder_struct.xyz = awcache_i; // [3:0] + // axi_m_responder_struct.xyz = awprot_i; // [2:0] + // axi_m_responder_struct.xyz = awid_i; // [X-1:0] + // axi_m_responder_struct.xyz = awlen_i; // [LEN-1:0] + // axi_m_responder_struct.xyz = awlock_i; // + // axi_m_responder_struct.xyz = awqos_i; // [3:0] + // axi_m_responder_struct.xyz = awregion_i; // [3:0] + // axi_m_responder_struct.xyz = awuser_i; // [X-1:0] + // axi_m_responder_struct.xyz = wvalid_i; // + // axi_m_responder_struct.xyz = wlast_i; // + // axi_m_responder_struct.xyz = wdata_i; // [DATA_WIDTH-1:0] + // axi_m_responder_struct.xyz = wstrb_i; // [DATA_WIDTH/8-1:0] + // axi_m_responder_struct.xyz = wid_i; // [X-1:0] + // axi_m_responder_struct.xyz = wuser_i; // [X-1:0] + // axi_m_responder_struct.xyz = bwready_i; // + // axi_m_responder_struct.xyz = arvalid_i; // + // axi_m_responder_struct.xyz = araddr_i; // [AW_WIDTH-1:0] + // axi_m_responder_struct.xyz = arsize_i; // [2:0] + // axi_m_responder_struct.xyz = arburst_i; // [1:0] + // axi_m_responder_struct.xyz = arcache_i; // [3:0] + // axi_m_responder_struct.xyz = arprot_i; // [2:0] + // axi_m_responder_struct.xyz = arid_i; // [X-1:0] + // axi_m_responder_struct.xyz = arlen_i; // [LEN-1:0] + // axi_m_responder_struct.xyz = arlock_i; // + // axi_m_responder_struct.xyz = arqos_i; // [3:0] + // axi_m_responder_struct.xyz = aregion_i; // [3:0] + // axi_m_responder_struct.xyz = aruser_i; // [X-1:0] + // axi_m_responder_struct.xyz = rready_i; // + // Responder inout signals + // How to assign a signal, named xyz, from an initiator struct member. + // All available responder output and inout signals listed. + // Notice the _o. Those are storage variables that allow for procedural assignment. + // Responder output signals + // awready_o <= axi_m_initiator_struct.xyz; // + // wready_o <= axi_m_initiator_struct.xyz; // + // bwvalid_o <= axi_m_initiator_struct.xyz; // + // bresp_o <= axi_m_initiator_struct.xyz; // [1:0] + // bid_o <= axi_m_initiator_struct.xyz; // [X-1:0] + // buser_o <= axi_m_initiator_struct.xyz; // [X-1:0] + // aready_o <= axi_m_initiator_struct.xyz; // + // rvalid_o <= axi_m_initiator_struct.xyz; // + // rlast_o <= axi_m_initiator_struct.xyz; // + // rdata_o <= axi_m_initiator_struct.xyz; // [DATA_WIDTH-1:0] + // rid_o <= axi_m_initiator_struct.xyz; // [X-1:0] + // ruser_o <= axi_m_initiator_struct.xyz; // [X-1:0] + // rresp_o <= axi_m_initiator_struct.xyz; // [1:0] + // Responder inout signals + + @(posedge axi_clk_i); + if (!first_transfer) begin + // Perform transfer response here. + // Reply using data recieved in the axi_m_responder_struct. + @(posedge axi_clk_i); + // Reply using data recieved in the transaction handle. + @(posedge axi_clk_i); + end + // Wait for next transfer then gather info from intiator about the transfer. + // Place the data into the axi_m_initiator_struct. + @(posedge axi_clk_i); + @(posedge axi_clk_i); + first_transfer = 0; + endtask +// pragma uvmf custom respond_and_wait_for_next_transfer end + + +endinterface + +// pragma uvmf custom external begin +// pragma uvmf custom external end +`endif diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/axi_m_pkg/src/axi_m_if.sv b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/axi_m_pkg/src/axi_m_if.sv new file mode 100644 index 00000000..0a712fb9 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/axi_m_pkg/src/axi_m_if.sv @@ -0,0 +1,291 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This interface contains the axi_m interface signals. +// It is instantiated once per axi_m bus. Bus Functional Models, +// BFM's named axi_m_driver_bfm, are used to drive signals on the bus. +// BFM's named axi_m_monitor_bfm are used to monitor signals on the +// bus. This interface signal bundle is passed in the port list of +// the BFM in order to give the BFM access to the signals in this +// interface. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +`ifndef AXI_M_IF +`define AXI_M_IF +// This template can be used to connect a DUT to these signals +// +// .dut_signal_port(axi_m_bus.awvalid), // Agent output +// .dut_signal_port(axi_m_bus.awready), // Agent input +// .dut_signal_port(axi_m_bus.awaddr), // Agent output +// .dut_signal_port(axi_m_bus.awsize), // Agent output +// .dut_signal_port(axi_m_bus.awburst), // Agent output +// .dut_signal_port(axi_m_bus.awcache), // Agent output +// .dut_signal_port(axi_m_bus.awprot), // Agent output +// .dut_signal_port(axi_m_bus.awid), // Agent output +// .dut_signal_port(axi_m_bus.awlen), // Agent output +// .dut_signal_port(axi_m_bus.awlock), // Agent output +// .dut_signal_port(axi_m_bus.awqos), // Agent output +// .dut_signal_port(axi_m_bus.awregion), // Agent output +// .dut_signal_port(axi_m_bus.awuser), // Agent output +// .dut_signal_port(axi_m_bus.wvalid), // Agent output +// .dut_signal_port(axi_m_bus.wready), // Agent input +// .dut_signal_port(axi_m_bus.wlast), // Agent output +// .dut_signal_port(axi_m_bus.wdata), // Agent output +// .dut_signal_port(axi_m_bus.wstrb), // Agent output +// .dut_signal_port(axi_m_bus.wid), // Agent output +// .dut_signal_port(axi_m_bus.wuser), // Agent output +// .dut_signal_port(axi_m_bus.bwvalid), // Agent input +// .dut_signal_port(axi_m_bus.bwready), // Agent output +// .dut_signal_port(axi_m_bus.bresp), // Agent input +// .dut_signal_port(axi_m_bus.bid), // Agent input +// .dut_signal_port(axi_m_bus.buser), // Agent input +// .dut_signal_port(axi_m_bus.arvalid), // Agent output +// .dut_signal_port(axi_m_bus.aready), // Agent input +// .dut_signal_port(axi_m_bus.araddr), // Agent output +// .dut_signal_port(axi_m_bus.arsize), // Agent output +// .dut_signal_port(axi_m_bus.arburst), // Agent output +// .dut_signal_port(axi_m_bus.arcache), // Agent output +// .dut_signal_port(axi_m_bus.arprot), // Agent output +// .dut_signal_port(axi_m_bus.arid), // Agent output +// .dut_signal_port(axi_m_bus.arlen), // Agent output +// .dut_signal_port(axi_m_bus.arlock), // Agent output +// .dut_signal_port(axi_m_bus.arqos), // Agent output +// .dut_signal_port(axi_m_bus.aregion), // Agent output +// .dut_signal_port(axi_m_bus.aruser), // Agent output +// .dut_signal_port(axi_m_bus.rvalid), // Agent input +// .dut_signal_port(axi_m_bus.rready), // Agent output +// .dut_signal_port(axi_m_bus.rlast), // Agent input +// .dut_signal_port(axi_m_bus.rdata), // Agent input +// .dut_signal_port(axi_m_bus.rid), // Agent input +// .dut_signal_port(axi_m_bus.ruser), // Agent input +// .dut_signal_port(axi_m_bus.rresp), // Agent input + +import uvmf_base_pkg_hdl::*; +import axi_m_pkg_hdl::*; + +interface axi_m_if #( + int AW_WIDTH = 32, + int LEN = 8, + int DATA_WIDTH = 32, + int X = 16 + ) + + ( + input logic axi_clk, + input logic rst, + output logic awvalid, + input logic awready, + output logic [AW_WIDTH-1:0] awaddr, + output logic [2:0] awsize, + output logic [1:0] awburst, + output logic [3:0] awcache, + output logic [2:0] awprot, + output logic [X-1:0] awid, + output logic [LEN-1:0] awlen, + output logic awlock, + output logic [3:0] awqos, + output logic [3:0] awregion, + output logic [X-1:0] awuser, + output logic wvalid, + input logic wready, + output logic wlast, + output logic [DATA_WIDTH-1:0] wdata, + output logic [DATA_WIDTH/8-1:0] wstrb, + output logic [X-1:0] wid, + output logic [X-1:0] wuser, + input logic bwvalid, + output logic bwready, + input logic [1:0] bresp, + input logic [X-1:0] bid, + input logic [X-1:0] buser, + output logic arvalid, + input logic aready, + output logic [AW_WIDTH-1:0] araddr, + output logic [2:0] arsize, + output logic [1:0] arburst, + output logic [3:0] arcache, + output logic [2:0] arprot, + output logic [X-1:0] arid, + output logic [LEN-1:0] arlen, + output logic arlock, + output logic [3:0] arqos, + output logic [3:0] aregion, + output logic [X-1:0] aruser, + input logic rvalid, + output logic rready, + input logic rlast, + input logic [DATA_WIDTH-1:0] rdata, + input logic [X-1:0] rid, + input logic [X-1:0] ruser, + input logic [1:0] rresp + ); + +modport monitor_port + ( + input axi_clk, + input rst, + input awvalid, + input awready, + input awaddr, + input awsize, + input awburst, + input awcache, + input awprot, + input awid, + input awlen, + input awlock, + input awqos, + input awregion, + input awuser, + input wvalid, + input wready, + input wlast, + input wdata, + input wstrb, + input wid, + input wuser, + input bwvalid, + input bwready, + input bresp, + input bid, + input buser, + input arvalid, + input aready, + input araddr, + input arsize, + input arburst, + input arcache, + input arprot, + input arid, + input arlen, + input arlock, + input arqos, + input aregion, + input aruser, + input rvalid, + input rready, + input rlast, + input rdata, + input rid, + input ruser, + input rresp + ); + +modport initiator_port + ( + input axi_clk, + input rst, + output awvalid, + input awready, + output awaddr, + output awsize, + output awburst, + output awcache, + output awprot, + output awid, + output awlen, + output awlock, + output awqos, + output awregion, + output awuser, + output wvalid, + input wready, + output wlast, + output wdata, + output wstrb, + output wid, + output wuser, + input bwvalid, + output bwready, + input bresp, + input bid, + input buser, + output arvalid, + input aready, + output araddr, + output arsize, + output arburst, + output arcache, + output arprot, + output arid, + output arlen, + output arlock, + output arqos, + output aregion, + output aruser, + input rvalid, + output rready, + input rlast, + input rdata, + input rid, + input ruser, + input rresp + ); + +modport responder_port + ( + input axi_clk, + input rst, + input awvalid, + output awready, + input awaddr, + input awsize, + input awburst, + input awcache, + input awprot, + input awid, + input awlen, + input awlock, + input awqos, + input awregion, + input awuser, + input wvalid, + output wready, + input wlast, + input wdata, + input wstrb, + input wid, + input wuser, + output bwvalid, + input bwready, + output bresp, + output bid, + output buser, + input arvalid, + output aready, + input araddr, + input arsize, + input arburst, + input arcache, + input arprot, + input arid, + input arlen, + input arlock, + input arqos, + input aregion, + input aruser, + output rvalid, + input rready, + output rlast, + output rdata, + output rid, + output ruser, + output rresp + ); + + +// pragma uvmf custom interface_item_additional begin +// pragma uvmf custom interface_item_additional end + +endinterface + +// pragma uvmf custom external begin +// pragma uvmf custom external end +`endif diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/axi_m_pkg/src/axi_m_infact_coverage_strategy.csv b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/axi_m_pkg/src/axi_m_infact_coverage_strategy.csv new file mode 100644 index 00000000..1c218e14 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/axi_m_pkg/src/axi_m_infact_coverage_strategy.csv @@ -0,0 +1,6 @@ +Global +auto_bin_max, 64 + +Name,Type,Include +rand_fields,coverpoint,=rand *.** + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/axi_m_pkg/src/axi_m_macros.svh b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/axi_m_pkg/src/axi_m_macros.svh new file mode 100644 index 00000000..f04eaa78 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/axi_m_pkg/src/axi_m_macros.svh @@ -0,0 +1,517 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This file contains macros used with the axi_m package. +// These macros include packed struct definitions. These structs are +// used to pass data between classes, hvl, and BFM's, hdl. Use of +// structs are more efficient and simpler to modify. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// + +// **************************************************************************** +// When changing the contents of this struct, be sure to update the to_struct +// and from_struct methods defined in the macros below that are used in +// the axi_m_configuration class. +// + `define axi_m_CONFIGURATION_STRUCT \ +typedef struct packed { \ + uvmf_active_passive_t active_passive; \ + uvmf_initiator_responder_t initiator_responder; \ + } axi_m_configuration_s; + + `define axi_m_CONFIGURATION_TO_STRUCT_FUNCTION \ + virtual function axi_m_configuration_s to_struct();\ + axi_m_configuration_struct = \ + {\ + this.active_passive,\ + this.initiator_responder\ + };\ + return ( axi_m_configuration_struct );\ + endfunction + + `define axi_m_CONFIGURATION_FROM_STRUCT_FUNCTION \ + virtual function void from_struct(axi_m_configuration_s axi_m_configuration_struct);\ + {\ + this.active_passive,\ + this.initiator_responder \ + } = axi_m_configuration_struct;\ + endfunction + +// **************************************************************************** +// When changing the contents of this struct, be sure to update the to_monitor_struct +// and from_monitor_struct methods of the axi_m_transaction class. +// + `define axi_m_MONITOR_STRUCT typedef struct packed { \ + bit awvalid ; \ + bit awready ; \ + bit [AW_WIDTH-1:0] awaddr ; \ + bit awsize ; \ + bit awburst ; \ + bit awcache ; \ + bit awprot ; \ + bit [X-1:0] awid ; \ + bit [LEN-1:0] awlen ; \ + bit awlock ; \ + bit awqos ; \ + bit awregion ; \ + bit [X-1:0] awuser ; \ + bit wvalid ; \ + bit wready ; \ + bit wlast ; \ + bit [DATA_WIDTH-1:0] wdata ; \ + bit [DATA_WIDTH/8-1:0] wstrb ; \ + bit [X-1:0] wid ; \ + bit [X-1:0] wuser ; \ + bit bwvalid ; \ + bit bwready ; \ + bit bresp ; \ + bit [X-1:0] bid ; \ + bit [X-1:0] buser ; \ + bit arvalid ; \ + bit aready ; \ + bit [AW_WIDTH-1:0] araddr ; \ + bit arsize ; \ + bit arburst ; \ + bit arcache ; \ + bit arprot ; \ + bit [X-1:0] arid ; \ + bit [LEN-1:0] arlen ; \ + bit arlock ; \ + bit arqos ; \ + bit aregion ; \ + bit [X-1:0] aruser ; \ + bit rvalid ; \ + bit rready ; \ + bit rlast ; \ + bit [DATA_WIDTH-1:0] rdata ; \ + bit [X-1:0] rid ; \ + bit [X-1:0] ruser ; \ + bit rresp ; \ + } axi_m_monitor_s; + + `define axi_m_TO_MONITOR_STRUCT_FUNCTION \ + virtual function axi_m_monitor_s to_monitor_struct();\ + axi_m_monitor_struct = \ + { \ + this.awvalid , \ + this.awready , \ + this.awaddr , \ + this.awsize , \ + this.awburst , \ + this.awcache , \ + this.awprot , \ + this.awid , \ + this.awlen , \ + this.awlock , \ + this.awqos , \ + this.awregion , \ + this.awuser , \ + this.wvalid , \ + this.wready , \ + this.wlast , \ + this.wdata , \ + this.wstrb , \ + this.wid , \ + this.wuser , \ + this.bwvalid , \ + this.bwready , \ + this.bresp , \ + this.bid , \ + this.buser , \ + this.arvalid , \ + this.aready , \ + this.araddr , \ + this.arsize , \ + this.arburst , \ + this.arcache , \ + this.arprot , \ + this.arid , \ + this.arlen , \ + this.arlock , \ + this.arqos , \ + this.aregion , \ + this.aruser , \ + this.rvalid , \ + this.rready , \ + this.rlast , \ + this.rdata , \ + this.rid , \ + this.ruser , \ + this.rresp \ + };\ + return ( axi_m_monitor_struct);\ + endfunction\ + + `define axi_m_FROM_MONITOR_STRUCT_FUNCTION \ + virtual function void from_monitor_struct(axi_m_monitor_s axi_m_monitor_struct);\ + {\ + this.awvalid , \ + this.awready , \ + this.awaddr , \ + this.awsize , \ + this.awburst , \ + this.awcache , \ + this.awprot , \ + this.awid , \ + this.awlen , \ + this.awlock , \ + this.awqos , \ + this.awregion , \ + this.awuser , \ + this.wvalid , \ + this.wready , \ + this.wlast , \ + this.wdata , \ + this.wstrb , \ + this.wid , \ + this.wuser , \ + this.bwvalid , \ + this.bwready , \ + this.bresp , \ + this.bid , \ + this.buser , \ + this.arvalid , \ + this.aready , \ + this.araddr , \ + this.arsize , \ + this.arburst , \ + this.arcache , \ + this.arprot , \ + this.arid , \ + this.arlen , \ + this.arlock , \ + this.arqos , \ + this.aregion , \ + this.aruser , \ + this.rvalid , \ + this.rready , \ + this.rlast , \ + this.rdata , \ + this.rid , \ + this.ruser , \ + this.rresp \ + } = axi_m_monitor_struct;\ + endfunction + +// **************************************************************************** +// When changing the contents of this struct, be sure to update the to_initiator_struct +// and from_initiator_struct methods of the axi_m_transaction class. +// Also update the comments in the driver BFM. +// + `define axi_m_INITIATOR_STRUCT typedef struct packed { \ + bit awvalid ; \ + bit awready ; \ + bit [AW_WIDTH-1:0] awaddr ; \ + bit awsize ; \ + bit awburst ; \ + bit awcache ; \ + bit awprot ; \ + bit [X-1:0] awid ; \ + bit [LEN-1:0] awlen ; \ + bit awlock ; \ + bit awqos ; \ + bit awregion ; \ + bit [X-1:0] awuser ; \ + bit wvalid ; \ + bit wready ; \ + bit wlast ; \ + bit [DATA_WIDTH-1:0] wdata ; \ + bit [DATA_WIDTH/8-1:0] wstrb ; \ + bit [X-1:0] wid ; \ + bit [X-1:0] wuser ; \ + bit bwvalid ; \ + bit bwready ; \ + bit bresp ; \ + bit [X-1:0] bid ; \ + bit [X-1:0] buser ; \ + bit arvalid ; \ + bit aready ; \ + bit [AW_WIDTH-1:0] araddr ; \ + bit arsize ; \ + bit arburst ; \ + bit arcache ; \ + bit arprot ; \ + bit [X-1:0] arid ; \ + bit [LEN-1:0] arlen ; \ + bit arlock ; \ + bit arqos ; \ + bit aregion ; \ + bit [X-1:0] aruser ; \ + bit rvalid ; \ + bit rready ; \ + bit rlast ; \ + bit [DATA_WIDTH-1:0] rdata ; \ + bit [X-1:0] rid ; \ + bit [X-1:0] ruser ; \ + bit rresp ; \ + } axi_m_initiator_s; + + `define axi_m_TO_INITIATOR_STRUCT_FUNCTION \ + virtual function axi_m_initiator_s to_initiator_struct();\ + axi_m_initiator_struct = \ + {\ + this.awvalid , \ + this.awready , \ + this.awaddr , \ + this.awsize , \ + this.awburst , \ + this.awcache , \ + this.awprot , \ + this.awid , \ + this.awlen , \ + this.awlock , \ + this.awqos , \ + this.awregion , \ + this.awuser , \ + this.wvalid , \ + this.wready , \ + this.wlast , \ + this.wdata , \ + this.wstrb , \ + this.wid , \ + this.wuser , \ + this.bwvalid , \ + this.bwready , \ + this.bresp , \ + this.bid , \ + this.buser , \ + this.arvalid , \ + this.aready , \ + this.araddr , \ + this.arsize , \ + this.arburst , \ + this.arcache , \ + this.arprot , \ + this.arid , \ + this.arlen , \ + this.arlock , \ + this.arqos , \ + this.aregion , \ + this.aruser , \ + this.rvalid , \ + this.rready , \ + this.rlast , \ + this.rdata , \ + this.rid , \ + this.ruser , \ + this.rresp \ + };\ + return ( axi_m_initiator_struct);\ + endfunction + + `define axi_m_FROM_INITIATOR_STRUCT_FUNCTION \ + virtual function void from_initiator_struct(axi_m_initiator_s axi_m_initiator_struct);\ + {\ + this.awvalid , \ + this.awready , \ + this.awaddr , \ + this.awsize , \ + this.awburst , \ + this.awcache , \ + this.awprot , \ + this.awid , \ + this.awlen , \ + this.awlock , \ + this.awqos , \ + this.awregion , \ + this.awuser , \ + this.wvalid , \ + this.wready , \ + this.wlast , \ + this.wdata , \ + this.wstrb , \ + this.wid , \ + this.wuser , \ + this.bwvalid , \ + this.bwready , \ + this.bresp , \ + this.bid , \ + this.buser , \ + this.arvalid , \ + this.aready , \ + this.araddr , \ + this.arsize , \ + this.arburst , \ + this.arcache , \ + this.arprot , \ + this.arid , \ + this.arlen , \ + this.arlock , \ + this.arqos , \ + this.aregion , \ + this.aruser , \ + this.rvalid , \ + this.rready , \ + this.rlast , \ + this.rdata , \ + this.rid , \ + this.ruser , \ + this.rresp \ + } = axi_m_initiator_struct;\ + endfunction + +// **************************************************************************** +// When changing the contents of this struct, be sure to update the to_responder_struct +// and from_responder_struct methods of the axi_m_transaction class. +// Also update the comments in the driver BFM. +// + `define axi_m_RESPONDER_STRUCT typedef struct packed { \ + bit awvalid ; \ + bit awready ; \ + bit [AW_WIDTH-1:0] awaddr ; \ + bit awsize ; \ + bit awburst ; \ + bit awcache ; \ + bit awprot ; \ + bit [X-1:0] awid ; \ + bit [LEN-1:0] awlen ; \ + bit awlock ; \ + bit awqos ; \ + bit awregion ; \ + bit [X-1:0] awuser ; \ + bit wvalid ; \ + bit wready ; \ + bit wlast ; \ + bit [DATA_WIDTH-1:0] wdata ; \ + bit [DATA_WIDTH/8-1:0] wstrb ; \ + bit [X-1:0] wid ; \ + bit [X-1:0] wuser ; \ + bit bwvalid ; \ + bit bwready ; \ + bit bresp ; \ + bit [X-1:0] bid ; \ + bit [X-1:0] buser ; \ + bit arvalid ; \ + bit aready ; \ + bit [AW_WIDTH-1:0] araddr ; \ + bit arsize ; \ + bit arburst ; \ + bit arcache ; \ + bit arprot ; \ + bit [X-1:0] arid ; \ + bit [LEN-1:0] arlen ; \ + bit arlock ; \ + bit arqos ; \ + bit aregion ; \ + bit [X-1:0] aruser ; \ + bit rvalid ; \ + bit rready ; \ + bit rlast ; \ + bit [DATA_WIDTH-1:0] rdata ; \ + bit [X-1:0] rid ; \ + bit [X-1:0] ruser ; \ + bit rresp ; \ + } axi_m_responder_s; + + `define axi_m_TO_RESPONDER_STRUCT_FUNCTION \ + virtual function axi_m_responder_s to_responder_struct();\ + axi_m_responder_struct = \ + {\ + this.awvalid , \ + this.awready , \ + this.awaddr , \ + this.awsize , \ + this.awburst , \ + this.awcache , \ + this.awprot , \ + this.awid , \ + this.awlen , \ + this.awlock , \ + this.awqos , \ + this.awregion , \ + this.awuser , \ + this.wvalid , \ + this.wready , \ + this.wlast , \ + this.wdata , \ + this.wstrb , \ + this.wid , \ + this.wuser , \ + this.bwvalid , \ + this.bwready , \ + this.bresp , \ + this.bid , \ + this.buser , \ + this.arvalid , \ + this.aready , \ + this.araddr , \ + this.arsize , \ + this.arburst , \ + this.arcache , \ + this.arprot , \ + this.arid , \ + this.arlen , \ + this.arlock , \ + this.arqos , \ + this.aregion , \ + this.aruser , \ + this.rvalid , \ + this.rready , \ + this.rlast , \ + this.rdata , \ + this.rid , \ + this.ruser , \ + this.rresp \ + };\ + return ( axi_m_responder_struct);\ + endfunction + + `define axi_m_FROM_RESPONDER_STRUCT_FUNCTION \ + virtual function void from_responder_struct(axi_m_responder_s axi_m_responder_struct);\ + {\ + this.awvalid , \ + this.awready , \ + this.awaddr , \ + this.awsize , \ + this.awburst , \ + this.awcache , \ + this.awprot , \ + this.awid , \ + this.awlen , \ + this.awlock , \ + this.awqos , \ + this.awregion , \ + this.awuser , \ + this.wvalid , \ + this.wready , \ + this.wlast , \ + this.wdata , \ + this.wstrb , \ + this.wid , \ + this.wuser , \ + this.bwvalid , \ + this.bwready , \ + this.bresp , \ + this.bid , \ + this.buser , \ + this.arvalid , \ + this.aready , \ + this.araddr , \ + this.arsize , \ + this.arburst , \ + this.arcache , \ + this.arprot , \ + this.arid , \ + this.arlen , \ + this.arlock , \ + this.arqos , \ + this.aregion , \ + this.aruser , \ + this.rvalid , \ + this.rready , \ + this.rlast , \ + this.rdata , \ + this.rid , \ + this.ruser , \ + this.rresp \ + } = axi_m_responder_struct;\ + endfunction +// pragma uvmf custom additional begin +// pragma uvmf custom additional end diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/axi_m_pkg/src/axi_m_monitor.svh b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/axi_m_pkg/src/axi_m_monitor.svh new file mode 100644 index 00000000..8f4f9f70 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/axi_m_pkg/src/axi_m_monitor.svh @@ -0,0 +1,114 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This class receives axi_m transactions observed by the +// axi_m monitor BFM and broadcasts them through the analysis port +// on the agent. It accesses the monitor BFM through the monitor +// task. This UVM component captures transactions +// for viewing in the waveform viewer if the +// enable_transaction_viewing flag is set in the configuration. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +`ifndef AXI_M_MONITOR +`define AXI_M_MONITOR +class axi_m_monitor #( + int AW_WIDTH = 32, + int LEN = 8, + int DATA_WIDTH = 32, + int X = 16 + ) extends uvmf_monitor_base #( + .CONFIG_T(axi_m_configuration #( + .AW_WIDTH(AW_WIDTH), + .LEN(LEN), + .DATA_WIDTH(DATA_WIDTH), + .X(X) + )), + .BFM_BIND_T(virtual axi_m_monitor_bfm #( + .AW_WIDTH(AW_WIDTH), + .LEN(LEN), + .DATA_WIDTH(DATA_WIDTH), + .X(X) + )), + .TRANS_T(axi_m_transaction #( + .AW_WIDTH(AW_WIDTH), + .LEN(LEN), + .DATA_WIDTH(DATA_WIDTH), + .X(X) + ))); + + `uvm_component_param_utils( axi_m_monitor #( + AW_WIDTH, + LEN, + DATA_WIDTH, + X + )) + +// Structure used to pass data from monitor BFM to monitor class in agent. +// Use to_monitor_struct function to pack transaction variables into structure. +// Use from_monitor_struct function to unpack transaction variables from structure. +`axi_m_MONITOR_STRUCT + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + +// **************************************************************************** +// This function is the standard SystemVerilog constructor. +// + function new( string name = "", uvm_component parent = null ); + super.new( name, parent ); + endfunction + +// **************************************************************************** +// This function sends configuration object variables to the monitor BFM +// using the configuration struct. +// + virtual function void configure(input CONFIG_T cfg); + bfm.configure( cfg.to_struct() ); + + endfunction + +// **************************************************************************** +// This function places a handle to this class in the proxy variable in the +// monitor BFM. This allows the monitor BFM to call the notify_transaction +// function within this class. +// + virtual function void set_bfm_proxy_handle(); + bfm.proxy = this; endfunction + +// *************************************************************************** + virtual task run_phase(uvm_phase phase); + // Start monitor BFM thread and don't call super.run() in order to + // override the default monitor proxy 'pull' behavior with the more + // emulation-friendly BFM 'push' approach using the notify_transaction + // function below + bfm.start_monitoring(); + endtask + +// ************************************************************************** + +// This function is called by the monitor BFM. It receives data observed by the +// monitor BFM. Data is passed using the axi_m_monitor_struct. + virtual function void notify_transaction(input axi_m_monitor_s axi_m_monitor_struct); + + + trans = new("trans"); + trans.from_monitor_struct(axi_m_monitor_struct); + trans.start_time = time_stamp; + trans.end_time = $time; + time_stamp = trans.end_time; + + analyze(trans); + endfunction + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end +`endif diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/axi_m_pkg/src/axi_m_monitor_bfm.sv b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/axi_m_pkg/src/axi_m_monitor_bfm.sv new file mode 100644 index 00000000..33b792d2 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/axi_m_pkg/src/axi_m_monitor_bfm.sv @@ -0,0 +1,362 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This interface performs the axi_m signal monitoring. +// It is accessed by the uvm axi_m monitor through a virtual +// interface handle in the axi_m configuration. It monitors the +// signals passed in through the port connection named bus of +// type axi_m_if. +// +// Input signals from the axi_m_if are assigned to an internal input +// signal with a _i suffix. The _i signal should be used for sampling. +// +// The input signal connections are as follows: +// bus.signal -> signal_i +// +// Interface functions and tasks used by UVM components: +// monitor(inout TRANS_T txn); +// This task receives the transaction, txn, from the +// UVM monitor and then populates variables in txn +// from values observed on bus activity. This task +// blocks until an operation on the axi_m bus is complete. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +`ifndef AXI_M_MONITOR_BFM +`define AXI_M_MONITOR_BFM +import uvmf_base_pkg_hdl::*; +import axi_m_pkg_hdl::*; +`include "src/axi_m_macros.svh" + + +interface axi_m_monitor_bfm #( + int AW_WIDTH = 32, + int LEN = 8, + int DATA_WIDTH = 32, + int X = 16 + ) + ( axi_m_if bus ); + // The pragma below and additional ones in-lined further down are for running this BFM on Veloce + // pragma attribute axi_m_monitor_bfm partition_interface_xif + +`ifndef XRTL +// This code is to aid in debugging parameter mismatches between the BFM and its corresponding agent. +// Enable this debug by setting UVM_VERBOSITY to UVM_DEBUG +// Setting UVM_VERBOSITY to UVM_DEBUG causes all BFM's and all agents to display their parameter settings. +// All of the messages from this feature have a UVM messaging id value of "CFG" +// The transcript or run.log can be parsed to ensure BFM parameter settings match its corresponding agents parameter settings. +import uvm_pkg::*; +`include "uvm_macros.svh" +initial begin : bfm_vs_agent_parameter_debug + `uvm_info("CFG", + $psprintf("The BFM at '%m' has the following parameters: AW_WIDTH=%x LEN=%x DATA_WIDTH=%x X=%x ", AW_WIDTH,LEN,DATA_WIDTH,X), + UVM_DEBUG) +end +`endif + + + // Structure used to pass transaction data from monitor BFM to monitor class in agent. +`axi_m_MONITOR_STRUCT + axi_m_monitor_s axi_m_monitor_struct; + + // Structure used to pass configuration data from monitor class to monitor BFM. + `axi_m_CONFIGURATION_STRUCT + + + // Config value to determine if this is an initiator or a responder + uvmf_initiator_responder_t initiator_responder; + // Custom configuration variables. + // These are set using the configure function which is called during the UVM connect_phase + + logic axi_clk_i; + logic rst_i; + tri awvalid_i; + tri awready_i; + tri [AW_WIDTH-1:0] awaddr_i; + tri [2:0] awsize_i; + tri [1:0] awburst_i; + tri [3:0] awcache_i; + tri [2:0] awprot_i; + tri [X-1:0] awid_i; + tri [LEN-1:0] awlen_i; + tri awlock_i; + tri [3:0] awqos_i; + tri [3:0] awregion_i; + tri [X-1:0] awuser_i; + tri wvalid_i; + tri wready_i; + tri wlast_i; + tri [DATA_WIDTH-1:0] wdata_i; + tri [DATA_WIDTH/8-1:0] wstrb_i; + tri [X-1:0] wid_i; + tri [X-1:0] wuser_i; + tri bwvalid_i; + tri bwready_i; + tri [1:0] bresp_i; + tri [X-1:0] bid_i; + tri [X-1:0] buser_i; + tri arvalid_i; + tri aready_i; + tri [AW_WIDTH-1:0] araddr_i; + tri [2:0] arsize_i; + tri [1:0] arburst_i; + tri [3:0] arcache_i; + tri [2:0] arprot_i; + tri [X-1:0] arid_i; + tri [LEN-1:0] arlen_i; + tri arlock_i; + tri [3:0] arqos_i; + tri [3:0] aregion_i; + tri [X-1:0] aruser_i; + tri rvalid_i; + tri rready_i; + tri rlast_i; + tri [DATA_WIDTH-1:0] rdata_i; + tri [X-1:0] rid_i; + tri [X-1:0] ruser_i; + tri [1:0] rresp_i; + assign axi_clk_i = bus.axi_clk; + assign rst_i = bus.rst; + assign awvalid_i = bus.awvalid; + assign awready_i = bus.awready; + assign awaddr_i = bus.awaddr; + assign awsize_i = bus.awsize; + assign awburst_i = bus.awburst; + assign awcache_i = bus.awcache; + assign awprot_i = bus.awprot; + assign awid_i = bus.awid; + assign awlen_i = bus.awlen; + assign awlock_i = bus.awlock; + assign awqos_i = bus.awqos; + assign awregion_i = bus.awregion; + assign awuser_i = bus.awuser; + assign wvalid_i = bus.wvalid; + assign wready_i = bus.wready; + assign wlast_i = bus.wlast; + assign wdata_i = bus.wdata; + assign wstrb_i = bus.wstrb; + assign wid_i = bus.wid; + assign wuser_i = bus.wuser; + assign bwvalid_i = bus.bwvalid; + assign bwready_i = bus.bwready; + assign bresp_i = bus.bresp; + assign bid_i = bus.bid; + assign buser_i = bus.buser; + assign arvalid_i = bus.arvalid; + assign aready_i = bus.aready; + assign araddr_i = bus.araddr; + assign arsize_i = bus.arsize; + assign arburst_i = bus.arburst; + assign arcache_i = bus.arcache; + assign arprot_i = bus.arprot; + assign arid_i = bus.arid; + assign arlen_i = bus.arlen; + assign arlock_i = bus.arlock; + assign arqos_i = bus.arqos; + assign aregion_i = bus.aregion; + assign aruser_i = bus.aruser; + assign rvalid_i = bus.rvalid; + assign rready_i = bus.rready; + assign rlast_i = bus.rlast; + assign rdata_i = bus.rdata; + assign rid_i = bus.rid; + assign ruser_i = bus.ruser; + assign rresp_i = bus.rresp; + + // Proxy handle to UVM monitor + axi_m_pkg::axi_m_monitor #( + .AW_WIDTH(AW_WIDTH), + .LEN(LEN), + .DATA_WIDTH(DATA_WIDTH), + .X(X) + ) proxy; + // pragma tbx oneway proxy.notify_transaction + + // pragma uvmf custom interface_item_additional begin + // pragma uvmf custom interface_item_additional end + + //****************************************************************** + task wait_for_reset();// pragma tbx xtf + @(posedge axi_clk_i) ; + do_wait_for_reset(); + endtask + + // **************************************************************************** + task do_wait_for_reset(); + // pragma uvmf custom reset_condition begin + wait ( rst_i === 1 ) ; + @(posedge axi_clk_i) ; + // pragma uvmf custom reset_condition end + endtask + + //****************************************************************** + + task wait_for_num_clocks(input int unsigned count); // pragma tbx xtf + @(posedge axi_clk_i); + + repeat (count-1) @(posedge axi_clk_i); + endtask + + //****************************************************************** + event go; + function void start_monitoring();// pragma tbx xtf + -> go; + endfunction + + // **************************************************************************** + initial begin + @go; + forever begin + @(posedge axi_clk_i); + do_monitor( axi_m_monitor_struct ); + + + proxy.notify_transaction( axi_m_monitor_struct ); + + end + end + + //****************************************************************** + // The configure() function is used to pass agent configuration + // variables to the monitor BFM. It is called by the monitor within + // the agent at the beginning of the simulation. It may be called + // during the simulation if agent configuration variables are updated + // and the monitor BFM needs to be aware of the new configuration + // variables. + // + function void configure(axi_m_configuration_s axi_m_configuration_arg); // pragma tbx xtf + initiator_responder = axi_m_configuration_arg.initiator_responder; + // pragma uvmf custom configure begin + // pragma uvmf custom configure end + endfunction + + + // **************************************************************************** + + task do_monitor(output axi_m_monitor_s axi_m_monitor_struct); + // + // Available struct members: + // // axi_m_monitor_struct.awvalid + // // axi_m_monitor_struct.awready + // // axi_m_monitor_struct.awaddr + // // axi_m_monitor_struct.awsize + // // axi_m_monitor_struct.awburst + // // axi_m_monitor_struct.awcache + // // axi_m_monitor_struct.awprot + // // axi_m_monitor_struct.awid + // // axi_m_monitor_struct.awlen + // // axi_m_monitor_struct.awlock + // // axi_m_monitor_struct.awqos + // // axi_m_monitor_struct.awregion + // // axi_m_monitor_struct.awuser + // // axi_m_monitor_struct.wvalid + // // axi_m_monitor_struct.wready + // // axi_m_monitor_struct.wlast + // // axi_m_monitor_struct.wdata + // // axi_m_monitor_struct.wstrb + // // axi_m_monitor_struct.wid + // // axi_m_monitor_struct.wuser + // // axi_m_monitor_struct.bwvalid + // // axi_m_monitor_struct.bwready + // // axi_m_monitor_struct.bresp + // // axi_m_monitor_struct.bid + // // axi_m_monitor_struct.buser + // // axi_m_monitor_struct.arvalid + // // axi_m_monitor_struct.aready + // // axi_m_monitor_struct.araddr + // // axi_m_monitor_struct.arsize + // // axi_m_monitor_struct.arburst + // // axi_m_monitor_struct.arcache + // // axi_m_monitor_struct.arprot + // // axi_m_monitor_struct.arid + // // axi_m_monitor_struct.arlen + // // axi_m_monitor_struct.arlock + // // axi_m_monitor_struct.arqos + // // axi_m_monitor_struct.aregion + // // axi_m_monitor_struct.aruser + // // axi_m_monitor_struct.rvalid + // // axi_m_monitor_struct.rready + // // axi_m_monitor_struct.rlast + // // axi_m_monitor_struct.rdata + // // axi_m_monitor_struct.rid + // // axi_m_monitor_struct.ruser + // // axi_m_monitor_struct.rresp + // // + // Reference code; + // How to wait for signal value + // while (control_signal === 1'b1) @(posedge axi_clk_i); + // + // How to assign a struct member, named xyz, from a signal. + // All available input signals listed. + // axi_m_monitor_struct.xyz = awvalid_i; // + // axi_m_monitor_struct.xyz = awready_i; // + // axi_m_monitor_struct.xyz = awaddr_i; // [AW_WIDTH-1:0] + // axi_m_monitor_struct.xyz = awsize_i; // [2:0] + // axi_m_monitor_struct.xyz = awburst_i; // [1:0] + // axi_m_monitor_struct.xyz = awcache_i; // [3:0] + // axi_m_monitor_struct.xyz = awprot_i; // [2:0] + // axi_m_monitor_struct.xyz = awid_i; // [X-1:0] + // axi_m_monitor_struct.xyz = awlen_i; // [LEN-1:0] + // axi_m_monitor_struct.xyz = awlock_i; // + // axi_m_monitor_struct.xyz = awqos_i; // [3:0] + // axi_m_monitor_struct.xyz = awregion_i; // [3:0] + // axi_m_monitor_struct.xyz = awuser_i; // [X-1:0] + // axi_m_monitor_struct.xyz = wvalid_i; // + // axi_m_monitor_struct.xyz = wready_i; // + // axi_m_monitor_struct.xyz = wlast_i; // + // axi_m_monitor_struct.xyz = wdata_i; // [DATA_WIDTH-1:0] + // axi_m_monitor_struct.xyz = wstrb_i; // [DATA_WIDTH/8-1:0] + // axi_m_monitor_struct.xyz = wid_i; // [X-1:0] + // axi_m_monitor_struct.xyz = wuser_i; // [X-1:0] + // axi_m_monitor_struct.xyz = bwvalid_i; // + // axi_m_monitor_struct.xyz = bwready_i; // + // axi_m_monitor_struct.xyz = bresp_i; // [1:0] + // axi_m_monitor_struct.xyz = bid_i; // [X-1:0] + // axi_m_monitor_struct.xyz = buser_i; // [X-1:0] + // axi_m_monitor_struct.xyz = arvalid_i; // + // axi_m_monitor_struct.xyz = aready_i; // + // axi_m_monitor_struct.xyz = araddr_i; // [AW_WIDTH-1:0] + // axi_m_monitor_struct.xyz = arsize_i; // [2:0] + // axi_m_monitor_struct.xyz = arburst_i; // [1:0] + // axi_m_monitor_struct.xyz = arcache_i; // [3:0] + // axi_m_monitor_struct.xyz = arprot_i; // [2:0] + // axi_m_monitor_struct.xyz = arid_i; // [X-1:0] + // axi_m_monitor_struct.xyz = arlen_i; // [LEN-1:0] + // axi_m_monitor_struct.xyz = arlock_i; // + // axi_m_monitor_struct.xyz = arqos_i; // [3:0] + // axi_m_monitor_struct.xyz = aregion_i; // [3:0] + // axi_m_monitor_struct.xyz = aruser_i; // [X-1:0] + // axi_m_monitor_struct.xyz = rvalid_i; // + // axi_m_monitor_struct.xyz = rready_i; // + // axi_m_monitor_struct.xyz = rlast_i; // + // axi_m_monitor_struct.xyz = rdata_i; // [DATA_WIDTH-1:0] + // axi_m_monitor_struct.xyz = rid_i; // [X-1:0] + // axi_m_monitor_struct.xyz = ruser_i; // [X-1:0] + // axi_m_monitor_struct.xyz = rresp_i; // [1:0] + // pragma uvmf custom do_monitor begin + // UVMF_CHANGE_ME : Implement protocol monitoring. The commented reference code + // below are examples of how to capture signal values and assign them to + // structure members. All available input signals are listed. The 'while' + // code example shows how to wait for a synchronous flow control signal. This + // task should return when a complete transfer has been observed. Once this task is + // exited with captured values, it is then called again to wait for and observe + // the next transfer. One clock cycle is consumed between calls to do_monitor. + @(posedge axi_clk_i); + @(posedge axi_clk_i); + @(posedge axi_clk_i); + @(posedge axi_clk_i); + // pragma uvmf custom do_monitor end + endtask + + +endinterface + +// pragma uvmf custom external begin +// pragma uvmf custom external end +`endif diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/axi_m_pkg/src/axi_m_random_sequence.svh b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/axi_m_pkg/src/axi_m_random_sequence.svh new file mode 100644 index 00000000..977d2ac1 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/axi_m_pkg/src/axi_m_random_sequence.svh @@ -0,0 +1,75 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: +// This sequences randomizes the axi_m transaction and sends it +// to the UVM driver. +// +// This sequence constructs and randomizes a axi_m_transaction. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +`ifndef AXI_M_RANDOM_SEQUENCE +`define AXI_M_RANDOM_SEQUENCE +class axi_m_random_sequence #( + int AW_WIDTH = 32, + int LEN = 8, + int DATA_WIDTH = 32, + int X = 16 + ) + extends axi_m_sequence_base #( + .AW_WIDTH(AW_WIDTH), + .LEN(LEN), + .DATA_WIDTH(DATA_WIDTH), + .X(X) + ); + + `uvm_object_param_utils( axi_m_random_sequence #( + AW_WIDTH, + LEN, + DATA_WIDTH, + X + )) + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + //***************************************************************** + function new(string name = ""); + super.new(name); + endfunction: new + + // **************************************************************************** + // TASK : body() + // This task is automatically executed when this sequence is started using the + // start(sequencerHandle) task. + // + task body(); + + // Construct the transaction + req=axi_m_transaction#( + .AW_WIDTH(AW_WIDTH), + .LEN(LEN), + .DATA_WIDTH(DATA_WIDTH), + .X(X) + )::type_id::create("req"); + start_item(req); + // Randomize the transaction + if(!req.randomize()) `uvm_fatal("SEQ", "axi_m_random_sequence::body()-axi_m_transaction randomization failed") + // Send the transaction to the axi_m_driver_bfm via the sequencer and axi_m_driver. + finish_item(req); + `uvm_info("SEQ", {"Response:",req.convert2string()},UVM_MEDIUM) + + endtask + +endclass: axi_m_random_sequence + +// pragma uvmf custom external begin +// pragma uvmf custom external end +`endif diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/axi_m_pkg/src/axi_m_responder_sequence.svh b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/axi_m_pkg/src/axi_m_responder_sequence.svh new file mode 100644 index 00000000..5e3f3d4d --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/axi_m_pkg/src/axi_m_responder_sequence.svh @@ -0,0 +1,71 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This class can be used to provide stimulus when an interface +// has been configured to run in a responder mode. It +// will never finish by default, always going back to the driver +// and driver BFM for the next transaction with which to respond. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +`ifndef AXI_M_RESPONDER_SEQUENCE +`define AXI_M_RESPONDER_SEQUENCE +class axi_m_responder_sequence #( + int AW_WIDTH = 32, + int LEN = 8, + int DATA_WIDTH = 32, + int X = 16 + ) + extends axi_m_sequence_base #( + .AW_WIDTH(AW_WIDTH), + .LEN(LEN), + .DATA_WIDTH(DATA_WIDTH), + .X(X) + ); + + `uvm_object_param_utils( axi_m_responder_sequence #( + AW_WIDTH, + LEN, + DATA_WIDTH, + X + )) + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + function new(string name = "axi_m_responder_sequence"); + super.new(name); + endfunction + + task body(); + req=axi_m_transaction#( + .AW_WIDTH(AW_WIDTH), + .LEN(LEN), + .DATA_WIDTH(DATA_WIDTH), + .X(X) + )::type_id::create("req"); + forever begin + start_item(req); + finish_item(req); + // pragma uvmf custom body begin + // UVMF_CHANGE_ME : Do something here with the resulting req item. The + // finish_item() call above will block until the req transaction is ready + // to be handled by the responder sequence. + // If this was an item that required a response, the expectation is + // that the response should be populated within this transaction now. + `uvm_info("SEQ",$sformatf("Processed txn: %s",req.convert2string()),UVM_HIGH) + // pragma uvmf custom body end + end + endtask + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end +`endif diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/axi_m_pkg/src/axi_m_sequence_base.svh b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/axi_m_pkg/src/axi_m_sequence_base.svh new file mode 100644 index 00000000..7a65c5ba --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/axi_m_pkg/src/axi_m_sequence_base.svh @@ -0,0 +1,128 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: +// This file contains the class used as the base class for all sequences +// for this interface. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +`ifndef AXI_M_SEQUENCE_BASE +`define AXI_M_SEQUENCE_BASE +class axi_m_sequence_base #( + int AW_WIDTH = 32, + int LEN = 8, + int DATA_WIDTH = 32, + int X = 16 + ) extends uvmf_sequence_base #( + .REQ(axi_m_transaction #( + .AW_WIDTH(AW_WIDTH), + .LEN(LEN), + .DATA_WIDTH(DATA_WIDTH), + .X(X) + )), + .RSP(axi_m_transaction #( + .AW_WIDTH(AW_WIDTH), + .LEN(LEN), + .DATA_WIDTH(DATA_WIDTH), + .X(X) + ))); + + `uvm_object_param_utils( axi_m_sequence_base #( + AW_WIDTH, + LEN, + DATA_WIDTH, + X + )) + + // variables + typedef axi_m_transaction #( + .AW_WIDTH(AW_WIDTH), + .LEN(LEN), + .DATA_WIDTH(DATA_WIDTH), + .X(X) + ) axi_m_transaction_req_t; + axi_m_transaction_req_t req; + typedef axi_m_transaction #( + .AW_WIDTH(AW_WIDTH), + .LEN(LEN), + .DATA_WIDTH(DATA_WIDTH), + .X(X) + ) axi_m_transaction_rsp_t; + axi_m_transaction_rsp_t rsp; + + // Event for identifying when a response was received from the sequencer + event new_rsp; + + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + // **************************************************************************** + // TASK : get_responses() + // This task recursively gets sequence item responses from the sequencer. + // + virtual task get_responses(); + fork + begin + // Block until new rsp available + get_response(rsp); + // New rsp received. Indicate to sequence using event. + ->new_rsp; + // Display the received response transaction + `uvm_info("SEQ", {"New response transaction:",rsp.convert2string()}, UVM_MEDIUM) + end + join_none + endtask + + // **************************************************************************** + // TASK : pre_body() + // This task is called automatically when start is called with call_pre_post set to 1 (default). + // By calling get_responses() within pre_body() any derived sequences are automatically + // processing response transactions. Only un-comment this call to get_responses() if you + // have configured the interface driver to utilize the response transaction path by setting + // the configuration variable "return_transaction_response" to 1. Otherwise it is possible + // to impact runtime performance and memory utilization. + // + virtual task pre_body(); + // pragma uvmf custom pre_body begin +// get_responses(); + // pragma uvmf custom pre_body end + endtask + + // **************************************************************************** + // TASK : body() + // This task is called automatically when start is called. This sequence sends + // a req sequence item to the sequencer identified as an argument in the call + // to start. + // + virtual task body(); + // pragma uvmf custom body begin + start_item(req); + finish_item(req); + // pragma uvmf custom body end + endtask + + // **************************************************************************** + // FUNCTION : new() + // This function is the standard SystemVerilog constructor. + // + function new( string name =""); + super.new( name ); + // pragma uvmf custom new begin + req = axi_m_transaction_req_t::type_id::create("req"); + rsp = axi_m_transaction_rsp_t::type_id::create("rsp"); + // pragma uvmf custom new end + endfunction + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end +`endif diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/axi_m_pkg/src/axi_m_transaction.svh b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/axi_m_pkg/src/axi_m_transaction.svh new file mode 100644 index 00000000..31342cde --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/axi_m_pkg/src/axi_m_transaction.svh @@ -0,0 +1,335 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This class defines the variables required for an axi_m +// transaction. Class variables to be displayed in waveform transaction +// viewing are added to the transaction viewing stream in the add_to_wave +// function. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +`ifndef AXI_M_TRANSACTION +`define AXI_M_TRANSACTION +class axi_m_transaction #( + int AW_WIDTH = 32, + int LEN = 8, + int DATA_WIDTH = 32, + int X = 16 + ) extends uvmf_transaction_base; + + `uvm_object_param_utils( axi_m_transaction #( + AW_WIDTH, + LEN, + DATA_WIDTH, + X + )) + + bit awvalid ; + bit awready ; + rand bit [AW_WIDTH-1:0] awaddr ; + rand bit awsize ; + rand bit awburst ; + rand bit awcache ; + rand bit awprot ; + rand bit [X-1:0] awid ; + rand bit [LEN-1:0] awlen ; + rand bit awlock ; + rand bit awqos ; + rand bit awregion ; + rand bit [X-1:0] awuser ; + bit wvalid ; + bit wready ; + bit wlast ; + rand bit [DATA_WIDTH-1:0] wdata ; + rand bit [DATA_WIDTH/8-1:0] wstrb ; + bit [X-1:0] wid ; + rand bit [X-1:0] wuser ; + bit bwvalid ; + bit bwready ; + rand bit bresp ; + bit [X-1:0] bid ; + rand bit [X-1:0] buser ; + bit arvalid ; + bit aready ; + rand bit [AW_WIDTH-1:0] araddr ; + rand bit arsize ; + rand bit arburst ; + rand bit arcache ; + rand bit arprot ; + rand bit [X-1:0] arid ; + rand bit [LEN-1:0] arlen ; + rand bit arlock ; + rand bit arqos ; + rand bit aregion ; + rand bit [X-1:0] aruser ; + bit rvalid ; + bit rready ; + bit rlast ; + rand bit [DATA_WIDTH-1:0] rdata ; + rand bit [X-1:0] rid ; + rand bit [X-1:0] ruser ; + rand bit rresp ; + + //Constraints for the transaction variables: + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + //******************************************************************* + //******************************************************************* + // Macros that define structs and associated functions are + // located in axi_m_macros.svh + + //******************************************************************* + // Monitor macro used by axi_m_monitor and axi_m_monitor_bfm + // This struct is defined in axi_m_macros.svh + `axi_m_MONITOR_STRUCT + axi_m_monitor_s axi_m_monitor_struct; + //******************************************************************* + // FUNCTION: to_monitor_struct() + // This function packs transaction variables into a axi_m_monitor_s + // structure. The function returns the handle to the axi_m_monitor_struct. + // This function is defined in axi_m_macros.svh + `axi_m_TO_MONITOR_STRUCT_FUNCTION + //******************************************************************* + // FUNCTION: from_monitor_struct() + // This function unpacks the struct provided as an argument into transaction + // variables of this class. + // This function is defined in axi_m_macros.svh + `axi_m_FROM_MONITOR_STRUCT_FUNCTION + + //******************************************************************* + // Initiator macro used by axi_m_driver and axi_m_driver_bfm + // to communicate initiator driven data to axi_m_driver_bfm. + // This struct is defined in axi_m_macros.svh + `axi_m_INITIATOR_STRUCT + axi_m_initiator_s axi_m_initiator_struct; + //******************************************************************* + // FUNCTION: to_initiator_struct() + // This function packs transaction variables into a axi_m_initiator_s + // structure. The function returns the handle to the axi_m_initiator_struct. + // This function is defined in axi_m_macros.svh + `axi_m_TO_INITIATOR_STRUCT_FUNCTION + //******************************************************************* + // FUNCTION: from_initiator_struct() + // This function unpacks the struct provided as an argument into transaction + // variables of this class. + // This function is defined in axi_m_macros.svh + `axi_m_FROM_INITIATOR_STRUCT_FUNCTION + + //******************************************************************* + // Responder macro used by axi_m_driver and axi_m_driver_bfm + // to communicate Responder driven data to axi_m_driver_bfm. + // This struct is defined in axi_m_macros.svh + `axi_m_RESPONDER_STRUCT + axi_m_responder_s axi_m_responder_struct; + //******************************************************************* + // FUNCTION: to_responder_struct() + // This function packs transaction variables into a axi_m_responder_s + // structure. The function returns the handle to the axi_m_responder_struct. + // This function is defined in axi_m_macros.svh + `axi_m_TO_RESPONDER_STRUCT_FUNCTION + //******************************************************************* + // FUNCTION: from_responder_struct() + // This function unpacks the struct provided as an argument into transaction + // variables of this class. + // This function is defined in axi_m_macros.svh + `axi_m_FROM_RESPONDER_STRUCT_FUNCTION + // **************************************************************************** + // FUNCTION : new() + // This function is the standard SystemVerilog constructor. + // + function new( string name = "" ); + super.new( name ); + endfunction + + // **************************************************************************** + // FUNCTION: convert2string() + // This function converts all variables in this class to a single string for + // logfile reporting. + // + virtual function string convert2string(); + // pragma uvmf custom convert2string begin + // UVMF_CHANGE_ME : Customize format if desired. + return $sformatf("awvalid:0x%x awready:0x%x awaddr:0x%x awsize:0x%x awburst:0x%x awcache:0x%x awprot:0x%x awid:0x%x awlen:0x%x awlock:0x%x awqos:0x%x awregion:0x%x awuser:0x%x wvalid:0x%x wready:0x%x wlast:0x%x wdata:0x%x wstrb:0x%x wid:0x%x wuser:0x%x bwvalid:0x%x bwready:0x%x bresp:0x%x bid:0x%x buser:0x%x arvalid:0x%x aready:0x%x araddr:0x%x arsize:0x%x arburst:0x%x arcache:0x%x arprot:0x%x arid:0x%x arlen:0x%x arlock:0x%x arqos:0x%x aregion:0x%x aruser:0x%x rvalid:0x%x rready:0x%x rlast:0x%x rdata:0x%x rid:0x%x ruser:0x%x rresp:0x%x ",awvalid,awready,awaddr,awsize,awburst,awcache,awprot,awid,awlen,awlock,awqos,awregion,awuser,wvalid,wready,wlast,wdata,wstrb,wid,wuser,bwvalid,bwready,bresp,bid,buser,arvalid,aready,araddr,arsize,arburst,arcache,arprot,arid,arlen,arlock,arqos,aregion,aruser,rvalid,rready,rlast,rdata,rid,ruser,rresp); + // pragma uvmf custom convert2string end + endfunction + + //******************************************************************* + // FUNCTION: do_print() + // This function is automatically called when the .print() function + // is called on this class. + // + virtual function void do_print(uvm_printer printer); + // pragma uvmf custom do_print begin + // UVMF_CHANGE_ME : Current contents of do_print allows for the use of UVM 1.1d, 1.2 or P1800.2. + // Update based on your own printing preference according to your preferred UVM version + $display(convert2string()); + // pragma uvmf custom do_print end + endfunction + + //******************************************************************* + // FUNCTION: do_compare() + // This function is automatically called when the .compare() function + // is called on this class. + // + virtual function bit do_compare (uvm_object rhs, uvm_comparer comparer); + axi_m_transaction #( + .AW_WIDTH(AW_WIDTH), + .LEN(LEN), + .DATA_WIDTH(DATA_WIDTH), + .X(X) + ) RHS; + if (!$cast(RHS,rhs)) return 0; + // pragma uvmf custom do_compare begin + // UVMF_CHANGE_ME : Eliminate comparison of variables not to be used for compare + return (super.do_compare(rhs,comparer) + ); + // pragma uvmf custom do_compare end + endfunction + + //******************************************************************* + // FUNCTION: do_copy() + // This function is automatically called when the .copy() function + // is called on this class. + // + virtual function void do_copy (uvm_object rhs); + axi_m_transaction #( + .AW_WIDTH(AW_WIDTH), + .LEN(LEN), + .DATA_WIDTH(DATA_WIDTH), + .X(X) + ) RHS; + assert($cast(RHS,rhs)); + // pragma uvmf custom do_copy begin + super.do_copy(rhs); + this.awvalid = RHS.awvalid; + this.awready = RHS.awready; + this.awaddr = RHS.awaddr; + this.awsize = RHS.awsize; + this.awburst = RHS.awburst; + this.awcache = RHS.awcache; + this.awprot = RHS.awprot; + this.awid = RHS.awid; + this.awlen = RHS.awlen; + this.awlock = RHS.awlock; + this.awqos = RHS.awqos; + this.awregion = RHS.awregion; + this.awuser = RHS.awuser; + this.wvalid = RHS.wvalid; + this.wready = RHS.wready; + this.wlast = RHS.wlast; + this.wdata = RHS.wdata; + this.wstrb = RHS.wstrb; + this.wid = RHS.wid; + this.wuser = RHS.wuser; + this.bwvalid = RHS.bwvalid; + this.bwready = RHS.bwready; + this.bresp = RHS.bresp; + this.bid = RHS.bid; + this.buser = RHS.buser; + this.arvalid = RHS.arvalid; + this.aready = RHS.aready; + this.araddr = RHS.araddr; + this.arsize = RHS.arsize; + this.arburst = RHS.arburst; + this.arcache = RHS.arcache; + this.arprot = RHS.arprot; + this.arid = RHS.arid; + this.arlen = RHS.arlen; + this.arlock = RHS.arlock; + this.arqos = RHS.arqos; + this.aregion = RHS.aregion; + this.aruser = RHS.aruser; + this.rvalid = RHS.rvalid; + this.rready = RHS.rready; + this.rlast = RHS.rlast; + this.rdata = RHS.rdata; + this.rid = RHS.rid; + this.ruser = RHS.ruser; + this.rresp = RHS.rresp; + // pragma uvmf custom do_copy end + endfunction + + // **************************************************************************** + // FUNCTION: add_to_wave() + // This function is used to display variables in this class in the waveform + // viewer. The start_time and end_time variables must be set before this + // function is called. If the start_time and end_time variables are not set + // the transaction will be hidden at 0ns on the waveform display. + // + virtual function void add_to_wave(int transaction_viewing_stream_h); + `ifdef QUESTA + if (transaction_view_h == 0) begin + transaction_view_h = $begin_transaction(transaction_viewing_stream_h,"axi_m_transaction",start_time); + end + super.add_to_wave(transaction_view_h); + // pragma uvmf custom add_to_wave begin + // UVMF_CHANGE_ME : Color can be applied to transaction entries based on content, example below + // case() + // 1 : $add_color(transaction_view_h,"red"); + // default : $add_color(transaction_view_h,"grey"); + // endcase + // UVMF_CHANGE_ME : Eliminate transaction variables not wanted in transaction viewing in the waveform viewer + $add_attribute(transaction_view_h,awvalid,"awvalid"); + $add_attribute(transaction_view_h,awready,"awready"); + $add_attribute(transaction_view_h,awaddr,"awaddr"); + $add_attribute(transaction_view_h,awsize,"awsize"); + $add_attribute(transaction_view_h,awburst,"awburst"); + $add_attribute(transaction_view_h,awcache,"awcache"); + $add_attribute(transaction_view_h,awprot,"awprot"); + $add_attribute(transaction_view_h,awid,"awid"); + $add_attribute(transaction_view_h,awlen,"awlen"); + $add_attribute(transaction_view_h,awlock,"awlock"); + $add_attribute(transaction_view_h,awqos,"awqos"); + $add_attribute(transaction_view_h,awregion,"awregion"); + $add_attribute(transaction_view_h,awuser,"awuser"); + $add_attribute(transaction_view_h,wvalid,"wvalid"); + $add_attribute(transaction_view_h,wready,"wready"); + $add_attribute(transaction_view_h,wlast,"wlast"); + $add_attribute(transaction_view_h,wdata,"wdata"); + $add_attribute(transaction_view_h,wstrb,"wstrb"); + $add_attribute(transaction_view_h,wid,"wid"); + $add_attribute(transaction_view_h,wuser,"wuser"); + $add_attribute(transaction_view_h,bwvalid,"bwvalid"); + $add_attribute(transaction_view_h,bwready,"bwready"); + $add_attribute(transaction_view_h,bresp,"bresp"); + $add_attribute(transaction_view_h,bid,"bid"); + $add_attribute(transaction_view_h,buser,"buser"); + $add_attribute(transaction_view_h,arvalid,"arvalid"); + $add_attribute(transaction_view_h,aready,"aready"); + $add_attribute(transaction_view_h,araddr,"araddr"); + $add_attribute(transaction_view_h,arsize,"arsize"); + $add_attribute(transaction_view_h,arburst,"arburst"); + $add_attribute(transaction_view_h,arcache,"arcache"); + $add_attribute(transaction_view_h,arprot,"arprot"); + $add_attribute(transaction_view_h,arid,"arid"); + $add_attribute(transaction_view_h,arlen,"arlen"); + $add_attribute(transaction_view_h,arlock,"arlock"); + $add_attribute(transaction_view_h,arqos,"arqos"); + $add_attribute(transaction_view_h,aregion,"aregion"); + $add_attribute(transaction_view_h,aruser,"aruser"); + $add_attribute(transaction_view_h,rvalid,"rvalid"); + $add_attribute(transaction_view_h,rready,"rready"); + $add_attribute(transaction_view_h,rlast,"rlast"); + $add_attribute(transaction_view_h,rdata,"rdata"); + $add_attribute(transaction_view_h,rid,"rid"); + $add_attribute(transaction_view_h,ruser,"ruser"); + $add_attribute(transaction_view_h,rresp,"rresp"); + // pragma uvmf custom add_to_wave end + $end_transaction(transaction_view_h,end_time); + $free_transaction(transaction_view_h); + `endif // QUESTA + endfunction + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end +`endif diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/axi_m_pkg/src/axi_m_transaction_coverage.svh b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/axi_m_pkg/src/axi_m_transaction_coverage.svh new file mode 100644 index 00000000..59820a17 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/axi_m_pkg/src/axi_m_transaction_coverage.svh @@ -0,0 +1,132 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This class records axi_m transaction information using +// a covergroup named axi_m_transaction_cg. An instance of this +// coverage component is instantiated in the uvmf_parameterized_agent +// if the has_coverage flag is set. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +`ifndef AXI_M_TRANSACTION_COVERAGE +`define AXI_M_TRANSACTION_COVERAGE +class axi_m_transaction_coverage #( + int AW_WIDTH = 32, + int LEN = 8, + int DATA_WIDTH = 32, + int X = 16 + ) extends uvm_subscriber #(.T(axi_m_transaction #( + .AW_WIDTH(AW_WIDTH), + .LEN(LEN), + .DATA_WIDTH(DATA_WIDTH), + .X(X) + ))); + + `uvm_component_param_utils( axi_m_transaction_coverage #( + AW_WIDTH, + LEN, + DATA_WIDTH, + X + )) + + T coverage_trans; + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + // **************************************************************************** + covergroup axi_m_transaction_cg; + // pragma uvmf custom covergroup begin + // UVMF_CHANGE_ME : Add coverage bins, crosses, exclusions, etc. according to coverage needs. + option.auto_bin_max=1024; + option.per_instance=1; + awvalid: coverpoint coverage_trans.awvalid; + awready: coverpoint coverage_trans.awready; + awaddr: coverpoint coverage_trans.awaddr; + awsize: coverpoint coverage_trans.awsize; + awburst: coverpoint coverage_trans.awburst; + awcache: coverpoint coverage_trans.awcache; + awprot: coverpoint coverage_trans.awprot; + awid: coverpoint coverage_trans.awid; + awlen: coverpoint coverage_trans.awlen; + awlock: coverpoint coverage_trans.awlock; + awqos: coverpoint coverage_trans.awqos; + awregion: coverpoint coverage_trans.awregion; + awuser: coverpoint coverage_trans.awuser; + wvalid: coverpoint coverage_trans.wvalid; + wready: coverpoint coverage_trans.wready; + wlast: coverpoint coverage_trans.wlast; + wdata: coverpoint coverage_trans.wdata; + wstrb: coverpoint coverage_trans.wstrb; + wid: coverpoint coverage_trans.wid; + wuser: coverpoint coverage_trans.wuser; + bwvalid: coverpoint coverage_trans.bwvalid; + bwready: coverpoint coverage_trans.bwready; + bresp: coverpoint coverage_trans.bresp; + bid: coverpoint coverage_trans.bid; + buser: coverpoint coverage_trans.buser; + arvalid: coverpoint coverage_trans.arvalid; + aready: coverpoint coverage_trans.aready; + araddr: coverpoint coverage_trans.araddr; + arsize: coverpoint coverage_trans.arsize; + arburst: coverpoint coverage_trans.arburst; + arcache: coverpoint coverage_trans.arcache; + arprot: coverpoint coverage_trans.arprot; + arid: coverpoint coverage_trans.arid; + arlen: coverpoint coverage_trans.arlen; + arlock: coverpoint coverage_trans.arlock; + arqos: coverpoint coverage_trans.arqos; + aregion: coverpoint coverage_trans.aregion; + aruser: coverpoint coverage_trans.aruser; + rvalid: coverpoint coverage_trans.rvalid; + rready: coverpoint coverage_trans.rready; + rlast: coverpoint coverage_trans.rlast; + rdata: coverpoint coverage_trans.rdata; + rid: coverpoint coverage_trans.rid; + ruser: coverpoint coverage_trans.ruser; + rresp: coverpoint coverage_trans.rresp; + // pragma uvmf custom covergroup end + endgroup + + // **************************************************************************** + // FUNCTION : new() + // This function is the standard SystemVerilog constructor. + // + function new(string name="", uvm_component parent=null); + super.new(name,parent); + axi_m_transaction_cg=new; + `uvm_warning("COVERAGE_MODEL_REVIEW", "A covergroup has been constructed which may need review because of either generation or re-generation with merging. Please note that transaction variables added as a result of re-generation and merging are not automatically added to the covergroup. Remove this warning after the covergroup has been reviewed.") + endfunction + + // **************************************************************************** + // FUNCTION : build_phase() + // This function is the standard UVM build_phase. + // + function void build_phase(uvm_phase phase); + axi_m_transaction_cg.set_inst_name($sformatf("axi_m_transaction_cg_%s",get_full_name())); + endfunction + + // **************************************************************************** + // FUNCTION: write (T t) + // This function is automatically executed when a transaction arrives on the + // analysis_export. It copies values from the variables in the transaction + // to local variables used to collect functional coverage. + // + virtual function void write (T t); + `uvm_info("COV","Received transaction",UVM_HIGH); + coverage_trans = t; + axi_m_transaction_cg.sample(); + endfunction + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + +`endif diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/axi_m_pkg/src/axi_m_typedefs.svh b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/axi_m_pkg/src/axi_m_typedefs.svh new file mode 100644 index 00000000..91e77a1c --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/axi_m_pkg/src/axi_m_typedefs.svh @@ -0,0 +1,21 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: +// This file contains defines and typedefs to be compiled for use in +// the simulation running on the host server when using Veloce. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +`ifndef TYPEDEFS_HVL +`definr TYPEDEFS_HVL + +// pragma uvmf custom additional begin +// pragma uvmf custom additional end +`endif diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/axi_m_pkg/src/axi_m_typedefs_hdl.svh b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/axi_m_pkg/src/axi_m_typedefs_hdl.svh new file mode 100644 index 00000000..bd6b6f41 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/axi_m_pkg/src/axi_m_typedefs_hdl.svh @@ -0,0 +1,23 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: +// This file contains defines and typedefs to be compiled for use in +// the simulation running on the emulator when using Veloce. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// + +`ifndef TYPEDEFS_HVL +`definr TYPEDEFS_HVL + + +// pragma uvmf custom additional begin +// pragma uvmf custom additional end +`endif diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/axi_m_pkg/yaml/axi_m_interface.yaml b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/axi_m_pkg/yaml/axi_m_interface.yaml new file mode 100644 index 00000000..98e0bca3 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/axi_m_pkg/yaml/axi_m_interface.yaml @@ -0,0 +1,481 @@ +uvmf: + interfaces: + axi_m: + clock: axi_clk + config_constraints: [] + config_vars: [] + existing_library_component: 'True' + gen_inbound_streaming_driver: 'False' + hdl_pkg_parameters: [] + hdl_typedefs: [] + hvl_pkg_parameters: [] + hvl_typedefs: [] + parameters: + - name: AW_WIDTH + type: int + value: '32' + - name: LEN + type: int + value: '8' + - name: DATA_WIDTH + type: int + value: '32' + - name: X + type: int + value: '16' + ports: + - dir: output + name: awvalid + reset_value: '''bz' + width: '1' + - dir: input + name: awready + reset_value: '''bz' + width: '1' + - dir: output + name: awaddr + reset_value: '''bz' + width: AW_WIDTH + - dir: output + name: awsize + reset_value: '''bz' + width: '3' + - dir: output + name: awburst + reset_value: '''bz' + width: '2' + - dir: output + name: awcache + reset_value: '''bz' + width: '4' + - dir: output + name: awprot + reset_value: '''bz' + width: '3' + - dir: output + name: awid + reset_value: '''bz' + width: X + - dir: output + name: awlen + reset_value: '''bz' + width: LEN + - dir: output + name: awlock + reset_value: '''bz' + width: '1' + - dir: output + name: awqos + reset_value: '''bz' + width: '4' + - dir: output + name: awregion + reset_value: '''bz' + width: '4' + - dir: output + name: awuser + reset_value: '''bz' + width: X + - dir: output + name: wvalid + reset_value: '''bz' + width: '1' + - dir: input + name: wready + reset_value: '''bz' + width: '1' + - dir: output + name: wlast + reset_value: '''bz' + width: '1' + - dir: output + name: wdata + reset_value: '''bz' + width: DATA_WIDTH + - dir: output + name: wstrb + reset_value: '''bz' + width: DATA_WIDTH/8 + - dir: output + name: wid + reset_value: '''bz' + width: X + - dir: output + name: wuser + reset_value: '''bz' + width: X + - dir: input + name: bwvalid + reset_value: '''bz' + width: '1' + - dir: output + name: bwready + reset_value: '''bz' + width: '1' + - dir: input + name: bresp + reset_value: '''bz' + width: '2' + - dir: input + name: bid + reset_value: '''bz' + width: X + - dir: input + name: buser + reset_value: '''bz' + width: X + - dir: output + name: arvalid + reset_value: '''bz' + width: '1' + - dir: input + name: aready + reset_value: '''bz' + width: '1' + - dir: output + name: araddr + reset_value: '''bz' + width: AW_WIDTH + - dir: output + name: arsize + reset_value: '''bz' + width: '3' + - dir: output + name: arburst + reset_value: '''bz' + width: '2' + - dir: output + name: arcache + reset_value: '''bz' + width: '4' + - dir: output + name: arprot + reset_value: '''bz' + width: '3' + - dir: output + name: arid + reset_value: '''bz' + width: X + - dir: output + name: arlen + reset_value: '''bz' + width: LEN + - dir: output + name: arlock + reset_value: '''bz' + width: '1' + - dir: output + name: arqos + reset_value: '''bz' + width: '4' + - dir: output + name: aregion + reset_value: '''bz' + width: '4' + - dir: output + name: aruser + reset_value: '''bz' + width: X + - dir: input + name: rvalid + reset_value: '''bz' + width: '1' + - dir: output + name: rready + reset_value: '''bz' + width: '1' + - dir: input + name: rlast + reset_value: '''bz' + width: '1' + - dir: input + name: rdata + reset_value: '''bz' + width: DATA_WIDTH + - dir: input + name: rid + reset_value: '''bz' + width: X + - dir: input + name: ruser + reset_value: '''bz' + width: X + - dir: input + name: rresp + reset_value: '''bz' + width: '2' + reset: rst + reset_assertion_level: 'False' + transaction_constraints: [] + transaction_vars: + - comment: '' + iscompare: 'False' + isrand: 'False' + name: awvalid + type: bit + unpacked_dimension: '' + - comment: '' + iscompare: 'False' + isrand: 'False' + name: awready + type: bit + unpacked_dimension: '' + - comment: '' + iscompare: 'False' + isrand: 'True' + name: awaddr + type: bit [AW_WIDTH-1:0] + unpacked_dimension: '' + - comment: '' + iscompare: 'False' + isrand: 'True' + name: awsize + type: bit + unpacked_dimension: '' + - comment: '' + iscompare: 'False' + isrand: 'True' + name: awburst + type: bit + unpacked_dimension: '' + - comment: '' + iscompare: 'False' + isrand: 'True' + name: awcache + type: bit + unpacked_dimension: '' + - comment: '' + iscompare: 'False' + isrand: 'True' + name: awprot + type: bit + unpacked_dimension: '' + - comment: '' + iscompare: 'False' + isrand: 'True' + name: awid + type: bit [X-1:0] + unpacked_dimension: '' + - comment: '' + iscompare: 'False' + isrand: 'True' + name: awlen + type: bit [LEN-1:0] + unpacked_dimension: '' + - comment: '' + iscompare: 'False' + isrand: 'True' + name: awlock + type: bit + unpacked_dimension: '' + - comment: '' + iscompare: 'False' + isrand: 'True' + name: awqos + type: bit + unpacked_dimension: '' + - comment: '' + iscompare: 'False' + isrand: 'True' + name: awregion + type: bit + unpacked_dimension: '' + - comment: '' + iscompare: 'False' + isrand: 'True' + name: awuser + type: bit [X-1:0] + unpacked_dimension: '' + - comment: '' + iscompare: 'False' + isrand: 'False' + name: wvalid + type: bit + unpacked_dimension: '' + - comment: '' + iscompare: 'False' + isrand: 'False' + name: wready + type: bit + unpacked_dimension: '' + - comment: '' + iscompare: 'False' + isrand: 'False' + name: wlast + type: bit + unpacked_dimension: '' + - comment: '' + iscompare: 'False' + isrand: 'True' + name: wdata + type: bit [DATA_WIDTH-1:0] + unpacked_dimension: '' + - comment: '' + iscompare: 'False' + isrand: 'True' + name: wstrb + type: bit [DATA_WIDTH/8-1:0] + unpacked_dimension: '' + - comment: '' + iscompare: 'False' + isrand: 'False' + name: wid + type: bit [X-1:0] + unpacked_dimension: '' + - comment: '' + iscompare: 'False' + isrand: 'True' + name: wuser + type: bit [X-1:0] + unpacked_dimension: '' + - comment: '' + iscompare: 'False' + isrand: 'False' + name: bwvalid + type: bit + unpacked_dimension: '' + - comment: '' + iscompare: 'False' + isrand: 'False' + name: bwready + type: bit + unpacked_dimension: '' + - comment: '' + iscompare: 'False' + isrand: 'True' + name: bresp + type: bit + unpacked_dimension: '' + - comment: '' + iscompare: 'False' + isrand: 'False' + name: bid + type: bit [X-1:0] + unpacked_dimension: '' + - comment: '' + iscompare: 'False' + isrand: 'True' + name: buser + type: bit [X-1:0] + unpacked_dimension: '' + - comment: '' + iscompare: 'False' + isrand: 'False' + name: arvalid + type: bit + unpacked_dimension: '' + - comment: '' + iscompare: 'False' + isrand: 'False' + name: aready + type: bit + unpacked_dimension: '' + - comment: '' + iscompare: 'False' + isrand: 'True' + name: araddr + type: bit [AW_WIDTH-1:0] + unpacked_dimension: '' + - comment: '' + iscompare: 'False' + isrand: 'True' + name: arsize + type: bit + unpacked_dimension: '' + - comment: '' + iscompare: 'False' + isrand: 'True' + name: arburst + type: bit + unpacked_dimension: '' + - comment: '' + iscompare: 'False' + isrand: 'True' + name: arcache + type: bit + unpacked_dimension: '' + - comment: '' + iscompare: 'False' + isrand: 'True' + name: arprot + type: bit + unpacked_dimension: '' + - comment: '' + iscompare: 'False' + isrand: 'True' + name: arid + type: bit [X-1:0] + unpacked_dimension: '' + - comment: '' + iscompare: 'False' + isrand: 'True' + name: arlen + type: bit [LEN-1:0] + unpacked_dimension: '' + - comment: '' + iscompare: 'False' + isrand: 'True' + name: arlock + type: bit + unpacked_dimension: '' + - comment: '' + iscompare: 'False' + isrand: 'True' + name: arqos + type: bit + unpacked_dimension: '' + - comment: '' + iscompare: 'False' + isrand: 'True' + name: aregion + type: bit + unpacked_dimension: '' + - comment: '' + iscompare: 'False' + isrand: 'True' + name: aruser + type: bit [X-1:0] + unpacked_dimension: '' + - comment: '' + iscompare: 'False' + isrand: 'False' + name: rvalid + type: bit + unpacked_dimension: '' + - comment: '' + iscompare: 'False' + isrand: 'False' + name: rready + type: bit + unpacked_dimension: '' + - comment: '' + iscompare: 'False' + isrand: 'False' + name: rlast + type: bit + unpacked_dimension: '' + - comment: '' + iscompare: 'False' + isrand: 'True' + name: rdata + type: bit [DATA_WIDTH-1:0] + unpacked_dimension: '' + - comment: '' + iscompare: 'False' + isrand: 'True' + name: rid + type: bit [X-1:0] + unpacked_dimension: '' + - comment: '' + iscompare: 'False' + isrand: 'True' + name: ruser + type: bit [X-1:0] + unpacked_dimension: '' + - comment: '' + iscompare: 'False' + isrand: 'True' + name: rresp + type: bit + unpacked_dimension: '' + use_dpi_link: 'False' diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/axi_s_pkg/.project b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/axi_s_pkg/.project new file mode 100644 index 00000000..009c04fc --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/axi_s_pkg/.project @@ -0,0 +1,30 @@ + + + axi_s_pkg + + + + + + org.python.pydev.PyDevBuilder + + + + + net.sf.sveditor.core.SVProjectBuilder + + + + + + net.sf.sveditor.core.SVNature + org.python.pydev.pythonNature + + + + UVMF_VIP_LIBRARY_HOME + $%7BPARENT-2-PROJECT_LOC%7D + + + + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/axi_s_pkg/.svproject b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/axi_s_pkg/.svproject new file mode 100644 index 00000000..2f7c662b --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/axi_s_pkg/.svproject @@ -0,0 +1,16 @@ + + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/axi_s_pkg/Makefile b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/axi_s_pkg/Makefile new file mode 100644 index 00000000..63d28f13 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/axi_s_pkg/Makefile @@ -0,0 +1,66 @@ +# axi_s interface packages source +# pragma uvmf custom additional begin +# pragma uvmf custom additional end + +axi_s_PKG = \ + +incdir+$(UVMF_VIP_LIBRARY_HOME)/interface_packages/axi_s_pkg \ + -F $(UVMF_VIP_LIBRARY_HOME)/interface_packages/axi_s_pkg/axi_s_filelist_hvl.f + +axi_s_PKG_HDL = \ + +incdir+$(UVMF_VIP_LIBRARY_HOME)/interface_packages/axi_s_pkg \ + -F $(UVMF_VIP_LIBRARY_HOME)/interface_packages/axi_s_pkg/axi_s_filelist_hdl.f + +axi_s_PKG_XRTL = \ + +incdir+$(UVMF_VIP_LIBRARY_HOME)/interface_packages/axi_s_pkg \ + -F $(UVMF_VIP_LIBRARY_HOME)/interface_packages/axi_s_pkg/axi_s_filelist_xrtl.f + +COMP_axi_s_PKG_TGT_0 = q_comp_axi_s_pkg +COMP_axi_s_PKG_TGT_1 = v_comp_axi_s_pkg +COMP_axi_s_PKG_TGT = $(COMP_axi_s_PKG_TGT_$(USE_VELOCE)) + +comp_axi_s_pkg: $(COMP_axi_s_PKG_TGT) + +q_comp_axi_s_pkg: + $(HDL_COMP_CMD) $(axi_s_PKG_HDL) + $(HVL_COMP_CMD) $(axi_s_PKG) + $(HDL_COMP_CMD) $(axi_s_PKG_XRTL) + +v_comp_axi_s_pkg: + $(HVL_COMP_CMD) $(axi_s_PKG_HDL) + $(HVL_COMP_CMD) $(axi_s_PKG) + $(VELANALYZE_CMD) $(axi_s_PKG_HDL) + $(VELANALYZE_HVL_CMD) $(axi_s_PKG) + $(HDL_COMP_CMD) $(axi_s_PKG_XRTL) + +ifeq ($(MTI_VCO_MODE),64) + GCC_COMP_ARCH = -m64 +else + GCC_COMP_ARCH = -m32 +endif + +export axi_s_IF_DPI_SRC ?= $(UVMF_VIP_LIBRARY_HOME)/interface_packages/axi_s_pkg/dpi + +C_FILE_COMPILE_LIST_axi_s_pkg = \ + +O_FILE_COMPILE_LIST_axi_s_pkg = $(notdir $(C_FILE_COMPILE_LIST_axi_s_pkg:.c=.o)) + +GCC_COMP_ARGS_axi_s_pkg += -I$(axi_s_IF_DPI_SRC) \ + -fPIC + +GCC_COMP_ARGS_axi_s_pkg += $(axi_s_IF_GCC_COMP_ARGUMENTS) + +GCC_LINK_ARGS_axi_s_pkg += \ + \ + -o .so + +comp_axi_s_pkg_c_files: + @echo "--------------------------------" + @echo "Compiling Interface C source" + @echo "--------------------------------" + gcc $(GCC_COMP_ARCH) $(GCC_COMP_ARGS_axi_s_pkg) $(C_FILE_COMPILE_LIST_axi_s_pkg) + @echo "--------------------------------" + @echo "Linking Interface C objects into a shared object" + @echo "--------------------------------" + gcc $(GCC_COMP_ARCH) $(GCC_LINK_ARGS_axi_s_pkg) $(O_FILE_COMPILE_LIST_axi_s_pkg) + @echo "--------------------------------" + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/axi_s_pkg/axi_s.compile b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/axi_s_pkg/axi_s.compile new file mode 100644 index 00000000..96602b5a --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/axi_s_pkg/axi_s.compile @@ -0,0 +1,3 @@ +needs: + - axi_s_hvl.compile + - axi_s_hdl.compile diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/axi_s_pkg/axi_s_bfm.vinfo b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/axi_s_pkg/axi_s_bfm.vinfo new file mode 100644 index 00000000..dc6f9acc --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/axi_s_pkg/axi_s_bfm.vinfo @@ -0,0 +1,6 @@ +@use $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg_hdl.vinfo +@use axi_s_pkg_hdl.vinfo ++incdir+@vinfodir +src/axi_s_if.sv +src/axi_s_driver_bfm.sv +src/axi_s_monitor_bfm.sv diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/axi_s_pkg/axi_s_common.compile b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/axi_s_pkg/axi_s_common.compile new file mode 100644 index 00000000..cb7464be --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/axi_s_pkg/axi_s_common.compile @@ -0,0 +1,7 @@ +needs: + - $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg_hdl.compile +incdir: + - . + - ${uvm_path}/src +src: + - axi_s_pkg_hdl.sv diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/axi_s_pkg/axi_s_filelist_hdl.f b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/axi_s_pkg/axi_s_filelist_hdl.f new file mode 100644 index 00000000..99d98e31 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/axi_s_pkg/axi_s_filelist_hdl.f @@ -0,0 +1 @@ +$UVMF_VIP_LIBRARY_HOME/interface_packages/axi_s_pkg/axi_s_pkg_hdl.sv diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/axi_s_pkg/axi_s_filelist_hvl.f b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/axi_s_pkg/axi_s_filelist_hvl.f new file mode 100644 index 00000000..40ec1992 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/axi_s_pkg/axi_s_filelist_hvl.f @@ -0,0 +1 @@ +$UVMF_VIP_LIBRARY_HOME/interface_packages/axi_s_pkg/axi_s_pkg.sv \ No newline at end of file diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/axi_s_pkg/axi_s_filelist_xrtl.f b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/axi_s_pkg/axi_s_filelist_xrtl.f new file mode 100644 index 00000000..d329ce6c --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/axi_s_pkg/axi_s_filelist_xrtl.f @@ -0,0 +1,3 @@ +$UVMF_VIP_LIBRARY_HOME/interface_packages/axi_s_pkg/src/axi_s_if.sv +$UVMF_VIP_LIBRARY_HOME/interface_packages/axi_s_pkg/src/axi_s_monitor_bfm.sv +$UVMF_VIP_LIBRARY_HOME/interface_packages/axi_s_pkg/src/axi_s_driver_bfm.sv diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/axi_s_pkg/axi_s_hdl.compile b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/axi_s_pkg/axi_s_hdl.compile new file mode 100644 index 00000000..f5769a4f --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/axi_s_pkg/axi_s_hdl.compile @@ -0,0 +1,9 @@ +needs: + - $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg_hdl.compile + - ./axi_s_common.compile +incdir: + - . +src: + - src/axi_s_if.sv + - src/axi_s_monitor_bfm.sv + - src/axi_s_driver_bfm.sv diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/axi_s_pkg/axi_s_hvl.compile b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/axi_s_pkg/axi_s_hvl.compile new file mode 100644 index 00000000..d65e6473 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/axi_s_pkg/axi_s_hvl.compile @@ -0,0 +1,7 @@ +needs: + - $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg.compile + - ./axi_s_common.compile +incdir: + - . +src: + - axi_s_pkg.sv diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/axi_s_pkg/axi_s_pkg.sv b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/axi_s_pkg/axi_s_pkg.sv new file mode 100644 index 00000000..05ee71c7 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/axi_s_pkg/axi_s_pkg.sv @@ -0,0 +1,79 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// PACKAGE: This file defines all of the files contained in the +// interface package that will run on the host simulator. +// +// CONTAINS: +// - +// - +// - + +// - +// - +// - + +// - +// - +// - + +// - +// - +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +`ifndef AXI_S_PKG +`define AXI_S_PKG +package axi_s_pkg; + + import uvm_pkg::*; + import uvmf_base_pkg_hdl::*; + import uvmf_base_pkg::*; + import axi_s_pkg_hdl::*; + + `include "uvm_macros.svh" + + // pragma uvmf custom package_imports_additional begin + // pragma uvmf custom package_imports_additional end + `include "src/axi_s_macros.svh" + + export axi_s_pkg_hdl::*; + + + + // Parameters defined as HVL parameters + + `include "src/axi_s_typedefs.svh" + `include "src/axi_s_transaction.svh" + + `include "src/axi_s_configuration.svh" + `include "src/axi_s_driver.svh" + `include "src/axi_s_monitor.svh" + + `include "src/axi_s_transaction_coverage.svh" + `include "src/axi_s_sequence_base.svh" + `include "src/axi_s_random_sequence.svh" + + `include "src/axi_s_responder_sequence.svh" + `include "src/axi_s2reg_adapter.svh" + + `include "src/axi_s_agent.svh" + + // pragma uvmf custom package_item_additional begin + // UVMF_CHANGE_ME : When adding new interface sequences to the src directory + // be sure to add the sequence file here so that it will be + // compiled as part of the interface package. Be sure to place + // the new sequence after any base sequences of the new sequence. + // pragma uvmf custom package_item_additional end + +endpackage + +// pragma uvmf custom external begin +// pragma uvmf custom external end +`endif diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/axi_s_pkg/axi_s_pkg.vinfo b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/axi_s_pkg/axi_s_pkg.vinfo new file mode 100644 index 00000000..4f79b005 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/axi_s_pkg/axi_s_pkg.vinfo @@ -0,0 +1,4 @@ +@use $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg.vinfo +@use axi_s_pkg_hdl.vinfo ++incdir+@vinfodir +axi_s_pkg.sv diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/axi_s_pkg/axi_s_pkg_hdl.sv b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/axi_s_pkg/axi_s_pkg_hdl.sv new file mode 100644 index 00000000..d8dc7080 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/axi_s_pkg/axi_s_pkg_hdl.sv @@ -0,0 +1,40 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// PACKAGE: This file defines all of the files contained in the +// interface package that needs to be compiled and synthesized +// for running on Veloce. +// +// CONTAINS: +// - +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +`ifndef AXI_S_PKG_HDL +`define AXI_S_PKG_HDL +package axi_s_pkg_hdl; + + import uvmf_base_pkg_hdl::*; + + // pragma uvmf custom package_imports_additional begin + // pragma uvmf custom package_imports_additional end + + // Parameters defined as HDL parameters + + `include "src/axi_s_typedefs_hdl.svh" + `include "src/axi_s_macros.svh" + + // pragma uvmf custom package_item_additional begin + // pragma uvmf custom package_item_additional end + +endpackage + +// pragma uvmf custom external begin +// pragma uvmf custom external end +`endif diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/axi_s_pkg/axi_s_pkg_hdl.vinfo b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/axi_s_pkg/axi_s_pkg_hdl.vinfo new file mode 100644 index 00000000..62905353 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/axi_s_pkg/axi_s_pkg_hdl.vinfo @@ -0,0 +1,2 @@ +@use $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg_hdl.vinfo +axi_s_pkg_hdl.sv diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/axi_s_pkg/axi_s_pkg_sve.F b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/axi_s_pkg/axi_s_pkg_sve.F new file mode 100644 index 00000000..13538815 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/axi_s_pkg/axi_s_pkg_sve.F @@ -0,0 +1,10 @@ +// UVM ++incdir+${UVM_HOME}/src +${UVM_HOME}/src/uvm_pkg.sv + +// Common UVMF files +-f ${UVMF_HOME}/common/common_sve.f + ++incdir+. +-f ${UVMF_VIP_LIBRARY_HOME}/interface_packages/axi_s_pkg/axi_s_filelist_hdl.f +-f ${UVMF_VIP_LIBRARY_HOME}/interface_packages/axi_s_pkg/axi_s_filelist_hvl.f diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/axi_s_pkg/compile.do b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/axi_s_pkg/compile.do new file mode 100644 index 00000000..6a9b5a78 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/axi_s_pkg/compile.do @@ -0,0 +1,14 @@ +# Tcl do file for compile of axi_s interface + +# pragma uvmf custom additional begin +# pragma uvmf custom additional end + + +vlog -sv -timescale 1ps/1ps -suppress 2223,2286 +incdir+$env(UVMF_VIP_LIBRARY_HOME)/interface_packages/axi_s_pkg \ + -F $env(UVMF_VIP_LIBRARY_HOME)/interface_packages/axi_s_pkg/axi_s_filelist_hdl.f + +vlog -sv -timescale 1ps/1ps -suppress 2223,2286 +incdir+$env(UVMF_VIP_LIBRARY_HOME)/interface_packages/axi_s_pkg \ + -F $env(UVMF_VIP_LIBRARY_HOME)/interface_packages/axi_s_pkg/axi_s_filelist_hvl.f + +vlog -sv -timescale 1ps/1ps -suppress 2223,2286 +incdir+$env(UVMF_VIP_LIBRARY_HOME)/interface_packages/axi_s_pkg \ + -F $env(UVMF_VIP_LIBRARY_HOME)/interface_packages/axi_s_pkg/axi_s_filelist_xrtl.f \ No newline at end of file diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/axi_s_pkg/src/axi_s2reg_adapter.svh b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/axi_s_pkg/src/axi_s2reg_adapter.svh new file mode 100644 index 00000000..42e482b1 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/axi_s_pkg/src/axi_s2reg_adapter.svh @@ -0,0 +1,125 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: +// This file contains the UVM register adapter for the axi_s interface. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +`ifndef AXI_S2REG_ADAPTER +`define AXI_S2REG_ADAPTER +class axi_s2reg_adapter #( + int AW_WIDTH = 32, + int LEN = 8, + int DATA_WIDTH = 32, + int X = 16 + ) extends uvm_reg_adapter; + + `uvm_object_param_utils( axi_s2reg_adapter #( + AW_WIDTH, + LEN, + DATA_WIDTH, + X + )) + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + //-------------------------------------------------------------------- + // new + //-------------------------------------------------------------------- + function new (string name = "axi_s2reg_adapter" ); + super.new(name); + // pragma uvmf custom new begin + // UVMF_CHANGE_ME : Configure the adapter regarding byte enables and provides response. + + // Does the protocol the Agent is modeling support byte enables? + // 0 = NO + // 1 = YES + supports_byte_enable = 0; + + // Does the Agent's Driver provide separate response sequence items? + // i.e. Does the driver call seq_item_port.put() + // and do the sequences call get_response()? + // 0 = NO + // 1 = YES + provides_responses = 0; + // pragma uvmf custom new end + + endfunction: new + + //-------------------------------------------------------------------- + // reg2bus + //-------------------------------------------------------------------- + virtual function uvm_sequence_item reg2bus(const ref uvm_reg_bus_op rw); + + axi_s_transaction #( + .AW_WIDTH(AW_WIDTH), + .LEN(LEN), + .DATA_WIDTH(DATA_WIDTH), + .X(X) + ) trans_h = axi_s_transaction #( + .AW_WIDTH(AW_WIDTH), + .LEN(LEN), + .DATA_WIDTH(DATA_WIDTH), + .X(X) + )::type_id::create("trans_h"); + + // pragma uvmf custom reg2bus begin + // UVMF_CHANGE_ME : Fill in the reg2bus adapter mapping registe fields to protocol fields. + + //Adapt the following for your sequence item type + // trans_h.op = (rw.kind == UVM_READ) ? WB_READ : WB_WRITE; + //Copy over address + // trans_h.addr = rw.addr; + //Copy over write data + // trans_h.data = rw.data; + + // pragma uvmf custom reg2bus end + + // Return the adapted transaction + return trans_h; + + endfunction: reg2bus + + //-------------------------------------------------------------------- + // bus2reg + //-------------------------------------------------------------------- + virtual function void bus2reg(uvm_sequence_item bus_item, + ref uvm_reg_bus_op rw); + axi_s_transaction #( + .AW_WIDTH(AW_WIDTH), + .LEN(LEN), + .DATA_WIDTH(DATA_WIDTH), + .X(X) + ) trans_h; + if (!$cast(trans_h, bus_item)) begin + `uvm_fatal("ADAPT","Provided bus_item is not of the correct type") + return; + end + // pragma uvmf custom bus2reg begin + // UVMF_CHANGE_ME : Fill in the bus2reg adapter mapping protocol fields to register fields. + //Adapt the following for your sequence item type + //Copy over instruction type + // rw.kind = (trans_h.op == WB_WRITE) ? UVM_WRITE : UVM_READ; + //Copy over address + // rw.addr = trans_h.addr; + //Copy over read data + // rw.data = trans_h.data; + //Check for errors on the bus and return UVM_NOT_OK if there is an error + // rw.status = UVM_IS_OK; + // pragma uvmf custom bus2reg end + + endfunction: bus2reg + +endclass : axi_s2reg_adapter + +// pragma uvmf custom external begin +// pragma uvmf custom external end +`endif diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/axi_s_pkg/src/axi_s_agent.svh b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/axi_s_pkg/src/axi_s_agent.svh new file mode 100644 index 00000000..09129fe8 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/axi_s_pkg/src/axi_s_agent.svh @@ -0,0 +1,93 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: Protocol specific agent class definition +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// + +`ifndef AXI_S_AGENT +`define AXI_S_AGENT + +class axi_s_agent #( + int AW_WIDTH = 32, + int LEN = 8, + int DATA_WIDTH = 32, + int X = 16 + ) extends uvmf_parameterized_agent #( + .CONFIG_T(axi_s_configuration #( + .AW_WIDTH(AW_WIDTH), + .LEN(LEN), + .DATA_WIDTH(DATA_WIDTH), + .X(X) + )), + .DRIVER_T(axi_s_driver #( + .AW_WIDTH(AW_WIDTH), + .LEN(LEN), + .DATA_WIDTH(DATA_WIDTH), + .X(X) + )), + .MONITOR_T(axi_s_monitor #( + .AW_WIDTH(AW_WIDTH), + .LEN(LEN), + .DATA_WIDTH(DATA_WIDTH), + .X(X) + )), + .COVERAGE_T(axi_s_transaction_coverage #( + .AW_WIDTH(AW_WIDTH), + .LEN(LEN), + .DATA_WIDTH(DATA_WIDTH), + .X(X) + )), + .TRANS_T(axi_s_transaction #( + .AW_WIDTH(AW_WIDTH), + .LEN(LEN), + .DATA_WIDTH(DATA_WIDTH), + .X(X) + )) + ); + + `uvm_component_param_utils( axi_s_agent #( + AW_WIDTH, + LEN, + DATA_WIDTH, + X + )) + +// pragma uvmf custom class_item_additional begin +// pragma uvmf custom class_item_additional end + +// **************************************************************************** +// FUNCTION : new() +// This function is the standard SystemVerilog constructor. +// + function new( string name = "", uvm_component parent = null ); + super.new( name, parent ); + endfunction + +// **************************************************************************** + // FUNCTION: build_phase + virtual function void build_phase(uvm_phase phase); +// pragma uvmf custom build_phase_pre_super begin +// pragma uvmf custom build_phase_pre_super end + super.build_phase(phase); + if (configuration.active_passive == ACTIVE) begin + // Place sequencer handle into configuration object + // so that it may be retrieved from configuration + // rather than using uvm_config_db + configuration.sequencer = this.sequencer; + end + endfunction + +endclass + + +// pragma uvmf custom external begin +// pragma uvmf custom external end +`endif diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/axi_s_pkg/src/axi_s_configuration.svh b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/axi_s_pkg/src/axi_s_configuration.svh new file mode 100644 index 00000000..bd86c617 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/axi_s_pkg/src/axi_s_configuration.svh @@ -0,0 +1,222 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This class contains all variables and functions used +// to configure the axi_s agent and its bfm's. It gets the +// bfm's from the uvm_config_db for use by the agent. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// + +`ifndef AXI_S_CONFIGURATION +`define AXI_S_CONFIGURATION +class axi_s_configuration #( + int AW_WIDTH = 32, + int LEN = 8, + int DATA_WIDTH = 32, + int X = 16 + ) extends uvmf_parameterized_agent_configuration_base #( + .DRIVER_BFM_BIND_T(virtual axi_s_driver_bfm #( + .AW_WIDTH(AW_WIDTH), + .LEN(LEN), + .DATA_WIDTH(DATA_WIDTH), + .X(X) + )), + .MONITOR_BFM_BIND_T( virtual axi_s_monitor_bfm #( + .AW_WIDTH(AW_WIDTH), + .LEN(LEN), + .DATA_WIDTH(DATA_WIDTH), + .X(X) + ))); + + `uvm_object_param_utils( axi_s_configuration #( + AW_WIDTH, + LEN, + DATA_WIDTH, + X + )) + + + // Sequencer handle populated by agent + uvm_sequencer #(axi_s_transaction #( + .AW_WIDTH(AW_WIDTH), + .LEN(LEN), + .DATA_WIDTH(DATA_WIDTH), + .X(X) + ) ) sequencer; + + //Constraints for the configuration variables: + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + covergroup axi_s_configuration_cg; + // pragma uvmf custom covergroup begin + option.auto_bin_max=1024; + // pragma uvmf custom covergroup end + endgroup + + //******************************************************************* + //******************************************************************* + // Structure used to pass configuration variables to monitor and driver BFM's. + // Use to_struct function to pack variables into structure. + // Use from_struct function to unpack variables from structure. + // This structure is defined in axi_s_macros.svh + `axi_s_CONFIGURATION_STRUCT + axi_s_configuration_s axi_s_configuration_struct; + //******************************************************************* + // FUNCTION: to_struct() + // This function packs variables into a axi_s_configuration_s + // structure. The function returns the handle to the axi_s_configuration_struct. + // This function is defined in axi_s_macros.svh + `axi_s_CONFIGURATION_TO_STRUCT_FUNCTION + //******************************************************************* + // FUNCTION: from_struct() + // This function unpacks the struct provided as an argument into + // variables of this class. + // This function is defined in axi_s_macros.svh + `axi_s_CONFIGURATION_FROM_STRUCT_FUNCTION + + // **************************************************************************** + // FUNCTION : new() + // This function is the standard SystemVerilog constructor. + // + function new( string name = "" ); + super.new( name ); + // Construct the covergroup for this configuration class + axi_s_configuration_cg = new; + endfunction + + // **************************************************************************** + // FUNCTION: post_randomize() + // This function is automatically called after the randomize() function + // is executed. + // + function void post_randomize(); + super.post_randomize(); + axi_s_configuration_cg.sample(); + endfunction + + // **************************************************************************** + // FUNCTION: initialize + // This function causes the configuration to retrieve + // its virtual interface handle from the uvm_config_db. + // This function also makes itself available to its + // agent through the uvm_config_db. + // + // ARGUMENTS: + // uvmf_active_passive_t activity: + // This argument identifies the simulation level + // as either BLOCK, CHIP, SIMULATION, etc. + // + // AGENT_PATH: + // This argument identifies the path to this + // configurations agent. This configuration + // makes itself available to the agent specified + // by agent_path by placing itself into the + // uvm_config_db. + // + // INTERFACE_NAME: + // This argument identifies the string name of + // this configurations BFM's. This string + // name is used to retrieve the driver and + // monitor BFM from the uvm_config_db. + // + virtual function void initialize(uvmf_active_passive_t activity, + string agent_path, + string interface_name); + + super.initialize( activity, agent_path, interface_name); + // The covergroup is given the same name as the interface + axi_s_configuration_cg.set_inst_name(interface_name); + + // This configuration places itself into the uvm_config_db for the agent, identified by the agent_path variable, to retrieve. + uvm_config_db #( axi_s_configuration #( + .AW_WIDTH(AW_WIDTH), + .LEN(LEN), + .DATA_WIDTH(DATA_WIDTH), + .X(X) + ) + )::set( null ,agent_path,UVMF_AGENT_CONFIG, this ); + + // This configuration also places itself in the config db using the same identifier used by the interface. This allows users to access + // configuration variables and the interface through the bfm api class rather than directly accessing the BFM. This is useful for + // accessingthe BFM when using Veloce + uvm_config_db #( axi_s_configuration #( + .AW_WIDTH(AW_WIDTH), + .LEN(LEN), + .DATA_WIDTH(DATA_WIDTH), + .X(X) + ) + )::set( null ,UVMF_CONFIGURATIONS, interface_name, this ); + + axi_s_configuration_cg.set_inst_name($sformatf("axi_s_configuration_cg_%s",get_full_name())); + +// This code is to aid in debugging parameter mismatches between the BFM and its corresponding agent. +// Enable this debug by setting UVM_VERBOSITY to UVM_DEBUG +// Setting UVM_VERBOSITY to UVM_DEBUG causes all BFM's and all agents to display their parameter settings. +// All of the messages from this feature have a UVM messaging id value of "CFG" +// The transcript or run.log can be parsed to ensure BFM parameter settings match its corresponding agents parameter settings. + `uvm_info("CFG", + $psprintf("The agent at '%s' is using interface named %s has the following parameters: AW_WIDTH=%x LEN=%x DATA_WIDTH=%x X=%x ", agent_path, interface_name, AW_WIDTH ,LEN ,DATA_WIDTH ,X ), + UVM_DEBUG) + + // pragma uvmf custom initialize begin + // This controls whether or not the agent returns a transaction handle in the driver when calling + // item_done() back into the sequencer or not. If set to 1, a transaction is sent back which means + // the sequence on the other end must use the get_response() part of the driver/sequence API. If + // this doesn't occur, there will eventually be response_queue overflow errors during the test. + return_transaction_response = 1'b0; + + // pragma uvmf custom initialize end + + endfunction + + // **************************************************************************** + // TASK: wait_for_reset + // *[Required]* Blocks until reset is released. The wait_for_reset operation is performed + // by a task in the monitor bfm. + virtual task wait_for_reset(); + monitor_bfm.wait_for_reset(); + endtask + + // **************************************************************************** + // TASK: wait_for_num_clocks + // *[Required]* Blocks until specified number of clocks have elapsed. The wait_for_num_clocks + // operation is performed by a task in the monitor bfm. + virtual task wait_for_num_clocks(int clocks); + monitor_bfm.wait_for_num_clocks(clocks); + endtask + + // **************************************************************************** + // FUNCTION : convert2string() + // This function is used to convert variables in this class into a string for log messaging. + // + virtual function string convert2string (); + // pragma uvmf custom convert2string begin + return $sformatf(""); + // pragma uvmf custom convert2string end + endfunction + + // **************************************************************************** + // FUNCTION: get_sequencer + function uvm_sequencer #(axi_s_transaction#( + .AW_WIDTH(AW_WIDTH), + .LEN(LEN), + .DATA_WIDTH(DATA_WIDTH), + .X(X) + )) get_sequencer(); + return sequencer; + endfunction + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end +`endif diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/axi_s_pkg/src/axi_s_driver.svh b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/axi_s_pkg/src/axi_s_driver.svh new file mode 100644 index 00000000..4a23c8c9 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/axi_s_pkg/src/axi_s_driver.svh @@ -0,0 +1,123 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This class passes transactions between the sequencer +// and the BFM driver interface. It accesses the driver BFM +// through the bfm handle. This driver +// passes transactions to the driver BFM through the access +// task. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +`ifndef AXI_S_DRIVER +`define AXI_S_DRIVER +class axi_s_driver #( + int AW_WIDTH = 32, + int LEN = 8, + int DATA_WIDTH = 32, + int X = 16 + ) extends uvmf_driver_base #( + .CONFIG_T(axi_s_configuration #( + .AW_WIDTH(AW_WIDTH), + .LEN(LEN), + .DATA_WIDTH(DATA_WIDTH), + .X(X) + ) ), + .BFM_BIND_T(virtual axi_s_driver_bfm #( + .AW_WIDTH(AW_WIDTH), + .LEN(LEN), + .DATA_WIDTH(DATA_WIDTH), + .X(X) + ) ), + .REQ(axi_s_transaction #( + .AW_WIDTH(AW_WIDTH), + .LEN(LEN), + .DATA_WIDTH(DATA_WIDTH), + .X(X) + ) ), + .RSP(axi_s_transaction #( + .AW_WIDTH(AW_WIDTH), + .LEN(LEN), + .DATA_WIDTH(DATA_WIDTH), + .X(X) + ) )); + + `uvm_component_param_utils( axi_s_driver #( + AW_WIDTH, + LEN, + DATA_WIDTH, + X + )) +//******************************************************************* +// Macros that define structs located in axi_s_macros.svh +//******************************************************************* +// Initiator macro used by axi_s_driver and axi_s_driver_bfm +// to communicate initiator driven data to axi_s_driver_bfm. +`axi_s_INITIATOR_STRUCT + axi_s_initiator_s axi_s_initiator_struct; +//******************************************************************* +// Responder macro used by axi_s_driver and axi_s_driver_bfm +// to communicate Responder driven data to axi_s_driver_bfm. +`axi_s_RESPONDER_STRUCT + axi_s_responder_s axi_s_responder_struct; + +// pragma uvmf custom class_item_additional begin +// pragma uvmf custom class_item_additional end + +// **************************************************************************** +// This function is the standard SystemVerilog constructor. +// + function new( string name = "", uvm_component parent=null ); + super.new( name, parent ); + endfunction + +// **************************************************************************** +// This function sends configuration object variables to the driver BFM +// using the configuration struct. +// + virtual function void configure(input CONFIG_T cfg); + bfm.configure( cfg.to_struct() ); + endfunction + +// **************************************************************************** +// This function places a handle to this class in the proxy variable in the +// driver BFM. This allows the driver BFM to call tasks and function within this class. +// + virtual function void set_bfm_proxy_handle(); + bfm.proxy = this; endfunction + +// **************************************************************************** +// This task is called by the run_phase in uvmf_driver_base. + virtual task access( inout REQ txn ); +// pragma uvmf custom access begin + if (configuration.initiator_responder==RESPONDER) begin + // Complete current transfer and wait for next transfer + bfm.respond_and_wait_for_next_transfer( + axi_s_initiator_struct, + txn.to_responder_struct() + ); + // Unpack information about initiated transfer received by this responder + txn.from_initiator_struct(axi_s_initiator_struct); + end else begin + // Initiate a transfer and get response + bfm.initiate_and_get_response( + txn.to_initiator_struct(), + axi_s_responder_struct + ); + // Unpack transfer response information received by this initiator + txn.from_responder_struct(axi_s_responder_struct); + end +// pragma uvmf custom access end + endtask + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end +`endif diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/axi_s_pkg/src/axi_s_driver_bfm.sv b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/axi_s_pkg/src/axi_s_driver_bfm.sv new file mode 100644 index 00000000..32c70466 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/axi_s_pkg/src/axi_s_driver_bfm.sv @@ -0,0 +1,765 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: +// This interface performs the axi_s signal driving. It is +// accessed by the uvm axi_s driver through a virtual interface +// handle in the axi_s configuration. It drives the singals passed +// in through the port connection named bus of type axi_s_if. +// +// Input signals from the axi_s_if are assigned to an internal input +// signal with a _i suffix. The _i signal should be used for sampling. +// +// The input signal connections are as follows: +// bus.signal -> signal_i +// +// This bfm drives signals with a _o suffix. These signals +// are driven onto signals within axi_s_if based on INITIATOR/RESPONDER and/or +// ARBITRATION/GRANT status. +// +// The output signal connections are as follows: +// signal_o -> bus.signal +// +// +// Interface functions and tasks used by UVM components: +// +// configure: +// This function gets configuration attributes from the +// UVM driver to set any required BFM configuration +// variables such as 'initiator_responder'. +// +// initiate_and_get_response: +// This task is used to perform signaling activity for initiating +// a protocol transfer. The task initiates the transfer, using +// input data from the initiator struct. Then the task captures +// response data, placing the data into the response struct. +// The response struct is returned to the driver class. +// +// respond_and_wait_for_next_transfer: +// This task is used to complete a current transfer as a responder +// and then wait for the initiator to start the next transfer. +// The task uses data in the responder struct to drive protocol +// signals to complete the transfer. The task then waits for +// the next transfer. Once the next transfer begins, data from +// the initiator is placed into the initiator struct and sent +// to the responder sequence for processing to determine +// what data to respond with. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +import uvmf_base_pkg_hdl::*; +import axi_s_pkg_hdl::*; +`include "src/axi_s_macros.svh" + +interface axi_s_driver_bfm #( + int AW_WIDTH = 32, + int LEN = 8, + int DATA_WIDTH = 32, + int X = 16 + ) + (axi_s_if bus); + // The following pragma and additional ones in-lined further below are for running this BFM on Veloce + // pragma attribute axi_s_driver_bfm partition_interface_xif + +`ifndef XRTL +// This code is to aid in debugging parameter mismatches between the BFM and its corresponding agent. +// Enable this debug by setting UVM_VERBOSITY to UVM_DEBUG +// Setting UVM_VERBOSITY to UVM_DEBUG causes all BFM's and all agents to display their parameter settings. +// All of the messages from this feature have a UVM messaging id value of "CFG" +// The transcript or run.log can be parsed to ensure BFM parameter settings match its corresponding agents parameter settings. +import uvm_pkg::*; +`include "uvm_macros.svh" +initial begin : bfm_vs_agent_parameter_debug + `uvm_info("CFG", + $psprintf("The BFM at '%m' has the following parameters: AW_WIDTH=%x LEN=%x DATA_WIDTH=%x X=%x ", AW_WIDTH,LEN,DATA_WIDTH,X), + UVM_DEBUG) +end +`endif + + // Config value to determine if this is an initiator or a responder + uvmf_initiator_responder_t initiator_responder; + // Custom configuration variables. + // These are set using the configure function which is called during the UVM connect_phase + + logic axi_clk_i; + logic rst_i; + + // Signal list (all signals are capable of being inputs and outputs for the sake + // of supporting both INITIATOR and RESPONDER mode operation. Expectation is that + // directionality in the config file was from the point-of-view of the INITIATOR + + // INITIATOR mode input signals + tri awvalid_i; + reg awvalid_o = 'bz; + tri [AW_WIDTH-1:0] awaddr_i; + reg [AW_WIDTH-1:0] awaddr_o = 'bz; + tri [2:0] awsize_i; + reg [2:0] awsize_o = 'bz; + tri [1:0] awburst_i; + reg [1:0] awburst_o = 'bz; + tri [3:0] awcache_i; + reg [3:0] awcache_o = 'bz; + tri [2:0] awprot_i; + reg [2:0] awprot_o = 'bz; + tri [X-1:0] awid_i; + reg [X-1:0] awid_o = 'bz; + tri [LEN-1:0] awlen_i; + reg [LEN-1:0] awlen_o = 'bz; + tri awlock_i; + reg awlock_o = 'bz; + tri [3:0] awqos_i; + reg [3:0] awqos_o = 'bz; + tri [3:0] awregion_i; + reg [3:0] awregion_o = 'bz; + tri [X-1:0] awuser_i; + reg [X-1:0] awuser_o = 'bz; + tri wvalid_i; + reg wvalid_o = 'bz; + tri wlast_i; + reg wlast_o = 'bz; + tri [DATA_WIDTH-1:0] wdata_i; + reg [DATA_WIDTH-1:0] wdata_o = 'bz; + tri [DATA_WIDTH/8-1:0] wstrb_i; + reg [DATA_WIDTH/8-1:0] wstrb_o = 'bz; + tri [X-1:0] wid_i; + reg [X-1:0] wid_o = 'bz; + tri [X-1:0] wuser_i; + reg [X-1:0] wuser_o = 'bz; + tri [1:0] bresp_i; + reg [1:0] bresp_o = 'bz; + tri arvalid_i; + reg arvalid_o = 'bz; + tri [AW_WIDTH-1:0] araddr_i; + reg [AW_WIDTH-1:0] araddr_o = 'bz; + tri [2:0] arsize_i; + reg [2:0] arsize_o = 'bz; + tri [1:0] arburst_i; + reg [1:0] arburst_o = 'bz; + tri [3:0] arcache_i; + reg [3:0] arcache_o = 'bz; + tri [2:0] arprot_i; + reg [2:0] arprot_o = 'bz; + tri [X-1:0] arid_i; + reg [X-1:0] arid_o = 'bz; + tri [LEN-1:0] arlen_i; + reg [LEN-1:0] arlen_o = 'bz; + tri arlock_i; + reg arlock_o = 'bz; + tri [3:0] arqos_i; + reg [3:0] arqos_o = 'bz; + tri [3:0] aregion_i; + reg [3:0] aregion_o = 'bz; + tri [X-1:0] aruser_i; + reg [X-1:0] aruser_o = 'bz; + tri rready_i; + reg rready_o = 'bz; + + // INITIATOR mode output signals + tri awready_i; + reg awready_o = 'bz; + tri wready_i; + reg wready_o = 'bz; + tri bwvalid_i; + reg bwvalid_o = 'bz; + tri bwready_i; + reg bwready_o = 'bz; + tri [X-1:0] bid_i; + reg [X-1:0] bid_o = 'bz; + tri [X-1:0] buser_i; + reg [X-1:0] buser_o = 'bz; + tri aready_i; + reg aready_o = 'bz; + tri rvalid_i; + reg rvalid_o = 'bz; + tri rlast_i; + reg rlast_o = 'bz; + tri [DATA_WIDTH-1:0] rdata_i; + reg [DATA_WIDTH-1:0] rdata_o = 'bz; + tri [X-1:0] rid_i; + reg [X-1:0] rid_o = 'bz; + tri [X-1:0] ruser_i; + reg [X-1:0] ruser_o = 'bz; + tri [1:0] rresp_i; + reg [1:0] rresp_o = 'bz; + + // Bi-directional signals + + + assign axi_clk_i = bus.axi_clk; + assign rst_i = bus.rst; + + // These are signals marked as 'input' by the config file, but the signals will be + // driven by this BFM if put into RESPONDER mode (flipping all signal directions around) + assign awvalid_i = bus.awvalid; + assign bus.awvalid = (initiator_responder == RESPONDER) ? awvalid_o : 'bz; + assign awaddr_i = bus.awaddr; + assign bus.awaddr = (initiator_responder == RESPONDER) ? awaddr_o : 'bz; + assign awsize_i = bus.awsize; + assign bus.awsize = (initiator_responder == RESPONDER) ? awsize_o : 'bz; + assign awburst_i = bus.awburst; + assign bus.awburst = (initiator_responder == RESPONDER) ? awburst_o : 'bz; + assign awcache_i = bus.awcache; + assign bus.awcache = (initiator_responder == RESPONDER) ? awcache_o : 'bz; + assign awprot_i = bus.awprot; + assign bus.awprot = (initiator_responder == RESPONDER) ? awprot_o : 'bz; + assign awid_i = bus.awid; + assign bus.awid = (initiator_responder == RESPONDER) ? awid_o : 'bz; + assign awlen_i = bus.awlen; + assign bus.awlen = (initiator_responder == RESPONDER) ? awlen_o : 'bz; + assign awlock_i = bus.awlock; + assign bus.awlock = (initiator_responder == RESPONDER) ? awlock_o : 'bz; + assign awqos_i = bus.awqos; + assign bus.awqos = (initiator_responder == RESPONDER) ? awqos_o : 'bz; + assign awregion_i = bus.awregion; + assign bus.awregion = (initiator_responder == RESPONDER) ? awregion_o : 'bz; + assign awuser_i = bus.awuser; + assign bus.awuser = (initiator_responder == RESPONDER) ? awuser_o : 'bz; + assign wvalid_i = bus.wvalid; + assign bus.wvalid = (initiator_responder == RESPONDER) ? wvalid_o : 'bz; + assign wlast_i = bus.wlast; + assign bus.wlast = (initiator_responder == RESPONDER) ? wlast_o : 'bz; + assign wdata_i = bus.wdata; + assign bus.wdata = (initiator_responder == RESPONDER) ? wdata_o : 'bz; + assign wstrb_i = bus.wstrb; + assign bus.wstrb = (initiator_responder == RESPONDER) ? wstrb_o : 'bz; + assign wid_i = bus.wid; + assign bus.wid = (initiator_responder == RESPONDER) ? wid_o : 'bz; + assign wuser_i = bus.wuser; + assign bus.wuser = (initiator_responder == RESPONDER) ? wuser_o : 'bz; + assign bresp_i = bus.bresp; + assign bus.bresp = (initiator_responder == RESPONDER) ? bresp_o : 'bz; + assign arvalid_i = bus.arvalid; + assign bus.arvalid = (initiator_responder == RESPONDER) ? arvalid_o : 'bz; + assign araddr_i = bus.araddr; + assign bus.araddr = (initiator_responder == RESPONDER) ? araddr_o : 'bz; + assign arsize_i = bus.arsize; + assign bus.arsize = (initiator_responder == RESPONDER) ? arsize_o : 'bz; + assign arburst_i = bus.arburst; + assign bus.arburst = (initiator_responder == RESPONDER) ? arburst_o : 'bz; + assign arcache_i = bus.arcache; + assign bus.arcache = (initiator_responder == RESPONDER) ? arcache_o : 'bz; + assign arprot_i = bus.arprot; + assign bus.arprot = (initiator_responder == RESPONDER) ? arprot_o : 'bz; + assign arid_i = bus.arid; + assign bus.arid = (initiator_responder == RESPONDER) ? arid_o : 'bz; + assign arlen_i = bus.arlen; + assign bus.arlen = (initiator_responder == RESPONDER) ? arlen_o : 'bz; + assign arlock_i = bus.arlock; + assign bus.arlock = (initiator_responder == RESPONDER) ? arlock_o : 'bz; + assign arqos_i = bus.arqos; + assign bus.arqos = (initiator_responder == RESPONDER) ? arqos_o : 'bz; + assign aregion_i = bus.aregion; + assign bus.aregion = (initiator_responder == RESPONDER) ? aregion_o : 'bz; + assign aruser_i = bus.aruser; + assign bus.aruser = (initiator_responder == RESPONDER) ? aruser_o : 'bz; + assign rready_i = bus.rready; + assign bus.rready = (initiator_responder == RESPONDER) ? rready_o : 'bz; + + + // These are signals marked as 'output' by the config file, but the outputs will + // not be driven by this BFM unless placed in INITIATOR mode. + assign bus.awready = (initiator_responder == INITIATOR) ? awready_o : 'bz; + assign awready_i = bus.awready; + assign bus.wready = (initiator_responder == INITIATOR) ? wready_o : 'bz; + assign wready_i = bus.wready; + assign bus.bwvalid = (initiator_responder == INITIATOR) ? bwvalid_o : 'bz; + assign bwvalid_i = bus.bwvalid; + assign bus.bwready = (initiator_responder == INITIATOR) ? bwready_o : 'bz; + assign bwready_i = bus.bwready; + assign bus.bid = (initiator_responder == INITIATOR) ? bid_o : 'bz; + assign bid_i = bus.bid; + assign bus.buser = (initiator_responder == INITIATOR) ? buser_o : 'bz; + assign buser_i = bus.buser; + assign bus.aready = (initiator_responder == INITIATOR) ? aready_o : 'bz; + assign aready_i = bus.aready; + assign bus.rvalid = (initiator_responder == INITIATOR) ? rvalid_o : 'bz; + assign rvalid_i = bus.rvalid; + assign bus.rlast = (initiator_responder == INITIATOR) ? rlast_o : 'bz; + assign rlast_i = bus.rlast; + assign bus.rdata = (initiator_responder == INITIATOR) ? rdata_o : 'bz; + assign rdata_i = bus.rdata; + assign bus.rid = (initiator_responder == INITIATOR) ? rid_o : 'bz; + assign rid_i = bus.rid; + assign bus.ruser = (initiator_responder == INITIATOR) ? ruser_o : 'bz; + assign ruser_i = bus.ruser; + assign bus.rresp = (initiator_responder == INITIATOR) ? rresp_o : 'bz; + assign rresp_i = bus.rresp; + + // Proxy handle to UVM driver + axi_s_pkg::axi_s_driver #( + .AW_WIDTH(AW_WIDTH), + .LEN(LEN), + .DATA_WIDTH(DATA_WIDTH), + .X(X) + ) proxy; + // pragma tbx oneway proxy.my_function_name_in_uvm_driver + + // **************************************************************************** + // **************************************************************************** + // Macros that define structs located in axi_s_macros.svh + // **************************************************************************** + // Struct for passing configuration data from axi_s_driver to this BFM + // **************************************************************************** + `axi_s_CONFIGURATION_STRUCT + // **************************************************************************** + // Structs for INITIATOR and RESPONDER data flow + //******************************************************************* + // Initiator macro used by axi_s_driver and axi_s_driver_bfm + // to communicate initiator driven data to axi_s_driver_bfm. + `axi_s_INITIATOR_STRUCT + axi_s_initiator_s initiator_struct; + // Responder macro used by axi_s_driver and axi_s_driver_bfm + // to communicate Responder driven data to axi_s_driver_bfm. + `axi_s_RESPONDER_STRUCT + axi_s_responder_s responder_struct; + + // **************************************************************************** +// pragma uvmf custom reset_condition_and_response begin + // Always block used to return signals to reset value upon assertion of reset + always @( negedge rst_i ) + begin + // RESPONDER mode output signals + awvalid_o <= 'bz; + awaddr_o <= 'bz; + awsize_o <= 'bz; + awburst_o <= 'bz; + awcache_o <= 'bz; + awprot_o <= 'bz; + awid_o <= 'bz; + awlen_o <= 'bz; + awlock_o <= 'bz; + awqos_o <= 'bz; + awregion_o <= 'bz; + awuser_o <= 'bz; + wvalid_o <= 'bz; + wlast_o <= 'bz; + wdata_o <= 'bz; + wstrb_o <= 'bz; + wid_o <= 'bz; + wuser_o <= 'bz; + bresp_o <= 'bz; + arvalid_o <= 'bz; + araddr_o <= 'bz; + arsize_o <= 'bz; + arburst_o <= 'bz; + arcache_o <= 'bz; + arprot_o <= 'bz; + arid_o <= 'bz; + arlen_o <= 'bz; + arlock_o <= 'bz; + arqos_o <= 'bz; + aregion_o <= 'bz; + aruser_o <= 'bz; + rready_o <= 'bz; + // INITIATOR mode output signals + awready_o <= 'bz; + wready_o <= 'bz; + bwvalid_o <= 'bz; + bwready_o <= 'bz; + bid_o <= 'bz; + buser_o <= 'bz; + aready_o <= 'bz; + rvalid_o <= 'bz; + rlast_o <= 'bz; + rdata_o <= 'bz; + rid_o <= 'bz; + ruser_o <= 'bz; + rresp_o <= 'bz; + // Bi-directional signals + + end +// pragma uvmf custom reset_condition_and_response end + + // pragma uvmf custom interface_item_additional begin + // pragma uvmf custom interface_item_additional end + + //****************************************************************** + // The configure() function is used to pass agent configuration + // variables to the driver BFM. It is called by the driver within + // the agent at the beginning of the simulation. It may be called + // during the simulation if agent configuration variables are updated + // and the driver BFM needs to be aware of the new configuration + // variables. + // + + function void configure(axi_s_configuration_s axi_s_configuration_arg); // pragma tbx xtf + initiator_responder = axi_s_configuration_arg.initiator_responder; + // pragma uvmf custom configure begin + // pragma uvmf custom configure end + endfunction + +// pragma uvmf custom initiate_and_get_response begin +// **************************************************************************** +// UVMF_CHANGE_ME +// This task is used by an initator. The task first initiates a transfer then +// waits for the responder to complete the transfer. + task initiate_and_get_response( + // This argument passes transaction variables used by an initiator + // to perform the initial part of a protocol transfer. The values + // come from a sequence item created in a sequence. + input axi_s_initiator_s axi_s_initiator_struct, + // This argument is used to send data received from the responder + // back to the sequence item. The sequence item is returned to the sequence. + output axi_s_responder_s axi_s_responder_struct + );// pragma tbx xtf + // + // Members within the axi_s_initiator_struct: + // bit awvalid ; + // bit awready ; + // bit [AW_WIDTH-1:0] awaddr ; + // bit awsize ; + // bit awburst ; + // bit awcache ; + // bit awprot ; + // bit [X-1:0] awid ; + // bit [LEN-1:0] awlen ; + // bit awlock ; + // bit awqos ; + // bit awregion ; + // bit [X-1:0] awuser ; + // bit wvalid ; + // bit wready ; + // bit wlast ; + // bit [DATA_WIDTH-1:0] wdata ; + // bit [DATA_WIDTH/8-1:0] wstrb ; + // bit [X-1:0] wid ; + // bit [X-1:0] wuser ; + // bit bwvalid ; + // bit bwready ; + // bit bresp ; + // bit [X-1:0] bid ; + // bit [X-1:0] buser ; + // bit arvalid ; + // bit aready ; + // bit [AW_WIDTH-1:0] araddr ; + // bit arsize ; + // bit arburst ; + // bit arcache ; + // bit arprot ; + // bit [X-1:0] arid ; + // bit [LEN-1:0] arlen ; + // bit arlock ; + // bit arqos ; + // bit aregion ; + // bit [X-1:0] aruser ; + // bit rvalid ; + // bit rready ; + // bit rlast ; + // bit [DATA_WIDTH-1:0] rdata ; + // bit [X-1:0] rid ; + // bit [X-1:0] ruser ; + // bit rresp ; + // Members within the axi_s_responder_struct: + // bit awvalid ; + // bit awready ; + // bit [AW_WIDTH-1:0] awaddr ; + // bit awsize ; + // bit awburst ; + // bit awcache ; + // bit awprot ; + // bit [X-1:0] awid ; + // bit [LEN-1:0] awlen ; + // bit awlock ; + // bit awqos ; + // bit awregion ; + // bit [X-1:0] awuser ; + // bit wvalid ; + // bit wready ; + // bit wlast ; + // bit [DATA_WIDTH-1:0] wdata ; + // bit [DATA_WIDTH/8-1:0] wstrb ; + // bit [X-1:0] wid ; + // bit [X-1:0] wuser ; + // bit bwvalid ; + // bit bwready ; + // bit bresp ; + // bit [X-1:0] bid ; + // bit [X-1:0] buser ; + // bit arvalid ; + // bit aready ; + // bit [AW_WIDTH-1:0] araddr ; + // bit arsize ; + // bit arburst ; + // bit arcache ; + // bit arprot ; + // bit [X-1:0] arid ; + // bit [LEN-1:0] arlen ; + // bit arlock ; + // bit arqos ; + // bit aregion ; + // bit [X-1:0] aruser ; + // bit rvalid ; + // bit rready ; + // bit rlast ; + // bit [DATA_WIDTH-1:0] rdata ; + // bit [X-1:0] rid ; + // bit [X-1:0] ruser ; + // bit rresp ; + initiator_struct = axi_s_initiator_struct; + // + // Reference code; + // How to wait for signal value + // while (control_signal == 1'b1) @(posedge axi_clk_i); + // + // How to assign a responder struct member, named xyz, from a signal. + // All available initiator input and inout signals listed. + // Initiator input signals + // axi_s_responder_struct.xyz = awvalid_i; // + // axi_s_responder_struct.xyz = awaddr_i; // [AW_WIDTH-1:0] + // axi_s_responder_struct.xyz = awsize_i; // [2:0] + // axi_s_responder_struct.xyz = awburst_i; // [1:0] + // axi_s_responder_struct.xyz = awcache_i; // [3:0] + // axi_s_responder_struct.xyz = awprot_i; // [2:0] + // axi_s_responder_struct.xyz = awid_i; // [X-1:0] + // axi_s_responder_struct.xyz = awlen_i; // [LEN-1:0] + // axi_s_responder_struct.xyz = awlock_i; // + // axi_s_responder_struct.xyz = awqos_i; // [3:0] + // axi_s_responder_struct.xyz = awregion_i; // [3:0] + // axi_s_responder_struct.xyz = awuser_i; // [X-1:0] + // axi_s_responder_struct.xyz = wvalid_i; // + // axi_s_responder_struct.xyz = wlast_i; // + // axi_s_responder_struct.xyz = wdata_i; // [DATA_WIDTH-1:0] + // axi_s_responder_struct.xyz = wstrb_i; // [DATA_WIDTH/8-1:0] + // axi_s_responder_struct.xyz = wid_i; // [X-1:0] + // axi_s_responder_struct.xyz = wuser_i; // [X-1:0] + // axi_s_responder_struct.xyz = bresp_i; // [1:0] + // axi_s_responder_struct.xyz = arvalid_i; // + // axi_s_responder_struct.xyz = araddr_i; // [AW_WIDTH-1:0] + // axi_s_responder_struct.xyz = arsize_i; // [2:0] + // axi_s_responder_struct.xyz = arburst_i; // [1:0] + // axi_s_responder_struct.xyz = arcache_i; // [3:0] + // axi_s_responder_struct.xyz = arprot_i; // [2:0] + // axi_s_responder_struct.xyz = arid_i; // [X-1:0] + // axi_s_responder_struct.xyz = arlen_i; // [LEN-1:0] + // axi_s_responder_struct.xyz = arlock_i; // + // axi_s_responder_struct.xyz = arqos_i; // [3:0] + // axi_s_responder_struct.xyz = aregion_i; // [3:0] + // axi_s_responder_struct.xyz = aruser_i; // [X-1:0] + // axi_s_responder_struct.xyz = rready_i; // + // Initiator inout signals + // How to assign a signal from an initiator struct member named xyz. + // All available initiator output and inout signals listed. + // Notice the _o. Those are storage variables that allow for procedural assignment. + // Initiator output signals + // awready_o <= axi_s_initiator_struct.xyz; // + // wready_o <= axi_s_initiator_struct.xyz; // + // bwvalid_o <= axi_s_initiator_struct.xyz; // + // bwready_o <= axi_s_initiator_struct.xyz; // + // bid_o <= axi_s_initiator_struct.xyz; // [X-1:0] + // buser_o <= axi_s_initiator_struct.xyz; // [X-1:0] + // aready_o <= axi_s_initiator_struct.xyz; // + // rvalid_o <= axi_s_initiator_struct.xyz; // + // rlast_o <= axi_s_initiator_struct.xyz; // + // rdata_o <= axi_s_initiator_struct.xyz; // [DATA_WIDTH-1:0] + // rid_o <= axi_s_initiator_struct.xyz; // [X-1:0] + // ruser_o <= axi_s_initiator_struct.xyz; // [X-1:0] + // rresp_o <= axi_s_initiator_struct.xyz; // [1:0] + // Initiator inout signals + // Initiate a transfer using the data received. + @(posedge axi_clk_i); + @(posedge axi_clk_i); + // Wait for the responder to complete the transfer then place the responder data into + // axi_s_responder_struct. + @(posedge axi_clk_i); + @(posedge axi_clk_i); + responder_struct = axi_s_responder_struct; + endtask +// pragma uvmf custom initiate_and_get_response end + +// pragma uvmf custom respond_and_wait_for_next_transfer begin +// **************************************************************************** +// The first_transfer variable is used to prevent completing a transfer in the +// first call to this task. For the first call to this task, there is not +// current transfer to complete. +bit first_transfer=1; + +// UVMF_CHANGE_ME +// This task is used by a responder. The task first completes the current +// transfer in progress then waits for the initiator to start the next transfer. + task respond_and_wait_for_next_transfer( + // This argument is used to send data received from the initiator + // back to the sequence item. The sequence determines how to respond. + output axi_s_initiator_s axi_s_initiator_struct, + // This argument passes transaction variables used by a responder + // to complete a protocol transfer. The values come from a sequence item. + input axi_s_responder_s axi_s_responder_struct + );// pragma tbx xtf + // Variables within the axi_s_initiator_struct: + // bit awvalid ; + // bit awready ; + // bit [AW_WIDTH-1:0] awaddr ; + // bit awsize ; + // bit awburst ; + // bit awcache ; + // bit awprot ; + // bit [X-1:0] awid ; + // bit [LEN-1:0] awlen ; + // bit awlock ; + // bit awqos ; + // bit awregion ; + // bit [X-1:0] awuser ; + // bit wvalid ; + // bit wready ; + // bit wlast ; + // bit [DATA_WIDTH-1:0] wdata ; + // bit [DATA_WIDTH/8-1:0] wstrb ; + // bit [X-1:0] wid ; + // bit [X-1:0] wuser ; + // bit bwvalid ; + // bit bwready ; + // bit bresp ; + // bit [X-1:0] bid ; + // bit [X-1:0] buser ; + // bit arvalid ; + // bit aready ; + // bit [AW_WIDTH-1:0] araddr ; + // bit arsize ; + // bit arburst ; + // bit arcache ; + // bit arprot ; + // bit [X-1:0] arid ; + // bit [LEN-1:0] arlen ; + // bit arlock ; + // bit arqos ; + // bit aregion ; + // bit [X-1:0] aruser ; + // bit rvalid ; + // bit rready ; + // bit rlast ; + // bit [DATA_WIDTH-1:0] rdata ; + // bit [X-1:0] rid ; + // bit [X-1:0] ruser ; + // bit rresp ; + // Variables within the axi_s_responder_struct: + // bit awvalid ; + // bit awready ; + // bit [AW_WIDTH-1:0] awaddr ; + // bit awsize ; + // bit awburst ; + // bit awcache ; + // bit awprot ; + // bit [X-1:0] awid ; + // bit [LEN-1:0] awlen ; + // bit awlock ; + // bit awqos ; + // bit awregion ; + // bit [X-1:0] awuser ; + // bit wvalid ; + // bit wready ; + // bit wlast ; + // bit [DATA_WIDTH-1:0] wdata ; + // bit [DATA_WIDTH/8-1:0] wstrb ; + // bit [X-1:0] wid ; + // bit [X-1:0] wuser ; + // bit bwvalid ; + // bit bwready ; + // bit bresp ; + // bit [X-1:0] bid ; + // bit [X-1:0] buser ; + // bit arvalid ; + // bit aready ; + // bit [AW_WIDTH-1:0] araddr ; + // bit arsize ; + // bit arburst ; + // bit arcache ; + // bit arprot ; + // bit [X-1:0] arid ; + // bit [LEN-1:0] arlen ; + // bit arlock ; + // bit arqos ; + // bit aregion ; + // bit [X-1:0] aruser ; + // bit rvalid ; + // bit rready ; + // bit rlast ; + // bit [DATA_WIDTH-1:0] rdata ; + // bit [X-1:0] rid ; + // bit [X-1:0] ruser ; + // bit rresp ; + // Reference code; + // How to wait for signal value + // while (control_signal == 1'b1) @(posedge axi_clk_i); + // + // How to assign a responder struct member, named xyz, from a signal. + // All available responder input and inout signals listed. + // Responder input signals + // axi_s_responder_struct.xyz = awready_i; // + // axi_s_responder_struct.xyz = wready_i; // + // axi_s_responder_struct.xyz = bwvalid_i; // + // axi_s_responder_struct.xyz = bwready_i; // + // axi_s_responder_struct.xyz = bid_i; // [X-1:0] + // axi_s_responder_struct.xyz = buser_i; // [X-1:0] + // axi_s_responder_struct.xyz = aready_i; // + // axi_s_responder_struct.xyz = rvalid_i; // + // axi_s_responder_struct.xyz = rlast_i; // + // axi_s_responder_struct.xyz = rdata_i; // [DATA_WIDTH-1:0] + // axi_s_responder_struct.xyz = rid_i; // [X-1:0] + // axi_s_responder_struct.xyz = ruser_i; // [X-1:0] + // axi_s_responder_struct.xyz = rresp_i; // [1:0] + // Responder inout signals + // How to assign a signal, named xyz, from an initiator struct member. + // All available responder output and inout signals listed. + // Notice the _o. Those are storage variables that allow for procedural assignment. + // Responder output signals + // awvalid_o <= axi_s_initiator_struct.xyz; // + // awaddr_o <= axi_s_initiator_struct.xyz; // [AW_WIDTH-1:0] + // awsize_o <= axi_s_initiator_struct.xyz; // [2:0] + // awburst_o <= axi_s_initiator_struct.xyz; // [1:0] + // awcache_o <= axi_s_initiator_struct.xyz; // [3:0] + // awprot_o <= axi_s_initiator_struct.xyz; // [2:0] + // awid_o <= axi_s_initiator_struct.xyz; // [X-1:0] + // awlen_o <= axi_s_initiator_struct.xyz; // [LEN-1:0] + // awlock_o <= axi_s_initiator_struct.xyz; // + // awqos_o <= axi_s_initiator_struct.xyz; // [3:0] + // awregion_o <= axi_s_initiator_struct.xyz; // [3:0] + // awuser_o <= axi_s_initiator_struct.xyz; // [X-1:0] + // wvalid_o <= axi_s_initiator_struct.xyz; // + // wlast_o <= axi_s_initiator_struct.xyz; // + // wdata_o <= axi_s_initiator_struct.xyz; // [DATA_WIDTH-1:0] + // wstrb_o <= axi_s_initiator_struct.xyz; // [DATA_WIDTH/8-1:0] + // wid_o <= axi_s_initiator_struct.xyz; // [X-1:0] + // wuser_o <= axi_s_initiator_struct.xyz; // [X-1:0] + // bresp_o <= axi_s_initiator_struct.xyz; // [1:0] + // arvalid_o <= axi_s_initiator_struct.xyz; // + // araddr_o <= axi_s_initiator_struct.xyz; // [AW_WIDTH-1:0] + // arsize_o <= axi_s_initiator_struct.xyz; // [2:0] + // arburst_o <= axi_s_initiator_struct.xyz; // [1:0] + // arcache_o <= axi_s_initiator_struct.xyz; // [3:0] + // arprot_o <= axi_s_initiator_struct.xyz; // [2:0] + // arid_o <= axi_s_initiator_struct.xyz; // [X-1:0] + // arlen_o <= axi_s_initiator_struct.xyz; // [LEN-1:0] + // arlock_o <= axi_s_initiator_struct.xyz; // + // arqos_o <= axi_s_initiator_struct.xyz; // [3:0] + // aregion_o <= axi_s_initiator_struct.xyz; // [3:0] + // aruser_o <= axi_s_initiator_struct.xyz; // [X-1:0] + // rready_o <= axi_s_initiator_struct.xyz; // + // Responder inout signals + + @(posedge axi_clk_i); + if (!first_transfer) begin + // Perform transfer response here. + // Reply using data recieved in the axi_s_responder_struct. + @(posedge axi_clk_i); + // Reply using data recieved in the transaction handle. + @(posedge axi_clk_i); + end + // Wait for next transfer then gather info from intiator about the transfer. + // Place the data into the axi_s_initiator_struct. + @(posedge axi_clk_i); + @(posedge axi_clk_i); + first_transfer = 0; + endtask +// pragma uvmf custom respond_and_wait_for_next_transfer end + + +endinterface + +// pragma uvmf custom external begin +// pragma uvmf custom external end +`endif diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/axi_s_pkg/src/axi_s_if.sv b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/axi_s_pkg/src/axi_s_if.sv new file mode 100644 index 00000000..9388f168 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/axi_s_pkg/src/axi_s_if.sv @@ -0,0 +1,291 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This interface contains the axi_s interface signals. +// It is instantiated once per axi_s bus. Bus Functional Models, +// BFM's named axi_s_driver_bfm, are used to drive signals on the bus. +// BFM's named axi_s_monitor_bfm are used to monitor signals on the +// bus. This interface signal bundle is passed in the port list of +// the BFM in order to give the BFM access to the signals in this +// interface. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +`ifndef AXI_S_IF +`define AXI_S_IF +// This template can be used to connect a DUT to these signals +// +// .dut_signal_port(axi_s_bus.awvalid), // Agent input +// .dut_signal_port(axi_s_bus.awready), // Agent output +// .dut_signal_port(axi_s_bus.awaddr), // Agent input +// .dut_signal_port(axi_s_bus.awsize), // Agent input +// .dut_signal_port(axi_s_bus.awburst), // Agent input +// .dut_signal_port(axi_s_bus.awcache), // Agent input +// .dut_signal_port(axi_s_bus.awprot), // Agent input +// .dut_signal_port(axi_s_bus.awid), // Agent input +// .dut_signal_port(axi_s_bus.awlen), // Agent input +// .dut_signal_port(axi_s_bus.awlock), // Agent input +// .dut_signal_port(axi_s_bus.awqos), // Agent input +// .dut_signal_port(axi_s_bus.awregion), // Agent input +// .dut_signal_port(axi_s_bus.awuser), // Agent input +// .dut_signal_port(axi_s_bus.wvalid), // Agent input +// .dut_signal_port(axi_s_bus.wready), // Agent output +// .dut_signal_port(axi_s_bus.wlast), // Agent input +// .dut_signal_port(axi_s_bus.wdata), // Agent input +// .dut_signal_port(axi_s_bus.wstrb), // Agent input +// .dut_signal_port(axi_s_bus.wid), // Agent input +// .dut_signal_port(axi_s_bus.wuser), // Agent input +// .dut_signal_port(axi_s_bus.bwvalid), // Agent output +// .dut_signal_port(axi_s_bus.bwready), // Agent output +// .dut_signal_port(axi_s_bus.bresp), // Agent input +// .dut_signal_port(axi_s_bus.bid), // Agent output +// .dut_signal_port(axi_s_bus.buser), // Agent output +// .dut_signal_port(axi_s_bus.arvalid), // Agent input +// .dut_signal_port(axi_s_bus.aready), // Agent output +// .dut_signal_port(axi_s_bus.araddr), // Agent input +// .dut_signal_port(axi_s_bus.arsize), // Agent input +// .dut_signal_port(axi_s_bus.arburst), // Agent input +// .dut_signal_port(axi_s_bus.arcache), // Agent input +// .dut_signal_port(axi_s_bus.arprot), // Agent input +// .dut_signal_port(axi_s_bus.arid), // Agent input +// .dut_signal_port(axi_s_bus.arlen), // Agent input +// .dut_signal_port(axi_s_bus.arlock), // Agent input +// .dut_signal_port(axi_s_bus.arqos), // Agent input +// .dut_signal_port(axi_s_bus.aregion), // Agent input +// .dut_signal_port(axi_s_bus.aruser), // Agent input +// .dut_signal_port(axi_s_bus.rvalid), // Agent output +// .dut_signal_port(axi_s_bus.rready), // Agent input +// .dut_signal_port(axi_s_bus.rlast), // Agent output +// .dut_signal_port(axi_s_bus.rdata), // Agent output +// .dut_signal_port(axi_s_bus.rid), // Agent output +// .dut_signal_port(axi_s_bus.ruser), // Agent output +// .dut_signal_port(axi_s_bus.rresp), // Agent output + +import uvmf_base_pkg_hdl::*; +import axi_s_pkg_hdl::*; + +interface axi_s_if #( + int AW_WIDTH = 32, + int LEN = 8, + int DATA_WIDTH = 32, + int X = 16 + ) + + ( + input logic axi_clk, + input logic rst, + input logic awvalid, + output logic awready, + input logic [AW_WIDTH-1:0] awaddr, + input logic [2:0] awsize, + input logic [1:0] awburst, + input logic [3:0] awcache, + input logic [2:0] awprot, + input logic [X-1:0] awid, + input logic [LEN-1:0] awlen, + input logic awlock, + input logic [3:0] awqos, + input logic [3:0] awregion, + input logic [X-1:0] awuser, + input logic wvalid, + output logic wready, + input logic wlast, + input logic [DATA_WIDTH-1:0] wdata, + input logic [DATA_WIDTH/8-1:0] wstrb, + input logic [X-1:0] wid, + input logic [X-1:0] wuser, + output logic bwvalid, + output logic bwready, + input logic [1:0] bresp, + output logic [X-1:0] bid, + output logic [X-1:0] buser, + input logic arvalid, + output logic aready, + input logic [AW_WIDTH-1:0] araddr, + input logic [2:0] arsize, + input logic [1:0] arburst, + input logic [3:0] arcache, + input logic [2:0] arprot, + input logic [X-1:0] arid, + input logic [LEN-1:0] arlen, + input logic arlock, + input logic [3:0] arqos, + input logic [3:0] aregion, + input logic [X-1:0] aruser, + output logic rvalid, + input logic rready, + output logic rlast, + output logic [DATA_WIDTH-1:0] rdata, + output logic [X-1:0] rid, + output logic [X-1:0] ruser, + output logic [1:0] rresp + ); + +modport monitor_port + ( + input axi_clk, + input rst, + input awvalid, + input awready, + input awaddr, + input awsize, + input awburst, + input awcache, + input awprot, + input awid, + input awlen, + input awlock, + input awqos, + input awregion, + input awuser, + input wvalid, + input wready, + input wlast, + input wdata, + input wstrb, + input wid, + input wuser, + input bwvalid, + input bwready, + input bresp, + input bid, + input buser, + input arvalid, + input aready, + input araddr, + input arsize, + input arburst, + input arcache, + input arprot, + input arid, + input arlen, + input arlock, + input arqos, + input aregion, + input aruser, + input rvalid, + input rready, + input rlast, + input rdata, + input rid, + input ruser, + input rresp + ); + +modport initiator_port + ( + input axi_clk, + input rst, + input awvalid, + output awready, + input awaddr, + input awsize, + input awburst, + input awcache, + input awprot, + input awid, + input awlen, + input awlock, + input awqos, + input awregion, + input awuser, + input wvalid, + output wready, + input wlast, + input wdata, + input wstrb, + input wid, + input wuser, + output bwvalid, + output bwready, + input bresp, + output bid, + output buser, + input arvalid, + output aready, + input araddr, + input arsize, + input arburst, + input arcache, + input arprot, + input arid, + input arlen, + input arlock, + input arqos, + input aregion, + input aruser, + output rvalid, + input rready, + output rlast, + output rdata, + output rid, + output ruser, + output rresp + ); + +modport responder_port + ( + input axi_clk, + input rst, + output awvalid, + input awready, + output awaddr, + output awsize, + output awburst, + output awcache, + output awprot, + output awid, + output awlen, + output awlock, + output awqos, + output awregion, + output awuser, + output wvalid, + input wready, + output wlast, + output wdata, + output wstrb, + output wid, + output wuser, + input bwvalid, + input bwready, + output bresp, + input bid, + input buser, + output arvalid, + input aready, + output araddr, + output arsize, + output arburst, + output arcache, + output arprot, + output arid, + output arlen, + output arlock, + output arqos, + output aregion, + output aruser, + input rvalid, + output rready, + input rlast, + input rdata, + input rid, + input ruser, + input rresp + ); + + +// pragma uvmf custom interface_item_additional begin +// pragma uvmf custom interface_item_additional end + +endinterface + +// pragma uvmf custom external begin +// pragma uvmf custom external end +`endif diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/axi_s_pkg/src/axi_s_infact_coverage_strategy.csv b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/axi_s_pkg/src/axi_s_infact_coverage_strategy.csv new file mode 100644 index 00000000..1c218e14 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/axi_s_pkg/src/axi_s_infact_coverage_strategy.csv @@ -0,0 +1,6 @@ +Global +auto_bin_max, 64 + +Name,Type,Include +rand_fields,coverpoint,=rand *.** + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/axi_s_pkg/src/axi_s_macros.svh b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/axi_s_pkg/src/axi_s_macros.svh new file mode 100644 index 00000000..84dc9f36 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/axi_s_pkg/src/axi_s_macros.svh @@ -0,0 +1,517 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This file contains macros used with the axi_s package. +// These macros include packed struct definitions. These structs are +// used to pass data between classes, hvl, and BFM's, hdl. Use of +// structs are more efficient and simpler to modify. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// + +// **************************************************************************** +// When changing the contents of this struct, be sure to update the to_struct +// and from_struct methods defined in the macros below that are used in +// the axi_s_configuration class. +// + `define axi_s_CONFIGURATION_STRUCT \ +typedef struct packed { \ + uvmf_active_passive_t active_passive; \ + uvmf_initiator_responder_t initiator_responder; \ + } axi_s_configuration_s; + + `define axi_s_CONFIGURATION_TO_STRUCT_FUNCTION \ + virtual function axi_s_configuration_s to_struct();\ + axi_s_configuration_struct = \ + {\ + this.active_passive,\ + this.initiator_responder\ + };\ + return ( axi_s_configuration_struct );\ + endfunction + + `define axi_s_CONFIGURATION_FROM_STRUCT_FUNCTION \ + virtual function void from_struct(axi_s_configuration_s axi_s_configuration_struct);\ + {\ + this.active_passive,\ + this.initiator_responder \ + } = axi_s_configuration_struct;\ + endfunction + +// **************************************************************************** +// When changing the contents of this struct, be sure to update the to_monitor_struct +// and from_monitor_struct methods of the axi_s_transaction class. +// + `define axi_s_MONITOR_STRUCT typedef struct packed { \ + bit awvalid ; \ + bit awready ; \ + bit [AW_WIDTH-1:0] awaddr ; \ + bit awsize ; \ + bit awburst ; \ + bit awcache ; \ + bit awprot ; \ + bit [X-1:0] awid ; \ + bit [LEN-1:0] awlen ; \ + bit awlock ; \ + bit awqos ; \ + bit awregion ; \ + bit [X-1:0] awuser ; \ + bit wvalid ; \ + bit wready ; \ + bit wlast ; \ + bit [DATA_WIDTH-1:0] wdata ; \ + bit [DATA_WIDTH/8-1:0] wstrb ; \ + bit [X-1:0] wid ; \ + bit [X-1:0] wuser ; \ + bit bwvalid ; \ + bit bwready ; \ + bit bresp ; \ + bit [X-1:0] bid ; \ + bit [X-1:0] buser ; \ + bit arvalid ; \ + bit aready ; \ + bit [AW_WIDTH-1:0] araddr ; \ + bit arsize ; \ + bit arburst ; \ + bit arcache ; \ + bit arprot ; \ + bit [X-1:0] arid ; \ + bit [LEN-1:0] arlen ; \ + bit arlock ; \ + bit arqos ; \ + bit aregion ; \ + bit [X-1:0] aruser ; \ + bit rvalid ; \ + bit rready ; \ + bit rlast ; \ + bit [DATA_WIDTH-1:0] rdata ; \ + bit [X-1:0] rid ; \ + bit [X-1:0] ruser ; \ + bit rresp ; \ + } axi_s_monitor_s; + + `define axi_s_TO_MONITOR_STRUCT_FUNCTION \ + virtual function axi_s_monitor_s to_monitor_struct();\ + axi_s_monitor_struct = \ + { \ + this.awvalid , \ + this.awready , \ + this.awaddr , \ + this.awsize , \ + this.awburst , \ + this.awcache , \ + this.awprot , \ + this.awid , \ + this.awlen , \ + this.awlock , \ + this.awqos , \ + this.awregion , \ + this.awuser , \ + this.wvalid , \ + this.wready , \ + this.wlast , \ + this.wdata , \ + this.wstrb , \ + this.wid , \ + this.wuser , \ + this.bwvalid , \ + this.bwready , \ + this.bresp , \ + this.bid , \ + this.buser , \ + this.arvalid , \ + this.aready , \ + this.araddr , \ + this.arsize , \ + this.arburst , \ + this.arcache , \ + this.arprot , \ + this.arid , \ + this.arlen , \ + this.arlock , \ + this.arqos , \ + this.aregion , \ + this.aruser , \ + this.rvalid , \ + this.rready , \ + this.rlast , \ + this.rdata , \ + this.rid , \ + this.ruser , \ + this.rresp \ + };\ + return ( axi_s_monitor_struct);\ + endfunction\ + + `define axi_s_FROM_MONITOR_STRUCT_FUNCTION \ + virtual function void from_monitor_struct(axi_s_monitor_s axi_s_monitor_struct);\ + {\ + this.awvalid , \ + this.awready , \ + this.awaddr , \ + this.awsize , \ + this.awburst , \ + this.awcache , \ + this.awprot , \ + this.awid , \ + this.awlen , \ + this.awlock , \ + this.awqos , \ + this.awregion , \ + this.awuser , \ + this.wvalid , \ + this.wready , \ + this.wlast , \ + this.wdata , \ + this.wstrb , \ + this.wid , \ + this.wuser , \ + this.bwvalid , \ + this.bwready , \ + this.bresp , \ + this.bid , \ + this.buser , \ + this.arvalid , \ + this.aready , \ + this.araddr , \ + this.arsize , \ + this.arburst , \ + this.arcache , \ + this.arprot , \ + this.arid , \ + this.arlen , \ + this.arlock , \ + this.arqos , \ + this.aregion , \ + this.aruser , \ + this.rvalid , \ + this.rready , \ + this.rlast , \ + this.rdata , \ + this.rid , \ + this.ruser , \ + this.rresp \ + } = axi_s_monitor_struct;\ + endfunction + +// **************************************************************************** +// When changing the contents of this struct, be sure to update the to_initiator_struct +// and from_initiator_struct methods of the axi_s_transaction class. +// Also update the comments in the driver BFM. +// + `define axi_s_INITIATOR_STRUCT typedef struct packed { \ + bit awvalid ; \ + bit awready ; \ + bit [AW_WIDTH-1:0] awaddr ; \ + bit awsize ; \ + bit awburst ; \ + bit awcache ; \ + bit awprot ; \ + bit [X-1:0] awid ; \ + bit [LEN-1:0] awlen ; \ + bit awlock ; \ + bit awqos ; \ + bit awregion ; \ + bit [X-1:0] awuser ; \ + bit wvalid ; \ + bit wready ; \ + bit wlast ; \ + bit [DATA_WIDTH-1:0] wdata ; \ + bit [DATA_WIDTH/8-1:0] wstrb ; \ + bit [X-1:0] wid ; \ + bit [X-1:0] wuser ; \ + bit bwvalid ; \ + bit bwready ; \ + bit bresp ; \ + bit [X-1:0] bid ; \ + bit [X-1:0] buser ; \ + bit arvalid ; \ + bit aready ; \ + bit [AW_WIDTH-1:0] araddr ; \ + bit arsize ; \ + bit arburst ; \ + bit arcache ; \ + bit arprot ; \ + bit [X-1:0] arid ; \ + bit [LEN-1:0] arlen ; \ + bit arlock ; \ + bit arqos ; \ + bit aregion ; \ + bit [X-1:0] aruser ; \ + bit rvalid ; \ + bit rready ; \ + bit rlast ; \ + bit [DATA_WIDTH-1:0] rdata ; \ + bit [X-1:0] rid ; \ + bit [X-1:0] ruser ; \ + bit rresp ; \ + } axi_s_initiator_s; + + `define axi_s_TO_INITIATOR_STRUCT_FUNCTION \ + virtual function axi_s_initiator_s to_initiator_struct();\ + axi_s_initiator_struct = \ + {\ + this.awvalid , \ + this.awready , \ + this.awaddr , \ + this.awsize , \ + this.awburst , \ + this.awcache , \ + this.awprot , \ + this.awid , \ + this.awlen , \ + this.awlock , \ + this.awqos , \ + this.awregion , \ + this.awuser , \ + this.wvalid , \ + this.wready , \ + this.wlast , \ + this.wdata , \ + this.wstrb , \ + this.wid , \ + this.wuser , \ + this.bwvalid , \ + this.bwready , \ + this.bresp , \ + this.bid , \ + this.buser , \ + this.arvalid , \ + this.aready , \ + this.araddr , \ + this.arsize , \ + this.arburst , \ + this.arcache , \ + this.arprot , \ + this.arid , \ + this.arlen , \ + this.arlock , \ + this.arqos , \ + this.aregion , \ + this.aruser , \ + this.rvalid , \ + this.rready , \ + this.rlast , \ + this.rdata , \ + this.rid , \ + this.ruser , \ + this.rresp \ + };\ + return ( axi_s_initiator_struct);\ + endfunction + + `define axi_s_FROM_INITIATOR_STRUCT_FUNCTION \ + virtual function void from_initiator_struct(axi_s_initiator_s axi_s_initiator_struct);\ + {\ + this.awvalid , \ + this.awready , \ + this.awaddr , \ + this.awsize , \ + this.awburst , \ + this.awcache , \ + this.awprot , \ + this.awid , \ + this.awlen , \ + this.awlock , \ + this.awqos , \ + this.awregion , \ + this.awuser , \ + this.wvalid , \ + this.wready , \ + this.wlast , \ + this.wdata , \ + this.wstrb , \ + this.wid , \ + this.wuser , \ + this.bwvalid , \ + this.bwready , \ + this.bresp , \ + this.bid , \ + this.buser , \ + this.arvalid , \ + this.aready , \ + this.araddr , \ + this.arsize , \ + this.arburst , \ + this.arcache , \ + this.arprot , \ + this.arid , \ + this.arlen , \ + this.arlock , \ + this.arqos , \ + this.aregion , \ + this.aruser , \ + this.rvalid , \ + this.rready , \ + this.rlast , \ + this.rdata , \ + this.rid , \ + this.ruser , \ + this.rresp \ + } = axi_s_initiator_struct;\ + endfunction + +// **************************************************************************** +// When changing the contents of this struct, be sure to update the to_responder_struct +// and from_responder_struct methods of the axi_s_transaction class. +// Also update the comments in the driver BFM. +// + `define axi_s_RESPONDER_STRUCT typedef struct packed { \ + bit awvalid ; \ + bit awready ; \ + bit [AW_WIDTH-1:0] awaddr ; \ + bit awsize ; \ + bit awburst ; \ + bit awcache ; \ + bit awprot ; \ + bit [X-1:0] awid ; \ + bit [LEN-1:0] awlen ; \ + bit awlock ; \ + bit awqos ; \ + bit awregion ; \ + bit [X-1:0] awuser ; \ + bit wvalid ; \ + bit wready ; \ + bit wlast ; \ + bit [DATA_WIDTH-1:0] wdata ; \ + bit [DATA_WIDTH/8-1:0] wstrb ; \ + bit [X-1:0] wid ; \ + bit [X-1:0] wuser ; \ + bit bwvalid ; \ + bit bwready ; \ + bit bresp ; \ + bit [X-1:0] bid ; \ + bit [X-1:0] buser ; \ + bit arvalid ; \ + bit aready ; \ + bit [AW_WIDTH-1:0] araddr ; \ + bit arsize ; \ + bit arburst ; \ + bit arcache ; \ + bit arprot ; \ + bit [X-1:0] arid ; \ + bit [LEN-1:0] arlen ; \ + bit arlock ; \ + bit arqos ; \ + bit aregion ; \ + bit [X-1:0] aruser ; \ + bit rvalid ; \ + bit rready ; \ + bit rlast ; \ + bit [DATA_WIDTH-1:0] rdata ; \ + bit [X-1:0] rid ; \ + bit [X-1:0] ruser ; \ + bit rresp ; \ + } axi_s_responder_s; + + `define axi_s_TO_RESPONDER_STRUCT_FUNCTION \ + virtual function axi_s_responder_s to_responder_struct();\ + axi_s_responder_struct = \ + {\ + this.awvalid , \ + this.awready , \ + this.awaddr , \ + this.awsize , \ + this.awburst , \ + this.awcache , \ + this.awprot , \ + this.awid , \ + this.awlen , \ + this.awlock , \ + this.awqos , \ + this.awregion , \ + this.awuser , \ + this.wvalid , \ + this.wready , \ + this.wlast , \ + this.wdata , \ + this.wstrb , \ + this.wid , \ + this.wuser , \ + this.bwvalid , \ + this.bwready , \ + this.bresp , \ + this.bid , \ + this.buser , \ + this.arvalid , \ + this.aready , \ + this.araddr , \ + this.arsize , \ + this.arburst , \ + this.arcache , \ + this.arprot , \ + this.arid , \ + this.arlen , \ + this.arlock , \ + this.arqos , \ + this.aregion , \ + this.aruser , \ + this.rvalid , \ + this.rready , \ + this.rlast , \ + this.rdata , \ + this.rid , \ + this.ruser , \ + this.rresp \ + };\ + return ( axi_s_responder_struct);\ + endfunction + + `define axi_s_FROM_RESPONDER_STRUCT_FUNCTION \ + virtual function void from_responder_struct(axi_s_responder_s axi_s_responder_struct);\ + {\ + this.awvalid , \ + this.awready , \ + this.awaddr , \ + this.awsize , \ + this.awburst , \ + this.awcache , \ + this.awprot , \ + this.awid , \ + this.awlen , \ + this.awlock , \ + this.awqos , \ + this.awregion , \ + this.awuser , \ + this.wvalid , \ + this.wready , \ + this.wlast , \ + this.wdata , \ + this.wstrb , \ + this.wid , \ + this.wuser , \ + this.bwvalid , \ + this.bwready , \ + this.bresp , \ + this.bid , \ + this.buser , \ + this.arvalid , \ + this.aready , \ + this.araddr , \ + this.arsize , \ + this.arburst , \ + this.arcache , \ + this.arprot , \ + this.arid , \ + this.arlen , \ + this.arlock , \ + this.arqos , \ + this.aregion , \ + this.aruser , \ + this.rvalid , \ + this.rready , \ + this.rlast , \ + this.rdata , \ + this.rid , \ + this.ruser , \ + this.rresp \ + } = axi_s_responder_struct;\ + endfunction +// pragma uvmf custom additional begin +// pragma uvmf custom additional end diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/axi_s_pkg/src/axi_s_monitor.svh b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/axi_s_pkg/src/axi_s_monitor.svh new file mode 100644 index 00000000..5c3f114a --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/axi_s_pkg/src/axi_s_monitor.svh @@ -0,0 +1,114 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This class receives axi_s transactions observed by the +// axi_s monitor BFM and broadcasts them through the analysis port +// on the agent. It accesses the monitor BFM through the monitor +// task. This UVM component captures transactions +// for viewing in the waveform viewer if the +// enable_transaction_viewing flag is set in the configuration. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +`ifndef AXI_S_MONITOR +`define AXI_S_MONITOR +class axi_s_monitor #( + int AW_WIDTH = 32, + int LEN = 8, + int DATA_WIDTH = 32, + int X = 16 + ) extends uvmf_monitor_base #( + .CONFIG_T(axi_s_configuration #( + .AW_WIDTH(AW_WIDTH), + .LEN(LEN), + .DATA_WIDTH(DATA_WIDTH), + .X(X) + )), + .BFM_BIND_T(virtual axi_s_monitor_bfm #( + .AW_WIDTH(AW_WIDTH), + .LEN(LEN), + .DATA_WIDTH(DATA_WIDTH), + .X(X) + )), + .TRANS_T(axi_s_transaction #( + .AW_WIDTH(AW_WIDTH), + .LEN(LEN), + .DATA_WIDTH(DATA_WIDTH), + .X(X) + ))); + + `uvm_component_param_utils( axi_s_monitor #( + AW_WIDTH, + LEN, + DATA_WIDTH, + X + )) + +// Structure used to pass data from monitor BFM to monitor class in agent. +// Use to_monitor_struct function to pack transaction variables into structure. +// Use from_monitor_struct function to unpack transaction variables from structure. +`axi_s_MONITOR_STRUCT + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + +// **************************************************************************** +// This function is the standard SystemVerilog constructor. +// + function new( string name = "", uvm_component parent = null ); + super.new( name, parent ); + endfunction + +// **************************************************************************** +// This function sends configuration object variables to the monitor BFM +// using the configuration struct. +// + virtual function void configure(input CONFIG_T cfg); + bfm.configure( cfg.to_struct() ); + + endfunction + +// **************************************************************************** +// This function places a handle to this class in the proxy variable in the +// monitor BFM. This allows the monitor BFM to call the notify_transaction +// function within this class. +// + virtual function void set_bfm_proxy_handle(); + bfm.proxy = this; endfunction + +// *************************************************************************** + virtual task run_phase(uvm_phase phase); + // Start monitor BFM thread and don't call super.run() in order to + // override the default monitor proxy 'pull' behavior with the more + // emulation-friendly BFM 'push' approach using the notify_transaction + // function below + bfm.start_monitoring(); + endtask + +// ************************************************************************** + +// This function is called by the monitor BFM. It receives data observed by the +// monitor BFM. Data is passed using the axi_s_monitor_struct. + virtual function void notify_transaction(input axi_s_monitor_s axi_s_monitor_struct); + + + trans = new("trans"); + trans.from_monitor_struct(axi_s_monitor_struct); + trans.start_time = time_stamp; + trans.end_time = $time; + time_stamp = trans.end_time; + + analyze(trans); + endfunction + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end +`endif diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/axi_s_pkg/src/axi_s_monitor_bfm.sv b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/axi_s_pkg/src/axi_s_monitor_bfm.sv new file mode 100644 index 00000000..80278734 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/axi_s_pkg/src/axi_s_monitor_bfm.sv @@ -0,0 +1,362 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This interface performs the axi_s signal monitoring. +// It is accessed by the uvm axi_s monitor through a virtual +// interface handle in the axi_s configuration. It monitors the +// signals passed in through the port connection named bus of +// type axi_s_if. +// +// Input signals from the axi_s_if are assigned to an internal input +// signal with a _i suffix. The _i signal should be used for sampling. +// +// The input signal connections are as follows: +// bus.signal -> signal_i +// +// Interface functions and tasks used by UVM components: +// monitor(inout TRANS_T txn); +// This task receives the transaction, txn, from the +// UVM monitor and then populates variables in txn +// from values observed on bus activity. This task +// blocks until an operation on the axi_s bus is complete. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +`ifndef AXI_S_MONITOR_BFM +`define AXI_S_MONITOR_BFM +import uvmf_base_pkg_hdl::*; +import axi_s_pkg_hdl::*; +`include "src/axi_s_macros.svh" + + +interface axi_s_monitor_bfm #( + int AW_WIDTH = 32, + int LEN = 8, + int DATA_WIDTH = 32, + int X = 16 + ) + ( axi_s_if bus ); + // The pragma below and additional ones in-lined further down are for running this BFM on Veloce + // pragma attribute axi_s_monitor_bfm partition_interface_xif + +`ifndef XRTL +// This code is to aid in debugging parameter mismatches between the BFM and its corresponding agent. +// Enable this debug by setting UVM_VERBOSITY to UVM_DEBUG +// Setting UVM_VERBOSITY to UVM_DEBUG causes all BFM's and all agents to display their parameter settings. +// All of the messages from this feature have a UVM messaging id value of "CFG" +// The transcript or run.log can be parsed to ensure BFM parameter settings match its corresponding agents parameter settings. +import uvm_pkg::*; +`include "uvm_macros.svh" +initial begin : bfm_vs_agent_parameter_debug + `uvm_info("CFG", + $psprintf("The BFM at '%m' has the following parameters: AW_WIDTH=%x LEN=%x DATA_WIDTH=%x X=%x ", AW_WIDTH,LEN,DATA_WIDTH,X), + UVM_DEBUG) +end +`endif + + + // Structure used to pass transaction data from monitor BFM to monitor class in agent. +`axi_s_MONITOR_STRUCT + axi_s_monitor_s axi_s_monitor_struct; + + // Structure used to pass configuration data from monitor class to monitor BFM. + `axi_s_CONFIGURATION_STRUCT + + + // Config value to determine if this is an initiator or a responder + uvmf_initiator_responder_t initiator_responder; + // Custom configuration variables. + // These are set using the configure function which is called during the UVM connect_phase + + logic axi_clk_i; + logic rst_i; + tri awvalid_i; + tri awready_i; + tri [AW_WIDTH-1:0] awaddr_i; + tri [2:0] awsize_i; + tri [1:0] awburst_i; + tri [3:0] awcache_i; + tri [2:0] awprot_i; + tri [X-1:0] awid_i; + tri [LEN-1:0] awlen_i; + tri awlock_i; + tri [3:0] awqos_i; + tri [3:0] awregion_i; + tri [X-1:0] awuser_i; + tri wvalid_i; + tri wready_i; + tri wlast_i; + tri [DATA_WIDTH-1:0] wdata_i; + tri [DATA_WIDTH/8-1:0] wstrb_i; + tri [X-1:0] wid_i; + tri [X-1:0] wuser_i; + tri bwvalid_i; + tri bwready_i; + tri [1:0] bresp_i; + tri [X-1:0] bid_i; + tri [X-1:0] buser_i; + tri arvalid_i; + tri aready_i; + tri [AW_WIDTH-1:0] araddr_i; + tri [2:0] arsize_i; + tri [1:0] arburst_i; + tri [3:0] arcache_i; + tri [2:0] arprot_i; + tri [X-1:0] arid_i; + tri [LEN-1:0] arlen_i; + tri arlock_i; + tri [3:0] arqos_i; + tri [3:0] aregion_i; + tri [X-1:0] aruser_i; + tri rvalid_i; + tri rready_i; + tri rlast_i; + tri [DATA_WIDTH-1:0] rdata_i; + tri [X-1:0] rid_i; + tri [X-1:0] ruser_i; + tri [1:0] rresp_i; + assign axi_clk_i = bus.axi_clk; + assign rst_i = bus.rst; + assign awvalid_i = bus.awvalid; + assign awready_i = bus.awready; + assign awaddr_i = bus.awaddr; + assign awsize_i = bus.awsize; + assign awburst_i = bus.awburst; + assign awcache_i = bus.awcache; + assign awprot_i = bus.awprot; + assign awid_i = bus.awid; + assign awlen_i = bus.awlen; + assign awlock_i = bus.awlock; + assign awqos_i = bus.awqos; + assign awregion_i = bus.awregion; + assign awuser_i = bus.awuser; + assign wvalid_i = bus.wvalid; + assign wready_i = bus.wready; + assign wlast_i = bus.wlast; + assign wdata_i = bus.wdata; + assign wstrb_i = bus.wstrb; + assign wid_i = bus.wid; + assign wuser_i = bus.wuser; + assign bwvalid_i = bus.bwvalid; + assign bwready_i = bus.bwready; + assign bresp_i = bus.bresp; + assign bid_i = bus.bid; + assign buser_i = bus.buser; + assign arvalid_i = bus.arvalid; + assign aready_i = bus.aready; + assign araddr_i = bus.araddr; + assign arsize_i = bus.arsize; + assign arburst_i = bus.arburst; + assign arcache_i = bus.arcache; + assign arprot_i = bus.arprot; + assign arid_i = bus.arid; + assign arlen_i = bus.arlen; + assign arlock_i = bus.arlock; + assign arqos_i = bus.arqos; + assign aregion_i = bus.aregion; + assign aruser_i = bus.aruser; + assign rvalid_i = bus.rvalid; + assign rready_i = bus.rready; + assign rlast_i = bus.rlast; + assign rdata_i = bus.rdata; + assign rid_i = bus.rid; + assign ruser_i = bus.ruser; + assign rresp_i = bus.rresp; + + // Proxy handle to UVM monitor + axi_s_pkg::axi_s_monitor #( + .AW_WIDTH(AW_WIDTH), + .LEN(LEN), + .DATA_WIDTH(DATA_WIDTH), + .X(X) + ) proxy; + // pragma tbx oneway proxy.notify_transaction + + // pragma uvmf custom interface_item_additional begin + // pragma uvmf custom interface_item_additional end + + //****************************************************************** + task wait_for_reset();// pragma tbx xtf + @(posedge axi_clk_i) ; + do_wait_for_reset(); + endtask + + // **************************************************************************** + task do_wait_for_reset(); + // pragma uvmf custom reset_condition begin + wait ( rst_i === 1 ) ; + @(posedge axi_clk_i) ; + // pragma uvmf custom reset_condition end + endtask + + //****************************************************************** + + task wait_for_num_clocks(input int unsigned count); // pragma tbx xtf + @(posedge axi_clk_i); + + repeat (count-1) @(posedge axi_clk_i); + endtask + + //****************************************************************** + event go; + function void start_monitoring();// pragma tbx xtf + -> go; + endfunction + + // **************************************************************************** + initial begin + @go; + forever begin + @(posedge axi_clk_i); + do_monitor( axi_s_monitor_struct ); + + + proxy.notify_transaction( axi_s_monitor_struct ); + + end + end + + //****************************************************************** + // The configure() function is used to pass agent configuration + // variables to the monitor BFM. It is called by the monitor within + // the agent at the beginning of the simulation. It may be called + // during the simulation if agent configuration variables are updated + // and the monitor BFM needs to be aware of the new configuration + // variables. + // + function void configure(axi_s_configuration_s axi_s_configuration_arg); // pragma tbx xtf + initiator_responder = axi_s_configuration_arg.initiator_responder; + // pragma uvmf custom configure begin + // pragma uvmf custom configure end + endfunction + + + // **************************************************************************** + + task do_monitor(output axi_s_monitor_s axi_s_monitor_struct); + // + // Available struct members: + // // axi_s_monitor_struct.awvalid + // // axi_s_monitor_struct.awready + // // axi_s_monitor_struct.awaddr + // // axi_s_monitor_struct.awsize + // // axi_s_monitor_struct.awburst + // // axi_s_monitor_struct.awcache + // // axi_s_monitor_struct.awprot + // // axi_s_monitor_struct.awid + // // axi_s_monitor_struct.awlen + // // axi_s_monitor_struct.awlock + // // axi_s_monitor_struct.awqos + // // axi_s_monitor_struct.awregion + // // axi_s_monitor_struct.awuser + // // axi_s_monitor_struct.wvalid + // // axi_s_monitor_struct.wready + // // axi_s_monitor_struct.wlast + // // axi_s_monitor_struct.wdata + // // axi_s_monitor_struct.wstrb + // // axi_s_monitor_struct.wid + // // axi_s_monitor_struct.wuser + // // axi_s_monitor_struct.bwvalid + // // axi_s_monitor_struct.bwready + // // axi_s_monitor_struct.bresp + // // axi_s_monitor_struct.bid + // // axi_s_monitor_struct.buser + // // axi_s_monitor_struct.arvalid + // // axi_s_monitor_struct.aready + // // axi_s_monitor_struct.araddr + // // axi_s_monitor_struct.arsize + // // axi_s_monitor_struct.arburst + // // axi_s_monitor_struct.arcache + // // axi_s_monitor_struct.arprot + // // axi_s_monitor_struct.arid + // // axi_s_monitor_struct.arlen + // // axi_s_monitor_struct.arlock + // // axi_s_monitor_struct.arqos + // // axi_s_monitor_struct.aregion + // // axi_s_monitor_struct.aruser + // // axi_s_monitor_struct.rvalid + // // axi_s_monitor_struct.rready + // // axi_s_monitor_struct.rlast + // // axi_s_monitor_struct.rdata + // // axi_s_monitor_struct.rid + // // axi_s_monitor_struct.ruser + // // axi_s_monitor_struct.rresp + // // + // Reference code; + // How to wait for signal value + // while (control_signal === 1'b1) @(posedge axi_clk_i); + // + // How to assign a struct member, named xyz, from a signal. + // All available input signals listed. + // axi_s_monitor_struct.xyz = awvalid_i; // + // axi_s_monitor_struct.xyz = awready_i; // + // axi_s_monitor_struct.xyz = awaddr_i; // [AW_WIDTH-1:0] + // axi_s_monitor_struct.xyz = awsize_i; // [2:0] + // axi_s_monitor_struct.xyz = awburst_i; // [1:0] + // axi_s_monitor_struct.xyz = awcache_i; // [3:0] + // axi_s_monitor_struct.xyz = awprot_i; // [2:0] + // axi_s_monitor_struct.xyz = awid_i; // [X-1:0] + // axi_s_monitor_struct.xyz = awlen_i; // [LEN-1:0] + // axi_s_monitor_struct.xyz = awlock_i; // + // axi_s_monitor_struct.xyz = awqos_i; // [3:0] + // axi_s_monitor_struct.xyz = awregion_i; // [3:0] + // axi_s_monitor_struct.xyz = awuser_i; // [X-1:0] + // axi_s_monitor_struct.xyz = wvalid_i; // + // axi_s_monitor_struct.xyz = wready_i; // + // axi_s_monitor_struct.xyz = wlast_i; // + // axi_s_monitor_struct.xyz = wdata_i; // [DATA_WIDTH-1:0] + // axi_s_monitor_struct.xyz = wstrb_i; // [DATA_WIDTH/8-1:0] + // axi_s_monitor_struct.xyz = wid_i; // [X-1:0] + // axi_s_monitor_struct.xyz = wuser_i; // [X-1:0] + // axi_s_monitor_struct.xyz = bwvalid_i; // + // axi_s_monitor_struct.xyz = bwready_i; // + // axi_s_monitor_struct.xyz = bresp_i; // [1:0] + // axi_s_monitor_struct.xyz = bid_i; // [X-1:0] + // axi_s_monitor_struct.xyz = buser_i; // [X-1:0] + // axi_s_monitor_struct.xyz = arvalid_i; // + // axi_s_monitor_struct.xyz = aready_i; // + // axi_s_monitor_struct.xyz = araddr_i; // [AW_WIDTH-1:0] + // axi_s_monitor_struct.xyz = arsize_i; // [2:0] + // axi_s_monitor_struct.xyz = arburst_i; // [1:0] + // axi_s_monitor_struct.xyz = arcache_i; // [3:0] + // axi_s_monitor_struct.xyz = arprot_i; // [2:0] + // axi_s_monitor_struct.xyz = arid_i; // [X-1:0] + // axi_s_monitor_struct.xyz = arlen_i; // [LEN-1:0] + // axi_s_monitor_struct.xyz = arlock_i; // + // axi_s_monitor_struct.xyz = arqos_i; // [3:0] + // axi_s_monitor_struct.xyz = aregion_i; // [3:0] + // axi_s_monitor_struct.xyz = aruser_i; // [X-1:0] + // axi_s_monitor_struct.xyz = rvalid_i; // + // axi_s_monitor_struct.xyz = rready_i; // + // axi_s_monitor_struct.xyz = rlast_i; // + // axi_s_monitor_struct.xyz = rdata_i; // [DATA_WIDTH-1:0] + // axi_s_monitor_struct.xyz = rid_i; // [X-1:0] + // axi_s_monitor_struct.xyz = ruser_i; // [X-1:0] + // axi_s_monitor_struct.xyz = rresp_i; // [1:0] + // pragma uvmf custom do_monitor begin + // UVMF_CHANGE_ME : Implement protocol monitoring. The commented reference code + // below are examples of how to capture signal values and assign them to + // structure members. All available input signals are listed. The 'while' + // code example shows how to wait for a synchronous flow control signal. This + // task should return when a complete transfer has been observed. Once this task is + // exited with captured values, it is then called again to wait for and observe + // the next transfer. One clock cycle is consumed between calls to do_monitor. + @(posedge axi_clk_i); + @(posedge axi_clk_i); + @(posedge axi_clk_i); + @(posedge axi_clk_i); + // pragma uvmf custom do_monitor end + endtask + + +endinterface + +// pragma uvmf custom external begin +// pragma uvmf custom external end +`endif diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/axi_s_pkg/src/axi_s_random_sequence.svh b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/axi_s_pkg/src/axi_s_random_sequence.svh new file mode 100644 index 00000000..f42e4d3b --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/axi_s_pkg/src/axi_s_random_sequence.svh @@ -0,0 +1,75 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: +// This sequences randomizes the axi_s transaction and sends it +// to the UVM driver. +// +// This sequence constructs and randomizes a axi_s_transaction. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +`ifndef AXI_S_RANDOM_SEQUENCE +`define AXI_S_RANDOM_SEQUENCE +class axi_s_random_sequence #( + int AW_WIDTH = 32, + int LEN = 8, + int DATA_WIDTH = 32, + int X = 16 + ) + extends axi_s_sequence_base #( + .AW_WIDTH(AW_WIDTH), + .LEN(LEN), + .DATA_WIDTH(DATA_WIDTH), + .X(X) + ); + + `uvm_object_param_utils( axi_s_random_sequence #( + AW_WIDTH, + LEN, + DATA_WIDTH, + X + )) + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + //***************************************************************** + function new(string name = ""); + super.new(name); + endfunction: new + + // **************************************************************************** + // TASK : body() + // This task is automatically executed when this sequence is started using the + // start(sequencerHandle) task. + // + task body(); + + // Construct the transaction + req=axi_s_transaction#( + .AW_WIDTH(AW_WIDTH), + .LEN(LEN), + .DATA_WIDTH(DATA_WIDTH), + .X(X) + )::type_id::create("req"); + start_item(req); + // Randomize the transaction + if(!req.randomize()) `uvm_fatal("SEQ", "axi_s_random_sequence::body()-axi_s_transaction randomization failed") + // Send the transaction to the axi_s_driver_bfm via the sequencer and axi_s_driver. + finish_item(req); + `uvm_info("SEQ", {"Response:",req.convert2string()},UVM_MEDIUM) + + endtask + +endclass: axi_s_random_sequence + +// pragma uvmf custom external begin +// pragma uvmf custom external end +`endif diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/axi_s_pkg/src/axi_s_responder_sequence.svh b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/axi_s_pkg/src/axi_s_responder_sequence.svh new file mode 100644 index 00000000..238c2fb4 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/axi_s_pkg/src/axi_s_responder_sequence.svh @@ -0,0 +1,71 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This class can be used to provide stimulus when an interface +// has been configured to run in a responder mode. It +// will never finish by default, always going back to the driver +// and driver BFM for the next transaction with which to respond. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +`ifndef AXI_S_RESPONDER_SEQUENCE +`define AXI_S_RESPONDER_SEQUENCE +class axi_s_responder_sequence #( + int AW_WIDTH = 32, + int LEN = 8, + int DATA_WIDTH = 32, + int X = 16 + ) + extends axi_s_sequence_base #( + .AW_WIDTH(AW_WIDTH), + .LEN(LEN), + .DATA_WIDTH(DATA_WIDTH), + .X(X) + ); + + `uvm_object_param_utils( axi_s_responder_sequence #( + AW_WIDTH, + LEN, + DATA_WIDTH, + X + )) + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + function new(string name = "axi_s_responder_sequence"); + super.new(name); + endfunction + + task body(); + req=axi_s_transaction#( + .AW_WIDTH(AW_WIDTH), + .LEN(LEN), + .DATA_WIDTH(DATA_WIDTH), + .X(X) + )::type_id::create("req"); + forever begin + start_item(req); + finish_item(req); + // pragma uvmf custom body begin + // UVMF_CHANGE_ME : Do something here with the resulting req item. The + // finish_item() call above will block until the req transaction is ready + // to be handled by the responder sequence. + // If this was an item that required a response, the expectation is + // that the response should be populated within this transaction now. + `uvm_info("SEQ",$sformatf("Processed txn: %s",req.convert2string()),UVM_HIGH) + // pragma uvmf custom body end + end + endtask + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end +`endif diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/axi_s_pkg/src/axi_s_sequence_base.svh b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/axi_s_pkg/src/axi_s_sequence_base.svh new file mode 100644 index 00000000..0d7f3046 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/axi_s_pkg/src/axi_s_sequence_base.svh @@ -0,0 +1,128 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: +// This file contains the class used as the base class for all sequences +// for this interface. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +`ifndef AXI_S_SEQUENCE_BASE +`define AXI_S_SEQUENCE_BASE +class axi_s_sequence_base #( + int AW_WIDTH = 32, + int LEN = 8, + int DATA_WIDTH = 32, + int X = 16 + ) extends uvmf_sequence_base #( + .REQ(axi_s_transaction #( + .AW_WIDTH(AW_WIDTH), + .LEN(LEN), + .DATA_WIDTH(DATA_WIDTH), + .X(X) + )), + .RSP(axi_s_transaction #( + .AW_WIDTH(AW_WIDTH), + .LEN(LEN), + .DATA_WIDTH(DATA_WIDTH), + .X(X) + ))); + + `uvm_object_param_utils( axi_s_sequence_base #( + AW_WIDTH, + LEN, + DATA_WIDTH, + X + )) + + // variables + typedef axi_s_transaction #( + .AW_WIDTH(AW_WIDTH), + .LEN(LEN), + .DATA_WIDTH(DATA_WIDTH), + .X(X) + ) axi_s_transaction_req_t; + axi_s_transaction_req_t req; + typedef axi_s_transaction #( + .AW_WIDTH(AW_WIDTH), + .LEN(LEN), + .DATA_WIDTH(DATA_WIDTH), + .X(X) + ) axi_s_transaction_rsp_t; + axi_s_transaction_rsp_t rsp; + + // Event for identifying when a response was received from the sequencer + event new_rsp; + + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + // **************************************************************************** + // TASK : get_responses() + // This task recursively gets sequence item responses from the sequencer. + // + virtual task get_responses(); + fork + begin + // Block until new rsp available + get_response(rsp); + // New rsp received. Indicate to sequence using event. + ->new_rsp; + // Display the received response transaction + `uvm_info("SEQ", {"New response transaction:",rsp.convert2string()}, UVM_MEDIUM) + end + join_none + endtask + + // **************************************************************************** + // TASK : pre_body() + // This task is called automatically when start is called with call_pre_post set to 1 (default). + // By calling get_responses() within pre_body() any derived sequences are automatically + // processing response transactions. Only un-comment this call to get_responses() if you + // have configured the interface driver to utilize the response transaction path by setting + // the configuration variable "return_transaction_response" to 1. Otherwise it is possible + // to impact runtime performance and memory utilization. + // + virtual task pre_body(); + // pragma uvmf custom pre_body begin +// get_responses(); + // pragma uvmf custom pre_body end + endtask + + // **************************************************************************** + // TASK : body() + // This task is called automatically when start is called. This sequence sends + // a req sequence item to the sequencer identified as an argument in the call + // to start. + // + virtual task body(); + // pragma uvmf custom body begin + start_item(req); + finish_item(req); + // pragma uvmf custom body end + endtask + + // **************************************************************************** + // FUNCTION : new() + // This function is the standard SystemVerilog constructor. + // + function new( string name =""); + super.new( name ); + // pragma uvmf custom new begin + req = axi_s_transaction_req_t::type_id::create("req"); + rsp = axi_s_transaction_rsp_t::type_id::create("rsp"); + // pragma uvmf custom new end + endfunction + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end +`endif diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/axi_s_pkg/src/axi_s_transaction.svh b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/axi_s_pkg/src/axi_s_transaction.svh new file mode 100644 index 00000000..69655a9f --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/axi_s_pkg/src/axi_s_transaction.svh @@ -0,0 +1,335 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This class defines the variables required for an axi_s +// transaction. Class variables to be displayed in waveform transaction +// viewing are added to the transaction viewing stream in the add_to_wave +// function. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +`ifndef AXI_S_TRANSACTION +`define AXI_S_TRANSACTION +class axi_s_transaction #( + int AW_WIDTH = 32, + int LEN = 8, + int DATA_WIDTH = 32, + int X = 16 + ) extends uvmf_transaction_base; + + `uvm_object_param_utils( axi_s_transaction #( + AW_WIDTH, + LEN, + DATA_WIDTH, + X + )) + + bit awvalid ; + bit awready ; + bit [AW_WIDTH-1:0] awaddr ; + bit awsize ; + bit awburst ; + bit awcache ; + bit awprot ; + bit [X-1:0] awid ; + bit [LEN-1:0] awlen ; + bit awlock ; + bit awqos ; + bit awregion ; + bit [X-1:0] awuser ; + bit wvalid ; + bit wready ; + bit wlast ; + bit [DATA_WIDTH-1:0] wdata ; + bit [DATA_WIDTH/8-1:0] wstrb ; + bit [X-1:0] wid ; + bit [X-1:0] wuser ; + bit bwvalid ; + bit bwready ; + rand bit bresp ; + bit [X-1:0] bid ; + rand bit [X-1:0] buser ; + bit arvalid ; + bit aready ; + rand bit [AW_WIDTH-1:0] araddr ; + rand bit arsize ; + rand bit arburst ; + rand bit arcache ; + rand bit arprot ; + rand bit [X-1:0] arid ; + rand bit [LEN-1:0] arlen ; + rand bit arlock ; + rand bit arqos ; + bit aregion ; + bit [X-1:0] aruser ; + bit rvalid ; + bit rready ; + bit rlast ; + rand bit [DATA_WIDTH-1:0] rdata ; + rand bit [X-1:0] rid ; + rand bit [X-1:0] ruser ; + rand bit rresp ; + + //Constraints for the transaction variables: + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + //******************************************************************* + //******************************************************************* + // Macros that define structs and associated functions are + // located in axi_s_macros.svh + + //******************************************************************* + // Monitor macro used by axi_s_monitor and axi_s_monitor_bfm + // This struct is defined in axi_s_macros.svh + `axi_s_MONITOR_STRUCT + axi_s_monitor_s axi_s_monitor_struct; + //******************************************************************* + // FUNCTION: to_monitor_struct() + // This function packs transaction variables into a axi_s_monitor_s + // structure. The function returns the handle to the axi_s_monitor_struct. + // This function is defined in axi_s_macros.svh + `axi_s_TO_MONITOR_STRUCT_FUNCTION + //******************************************************************* + // FUNCTION: from_monitor_struct() + // This function unpacks the struct provided as an argument into transaction + // variables of this class. + // This function is defined in axi_s_macros.svh + `axi_s_FROM_MONITOR_STRUCT_FUNCTION + + //******************************************************************* + // Initiator macro used by axi_s_driver and axi_s_driver_bfm + // to communicate initiator driven data to axi_s_driver_bfm. + // This struct is defined in axi_s_macros.svh + `axi_s_INITIATOR_STRUCT + axi_s_initiator_s axi_s_initiator_struct; + //******************************************************************* + // FUNCTION: to_initiator_struct() + // This function packs transaction variables into a axi_s_initiator_s + // structure. The function returns the handle to the axi_s_initiator_struct. + // This function is defined in axi_s_macros.svh + `axi_s_TO_INITIATOR_STRUCT_FUNCTION + //******************************************************************* + // FUNCTION: from_initiator_struct() + // This function unpacks the struct provided as an argument into transaction + // variables of this class. + // This function is defined in axi_s_macros.svh + `axi_s_FROM_INITIATOR_STRUCT_FUNCTION + + //******************************************************************* + // Responder macro used by axi_s_driver and axi_s_driver_bfm + // to communicate Responder driven data to axi_s_driver_bfm. + // This struct is defined in axi_s_macros.svh + `axi_s_RESPONDER_STRUCT + axi_s_responder_s axi_s_responder_struct; + //******************************************************************* + // FUNCTION: to_responder_struct() + // This function packs transaction variables into a axi_s_responder_s + // structure. The function returns the handle to the axi_s_responder_struct. + // This function is defined in axi_s_macros.svh + `axi_s_TO_RESPONDER_STRUCT_FUNCTION + //******************************************************************* + // FUNCTION: from_responder_struct() + // This function unpacks the struct provided as an argument into transaction + // variables of this class. + // This function is defined in axi_s_macros.svh + `axi_s_FROM_RESPONDER_STRUCT_FUNCTION + // **************************************************************************** + // FUNCTION : new() + // This function is the standard SystemVerilog constructor. + // + function new( string name = "" ); + super.new( name ); + endfunction + + // **************************************************************************** + // FUNCTION: convert2string() + // This function converts all variables in this class to a single string for + // logfile reporting. + // + virtual function string convert2string(); + // pragma uvmf custom convert2string begin + // UVMF_CHANGE_ME : Customize format if desired. + return $sformatf("awvalid:0x%x awready:0x%x awaddr:0x%x awsize:0x%x awburst:0x%x awcache:0x%x awprot:0x%x awid:0x%x awlen:0x%x awlock:0x%x awqos:0x%x awregion:0x%x awuser:0x%x wvalid:0x%x wready:0x%x wlast:0x%x wdata:0x%x wstrb:0x%x wid:0x%x wuser:0x%x bwvalid:0x%x bwready:0x%x bresp:0x%x bid:0x%x buser:0x%x arvalid:0x%x aready:0x%x araddr:0x%x arsize:0x%x arburst:0x%x arcache:0x%x arprot:0x%x arid:0x%x arlen:0x%x arlock:0x%x arqos:0x%x aregion:0x%x aruser:0x%x rvalid:0x%x rready:0x%x rlast:0x%x rdata:0x%x rid:0x%x ruser:0x%x rresp:0x%x ",awvalid,awready,awaddr,awsize,awburst,awcache,awprot,awid,awlen,awlock,awqos,awregion,awuser,wvalid,wready,wlast,wdata,wstrb,wid,wuser,bwvalid,bwready,bresp,bid,buser,arvalid,aready,araddr,arsize,arburst,arcache,arprot,arid,arlen,arlock,arqos,aregion,aruser,rvalid,rready,rlast,rdata,rid,ruser,rresp); + // pragma uvmf custom convert2string end + endfunction + + //******************************************************************* + // FUNCTION: do_print() + // This function is automatically called when the .print() function + // is called on this class. + // + virtual function void do_print(uvm_printer printer); + // pragma uvmf custom do_print begin + // UVMF_CHANGE_ME : Current contents of do_print allows for the use of UVM 1.1d, 1.2 or P1800.2. + // Update based on your own printing preference according to your preferred UVM version + $display(convert2string()); + // pragma uvmf custom do_print end + endfunction + + //******************************************************************* + // FUNCTION: do_compare() + // This function is automatically called when the .compare() function + // is called on this class. + // + virtual function bit do_compare (uvm_object rhs, uvm_comparer comparer); + axi_s_transaction #( + .AW_WIDTH(AW_WIDTH), + .LEN(LEN), + .DATA_WIDTH(DATA_WIDTH), + .X(X) + ) RHS; + if (!$cast(RHS,rhs)) return 0; + // pragma uvmf custom do_compare begin + // UVMF_CHANGE_ME : Eliminate comparison of variables not to be used for compare + return (super.do_compare(rhs,comparer) + ); + // pragma uvmf custom do_compare end + endfunction + + //******************************************************************* + // FUNCTION: do_copy() + // This function is automatically called when the .copy() function + // is called on this class. + // + virtual function void do_copy (uvm_object rhs); + axi_s_transaction #( + .AW_WIDTH(AW_WIDTH), + .LEN(LEN), + .DATA_WIDTH(DATA_WIDTH), + .X(X) + ) RHS; + assert($cast(RHS,rhs)); + // pragma uvmf custom do_copy begin + super.do_copy(rhs); + this.awvalid = RHS.awvalid; + this.awready = RHS.awready; + this.awaddr = RHS.awaddr; + this.awsize = RHS.awsize; + this.awburst = RHS.awburst; + this.awcache = RHS.awcache; + this.awprot = RHS.awprot; + this.awid = RHS.awid; + this.awlen = RHS.awlen; + this.awlock = RHS.awlock; + this.awqos = RHS.awqos; + this.awregion = RHS.awregion; + this.awuser = RHS.awuser; + this.wvalid = RHS.wvalid; + this.wready = RHS.wready; + this.wlast = RHS.wlast; + this.wdata = RHS.wdata; + this.wstrb = RHS.wstrb; + this.wid = RHS.wid; + this.wuser = RHS.wuser; + this.bwvalid = RHS.bwvalid; + this.bwready = RHS.bwready; + this.bresp = RHS.bresp; + this.bid = RHS.bid; + this.buser = RHS.buser; + this.arvalid = RHS.arvalid; + this.aready = RHS.aready; + this.araddr = RHS.araddr; + this.arsize = RHS.arsize; + this.arburst = RHS.arburst; + this.arcache = RHS.arcache; + this.arprot = RHS.arprot; + this.arid = RHS.arid; + this.arlen = RHS.arlen; + this.arlock = RHS.arlock; + this.arqos = RHS.arqos; + this.aregion = RHS.aregion; + this.aruser = RHS.aruser; + this.rvalid = RHS.rvalid; + this.rready = RHS.rready; + this.rlast = RHS.rlast; + this.rdata = RHS.rdata; + this.rid = RHS.rid; + this.ruser = RHS.ruser; + this.rresp = RHS.rresp; + // pragma uvmf custom do_copy end + endfunction + + // **************************************************************************** + // FUNCTION: add_to_wave() + // This function is used to display variables in this class in the waveform + // viewer. The start_time and end_time variables must be set before this + // function is called. If the start_time and end_time variables are not set + // the transaction will be hidden at 0ns on the waveform display. + // + virtual function void add_to_wave(int transaction_viewing_stream_h); + `ifdef QUESTA + if (transaction_view_h == 0) begin + transaction_view_h = $begin_transaction(transaction_viewing_stream_h,"axi_s_transaction",start_time); + end + super.add_to_wave(transaction_view_h); + // pragma uvmf custom add_to_wave begin + // UVMF_CHANGE_ME : Color can be applied to transaction entries based on content, example below + // case() + // 1 : $add_color(transaction_view_h,"red"); + // default : $add_color(transaction_view_h,"grey"); + // endcase + // UVMF_CHANGE_ME : Eliminate transaction variables not wanted in transaction viewing in the waveform viewer + $add_attribute(transaction_view_h,awvalid,"awvalid"); + $add_attribute(transaction_view_h,awready,"awready"); + $add_attribute(transaction_view_h,awaddr,"awaddr"); + $add_attribute(transaction_view_h,awsize,"awsize"); + $add_attribute(transaction_view_h,awburst,"awburst"); + $add_attribute(transaction_view_h,awcache,"awcache"); + $add_attribute(transaction_view_h,awprot,"awprot"); + $add_attribute(transaction_view_h,awid,"awid"); + $add_attribute(transaction_view_h,awlen,"awlen"); + $add_attribute(transaction_view_h,awlock,"awlock"); + $add_attribute(transaction_view_h,awqos,"awqos"); + $add_attribute(transaction_view_h,awregion,"awregion"); + $add_attribute(transaction_view_h,awuser,"awuser"); + $add_attribute(transaction_view_h,wvalid,"wvalid"); + $add_attribute(transaction_view_h,wready,"wready"); + $add_attribute(transaction_view_h,wlast,"wlast"); + $add_attribute(transaction_view_h,wdata,"wdata"); + $add_attribute(transaction_view_h,wstrb,"wstrb"); + $add_attribute(transaction_view_h,wid,"wid"); + $add_attribute(transaction_view_h,wuser,"wuser"); + $add_attribute(transaction_view_h,bwvalid,"bwvalid"); + $add_attribute(transaction_view_h,bwready,"bwready"); + $add_attribute(transaction_view_h,bresp,"bresp"); + $add_attribute(transaction_view_h,bid,"bid"); + $add_attribute(transaction_view_h,buser,"buser"); + $add_attribute(transaction_view_h,arvalid,"arvalid"); + $add_attribute(transaction_view_h,aready,"aready"); + $add_attribute(transaction_view_h,araddr,"araddr"); + $add_attribute(transaction_view_h,arsize,"arsize"); + $add_attribute(transaction_view_h,arburst,"arburst"); + $add_attribute(transaction_view_h,arcache,"arcache"); + $add_attribute(transaction_view_h,arprot,"arprot"); + $add_attribute(transaction_view_h,arid,"arid"); + $add_attribute(transaction_view_h,arlen,"arlen"); + $add_attribute(transaction_view_h,arlock,"arlock"); + $add_attribute(transaction_view_h,arqos,"arqos"); + $add_attribute(transaction_view_h,aregion,"aregion"); + $add_attribute(transaction_view_h,aruser,"aruser"); + $add_attribute(transaction_view_h,rvalid,"rvalid"); + $add_attribute(transaction_view_h,rready,"rready"); + $add_attribute(transaction_view_h,rlast,"rlast"); + $add_attribute(transaction_view_h,rdata,"rdata"); + $add_attribute(transaction_view_h,rid,"rid"); + $add_attribute(transaction_view_h,ruser,"ruser"); + $add_attribute(transaction_view_h,rresp,"rresp"); + // pragma uvmf custom add_to_wave end + $end_transaction(transaction_view_h,end_time); + $free_transaction(transaction_view_h); + `endif // QUESTA + endfunction + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end +`endif diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/axi_s_pkg/src/axi_s_transaction_coverage.svh b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/axi_s_pkg/src/axi_s_transaction_coverage.svh new file mode 100644 index 00000000..30ee858a --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/axi_s_pkg/src/axi_s_transaction_coverage.svh @@ -0,0 +1,132 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This class records axi_s transaction information using +// a covergroup named axi_s_transaction_cg. An instance of this +// coverage component is instantiated in the uvmf_parameterized_agent +// if the has_coverage flag is set. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +`ifndef AXI_S_TRANSACTION_COVERAGE +`define AXI_S_TRANSACTION_COVERAGE +class axi_s_transaction_coverage #( + int AW_WIDTH = 32, + int LEN = 8, + int DATA_WIDTH = 32, + int X = 16 + ) extends uvm_subscriber #(.T(axi_s_transaction #( + .AW_WIDTH(AW_WIDTH), + .LEN(LEN), + .DATA_WIDTH(DATA_WIDTH), + .X(X) + ))); + + `uvm_component_param_utils( axi_s_transaction_coverage #( + AW_WIDTH, + LEN, + DATA_WIDTH, + X + )) + + T coverage_trans; + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + // **************************************************************************** + covergroup axi_s_transaction_cg; + // pragma uvmf custom covergroup begin + // UVMF_CHANGE_ME : Add coverage bins, crosses, exclusions, etc. according to coverage needs. + option.auto_bin_max=1024; + option.per_instance=1; + awvalid: coverpoint coverage_trans.awvalid; + awready: coverpoint coverage_trans.awready; + awaddr: coverpoint coverage_trans.awaddr; + awsize: coverpoint coverage_trans.awsize; + awburst: coverpoint coverage_trans.awburst; + awcache: coverpoint coverage_trans.awcache; + awprot: coverpoint coverage_trans.awprot; + awid: coverpoint coverage_trans.awid; + awlen: coverpoint coverage_trans.awlen; + awlock: coverpoint coverage_trans.awlock; + awqos: coverpoint coverage_trans.awqos; + awregion: coverpoint coverage_trans.awregion; + awuser: coverpoint coverage_trans.awuser; + wvalid: coverpoint coverage_trans.wvalid; + wready: coverpoint coverage_trans.wready; + wlast: coverpoint coverage_trans.wlast; + wdata: coverpoint coverage_trans.wdata; + wstrb: coverpoint coverage_trans.wstrb; + wid: coverpoint coverage_trans.wid; + wuser: coverpoint coverage_trans.wuser; + bwvalid: coverpoint coverage_trans.bwvalid; + bwready: coverpoint coverage_trans.bwready; + bresp: coverpoint coverage_trans.bresp; + bid: coverpoint coverage_trans.bid; + buser: coverpoint coverage_trans.buser; + arvalid: coverpoint coverage_trans.arvalid; + aready: coverpoint coverage_trans.aready; + araddr: coverpoint coverage_trans.araddr; + arsize: coverpoint coverage_trans.arsize; + arburst: coverpoint coverage_trans.arburst; + arcache: coverpoint coverage_trans.arcache; + arprot: coverpoint coverage_trans.arprot; + arid: coverpoint coverage_trans.arid; + arlen: coverpoint coverage_trans.arlen; + arlock: coverpoint coverage_trans.arlock; + arqos: coverpoint coverage_trans.arqos; + aregion: coverpoint coverage_trans.aregion; + aruser: coverpoint coverage_trans.aruser; + rvalid: coverpoint coverage_trans.rvalid; + rready: coverpoint coverage_trans.rready; + rlast: coverpoint coverage_trans.rlast; + rdata: coverpoint coverage_trans.rdata; + rid: coverpoint coverage_trans.rid; + ruser: coverpoint coverage_trans.ruser; + rresp: coverpoint coverage_trans.rresp; + // pragma uvmf custom covergroup end + endgroup + + // **************************************************************************** + // FUNCTION : new() + // This function is the standard SystemVerilog constructor. + // + function new(string name="", uvm_component parent=null); + super.new(name,parent); + axi_s_transaction_cg=new; + `uvm_warning("COVERAGE_MODEL_REVIEW", "A covergroup has been constructed which may need review because of either generation or re-generation with merging. Please note that transaction variables added as a result of re-generation and merging are not automatically added to the covergroup. Remove this warning after the covergroup has been reviewed.") + endfunction + + // **************************************************************************** + // FUNCTION : build_phase() + // This function is the standard UVM build_phase. + // + function void build_phase(uvm_phase phase); + axi_s_transaction_cg.set_inst_name($sformatf("axi_s_transaction_cg_%s",get_full_name())); + endfunction + + // **************************************************************************** + // FUNCTION: write (T t) + // This function is automatically executed when a transaction arrives on the + // analysis_export. It copies values from the variables in the transaction + // to local variables used to collect functional coverage. + // + virtual function void write (T t); + `uvm_info("COV","Received transaction",UVM_HIGH); + coverage_trans = t; + axi_s_transaction_cg.sample(); + endfunction + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + +`endif diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/axi_s_pkg/src/axi_s_typedefs.svh b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/axi_s_pkg/src/axi_s_typedefs.svh new file mode 100644 index 00000000..91e77a1c --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/axi_s_pkg/src/axi_s_typedefs.svh @@ -0,0 +1,21 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: +// This file contains defines and typedefs to be compiled for use in +// the simulation running on the host server when using Veloce. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +`ifndef TYPEDEFS_HVL +`definr TYPEDEFS_HVL + +// pragma uvmf custom additional begin +// pragma uvmf custom additional end +`endif diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/axi_s_pkg/src/axi_s_typedefs_hdl.svh b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/axi_s_pkg/src/axi_s_typedefs_hdl.svh new file mode 100644 index 00000000..bd6b6f41 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/axi_s_pkg/src/axi_s_typedefs_hdl.svh @@ -0,0 +1,23 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: +// This file contains defines and typedefs to be compiled for use in +// the simulation running on the emulator when using Veloce. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// + +`ifndef TYPEDEFS_HVL +`definr TYPEDEFS_HVL + + +// pragma uvmf custom additional begin +// pragma uvmf custom additional end +`endif diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/axi_s_pkg/yaml/axi_s_interface.yaml b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/axi_s_pkg/yaml/axi_s_interface.yaml new file mode 100644 index 00000000..5f0bb407 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/axi_s_pkg/yaml/axi_s_interface.yaml @@ -0,0 +1,481 @@ +uvmf: + interfaces: + axi_s: + clock: axi_clk + config_constraints: [] + config_vars: [] + existing_library_component: 'True' + gen_inbound_streaming_driver: 'False' + hdl_pkg_parameters: [] + hdl_typedefs: [] + hvl_pkg_parameters: [] + hvl_typedefs: [] + parameters: + - name: AW_WIDTH + type: int + value: '32' + - name: LEN + type: int + value: '8' + - name: DATA_WIDTH + type: int + value: '32' + - name: X + type: int + value: '16' + ports: + - dir: input + name: awvalid + reset_value: '''bz' + width: '1' + - dir: output + name: awready + reset_value: '''bz' + width: '1' + - dir: input + name: awaddr + reset_value: '''bz' + width: AW_WIDTH + - dir: input + name: awsize + reset_value: '''bz' + width: '3' + - dir: input + name: awburst + reset_value: '''bz' + width: '2' + - dir: input + name: awcache + reset_value: '''bz' + width: '4' + - dir: input + name: awprot + reset_value: '''bz' + width: '3' + - dir: input + name: awid + reset_value: '''bz' + width: X + - dir: input + name: awlen + reset_value: '''bz' + width: LEN + - dir: input + name: awlock + reset_value: '''bz' + width: '1' + - dir: input + name: awqos + reset_value: '''bz' + width: '4' + - dir: input + name: awregion + reset_value: '''bz' + width: '4' + - dir: input + name: awuser + reset_value: '''bz' + width: X + - dir: input + name: wvalid + reset_value: '''bz' + width: '1' + - dir: output + name: wready + reset_value: '''bz' + width: '1' + - dir: input + name: wlast + reset_value: '''bz' + width: '1' + - dir: input + name: wdata + reset_value: '''bz' + width: DATA_WIDTH + - dir: input + name: wstrb + reset_value: '''bz' + width: DATA_WIDTH/8 + - dir: input + name: wid + reset_value: '''bz' + width: X + - dir: input + name: wuser + reset_value: '''bz' + width: X + - dir: output + name: bwvalid + reset_value: '''bz' + width: '1' + - dir: output + name: bwready + reset_value: '''bz' + width: '1' + - dir: input + name: bresp + reset_value: '''bz' + width: '2' + - dir: output + name: bid + reset_value: '''bz' + width: X + - dir: output + name: buser + reset_value: '''bz' + width: X + - dir: input + name: arvalid + reset_value: '''bz' + width: '1' + - dir: output + name: aready + reset_value: '''bz' + width: '1' + - dir: input + name: araddr + reset_value: '''bz' + width: AW_WIDTH + - dir: input + name: arsize + reset_value: '''bz' + width: '3' + - dir: input + name: arburst + reset_value: '''bz' + width: '2' + - dir: input + name: arcache + reset_value: '''bz' + width: '4' + - dir: input + name: arprot + reset_value: '''bz' + width: '3' + - dir: input + name: arid + reset_value: '''bz' + width: X + - dir: input + name: arlen + reset_value: '''bz' + width: LEN + - dir: input + name: arlock + reset_value: '''bz' + width: '1' + - dir: input + name: arqos + reset_value: '''bz' + width: '4' + - dir: input + name: aregion + reset_value: '''bz' + width: '4' + - dir: input + name: aruser + reset_value: '''bz' + width: X + - dir: output + name: rvalid + reset_value: '''bz' + width: '1' + - dir: input + name: rready + reset_value: '''bz' + width: '1' + - dir: output + name: rlast + reset_value: '''bz' + width: '1' + - dir: output + name: rdata + reset_value: '''bz' + width: DATA_WIDTH + - dir: output + name: rid + reset_value: '''bz' + width: X + - dir: output + name: ruser + reset_value: '''bz' + width: X + - dir: output + name: rresp + reset_value: '''bz' + width: '2' + reset: rst + reset_assertion_level: 'False' + transaction_constraints: [] + transaction_vars: + - comment: '' + iscompare: 'False' + isrand: 'False' + name: awvalid + type: bit + unpacked_dimension: '' + - comment: '' + iscompare: 'False' + isrand: 'False' + name: awready + type: bit + unpacked_dimension: '' + - comment: '' + iscompare: 'False' + isrand: 'False' + name: awaddr + type: bit [AW_WIDTH-1:0] + unpacked_dimension: '' + - comment: '' + iscompare: 'False' + isrand: 'False' + name: awsize + type: bit + unpacked_dimension: '' + - comment: '' + iscompare: 'False' + isrand: 'False' + name: awburst + type: bit + unpacked_dimension: '' + - comment: '' + iscompare: 'False' + isrand: 'False' + name: awcache + type: bit + unpacked_dimension: '' + - comment: '' + iscompare: 'False' + isrand: 'False' + name: awprot + type: bit + unpacked_dimension: '' + - comment: '' + iscompare: 'False' + isrand: 'False' + name: awid + type: bit [X-1:0] + unpacked_dimension: '' + - comment: '' + iscompare: 'False' + isrand: 'False' + name: awlen + type: bit [LEN-1:0] + unpacked_dimension: '' + - comment: '' + iscompare: 'False' + isrand: 'False' + name: awlock + type: bit + unpacked_dimension: '' + - comment: '' + iscompare: 'False' + isrand: 'False' + name: awqos + type: bit + unpacked_dimension: '' + - comment: '' + iscompare: 'False' + isrand: 'False' + name: awregion + type: bit + unpacked_dimension: '' + - comment: '' + iscompare: 'False' + isrand: 'False' + name: awuser + type: bit [X-1:0] + unpacked_dimension: '' + - comment: '' + iscompare: 'False' + isrand: 'False' + name: wvalid + type: bit + unpacked_dimension: '' + - comment: '' + iscompare: 'False' + isrand: 'False' + name: wready + type: bit + unpacked_dimension: '' + - comment: '' + iscompare: 'False' + isrand: 'False' + name: wlast + type: bit + unpacked_dimension: '' + - comment: '' + iscompare: 'False' + isrand: 'False' + name: wdata + type: bit [DATA_WIDTH-1:0] + unpacked_dimension: '' + - comment: '' + iscompare: 'False' + isrand: 'False' + name: wstrb + type: bit [DATA_WIDTH/8-1:0] + unpacked_dimension: '' + - comment: '' + iscompare: 'False' + isrand: 'False' + name: wid + type: bit [X-1:0] + unpacked_dimension: '' + - comment: '' + iscompare: 'False' + isrand: 'False' + name: wuser + type: bit [X-1:0] + unpacked_dimension: '' + - comment: '' + iscompare: 'False' + isrand: 'False' + name: bwvalid + type: bit + unpacked_dimension: '' + - comment: '' + iscompare: 'False' + isrand: 'False' + name: bwready + type: bit + unpacked_dimension: '' + - comment: '' + iscompare: 'False' + isrand: 'True' + name: bresp + type: bit + unpacked_dimension: '' + - comment: '' + iscompare: 'False' + isrand: 'False' + name: bid + type: bit [X-1:0] + unpacked_dimension: '' + - comment: '' + iscompare: 'False' + isrand: 'True' + name: buser + type: bit [X-1:0] + unpacked_dimension: '' + - comment: '' + iscompare: 'False' + isrand: 'False' + name: arvalid + type: bit + unpacked_dimension: '' + - comment: '' + iscompare: 'False' + isrand: 'False' + name: aready + type: bit + unpacked_dimension: '' + - comment: '' + iscompare: 'False' + isrand: 'True' + name: araddr + type: bit [AW_WIDTH-1:0] + unpacked_dimension: '' + - comment: '' + iscompare: 'False' + isrand: 'True' + name: arsize + type: bit + unpacked_dimension: '' + - comment: '' + iscompare: 'False' + isrand: 'True' + name: arburst + type: bit + unpacked_dimension: '' + - comment: '' + iscompare: 'False' + isrand: 'True' + name: arcache + type: bit + unpacked_dimension: '' + - comment: '' + iscompare: 'False' + isrand: 'True' + name: arprot + type: bit + unpacked_dimension: '' + - comment: '' + iscompare: 'False' + isrand: 'True' + name: arid + type: bit [X-1:0] + unpacked_dimension: '' + - comment: '' + iscompare: 'False' + isrand: 'True' + name: arlen + type: bit [LEN-1:0] + unpacked_dimension: '' + - comment: '' + iscompare: 'False' + isrand: 'True' + name: arlock + type: bit + unpacked_dimension: '' + - comment: '' + iscompare: 'False' + isrand: 'True' + name: arqos + type: bit + unpacked_dimension: '' + - comment: '' + iscompare: 'False' + isrand: 'False' + name: aregion + type: bit + unpacked_dimension: '' + - comment: '' + iscompare: 'False' + isrand: 'False' + name: aruser + type: bit [X-1:0] + unpacked_dimension: '' + - comment: '' + iscompare: 'False' + isrand: 'False' + name: rvalid + type: bit + unpacked_dimension: '' + - comment: '' + iscompare: 'False' + isrand: 'False' + name: rready + type: bit + unpacked_dimension: '' + - comment: '' + iscompare: 'False' + isrand: 'False' + name: rlast + type: bit + unpacked_dimension: '' + - comment: '' + iscompare: 'False' + isrand: 'True' + name: rdata + type: bit [DATA_WIDTH-1:0] + unpacked_dimension: '' + - comment: '' + iscompare: 'False' + isrand: 'True' + name: rid + type: bit [X-1:0] + unpacked_dimension: '' + - comment: '' + iscompare: 'False' + isrand: 'True' + name: ruser + type: bit [X-1:0] + unpacked_dimension: '' + - comment: '' + iscompare: 'False' + isrand: 'True' + name: rresp + type: bit + unpacked_dimension: '' + use_dpi_link: 'False' diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/spi_m_pkg/.project b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/spi_m_pkg/.project new file mode 100644 index 00000000..712c4d7d --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/spi_m_pkg/.project @@ -0,0 +1,30 @@ + + + spi_m_pkg + + + + + + org.python.pydev.PyDevBuilder + + + + + net.sf.sveditor.core.SVProjectBuilder + + + + + + net.sf.sveditor.core.SVNature + org.python.pydev.pythonNature + + + + UVMF_VIP_LIBRARY_HOME + $%7BPARENT-2-PROJECT_LOC%7D + + + + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/spi_m_pkg/.svproject b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/spi_m_pkg/.svproject new file mode 100644 index 00000000..df5b00f1 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/spi_m_pkg/.svproject @@ -0,0 +1,16 @@ + + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/spi_m_pkg/Makefile b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/spi_m_pkg/Makefile new file mode 100644 index 00000000..1dd05009 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/spi_m_pkg/Makefile @@ -0,0 +1,66 @@ +# spi_m interface packages source +# pragma uvmf custom additional begin +# pragma uvmf custom additional end + +spi_m_PKG = \ + +incdir+$(UVMF_VIP_LIBRARY_HOME)/interface_packages/spi_m_pkg \ + -F $(UVMF_VIP_LIBRARY_HOME)/interface_packages/spi_m_pkg/spi_m_filelist_hvl.f + +spi_m_PKG_HDL = \ + +incdir+$(UVMF_VIP_LIBRARY_HOME)/interface_packages/spi_m_pkg \ + -F $(UVMF_VIP_LIBRARY_HOME)/interface_packages/spi_m_pkg/spi_m_filelist_hdl.f + +spi_m_PKG_XRTL = \ + +incdir+$(UVMF_VIP_LIBRARY_HOME)/interface_packages/spi_m_pkg \ + -F $(UVMF_VIP_LIBRARY_HOME)/interface_packages/spi_m_pkg/spi_m_filelist_xrtl.f + +COMP_spi_m_PKG_TGT_0 = q_comp_spi_m_pkg +COMP_spi_m_PKG_TGT_1 = v_comp_spi_m_pkg +COMP_spi_m_PKG_TGT = $(COMP_spi_m_PKG_TGT_$(USE_VELOCE)) + +comp_spi_m_pkg: $(COMP_spi_m_PKG_TGT) + +q_comp_spi_m_pkg: + $(HDL_COMP_CMD) $(spi_m_PKG_HDL) + $(HVL_COMP_CMD) $(spi_m_PKG) + $(HDL_COMP_CMD) $(spi_m_PKG_XRTL) + +v_comp_spi_m_pkg: + $(HVL_COMP_CMD) $(spi_m_PKG_HDL) + $(HVL_COMP_CMD) $(spi_m_PKG) + $(VELANALYZE_CMD) $(spi_m_PKG_HDL) + $(VELANALYZE_HVL_CMD) $(spi_m_PKG) + $(HDL_COMP_CMD) $(spi_m_PKG_XRTL) + +ifeq ($(MTI_VCO_MODE),64) + GCC_COMP_ARCH = -m64 +else + GCC_COMP_ARCH = -m32 +endif + +export spi_m_IF_DPI_SRC ?= $(UVMF_VIP_LIBRARY_HOME)/interface_packages/spi_m_pkg/dpi + +C_FILE_COMPILE_LIST_spi_m_pkg = \ + +O_FILE_COMPILE_LIST_spi_m_pkg = $(notdir $(C_FILE_COMPILE_LIST_spi_m_pkg:.c=.o)) + +GCC_COMP_ARGS_spi_m_pkg += -I$(spi_m_IF_DPI_SRC) \ + -fPIC + +GCC_COMP_ARGS_spi_m_pkg += $(spi_m_IF_GCC_COMP_ARGUMENTS) + +GCC_LINK_ARGS_spi_m_pkg += \ + \ + -o .so + +comp_spi_m_pkg_c_files: + @echo "--------------------------------" + @echo "Compiling Interface C source" + @echo "--------------------------------" + gcc $(GCC_COMP_ARCH) $(GCC_COMP_ARGS_spi_m_pkg) $(C_FILE_COMPILE_LIST_spi_m_pkg) + @echo "--------------------------------" + @echo "Linking Interface C objects into a shared object" + @echo "--------------------------------" + gcc $(GCC_COMP_ARCH) $(GCC_LINK_ARGS_spi_m_pkg) $(O_FILE_COMPILE_LIST_spi_m_pkg) + @echo "--------------------------------" + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/spi_m_pkg/compile.do b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/spi_m_pkg/compile.do new file mode 100644 index 00000000..13f6b813 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/spi_m_pkg/compile.do @@ -0,0 +1,14 @@ +# Tcl do file for compile of spi_m interface + +# pragma uvmf custom additional begin +# pragma uvmf custom additional end + + +vlog -sv -timescale 1ps/1ps -suppress 2223,2286 +incdir+$env(UVMF_VIP_LIBRARY_HOME)/interface_packages/spi_m_pkg \ + -F $env(UVMF_VIP_LIBRARY_HOME)/interface_packages/spi_m_pkg/spi_m_filelist_hdl.f + +vlog -sv -timescale 1ps/1ps -suppress 2223,2286 +incdir+$env(UVMF_VIP_LIBRARY_HOME)/interface_packages/spi_m_pkg \ + -F $env(UVMF_VIP_LIBRARY_HOME)/interface_packages/spi_m_pkg/spi_m_filelist_hvl.f + +vlog -sv -timescale 1ps/1ps -suppress 2223,2286 +incdir+$env(UVMF_VIP_LIBRARY_HOME)/interface_packages/spi_m_pkg \ + -F $env(UVMF_VIP_LIBRARY_HOME)/interface_packages/spi_m_pkg/spi_m_filelist_xrtl.f \ No newline at end of file diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/spi_m_pkg/spi_m.compile b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/spi_m_pkg/spi_m.compile new file mode 100644 index 00000000..6cfb1a16 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/spi_m_pkg/spi_m.compile @@ -0,0 +1,3 @@ +needs: + - spi_m_hvl.compile + - spi_m_hdl.compile diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/spi_m_pkg/spi_m_bfm.vinfo b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/spi_m_pkg/spi_m_bfm.vinfo new file mode 100644 index 00000000..054f46b2 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/spi_m_pkg/spi_m_bfm.vinfo @@ -0,0 +1,6 @@ +@use $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg_hdl.vinfo +@use spi_m_pkg_hdl.vinfo ++incdir+@vinfodir +src/spi_m_if.sv +src/spi_m_driver_bfm.sv +src/spi_m_monitor_bfm.sv diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/spi_m_pkg/spi_m_common.compile b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/spi_m_pkg/spi_m_common.compile new file mode 100644 index 00000000..31a2c1bc --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/spi_m_pkg/spi_m_common.compile @@ -0,0 +1,7 @@ +needs: + - $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg_hdl.compile +incdir: + - . + - ${uvm_path}/src +src: + - spi_m_pkg_hdl.sv diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/spi_m_pkg/spi_m_filelist_hdl.f b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/spi_m_pkg/spi_m_filelist_hdl.f new file mode 100644 index 00000000..952ce3e3 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/spi_m_pkg/spi_m_filelist_hdl.f @@ -0,0 +1 @@ +$UVMF_VIP_LIBRARY_HOME/interface_packages/spi_m_pkg/spi_m_pkg_hdl.sv diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/spi_m_pkg/spi_m_filelist_hvl.f b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/spi_m_pkg/spi_m_filelist_hvl.f new file mode 100644 index 00000000..f7b45778 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/spi_m_pkg/spi_m_filelist_hvl.f @@ -0,0 +1 @@ +$UVMF_VIP_LIBRARY_HOME/interface_packages/spi_m_pkg/spi_m_pkg.sv \ No newline at end of file diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/spi_m_pkg/spi_m_filelist_xrtl.f b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/spi_m_pkg/spi_m_filelist_xrtl.f new file mode 100644 index 00000000..996b7bf9 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/spi_m_pkg/spi_m_filelist_xrtl.f @@ -0,0 +1,3 @@ +$UVMF_VIP_LIBRARY_HOME/interface_packages/spi_m_pkg/src/spi_m_if.sv +$UVMF_VIP_LIBRARY_HOME/interface_packages/spi_m_pkg/src/spi_m_monitor_bfm.sv +$UVMF_VIP_LIBRARY_HOME/interface_packages/spi_m_pkg/src/spi_m_driver_bfm.sv diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/spi_m_pkg/spi_m_hdl.compile b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/spi_m_pkg/spi_m_hdl.compile new file mode 100644 index 00000000..e0606ef0 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/spi_m_pkg/spi_m_hdl.compile @@ -0,0 +1,9 @@ +needs: + - $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg_hdl.compile + - ./spi_m_common.compile +incdir: + - . +src: + - src/spi_m_if.sv + - src/spi_m_monitor_bfm.sv + - src/spi_m_driver_bfm.sv diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/spi_m_pkg/spi_m_hvl.compile b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/spi_m_pkg/spi_m_hvl.compile new file mode 100644 index 00000000..ef56d81f --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/spi_m_pkg/spi_m_hvl.compile @@ -0,0 +1,7 @@ +needs: + - $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg.compile + - ./spi_m_common.compile +incdir: + - . +src: + - spi_m_pkg.sv diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/spi_m_pkg/spi_m_pkg.sv b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/spi_m_pkg/spi_m_pkg.sv new file mode 100644 index 00000000..454cc83e --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/spi_m_pkg/spi_m_pkg.sv @@ -0,0 +1,79 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// PACKAGE: This file defines all of the files contained in the +// interface package that will run on the host simulator. +// +// CONTAINS: +// - +// - +// - + +// - +// - +// - + +// - +// - +// - + +// - +// - +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +`ifndef SPI_M_PKG +`define SPI_M_PKG +package spi_m_pkg; + + import uvm_pkg::*; + import uvmf_base_pkg_hdl::*; + import uvmf_base_pkg::*; + import spi_m_pkg_hdl::*; + + `include "uvm_macros.svh" + + // pragma uvmf custom package_imports_additional begin + // pragma uvmf custom package_imports_additional end + `include "src/spi_m_macros.svh" + + export spi_m_pkg_hdl::*; + + + + // Parameters defined as HVL parameters + + `include "src/spi_m_typedefs.svh" + `include "src/spi_m_transaction.svh" + + `include "src/spi_m_configuration.svh" + `include "src/spi_m_driver.svh" + `include "src/spi_m_monitor.svh" + + `include "src/spi_m_transaction_coverage.svh" + `include "src/spi_m_sequence_base.svh" + `include "src/spi_m_random_sequence.svh" + + `include "src/spi_m_responder_sequence.svh" + `include "src/spi_m2reg_adapter.svh" + + `include "src/spi_m_agent.svh" + + // pragma uvmf custom package_item_additional begin + // UVMF_CHANGE_ME : When adding new interface sequences to the src directory + // be sure to add the sequence file here so that it will be + // compiled as part of the interface package. Be sure to place + // the new sequence after any base sequences of the new sequence. + // pragma uvmf custom package_item_additional end + +endpackage + +// pragma uvmf custom external begin +// pragma uvmf custom external end +`endif diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/spi_m_pkg/spi_m_pkg.vinfo b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/spi_m_pkg/spi_m_pkg.vinfo new file mode 100644 index 00000000..a05007a1 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/spi_m_pkg/spi_m_pkg.vinfo @@ -0,0 +1,4 @@ +@use $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg.vinfo +@use spi_m_pkg_hdl.vinfo ++incdir+@vinfodir +spi_m_pkg.sv diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/spi_m_pkg/spi_m_pkg_hdl.sv b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/spi_m_pkg/spi_m_pkg_hdl.sv new file mode 100644 index 00000000..070a6bd8 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/spi_m_pkg/spi_m_pkg_hdl.sv @@ -0,0 +1,40 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// PACKAGE: This file defines all of the files contained in the +// interface package that needs to be compiled and synthesized +// for running on Veloce. +// +// CONTAINS: +// - +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +`ifndef SPI_M_PKG_HDL +`define SPI_M_PKG_HDL +package spi_m_pkg_hdl; + + import uvmf_base_pkg_hdl::*; + + // pragma uvmf custom package_imports_additional begin + // pragma uvmf custom package_imports_additional end + + // Parameters defined as HDL parameters + + `include "src/spi_m_typedefs_hdl.svh" + `include "src/spi_m_macros.svh" + + // pragma uvmf custom package_item_additional begin + // pragma uvmf custom package_item_additional end + +endpackage + +// pragma uvmf custom external begin +// pragma uvmf custom external end +`endif diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/spi_m_pkg/spi_m_pkg_hdl.vinfo b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/spi_m_pkg/spi_m_pkg_hdl.vinfo new file mode 100644 index 00000000..ed83921b --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/spi_m_pkg/spi_m_pkg_hdl.vinfo @@ -0,0 +1,2 @@ +@use $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg_hdl.vinfo +spi_m_pkg_hdl.sv diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/spi_m_pkg/spi_m_pkg_sve.F b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/spi_m_pkg/spi_m_pkg_sve.F new file mode 100644 index 00000000..b48ecf8c --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/spi_m_pkg/spi_m_pkg_sve.F @@ -0,0 +1,10 @@ +// UVM ++incdir+${UVM_HOME}/src +${UVM_HOME}/src/uvm_pkg.sv + +// Common UVMF files +-f ${UVMF_HOME}/common/common_sve.f + ++incdir+. +-f ${UVMF_VIP_LIBRARY_HOME}/interface_packages/spi_m_pkg/spi_m_filelist_hdl.f +-f ${UVMF_VIP_LIBRARY_HOME}/interface_packages/spi_m_pkg/spi_m_filelist_hvl.f diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/spi_m_pkg/src/spi_m2reg_adapter.svh b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/spi_m_pkg/src/spi_m2reg_adapter.svh new file mode 100644 index 00000000..602a15c9 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/spi_m_pkg/src/spi_m2reg_adapter.svh @@ -0,0 +1,100 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: +// This file contains the UVM register adapter for the spi_m interface. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +`ifndef SPI_M2REG_ADAPTER +`define SPI_M2REG_ADAPTER +class spi_m2reg_adapter extends uvm_reg_adapter; + + `uvm_object_utils( spi_m2reg_adapter ) + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + //-------------------------------------------------------------------- + // new + //-------------------------------------------------------------------- + function new (string name = "spi_m2reg_adapter" ); + super.new(name); + // pragma uvmf custom new begin + // UVMF_CHANGE_ME : Configure the adapter regarding byte enables and provides response. + + // Does the protocol the Agent is modeling support byte enables? + // 0 = NO + // 1 = YES + supports_byte_enable = 0; + + // Does the Agent's Driver provide separate response sequence items? + // i.e. Does the driver call seq_item_port.put() + // and do the sequences call get_response()? + // 0 = NO + // 1 = YES + provides_responses = 0; + // pragma uvmf custom new end + + endfunction: new + + //-------------------------------------------------------------------- + // reg2bus + //-------------------------------------------------------------------- + virtual function uvm_sequence_item reg2bus(const ref uvm_reg_bus_op rw); + + spi_m_transaction trans_h = spi_m_transaction ::type_id::create("trans_h"); + + // pragma uvmf custom reg2bus begin + // UVMF_CHANGE_ME : Fill in the reg2bus adapter mapping registe fields to protocol fields. + + //Adapt the following for your sequence item type + // trans_h.op = (rw.kind == UVM_READ) ? WB_READ : WB_WRITE; + //Copy over address + // trans_h.addr = rw.addr; + //Copy over write data + // trans_h.data = rw.data; + + // pragma uvmf custom reg2bus end + + // Return the adapted transaction + return trans_h; + + endfunction: reg2bus + + //-------------------------------------------------------------------- + // bus2reg + //-------------------------------------------------------------------- + virtual function void bus2reg(uvm_sequence_item bus_item, + ref uvm_reg_bus_op rw); + spi_m_transaction trans_h; + if (!$cast(trans_h, bus_item)) begin + `uvm_fatal("ADAPT","Provided bus_item is not of the correct type") + return; + end + // pragma uvmf custom bus2reg begin + // UVMF_CHANGE_ME : Fill in the bus2reg adapter mapping protocol fields to register fields. + //Adapt the following for your sequence item type + //Copy over instruction type + // rw.kind = (trans_h.op == WB_WRITE) ? UVM_WRITE : UVM_READ; + //Copy over address + // rw.addr = trans_h.addr; + //Copy over read data + // rw.data = trans_h.data; + //Check for errors on the bus and return UVM_NOT_OK if there is an error + // rw.status = UVM_IS_OK; + // pragma uvmf custom bus2reg end + + endfunction: bus2reg + +endclass : spi_m2reg_adapter + +// pragma uvmf custom external begin +// pragma uvmf custom external end +`endif diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/spi_m_pkg/src/spi_m_agent.svh b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/spi_m_pkg/src/spi_m_agent.svh new file mode 100644 index 00000000..44470f7f --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/spi_m_pkg/src/spi_m_agent.svh @@ -0,0 +1,58 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: Protocol specific agent class definition +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// + +`ifndef SPI_M_AGENT +`define SPI_M_AGENT + +class spi_m_agent extends uvmf_parameterized_agent #( + .CONFIG_T(spi_m_configuration ), + .DRIVER_T(spi_m_driver ), + .MONITOR_T(spi_m_monitor ), + .COVERAGE_T(spi_m_transaction_coverage ), + .TRANS_T(spi_m_transaction ) + ); + + `uvm_component_utils( spi_m_agent ) + +// pragma uvmf custom class_item_additional begin +// pragma uvmf custom class_item_additional end + +// **************************************************************************** +// FUNCTION : new() +// This function is the standard SystemVerilog constructor. +// + function new( string name = "", uvm_component parent = null ); + super.new( name, parent ); + endfunction + +// **************************************************************************** + // FUNCTION: build_phase + virtual function void build_phase(uvm_phase phase); +// pragma uvmf custom build_phase_pre_super begin +// pragma uvmf custom build_phase_pre_super end + super.build_phase(phase); + if (configuration.active_passive == ACTIVE) begin + // Place sequencer handle into configuration object + // so that it may be retrieved from configuration + // rather than using uvm_config_db + configuration.sequencer = this.sequencer; + end + endfunction + +endclass + + +// pragma uvmf custom external begin +// pragma uvmf custom external end +`endif diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/spi_m_pkg/src/spi_m_configuration.svh b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/spi_m_pkg/src/spi_m_configuration.svh new file mode 100644 index 00000000..2b6623e1 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/spi_m_pkg/src/spi_m_configuration.svh @@ -0,0 +1,182 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This class contains all variables and functions used +// to configure the spi_m agent and its bfm's. It gets the +// bfm's from the uvm_config_db for use by the agent. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// + +`ifndef SPI_M_CONFIGURATION +`define SPI_M_CONFIGURATION +class spi_m_configuration extends uvmf_parameterized_agent_configuration_base #( + .DRIVER_BFM_BIND_T(virtual spi_m_driver_bfm ), + .MONITOR_BFM_BIND_T( virtual spi_m_monitor_bfm )); + + `uvm_object_utils( spi_m_configuration ) + + + // Sequencer handle populated by agent + uvm_sequencer #(spi_m_transaction ) sequencer; + + //Constraints for the configuration variables: + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + covergroup spi_m_configuration_cg; + // pragma uvmf custom covergroup begin + option.auto_bin_max=1024; + // pragma uvmf custom covergroup end + endgroup + + //******************************************************************* + //******************************************************************* + // Structure used to pass configuration variables to monitor and driver BFM's. + // Use to_struct function to pack variables into structure. + // Use from_struct function to unpack variables from structure. + // This structure is defined in spi_m_macros.svh + `spi_m_CONFIGURATION_STRUCT + spi_m_configuration_s spi_m_configuration_struct; + //******************************************************************* + // FUNCTION: to_struct() + // This function packs variables into a spi_m_configuration_s + // structure. The function returns the handle to the spi_m_configuration_struct. + // This function is defined in spi_m_macros.svh + `spi_m_CONFIGURATION_TO_STRUCT_FUNCTION + //******************************************************************* + // FUNCTION: from_struct() + // This function unpacks the struct provided as an argument into + // variables of this class. + // This function is defined in spi_m_macros.svh + `spi_m_CONFIGURATION_FROM_STRUCT_FUNCTION + + // **************************************************************************** + // FUNCTION : new() + // This function is the standard SystemVerilog constructor. + // + function new( string name = "" ); + super.new( name ); + // Construct the covergroup for this configuration class + spi_m_configuration_cg = new; + endfunction + + // **************************************************************************** + // FUNCTION: post_randomize() + // This function is automatically called after the randomize() function + // is executed. + // + function void post_randomize(); + super.post_randomize(); + spi_m_configuration_cg.sample(); + endfunction + + // **************************************************************************** + // FUNCTION: initialize + // This function causes the configuration to retrieve + // its virtual interface handle from the uvm_config_db. + // This function also makes itself available to its + // agent through the uvm_config_db. + // + // ARGUMENTS: + // uvmf_active_passive_t activity: + // This argument identifies the simulation level + // as either BLOCK, CHIP, SIMULATION, etc. + // + // AGENT_PATH: + // This argument identifies the path to this + // configurations agent. This configuration + // makes itself available to the agent specified + // by agent_path by placing itself into the + // uvm_config_db. + // + // INTERFACE_NAME: + // This argument identifies the string name of + // this configurations BFM's. This string + // name is used to retrieve the driver and + // monitor BFM from the uvm_config_db. + // + virtual function void initialize(uvmf_active_passive_t activity, + string agent_path, + string interface_name); + + super.initialize( activity, agent_path, interface_name); + // The covergroup is given the same name as the interface + spi_m_configuration_cg.set_inst_name(interface_name); + + // This configuration places itself into the uvm_config_db for the agent, identified by the agent_path variable, to retrieve. + uvm_config_db #( spi_m_configuration + )::set( null ,agent_path,UVMF_AGENT_CONFIG, this ); + + // This configuration also places itself in the config db using the same identifier used by the interface. This allows users to access + // configuration variables and the interface through the bfm api class rather than directly accessing the BFM. This is useful for + // accessingthe BFM when using Veloce + uvm_config_db #( spi_m_configuration + )::set( null ,UVMF_CONFIGURATIONS, interface_name, this ); + + spi_m_configuration_cg.set_inst_name($sformatf("spi_m_configuration_cg_%s",get_full_name())); + +// This code is to aid in debugging parameter mismatches between the BFM and its corresponding agent. +// Enable this debug by setting UVM_VERBOSITY to UVM_DEBUG +// Setting UVM_VERBOSITY to UVM_DEBUG causes all BFM's and all agents to display their parameter settings. +// All of the messages from this feature have a UVM messaging id value of "CFG" +// The transcript or run.log can be parsed to ensure BFM parameter settings match its corresponding agents parameter settings. + `uvm_info("CFG", + $psprintf("The agent at '%s' is using interface named %s has the following parameters: ", agent_path, interface_name, ), + UVM_DEBUG) + + // pragma uvmf custom initialize begin + // This controls whether or not the agent returns a transaction handle in the driver when calling + // item_done() back into the sequencer or not. If set to 1, a transaction is sent back which means + // the sequence on the other end must use the get_response() part of the driver/sequence API. If + // this doesn't occur, there will eventually be response_queue overflow errors during the test. + return_transaction_response = 1'b0; + + // pragma uvmf custom initialize end + + endfunction + + // **************************************************************************** + // TASK: wait_for_reset + // *[Required]* Blocks until reset is released. The wait_for_reset operation is performed + // by a task in the monitor bfm. + virtual task wait_for_reset(); + monitor_bfm.wait_for_reset(); + endtask + + // **************************************************************************** + // TASK: wait_for_num_clocks + // *[Required]* Blocks until specified number of clocks have elapsed. The wait_for_num_clocks + // operation is performed by a task in the monitor bfm. + virtual task wait_for_num_clocks(int clocks); + monitor_bfm.wait_for_num_clocks(clocks); + endtask + + // **************************************************************************** + // FUNCTION : convert2string() + // This function is used to convert variables in this class into a string for log messaging. + // + virtual function string convert2string (); + // pragma uvmf custom convert2string begin + return $sformatf(""); + // pragma uvmf custom convert2string end + endfunction + + // **************************************************************************** + // FUNCTION: get_sequencer + function uvm_sequencer #(spi_m_transaction) get_sequencer(); + return sequencer; + endfunction + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end +`endif diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/spi_m_pkg/src/spi_m_driver.svh b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/spi_m_pkg/src/spi_m_driver.svh new file mode 100644 index 00000000..5d75d3b7 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/spi_m_pkg/src/spi_m_driver.svh @@ -0,0 +1,93 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This class passes transactions between the sequencer +// and the BFM driver interface. It accesses the driver BFM +// through the bfm handle. This driver +// passes transactions to the driver BFM through the access +// task. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +`ifndef SPI_M_DRIVER +`define SPI_M_DRIVER +class spi_m_driver extends uvmf_driver_base #( + .CONFIG_T(spi_m_configuration ), + .BFM_BIND_T(virtual spi_m_driver_bfm ), + .REQ(spi_m_transaction ), + .RSP(spi_m_transaction )); + + `uvm_component_utils( spi_m_driver ) +//******************************************************************* +// Macros that define structs located in spi_m_macros.svh +//******************************************************************* +// Initiator macro used by spi_m_driver and spi_m_driver_bfm +// to communicate initiator driven data to spi_m_driver_bfm. +`spi_m_INITIATOR_STRUCT + spi_m_initiator_s spi_m_initiator_struct; +//******************************************************************* +// Responder macro used by spi_m_driver and spi_m_driver_bfm +// to communicate Responder driven data to spi_m_driver_bfm. +`spi_m_RESPONDER_STRUCT + spi_m_responder_s spi_m_responder_struct; + +// pragma uvmf custom class_item_additional begin +// pragma uvmf custom class_item_additional end + +// **************************************************************************** +// This function is the standard SystemVerilog constructor. +// + function new( string name = "", uvm_component parent=null ); + super.new( name, parent ); + endfunction + +// **************************************************************************** +// This function sends configuration object variables to the driver BFM +// using the configuration struct. +// + virtual function void configure(input CONFIG_T cfg); + bfm.configure( cfg.to_struct() ); + endfunction + +// **************************************************************************** +// This function places a handle to this class in the proxy variable in the +// driver BFM. This allows the driver BFM to call tasks and function within this class. +// + virtual function void set_bfm_proxy_handle(); + bfm.proxy = this; endfunction + +// **************************************************************************** +// This task is called by the run_phase in uvmf_driver_base. + virtual task access( inout REQ txn ); +// pragma uvmf custom access begin + if (configuration.initiator_responder==RESPONDER) begin + // Complete current transfer and wait for next transfer + bfm.respond_and_wait_for_next_transfer( + spi_m_initiator_struct, + txn.to_responder_struct() + ); + // Unpack information about initiated transfer received by this responder + txn.from_initiator_struct(spi_m_initiator_struct); + end else begin + // Initiate a transfer and get response + bfm.initiate_and_get_response( + txn.to_initiator_struct(), + spi_m_responder_struct + ); + // Unpack transfer response information received by this initiator + txn.from_responder_struct(spi_m_responder_struct); + end +// pragma uvmf custom access end + endtask + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end +`endif diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/spi_m_pkg/src/spi_m_driver_bfm.sv b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/spi_m_pkg/src/spi_m_driver_bfm.sv new file mode 100644 index 00000000..2fb0a5c4 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/spi_m_pkg/src/spi_m_driver_bfm.sv @@ -0,0 +1,300 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: +// This interface performs the spi_m signal driving. It is +// accessed by the uvm spi_m driver through a virtual interface +// handle in the spi_m configuration. It drives the singals passed +// in through the port connection named bus of type spi_m_if. +// +// Input signals from the spi_m_if are assigned to an internal input +// signal with a _i suffix. The _i signal should be used for sampling. +// +// The input signal connections are as follows: +// bus.signal -> signal_i +// +// This bfm drives signals with a _o suffix. These signals +// are driven onto signals within spi_m_if based on INITIATOR/RESPONDER and/or +// ARBITRATION/GRANT status. +// +// The output signal connections are as follows: +// signal_o -> bus.signal +// +// +// Interface functions and tasks used by UVM components: +// +// configure: +// This function gets configuration attributes from the +// UVM driver to set any required BFM configuration +// variables such as 'initiator_responder'. +// +// initiate_and_get_response: +// This task is used to perform signaling activity for initiating +// a protocol transfer. The task initiates the transfer, using +// input data from the initiator struct. Then the task captures +// response data, placing the data into the response struct. +// The response struct is returned to the driver class. +// +// respond_and_wait_for_next_transfer: +// This task is used to complete a current transfer as a responder +// and then wait for the initiator to start the next transfer. +// The task uses data in the responder struct to drive protocol +// signals to complete the transfer. The task then waits for +// the next transfer. Once the next transfer begins, data from +// the initiator is placed into the initiator struct and sent +// to the responder sequence for processing to determine +// what data to respond with. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +import uvmf_base_pkg_hdl::*; +import spi_m_pkg_hdl::*; +`include "src/spi_m_macros.svh" + +interface spi_m_driver_bfm + (spi_m_if bus); + // The following pragma and additional ones in-lined further below are for running this BFM on Veloce + // pragma attribute spi_m_driver_bfm partition_interface_xif + +`ifndef XRTL +// This code is to aid in debugging parameter mismatches between the BFM and its corresponding agent. +// Enable this debug by setting UVM_VERBOSITY to UVM_DEBUG +// Setting UVM_VERBOSITY to UVM_DEBUG causes all BFM's and all agents to display their parameter settings. +// All of the messages from this feature have a UVM messaging id value of "CFG" +// The transcript or run.log can be parsed to ensure BFM parameter settings match its corresponding agents parameter settings. +import uvm_pkg::*; +`include "uvm_macros.svh" +initial begin : bfm_vs_agent_parameter_debug + `uvm_info("CFG", + $psprintf("The BFM at '%m' has the following parameters: ", ), + UVM_DEBUG) +end +`endif + + // Config value to determine if this is an initiator or a responder + uvmf_initiator_responder_t initiator_responder; + // Custom configuration variables. + // These are set using the configure function which is called during the UVM connect_phase + + logic sck_i; + logic rst_i; + + // Signal list (all signals are capable of being inputs and outputs for the sake + // of supporting both INITIATOR and RESPONDER mode operation. Expectation is that + // directionality in the config file was from the point-of-view of the INITIATOR + + // INITIATOR mode input signals + tri [7:0] miso_i; + reg [7:0] miso_o = 'b0; + + // INITIATOR mode output signals + tri sclk_i; + reg sclk_o = 'b0; + tri ss_i; + reg ss_o = 'b0; + tri [7:0] mosi_i; + reg [7:0] mosi_o = 'b0; + + // Bi-directional signals + + + assign sck_i = bus.sck; + assign rst_i = bus.rst; + + // These are signals marked as 'input' by the config file, but the signals will be + // driven by this BFM if put into RESPONDER mode (flipping all signal directions around) + assign miso_i = bus.miso; + assign bus.miso = (initiator_responder == RESPONDER) ? miso_o : 'bz; + + + // These are signals marked as 'output' by the config file, but the outputs will + // not be driven by this BFM unless placed in INITIATOR mode. + assign bus.sclk = (initiator_responder == INITIATOR) ? sclk_o : 'bz; + assign sclk_i = bus.sclk; + assign bus.ss = (initiator_responder == INITIATOR) ? ss_o : 'bz; + assign ss_i = bus.ss; + assign bus.mosi = (initiator_responder == INITIATOR) ? mosi_o : 'bz; + assign mosi_i = bus.mosi; + + // Proxy handle to UVM driver + spi_m_pkg::spi_m_driver proxy; + // pragma tbx oneway proxy.my_function_name_in_uvm_driver + + // **************************************************************************** + // **************************************************************************** + // Macros that define structs located in spi_m_macros.svh + // **************************************************************************** + // Struct for passing configuration data from spi_m_driver to this BFM + // **************************************************************************** + `spi_m_CONFIGURATION_STRUCT + // **************************************************************************** + // Structs for INITIATOR and RESPONDER data flow + //******************************************************************* + // Initiator macro used by spi_m_driver and spi_m_driver_bfm + // to communicate initiator driven data to spi_m_driver_bfm. + `spi_m_INITIATOR_STRUCT + spi_m_initiator_s initiator_struct; + // Responder macro used by spi_m_driver and spi_m_driver_bfm + // to communicate Responder driven data to spi_m_driver_bfm. + `spi_m_RESPONDER_STRUCT + spi_m_responder_s responder_struct; + + // **************************************************************************** +// pragma uvmf custom reset_condition_and_response begin + // Always block used to return signals to reset value upon assertion of reset + always @( posedge rst_i ) + begin + // RESPONDER mode output signals + miso_o <= 'b0; + // INITIATOR mode output signals + sclk_o <= 'b0; + ss_o <= 'b0; + mosi_o <= 'b0; + // Bi-directional signals + + end +// pragma uvmf custom reset_condition_and_response end + + // pragma uvmf custom interface_item_additional begin + // pragma uvmf custom interface_item_additional end + + //****************************************************************** + // The configure() function is used to pass agent configuration + // variables to the driver BFM. It is called by the driver within + // the agent at the beginning of the simulation. It may be called + // during the simulation if agent configuration variables are updated + // and the driver BFM needs to be aware of the new configuration + // variables. + // + + function void configure(spi_m_configuration_s spi_m_configuration_arg); // pragma tbx xtf + initiator_responder = spi_m_configuration_arg.initiator_responder; + // pragma uvmf custom configure begin + // pragma uvmf custom configure end + endfunction + +// pragma uvmf custom initiate_and_get_response begin +// **************************************************************************** +// UVMF_CHANGE_ME +// This task is used by an initator. The task first initiates a transfer then +// waits for the responder to complete the transfer. + task initiate_and_get_response( + // This argument passes transaction variables used by an initiator + // to perform the initial part of a protocol transfer. The values + // come from a sequence item created in a sequence. + input spi_m_initiator_s spi_m_initiator_struct, + // This argument is used to send data received from the responder + // back to the sequence item. The sequence item is returned to the sequence. + output spi_m_responder_s spi_m_responder_struct + );// pragma tbx xtf + // + // Members within the spi_m_initiator_struct: + // bit ssel ; + // bit [7:0] mosi ; + // bit [7:0] miso ; + // Members within the spi_m_responder_struct: + // bit ssel ; + // bit [7:0] mosi ; + // bit [7:0] miso ; + initiator_struct = spi_m_initiator_struct; + // + // Reference code; + // How to wait for signal value + // while (control_signal == 1'b1) @(posedge sck_i); + // + // How to assign a responder struct member, named xyz, from a signal. + // All available initiator input and inout signals listed. + // Initiator input signals + // spi_m_responder_struct.xyz = miso_i; // [7:0] + // Initiator inout signals + // How to assign a signal from an initiator struct member named xyz. + // All available initiator output and inout signals listed. + // Notice the _o. Those are storage variables that allow for procedural assignment. + // Initiator output signals + // sclk_o <= spi_m_initiator_struct.xyz; // + // ss_o <= spi_m_initiator_struct.xyz; // + // mosi_o <= spi_m_initiator_struct.xyz; // [7:0] + // Initiator inout signals + // Initiate a transfer using the data received. + @(posedge sck_i); + @(posedge sck_i); + // Wait for the responder to complete the transfer then place the responder data into + // spi_m_responder_struct. + @(posedge sck_i); + @(posedge sck_i); + responder_struct = spi_m_responder_struct; + endtask +// pragma uvmf custom initiate_and_get_response end + +// pragma uvmf custom respond_and_wait_for_next_transfer begin +// **************************************************************************** +// The first_transfer variable is used to prevent completing a transfer in the +// first call to this task. For the first call to this task, there is not +// current transfer to complete. +bit first_transfer=1; + +// UVMF_CHANGE_ME +// This task is used by a responder. The task first completes the current +// transfer in progress then waits for the initiator to start the next transfer. + task respond_and_wait_for_next_transfer( + // This argument is used to send data received from the initiator + // back to the sequence item. The sequence determines how to respond. + output spi_m_initiator_s spi_m_initiator_struct, + // This argument passes transaction variables used by a responder + // to complete a protocol transfer. The values come from a sequence item. + input spi_m_responder_s spi_m_responder_struct + );// pragma tbx xtf + // Variables within the spi_m_initiator_struct: + // bit ssel ; + // bit [7:0] mosi ; + // bit [7:0] miso ; + // Variables within the spi_m_responder_struct: + // bit ssel ; + // bit [7:0] mosi ; + // bit [7:0] miso ; + // Reference code; + // How to wait for signal value + // while (control_signal == 1'b1) @(posedge sck_i); + // + // How to assign a responder struct member, named xyz, from a signal. + // All available responder input and inout signals listed. + // Responder input signals + // spi_m_responder_struct.xyz = sclk_i; // + // spi_m_responder_struct.xyz = ss_i; // + // spi_m_responder_struct.xyz = mosi_i; // [7:0] + // Responder inout signals + // How to assign a signal, named xyz, from an initiator struct member. + // All available responder output and inout signals listed. + // Notice the _o. Those are storage variables that allow for procedural assignment. + // Responder output signals + // miso_o <= spi_m_initiator_struct.xyz; // [7:0] + // Responder inout signals + + @(posedge sck_i); + if (!first_transfer) begin + // Perform transfer response here. + // Reply using data recieved in the spi_m_responder_struct. + @(posedge sck_i); + // Reply using data recieved in the transaction handle. + @(posedge sck_i); + end + // Wait for next transfer then gather info from intiator about the transfer. + // Place the data into the spi_m_initiator_struct. + @(posedge sck_i); + @(posedge sck_i); + first_transfer = 0; + endtask +// pragma uvmf custom respond_and_wait_for_next_transfer end + + +endinterface + +// pragma uvmf custom external begin +// pragma uvmf custom external end +`endif diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/spi_m_pkg/src/spi_m_if.sv b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/spi_m_pkg/src/spi_m_if.sv new file mode 100644 index 00000000..97330675 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/spi_m_pkg/src/spi_m_if.sv @@ -0,0 +1,81 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This interface contains the spi_m interface signals. +// It is instantiated once per spi_m bus. Bus Functional Models, +// BFM's named spi_m_driver_bfm, are used to drive signals on the bus. +// BFM's named spi_m_monitor_bfm are used to monitor signals on the +// bus. This interface signal bundle is passed in the port list of +// the BFM in order to give the BFM access to the signals in this +// interface. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +`ifndef SPI_M_IF +`define SPI_M_IF +// This template can be used to connect a DUT to these signals +// +// .dut_signal_port(spi_m_bus.sclk), // Agent output +// .dut_signal_port(spi_m_bus.ss), // Agent output +// .dut_signal_port(spi_m_bus.mosi), // Agent output +// .dut_signal_port(spi_m_bus.miso), // Agent input + +import uvmf_base_pkg_hdl::*; +import spi_m_pkg_hdl::*; + +interface spi_m_if + + ( + input logic sck, + input logic rst, + output logic sclk, + output logic ss, + output logic [7:0] mosi, + input logic [7:0] miso + ); + +modport monitor_port + ( + input sck, + input rst, + input sclk, + input ss, + input mosi, + input miso + ); + +modport initiator_port + ( + input sck, + input rst, + output sclk, + output ss, + output mosi, + input miso + ); + +modport responder_port + ( + input sck, + input rst, + input sclk, + input ss, + input mosi, + output miso + ); + + +// pragma uvmf custom interface_item_additional begin +// pragma uvmf custom interface_item_additional end + +endinterface + +// pragma uvmf custom external begin +// pragma uvmf custom external end +`endif diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/spi_m_pkg/src/spi_m_infact_coverage_strategy.csv b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/spi_m_pkg/src/spi_m_infact_coverage_strategy.csv new file mode 100644 index 00000000..1c218e14 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/spi_m_pkg/src/spi_m_infact_coverage_strategy.csv @@ -0,0 +1,6 @@ +Global +auto_bin_max, 64 + +Name,Type,Include +rand_fields,coverpoint,=rand *.** + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/spi_m_pkg/src/spi_m_macros.svh b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/spi_m_pkg/src/spi_m_macros.svh new file mode 100644 index 00000000..a67d1c47 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/spi_m_pkg/src/spi_m_macros.svh @@ -0,0 +1,139 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This file contains macros used with the spi_m package. +// These macros include packed struct definitions. These structs are +// used to pass data between classes, hvl, and BFM's, hdl. Use of +// structs are more efficient and simpler to modify. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// + +// **************************************************************************** +// When changing the contents of this struct, be sure to update the to_struct +// and from_struct methods defined in the macros below that are used in +// the spi_m_configuration class. +// + `define spi_m_CONFIGURATION_STRUCT \ +typedef struct packed { \ + uvmf_active_passive_t active_passive; \ + uvmf_initiator_responder_t initiator_responder; \ + } spi_m_configuration_s; + + `define spi_m_CONFIGURATION_TO_STRUCT_FUNCTION \ + virtual function spi_m_configuration_s to_struct();\ + spi_m_configuration_struct = \ + {\ + this.active_passive,\ + this.initiator_responder\ + };\ + return ( spi_m_configuration_struct );\ + endfunction + + `define spi_m_CONFIGURATION_FROM_STRUCT_FUNCTION \ + virtual function void from_struct(spi_m_configuration_s spi_m_configuration_struct);\ + {\ + this.active_passive,\ + this.initiator_responder \ + } = spi_m_configuration_struct;\ + endfunction + +// **************************************************************************** +// When changing the contents of this struct, be sure to update the to_monitor_struct +// and from_monitor_struct methods of the spi_m_transaction class. +// + `define spi_m_MONITOR_STRUCT typedef struct packed { \ + bit ssel ; \ + bit [7:0] mosi ; \ + bit [7:0] miso ; \ + } spi_m_monitor_s; + + `define spi_m_TO_MONITOR_STRUCT_FUNCTION \ + virtual function spi_m_monitor_s to_monitor_struct();\ + spi_m_monitor_struct = \ + { \ + this.ssel , \ + this.mosi , \ + this.miso \ + };\ + return ( spi_m_monitor_struct);\ + endfunction\ + + `define spi_m_FROM_MONITOR_STRUCT_FUNCTION \ + virtual function void from_monitor_struct(spi_m_monitor_s spi_m_monitor_struct);\ + {\ + this.ssel , \ + this.mosi , \ + this.miso \ + } = spi_m_monitor_struct;\ + endfunction + +// **************************************************************************** +// When changing the contents of this struct, be sure to update the to_initiator_struct +// and from_initiator_struct methods of the spi_m_transaction class. +// Also update the comments in the driver BFM. +// + `define spi_m_INITIATOR_STRUCT typedef struct packed { \ + bit ssel ; \ + bit [7:0] mosi ; \ + bit [7:0] miso ; \ + } spi_m_initiator_s; + + `define spi_m_TO_INITIATOR_STRUCT_FUNCTION \ + virtual function spi_m_initiator_s to_initiator_struct();\ + spi_m_initiator_struct = \ + {\ + this.ssel , \ + this.mosi , \ + this.miso \ + };\ + return ( spi_m_initiator_struct);\ + endfunction + + `define spi_m_FROM_INITIATOR_STRUCT_FUNCTION \ + virtual function void from_initiator_struct(spi_m_initiator_s spi_m_initiator_struct);\ + {\ + this.ssel , \ + this.mosi , \ + this.miso \ + } = spi_m_initiator_struct;\ + endfunction + +// **************************************************************************** +// When changing the contents of this struct, be sure to update the to_responder_struct +// and from_responder_struct methods of the spi_m_transaction class. +// Also update the comments in the driver BFM. +// + `define spi_m_RESPONDER_STRUCT typedef struct packed { \ + bit ssel ; \ + bit [7:0] mosi ; \ + bit [7:0] miso ; \ + } spi_m_responder_s; + + `define spi_m_TO_RESPONDER_STRUCT_FUNCTION \ + virtual function spi_m_responder_s to_responder_struct();\ + spi_m_responder_struct = \ + {\ + this.ssel , \ + this.mosi , \ + this.miso \ + };\ + return ( spi_m_responder_struct);\ + endfunction + + `define spi_m_FROM_RESPONDER_STRUCT_FUNCTION \ + virtual function void from_responder_struct(spi_m_responder_s spi_m_responder_struct);\ + {\ + this.ssel , \ + this.mosi , \ + this.miso \ + } = spi_m_responder_struct;\ + endfunction +// pragma uvmf custom additional begin +// pragma uvmf custom additional end diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/spi_m_pkg/src/spi_m_monitor.svh b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/spi_m_pkg/src/spi_m_monitor.svh new file mode 100644 index 00000000..8779458a --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/spi_m_pkg/src/spi_m_monitor.svh @@ -0,0 +1,89 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This class receives spi_m transactions observed by the +// spi_m monitor BFM and broadcasts them through the analysis port +// on the agent. It accesses the monitor BFM through the monitor +// task. This UVM component captures transactions +// for viewing in the waveform viewer if the +// enable_transaction_viewing flag is set in the configuration. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +`ifndef SPI_M_MONITOR +`define SPI_M_MONITOR +class spi_m_monitor extends uvmf_monitor_base #( + .CONFIG_T(spi_m_configuration ), + .BFM_BIND_T(virtual spi_m_monitor_bfm ), + .TRANS_T(spi_m_transaction )); + + `uvm_component_utils( spi_m_monitor ) + +// Structure used to pass data from monitor BFM to monitor class in agent. +// Use to_monitor_struct function to pack transaction variables into structure. +// Use from_monitor_struct function to unpack transaction variables from structure. +`spi_m_MONITOR_STRUCT + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + +// **************************************************************************** +// This function is the standard SystemVerilog constructor. +// + function new( string name = "", uvm_component parent = null ); + super.new( name, parent ); + endfunction + +// **************************************************************************** +// This function sends configuration object variables to the monitor BFM +// using the configuration struct. +// + virtual function void configure(input CONFIG_T cfg); + bfm.configure( cfg.to_struct() ); + + endfunction + +// **************************************************************************** +// This function places a handle to this class in the proxy variable in the +// monitor BFM. This allows the monitor BFM to call the notify_transaction +// function within this class. +// + virtual function void set_bfm_proxy_handle(); + bfm.proxy = this; endfunction + +// *************************************************************************** + virtual task run_phase(uvm_phase phase); + // Start monitor BFM thread and don't call super.run() in order to + // override the default monitor proxy 'pull' behavior with the more + // emulation-friendly BFM 'push' approach using the notify_transaction + // function below + bfm.start_monitoring(); + endtask + +// ************************************************************************** + +// This function is called by the monitor BFM. It receives data observed by the +// monitor BFM. Data is passed using the spi_m_monitor_struct. + virtual function void notify_transaction(input spi_m_monitor_s spi_m_monitor_struct); + + + trans = new("trans"); + trans.from_monitor_struct(spi_m_monitor_struct); + trans.start_time = time_stamp; + trans.end_time = $time; + time_stamp = trans.end_time; + + analyze(trans); + endfunction + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end +`endif diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/spi_m_pkg/src/spi_m_monitor_bfm.sv b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/spi_m_pkg/src/spi_m_monitor_bfm.sv new file mode 100644 index 00000000..b1917bce --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/spi_m_pkg/src/spi_m_monitor_bfm.sv @@ -0,0 +1,187 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This interface performs the spi_m signal monitoring. +// It is accessed by the uvm spi_m monitor through a virtual +// interface handle in the spi_m configuration. It monitors the +// signals passed in through the port connection named bus of +// type spi_m_if. +// +// Input signals from the spi_m_if are assigned to an internal input +// signal with a _i suffix. The _i signal should be used for sampling. +// +// The input signal connections are as follows: +// bus.signal -> signal_i +// +// Interface functions and tasks used by UVM components: +// monitor(inout TRANS_T txn); +// This task receives the transaction, txn, from the +// UVM monitor and then populates variables in txn +// from values observed on bus activity. This task +// blocks until an operation on the spi_m bus is complete. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +`ifndef SPI_M_MONITOR_BFM +`define SPI_M_MONITOR_BFM +import uvmf_base_pkg_hdl::*; +import spi_m_pkg_hdl::*; +`include "src/spi_m_macros.svh" + + +interface spi_m_monitor_bfm + ( spi_m_if bus ); + // The pragma below and additional ones in-lined further down are for running this BFM on Veloce + // pragma attribute spi_m_monitor_bfm partition_interface_xif + +`ifndef XRTL +// This code is to aid in debugging parameter mismatches between the BFM and its corresponding agent. +// Enable this debug by setting UVM_VERBOSITY to UVM_DEBUG +// Setting UVM_VERBOSITY to UVM_DEBUG causes all BFM's and all agents to display their parameter settings. +// All of the messages from this feature have a UVM messaging id value of "CFG" +// The transcript or run.log can be parsed to ensure BFM parameter settings match its corresponding agents parameter settings. +import uvm_pkg::*; +`include "uvm_macros.svh" +initial begin : bfm_vs_agent_parameter_debug + `uvm_info("CFG", + $psprintf("The BFM at '%m' has the following parameters: ", ), + UVM_DEBUG) +end +`endif + + + // Structure used to pass transaction data from monitor BFM to monitor class in agent. +`spi_m_MONITOR_STRUCT + spi_m_monitor_s spi_m_monitor_struct; + + // Structure used to pass configuration data from monitor class to monitor BFM. + `spi_m_CONFIGURATION_STRUCT + + + // Config value to determine if this is an initiator or a responder + uvmf_initiator_responder_t initiator_responder; + // Custom configuration variables. + // These are set using the configure function which is called during the UVM connect_phase + + logic sck_i; + logic rst_i; + tri sclk_i; + tri ss_i; + tri [7:0] mosi_i; + tri [7:0] miso_i; + assign sck_i = bus.sck; + assign rst_i = bus.rst; + assign sclk_i = bus.sclk; + assign ss_i = bus.ss; + assign mosi_i = bus.mosi; + assign miso_i = bus.miso; + + // Proxy handle to UVM monitor + spi_m_pkg::spi_m_monitor proxy; + // pragma tbx oneway proxy.notify_transaction + + // pragma uvmf custom interface_item_additional begin + // pragma uvmf custom interface_item_additional end + + //****************************************************************** + task wait_for_reset();// pragma tbx xtf + @(posedge sck_i) ; + do_wait_for_reset(); + endtask + + // **************************************************************************** + task do_wait_for_reset(); + // pragma uvmf custom reset_condition begin + wait ( rst_i === 0 ) ; + @(posedge sck_i) ; + // pragma uvmf custom reset_condition end + endtask + + //****************************************************************** + + task wait_for_num_clocks(input int unsigned count); // pragma tbx xtf + @(posedge sck_i); + + repeat (count-1) @(posedge sck_i); + endtask + + //****************************************************************** + event go; + function void start_monitoring();// pragma tbx xtf + -> go; + endfunction + + // **************************************************************************** + initial begin + @go; + forever begin + @(posedge sck_i); + do_monitor( spi_m_monitor_struct ); + + + proxy.notify_transaction( spi_m_monitor_struct ); + + end + end + + //****************************************************************** + // The configure() function is used to pass agent configuration + // variables to the monitor BFM. It is called by the monitor within + // the agent at the beginning of the simulation. It may be called + // during the simulation if agent configuration variables are updated + // and the monitor BFM needs to be aware of the new configuration + // variables. + // + function void configure(spi_m_configuration_s spi_m_configuration_arg); // pragma tbx xtf + initiator_responder = spi_m_configuration_arg.initiator_responder; + // pragma uvmf custom configure begin + // pragma uvmf custom configure end + endfunction + + + // **************************************************************************** + + task do_monitor(output spi_m_monitor_s spi_m_monitor_struct); + // + // Available struct members: + // // spi_m_monitor_struct.ssel + // // spi_m_monitor_struct.mosi + // // spi_m_monitor_struct.miso + // // + // Reference code; + // How to wait for signal value + // while (control_signal === 1'b1) @(posedge sck_i); + // + // How to assign a struct member, named xyz, from a signal. + // All available input signals listed. + // spi_m_monitor_struct.xyz = sclk_i; // + // spi_m_monitor_struct.xyz = ss_i; // + // spi_m_monitor_struct.xyz = mosi_i; // [7:0] + // spi_m_monitor_struct.xyz = miso_i; // [7:0] + // pragma uvmf custom do_monitor begin + // UVMF_CHANGE_ME : Implement protocol monitoring. The commented reference code + // below are examples of how to capture signal values and assign them to + // structure members. All available input signals are listed. The 'while' + // code example shows how to wait for a synchronous flow control signal. This + // task should return when a complete transfer has been observed. Once this task is + // exited with captured values, it is then called again to wait for and observe + // the next transfer. One clock cycle is consumed between calls to do_monitor. + @(posedge sck_i); + @(posedge sck_i); + @(posedge sck_i); + @(posedge sck_i); + // pragma uvmf custom do_monitor end + endtask + + +endinterface + +// pragma uvmf custom external begin +// pragma uvmf custom external end +`endif diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/spi_m_pkg/src/spi_m_random_sequence.svh b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/spi_m_pkg/src/spi_m_random_sequence.svh new file mode 100644 index 00000000..1ecbc8df --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/spi_m_pkg/src/spi_m_random_sequence.svh @@ -0,0 +1,55 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: +// This sequences randomizes the spi_m transaction and sends it +// to the UVM driver. +// +// This sequence constructs and randomizes a spi_m_transaction. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +`ifndef SPI_M_RANDOM_SEQUENCE +`define SPI_M_RANDOM_SEQUENCE +class spi_m_random_sequence + extends spi_m_sequence_base ; + + `uvm_object_utils( spi_m_random_sequence ) + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + //***************************************************************** + function new(string name = ""); + super.new(name); + endfunction: new + + // **************************************************************************** + // TASK : body() + // This task is automatically executed when this sequence is started using the + // start(sequencerHandle) task. + // + task body(); + + // Construct the transaction + req=spi_m_transaction::type_id::create("req"); + start_item(req); + // Randomize the transaction + if(!req.randomize()) `uvm_fatal("SEQ", "spi_m_random_sequence::body()-spi_m_transaction randomization failed") + // Send the transaction to the spi_m_driver_bfm via the sequencer and spi_m_driver. + finish_item(req); + `uvm_info("SEQ", {"Response:",req.convert2string()},UVM_MEDIUM) + + endtask + +endclass: spi_m_random_sequence + +// pragma uvmf custom external begin +// pragma uvmf custom external end +`endif diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/spi_m_pkg/src/spi_m_responder_sequence.svh b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/spi_m_pkg/src/spi_m_responder_sequence.svh new file mode 100644 index 00000000..16daf8f9 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/spi_m_pkg/src/spi_m_responder_sequence.svh @@ -0,0 +1,51 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This class can be used to provide stimulus when an interface +// has been configured to run in a responder mode. It +// will never finish by default, always going back to the driver +// and driver BFM for the next transaction with which to respond. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +`ifndef SPI_M_RESPONDER_SEQUENCE +`define SPI_M_RESPONDER_SEQUENCE +class spi_m_responder_sequence + extends spi_m_sequence_base ; + + `uvm_object_utils( spi_m_responder_sequence ) + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + function new(string name = "spi_m_responder_sequence"); + super.new(name); + endfunction + + task body(); + req=spi_m_transaction::type_id::create("req"); + forever begin + start_item(req); + finish_item(req); + // pragma uvmf custom body begin + // UVMF_CHANGE_ME : Do something here with the resulting req item. The + // finish_item() call above will block until the req transaction is ready + // to be handled by the responder sequence. + // If this was an item that required a response, the expectation is + // that the response should be populated within this transaction now. + `uvm_info("SEQ",$sformatf("Processed txn: %s",req.convert2string()),UVM_HIGH) + // pragma uvmf custom body end + end + endtask + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end +`endif diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/spi_m_pkg/src/spi_m_sequence_base.svh b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/spi_m_pkg/src/spi_m_sequence_base.svh new file mode 100644 index 00000000..f9e4fa7e --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/spi_m_pkg/src/spi_m_sequence_base.svh @@ -0,0 +1,98 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: +// This file contains the class used as the base class for all sequences +// for this interface. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +`ifndef SPI_M_SEQUENCE_BASE +`define SPI_M_SEQUENCE_BASE +class spi_m_sequence_base extends uvmf_sequence_base #( + .REQ(spi_m_transaction ), + .RSP(spi_m_transaction )); + + `uvm_object_utils( spi_m_sequence_base ) + + // variables + typedef spi_m_transaction spi_m_transaction_req_t; + spi_m_transaction_req_t req; + typedef spi_m_transaction spi_m_transaction_rsp_t; + spi_m_transaction_rsp_t rsp; + + // Event for identifying when a response was received from the sequencer + event new_rsp; + + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + // **************************************************************************** + // TASK : get_responses() + // This task recursively gets sequence item responses from the sequencer. + // + virtual task get_responses(); + fork + begin + // Block until new rsp available + get_response(rsp); + // New rsp received. Indicate to sequence using event. + ->new_rsp; + // Display the received response transaction + `uvm_info("SEQ", {"New response transaction:",rsp.convert2string()}, UVM_MEDIUM) + end + join_none + endtask + + // **************************************************************************** + // TASK : pre_body() + // This task is called automatically when start is called with call_pre_post set to 1 (default). + // By calling get_responses() within pre_body() any derived sequences are automatically + // processing response transactions. Only un-comment this call to get_responses() if you + // have configured the interface driver to utilize the response transaction path by setting + // the configuration variable "return_transaction_response" to 1. Otherwise it is possible + // to impact runtime performance and memory utilization. + // + virtual task pre_body(); + // pragma uvmf custom pre_body begin +// get_responses(); + // pragma uvmf custom pre_body end + endtask + + // **************************************************************************** + // TASK : body() + // This task is called automatically when start is called. This sequence sends + // a req sequence item to the sequencer identified as an argument in the call + // to start. + // + virtual task body(); + // pragma uvmf custom body begin + start_item(req); + finish_item(req); + // pragma uvmf custom body end + endtask + + // **************************************************************************** + // FUNCTION : new() + // This function is the standard SystemVerilog constructor. + // + function new( string name =""); + super.new( name ); + // pragma uvmf custom new begin + req = spi_m_transaction_req_t::type_id::create("req"); + rsp = spi_m_transaction_rsp_t::type_id::create("rsp"); + // pragma uvmf custom new end + endfunction + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end +`endif diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/spi_m_pkg/src/spi_m_transaction.svh b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/spi_m_pkg/src/spi_m_transaction.svh new file mode 100644 index 00000000..2717764d --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/spi_m_pkg/src/spi_m_transaction.svh @@ -0,0 +1,192 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This class defines the variables required for an spi_m +// transaction. Class variables to be displayed in waveform transaction +// viewing are added to the transaction viewing stream in the add_to_wave +// function. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +`ifndef SPI_M_TRANSACTION +`define SPI_M_TRANSACTION +class spi_m_transaction extends uvmf_transaction_base; + + `uvm_object_utils( spi_m_transaction ) + + rand bit ssel ; + rand bit [7:0] mosi ; + bit [7:0] miso ; + + //Constraints for the transaction variables: + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + //******************************************************************* + //******************************************************************* + // Macros that define structs and associated functions are + // located in spi_m_macros.svh + + //******************************************************************* + // Monitor macro used by spi_m_monitor and spi_m_monitor_bfm + // This struct is defined in spi_m_macros.svh + `spi_m_MONITOR_STRUCT + spi_m_monitor_s spi_m_monitor_struct; + //******************************************************************* + // FUNCTION: to_monitor_struct() + // This function packs transaction variables into a spi_m_monitor_s + // structure. The function returns the handle to the spi_m_monitor_struct. + // This function is defined in spi_m_macros.svh + `spi_m_TO_MONITOR_STRUCT_FUNCTION + //******************************************************************* + // FUNCTION: from_monitor_struct() + // This function unpacks the struct provided as an argument into transaction + // variables of this class. + // This function is defined in spi_m_macros.svh + `spi_m_FROM_MONITOR_STRUCT_FUNCTION + + //******************************************************************* + // Initiator macro used by spi_m_driver and spi_m_driver_bfm + // to communicate initiator driven data to spi_m_driver_bfm. + // This struct is defined in spi_m_macros.svh + `spi_m_INITIATOR_STRUCT + spi_m_initiator_s spi_m_initiator_struct; + //******************************************************************* + // FUNCTION: to_initiator_struct() + // This function packs transaction variables into a spi_m_initiator_s + // structure. The function returns the handle to the spi_m_initiator_struct. + // This function is defined in spi_m_macros.svh + `spi_m_TO_INITIATOR_STRUCT_FUNCTION + //******************************************************************* + // FUNCTION: from_initiator_struct() + // This function unpacks the struct provided as an argument into transaction + // variables of this class. + // This function is defined in spi_m_macros.svh + `spi_m_FROM_INITIATOR_STRUCT_FUNCTION + + //******************************************************************* + // Responder macro used by spi_m_driver and spi_m_driver_bfm + // to communicate Responder driven data to spi_m_driver_bfm. + // This struct is defined in spi_m_macros.svh + `spi_m_RESPONDER_STRUCT + spi_m_responder_s spi_m_responder_struct; + //******************************************************************* + // FUNCTION: to_responder_struct() + // This function packs transaction variables into a spi_m_responder_s + // structure. The function returns the handle to the spi_m_responder_struct. + // This function is defined in spi_m_macros.svh + `spi_m_TO_RESPONDER_STRUCT_FUNCTION + //******************************************************************* + // FUNCTION: from_responder_struct() + // This function unpacks the struct provided as an argument into transaction + // variables of this class. + // This function is defined in spi_m_macros.svh + `spi_m_FROM_RESPONDER_STRUCT_FUNCTION + // **************************************************************************** + // FUNCTION : new() + // This function is the standard SystemVerilog constructor. + // + function new( string name = "" ); + super.new( name ); + endfunction + + // **************************************************************************** + // FUNCTION: convert2string() + // This function converts all variables in this class to a single string for + // logfile reporting. + // + virtual function string convert2string(); + // pragma uvmf custom convert2string begin + // UVMF_CHANGE_ME : Customize format if desired. + return $sformatf("ssel:0x%x mosi:0x%x miso:0x%x ",ssel,mosi,miso); + // pragma uvmf custom convert2string end + endfunction + + //******************************************************************* + // FUNCTION: do_print() + // This function is automatically called when the .print() function + // is called on this class. + // + virtual function void do_print(uvm_printer printer); + // pragma uvmf custom do_print begin + // UVMF_CHANGE_ME : Current contents of do_print allows for the use of UVM 1.1d, 1.2 or P1800.2. + // Update based on your own printing preference according to your preferred UVM version + $display(convert2string()); + // pragma uvmf custom do_print end + endfunction + + //******************************************************************* + // FUNCTION: do_compare() + // This function is automatically called when the .compare() function + // is called on this class. + // + virtual function bit do_compare (uvm_object rhs, uvm_comparer comparer); + spi_m_transaction RHS; + if (!$cast(RHS,rhs)) return 0; + // pragma uvmf custom do_compare begin + // UVMF_CHANGE_ME : Eliminate comparison of variables not to be used for compare + return (super.do_compare(rhs,comparer) + &&(this.ssel == RHS.ssel) + &&(this.mosi == RHS.mosi) + &&(this.miso == RHS.miso) + ); + // pragma uvmf custom do_compare end + endfunction + + //******************************************************************* + // FUNCTION: do_copy() + // This function is automatically called when the .copy() function + // is called on this class. + // + virtual function void do_copy (uvm_object rhs); + spi_m_transaction RHS; + assert($cast(RHS,rhs)); + // pragma uvmf custom do_copy begin + super.do_copy(rhs); + this.ssel = RHS.ssel; + this.mosi = RHS.mosi; + this.miso = RHS.miso; + // pragma uvmf custom do_copy end + endfunction + + // **************************************************************************** + // FUNCTION: add_to_wave() + // This function is used to display variables in this class in the waveform + // viewer. The start_time and end_time variables must be set before this + // function is called. If the start_time and end_time variables are not set + // the transaction will be hidden at 0ns on the waveform display. + // + virtual function void add_to_wave(int transaction_viewing_stream_h); + `ifdef QUESTA + if (transaction_view_h == 0) begin + transaction_view_h = $begin_transaction(transaction_viewing_stream_h,"spi_m_transaction",start_time); + end + super.add_to_wave(transaction_view_h); + // pragma uvmf custom add_to_wave begin + // UVMF_CHANGE_ME : Color can be applied to transaction entries based on content, example below + // case() + // 1 : $add_color(transaction_view_h,"red"); + // default : $add_color(transaction_view_h,"grey"); + // endcase + // UVMF_CHANGE_ME : Eliminate transaction variables not wanted in transaction viewing in the waveform viewer + $add_attribute(transaction_view_h,ssel,"ssel"); + $add_attribute(transaction_view_h,mosi,"mosi"); + $add_attribute(transaction_view_h,miso,"miso"); + // pragma uvmf custom add_to_wave end + $end_transaction(transaction_view_h,end_time); + $free_transaction(transaction_view_h); + `endif // QUESTA + endfunction + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end +`endif diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/spi_m_pkg/src/spi_m_transaction_coverage.svh b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/spi_m_pkg/src/spi_m_transaction_coverage.svh new file mode 100644 index 00000000..e89c599c --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/spi_m_pkg/src/spi_m_transaction_coverage.svh @@ -0,0 +1,75 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This class records spi_m transaction information using +// a covergroup named spi_m_transaction_cg. An instance of this +// coverage component is instantiated in the uvmf_parameterized_agent +// if the has_coverage flag is set. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +`ifndef SPI_M_TRANSACTION_COVERAGE +`define SPI_M_TRANSACTION_COVERAGE +class spi_m_transaction_coverage extends uvm_subscriber #(.T(spi_m_transaction )); + + `uvm_component_utils( spi_m_transaction_coverage ) + + T coverage_trans; + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + // **************************************************************************** + covergroup spi_m_transaction_cg; + // pragma uvmf custom covergroup begin + // UVMF_CHANGE_ME : Add coverage bins, crosses, exclusions, etc. according to coverage needs. + option.auto_bin_max=1024; + option.per_instance=1; + ssel: coverpoint coverage_trans.ssel; + mosi: coverpoint coverage_trans.mosi; + miso: coverpoint coverage_trans.miso; + // pragma uvmf custom covergroup end + endgroup + + // **************************************************************************** + // FUNCTION : new() + // This function is the standard SystemVerilog constructor. + // + function new(string name="", uvm_component parent=null); + super.new(name,parent); + spi_m_transaction_cg=new; + `uvm_warning("COVERAGE_MODEL_REVIEW", "A covergroup has been constructed which may need review because of either generation or re-generation with merging. Please note that transaction variables added as a result of re-generation and merging are not automatically added to the covergroup. Remove this warning after the covergroup has been reviewed.") + endfunction + + // **************************************************************************** + // FUNCTION : build_phase() + // This function is the standard UVM build_phase. + // + function void build_phase(uvm_phase phase); + spi_m_transaction_cg.set_inst_name($sformatf("spi_m_transaction_cg_%s",get_full_name())); + endfunction + + // **************************************************************************** + // FUNCTION: write (T t) + // This function is automatically executed when a transaction arrives on the + // analysis_export. It copies values from the variables in the transaction + // to local variables used to collect functional coverage. + // + virtual function void write (T t); + `uvm_info("COV","Received transaction",UVM_HIGH); + coverage_trans = t; + spi_m_transaction_cg.sample(); + endfunction + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + +`endif diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/spi_m_pkg/src/spi_m_typedefs.svh b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/spi_m_pkg/src/spi_m_typedefs.svh new file mode 100644 index 00000000..91e77a1c --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/spi_m_pkg/src/spi_m_typedefs.svh @@ -0,0 +1,21 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: +// This file contains defines and typedefs to be compiled for use in +// the simulation running on the host server when using Veloce. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +`ifndef TYPEDEFS_HVL +`definr TYPEDEFS_HVL + +// pragma uvmf custom additional begin +// pragma uvmf custom additional end +`endif diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/spi_m_pkg/src/spi_m_typedefs_hdl.svh b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/spi_m_pkg/src/spi_m_typedefs_hdl.svh new file mode 100644 index 00000000..bd6b6f41 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/spi_m_pkg/src/spi_m_typedefs_hdl.svh @@ -0,0 +1,23 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: +// This file contains defines and typedefs to be compiled for use in +// the simulation running on the emulator when using Veloce. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// + +`ifndef TYPEDEFS_HVL +`definr TYPEDEFS_HVL + + +// pragma uvmf custom additional begin +// pragma uvmf custom additional end +`endif diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/spi_m_pkg/yaml/spi_m_interface.yaml b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/spi_m_pkg/yaml/spi_m_interface.yaml new file mode 100644 index 00000000..1eca4f64 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/spi_m_pkg/yaml/spi_m_interface.yaml @@ -0,0 +1,53 @@ +uvmf: + interfaces: + spi_m: + clock: sck + config_constraints: [] + config_vars: [] + existing_library_component: 'True' + gen_inbound_streaming_driver: 'False' + hdl_pkg_parameters: [] + hdl_typedefs: [] + hvl_pkg_parameters: [] + hvl_typedefs: [] + parameters: [] + ports: + - dir: output + name: sclk + reset_value: '''b0' + width: '1' + - dir: output + name: ss + reset_value: '''b0' + width: '1' + - dir: output + name: mosi + reset_value: '''b0' + width: '8' + - dir: input + name: miso + reset_value: '''b0' + width: '8' + reset: rst + reset_assertion_level: 'True' + transaction_constraints: [] + transaction_vars: + - comment: '' + iscompare: 'True' + isrand: 'True' + name: ssel + type: bit + unpacked_dimension: '' + - comment: '' + iscompare: 'True' + isrand: 'True' + name: mosi + type: bit [7:0] + unpacked_dimension: '' + - comment: '' + iscompare: 'True' + isrand: 'False' + name: miso + type: bit [7:0] + unpacked_dimension: '' + use_dpi_link: 'False' diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/spi_s_pkg/.project b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/spi_s_pkg/.project new file mode 100644 index 00000000..548e937e --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/spi_s_pkg/.project @@ -0,0 +1,30 @@ + + + spi_s_pkg + + + + + + org.python.pydev.PyDevBuilder + + + + + net.sf.sveditor.core.SVProjectBuilder + + + + + + net.sf.sveditor.core.SVNature + org.python.pydev.pythonNature + + + + UVMF_VIP_LIBRARY_HOME + $%7BPARENT-2-PROJECT_LOC%7D + + + + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/spi_s_pkg/.svproject b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/spi_s_pkg/.svproject new file mode 100644 index 00000000..dbc66e83 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/spi_s_pkg/.svproject @@ -0,0 +1,16 @@ + + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/spi_s_pkg/Makefile b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/spi_s_pkg/Makefile new file mode 100644 index 00000000..d4c678b7 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/spi_s_pkg/Makefile @@ -0,0 +1,66 @@ +# spi_s interface packages source +# pragma uvmf custom additional begin +# pragma uvmf custom additional end + +spi_s_PKG = \ + +incdir+$(UVMF_VIP_LIBRARY_HOME)/interface_packages/spi_s_pkg \ + -F $(UVMF_VIP_LIBRARY_HOME)/interface_packages/spi_s_pkg/spi_s_filelist_hvl.f + +spi_s_PKG_HDL = \ + +incdir+$(UVMF_VIP_LIBRARY_HOME)/interface_packages/spi_s_pkg \ + -F $(UVMF_VIP_LIBRARY_HOME)/interface_packages/spi_s_pkg/spi_s_filelist_hdl.f + +spi_s_PKG_XRTL = \ + +incdir+$(UVMF_VIP_LIBRARY_HOME)/interface_packages/spi_s_pkg \ + -F $(UVMF_VIP_LIBRARY_HOME)/interface_packages/spi_s_pkg/spi_s_filelist_xrtl.f + +COMP_spi_s_PKG_TGT_0 = q_comp_spi_s_pkg +COMP_spi_s_PKG_TGT_1 = v_comp_spi_s_pkg +COMP_spi_s_PKG_TGT = $(COMP_spi_s_PKG_TGT_$(USE_VELOCE)) + +comp_spi_s_pkg: $(COMP_spi_s_PKG_TGT) + +q_comp_spi_s_pkg: + $(HDL_COMP_CMD) $(spi_s_PKG_HDL) + $(HVL_COMP_CMD) $(spi_s_PKG) + $(HDL_COMP_CMD) $(spi_s_PKG_XRTL) + +v_comp_spi_s_pkg: + $(HVL_COMP_CMD) $(spi_s_PKG_HDL) + $(HVL_COMP_CMD) $(spi_s_PKG) + $(VELANALYZE_CMD) $(spi_s_PKG_HDL) + $(VELANALYZE_HVL_CMD) $(spi_s_PKG) + $(HDL_COMP_CMD) $(spi_s_PKG_XRTL) + +ifeq ($(MTI_VCO_MODE),64) + GCC_COMP_ARCH = -m64 +else + GCC_COMP_ARCH = -m32 +endif + +export spi_s_IF_DPI_SRC ?= $(UVMF_VIP_LIBRARY_HOME)/interface_packages/spi_s_pkg/dpi + +C_FILE_COMPILE_LIST_spi_s_pkg = \ + +O_FILE_COMPILE_LIST_spi_s_pkg = $(notdir $(C_FILE_COMPILE_LIST_spi_s_pkg:.c=.o)) + +GCC_COMP_ARGS_spi_s_pkg += -I$(spi_s_IF_DPI_SRC) \ + -fPIC + +GCC_COMP_ARGS_spi_s_pkg += $(spi_s_IF_GCC_COMP_ARGUMENTS) + +GCC_LINK_ARGS_spi_s_pkg += \ + \ + -o .so + +comp_spi_s_pkg_c_files: + @echo "--------------------------------" + @echo "Compiling Interface C source" + @echo "--------------------------------" + gcc $(GCC_COMP_ARCH) $(GCC_COMP_ARGS_spi_s_pkg) $(C_FILE_COMPILE_LIST_spi_s_pkg) + @echo "--------------------------------" + @echo "Linking Interface C objects into a shared object" + @echo "--------------------------------" + gcc $(GCC_COMP_ARCH) $(GCC_LINK_ARGS_spi_s_pkg) $(O_FILE_COMPILE_LIST_spi_s_pkg) + @echo "--------------------------------" + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/spi_s_pkg/compile.do b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/spi_s_pkg/compile.do new file mode 100644 index 00000000..303c17b2 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/spi_s_pkg/compile.do @@ -0,0 +1,14 @@ +# Tcl do file for compile of spi_s interface + +# pragma uvmf custom additional begin +# pragma uvmf custom additional end + + +vlog -sv -timescale 1ps/1ps -suppress 2223,2286 +incdir+$env(UVMF_VIP_LIBRARY_HOME)/interface_packages/spi_s_pkg \ + -F $env(UVMF_VIP_LIBRARY_HOME)/interface_packages/spi_s_pkg/spi_s_filelist_hdl.f + +vlog -sv -timescale 1ps/1ps -suppress 2223,2286 +incdir+$env(UVMF_VIP_LIBRARY_HOME)/interface_packages/spi_s_pkg \ + -F $env(UVMF_VIP_LIBRARY_HOME)/interface_packages/spi_s_pkg/spi_s_filelist_hvl.f + +vlog -sv -timescale 1ps/1ps -suppress 2223,2286 +incdir+$env(UVMF_VIP_LIBRARY_HOME)/interface_packages/spi_s_pkg \ + -F $env(UVMF_VIP_LIBRARY_HOME)/interface_packages/spi_s_pkg/spi_s_filelist_xrtl.f \ No newline at end of file diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/spi_s_pkg/spi_s.compile b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/spi_s_pkg/spi_s.compile new file mode 100644 index 00000000..8b8aa6e2 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/spi_s_pkg/spi_s.compile @@ -0,0 +1,3 @@ +needs: + - spi_s_hvl.compile + - spi_s_hdl.compile diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/spi_s_pkg/spi_s_bfm.vinfo b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/spi_s_pkg/spi_s_bfm.vinfo new file mode 100644 index 00000000..0f12baaf --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/spi_s_pkg/spi_s_bfm.vinfo @@ -0,0 +1,6 @@ +@use $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg_hdl.vinfo +@use spi_s_pkg_hdl.vinfo ++incdir+@vinfodir +src/spi_s_if.sv +src/spi_s_driver_bfm.sv +src/spi_s_monitor_bfm.sv diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/spi_s_pkg/spi_s_common.compile b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/spi_s_pkg/spi_s_common.compile new file mode 100644 index 00000000..08bd125f --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/spi_s_pkg/spi_s_common.compile @@ -0,0 +1,7 @@ +needs: + - $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg_hdl.compile +incdir: + - . + - ${uvm_path}/src +src: + - spi_s_pkg_hdl.sv diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/spi_s_pkg/spi_s_filelist_hdl.f b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/spi_s_pkg/spi_s_filelist_hdl.f new file mode 100644 index 00000000..d7724020 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/spi_s_pkg/spi_s_filelist_hdl.f @@ -0,0 +1 @@ +$UVMF_VIP_LIBRARY_HOME/interface_packages/spi_s_pkg/spi_s_pkg_hdl.sv diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/spi_s_pkg/spi_s_filelist_hvl.f b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/spi_s_pkg/spi_s_filelist_hvl.f new file mode 100644 index 00000000..cbc4a9ef --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/spi_s_pkg/spi_s_filelist_hvl.f @@ -0,0 +1 @@ +$UVMF_VIP_LIBRARY_HOME/interface_packages/spi_s_pkg/spi_s_pkg.sv \ No newline at end of file diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/spi_s_pkg/spi_s_filelist_xrtl.f b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/spi_s_pkg/spi_s_filelist_xrtl.f new file mode 100644 index 00000000..175919ef --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/spi_s_pkg/spi_s_filelist_xrtl.f @@ -0,0 +1,3 @@ +$UVMF_VIP_LIBRARY_HOME/interface_packages/spi_s_pkg/src/spi_s_if.sv +$UVMF_VIP_LIBRARY_HOME/interface_packages/spi_s_pkg/src/spi_s_monitor_bfm.sv +$UVMF_VIP_LIBRARY_HOME/interface_packages/spi_s_pkg/src/spi_s_driver_bfm.sv diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/spi_s_pkg/spi_s_hdl.compile b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/spi_s_pkg/spi_s_hdl.compile new file mode 100644 index 00000000..e63a6a97 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/spi_s_pkg/spi_s_hdl.compile @@ -0,0 +1,9 @@ +needs: + - $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg_hdl.compile + - ./spi_s_common.compile +incdir: + - . +src: + - src/spi_s_if.sv + - src/spi_s_monitor_bfm.sv + - src/spi_s_driver_bfm.sv diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/spi_s_pkg/spi_s_hvl.compile b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/spi_s_pkg/spi_s_hvl.compile new file mode 100644 index 00000000..569dc399 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/spi_s_pkg/spi_s_hvl.compile @@ -0,0 +1,7 @@ +needs: + - $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg.compile + - ./spi_s_common.compile +incdir: + - . +src: + - spi_s_pkg.sv diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/spi_s_pkg/spi_s_pkg.sv b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/spi_s_pkg/spi_s_pkg.sv new file mode 100644 index 00000000..048a44ab --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/spi_s_pkg/spi_s_pkg.sv @@ -0,0 +1,79 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// PACKAGE: This file defines all of the files contained in the +// interface package that will run on the host simulator. +// +// CONTAINS: +// - +// - +// - + +// - +// - +// - + +// - +// - +// - + +// - +// - +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +`ifndef SPI_S_PKG +`define SPI_S_PKG +package spi_s_pkg; + + import uvm_pkg::*; + import uvmf_base_pkg_hdl::*; + import uvmf_base_pkg::*; + import spi_s_pkg_hdl::*; + + `include "uvm_macros.svh" + + // pragma uvmf custom package_imports_additional begin + // pragma uvmf custom package_imports_additional end + `include "src/spi_s_macros.svh" + + export spi_s_pkg_hdl::*; + + + + // Parameters defined as HVL parameters + + `include "src/spi_s_typedefs.svh" + `include "src/spi_s_transaction.svh" + + `include "src/spi_s_configuration.svh" + `include "src/spi_s_driver.svh" + `include "src/spi_s_monitor.svh" + + `include "src/spi_s_transaction_coverage.svh" + `include "src/spi_s_sequence_base.svh" + `include "src/spi_s_random_sequence.svh" + + `include "src/spi_s_responder_sequence.svh" + `include "src/spi_s2reg_adapter.svh" + + `include "src/spi_s_agent.svh" + + // pragma uvmf custom package_item_additional begin + // UVMF_CHANGE_ME : When adding new interface sequences to the src directory + // be sure to add the sequence file here so that it will be + // compiled as part of the interface package. Be sure to place + // the new sequence after any base sequences of the new sequence. + // pragma uvmf custom package_item_additional end + +endpackage + +// pragma uvmf custom external begin +// pragma uvmf custom external end +`endif diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/spi_s_pkg/spi_s_pkg.vinfo b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/spi_s_pkg/spi_s_pkg.vinfo new file mode 100644 index 00000000..b849145a --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/spi_s_pkg/spi_s_pkg.vinfo @@ -0,0 +1,4 @@ +@use $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg.vinfo +@use spi_s_pkg_hdl.vinfo ++incdir+@vinfodir +spi_s_pkg.sv diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/spi_s_pkg/spi_s_pkg_hdl.sv b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/spi_s_pkg/spi_s_pkg_hdl.sv new file mode 100644 index 00000000..b5b57d9e --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/spi_s_pkg/spi_s_pkg_hdl.sv @@ -0,0 +1,40 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// PACKAGE: This file defines all of the files contained in the +// interface package that needs to be compiled and synthesized +// for running on Veloce. +// +// CONTAINS: +// - +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +`ifndef SPI_S_PKG_HDL +`define SPI_S_PKG_HDL +package spi_s_pkg_hdl; + + import uvmf_base_pkg_hdl::*; + + // pragma uvmf custom package_imports_additional begin + // pragma uvmf custom package_imports_additional end + + // Parameters defined as HDL parameters + + `include "src/spi_s_typedefs_hdl.svh" + `include "src/spi_s_macros.svh" + + // pragma uvmf custom package_item_additional begin + // pragma uvmf custom package_item_additional end + +endpackage + +// pragma uvmf custom external begin +// pragma uvmf custom external end +`endif diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/spi_s_pkg/spi_s_pkg_hdl.vinfo b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/spi_s_pkg/spi_s_pkg_hdl.vinfo new file mode 100644 index 00000000..969589c7 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/spi_s_pkg/spi_s_pkg_hdl.vinfo @@ -0,0 +1,2 @@ +@use $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg_hdl.vinfo +spi_s_pkg_hdl.sv diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/spi_s_pkg/spi_s_pkg_sve.F b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/spi_s_pkg/spi_s_pkg_sve.F new file mode 100644 index 00000000..13508e71 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/spi_s_pkg/spi_s_pkg_sve.F @@ -0,0 +1,10 @@ +// UVM ++incdir+${UVM_HOME}/src +${UVM_HOME}/src/uvm_pkg.sv + +// Common UVMF files +-f ${UVMF_HOME}/common/common_sve.f + ++incdir+. +-f ${UVMF_VIP_LIBRARY_HOME}/interface_packages/spi_s_pkg/spi_s_filelist_hdl.f +-f ${UVMF_VIP_LIBRARY_HOME}/interface_packages/spi_s_pkg/spi_s_filelist_hvl.f diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/spi_s_pkg/src/spi_s2reg_adapter.svh b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/spi_s_pkg/src/spi_s2reg_adapter.svh new file mode 100644 index 00000000..d115d3bc --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/spi_s_pkg/src/spi_s2reg_adapter.svh @@ -0,0 +1,100 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: +// This file contains the UVM register adapter for the spi_s interface. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +`ifndef SPI_S2REG_ADAPTER +`define SPI_S2REG_ADAPTER +class spi_s2reg_adapter extends uvm_reg_adapter; + + `uvm_object_utils( spi_s2reg_adapter ) + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + //-------------------------------------------------------------------- + // new + //-------------------------------------------------------------------- + function new (string name = "spi_s2reg_adapter" ); + super.new(name); + // pragma uvmf custom new begin + // UVMF_CHANGE_ME : Configure the adapter regarding byte enables and provides response. + + // Does the protocol the Agent is modeling support byte enables? + // 0 = NO + // 1 = YES + supports_byte_enable = 0; + + // Does the Agent's Driver provide separate response sequence items? + // i.e. Does the driver call seq_item_port.put() + // and do the sequences call get_response()? + // 0 = NO + // 1 = YES + provides_responses = 0; + // pragma uvmf custom new end + + endfunction: new + + //-------------------------------------------------------------------- + // reg2bus + //-------------------------------------------------------------------- + virtual function uvm_sequence_item reg2bus(const ref uvm_reg_bus_op rw); + + spi_s_transaction trans_h = spi_s_transaction ::type_id::create("trans_h"); + + // pragma uvmf custom reg2bus begin + // UVMF_CHANGE_ME : Fill in the reg2bus adapter mapping registe fields to protocol fields. + + //Adapt the following for your sequence item type + // trans_h.op = (rw.kind == UVM_READ) ? WB_READ : WB_WRITE; + //Copy over address + // trans_h.addr = rw.addr; + //Copy over write data + // trans_h.data = rw.data; + + // pragma uvmf custom reg2bus end + + // Return the adapted transaction + return trans_h; + + endfunction: reg2bus + + //-------------------------------------------------------------------- + // bus2reg + //-------------------------------------------------------------------- + virtual function void bus2reg(uvm_sequence_item bus_item, + ref uvm_reg_bus_op rw); + spi_s_transaction trans_h; + if (!$cast(trans_h, bus_item)) begin + `uvm_fatal("ADAPT","Provided bus_item is not of the correct type") + return; + end + // pragma uvmf custom bus2reg begin + // UVMF_CHANGE_ME : Fill in the bus2reg adapter mapping protocol fields to register fields. + //Adapt the following for your sequence item type + //Copy over instruction type + // rw.kind = (trans_h.op == WB_WRITE) ? UVM_WRITE : UVM_READ; + //Copy over address + // rw.addr = trans_h.addr; + //Copy over read data + // rw.data = trans_h.data; + //Check for errors on the bus and return UVM_NOT_OK if there is an error + // rw.status = UVM_IS_OK; + // pragma uvmf custom bus2reg end + + endfunction: bus2reg + +endclass : spi_s2reg_adapter + +// pragma uvmf custom external begin +// pragma uvmf custom external end +`endif diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/spi_s_pkg/src/spi_s_agent.svh b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/spi_s_pkg/src/spi_s_agent.svh new file mode 100644 index 00000000..dc77b9e6 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/spi_s_pkg/src/spi_s_agent.svh @@ -0,0 +1,58 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: Protocol specific agent class definition +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// + +`ifndef SPI_S_AGENT +`define SPI_S_AGENT + +class spi_s_agent extends uvmf_parameterized_agent #( + .CONFIG_T(spi_s_configuration ), + .DRIVER_T(spi_s_driver ), + .MONITOR_T(spi_s_monitor ), + .COVERAGE_T(spi_s_transaction_coverage ), + .TRANS_T(spi_s_transaction ) + ); + + `uvm_component_utils( spi_s_agent ) + +// pragma uvmf custom class_item_additional begin +// pragma uvmf custom class_item_additional end + +// **************************************************************************** +// FUNCTION : new() +// This function is the standard SystemVerilog constructor. +// + function new( string name = "", uvm_component parent = null ); + super.new( name, parent ); + endfunction + +// **************************************************************************** + // FUNCTION: build_phase + virtual function void build_phase(uvm_phase phase); +// pragma uvmf custom build_phase_pre_super begin +// pragma uvmf custom build_phase_pre_super end + super.build_phase(phase); + if (configuration.active_passive == ACTIVE) begin + // Place sequencer handle into configuration object + // so that it may be retrieved from configuration + // rather than using uvm_config_db + configuration.sequencer = this.sequencer; + end + endfunction + +endclass + + +// pragma uvmf custom external begin +// pragma uvmf custom external end +`endif diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/spi_s_pkg/src/spi_s_configuration.svh b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/spi_s_pkg/src/spi_s_configuration.svh new file mode 100644 index 00000000..cd9bd9e9 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/spi_s_pkg/src/spi_s_configuration.svh @@ -0,0 +1,182 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This class contains all variables and functions used +// to configure the spi_s agent and its bfm's. It gets the +// bfm's from the uvm_config_db for use by the agent. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// + +`ifndef SPI_S_CONFIGURATION +`define SPI_S_CONFIGURATION +class spi_s_configuration extends uvmf_parameterized_agent_configuration_base #( + .DRIVER_BFM_BIND_T(virtual spi_s_driver_bfm ), + .MONITOR_BFM_BIND_T( virtual spi_s_monitor_bfm )); + + `uvm_object_utils( spi_s_configuration ) + + + // Sequencer handle populated by agent + uvm_sequencer #(spi_s_transaction ) sequencer; + + //Constraints for the configuration variables: + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + covergroup spi_s_configuration_cg; + // pragma uvmf custom covergroup begin + option.auto_bin_max=1024; + // pragma uvmf custom covergroup end + endgroup + + //******************************************************************* + //******************************************************************* + // Structure used to pass configuration variables to monitor and driver BFM's. + // Use to_struct function to pack variables into structure. + // Use from_struct function to unpack variables from structure. + // This structure is defined in spi_s_macros.svh + `spi_s_CONFIGURATION_STRUCT + spi_s_configuration_s spi_s_configuration_struct; + //******************************************************************* + // FUNCTION: to_struct() + // This function packs variables into a spi_s_configuration_s + // structure. The function returns the handle to the spi_s_configuration_struct. + // This function is defined in spi_s_macros.svh + `spi_s_CONFIGURATION_TO_STRUCT_FUNCTION + //******************************************************************* + // FUNCTION: from_struct() + // This function unpacks the struct provided as an argument into + // variables of this class. + // This function is defined in spi_s_macros.svh + `spi_s_CONFIGURATION_FROM_STRUCT_FUNCTION + + // **************************************************************************** + // FUNCTION : new() + // This function is the standard SystemVerilog constructor. + // + function new( string name = "" ); + super.new( name ); + // Construct the covergroup for this configuration class + spi_s_configuration_cg = new; + endfunction + + // **************************************************************************** + // FUNCTION: post_randomize() + // This function is automatically called after the randomize() function + // is executed. + // + function void post_randomize(); + super.post_randomize(); + spi_s_configuration_cg.sample(); + endfunction + + // **************************************************************************** + // FUNCTION: initialize + // This function causes the configuration to retrieve + // its virtual interface handle from the uvm_config_db. + // This function also makes itself available to its + // agent through the uvm_config_db. + // + // ARGUMENTS: + // uvmf_active_passive_t activity: + // This argument identifies the simulation level + // as either BLOCK, CHIP, SIMULATION, etc. + // + // AGENT_PATH: + // This argument identifies the path to this + // configurations agent. This configuration + // makes itself available to the agent specified + // by agent_path by placing itself into the + // uvm_config_db. + // + // INTERFACE_NAME: + // This argument identifies the string name of + // this configurations BFM's. This string + // name is used to retrieve the driver and + // monitor BFM from the uvm_config_db. + // + virtual function void initialize(uvmf_active_passive_t activity, + string agent_path, + string interface_name); + + super.initialize( activity, agent_path, interface_name); + // The covergroup is given the same name as the interface + spi_s_configuration_cg.set_inst_name(interface_name); + + // This configuration places itself into the uvm_config_db for the agent, identified by the agent_path variable, to retrieve. + uvm_config_db #( spi_s_configuration + )::set( null ,agent_path,UVMF_AGENT_CONFIG, this ); + + // This configuration also places itself in the config db using the same identifier used by the interface. This allows users to access + // configuration variables and the interface through the bfm api class rather than directly accessing the BFM. This is useful for + // accessingthe BFM when using Veloce + uvm_config_db #( spi_s_configuration + )::set( null ,UVMF_CONFIGURATIONS, interface_name, this ); + + spi_s_configuration_cg.set_inst_name($sformatf("spi_s_configuration_cg_%s",get_full_name())); + +// This code is to aid in debugging parameter mismatches between the BFM and its corresponding agent. +// Enable this debug by setting UVM_VERBOSITY to UVM_DEBUG +// Setting UVM_VERBOSITY to UVM_DEBUG causes all BFM's and all agents to display their parameter settings. +// All of the messages from this feature have a UVM messaging id value of "CFG" +// The transcript or run.log can be parsed to ensure BFM parameter settings match its corresponding agents parameter settings. + `uvm_info("CFG", + $psprintf("The agent at '%s' is using interface named %s has the following parameters: ", agent_path, interface_name, ), + UVM_DEBUG) + + // pragma uvmf custom initialize begin + // This controls whether or not the agent returns a transaction handle in the driver when calling + // item_done() back into the sequencer or not. If set to 1, a transaction is sent back which means + // the sequence on the other end must use the get_response() part of the driver/sequence API. If + // this doesn't occur, there will eventually be response_queue overflow errors during the test. + return_transaction_response = 1'b0; + + // pragma uvmf custom initialize end + + endfunction + + // **************************************************************************** + // TASK: wait_for_reset + // *[Required]* Blocks until reset is released. The wait_for_reset operation is performed + // by a task in the monitor bfm. + virtual task wait_for_reset(); + monitor_bfm.wait_for_reset(); + endtask + + // **************************************************************************** + // TASK: wait_for_num_clocks + // *[Required]* Blocks until specified number of clocks have elapsed. The wait_for_num_clocks + // operation is performed by a task in the monitor bfm. + virtual task wait_for_num_clocks(int clocks); + monitor_bfm.wait_for_num_clocks(clocks); + endtask + + // **************************************************************************** + // FUNCTION : convert2string() + // This function is used to convert variables in this class into a string for log messaging. + // + virtual function string convert2string (); + // pragma uvmf custom convert2string begin + return $sformatf(""); + // pragma uvmf custom convert2string end + endfunction + + // **************************************************************************** + // FUNCTION: get_sequencer + function uvm_sequencer #(spi_s_transaction) get_sequencer(); + return sequencer; + endfunction + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end +`endif diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/spi_s_pkg/src/spi_s_driver.svh b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/spi_s_pkg/src/spi_s_driver.svh new file mode 100644 index 00000000..4a3165a4 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/spi_s_pkg/src/spi_s_driver.svh @@ -0,0 +1,93 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This class passes transactions between the sequencer +// and the BFM driver interface. It accesses the driver BFM +// through the bfm handle. This driver +// passes transactions to the driver BFM through the access +// task. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +`ifndef SPI_S_DRIVER +`define SPI_S_DRIVER +class spi_s_driver extends uvmf_driver_base #( + .CONFIG_T(spi_s_configuration ), + .BFM_BIND_T(virtual spi_s_driver_bfm ), + .REQ(spi_s_transaction ), + .RSP(spi_s_transaction )); + + `uvm_component_utils( spi_s_driver ) +//******************************************************************* +// Macros that define structs located in spi_s_macros.svh +//******************************************************************* +// Initiator macro used by spi_s_driver and spi_s_driver_bfm +// to communicate initiator driven data to spi_s_driver_bfm. +`spi_s_INITIATOR_STRUCT + spi_s_initiator_s spi_s_initiator_struct; +//******************************************************************* +// Responder macro used by spi_s_driver and spi_s_driver_bfm +// to communicate Responder driven data to spi_s_driver_bfm. +`spi_s_RESPONDER_STRUCT + spi_s_responder_s spi_s_responder_struct; + +// pragma uvmf custom class_item_additional begin +// pragma uvmf custom class_item_additional end + +// **************************************************************************** +// This function is the standard SystemVerilog constructor. +// + function new( string name = "", uvm_component parent=null ); + super.new( name, parent ); + endfunction + +// **************************************************************************** +// This function sends configuration object variables to the driver BFM +// using the configuration struct. +// + virtual function void configure(input CONFIG_T cfg); + bfm.configure( cfg.to_struct() ); + endfunction + +// **************************************************************************** +// This function places a handle to this class in the proxy variable in the +// driver BFM. This allows the driver BFM to call tasks and function within this class. +// + virtual function void set_bfm_proxy_handle(); + bfm.proxy = this; endfunction + +// **************************************************************************** +// This task is called by the run_phase in uvmf_driver_base. + virtual task access( inout REQ txn ); +// pragma uvmf custom access begin + if (configuration.initiator_responder==RESPONDER) begin + // Complete current transfer and wait for next transfer + bfm.respond_and_wait_for_next_transfer( + spi_s_initiator_struct, + txn.to_responder_struct() + ); + // Unpack information about initiated transfer received by this responder + txn.from_initiator_struct(spi_s_initiator_struct); + end else begin + // Initiate a transfer and get response + bfm.initiate_and_get_response( + txn.to_initiator_struct(), + spi_s_responder_struct + ); + // Unpack transfer response information received by this initiator + txn.from_responder_struct(spi_s_responder_struct); + end +// pragma uvmf custom access end + endtask + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end +`endif diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/spi_s_pkg/src/spi_s_driver_bfm.sv b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/spi_s_pkg/src/spi_s_driver_bfm.sv new file mode 100644 index 00000000..5d593ee3 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/spi_s_pkg/src/spi_s_driver_bfm.sv @@ -0,0 +1,300 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: +// This interface performs the spi_s signal driving. It is +// accessed by the uvm spi_s driver through a virtual interface +// handle in the spi_s configuration. It drives the singals passed +// in through the port connection named bus of type spi_s_if. +// +// Input signals from the spi_s_if are assigned to an internal input +// signal with a _i suffix. The _i signal should be used for sampling. +// +// The input signal connections are as follows: +// bus.signal -> signal_i +// +// This bfm drives signals with a _o suffix. These signals +// are driven onto signals within spi_s_if based on INITIATOR/RESPONDER and/or +// ARBITRATION/GRANT status. +// +// The output signal connections are as follows: +// signal_o -> bus.signal +// +// +// Interface functions and tasks used by UVM components: +// +// configure: +// This function gets configuration attributes from the +// UVM driver to set any required BFM configuration +// variables such as 'initiator_responder'. +// +// initiate_and_get_response: +// This task is used to perform signaling activity for initiating +// a protocol transfer. The task initiates the transfer, using +// input data from the initiator struct. Then the task captures +// response data, placing the data into the response struct. +// The response struct is returned to the driver class. +// +// respond_and_wait_for_next_transfer: +// This task is used to complete a current transfer as a responder +// and then wait for the initiator to start the next transfer. +// The task uses data in the responder struct to drive protocol +// signals to complete the transfer. The task then waits for +// the next transfer. Once the next transfer begins, data from +// the initiator is placed into the initiator struct and sent +// to the responder sequence for processing to determine +// what data to respond with. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +import uvmf_base_pkg_hdl::*; +import spi_s_pkg_hdl::*; +`include "src/spi_s_macros.svh" + +interface spi_s_driver_bfm + (spi_s_if bus); + // The following pragma and additional ones in-lined further below are for running this BFM on Veloce + // pragma attribute spi_s_driver_bfm partition_interface_xif + +`ifndef XRTL +// This code is to aid in debugging parameter mismatches between the BFM and its corresponding agent. +// Enable this debug by setting UVM_VERBOSITY to UVM_DEBUG +// Setting UVM_VERBOSITY to UVM_DEBUG causes all BFM's and all agents to display their parameter settings. +// All of the messages from this feature have a UVM messaging id value of "CFG" +// The transcript or run.log can be parsed to ensure BFM parameter settings match its corresponding agents parameter settings. +import uvm_pkg::*; +`include "uvm_macros.svh" +initial begin : bfm_vs_agent_parameter_debug + `uvm_info("CFG", + $psprintf("The BFM at '%m' has the following parameters: ", ), + UVM_DEBUG) +end +`endif + + // Config value to determine if this is an initiator or a responder + uvmf_initiator_responder_t initiator_responder; + // Custom configuration variables. + // These are set using the configure function which is called during the UVM connect_phase + + logic sck_i; + logic rst_i; + + // Signal list (all signals are capable of being inputs and outputs for the sake + // of supporting both INITIATOR and RESPONDER mode operation. Expectation is that + // directionality in the config file was from the point-of-view of the INITIATOR + + // INITIATOR mode input signals + tri sclk_i; + reg sclk_o = 'b0; + tri ss_i; + reg ss_o = 'b0; + tri [7:0] mosi_i; + reg [7:0] mosi_o = 'b0; + + // INITIATOR mode output signals + tri [7:0] miso_i; + reg [7:0] miso_o = 'b0; + + // Bi-directional signals + + + assign sck_i = bus.sck; + assign rst_i = bus.rst; + + // These are signals marked as 'input' by the config file, but the signals will be + // driven by this BFM if put into RESPONDER mode (flipping all signal directions around) + assign sclk_i = bus.sclk; + assign bus.sclk = (initiator_responder == RESPONDER) ? sclk_o : 'bz; + assign ss_i = bus.ss; + assign bus.ss = (initiator_responder == RESPONDER) ? ss_o : 'bz; + assign mosi_i = bus.mosi; + assign bus.mosi = (initiator_responder == RESPONDER) ? mosi_o : 'bz; + + + // These are signals marked as 'output' by the config file, but the outputs will + // not be driven by this BFM unless placed in INITIATOR mode. + assign bus.miso = (initiator_responder == INITIATOR) ? miso_o : 'bz; + assign miso_i = bus.miso; + + // Proxy handle to UVM driver + spi_s_pkg::spi_s_driver proxy; + // pragma tbx oneway proxy.my_function_name_in_uvm_driver + + // **************************************************************************** + // **************************************************************************** + // Macros that define structs located in spi_s_macros.svh + // **************************************************************************** + // Struct for passing configuration data from spi_s_driver to this BFM + // **************************************************************************** + `spi_s_CONFIGURATION_STRUCT + // **************************************************************************** + // Structs for INITIATOR and RESPONDER data flow + //******************************************************************* + // Initiator macro used by spi_s_driver and spi_s_driver_bfm + // to communicate initiator driven data to spi_s_driver_bfm. + `spi_s_INITIATOR_STRUCT + spi_s_initiator_s initiator_struct; + // Responder macro used by spi_s_driver and spi_s_driver_bfm + // to communicate Responder driven data to spi_s_driver_bfm. + `spi_s_RESPONDER_STRUCT + spi_s_responder_s responder_struct; + + // **************************************************************************** +// pragma uvmf custom reset_condition_and_response begin + // Always block used to return signals to reset value upon assertion of reset + always @( posedge rst_i ) + begin + // RESPONDER mode output signals + sclk_o <= 'b0; + ss_o <= 'b0; + mosi_o <= 'b0; + // INITIATOR mode output signals + miso_o <= 'b0; + // Bi-directional signals + + end +// pragma uvmf custom reset_condition_and_response end + + // pragma uvmf custom interface_item_additional begin + // pragma uvmf custom interface_item_additional end + + //****************************************************************** + // The configure() function is used to pass agent configuration + // variables to the driver BFM. It is called by the driver within + // the agent at the beginning of the simulation. It may be called + // during the simulation if agent configuration variables are updated + // and the driver BFM needs to be aware of the new configuration + // variables. + // + + function void configure(spi_s_configuration_s spi_s_configuration_arg); // pragma tbx xtf + initiator_responder = spi_s_configuration_arg.initiator_responder; + // pragma uvmf custom configure begin + // pragma uvmf custom configure end + endfunction + +// pragma uvmf custom initiate_and_get_response begin +// **************************************************************************** +// UVMF_CHANGE_ME +// This task is used by an initator. The task first initiates a transfer then +// waits for the responder to complete the transfer. + task initiate_and_get_response( + // This argument passes transaction variables used by an initiator + // to perform the initial part of a protocol transfer. The values + // come from a sequence item created in a sequence. + input spi_s_initiator_s spi_s_initiator_struct, + // This argument is used to send data received from the responder + // back to the sequence item. The sequence item is returned to the sequence. + output spi_s_responder_s spi_s_responder_struct + );// pragma tbx xtf + // + // Members within the spi_s_initiator_struct: + // bit ssel ; + // bit [7:0] mosi ; + // bit [7:0] miso ; + // Members within the spi_s_responder_struct: + // bit ssel ; + // bit [7:0] mosi ; + // bit [7:0] miso ; + initiator_struct = spi_s_initiator_struct; + // + // Reference code; + // How to wait for signal value + // while (control_signal == 1'b1) @(posedge sck_i); + // + // How to assign a responder struct member, named xyz, from a signal. + // All available initiator input and inout signals listed. + // Initiator input signals + // spi_s_responder_struct.xyz = sclk_i; // + // spi_s_responder_struct.xyz = ss_i; // + // spi_s_responder_struct.xyz = mosi_i; // [7:0] + // Initiator inout signals + // How to assign a signal from an initiator struct member named xyz. + // All available initiator output and inout signals listed. + // Notice the _o. Those are storage variables that allow for procedural assignment. + // Initiator output signals + // miso_o <= spi_s_initiator_struct.xyz; // [7:0] + // Initiator inout signals + // Initiate a transfer using the data received. + @(posedge sck_i); + @(posedge sck_i); + // Wait for the responder to complete the transfer then place the responder data into + // spi_s_responder_struct. + @(posedge sck_i); + @(posedge sck_i); + responder_struct = spi_s_responder_struct; + endtask +// pragma uvmf custom initiate_and_get_response end + +// pragma uvmf custom respond_and_wait_for_next_transfer begin +// **************************************************************************** +// The first_transfer variable is used to prevent completing a transfer in the +// first call to this task. For the first call to this task, there is not +// current transfer to complete. +bit first_transfer=1; + +// UVMF_CHANGE_ME +// This task is used by a responder. The task first completes the current +// transfer in progress then waits for the initiator to start the next transfer. + task respond_and_wait_for_next_transfer( + // This argument is used to send data received from the initiator + // back to the sequence item. The sequence determines how to respond. + output spi_s_initiator_s spi_s_initiator_struct, + // This argument passes transaction variables used by a responder + // to complete a protocol transfer. The values come from a sequence item. + input spi_s_responder_s spi_s_responder_struct + );// pragma tbx xtf + // Variables within the spi_s_initiator_struct: + // bit ssel ; + // bit [7:0] mosi ; + // bit [7:0] miso ; + // Variables within the spi_s_responder_struct: + // bit ssel ; + // bit [7:0] mosi ; + // bit [7:0] miso ; + // Reference code; + // How to wait for signal value + // while (control_signal == 1'b1) @(posedge sck_i); + // + // How to assign a responder struct member, named xyz, from a signal. + // All available responder input and inout signals listed. + // Responder input signals + // spi_s_responder_struct.xyz = miso_i; // [7:0] + // Responder inout signals + // How to assign a signal, named xyz, from an initiator struct member. + // All available responder output and inout signals listed. + // Notice the _o. Those are storage variables that allow for procedural assignment. + // Responder output signals + // sclk_o <= spi_s_initiator_struct.xyz; // + // ss_o <= spi_s_initiator_struct.xyz; // + // mosi_o <= spi_s_initiator_struct.xyz; // [7:0] + // Responder inout signals + + @(posedge sck_i); + if (!first_transfer) begin + // Perform transfer response here. + // Reply using data recieved in the spi_s_responder_struct. + @(posedge sck_i); + // Reply using data recieved in the transaction handle. + @(posedge sck_i); + end + // Wait for next transfer then gather info from intiator about the transfer. + // Place the data into the spi_s_initiator_struct. + @(posedge sck_i); + @(posedge sck_i); + first_transfer = 0; + endtask +// pragma uvmf custom respond_and_wait_for_next_transfer end + + +endinterface + +// pragma uvmf custom external begin +// pragma uvmf custom external end +`endif diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/spi_s_pkg/src/spi_s_if.sv b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/spi_s_pkg/src/spi_s_if.sv new file mode 100644 index 00000000..9161fc4b --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/spi_s_pkg/src/spi_s_if.sv @@ -0,0 +1,81 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This interface contains the spi_s interface signals. +// It is instantiated once per spi_s bus. Bus Functional Models, +// BFM's named spi_s_driver_bfm, are used to drive signals on the bus. +// BFM's named spi_s_monitor_bfm are used to monitor signals on the +// bus. This interface signal bundle is passed in the port list of +// the BFM in order to give the BFM access to the signals in this +// interface. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +`ifndef SPI_S_IF +`define SPI_S_IF +// This template can be used to connect a DUT to these signals +// +// .dut_signal_port(spi_s_bus.sclk), // Agent input +// .dut_signal_port(spi_s_bus.ss), // Agent input +// .dut_signal_port(spi_s_bus.mosi), // Agent input +// .dut_signal_port(spi_s_bus.miso), // Agent output + +import uvmf_base_pkg_hdl::*; +import spi_s_pkg_hdl::*; + +interface spi_s_if + + ( + input logic sck, + input logic rst, + input logic sclk, + input logic ss, + input logic [7:0] mosi, + output logic [7:0] miso + ); + +modport monitor_port + ( + input sck, + input rst, + input sclk, + input ss, + input mosi, + input miso + ); + +modport initiator_port + ( + input sck, + input rst, + input sclk, + input ss, + input mosi, + output miso + ); + +modport responder_port + ( + input sck, + input rst, + output sclk, + output ss, + output mosi, + input miso + ); + + +// pragma uvmf custom interface_item_additional begin +// pragma uvmf custom interface_item_additional end + +endinterface + +// pragma uvmf custom external begin +// pragma uvmf custom external end +`endif diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/spi_s_pkg/src/spi_s_infact_coverage_strategy.csv b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/spi_s_pkg/src/spi_s_infact_coverage_strategy.csv new file mode 100644 index 00000000..1c218e14 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/spi_s_pkg/src/spi_s_infact_coverage_strategy.csv @@ -0,0 +1,6 @@ +Global +auto_bin_max, 64 + +Name,Type,Include +rand_fields,coverpoint,=rand *.** + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/spi_s_pkg/src/spi_s_macros.svh b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/spi_s_pkg/src/spi_s_macros.svh new file mode 100644 index 00000000..cbf12ff6 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/spi_s_pkg/src/spi_s_macros.svh @@ -0,0 +1,139 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This file contains macros used with the spi_s package. +// These macros include packed struct definitions. These structs are +// used to pass data between classes, hvl, and BFM's, hdl. Use of +// structs are more efficient and simpler to modify. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// + +// **************************************************************************** +// When changing the contents of this struct, be sure to update the to_struct +// and from_struct methods defined in the macros below that are used in +// the spi_s_configuration class. +// + `define spi_s_CONFIGURATION_STRUCT \ +typedef struct packed { \ + uvmf_active_passive_t active_passive; \ + uvmf_initiator_responder_t initiator_responder; \ + } spi_s_configuration_s; + + `define spi_s_CONFIGURATION_TO_STRUCT_FUNCTION \ + virtual function spi_s_configuration_s to_struct();\ + spi_s_configuration_struct = \ + {\ + this.active_passive,\ + this.initiator_responder\ + };\ + return ( spi_s_configuration_struct );\ + endfunction + + `define spi_s_CONFIGURATION_FROM_STRUCT_FUNCTION \ + virtual function void from_struct(spi_s_configuration_s spi_s_configuration_struct);\ + {\ + this.active_passive,\ + this.initiator_responder \ + } = spi_s_configuration_struct;\ + endfunction + +// **************************************************************************** +// When changing the contents of this struct, be sure to update the to_monitor_struct +// and from_monitor_struct methods of the spi_s_transaction class. +// + `define spi_s_MONITOR_STRUCT typedef struct packed { \ + bit ssel ; \ + bit [7:0] mosi ; \ + bit [7:0] miso ; \ + } spi_s_monitor_s; + + `define spi_s_TO_MONITOR_STRUCT_FUNCTION \ + virtual function spi_s_monitor_s to_monitor_struct();\ + spi_s_monitor_struct = \ + { \ + this.ssel , \ + this.mosi , \ + this.miso \ + };\ + return ( spi_s_monitor_struct);\ + endfunction\ + + `define spi_s_FROM_MONITOR_STRUCT_FUNCTION \ + virtual function void from_monitor_struct(spi_s_monitor_s spi_s_monitor_struct);\ + {\ + this.ssel , \ + this.mosi , \ + this.miso \ + } = spi_s_monitor_struct;\ + endfunction + +// **************************************************************************** +// When changing the contents of this struct, be sure to update the to_initiator_struct +// and from_initiator_struct methods of the spi_s_transaction class. +// Also update the comments in the driver BFM. +// + `define spi_s_INITIATOR_STRUCT typedef struct packed { \ + bit ssel ; \ + bit [7:0] mosi ; \ + bit [7:0] miso ; \ + } spi_s_initiator_s; + + `define spi_s_TO_INITIATOR_STRUCT_FUNCTION \ + virtual function spi_s_initiator_s to_initiator_struct();\ + spi_s_initiator_struct = \ + {\ + this.ssel , \ + this.mosi , \ + this.miso \ + };\ + return ( spi_s_initiator_struct);\ + endfunction + + `define spi_s_FROM_INITIATOR_STRUCT_FUNCTION \ + virtual function void from_initiator_struct(spi_s_initiator_s spi_s_initiator_struct);\ + {\ + this.ssel , \ + this.mosi , \ + this.miso \ + } = spi_s_initiator_struct;\ + endfunction + +// **************************************************************************** +// When changing the contents of this struct, be sure to update the to_responder_struct +// and from_responder_struct methods of the spi_s_transaction class. +// Also update the comments in the driver BFM. +// + `define spi_s_RESPONDER_STRUCT typedef struct packed { \ + bit ssel ; \ + bit [7:0] mosi ; \ + bit [7:0] miso ; \ + } spi_s_responder_s; + + `define spi_s_TO_RESPONDER_STRUCT_FUNCTION \ + virtual function spi_s_responder_s to_responder_struct();\ + spi_s_responder_struct = \ + {\ + this.ssel , \ + this.mosi , \ + this.miso \ + };\ + return ( spi_s_responder_struct);\ + endfunction + + `define spi_s_FROM_RESPONDER_STRUCT_FUNCTION \ + virtual function void from_responder_struct(spi_s_responder_s spi_s_responder_struct);\ + {\ + this.ssel , \ + this.mosi , \ + this.miso \ + } = spi_s_responder_struct;\ + endfunction +// pragma uvmf custom additional begin +// pragma uvmf custom additional end diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/spi_s_pkg/src/spi_s_monitor.svh b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/spi_s_pkg/src/spi_s_monitor.svh new file mode 100644 index 00000000..20d9ff75 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/spi_s_pkg/src/spi_s_monitor.svh @@ -0,0 +1,89 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This class receives spi_s transactions observed by the +// spi_s monitor BFM and broadcasts them through the analysis port +// on the agent. It accesses the monitor BFM through the monitor +// task. This UVM component captures transactions +// for viewing in the waveform viewer if the +// enable_transaction_viewing flag is set in the configuration. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +`ifndef SPI_S_MONITOR +`define SPI_S_MONITOR +class spi_s_monitor extends uvmf_monitor_base #( + .CONFIG_T(spi_s_configuration ), + .BFM_BIND_T(virtual spi_s_monitor_bfm ), + .TRANS_T(spi_s_transaction )); + + `uvm_component_utils( spi_s_monitor ) + +// Structure used to pass data from monitor BFM to monitor class in agent. +// Use to_monitor_struct function to pack transaction variables into structure. +// Use from_monitor_struct function to unpack transaction variables from structure. +`spi_s_MONITOR_STRUCT + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + +// **************************************************************************** +// This function is the standard SystemVerilog constructor. +// + function new( string name = "", uvm_component parent = null ); + super.new( name, parent ); + endfunction + +// **************************************************************************** +// This function sends configuration object variables to the monitor BFM +// using the configuration struct. +// + virtual function void configure(input CONFIG_T cfg); + bfm.configure( cfg.to_struct() ); + + endfunction + +// **************************************************************************** +// This function places a handle to this class in the proxy variable in the +// monitor BFM. This allows the monitor BFM to call the notify_transaction +// function within this class. +// + virtual function void set_bfm_proxy_handle(); + bfm.proxy = this; endfunction + +// *************************************************************************** + virtual task run_phase(uvm_phase phase); + // Start monitor BFM thread and don't call super.run() in order to + // override the default monitor proxy 'pull' behavior with the more + // emulation-friendly BFM 'push' approach using the notify_transaction + // function below + bfm.start_monitoring(); + endtask + +// ************************************************************************** + +// This function is called by the monitor BFM. It receives data observed by the +// monitor BFM. Data is passed using the spi_s_monitor_struct. + virtual function void notify_transaction(input spi_s_monitor_s spi_s_monitor_struct); + + + trans = new("trans"); + trans.from_monitor_struct(spi_s_monitor_struct); + trans.start_time = time_stamp; + trans.end_time = $time; + time_stamp = trans.end_time; + + analyze(trans); + endfunction + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end +`endif diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/spi_s_pkg/src/spi_s_monitor_bfm.sv b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/spi_s_pkg/src/spi_s_monitor_bfm.sv new file mode 100644 index 00000000..96ccc00e --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/spi_s_pkg/src/spi_s_monitor_bfm.sv @@ -0,0 +1,187 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This interface performs the spi_s signal monitoring. +// It is accessed by the uvm spi_s monitor through a virtual +// interface handle in the spi_s configuration. It monitors the +// signals passed in through the port connection named bus of +// type spi_s_if. +// +// Input signals from the spi_s_if are assigned to an internal input +// signal with a _i suffix. The _i signal should be used for sampling. +// +// The input signal connections are as follows: +// bus.signal -> signal_i +// +// Interface functions and tasks used by UVM components: +// monitor(inout TRANS_T txn); +// This task receives the transaction, txn, from the +// UVM monitor and then populates variables in txn +// from values observed on bus activity. This task +// blocks until an operation on the spi_s bus is complete. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +`ifndef SPI_S_MONITOR_BFM +`define SPI_S_MONITOR_BFM +import uvmf_base_pkg_hdl::*; +import spi_s_pkg_hdl::*; +`include "src/spi_s_macros.svh" + + +interface spi_s_monitor_bfm + ( spi_s_if bus ); + // The pragma below and additional ones in-lined further down are for running this BFM on Veloce + // pragma attribute spi_s_monitor_bfm partition_interface_xif + +`ifndef XRTL +// This code is to aid in debugging parameter mismatches between the BFM and its corresponding agent. +// Enable this debug by setting UVM_VERBOSITY to UVM_DEBUG +// Setting UVM_VERBOSITY to UVM_DEBUG causes all BFM's and all agents to display their parameter settings. +// All of the messages from this feature have a UVM messaging id value of "CFG" +// The transcript or run.log can be parsed to ensure BFM parameter settings match its corresponding agents parameter settings. +import uvm_pkg::*; +`include "uvm_macros.svh" +initial begin : bfm_vs_agent_parameter_debug + `uvm_info("CFG", + $psprintf("The BFM at '%m' has the following parameters: ", ), + UVM_DEBUG) +end +`endif + + + // Structure used to pass transaction data from monitor BFM to monitor class in agent. +`spi_s_MONITOR_STRUCT + spi_s_monitor_s spi_s_monitor_struct; + + // Structure used to pass configuration data from monitor class to monitor BFM. + `spi_s_CONFIGURATION_STRUCT + + + // Config value to determine if this is an initiator or a responder + uvmf_initiator_responder_t initiator_responder; + // Custom configuration variables. + // These are set using the configure function which is called during the UVM connect_phase + + logic sck_i; + logic rst_i; + tri sclk_i; + tri ss_i; + tri [7:0] mosi_i; + tri [7:0] miso_i; + assign sck_i = bus.sck; + assign rst_i = bus.rst; + assign sclk_i = bus.sclk; + assign ss_i = bus.ss; + assign mosi_i = bus.mosi; + assign miso_i = bus.miso; + + // Proxy handle to UVM monitor + spi_s_pkg::spi_s_monitor proxy; + // pragma tbx oneway proxy.notify_transaction + + // pragma uvmf custom interface_item_additional begin + // pragma uvmf custom interface_item_additional end + + //****************************************************************** + task wait_for_reset();// pragma tbx xtf + @(posedge sck_i) ; + do_wait_for_reset(); + endtask + + // **************************************************************************** + task do_wait_for_reset(); + // pragma uvmf custom reset_condition begin + wait ( rst_i === 0 ) ; + @(posedge sck_i) ; + // pragma uvmf custom reset_condition end + endtask + + //****************************************************************** + + task wait_for_num_clocks(input int unsigned count); // pragma tbx xtf + @(posedge sck_i); + + repeat (count-1) @(posedge sck_i); + endtask + + //****************************************************************** + event go; + function void start_monitoring();// pragma tbx xtf + -> go; + endfunction + + // **************************************************************************** + initial begin + @go; + forever begin + @(posedge sck_i); + do_monitor( spi_s_monitor_struct ); + + + proxy.notify_transaction( spi_s_monitor_struct ); + + end + end + + //****************************************************************** + // The configure() function is used to pass agent configuration + // variables to the monitor BFM. It is called by the monitor within + // the agent at the beginning of the simulation. It may be called + // during the simulation if agent configuration variables are updated + // and the monitor BFM needs to be aware of the new configuration + // variables. + // + function void configure(spi_s_configuration_s spi_s_configuration_arg); // pragma tbx xtf + initiator_responder = spi_s_configuration_arg.initiator_responder; + // pragma uvmf custom configure begin + // pragma uvmf custom configure end + endfunction + + + // **************************************************************************** + + task do_monitor(output spi_s_monitor_s spi_s_monitor_struct); + // + // Available struct members: + // // spi_s_monitor_struct.ssel + // // spi_s_monitor_struct.mosi + // // spi_s_monitor_struct.miso + // // + // Reference code; + // How to wait for signal value + // while (control_signal === 1'b1) @(posedge sck_i); + // + // How to assign a struct member, named xyz, from a signal. + // All available input signals listed. + // spi_s_monitor_struct.xyz = sclk_i; // + // spi_s_monitor_struct.xyz = ss_i; // + // spi_s_monitor_struct.xyz = mosi_i; // [7:0] + // spi_s_monitor_struct.xyz = miso_i; // [7:0] + // pragma uvmf custom do_monitor begin + // UVMF_CHANGE_ME : Implement protocol monitoring. The commented reference code + // below are examples of how to capture signal values and assign them to + // structure members. All available input signals are listed. The 'while' + // code example shows how to wait for a synchronous flow control signal. This + // task should return when a complete transfer has been observed. Once this task is + // exited with captured values, it is then called again to wait for and observe + // the next transfer. One clock cycle is consumed between calls to do_monitor. + @(posedge sck_i); + @(posedge sck_i); + @(posedge sck_i); + @(posedge sck_i); + // pragma uvmf custom do_monitor end + endtask + + +endinterface + +// pragma uvmf custom external begin +// pragma uvmf custom external end +`endif diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/spi_s_pkg/src/spi_s_random_sequence.svh b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/spi_s_pkg/src/spi_s_random_sequence.svh new file mode 100644 index 00000000..896de0cd --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/spi_s_pkg/src/spi_s_random_sequence.svh @@ -0,0 +1,55 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: +// This sequences randomizes the spi_s transaction and sends it +// to the UVM driver. +// +// This sequence constructs and randomizes a spi_s_transaction. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +`ifndef SPI_S_RANDOM_SEQUENCE +`define SPI_S_RANDOM_SEQUENCE +class spi_s_random_sequence + extends spi_s_sequence_base ; + + `uvm_object_utils( spi_s_random_sequence ) + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + //***************************************************************** + function new(string name = ""); + super.new(name); + endfunction: new + + // **************************************************************************** + // TASK : body() + // This task is automatically executed when this sequence is started using the + // start(sequencerHandle) task. + // + task body(); + + // Construct the transaction + req=spi_s_transaction::type_id::create("req"); + start_item(req); + // Randomize the transaction + if(!req.randomize()) `uvm_fatal("SEQ", "spi_s_random_sequence::body()-spi_s_transaction randomization failed") + // Send the transaction to the spi_s_driver_bfm via the sequencer and spi_s_driver. + finish_item(req); + `uvm_info("SEQ", {"Response:",req.convert2string()},UVM_MEDIUM) + + endtask + +endclass: spi_s_random_sequence + +// pragma uvmf custom external begin +// pragma uvmf custom external end +`endif diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/spi_s_pkg/src/spi_s_responder_sequence.svh b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/spi_s_pkg/src/spi_s_responder_sequence.svh new file mode 100644 index 00000000..5313f39a --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/spi_s_pkg/src/spi_s_responder_sequence.svh @@ -0,0 +1,51 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This class can be used to provide stimulus when an interface +// has been configured to run in a responder mode. It +// will never finish by default, always going back to the driver +// and driver BFM for the next transaction with which to respond. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +`ifndef SPI_S_RESPONDER_SEQUENCE +`define SPI_S_RESPONDER_SEQUENCE +class spi_s_responder_sequence + extends spi_s_sequence_base ; + + `uvm_object_utils( spi_s_responder_sequence ) + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + function new(string name = "spi_s_responder_sequence"); + super.new(name); + endfunction + + task body(); + req=spi_s_transaction::type_id::create("req"); + forever begin + start_item(req); + finish_item(req); + // pragma uvmf custom body begin + // UVMF_CHANGE_ME : Do something here with the resulting req item. The + // finish_item() call above will block until the req transaction is ready + // to be handled by the responder sequence. + // If this was an item that required a response, the expectation is + // that the response should be populated within this transaction now. + `uvm_info("SEQ",$sformatf("Processed txn: %s",req.convert2string()),UVM_HIGH) + // pragma uvmf custom body end + end + endtask + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end +`endif diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/spi_s_pkg/src/spi_s_sequence_base.svh b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/spi_s_pkg/src/spi_s_sequence_base.svh new file mode 100644 index 00000000..11216c25 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/spi_s_pkg/src/spi_s_sequence_base.svh @@ -0,0 +1,98 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: +// This file contains the class used as the base class for all sequences +// for this interface. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +`ifndef SPI_S_SEQUENCE_BASE +`define SPI_S_SEQUENCE_BASE +class spi_s_sequence_base extends uvmf_sequence_base #( + .REQ(spi_s_transaction ), + .RSP(spi_s_transaction )); + + `uvm_object_utils( spi_s_sequence_base ) + + // variables + typedef spi_s_transaction spi_s_transaction_req_t; + spi_s_transaction_req_t req; + typedef spi_s_transaction spi_s_transaction_rsp_t; + spi_s_transaction_rsp_t rsp; + + // Event for identifying when a response was received from the sequencer + event new_rsp; + + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + // **************************************************************************** + // TASK : get_responses() + // This task recursively gets sequence item responses from the sequencer. + // + virtual task get_responses(); + fork + begin + // Block until new rsp available + get_response(rsp); + // New rsp received. Indicate to sequence using event. + ->new_rsp; + // Display the received response transaction + `uvm_info("SEQ", {"New response transaction:",rsp.convert2string()}, UVM_MEDIUM) + end + join_none + endtask + + // **************************************************************************** + // TASK : pre_body() + // This task is called automatically when start is called with call_pre_post set to 1 (default). + // By calling get_responses() within pre_body() any derived sequences are automatically + // processing response transactions. Only un-comment this call to get_responses() if you + // have configured the interface driver to utilize the response transaction path by setting + // the configuration variable "return_transaction_response" to 1. Otherwise it is possible + // to impact runtime performance and memory utilization. + // + virtual task pre_body(); + // pragma uvmf custom pre_body begin +// get_responses(); + // pragma uvmf custom pre_body end + endtask + + // **************************************************************************** + // TASK : body() + // This task is called automatically when start is called. This sequence sends + // a req sequence item to the sequencer identified as an argument in the call + // to start. + // + virtual task body(); + // pragma uvmf custom body begin + start_item(req); + finish_item(req); + // pragma uvmf custom body end + endtask + + // **************************************************************************** + // FUNCTION : new() + // This function is the standard SystemVerilog constructor. + // + function new( string name =""); + super.new( name ); + // pragma uvmf custom new begin + req = spi_s_transaction_req_t::type_id::create("req"); + rsp = spi_s_transaction_rsp_t::type_id::create("rsp"); + // pragma uvmf custom new end + endfunction + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end +`endif diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/spi_s_pkg/src/spi_s_transaction.svh b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/spi_s_pkg/src/spi_s_transaction.svh new file mode 100644 index 00000000..eed56858 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/spi_s_pkg/src/spi_s_transaction.svh @@ -0,0 +1,192 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This class defines the variables required for an spi_s +// transaction. Class variables to be displayed in waveform transaction +// viewing are added to the transaction viewing stream in the add_to_wave +// function. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +`ifndef SPI_S_TRANSACTION +`define SPI_S_TRANSACTION +class spi_s_transaction extends uvmf_transaction_base; + + `uvm_object_utils( spi_s_transaction ) + + bit ssel ; + bit [7:0] mosi ; + rand bit [7:0] miso ; + + //Constraints for the transaction variables: + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + //******************************************************************* + //******************************************************************* + // Macros that define structs and associated functions are + // located in spi_s_macros.svh + + //******************************************************************* + // Monitor macro used by spi_s_monitor and spi_s_monitor_bfm + // This struct is defined in spi_s_macros.svh + `spi_s_MONITOR_STRUCT + spi_s_monitor_s spi_s_monitor_struct; + //******************************************************************* + // FUNCTION: to_monitor_struct() + // This function packs transaction variables into a spi_s_monitor_s + // structure. The function returns the handle to the spi_s_monitor_struct. + // This function is defined in spi_s_macros.svh + `spi_s_TO_MONITOR_STRUCT_FUNCTION + //******************************************************************* + // FUNCTION: from_monitor_struct() + // This function unpacks the struct provided as an argument into transaction + // variables of this class. + // This function is defined in spi_s_macros.svh + `spi_s_FROM_MONITOR_STRUCT_FUNCTION + + //******************************************************************* + // Initiator macro used by spi_s_driver and spi_s_driver_bfm + // to communicate initiator driven data to spi_s_driver_bfm. + // This struct is defined in spi_s_macros.svh + `spi_s_INITIATOR_STRUCT + spi_s_initiator_s spi_s_initiator_struct; + //******************************************************************* + // FUNCTION: to_initiator_struct() + // This function packs transaction variables into a spi_s_initiator_s + // structure. The function returns the handle to the spi_s_initiator_struct. + // This function is defined in spi_s_macros.svh + `spi_s_TO_INITIATOR_STRUCT_FUNCTION + //******************************************************************* + // FUNCTION: from_initiator_struct() + // This function unpacks the struct provided as an argument into transaction + // variables of this class. + // This function is defined in spi_s_macros.svh + `spi_s_FROM_INITIATOR_STRUCT_FUNCTION + + //******************************************************************* + // Responder macro used by spi_s_driver and spi_s_driver_bfm + // to communicate Responder driven data to spi_s_driver_bfm. + // This struct is defined in spi_s_macros.svh + `spi_s_RESPONDER_STRUCT + spi_s_responder_s spi_s_responder_struct; + //******************************************************************* + // FUNCTION: to_responder_struct() + // This function packs transaction variables into a spi_s_responder_s + // structure. The function returns the handle to the spi_s_responder_struct. + // This function is defined in spi_s_macros.svh + `spi_s_TO_RESPONDER_STRUCT_FUNCTION + //******************************************************************* + // FUNCTION: from_responder_struct() + // This function unpacks the struct provided as an argument into transaction + // variables of this class. + // This function is defined in spi_s_macros.svh + `spi_s_FROM_RESPONDER_STRUCT_FUNCTION + // **************************************************************************** + // FUNCTION : new() + // This function is the standard SystemVerilog constructor. + // + function new( string name = "" ); + super.new( name ); + endfunction + + // **************************************************************************** + // FUNCTION: convert2string() + // This function converts all variables in this class to a single string for + // logfile reporting. + // + virtual function string convert2string(); + // pragma uvmf custom convert2string begin + // UVMF_CHANGE_ME : Customize format if desired. + return $sformatf("ssel:0x%x mosi:0x%x miso:0x%x ",ssel,mosi,miso); + // pragma uvmf custom convert2string end + endfunction + + //******************************************************************* + // FUNCTION: do_print() + // This function is automatically called when the .print() function + // is called on this class. + // + virtual function void do_print(uvm_printer printer); + // pragma uvmf custom do_print begin + // UVMF_CHANGE_ME : Current contents of do_print allows for the use of UVM 1.1d, 1.2 or P1800.2. + // Update based on your own printing preference according to your preferred UVM version + $display(convert2string()); + // pragma uvmf custom do_print end + endfunction + + //******************************************************************* + // FUNCTION: do_compare() + // This function is automatically called when the .compare() function + // is called on this class. + // + virtual function bit do_compare (uvm_object rhs, uvm_comparer comparer); + spi_s_transaction RHS; + if (!$cast(RHS,rhs)) return 0; + // pragma uvmf custom do_compare begin + // UVMF_CHANGE_ME : Eliminate comparison of variables not to be used for compare + return (super.do_compare(rhs,comparer) + &&(this.ssel == RHS.ssel) + &&(this.mosi == RHS.mosi) + &&(this.miso == RHS.miso) + ); + // pragma uvmf custom do_compare end + endfunction + + //******************************************************************* + // FUNCTION: do_copy() + // This function is automatically called when the .copy() function + // is called on this class. + // + virtual function void do_copy (uvm_object rhs); + spi_s_transaction RHS; + assert($cast(RHS,rhs)); + // pragma uvmf custom do_copy begin + super.do_copy(rhs); + this.ssel = RHS.ssel; + this.mosi = RHS.mosi; + this.miso = RHS.miso; + // pragma uvmf custom do_copy end + endfunction + + // **************************************************************************** + // FUNCTION: add_to_wave() + // This function is used to display variables in this class in the waveform + // viewer. The start_time and end_time variables must be set before this + // function is called. If the start_time and end_time variables are not set + // the transaction will be hidden at 0ns on the waveform display. + // + virtual function void add_to_wave(int transaction_viewing_stream_h); + `ifdef QUESTA + if (transaction_view_h == 0) begin + transaction_view_h = $begin_transaction(transaction_viewing_stream_h,"spi_s_transaction",start_time); + end + super.add_to_wave(transaction_view_h); + // pragma uvmf custom add_to_wave begin + // UVMF_CHANGE_ME : Color can be applied to transaction entries based on content, example below + // case() + // 1 : $add_color(transaction_view_h,"red"); + // default : $add_color(transaction_view_h,"grey"); + // endcase + // UVMF_CHANGE_ME : Eliminate transaction variables not wanted in transaction viewing in the waveform viewer + $add_attribute(transaction_view_h,ssel,"ssel"); + $add_attribute(transaction_view_h,mosi,"mosi"); + $add_attribute(transaction_view_h,miso,"miso"); + // pragma uvmf custom add_to_wave end + $end_transaction(transaction_view_h,end_time); + $free_transaction(transaction_view_h); + `endif // QUESTA + endfunction + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end +`endif diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/spi_s_pkg/src/spi_s_transaction_coverage.svh b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/spi_s_pkg/src/spi_s_transaction_coverage.svh new file mode 100644 index 00000000..72092da7 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/spi_s_pkg/src/spi_s_transaction_coverage.svh @@ -0,0 +1,75 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This class records spi_s transaction information using +// a covergroup named spi_s_transaction_cg. An instance of this +// coverage component is instantiated in the uvmf_parameterized_agent +// if the has_coverage flag is set. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +`ifndef SPI_S_TRANSACTION_COVERAGE +`define SPI_S_TRANSACTION_COVERAGE +class spi_s_transaction_coverage extends uvm_subscriber #(.T(spi_s_transaction )); + + `uvm_component_utils( spi_s_transaction_coverage ) + + T coverage_trans; + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + // **************************************************************************** + covergroup spi_s_transaction_cg; + // pragma uvmf custom covergroup begin + // UVMF_CHANGE_ME : Add coverage bins, crosses, exclusions, etc. according to coverage needs. + option.auto_bin_max=1024; + option.per_instance=1; + ssel: coverpoint coverage_trans.ssel; + mosi: coverpoint coverage_trans.mosi; + miso: coverpoint coverage_trans.miso; + // pragma uvmf custom covergroup end + endgroup + + // **************************************************************************** + // FUNCTION : new() + // This function is the standard SystemVerilog constructor. + // + function new(string name="", uvm_component parent=null); + super.new(name,parent); + spi_s_transaction_cg=new; + `uvm_warning("COVERAGE_MODEL_REVIEW", "A covergroup has been constructed which may need review because of either generation or re-generation with merging. Please note that transaction variables added as a result of re-generation and merging are not automatically added to the covergroup. Remove this warning after the covergroup has been reviewed.") + endfunction + + // **************************************************************************** + // FUNCTION : build_phase() + // This function is the standard UVM build_phase. + // + function void build_phase(uvm_phase phase); + spi_s_transaction_cg.set_inst_name($sformatf("spi_s_transaction_cg_%s",get_full_name())); + endfunction + + // **************************************************************************** + // FUNCTION: write (T t) + // This function is automatically executed when a transaction arrives on the + // analysis_export. It copies values from the variables in the transaction + // to local variables used to collect functional coverage. + // + virtual function void write (T t); + `uvm_info("COV","Received transaction",UVM_HIGH); + coverage_trans = t; + spi_s_transaction_cg.sample(); + endfunction + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + +`endif diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/spi_s_pkg/src/spi_s_typedefs.svh b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/spi_s_pkg/src/spi_s_typedefs.svh new file mode 100644 index 00000000..91e77a1c --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/spi_s_pkg/src/spi_s_typedefs.svh @@ -0,0 +1,21 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: +// This file contains defines and typedefs to be compiled for use in +// the simulation running on the host server when using Veloce. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +`ifndef TYPEDEFS_HVL +`definr TYPEDEFS_HVL + +// pragma uvmf custom additional begin +// pragma uvmf custom additional end +`endif diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/spi_s_pkg/src/spi_s_typedefs_hdl.svh b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/spi_s_pkg/src/spi_s_typedefs_hdl.svh new file mode 100644 index 00000000..bd6b6f41 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/spi_s_pkg/src/spi_s_typedefs_hdl.svh @@ -0,0 +1,23 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: +// This file contains defines and typedefs to be compiled for use in +// the simulation running on the emulator when using Veloce. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// + +`ifndef TYPEDEFS_HVL +`definr TYPEDEFS_HVL + + +// pragma uvmf custom additional begin +// pragma uvmf custom additional end +`endif diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/spi_s_pkg/yaml/spi_s_interface.yaml b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/spi_s_pkg/yaml/spi_s_interface.yaml new file mode 100644 index 00000000..b00c98ca --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/spi_s_pkg/yaml/spi_s_interface.yaml @@ -0,0 +1,53 @@ +uvmf: + interfaces: + spi_s: + clock: sck + config_constraints: [] + config_vars: [] + existing_library_component: 'True' + gen_inbound_streaming_driver: 'False' + hdl_pkg_parameters: [] + hdl_typedefs: [] + hvl_pkg_parameters: [] + hvl_typedefs: [] + parameters: [] + ports: + - dir: input + name: sclk + reset_value: '''b0' + width: '1' + - dir: input + name: ss + reset_value: '''b0' + width: '1' + - dir: input + name: mosi + reset_value: '''b0' + width: '8' + - dir: output + name: miso + reset_value: '''b0' + width: '8' + reset: rst + reset_assertion_level: 'True' + transaction_constraints: [] + transaction_vars: + - comment: '' + iscompare: 'True' + isrand: 'False' + name: ssel + type: bit + unpacked_dimension: '' + - comment: '' + iscompare: 'True' + isrand: 'False' + name: mosi + type: bit [7:0] + unpacked_dimension: '' + - comment: '' + iscompare: 'True' + isrand: 'True' + name: miso + type: bit [7:0] + unpacked_dimension: '' + use_dpi_link: 'False' diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/wb_m_pkg/.project b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/wb_m_pkg/.project new file mode 100644 index 00000000..fd80e149 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/wb_m_pkg/.project @@ -0,0 +1,30 @@ + + + wb_m_pkg + + + + + + org.python.pydev.PyDevBuilder + + + + + net.sf.sveditor.core.SVProjectBuilder + + + + + + net.sf.sveditor.core.SVNature + org.python.pydev.pythonNature + + + + UVMF_VIP_LIBRARY_HOME + $%7BPARENT-2-PROJECT_LOC%7D + + + + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/wb_m_pkg/.svproject b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/wb_m_pkg/.svproject new file mode 100644 index 00000000..51ce829e --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/wb_m_pkg/.svproject @@ -0,0 +1,16 @@ + + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/wb_m_pkg/Makefile b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/wb_m_pkg/Makefile new file mode 100644 index 00000000..c00e8a8f --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/wb_m_pkg/Makefile @@ -0,0 +1,66 @@ +# wb_m interface packages source +# pragma uvmf custom additional begin +# pragma uvmf custom additional end + +wb_m_PKG = \ + +incdir+$(UVMF_VIP_LIBRARY_HOME)/interface_packages/wb_m_pkg \ + -F $(UVMF_VIP_LIBRARY_HOME)/interface_packages/wb_m_pkg/wb_m_filelist_hvl.f + +wb_m_PKG_HDL = \ + +incdir+$(UVMF_VIP_LIBRARY_HOME)/interface_packages/wb_m_pkg \ + -F $(UVMF_VIP_LIBRARY_HOME)/interface_packages/wb_m_pkg/wb_m_filelist_hdl.f + +wb_m_PKG_XRTL = \ + +incdir+$(UVMF_VIP_LIBRARY_HOME)/interface_packages/wb_m_pkg \ + -F $(UVMF_VIP_LIBRARY_HOME)/interface_packages/wb_m_pkg/wb_m_filelist_xrtl.f + +COMP_wb_m_PKG_TGT_0 = q_comp_wb_m_pkg +COMP_wb_m_PKG_TGT_1 = v_comp_wb_m_pkg +COMP_wb_m_PKG_TGT = $(COMP_wb_m_PKG_TGT_$(USE_VELOCE)) + +comp_wb_m_pkg: $(COMP_wb_m_PKG_TGT) + +q_comp_wb_m_pkg: + $(HDL_COMP_CMD) $(wb_m_PKG_HDL) + $(HVL_COMP_CMD) $(wb_m_PKG) + $(HDL_COMP_CMD) $(wb_m_PKG_XRTL) + +v_comp_wb_m_pkg: + $(HVL_COMP_CMD) $(wb_m_PKG_HDL) + $(HVL_COMP_CMD) $(wb_m_PKG) + $(VELANALYZE_CMD) $(wb_m_PKG_HDL) + $(VELANALYZE_HVL_CMD) $(wb_m_PKG) + $(HDL_COMP_CMD) $(wb_m_PKG_XRTL) + +ifeq ($(MTI_VCO_MODE),64) + GCC_COMP_ARCH = -m64 +else + GCC_COMP_ARCH = -m32 +endif + +export wb_m_IF_DPI_SRC ?= $(UVMF_VIP_LIBRARY_HOME)/interface_packages/wb_m_pkg/dpi + +C_FILE_COMPILE_LIST_wb_m_pkg = \ + +O_FILE_COMPILE_LIST_wb_m_pkg = $(notdir $(C_FILE_COMPILE_LIST_wb_m_pkg:.c=.o)) + +GCC_COMP_ARGS_wb_m_pkg += -I$(wb_m_IF_DPI_SRC) \ + -fPIC + +GCC_COMP_ARGS_wb_m_pkg += $(wb_m_IF_GCC_COMP_ARGUMENTS) + +GCC_LINK_ARGS_wb_m_pkg += \ + \ + -o .so + +comp_wb_m_pkg_c_files: + @echo "--------------------------------" + @echo "Compiling Interface C source" + @echo "--------------------------------" + gcc $(GCC_COMP_ARCH) $(GCC_COMP_ARGS_wb_m_pkg) $(C_FILE_COMPILE_LIST_wb_m_pkg) + @echo "--------------------------------" + @echo "Linking Interface C objects into a shared object" + @echo "--------------------------------" + gcc $(GCC_COMP_ARCH) $(GCC_LINK_ARGS_wb_m_pkg) $(O_FILE_COMPILE_LIST_wb_m_pkg) + @echo "--------------------------------" + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/wb_m_pkg/compile.do b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/wb_m_pkg/compile.do new file mode 100644 index 00000000..6e931196 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/wb_m_pkg/compile.do @@ -0,0 +1,14 @@ +# Tcl do file for compile of wb_m interface + +# pragma uvmf custom additional begin +# pragma uvmf custom additional end + + +vlog -sv -timescale 1ps/1ps -suppress 2223,2286 +incdir+$env(UVMF_VIP_LIBRARY_HOME)/interface_packages/wb_m_pkg \ + -F $env(UVMF_VIP_LIBRARY_HOME)/interface_packages/wb_m_pkg/wb_m_filelist_hdl.f + +vlog -sv -timescale 1ps/1ps -suppress 2223,2286 +incdir+$env(UVMF_VIP_LIBRARY_HOME)/interface_packages/wb_m_pkg \ + -F $env(UVMF_VIP_LIBRARY_HOME)/interface_packages/wb_m_pkg/wb_m_filelist_hvl.f + +vlog -sv -timescale 1ps/1ps -suppress 2223,2286 +incdir+$env(UVMF_VIP_LIBRARY_HOME)/interface_packages/wb_m_pkg \ + -F $env(UVMF_VIP_LIBRARY_HOME)/interface_packages/wb_m_pkg/wb_m_filelist_xrtl.f \ No newline at end of file diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/wb_m_pkg/src/wb_m2reg_adapter.svh b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/wb_m_pkg/src/wb_m2reg_adapter.svh new file mode 100644 index 00000000..86ecd885 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/wb_m_pkg/src/wb_m2reg_adapter.svh @@ -0,0 +1,115 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: +// This file contains the UVM register adapter for the wb_m interface. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +`ifndef WB_M2REG_ADAPTER +`define WB_M2REG_ADAPTER +class wb_m2reg_adapter #( + int WB_ADDR_WIDTH = 32, + int WB_DATA_WIDTH = 16 + ) extends uvm_reg_adapter; + + `uvm_object_param_utils( wb_m2reg_adapter #( + WB_ADDR_WIDTH, + WB_DATA_WIDTH + )) + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + //-------------------------------------------------------------------- + // new + //-------------------------------------------------------------------- + function new (string name = "wb_m2reg_adapter" ); + super.new(name); + // pragma uvmf custom new begin + // UVMF_CHANGE_ME : Configure the adapter regarding byte enables and provides response. + + // Does the protocol the Agent is modeling support byte enables? + // 0 = NO + // 1 = YES + supports_byte_enable = 0; + + // Does the Agent's Driver provide separate response sequence items? + // i.e. Does the driver call seq_item_port.put() + // and do the sequences call get_response()? + // 0 = NO + // 1 = YES + provides_responses = 0; + // pragma uvmf custom new end + + endfunction: new + + //-------------------------------------------------------------------- + // reg2bus + //-------------------------------------------------------------------- + virtual function uvm_sequence_item reg2bus(const ref uvm_reg_bus_op rw); + + wb_m_transaction #( + .WB_ADDR_WIDTH(WB_ADDR_WIDTH), + .WB_DATA_WIDTH(WB_DATA_WIDTH) + ) trans_h = wb_m_transaction #( + .WB_ADDR_WIDTH(WB_ADDR_WIDTH), + .WB_DATA_WIDTH(WB_DATA_WIDTH) + )::type_id::create("trans_h"); + + // pragma uvmf custom reg2bus begin + // UVMF_CHANGE_ME : Fill in the reg2bus adapter mapping registe fields to protocol fields. + + //Adapt the following for your sequence item type + // trans_h.op = (rw.kind == UVM_READ) ? WB_READ : WB_WRITE; + //Copy over address + // trans_h.addr = rw.addr; + //Copy over write data + // trans_h.data = rw.data; + + // pragma uvmf custom reg2bus end + + // Return the adapted transaction + return trans_h; + + endfunction: reg2bus + + //-------------------------------------------------------------------- + // bus2reg + //-------------------------------------------------------------------- + virtual function void bus2reg(uvm_sequence_item bus_item, + ref uvm_reg_bus_op rw); + wb_m_transaction #( + .WB_ADDR_WIDTH(WB_ADDR_WIDTH), + .WB_DATA_WIDTH(WB_DATA_WIDTH) + ) trans_h; + if (!$cast(trans_h, bus_item)) begin + `uvm_fatal("ADAPT","Provided bus_item is not of the correct type") + return; + end + // pragma uvmf custom bus2reg begin + // UVMF_CHANGE_ME : Fill in the bus2reg adapter mapping protocol fields to register fields. + //Adapt the following for your sequence item type + //Copy over instruction type + // rw.kind = (trans_h.op == WB_WRITE) ? UVM_WRITE : UVM_READ; + //Copy over address + // rw.addr = trans_h.addr; + //Copy over read data + // rw.data = trans_h.data; + //Check for errors on the bus and return UVM_NOT_OK if there is an error + // rw.status = UVM_IS_OK; + // pragma uvmf custom bus2reg end + + endfunction: bus2reg + +endclass : wb_m2reg_adapter + +// pragma uvmf custom external begin +// pragma uvmf custom external end +`endif diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/wb_m_pkg/src/wb_m_agent.svh b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/wb_m_pkg/src/wb_m_agent.svh new file mode 100644 index 00000000..f74df67e --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/wb_m_pkg/src/wb_m_agent.svh @@ -0,0 +1,79 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: Protocol specific agent class definition +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// + +`ifndef WB_M_AGENT +`define WB_M_AGENT + +class wb_m_agent #( + int WB_ADDR_WIDTH = 32, + int WB_DATA_WIDTH = 16 + ) extends uvmf_parameterized_agent #( + .CONFIG_T(wb_m_configuration #( + .WB_ADDR_WIDTH(WB_ADDR_WIDTH), + .WB_DATA_WIDTH(WB_DATA_WIDTH) + )), + .DRIVER_T(wb_m_driver #( + .WB_ADDR_WIDTH(WB_ADDR_WIDTH), + .WB_DATA_WIDTH(WB_DATA_WIDTH) + )), + .MONITOR_T(wb_m_monitor #( + .WB_ADDR_WIDTH(WB_ADDR_WIDTH), + .WB_DATA_WIDTH(WB_DATA_WIDTH) + )), + .COVERAGE_T(wb_m_transaction_coverage #( + .WB_ADDR_WIDTH(WB_ADDR_WIDTH), + .WB_DATA_WIDTH(WB_DATA_WIDTH) + )), + .TRANS_T(wb_m_transaction #( + .WB_ADDR_WIDTH(WB_ADDR_WIDTH), + .WB_DATA_WIDTH(WB_DATA_WIDTH) + )) + ); + + `uvm_component_param_utils( wb_m_agent #( + WB_ADDR_WIDTH, + WB_DATA_WIDTH + )) + +// pragma uvmf custom class_item_additional begin +// pragma uvmf custom class_item_additional end + +// **************************************************************************** +// FUNCTION : new() +// This function is the standard SystemVerilog constructor. +// + function new( string name = "", uvm_component parent = null ); + super.new( name, parent ); + endfunction + +// **************************************************************************** + // FUNCTION: build_phase + virtual function void build_phase(uvm_phase phase); +// pragma uvmf custom build_phase_pre_super begin +// pragma uvmf custom build_phase_pre_super end + super.build_phase(phase); + if (configuration.active_passive == ACTIVE) begin + // Place sequencer handle into configuration object + // so that it may be retrieved from configuration + // rather than using uvm_config_db + configuration.sequencer = this.sequencer; + end + endfunction + +endclass + + +// pragma uvmf custom external begin +// pragma uvmf custom external end +`endif diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/wb_m_pkg/src/wb_m_configuration.svh b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/wb_m_pkg/src/wb_m_configuration.svh new file mode 100644 index 00000000..11140f63 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/wb_m_pkg/src/wb_m_configuration.svh @@ -0,0 +1,206 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This class contains all variables and functions used +// to configure the wb_m agent and its bfm's. It gets the +// bfm's from the uvm_config_db for use by the agent. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// + +`ifndef WB_M_CONFIGURATION +`define WB_M_CONFIGURATION +class wb_m_configuration #( + int WB_ADDR_WIDTH = 32, + int WB_DATA_WIDTH = 16 + ) extends uvmf_parameterized_agent_configuration_base #( + .DRIVER_BFM_BIND_T(virtual wb_m_driver_bfm #( + .WB_ADDR_WIDTH(WB_ADDR_WIDTH), + .WB_DATA_WIDTH(WB_DATA_WIDTH) + )), + .MONITOR_BFM_BIND_T( virtual wb_m_monitor_bfm #( + .WB_ADDR_WIDTH(WB_ADDR_WIDTH), + .WB_DATA_WIDTH(WB_DATA_WIDTH) + ))); + + `uvm_object_param_utils( wb_m_configuration #( + WB_ADDR_WIDTH, + WB_DATA_WIDTH + )) + + + // Sequencer handle populated by agent + uvm_sequencer #(wb_m_transaction #( + .WB_ADDR_WIDTH(WB_ADDR_WIDTH), + .WB_DATA_WIDTH(WB_DATA_WIDTH) + ) ) sequencer; + + //Constraints for the configuration variables: + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + covergroup wb_m_configuration_cg; + // pragma uvmf custom covergroup begin + option.auto_bin_max=1024; + // pragma uvmf custom covergroup end + endgroup + + //******************************************************************* + //******************************************************************* + // Structure used to pass configuration variables to monitor and driver BFM's. + // Use to_struct function to pack variables into structure. + // Use from_struct function to unpack variables from structure. + // This structure is defined in wb_m_macros.svh + `wb_m_CONFIGURATION_STRUCT + wb_m_configuration_s wb_m_configuration_struct; + //******************************************************************* + // FUNCTION: to_struct() + // This function packs variables into a wb_m_configuration_s + // structure. The function returns the handle to the wb_m_configuration_struct. + // This function is defined in wb_m_macros.svh + `wb_m_CONFIGURATION_TO_STRUCT_FUNCTION + //******************************************************************* + // FUNCTION: from_struct() + // This function unpacks the struct provided as an argument into + // variables of this class. + // This function is defined in wb_m_macros.svh + `wb_m_CONFIGURATION_FROM_STRUCT_FUNCTION + + // **************************************************************************** + // FUNCTION : new() + // This function is the standard SystemVerilog constructor. + // + function new( string name = "" ); + super.new( name ); + // Construct the covergroup for this configuration class + wb_m_configuration_cg = new; + endfunction + + // **************************************************************************** + // FUNCTION: post_randomize() + // This function is automatically called after the randomize() function + // is executed. + // + function void post_randomize(); + super.post_randomize(); + wb_m_configuration_cg.sample(); + endfunction + + // **************************************************************************** + // FUNCTION: initialize + // This function causes the configuration to retrieve + // its virtual interface handle from the uvm_config_db. + // This function also makes itself available to its + // agent through the uvm_config_db. + // + // ARGUMENTS: + // uvmf_active_passive_t activity: + // This argument identifies the simulation level + // as either BLOCK, CHIP, SIMULATION, etc. + // + // AGENT_PATH: + // This argument identifies the path to this + // configurations agent. This configuration + // makes itself available to the agent specified + // by agent_path by placing itself into the + // uvm_config_db. + // + // INTERFACE_NAME: + // This argument identifies the string name of + // this configurations BFM's. This string + // name is used to retrieve the driver and + // monitor BFM from the uvm_config_db. + // + virtual function void initialize(uvmf_active_passive_t activity, + string agent_path, + string interface_name); + + super.initialize( activity, agent_path, interface_name); + // The covergroup is given the same name as the interface + wb_m_configuration_cg.set_inst_name(interface_name); + + // This configuration places itself into the uvm_config_db for the agent, identified by the agent_path variable, to retrieve. + uvm_config_db #( wb_m_configuration #( + .WB_ADDR_WIDTH(WB_ADDR_WIDTH), + .WB_DATA_WIDTH(WB_DATA_WIDTH) + ) + )::set( null ,agent_path,UVMF_AGENT_CONFIG, this ); + + // This configuration also places itself in the config db using the same identifier used by the interface. This allows users to access + // configuration variables and the interface through the bfm api class rather than directly accessing the BFM. This is useful for + // accessingthe BFM when using Veloce + uvm_config_db #( wb_m_configuration #( + .WB_ADDR_WIDTH(WB_ADDR_WIDTH), + .WB_DATA_WIDTH(WB_DATA_WIDTH) + ) + )::set( null ,UVMF_CONFIGURATIONS, interface_name, this ); + + wb_m_configuration_cg.set_inst_name($sformatf("wb_m_configuration_cg_%s",get_full_name())); + +// This code is to aid in debugging parameter mismatches between the BFM and its corresponding agent. +// Enable this debug by setting UVM_VERBOSITY to UVM_DEBUG +// Setting UVM_VERBOSITY to UVM_DEBUG causes all BFM's and all agents to display their parameter settings. +// All of the messages from this feature have a UVM messaging id value of "CFG" +// The transcript or run.log can be parsed to ensure BFM parameter settings match its corresponding agents parameter settings. + `uvm_info("CFG", + $psprintf("The agent at '%s' is using interface named %s has the following parameters: WB_ADDR_WIDTH=%x WB_DATA_WIDTH=%x ", agent_path, interface_name, WB_ADDR_WIDTH ,WB_DATA_WIDTH ), + UVM_DEBUG) + + // pragma uvmf custom initialize begin + // This controls whether or not the agent returns a transaction handle in the driver when calling + // item_done() back into the sequencer or not. If set to 1, a transaction is sent back which means + // the sequence on the other end must use the get_response() part of the driver/sequence API. If + // this doesn't occur, there will eventually be response_queue overflow errors during the test. + return_transaction_response = 1'b0; + + // pragma uvmf custom initialize end + + endfunction + + // **************************************************************************** + // TASK: wait_for_reset + // *[Required]* Blocks until reset is released. The wait_for_reset operation is performed + // by a task in the monitor bfm. + virtual task wait_for_reset(); + monitor_bfm.wait_for_reset(); + endtask + + // **************************************************************************** + // TASK: wait_for_num_clocks + // *[Required]* Blocks until specified number of clocks have elapsed. The wait_for_num_clocks + // operation is performed by a task in the monitor bfm. + virtual task wait_for_num_clocks(int clocks); + monitor_bfm.wait_for_num_clocks(clocks); + endtask + + // **************************************************************************** + // FUNCTION : convert2string() + // This function is used to convert variables in this class into a string for log messaging. + // + virtual function string convert2string (); + // pragma uvmf custom convert2string begin + return $sformatf(""); + // pragma uvmf custom convert2string end + endfunction + + // **************************************************************************** + // FUNCTION: get_sequencer + function uvm_sequencer #(wb_m_transaction#( + .WB_ADDR_WIDTH(WB_ADDR_WIDTH), + .WB_DATA_WIDTH(WB_DATA_WIDTH) + )) get_sequencer(); + return sequencer; + endfunction + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end +`endif diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/wb_m_pkg/src/wb_m_driver.svh b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/wb_m_pkg/src/wb_m_driver.svh new file mode 100644 index 00000000..ea48e090 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/wb_m_pkg/src/wb_m_driver.svh @@ -0,0 +1,111 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This class passes transactions between the sequencer +// and the BFM driver interface. It accesses the driver BFM +// through the bfm handle. This driver +// passes transactions to the driver BFM through the access +// task. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +`ifndef WB_M_DRIVER +`define WB_M_DRIVER +class wb_m_driver #( + int WB_ADDR_WIDTH = 32, + int WB_DATA_WIDTH = 16 + ) extends uvmf_driver_base #( + .CONFIG_T(wb_m_configuration #( + .WB_ADDR_WIDTH(WB_ADDR_WIDTH), + .WB_DATA_WIDTH(WB_DATA_WIDTH) + ) ), + .BFM_BIND_T(virtual wb_m_driver_bfm #( + .WB_ADDR_WIDTH(WB_ADDR_WIDTH), + .WB_DATA_WIDTH(WB_DATA_WIDTH) + ) ), + .REQ(wb_m_transaction #( + .WB_ADDR_WIDTH(WB_ADDR_WIDTH), + .WB_DATA_WIDTH(WB_DATA_WIDTH) + ) ), + .RSP(wb_m_transaction #( + .WB_ADDR_WIDTH(WB_ADDR_WIDTH), + .WB_DATA_WIDTH(WB_DATA_WIDTH) + ) )); + + `uvm_component_param_utils( wb_m_driver #( + WB_ADDR_WIDTH, + WB_DATA_WIDTH + )) +//******************************************************************* +// Macros that define structs located in wb_m_macros.svh +//******************************************************************* +// Initiator macro used by wb_m_driver and wb_m_driver_bfm +// to communicate initiator driven data to wb_m_driver_bfm. +`wb_m_INITIATOR_STRUCT + wb_m_initiator_s wb_m_initiator_struct; +//******************************************************************* +// Responder macro used by wb_m_driver and wb_m_driver_bfm +// to communicate Responder driven data to wb_m_driver_bfm. +`wb_m_RESPONDER_STRUCT + wb_m_responder_s wb_m_responder_struct; + +// pragma uvmf custom class_item_additional begin +// pragma uvmf custom class_item_additional end + +// **************************************************************************** +// This function is the standard SystemVerilog constructor. +// + function new( string name = "", uvm_component parent=null ); + super.new( name, parent ); + endfunction + +// **************************************************************************** +// This function sends configuration object variables to the driver BFM +// using the configuration struct. +// + virtual function void configure(input CONFIG_T cfg); + bfm.configure( cfg.to_struct() ); + endfunction + +// **************************************************************************** +// This function places a handle to this class in the proxy variable in the +// driver BFM. This allows the driver BFM to call tasks and function within this class. +// + virtual function void set_bfm_proxy_handle(); + bfm.proxy = this; endfunction + +// **************************************************************************** +// This task is called by the run_phase in uvmf_driver_base. + virtual task access( inout REQ txn ); +// pragma uvmf custom access begin + if (configuration.initiator_responder==RESPONDER) begin + // Complete current transfer and wait for next transfer + bfm.respond_and_wait_for_next_transfer( + wb_m_initiator_struct, + txn.to_responder_struct() + ); + // Unpack information about initiated transfer received by this responder + txn.from_initiator_struct(wb_m_initiator_struct); + end else begin + // Initiate a transfer and get response + bfm.initiate_and_get_response( + txn.to_initiator_struct(), + wb_m_responder_struct + ); + // Unpack transfer response information received by this initiator + txn.from_responder_struct(wb_m_responder_struct); + end +// pragma uvmf custom access end + endtask + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end +`endif diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/wb_m_pkg/src/wb_m_driver_bfm.sv b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/wb_m_pkg/src/wb_m_driver_bfm.sv new file mode 100644 index 00000000..34f87263 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/wb_m_pkg/src/wb_m_driver_bfm.sv @@ -0,0 +1,359 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: +// This interface performs the wb_m signal driving. It is +// accessed by the uvm wb_m driver through a virtual interface +// handle in the wb_m configuration. It drives the singals passed +// in through the port connection named bus of type wb_m_if. +// +// Input signals from the wb_m_if are assigned to an internal input +// signal with a _i suffix. The _i signal should be used for sampling. +// +// The input signal connections are as follows: +// bus.signal -> signal_i +// +// This bfm drives signals with a _o suffix. These signals +// are driven onto signals within wb_m_if based on INITIATOR/RESPONDER and/or +// ARBITRATION/GRANT status. +// +// The output signal connections are as follows: +// signal_o -> bus.signal +// +// +// Interface functions and tasks used by UVM components: +// +// configure: +// This function gets configuration attributes from the +// UVM driver to set any required BFM configuration +// variables such as 'initiator_responder'. +// +// initiate_and_get_response: +// This task is used to perform signaling activity for initiating +// a protocol transfer. The task initiates the transfer, using +// input data from the initiator struct. Then the task captures +// response data, placing the data into the response struct. +// The response struct is returned to the driver class. +// +// respond_and_wait_for_next_transfer: +// This task is used to complete a current transfer as a responder +// and then wait for the initiator to start the next transfer. +// The task uses data in the responder struct to drive protocol +// signals to complete the transfer. The task then waits for +// the next transfer. Once the next transfer begins, data from +// the initiator is placed into the initiator struct and sent +// to the responder sequence for processing to determine +// what data to respond with. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +import uvmf_base_pkg_hdl::*; +import wb_m_pkg_hdl::*; +`include "src/wb_m_macros.svh" + +interface wb_m_driver_bfm #( + int WB_ADDR_WIDTH = 32, + int WB_DATA_WIDTH = 16 + ) + (wb_m_if bus); + // The following pragma and additional ones in-lined further below are for running this BFM on Veloce + // pragma attribute wb_m_driver_bfm partition_interface_xif + +`ifndef XRTL +// This code is to aid in debugging parameter mismatches between the BFM and its corresponding agent. +// Enable this debug by setting UVM_VERBOSITY to UVM_DEBUG +// Setting UVM_VERBOSITY to UVM_DEBUG causes all BFM's and all agents to display their parameter settings. +// All of the messages from this feature have a UVM messaging id value of "CFG" +// The transcript or run.log can be parsed to ensure BFM parameter settings match its corresponding agents parameter settings. +import uvm_pkg::*; +`include "uvm_macros.svh" +initial begin : bfm_vs_agent_parameter_debug + `uvm_info("CFG", + $psprintf("The BFM at '%m' has the following parameters: WB_ADDR_WIDTH=%x WB_DATA_WIDTH=%x ", WB_ADDR_WIDTH,WB_DATA_WIDTH), + UVM_DEBUG) +end +`endif + + // Config value to determine if this is an initiator or a responder + uvmf_initiator_responder_t initiator_responder; + // Custom configuration variables. + // These are set using the configure function which is called during the UVM connect_phase + + logic clock_i; + logic reset_i; + + // Signal list (all signals are capable of being inputs and outputs for the sake + // of supporting both INITIATOR and RESPONDER mode operation. Expectation is that + // directionality in the config file was from the point-of-view of the INITIATOR + + // INITIATOR mode input signals + tri [WB_DATA_WIDTH-1:0] din_i; + reg [WB_DATA_WIDTH-1:0] din_o = 'b0; + tri [WB_DATA_WIDTH-1:0] TGD_I_i; + reg [WB_DATA_WIDTH-1:0] TGD_I_o = 'bz; + tri err_i; + reg err_o = 'b0; + + // INITIATOR mode output signals + tri [WB_DATA_WIDTH-1:0] dout_i; + reg [WB_DATA_WIDTH-1:0] dout_o = 'b0; + tri [WB_DATA_WIDTH-1:0] TGD_O_i; + reg [WB_DATA_WIDTH-1:0] TGD_O_o = 'bz; + tri ack_i; + reg ack_o = 1'b0; + tri [WB_ADDR_WIDTH-1:0] adr_i; + reg [WB_ADDR_WIDTH-1:0] adr_o = 'b0; + tri cyc_i; + reg cyc_o = 0; + tri we_i; + reg we_o = 0; + tri stb_i; + reg stb_o = 0; + tri [WB_DATA_WIDTH/8-1:0] sel_i; + reg [WB_DATA_WIDTH/8-1:0] sel_o = 'b0; + + // Bi-directional signals + + + assign clock_i = bus.clock; + assign reset_i = bus.reset; + + // These are signals marked as 'input' by the config file, but the signals will be + // driven by this BFM if put into RESPONDER mode (flipping all signal directions around) + assign din_i = bus.din; + assign bus.din = (initiator_responder == RESPONDER) ? din_o : 'bz; + assign TGD_I_i = bus.TGD_I; + assign bus.TGD_I = (initiator_responder == RESPONDER) ? TGD_I_o : 'bz; + assign err_i = bus.err; + assign bus.err = (initiator_responder == RESPONDER) ? err_o : 'bz; + + + // These are signals marked as 'output' by the config file, but the outputs will + // not be driven by this BFM unless placed in INITIATOR mode. + assign bus.dout = (initiator_responder == INITIATOR) ? dout_o : 'bz; + assign dout_i = bus.dout; + assign bus.TGD_O = (initiator_responder == INITIATOR) ? TGD_O_o : 'bz; + assign TGD_O_i = bus.TGD_O; + assign bus.ack = (initiator_responder == INITIATOR) ? ack_o : 'bz; + assign ack_i = bus.ack; + assign bus.adr = (initiator_responder == INITIATOR) ? adr_o : 'bz; + assign adr_i = bus.adr; + assign bus.cyc = (initiator_responder == INITIATOR) ? cyc_o : 'bz; + assign cyc_i = bus.cyc; + assign bus.we = (initiator_responder == INITIATOR) ? we_o : 'bz; + assign we_i = bus.we; + assign bus.stb = (initiator_responder == INITIATOR) ? stb_o : 'bz; + assign stb_i = bus.stb; + assign bus.sel = (initiator_responder == INITIATOR) ? sel_o : 'bz; + assign sel_i = bus.sel; + + // Proxy handle to UVM driver + wb_m_pkg::wb_m_driver #( + .WB_ADDR_WIDTH(WB_ADDR_WIDTH), + .WB_DATA_WIDTH(WB_DATA_WIDTH) + ) proxy; + // pragma tbx oneway proxy.my_function_name_in_uvm_driver + + // **************************************************************************** + // **************************************************************************** + // Macros that define structs located in wb_m_macros.svh + // **************************************************************************** + // Struct for passing configuration data from wb_m_driver to this BFM + // **************************************************************************** + `wb_m_CONFIGURATION_STRUCT + // **************************************************************************** + // Structs for INITIATOR and RESPONDER data flow + //******************************************************************* + // Initiator macro used by wb_m_driver and wb_m_driver_bfm + // to communicate initiator driven data to wb_m_driver_bfm. + `wb_m_INITIATOR_STRUCT + wb_m_initiator_s initiator_struct; + // Responder macro used by wb_m_driver and wb_m_driver_bfm + // to communicate Responder driven data to wb_m_driver_bfm. + `wb_m_RESPONDER_STRUCT + wb_m_responder_s responder_struct; + + // **************************************************************************** +// pragma uvmf custom reset_condition_and_response begin + // Always block used to return signals to reset value upon assertion of reset + always @( posedge reset_i ) + begin + // RESPONDER mode output signals + din_o <= 'b0; + TGD_I_o <= 'bz; + err_o <= 'b0; + // INITIATOR mode output signals + dout_o <= 'b0; + TGD_O_o <= 'bz; + ack_o <= 1'b0; + adr_o <= 'b0; + cyc_o <= 0; + we_o <= 0; + stb_o <= 0; + sel_o <= 'b0; + // Bi-directional signals + + end +// pragma uvmf custom reset_condition_and_response end + + // pragma uvmf custom interface_item_additional begin + // pragma uvmf custom interface_item_additional end + + //****************************************************************** + // The configure() function is used to pass agent configuration + // variables to the driver BFM. It is called by the driver within + // the agent at the beginning of the simulation. It may be called + // during the simulation if agent configuration variables are updated + // and the driver BFM needs to be aware of the new configuration + // variables. + // + + function void configure(wb_m_configuration_s wb_m_configuration_arg); // pragma tbx xtf + initiator_responder = wb_m_configuration_arg.initiator_responder; + // pragma uvmf custom configure begin + // pragma uvmf custom configure end + endfunction + +// pragma uvmf custom initiate_and_get_response begin +// **************************************************************************** +// UVMF_CHANGE_ME +// This task is used by an initator. The task first initiates a transfer then +// waits for the responder to complete the transfer. + task initiate_and_get_response( + // This argument passes transaction variables used by an initiator + // to perform the initial part of a protocol transfer. The values + // come from a sequence item created in a sequence. + input wb_m_initiator_s wb_m_initiator_struct, + // This argument is used to send data received from the responder + // back to the sequence item. The sequence item is returned to the sequence. + output wb_m_responder_s wb_m_responder_struct + );// pragma tbx xtf + // + // Members within the wb_m_initiator_struct: + // bit [WB_DATA_WIDTH-1:0] data ; + // bit [(WB_DATA_WIDTH/8)-1:0] byte_select ; + // bit WrENB ; + // bit selslv ; + // Members within the wb_m_responder_struct: + // bit [WB_DATA_WIDTH-1:0] data ; + // bit [(WB_DATA_WIDTH/8)-1:0] byte_select ; + // bit WrENB ; + // bit selslv ; + initiator_struct = wb_m_initiator_struct; + // + // Reference code; + // How to wait for signal value + // while (control_signal == 1'b1) @(posedge clock_i); + // + // How to assign a responder struct member, named xyz, from a signal. + // All available initiator input and inout signals listed. + // Initiator input signals + // wb_m_responder_struct.xyz = din_i; // [WB_DATA_WIDTH-1:0] + // wb_m_responder_struct.xyz = TGD_I_i; // [WB_DATA_WIDTH-1:0] + // wb_m_responder_struct.xyz = err_i; // + // Initiator inout signals + // How to assign a signal from an initiator struct member named xyz. + // All available initiator output and inout signals listed. + // Notice the _o. Those are storage variables that allow for procedural assignment. + // Initiator output signals + // dout_o <= wb_m_initiator_struct.xyz; // [WB_DATA_WIDTH-1:0] + // TGD_O_o <= wb_m_initiator_struct.xyz; // [WB_DATA_WIDTH-1:0] + // ack_o <= wb_m_initiator_struct.xyz; // + // adr_o <= wb_m_initiator_struct.xyz; // [WB_ADDR_WIDTH-1:0] + // cyc_o <= wb_m_initiator_struct.xyz; // + // we_o <= wb_m_initiator_struct.xyz; // + // stb_o <= wb_m_initiator_struct.xyz; // + // sel_o <= wb_m_initiator_struct.xyz; // [WB_DATA_WIDTH/8-1:0] + // Initiator inout signals + // Initiate a transfer using the data received. + @(posedge clock_i); + @(posedge clock_i); + // Wait for the responder to complete the transfer then place the responder data into + // wb_m_responder_struct. + @(posedge clock_i); + @(posedge clock_i); + responder_struct = wb_m_responder_struct; + endtask +// pragma uvmf custom initiate_and_get_response end + +// pragma uvmf custom respond_and_wait_for_next_transfer begin +// **************************************************************************** +// The first_transfer variable is used to prevent completing a transfer in the +// first call to this task. For the first call to this task, there is not +// current transfer to complete. +bit first_transfer=1; + +// UVMF_CHANGE_ME +// This task is used by a responder. The task first completes the current +// transfer in progress then waits for the initiator to start the next transfer. + task respond_and_wait_for_next_transfer( + // This argument is used to send data received from the initiator + // back to the sequence item. The sequence determines how to respond. + output wb_m_initiator_s wb_m_initiator_struct, + // This argument passes transaction variables used by a responder + // to complete a protocol transfer. The values come from a sequence item. + input wb_m_responder_s wb_m_responder_struct + );// pragma tbx xtf + // Variables within the wb_m_initiator_struct: + // bit [WB_DATA_WIDTH-1:0] data ; + // bit [(WB_DATA_WIDTH/8)-1:0] byte_select ; + // bit WrENB ; + // bit selslv ; + // Variables within the wb_m_responder_struct: + // bit [WB_DATA_WIDTH-1:0] data ; + // bit [(WB_DATA_WIDTH/8)-1:0] byte_select ; + // bit WrENB ; + // bit selslv ; + // Reference code; + // How to wait for signal value + // while (control_signal == 1'b1) @(posedge clock_i); + // + // How to assign a responder struct member, named xyz, from a signal. + // All available responder input and inout signals listed. + // Responder input signals + // wb_m_responder_struct.xyz = dout_i; // [WB_DATA_WIDTH-1:0] + // wb_m_responder_struct.xyz = TGD_O_i; // [WB_DATA_WIDTH-1:0] + // wb_m_responder_struct.xyz = ack_i; // + // wb_m_responder_struct.xyz = adr_i; // [WB_ADDR_WIDTH-1:0] + // wb_m_responder_struct.xyz = cyc_i; // + // wb_m_responder_struct.xyz = we_i; // + // wb_m_responder_struct.xyz = stb_i; // + // wb_m_responder_struct.xyz = sel_i; // [WB_DATA_WIDTH/8-1:0] + // Responder inout signals + // How to assign a signal, named xyz, from an initiator struct member. + // All available responder output and inout signals listed. + // Notice the _o. Those are storage variables that allow for procedural assignment. + // Responder output signals + // din_o <= wb_m_initiator_struct.xyz; // [WB_DATA_WIDTH-1:0] + // TGD_I_o <= wb_m_initiator_struct.xyz; // [WB_DATA_WIDTH-1:0] + // err_o <= wb_m_initiator_struct.xyz; // + // Responder inout signals + + @(posedge clock_i); + if (!first_transfer) begin + // Perform transfer response here. + // Reply using data recieved in the wb_m_responder_struct. + @(posedge clock_i); + // Reply using data recieved in the transaction handle. + @(posedge clock_i); + end + // Wait for next transfer then gather info from intiator about the transfer. + // Place the data into the wb_m_initiator_struct. + @(posedge clock_i); + @(posedge clock_i); + first_transfer = 0; + endtask +// pragma uvmf custom respond_and_wait_for_next_transfer end + + +endinterface + +// pragma uvmf custom external begin +// pragma uvmf custom external end +`endif diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/wb_m_pkg/src/wb_m_if.sv b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/wb_m_pkg/src/wb_m_if.sv new file mode 100644 index 00000000..ce1368c2 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/wb_m_pkg/src/wb_m_if.sv @@ -0,0 +1,119 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This interface contains the wb_m interface signals. +// It is instantiated once per wb_m bus. Bus Functional Models, +// BFM's named wb_m_driver_bfm, are used to drive signals on the bus. +// BFM's named wb_m_monitor_bfm are used to monitor signals on the +// bus. This interface signal bundle is passed in the port list of +// the BFM in order to give the BFM access to the signals in this +// interface. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +`ifndef WB_M_IF +`define WB_M_IF +// This template can be used to connect a DUT to these signals +// +// .dut_signal_port(wb_m_bus.din), // Agent input +// .dut_signal_port(wb_m_bus.dout), // Agent output +// .dut_signal_port(wb_m_bus.TGD_I), // Agent input +// .dut_signal_port(wb_m_bus.TGD_O), // Agent output +// .dut_signal_port(wb_m_bus.ack), // Agent output +// .dut_signal_port(wb_m_bus.adr), // Agent output +// .dut_signal_port(wb_m_bus.cyc), // Agent output +// .dut_signal_port(wb_m_bus.err), // Agent input +// .dut_signal_port(wb_m_bus.we), // Agent output +// .dut_signal_port(wb_m_bus.stb), // Agent output +// .dut_signal_port(wb_m_bus.sel), // Agent output + +import uvmf_base_pkg_hdl::*; +import wb_m_pkg_hdl::*; + +interface wb_m_if #( + int WB_ADDR_WIDTH = 32, + int WB_DATA_WIDTH = 16 + ) + + ( + input logic clock, + input logic reset, + input logic [WB_DATA_WIDTH-1:0] din, + output logic [WB_DATA_WIDTH-1:0] dout, + input logic [WB_DATA_WIDTH-1:0] TGD_I, + output logic [WB_DATA_WIDTH-1:0] TGD_O, + output logic ack, + output logic [WB_ADDR_WIDTH-1:0] adr, + output logic cyc, + input logic err, + output logic we, + output logic stb, + output logic [WB_DATA_WIDTH/8-1:0] sel + ); + +modport monitor_port + ( + input clock, + input reset, + input din, + input dout, + input TGD_I, + input TGD_O, + input ack, + input adr, + input cyc, + input err, + input we, + input stb, + input sel + ); + +modport initiator_port + ( + input clock, + input reset, + input din, + output dout, + input TGD_I, + output TGD_O, + output ack, + output adr, + output cyc, + input err, + output we, + output stb, + output sel + ); + +modport responder_port + ( + input clock, + input reset, + output din, + input dout, + output TGD_I, + input TGD_O, + input ack, + input adr, + input cyc, + output err, + input we, + input stb, + input sel + ); + + +// pragma uvmf custom interface_item_additional begin +// pragma uvmf custom interface_item_additional end + +endinterface + +// pragma uvmf custom external begin +// pragma uvmf custom external end +`endif diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/wb_m_pkg/src/wb_m_infact_coverage_strategy.csv b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/wb_m_pkg/src/wb_m_infact_coverage_strategy.csv new file mode 100644 index 00000000..1c218e14 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/wb_m_pkg/src/wb_m_infact_coverage_strategy.csv @@ -0,0 +1,6 @@ +Global +auto_bin_max, 64 + +Name,Type,Include +rand_fields,coverpoint,=rand *.** + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/wb_m_pkg/src/wb_m_macros.svh b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/wb_m_pkg/src/wb_m_macros.svh new file mode 100644 index 00000000..9977f6fa --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/wb_m_pkg/src/wb_m_macros.svh @@ -0,0 +1,148 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This file contains macros used with the wb_m package. +// These macros include packed struct definitions. These structs are +// used to pass data between classes, hvl, and BFM's, hdl. Use of +// structs are more efficient and simpler to modify. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// + +// **************************************************************************** +// When changing the contents of this struct, be sure to update the to_struct +// and from_struct methods defined in the macros below that are used in +// the wb_m_configuration class. +// + `define wb_m_CONFIGURATION_STRUCT \ +typedef struct packed { \ + uvmf_active_passive_t active_passive; \ + uvmf_initiator_responder_t initiator_responder; \ + } wb_m_configuration_s; + + `define wb_m_CONFIGURATION_TO_STRUCT_FUNCTION \ + virtual function wb_m_configuration_s to_struct();\ + wb_m_configuration_struct = \ + {\ + this.active_passive,\ + this.initiator_responder\ + };\ + return ( wb_m_configuration_struct );\ + endfunction + + `define wb_m_CONFIGURATION_FROM_STRUCT_FUNCTION \ + virtual function void from_struct(wb_m_configuration_s wb_m_configuration_struct);\ + {\ + this.active_passive,\ + this.initiator_responder \ + } = wb_m_configuration_struct;\ + endfunction + +// **************************************************************************** +// When changing the contents of this struct, be sure to update the to_monitor_struct +// and from_monitor_struct methods of the wb_m_transaction class. +// + `define wb_m_MONITOR_STRUCT typedef struct packed { \ + bit [WB_DATA_WIDTH-1:0] data ; \ + bit [(WB_DATA_WIDTH/8)-1:0] byte_select ; \ + bit WrENB ; \ + bit selslv ; \ + } wb_m_monitor_s; + + `define wb_m_TO_MONITOR_STRUCT_FUNCTION \ + virtual function wb_m_monitor_s to_monitor_struct();\ + wb_m_monitor_struct = \ + { \ + this.data , \ + this.byte_select , \ + this.WrENB , \ + this.selslv \ + };\ + return ( wb_m_monitor_struct);\ + endfunction\ + + `define wb_m_FROM_MONITOR_STRUCT_FUNCTION \ + virtual function void from_monitor_struct(wb_m_monitor_s wb_m_monitor_struct);\ + {\ + this.data , \ + this.byte_select , \ + this.WrENB , \ + this.selslv \ + } = wb_m_monitor_struct;\ + endfunction + +// **************************************************************************** +// When changing the contents of this struct, be sure to update the to_initiator_struct +// and from_initiator_struct methods of the wb_m_transaction class. +// Also update the comments in the driver BFM. +// + `define wb_m_INITIATOR_STRUCT typedef struct packed { \ + bit [WB_DATA_WIDTH-1:0] data ; \ + bit [(WB_DATA_WIDTH/8)-1:0] byte_select ; \ + bit WrENB ; \ + bit selslv ; \ + } wb_m_initiator_s; + + `define wb_m_TO_INITIATOR_STRUCT_FUNCTION \ + virtual function wb_m_initiator_s to_initiator_struct();\ + wb_m_initiator_struct = \ + {\ + this.data , \ + this.byte_select , \ + this.WrENB , \ + this.selslv \ + };\ + return ( wb_m_initiator_struct);\ + endfunction + + `define wb_m_FROM_INITIATOR_STRUCT_FUNCTION \ + virtual function void from_initiator_struct(wb_m_initiator_s wb_m_initiator_struct);\ + {\ + this.data , \ + this.byte_select , \ + this.WrENB , \ + this.selslv \ + } = wb_m_initiator_struct;\ + endfunction + +// **************************************************************************** +// When changing the contents of this struct, be sure to update the to_responder_struct +// and from_responder_struct methods of the wb_m_transaction class. +// Also update the comments in the driver BFM. +// + `define wb_m_RESPONDER_STRUCT typedef struct packed { \ + bit [WB_DATA_WIDTH-1:0] data ; \ + bit [(WB_DATA_WIDTH/8)-1:0] byte_select ; \ + bit WrENB ; \ + bit selslv ; \ + } wb_m_responder_s; + + `define wb_m_TO_RESPONDER_STRUCT_FUNCTION \ + virtual function wb_m_responder_s to_responder_struct();\ + wb_m_responder_struct = \ + {\ + this.data , \ + this.byte_select , \ + this.WrENB , \ + this.selslv \ + };\ + return ( wb_m_responder_struct);\ + endfunction + + `define wb_m_FROM_RESPONDER_STRUCT_FUNCTION \ + virtual function void from_responder_struct(wb_m_responder_s wb_m_responder_struct);\ + {\ + this.data , \ + this.byte_select , \ + this.WrENB , \ + this.selslv \ + } = wb_m_responder_struct;\ + endfunction +// pragma uvmf custom additional begin +// pragma uvmf custom additional end diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/wb_m_pkg/src/wb_m_monitor.svh b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/wb_m_pkg/src/wb_m_monitor.svh new file mode 100644 index 00000000..4605ea2a --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/wb_m_pkg/src/wb_m_monitor.svh @@ -0,0 +1,104 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This class receives wb_m transactions observed by the +// wb_m monitor BFM and broadcasts them through the analysis port +// on the agent. It accesses the monitor BFM through the monitor +// task. This UVM component captures transactions +// for viewing in the waveform viewer if the +// enable_transaction_viewing flag is set in the configuration. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +`ifndef WB_M_MONITOR +`define WB_M_MONITOR +class wb_m_monitor #( + int WB_ADDR_WIDTH = 32, + int WB_DATA_WIDTH = 16 + ) extends uvmf_monitor_base #( + .CONFIG_T(wb_m_configuration #( + .WB_ADDR_WIDTH(WB_ADDR_WIDTH), + .WB_DATA_WIDTH(WB_DATA_WIDTH) + )), + .BFM_BIND_T(virtual wb_m_monitor_bfm #( + .WB_ADDR_WIDTH(WB_ADDR_WIDTH), + .WB_DATA_WIDTH(WB_DATA_WIDTH) + )), + .TRANS_T(wb_m_transaction #( + .WB_ADDR_WIDTH(WB_ADDR_WIDTH), + .WB_DATA_WIDTH(WB_DATA_WIDTH) + ))); + + `uvm_component_param_utils( wb_m_monitor #( + WB_ADDR_WIDTH, + WB_DATA_WIDTH + )) + +// Structure used to pass data from monitor BFM to monitor class in agent. +// Use to_monitor_struct function to pack transaction variables into structure. +// Use from_monitor_struct function to unpack transaction variables from structure. +`wb_m_MONITOR_STRUCT + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + +// **************************************************************************** +// This function is the standard SystemVerilog constructor. +// + function new( string name = "", uvm_component parent = null ); + super.new( name, parent ); + endfunction + +// **************************************************************************** +// This function sends configuration object variables to the monitor BFM +// using the configuration struct. +// + virtual function void configure(input CONFIG_T cfg); + bfm.configure( cfg.to_struct() ); + + endfunction + +// **************************************************************************** +// This function places a handle to this class in the proxy variable in the +// monitor BFM. This allows the monitor BFM to call the notify_transaction +// function within this class. +// + virtual function void set_bfm_proxy_handle(); + bfm.proxy = this; endfunction + +// *************************************************************************** + virtual task run_phase(uvm_phase phase); + // Start monitor BFM thread and don't call super.run() in order to + // override the default monitor proxy 'pull' behavior with the more + // emulation-friendly BFM 'push' approach using the notify_transaction + // function below + bfm.start_monitoring(); + endtask + +// ************************************************************************** + +// This function is called by the monitor BFM. It receives data observed by the +// monitor BFM. Data is passed using the wb_m_monitor_struct. + virtual function void notify_transaction(input wb_m_monitor_s wb_m_monitor_struct); + + + trans = new("trans"); + trans.from_monitor_struct(wb_m_monitor_struct); + trans.start_time = time_stamp; + trans.end_time = $time; + time_stamp = trans.end_time; + + analyze(trans); + endfunction + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end +`endif diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/wb_m_pkg/src/wb_m_monitor_bfm.sv b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/wb_m_pkg/src/wb_m_monitor_bfm.sv new file mode 100644 index 00000000..12e934a3 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/wb_m_pkg/src/wb_m_monitor_bfm.sv @@ -0,0 +1,215 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This interface performs the wb_m signal monitoring. +// It is accessed by the uvm wb_m monitor through a virtual +// interface handle in the wb_m configuration. It monitors the +// signals passed in through the port connection named bus of +// type wb_m_if. +// +// Input signals from the wb_m_if are assigned to an internal input +// signal with a _i suffix. The _i signal should be used for sampling. +// +// The input signal connections are as follows: +// bus.signal -> signal_i +// +// Interface functions and tasks used by UVM components: +// monitor(inout TRANS_T txn); +// This task receives the transaction, txn, from the +// UVM monitor and then populates variables in txn +// from values observed on bus activity. This task +// blocks until an operation on the wb_m bus is complete. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +`ifndef WB_M_MONITOR_BFM +`define WB_M_MONITOR_BFM +import uvmf_base_pkg_hdl::*; +import wb_m_pkg_hdl::*; +`include "src/wb_m_macros.svh" + + +interface wb_m_monitor_bfm #( + int WB_ADDR_WIDTH = 32, + int WB_DATA_WIDTH = 16 + ) + ( wb_m_if bus ); + // The pragma below and additional ones in-lined further down are for running this BFM on Veloce + // pragma attribute wb_m_monitor_bfm partition_interface_xif + +`ifndef XRTL +// This code is to aid in debugging parameter mismatches between the BFM and its corresponding agent. +// Enable this debug by setting UVM_VERBOSITY to UVM_DEBUG +// Setting UVM_VERBOSITY to UVM_DEBUG causes all BFM's and all agents to display their parameter settings. +// All of the messages from this feature have a UVM messaging id value of "CFG" +// The transcript or run.log can be parsed to ensure BFM parameter settings match its corresponding agents parameter settings. +import uvm_pkg::*; +`include "uvm_macros.svh" +initial begin : bfm_vs_agent_parameter_debug + `uvm_info("CFG", + $psprintf("The BFM at '%m' has the following parameters: WB_ADDR_WIDTH=%x WB_DATA_WIDTH=%x ", WB_ADDR_WIDTH,WB_DATA_WIDTH), + UVM_DEBUG) +end +`endif + + + // Structure used to pass transaction data from monitor BFM to monitor class in agent. +`wb_m_MONITOR_STRUCT + wb_m_monitor_s wb_m_monitor_struct; + + // Structure used to pass configuration data from monitor class to monitor BFM. + `wb_m_CONFIGURATION_STRUCT + + + // Config value to determine if this is an initiator or a responder + uvmf_initiator_responder_t initiator_responder; + // Custom configuration variables. + // These are set using the configure function which is called during the UVM connect_phase + + logic clock_i; + logic reset_i; + tri [WB_DATA_WIDTH-1:0] din_i; + tri [WB_DATA_WIDTH-1:0] dout_i; + tri [WB_DATA_WIDTH-1:0] TGD_I_i; + tri [WB_DATA_WIDTH-1:0] TGD_O_i; + tri ack_i; + tri [WB_ADDR_WIDTH-1:0] adr_i; + tri cyc_i; + tri err_i; + tri we_i; + tri stb_i; + tri [WB_DATA_WIDTH/8-1:0] sel_i; + assign clock_i = bus.clock; + assign reset_i = bus.reset; + assign din_i = bus.din; + assign dout_i = bus.dout; + assign TGD_I_i = bus.TGD_I; + assign TGD_O_i = bus.TGD_O; + assign ack_i = bus.ack; + assign adr_i = bus.adr; + assign cyc_i = bus.cyc; + assign err_i = bus.err; + assign we_i = bus.we; + assign stb_i = bus.stb; + assign sel_i = bus.sel; + + // Proxy handle to UVM monitor + wb_m_pkg::wb_m_monitor #( + .WB_ADDR_WIDTH(WB_ADDR_WIDTH), + .WB_DATA_WIDTH(WB_DATA_WIDTH) + ) proxy; + // pragma tbx oneway proxy.notify_transaction + + // pragma uvmf custom interface_item_additional begin + // pragma uvmf custom interface_item_additional end + + //****************************************************************** + task wait_for_reset();// pragma tbx xtf + @(posedge clock_i) ; + do_wait_for_reset(); + endtask + + // **************************************************************************** + task do_wait_for_reset(); + // pragma uvmf custom reset_condition begin + wait ( reset_i === 0 ) ; + @(posedge clock_i) ; + // pragma uvmf custom reset_condition end + endtask + + //****************************************************************** + + task wait_for_num_clocks(input int unsigned count); // pragma tbx xtf + @(posedge clock_i); + + repeat (count-1) @(posedge clock_i); + endtask + + //****************************************************************** + event go; + function void start_monitoring();// pragma tbx xtf + -> go; + endfunction + + // **************************************************************************** + initial begin + @go; + forever begin + @(posedge clock_i); + do_monitor( wb_m_monitor_struct ); + + + proxy.notify_transaction( wb_m_monitor_struct ); + + end + end + + //****************************************************************** + // The configure() function is used to pass agent configuration + // variables to the monitor BFM. It is called by the monitor within + // the agent at the beginning of the simulation. It may be called + // during the simulation if agent configuration variables are updated + // and the monitor BFM needs to be aware of the new configuration + // variables. + // + function void configure(wb_m_configuration_s wb_m_configuration_arg); // pragma tbx xtf + initiator_responder = wb_m_configuration_arg.initiator_responder; + // pragma uvmf custom configure begin + // pragma uvmf custom configure end + endfunction + + + // **************************************************************************** + + task do_monitor(output wb_m_monitor_s wb_m_monitor_struct); + // + // Available struct members: + // // wb_m_monitor_struct.data + // // wb_m_monitor_struct.byte_select + // // wb_m_monitor_struct.WrENB + // // wb_m_monitor_struct.selslv + // // + // Reference code; + // How to wait for signal value + // while (control_signal === 1'b1) @(posedge clock_i); + // + // How to assign a struct member, named xyz, from a signal. + // All available input signals listed. + // wb_m_monitor_struct.xyz = din_i; // [WB_DATA_WIDTH-1:0] + // wb_m_monitor_struct.xyz = dout_i; // [WB_DATA_WIDTH-1:0] + // wb_m_monitor_struct.xyz = TGD_I_i; // [WB_DATA_WIDTH-1:0] + // wb_m_monitor_struct.xyz = TGD_O_i; // [WB_DATA_WIDTH-1:0] + // wb_m_monitor_struct.xyz = ack_i; // + // wb_m_monitor_struct.xyz = adr_i; // [WB_ADDR_WIDTH-1:0] + // wb_m_monitor_struct.xyz = cyc_i; // + // wb_m_monitor_struct.xyz = err_i; // + // wb_m_monitor_struct.xyz = we_i; // + // wb_m_monitor_struct.xyz = stb_i; // + // wb_m_monitor_struct.xyz = sel_i; // [WB_DATA_WIDTH/8-1:0] + // pragma uvmf custom do_monitor begin + // UVMF_CHANGE_ME : Implement protocol monitoring. The commented reference code + // below are examples of how to capture signal values and assign them to + // structure members. All available input signals are listed. The 'while' + // code example shows how to wait for a synchronous flow control signal. This + // task should return when a complete transfer has been observed. Once this task is + // exited with captured values, it is then called again to wait for and observe + // the next transfer. One clock cycle is consumed between calls to do_monitor. + @(posedge clock_i); + @(posedge clock_i); + @(posedge clock_i); + @(posedge clock_i); + // pragma uvmf custom do_monitor end + endtask + + +endinterface + +// pragma uvmf custom external begin +// pragma uvmf custom external end +`endif diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/wb_m_pkg/src/wb_m_random_sequence.svh b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/wb_m_pkg/src/wb_m_random_sequence.svh new file mode 100644 index 00000000..8e2570eb --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/wb_m_pkg/src/wb_m_random_sequence.svh @@ -0,0 +1,67 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: +// This sequences randomizes the wb_m transaction and sends it +// to the UVM driver. +// +// This sequence constructs and randomizes a wb_m_transaction. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +`ifndef WB_M_RANDOM_SEQUENCE +`define WB_M_RANDOM_SEQUENCE +class wb_m_random_sequence #( + int WB_ADDR_WIDTH = 32, + int WB_DATA_WIDTH = 16 + ) + extends wb_m_sequence_base #( + .WB_ADDR_WIDTH(WB_ADDR_WIDTH), + .WB_DATA_WIDTH(WB_DATA_WIDTH) + ); + + `uvm_object_param_utils( wb_m_random_sequence #( + WB_ADDR_WIDTH, + WB_DATA_WIDTH + )) + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + //***************************************************************** + function new(string name = ""); + super.new(name); + endfunction: new + + // **************************************************************************** + // TASK : body() + // This task is automatically executed when this sequence is started using the + // start(sequencerHandle) task. + // + task body(); + + // Construct the transaction + req=wb_m_transaction#( + .WB_ADDR_WIDTH(WB_ADDR_WIDTH), + .WB_DATA_WIDTH(WB_DATA_WIDTH) + )::type_id::create("req"); + start_item(req); + // Randomize the transaction + if(!req.randomize()) `uvm_fatal("SEQ", "wb_m_random_sequence::body()-wb_m_transaction randomization failed") + // Send the transaction to the wb_m_driver_bfm via the sequencer and wb_m_driver. + finish_item(req); + `uvm_info("SEQ", {"Response:",req.convert2string()},UVM_MEDIUM) + + endtask + +endclass: wb_m_random_sequence + +// pragma uvmf custom external begin +// pragma uvmf custom external end +`endif diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/wb_m_pkg/src/wb_m_responder_sequence.svh b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/wb_m_pkg/src/wb_m_responder_sequence.svh new file mode 100644 index 00000000..672468c3 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/wb_m_pkg/src/wb_m_responder_sequence.svh @@ -0,0 +1,63 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This class can be used to provide stimulus when an interface +// has been configured to run in a responder mode. It +// will never finish by default, always going back to the driver +// and driver BFM for the next transaction with which to respond. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +`ifndef WB_M_RESPONDER_SEQUENCE +`define WB_M_RESPONDER_SEQUENCE +class wb_m_responder_sequence #( + int WB_ADDR_WIDTH = 32, + int WB_DATA_WIDTH = 16 + ) + extends wb_m_sequence_base #( + .WB_ADDR_WIDTH(WB_ADDR_WIDTH), + .WB_DATA_WIDTH(WB_DATA_WIDTH) + ); + + `uvm_object_param_utils( wb_m_responder_sequence #( + WB_ADDR_WIDTH, + WB_DATA_WIDTH + )) + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + function new(string name = "wb_m_responder_sequence"); + super.new(name); + endfunction + + task body(); + req=wb_m_transaction#( + .WB_ADDR_WIDTH(WB_ADDR_WIDTH), + .WB_DATA_WIDTH(WB_DATA_WIDTH) + )::type_id::create("req"); + forever begin + start_item(req); + finish_item(req); + // pragma uvmf custom body begin + // UVMF_CHANGE_ME : Do something here with the resulting req item. The + // finish_item() call above will block until the req transaction is ready + // to be handled by the responder sequence. + // If this was an item that required a response, the expectation is + // that the response should be populated within this transaction now. + `uvm_info("SEQ",$sformatf("Processed txn: %s",req.convert2string()),UVM_HIGH) + // pragma uvmf custom body end + end + endtask + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end +`endif diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/wb_m_pkg/src/wb_m_sequence_base.svh b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/wb_m_pkg/src/wb_m_sequence_base.svh new file mode 100644 index 00000000..4011b8a9 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/wb_m_pkg/src/wb_m_sequence_base.svh @@ -0,0 +1,116 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: +// This file contains the class used as the base class for all sequences +// for this interface. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +`ifndef WB_M_SEQUENCE_BASE +`define WB_M_SEQUENCE_BASE +class wb_m_sequence_base #( + int WB_ADDR_WIDTH = 32, + int WB_DATA_WIDTH = 16 + ) extends uvmf_sequence_base #( + .REQ(wb_m_transaction #( + .WB_ADDR_WIDTH(WB_ADDR_WIDTH), + .WB_DATA_WIDTH(WB_DATA_WIDTH) + )), + .RSP(wb_m_transaction #( + .WB_ADDR_WIDTH(WB_ADDR_WIDTH), + .WB_DATA_WIDTH(WB_DATA_WIDTH) + ))); + + `uvm_object_param_utils( wb_m_sequence_base #( + WB_ADDR_WIDTH, + WB_DATA_WIDTH + )) + + // variables + typedef wb_m_transaction #( + .WB_ADDR_WIDTH(WB_ADDR_WIDTH), + .WB_DATA_WIDTH(WB_DATA_WIDTH) + ) wb_m_transaction_req_t; + wb_m_transaction_req_t req; + typedef wb_m_transaction #( + .WB_ADDR_WIDTH(WB_ADDR_WIDTH), + .WB_DATA_WIDTH(WB_DATA_WIDTH) + ) wb_m_transaction_rsp_t; + wb_m_transaction_rsp_t rsp; + + // Event for identifying when a response was received from the sequencer + event new_rsp; + + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + // **************************************************************************** + // TASK : get_responses() + // This task recursively gets sequence item responses from the sequencer. + // + virtual task get_responses(); + fork + begin + // Block until new rsp available + get_response(rsp); + // New rsp received. Indicate to sequence using event. + ->new_rsp; + // Display the received response transaction + `uvm_info("SEQ", {"New response transaction:",rsp.convert2string()}, UVM_MEDIUM) + end + join_none + endtask + + // **************************************************************************** + // TASK : pre_body() + // This task is called automatically when start is called with call_pre_post set to 1 (default). + // By calling get_responses() within pre_body() any derived sequences are automatically + // processing response transactions. Only un-comment this call to get_responses() if you + // have configured the interface driver to utilize the response transaction path by setting + // the configuration variable "return_transaction_response" to 1. Otherwise it is possible + // to impact runtime performance and memory utilization. + // + virtual task pre_body(); + // pragma uvmf custom pre_body begin +// get_responses(); + // pragma uvmf custom pre_body end + endtask + + // **************************************************************************** + // TASK : body() + // This task is called automatically when start is called. This sequence sends + // a req sequence item to the sequencer identified as an argument in the call + // to start. + // + virtual task body(); + // pragma uvmf custom body begin + start_item(req); + finish_item(req); + // pragma uvmf custom body end + endtask + + // **************************************************************************** + // FUNCTION : new() + // This function is the standard SystemVerilog constructor. + // + function new( string name =""); + super.new( name ); + // pragma uvmf custom new begin + req = wb_m_transaction_req_t::type_id::create("req"); + rsp = wb_m_transaction_rsp_t::type_id::create("rsp"); + // pragma uvmf custom new end + endfunction + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end +`endif diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/wb_m_pkg/src/wb_m_transaction.svh b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/wb_m_pkg/src/wb_m_transaction.svh new file mode 100644 index 00000000..a7808d2a --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/wb_m_pkg/src/wb_m_transaction.svh @@ -0,0 +1,208 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This class defines the variables required for an wb_m +// transaction. Class variables to be displayed in waveform transaction +// viewing are added to the transaction viewing stream in the add_to_wave +// function. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +`ifndef WB_M_TRANSACTION +`define WB_M_TRANSACTION +class wb_m_transaction #( + int WB_ADDR_WIDTH = 32, + int WB_DATA_WIDTH = 16 + ) extends uvmf_transaction_base; + + `uvm_object_param_utils( wb_m_transaction #( + WB_ADDR_WIDTH, + WB_DATA_WIDTH + )) + + rand bit [WB_DATA_WIDTH-1:0] data ; + rand bit [(WB_DATA_WIDTH/8)-1:0] byte_select ; + rand bit WrENB ; + rand bit selslv ; + + //Constraints for the transaction variables: + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + //******************************************************************* + //******************************************************************* + // Macros that define structs and associated functions are + // located in wb_m_macros.svh + + //******************************************************************* + // Monitor macro used by wb_m_monitor and wb_m_monitor_bfm + // This struct is defined in wb_m_macros.svh + `wb_m_MONITOR_STRUCT + wb_m_monitor_s wb_m_monitor_struct; + //******************************************************************* + // FUNCTION: to_monitor_struct() + // This function packs transaction variables into a wb_m_monitor_s + // structure. The function returns the handle to the wb_m_monitor_struct. + // This function is defined in wb_m_macros.svh + `wb_m_TO_MONITOR_STRUCT_FUNCTION + //******************************************************************* + // FUNCTION: from_monitor_struct() + // This function unpacks the struct provided as an argument into transaction + // variables of this class. + // This function is defined in wb_m_macros.svh + `wb_m_FROM_MONITOR_STRUCT_FUNCTION + + //******************************************************************* + // Initiator macro used by wb_m_driver and wb_m_driver_bfm + // to communicate initiator driven data to wb_m_driver_bfm. + // This struct is defined in wb_m_macros.svh + `wb_m_INITIATOR_STRUCT + wb_m_initiator_s wb_m_initiator_struct; + //******************************************************************* + // FUNCTION: to_initiator_struct() + // This function packs transaction variables into a wb_m_initiator_s + // structure. The function returns the handle to the wb_m_initiator_struct. + // This function is defined in wb_m_macros.svh + `wb_m_TO_INITIATOR_STRUCT_FUNCTION + //******************************************************************* + // FUNCTION: from_initiator_struct() + // This function unpacks the struct provided as an argument into transaction + // variables of this class. + // This function is defined in wb_m_macros.svh + `wb_m_FROM_INITIATOR_STRUCT_FUNCTION + + //******************************************************************* + // Responder macro used by wb_m_driver and wb_m_driver_bfm + // to communicate Responder driven data to wb_m_driver_bfm. + // This struct is defined in wb_m_macros.svh + `wb_m_RESPONDER_STRUCT + wb_m_responder_s wb_m_responder_struct; + //******************************************************************* + // FUNCTION: to_responder_struct() + // This function packs transaction variables into a wb_m_responder_s + // structure. The function returns the handle to the wb_m_responder_struct. + // This function is defined in wb_m_macros.svh + `wb_m_TO_RESPONDER_STRUCT_FUNCTION + //******************************************************************* + // FUNCTION: from_responder_struct() + // This function unpacks the struct provided as an argument into transaction + // variables of this class. + // This function is defined in wb_m_macros.svh + `wb_m_FROM_RESPONDER_STRUCT_FUNCTION + // **************************************************************************** + // FUNCTION : new() + // This function is the standard SystemVerilog constructor. + // + function new( string name = "" ); + super.new( name ); + endfunction + + // **************************************************************************** + // FUNCTION: convert2string() + // This function converts all variables in this class to a single string for + // logfile reporting. + // + virtual function string convert2string(); + // pragma uvmf custom convert2string begin + // UVMF_CHANGE_ME : Customize format if desired. + return $sformatf("data:0x%x byte_select:0x%x WrENB:0x%x selslv:0x%x ",data,byte_select,WrENB,selslv); + // pragma uvmf custom convert2string end + endfunction + + //******************************************************************* + // FUNCTION: do_print() + // This function is automatically called when the .print() function + // is called on this class. + // + virtual function void do_print(uvm_printer printer); + // pragma uvmf custom do_print begin + // UVMF_CHANGE_ME : Current contents of do_print allows for the use of UVM 1.1d, 1.2 or P1800.2. + // Update based on your own printing preference according to your preferred UVM version + $display(convert2string()); + // pragma uvmf custom do_print end + endfunction + + //******************************************************************* + // FUNCTION: do_compare() + // This function is automatically called when the .compare() function + // is called on this class. + // + virtual function bit do_compare (uvm_object rhs, uvm_comparer comparer); + wb_m_transaction #( + .WB_ADDR_WIDTH(WB_ADDR_WIDTH), + .WB_DATA_WIDTH(WB_DATA_WIDTH) + ) RHS; + if (!$cast(RHS,rhs)) return 0; + // pragma uvmf custom do_compare begin + // UVMF_CHANGE_ME : Eliminate comparison of variables not to be used for compare + return (super.do_compare(rhs,comparer) + &&(this.data == RHS.data) + &&(this.byte_select == RHS.byte_select) + &&(this.WrENB == RHS.WrENB) + &&(this.selslv == RHS.selslv) + ); + // pragma uvmf custom do_compare end + endfunction + + //******************************************************************* + // FUNCTION: do_copy() + // This function is automatically called when the .copy() function + // is called on this class. + // + virtual function void do_copy (uvm_object rhs); + wb_m_transaction #( + .WB_ADDR_WIDTH(WB_ADDR_WIDTH), + .WB_DATA_WIDTH(WB_DATA_WIDTH) + ) RHS; + assert($cast(RHS,rhs)); + // pragma uvmf custom do_copy begin + super.do_copy(rhs); + this.data = RHS.data; + this.byte_select = RHS.byte_select; + this.WrENB = RHS.WrENB; + this.selslv = RHS.selslv; + // pragma uvmf custom do_copy end + endfunction + + // **************************************************************************** + // FUNCTION: add_to_wave() + // This function is used to display variables in this class in the waveform + // viewer. The start_time and end_time variables must be set before this + // function is called. If the start_time and end_time variables are not set + // the transaction will be hidden at 0ns on the waveform display. + // + virtual function void add_to_wave(int transaction_viewing_stream_h); + `ifdef QUESTA + if (transaction_view_h == 0) begin + transaction_view_h = $begin_transaction(transaction_viewing_stream_h,"wb_m_transaction",start_time); + end + super.add_to_wave(transaction_view_h); + // pragma uvmf custom add_to_wave begin + // UVMF_CHANGE_ME : Color can be applied to transaction entries based on content, example below + // case() + // 1 : $add_color(transaction_view_h,"red"); + // default : $add_color(transaction_view_h,"grey"); + // endcase + // UVMF_CHANGE_ME : Eliminate transaction variables not wanted in transaction viewing in the waveform viewer + $add_attribute(transaction_view_h,data,"data"); + $add_attribute(transaction_view_h,byte_select,"byte_select"); + $add_attribute(transaction_view_h,WrENB,"WrENB"); + $add_attribute(transaction_view_h,selslv,"selslv"); + // pragma uvmf custom add_to_wave end + $end_transaction(transaction_view_h,end_time); + $free_transaction(transaction_view_h); + `endif // QUESTA + endfunction + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end +`endif diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/wb_m_pkg/src/wb_m_transaction_coverage.svh b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/wb_m_pkg/src/wb_m_transaction_coverage.svh new file mode 100644 index 00000000..a0243e95 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/wb_m_pkg/src/wb_m_transaction_coverage.svh @@ -0,0 +1,85 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This class records wb_m transaction information using +// a covergroup named wb_m_transaction_cg. An instance of this +// coverage component is instantiated in the uvmf_parameterized_agent +// if the has_coverage flag is set. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +`ifndef WB_M_TRANSACTION_COVERAGE +`define WB_M_TRANSACTION_COVERAGE +class wb_m_transaction_coverage #( + int WB_ADDR_WIDTH = 32, + int WB_DATA_WIDTH = 16 + ) extends uvm_subscriber #(.T(wb_m_transaction #( + .WB_ADDR_WIDTH(WB_ADDR_WIDTH), + .WB_DATA_WIDTH(WB_DATA_WIDTH) + ))); + + `uvm_component_param_utils( wb_m_transaction_coverage #( + WB_ADDR_WIDTH, + WB_DATA_WIDTH + )) + + T coverage_trans; + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + // **************************************************************************** + covergroup wb_m_transaction_cg; + // pragma uvmf custom covergroup begin + // UVMF_CHANGE_ME : Add coverage bins, crosses, exclusions, etc. according to coverage needs. + option.auto_bin_max=1024; + option.per_instance=1; + data: coverpoint coverage_trans.data; + byte_select: coverpoint coverage_trans.byte_select; + WrENB: coverpoint coverage_trans.WrENB; + selslv: coverpoint coverage_trans.selslv; + // pragma uvmf custom covergroup end + endgroup + + // **************************************************************************** + // FUNCTION : new() + // This function is the standard SystemVerilog constructor. + // + function new(string name="", uvm_component parent=null); + super.new(name,parent); + wb_m_transaction_cg=new; + `uvm_warning("COVERAGE_MODEL_REVIEW", "A covergroup has been constructed which may need review because of either generation or re-generation with merging. Please note that transaction variables added as a result of re-generation and merging are not automatically added to the covergroup. Remove this warning after the covergroup has been reviewed.") + endfunction + + // **************************************************************************** + // FUNCTION : build_phase() + // This function is the standard UVM build_phase. + // + function void build_phase(uvm_phase phase); + wb_m_transaction_cg.set_inst_name($sformatf("wb_m_transaction_cg_%s",get_full_name())); + endfunction + + // **************************************************************************** + // FUNCTION: write (T t) + // This function is automatically executed when a transaction arrives on the + // analysis_export. It copies values from the variables in the transaction + // to local variables used to collect functional coverage. + // + virtual function void write (T t); + `uvm_info("COV","Received transaction",UVM_HIGH); + coverage_trans = t; + wb_m_transaction_cg.sample(); + endfunction + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + +`endif diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/wb_m_pkg/src/wb_m_typedefs.svh b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/wb_m_pkg/src/wb_m_typedefs.svh new file mode 100644 index 00000000..91e77a1c --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/wb_m_pkg/src/wb_m_typedefs.svh @@ -0,0 +1,21 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: +// This file contains defines and typedefs to be compiled for use in +// the simulation running on the host server when using Veloce. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +`ifndef TYPEDEFS_HVL +`definr TYPEDEFS_HVL + +// pragma uvmf custom additional begin +// pragma uvmf custom additional end +`endif diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/wb_m_pkg/src/wb_m_typedefs_hdl.svh b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/wb_m_pkg/src/wb_m_typedefs_hdl.svh new file mode 100644 index 00000000..bd6b6f41 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/wb_m_pkg/src/wb_m_typedefs_hdl.svh @@ -0,0 +1,23 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: +// This file contains defines and typedefs to be compiled for use in +// the simulation running on the emulator when using Veloce. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// + +`ifndef TYPEDEFS_HVL +`definr TYPEDEFS_HVL + + +// pragma uvmf custom additional begin +// pragma uvmf custom additional end +`endif diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/wb_m_pkg/wb_m.compile b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/wb_m_pkg/wb_m.compile new file mode 100644 index 00000000..fd2781af --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/wb_m_pkg/wb_m.compile @@ -0,0 +1,3 @@ +needs: + - wb_m_hvl.compile + - wb_m_hdl.compile diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/wb_m_pkg/wb_m_bfm.vinfo b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/wb_m_pkg/wb_m_bfm.vinfo new file mode 100644 index 00000000..41134f65 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/wb_m_pkg/wb_m_bfm.vinfo @@ -0,0 +1,6 @@ +@use $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg_hdl.vinfo +@use wb_m_pkg_hdl.vinfo ++incdir+@vinfodir +src/wb_m_if.sv +src/wb_m_driver_bfm.sv +src/wb_m_monitor_bfm.sv diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/wb_m_pkg/wb_m_common.compile b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/wb_m_pkg/wb_m_common.compile new file mode 100644 index 00000000..abbb916d --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/wb_m_pkg/wb_m_common.compile @@ -0,0 +1,7 @@ +needs: + - $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg_hdl.compile +incdir: + - . + - ${uvm_path}/src +src: + - wb_m_pkg_hdl.sv diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/wb_m_pkg/wb_m_filelist_hdl.f b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/wb_m_pkg/wb_m_filelist_hdl.f new file mode 100644 index 00000000..2b237fad --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/wb_m_pkg/wb_m_filelist_hdl.f @@ -0,0 +1 @@ +$UVMF_VIP_LIBRARY_HOME/interface_packages/wb_m_pkg/wb_m_pkg_hdl.sv diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/wb_m_pkg/wb_m_filelist_hvl.f b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/wb_m_pkg/wb_m_filelist_hvl.f new file mode 100644 index 00000000..4ec20bef --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/wb_m_pkg/wb_m_filelist_hvl.f @@ -0,0 +1 @@ +$UVMF_VIP_LIBRARY_HOME/interface_packages/wb_m_pkg/wb_m_pkg.sv \ No newline at end of file diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/wb_m_pkg/wb_m_filelist_xrtl.f b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/wb_m_pkg/wb_m_filelist_xrtl.f new file mode 100644 index 00000000..6e2ee491 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/wb_m_pkg/wb_m_filelist_xrtl.f @@ -0,0 +1,3 @@ +$UVMF_VIP_LIBRARY_HOME/interface_packages/wb_m_pkg/src/wb_m_if.sv +$UVMF_VIP_LIBRARY_HOME/interface_packages/wb_m_pkg/src/wb_m_monitor_bfm.sv +$UVMF_VIP_LIBRARY_HOME/interface_packages/wb_m_pkg/src/wb_m_driver_bfm.sv diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/wb_m_pkg/wb_m_hdl.compile b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/wb_m_pkg/wb_m_hdl.compile new file mode 100644 index 00000000..0096f879 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/wb_m_pkg/wb_m_hdl.compile @@ -0,0 +1,9 @@ +needs: + - $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg_hdl.compile + - ./wb_m_common.compile +incdir: + - . +src: + - src/wb_m_if.sv + - src/wb_m_monitor_bfm.sv + - src/wb_m_driver_bfm.sv diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/wb_m_pkg/wb_m_hvl.compile b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/wb_m_pkg/wb_m_hvl.compile new file mode 100644 index 00000000..dd992808 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/wb_m_pkg/wb_m_hvl.compile @@ -0,0 +1,7 @@ +needs: + - $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg.compile + - ./wb_m_common.compile +incdir: + - . +src: + - wb_m_pkg.sv diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/wb_m_pkg/wb_m_pkg.sv b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/wb_m_pkg/wb_m_pkg.sv new file mode 100644 index 00000000..b1c6f19a --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/wb_m_pkg/wb_m_pkg.sv @@ -0,0 +1,79 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// PACKAGE: This file defines all of the files contained in the +// interface package that will run on the host simulator. +// +// CONTAINS: +// - +// - +// - + +// - +// - +// - + +// - +// - +// - + +// - +// - +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +`ifndef WB_M_PKG +`define WB_M_PKG +package wb_m_pkg; + + import uvm_pkg::*; + import uvmf_base_pkg_hdl::*; + import uvmf_base_pkg::*; + import wb_m_pkg_hdl::*; + + `include "uvm_macros.svh" + + // pragma uvmf custom package_imports_additional begin + // pragma uvmf custom package_imports_additional end + `include "src/wb_m_macros.svh" + + export wb_m_pkg_hdl::*; + + + + // Parameters defined as HVL parameters + + `include "src/wb_m_typedefs.svh" + `include "src/wb_m_transaction.svh" + + `include "src/wb_m_configuration.svh" + `include "src/wb_m_driver.svh" + `include "src/wb_m_monitor.svh" + + `include "src/wb_m_transaction_coverage.svh" + `include "src/wb_m_sequence_base.svh" + `include "src/wb_m_random_sequence.svh" + + `include "src/wb_m_responder_sequence.svh" + `include "src/wb_m2reg_adapter.svh" + + `include "src/wb_m_agent.svh" + + // pragma uvmf custom package_item_additional begin + // UVMF_CHANGE_ME : When adding new interface sequences to the src directory + // be sure to add the sequence file here so that it will be + // compiled as part of the interface package. Be sure to place + // the new sequence after any base sequences of the new sequence. + // pragma uvmf custom package_item_additional end + +endpackage + +// pragma uvmf custom external begin +// pragma uvmf custom external end +`endif diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/wb_m_pkg/wb_m_pkg.vinfo b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/wb_m_pkg/wb_m_pkg.vinfo new file mode 100644 index 00000000..5507608c --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/wb_m_pkg/wb_m_pkg.vinfo @@ -0,0 +1,4 @@ +@use $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg.vinfo +@use wb_m_pkg_hdl.vinfo ++incdir+@vinfodir +wb_m_pkg.sv diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/wb_m_pkg/wb_m_pkg_hdl.sv b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/wb_m_pkg/wb_m_pkg_hdl.sv new file mode 100644 index 00000000..79989e19 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/wb_m_pkg/wb_m_pkg_hdl.sv @@ -0,0 +1,40 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// PACKAGE: This file defines all of the files contained in the +// interface package that needs to be compiled and synthesized +// for running on Veloce. +// +// CONTAINS: +// - +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +`ifndef WB_M_PKG_HDL +`define WB_M_PKG_HDL +package wb_m_pkg_hdl; + + import uvmf_base_pkg_hdl::*; + + // pragma uvmf custom package_imports_additional begin + // pragma uvmf custom package_imports_additional end + + // Parameters defined as HDL parameters + + `include "src/wb_m_typedefs_hdl.svh" + `include "src/wb_m_macros.svh" + + // pragma uvmf custom package_item_additional begin + // pragma uvmf custom package_item_additional end + +endpackage + +// pragma uvmf custom external begin +// pragma uvmf custom external end +`endif diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/wb_m_pkg/wb_m_pkg_hdl.vinfo b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/wb_m_pkg/wb_m_pkg_hdl.vinfo new file mode 100644 index 00000000..24e5d862 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/wb_m_pkg/wb_m_pkg_hdl.vinfo @@ -0,0 +1,2 @@ +@use $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg_hdl.vinfo +wb_m_pkg_hdl.sv diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/wb_m_pkg/wb_m_pkg_sve.F b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/wb_m_pkg/wb_m_pkg_sve.F new file mode 100644 index 00000000..2f158a42 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/wb_m_pkg/wb_m_pkg_sve.F @@ -0,0 +1,10 @@ +// UVM ++incdir+${UVM_HOME}/src +${UVM_HOME}/src/uvm_pkg.sv + +// Common UVMF files +-f ${UVMF_HOME}/common/common_sve.f + ++incdir+. +-f ${UVMF_VIP_LIBRARY_HOME}/interface_packages/wb_m_pkg/wb_m_filelist_hdl.f +-f ${UVMF_VIP_LIBRARY_HOME}/interface_packages/wb_m_pkg/wb_m_filelist_hvl.f diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/wb_m_pkg/yaml/wb_m_interface.yaml b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/wb_m_pkg/yaml/wb_m_interface.yaml new file mode 100644 index 00000000..0057e3d0 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/wb_m_pkg/yaml/wb_m_interface.yaml @@ -0,0 +1,93 @@ +uvmf: + interfaces: + wb_m: + clock: clock + config_constraints: [] + config_vars: [] + existing_library_component: 'True' + gen_inbound_streaming_driver: 'False' + hdl_pkg_parameters: [] + hdl_typedefs: [] + hvl_pkg_parameters: [] + hvl_typedefs: [] + parameters: + - name: WB_ADDR_WIDTH + type: int + value: '32' + - name: WB_DATA_WIDTH + type: int + value: '16' + ports: + - dir: input + name: din + reset_value: '''b0' + width: WB_DATA_WIDTH + - dir: output + name: dout + reset_value: '''b0' + width: WB_DATA_WIDTH + - dir: input + name: TGD_I + reset_value: '''bz' + width: WB_DATA_WIDTH + - dir: output + name: TGD_O + reset_value: '''bz' + width: WB_DATA_WIDTH + - dir: output + name: ack + reset_value: 1'b0 + width: '1' + - dir: output + name: adr + reset_value: '''b0' + width: WB_ADDR_WIDTH + - dir: output + name: cyc + reset_value: '0' + width: '1' + - dir: input + name: err + reset_value: '''b0' + width: '1' + - dir: output + name: we + reset_value: '0' + width: '1' + - dir: output + name: stb + reset_value: '0' + width: '1' + - dir: output + name: sel + reset_value: '''b0' + width: WB_DATA_WIDTH/8 + reset: reset + reset_assertion_level: 'True' + transaction_constraints: [] + transaction_vars: + - comment: '' + iscompare: 'True' + isrand: 'True' + name: data + type: bit [WB_DATA_WIDTH-1:0] + unpacked_dimension: '' + - comment: '' + iscompare: 'True' + isrand: 'True' + name: byte_select + type: bit [(WB_DATA_WIDTH/8)-1:0] + unpacked_dimension: '' + - comment: '' + iscompare: 'True' + isrand: 'True' + name: WrENB + type: bit + unpacked_dimension: '' + - comment: '' + iscompare: 'True' + isrand: 'True' + name: selslv + type: bit + unpacked_dimension: '' + use_dpi_link: 'False' diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/wb_s_pkg/.project b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/wb_s_pkg/.project new file mode 100644 index 00000000..d9963c6a --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/wb_s_pkg/.project @@ -0,0 +1,30 @@ + + + wb_s_pkg + + + + + + org.python.pydev.PyDevBuilder + + + + + net.sf.sveditor.core.SVProjectBuilder + + + + + + net.sf.sveditor.core.SVNature + org.python.pydev.pythonNature + + + + UVMF_VIP_LIBRARY_HOME + $%7BPARENT-2-PROJECT_LOC%7D + + + + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/wb_s_pkg/.svproject b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/wb_s_pkg/.svproject new file mode 100644 index 00000000..0edf84a9 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/wb_s_pkg/.svproject @@ -0,0 +1,16 @@ + + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/wb_s_pkg/Makefile b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/wb_s_pkg/Makefile new file mode 100644 index 00000000..2ccf8e80 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/wb_s_pkg/Makefile @@ -0,0 +1,66 @@ +# wb_s interface packages source +# pragma uvmf custom additional begin +# pragma uvmf custom additional end + +wb_s_PKG = \ + +incdir+$(UVMF_VIP_LIBRARY_HOME)/interface_packages/wb_s_pkg \ + -F $(UVMF_VIP_LIBRARY_HOME)/interface_packages/wb_s_pkg/wb_s_filelist_hvl.f + +wb_s_PKG_HDL = \ + +incdir+$(UVMF_VIP_LIBRARY_HOME)/interface_packages/wb_s_pkg \ + -F $(UVMF_VIP_LIBRARY_HOME)/interface_packages/wb_s_pkg/wb_s_filelist_hdl.f + +wb_s_PKG_XRTL = \ + +incdir+$(UVMF_VIP_LIBRARY_HOME)/interface_packages/wb_s_pkg \ + -F $(UVMF_VIP_LIBRARY_HOME)/interface_packages/wb_s_pkg/wb_s_filelist_xrtl.f + +COMP_wb_s_PKG_TGT_0 = q_comp_wb_s_pkg +COMP_wb_s_PKG_TGT_1 = v_comp_wb_s_pkg +COMP_wb_s_PKG_TGT = $(COMP_wb_s_PKG_TGT_$(USE_VELOCE)) + +comp_wb_s_pkg: $(COMP_wb_s_PKG_TGT) + +q_comp_wb_s_pkg: + $(HDL_COMP_CMD) $(wb_s_PKG_HDL) + $(HVL_COMP_CMD) $(wb_s_PKG) + $(HDL_COMP_CMD) $(wb_s_PKG_XRTL) + +v_comp_wb_s_pkg: + $(HVL_COMP_CMD) $(wb_s_PKG_HDL) + $(HVL_COMP_CMD) $(wb_s_PKG) + $(VELANALYZE_CMD) $(wb_s_PKG_HDL) + $(VELANALYZE_HVL_CMD) $(wb_s_PKG) + $(HDL_COMP_CMD) $(wb_s_PKG_XRTL) + +ifeq ($(MTI_VCO_MODE),64) + GCC_COMP_ARCH = -m64 +else + GCC_COMP_ARCH = -m32 +endif + +export wb_s_IF_DPI_SRC ?= $(UVMF_VIP_LIBRARY_HOME)/interface_packages/wb_s_pkg/dpi + +C_FILE_COMPILE_LIST_wb_s_pkg = \ + +O_FILE_COMPILE_LIST_wb_s_pkg = $(notdir $(C_FILE_COMPILE_LIST_wb_s_pkg:.c=.o)) + +GCC_COMP_ARGS_wb_s_pkg += -I$(wb_s_IF_DPI_SRC) \ + -fPIC + +GCC_COMP_ARGS_wb_s_pkg += $(wb_s_IF_GCC_COMP_ARGUMENTS) + +GCC_LINK_ARGS_wb_s_pkg += \ + \ + -o .so + +comp_wb_s_pkg_c_files: + @echo "--------------------------------" + @echo "Compiling Interface C source" + @echo "--------------------------------" + gcc $(GCC_COMP_ARCH) $(GCC_COMP_ARGS_wb_s_pkg) $(C_FILE_COMPILE_LIST_wb_s_pkg) + @echo "--------------------------------" + @echo "Linking Interface C objects into a shared object" + @echo "--------------------------------" + gcc $(GCC_COMP_ARCH) $(GCC_LINK_ARGS_wb_s_pkg) $(O_FILE_COMPILE_LIST_wb_s_pkg) + @echo "--------------------------------" + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/wb_s_pkg/compile.do b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/wb_s_pkg/compile.do new file mode 100644 index 00000000..55cf9dcd --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/wb_s_pkg/compile.do @@ -0,0 +1,14 @@ +# Tcl do file for compile of wb_s interface + +# pragma uvmf custom additional begin +# pragma uvmf custom additional end + + +vlog -sv -timescale 1ps/1ps -suppress 2223,2286 +incdir+$env(UVMF_VIP_LIBRARY_HOME)/interface_packages/wb_s_pkg \ + -F $env(UVMF_VIP_LIBRARY_HOME)/interface_packages/wb_s_pkg/wb_s_filelist_hdl.f + +vlog -sv -timescale 1ps/1ps -suppress 2223,2286 +incdir+$env(UVMF_VIP_LIBRARY_HOME)/interface_packages/wb_s_pkg \ + -F $env(UVMF_VIP_LIBRARY_HOME)/interface_packages/wb_s_pkg/wb_s_filelist_hvl.f + +vlog -sv -timescale 1ps/1ps -suppress 2223,2286 +incdir+$env(UVMF_VIP_LIBRARY_HOME)/interface_packages/wb_s_pkg \ + -F $env(UVMF_VIP_LIBRARY_HOME)/interface_packages/wb_s_pkg/wb_s_filelist_xrtl.f \ No newline at end of file diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/wb_s_pkg/src/wb_s2reg_adapter.svh b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/wb_s_pkg/src/wb_s2reg_adapter.svh new file mode 100644 index 00000000..35370a2d --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/wb_s_pkg/src/wb_s2reg_adapter.svh @@ -0,0 +1,115 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: +// This file contains the UVM register adapter for the wb_s interface. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +`ifndef WB_S2REG_ADAPTER +`define WB_S2REG_ADAPTER +class wb_s2reg_adapter #( + int WB_ADDR_WIDTH = 32, + int WB_DATA_WIDTH = 16 + ) extends uvm_reg_adapter; + + `uvm_object_param_utils( wb_s2reg_adapter #( + WB_ADDR_WIDTH, + WB_DATA_WIDTH + )) + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + //-------------------------------------------------------------------- + // new + //-------------------------------------------------------------------- + function new (string name = "wb_s2reg_adapter" ); + super.new(name); + // pragma uvmf custom new begin + // UVMF_CHANGE_ME : Configure the adapter regarding byte enables and provides response. + + // Does the protocol the Agent is modeling support byte enables? + // 0 = NO + // 1 = YES + supports_byte_enable = 0; + + // Does the Agent's Driver provide separate response sequence items? + // i.e. Does the driver call seq_item_port.put() + // and do the sequences call get_response()? + // 0 = NO + // 1 = YES + provides_responses = 0; + // pragma uvmf custom new end + + endfunction: new + + //-------------------------------------------------------------------- + // reg2bus + //-------------------------------------------------------------------- + virtual function uvm_sequence_item reg2bus(const ref uvm_reg_bus_op rw); + + wb_s_transaction #( + .WB_ADDR_WIDTH(WB_ADDR_WIDTH), + .WB_DATA_WIDTH(WB_DATA_WIDTH) + ) trans_h = wb_s_transaction #( + .WB_ADDR_WIDTH(WB_ADDR_WIDTH), + .WB_DATA_WIDTH(WB_DATA_WIDTH) + )::type_id::create("trans_h"); + + // pragma uvmf custom reg2bus begin + // UVMF_CHANGE_ME : Fill in the reg2bus adapter mapping registe fields to protocol fields. + + //Adapt the following for your sequence item type + // trans_h.op = (rw.kind == UVM_READ) ? WB_READ : WB_WRITE; + //Copy over address + // trans_h.addr = rw.addr; + //Copy over write data + // trans_h.data = rw.data; + + // pragma uvmf custom reg2bus end + + // Return the adapted transaction + return trans_h; + + endfunction: reg2bus + + //-------------------------------------------------------------------- + // bus2reg + //-------------------------------------------------------------------- + virtual function void bus2reg(uvm_sequence_item bus_item, + ref uvm_reg_bus_op rw); + wb_s_transaction #( + .WB_ADDR_WIDTH(WB_ADDR_WIDTH), + .WB_DATA_WIDTH(WB_DATA_WIDTH) + ) trans_h; + if (!$cast(trans_h, bus_item)) begin + `uvm_fatal("ADAPT","Provided bus_item is not of the correct type") + return; + end + // pragma uvmf custom bus2reg begin + // UVMF_CHANGE_ME : Fill in the bus2reg adapter mapping protocol fields to register fields. + //Adapt the following for your sequence item type + //Copy over instruction type + // rw.kind = (trans_h.op == WB_WRITE) ? UVM_WRITE : UVM_READ; + //Copy over address + // rw.addr = trans_h.addr; + //Copy over read data + // rw.data = trans_h.data; + //Check for errors on the bus and return UVM_NOT_OK if there is an error + // rw.status = UVM_IS_OK; + // pragma uvmf custom bus2reg end + + endfunction: bus2reg + +endclass : wb_s2reg_adapter + +// pragma uvmf custom external begin +// pragma uvmf custom external end +`endif diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/wb_s_pkg/src/wb_s_agent.svh b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/wb_s_pkg/src/wb_s_agent.svh new file mode 100644 index 00000000..0ba32fe2 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/wb_s_pkg/src/wb_s_agent.svh @@ -0,0 +1,79 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: Protocol specific agent class definition +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// + +`ifndef WB_S_AGENT +`define WB_S_AGENT + +class wb_s_agent #( + int WB_ADDR_WIDTH = 32, + int WB_DATA_WIDTH = 16 + ) extends uvmf_parameterized_agent #( + .CONFIG_T(wb_s_configuration #( + .WB_ADDR_WIDTH(WB_ADDR_WIDTH), + .WB_DATA_WIDTH(WB_DATA_WIDTH) + )), + .DRIVER_T(wb_s_driver #( + .WB_ADDR_WIDTH(WB_ADDR_WIDTH), + .WB_DATA_WIDTH(WB_DATA_WIDTH) + )), + .MONITOR_T(wb_s_monitor #( + .WB_ADDR_WIDTH(WB_ADDR_WIDTH), + .WB_DATA_WIDTH(WB_DATA_WIDTH) + )), + .COVERAGE_T(wb_s_transaction_coverage #( + .WB_ADDR_WIDTH(WB_ADDR_WIDTH), + .WB_DATA_WIDTH(WB_DATA_WIDTH) + )), + .TRANS_T(wb_s_transaction #( + .WB_ADDR_WIDTH(WB_ADDR_WIDTH), + .WB_DATA_WIDTH(WB_DATA_WIDTH) + )) + ); + + `uvm_component_param_utils( wb_s_agent #( + WB_ADDR_WIDTH, + WB_DATA_WIDTH + )) + +// pragma uvmf custom class_item_additional begin +// pragma uvmf custom class_item_additional end + +// **************************************************************************** +// FUNCTION : new() +// This function is the standard SystemVerilog constructor. +// + function new( string name = "", uvm_component parent = null ); + super.new( name, parent ); + endfunction + +// **************************************************************************** + // FUNCTION: build_phase + virtual function void build_phase(uvm_phase phase); +// pragma uvmf custom build_phase_pre_super begin +// pragma uvmf custom build_phase_pre_super end + super.build_phase(phase); + if (configuration.active_passive == ACTIVE) begin + // Place sequencer handle into configuration object + // so that it may be retrieved from configuration + // rather than using uvm_config_db + configuration.sequencer = this.sequencer; + end + endfunction + +endclass + + +// pragma uvmf custom external begin +// pragma uvmf custom external end +`endif diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/wb_s_pkg/src/wb_s_configuration.svh b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/wb_s_pkg/src/wb_s_configuration.svh new file mode 100644 index 00000000..2edf1987 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/wb_s_pkg/src/wb_s_configuration.svh @@ -0,0 +1,206 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This class contains all variables and functions used +// to configure the wb_s agent and its bfm's. It gets the +// bfm's from the uvm_config_db for use by the agent. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// + +`ifndef WB_S_CONFIGURATION +`define WB_S_CONFIGURATION +class wb_s_configuration #( + int WB_ADDR_WIDTH = 32, + int WB_DATA_WIDTH = 16 + ) extends uvmf_parameterized_agent_configuration_base #( + .DRIVER_BFM_BIND_T(virtual wb_s_driver_bfm #( + .WB_ADDR_WIDTH(WB_ADDR_WIDTH), + .WB_DATA_WIDTH(WB_DATA_WIDTH) + )), + .MONITOR_BFM_BIND_T( virtual wb_s_monitor_bfm #( + .WB_ADDR_WIDTH(WB_ADDR_WIDTH), + .WB_DATA_WIDTH(WB_DATA_WIDTH) + ))); + + `uvm_object_param_utils( wb_s_configuration #( + WB_ADDR_WIDTH, + WB_DATA_WIDTH + )) + + + // Sequencer handle populated by agent + uvm_sequencer #(wb_s_transaction #( + .WB_ADDR_WIDTH(WB_ADDR_WIDTH), + .WB_DATA_WIDTH(WB_DATA_WIDTH) + ) ) sequencer; + + //Constraints for the configuration variables: + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + covergroup wb_s_configuration_cg; + // pragma uvmf custom covergroup begin + option.auto_bin_max=1024; + // pragma uvmf custom covergroup end + endgroup + + //******************************************************************* + //******************************************************************* + // Structure used to pass configuration variables to monitor and driver BFM's. + // Use to_struct function to pack variables into structure. + // Use from_struct function to unpack variables from structure. + // This structure is defined in wb_s_macros.svh + `wb_s_CONFIGURATION_STRUCT + wb_s_configuration_s wb_s_configuration_struct; + //******************************************************************* + // FUNCTION: to_struct() + // This function packs variables into a wb_s_configuration_s + // structure. The function returns the handle to the wb_s_configuration_struct. + // This function is defined in wb_s_macros.svh + `wb_s_CONFIGURATION_TO_STRUCT_FUNCTION + //******************************************************************* + // FUNCTION: from_struct() + // This function unpacks the struct provided as an argument into + // variables of this class. + // This function is defined in wb_s_macros.svh + `wb_s_CONFIGURATION_FROM_STRUCT_FUNCTION + + // **************************************************************************** + // FUNCTION : new() + // This function is the standard SystemVerilog constructor. + // + function new( string name = "" ); + super.new( name ); + // Construct the covergroup for this configuration class + wb_s_configuration_cg = new; + endfunction + + // **************************************************************************** + // FUNCTION: post_randomize() + // This function is automatically called after the randomize() function + // is executed. + // + function void post_randomize(); + super.post_randomize(); + wb_s_configuration_cg.sample(); + endfunction + + // **************************************************************************** + // FUNCTION: initialize + // This function causes the configuration to retrieve + // its virtual interface handle from the uvm_config_db. + // This function also makes itself available to its + // agent through the uvm_config_db. + // + // ARGUMENTS: + // uvmf_active_passive_t activity: + // This argument identifies the simulation level + // as either BLOCK, CHIP, SIMULATION, etc. + // + // AGENT_PATH: + // This argument identifies the path to this + // configurations agent. This configuration + // makes itself available to the agent specified + // by agent_path by placing itself into the + // uvm_config_db. + // + // INTERFACE_NAME: + // This argument identifies the string name of + // this configurations BFM's. This string + // name is used to retrieve the driver and + // monitor BFM from the uvm_config_db. + // + virtual function void initialize(uvmf_active_passive_t activity, + string agent_path, + string interface_name); + + super.initialize( activity, agent_path, interface_name); + // The covergroup is given the same name as the interface + wb_s_configuration_cg.set_inst_name(interface_name); + + // This configuration places itself into the uvm_config_db for the agent, identified by the agent_path variable, to retrieve. + uvm_config_db #( wb_s_configuration #( + .WB_ADDR_WIDTH(WB_ADDR_WIDTH), + .WB_DATA_WIDTH(WB_DATA_WIDTH) + ) + )::set( null ,agent_path,UVMF_AGENT_CONFIG, this ); + + // This configuration also places itself in the config db using the same identifier used by the interface. This allows users to access + // configuration variables and the interface through the bfm api class rather than directly accessing the BFM. This is useful for + // accessingthe BFM when using Veloce + uvm_config_db #( wb_s_configuration #( + .WB_ADDR_WIDTH(WB_ADDR_WIDTH), + .WB_DATA_WIDTH(WB_DATA_WIDTH) + ) + )::set( null ,UVMF_CONFIGURATIONS, interface_name, this ); + + wb_s_configuration_cg.set_inst_name($sformatf("wb_s_configuration_cg_%s",get_full_name())); + +// This code is to aid in debugging parameter mismatches between the BFM and its corresponding agent. +// Enable this debug by setting UVM_VERBOSITY to UVM_DEBUG +// Setting UVM_VERBOSITY to UVM_DEBUG causes all BFM's and all agents to display their parameter settings. +// All of the messages from this feature have a UVM messaging id value of "CFG" +// The transcript or run.log can be parsed to ensure BFM parameter settings match its corresponding agents parameter settings. + `uvm_info("CFG", + $psprintf("The agent at '%s' is using interface named %s has the following parameters: WB_ADDR_WIDTH=%x WB_DATA_WIDTH=%x ", agent_path, interface_name, WB_ADDR_WIDTH ,WB_DATA_WIDTH ), + UVM_DEBUG) + + // pragma uvmf custom initialize begin + // This controls whether or not the agent returns a transaction handle in the driver when calling + // item_done() back into the sequencer or not. If set to 1, a transaction is sent back which means + // the sequence on the other end must use the get_response() part of the driver/sequence API. If + // this doesn't occur, there will eventually be response_queue overflow errors during the test. + return_transaction_response = 1'b0; + + // pragma uvmf custom initialize end + + endfunction + + // **************************************************************************** + // TASK: wait_for_reset + // *[Required]* Blocks until reset is released. The wait_for_reset operation is performed + // by a task in the monitor bfm. + virtual task wait_for_reset(); + monitor_bfm.wait_for_reset(); + endtask + + // **************************************************************************** + // TASK: wait_for_num_clocks + // *[Required]* Blocks until specified number of clocks have elapsed. The wait_for_num_clocks + // operation is performed by a task in the monitor bfm. + virtual task wait_for_num_clocks(int clocks); + monitor_bfm.wait_for_num_clocks(clocks); + endtask + + // **************************************************************************** + // FUNCTION : convert2string() + // This function is used to convert variables in this class into a string for log messaging. + // + virtual function string convert2string (); + // pragma uvmf custom convert2string begin + return $sformatf(""); + // pragma uvmf custom convert2string end + endfunction + + // **************************************************************************** + // FUNCTION: get_sequencer + function uvm_sequencer #(wb_s_transaction#( + .WB_ADDR_WIDTH(WB_ADDR_WIDTH), + .WB_DATA_WIDTH(WB_DATA_WIDTH) + )) get_sequencer(); + return sequencer; + endfunction + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end +`endif diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/wb_s_pkg/src/wb_s_driver.svh b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/wb_s_pkg/src/wb_s_driver.svh new file mode 100644 index 00000000..ab06adc5 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/wb_s_pkg/src/wb_s_driver.svh @@ -0,0 +1,111 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This class passes transactions between the sequencer +// and the BFM driver interface. It accesses the driver BFM +// through the bfm handle. This driver +// passes transactions to the driver BFM through the access +// task. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +`ifndef WB_S_DRIVER +`define WB_S_DRIVER +class wb_s_driver #( + int WB_ADDR_WIDTH = 32, + int WB_DATA_WIDTH = 16 + ) extends uvmf_driver_base #( + .CONFIG_T(wb_s_configuration #( + .WB_ADDR_WIDTH(WB_ADDR_WIDTH), + .WB_DATA_WIDTH(WB_DATA_WIDTH) + ) ), + .BFM_BIND_T(virtual wb_s_driver_bfm #( + .WB_ADDR_WIDTH(WB_ADDR_WIDTH), + .WB_DATA_WIDTH(WB_DATA_WIDTH) + ) ), + .REQ(wb_s_transaction #( + .WB_ADDR_WIDTH(WB_ADDR_WIDTH), + .WB_DATA_WIDTH(WB_DATA_WIDTH) + ) ), + .RSP(wb_s_transaction #( + .WB_ADDR_WIDTH(WB_ADDR_WIDTH), + .WB_DATA_WIDTH(WB_DATA_WIDTH) + ) )); + + `uvm_component_param_utils( wb_s_driver #( + WB_ADDR_WIDTH, + WB_DATA_WIDTH + )) +//******************************************************************* +// Macros that define structs located in wb_s_macros.svh +//******************************************************************* +// Initiator macro used by wb_s_driver and wb_s_driver_bfm +// to communicate initiator driven data to wb_s_driver_bfm. +`wb_s_INITIATOR_STRUCT + wb_s_initiator_s wb_s_initiator_struct; +//******************************************************************* +// Responder macro used by wb_s_driver and wb_s_driver_bfm +// to communicate Responder driven data to wb_s_driver_bfm. +`wb_s_RESPONDER_STRUCT + wb_s_responder_s wb_s_responder_struct; + +// pragma uvmf custom class_item_additional begin +// pragma uvmf custom class_item_additional end + +// **************************************************************************** +// This function is the standard SystemVerilog constructor. +// + function new( string name = "", uvm_component parent=null ); + super.new( name, parent ); + endfunction + +// **************************************************************************** +// This function sends configuration object variables to the driver BFM +// using the configuration struct. +// + virtual function void configure(input CONFIG_T cfg); + bfm.configure( cfg.to_struct() ); + endfunction + +// **************************************************************************** +// This function places a handle to this class in the proxy variable in the +// driver BFM. This allows the driver BFM to call tasks and function within this class. +// + virtual function void set_bfm_proxy_handle(); + bfm.proxy = this; endfunction + +// **************************************************************************** +// This task is called by the run_phase in uvmf_driver_base. + virtual task access( inout REQ txn ); +// pragma uvmf custom access begin + if (configuration.initiator_responder==RESPONDER) begin + // Complete current transfer and wait for next transfer + bfm.respond_and_wait_for_next_transfer( + wb_s_initiator_struct, + txn.to_responder_struct() + ); + // Unpack information about initiated transfer received by this responder + txn.from_initiator_struct(wb_s_initiator_struct); + end else begin + // Initiate a transfer and get response + bfm.initiate_and_get_response( + txn.to_initiator_struct(), + wb_s_responder_struct + ); + // Unpack transfer response information received by this initiator + txn.from_responder_struct(wb_s_responder_struct); + end +// pragma uvmf custom access end + endtask + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end +`endif diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/wb_s_pkg/src/wb_s_driver_bfm.sv b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/wb_s_pkg/src/wb_s_driver_bfm.sv new file mode 100644 index 00000000..c525182d --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/wb_s_pkg/src/wb_s_driver_bfm.sv @@ -0,0 +1,347 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: +// This interface performs the wb_s signal driving. It is +// accessed by the uvm wb_s driver through a virtual interface +// handle in the wb_s configuration. It drives the singals passed +// in through the port connection named bus of type wb_s_if. +// +// Input signals from the wb_s_if are assigned to an internal input +// signal with a _i suffix. The _i signal should be used for sampling. +// +// The input signal connections are as follows: +// bus.signal -> signal_i +// +// This bfm drives signals with a _o suffix. These signals +// are driven onto signals within wb_s_if based on INITIATOR/RESPONDER and/or +// ARBITRATION/GRANT status. +// +// The output signal connections are as follows: +// signal_o -> bus.signal +// +// +// Interface functions and tasks used by UVM components: +// +// configure: +// This function gets configuration attributes from the +// UVM driver to set any required BFM configuration +// variables such as 'initiator_responder'. +// +// initiate_and_get_response: +// This task is used to perform signaling activity for initiating +// a protocol transfer. The task initiates the transfer, using +// input data from the initiator struct. Then the task captures +// response data, placing the data into the response struct. +// The response struct is returned to the driver class. +// +// respond_and_wait_for_next_transfer: +// This task is used to complete a current transfer as a responder +// and then wait for the initiator to start the next transfer. +// The task uses data in the responder struct to drive protocol +// signals to complete the transfer. The task then waits for +// the next transfer. Once the next transfer begins, data from +// the initiator is placed into the initiator struct and sent +// to the responder sequence for processing to determine +// what data to respond with. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +import uvmf_base_pkg_hdl::*; +import wb_s_pkg_hdl::*; +`include "src/wb_s_macros.svh" + +interface wb_s_driver_bfm #( + int WB_ADDR_WIDTH = 32, + int WB_DATA_WIDTH = 16 + ) + (wb_s_if bus); + // The following pragma and additional ones in-lined further below are for running this BFM on Veloce + // pragma attribute wb_s_driver_bfm partition_interface_xif + +`ifndef XRTL +// This code is to aid in debugging parameter mismatches between the BFM and its corresponding agent. +// Enable this debug by setting UVM_VERBOSITY to UVM_DEBUG +// Setting UVM_VERBOSITY to UVM_DEBUG causes all BFM's and all agents to display their parameter settings. +// All of the messages from this feature have a UVM messaging id value of "CFG" +// The transcript or run.log can be parsed to ensure BFM parameter settings match its corresponding agents parameter settings. +import uvm_pkg::*; +`include "uvm_macros.svh" +initial begin : bfm_vs_agent_parameter_debug + `uvm_info("CFG", + $psprintf("The BFM at '%m' has the following parameters: WB_ADDR_WIDTH=%x WB_DATA_WIDTH=%x ", WB_ADDR_WIDTH,WB_DATA_WIDTH), + UVM_DEBUG) +end +`endif + + // Config value to determine if this is an initiator or a responder + uvmf_initiator_responder_t initiator_responder; + // Custom configuration variables. + // These are set using the configure function which is called during the UVM connect_phase + + logic clock_i; + logic reset_i; + + // Signal list (all signals are capable of being inputs and outputs for the sake + // of supporting both INITIATOR and RESPONDER mode operation. Expectation is that + // directionality in the config file was from the point-of-view of the INITIATOR + + // INITIATOR mode input signals + tri [WB_DATA_WIDTH-1:0] din_i; + reg [WB_DATA_WIDTH-1:0] din_o = 'b0; + tri [WB_DATA_WIDTH-1:0] TGD_I_i; + reg [WB_DATA_WIDTH-1:0] TGD_I_o = 'bz; + tri [WB_ADDR_WIDTH-1:0] adr_i; + reg [WB_ADDR_WIDTH-1:0] adr_o = 'b0; + tri cyc_i; + reg cyc_o = 0; + tri we_i; + reg we_o = 0; + tri stb_i; + reg stb_o = 0; + tri [WB_DATA_WIDTH/8-1:0] sel_i; + reg [WB_DATA_WIDTH/8-1:0] sel_o = 'b0; + + // INITIATOR mode output signals + tri [WB_DATA_WIDTH-1:0] dout_i; + reg [WB_DATA_WIDTH-1:0] dout_o = 'b0; + tri [WB_DATA_WIDTH-1:0] TGD_O_i; + reg [WB_DATA_WIDTH-1:0] TGD_O_o = 'bz; + tri ack_i; + reg ack_o = 'b0; + tri err_i; + reg err_o = 'b0; + + // Bi-directional signals + + + assign clock_i = bus.clock; + assign reset_i = bus.reset; + + // These are signals marked as 'input' by the config file, but the signals will be + // driven by this BFM if put into RESPONDER mode (flipping all signal directions around) + assign din_i = bus.din; + assign bus.din = (initiator_responder == RESPONDER) ? din_o : 'bz; + assign TGD_I_i = bus.TGD_I; + assign bus.TGD_I = (initiator_responder == RESPONDER) ? TGD_I_o : 'bz; + assign adr_i = bus.adr; + assign bus.adr = (initiator_responder == RESPONDER) ? adr_o : 'bz; + assign cyc_i = bus.cyc; + assign bus.cyc = (initiator_responder == RESPONDER) ? cyc_o : 'bz; + assign we_i = bus.we; + assign bus.we = (initiator_responder == RESPONDER) ? we_o : 'bz; + assign stb_i = bus.stb; + assign bus.stb = (initiator_responder == RESPONDER) ? stb_o : 'bz; + assign sel_i = bus.sel; + assign bus.sel = (initiator_responder == RESPONDER) ? sel_o : 'bz; + + + // These are signals marked as 'output' by the config file, but the outputs will + // not be driven by this BFM unless placed in INITIATOR mode. + assign bus.dout = (initiator_responder == INITIATOR) ? dout_o : 'bz; + assign dout_i = bus.dout; + assign bus.TGD_O = (initiator_responder == INITIATOR) ? TGD_O_o : 'bz; + assign TGD_O_i = bus.TGD_O; + assign bus.ack = (initiator_responder == INITIATOR) ? ack_o : 'bz; + assign ack_i = bus.ack; + assign bus.err = (initiator_responder == INITIATOR) ? err_o : 'bz; + assign err_i = bus.err; + + // Proxy handle to UVM driver + wb_s_pkg::wb_s_driver #( + .WB_ADDR_WIDTH(WB_ADDR_WIDTH), + .WB_DATA_WIDTH(WB_DATA_WIDTH) + ) proxy; + // pragma tbx oneway proxy.my_function_name_in_uvm_driver + + // **************************************************************************** + // **************************************************************************** + // Macros that define structs located in wb_s_macros.svh + // **************************************************************************** + // Struct for passing configuration data from wb_s_driver to this BFM + // **************************************************************************** + `wb_s_CONFIGURATION_STRUCT + // **************************************************************************** + // Structs for INITIATOR and RESPONDER data flow + //******************************************************************* + // Initiator macro used by wb_s_driver and wb_s_driver_bfm + // to communicate initiator driven data to wb_s_driver_bfm. + `wb_s_INITIATOR_STRUCT + wb_s_initiator_s initiator_struct; + // Responder macro used by wb_s_driver and wb_s_driver_bfm + // to communicate Responder driven data to wb_s_driver_bfm. + `wb_s_RESPONDER_STRUCT + wb_s_responder_s responder_struct; + + // **************************************************************************** +// pragma uvmf custom reset_condition_and_response begin + // Always block used to return signals to reset value upon assertion of reset + always @( posedge reset_i ) + begin + // RESPONDER mode output signals + din_o <= 'b0; + TGD_I_o <= 'bz; + adr_o <= 'b0; + cyc_o <= 0; + we_o <= 0; + stb_o <= 0; + sel_o <= 'b0; + // INITIATOR mode output signals + dout_o <= 'b0; + TGD_O_o <= 'bz; + ack_o <= 'b0; + err_o <= 'b0; + // Bi-directional signals + + end +// pragma uvmf custom reset_condition_and_response end + + // pragma uvmf custom interface_item_additional begin + // pragma uvmf custom interface_item_additional end + + //****************************************************************** + // The configure() function is used to pass agent configuration + // variables to the driver BFM. It is called by the driver within + // the agent at the beginning of the simulation. It may be called + // during the simulation if agent configuration variables are updated + // and the driver BFM needs to be aware of the new configuration + // variables. + // + + function void configure(wb_s_configuration_s wb_s_configuration_arg); // pragma tbx xtf + initiator_responder = wb_s_configuration_arg.initiator_responder; + // pragma uvmf custom configure begin + // pragma uvmf custom configure end + endfunction + +// pragma uvmf custom initiate_and_get_response begin +// **************************************************************************** +// UVMF_CHANGE_ME +// This task is used by an initator. The task first initiates a transfer then +// waits for the responder to complete the transfer. + task initiate_and_get_response( + // This argument passes transaction variables used by an initiator + // to perform the initial part of a protocol transfer. The values + // come from a sequence item created in a sequence. + input wb_s_initiator_s wb_s_initiator_struct, + // This argument is used to send data received from the responder + // back to the sequence item. The sequence item is returned to the sequence. + output wb_s_responder_s wb_s_responder_struct + );// pragma tbx xtf + // + // Members within the wb_s_initiator_struct: + // bit [WB_DATA_WIDTH-1:0] data ; + // Members within the wb_s_responder_struct: + // bit [WB_DATA_WIDTH-1:0] data ; + initiator_struct = wb_s_initiator_struct; + // + // Reference code; + // How to wait for signal value + // while (control_signal == 1'b1) @(posedge clock_i); + // + // How to assign a responder struct member, named xyz, from a signal. + // All available initiator input and inout signals listed. + // Initiator input signals + // wb_s_responder_struct.xyz = din_i; // [WB_DATA_WIDTH-1:0] + // wb_s_responder_struct.xyz = TGD_I_i; // [WB_DATA_WIDTH-1:0] + // wb_s_responder_struct.xyz = adr_i; // [WB_ADDR_WIDTH-1:0] + // wb_s_responder_struct.xyz = cyc_i; // + // wb_s_responder_struct.xyz = we_i; // + // wb_s_responder_struct.xyz = stb_i; // + // wb_s_responder_struct.xyz = sel_i; // [WB_DATA_WIDTH/8-1:0] + // Initiator inout signals + // How to assign a signal from an initiator struct member named xyz. + // All available initiator output and inout signals listed. + // Notice the _o. Those are storage variables that allow for procedural assignment. + // Initiator output signals + // dout_o <= wb_s_initiator_struct.xyz; // [WB_DATA_WIDTH-1:0] + // TGD_O_o <= wb_s_initiator_struct.xyz; // [WB_DATA_WIDTH-1:0] + // ack_o <= wb_s_initiator_struct.xyz; // + // err_o <= wb_s_initiator_struct.xyz; // + // Initiator inout signals + // Initiate a transfer using the data received. + @(posedge clock_i); + @(posedge clock_i); + // Wait for the responder to complete the transfer then place the responder data into + // wb_s_responder_struct. + @(posedge clock_i); + @(posedge clock_i); + responder_struct = wb_s_responder_struct; + endtask +// pragma uvmf custom initiate_and_get_response end + +// pragma uvmf custom respond_and_wait_for_next_transfer begin +// **************************************************************************** +// The first_transfer variable is used to prevent completing a transfer in the +// first call to this task. For the first call to this task, there is not +// current transfer to complete. +bit first_transfer=1; + +// UVMF_CHANGE_ME +// This task is used by a responder. The task first completes the current +// transfer in progress then waits for the initiator to start the next transfer. + task respond_and_wait_for_next_transfer( + // This argument is used to send data received from the initiator + // back to the sequence item. The sequence determines how to respond. + output wb_s_initiator_s wb_s_initiator_struct, + // This argument passes transaction variables used by a responder + // to complete a protocol transfer. The values come from a sequence item. + input wb_s_responder_s wb_s_responder_struct + );// pragma tbx xtf + // Variables within the wb_s_initiator_struct: + // bit [WB_DATA_WIDTH-1:0] data ; + // Variables within the wb_s_responder_struct: + // bit [WB_DATA_WIDTH-1:0] data ; + // Reference code; + // How to wait for signal value + // while (control_signal == 1'b1) @(posedge clock_i); + // + // How to assign a responder struct member, named xyz, from a signal. + // All available responder input and inout signals listed. + // Responder input signals + // wb_s_responder_struct.xyz = dout_i; // [WB_DATA_WIDTH-1:0] + // wb_s_responder_struct.xyz = TGD_O_i; // [WB_DATA_WIDTH-1:0] + // wb_s_responder_struct.xyz = ack_i; // + // wb_s_responder_struct.xyz = err_i; // + // Responder inout signals + // How to assign a signal, named xyz, from an initiator struct member. + // All available responder output and inout signals listed. + // Notice the _o. Those are storage variables that allow for procedural assignment. + // Responder output signals + // din_o <= wb_s_initiator_struct.xyz; // [WB_DATA_WIDTH-1:0] + // TGD_I_o <= wb_s_initiator_struct.xyz; // [WB_DATA_WIDTH-1:0] + // adr_o <= wb_s_initiator_struct.xyz; // [WB_ADDR_WIDTH-1:0] + // cyc_o <= wb_s_initiator_struct.xyz; // + // we_o <= wb_s_initiator_struct.xyz; // + // stb_o <= wb_s_initiator_struct.xyz; // + // sel_o <= wb_s_initiator_struct.xyz; // [WB_DATA_WIDTH/8-1:0] + // Responder inout signals + + @(posedge clock_i); + if (!first_transfer) begin + // Perform transfer response here. + // Reply using data recieved in the wb_s_responder_struct. + @(posedge clock_i); + // Reply using data recieved in the transaction handle. + @(posedge clock_i); + end + // Wait for next transfer then gather info from intiator about the transfer. + // Place the data into the wb_s_initiator_struct. + @(posedge clock_i); + @(posedge clock_i); + first_transfer = 0; + endtask +// pragma uvmf custom respond_and_wait_for_next_transfer end + + +endinterface + +// pragma uvmf custom external begin +// pragma uvmf custom external end +`endif diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/wb_s_pkg/src/wb_s_if.sv b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/wb_s_pkg/src/wb_s_if.sv new file mode 100644 index 00000000..1b8fc1f2 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/wb_s_pkg/src/wb_s_if.sv @@ -0,0 +1,119 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This interface contains the wb_s interface signals. +// It is instantiated once per wb_s bus. Bus Functional Models, +// BFM's named wb_s_driver_bfm, are used to drive signals on the bus. +// BFM's named wb_s_monitor_bfm are used to monitor signals on the +// bus. This interface signal bundle is passed in the port list of +// the BFM in order to give the BFM access to the signals in this +// interface. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +`ifndef WB_S_IF +`define WB_S_IF +// This template can be used to connect a DUT to these signals +// +// .dut_signal_port(wb_s_bus.din), // Agent input +// .dut_signal_port(wb_s_bus.dout), // Agent output +// .dut_signal_port(wb_s_bus.TGD_I), // Agent input +// .dut_signal_port(wb_s_bus.TGD_O), // Agent output +// .dut_signal_port(wb_s_bus.ack), // Agent output +// .dut_signal_port(wb_s_bus.adr), // Agent input +// .dut_signal_port(wb_s_bus.cyc), // Agent input +// .dut_signal_port(wb_s_bus.err), // Agent output +// .dut_signal_port(wb_s_bus.we), // Agent input +// .dut_signal_port(wb_s_bus.stb), // Agent input +// .dut_signal_port(wb_s_bus.sel), // Agent input + +import uvmf_base_pkg_hdl::*; +import wb_s_pkg_hdl::*; + +interface wb_s_if #( + int WB_ADDR_WIDTH = 32, + int WB_DATA_WIDTH = 16 + ) + + ( + input logic clock, + input logic reset, + input logic [WB_DATA_WIDTH-1:0] din, + output logic [WB_DATA_WIDTH-1:0] dout, + input logic [WB_DATA_WIDTH-1:0] TGD_I, + output logic [WB_DATA_WIDTH-1:0] TGD_O, + output logic ack, + input logic [WB_ADDR_WIDTH-1:0] adr, + input logic cyc, + output logic err, + input logic we, + input logic stb, + input logic [WB_DATA_WIDTH/8-1:0] sel + ); + +modport monitor_port + ( + input clock, + input reset, + input din, + input dout, + input TGD_I, + input TGD_O, + input ack, + input adr, + input cyc, + input err, + input we, + input stb, + input sel + ); + +modport initiator_port + ( + input clock, + input reset, + input din, + output dout, + input TGD_I, + output TGD_O, + output ack, + input adr, + input cyc, + output err, + input we, + input stb, + input sel + ); + +modport responder_port + ( + input clock, + input reset, + output din, + input dout, + output TGD_I, + input TGD_O, + input ack, + output adr, + output cyc, + input err, + output we, + output stb, + output sel + ); + + +// pragma uvmf custom interface_item_additional begin +// pragma uvmf custom interface_item_additional end + +endinterface + +// pragma uvmf custom external begin +// pragma uvmf custom external end +`endif diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/wb_s_pkg/src/wb_s_infact_coverage_strategy.csv b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/wb_s_pkg/src/wb_s_infact_coverage_strategy.csv new file mode 100644 index 00000000..1c218e14 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/wb_s_pkg/src/wb_s_infact_coverage_strategy.csv @@ -0,0 +1,6 @@ +Global +auto_bin_max, 64 + +Name,Type,Include +rand_fields,coverpoint,=rand *.** + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/wb_s_pkg/src/wb_s_macros.svh b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/wb_s_pkg/src/wb_s_macros.svh new file mode 100644 index 00000000..5758385f --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/wb_s_pkg/src/wb_s_macros.svh @@ -0,0 +1,121 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This file contains macros used with the wb_s package. +// These macros include packed struct definitions. These structs are +// used to pass data between classes, hvl, and BFM's, hdl. Use of +// structs are more efficient and simpler to modify. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// + +// **************************************************************************** +// When changing the contents of this struct, be sure to update the to_struct +// and from_struct methods defined in the macros below that are used in +// the wb_s_configuration class. +// + `define wb_s_CONFIGURATION_STRUCT \ +typedef struct packed { \ + uvmf_active_passive_t active_passive; \ + uvmf_initiator_responder_t initiator_responder; \ + } wb_s_configuration_s; + + `define wb_s_CONFIGURATION_TO_STRUCT_FUNCTION \ + virtual function wb_s_configuration_s to_struct();\ + wb_s_configuration_struct = \ + {\ + this.active_passive,\ + this.initiator_responder\ + };\ + return ( wb_s_configuration_struct );\ + endfunction + + `define wb_s_CONFIGURATION_FROM_STRUCT_FUNCTION \ + virtual function void from_struct(wb_s_configuration_s wb_s_configuration_struct);\ + {\ + this.active_passive,\ + this.initiator_responder \ + } = wb_s_configuration_struct;\ + endfunction + +// **************************************************************************** +// When changing the contents of this struct, be sure to update the to_monitor_struct +// and from_monitor_struct methods of the wb_s_transaction class. +// + `define wb_s_MONITOR_STRUCT typedef struct packed { \ + bit [WB_DATA_WIDTH-1:0] data ; \ + } wb_s_monitor_s; + + `define wb_s_TO_MONITOR_STRUCT_FUNCTION \ + virtual function wb_s_monitor_s to_monitor_struct();\ + wb_s_monitor_struct = \ + { \ + this.data \ + };\ + return ( wb_s_monitor_struct);\ + endfunction\ + + `define wb_s_FROM_MONITOR_STRUCT_FUNCTION \ + virtual function void from_monitor_struct(wb_s_monitor_s wb_s_monitor_struct);\ + {\ + this.data \ + } = wb_s_monitor_struct;\ + endfunction + +// **************************************************************************** +// When changing the contents of this struct, be sure to update the to_initiator_struct +// and from_initiator_struct methods of the wb_s_transaction class. +// Also update the comments in the driver BFM. +// + `define wb_s_INITIATOR_STRUCT typedef struct packed { \ + bit [WB_DATA_WIDTH-1:0] data ; \ + } wb_s_initiator_s; + + `define wb_s_TO_INITIATOR_STRUCT_FUNCTION \ + virtual function wb_s_initiator_s to_initiator_struct();\ + wb_s_initiator_struct = \ + {\ + this.data \ + };\ + return ( wb_s_initiator_struct);\ + endfunction + + `define wb_s_FROM_INITIATOR_STRUCT_FUNCTION \ + virtual function void from_initiator_struct(wb_s_initiator_s wb_s_initiator_struct);\ + {\ + this.data \ + } = wb_s_initiator_struct;\ + endfunction + +// **************************************************************************** +// When changing the contents of this struct, be sure to update the to_responder_struct +// and from_responder_struct methods of the wb_s_transaction class. +// Also update the comments in the driver BFM. +// + `define wb_s_RESPONDER_STRUCT typedef struct packed { \ + bit [WB_DATA_WIDTH-1:0] data ; \ + } wb_s_responder_s; + + `define wb_s_TO_RESPONDER_STRUCT_FUNCTION \ + virtual function wb_s_responder_s to_responder_struct();\ + wb_s_responder_struct = \ + {\ + this.data \ + };\ + return ( wb_s_responder_struct);\ + endfunction + + `define wb_s_FROM_RESPONDER_STRUCT_FUNCTION \ + virtual function void from_responder_struct(wb_s_responder_s wb_s_responder_struct);\ + {\ + this.data \ + } = wb_s_responder_struct;\ + endfunction +// pragma uvmf custom additional begin +// pragma uvmf custom additional end diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/wb_s_pkg/src/wb_s_monitor.svh b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/wb_s_pkg/src/wb_s_monitor.svh new file mode 100644 index 00000000..b1da8150 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/wb_s_pkg/src/wb_s_monitor.svh @@ -0,0 +1,104 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This class receives wb_s transactions observed by the +// wb_s monitor BFM and broadcasts them through the analysis port +// on the agent. It accesses the monitor BFM through the monitor +// task. This UVM component captures transactions +// for viewing in the waveform viewer if the +// enable_transaction_viewing flag is set in the configuration. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +`ifndef WB_S_MONITOR +`define WB_S_MONITOR +class wb_s_monitor #( + int WB_ADDR_WIDTH = 32, + int WB_DATA_WIDTH = 16 + ) extends uvmf_monitor_base #( + .CONFIG_T(wb_s_configuration #( + .WB_ADDR_WIDTH(WB_ADDR_WIDTH), + .WB_DATA_WIDTH(WB_DATA_WIDTH) + )), + .BFM_BIND_T(virtual wb_s_monitor_bfm #( + .WB_ADDR_WIDTH(WB_ADDR_WIDTH), + .WB_DATA_WIDTH(WB_DATA_WIDTH) + )), + .TRANS_T(wb_s_transaction #( + .WB_ADDR_WIDTH(WB_ADDR_WIDTH), + .WB_DATA_WIDTH(WB_DATA_WIDTH) + ))); + + `uvm_component_param_utils( wb_s_monitor #( + WB_ADDR_WIDTH, + WB_DATA_WIDTH + )) + +// Structure used to pass data from monitor BFM to monitor class in agent. +// Use to_monitor_struct function to pack transaction variables into structure. +// Use from_monitor_struct function to unpack transaction variables from structure. +`wb_s_MONITOR_STRUCT + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + +// **************************************************************************** +// This function is the standard SystemVerilog constructor. +// + function new( string name = "", uvm_component parent = null ); + super.new( name, parent ); + endfunction + +// **************************************************************************** +// This function sends configuration object variables to the monitor BFM +// using the configuration struct. +// + virtual function void configure(input CONFIG_T cfg); + bfm.configure( cfg.to_struct() ); + + endfunction + +// **************************************************************************** +// This function places a handle to this class in the proxy variable in the +// monitor BFM. This allows the monitor BFM to call the notify_transaction +// function within this class. +// + virtual function void set_bfm_proxy_handle(); + bfm.proxy = this; endfunction + +// *************************************************************************** + virtual task run_phase(uvm_phase phase); + // Start monitor BFM thread and don't call super.run() in order to + // override the default monitor proxy 'pull' behavior with the more + // emulation-friendly BFM 'push' approach using the notify_transaction + // function below + bfm.start_monitoring(); + endtask + +// ************************************************************************** + +// This function is called by the monitor BFM. It receives data observed by the +// monitor BFM. Data is passed using the wb_s_monitor_struct. + virtual function void notify_transaction(input wb_s_monitor_s wb_s_monitor_struct); + + + trans = new("trans"); + trans.from_monitor_struct(wb_s_monitor_struct); + trans.start_time = time_stamp; + trans.end_time = $time; + time_stamp = trans.end_time; + + analyze(trans); + endfunction + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end +`endif diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/wb_s_pkg/src/wb_s_monitor_bfm.sv b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/wb_s_pkg/src/wb_s_monitor_bfm.sv new file mode 100644 index 00000000..e2cd353c --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/wb_s_pkg/src/wb_s_monitor_bfm.sv @@ -0,0 +1,212 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This interface performs the wb_s signal monitoring. +// It is accessed by the uvm wb_s monitor through a virtual +// interface handle in the wb_s configuration. It monitors the +// signals passed in through the port connection named bus of +// type wb_s_if. +// +// Input signals from the wb_s_if are assigned to an internal input +// signal with a _i suffix. The _i signal should be used for sampling. +// +// The input signal connections are as follows: +// bus.signal -> signal_i +// +// Interface functions and tasks used by UVM components: +// monitor(inout TRANS_T txn); +// This task receives the transaction, txn, from the +// UVM monitor and then populates variables in txn +// from values observed on bus activity. This task +// blocks until an operation on the wb_s bus is complete. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +`ifndef WB_S_MONITOR_BFM +`define WB_S_MONITOR_BFM +import uvmf_base_pkg_hdl::*; +import wb_s_pkg_hdl::*; +`include "src/wb_s_macros.svh" + + +interface wb_s_monitor_bfm #( + int WB_ADDR_WIDTH = 32, + int WB_DATA_WIDTH = 16 + ) + ( wb_s_if bus ); + // The pragma below and additional ones in-lined further down are for running this BFM on Veloce + // pragma attribute wb_s_monitor_bfm partition_interface_xif + +`ifndef XRTL +// This code is to aid in debugging parameter mismatches between the BFM and its corresponding agent. +// Enable this debug by setting UVM_VERBOSITY to UVM_DEBUG +// Setting UVM_VERBOSITY to UVM_DEBUG causes all BFM's and all agents to display their parameter settings. +// All of the messages from this feature have a UVM messaging id value of "CFG" +// The transcript or run.log can be parsed to ensure BFM parameter settings match its corresponding agents parameter settings. +import uvm_pkg::*; +`include "uvm_macros.svh" +initial begin : bfm_vs_agent_parameter_debug + `uvm_info("CFG", + $psprintf("The BFM at '%m' has the following parameters: WB_ADDR_WIDTH=%x WB_DATA_WIDTH=%x ", WB_ADDR_WIDTH,WB_DATA_WIDTH), + UVM_DEBUG) +end +`endif + + + // Structure used to pass transaction data from monitor BFM to monitor class in agent. +`wb_s_MONITOR_STRUCT + wb_s_monitor_s wb_s_monitor_struct; + + // Structure used to pass configuration data from monitor class to monitor BFM. + `wb_s_CONFIGURATION_STRUCT + + + // Config value to determine if this is an initiator or a responder + uvmf_initiator_responder_t initiator_responder; + // Custom configuration variables. + // These are set using the configure function which is called during the UVM connect_phase + + logic clock_i; + logic reset_i; + tri [WB_DATA_WIDTH-1:0] din_i; + tri [WB_DATA_WIDTH-1:0] dout_i; + tri [WB_DATA_WIDTH-1:0] TGD_I_i; + tri [WB_DATA_WIDTH-1:0] TGD_O_i; + tri ack_i; + tri [WB_ADDR_WIDTH-1:0] adr_i; + tri cyc_i; + tri err_i; + tri we_i; + tri stb_i; + tri [WB_DATA_WIDTH/8-1:0] sel_i; + assign clock_i = bus.clock; + assign reset_i = bus.reset; + assign din_i = bus.din; + assign dout_i = bus.dout; + assign TGD_I_i = bus.TGD_I; + assign TGD_O_i = bus.TGD_O; + assign ack_i = bus.ack; + assign adr_i = bus.adr; + assign cyc_i = bus.cyc; + assign err_i = bus.err; + assign we_i = bus.we; + assign stb_i = bus.stb; + assign sel_i = bus.sel; + + // Proxy handle to UVM monitor + wb_s_pkg::wb_s_monitor #( + .WB_ADDR_WIDTH(WB_ADDR_WIDTH), + .WB_DATA_WIDTH(WB_DATA_WIDTH) + ) proxy; + // pragma tbx oneway proxy.notify_transaction + + // pragma uvmf custom interface_item_additional begin + // pragma uvmf custom interface_item_additional end + + //****************************************************************** + task wait_for_reset();// pragma tbx xtf + @(posedge clock_i) ; + do_wait_for_reset(); + endtask + + // **************************************************************************** + task do_wait_for_reset(); + // pragma uvmf custom reset_condition begin + wait ( reset_i === 0 ) ; + @(posedge clock_i) ; + // pragma uvmf custom reset_condition end + endtask + + //****************************************************************** + + task wait_for_num_clocks(input int unsigned count); // pragma tbx xtf + @(posedge clock_i); + + repeat (count-1) @(posedge clock_i); + endtask + + //****************************************************************** + event go; + function void start_monitoring();// pragma tbx xtf + -> go; + endfunction + + // **************************************************************************** + initial begin + @go; + forever begin + @(posedge clock_i); + do_monitor( wb_s_monitor_struct ); + + + proxy.notify_transaction( wb_s_monitor_struct ); + + end + end + + //****************************************************************** + // The configure() function is used to pass agent configuration + // variables to the monitor BFM. It is called by the monitor within + // the agent at the beginning of the simulation. It may be called + // during the simulation if agent configuration variables are updated + // and the monitor BFM needs to be aware of the new configuration + // variables. + // + function void configure(wb_s_configuration_s wb_s_configuration_arg); // pragma tbx xtf + initiator_responder = wb_s_configuration_arg.initiator_responder; + // pragma uvmf custom configure begin + // pragma uvmf custom configure end + endfunction + + + // **************************************************************************** + + task do_monitor(output wb_s_monitor_s wb_s_monitor_struct); + // + // Available struct members: + // // wb_s_monitor_struct.data + // // + // Reference code; + // How to wait for signal value + // while (control_signal === 1'b1) @(posedge clock_i); + // + // How to assign a struct member, named xyz, from a signal. + // All available input signals listed. + // wb_s_monitor_struct.xyz = din_i; // [WB_DATA_WIDTH-1:0] + // wb_s_monitor_struct.xyz = dout_i; // [WB_DATA_WIDTH-1:0] + // wb_s_monitor_struct.xyz = TGD_I_i; // [WB_DATA_WIDTH-1:0] + // wb_s_monitor_struct.xyz = TGD_O_i; // [WB_DATA_WIDTH-1:0] + // wb_s_monitor_struct.xyz = ack_i; // + // wb_s_monitor_struct.xyz = adr_i; // [WB_ADDR_WIDTH-1:0] + // wb_s_monitor_struct.xyz = cyc_i; // + // wb_s_monitor_struct.xyz = err_i; // + // wb_s_monitor_struct.xyz = we_i; // + // wb_s_monitor_struct.xyz = stb_i; // + // wb_s_monitor_struct.xyz = sel_i; // [WB_DATA_WIDTH/8-1:0] + // pragma uvmf custom do_monitor begin + // UVMF_CHANGE_ME : Implement protocol monitoring. The commented reference code + // below are examples of how to capture signal values and assign them to + // structure members. All available input signals are listed. The 'while' + // code example shows how to wait for a synchronous flow control signal. This + // task should return when a complete transfer has been observed. Once this task is + // exited with captured values, it is then called again to wait for and observe + // the next transfer. One clock cycle is consumed between calls to do_monitor. + @(posedge clock_i); + @(posedge clock_i); + @(posedge clock_i); + @(posedge clock_i); + // pragma uvmf custom do_monitor end + endtask + + +endinterface + +// pragma uvmf custom external begin +// pragma uvmf custom external end +`endif diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/wb_s_pkg/src/wb_s_random_sequence.svh b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/wb_s_pkg/src/wb_s_random_sequence.svh new file mode 100644 index 00000000..49de2027 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/wb_s_pkg/src/wb_s_random_sequence.svh @@ -0,0 +1,67 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: +// This sequences randomizes the wb_s transaction and sends it +// to the UVM driver. +// +// This sequence constructs and randomizes a wb_s_transaction. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +`ifndef WB_S_RANDOM_SEQUENCE +`define WB_S_RANDOM_SEQUENCE +class wb_s_random_sequence #( + int WB_ADDR_WIDTH = 32, + int WB_DATA_WIDTH = 16 + ) + extends wb_s_sequence_base #( + .WB_ADDR_WIDTH(WB_ADDR_WIDTH), + .WB_DATA_WIDTH(WB_DATA_WIDTH) + ); + + `uvm_object_param_utils( wb_s_random_sequence #( + WB_ADDR_WIDTH, + WB_DATA_WIDTH + )) + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + //***************************************************************** + function new(string name = ""); + super.new(name); + endfunction: new + + // **************************************************************************** + // TASK : body() + // This task is automatically executed when this sequence is started using the + // start(sequencerHandle) task. + // + task body(); + + // Construct the transaction + req=wb_s_transaction#( + .WB_ADDR_WIDTH(WB_ADDR_WIDTH), + .WB_DATA_WIDTH(WB_DATA_WIDTH) + )::type_id::create("req"); + start_item(req); + // Randomize the transaction + if(!req.randomize()) `uvm_fatal("SEQ", "wb_s_random_sequence::body()-wb_s_transaction randomization failed") + // Send the transaction to the wb_s_driver_bfm via the sequencer and wb_s_driver. + finish_item(req); + `uvm_info("SEQ", {"Response:",req.convert2string()},UVM_MEDIUM) + + endtask + +endclass: wb_s_random_sequence + +// pragma uvmf custom external begin +// pragma uvmf custom external end +`endif diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/wb_s_pkg/src/wb_s_responder_sequence.svh b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/wb_s_pkg/src/wb_s_responder_sequence.svh new file mode 100644 index 00000000..289c4234 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/wb_s_pkg/src/wb_s_responder_sequence.svh @@ -0,0 +1,63 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This class can be used to provide stimulus when an interface +// has been configured to run in a responder mode. It +// will never finish by default, always going back to the driver +// and driver BFM for the next transaction with which to respond. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +`ifndef WB_S_RESPONDER_SEQUENCE +`define WB_S_RESPONDER_SEQUENCE +class wb_s_responder_sequence #( + int WB_ADDR_WIDTH = 32, + int WB_DATA_WIDTH = 16 + ) + extends wb_s_sequence_base #( + .WB_ADDR_WIDTH(WB_ADDR_WIDTH), + .WB_DATA_WIDTH(WB_DATA_WIDTH) + ); + + `uvm_object_param_utils( wb_s_responder_sequence #( + WB_ADDR_WIDTH, + WB_DATA_WIDTH + )) + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + function new(string name = "wb_s_responder_sequence"); + super.new(name); + endfunction + + task body(); + req=wb_s_transaction#( + .WB_ADDR_WIDTH(WB_ADDR_WIDTH), + .WB_DATA_WIDTH(WB_DATA_WIDTH) + )::type_id::create("req"); + forever begin + start_item(req); + finish_item(req); + // pragma uvmf custom body begin + // UVMF_CHANGE_ME : Do something here with the resulting req item. The + // finish_item() call above will block until the req transaction is ready + // to be handled by the responder sequence. + // If this was an item that required a response, the expectation is + // that the response should be populated within this transaction now. + `uvm_info("SEQ",$sformatf("Processed txn: %s",req.convert2string()),UVM_HIGH) + // pragma uvmf custom body end + end + endtask + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end +`endif diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/wb_s_pkg/src/wb_s_sequence_base.svh b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/wb_s_pkg/src/wb_s_sequence_base.svh new file mode 100644 index 00000000..460ab86f --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/wb_s_pkg/src/wb_s_sequence_base.svh @@ -0,0 +1,116 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: +// This file contains the class used as the base class for all sequences +// for this interface. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +`ifndef WB_S_SEQUENCE_BASE +`define WB_S_SEQUENCE_BASE +class wb_s_sequence_base #( + int WB_ADDR_WIDTH = 32, + int WB_DATA_WIDTH = 16 + ) extends uvmf_sequence_base #( + .REQ(wb_s_transaction #( + .WB_ADDR_WIDTH(WB_ADDR_WIDTH), + .WB_DATA_WIDTH(WB_DATA_WIDTH) + )), + .RSP(wb_s_transaction #( + .WB_ADDR_WIDTH(WB_ADDR_WIDTH), + .WB_DATA_WIDTH(WB_DATA_WIDTH) + ))); + + `uvm_object_param_utils( wb_s_sequence_base #( + WB_ADDR_WIDTH, + WB_DATA_WIDTH + )) + + // variables + typedef wb_s_transaction #( + .WB_ADDR_WIDTH(WB_ADDR_WIDTH), + .WB_DATA_WIDTH(WB_DATA_WIDTH) + ) wb_s_transaction_req_t; + wb_s_transaction_req_t req; + typedef wb_s_transaction #( + .WB_ADDR_WIDTH(WB_ADDR_WIDTH), + .WB_DATA_WIDTH(WB_DATA_WIDTH) + ) wb_s_transaction_rsp_t; + wb_s_transaction_rsp_t rsp; + + // Event for identifying when a response was received from the sequencer + event new_rsp; + + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + // **************************************************************************** + // TASK : get_responses() + // This task recursively gets sequence item responses from the sequencer. + // + virtual task get_responses(); + fork + begin + // Block until new rsp available + get_response(rsp); + // New rsp received. Indicate to sequence using event. + ->new_rsp; + // Display the received response transaction + `uvm_info("SEQ", {"New response transaction:",rsp.convert2string()}, UVM_MEDIUM) + end + join_none + endtask + + // **************************************************************************** + // TASK : pre_body() + // This task is called automatically when start is called with call_pre_post set to 1 (default). + // By calling get_responses() within pre_body() any derived sequences are automatically + // processing response transactions. Only un-comment this call to get_responses() if you + // have configured the interface driver to utilize the response transaction path by setting + // the configuration variable "return_transaction_response" to 1. Otherwise it is possible + // to impact runtime performance and memory utilization. + // + virtual task pre_body(); + // pragma uvmf custom pre_body begin +// get_responses(); + // pragma uvmf custom pre_body end + endtask + + // **************************************************************************** + // TASK : body() + // This task is called automatically when start is called. This sequence sends + // a req sequence item to the sequencer identified as an argument in the call + // to start. + // + virtual task body(); + // pragma uvmf custom body begin + start_item(req); + finish_item(req); + // pragma uvmf custom body end + endtask + + // **************************************************************************** + // FUNCTION : new() + // This function is the standard SystemVerilog constructor. + // + function new( string name =""); + super.new( name ); + // pragma uvmf custom new begin + req = wb_s_transaction_req_t::type_id::create("req"); + rsp = wb_s_transaction_rsp_t::type_id::create("rsp"); + // pragma uvmf custom new end + endfunction + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end +`endif diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/wb_s_pkg/src/wb_s_transaction.svh b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/wb_s_pkg/src/wb_s_transaction.svh new file mode 100644 index 00000000..344f2daf --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/wb_s_pkg/src/wb_s_transaction.svh @@ -0,0 +1,196 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This class defines the variables required for an wb_s +// transaction. Class variables to be displayed in waveform transaction +// viewing are added to the transaction viewing stream in the add_to_wave +// function. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +`ifndef WB_S_TRANSACTION +`define WB_S_TRANSACTION +class wb_s_transaction #( + int WB_ADDR_WIDTH = 32, + int WB_DATA_WIDTH = 16 + ) extends uvmf_transaction_base; + + `uvm_object_param_utils( wb_s_transaction #( + WB_ADDR_WIDTH, + WB_DATA_WIDTH + )) + + rand bit [WB_DATA_WIDTH-1:0] data ; + + //Constraints for the transaction variables: + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + //******************************************************************* + //******************************************************************* + // Macros that define structs and associated functions are + // located in wb_s_macros.svh + + //******************************************************************* + // Monitor macro used by wb_s_monitor and wb_s_monitor_bfm + // This struct is defined in wb_s_macros.svh + `wb_s_MONITOR_STRUCT + wb_s_monitor_s wb_s_monitor_struct; + //******************************************************************* + // FUNCTION: to_monitor_struct() + // This function packs transaction variables into a wb_s_monitor_s + // structure. The function returns the handle to the wb_s_monitor_struct. + // This function is defined in wb_s_macros.svh + `wb_s_TO_MONITOR_STRUCT_FUNCTION + //******************************************************************* + // FUNCTION: from_monitor_struct() + // This function unpacks the struct provided as an argument into transaction + // variables of this class. + // This function is defined in wb_s_macros.svh + `wb_s_FROM_MONITOR_STRUCT_FUNCTION + + //******************************************************************* + // Initiator macro used by wb_s_driver and wb_s_driver_bfm + // to communicate initiator driven data to wb_s_driver_bfm. + // This struct is defined in wb_s_macros.svh + `wb_s_INITIATOR_STRUCT + wb_s_initiator_s wb_s_initiator_struct; + //******************************************************************* + // FUNCTION: to_initiator_struct() + // This function packs transaction variables into a wb_s_initiator_s + // structure. The function returns the handle to the wb_s_initiator_struct. + // This function is defined in wb_s_macros.svh + `wb_s_TO_INITIATOR_STRUCT_FUNCTION + //******************************************************************* + // FUNCTION: from_initiator_struct() + // This function unpacks the struct provided as an argument into transaction + // variables of this class. + // This function is defined in wb_s_macros.svh + `wb_s_FROM_INITIATOR_STRUCT_FUNCTION + + //******************************************************************* + // Responder macro used by wb_s_driver and wb_s_driver_bfm + // to communicate Responder driven data to wb_s_driver_bfm. + // This struct is defined in wb_s_macros.svh + `wb_s_RESPONDER_STRUCT + wb_s_responder_s wb_s_responder_struct; + //******************************************************************* + // FUNCTION: to_responder_struct() + // This function packs transaction variables into a wb_s_responder_s + // structure. The function returns the handle to the wb_s_responder_struct. + // This function is defined in wb_s_macros.svh + `wb_s_TO_RESPONDER_STRUCT_FUNCTION + //******************************************************************* + // FUNCTION: from_responder_struct() + // This function unpacks the struct provided as an argument into transaction + // variables of this class. + // This function is defined in wb_s_macros.svh + `wb_s_FROM_RESPONDER_STRUCT_FUNCTION + // **************************************************************************** + // FUNCTION : new() + // This function is the standard SystemVerilog constructor. + // + function new( string name = "" ); + super.new( name ); + endfunction + + // **************************************************************************** + // FUNCTION: convert2string() + // This function converts all variables in this class to a single string for + // logfile reporting. + // + virtual function string convert2string(); + // pragma uvmf custom convert2string begin + // UVMF_CHANGE_ME : Customize format if desired. + return $sformatf("data:0x%x ",data); + // pragma uvmf custom convert2string end + endfunction + + //******************************************************************* + // FUNCTION: do_print() + // This function is automatically called when the .print() function + // is called on this class. + // + virtual function void do_print(uvm_printer printer); + // pragma uvmf custom do_print begin + // UVMF_CHANGE_ME : Current contents of do_print allows for the use of UVM 1.1d, 1.2 or P1800.2. + // Update based on your own printing preference according to your preferred UVM version + $display(convert2string()); + // pragma uvmf custom do_print end + endfunction + + //******************************************************************* + // FUNCTION: do_compare() + // This function is automatically called when the .compare() function + // is called on this class. + // + virtual function bit do_compare (uvm_object rhs, uvm_comparer comparer); + wb_s_transaction #( + .WB_ADDR_WIDTH(WB_ADDR_WIDTH), + .WB_DATA_WIDTH(WB_DATA_WIDTH) + ) RHS; + if (!$cast(RHS,rhs)) return 0; + // pragma uvmf custom do_compare begin + // UVMF_CHANGE_ME : Eliminate comparison of variables not to be used for compare + return (super.do_compare(rhs,comparer) + &&(this.data == RHS.data) + ); + // pragma uvmf custom do_compare end + endfunction + + //******************************************************************* + // FUNCTION: do_copy() + // This function is automatically called when the .copy() function + // is called on this class. + // + virtual function void do_copy (uvm_object rhs); + wb_s_transaction #( + .WB_ADDR_WIDTH(WB_ADDR_WIDTH), + .WB_DATA_WIDTH(WB_DATA_WIDTH) + ) RHS; + assert($cast(RHS,rhs)); + // pragma uvmf custom do_copy begin + super.do_copy(rhs); + this.data = RHS.data; + // pragma uvmf custom do_copy end + endfunction + + // **************************************************************************** + // FUNCTION: add_to_wave() + // This function is used to display variables in this class in the waveform + // viewer. The start_time and end_time variables must be set before this + // function is called. If the start_time and end_time variables are not set + // the transaction will be hidden at 0ns on the waveform display. + // + virtual function void add_to_wave(int transaction_viewing_stream_h); + `ifdef QUESTA + if (transaction_view_h == 0) begin + transaction_view_h = $begin_transaction(transaction_viewing_stream_h,"wb_s_transaction",start_time); + end + super.add_to_wave(transaction_view_h); + // pragma uvmf custom add_to_wave begin + // UVMF_CHANGE_ME : Color can be applied to transaction entries based on content, example below + // case() + // 1 : $add_color(transaction_view_h,"red"); + // default : $add_color(transaction_view_h,"grey"); + // endcase + // UVMF_CHANGE_ME : Eliminate transaction variables not wanted in transaction viewing in the waveform viewer + $add_attribute(transaction_view_h,data,"data"); + // pragma uvmf custom add_to_wave end + $end_transaction(transaction_view_h,end_time); + $free_transaction(transaction_view_h); + `endif // QUESTA + endfunction + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end +`endif diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/wb_s_pkg/src/wb_s_transaction_coverage.svh b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/wb_s_pkg/src/wb_s_transaction_coverage.svh new file mode 100644 index 00000000..06a0e7b7 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/wb_s_pkg/src/wb_s_transaction_coverage.svh @@ -0,0 +1,82 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This class records wb_s transaction information using +// a covergroup named wb_s_transaction_cg. An instance of this +// coverage component is instantiated in the uvmf_parameterized_agent +// if the has_coverage flag is set. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +`ifndef WB_S_TRANSACTION_COVERAGE +`define WB_S_TRANSACTION_COVERAGE +class wb_s_transaction_coverage #( + int WB_ADDR_WIDTH = 32, + int WB_DATA_WIDTH = 16 + ) extends uvm_subscriber #(.T(wb_s_transaction #( + .WB_ADDR_WIDTH(WB_ADDR_WIDTH), + .WB_DATA_WIDTH(WB_DATA_WIDTH) + ))); + + `uvm_component_param_utils( wb_s_transaction_coverage #( + WB_ADDR_WIDTH, + WB_DATA_WIDTH + )) + + T coverage_trans; + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + // **************************************************************************** + covergroup wb_s_transaction_cg; + // pragma uvmf custom covergroup begin + // UVMF_CHANGE_ME : Add coverage bins, crosses, exclusions, etc. according to coverage needs. + option.auto_bin_max=1024; + option.per_instance=1; + data: coverpoint coverage_trans.data; + // pragma uvmf custom covergroup end + endgroup + + // **************************************************************************** + // FUNCTION : new() + // This function is the standard SystemVerilog constructor. + // + function new(string name="", uvm_component parent=null); + super.new(name,parent); + wb_s_transaction_cg=new; + `uvm_warning("COVERAGE_MODEL_REVIEW", "A covergroup has been constructed which may need review because of either generation or re-generation with merging. Please note that transaction variables added as a result of re-generation and merging are not automatically added to the covergroup. Remove this warning after the covergroup has been reviewed.") + endfunction + + // **************************************************************************** + // FUNCTION : build_phase() + // This function is the standard UVM build_phase. + // + function void build_phase(uvm_phase phase); + wb_s_transaction_cg.set_inst_name($sformatf("wb_s_transaction_cg_%s",get_full_name())); + endfunction + + // **************************************************************************** + // FUNCTION: write (T t) + // This function is automatically executed when a transaction arrives on the + // analysis_export. It copies values from the variables in the transaction + // to local variables used to collect functional coverage. + // + virtual function void write (T t); + `uvm_info("COV","Received transaction",UVM_HIGH); + coverage_trans = t; + wb_s_transaction_cg.sample(); + endfunction + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + +`endif diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/wb_s_pkg/src/wb_s_typedefs.svh b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/wb_s_pkg/src/wb_s_typedefs.svh new file mode 100644 index 00000000..91e77a1c --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/wb_s_pkg/src/wb_s_typedefs.svh @@ -0,0 +1,21 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: +// This file contains defines and typedefs to be compiled for use in +// the simulation running on the host server when using Veloce. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +`ifndef TYPEDEFS_HVL +`definr TYPEDEFS_HVL + +// pragma uvmf custom additional begin +// pragma uvmf custom additional end +`endif diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/wb_s_pkg/src/wb_s_typedefs_hdl.svh b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/wb_s_pkg/src/wb_s_typedefs_hdl.svh new file mode 100644 index 00000000..bd6b6f41 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/wb_s_pkg/src/wb_s_typedefs_hdl.svh @@ -0,0 +1,23 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: +// This file contains defines and typedefs to be compiled for use in +// the simulation running on the emulator when using Veloce. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// + +`ifndef TYPEDEFS_HVL +`definr TYPEDEFS_HVL + + +// pragma uvmf custom additional begin +// pragma uvmf custom additional end +`endif diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/wb_s_pkg/wb_s.compile b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/wb_s_pkg/wb_s.compile new file mode 100644 index 00000000..177c6693 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/wb_s_pkg/wb_s.compile @@ -0,0 +1,3 @@ +needs: + - wb_s_hvl.compile + - wb_s_hdl.compile diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/wb_s_pkg/wb_s_bfm.vinfo b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/wb_s_pkg/wb_s_bfm.vinfo new file mode 100644 index 00000000..712d86d9 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/wb_s_pkg/wb_s_bfm.vinfo @@ -0,0 +1,6 @@ +@use $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg_hdl.vinfo +@use wb_s_pkg_hdl.vinfo ++incdir+@vinfodir +src/wb_s_if.sv +src/wb_s_driver_bfm.sv +src/wb_s_monitor_bfm.sv diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/wb_s_pkg/wb_s_common.compile b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/wb_s_pkg/wb_s_common.compile new file mode 100644 index 00000000..cab218ee --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/wb_s_pkg/wb_s_common.compile @@ -0,0 +1,7 @@ +needs: + - $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg_hdl.compile +incdir: + - . + - ${uvm_path}/src +src: + - wb_s_pkg_hdl.sv diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/wb_s_pkg/wb_s_filelist_hdl.f b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/wb_s_pkg/wb_s_filelist_hdl.f new file mode 100644 index 00000000..569bcef6 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/wb_s_pkg/wb_s_filelist_hdl.f @@ -0,0 +1 @@ +$UVMF_VIP_LIBRARY_HOME/interface_packages/wb_s_pkg/wb_s_pkg_hdl.sv diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/wb_s_pkg/wb_s_filelist_hvl.f b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/wb_s_pkg/wb_s_filelist_hvl.f new file mode 100644 index 00000000..6c9a363f --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/wb_s_pkg/wb_s_filelist_hvl.f @@ -0,0 +1 @@ +$UVMF_VIP_LIBRARY_HOME/interface_packages/wb_s_pkg/wb_s_pkg.sv \ No newline at end of file diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/wb_s_pkg/wb_s_filelist_xrtl.f b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/wb_s_pkg/wb_s_filelist_xrtl.f new file mode 100644 index 00000000..23f4bc76 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/wb_s_pkg/wb_s_filelist_xrtl.f @@ -0,0 +1,3 @@ +$UVMF_VIP_LIBRARY_HOME/interface_packages/wb_s_pkg/src/wb_s_if.sv +$UVMF_VIP_LIBRARY_HOME/interface_packages/wb_s_pkg/src/wb_s_monitor_bfm.sv +$UVMF_VIP_LIBRARY_HOME/interface_packages/wb_s_pkg/src/wb_s_driver_bfm.sv diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/wb_s_pkg/wb_s_hdl.compile b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/wb_s_pkg/wb_s_hdl.compile new file mode 100644 index 00000000..4f4110eb --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/wb_s_pkg/wb_s_hdl.compile @@ -0,0 +1,9 @@ +needs: + - $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg_hdl.compile + - ./wb_s_common.compile +incdir: + - . +src: + - src/wb_s_if.sv + - src/wb_s_monitor_bfm.sv + - src/wb_s_driver_bfm.sv diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/wb_s_pkg/wb_s_hvl.compile b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/wb_s_pkg/wb_s_hvl.compile new file mode 100644 index 00000000..e94eaf9b --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/wb_s_pkg/wb_s_hvl.compile @@ -0,0 +1,7 @@ +needs: + - $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg.compile + - ./wb_s_common.compile +incdir: + - . +src: + - wb_s_pkg.sv diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/wb_s_pkg/wb_s_pkg.sv b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/wb_s_pkg/wb_s_pkg.sv new file mode 100644 index 00000000..fbc12fea --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/wb_s_pkg/wb_s_pkg.sv @@ -0,0 +1,79 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// PACKAGE: This file defines all of the files contained in the +// interface package that will run on the host simulator. +// +// CONTAINS: +// - +// - +// - + +// - +// - +// - + +// - +// - +// - + +// - +// - +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +`ifndef WB_S_PKG +`define WB_S_PKG +package wb_s_pkg; + + import uvm_pkg::*; + import uvmf_base_pkg_hdl::*; + import uvmf_base_pkg::*; + import wb_s_pkg_hdl::*; + + `include "uvm_macros.svh" + + // pragma uvmf custom package_imports_additional begin + // pragma uvmf custom package_imports_additional end + `include "src/wb_s_macros.svh" + + export wb_s_pkg_hdl::*; + + + + // Parameters defined as HVL parameters + + `include "src/wb_s_typedefs.svh" + `include "src/wb_s_transaction.svh" + + `include "src/wb_s_configuration.svh" + `include "src/wb_s_driver.svh" + `include "src/wb_s_monitor.svh" + + `include "src/wb_s_transaction_coverage.svh" + `include "src/wb_s_sequence_base.svh" + `include "src/wb_s_random_sequence.svh" + + `include "src/wb_s_responder_sequence.svh" + `include "src/wb_s2reg_adapter.svh" + + `include "src/wb_s_agent.svh" + + // pragma uvmf custom package_item_additional begin + // UVMF_CHANGE_ME : When adding new interface sequences to the src directory + // be sure to add the sequence file here so that it will be + // compiled as part of the interface package. Be sure to place + // the new sequence after any base sequences of the new sequence. + // pragma uvmf custom package_item_additional end + +endpackage + +// pragma uvmf custom external begin +// pragma uvmf custom external end +`endif diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/wb_s_pkg/wb_s_pkg.vinfo b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/wb_s_pkg/wb_s_pkg.vinfo new file mode 100644 index 00000000..617cce78 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/wb_s_pkg/wb_s_pkg.vinfo @@ -0,0 +1,4 @@ +@use $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg.vinfo +@use wb_s_pkg_hdl.vinfo ++incdir+@vinfodir +wb_s_pkg.sv diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/wb_s_pkg/wb_s_pkg_hdl.sv b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/wb_s_pkg/wb_s_pkg_hdl.sv new file mode 100644 index 00000000..0a2f29ab --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/wb_s_pkg/wb_s_pkg_hdl.sv @@ -0,0 +1,40 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// PACKAGE: This file defines all of the files contained in the +// interface package that needs to be compiled and synthesized +// for running on Veloce. +// +// CONTAINS: +// - +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +`ifndef WB_S_PKG_HDL +`define WB_S_PKG_HDL +package wb_s_pkg_hdl; + + import uvmf_base_pkg_hdl::*; + + // pragma uvmf custom package_imports_additional begin + // pragma uvmf custom package_imports_additional end + + // Parameters defined as HDL parameters + + `include "src/wb_s_typedefs_hdl.svh" + `include "src/wb_s_macros.svh" + + // pragma uvmf custom package_item_additional begin + // pragma uvmf custom package_item_additional end + +endpackage + +// pragma uvmf custom external begin +// pragma uvmf custom external end +`endif diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/wb_s_pkg/wb_s_pkg_hdl.vinfo b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/wb_s_pkg/wb_s_pkg_hdl.vinfo new file mode 100644 index 00000000..51a2e086 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/wb_s_pkg/wb_s_pkg_hdl.vinfo @@ -0,0 +1,2 @@ +@use $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg_hdl.vinfo +wb_s_pkg_hdl.sv diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/wb_s_pkg/wb_s_pkg_sve.F b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/wb_s_pkg/wb_s_pkg_sve.F new file mode 100644 index 00000000..75e70906 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/wb_s_pkg/wb_s_pkg_sve.F @@ -0,0 +1,10 @@ +// UVM ++incdir+${UVM_HOME}/src +${UVM_HOME}/src/uvm_pkg.sv + +// Common UVMF files +-f ${UVMF_HOME}/common/common_sve.f + ++incdir+. +-f ${UVMF_VIP_LIBRARY_HOME}/interface_packages/wb_s_pkg/wb_s_filelist_hdl.f +-f ${UVMF_VIP_LIBRARY_HOME}/interface_packages/wb_s_pkg/wb_s_filelist_hvl.f diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/wb_s_pkg/yaml/wb_s_interface.yaml b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/wb_s_pkg/yaml/wb_s_interface.yaml new file mode 100644 index 00000000..f37041fc --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/challenge_4_outpt_with_macros/verification_ip/interface_packages/wb_s_pkg/yaml/wb_s_interface.yaml @@ -0,0 +1,75 @@ +uvmf: + interfaces: + wb_s: + clock: clock + config_constraints: [] + config_vars: [] + existing_library_component: 'True' + gen_inbound_streaming_driver: 'False' + hdl_pkg_parameters: [] + hdl_typedefs: [] + hvl_pkg_parameters: [] + hvl_typedefs: [] + parameters: + - name: WB_ADDR_WIDTH + type: int + value: '32' + - name: WB_DATA_WIDTH + type: int + value: '16' + ports: + - dir: input + name: din + reset_value: '''b0' + width: WB_DATA_WIDTH + - dir: output + name: dout + reset_value: '''b0' + width: WB_DATA_WIDTH + - dir: input + name: TGD_I + reset_value: '''bz' + width: WB_DATA_WIDTH + - dir: output + name: TGD_O + reset_value: '''bz' + width: WB_DATA_WIDTH + - dir: output + name: ack + reset_value: '''b0' + width: '1' + - dir: input + name: adr + reset_value: '''b0' + width: WB_ADDR_WIDTH + - dir: input + name: cyc + reset_value: '0' + width: '1' + - dir: output + name: err + reset_value: '''b0' + width: '1' + - dir: input + name: we + reset_value: '0' + width: '1' + - dir: input + name: stb + reset_value: '0' + width: '1' + - dir: input + name: sel + reset_value: '''b0' + width: WB_DATA_WIDTH/8 + reset: reset + reset_assertion_level: 'True' + transaction_constraints: [] + transaction_vars: + - comment: '' + iscompare: 'True' + isrand: 'True' + name: data + type: bit [WB_DATA_WIDTH-1:0] + unpacked_dimension: '' + use_dpi_link: 'False' diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/system.csh b/UVM_Framework/UVMF_2022.3/challenge_3/system/system.csh new file mode 100644 index 00000000..1bcbca0e --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/system.csh @@ -0,0 +1,7 @@ +# Setting the path for making "make cli" command works fine. + +setenv UVMF_HOME /hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3/ + +# This is the command to generate you block_1_level bench + +python ../../../UVMF_2022.3/scripts/yaml2uvmf.py ../intf/apb_m_intf.yaml ../intf/axi_m_intf.yaml ../intf/axi_s_intf.yaml ../intf/spi_m_intf.yaml ../intf/spi_s_intf.yaml ../intf/wb_m_intf.yaml ../intf/wb_s_intf.yaml ../block_1/block1_env.yaml ../block_1/block1_util.yaml ../block_2/block2_env.yaml ../block_2/block2_util.yaml ../block_3/block3_env.yaml ../block_3/block3_util.yaml ../subsystem/subsystem.yaml ../subsystem/subsystem_utils.yaml ../system/system.yaml ../system/system_util.yaml diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/system.yaml b/UVM_Framework/UVMF_2022.3/challenge_3/system/system.yaml new file mode 100644 index 00000000..839c5c57 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/system.yaml @@ -0,0 +1,40 @@ +uvmf: + benches: + "system": + ## Specify the top-level block + top_env: "system" + environments: + "system": + subenvs: + - name: "s1" + type: "subsys" + - name: "b3" + type: "block_3" + + analysis_components: + - name: "sys_pred" + type: "sys_predictor" + - name: "sys_sb" + type: "sys_scoreboard" + imports: + - name: "apb_m_pkg" + - name: "axi_m_pkg" + - name: "axi_s_pkg" + - name: "block_1_env_pkg" + - name: "block_2_env_pkg" + tlm_connections: + - driver: "s1.block_1_ap1" + receiver: "sys_pred.sys_apb_ae" + - driver: "s1.block_1_ap2" + receiver: "sys_pred.sys_axi_1_ae" + - driver: "s1.block_1_ap3" + receiver: "sys_pred.sys_axi_2_ae" + - driver: "sys_pred.sys_pre_to_sco_ap" + receiver: "sys_sb.sys_sco_from_pre_ae" + - driver: "b3.axi_slave_ap" + receiver: "sys_sb.sys_axi_ae" + + config_vars : + - name: "has_scoreboard" + type : "bit" + isrand : "False" diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/system/system_util.yaml b/UVM_Framework/UVMF_2022.3/challenge_3/system/system_util.yaml new file mode 100644 index 00000000..492fafdd --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/system/system_util.yaml @@ -0,0 +1,24 @@ +uvmf: + util_components: + sys_predictor: + analysis_exports: + - name: "sys_apb_ae" + type: "apb_m_transaction" + - name: "sys_axi_1_ae" + type: "axi_m_transaction" + - name: "sys_axi_2_ae" + type: "axi_m_transaction" + + analysis_ports: + - name: "sys_pre_to_sco_ap" + type: "axi_s_transaction" + existing_library_component: 'True' + type: predictor + sys_scoreboard: + analysis_exports: + - name: "sys_axi_ae" + type: "axi_s_transaction" + - name: "sys_sco_from_pre_ae" + type: "axi_s_transaction" + type: "scoreboard" + diff --git a/UVM_Framework/UVMF_2022.3/challenge_3/yaml2uvmf.py b/UVM_Framework/UVMF_2022.3/challenge_3/yaml2uvmf.py new file mode 100755 index 00000000..286bec9b --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge_3/yaml2uvmf.py @@ -0,0 +1,1659 @@ +#! /usr/bin/env python + +############################################################################## +## Copyright 2017 Mentor Graphics +## All Rights Reserved Worldwide +## +## Licensed under the Apache License, Version 2.0 (the "License"); you may +## not use this file except in compliance with the License. You may obtain +## a copy of the License at +## +## http://www.apache.org/license/LICENSE-2.0 +## +## Unless required by applicable law or agreed to in +## writing, software distributed under the License is +## distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +## CONDITIONS OF ANY KIND, either express or implied. See +## the License for the specific language governing +## permissions and limitations under the License. +## +############################################################################## +## +## Mentor Graphics Inc +## +############################################################################## +## +## Created by : Jon Craft & Bob Oden +## Creation date : May 25 2017 +## +############################################################################## +## +## This script utilizes the Python-based generator API to take data structures +## defined in YAML and convert them into UVMF code for interfaces, environments +## and benches. +## +## Run 'yaml2uvmf.py --help' for more information +## +############################################################################## + +import sys +import os +import time +import re +import inspect +import copy +import pprint +from optparse import OptionParser, SUPPRESS_HELP +from fnmatch import fnmatch +import shutil + +# Determine addition to sys.path automatically based on script location +# This means user does not have to explicitly set PYTHONPATH in order for this +# script to work properly. + +sys.path.insert(0,os.path.dirname(os.path.dirname(os.path.realpath(__file__)))+"/templates/python"); +# Only need python2 packages if using python2 +if sys.version_info[0] < 3: + sys.path.insert(0,os.path.dirname(os.path.dirname(os.path.realpath(__file__)))+"/templates/python/python2"); + +from uvmf_yaml import * +import uvmf_gen +from uvmf_gen import (UVMFCommandLineParser,PassThroughOptionParser,UserError,InterfaceClass,EnvironmentClass,BenchClass) +from voluptuous import Invalid, MultipleInvalid +from voluptuous.humanize import humanize_error +from uvmf_version import version + +try: + import yaml +except ImportError: + print("ERROR : yaml package not found. See templates.README for more information") + print("Python version info:\n{}".format(sys.version)) + sys.exit(1) + +def merge_summary(merge,verbose=False): + block_count = sum(len(l) for l in merge.found_blocks.values()) + new_block_count = sum(len(l) for l in merge.new_blocks.values()) + if verbose: + print("============================== Merge Details ==============================") + print(" Parsed {0} original files finding a total of {1} \"pragma uvmf custom\" blocks".format(len(merge.rd), block_count)) + if verbose and (len(merge.found_blocks)>0): + for f in merge.found_blocks: + print(" File: {0}".format(f)) + for l in merge.found_blocks[f]: + print(" \"{0}\"".format(l['name'])) + print(" Copied {0} new files from generated source".format(len(merge.copied_files))) + if verbose and (len(merge.copied_files)>0): + print(" Files found in new output but not in merged source. List of copied file destinations:") + for f in merge.copied_files: + print(" {0}".format(f)) + print(" Found {0} new \"pragma uvmf custom\" blocks in generated source".format(new_block_count)) + if verbose and (len(merge.new_blocks)>0): + print(" Blocks found in new output but not in merged source. List of new blocks and their associated source file locations:") + for f in merge.new_blocks: + print(" File: {0}".format(f)) + for l in merge.new_blocks[f]: + print(" \"{0}\"".format(l)) + if verbose: + print("===========================================================================") + +class ConfigFileReader: + """Reads in a .f file and builds up array of files to parse""" + def __init__(self,fname,relative_to_file=False): + self.fname = fname + self.files = [] + try: + self.fh = open(fname,'r') + except IOError: + raise UserError("Unable to open -f/-F file "+fname) + self.lines = self.fh.readlines() + for line in self.lines: + # Strip comments + line = re.sub(r"(.*?)#.*",r"\1",line.rstrip()).strip() + # Elaborate environment variables + line = os.path.expandvars(line) + if (line != ""): + if relative_to_file: + line = os.path.normpath(os.path.dirname(os.path.abspath(fname))+os.path.sep+line) + self.files.append(line) + self.fh.close() + +class DataClass: + def __init__(self,parser,debug=False): + self.data = {'interfaces':{},'environments':{},'benches':{},'util_components':{},'qvip_environments':{},'qvip_library':{},'global':{}} + self.parser = parser + self.debug = debug + self.validators = {} + self.used_ac_items = [] + + def parseFile(self,fname): + try: + fs = open(fname) + except IOError: + raise UserError("Unable to open config file "+fname) + d = yaml.safe_load(fs) + fs.close() + try: + if 'uvmf' not in d.keys(): + raise UserError("Contents of "+fname+" not valid UVMF info") + except: + raise UserError("Contents of "+fname+" not valid UVMF info") + for k in d['uvmf'].keys(): + if k not in self.data.keys(): + raise UserError("Top-level element \""+k+"\" in "+fname+" is not valid. Allowed entries:\n "+str(self.data.keys())) + for elem in self.data.keys(): + try: self.data[elem].update(d['uvmf'][elem]) + except KeyError: + pass + + ## Validate various data structures against the associated schema + def validate(self): + self.validators = { + 'interfaces':InterfaceValidator(), + 'util_components':ComponentValidator(), + 'qvip_environments':QVIPEnvValidator(), + 'environments':EnvironmentValidator(), + 'benches':BenchValidator(), + 'global':GlobalValidator(), +# 'qvip_library':QVIPLibValidator(), ## Don't validate QVIP library info, for debug purposes only + } + ## Check for any incorrect top-level keys + for t in self.validators.keys(): + for c in self.data[t].keys(): + if (t=='global'): + v = self.data[t] + else: + v = self.data[t][c] + try: + self.validators[t].schema(v) + except MultipleInvalid as e: + resp = humanize_error(v,e).split('\n') + raise UserError("While validating "+t+" YAML '"+c+"':\n"+pprint.pformat(resp,indent=2)) + + def calculateRelativeVipLocation(self,compClass): + ## Determine relative path to "loc" if CWD is bench's "sim" directory + simpath = compClass.bench_location+"/bench_name/sim" + ret = os.path.relpath(compClass.vip_location,simpath) + ## Even on Windows, these need to be forward slashes because they'll be normalized within Tcl. Replace any backslashes with forward ones + ## Can't use pathlib here due to Python2 back-compat, just do a global search/replace + return ret.replace('\\','/') + + def calculateRelativeVipToCwd(self,compClass): + ret = os.path.relpath(os.getcwd(),compClass.vip_location) + return ret.replace('\\','/') + + def calculateRelativeBenchToCwd(self,compClass): + ret = os.path.relpath(os.getcwd(),compClass.bench_location) + return ret.replace('\\','/') + + def calculateRelativeInterfaceToCwd(self,compClass): + ret = os.path.relpath(os.getcwd(),compClass.vip_location+os.path.sep+compClass.interface_location) + return ret.replace('\\','/') + + def calculateRelativeEnvironmentToCwd(self,compClass): + ret = os.path.relpath(os.getcwd(),compClass.vip_location+os.path.sep+compClass.environment_location) + return ret.replace('\\','/') + + def setupGlobalVars(self,compClass): + try: + compClass.header = self.data['global']['header'] + except KeyError: + compClass.header = None + pass + try: + compClass.flat_output = (self.data['global']['flat_output'] == "True") + except KeyError: + compClass.flat_output = False + pass + try: + compClass.vip_location = self.data['global']['vip_location'] + except KeyError: + pass + try: + compClass.interface_location = self.data['global']['interface_location'] + except KeyError: + pass + try: + compClass.environment_location = self.data['global']['environment_location'] + except KeyError: + pass + try: + compClass.bench_location = self.data['global']['bench_location'] + except KeyError: + pass + compClass.relative_vip_from_sim = self.calculateRelativeVipLocation(compClass) + compClass.relative_vip_from_cwd = self.calculateRelativeVipToCwd(compClass) + compClass.relative_bench_from_cwd = self.calculateRelativeBenchToCwd(compClass) + compClass.relative_interface_from_cwd = self.calculateRelativeInterfaceToCwd(compClass) + compClass.relative_environment_from_cwd = self.calculateRelativeEnvironmentToCwd(compClass) + return compClass + + ## Generate everything from the data structures + def buildElements(self,genarray,verify=True,build_existing=False,archive_yaml=True): + count = 0 + self.interfaceDict = {} + try: + arrlen = len(genarray) + except TypeError: + arrlen = 0 + pass + for interface_name in self.data['interfaces']: + if ((arrlen>0) and (interface_name in genarray)) or (arrlen==0): + self.interfaceDict[interface_name] = self.generateInterface(interface_name,build_existing,archive_yaml) + count = count + 1 + self.environmentDict = {} + for environment_name in self.data['environments']: + if ((arrlen>0) and (environment_name in genarray)) or (arrlen==0): + self.environmentDict[environment_name] = self.generateEnvironment(environment_name,build_existing,archive_yaml) + count = count + 1 + self.benchDict = {} + for bench_name in self.data['benches']: + if ((arrlen>0) and (bench_name in genarray)) or (arrlen==0): + self.benchDict[bench_name] = self.generateBench(bench_name,build_existing,archive_yaml) + count = count + 1 + ## Check to see if any utility components were defined but never instantiated, flag that as a warning + for util_comp in self.data['util_components']: + if util_comp not in self.used_ac_items: + print(" WARNING : Utility component \""+util_comp+"\" was defined but never used. It will not be generated.") + ## Verify that something was produced (possible that YAML input was empty or genarray had no matches) + if count==0 and verify: + raise UserError("No output was produced!") + + + def recursion_print(self,recurse_list): + r = "" + for i,s in enumerate(recurse_list): + r = r + s + if i != len(recurse_list)-1: + r = r + " -> " + return r + + ## This method recursively searches all environments from the specified level down for QVIP subenvs, compiling + ## a list of underlying QVIP agents, their subenvironment parent names, their import list and active/passive info + def getQVIPAgents(self,topEnv,recurse_list=[]): + struct = self.data['environments'] + # Check for recursion, error out if detected + if topEnv in recurse_list: + raise UserError("Sub-environment recursion detected within environment \""+topEnv+"\". Tree: \""+self.recursion_print(recurse_list+[topEnv])+"\"") + try: + env = struct[topEnv] + except KeyError: + raise UserError("Unable to find environment \""+topEnv+"\" in defined environments (available list is "+str(struct.keys())) + agent_list = [] + import_list = [] + ## First look for any local QVIP subenvironments and extract those agent names + try: + qvip_subenv_list = env['qvip_subenvs'] + except KeyError: + qvip_subenv_list = [] + pass + for s in qvip_subenv_list: + try: + d = self.data['qvip_environments'][s['type']] + except KeyError: + raise UserError("Definition for QVIP subenvironment \""+s['name']+"\" of type \""+s['type']+"\" is not found") + local_agents = d['agents'] + for a in local_agents: + try: + active_passive = a['active_passive'] + except KeyError: + active_passive = None + agent_list = agent_list + [{ 'name': a['name'], 'parent': s['type'], 'active_passive': active_passive }] + try: + import_list = import_list + a['imports'] + except KeyError: pass + ## Next drill down and call getQVIPAgents on any non-QVIP subenvironments + try: + subenv_list = env['subenvs'] + except KeyError: + subenv_list = [] + pass + for s in subenv_list: + qstruct = self.getQVIPAgents(s['type'],recurse_list+[topEnv]) + agent_list = agent_list + qstruct['alist']; + import_list = import_list + qstruct['ilist']; + ## Finally, uniquify the import list + ilist = import_list + import_list = [] + for i in ilist: + if i not in import_list: + import_list = import_list + [ i ] + return {'alist':agent_list, 'ilist':import_list} + + ## This method will return a list of environments at the provided environment level or recursively. + def getEnvironments(self,topEnv,recursive=True): + struct = self.data['environments'] + try: + env = struct[topEnv] + except KeyError: + raise UserError("Unable to find environment \""+topEnv+"\" in defined environments (available list is "+str(struct.keys())) + envs = [] + try: + envs = env['subenvs'] + except KeyError: pass + if not recursive: + return envs + for subenv in envs: + envs = envs + self.getEnvironments(subenv['type'],recursive=True) + return envs + + ## This method takes a dotted component hierarchy string and returns + ## the same but with underscores. For use in cases where a unique identifier + ## is required. Removes final entry in component hierarchy too. + def getUniqueID(self,val): + l = val.split(".") + return "uvm_test_top."+'.'.join(l[:-1])+"." + + ## This method returns an ordered list of information on ALL BFMs from a given top-level environment, down. + ## The list entries all have the following structure: + ## - BFM Name ('bfm_name') + ## - BFM Type ('bfm_type') + ## - BFM Parent Type ('parent_type') + ## - Environment Path ('env_path') + ## - VIP Library Env Variable Name ('lib_env_var_name') (only valid for non-QVIP) + ## - QVIP/Non-QVIP flag ('is_qvip') + ## - Initiator/Responder info ('initiator_responder') + ## - VeloceReady flag ('veloce_ready') + def getAllAgents(self,env_type,env_inst,isQVIP,envPath): + alist = [] + if (isQVIP==1): + # This environment we've been given is a QVIP environment which is stored + # in a different structure + struct = self.data['qvip_environments'] + try: + env = struct[env_type] + except KeyError: + raise UserError("Unable to find QVIP environment \""+env_type+"\" in defined QVIP environments (available list is "+str(struct.keys())+")") + for a in env['agents']: + ## All we have is the name of each BFM. + alist = alist + [{ 'bfm_name': a['name'], + 'bfm_type': 'unknown', + 'parent_type': env_type, + 'env_path': envPath+"."+a['name'], + 'lib_env_var_name':'unknown', + 'is_qvip': 1 , + 'initiator_responder':'UNKNOWN', + 'veloce_ready':False }] + ## No nesting with QVIP environments so safe to just return here + return alist + else: + struct = self.data['environments'] + try: + env = struct[env_type] + except KeyError: + raise UserError("Unable to find environment \""+env_type+"\" in defined environments (available list is "+str(struct.keys())) + ## We're looking at a non-QVIP environment. This can have underlying QVIP and/or non-QVIP sub-environments as well as local agents. + ## Look for underlying QVIP subenvs first, then non-QVIP sub-envs, then local agents. + try: + qvip_subenvs = env['qvip_subenvs'] + for e in qvip_subenvs: + alist = alist + self.getAllAgents(e['type'],e['name'],1,envPath+"."+e['name']) + except KeyError: pass + try: + subenvs = env['subenvs'] + for e in subenvs: + alist = alist + self.getAllAgents(e['type'],e['name'],0,envPath+"."+e['name']) + except KeyError: pass + try: + agents = env['agents'] + for a in agents: + try: + env_var_name = self.data['interfaces'][a['type']]['vip_lib_env_variable'] + except KeyError: + env_var_name = 'UVMF_VIP_LIBRARY_HOME' + pass + try: + init_resp = a['initiator_responder'] + except KeyError: + init_resp = 'INITIATOR' + pass + try: + veloce_ready = (self.data['interfaces'][a['type']]['veloce_ready']=="True") + except KeyError: + veloce_ready = True + pass + infact_ready = ('infact_ready' in self.data['interfaces'][a['type']].keys() and self.data['interfaces'][a['type']]['infact_ready']) + + alist = alist + [{ 'bfm_name': a['name'], + 'bfm_type': a['type'], + 'parent_type': env_type, + 'env_path': envPath+"."+a['name'], + 'lib_env_var_name':env_var_name, + 'is_qvip': 0, + 'initiator_responder':init_resp , + 'veloce_ready':veloce_ready, + 'infact_ready':infact_ready }] + except KeyError: pass + return alist + + ## This method returns an ordered list of information on ALL BFMs from a given top-level environment, down. + ## The list entries all have the following structure: + ## - BFM Name ('bfm_name') + ## - BFM Type ('bfm_type') + ## - BFM Parent Type ('parent_type') + ## - Environment Path ('env_path') + ## - VIP Library Env Variable Name ('lib_env_var_name') (only valid for non-QVIP) + ## - QVIP/Non-QVIP flag ('is_qvip') + ## - Initiator/Responder info ('initiator_responder') + ## - VeloceReady flag ('veloce_ready') + def getAllScoreboards(self,env_type,env_inst,envPath): + sblist = [] + struct = self.data['environments'] + try: + env = struct[env_type] + except KeyError: + raise UserError("Unable to find environment \""+env_type+"\" in defined environments (available list is "+str(struct.keys())) + try: + subenvs = env['subenvs'] + for e in subenvs: + sblist = sblist + self.getAllScoreboards(e['type'],e['name'],envPath+"."+e['name']) + except KeyError: pass + try: + sbs = env['scoreboards'] + for sb in sbs: + sblist = sblist + [envPath+"."+sb['name']] + except KeyError: pass + return sblist + + ## This method can be employed to return either a list of (non-QVIP) agents at the provided environment + ## level or recursively, searching through all sub-environments and down. + def getAgents(self,topEnv,recursive=True,givePath=False,parentPath=[]): + struct = self.data['environments'] + try: + env = struct[topEnv] + except KeyError: + raise UserError("Unable to find environment \""+topEnv+"\" in defined environments (available list is "+str(struct.keys())) + agents = [] + try: + agents = env['agents'] + except: + agents = [] + pass + if not givePath: + structure = agents + else: + structure = [] + for agent in agents: + try: + vip_lib_env_variable = self.data['interfaces'][agent['type']]['vip_lib_env_variable'] + except KeyError: + vip_lib_env_variable = "UVMF_VIP_LIBRARY_HOME" + structure = structure + [{ 'envpath' : parentPath, 'agent' : agent, 'vip_lib_env_variable' : vip_lib_env_variable }] + if not recursive: + return structure + try: + subEnvs = env['subenvs'] + for subEnv in subEnvs: + structure = structure + self.getAgents(subEnv['type'],recursive=True,givePath=givePath,parentPath=parentPath+[subEnv['name']]) + except KeyError: pass + return structure + + def dataExtract(self,keys,dictionary): + ## Pull the specified keys out of the given structure. If the key + ## does not exist return None for the given value + ret = [] + for key in keys: + try: + ret = ret + [dictionary[key]] + except KeyError: + ret = ret + [None] + pass + return ret + + def generateEnvironment(self,name,build_existing=False,archive_yaml=True): + env = EnvironmentClass(name) + struct = self.data['environments'][name] + qvip_agents_dot = [] + qvip_agents_und = [] + valid_ap_list = [] + valid_ae_list = [] + valid_qsubenv_list = [] + env_has_extdef_items = False + env = self.setupGlobalVars(env) + ## Extract any environment-level parameters and add them + try: + for param in struct['parameters']: + pname,ptype,pval = self.dataExtract(['name','type','value'],param) + env.addParamDef(pname,ptype,pval) + except KeyError: pass + try: + for param in struct['hvl_pkg_parameters']: + pname,ptype,pval = self.dataExtract(['name','type','value'],param) + env.addHvlPkgParamDef(pname,ptype,pval) + except KeyError: pass + ## Extract any configuration variable settings and add them + try: + for cv_val in struct['config_variable_values']: + cvvname,cvvval = self.dataExtract(['name','value'],cv_val) + env.addConfigVariableValue(cvvname,cvvval) + except KeyError: pass + ## Drill down into any QVIP subenvironments for import information, that'll be needed here + qstruct = self.getQVIPAgents(name) + ilist = qstruct['ilist'] + for i in ilist: + env.addImport(i) + ## Call out any locally defined imports + try: + for imp in struct['imports']: + env.addImport(imp['name']) + except KeyError: pass + ## If imp-decl macros are needed, add them + try: + for impdecl in struct ['imp_decls']: + env.addImpDecl(impdecl['name']) + except KeyError: pass + try: + for nonUvmfComps in struct ['non_uvmf_components']: + cname,ctype = self.dataExtract(['name', 'type'],nonUvmfComps) + try: + cextdef = ( nonUvmfComps['extdef'] == 'True' ) + env_has_extdef_items = True + except KeyError: + pass + try: + cparams_array = nonUvmfComps['parameters'] + except KeyError: + cparams_array = {} + pass + cparams = {} + for item in cparams_array: + n,v = self.dataExtract(['name','value'],item) + cparams[n] = v + env.addNonUvmfComponent(cname,ctype,cparams) + except KeyError: pass + try: + for qvipMemAgents in struct ['qvip_memory_agents']: + qmaname,qmatype,qmaqenv = self.dataExtract(['name', 'type','qvip_environment'],qvipMemAgents) + try: + qmaparams_array = qvipMemAgents['parameters'] + except KeyError: + qmaparams_array = {} + pass + qmaparams = {} + for item in qmaparams_array: + n,v = self.dataExtract(['name','value'],item) + qmaparams[n] = v + env.addQvipMemoryAgent(qmaname,qmatype,qmaqenv,qmaparams) + except KeyError: pass + ## The order of the following loops is important. The order in which local agents, sub-environments and QVIP + ## sub-environments are added must match the order in which they will be added at the bench level, otherwise + ## things will be configured out-of-order. + ## The order is as follows: + ## QVIP subenvs + ## Custom sub-environments + ## Locally defined custom interfaces + ## Look for defined QVIP sub-environments and add those + try: + for subenv in struct['qvip_subenvs']: + n,t = self.dataExtract(['name','type'],subenv) + try: + qvipStruct = self.data['qvip_environments'][t] + except KeyError: + raise UserError("QVIP environment \""+t+"\" in environment \""+name+"\" is not defined") + alist = [] + for a in qvipStruct['agents']: + alist = alist + [a['name']] + qvip_agents_dot = qvip_agents_dot + [n+"."+a['name']] + qvip_agents_und = qvip_agents_und + [n+"_"+a['name']] + valid_qsubenv_list = valid_qsubenv_list + [n] + env.addQvipSubEnv(name=n,envPkg=t,agentList=alist) + except KeyError: pass + ## Look for defined sub-environments and add them + try: + for subenv in struct['subenvs']: + ename,etype = self.dataExtract(['name','type'],subenv) + try: + subextdef = ( subenv['extdef'] == 'True' ) + env_has_extdef_items = True + except KeyError: + pass + try: + eparams_array = subenv['parameters'] + except KeyError: + eparams_array = {} + pass + eparams = {} + num = 0 + for item in eparams_array: + n,v = self.dataExtract(['name','value'],item) + eparams[n] = v + num += 1 + ## Determine how many agents are defined in the subenvironment as that is a required argument going into + ## this API call. This is a recursive count of agents. + agents = self.getAgents(etype,recursive=True) + ## Also find any underlying QVIP agents underneath this subenvironment (nested underneath underlying QVIP subenvs) + qvip_agents_struct = self.getQVIPAgents(etype); + qvip_agents = qvip_agents_struct['alist'] + if agents==None: + raise UserError("Sub-environment type \""+etype+"\" used in environment \""+name+"\" is not found") + self.check_parameters('environment',name,'subenv',ename,etype,eparams_array,self.data['environments'][etype]) + ## Check if subenv has a register model defined unless asked explicitly to avoid it + try: + v = subenv['use_register_model']=='True' + except KeyError: + v = True + pass + if v: + try: + rm = self.data['environments'][etype]['register_model'] + except KeyError: + rm = None + pass + else: + rm = None + if not rm: + rm_pkg = None + rm_block_class = None + else: + try: + rm_pkg = rm['reg_model_package'] + except KeyError: + rm_pkg = etype+"_reg_pkg" + pass + try: + rm_block_class = rm['reg_block_class'] + except KeyError: + rm_block_class = etype+"_reg_model" + pass + env.addSubEnv(ename,etype,len(agents)+len(qvip_agents),eparams,rm_pkg,rm_block_class) + env_def = self.data['environments'][etype] + try: + env_ap_list = env_def['analysis_ports'] + for env_ap in env_ap_list: + valid_ap_list = valid_ap_list + [ename+"."+env_ap['name']] + except KeyError: pass + try: + env_ae_list = env_def['analysis_exports'] + for env_ae in env_ae_list: + valid_ae_list = valid_ae_list + [ename+"."+env_ae['name']] + except KeyError: pass + except KeyError: pass + ## Locally defined agent instantiations + try: + for agent in self.getAgents(name,recursive=False): + aname,atype = self.dataExtract(['name','type'],agent) + try: + aextdef = ( agent['extdef'] == 'True' ) + env_has_extdef_items = True + except KeyError: + pass + try: + aparams_list = agent['parameters'] + except KeyError: + aparams_list = [] + pass + aparams = {} + for item in aparams_list: + n,v = self.dataExtract(['name','value'],item) + aparams[n] = v; + try: + intf = self.data['interfaces'][atype] + except KeyError: + raise UserError("Agent type \""+atype+"\" in environment \""+name+"\" is not recognized") + try: + initResp = agent['initiator_responder'] + except KeyError: + initResp = 'INITIATOR' + pass + self.check_parameters('environment',name,'agent',agent['name'],atype,aparams_list,self.data['interfaces'][atype]) + env.addAgent(agent['name'],atype,intf['clock'],intf['reset'],aparams,initResp) + valid_ap_list = valid_ap_list + [agent['name']+".monitored_ap"] + except KeyError: pass + defined_ac_items = [] + try: + ac_items = struct['analysis_components'] + except KeyError: + ac_items = [] + pass + for ac_item in ac_items: + ac_type,ac_name = self.dataExtract(['type','name'],ac_item) + try: + ac_params = ac_item['parameters'] + except KeyError: + ac_params = [] + pass + ## Don't go through the trouble of poking at the definition of the analysis component if it was already + ## used before. Just instantiate it + try: + extdef = (ac_item['extdef'] == 'True') + env_has_extdef_items = True + except KeyError: + extdef = False + pass + if (ac_type not in defined_ac_items) and (not extdef): + try: + definition = self.data['util_components'][ac_type] + except KeyError: + raise UserError("No definition found for component \""+ac_name+"\" of type \""+ac_type) + ac_type_type = definition['type'] + exports = {} + try: + for item in definition['analysis_exports']: + exports[item['name']] = item['type'] + except KeyError: pass + ports = {} + try: + for item in definition['analysis_ports']: + ports[item['name']] = item['type'] + except KeyError: pass + qvip_exports = {} + try: + for item in definition['qvip_analysis_exports']: + qvip_exports[item['name']] = item['type'] + except KeyError: pass + try: + parameters = definition['parameters'] + except KeyError: + parameters = [] + pass + try: + ac_mtlb_ready = definition['mtlb_ready']==True + except KeyError: + ac_mtlb_ready = False + env.defineAnalysisComponent(ac_type_type,ac_type,exports,ports,qvip_exports,parameters,mtlbReady=ac_mtlb_ready) + defined_ac_items = defined_ac_items + [ac_type] + if ac_type not in self.used_ac_items: + self.used_ac_items = self.used_ac_items + [ac_type] + if not extdef: + self.check_parameters('environment',name,ac_type_type,ac_name,ac_type,ac_params,self.data['util_components'][ac_type]) + env.addAnalysisComponent(ac_name,ac_type,ac_params,extdef) + try: ports + except NameError: ports = None + if ports is not None: + for ap in ports: + valid_ap_list = valid_ap_list + [ac_name+"."+ap] + try: exports + except NameError: exports = None + if exports is not None: + for ae in exports: + valid_ae_list = valid_ae_list + [ac_name+"."+ae] + try: qvip_exports + except NameError: qvip_exports = None + if qvip_exports is not None: + for qae in qvip_exports: + valid_ae_list = valid_ae_list + [ac_name+"."+qae] + try: + sb_items = struct['scoreboards'] + except KeyError: + sb_items = [] + pass + for sb_item in sb_items: + sb_name,sb_type,trans_type = self.dataExtract(['name','sb_type','trans_type'],sb_item) + try: + sb_params_list = sb_item['parameters'] + except KeyError: + sb_params_list = [] + pass + sb_params = {} + for item in sb_params_list: + n,v = self.dataExtract(['name','value'],item) + sb_params[n] = v + env.addUvmfScoreboard(sb_name,sb_type,trans_type,sb_params) + valid_ae_list = valid_ae_list + [sb_name+".expected_analysis_export"] + valid_ae_list = valid_ae_list + [sb_name+".actual_analysis_export"] + try: + for item in struct['analysis_ports']: + n,t,c = self.dataExtract(['name','trans_type','connected_to'],item) + if c not in valid_ap_list: + mess = "TLM connected_to entry \""+c+"\" listed in analysis_ports for environment \""+name+"\" not a valid TLM driver name. \nValid names:" + for ap in valid_ap_list: + mess = mess+"\n "+ap + if env_has_extdef_items: + mess = mess+"\nPort may be on externally defined component - Skipping check on this connnection." + print(mess) + else: + raise UserError(mess) + env.addAnalysisPort(n,t,c) + except KeyError: pass + try: + for item in struct['analysis_exports']: + n,t,c = self.dataExtract(['name','trans_type','connected_to'],item) + if c not in valid_ae_list: + mess = "TLM connected_to entry \""+c+"\" listed in analysis_exports for environment \""+name+"\" not a valid TLM receiver name. \nValid names:" + for ae in valid_ae_list: + mess = mess+"\n "+ae + if env_has_extdef_items: + mess = mess+"\nPort may be on externally defined component - Skipping check on this connnection." + print(mess) + else: + raise UserError(mess) + env.addAnalysisExport(n,t,c) + except KeyError: pass + try: + for item in struct['qvip_connections']: + d,r,k,v = self.dataExtract(['driver','receiver','ap_key','validate'],item) + rlist = r.split(".") + ## Allow the driver (QVIP) to contain regular "." hierarchy for clarity. Convert any found + ## to underscores in order to adhere to the API + dm = re.sub(r'\.','_',d) + if not v: + v = 'True' + if v == 'True': + if dm not in qvip_agents_und: + mess = "QVIP TLM Driver name entry \""+d+"\" listed in qvip_connections for environment \""+name+"\" not a valid QVIP agent name. \nValid names:" + for b in qvip_agents_dot: + mess = mess+"\n "+b + mess = mess+"\nNote: Underscores are valid substitutions within YAML for dot delimeters in this list of valid names.\n" + if env_has_extdef_items: + mess = mess+"\nPort may be on externally defined component - Skipping check on this connnection." + print(mess) + else: + raise UserError(mess) + if r not in valid_ae_list: + mess = "QVIP TLM Receiver name entry \""+r+"\" listed in qvip_connections for environment \""+name+"\" not a valid QVIP TLM receiver name. \nValid names:" + for ae in valid_ae_list: + mess = mess+"\n "+ae + if env_has_extdef_items: + mess = mess+"\nPort may be on externally defined component - Skipping check on this connnection." + print(mess) + else: + raise UserError(mess) + env.addQvipConnection(dm,k,'.'.join(rlist[:-1]),rlist[-1],v) + except KeyError: pass + try: + for conn in struct['tlm_connections']: + d,r,v = self.dataExtract(['driver','receiver', 'validate'],conn) + dlist = d.split(".") + rlist = r.split(".") + ## The driver and receiver entries provided need to be split to work with the API in uvmf_gen + if not v: + v = 'True' + if v == 'True': + if d not in valid_ap_list: + mess = "TLM Driver name entry \""+d+"\" listed in tlm_connections for environment \""+name+"\" not a valid TLM driver name. \nValid names:" + for ap in valid_ap_list: + mess = mess+"\n "+ap + if dlist[0] not in valid_qsubenv_list: + if env_has_extdef_items: + mess = mess+"\nPort may be on externally defined component - Skipping check on this connnection." + print(mess) + else: + raise UserError(mess) + if r not in valid_ae_list: + mess = "TLM Receiver name entry \""+r+"\" listed in tlm_connections for environment \""+name+"\" not a valid TLM receiver name. \nValid names:" + for ae in valid_ae_list: + mess = mess+"\n "+ae + if env_has_extdef_items: + mess = mess+"\nPort may be on externally defined component - Skipping check on this connnection." + print(mess) + else: + raise UserError(mess) + env.addConnection('.'.join(dlist[:-1]),dlist[-1],'.'.join(rlist[:-1]),rlist[-1],v) + except KeyError: pass + try: + for cfg_item in struct['config_vars']: + n,t,c = self.dataExtract(['name','type','comment'],cfg_item) + if not c: + c = "" + try: + crand = (cfg_item['isrand']=="True") + except KeyError: + crand = False + pass + cval = '' + try: + cval = cfg_item['value'] + except KeyError: pass + try: + cvud = cfg_item['unpacked_dimension'] + except KeyError: + cvud = "" + pass + env.addConfigVar(n,t,crand,cval,c,cvud) + except KeyError: pass + try: + for item in struct['config_constraints']: + n,v,c = self.dataExtract(['name','value','comment'],item) + if not c: + c = "" + env.addConfigVarConstraint(n,v,c) + except KeyError: pass + try: + regInfo = struct['register_model'] + except KeyError: + regInfo = None + pass + if regInfo != None: + try: + reg_model_pkg = regInfo['reg_model_package'] + except KeyError: + reg_model_pkg = name+"_reg_pkg" + pass + try: + reg_blk_class = regInfo['reg_block_class'] + except KeyError: + reg_blk_class = name+"_reg_model" + pass + try: + maps = regInfo['maps'] + except KeyError: + maps = None + pass + if maps==None: + use_adapter = False + use_explicit_prediction = False + sequencer = None + trans = None + adapter = None + mapName = None + qvip_agent = False + else: + try: + use_adapter = regInfo['use_adapter'] == "True" + except KeyError: + use_adapter = True + try: + use_explicit_prediction = regInfo['use_explicit_prediction'] == "True" + except KeyError: + use_explicit_prediction = True + maps = regInfo['maps'] + ## Currently only support a single map - this will change in the future, hopefully + if len(maps) != 1: + raise UserError("Register model in environment \""+name+"\" can only have one map defined") + ## Extract information regarding the interface we should be attaching to. + ## First, confirm that the name of the agent is a valid instance. This will return a list + ## of structures, each with an 'name' key and 'type' key. The interface we're attaching to + ## must match up with the 'name' key in this list somewhere + try: + qvip_agent = maps[0]['qvip_agent'] + except KeyError: + qvip_agent = "False" + pass + if qvip_agent == "False": + agent_list = self.getAgents(name,recursive=True) + agent_type = "" + for a in agent_list: + if a['name'] == maps[0]['interface']: + ## Testing for a defined type might be thought to be needed here but if it wasn't a + ## valid agent type the above check would never pass + agent_type = a['type'] + try: + agent_params = self.parameterSyntax(a['parameters']) + except KeyError: + agent_params = "" + pass + break + if agent_type == "": + raise UserError("For register map \""+maps[0]['name']+"\" in environment \""+name+"\" no interface \""+maps[0]['interface']+"\" was found") + sequencer = maps[0]['interface'] + trans = agent_type+"_transaction"+agent_params + adapter = agent_type+"2reg_adapter"+agent_params + mapName = maps[0]['name'] + else: + sequencer = maps[0]['interface'] + trans = "uvm_sequence_item" + adapter = "uvm_reg_adapter" + mapName = maps[0]['name'] + env.addRegisterModel( + sequencer=sequencer, + transactionType=trans, + adapterType=adapter, + busMap=mapName, + useAdapter=use_adapter, + useExplicitPrediction=use_explicit_prediction, + qvipAgent=qvip_agent, + regModelPkg=reg_model_pkg, + regBlockClass=reg_blk_class) + try: + dpi_def = struct['dpi_define'] + ca = "" + la = "" + try: + ca = dpi_def['comp_args'] + except KeyError: pass + try: + la = dpi_def['link_args'] + except KeyError: pass + env.setDPISOName(value=dpi_def['name'],compArgs=ca,linkArgs=la) + for f in dpi_def['files']: + env.addDPIFile(f) + try: + for imp in dpi_def['imports']: + sv_args = [] + try: + sv_args = imp['sv_args'] + except KeyError: pass + env.addDPIImport(imp['c_return_type'],imp['sv_return_type'],imp['name'],imp['c_args'],sv_args) + except KeyError: pass + try: + for exp in dpi_def['exports']: + intf.addDPIExport(exp) + except KeyError: pass + except KeyError: pass + try: + typedefs = struct['typedefs'] + for t in typedefs: + n,v = self.dataExtract(['name','type'],t) + env.addTypedef(n,v) + except KeyError: pass + ## UVMC Stuff + try: + env.addUVMCflags(struct['uvmc_flags']) + except KeyError: pass + try: + env.addUVMClinkArgs(struct['uvmc_link_args']) + except KeyError: pass + try: + cpp_files = struct['uvmc_files'] + for f in cpp_files: + env.addUVMCfile(f) + except KeyError: pass + try: + env.mtlbReady = (struct['mtlb_ready']=="True") + except KeyError: + pass + existing_component = False + try: + if not build_existing: + existing_component = (struct['existing_library_component']=="True") + except KeyError: + pass + if (existing_component == True): + print(" Skipping generation of predefined component "+str(name)) + else: + env.create(parser=self.parser,archive_yaml=archive_yaml) + return env + + def parameterSyntax(self,parameterList): + ## Take the parameter list provided and return the SV syntax for a parameterized type + ## This is expected to be of "parameterUseSchema" with 'name' and a 'value' keys + l = [] + for p in parameterList: + s = "."+p['name']+"("+p['value']+")" + l = l + [ s ] + fs = "#("+','.join(l)+")" + return fs + + def generateBench(self,name,build_existing=False,archive_yaml=True): + ## Isolate the YAML structure for this bench + struct = self.data['benches'][name] + ## Get the name of the top-level environment + top_env = struct['top_env'] + ## Confirm top-level environment is defined + if top_env not in self.data['environments']: + raise UserError("Bench \"{}\" top-env of type \"{}\" is not defined".format(name,top_env)) + ## Top-level environment parameters + try: + env_params_list = struct['top_env_params'] + except KeyError: + env_params_list = [] + pass + ## Build up simpler name/value pair dict of env params + env_params = {} + for p in env_params_list: + env_params[p['name']] = p['value'] + ## Check that parameterization is valid for the top-env + self.check_parameters('bench',name,'environment',top_env,'top_env',env_params_list,self.data['environments'][top_env]) + ## With this information we can create the bench class object + ben = BenchClass(name,top_env,env_params) + ben = self.setupGlobalVars(ben) + ## Look for clock and reset control settings (all optional) + try: + ben.clockHalfPeriod = struct['clock_half_period'] + except KeyError: pass + try: + ben.clockPhaseOffset = struct['clock_phase_offset'] + except KeyError: pass + try: + ben.resetAssertionLevel = (struct['reset_assertion_level']=='True') + except KeyError: pass + try: + ben.useDpiLink = (struct['use_dpi_link']=='True') + except KeyError: pass + try: + ben.resetDuration = struct['reset_duration'] + except KeyError: pass + try: + ben.activePassiveDefault = struct['active_passive_default'] + except KeyError: + ben.activePassiveDefault = 'ACTIVE' + pass + ## Check for inFact ready flag + ben.inFactEnabled = ('infact_enabled' in struct.keys() and struct['infact_enabled']=='True') + + ## Use co-emulation clk/rst generator + try: + ben.useCoEmuClkRstGen = (struct['use_coemu_clk_rst_gen']=='True') + except KeyError: pass + ## Set the veloceReady flag for the bench + try: + ben.veloceReady = (struct['veloce_ready'] == "True") + except KeyError: + ben.veloceReady = True + pass + ## Pull out bench-level parameter definitions, if any + try: + for param in struct['parameters']: + pname,ptype,pval = self.dataExtract(['name','type','value'],param) + ben.addParamDef(pname,ptype,pval) + except KeyError: pass + ## Drill down into any QVIP subenvironments for import information, that'll be needed here + qstruct = self.getQVIPAgents(top_env) + ilist = qstruct['ilist'] + for i in ilist: + ben.addImport(i) + ## Imports + try: + for imp in struct['imports']: + ben.addImport(imp['name']) + except KeyError: pass + ## Pull out active/passive list and produce more easily parsed dict keyed by the BFM names + try: + ap_list = struct['active_passive'] + except KeyError: + ap_list = [] + pass + ap_dict = {} + for i in ap_list: + ap_dict[i['bfm_name']] = i['value'] + ## Do the same for interface parameters + try: + ifp_list = struct['interface_params'] + except KeyError: + ifp_list = [] + ifp_dict = {} + for entry in ifp_list: + bfm_name = entry['bfm_name'] + param_list = entry['value'] + ifp_dict[bfm_name] = {} + for p in param_list: + ifp_dict[bfm_name][p['name']] = p['value'] + ## Determine if top_env has a register model associated with it + try: + e = self.data['environments'][top_env] + except KeyError: + raise UserError("Top-level env \""+top_env+"\" is not defined") + try: + rm = e['register_model'] + ben.topEnvHasRegisterModel = True + try: + rm_pkg = rm['reg_model_package'] + ben.regModelPkg = e['register_model']['reg_model_package'] + except KeyError: + ben.regModelPkg = top_env+"_reg_pkg" + pass + try: + ben.regBlockClass = e['register_model']['reg_block_class'] + except KeyError: + ben.regBlockClass = top_env+"_reg_model" + pass + except KeyError: + ben.topEnvHasRegisterModel = False + pass + ## Find BFMs and add those - order is important, must match how we instantiated the components + ## within the environment. Traverse the environment topology in the order in which sub-envs were + ## called out in the YAML. Use getAllAgents to intelligently traverse the topology and build up a list + ## of BFMs (may be a mix of QVIP and non-QVIP BFMs). Each entry in the resulting list will be a structure + ## with the following information: + ## - BFM Name + ## - BFM Type + ## - Environment Path + ## - QVIP/Non-QVIP flag + ## - Active/Passive flag + ## - Initiator/Responder flag + ## - Veloce Ready flag (for checking) + alist = self.getAllAgents(top_env,'environment',0,'environment') + ## Check for Veloce compatibility. If the bench has been flagged for veloce_ready then none of the underlying + ## non-QVIP agents can be flagged differently. QVIP is a different story, for now. + if ben.veloceReady: + for a in alist: + if a['is_qvip']==0: # Don't bother checking QVIP agents + if not a['veloce_ready']: + ## Fatal out if bench veloce_ready is TRUE but any agents underneath are FALSE + raise UserError("Bench \""+name+"\" is flagged veloce_ready True but underlying agent \""+a['env_path']+"\" of type \""+a['bfm_type']+"\" is flagged veloce_ready False") + valid_bfm_names = [] + ## Now that we have an ordered list of BFMs we can call the appropriate API call for each + for a in alist: + if a['env_path'].count('.')==1: + bfm_name = a['bfm_name'] + debugpath = 'environment' + else: + debugpath = re.sub(r'(.*)\.\w+',r'\1',a['env_path']) + bfm_name = re.sub(r'^environment\.','',a['env_path']) + bfm_name = re.sub(r'\.',r'_',bfm_name) + valid_bfm_names = valid_bfm_names + [bfm_name] + try: + active_passive = ap_dict[bfm_name] + except KeyError: + active_passive = ben.activePassiveDefault + if a['is_qvip']==1: + ## Add each QVIP BFM instantiation. Function API is slightly different for QVIP vs. non-QVIP + ben.addQvipBfm(name=a['bfm_name'],ifPkg=a['parent_type'],activity=active_passive,unique_id=self.getUniqueID(a['env_path'])) + else: + ## Name of each BFM is simplified if they live under the top-level env + ## Determine this by inspecting the env_path entry for each item and counting + ## the number of dots (.). If only one, means this BFM lives at the top-most + ## level. + try: + agentDef = self.data['interfaces'][a['bfm_type']] + except: + raise UserError("Definition for interface type \""+a['bfm_type']+"\" for instance \""+a['env_path']+"\" is not found") + try: + aParams = ifp_dict[bfm_name] + except KeyError: + aParams = {} + pass + infact_ready = ('infact_ready' in a.keys() and a['infact_ready']) + try: + port_list = agentDef['ports'] + except KeyError: + port_list = [] + ben.addBfm(name=bfm_name,ifPkg=a['bfm_type'],clk=agentDef['clock'],rst=agentDef['reset'],activity=active_passive,parametersDict=aParams,sub_env_path=debugpath,agentInstName=a['bfm_name'],vipLibEnvVariable=a['lib_env_var_name'],initResp=a['initiator_responder'],inFactReady=infact_ready,portList=port_list) + ## Check that all keys in the ifp_dict and ap_dict match something in the valid_bfm_names list that + ## was based on the actual UVM component hierarchy elements. If not, it probably means we have a typo somewhere in the bench YAML + for k in ifp_dict.keys(): + if k not in valid_bfm_names: + mess = "BFM name entry \""+k+"\" listed in interface_params structure for bench \""+name+"\" but not a valid BFM name. Valid BFM names:" + for b in valid_bfm_names: + mess = mess+"\n "+b + raise UserError(mess) + for k in ap_dict.keys(): + if k not in valid_bfm_names: + mess = "BFM name entry \""+k+"\" listed in active_passive structure for bench \""+name+"\" but not a valid BFM name. Valid BFM names:" + for b in valid_bfm_names: + mess = mess+"\n "+b + raise UserError(mess) + ## Now drill down again but this time find any DPI packages - these could be defined at any + ## interface or environment, so getAgents isn't good enough. Also need to call getEnvironments + dpi_packages = [] + vinfo_interface_dpi_dependencies = [] + vinfo_environment_dpi_dependencies = [] + for agent in self.getAgents(top_env,recursive=True): + try: + dpi_pkg = self.data['interfaces'][agent['type']]['dpi_define']['name'] + if dpi_pkg not in dpi_packages: + dpi_packages.append(dpi_pkg) + #vinfo_interface_dpi_dependencies.append(self.data['interfaces'][agent['type']]['dpi_define']['name']) + vinfo_interface_dpi_dependencies.append(agent['type']) + except KeyError: pass + envs = self.getEnvironments(top_env,recursive=True) + ## Also add the top-environment to the array when searching for DPI + for env in envs+[{'type':top_env}]: + try: + dpi_pkg = self.data['environments'][env['type']]['dpi_define']['name'] + if dpi_pkg not in dpi_packages: + dpi_packages.append(dpi_pkg) + #vinfo_environment_dpi_dependencies.append(self.data['environments'][env['type']]['dpi_define']['name']) + vinfo_environment_dpi_dependencies.append(env['type']) + except KeyError: pass + for d in dpi_packages: + ben.addDPILibName(d) + for d in vinfo_interface_dpi_dependencies: + ben.addVinfoDependency("comp_"+d+"_pkg_c_files") + for d in vinfo_environment_dpi_dependencies: + ben.addVinfoDependency("comp_"+d+"_env_pkg_c_files") + sblist = self.getAllScoreboards(top_env,'environment','environment') + try: sblist + except NameError: sblist = None + if sblist is not None: + for sb in sblist: + ben.addScoreboard(sb) + try: + for t in struct['additional_tops']: + ben.addTopLevel(t) + except KeyError: pass + try: + ben.mtlbReady = (struct['mtlb_ready']=="True") + except KeyError: + pass + try: + ben.useBCR = (struct['use_bcr']=="True") + except KeyError: + ben.useBCR = False + existing_component = False + try: + if not build_existing: + existing_component = (struct['existing_library_component']=="True") + except KeyError: + pass + if (existing_component == True): + print(" Skipping generation of predefined component "+str(name)) + else: + ben.create(parser=self.parser,archive_yaml=archive_yaml) + return ben + + def generateInterface(self,name,build_existing=False,archive_yaml=True): + intf = InterfaceClass(name) + struct = self.data['interfaces'][name] + intf.clock = struct['clock'] + intf.reset = struct['reset'] + intf = self.setupGlobalVars(intf) + try: + intf.resetAssertionLevel = (struct['reset_assertion_level'] == 'True') + except KeyError: pass + try: + intf.useDpiLink = (struct['use_dpi_link']=='True') + except KeyError: pass + try: + intf.genInBoundStreamingDriver = (struct['gen_inbound_streaming_driver']=='True') + except KeyError: pass + try: + intf.vipLibEnvVariable = struct['vip_lib_env_variable'] + except KeyError: pass + try: + for imp in struct['imports']: + intf.addImport(imp['name']) + except KeyError: pass + try: + for item in struct['parameters']: + n,t,v = self.dataExtract(['name','type','value'],item) + intf.addParamDef(n,t,v) + except KeyError: pass + try: + for item in struct['hdl_pkg_parameters']: + n,t,v = self.dataExtract(['name','type','value'],item) + intf.addHdlPkgParamDef(n,t,v) + except KeyError: pass + try: + for item in struct['hvl_pkg_parameters']: + n,t,v = self.dataExtract(['name','type','value'],item) + intf.addHvlPkgParamDef(n,t,v) + except KeyError: pass + try: + for item in struct['hdl_typedefs']: + n,t = self.dataExtract(['name','type'],item) + intf.addHdlTypedef(n,t) + except KeyError: pass + try: + for item in struct['hvl_typedefs']: + n,t = self.dataExtract(['name','type'],item) + intf.addHvlTypedef(n,t) + except KeyError: pass + try: + for port in struct['ports']: + n,w,d = self.dataExtract(['name','width','dir'],port) + if not re.search(r"^(input|output|inout)$",d): + raise UserError("Direction \""+d+"\" invalid for port \""+n+"\" in interface \""+name+"\"") + try: + r = (port['reset_value']) + except KeyError: + r = "'bz" + intf.addPort(n,w,d,r) + except KeyError: pass + try: + for trans in struct['transaction_vars']: + n,t,c = self.dataExtract(['name','type','comment'],trans) + if not c: + c = "" + try: + trand = (trans['isrand']=="True") + except KeyError: + trand = False + pass + try: + tcomp = (trans['iscompare']=="True") + except KeyError: + tcomp = True + pass + try: + ud = trans['unpacked_dimension'] + except KeyError: + ud = "" + pass + intf.addTransVar(n,t,isrand=trand,iscompare=tcomp,unpackedDim=ud,comment=c) + except KeyError: pass + try: + for cfg in struct['config_vars']: + n,t,c = self.dataExtract(['name','type','comment'],cfg) + if not c: + c = "" + try: + crand = (cfg['isrand']=="True") + except KeyError: + crand = False + pass + cval = '' + try: + cval = cfg['value'] + except KeyError: pass + try: + cvud = cfg['unpacked_dimension'] + except KeyError: + cvud = "" + pass + intf.addConfigVar(n,t,crand,cval,c,cvud) + except KeyError: pass + try: + for item in struct['transaction_constraints']: + n,v,c = self.dataExtract(['name','value','comment'],item) + if not c: + c = "" + intf.addTransVarConstraint(n,v,c) + except KeyError: pass + try: + for item in struct['config_constraints']: + n,v,c = self.dataExtract(['name','value','comment'],item) + if not c: + c = "" + intf.addConfigVarConstraint(n,v,c) + except KeyError: pass + try: + response_info = struct['response_info'] + resp_op = response_info['operation'] + intf.specifyResponseOperation(resp_op) + resp_data = response_info['data'] + intf.specifyResponseData(resp_data) + print("Warning: response_info YAML structure deprecated. Slave agent response data now determined by arguments to respond_and_wait_for_next_transfer task within generated driver_bfm.") + except KeyError: pass + try: + dpi_def = struct['dpi_define'] + ca = "" + la = "" + try: + ca = dpi_def['comp_args'] + except KeyError: pass + try: + la = dpi_def['link_args'] + except KeyError: pass + intf.setDPISOName(value=dpi_def['name'],compArgs=ca,linkArgs=la) + for f in dpi_def['files']: + intf.addDPIFile(f) + try: + for imp in dpi_def['imports']: + sv_args = [] + try: + sv_args = imp['sv_args'] + except KeyError: pass + intf.addDPIImport(imp['c_return_type'],imp['sv_return_type'],imp['name'],imp['c_args'],sv_args) + except KeyError: pass + try: + for exp in dpi_def['exports']: + intf.addDPIExport(exp) + except KeyError: pass + except KeyError: pass + intf.inFactReady = ('infact_ready' in struct.keys() and struct['infact_ready']) + try: + intf.mtlbReady = (struct['mtlb_ready']=="True") + except KeyError: + pass + try: + intf.veloceReady = (struct['veloce_ready'] == "True") + except KeyError: + intf.veloceReady = True + pass + try: + intf.enableFunctionalCoverage = (struct['enable_functional_coverage'] == "True") + except KeyError: pass + if intf.veloceReady == True: + try: + for trans in struct['transaction_vars']: + try: + if trans['unpacked_dimension'] != "": + raise UserError("Interface \""+name+"\" flagged to be Veloce ready but transaction variable \""+trans['name']+"\" has specified an unpacked dimension") + except KeyError: pass + except KeyError: + ## If this happens it means there are no transaction variables, which is also illegal + raise UserError("Interface \"{0}\" flagged to be Veloce ready but no transaction variables have been defined. Must define at least one".format(name)) + pass + try: + for cfg in struct['config_vars']: + try: + if cfg['unpacked_dimension'] != "": + raise UserError("Interface \""+name+"\" flagged to be Veloce ready but configuration variable \""+cfg['name']+"\" has specified an unpacked dimension") + except KeyError: pass + except KeyError: pass + ## If this happens it means there are no transaction variables, which is also illegal +# raise UserError("Interface \"{0}\" flagged to be Veloce ready but no transaction variables have been defined. Must define at least one".format(name)) +# pass + ## Also possible that there was a transaction variables array defined but its empty. Also illegal + if len(struct['transaction_vars'])==0: + raise UserError("Interface \"{0}\" flagged to be Veloce ready but no transaction variables have been defined. Must define at least one".format(name)) + existing_component = False + try: + if not build_existing: + existing_component = (struct['existing_library_component']=="True") + except KeyError: + pass + if existing_component == True: + print(" Skipping generation of predefined component "+str(name)) + else: + intf.create(parser=self.parser,archive_yaml=archive_yaml) + return intf + + def check_parameters(self,parentType,parentName,instanceType,instanceName,definitionName,instanceParams,instanceDefinition): + ## Compare the parameters in a given instance to make sure that the names match up with + ## something in the list of parameters given in the definition. Can be used for any component. Pass + ## in the list of parameters for both. If problem found, display debug information + ## including the name of the parent component, the name and type of the instance and the + ## parameter in question. + ## Don't bother checking anything if the instiation was not provided any parameters. + if len(instanceParams) == 0: + return + try: + definitionParams = instanceDefinition['parameters'] + except KeyError: + raise UserError("When instantiating "+instanceType+" \""+instanceName+"\" of type \""+definitionName+"\" inside "+parentType+" \""+parentName+"\", parameters were provided but definition had no parameters") + ipn = [] + dpn = [] + for p in definitionParams: + dpn = dpn + [p['name']] + for p in instanceParams: + if p['name'] not in dpn: + raise UserError("Unable to find parameter \""+p['name']+"\" in definition of "+instanceType+" \""+definitionName+"\" as instance \""+instanceName+"\" in "+parentType+" \""+parentName+"\"") + +def run(): + ## When invoked, this script can read a series of provided YAML-based configuration files and parse them, building + ## up a database of information on the contained components. Each component will have an associated uvmf_gen class + ## created around it based on the contents. + + ## User can specify that a particular element(s) be created with the -g/--generate switch but the default is to produce + ## everything (i.e. call ".create()" against all defined elements). Any item passed in via --generate + ## that matches the name of a defined element will be generated (if environments/benches/interfaces are named the + ## same the script will match all of them) + search_paths = ['.'] + __version__ = version + uvmf_parser = UVMFCommandLineParser(version=__version__,usage="yaml2uvmf.py [options] [yaml_file1 [yaml_fileN]]") + uvmf_parser.parser.add_option("-f","--file",dest="configfile",action="append",help="Specify a file list of YAML configs. Relative paths relative to the invocation directory") + uvmf_parser.parser.add_option("-F","--relfile",dest="rel_configfile",action="append",help="Specify a file list of YAML configs. Relative paths relative to the file list itself") + uvmf_parser.parser.add_option("-g","--generate",dest="gen_name",action="append",help="Specify which elements to generate (default is everything") + uvmf_parser.parser.add_option("--pdb",dest="enable_pdb",action="store_true",help=SUPPRESS_HELP,default=False) + uvmf_parser.parser.add_option("-m","--merge_source",dest="merge_source",action="store",help="Enable auto-merge flow, pulling from the specified source directory") + uvmf_parser.parser.add_option("-s","--merge_skip_missing_blocks",dest="merge_skip_missing",action="store_true",help="Continue merge if unable to locate a custom block that was defined in old source, producing a report at the end. Default behavior is to raise an error",default=False) + uvmf_parser.parser.add_option("--merge_export_yaml",dest="merge_export_yaml",action="store",help=SUPPRESS_HELP,default=None) + uvmf_parser.parser.add_option("--merge_import_yaml",dest="merge_import_yaml",action="store",help=SUPPRESS_HELP,default=None) + uvmf_parser.parser.add_option("--merge_import_yaml_output",dest="merge_import_yaml_output",action="store",help=SUPPRESS_HELP,default="uvmf_template_merged") + uvmf_parser.parser.add_option("--merge_no_backup",dest="merge_no_backup",action="store_true",help="Do not back up original merge source",default=False) + uvmf_parser.parser.add_option("--merge_debug",dest="merge_debug",action="store_true",help="Provide intermediate unmerged output directory for debug purposes. Debug directory can be specified by --dest_dir switch.",default=False) + uvmf_parser.parser.add_option("--merge_verbose",dest="merge_verbose",action="store_true",help="Output more verbose messages during the merge operation for debug purposes.",default=False) + uvmf_parser.parser.add_option("--build_existing_components",dest="build_existing_components",action="store_true",help="Ignore \"existing_library_component\" flags and attempt to build anyway.",default=False) + uvmf_parser.parser.add_option("--no_archive_yaml",dest="no_archive_yaml",action="store_true",default=False,help="Disable YAML archive creation") + (options,args) = uvmf_parser.parser.parse_args() + if options.enable_pdb or options.debug: + print("Python version info:\n"+sys.version) + if options.enable_pdb == True: + import pdb + pdb.set_trace() + elif options.debug == False: + sys.tracebacklimit = 0 + if (len(args) == 0) and (options.configfile == None) and (options.rel_configfile == None) and (options.merge_source == None): + raise UserError("No configurations or config file specified as input. Must provide one or both") + if (options.merge_source != None) and (options.merge_import_yaml != None): + raise UserError("--merge_source and --merge_import_yaml options are mutually exclusive") + dataObj = DataClass(uvmf_parser) + configfiles = [] + if options.configfile != None: + for cf in options.configfile: + cfr = ConfigFileReader(cf) + configfiles = configfiles + cfr.files + if options.rel_configfile != None: + for cf in options.rel_configfile: + cfr = ConfigFileReader(cf,relative_to_file=True) + configfiles = configfiles + cfr.files + try: + configfiles = configfiles + args + except TypeError: + pass + if len(configfiles) == 0: + if not ((options.merge_source != None) and (options.merge_export_yaml)): + raise UserError("No configuration YAML specified to parse, must provide at least one") + if options.merge_source != None: + if os.path.abspath(os.path.normpath(options.dest_dir)) == os.path.abspath(os.path.normpath(options.merge_source)): + raise UserError("Cannot merge changes into source directory \"{0}\" without specifying an alternate output directory with --dest_dir switch".format(os.path.abspath(os.path.normpath(options.dest_dir)))) + for cfg in configfiles: + dataObj.parseFile(cfg) + dataObj.validate() + dataObj.buildElements(options.gen_name,verify=options.merge_export_yaml==None,build_existing=options.build_existing_components,archive_yaml=(not options.no_archive_yaml)) + if options.merge_source or options.merge_import_yaml: + if not options.merge_import_yaml: + if not (options.merge_no_backup or options.merge_export_yaml): + ## Create a backup of the original source. + backup_copy = backup(options.merge_source) + if not options.quiet: + print("Backed up original source to {0}".format(backup_copy)) + if not options.quiet: + print("Parsing customizations from {0} ...".format(options.merge_source)) + # Parse old source for pragma blocks. Resulting object will contain data structure of this activity + parse = Parse(quiet=options.quiet,cleanup=options.merge_import_yaml,root=os.path.abspath(os.path.normpath(options.merge_source))) + # Need to first produce a list of directories in the new output. Only validate files in the merge source + # that are in the equivalent directories (to do otherwise would be a waste of time) + parse.collect_directories(new_root_dir=options.dest_dir,old_root_dir=options.merge_source) + # Traverse through the merged source directory structure. This will only collect data on + # directories that were just re-generated, nothing outside of that area. + parse.traverse_dir(options.merge_source) + old_root = parse.root + if options.merge_export_yaml: + if not options.quiet: + print(" Exporting merge data to {0}".format(options.merge_export_yaml)) + parse.dump(options.merge_export_yaml) + sys.exit(0) + else: + if not options.quiet: + print("Merging custom code in {0} with new output ...".format(options.merge_source)) + else: + if not options.quiet: + print("Pulling in customizations from imported YAML file {0}".format(options.merge_import_yaml)) + old_root = os.path.abspath(os.path.normpath(options.merge_import_yaml_output)) + merge = Merge(outdir=old_root,skip_missing_blocks=options.merge_skip_missing,new_root=os.path.abspath(os.path.normpath(options.dest_dir)),old_root=old_root,quiet=options.quiet) + if options.merge_import_yaml: + merge.load_yaml(options.merge_import_yaml) + # If we're importing the data, copy newly generated source over to desired final location. This will be what we treat as the "original" output directory + from shutil import copytree + try: + copytree(options.dest_dir,options.merge_import_yaml_output) + except: + pass + else: + merge.load_data(parse.data) + merge.traverse_dir(options.dest_dir) + if (not options.merge_debug): + # Remove the intermediate directory unless asked otherwise + if not options.quiet: + print("Deleting intermediate directory {0} after merging data...".format(options.dest_dir)) + try: + shutil.rmtree(options.dest_dir) + except: + raise UserError("Unable to remove intermediate output directory {0}. Permissions issue?".format(options.dest_dir)) + if not options.quiet: + print("Merge complete!") + if options.merge_verbose: + merge_summary(merge,verbose=True) + merge_summary(merge) + if len(merge.missing_blocks)>0: + print("WARNING: Found \"pragma uvmf custom\" blocks in original source that could not be mapped to new output. These require hand-edits:") + for f in merge.missing_blocks: + print (" File: {0}".format(f)) + for l in merge.missing_blocks[f]: + print(" \"{0}\"".format(l)) + print(" Use backup or revision control source to recover the original content of these blocks") + +if __name__ == '__main__': + run() diff --git a/UVM_Framework/UVMF_2022.3/scripts/Makefile b/UVM_Framework/UVMF_2022.3/scripts/Makefile index bac8b10a..ef3b1e31 100644 --- a/UVM_Framework/UVMF_2022.3/scripts/Makefile +++ b/UVM_Framework/UVMF_2022.3/scripts/Makefile @@ -49,7 +49,7 @@ ifeq ($(DEBUG),1) endif # Control if we wish to use the multi-user coverage mode -MULTIUSER ?= 1 +MULTIUSER ?= 0 # Control whether or not to run at all in debug simulation NO_RUN ?= 0 diff --git a/UVM_Framework/UVMF_2022.3/templates/python/python2/jinja2/__init__.pyc b/UVM_Framework/UVMF_2022.3/templates/python/python2/jinja2/__init__.pyc new file mode 100644 index 00000000..702cc5d8 Binary files /dev/null and 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--git a/UVM_Framework/UVMF_2022.3/templates/python/python2/yaml/tokens.pyc b/UVM_Framework/UVMF_2022.3/templates/python/python2/yaml/tokens.pyc new file mode 100644 index 00000000..b88a600f Binary files /dev/null and b/UVM_Framework/UVMF_2022.3/templates/python/python2/yaml/tokens.pyc differ diff --git a/UVM_Framework/UVMF_2022.3/templates/python/template_files/bench_templates/bench_tb_parameters_bench_parameters_pkg_sv.TMPL b/UVM_Framework/UVMF_2022.3/templates/python/template_files/bench_templates/bench_tb_parameters_bench_parameters_pkg_sv.TMPL index 2712e40d..c8de9055 100644 --- a/UVM_Framework/UVMF_2022.3/templates/python/template_files/bench_templates/bench_tb_parameters_bench_parameters_pkg_sv.TMPL +++ b/UVM_Framework/UVMF_2022.3/templates/python/template_files/bench_templates/bench_tb_parameters_bench_parameters_pkg_sv.TMPL @@ -10,7 +10,8 @@ {% endblock %} {% block contents %} - +`ifndef {{name|upper}}_PARAMETERS_PKG_BENCH +`define {{name|upper}}_PARAMETERS_PKG_BENCH package {{name}}_parameters_pkg; @@ -53,5 +54,5 @@ endpackage // pragma uvmf custom external begin // pragma uvmf custom external end - +`endif {% endblock %} diff --git a/UVM_Framework/UVMF_2022.3/templates/python/template_files/bench_templates/bench_tb_sequences_bench_sequences_pkg_sv.TMPL b/UVM_Framework/UVMF_2022.3/templates/python/template_files/bench_templates/bench_tb_sequences_bench_sequences_pkg_sv.TMPL index d10f8759..2c71b156 100644 --- a/UVM_Framework/UVMF_2022.3/templates/python/template_files/bench_templates/bench_tb_sequences_bench_sequences_pkg_sv.TMPL +++ b/UVM_Framework/UVMF_2022.3/templates/python/template_files/bench_templates/bench_tb_sequences_bench_sequences_pkg_sv.TMPL @@ -17,7 +17,8 @@ {% endblock %} {% block contents %} - +`ifndef {{name|upper}}_SEQUENCES_PKG_BENCH +`define {{name|upper}}_SEQUENCES_PKG_BENCH package {{name}}_sequences_pkg; import uvm_pkg::*; import uvmf_base_pkg::*; @@ -65,5 +66,5 @@ endpackage // pragma uvmf custom external begin // pragma uvmf custom external end - +`endif {% endblock %} diff --git a/UVM_Framework/UVMF_2022.3/templates/python/template_files/bench_templates/bench_tb_sequences_bench_sequences_pkg_sv_mtlb.TMPL b/UVM_Framework/UVMF_2022.3/templates/python/template_files/bench_templates/bench_tb_sequences_bench_sequences_pkg_sv_mtlb.TMPL index a8fddbef..91a4dbd9 100644 --- a/UVM_Framework/UVMF_2022.3/templates/python/template_files/bench_templates/bench_tb_sequences_bench_sequences_pkg_sv_mtlb.TMPL +++ b/UVM_Framework/UVMF_2022.3/templates/python/template_files/bench_templates/bench_tb_sequences_bench_sequences_pkg_sv_mtlb.TMPL @@ -22,6 +22,8 @@ {% block contents %} +`ifndef {{name}}_SEQUENCES_PKG_BENCH_MATLAB +`define {{name}}_SEQUENCES_PKG_BENCH_MATLAB package {{name}}_sequences_pkg; import uvm_pkg::*; import uvmf_base_pkg::*; @@ -71,5 +73,5 @@ endpackage // pragma uvmf custom external begin // pragma uvmf custom external end - +`endif {% endblock %} diff --git a/UVM_Framework/UVMF_2022.3/templates/python/template_files/bench_templates/bench_tb_sequences_infact_bench_sequences_pkg_sv.TMPL b/UVM_Framework/UVMF_2022.3/templates/python/template_files/bench_templates/bench_tb_sequences_infact_bench_sequences_pkg_sv.TMPL index 6fe9a637..5e53d0b0 100644 --- a/UVM_Framework/UVMF_2022.3/templates/python/template_files/bench_templates/bench_tb_sequences_infact_bench_sequences_pkg_sv.TMPL +++ b/UVM_Framework/UVMF_2022.3/templates/python/template_files/bench_templates/bench_tb_sequences_infact_bench_sequences_pkg_sv.TMPL @@ -18,7 +18,8 @@ {% endblock %} {% block contents %} - +`ifndef {{name|upper}}_INFACT_SEQUENCES_PKG +`define {{name|upper}}_INFACT_SEQUENCES_PKG package {{name}}_infact_sequences_pkg; import uvm_pkg::*; import uvmf_base_pkg::*; @@ -70,5 +71,5 @@ endpackage // pragma uvmf custom external begin // pragma uvmf custom external end - +`endif {% endblock %} diff --git a/UVM_Framework/UVMF_2022.3/templates/python/template_files/bench_templates/bench_tb_sequences_src_DPI_stimgen_sequence_svh_mtlb.TMPL b/UVM_Framework/UVMF_2022.3/templates/python/template_files/bench_templates/bench_tb_sequences_src_DPI_stimgen_sequence_svh_mtlb.TMPL index 2583d70a..f2e61bb1 100644 --- a/UVM_Framework/UVMF_2022.3/templates/python/template_files/bench_templates/bench_tb_sequences_src_DPI_stimgen_sequence_svh_mtlb.TMPL +++ b/UVM_Framework/UVMF_2022.3/templates/python/template_files/bench_templates/bench_tb_sequences_src_DPI_stimgen_sequence_svh_mtlb.TMPL @@ -14,7 +14,8 @@ {% endblock %} {% block contents %} - +`ifndef DPI_STIMGEN_SEQUENCE_SEQUENCE +`define DPI_STIMGEN_SEQUENCE_SEQUENCE class DPI_stimgen_sequence extends {{name}}_bench_sequence_base; `uvm_object_utils( DPI_stimgen_sequence ); @@ -73,5 +74,5 @@ endclass // pragma uvmf custom external begin // pragma uvmf custom external end - +`endif {% endblock %} diff --git a/UVM_Framework/UVMF_2022.3/templates/python/template_files/bench_templates/bench_tb_sequences_src_bench_sequence_base_svh.TMPL b/UVM_Framework/UVMF_2022.3/templates/python/template_files/bench_templates/bench_tb_sequences_src_bench_sequence_base_svh.TMPL index c7ad4190..c4c84dee 100644 --- a/UVM_Framework/UVMF_2022.3/templates/python/template_files/bench_templates/bench_tb_sequences_src_bench_sequence_base_svh.TMPL +++ b/UVM_Framework/UVMF_2022.3/templates/python/template_files/bench_templates/bench_tb_sequences_src_bench_sequence_base_svh.TMPL @@ -13,7 +13,8 @@ {% endblock %} {% block contents %} - +`ifndef {{name|upper}}_BENCH_SEQUENCE_BASE +`define {{name|upper}}_BENCH_SEQUENCE_BASE typedef {{env_name}}_env_configuration {{macro.paramUseNested(envParamDefs)|indent(8)}} {{env_name}}_env_configuration_t; @@ -214,5 +215,5 @@ endclass // pragma uvmf custom external begin // pragma uvmf custom external end - +`endif {% endblock %} diff --git a/UVM_Framework/UVMF_2022.3/templates/python/template_files/bench_templates/bench_tb_sequences_src_example_derived_test_sequence_svh.TMPL b/UVM_Framework/UVMF_2022.3/templates/python/template_files/bench_templates/bench_tb_sequences_src_example_derived_test_sequence_svh.TMPL index dee1b331..c19f02df 100644 --- a/UVM_Framework/UVMF_2022.3/templates/python/template_files/bench_templates/bench_tb_sequences_src_example_derived_test_sequence_svh.TMPL +++ b/UVM_Framework/UVMF_2022.3/templates/python/template_files/bench_templates/bench_tb_sequences_src_example_derived_test_sequence_svh.TMPL @@ -13,7 +13,8 @@ {% endblock %} {% block contents %} - +`ifndef EXAMPLE_DERIVED_TEST_SEQUENCE +`define EXAMPLE_DERIVED_TEST_SEQUENCE class example_derived_test_sequence extends {{name}}_bench_sequence_base; `uvm_object_utils( example_derived_test_sequence ); @@ -26,5 +27,5 @@ endclass // pragma uvmf custom external begin // pragma uvmf custom external end - +`endif {% endblock %} diff --git a/UVM_Framework/UVMF_2022.3/templates/python/template_files/bench_templates/bench_tb_sequences_src_infact_bench_sequence_svh.TMPL b/UVM_Framework/UVMF_2022.3/templates/python/template_files/bench_templates/bench_tb_sequences_src_infact_bench_sequence_svh.TMPL index 3df49e72..df55200b 100644 --- a/UVM_Framework/UVMF_2022.3/templates/python/template_files/bench_templates/bench_tb_sequences_src_infact_bench_sequence_svh.TMPL +++ b/UVM_Framework/UVMF_2022.3/templates/python/template_files/bench_templates/bench_tb_sequences_src_infact_bench_sequence_svh.TMPL @@ -12,7 +12,8 @@ {% endblock %} {% block contents %} - +`ifndef INFACT_{{name|upper}}_BENCH_SEQUENCE_BASE +`define INFACT_{{name|upper}}_BENCH_SEQUENCE_BASE class infact_{{name}}_bench_sequence_base extends {{name}}_bench_sequence_base; `uvm_object_utils( infact_{{name}}_bench_sequence_base ); @@ -80,5 +81,5 @@ endclass // pragma uvmf custom external begin // pragma uvmf custom external end - +`endif {% endblock %} diff --git a/UVM_Framework/UVMF_2022.3/templates/python/template_files/bench_templates/bench_tb_sequences_src_read_from_file_sequence_svh_mtlb.TMPL b/UVM_Framework/UVMF_2022.3/templates/python/template_files/bench_templates/bench_tb_sequences_src_read_from_file_sequence_svh_mtlb.TMPL index 7fa3c596..1bc19931 100644 --- a/UVM_Framework/UVMF_2022.3/templates/python/template_files/bench_templates/bench_tb_sequences_src_read_from_file_sequence_svh_mtlb.TMPL +++ b/UVM_Framework/UVMF_2022.3/templates/python/template_files/bench_templates/bench_tb_sequences_src_read_from_file_sequence_svh_mtlb.TMPL @@ -14,7 +14,8 @@ {% endblock %} {% block contents %} - +`ifndef READ_FROM_FILE_SEQUENCE +`define READ_FROM_FILE_SEQUENCE class read_from_file_sequence extends {{name}}_bench_sequence_base; `uvm_object_utils( read_from_file_sequence ); @@ -71,5 +72,5 @@ endclass // pragma uvmf custom external begin // pragma uvmf custom external end - +`endif {% endblock %} diff --git a/UVM_Framework/UVMF_2022.3/templates/python/template_files/bench_templates/bench_tb_sequences_src_register_test_sequence_svh.TMPL b/UVM_Framework/UVMF_2022.3/templates/python/template_files/bench_templates/bench_tb_sequences_src_register_test_sequence_svh.TMPL index 0006e270..3f09584e 100644 --- a/UVM_Framework/UVMF_2022.3/templates/python/template_files/bench_templates/bench_tb_sequences_src_register_test_sequence_svh.TMPL +++ b/UVM_Framework/UVMF_2022.3/templates/python/template_files/bench_templates/bench_tb_sequences_src_register_test_sequence_svh.TMPL @@ -12,7 +12,8 @@ {% endblock %} {% block contents %} - +`ifndef REGISTER_TEST_SEQUENCE +`define REGISTER_TEST_SEQUENCE class register_test_sequence extends {{name}}_bench_sequence_base; `uvm_object_utils( register_test_sequence ); @@ -82,5 +83,5 @@ endclass // pragma uvmf custom external begin // pragma uvmf custom external end - +`endif {% endblock %} diff --git a/UVM_Framework/UVMF_2022.3/templates/python/template_files/bench_templates/bench_tb_tests_bench_tests_pkg_sv.TMPL b/UVM_Framework/UVMF_2022.3/templates/python/template_files/bench_templates/bench_tb_tests_bench_tests_pkg_sv.TMPL index e91cbad5..3601b622 100644 --- a/UVM_Framework/UVMF_2022.3/templates/python/template_files/bench_templates/bench_tb_tests_bench_tests_pkg_sv.TMPL +++ b/UVM_Framework/UVMF_2022.3/templates/python/template_files/bench_templates/bench_tb_tests_bench_tests_pkg_sv.TMPL @@ -16,7 +16,8 @@ {% endblock %} {% block contents %} - +`ifndef {{name|upper}}_TESTS_PKG +`define {{name|upper}}_TESTS_PKG package {{name}}_tests_pkg; import uvm_pkg::*; diff --git a/UVM_Framework/UVMF_2022.3/templates/python/template_files/bench_templates/bench_tb_tests_bench_tests_pkg_sv_mtlb.TMPL b/UVM_Framework/UVMF_2022.3/templates/python/template_files/bench_templates/bench_tb_tests_bench_tests_pkg_sv_mtlb.TMPL index d8949452..aa2b7353 100644 --- a/UVM_Framework/UVMF_2022.3/templates/python/template_files/bench_templates/bench_tb_tests_bench_tests_pkg_sv_mtlb.TMPL +++ b/UVM_Framework/UVMF_2022.3/templates/python/template_files/bench_templates/bench_tb_tests_bench_tests_pkg_sv_mtlb.TMPL @@ -21,6 +21,8 @@ {% block contents %} +`ifndef {{name|upper}}_TESTS_PKG_MATLAB +`define {{name|upper}}_TESTS_PKG_MATLAB package {{name}}_tests_pkg; import uvm_pkg::*; @@ -69,5 +71,5 @@ endpackage // pragma uvmf custom external begin // pragma uvmf custom external end - +`endif {% endblock %} diff --git a/UVM_Framework/UVMF_2022.3/templates/python/template_files/bench_templates/bench_tb_tests_src_DPI_stimgen_test_svh_mtlb.TMPL b/UVM_Framework/UVMF_2022.3/templates/python/template_files/bench_templates/bench_tb_tests_src_DPI_stimgen_test_svh_mtlb.TMPL index 0666c775..475e5559 100644 --- a/UVM_Framework/UVMF_2022.3/templates/python/template_files/bench_templates/bench_tb_tests_src_DPI_stimgen_test_svh_mtlb.TMPL +++ b/UVM_Framework/UVMF_2022.3/templates/python/template_files/bench_templates/bench_tb_tests_src_DPI_stimgen_test_svh_mtlb.TMPL @@ -17,6 +17,8 @@ {% endblock %} {% block contents %} +`ifndef DPI_STIMGEN_TEST +`define DPI_STIMGEN_TEST class DPI_stimgen_test extends test_top; @@ -36,5 +38,5 @@ endclass // pragma uvmf custom external begin // pragma uvmf custom external end - +`endif {% endblock %} diff --git a/UVM_Framework/UVMF_2022.3/templates/python/template_files/bench_templates/bench_tb_tests_src_example_derived_test_svh.TMPL b/UVM_Framework/UVMF_2022.3/templates/python/template_files/bench_templates/bench_tb_tests_src_example_derived_test_svh.TMPL index 9fdf8a03..f4b98a1a 100644 --- a/UVM_Framework/UVMF_2022.3/templates/python/template_files/bench_templates/bench_tb_tests_src_example_derived_test_svh.TMPL +++ b/UVM_Framework/UVMF_2022.3/templates/python/template_files/bench_templates/bench_tb_tests_src_example_derived_test_svh.TMPL @@ -14,7 +14,8 @@ {% endblock %} {% block contents %} - +`ifndef EXAMPLE_DERIVED_TEST +`define EXAMPLE_DERIVED_TEST class example_derived_test extends test_top; `uvm_component_utils( example_derived_test ); @@ -39,5 +40,5 @@ endclass // pragma uvmf custom external begin // pragma uvmf custom external end - +`endif {% endblock %} diff --git a/UVM_Framework/UVMF_2022.3/templates/python/template_files/bench_templates/bench_tb_tests_src_infact_test_base.TMPL b/UVM_Framework/UVMF_2022.3/templates/python/template_files/bench_templates/bench_tb_tests_src_infact_test_base.TMPL index f5251cd6..36bf93cc 100644 --- a/UVM_Framework/UVMF_2022.3/templates/python/template_files/bench_templates/bench_tb_tests_src_infact_test_base.TMPL +++ b/UVM_Framework/UVMF_2022.3/templates/python/template_files/bench_templates/bench_tb_tests_src_infact_test_base.TMPL @@ -13,7 +13,8 @@ {% endblock %} {% block contents %} - +`ifndef INFACT_TEST_BASE +`define INFACT_TEST_BASE class infact_test_base extends test_top; `uvm_component_utils( infact_test_base ); @@ -37,5 +38,5 @@ endclass // pragma uvmf custom external begin // pragma uvmf custom external end - +`endif {% endblock %} diff --git a/UVM_Framework/UVMF_2022.3/templates/python/template_files/bench_templates/bench_tb_tests_src_read_from_file_test_svh_mtlb.TMPL b/UVM_Framework/UVMF_2022.3/templates/python/template_files/bench_templates/bench_tb_tests_src_read_from_file_test_svh_mtlb.TMPL index ec1ad2a7..3e0c3f68 100755 --- a/UVM_Framework/UVMF_2022.3/templates/python/template_files/bench_templates/bench_tb_tests_src_read_from_file_test_svh_mtlb.TMPL +++ b/UVM_Framework/UVMF_2022.3/templates/python/template_files/bench_templates/bench_tb_tests_src_read_from_file_test_svh_mtlb.TMPL @@ -17,7 +17,8 @@ {% endblock %} {% block contents %} - +`ifndef READ_FROM_FILE_TEST +`define READ_FROM_FILE_TEST class read_from_file_test extends test_top; `uvm_component_utils( read_from_file_test ); @@ -36,5 +37,5 @@ endclass // pragma uvmf custom external begin // pragma uvmf custom external end - +`endif {% endblock %} diff --git a/UVM_Framework/UVMF_2022.3/templates/python/template_files/bench_templates/bench_tb_tests_src_register_test_svh.TMPL b/UVM_Framework/UVMF_2022.3/templates/python/template_files/bench_templates/bench_tb_tests_src_register_test_svh.TMPL index 8140d2ac..c787befe 100644 --- a/UVM_Framework/UVMF_2022.3/templates/python/template_files/bench_templates/bench_tb_tests_src_register_test_svh.TMPL +++ b/UVM_Framework/UVMF_2022.3/templates/python/template_files/bench_templates/bench_tb_tests_src_register_test_svh.TMPL @@ -14,7 +14,8 @@ {% endblock %} {% block contents %} - +`ifndef REGISTER_TEST +`define REGISTER_TEST class register_test extends test_top; `uvm_component_utils( register_test ); @@ -51,5 +52,5 @@ endclass // pragma uvmf custom external begin // pragma uvmf custom external end - +`endif {% endblock %} diff --git a/UVM_Framework/UVMF_2022.3/templates/python/template_files/bench_templates/bench_tb_tests_src_test_top_svh.TMPL b/UVM_Framework/UVMF_2022.3/templates/python/template_files/bench_templates/bench_tb_tests_src_test_top_svh.TMPL index 7bd893d0..27beac96 100644 --- a/UVM_Framework/UVMF_2022.3/templates/python/template_files/bench_templates/bench_tb_tests_src_test_top_svh.TMPL +++ b/UVM_Framework/UVMF_2022.3/templates/python/template_files/bench_templates/bench_tb_tests_src_test_top_svh.TMPL @@ -18,7 +18,8 @@ typedef {{env_name}}_env_configuration {{macro.paramUseNested(envParamDefs)|indent(8)}}{{env_name}}_env_configuration_t; typedef {{env_name}}_environment {{macro.paramUseNested(envParamDefs)|indent(8)}}{{env_name}}_environment_t; - +`ifndef TEST_TOP +`define TEST_TOP class test_top extends uvmf_test_base #(.CONFIG_T({{env_name}}_env_configuration_t), .ENV_T({{env_name}}_environment_t), .TOP_LEVEL_SEQ_T({{name}}_bench_sequence_base)); @@ -137,5 +138,5 @@ endclass // pragma uvmf custom external begin // pragma uvmf custom external end - +`endif {% endblock %} diff --git a/UVM_Framework/UVMF_2022.3/templates/python/template_files/environment_templates/coverage.TMPL b/UVM_Framework/UVMF_2022.3/templates/python/template_files/environment_templates/coverage.TMPL index 1ad18a34..86dfa231 100644 --- a/UVM_Framework/UVMF_2022.3/templates/python/template_files/environment_templates/coverage.TMPL +++ b/UVM_Framework/UVMF_2022.3/templates/python/template_files/environment_templates/coverage.TMPL @@ -29,6 +29,8 @@ {% endblock %} {% block contents %} +`ifndef {{name|upper}} +`define {{name|upper}} class {{name}} {{macro.paramDeclare(parameters)|indent(2)}} extends BASE_T; @@ -166,8 +168,8 @@ class {{name}} {{macro.paramDeclare(parameters)|indent(2)}} extends BASE_T; endfunction {% endfor %} endclass - // pragma uvmf custom external begin // pragma uvmf custom external end +`endif {% endblock %} diff --git a/UVM_Framework/UVMF_2022.3/templates/python/template_files/environment_templates/environment_configuration.TMPL b/UVM_Framework/UVMF_2022.3/templates/python/template_files/environment_templates/environment_configuration.TMPL index 0afa2eb9..b13e54e8 100644 --- a/UVM_Framework/UVMF_2022.3/templates/python/template_files/environment_templates/environment_configuration.TMPL +++ b/UVM_Framework/UVMF_2022.3/templates/python/template_files/environment_templates/environment_configuration.TMPL @@ -12,6 +12,9 @@ {% endblock %} {% block contents %} +`ifndef {{name|upper}}_ENV_CONFIGURATION +`define {{name|upper}}_ENV_CONFIGURATION + class {{name}}_env_configuration {{macro.paramDeclare(paramDefs)|indent(13)}} extends uvmf_environment_configuration_base; @@ -241,5 +244,6 @@ endclass // pragma uvmf custom external begin // pragma uvmf custom external end +`endif {% endblock %} diff --git a/UVM_Framework/UVMF_2022.3/templates/python/template_files/environment_templates/environment_dotsvproject.TMPL b/UVM_Framework/UVMF_2022.3/templates/python/template_files/environment_templates/environment_dotsvproject.TMPL index b40f67fd..f929d355 100644 --- a/UVM_Framework/UVMF_2022.3/templates/python/template_files/environment_templates/environment_dotsvproject.TMPL +++ b/UVM_Framework/UVMF_2022.3/templates/python/template_files/environment_templates/environment_dotsvproject.TMPL @@ -14,4 +14,4 @@ - \ No newline at end of file + diff --git a/UVM_Framework/UVMF_2022.3/templates/python/template_files/environment_templates/environment_environment.TMPL b/UVM_Framework/UVMF_2022.3/templates/python/template_files/environment_templates/environment_environment.TMPL index 736861da..8799a970 100755 --- a/UVM_Framework/UVMF_2022.3/templates/python/template_files/environment_templates/environment_environment.TMPL +++ b/UVM_Framework/UVMF_2022.3/templates/python/template_files/environment_templates/environment_environment.TMPL @@ -11,6 +11,8 @@ {% endblock %} {% block contents %} +`ifndef {{name|upper}}_ENVIRONMENT +`define {{name|upper}}_ENVIRONMENT class {{name}}_environment {{macro.paramDeclare(paramDefs)|indent(2)}} extends uvmf_environment_base #( .CONFIG_T( {{name}}_env_configuration {{macro.paramUse(paramDefs)|indent(22)}} @@ -259,8 +261,8 @@ class {{name}}_environment {{macro.paramDeclare(paramDefs)|indent(2)}} extends u endfunction endclass - // pragma uvmf custom external begin // pragma uvmf custom external end +`endif {% endblock %} diff --git a/UVM_Framework/UVMF_2022.3/templates/python/template_files/environment_templates/environment_sequence_base.TMPL b/UVM_Framework/UVMF_2022.3/templates/python/template_files/environment_templates/environment_sequence_base.TMPL index ad0e5dbc..f5f388b3 100644 --- a/UVM_Framework/UVMF_2022.3/templates/python/template_files/environment_templates/environment_sequence_base.TMPL +++ b/UVM_Framework/UVMF_2022.3/templates/python/template_files/environment_templates/environment_sequence_base.TMPL @@ -11,6 +11,9 @@ {% endblock %} {% block contents %} +`ifndef {{name|upper}}_ENV_SEQUENCE_BASE +`define {{name|upper}}_ENV_SEQUENCE_BASE + class {{name}}_env_sequence_base #( type CONFIG_T{% if paramDefs|length > 0 %}{% for param in paramDefs -%}{% if loop.first %}, {% endif %} @@ -115,8 +118,8 @@ rand {{sub_env.name}}_sequence_base_t {{sub_env.name}}_seq; endtask endclass - // pragma uvmf custom external begin // pragma uvmf custom external end +`endif {% endblock %} diff --git a/UVM_Framework/UVMF_2022.3/templates/python/template_files/environment_templates/environment_sequence_base.TMPL.stash b/UVM_Framework/UVMF_2022.3/templates/python/template_files/environment_templates/environment_sequence_base.TMPL.stash index ad0e5dbc..f5f388b3 100644 --- a/UVM_Framework/UVMF_2022.3/templates/python/template_files/environment_templates/environment_sequence_base.TMPL.stash +++ b/UVM_Framework/UVMF_2022.3/templates/python/template_files/environment_templates/environment_sequence_base.TMPL.stash @@ -11,6 +11,9 @@ {% endblock %} {% block contents %} +`ifndef {{name|upper}}_ENV_SEQUENCE_BASE +`define {{name|upper}}_ENV_SEQUENCE_BASE + class {{name}}_env_sequence_base #( type CONFIG_T{% if paramDefs|length > 0 %}{% for param in paramDefs -%}{% if loop.first %}, {% endif %} @@ -115,8 +118,8 @@ rand {{sub_env.name}}_sequence_base_t {{sub_env.name}}_seq; endtask endclass - // pragma uvmf custom external begin // pragma uvmf custom external end +`endif {% endblock %} diff --git a/UVM_Framework/UVMF_2022.3/templates/python/template_files/environment_templates/predictor.TMPL b/UVM_Framework/UVMF_2022.3/templates/python/template_files/environment_templates/predictor.TMPL index d61ee4f1..cd01c217 100644 --- a/UVM_Framework/UVMF_2022.3/templates/python/template_files/environment_templates/predictor.TMPL +++ b/UVM_Framework/UVMF_2022.3/templates/python/template_files/environment_templates/predictor.TMPL @@ -25,6 +25,8 @@ //---------------------------------------------------------------------- {% endblock %} {% block contents %} +`ifndef {{name|upper}} +`define {{name|upper}} class {{name}} {{macro.paramDeclare(parameters)|indent(2)}} extends BASE_T; @@ -189,4 +191,5 @@ endclass // pragma uvmf custom external begin // pragma uvmf custom external end +`endif {% endblock %} diff --git a/UVM_Framework/UVMF_2022.3/templates/python/template_files/environment_templates/predictor_mtlb.TMPL b/UVM_Framework/UVMF_2022.3/templates/python/template_files/environment_templates/predictor_mtlb.TMPL index e73398cd..0e9f9b43 100644 --- a/UVM_Framework/UVMF_2022.3/templates/python/template_files/environment_templates/predictor_mtlb.TMPL +++ b/UVM_Framework/UVMF_2022.3/templates/python/template_files/environment_templates/predictor_mtlb.TMPL @@ -27,6 +27,8 @@ //---------------------------------------------------------------------- {% endblock %} {% block contents %} +`ifndef {{name|upper}} +`define {{name|upper}} class {{name}} {{macro.paramDeclare(parameters)|indent(2)}} extends uvm_component; @@ -215,8 +217,8 @@ class {{name}} {{macro.paramDeclare(parameters)|indent(2)}} extends uvm_componen endfunction endclass - // pragma uvmf custom external begin // pragma uvmf custom external end +`endif {% endblock %} diff --git a/UVM_Framework/UVMF_2022.3/templates/python/template_files/environment_templates/reg_model.TMPL b/UVM_Framework/UVMF_2022.3/templates/python/template_files/environment_templates/reg_model.TMPL index 089b1648..9912f805 100755 --- a/UVM_Framework/UVMF_2022.3/templates/python/template_files/environment_templates/reg_model.TMPL +++ b/UVM_Framework/UVMF_2022.3/templates/python/template_files/environment_templates/reg_model.TMPL @@ -29,6 +29,15 @@ package {{regModelPkg}}; // Class: {{env_name}}_example_reg0 // //-------------------------------------------------------------------- + `ifndef {{env_name|upper}}_EXAMPLE_REG0 + `define {{env_name|upper}}_EXAMPLE_REG0 + `ifndef {{env_name|upper}}_EXAMPLE_REG1 + `define {{env_name|upper}}_EXAMPLE_REG1 + `ifndef {{env_name|upper}}_{{busMap}}_COVERAGE + `define {{env_name|upper}}_{{busMap}}_COVERAGE + `ifndef {{regBlockClass|upper}} + `define {{regBlockClass|upper}} + class {{env_name}}_example_reg0 extends uvm_reg; `uvm_object_utils({{env_name}}_example_reg0) @@ -203,5 +212,6 @@ endpackage // pragma uvmf custom external begin // pragma uvmf custom external end +`endif {% endblock %} diff --git a/UVM_Framework/UVMF_2022.3/templates/python/template_files/environment_templates/scoreboard.TMPL b/UVM_Framework/UVMF_2022.3/templates/python/template_files/environment_templates/scoreboard.TMPL index 1e135ce1..894ee52c 100644 --- a/UVM_Framework/UVMF_2022.3/templates/python/template_files/environment_templates/scoreboard.TMPL +++ b/UVM_Framework/UVMF_2022.3/templates/python/template_files/environment_templates/scoreboard.TMPL @@ -24,7 +24,8 @@ //---------------------------------------------------------------------- {% endblock %} {% block contents %} - +`ifndef {{name|upper}} +`define {{name|upper}} class {{name}} {{macro.paramDeclare(parameters)|indent(2)}} extends BASE_T; @@ -185,8 +186,8 @@ class {{name}} {{macro.paramDeclare(parameters)|indent(2)}} extends BASE_T; endfunction endclass - // pragma uvmf custom external begin // pragma uvmf custom external end +`endif {% endblock %} diff --git a/UVM_Framework/UVMF_2022.3/templates/python/template_files/environment_templates/tlm2_sysc_predictor.TMPL b/UVM_Framework/UVMF_2022.3/templates/python/template_files/environment_templates/tlm2_sysc_predictor.TMPL index 5a5b648b..bf2f5c3f 100644 --- a/UVM_Framework/UVMF_2022.3/templates/python/template_files/environment_templates/tlm2_sysc_predictor.TMPL +++ b/UVM_Framework/UVMF_2022.3/templates/python/template_files/environment_templates/tlm2_sysc_predictor.TMPL @@ -44,6 +44,7 @@ import uvmc_pkg::*; /// b_transport_XXX IMP //////////////////////////////////////////// + `define UVM_TLM_B_TRANSPORT_IMP_DECL(SFX,imp, T, t, delay) \ task b_transport(T t, uvm_tlm_time delay); \ if (delay == null) begin \ diff --git a/UVM_Framework/UVMF_2022.3/templates/python/template_files/interface_templates/interface_DPI_stimgen_sequence_mtlb.TMPL b/UVM_Framework/UVMF_2022.3/templates/python/template_files/interface_templates/interface_DPI_stimgen_sequence_mtlb.TMPL index cf700f09..505e4285 100755 --- a/UVM_Framework/UVMF_2022.3/templates/python/template_files/interface_templates/interface_DPI_stimgen_sequence_mtlb.TMPL +++ b/UVM_Framework/UVMF_2022.3/templates/python/template_files/interface_templates/interface_DPI_stimgen_sequence_mtlb.TMPL @@ -19,6 +19,8 @@ // **************************************************************************** // This sequence constructs a {{name}}_transaction and uses DPI-C to create stimulus values. // +`ifndef {{name|upper}}_DPI_STIMGEN_SEQUENCE +`define {{name|upper}}_DPI_STIMGEN_SEQUENCE class {{name}}_DPI_stimgen_sequence {%if paramDefs|length > 0%} #( {% for param in paramDefs %} {{param.type}} {{param.name}} = {{param.value}}{% if not loop.last %},{% endif %} {% endfor %} ) @@ -156,5 +158,5 @@ endclass: {{name}}_DPI_stimgen_sequence // pragma uvmf custom external begin // pragma uvmf custom external end - +`endif {% endblock %} diff --git a/UVM_Framework/UVMF_2022.3/templates/python/template_files/interface_templates/interface_agent.TMPL b/UVM_Framework/UVMF_2022.3/templates/python/template_files/interface_templates/interface_agent.TMPL index 69608ce0..957fd334 100755 --- a/UVM_Framework/UVMF_2022.3/templates/python/template_files/interface_templates/interface_agent.TMPL +++ b/UVM_Framework/UVMF_2022.3/templates/python/template_files/interface_templates/interface_agent.TMPL @@ -8,8 +8,11 @@ // //---------------------------------------------------------------------- {% endblock %} - {% block contents %} + +`ifndef {{name|upper}}_AGENT +`define {{name|upper}}_AGENT + class {{name}}_agent {{macro.paramDeclare(paramDefs)|indent(5)}} extends uvmf_parameterized_agent #( .CONFIG_T({{name}}_configuration {{macro.paramUse(paramDefs)|indent(30)}}), .DRIVER_T({{name}}_driver {{macro.paramUse(paramDefs)|indent(30)}}), @@ -47,7 +50,8 @@ class {{name}}_agent {{macro.paramDeclare(paramDefs)|indent(5)}} extends uvmf_pa endclass + // pragma uvmf custom external begin // pragma uvmf custom external end - +`endif {% endblock %} diff --git a/UVM_Framework/UVMF_2022.3/templates/python/template_files/interface_templates/interface_configuration.TMPL b/UVM_Framework/UVMF_2022.3/templates/python/template_files/interface_templates/interface_configuration.TMPL index 848f2788..53bded17 100755 --- a/UVM_Framework/UVMF_2022.3/templates/python/template_files/interface_templates/interface_configuration.TMPL +++ b/UVM_Framework/UVMF_2022.3/templates/python/template_files/interface_templates/interface_configuration.TMPL @@ -10,8 +10,10 @@ // //---------------------------------------------------------------------- {% endblock %} - {% block contents %} + +`ifndef {{name|upper}}_CONFIGURATION +`define {{name|upper}}_CONFIGURATION class {{name}}_configuration {{macro.paramDeclare(paramDefs)|indent(6)}} extends uvmf_parameterized_agent_configuration_base #( .DRIVER_BFM_BIND_T({% if useDpiLink %}{{name}}_driver_proxy {% else %}virtual {{name}}_driver_bfm {% endif %}{{macro.paramUse(paramDefs)|indent(26)}}), .MONITOR_BFM_BIND_T({% if useDpiLink %} {{name}}_monitor_proxy {% else %} virtual {{name}}_monitor_bfm {% endif %}{{macro.paramUse(paramDefs)|indent(26)}})); @@ -201,5 +203,5 @@ endclass // pragma uvmf custom external begin // pragma uvmf custom external end - +`endif {% endblock %} diff --git a/UVM_Framework/UVMF_2022.3/templates/python/template_files/interface_templates/interface_driver.TMPL b/UVM_Framework/UVMF_2022.3/templates/python/template_files/interface_templates/interface_driver.TMPL index 2149d2b8..45e02677 100644 --- a/UVM_Framework/UVMF_2022.3/templates/python/template_files/interface_templates/interface_driver.TMPL +++ b/UVM_Framework/UVMF_2022.3/templates/python/template_files/interface_templates/interface_driver.TMPL @@ -12,8 +12,9 @@ // //---------------------------------------------------------------------- {% endblock %} - {% block contents %} +`ifndef {{name|upper}}_DRIVER +`define {{name|upper}}_DRIVER class {{name}}_driver {{macro.paramDeclare(paramDefs)|indent(6)}} extends uvmf_driver_base #( .CONFIG_T({{name}}_configuration {{macro.paramUse(paramDefs)|indent(29)}} ), .BFM_BIND_T({% if useDpiLink %}{{name}}_driver_proxy {% else %}virtual {{name}}_driver_bfm {% endif %} {{macro.paramUse(paramDefs)|indent(29)}} ), @@ -102,5 +103,5 @@ endclass // pragma uvmf custom external begin // pragma uvmf custom external end - +`endif {% endblock %} diff --git a/UVM_Framework/UVMF_2022.3/templates/python/template_files/interface_templates/interface_driver_bfm.TMPL b/UVM_Framework/UVMF_2022.3/templates/python/template_files/interface_templates/interface_driver_bfm.TMPL index 2883d5e7..90c8592f 100644 --- a/UVM_Framework/UVMF_2022.3/templates/python/template_files/interface_templates/interface_driver_bfm.TMPL +++ b/UVM_Framework/UVMF_2022.3/templates/python/template_files/interface_templates/interface_driver_bfm.TMPL @@ -50,7 +50,8 @@ // //---------------------------------------------------------------------- {% endblock %} - +`ifndef {{name|upper}}_DRIVER_BFM +`define {{name|upper}}_DRIVER_BFM {% block contents %} import uvmf_base_pkg_hdl::*; import {{name}}_pkg_hdl::*; @@ -96,8 +97,8 @@ end {{config.type}} {{config.name}} {{config.unpackedDim}}; {% endfor %} - tri {{clock}}_i; - tri {{reset}}_i; + logic {{clock}}_i; + logic {{reset}}_i; // Signal list (all signals are capable of being inputs and outputs for the sake // of supporting both INITIATOR and RESPONDER mode operation. Expectation is that @@ -462,5 +463,5 @@ endinterface // pragma uvmf custom external begin // pragma uvmf custom external end - +`endif {% endblock %} diff --git a/UVM_Framework/UVMF_2022.3/templates/python/template_files/interface_templates/interface_driver_bfm_mtlb.TMPL b/UVM_Framework/UVMF_2022.3/templates/python/template_files/interface_templates/interface_driver_bfm_mtlb.TMPL index 7a57892b..16479325 100644 --- a/UVM_Framework/UVMF_2022.3/templates/python/template_files/interface_templates/interface_driver_bfm_mtlb.TMPL +++ b/UVM_Framework/UVMF_2022.3/templates/python/template_files/interface_templates/interface_driver_bfm_mtlb.TMPL @@ -54,8 +54,10 @@ // //---------------------------------------------------------------------- {% endblock %} - {% block contents %} + +`ifndef {{name|upper}}_DRIVER_BFM_MATLAB +`define {{name|upper}}_DRIVER_BFM_MATLAB import uvmf_base_pkg_hdl::*; import {{name}}_pkg_hdl::*; {% if veloceReady %} @@ -374,5 +376,5 @@ endinterface // pragma uvmf custom external begin // pragma uvmf custom external end - +`endif {% endblock %} diff --git a/UVM_Framework/UVMF_2022.3/templates/python/template_files/interface_templates/interface_driver_proxy.TMPL b/UVM_Framework/UVMF_2022.3/templates/python/template_files/interface_templates/interface_driver_proxy.TMPL index e940477a..532fcd52 100644 --- a/UVM_Framework/UVMF_2022.3/templates/python/template_files/interface_templates/interface_driver_proxy.TMPL +++ b/UVM_Framework/UVMF_2022.3/templates/python/template_files/interface_templates/interface_driver_proxy.TMPL @@ -13,7 +13,8 @@ //---------------------------------------------------------------------- {% endblock %} {% block contents %} - +`ifndef {{name|upper}}_DRIVER_PROXY +`define {{name|upper}}_DRIVER_PROXY class {{name}}_driver_proxy {%if paramDefs|length > 0%} #( {% for param in paramDefs %} {{param.type}} {{param.name}}{% if param.value != None %} = {{param.value}}{% endif %}{% if not loop.last %},{% endif %} {% endfor %} ) @@ -84,5 +85,5 @@ endclass // pragma uvmf custom external begin // pragma uvmf custom external end - +`endif {% endblock %} diff --git a/UVM_Framework/UVMF_2022.3/templates/python/template_files/interface_templates/interface_ibs_driver.TMPL b/UVM_Framework/UVMF_2022.3/templates/python/template_files/interface_templates/interface_ibs_driver.TMPL index e77d1dc6..faa42348 100644 --- a/UVM_Framework/UVMF_2022.3/templates/python/template_files/interface_templates/interface_ibs_driver.TMPL +++ b/UVM_Framework/UVMF_2022.3/templates/python/template_files/interface_templates/interface_ibs_driver.TMPL @@ -13,8 +13,9 @@ // //---------------------------------------------------------------------- {% endblock %} - {% block contents %} +`ifndef {{name|upper}}_IBS_DRIVER +`define {{name|upper}}_IBS_DRIVER class {{name}}_ibs_driver {{macro.paramDeclare(paramDefs)|indent(8)}} extends {{name}}_driver {{macro.paramUse(paramDefs)|indent(16)}}; {{macro.compUtils([ name,'_ibs_driver']|join(""),paramDefs)}} @@ -81,5 +82,5 @@ endclass // pragma uvmf custom external begin // pragma uvmf custom external end - +`endif {% endblock %} diff --git a/UVM_Framework/UVMF_2022.3/templates/python/template_files/interface_templates/interface_ibs_driver_bfm.TMPL b/UVM_Framework/UVMF_2022.3/templates/python/template_files/interface_templates/interface_ibs_driver_bfm.TMPL index 6eaab02f..60746383 100644 --- a/UVM_Framework/UVMF_2022.3/templates/python/template_files/interface_templates/interface_ibs_driver_bfm.TMPL +++ b/UVM_Framework/UVMF_2022.3/templates/python/template_files/interface_templates/interface_ibs_driver_bfm.TMPL @@ -42,8 +42,9 @@ // //---------------------------------------------------------------------- {% endblock %} - {% block contents %} +`ifndef {{name|upper}}_IBS_DRIVER_BFM +`define {{name|upper}}_IBS_DRIVER_BFM import uvmf_base_pkg_hdl::*; import {{name}}_pkg_hdl::*; {% if not veloceReady %} @@ -431,5 +432,5 @@ endinterface // pragma uvmf custom external begin // pragma uvmf custom external end - +`endif {% endblock %} diff --git a/UVM_Framework/UVMF_2022.3/templates/python/template_files/interface_templates/interface_if.TMPL b/UVM_Framework/UVMF_2022.3/templates/python/template_files/interface_templates/interface_if.TMPL index 95cfb328..e9c7ad3d 100644 --- a/UVM_Framework/UVMF_2022.3/templates/python/template_files/interface_templates/interface_if.TMPL +++ b/UVM_Framework/UVMF_2022.3/templates/python/template_files/interface_templates/interface_if.TMPL @@ -14,8 +14,9 @@ // //---------------------------------------------------------------------- {% endblock %} - {% block contents %} +`ifndef {{name|upper}}_IF +`define {{name|upper}}_IF // This template can be used to connect a DUT to these signals // {% for sig in sigs %} @@ -28,11 +29,11 @@ import {{name}}_pkg_hdl::*; interface {{name}}_if {{macro.paramDeclare(paramDefs)|indent(2)}} ( - input tri {{clock}}, - input tri {{reset}}{% if sigs|length > 0 %},{% endif %} + input logic {{clock}}, + input logic {{reset}}{% if sigs|length > 0 %},{% endif %} {% for sig in sigs %} - inout tri {{sig.vector}} {{sig.name}}{{macro.commalist(loop)}} + {{sig.dir}} logic {{sig.vector}} {{sig.name}}{{macro.commalist(loop)}} {%- endfor %} ); @@ -78,5 +79,5 @@ endinterface // pragma uvmf custom external begin // pragma uvmf custom external end - +`endif {% endblock %} diff --git a/UVM_Framework/UVMF_2022.3/templates/python/template_files/interface_templates/interface_if_mtlb.TMPL b/UVM_Framework/UVMF_2022.3/templates/python/template_files/interface_templates/interface_if_mtlb.TMPL index 5b3a6939..313e3d31 100644 --- a/UVM_Framework/UVMF_2022.3/templates/python/template_files/interface_templates/interface_if_mtlb.TMPL +++ b/UVM_Framework/UVMF_2022.3/templates/python/template_files/interface_templates/interface_if_mtlb.TMPL @@ -18,8 +18,9 @@ // //---------------------------------------------------------------------- {% endblock %} - {% block contents %} +`ifndef {{name|upper}}_IF_MATLAB +`define {{name|upper}}_IF_MATLAB // This template can be used to connect a DUT to these signals // {% for sig in sigs %} @@ -82,5 +83,5 @@ endinterface // pragma uvmf custom external begin // pragma uvmf custom external end - +`endif {% endblock %} diff --git a/UVM_Framework/UVMF_2022.3/templates/python/template_files/interface_templates/interface_infact_sequence.TMPL b/UVM_Framework/UVMF_2022.3/templates/python/template_files/interface_templates/interface_infact_sequence.TMPL index 1863cd80..01ef248d 100644 --- a/UVM_Framework/UVMF_2022.3/templates/python/template_files/interface_templates/interface_infact_sequence.TMPL +++ b/UVM_Framework/UVMF_2022.3/templates/python/template_files/interface_templates/interface_infact_sequence.TMPL @@ -12,6 +12,8 @@ //---------------------------------------------------------------------- {% endblock %} {% block contents %} +`ifndef {{name|upper}}_INFACT_SEQUENCE +`define {{name|upper}}_INFACT_SEQUENCE class {{name}}_infact_sequence {%if paramDefs|length > 0%} #( {% for param in paramDefs %} {{param.type}} {{param.name}}{% if param.value != None %} = {{param.value}}{% endif %}{% if not loop.last %},{% endif %} {% endfor %} ) {% endif %} @@ -40,5 +42,5 @@ endclass: {{name}}_infact_sequence // pragma uvmf custom external begin // pragma uvmf custom external end - +`endif {% endblock %} diff --git a/UVM_Framework/UVMF_2022.3/templates/python/template_files/interface_templates/interface_monitor.TMPL b/UVM_Framework/UVMF_2022.3/templates/python/template_files/interface_templates/interface_monitor.TMPL index 1859f0d7..235a69a4 100644 --- a/UVM_Framework/UVMF_2022.3/templates/python/template_files/interface_templates/interface_monitor.TMPL +++ b/UVM_Framework/UVMF_2022.3/templates/python/template_files/interface_templates/interface_monitor.TMPL @@ -13,8 +13,9 @@ // //---------------------------------------------------------------------- {% endblock %} - {% block contents %} +`ifndef {{name|upper}}_MONITOR +`define {{name|upper}}_MONITOR class {{name}}_monitor {{macro.paramDeclare(paramDefs)|indent(6)}} extends uvmf_monitor_base #( .CONFIG_T({{name}}_configuration {{macro.paramUse(paramDefs)|indent(29)}}), .BFM_BIND_T({%if useDpiLink %}{{name}}_monitor_proxy {% else %}virtual {{name}}_monitor_bfm {% endif %} {{macro.paramUse(paramDefs)|indent(29)}}), @@ -102,5 +103,5 @@ endclass // pragma uvmf custom external begin // pragma uvmf custom external end - +`endif {% endblock %} diff --git a/UVM_Framework/UVMF_2022.3/templates/python/template_files/interface_templates/interface_monitor_bfm.TMPL b/UVM_Framework/UVMF_2022.3/templates/python/template_files/interface_templates/interface_monitor_bfm.TMPL index c346a492..5469bd80 100644 --- a/UVM_Framework/UVMF_2022.3/templates/python/template_files/interface_templates/interface_monitor_bfm.TMPL +++ b/UVM_Framework/UVMF_2022.3/templates/python/template_files/interface_templates/interface_monitor_bfm.TMPL @@ -25,8 +25,9 @@ // //---------------------------------------------------------------------- {% endblock %} - {% block contents %} +`ifndef {{name|upper}}_MONITOR_BFM +`define {{name|upper}}_MONITOR_BFM import uvmf_base_pkg_hdl::*; import {{name}}_pkg_hdl::*; {% if veloceReady %} @@ -87,8 +88,8 @@ end {{config.type}} {{config.name}} {{config.unpackedDim}}; {% endfor %} - tri {{clock}}_i; - tri {{reset}}_i; + logic {{clock}}_i; + logic {{reset}}_i; {% for sig in sigs %} tri {{sig.vector}} {{sig.name}}_i; {% endfor %} @@ -270,5 +271,5 @@ endinterface // pragma uvmf custom external begin // pragma uvmf custom external end - +`endif {% endblock %} diff --git a/UVM_Framework/UVMF_2022.3/templates/python/template_files/interface_templates/interface_monitor_bfm_mtlb.TMPL b/UVM_Framework/UVMF_2022.3/templates/python/template_files/interface_templates/interface_monitor_bfm_mtlb.TMPL index bfaff838..bd648a1d 100644 --- a/UVM_Framework/UVMF_2022.3/templates/python/template_files/interface_templates/interface_monitor_bfm_mtlb.TMPL +++ b/UVM_Framework/UVMF_2022.3/templates/python/template_files/interface_templates/interface_monitor_bfm_mtlb.TMPL @@ -29,8 +29,9 @@ // //---------------------------------------------------------------------- {% endblock %} - {% block contents %} +`ifndef {{name|upper}}_MONITOR_BFM +`define {{name|upper}}_MONITOR_BFM import uvmf_base_pkg_hdl::*; import {{name}}_pkg_hdl::*; {% if veloceReady %} @@ -262,5 +263,5 @@ endinterface // pragma uvmf custom external begin // pragma uvmf custom external end - +`endif {% endblock %} diff --git a/UVM_Framework/UVMF_2022.3/templates/python/template_files/interface_templates/interface_monitor_proxy.TMPL b/UVM_Framework/UVMF_2022.3/templates/python/template_files/interface_templates/interface_monitor_proxy.TMPL index ca93ccc4..9e955953 100644 --- a/UVM_Framework/UVMF_2022.3/templates/python/template_files/interface_templates/interface_monitor_proxy.TMPL +++ b/UVM_Framework/UVMF_2022.3/templates/python/template_files/interface_templates/interface_monitor_proxy.TMPL @@ -12,8 +12,10 @@ // //---------------------------------------------------------------------- {% endblock %} -{% block contents %} +{% block contents %} +`ifndef {{name|upper}}_MONITOR_PROXY +`define {{name|upper}}_MONITOR_PROXY typedef class {{name}}_monitor; class {{name}}_monitor_proxy {%if paramDefs|length > 0%} #( @@ -79,5 +81,5 @@ endclass // pragma uvmf custom external begin // pragma uvmf custom external end - +`endif {% endblock %} diff --git a/UVM_Framework/UVMF_2022.3/templates/python/template_files/interface_templates/interface_pkg.TMPL b/UVM_Framework/UVMF_2022.3/templates/python/template_files/interface_templates/interface_pkg.TMPL index fe553a72..5f44e11e 100644 --- a/UVM_Framework/UVMF_2022.3/templates/python/template_files/interface_templates/interface_pkg.TMPL +++ b/UVM_Framework/UVMF_2022.3/templates/python/template_files/interface_templates/interface_pkg.TMPL @@ -27,6 +27,8 @@ {% endblock %} {% block contents %} +`ifndef {{name|upper}}_PKG +`define {{name|upper}}_PKG package {{name}}_pkg; import uvm_pkg::*; @@ -107,5 +109,5 @@ endpackage // pragma uvmf custom external begin // pragma uvmf custom external end - +`endif {% endblock %} diff --git a/UVM_Framework/UVMF_2022.3/templates/python/template_files/interface_templates/interface_pkg_hdl.TMPL b/UVM_Framework/UVMF_2022.3/templates/python/template_files/interface_templates/interface_pkg_hdl.TMPL index ca1ee886..74ff87e7 100644 --- a/UVM_Framework/UVMF_2022.3/templates/python/template_files/interface_templates/interface_pkg_hdl.TMPL +++ b/UVM_Framework/UVMF_2022.3/templates/python/template_files/interface_templates/interface_pkg_hdl.TMPL @@ -15,6 +15,8 @@ {% endblock %} {% block contents %} +`ifndef {{name|upper}}_PKG_HDL +`define {{name|upper}}_PKG_HDL package {{name}}_pkg_hdl; import uvmf_base_pkg_hdl::*; @@ -37,5 +39,5 @@ endpackage // pragma uvmf custom external begin // pragma uvmf custom external end - +`endif {% endblock %} diff --git a/UVM_Framework/UVMF_2022.3/templates/python/template_files/interface_templates/interface_pkg_mtlb.TMPL b/UVM_Framework/UVMF_2022.3/templates/python/template_files/interface_templates/interface_pkg_mtlb.TMPL index 263538ec..60eea29e 100644 --- a/UVM_Framework/UVMF_2022.3/templates/python/template_files/interface_templates/interface_pkg_mtlb.TMPL +++ b/UVM_Framework/UVMF_2022.3/templates/python/template_files/interface_templates/interface_pkg_mtlb.TMPL @@ -33,6 +33,8 @@ {% endblock %} {% block contents %} +`ifndef {{name|upper}}_PKG_MATLAB +`define {{name|upper}}_PKG_MATLAB package {{name}}_pkg; import uvm_pkg::*; @@ -114,5 +116,5 @@ endpackage // pragma uvmf custom external begin // pragma uvmf custom external end - +`endif {% endblock %} diff --git a/UVM_Framework/UVMF_2022.3/templates/python/template_files/interface_templates/interface_random_sequence.TMPL b/UVM_Framework/UVMF_2022.3/templates/python/template_files/interface_templates/interface_random_sequence.TMPL index a29a0208..3e67eb05 100644 --- a/UVM_Framework/UVMF_2022.3/templates/python/template_files/interface_templates/interface_random_sequence.TMPL +++ b/UVM_Framework/UVMF_2022.3/templates/python/template_files/interface_templates/interface_random_sequence.TMPL @@ -13,6 +13,8 @@ //---------------------------------------------------------------------- {% endblock %} {% block contents %} +`ifndef {{name|upper}}_RANDOM_SEQUENCE +`define {{name|upper}}_RANDOM_SEQUENCE class {{name}}_random_sequence {{macro.paramDeclare(paramDefs)|indent(6)}} extends {{name}}_sequence_base {{macro.paramUse(paramDefs)|indent(6)}}; @@ -48,5 +50,5 @@ endclass: {{name}}_random_sequence // pragma uvmf custom external begin // pragma uvmf custom external end - +`endif {% endblock %} diff --git a/UVM_Framework/UVMF_2022.3/templates/python/template_files/interface_templates/interface_read_from_file_sequence_mtlb.TMPL b/UVM_Framework/UVMF_2022.3/templates/python/template_files/interface_templates/interface_read_from_file_sequence_mtlb.TMPL index b2ab1f25..956e6c56 100755 --- a/UVM_Framework/UVMF_2022.3/templates/python/template_files/interface_templates/interface_read_from_file_sequence_mtlb.TMPL +++ b/UVM_Framework/UVMF_2022.3/templates/python/template_files/interface_templates/interface_read_from_file_sequence_mtlb.TMPL @@ -19,6 +19,8 @@ // **************************************************************************** // This sequence constructs a {{name}}_transaction and uses file input to create stimulus values. // +`ifndef {{name|upper}}_READ_FROM_FILE_SEQUENCE +`define {{name|upper}}_READ_FROM_FILE_SEQUENCE class {{name}}_read_from_file_sequence {%if paramDefs|length > 0%} #( {% for param in paramDefs %} {{param.type}} {{param.name}} = {{param.value}}{% if not loop.last %},{% endif %} {% endfor %} ) @@ -109,5 +111,5 @@ endclass: {{name}}_read_from_file_sequence // pragma uvmf custom external begin // pragma uvmf custom external end - +`endif {% endblock %} diff --git a/UVM_Framework/UVMF_2022.3/templates/python/template_files/interface_templates/interface_reg_adapter.TMPL b/UVM_Framework/UVMF_2022.3/templates/python/template_files/interface_templates/interface_reg_adapter.TMPL index f58105d6..1d5334c1 100644 --- a/UVM_Framework/UVMF_2022.3/templates/python/template_files/interface_templates/interface_reg_adapter.TMPL +++ b/UVM_Framework/UVMF_2022.3/templates/python/template_files/interface_templates/interface_reg_adapter.TMPL @@ -10,6 +10,8 @@ //---------------------------------------------------------------------- {% endblock %} {% block contents %} +`ifndef {{name|upper}}2REG_ADAPTER +`define {{name|upper}}2REG_ADAPTER class {{name}}2reg_adapter {{macro.paramDeclare(paramDefs)|indent(6)}} extends uvm_reg_adapter; {{macro.objUtils([name,'2reg_adapter']|join(""),paramDefs)}} @@ -93,5 +95,5 @@ endclass : {{name}}2reg_adapter // pragma uvmf custom external begin // pragma uvmf custom external end - +`endif {% endblock %} diff --git a/UVM_Framework/UVMF_2022.3/templates/python/template_files/interface_templates/interface_responder_sequence.TMPL b/UVM_Framework/UVMF_2022.3/templates/python/template_files/interface_templates/interface_responder_sequence.TMPL index 87b35700..0678a8a3 100644 --- a/UVM_Framework/UVMF_2022.3/templates/python/template_files/interface_templates/interface_responder_sequence.TMPL +++ b/UVM_Framework/UVMF_2022.3/templates/python/template_files/interface_templates/interface_responder_sequence.TMPL @@ -13,6 +13,8 @@ {% endblock %} {% block contents %} +`ifndef {{name|upper}}_RESPONDER_SEQUENCE +`define {{name|upper}}_RESPONDER_SEQUENCE class {{name}}_responder_sequence {{macro.paramDeclare(paramDefs)|indent(6)}} extends {{name}}_sequence_base {{macro.paramUse(paramDefs)|indent(6)}}; @@ -45,5 +47,5 @@ endclass // pragma uvmf custom external begin // pragma uvmf custom external end - +`endif {% endblock %} diff --git a/UVM_Framework/UVMF_2022.3/templates/python/template_files/interface_templates/interface_sequence_base.TMPL b/UVM_Framework/UVMF_2022.3/templates/python/template_files/interface_templates/interface_sequence_base.TMPL index ce8f1591..a6e0aeb1 100644 --- a/UVM_Framework/UVMF_2022.3/templates/python/template_files/interface_templates/interface_sequence_base.TMPL +++ b/UVM_Framework/UVMF_2022.3/templates/python/template_files/interface_templates/interface_sequence_base.TMPL @@ -11,6 +11,8 @@ //---------------------------------------------------------------------- {% endblock %} {% block contents %} +`ifndef {{name|upper}}_SEQUENCE_BASE +`define {{name|upper}}_SEQUENCE_BASE class {{name}}_sequence_base {{macro.paramDeclare(paramDefs)|indent(6)}} extends uvmf_sequence_base #( .REQ({{name}}_transaction {{macro.paramUse(paramDefs)|indent(33)}}), .RSP({{name}}_transaction {{macro.paramUse(paramDefs)|indent(33)}})); @@ -108,5 +110,5 @@ endclass // pragma uvmf custom external begin // pragma uvmf custom external end - +`endif {% endblock %} diff --git a/UVM_Framework/UVMF_2022.3/templates/python/template_files/interface_templates/interface_sequence_base_mtlb.TMPL b/UVM_Framework/UVMF_2022.3/templates/python/template_files/interface_templates/interface_sequence_base_mtlb.TMPL index 6e3527fa..be1f0f66 100644 --- a/UVM_Framework/UVMF_2022.3/templates/python/template_files/interface_templates/interface_sequence_base_mtlb.TMPL +++ b/UVM_Framework/UVMF_2022.3/templates/python/template_files/interface_templates/interface_sequence_base_mtlb.TMPL @@ -12,6 +12,8 @@ //---------------------------------------------------------------------- {% endblock %} {% block contents %} +`ifndef {{name|upper}}_SEQUENCE_BASE_MATLAB +`define {{name|upper}}_SEQUENCE_BASE_MATLAB class {{name}}_sequence_base {{macro.paramDeclare(paramDefs)|indent(6)}} extends uvmf_sequence_base #( .REQ({{name}}_transaction {{macro.paramUse(paramDefs)|indent(33)}}), .RSP({{name}}_transaction {{macro.paramUse(paramDefs)|indent(33)}})); @@ -88,5 +90,5 @@ endclass // pragma uvmf custom external begin // pragma uvmf custom external end - +`endif {% endblock %} diff --git a/UVM_Framework/UVMF_2022.3/templates/python/template_files/interface_templates/interface_tc_cpp.TMPL b/UVM_Framework/UVMF_2022.3/templates/python/template_files/interface_templates/interface_tc_cpp.TMPL index 0dee5fcb..cfd82ef0 100644 --- a/UVM_Framework/UVMF_2022.3/templates/python/template_files/interface_templates/interface_tc_cpp.TMPL +++ b/UVM_Framework/UVMF_2022.3/templates/python/template_files/interface_templates/interface_tc_cpp.TMPL @@ -19,7 +19,8 @@ */ {% endblock %} {% block contents %} - +`ifndef {{name|upper}}_INTERFACE_TC_CPP +`define {{name|upper}}_INTERFACE_TC_CPP #include "dpiheader.h" #include "dpi_link.h" // pragma uvmf custom header begin @@ -42,5 +43,5 @@ extern "C" { // pragma uvmf custom additional begin // pragma uvmf custom additional end - +`endif {% endblock %} diff --git a/UVM_Framework/UVMF_2022.3/templates/python/template_files/interface_templates/interface_transaction.TMPL b/UVM_Framework/UVMF_2022.3/templates/python/template_files/interface_templates/interface_transaction.TMPL index 6bb1a12f..55da1b03 100755 --- a/UVM_Framework/UVMF_2022.3/templates/python/template_files/interface_templates/interface_transaction.TMPL +++ b/UVM_Framework/UVMF_2022.3/templates/python/template_files/interface_templates/interface_transaction.TMPL @@ -13,6 +13,8 @@ {% endblock %} {% block contents %} +`ifndef {{name|upper}}_TRANSACTION +`define {{name|upper}}_TRANSACTION class {{name}}_transaction {{macro.paramDeclare(paramDefs)|indent(6)}} extends uvmf_transaction_base; {{macro.objUtils([name,'_transaction']|join(""),paramDefs)}} @@ -193,5 +195,5 @@ endclass // pragma uvmf custom external begin // pragma uvmf custom external end - +`endif {% endblock %} diff --git a/UVM_Framework/UVMF_2022.3/templates/python/template_files/interface_templates/interface_transaction_coverage.TMPL b/UVM_Framework/UVMF_2022.3/templates/python/template_files/interface_templates/interface_transaction_coverage.TMPL index ffa70f2d..d446f66b 100644 --- a/UVM_Framework/UVMF_2022.3/templates/python/template_files/interface_templates/interface_transaction_coverage.TMPL +++ b/UVM_Framework/UVMF_2022.3/templates/python/template_files/interface_templates/interface_transaction_coverage.TMPL @@ -13,6 +13,8 @@ {% endblock %} {% block contents %} +`ifndef {{name|upper}}_TRANSACTION_COVERAGE +`define {{name|upper}}_TRANSACTION_COVERAGE class {{name}}_transaction_coverage {{macro.paramDeclare(paramDefs)|indent(6)}} extends uvm_subscriber #(.T({{name}}_transaction {{macro.paramUse(paramDefs)|indent(44)}})); {{macro.compUtils([name,'_transaction_coverage']|join(""),paramDefs)}} @@ -69,4 +71,5 @@ endclass // pragma uvmf custom external begin // pragma uvmf custom external end +`endif {% endblock %} diff --git a/UVM_Framework/UVMF_2022.3/templates/python/template_files/interface_templates/interface_transaction_coverage_mtlb.TMPL b/UVM_Framework/UVMF_2022.3/templates/python/template_files/interface_templates/interface_transaction_coverage_mtlb.TMPL index cec3b6d5..713b9659 100644 --- a/UVM_Framework/UVMF_2022.3/templates/python/template_files/interface_templates/interface_transaction_coverage_mtlb.TMPL +++ b/UVM_Framework/UVMF_2022.3/templates/python/template_files/interface_templates/interface_transaction_coverage_mtlb.TMPL @@ -17,6 +17,8 @@ {% endblock %} {% block contents %} +`ifndef {{name|upper}}_TRANSACTION_COVERAGE_MATLAB +`define {{name|upper}}_TRANSACTION_COVERAGE_MATLAB class {{name}}_transaction_coverage {{macro.paramDeclare(paramDefs)|indent(6)}} extends uvm_subscriber #(.T({{name}}_transaction {{macro.paramUse(paramDefs)|indent(44)}})); {{macro.compUtils([name,'_transaction_coverage']|join(""),paramDefs)}} @@ -72,5 +74,5 @@ endclass // pragma uvmf custom external begin // pragma uvmf custom external end - +`endif {% endblock %} diff --git a/UVM_Framework/UVMF_2022.3/templates/python/template_files/interface_templates/interface_transaction_mtlb.TMPL b/UVM_Framework/UVMF_2022.3/templates/python/template_files/interface_templates/interface_transaction_mtlb.TMPL index 5bc40959..f0c0ccdb 100755 --- a/UVM_Framework/UVMF_2022.3/templates/python/template_files/interface_templates/interface_transaction_mtlb.TMPL +++ b/UVM_Framework/UVMF_2022.3/templates/python/template_files/interface_templates/interface_transaction_mtlb.TMPL @@ -17,6 +17,8 @@ {% endblock %} {% block contents %} +`ifndef {{name|upper}}_TRANSACTION_MATLAB +`define {{name|upper}}_TRANSACTION_MATLAB class {{name}}_transaction {{macro.paramDeclare(paramDefs)|indent(6)}} extends uvmf_transaction_base; {{macro.objUtils([name,'_transaction']|join(""),paramDefs)}} @@ -191,4 +193,5 @@ endclass // pragma uvmf custom external begin // pragma uvmf custom external end +`endif {% endblock %} diff --git a/UVM_Framework/UVMF_2022.3/templates/python/template_files/interface_templates/interface_typedefs.TMPL b/UVM_Framework/UVMF_2022.3/templates/python/template_files/interface_templates/interface_typedefs.TMPL index 0dc1ea03..487cd6bb 100644 --- a/UVM_Framework/UVMF_2022.3/templates/python/template_files/interface_templates/interface_typedefs.TMPL +++ b/UVM_Framework/UVMF_2022.3/templates/python/template_files/interface_templates/interface_typedefs.TMPL @@ -13,13 +13,14 @@ {% block contents %} - +`ifndef TYPEDEFS_HVL +`definr TYPEDEFS_HVL {% for types in hvlTypedefs %} typedef {{types.type}} {{types.name}}; {% endfor %} // pragma uvmf custom additional begin // pragma uvmf custom additional end - +`endif {% endblock %} ~ diff --git a/UVM_Framework/UVMF_2022.3/templates/python/template_files/interface_templates/interface_typedefs_hdl.TMPL b/UVM_Framework/UVMF_2022.3/templates/python/template_files/interface_templates/interface_typedefs_hdl.TMPL index 5dcc2df2..92c1bb70 100644 --- a/UVM_Framework/UVMF_2022.3/templates/python/template_files/interface_templates/interface_typedefs_hdl.TMPL +++ b/UVM_Framework/UVMF_2022.3/templates/python/template_files/interface_templates/interface_typedefs_hdl.TMPL @@ -13,6 +13,8 @@ {% block contents %} +`ifndef TYPEDEFS_HVL +`definr TYPEDEFS_HVL {% for types in hdlTypedefs %} typedef {{types.type}} {{types.name}}; @@ -20,5 +22,5 @@ typedef {{types.type}} {{types.name}}; // pragma uvmf custom additional begin // pragma uvmf custom additional end - +`endif {% endblock %} diff --git a/UVM_Framework/UVMF_2022.3/templates/python/uvmf_gen.pyc b/UVM_Framework/UVMF_2022.3/templates/python/uvmf_gen.pyc new file mode 100644 index 00000000..197e0ba0 Binary files /dev/null and b/UVM_Framework/UVMF_2022.3/templates/python/uvmf_gen.pyc differ diff --git a/UVM_Framework/UVMF_2022.3/templates/python/uvmf_version.pyc b/UVM_Framework/UVMF_2022.3/templates/python/uvmf_version.pyc new file mode 100644 index 00000000..e54b1108 Binary files /dev/null and b/UVM_Framework/UVMF_2022.3/templates/python/uvmf_version.pyc differ diff --git a/UVM_Framework/UVMF_2022.3/templates/python/uvmf_yaml/__init__.pyc b/UVM_Framework/UVMF_2022.3/templates/python/uvmf_yaml/__init__.pyc new file mode 100644 index 00000000..efb7e9cd Binary files /dev/null and b/UVM_Framework/UVMF_2022.3/templates/python/uvmf_yaml/__init__.pyc differ diff --git a/UVM_Framework/UVMF_2022.3/templates/python/uvmf_yaml/backup.pyc b/UVM_Framework/UVMF_2022.3/templates/python/uvmf_yaml/backup.pyc new file mode 100644 index 00000000..5d1e45c3 Binary files /dev/null and b/UVM_Framework/UVMF_2022.3/templates/python/uvmf_yaml/backup.pyc differ diff --git a/UVM_Framework/UVMF_2022.3/templates/python/uvmf_yaml/dumper.pyc b/UVM_Framework/UVMF_2022.3/templates/python/uvmf_yaml/dumper.pyc new file mode 100644 index 00000000..269546a4 Binary files /dev/null and b/UVM_Framework/UVMF_2022.3/templates/python/uvmf_yaml/dumper.pyc differ diff --git a/UVM_Framework/UVMF_2022.3/templates/python/uvmf_yaml/regen.pyc b/UVM_Framework/UVMF_2022.3/templates/python/uvmf_yaml/regen.pyc new file mode 100644 index 00000000..a42a978a Binary files /dev/null and b/UVM_Framework/UVMF_2022.3/templates/python/uvmf_yaml/regen.pyc differ diff --git a/UVM_Framework/UVMF_2022.3/templates/python/uvmf_yaml/validator.pyc b/UVM_Framework/UVMF_2022.3/templates/python/uvmf_yaml/validator.pyc new file mode 100644 index 00000000..dee26d7c Binary files /dev/null and b/UVM_Framework/UVMF_2022.3/templates/python/uvmf_yaml/validator.pyc differ diff --git a/UVM_Framework/UVMF_2022.3/templates/python/voluptuous/__init__.pyc b/UVM_Framework/UVMF_2022.3/templates/python/voluptuous/__init__.pyc new file mode 100644 index 00000000..8b9d7ce8 Binary files /dev/null and b/UVM_Framework/UVMF_2022.3/templates/python/voluptuous/__init__.pyc differ diff --git a/UVM_Framework/UVMF_2022.3/templates/python/voluptuous/error.pyc b/UVM_Framework/UVMF_2022.3/templates/python/voluptuous/error.pyc new file mode 100644 index 00000000..43db0461 Binary files /dev/null and b/UVM_Framework/UVMF_2022.3/templates/python/voluptuous/error.pyc differ diff --git a/UVM_Framework/UVMF_2022.3/templates/python/voluptuous/humanize.pyc b/UVM_Framework/UVMF_2022.3/templates/python/voluptuous/humanize.pyc new file mode 100644 index 00000000..84b96e97 Binary files /dev/null and b/UVM_Framework/UVMF_2022.3/templates/python/voluptuous/humanize.pyc differ diff --git a/UVM_Framework/UVMF_2022.3/templates/python/voluptuous/schema_builder.pyc b/UVM_Framework/UVMF_2022.3/templates/python/voluptuous/schema_builder.pyc new file mode 100644 index 00000000..e7d3923b Binary files /dev/null and b/UVM_Framework/UVMF_2022.3/templates/python/voluptuous/schema_builder.pyc differ diff --git a/UVM_Framework/UVMF_2022.3/templates/python/voluptuous/util.pyc b/UVM_Framework/UVMF_2022.3/templates/python/voluptuous/util.pyc new file mode 100644 index 00000000..c7ddbb22 Binary files /dev/null and b/UVM_Framework/UVMF_2022.3/templates/python/voluptuous/util.pyc differ diff --git a/UVM_Framework/UVMF_2022.3/templates/python/voluptuous/validators.pyc b/UVM_Framework/UVMF_2022.3/templates/python/voluptuous/validators.pyc new file mode 100644 index 00000000..5b735ffd Binary files /dev/null and b/UVM_Framework/UVMF_2022.3/templates/python/voluptuous/validators.pyc differ