diff --git a/UVM_Framework/UVMF_2022.3/adder_test_cases/fixed_sequence.sv b/UVM_Framework/UVMF_2022.3/adder_test_cases/fixed_sequence.sv new file mode 100644 index 00000000..81b6460a --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/adder_test_cases/fixed_sequence.sv @@ -0,0 +1,17 @@ +class add_in_fixed extends add_in_sequence_base; + + function new(string name = "add_in_fixed"); + super.new(name); + endfunction: new + + task body(); + req=add_in_transaction ::type_id::create("req"); + start_item(req); + if(!req.randomize()) `uvm_fatal("SEQ", "add_in_fixed randomization failed") + req.a=5; + req.b=6; + finish_item(req); + `uvm_info("SEQ", {"Response:",req.convert2string()},UVM_MEDIUM) + + endtask +endclass diff --git a/UVM_Framework/UVMF_2022.3/adder_test_cases/fixed_test.sv b/UVM_Framework/UVMF_2022.3/adder_test_cases/fixed_test.sv new file mode 100644 index 00000000..a7fb0e59 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/adder_test_cases/fixed_test.sv @@ -0,0 +1,16 @@ +`include "uvm_macros.svh" + +class add_fixed_test extends test_top; + + `uvm_component_utils(add_fixed_test) + + function new(string name = "add_fixed_test", uvm_component parent = null ); + super.new(name, parent); + endfunction : new + + virtual function void build_phase(uvm_phase phase ); + add_bench_sequence_base::type_id::set_type_override(add_fixed_sequence::get_type()); + super.build_phase(phase); + endfunction : build_phase + +endclass : add_fixed_test diff --git a/UVM_Framework/UVMF_2022.3/adder_test_cases/random_sequence.sv b/UVM_Framework/UVMF_2022.3/adder_test_cases/random_sequence.sv new file mode 100644 index 00000000..d5b22d11 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/adder_test_cases/random_sequence.sv @@ -0,0 +1,23 @@ +`include "uvm_macros.svh" + +class add_random_sequence extends add_bench_sequence_base; + + `uvm_object_utils(add_random_sequence) + + function new(string name = "add_random_sequence"); + super.new(name); + endfunction : new + + virtual task body(); + add_random_seq = add_random_sequence#()::type_id::create("add_agent_random_seq"); + + add_agent_config.wait_for_reset(); + add_agent_config.wait_for_num_clocks(10); + + repeat (10) add_agent_random_seq.start(add_agent_sequencer); + + add_agent_config.wait_for_num_clocks(10); + +endtask + +endclass : ALU_random_sequence diff --git a/UVM_Framework/UVMF_2022.3/adder_test_cases/random_test.sv b/UVM_Framework/UVMF_2022.3/adder_test_cases/random_test.sv new file mode 100644 index 00000000..9c1422e9 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/adder_test_cases/random_test.sv @@ -0,0 +1,16 @@ +`include "uvm_macros.svh" + +class add_random_test extends test_top; + + `uvm_component_utils(add_random_test) + + function new(string name = "add_random_test", uvm_component parent = null ); + super.new(name, parent); + endfunction : new + + virtual function void build_phase(uvm_phase phase ); + add_bench_sequence_base::type_id::set_type_override(add_random_sequence::get_type()); + super.build_phase(phase); + endfunction : build_phase + +endclass : add_random_test diff --git a/UVM_Framework/UVMF_2022.3/adder_test_cases/reset_sequence.sv b/UVM_Framework/UVMF_2022.3/adder_test_cases/reset_sequence.sv new file mode 100644 index 00000000..436bd7ea --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/adder_test_cases/reset_sequence.sv @@ -0,0 +1,17 @@ +class add_in_reset_sequence extends add_in_sequence_base; + + function new(string name = "add_reset_sequence"); + super.new(name); + endfunction: new + + task body(); + req=add_in_transaction ::type_id::create("req"); + start_item(req); + if(!req.randomize()) `uvm_fatal("SEQ", "add_in_reset_sequence::body()-add_transaction randomization failed") + // req.reset=1; + req.op = rst_op; + finish_item(req); + `uvm_info("SEQ", {"Response:",req.convert2string()},UVM_MEDIUM) + + endtask +endclass diff --git a/UVM_Framework/UVMF_2022.3/adder_test_cases/sequence_1.sv b/UVM_Framework/UVMF_2022.3/adder_test_cases/sequence_1.sv new file mode 100644 index 00000000..8f2ce32c --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/adder_test_cases/sequence_1.sv @@ -0,0 +1,21 @@ +`include "uvm_macros.svh" + +class sequence_1_reset extends add_bench_sequence_base; + + + `uvm_object_utils(sequence_1_reset) + + typedef add_in_reset_sequence add_in_reset_sequence_t; + add_in_reset_sequence_t add_in_reset_s; + + function new(string name="sequence_1_reset"); + super.new(name); + endfunction + + virtual task body(); + add_in_reset_s = add_in_reset_sequence#() ::type_id::create("add_in_reset_s"); + + add_in_reset_s.start(add_in_agent_sequencer); + endtask + +endclass diff --git a/UVM_Framework/UVMF_2022.3/adder_test_cases/sequence_2.sv b/UVM_Framework/UVMF_2022.3/adder_test_cases/sequence_2.sv new file mode 100644 index 00000000..45ec29d4 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/adder_test_cases/sequence_2.sv @@ -0,0 +1,23 @@ +`include "uvm_macros.svh" + +class sequence_2_fixed extends add_bench_sequence_base; + + + `uvm_object_utils(sequence_2_fixed) + + typedef add_in_reset_sequence add_in_reset_sequence_t; + add_in_reset_sequence_t add_in_reset_s; + + function new(string name="sequence_2_fixed"); + super.new(name); + endfunction + + virtual task body(); + add_in_reset_s = add_in_reset_sequence#() ::type_id::create("add_in_reset_s"); + add_in_fixed = add_in_fixed_sequence#() ::type_id::create("add_in_reset_s"); + + add_in_reset_s.start(add_in_agent_sequencer); + add_in_fixed.start(add_in_agent_sequencer); + endtask + +endclass diff --git a/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/project_benches/jtag/.project b/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/project_benches/jtag/.project new file mode 100644 index 00000000..8669c089 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/project_benches/jtag/.project @@ -0,0 +1,37 @@ + + + jtag + + + + + + org.python.pydev.PyDevBuilder + + + + + net.sf.sveditor.core.SVProjectBuilder + + + + + + net.sf.sveditor.core.SVNature + org.python.pydev.pythonNature + + + + verification_ip + 2 + UVMF_VIP_LIBRARY_HOME + + + + + UVMF_VIP_LIBRARY_HOME + $%7BPARENT-2-PROJECT_LOC%7D/verification_ip + + + + diff --git a/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/project_benches/jtag/.svproject b/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/project_benches/jtag/.svproject new file mode 100644 index 00000000..d5250ea5 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/project_benches/jtag/.svproject @@ -0,0 +1,16 @@ + + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/project_benches/jtag/docs/interfaces.csv b/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/project_benches/jtag/docs/interfaces.csv new file mode 100644 index 00000000..f31b9cf5 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/project_benches/jtag/docs/interfaces.csv @@ -0,0 +1,14 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// + +, +Interface Description, Interface Type, Interface Transaction, Interface Name, +jtag_in, jtag_driver_bfm jtag_monitor_bfm, jtag_transaction, jtag_pkg_jtag_in_BFM, +jtag_out, jtag_driver_bfm jtag_monitor_bfm, jtag_transaction, jtag_pkg_jtag_out_BFM, + diff --git a/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/project_benches/jtag/jtag_sve.F b/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/project_benches/jtag/jtag_sve.F new file mode 100644 index 00000000..cd7aee30 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/project_benches/jtag/jtag_sve.F @@ -0,0 +1,27 @@ + +// UVM ++incdir+${UVM_HOME}/src +${UVM_HOME}/src/uvm_pkg.sv + +// Common UVMF files +-f ${UVMF_HOME}/common/common_sve.f + +// BFM Files +-F ${UVMF_VIP_LIBRARY_HOME}/interface_packages/jtag_pkg/jtag_pkg_sve.F + +// Environment Files +-F ${UVMF_VIP_LIBRARY_HOME}/environment_packages/jtag_env_pkg/jtag_env_pkg_sve.F + +// Bench Files ++incdir+./tb/tests +./tb/tests/jtag_tests_pkg.sv + ++incdir+./tb/sequences +./tb/sequences/jtag_sequences_pkg.sv + ++incdir+./tb/parameters +./tb/parameters/jtag_parameters_pkg.sv + +./tb/testbench/hdl_top.sv +./tb/testbench/hvl_top.sv + diff --git a/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/project_benches/jtag/rtl/dut.compile b/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/project_benches/jtag/rtl/dut.compile new file mode 100644 index 00000000..9b0008fc --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/project_benches/jtag/rtl/dut.compile @@ -0,0 +1,6 @@ + +# pragma uvmf custom dut_compile_info begin +src: + - ./vhdl/vhdl_dut.vhd + - ./verilog/verilog_dut.v +# pragma uvmf custom dut_compile_info end diff --git a/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/project_benches/jtag/rtl/verilog/verilog_dut.v b/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/project_benches/jtag/rtl/verilog/verilog_dut.v new file mode 100644 index 00000000..96198441 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/project_benches/jtag/rtl/verilog/verilog_dut.v @@ -0,0 +1,21 @@ +module verilog_dut(clk, rst, in_signal, out_signal); + +input clk; +input rst; +input in_signal; +output out_signal; + +reg out_signal_o; + +always @(posedge clk) begin + if (rst) begin + out_signal_o <= 0; + end + else begin + out_signal_o <= ~in_signal; + end + end + +assign out_signal = out_signal_o; + +endmodule diff --git a/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/project_benches/jtag/rtl/verilog/verilog_dut.vinfo b/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/project_benches/jtag/rtl/verilog/verilog_dut.vinfo new file mode 100644 index 00000000..87e95f36 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/project_benches/jtag/rtl/verilog/verilog_dut.vinfo @@ -0,0 +1 @@ +verilog_dut.v diff --git a/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/project_benches/jtag/rtl/vhdl/vhdl_dut.vhd b/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/project_benches/jtag/rtl/vhdl/vhdl_dut.vhd new file mode 100644 index 00000000..904aa37d --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/project_benches/jtag/rtl/vhdl/vhdl_dut.vhd @@ -0,0 +1,21 @@ +library ieee; +use ieee.std_logic_1164.all ; + +entity vhdl_dut is + port ( clk : in std_logic ; + rst : in std_logic ; + in_signal : in std_logic ; + out_signal :out std_logic + ); +end vhdl_dut; + +architecture rtl of vhdl_dut is + begin + P1: process + variable out_signal_o : std_logic; + begin + wait until clk'event and clk = '1'; + out_signal_o := in_signal; + out_signal <= out_signal_o; + end process; + end rtl; diff --git a/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/project_benches/jtag/sim/Makefile b/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/project_benches/jtag/sim/Makefile new file mode 100644 index 00000000..0a54d158 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/project_benches/jtag/sim/Makefile @@ -0,0 +1,198 @@ + +# +#---------------------------------------------------------------------- +# +# DESCRIPTION: This makefile includes the shared makefile and contains +# bench level make targets. +# +#---------------------------------------------------------------------- + + +# pragma uvmf custom additional begin +# pragma uvmf custom additional end + +# ********************************************************************************************* +# UVMF library directory: +# This variable points to the UVMF release where uvmf_base_pkg directory resides. +# This variable points to release code that is not user modified. +# This variable allows for UVMF release directories to reside independent of project related verification IP and project bench directories. +# This code below looks "upward" for directory starting with UVMF_* and returns first match for use with the release examples. +UVMF_HOME ?= ___PLEASE_SET_AN_ENVIRONMENT_VARIABLE_NAMED_UVMF_HOME_TO_POINT_TO_THE_UVMF_INSTALLATION___ + +# pragma uvmf custom exports begin +# +# Project(s) specific verification IP library: +# Directory where reusable verification packages for interfaces, environments, utilities, etc. reside. +# This variable allows for your verification IP to reside independent of project bench and UVMF release directories. +# For examples deployed with UVMF this will be $(UVMF_HOME)//verification_ip +export UVMF_VIP_LIBRARY_HOME ?= $(PWD)/../../../verification_ip +# +# Project specific bench: +# Directory where bench specific code is located. +# This variable allows for project_benches to reside independent of verification IP and UVMF release directories. +# For examples deployed with UVMF this will be $(UVMF_HOME)//project_benches/ +export UVMF_PROJECT_DIR ?= $(PWD)/.. +# +# +# pragma uvmf custom exports end +# ********************************************************************************************* + +## Check PATH for required vinfo scripts +PVAL := $(shell command -v make_filelist.py 2> /dev/null) +ifndef PVAL + MFLIST = $(UVMF_HOME)/scripts/make_filelist.py +else + MFLIST = make_filelist.py +endif + + +# Set test case specific Variables +TEST_NAME ?= test_top + +TEST_SEED ?= random +UVM_CLI_ARGS = + +# Usage of Veloce, etc. to be input by the user (subject to defaults) +USE_VELOCE ?= 0 + +# Usage of vinfo flow for generating file list +USE_VINFO ?= 0 + +# Usage of Veloce and Questa profilers +USE_VELOCE_PROFILER ?= 0 +USE_QUESTA_PROFILER ?= 0 + + +# Set project Variables +TEST_PLAN_NAME = jtag_TestPlan +REPORTING_DO_FILE = jtag_reports_script + + +# Include makefile that includes targets for UVM_VIP_Library packages +include $(UVMF_HOME)/scripts/Makefile + + + + +# Include all requisite interface package targets for this bench +include $(UVMF_VIP_LIBRARY_HOME)/interface_packages/jtag_pkg/Makefile + +# Include all requisite environment package targets for this bench +include $(UVMF_VIP_LIBRARY_HOME)/environment_packages/jtag_env_pkg/Makefile + + + +# Add to default compile/load/run arguments +VCOM_ARGS += + +# Note: vsim-3009 error can be eliminated by adding -timescale 1ps/1ps to VLOG_ARGS + +VLOG_ARGS += $(UVM_DISABLE_FILE_LINE_CMD) + +VELANALYZE_ARGS += +VELANALYZE_HVL_ARGS += + +BATCH_VOPT_ARGS += +DEBUG_VOPT_ARGS += +EXTRA_VOPT_TOPS += +COMMON_VSIM_ARGS += +COMMON_VSIM_ARGS += + + +BATCH_VSIM_ARGS += #-uvmcontrol=none +DEBUG_VSIM_ARGS += +EXTRA_VSIM_TOPS += + +# pragma uvmf custom additional_args begin +# pragma uvmf custom additional_args end + + +# Project bench package source +jtag_PARAMETERS_PKG ?=\ +$(UVMF_PROJECT_DIR)/tb/parameters/jtag_parameters_pkg.sv + + +jtag_SEQUENCES_PKG ?=\ +$(UVMF_PROJECT_DIR)/tb/sequences/jtag_sequences_pkg.sv + + +jtag_TEST_PKG ?=\ +$(UVMF_PROJECT_DIR)/tb/tests/jtag_tests_pkg.sv + +# pragma uvmf custom dut_files begin +# UVMF_CHANGE_ME : Reference Verilog DUT source. +jtag_VERILOG_DUT ?=\ +$(UVMF_PROJECT_DIR)/rtl/verilog/verilog_dut.v + +# UVMF_CHANGE_ME : Reference VHDL DUT source. +jtag_VHDL_DUT ?=\ +$(UVMF_PROJECT_DIR)/rtl/vhdl/vhdl_dut.vhd +# pragma uvmf custom dut_files end + + +# Project bench package targets +COMP_jtag_PARAMETERS_PKG_TGT_0 = q_comp_jtag_parameters_pkg +COMP_jtag_PARAMETERS_PKG_TGT_1 = v_comp_jtag_parameters_pkg +COMP_jtag_PARAMETERS_PKG_TGT = $(COMP_jtag_PARAMETERS_PKG_TGT_$(USE_VELOCE)) + +comp_jtag_parameters_pkg: $(COMP_jtag_PARAMETERS_PKG_TGT) + +q_comp_jtag_parameters_pkg: + $(HVL_COMP_CMD) +incdir+$(UVMF_PROJECT_DIR)/tb/parameters $(jtag_PARAMETERS_PKG) + +v_comp_jtag_parameters_pkg: q_comp_jtag_parameters_pkg + $(HDL_COMP_CMD) +incdir+$(UVMF_PROJECT_DIR)/tb/parameters $(jtag_PARAMETERS_PKG) + + +comp_jtag_sequence_pkg: + $(HVL_COMP_CMD) +incdir+$(UVMF_PROJECT_DIR)/tb/sequences $(jtag_SEQUENCES_PKG) + +comp_jtag_tests_pkg: + $(HVL_COMP_CMD) +incdir+$(UVMF_PROJECT_DIR)/tb/tests $(jtag_TEST_PKG) + +# pragma uvmf custom dut_compile_make_target begin +# UVMF_CHANGE_ME : Add make target to compile your verilog dut here +comp_jtag_verilog_dut: + echo "Compile your verilog DUT here" + $(HDL_COMP_CMD) $(jtag_VERILOG_DUT) + +# UVMF_CHANGE_ME : Add make target to compile your vhdl dut here +comp_jtag_vhdl_dut: + echo "Compile your vhdl DUT here" + $(HDL_COMP_CMD_VHDL) $(jtag_VHDL_DUT) + +# UVMF_CHANGE_ME : Add make target to compile your dut here +comp_jtag_dut: comp_jtag_vhdl_dut comp_jtag_verilog_dut +# pragma uvmf custom dut_compile_make_target end + + +BUILD_TGT_0 = make_build +BUILD_TGT_1 = vinfo_build +BUILD_TGT = $(BUILD_TGT_$(USE_VINFO)) + + +comp_hvl : comp_hvl_core + + +comp_hvl_core : \ + comp_jtag_pkg \ + comp_jtag_env_pkg \ + comp_jtag_parameters_pkg comp_jtag_sequence_pkg comp_jtag_tests_pkg + +comp_uvmf_core : comp_uvm_pkg comp_uvmf_base_pkg + +make_build: comp_jtag_dut comp_uvmf_core comp_hvl comp_test_bench + +hvl_build: q_comp_jtag_pkg comp_jtag_env_pkg comp_jtag_sequence_pkg comp_jtag_tests_pkg hvl_comp_testbench link optimize + + +vinfo_build: comp_jtag_vhdl_dut build_hdl_vinfo build_hvl_vinfo $(VINFO_TGT) + + $(HDL_COMP_CMD) -F hdl.vf + $(VEL_COMP) + +build: $(BUILD_TGT) + +# pragma uvmf custom additional_targets begin +# pragma uvmf custom additional_targets end + diff --git a/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/project_benches/jtag/sim/bcr_testlist b/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/project_benches/jtag/sim/bcr_testlist new file mode 100644 index 00000000..ee75aff8 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/project_benches/jtag/sim/bcr_testlist @@ -0,0 +1,19 @@ + + + +# Test list for use by RMDB file +# File syntax is +# TB_INFO { } { } +# TB ## All subsequent tests will run on this bench until a different "TB" line is seen +# TEST <1st_seed> ... +# If not enough seeds are provided then random seeds are used to pad +# If no repeat count is given, default is 1 +# pragma uvmf custom tb_info begin +TB_INFO jtag { } { } +# pragma uvmf custom tb_info end +TB jtag +# pragma uvmf custom regression_suite begin +TEST test_top 3 +# pragma uvmf custom regression_suite end + + diff --git a/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/project_benches/jtag/sim/bcr_testlist.yaml b/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/project_benches/jtag/sim/bcr_testlist.yaml new file mode 100644 index 00000000..660b9ebe --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/project_benches/jtag/sim/bcr_testlist.yaml @@ -0,0 +1,44 @@ + + + +# YAML test list for use by RMDB file +# File syntax is +# uvmf_testlist: +# testbenches: +# - name: +# extra_build_options: +# extra_run_options: +# - name: +# ... +# - name: +# tests: +# - name: +# uvm_testname: (defaults to test_name) +# testbench: (defaults to last tb name seen) +# repeat: (defaults to 1) +# seeds: [,,...,] (defaults to all random) +# extra_test_options: +# - name: +# ... +# - name: +# include: +# - (relative path reference is to the including YAML file) +# - +# ... +# - + +uvmf_testlist: + testbenches: +# pragma uvmf custom tb_info begin + - name: jtag + extra_build_options: "" + extra_run_options: "" +# pragma uvmf custom tb_info end + tests: + - testbench: jtag +# pragma uvmf custom regression_suite begin + - name: test_top + repeat: 3 +# pragma uvmf custom regression_suite end + + diff --git a/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/project_benches/jtag/sim/cli_output.txt b/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/project_benches/jtag/sim/cli_output.txt new file mode 100644 index 00000000..607d30f7 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/project_benches/jtag/sim/cli_output.txt @@ -0,0 +1,264 @@ +test -e work || vlib work +echo "Compile your vhdl DUT here" +Compile your vhdl DUT here +vcom /hwetools/work_area/frontend/hemanth_b7/github_dir/UVMF_ch2/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/project_benches/jtag/sim/../rtl/vhdl/vhdl_dut.vhd +Start time: 14:33:16 on Dec 20,2022 +vcom /hwetools/work_area/frontend/hemanth_b7/github_dir/UVMF_ch2/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/project_benches/jtag/sim/../rtl/vhdl/vhdl_dut.vhd +QuestaSim vcom 10.6c Compiler 2017.07 Jul 25 2017 +-- Loading package STANDARD +-- Loading package TEXTIO +-- Loading package std_logic_1164 +-- Compiling entity vhdl_dut +-- Compiling architecture rtl of vhdl_dut +End time: 14:33:17 on Dec 20,2022, Elapsed time: 0:00:01 +Errors: 0, Warnings: 0 +echo "Compile your verilog DUT here" +Compile your verilog DUT here +vlog -sv -suppress 2223 -suppress 2286 +define+UVM_REPORT_DISABLE_FILE_LINE +define+UVM_REPORT_DISABLE_FILE_LINE /hwetools/work_area/frontend/hemanth_b7/github_dir/UVMF_ch2/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/project_benches/jtag/sim/../rtl/verilog/verilog_dut.v +QuestaSim vlog 10.6c Compiler 2017.07 Jul 25 2017 +Start time: 14:33:17 on Dec 20,2022 +vlog -sv -suppress 2223 -suppress 2286 "+define+UVM_REPORT_DISABLE_FILE_LINE" "+define+UVM_REPORT_DISABLE_FILE_LINE" /hwetools/work_area/frontend/hemanth_b7/github_dir/UVMF_ch2/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/project_benches/jtag/sim/../rtl/verilog/verilog_dut.v +-- Compiling module verilog_dut + +Top level modules: + verilog_dut +End time: 14:33:17 on Dec 20,2022, Elapsed time: 0:00:00 +Errors: 0, Warnings: 0 +vlog -sv -suppress 2223 -suppress 2286 +define+UVM_REPORT_DISABLE_FILE_LINE +define+UVM_REPORT_DISABLE_FILE_LINE +incdir+/hwetools/work_area/frontend/hemanth_b7/github_dir/UVMF_ch2/UVM_Framework/UVMF_2022.3/uvmf_base_pkg -F /hwetools/work_area/frontend/hemanth_b7/github_dir/UVMF_ch2/UVM_Framework/UVMF_2022.3/uvmf_base_pkg/uvmf_base_pkg_filelist_hdl.f +QuestaSim vlog 10.6c Compiler 2017.07 Jul 25 2017 +Start time: 14:33:17 on Dec 20,2022 +vlog -sv -suppress 2223 -suppress 2286 "+define+UVM_REPORT_DISABLE_FILE_LINE" "+define+UVM_REPORT_DISABLE_FILE_LINE" "+incdir+/hwetools/work_area/frontend/hemanth_b7/github_dir/UVMF_ch2/UVM_Framework/UVMF_2022.3/uvmf_base_pkg" -F /hwetools/work_area/frontend/hemanth_b7/github_dir/UVMF_ch2/UVM_Framework/UVMF_2022.3/uvmf_base_pkg/uvmf_base_pkg_filelist_hdl.f +-- Compiling package uvmf_base_pkg_hdl + +Top level modules: + --none-- +End time: 14:33:17 on Dec 20,2022, Elapsed time: 0:00:00 +Errors: 0, Warnings: 0 +vlog -sv -suppress 2223 -suppress 2286 +define+UVM_REPORT_DISABLE_FILE_LINE +define+UVM_REPORT_DISABLE_FILE_LINE +incdir+/hwetools/work_area/frontend/hemanth_b7/github_dir/UVMF_ch2/UVM_Framework/UVMF_2022.3/uvmf_base_pkg -F /hwetools/work_area/frontend/hemanth_b7/github_dir/UVMF_ch2/UVM_Framework/UVMF_2022.3/uvmf_base_pkg/uvmf_base_pkg_filelist_hvl.f +QuestaSim vlog 10.6c Compiler 2017.07 Jul 25 2017 +Start time: 14:33:17 on Dec 20,2022 +vlog -sv -suppress 2223 -suppress 2286 "+define+UVM_REPORT_DISABLE_FILE_LINE" "+define+UVM_REPORT_DISABLE_FILE_LINE" "+incdir+/hwetools/work_area/frontend/hemanth_b7/github_dir/UVMF_ch2/UVM_Framework/UVMF_2022.3/uvmf_base_pkg" -F /hwetools/work_area/frontend/hemanth_b7/github_dir/UVMF_ch2/UVM_Framework/UVMF_2022.3/uvmf_base_pkg/uvmf_base_pkg_filelist_hvl.f +-- Compiling package uvmf_base_pkg +-- Importing package mtiUvm.uvm_pkg (uvm-1.1d Built-in) +-- Importing package uvmf_base_pkg_hdl + +Top level modules: + --none-- +End time: 14:33:17 on Dec 20,2022, Elapsed time: 0:00:00 +Errors: 0, Warnings: 0 +vlog -sv -suppress 2223 -suppress 2286 +define+UVM_REPORT_DISABLE_FILE_LINE +define+UVM_REPORT_DISABLE_FILE_LINE +incdir+/hwetools/work_area/frontend/hemanth_b7/github_dir/UVMF_ch2/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/verification_ip/interface_packages/jtag_pkg -F /hwetools/work_area/frontend/hemanth_b7/github_dir/UVMF_ch2/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/verification_ip/interface_packages/jtag_pkg/jtag_filelist_hdl.f +QuestaSim vlog 10.6c Compiler 2017.07 Jul 25 2017 +Start time: 14:33:17 on Dec 20,2022 +vlog -sv -suppress 2223 -suppress 2286 "+define+UVM_REPORT_DISABLE_FILE_LINE" "+define+UVM_REPORT_DISABLE_FILE_LINE" "+incdir+/hwetools/work_area/frontend/hemanth_b7/github_dir/UVMF_ch2/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/verification_ip/interface_packages/jtag_pkg" -F /hwetools/work_area/frontend/hemanth_b7/github_dir/UVMF_ch2/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/verification_ip/interface_packages/jtag_pkg/jtag_filelist_hdl.f +-- Compiling package jtag_pkg_hdl +-- Importing package uvmf_base_pkg_hdl + +Top level modules: + --none-- +End time: 14:33:17 on Dec 20,2022, Elapsed time: 0:00:00 +Errors: 0, Warnings: 0 +vlog -sv -suppress 2223 -suppress 2286 +define+UVM_REPORT_DISABLE_FILE_LINE +define+UVM_REPORT_DISABLE_FILE_LINE +incdir+/hwetools/work_area/frontend/hemanth_b7/github_dir/UVMF_ch2/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/verification_ip/interface_packages/jtag_pkg -F /hwetools/work_area/frontend/hemanth_b7/github_dir/UVMF_ch2/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/verification_ip/interface_packages/jtag_pkg/jtag_filelist_hvl.f +QuestaSim vlog 10.6c Compiler 2017.07 Jul 25 2017 +Start time: 14:33:17 on Dec 20,2022 +vlog -sv -suppress 2223 -suppress 2286 "+define+UVM_REPORT_DISABLE_FILE_LINE" "+define+UVM_REPORT_DISABLE_FILE_LINE" "+incdir+/hwetools/work_area/frontend/hemanth_b7/github_dir/UVMF_ch2/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/verification_ip/interface_packages/jtag_pkg" -F /hwetools/work_area/frontend/hemanth_b7/github_dir/UVMF_ch2/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/verification_ip/interface_packages/jtag_pkg/jtag_filelist_hvl.f +-- Compiling package jtag_pkg +-- Importing package mtiUvm.uvm_pkg (uvm-1.1d Built-in) +-- Importing package uvmf_base_pkg_hdl +-- Importing package uvmf_base_pkg +-- Importing package jtag_pkg_hdl + +Top level modules: + --none-- +End time: 14:33:18 on Dec 20,2022, Elapsed time: 0:00:01 +Errors: 0, Warnings: 0 +vlog -sv -suppress 2223 -suppress 2286 +define+UVM_REPORT_DISABLE_FILE_LINE +define+UVM_REPORT_DISABLE_FILE_LINE +incdir+/hwetools/work_area/frontend/hemanth_b7/github_dir/UVMF_ch2/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/verification_ip/interface_packages/jtag_pkg -F /hwetools/work_area/frontend/hemanth_b7/github_dir/UVMF_ch2/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/verification_ip/interface_packages/jtag_pkg/jtag_filelist_xrtl.f +QuestaSim vlog 10.6c Compiler 2017.07 Jul 25 2017 +Start time: 14:33:18 on Dec 20,2022 +vlog -sv -suppress 2223 -suppress 2286 "+define+UVM_REPORT_DISABLE_FILE_LINE" "+define+UVM_REPORT_DISABLE_FILE_LINE" "+incdir+/hwetools/work_area/frontend/hemanth_b7/github_dir/UVMF_ch2/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/verification_ip/interface_packages/jtag_pkg" -F /hwetools/work_area/frontend/hemanth_b7/github_dir/UVMF_ch2/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/verification_ip/interface_packages/jtag_pkg/jtag_filelist_xrtl.f +-- Compiling package jtag_if_sv_unit +-- Importing package uvmf_base_pkg_hdl +-- Importing package jtag_pkg_hdl +-- Compiling interface jtag_if +-- Compiling package jtag_monitor_bfm_sv_unit +-- Importing package uvmf_base_pkg_hdl +-- Importing package jtag_pkg_hdl +-- Compiling interface jtag_monitor_bfm +-- Importing package mtiUvm.uvm_pkg (uvm-1.1d Built-in) +-- Importing package jtag_pkg +-- Importing package uvmf_base_pkg +-- Compiling package jtag_driver_bfm_sv_unit +-- Importing package uvmf_base_pkg_hdl +-- Importing package jtag_pkg_hdl +-- Compiling interface jtag_driver_bfm +-- Importing package mtiUvm.uvm_pkg (uvm-1.1d Built-in) +-- Importing package jtag_pkg +-- Importing package uvmf_base_pkg + +Top level modules: + --none-- +End time: 14:33:19 on Dec 20,2022, Elapsed time: 0:00:01 +Errors: 0, Warnings: 0 +vlog -sv -suppress 2223 -suppress 2286 +define+UVM_REPORT_DISABLE_FILE_LINE +define+UVM_REPORT_DISABLE_FILE_LINE +incdir+/hwetools/work_area/frontend/hemanth_b7/github_dir/UVMF_ch2/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/verification_ip/environment_packages/jtag_env_pkg /hwetools/work_area/frontend/hemanth_b7/github_dir/UVMF_ch2/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/verification_ip/environment_packages/jtag_env_pkg/jtag_env_pkg.sv +QuestaSim vlog 10.6c Compiler 2017.07 Jul 25 2017 +Start time: 14:33:19 on Dec 20,2022 +vlog -sv -suppress 2223 -suppress 2286 "+define+UVM_REPORT_DISABLE_FILE_LINE" "+define+UVM_REPORT_DISABLE_FILE_LINE" "+incdir+/hwetools/work_area/frontend/hemanth_b7/github_dir/UVMF_ch2/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/verification_ip/environment_packages/jtag_env_pkg" /hwetools/work_area/frontend/hemanth_b7/github_dir/UVMF_ch2/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/verification_ip/environment_packages/jtag_env_pkg/jtag_env_pkg.sv +-- Compiling package jtag_env_pkg +-- Importing package mtiUvm.uvm_pkg (uvm-1.1d Built-in) +-- Importing package uvmf_base_pkg +-- Importing package uvmf_base_pkg_hdl +-- Importing package jtag_pkg +-- Importing package jtag_pkg_hdl + +Top level modules: + --none-- +End time: 14:33:20 on Dec 20,2022, Elapsed time: 0:00:01 +Errors: 0, Warnings: 0 +vlog -sv -suppress 2223 -suppress 2286 +define+UVM_REPORT_DISABLE_FILE_LINE +define+UVM_REPORT_DISABLE_FILE_LINE +incdir+/hwetools/work_area/frontend/hemanth_b7/github_dir/UVMF_ch2/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/project_benches/jtag/sim/../tb/parameters /hwetools/work_area/frontend/hemanth_b7/github_dir/UVMF_ch2/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/project_benches/jtag/sim/../tb/parameters/jtag_parameters_pkg.sv +QuestaSim vlog 10.6c Compiler 2017.07 Jul 25 2017 +Start time: 14:33:20 on Dec 20,2022 +vlog -sv -suppress 2223 -suppress 2286 "+define+UVM_REPORT_DISABLE_FILE_LINE" "+define+UVM_REPORT_DISABLE_FILE_LINE" "+incdir+/hwetools/work_area/frontend/hemanth_b7/github_dir/UVMF_ch2/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/project_benches/jtag/sim/../tb/parameters" /hwetools/work_area/frontend/hemanth_b7/github_dir/UVMF_ch2/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/project_benches/jtag/sim/../tb/parameters/jtag_parameters_pkg.sv +-- Compiling package jtag_parameters_pkg +-- Importing package uvmf_base_pkg_hdl + +Top level modules: + --none-- +End time: 14:33:20 on Dec 20,2022, Elapsed time: 0:00:00 +Errors: 0, Warnings: 0 +vlog -sv -suppress 2223 -suppress 2286 +define+UVM_REPORT_DISABLE_FILE_LINE +define+UVM_REPORT_DISABLE_FILE_LINE +incdir+/hwetools/work_area/frontend/hemanth_b7/github_dir/UVMF_ch2/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/project_benches/jtag/sim/../tb/sequences /hwetools/work_area/frontend/hemanth_b7/github_dir/UVMF_ch2/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/project_benches/jtag/sim/../tb/sequences/jtag_sequences_pkg.sv +QuestaSim vlog 10.6c Compiler 2017.07 Jul 25 2017 +Start time: 14:33:20 on Dec 20,2022 +vlog -sv -suppress 2223 -suppress 2286 "+define+UVM_REPORT_DISABLE_FILE_LINE" "+define+UVM_REPORT_DISABLE_FILE_LINE" "+incdir+/hwetools/work_area/frontend/hemanth_b7/github_dir/UVMF_ch2/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/project_benches/jtag/sim/../tb/sequences" /hwetools/work_area/frontend/hemanth_b7/github_dir/UVMF_ch2/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/project_benches/jtag/sim/../tb/sequences/jtag_sequences_pkg.sv +-- Compiling package jtag_sequences_pkg +-- Importing package mtiUvm.uvm_pkg (uvm-1.1d Built-in) +-- Importing package uvmf_base_pkg +-- Importing package uvmf_base_pkg_hdl +-- Importing package jtag_pkg +-- Importing package jtag_pkg_hdl +-- Importing package jtag_parameters_pkg +-- Importing package jtag_env_pkg + +Top level modules: + --none-- +End time: 14:33:21 on Dec 20,2022, Elapsed time: 0:00:01 +Errors: 0, Warnings: 0 +vlog -sv -suppress 2223 -suppress 2286 +define+UVM_REPORT_DISABLE_FILE_LINE +define+UVM_REPORT_DISABLE_FILE_LINE +incdir+/hwetools/work_area/frontend/hemanth_b7/github_dir/UVMF_ch2/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/project_benches/jtag/sim/../tb/tests /hwetools/work_area/frontend/hemanth_b7/github_dir/UVMF_ch2/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/project_benches/jtag/sim/../tb/tests/jtag_tests_pkg.sv +QuestaSim vlog 10.6c Compiler 2017.07 Jul 25 2017 +Start time: 14:33:21 on Dec 20,2022 +vlog -sv -suppress 2223 -suppress 2286 "+define+UVM_REPORT_DISABLE_FILE_LINE" "+define+UVM_REPORT_DISABLE_FILE_LINE" "+incdir+/hwetools/work_area/frontend/hemanth_b7/github_dir/UVMF_ch2/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/project_benches/jtag/sim/../tb/tests" /hwetools/work_area/frontend/hemanth_b7/github_dir/UVMF_ch2/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/project_benches/jtag/sim/../tb/tests/jtag_tests_pkg.sv +-- Compiling package jtag_tests_pkg +-- Importing package mtiUvm.uvm_pkg (uvm-1.1d Built-in) +-- Importing package uvmf_base_pkg +-- Importing package uvmf_base_pkg_hdl +-- Importing package jtag_parameters_pkg +-- Importing package jtag_env_pkg +-- Importing package jtag_pkg +-- Importing package jtag_pkg_hdl +-- Importing package jtag_sequences_pkg + +Top level modules: + --none-- +End time: 14:33:21 on Dec 20,2022, Elapsed time: 0:00:00 +Errors: 0, Warnings: 0 +vlog -sv -suppress 2223 -suppress 2286 +define+UVM_REPORT_DISABLE_FILE_LINE +define+UVM_REPORT_DISABLE_FILE_LINE +incdir+/questa_mvc_src/sv +incdir+/hwetools/work_area/frontend/hemanth_b7/github_dir/UVMF_ch2/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/project_benches/jtag/sim/../tb/testbench -F /hwetools/work_area/frontend/hemanth_b7/github_dir/UVMF_ch2/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/project_benches/jtag/sim/../tb/testbench/top_filelist_hvl.f +QuestaSim vlog 10.6c Compiler 2017.07 Jul 25 2017 +Start time: 14:33:21 on Dec 20,2022 +vlog -sv -suppress 2223 -suppress 2286 "+define+UVM_REPORT_DISABLE_FILE_LINE" "+define+UVM_REPORT_DISABLE_FILE_LINE" "+incdir+/questa_mvc_src/sv" "+incdir+/hwetools/work_area/frontend/hemanth_b7/github_dir/UVMF_ch2/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/project_benches/jtag/sim/../tb/testbench" -F /hwetools/work_area/frontend/hemanth_b7/github_dir/UVMF_ch2/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/project_benches/jtag/sim/../tb/testbench/top_filelist_hvl.f +-- Compiling module hvl_top +-- Importing package mtiUvm.uvm_pkg (uvm-1.1d Built-in) +-- Importing package jtag_tests_pkg +-- Importing package uvmf_base_pkg +-- Importing package uvmf_base_pkg_hdl +-- Importing package jtag_parameters_pkg +-- Importing package jtag_env_pkg +-- Importing package jtag_pkg +-- Importing package jtag_pkg_hdl +-- Importing package jtag_sequences_pkg + +Top level modules: + hvl_top +End time: 14:33:22 on Dec 20,2022, Elapsed time: 0:00:01 +Errors: 0, Warnings: 0 +vlog -sv -suppress 2223 -suppress 2286 +define+UVM_REPORT_DISABLE_FILE_LINE +define+UVM_REPORT_DISABLE_FILE_LINE +incdir+/hwetools/work_area/frontend/hemanth_b7/github_dir/UVMF_ch2/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/project_benches/jtag/sim/../tb/testbench -F /hwetools/work_area/frontend/hemanth_b7/github_dir/UVMF_ch2/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/project_benches/jtag/sim/../tb/testbench/top_filelist_hdl.f +QuestaSim vlog 10.6c Compiler 2017.07 Jul 25 2017 +Start time: 14:33:22 on Dec 20,2022 +vlog -sv -suppress 2223 -suppress 2286 "+define+UVM_REPORT_DISABLE_FILE_LINE" "+define+UVM_REPORT_DISABLE_FILE_LINE" "+incdir+/hwetools/work_area/frontend/hemanth_b7/github_dir/UVMF_ch2/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/project_benches/jtag/sim/../tb/testbench" -F /hwetools/work_area/frontend/hemanth_b7/github_dir/UVMF_ch2/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/project_benches/jtag/sim/../tb/testbench/top_filelist_hdl.f +-- Compiling module hdl_top +-- Importing package jtag_parameters_pkg +-- Importing package uvmf_base_pkg_hdl +-- Importing package mtiUvm.uvm_pkg (uvm-1.1d Built-in) + +Top level modules: + hdl_top +End time: 14:33:22 on Dec 20,2022, Elapsed time: 0:00:00 +Errors: 0, Warnings: 0 +vopt hvl_top hdl_top -o optimized_batch_top_tb +QuestaSim vopt 10.6c Compiler 2017.07 Jul 25 2017 +Start time: 14:33:22 on Dec 20,2022 +vopt hvl_top hdl_top -o optimized_batch_top_tb + +Top level modules: + hvl_top + hdl_top + +Analyzing design... +-- Loading module hvl_top +-- Importing package mtiUvm.uvm_pkg (uvm-1.1d Built-in) +-- Importing package jtag_tests_pkg +-- Importing package uvmf_base_pkg +-- Importing package uvmf_base_pkg_hdl +-- Importing package jtag_parameters_pkg +-- Importing package jtag_env_pkg +-- Importing package jtag_pkg +-- Importing package jtag_pkg_hdl +-- Importing package jtag_sequences_pkg +-- Loading module hdl_top +-- Loading interface jtag_if +-- Loading interface jtag_monitor_bfm +-- Loading interface jtag_driver_bfm +-- Loading module verilog_dut +-- Loading package STANDARD +-- Loading package TEXTIO +-- Loading package std_logic_1164 +-- Loading entity vhdl_dut +-- Loading architecture rtl of vhdl_dut +-- Loading package mtiUvm.questa_uvm_pkg +Incremental compilation check found no design-units have changed. +Optimized design name is optimized_batch_top_tb +End time: 14:33:23 on Dec 20,2022, Elapsed time: 0:00:01 +Errors: 0, Warnings: 0 +vopt +acc hvl_top hdl_top -o optimized_debug_top_tb +QuestaSim vopt 10.6c Compiler 2017.07 Jul 25 2017 +Start time: 14:33:23 on Dec 20,2022 +vopt "+acc" hvl_top hdl_top -o optimized_debug_top_tb + +Top level modules: + hvl_top + hdl_top + +Analyzing design... +-- Loading module hvl_top +-- Importing package mtiUvm.uvm_pkg (uvm-1.1d Built-in) +-- Importing package jtag_tests_pkg +-- Importing package uvmf_base_pkg +-- Importing package uvmf_base_pkg_hdl +-- Importing package jtag_parameters_pkg +-- Importing package jtag_env_pkg +-- Importing package jtag_pkg +-- Importing package jtag_pkg_hdl +-- Importing package jtag_sequences_pkg +-- Loading module hdl_top +-- Loading interface jtag_if +-- Loading interface jtag_monitor_bfm +-- Loading interface jtag_driver_bfm +-- Loading module verilog_dut +-- Loading package STANDARD +-- Loading package TEXTIO +-- Loading package std_logic_1164 +-- Loading entity vhdl_dut +-- Loading architecture rtl of vhdl_dut +-- Loading package mtiUvm.questa_uvm_pkg +Incremental compilation check found no design-units have changed. +Optimized design name is optimized_debug_top_tb +End time: 14:33:24 on Dec 20,2022, Elapsed time: 0:00:01 +Errors: 0, Warnings: 0 +vsim -c -sv_seed random +UVM_TESTNAME=test_top -permit_unmatched_virtual_intf +notimingchecks -suppress 8887 -solvefaildebug -solvefailtestcase -uvmcontrol=none -printsimstats -do " coverage save -onexit test_top.ucdb; set IterationLimit 140000; set NoQuitOnFinish 1; run -all; quit -f;" optimized_batch_top_tb diff --git a/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/project_benches/jtag/sim/compile.do b/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/project_benches/jtag/sim/compile.do new file mode 100644 index 00000000..6e5ee58a --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/project_benches/jtag/sim/compile.do @@ -0,0 +1,70 @@ + + +################################################################## +## ENVIRONMENT VARIABLES +################################################################## +quietly set ::env(UVMF_VIP_LIBRARY_HOME) ../../../verification_ip +quietly set ::env(UVMF_PROJECT_DIR) .. + +## Using VRM means that the build is occuring several more directories deeper underneath +## the sim directory, need to prepend some more '..' +if {[info exists ::env(VRM_BUILD)]} { + quietly set ::env(UVMF_VIP_LIBRARY_HOME) "../../../../../$::env(UVMF_VIP_LIBRARY_HOME)" + quietly set ::env(UVMF_PROJECT_DIR) "../../../../../$::env(UVMF_PROJECT_DIR)" +} +quietly set ::env(UVMF_VIP_LIBRARY_HOME) [file normalize $::env(UVMF_VIP_LIBRARY_HOME)] +quietly set ::env(UVMF_PROJECT_DIR) [file normalize $::env(UVMF_PROJECT_DIR)] +quietly echo "UVMF_VIP_LIBRARY_HOME = $::env(UVMF_VIP_LIBRARY_HOME)" +quietly echo "UVMF_PROJECT_DIR = $::env(UVMF_PROJECT_DIR)" + + +################################################################### +## HOUSEKEEPING : DELETE FILES THAT WILL BE REGENERATED +################################################################### +file delete -force *~ *.ucdb vsim.dbg *.vstf *.log work *.mem *.transcript.txt certe_dump.xml *.wlf covhtmlreport VRMDATA +file delete -force design.bin qwave.db dpiheader.h visualizer*.ses +file delete -force veloce.med veloce.wave veloce.map tbxbindings.h edsenv velrunopts.ini +file delete -force sv_connect.* + +################################################################### +## COMPILE DUT SOURCE CODE +################################################################### +vlib work +# pragma uvmf custom dut_compile_dofile_target begin +# UVMF_CHANGE_ME : Add commands to compile your dut here, replacing the default examples +vlog -sv -timescale 1ps/1ps -suppress 2223,2286 $env(UVMF_PROJECT_DIR)/rtl/verilog/verilog_dut.v +vcom $env(UVMF_PROJECT_DIR)/rtl/vhdl/vhdl_dut.vhd +# pragma uvmf custom dut_compile_dofile_target end + +################################################################### +## COMPILE UVMF BASE/COMMON SOURCE CODE +################################################################### +vlog -sv -timescale 1ps/1ps -suppress 2223 -suppress 2286 +incdir+$env(UVMF_HOME)/uvmf_base_pkg -F $env(UVMF_HOME)/uvmf_base_pkg/uvmf_base_pkg_filelist_hdl.f +vlog -sv -timescale 1ps/1ps -suppress 2223 -suppress 2286 +incdir+$env(UVMF_HOME)/uvmf_base_pkg -F $env(UVMF_HOME)/uvmf_base_pkg/uvmf_base_pkg_filelist_hvl.f + + +################################################################### +## UVMF INTERFACE COMPILATION +################################################################### +do $env(UVMF_VIP_LIBRARY_HOME)/interface_packages/jtag_pkg/compile.do + +################################################################### +## UVMF ENVIRONMENT COMPILATION +################################################################### +do $env(UVMF_VIP_LIBRARY_HOME)/environment_packages/jtag_env_pkg/compile.do + +################################################################### +## UVMF BENCHES COMPILATION +################################################################### +vlog -sv -timescale 1ps/1ps -suppress 2223 -suppress 2286 +incdir+$env(UVMF_PROJECT_DIR)/tb/parameters $env(UVMF_PROJECT_DIR)/tb/parameters/jtag_parameters_pkg.sv +vlog -sv -timescale 1ps/1ps -suppress 2223 -suppress 2286 +incdir+$env(UVMF_PROJECT_DIR)/tb/sequences $env(UVMF_PROJECT_DIR)/tb/sequences/jtag_sequences_pkg.sv +vlog -sv -timescale 1ps/1ps -suppress 2223 -suppress 2286 +incdir+$env(UVMF_PROJECT_DIR)/tb/tests $env(UVMF_PROJECT_DIR)/tb/tests/jtag_tests_pkg.sv + +vlog -sv -timescale 1ps/1ps -suppress 2223 -suppress 2286 +incdir+$env(UVMF_PROJECT_DIR)/tb/testbench -F $env(UVMF_PROJECT_DIR)/tb/testbench/top_filelist_hdl.f +vlog -sv -timescale 1ps/1ps -suppress 2223 -suppress 2286 +incdir+$env(UVMF_PROJECT_DIR)/tb/testbench -F $env(UVMF_PROJECT_DIR)/tb/testbench/top_filelist_hvl.f + +################################################################### +## OPTIMIZATION +################################################################### +vopt hvl_top hdl_top -o optimized_batch_top_tb +vopt +acc hvl_top hdl_top -o optimized_debug_top_tb diff --git a/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/project_benches/jtag/sim/hdl.compile b/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/project_benches/jtag/sim/hdl.compile new file mode 100644 index 00000000..8e7bd41a --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/project_benches/jtag/sim/hdl.compile @@ -0,0 +1,5 @@ +needs: +# pragma uvmf custom dut_compile_info begin + - ../rtl/dut.compile +# pragma uvmf custom dut_compile_info end + - ../tb/testbench/hdl_top.compile diff --git a/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/project_benches/jtag/sim/hdl.vinfo b/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/project_benches/jtag/sim/hdl.vinfo new file mode 100644 index 00000000..da27ec77 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/project_benches/jtag/sim/hdl.vinfo @@ -0,0 +1 @@ +@use $UVMF_PROJECT_DIR/tb/testbench/hdl_top.vinfo diff --git a/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/project_benches/jtag/sim/hvl.compile b/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/project_benches/jtag/sim/hvl.compile new file mode 100644 index 00000000..ce952549 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/project_benches/jtag/sim/hvl.compile @@ -0,0 +1,2 @@ +needs: + - ../tb/testbench/hvl_top.compile diff --git a/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/project_benches/jtag/sim/hvl.vinfo b/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/project_benches/jtag/sim/hvl.vinfo new file mode 100644 index 00000000..d22eff33 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/project_benches/jtag/sim/hvl.vinfo @@ -0,0 +1 @@ +@use $UVMF_PROJECT_DIR/tb/testbench/hvl_top.vinfo diff --git a/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/project_benches/jtag/sim/run.do b/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/project_benches/jtag/sim/run.do new file mode 100644 index 00000000..101ddc48 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/project_benches/jtag/sim/run.do @@ -0,0 +1,21 @@ + + +quietly set svLibs "" +quietly set extra_vsim_args "" + +################################################################### +## Check for additional vsim arguments passed using env var $UVMF_EXTRA_VSIM_ARGS +################################################################### +if {[info exists ::env(UVMF_EXTRA_VSIM_ARGS)]} { + echo "Adding more args to vsim command" + quietly set extra_vsim_args $::env(UVMF_EXTRA_VSIM_ARGS) +} + +################################################################## +## Launch Questa : generate vsim command line and execute +################################################################## +# pragma uvmf custom dut_run_dofile_target begin +# UVMF_CHANGE_ME : Change the UVM_TESTNAME plusarg to run a different test +quietly set cmd [format "vsim -i -sv_seed random +UVM_TESTNAME=test_top +UVM_VERBOSITY=UVM_HIGH -permit_unmatched_virtual_intf +notimingchecks -suppress 8887 %s %s -uvmcontrol=all -msgmode both -classdebug -assertdebug +uvm_set_config_int=*,enable_transaction_viewing,1 -do { set NoQuitOnFinish 1; onbreak {resume}; run 0; do wave.do; set PrefSource(OpenOnBreak) 0; radix hex showbase; } optimized_debug_top_tb" $svLibs $extra_vsim_args] +# pragma uvmf custom dut_run_dofile_target end +eval $cmd diff --git a/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/project_benches/jtag/sim/tbx.config b/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/project_benches/jtag/sim/tbx.config new file mode 100644 index 00000000..eec58168 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/project_benches/jtag/sim/tbx.config @@ -0,0 +1,10 @@ + + + + + +comp -questa +velsyn -D1S +rtlc -allow_4ST + + diff --git a/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/project_benches/jtag/sim/testlist b/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/project_benches/jtag/sim/testlist new file mode 100644 index 00000000..62d99e25 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/project_benches/jtag/sim/testlist @@ -0,0 +1,20 @@ + + + + +# Test list for use by RMDB file +# File syntax is +# TB_INFO { } { } +# TB ## All subsequent tests will run on this bench until a different "TB" line is seen +# TEST <1st_seed> ... +# If not enough seeds are provided then random seeds are used to pad +# If no repeat count is given, default is 1 +# pragma uvmf custom tb_info begin +TB_INFO jtag { UVMF_VIP_LIBRARY_HOME=../../../../../../../../verification_ip UVMF_PROJECT_DIR=../../../../../../../jtag } { } +# pragma uvmf custom tb_info end +TB jtag +# pragma uvmf custom regression_suite begin +TEST test_top 3 +# pragma uvmf custom regression_suite end + + diff --git a/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/project_benches/jtag/sim/testlist.yaml b/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/project_benches/jtag/sim/testlist.yaml new file mode 100644 index 00000000..ce061ee9 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/project_benches/jtag/sim/testlist.yaml @@ -0,0 +1,44 @@ + + + +# YAML test list for use by RMDB file +# File syntax is +# uvmf_testlist: +# testbenches: +# - name: +# extra_build_options: +# extra_run_options: +# - name: +# ... +# - name: +# tests: +# - name: +# uvm_testname: (defaults to test_name) +# testbench: (defaults to last tb name seen) +# repeat: (defaults to 1) +# seeds: [,,...,] (defaults to all random) +# extra_test_options: +# - name: +# ... +# - name: +# include: +# - (relative path reference is to the including YAML file) +# - +# ... +# - + +uvmf_testlist: + testbenches: +# pragma uvmf custom tb_info begin + - name: jtag + extra_build_options: "UVMF_VIP_LIBRARY_HOME=../../../../../../../../verification_ip UVMF_PROJECT_DIR=../../../../../../../jtag" + extra_run_options: "" +# pragma uvmf custom tb_info end + tests: + - testbench: jtag +# pragma uvmf custom regression_suite begin + - name: test_top + repeat: 3 +# pragma uvmf custom regression_suite end + + diff --git a/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/project_benches/jtag/sim/top.compile b/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/project_benches/jtag/sim/top.compile new file mode 100644 index 00000000..efd51c07 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/project_benches/jtag/sim/top.compile @@ -0,0 +1,3 @@ +needs: + - hvl.compile + - hdl.compile diff --git a/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/project_benches/jtag/sim/veloce.config b/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/project_benches/jtag/sim/veloce.config new file mode 100644 index 00000000..d0975155 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/project_benches/jtag/sim/veloce.config @@ -0,0 +1,26 @@ + + + + + +# pragma uvmf custom additional begin +comp -num_boards 1 +comp -hvl questa +# Please choose the correct emulator type code for +# comp -platform command or else velcomp will fail +# Available types are: +# - Veloce2 Quattro: D2 +# - Veloce2 Maximus: D2M +# - Veloce Strato TiL, Ti, and Mi: Strato +# - Veloce Strato M and Strato T: StratoM +# - comp -platform +comp -platform Strato + +rtlc -enable_tbx_pragma_checks +rtlc -allow_4ST +rtlc -allow_MDR +rtlc -compile_display +rtlc -xwave_siglist xwaves.sigs +# pragma uvmf custom additional end + + diff --git a/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/project_benches/jtag/sim/viswave.do b/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/project_benches/jtag/sim/viswave.do new file mode 100644 index 00000000..33f2de1c --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/project_benches/jtag/sim/viswave.do @@ -0,0 +1,22 @@ + + +onerror resume +wave tags F0 +wave update off + +wave spacer -backgroundcolor Salmon { jtag_in } +wave add uvm_test_top.environment.jtag_in.jtag_in_monitor.txn_stream -radix string -tag F0 +wave group jtag_in_bus +wave add -group jtag_in_bus hdl_top.jtag_in_bus.* -radix hexadecimal -tag F0 +wave group jtag_in_bus -collapse +wave insertion [expr [wave index insertpoint] +1] +wave spacer -backgroundcolor Salmon { jtag_out } +wave add uvm_test_top.environment.jtag_out.jtag_out_monitor.txn_stream -radix string -tag F0 +wave group jtag_out_bus +wave add -group jtag_out_bus hdl_top.jtag_out_bus.* -radix hexadecimal -tag F0 +wave group jtag_out_bus -collapse +wave insertion [expr [wave index insertpoint] +1] + +wave update on +WaveSetStreamView + diff --git a/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/project_benches/jtag/sim/wave.do b/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/project_benches/jtag/sim/wave.do new file mode 100644 index 00000000..11a4bd82 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/project_benches/jtag/sim/wave.do @@ -0,0 +1,30 @@ + + +onerror {resume} +quietly WaveActivateNextPane {} 0 + +add wave -noupdate -divider jtag_in +add wave -noupdate /uvm_root/uvm_test_top/environment/jtag_in/jtag_in_monitor/txn_stream +add wave -noupdate -group jtag_in_bus /hdl_top/jtag_in_bus/* +add wave -noupdate -divider jtag_out +add wave -noupdate /uvm_root/uvm_test_top/environment/jtag_out/jtag_out_monitor/txn_stream +add wave -noupdate -group jtag_out_bus /hdl_top/jtag_out_bus/* + +TreeUpdate [SetDefaultTree] +quietly wave cursor active 0 +configure wave -namecolwidth 472 +configure wave -valuecolwidth 100 +configure wave -justifyvalue left +configure wave -signalnamewidth 0 +configure wave -snapdistance 10 +configure wave -datasetprefix 0 +configure wave -rowmargin 4 +configure wave -childrowmargin 2 +configure wave -gridoffset 0 +configure wave -gridperiod 1 +configure wave -griddelta 40 +configure wave -timeline 0 +configure wave -timelineunits ns +update +WaveRestoreZoom {27 ns} {168 ns} + diff --git a/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/project_benches/jtag/sim/work/_info b/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/project_benches/jtag/sim/work/_info new file mode 100644 index 00000000..16b26fbb --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/project_benches/jtag/sim/work/_info @@ -0,0 +1,680 @@ +m255 +K4 +z2 +13 +!s112 1.1 +!i10d 8192 +!i10e 25 +!i10f 100 +cModel Technology +Z0 d/hwetools/work_area/frontend/hemanth_b7/github_dir/UVMF_ch2/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/project_benches/jtag/sim +vhdl_top +Z1 DXx6 sv_std 3 std 0 22 AD7iAPLo6nTIKkLE6@MJe7=2><1 +Z5 !s110 1671527002 +!i10b 1 +!s100 FibF[gTc?OCkl016XZGDZ2 +IbPkANCVo]C@g29bnom@o73 +Z6 VDg1SIo80bB@j0V0VzS_@n1 +!s105 hdl_top_sv_unit +S1 +R0 +Z7 w1671526951 +8/hwetools/work_area/frontend/hemanth_b7/github_dir/UVMF_ch2/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/project_benches/jtag/sim/../tb/testbench/hdl_top.sv +F/hwetools/work_area/frontend/hemanth_b7/github_dir/UVMF_ch2/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/project_benches/jtag/sim/../tb/testbench/hdl_top.sv +L0 24 +Z8 OE;L;10.6c;65 +r1 +!s85 0 +31 +!s108 1671527002.000000 +!s107 /hwetools/work_area/frontend/hemanth_b7/github_dir/UVMF_ch2/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/project_benches/jtag/sim/../tb/testbench/hdl_top.sv| +!s90 -sv|-suppress|2223|-suppress|2286|+define+UVM_REPORT_DISABLE_FILE_LINE|+define+UVM_REPORT_DISABLE_FILE_LINE|+incdir+/hwetools/work_area/frontend/hemanth_b7/github_dir/UVMF_ch2/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/project_benches/jtag/sim/../tb/testbench|-F|/hwetools/work_area/frontend/hemanth_b7/github_dir/UVMF_ch2/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/project_benches/jtag/sim/../tb/testbench/top_filelist_hdl.f| +!i113 0 +Z9 o-suppress 2223 -suppress 2286 -sv -L mtiAvm -L mtiRnm -L mtiOvm -L mtiUvm -L mtiUPF -L infact +!s92 -suppress 2223 -suppress 2286 -sv +define+UVM_REPORT_DISABLE_FILE_LINE +define+UVM_REPORT_DISABLE_FILE_LINE +incdir+/hwetools/work_area/frontend/hemanth_b7/github_dir/UVMF_ch2/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/project_benches/jtag/sim/../tb/testbench -L mtiAvm -L mtiRnm -L mtiOvm -L mtiUvm -L mtiUPF -L infact +Z10 tCvgOpt 0 +vhvl_top +R1 +R4 +R2 +Z11 DXx4 work 13 uvmf_base_pkg 0 22 hbzhf3:;RbM]Qo[lD5;SV1 +R3 +Z12 DXx4 work 12 jtag_pkg_hdl 0 22 =QP0>dM^P7V=hamYR@XmP2 +Z13 DXx4 work 8 jtag_pkg 0 22 7O:b]M6gIkAGAeE^L@9h;3 +Z14 DXx4 work 12 jtag_env_pkg 0 22 GV?^9gGB^a=Q7SnehkJ2m2 +Z15 DXx4 work 18 jtag_sequences_pkg 0 22 :HdCbi<186i^GFZ_^5]I;1 +DXx4 work 14 jtag_tests_pkg 0 22 =KD@[3A9k]PAYKkKhlj5h2 +R5 +!i10b 1 +!s100 aYZX=i^aS4R=bP@_Gi2Q`2 +IJkV=i:Ek9IU1l57WaP]m90 +R6 +!s105 hvl_top_sv_unit +S1 +R0 +R7 +8/hwetools/work_area/frontend/hemanth_b7/github_dir/UVMF_ch2/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/project_benches/jtag/sim/../tb/testbench/hvl_top.sv +F/hwetools/work_area/frontend/hemanth_b7/github_dir/UVMF_ch2/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/project_benches/jtag/sim/../tb/testbench/hvl_top.sv +Z16 L0 16 +R8 +r1 +!s85 0 +31 +Z17 !s108 1671527001.000000 +!s107 /hwetools/work_area/frontend/hemanth_b7/github_dir/UVMF_ch2/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/project_benches/jtag/sim/../tb/testbench/hvl_top.sv| +!s90 -sv|-suppress|2223|-suppress|2286|+define+UVM_REPORT_DISABLE_FILE_LINE|+define+UVM_REPORT_DISABLE_FILE_LINE|+incdir+/questa_mvc_src/sv|+incdir+/hwetools/work_area/frontend/hemanth_b7/github_dir/UVMF_ch2/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/project_benches/jtag/sim/../tb/testbench|-F|/hwetools/work_area/frontend/hemanth_b7/github_dir/UVMF_ch2/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/project_benches/jtag/sim/../tb/testbench/top_filelist_hvl.f| +!i113 0 +R9 +!s92 -suppress 2223 -suppress 2286 -sv +define+UVM_REPORT_DISABLE_FILE_LINE +define+UVM_REPORT_DISABLE_FILE_LINE +incdir+/questa_mvc_src/sv +incdir+/hwetools/work_area/frontend/hemanth_b7/github_dir/UVMF_ch2/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/project_benches/jtag/sim/../tb/testbench -L mtiAvm -L mtiRnm -L mtiOvm -L mtiUvm -L mtiUPF -L infact +R10 +Yjtag_driver_bfm +R1 +R2 +R12 +DXx4 work 23 jtag_driver_bfm_sv_unit 0 22 OU<`F`cJ2`IE[c6i54;fzc14`NM?H?k0 +IfB4cCzDH`n?[23 +I=QP0>dM^P7V=hamYR@XmP2 +V=QP0>dM^P7V=hamYR@XmP2 +S1 +R0 +R18 +8/hwetools/work_area/frontend/hemanth_b7/github_dir/UVMF_ch2/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/verification_ip/interface_packages/jtag_pkg/jtag_pkg_hdl.sv +F/hwetools/work_area/frontend/hemanth_b7/github_dir/UVMF_ch2/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/verification_ip/interface_packages/jtag_pkg/jtag_pkg_hdl.sv +F/hwetools/work_area/frontend/hemanth_b7/github_dir/UVMF_ch2/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/verification_ip/interface_packages/jtag_pkg/src/jtag_typedefs_hdl.svh +R37 +L0 19 +R8 +r1 +!s85 0 +31 +R47 +!s107 /hwetools/work_area/frontend/hemanth_b7/github_dir/UVMF_ch2/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/verification_ip/interface_packages/jtag_pkg/src/jtag_macros.svh|/hwetools/work_area/frontend/hemanth_b7/github_dir/UVMF_ch2/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/verification_ip/interface_packages/jtag_pkg/src/jtag_typedefs_hdl.svh|/hwetools/work_area/frontend/hemanth_b7/github_dir/UVMF_ch2/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/verification_ip/interface_packages/jtag_pkg/jtag_pkg_hdl.sv| +!s90 -sv|-suppress|2223|-suppress|2286|+define+UVM_REPORT_DISABLE_FILE_LINE|+define+UVM_REPORT_DISABLE_FILE_LINE|+incdir+/hwetools/work_area/frontend/hemanth_b7/github_dir/UVMF_ch2/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/verification_ip/interface_packages/jtag_pkg|-F|/hwetools/work_area/frontend/hemanth_b7/github_dir/UVMF_ch2/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/verification_ip/interface_packages/jtag_pkg/jtag_filelist_hdl.f| +!i113 0 +R9 +R36 +R10 +Xjtag_sequences_pkg +R1 +R4 +R2 +R11 +R12 +R13 +R3 +R14 +Z49 !s110 1671527001 +!i10b 1 +!s100 P566>IXCB4Z3`^Vcc`dY_0 +I:HdCbi<186i^GFZ_^5]I;1 +V:HdCbi<186i^GFZ_^5]I;1 +S1 +R0 +R7 +8/hwetools/work_area/frontend/hemanth_b7/github_dir/UVMF_ch2/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/project_benches/jtag/sim/../tb/sequences/jtag_sequences_pkg.sv +F/hwetools/work_area/frontend/hemanth_b7/github_dir/UVMF_ch2/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/project_benches/jtag/sim/../tb/sequences/jtag_sequences_pkg.sv +R21 +R22 +R23 +R24 +R25 +R26 +R27 +R28 +R29 +R30 +R31 +R32 +F/hwetools/work_area/frontend/hemanth_b7/github_dir/UVMF_ch2/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/project_benches/jtag/sim/../tb/sequences/src/jtag_bench_sequence_base.svh +F/hwetools/work_area/frontend/hemanth_b7/github_dir/UVMF_ch2/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/project_benches/jtag/sim/../tb/sequences/src/register_test_sequence.svh +F/hwetools/work_area/frontend/hemanth_b7/github_dir/UVMF_ch2/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/project_benches/jtag/sim/../tb/sequences/src/example_derived_test_sequence.svh +R39 +R8 +r1 +!s85 0 +31 +R46 +!s107 /hwetools/work_area/frontend/hemanth_b7/github_dir/UVMF_ch2/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/project_benches/jtag/sim/../tb/sequences/src/example_derived_test_sequence.svh|/hwetools/work_area/frontend/hemanth_b7/github_dir/UVMF_ch2/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/project_benches/jtag/sim/../tb/sequences/src/register_test_sequence.svh|/hwetools/work_area/frontend/hemanth_b7/github_dir/UVMF_ch2/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/project_benches/jtag/sim/../tb/sequences/src/jtag_bench_sequence_base.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/macros/uvm_deprecated_defines.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/macros/uvm_reg_defines.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/macros/uvm_callback_defines.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/macros/uvm_sequence_defines.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/tlm1/uvm_tlm_imps.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/macros/uvm_tlm_defines.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/macros/uvm_printer_defines.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/macros/uvm_object_defines.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/macros/uvm_phase_defines.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/macros/uvm_message_defines.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/macros/uvm_version_defines.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/uvm_macros.svh|/hwetools/work_area/frontend/hemanth_b7/github_dir/UVMF_ch2/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/project_benches/jtag/sim/../tb/sequences/jtag_sequences_pkg.sv| +!s90 -sv|-suppress|2223|-suppress|2286|+define+UVM_REPORT_DISABLE_FILE_LINE|+define+UVM_REPORT_DISABLE_FILE_LINE|+incdir+/hwetools/work_area/frontend/hemanth_b7/github_dir/UVMF_ch2/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/project_benches/jtag/sim/../tb/sequences|/hwetools/work_area/frontend/hemanth_b7/github_dir/UVMF_ch2/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/project_benches/jtag/sim/../tb/sequences/jtag_sequences_pkg.sv| +!i113 0 +R9 +!s92 -suppress 2223 -suppress 2286 -sv +define+UVM_REPORT_DISABLE_FILE_LINE +define+UVM_REPORT_DISABLE_FILE_LINE +incdir+/hwetools/work_area/frontend/hemanth_b7/github_dir/UVMF_ch2/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/project_benches/jtag/sim/../tb/sequences -L mtiAvm -L mtiRnm -L mtiOvm -L mtiUvm -L mtiUPF -L infact +R10 +Xjtag_tests_pkg +R1 +R4 +R2 +R11 +R3 +R12 +R13 +R14 +R15 +R49 +!i10b 1 +!s100 I32aL5KcbQDHPa1kl3DG>3 +I=KD@[3A9k]PAYKkKhlj5h2 +V=KD@[3A9k]PAYKkKhlj5h2 +S1 +R0 +R7 +8/hwetools/work_area/frontend/hemanth_b7/github_dir/UVMF_ch2/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/project_benches/jtag/sim/../tb/tests/jtag_tests_pkg.sv +F/hwetools/work_area/frontend/hemanth_b7/github_dir/UVMF_ch2/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/project_benches/jtag/sim/../tb/tests/jtag_tests_pkg.sv +R21 +R22 +R23 +R24 +R25 +R26 +R27 +R28 +R29 +R30 +R31 +R32 +F/hwetools/work_area/frontend/hemanth_b7/github_dir/UVMF_ch2/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/project_benches/jtag/sim/../tb/tests/src/test_top.svh +F/hwetools/work_area/frontend/hemanth_b7/github_dir/UVMF_ch2/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/project_benches/jtag/sim/../tb/tests/src/register_test.svh +F/hwetools/work_area/frontend/hemanth_b7/github_dir/UVMF_ch2/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/project_benches/jtag/sim/../tb/tests/src/example_derived_test.svh +L0 21 +R8 +r1 +!s85 0 +31 +R17 +!s107 /hwetools/work_area/frontend/hemanth_b7/github_dir/UVMF_ch2/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/project_benches/jtag/sim/../tb/tests/src/example_derived_test.svh|/hwetools/work_area/frontend/hemanth_b7/github_dir/UVMF_ch2/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/project_benches/jtag/sim/../tb/tests/src/register_test.svh|/hwetools/work_area/frontend/hemanth_b7/github_dir/UVMF_ch2/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/project_benches/jtag/sim/../tb/tests/src/test_top.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/macros/uvm_deprecated_defines.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/macros/uvm_reg_defines.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/macros/uvm_callback_defines.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/macros/uvm_sequence_defines.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/tlm1/uvm_tlm_imps.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/macros/uvm_tlm_defines.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/macros/uvm_printer_defines.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/macros/uvm_object_defines.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/macros/uvm_phase_defines.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/macros/uvm_message_defines.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/macros/uvm_version_defines.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/uvm_macros.svh|/hwetools/work_area/frontend/hemanth_b7/github_dir/UVMF_ch2/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/project_benches/jtag/sim/../tb/tests/jtag_tests_pkg.sv| +!s90 -sv|-suppress|2223|-suppress|2286|+define+UVM_REPORT_DISABLE_FILE_LINE|+define+UVM_REPORT_DISABLE_FILE_LINE|+incdir+/hwetools/work_area/frontend/hemanth_b7/github_dir/UVMF_ch2/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/project_benches/jtag/sim/../tb/tests|/hwetools/work_area/frontend/hemanth_b7/github_dir/UVMF_ch2/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/project_benches/jtag/sim/../tb/tests/jtag_tests_pkg.sv| +!i113 0 +R9 +!s92 -suppress 2223 -suppress 2286 -sv +define+UVM_REPORT_DISABLE_FILE_LINE +define+UVM_REPORT_DISABLE_FILE_LINE +incdir+/hwetools/work_area/frontend/hemanth_b7/github_dir/UVMF_ch2/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/project_benches/jtag/sim/../tb/tests -L mtiAvm -L mtiRnm -L mtiOvm -L mtiUvm -L mtiUPF -L infact +R10 +Toptimized_batch_top_tb +!s110 1671527003 +ViQWj223Zl3T2>I70eK2Ce0 +Z50 04 7 4 work hvl_top fast 0 +Z51 04 7 4 work hdl_top fast 0 +o +R10 +noptimized_batch_top_tb +Z52 OE;O;10.6c;65 +R0 +Toptimized_debug_top_tb +!s110 1671527004 +V^hGob?P1WMPi7O16dG7^E2 +R50 +R51 +o+acc +R10 +noptimized_debug_top_tb +R52 +Xuvmf_base_pkg +R1 +R4 +R2 +R48 +!i10b 1 +!s100 aZaFYJKjJI1f]L:MSl:9<2 +Ihbzhf3:;RbM]Qo[lD5;SV1 +Vhbzhf3:;RbM]Qo[lD5;SV1 +S1 +R0 +Z53 w1671525286 +8/hwetools/work_area/frontend/hemanth_b7/github_dir/UVMF_ch2/UVM_Framework/UVMF_2022.3/uvmf_base_pkg/uvmf_base_pkg.sv +F/hwetools/work_area/frontend/hemanth_b7/github_dir/UVMF_ch2/UVM_Framework/UVMF_2022.3/uvmf_base_pkg/uvmf_base_pkg.sv +R21 +R22 +R23 +R24 +R25 +R26 +R27 +R28 +R29 +R30 +R31 +R32 +F/hwetools/work_area/frontend/hemanth_b7/github_dir/UVMF_ch2/UVM_Framework/UVMF_2022.3/uvmf_base_pkg/src/uvmf_version.svh +F/hwetools/work_area/frontend/hemanth_b7/github_dir/UVMF_ch2/UVM_Framework/UVMF_2022.3/uvmf_base_pkg/src/uvmf_base_typedefs.svh +F/hwetools/work_area/frontend/hemanth_b7/github_dir/UVMF_ch2/UVM_Framework/UVMF_2022.3/uvmf_base_pkg/src/uvmf_transaction_base.svh +F/hwetools/work_area/frontend/hemanth_b7/github_dir/UVMF_ch2/UVM_Framework/UVMF_2022.3/uvmf_base_pkg/src/uvmf_sequence_base.svh +F/hwetools/work_area/frontend/hemanth_b7/github_dir/UVMF_ch2/UVM_Framework/UVMF_2022.3/uvmf_base_pkg/src/uvmf_scoreboard_base.svh +F/hwetools/work_area/frontend/hemanth_b7/github_dir/UVMF_ch2/UVM_Framework/UVMF_2022.3/uvmf_base_pkg/src/uvmf_in_order_scoreboard.svh +F/hwetools/work_area/frontend/hemanth_b7/github_dir/UVMF_ch2/UVM_Framework/UVMF_2022.3/uvmf_base_pkg/src/uvmf_in_order_race_scoreboard.svh +F/hwetools/work_area/frontend/hemanth_b7/github_dir/UVMF_ch2/UVM_Framework/UVMF_2022.3/uvmf_base_pkg/src/uvmf_in_order_race_scoreboard_array.svh +F/hwetools/work_area/frontend/hemanth_b7/github_dir/UVMF_ch2/UVM_Framework/UVMF_2022.3/uvmf_base_pkg/src/uvmf_out_of_order_scoreboard.svh +F/hwetools/work_area/frontend/hemanth_b7/github_dir/UVMF_ch2/UVM_Framework/UVMF_2022.3/uvmf_base_pkg/src/uvmf_out_of_order_race_scoreboard.svh +F/hwetools/work_area/frontend/hemanth_b7/github_dir/UVMF_ch2/UVM_Framework/UVMF_2022.3/uvmf_base_pkg/src/uvmf_in_order_scoreboard_array.svh +F/hwetools/work_area/frontend/hemanth_b7/github_dir/UVMF_ch2/UVM_Framework/UVMF_2022.3/uvmf_base_pkg/src/uvmf_catapult_scoreboard.svh +F/hwetools/work_area/frontend/hemanth_b7/github_dir/UVMF_ch2/UVM_Framework/UVMF_2022.3/uvmf_base_pkg/src/uvmf_predictor_base.svh +F/hwetools/work_area/frontend/hemanth_b7/github_dir/UVMF_ch2/UVM_Framework/UVMF_2022.3/uvmf_base_pkg/src/uvmf_sorting_predictor_base.svh +F/hwetools/work_area/frontend/hemanth_b7/github_dir/UVMF_ch2/UVM_Framework/UVMF_2022.3/uvmf_base_pkg/src/uvmf_parameterized_agent_configuration_base.svh +F/hwetools/work_area/frontend/hemanth_b7/github_dir/UVMF_ch2/UVM_Framework/UVMF_2022.3/uvmf_base_pkg/src/uvmf_driver_base.svh +F/hwetools/work_area/frontend/hemanth_b7/github_dir/UVMF_ch2/UVM_Framework/UVMF_2022.3/uvmf_base_pkg/src/uvmf_monitor_base.svh +F/hwetools/work_area/frontend/hemanth_b7/github_dir/UVMF_ch2/UVM_Framework/UVMF_2022.3/uvmf_base_pkg/src/uvmf_parameterized_agent.svh +F/hwetools/work_area/frontend/hemanth_b7/github_dir/UVMF_ch2/UVM_Framework/UVMF_2022.3/uvmf_base_pkg/src/uvmf_virtual_sequencer_base.svh +F/hwetools/work_area/frontend/hemanth_b7/github_dir/UVMF_ch2/UVM_Framework/UVMF_2022.3/uvmf_base_pkg/src/uvmf_virtual_sequence_base.svh +F/hwetools/work_area/frontend/hemanth_b7/github_dir/UVMF_ch2/UVM_Framework/UVMF_2022.3/uvmf_base_pkg/src/uvmf_environment_configuration_base.svh +F/hwetools/work_area/frontend/hemanth_b7/github_dir/UVMF_ch2/UVM_Framework/UVMF_2022.3/uvmf_base_pkg/src/uvmf_environment_base.svh +F/hwetools/work_area/frontend/hemanth_b7/github_dir/UVMF_ch2/UVM_Framework/UVMF_2022.3/uvmf_base_pkg/src/uvmf_parameterized_simplex_environment.svh +F/hwetools/work_area/frontend/hemanth_b7/github_dir/UVMF_ch2/UVM_Framework/UVMF_2022.3/uvmf_base_pkg/src/uvmf_parameterized_1agent_environment.svh +F/hwetools/work_area/frontend/hemanth_b7/github_dir/UVMF_ch2/UVM_Framework/UVMF_2022.3/uvmf_base_pkg/src/uvmf_parameterized_2agent_environment.svh +F/hwetools/work_area/frontend/hemanth_b7/github_dir/UVMF_ch2/UVM_Framework/UVMF_2022.3/uvmf_base_pkg/src/uvmf_parameterized_3agent_environment.svh +F/hwetools/work_area/frontend/hemanth_b7/github_dir/UVMF_ch2/UVM_Framework/UVMF_2022.3/uvmf_base_pkg/src/uvmf_test_base.svh +L0 65 +R8 +r1 +!s85 0 +31 +R47 +!s107 /hwetools/work_area/frontend/hemanth_b7/github_dir/UVMF_ch2/UVM_Framework/UVMF_2022.3/uvmf_base_pkg/src/uvmf_test_base.svh|/hwetools/work_area/frontend/hemanth_b7/github_dir/UVMF_ch2/UVM_Framework/UVMF_2022.3/uvmf_base_pkg/src/uvmf_parameterized_3agent_environment.svh|/hwetools/work_area/frontend/hemanth_b7/github_dir/UVMF_ch2/UVM_Framework/UVMF_2022.3/uvmf_base_pkg/src/uvmf_parameterized_2agent_environment.svh|/hwetools/work_area/frontend/hemanth_b7/github_dir/UVMF_ch2/UVM_Framework/UVMF_2022.3/uvmf_base_pkg/src/uvmf_parameterized_1agent_environment.svh|/hwetools/work_area/frontend/hemanth_b7/github_dir/UVMF_ch2/UVM_Framework/UVMF_2022.3/uvmf_base_pkg/src/uvmf_parameterized_simplex_environment.svh|/hwetools/work_area/frontend/hemanth_b7/github_dir/UVMF_ch2/UVM_Framework/UVMF_2022.3/uvmf_base_pkg/src/uvmf_environment_base.svh|/hwetools/work_area/frontend/hemanth_b7/github_dir/UVMF_ch2/UVM_Framework/UVMF_2022.3/uvmf_base_pkg/src/uvmf_environment_configuration_base.svh|/hwetools/work_area/frontend/hemanth_b7/github_dir/UVMF_ch2/UVM_Framework/UVMF_2022.3/uvmf_base_pkg/src/uvmf_virtual_sequence_base.svh|/hwetools/work_area/frontend/hemanth_b7/github_dir/UVMF_ch2/UVM_Framework/UVMF_2022.3/uvmf_base_pkg/src/uvmf_virtual_sequencer_base.svh|/hwetools/work_area/frontend/hemanth_b7/github_dir/UVMF_ch2/UVM_Framework/UVMF_2022.3/uvmf_base_pkg/src/uvmf_parameterized_agent.svh|/hwetools/work_area/frontend/hemanth_b7/github_dir/UVMF_ch2/UVM_Framework/UVMF_2022.3/uvmf_base_pkg/src/uvmf_monitor_base.svh|/hwetools/work_area/frontend/hemanth_b7/github_dir/UVMF_ch2/UVM_Framework/UVMF_2022.3/uvmf_base_pkg/src/uvmf_driver_base.svh|/hwetools/work_area/frontend/hemanth_b7/github_dir/UVMF_ch2/UVM_Framework/UVMF_2022.3/uvmf_base_pkg/src/uvmf_parameterized_agent_configuration_base.svh|/hwetools/work_area/frontend/hemanth_b7/github_dir/UVMF_ch2/UVM_Framework/UVMF_2022.3/uvmf_base_pkg/src/uvmf_sorting_predictor_base.svh|/hwetools/work_area/frontend/hemanth_b7/github_dir/UVMF_ch2/UVM_Framework/UVMF_2022.3/uvmf_base_pkg/src/uvmf_predictor_base.svh|/hwetools/work_area/frontend/hemanth_b7/github_dir/UVMF_ch2/UVM_Framework/UVMF_2022.3/uvmf_base_pkg/src/uvmf_catapult_scoreboard.svh|/hwetools/work_area/frontend/hemanth_b7/github_dir/UVMF_ch2/UVM_Framework/UVMF_2022.3/uvmf_base_pkg/src/uvmf_in_order_scoreboard_array.svh|/hwetools/work_area/frontend/hemanth_b7/github_dir/UVMF_ch2/UVM_Framework/UVMF_2022.3/uvmf_base_pkg/src/uvmf_out_of_order_race_scoreboard.svh|/hwetools/work_area/frontend/hemanth_b7/github_dir/UVMF_ch2/UVM_Framework/UVMF_2022.3/uvmf_base_pkg/src/uvmf_out_of_order_scoreboard.svh|/hwetools/work_area/frontend/hemanth_b7/github_dir/UVMF_ch2/UVM_Framework/UVMF_2022.3/uvmf_base_pkg/src/uvmf_in_order_race_scoreboard_array.svh|/hwetools/work_area/frontend/hemanth_b7/github_dir/UVMF_ch2/UVM_Framework/UVMF_2022.3/uvmf_base_pkg/src/uvmf_in_order_race_scoreboard.svh|/hwetools/work_area/frontend/hemanth_b7/github_dir/UVMF_ch2/UVM_Framework/UVMF_2022.3/uvmf_base_pkg/src/uvmf_in_order_scoreboard.svh|/hwetools/work_area/frontend/hemanth_b7/github_dir/UVMF_ch2/UVM_Framework/UVMF_2022.3/uvmf_base_pkg/src/uvmf_scoreboard_base.svh|/hwetools/work_area/frontend/hemanth_b7/github_dir/UVMF_ch2/UVM_Framework/UVMF_2022.3/uvmf_base_pkg/src/uvmf_sequence_base.svh|/hwetools/work_area/frontend/hemanth_b7/github_dir/UVMF_ch2/UVM_Framework/UVMF_2022.3/uvmf_base_pkg/src/uvmf_transaction_base.svh|/hwetools/work_area/frontend/hemanth_b7/github_dir/UVMF_ch2/UVM_Framework/UVMF_2022.3/uvmf_base_pkg/src/uvmf_base_typedefs.svh|/hwetools/work_area/frontend/hemanth_b7/github_dir/UVMF_ch2/UVM_Framework/UVMF_2022.3/uvmf_base_pkg/src/uvmf_version.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/macros/uvm_deprecated_defines.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/macros/uvm_reg_defines.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/macros/uvm_callback_defines.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/macros/uvm_sequence_defines.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/tlm1/uvm_tlm_imps.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/macros/uvm_tlm_defines.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/macros/uvm_printer_defines.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/macros/uvm_object_defines.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/macros/uvm_phase_defines.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/macros/uvm_message_defines.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/macros/uvm_version_defines.svh|/tools/mentor/questasim_10.6c/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src/uvm_macros.svh|/hwetools/work_area/frontend/hemanth_b7/github_dir/UVMF_ch2/UVM_Framework/UVMF_2022.3/uvmf_base_pkg/uvmf_base_pkg.sv| +!s90 -sv|-suppress|2223|-suppress|2286|+define+UVM_REPORT_DISABLE_FILE_LINE|+define+UVM_REPORT_DISABLE_FILE_LINE|+incdir+/hwetools/work_area/frontend/hemanth_b7/github_dir/UVMF_ch2/UVM_Framework/UVMF_2022.3/uvmf_base_pkg|-F|/hwetools/work_area/frontend/hemanth_b7/github_dir/UVMF_ch2/UVM_Framework/UVMF_2022.3/uvmf_base_pkg/uvmf_base_pkg_filelist_hvl.f| +!i113 0 +R9 +Z54 !s92 -suppress 2223 -suppress 2286 -sv +define+UVM_REPORT_DISABLE_FILE_LINE +define+UVM_REPORT_DISABLE_FILE_LINE +incdir+/hwetools/work_area/frontend/hemanth_b7/github_dir/UVMF_ch2/UVM_Framework/UVMF_2022.3/uvmf_base_pkg -L mtiAvm -L mtiRnm -L mtiOvm -L mtiUvm -L mtiUPF -L infact +R10 +Xuvmf_base_pkg_hdl +R1 +R48 +!i10b 1 +!s100 N^6_:OJbGczhbSBTX23QOg0 +R6 +!s105 verilog_dut_v_unit +S1 +R0 +R7 +8/hwetools/work_area/frontend/hemanth_b7/github_dir/UVMF_ch2/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/project_benches/jtag/sim/../rtl/verilog/verilog_dut.v +F/hwetools/work_area/frontend/hemanth_b7/github_dir/UVMF_ch2/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/project_benches/jtag/sim/../rtl/verilog/verilog_dut.v +L0 1 +R8 +r1 +!s85 0 +31 +R47 +!s107 /hwetools/work_area/frontend/hemanth_b7/github_dir/UVMF_ch2/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/project_benches/jtag/sim/../rtl/verilog/verilog_dut.v| +!s90 -sv|-suppress|2223|-suppress|2286|+define+UVM_REPORT_DISABLE_FILE_LINE|+define+UVM_REPORT_DISABLE_FILE_LINE|/hwetools/work_area/frontend/hemanth_b7/github_dir/UVMF_ch2/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/project_benches/jtag/sim/../rtl/verilog/verilog_dut.v| +!i113 0 +R9 +!s92 -suppress 2223 -suppress 2286 -sv +define+UVM_REPORT_DISABLE_FILE_LINE +define+UVM_REPORT_DISABLE_FILE_LINE -L mtiAvm -L mtiRnm -L mtiOvm -L mtiUvm -L mtiUPF -L infact +R10 +Evhdl_dut +R7 +Z55 DPx3 std 6 textio 0 22 zE1`LPoLg^DX3Oz^4Fj1K3 +Z56 DPx4 ieee 14 std_logic_1164 0 22 eNV`TJ_GofJTzYa?f<@Oe1 +R0 +Z57 8/hwetools/work_area/frontend/hemanth_b7/github_dir/UVMF_ch2/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/project_benches/jtag/sim/../rtl/vhdl/vhdl_dut.vhd +Z58 F/hwetools/work_area/frontend/hemanth_b7/github_dir/UVMF_ch2/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/project_benches/jtag/sim/../rtl/vhdl/vhdl_dut.vhd +l0 +L4 +V4_]Q6fT]^UP;BkHShHi9j2 +!s100 YHiX09^FS?9c7;MH[92@@2 +Z59 OE;C;10.6c;65 +32 +R48 +!i10b 1 +Z60 !s108 1671526996.000000 +Z61 !s90 /hwetools/work_area/frontend/hemanth_b7/github_dir/UVMF_ch2/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/project_benches/jtag/sim/../rtl/vhdl/vhdl_dut.vhd| +Z62 !s107 /hwetools/work_area/frontend/hemanth_b7/github_dir/UVMF_ch2/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/project_benches/jtag/sim/../rtl/vhdl/vhdl_dut.vhd| +!i113 0 +Z63 tExplicit 1 CvgOpt 0 +Artl +R55 +R56 +DEx4 work 8 vhdl_dut 0 22 4_]Q6fT]^UP;BkHShHi9j2 +l13 +L12 +VD8Z[WTM3SDlI +112 4 +size +177 19 +uvm_pkg::uvm_path_e +212 32 +uvm_default_sequencer_param_type +183 24 +uvm_pkg::uvm_elem_kind_e +106 27 +uvm_pkg::uvm_config_wrapper +266 15 +uvm_hdl_release +94 26 +uvm_pkg::uvm_config_string +187 19 +uvm_pkg::uvm_hier_e +264 13 +uvm_hdl_force +221 53 +uvm_pkg:: +59 23 +uvm_active_passive_enum +197 23 +uvm_pkg::uvm_config_seq +199 30 +uvm_pkg::uvm_virtual_sequencer +85 17 +uvm_id_file_array +203 56 +uvm_pkg:: +240 53 + +32 24 +uvm_pkg::uvm_mem_cb_iter +144 11 +value_width +253 4 +preg +165 26 +uvm_pkg::uvm_reg_byte_en_t +70 22 +uvm_pkg::uvm_verbosity +107 20 +uvm_printer_row_info +20 50 +uvm_pkg:: +95 17 +uvm_config_object +210 23 +uvm_default_driver_type +245 57 +uvm_pkg:: +236 48 + +33 16 +uvm_reg_field_cb +198 21 +uvm_virtual_sequencer +214 17 +uvm_tlm_command_e +17 7 +byte_en +6 22 +uvm_reg_map_addr_range +180 16 +uvm_endianness_e +204 43 + +225 49 +uvm_pkg:: +256 17 +uvm_dump_re_cache +104 45 +uvm_pkg:: +28 27 +uvm_pkg::uvm_reg_bd_cb_iter +237 57 +uvm_pkg:: +122 10 +identifier +244 48 + +71 15 +uvm_port_type_e +163 29 +uvm_pkg::uvm_reg_addr_logic_t +37 17 +uvm_vreg_field_cb +220 44 + +255 15 +uvm_dpi_regfree +43 11 +uvm_vreg_cb +247 46 +verilog_src/uvm-1.1d/src/dpi/uvm_svcmd_dpi.svh +161 28 +uvm_pkg::uvm_reg_mem_tests_e +11 14 +uvm_reg_bus_op +263 5 +value +88 33 +uvm_pkg::uvm_id_verbosities_array +218 13 +uvm_apprepend +190 19 +uvm_objection_event +158 14 +uvm_tlm_sync_e +159 23 +uvm_pkg::uvm_tlm_sync_e +136 9 +oct_radix +68 24 +uvm_pkg::uvm_action_type +64 26 +uvm_pkg::uvm_severity_type +14 4 +addr +267 24 +uvm_hdl_release_and_read +102 44 +uvm_pkg:: +142 10 +type_width +58 34 +uvm_pkg::uvm_recursion_policy_enum +189 22 +uvm_pkg::uvm_predict_e +18 6 +status +91 14 +uvm_config_int +56 23 +uvm_pkg::uvm_radix_enum +110 4 +name +160 19 +uvm_reg_mem_tests_e +50 59 +uvm_pkg:: +174 12 +uvm_status_e +192 19 +uvm_heartbeat_modes +223 55 +uvm_pkg:: +41 49 + +171 6 +offset +156 15 +uvm_tlm_phase_e +146 20 +uvm_pack_bitstream_t +84 29 +uvm_pkg::uvm_phase_transition +55 14 +uvm_radix_enum +115 31 +uvm_pkg::uvm_tree_printer_knobs +27 18 +uvm_reg_bd_cb_iter +200 42 + +83 20 +uvm_phase_transition +238 49 + +227 57 +uvm_pkg:: +73 12 +SEQ_ARB_TYPE +215 26 +uvm_pkg::uvm_tlm_command_e +164 17 +uvm_reg_byte_en_t +138 9 +hex_radix +242 47 + +224 40 + +87 24 +uvm_id_verbosities_array +86 26 +uvm_pkg::uvm_id_file_array +259 4 +glob +24 24 +uvm_pkg::uvm_reg_cb_iter +181 25 +uvm_pkg::uvm_endianness_e +149 22 +uvm_pkg::uvm_report_cb +67 15 +uvm_action_type +46 25 +uvm_pkg::uvm_vreg_cb_iter +172 19 +uvm_reg_cvr_rsrc_db +246 22 +uvm_dpi_get_next_arg_c +57 25 +uvm_recursion_policy_enum +61 14 + +229 51 +uvm_pkg:: +81 15 +uvm_phase_state +31 15 +uvm_mem_cb_iter +195 28 +uvm_pkg::uvm_heartbeat_cbs_t +185 21 +uvm_pkg::uvm_access_e +38 26 +uvm_pkg::uvm_vreg_field_cb +131 9 +separator +79 14 +uvm_phase_type +53 14 + +12 23 +uvm_pkg::uvm_reg_bus_op +111 9 +type_name +132 10 +show_radix +157 24 +uvm_pkg::uvm_tlm_phase_e +206 25 +uvm_default_sequence_type +49 50 + +128 6 +indent +150 18 +uvm_report_cb_iter +216 14 +uvm_hdl_data_t +116 6 +#vtbl# +147 29 +uvm_pkg::uvm_pack_bitstream_t +141 10 +name_width +269 2 +re +205 52 +uvm_pkg:: +230 48 + +228 42 + +82 24 +uvm_pkg::uvm_phase_state +105 18 +uvm_config_wrapper +123 5 +depth +15 4 +data +201 51 +uvm_pkg:: +98 28 +uvm_pkg::uvm_objection_cbs_t +42 58 +uvm_pkg:: +139 9 +max_width +168 18 +uvm_hdl_path_slice +151 27 +uvm_pkg::uvm_report_cb_iter +226 48 + +119 6 +header +7 31 +uvm_pkg::uvm_reg_map_addr_range +2 11 +uvm_wait_op +13 4 +kind +143 10 +size_width +176 10 +uvm_path_e +251 5 +regex +129 9 +show_root +193 28 +uvm_pkg::uvm_heartbeat_modes +16 6 +n_bits +54 23 +uvm_pkg:: +261 40 +verilog_src/uvm-1.1d/src/dpi/uvm_hdl.svh +208 26 +uvm_default_sequencer_type +170 4 +path +66 23 +uvm_pkg:: +249 26 +uvm_dpi_get_tool_version_c +207 34 +uvm_pkg::uvm_default_sequence_type +29 10 +uvm_mem_cb +178 11 +uvm_check_e +134 9 +dec_radix +5 23 +uvm_pkg::uvm_event_pool +75 23 +uvm_sequence_state_enum +9 3 +max +260 18 +uvm_hdl_check_path +10 6 +stride +222 46 + +196 14 +uvm_config_seq +191 28 +uvm_pkg::uvm_objection_event +234 46 + +101 35 + +179 20 +uvm_pkg::uvm_check_e +130 3 +mcd +52 25 +uvm_pkg::uvm_barrier_pool +78 30 +uvm_pkg::uvm_sequence_lib_mode +99 38 + +166 20 +uvm_coverage_model_e +96 26 +uvm_pkg::uvm_config_object +103 36 + +217 23 +uvm_pkg::uvm_hdl_data_t +60 32 +uvm_pkg::uvm_active_passive_enum +154 25 +uvm_tlm_response_status_e +30 19 +uvm_pkg::uvm_mem_cb +202 47 + +93 17 +uvm_config_string +1 23 +uvm_pkg:: +26 22 +uvm_pkg::uvm_reg_bd_cb +80 23 +uvm_pkg::uvm_phase_type +175 21 +uvm_pkg::uvm_status_e +135 9 +bin_radix +0 14 + +118 6 +#ciid# +231 57 +uvm_pkg:: +219 22 +uvm_pkg::uvm_apprepend +209 35 +uvm_pkg::uvm_default_sequencer_type +257 42 +verilog_src/uvm-1.1d/src/dpi/uvm_regex.svh +232 42 + +133 13 +default_radix +169 27 +uvm_pkg::uvm_hdl_path_slice +127 6 +prefix +248 23 +uvm_dpi_get_tool_name_c +235 55 +uvm_pkg:: +114 22 +uvm_tree_printer_knobs +233 51 +uvm_pkg:: +243 56 +uvm_pkg:: +173 28 +uvm_pkg::uvm_reg_cvr_rsrc_db +34 25 +uvm_pkg::uvm_reg_field_cb +3 20 +uvm_pkg::uvm_wait_op +213 41 +uvm_pkg::uvm_default_sequencer_param_type +40 31 +uvm_pkg::uvm_vreg_field_cb_iter +39 22 +uvm_vreg_field_cb_iter +126 12 +end_elements +258 14 +uvm_glob_to_re +137 14 +unsigned_radix +65 14 + +100 47 +uvm_pkg:: +22 19 +uvm_pkg::uvm_reg_cb +23 15 +uvm_reg_cb_iter +153 29 +uvm_pkg::uvm_id_actions_array +69 13 +uvm_verbosity +145 6 +sprint +265 12 +uvm_hdl_read +120 6 +footer +250 15 +uvm_dpi_regcomp +152 20 +uvm_id_actions_array +63 17 +uvm_severity_type +44 20 +uvm_pkg::uvm_vreg_cb +19 41 + +194 19 +uvm_heartbeat_cbs_t +35 21 +uvm_reg_field_cb_iter +90 31 +uvm_pkg::uvm_sev_override_array +162 20 +uvm_reg_addr_logic_t +239 58 +uvm_pkg:: +45 16 +uvm_vreg_cb_iter +8 3 +min +48 52 +uvm_pkg:: +140 10 +truncation +77 21 +uvm_sequence_lib_mode +254 3 +str +108 29 +uvm_pkg::uvm_printer_row_info +36 30 +uvm_pkg::uvm_reg_field_cb_iter +241 62 +uvm_pkg:: +76 32 +uvm_pkg::uvm_sequence_state_enum +74 21 +uvm_pkg::SEQ_ARB_TYPE +89 22 +uvm_sev_override_array +167 29 +uvm_pkg::uvm_coverage_model_e +182 15 +uvm_elem_kind_e +211 32 +uvm_pkg::uvm_default_driver_type +109 5 +level +21 10 +uvm_reg_cb +47 43 + +25 13 +uvm_reg_bd_cb +4 14 +uvm_event_pool +72 24 +uvm_pkg::uvm_port_type_e +117 12 +#rand_state# +113 3 +val +262 15 +uvm_hdl_deposit +268 12 +uvm_re_match +121 9 +full_name +125 14 +begin_elements +124 9 +reference +SYM_END +TYPEDEF_BEGIN 100 +0 52 +0 -1 1 0x0 1 0 52 16 1 4 17413 0 0 0 -1 0 0 0x1 1 0 +2 56 +2 -1 3 0x0 1 0 12 0 -1 4 278571 32 0 31 31 0 32 0x1 2 0 +4 81 +4 -1 5 0x0 1 0 24 0 1 4 33 32 0 0 0 0 0x0 1 0 22 0 1 8 9 1 0 0 0 0 1 0x1 0x1 3 0 +6 236 +6 -1 7 0x0 1 0 2 0 0 20 41 160 3 3 0 0 0x2 1 3 8 96 0x0 1 0 12 0 -1 8 262185 64 0 63 63 0 64 0x1 0 0 0 -1 9 32 0x0 1 0 12 0 -1 8 262185 64 0 63 63 0 64 0x1 0 0 0 -1 10 0 0x0 1 0 12 0 -1 4 278569 32 0 31 31 0 32 0x1 0 0 0 -1 0x3 0x1 4 0 +11 414 +11 -1 12 0x0 1 0 2 0 0 40 1 232 6 6 0 0 0x2 1 6 13 0 0x0 1 0 12 0 -1 4 278571 32 0 31 31 0 32 0x1 0 0 0 -1 14 8 0x0 1 0 12 0 -1 8 262185 64 0 63 63 0 64 0x1 0 0 0 -1 15 16 0x0 1 0 12 0 -1 8 262185 64 0 63 63 0 64 0x1 0 0 0 -1 16 24 0x0 1 0 12 0 -1 4 278571 32 0 31 31 0 32 0x1 0 0 0 -1 17 28 0x0 1 0 12 0 -1 1 262185 8 0 7 7 0 8 0x1 0 0 0 -1 18 32 0x0 1 0 12 0 -1 4 278571 32 0 31 31 0 32 0x1 0 0 0 -1 0x3 0x1 5 0 +19 83 +19 -1 20 0x0 1 0 24 0 1 4 33 32 0 0 0 0 0x0 1 0 22 0 1 8 9 1 0 0 0 0 1 0x1 0x1 6 0 +21 83 +21 -1 22 0x0 1 0 24 0 1 4 33 32 0 0 0 0 0x0 1 0 22 0 1 8 9 1 0 0 0 0 1 0x1 0x1 7 0 +23 83 +23 -1 24 0x0 1 0 24 0 1 4 33 32 0 0 0 0 0x0 1 0 22 0 1 8 9 1 0 0 0 0 1 0x1 0x1 8 0 +25 83 +25 -1 26 0x0 1 0 24 0 1 4 33 32 0 0 0 0 0x0 1 0 22 0 1 8 9 1 0 0 0 0 1 0x1 0x1 9 0 +27 84 +27 -1 28 0x0 1 0 24 0 1 4 33 32 0 0 0 0 0x0 1 0 22 0 1 8 9 1 0 0 0 0 1 0x1 0x1 10 0 +29 84 +29 -1 30 0x0 1 0 24 0 1 4 33 32 0 0 0 0 0x0 1 0 22 0 1 8 9 1 0 0 0 0 1 0x1 0x1 11 0 +31 84 +31 -1 32 0x0 1 0 24 0 1 4 33 32 0 0 0 0 0x0 1 0 22 0 1 8 9 1 0 0 0 0 1 0x1 0x1 12 0 +33 84 +33 -1 34 0x0 1 0 24 0 1 4 33 32 0 0 0 0 0x0 1 0 22 0 1 8 9 1 0 0 0 0 1 0x1 0x1 13 0 +35 84 +35 -1 36 0x0 1 0 24 0 1 4 33 32 0 0 0 0 0x0 1 0 22 0 1 8 9 1 0 0 0 0 1 0x1 0x1 14 0 +37 84 +37 -1 38 0x0 1 0 24 0 1 4 33 32 0 0 0 0 0x0 1 0 22 0 1 8 9 1 0 0 0 0 1 0x1 0x1 15 0 +39 84 +39 -1 40 0x0 1 0 24 0 1 4 33 32 0 0 0 0 0x0 1 0 22 0 1 8 9 1 0 0 0 0 1 0x1 0x1 16 0 +41 84 +41 -1 42 0x0 1 0 24 0 1 4 33 32 0 0 0 0 0x0 1 0 22 0 1 8 9 1 0 0 0 0 1 0x1 0x1 17 0 +43 84 +43 -1 44 0x0 1 0 24 0 1 4 33 32 0 0 0 0 0x0 1 0 22 0 1 8 9 1 0 0 0 0 1 0x1 0x1 18 0 +45 84 +45 -1 46 0x0 1 0 24 0 1 4 33 32 0 0 0 0 0x0 1 0 22 0 1 8 9 1 0 0 0 0 1 0x1 0x1 19 0 +47 84 +47 -1 48 0x0 1 0 24 0 1 4 33 32 0 0 0 0 0x0 1 0 22 0 1 8 9 1 0 0 0 0 1 0x1 0x1 20 0 +49 84 +49 -1 50 0x0 1 0 24 0 1 4 33 32 0 0 0 0 0x0 1 0 22 0 1 8 9 1 0 0 0 0 1 0x1 0x1 21 0 +51 84 +51 -1 52 0x0 1 0 24 0 1 4 33 32 0 0 0 0 0x0 1 0 22 0 1 8 9 1 0 0 0 0 1 0x1 0x1 22 0 +53 70 +53 -1 54 0x0 1 0 10 0 -1 1024 262155 4096 0 4095 4095 0 4096 0x1 23 0 +55 59 +55 -1 56 0x0 1 0 12 0 -1 4 278571 32 0 31 31 0 32 0x1 24 0 +57 59 +57 -1 58 0x0 1 0 12 0 -1 4 278571 32 0 31 31 0 32 0x1 25 0 +59 50 +59 -1 60 0x0 1 0 12 0 1 4 41 1 0 0 0 0 1 0x1 26 0 +61 55 +61 -1 62 0x0 1 0 12 0 -1 1 262185 2 0 1 1 0 2 0x1 27 0 +63 55 +63 -1 64 0x0 1 0 12 0 -1 4 262185 2 0 1 1 0 2 0x1 28 0 +65 59 +65 -1 66 0x0 1 0 12 0 -1 4 278571 32 0 31 31 0 32 0x1 29 0 +67 59 +67 -1 68 0x0 1 0 12 0 -1 4 278571 32 0 31 31 0 32 0x1 30 0 +69 59 +69 -1 70 0x0 1 0 12 0 -1 4 278571 32 0 31 31 0 32 0x1 31 0 +71 59 +71 -1 72 0x0 1 0 12 0 -1 4 278571 32 0 31 31 0 32 0x1 32 0 +73 59 +73 -1 74 0x0 1 0 12 0 -1 4 278571 32 0 31 31 0 32 0x1 33 0 +75 59 +75 -1 76 0x0 1 0 12 0 -1 4 278571 32 0 31 31 0 32 0x1 34 0 +77 59 +77 -1 78 0x0 1 0 12 0 -1 4 278571 32 0 31 31 0 32 0x1 35 0 +79 59 +79 -1 80 0x0 1 0 12 0 -1 4 278571 32 0 31 31 0 32 0x1 36 0 +81 59 +81 -1 82 0x0 1 0 12 0 -1 4 278571 32 0 31 31 0 32 0x1 37 0 +83 59 +83 -1 84 0x0 1 0 12 0 -1 4 278571 32 0 31 31 0 32 0x1 38 0 +85 84 +85 -1 86 0x0 1 0 24 0 1 4 33 32 0 0 0 0 0x0 1 0 22 0 1 8 9 1 0 0 0 0 1 0x1 0x1 39 0 +87 84 +87 -1 88 0x0 1 0 24 0 1 4 33 32 0 0 0 0 0x0 1 0 22 0 1 8 9 1 0 0 0 0 1 0x1 0x1 40 0 +89 84 +89 -1 90 0x0 1 0 24 0 1 4 33 32 0 0 0 0 0x0 1 0 22 0 1 8 9 1 0 0 0 0 1 0x1 0x1 41 0 +91 84 +91 -1 92 0x0 1 0 24 0 1 4 33 32 0 0 0 0 0x0 1 0 22 0 1 8 9 1 0 0 0 0 1 0x1 0x1 42 0 +93 84 +93 -1 94 0x0 1 0 24 0 1 4 33 32 0 0 0 0 0x0 1 0 22 0 1 8 9 1 0 0 0 0 1 0x1 0x1 43 0 +95 84 +95 -1 96 0x0 1 0 24 0 1 4 33 32 0 0 0 0 0x0 1 0 22 0 1 8 9 1 0 0 0 0 1 0x1 0x1 44 0 +97 84 +97 -1 98 0x0 1 0 24 0 1 4 33 32 0 0 0 0 0x0 1 0 22 0 1 8 9 1 0 0 0 0 1 0x1 0x1 45 0 +99 85 +99 -1 100 0x0 1 0 24 0 1 4 33 32 0 0 0 0 0x0 1 0 22 0 1 8 9 1 0 0 0 0 1 0x1 0x1 46 0 +101 86 +101 -1 102 0x0 1 0 24 0 1 4 33 32 0 0 0 0 0x0 1 0 22 0 1 8 9 1 0 0 0 0 1 0x1 0x1 47 0 +103 86 +103 -1 104 0x0 1 0 24 0 1 4 33 32 0 0 0 0 0x0 1 0 22 0 1 8 9 1 0 0 0 0 1 0x1 0x1 48 0 +105 86 +105 -1 106 0x0 1 0 24 0 1 4 33 32 0 0 0 0 0x0 1 0 22 0 1 8 9 1 0 0 0 0 1 0x1 0x1 49 0 +107 348 +107 -1 108 0x0 1 0 2 0 0 20 1 32 5 5 0 0 0x2 1 5 109 0 0x0 1 0 12 0 -1 4 278571 32 0 31 31 0 32 0x1 0 0 0 -1 110 4 0x0 1 0 52 16 1 4 17413 0 0 0 -1 0 0 0x1 0 0 0 -1 111 8 0x0 1 0 52 16 1 4 17413 0 0 0 -1 0 0 0x1 0 0 0 -1 112 12 0x0 1 0 52 16 1 4 17413 0 0 0 -1 0 0 0x1 0 0 0 -1 113 16 0x0 1 0 52 16 1 4 17413 0 0 0 -1 0 0 0x1 0 0 0 -1 0x3 0x1 50 0 +114 1933 +114 -1 115 0x0 1 0 24 0 1 4 33 32 0 0 0 0 0x0 1 0 2 0 0 120 1 490 32 32 0 0 0x2 1 32 116 0 0x0 1 0 25 0 -1 4 278561 32 0 31 31 0 32 0x1 0 0 0 -1 117 4 0x0 1 0 25 0 -1 4 278561 32 0 31 31 0 32 0x1 0 0 0 -1 118 8 0x0 1 0 12 0 -1 8 278571 64 0 63 63 0 64 0x1 0 0 0 -1 119 16 0x0 1 0 12 0 1 1 41 1 0 0 0 0 1 0x1 0 0 0 -1 120 17 0x0 1 0 12 0 1 1 41 1 0 0 0 0 1 0x1 0 0 0 -1 121 18 0x0 1 0 12 0 1 1 41 1 0 0 0 0 1 0x1 0 0 0 -1 122 19 0x0 1 0 12 0 1 1 41 1 0 0 0 0 1 0x1 0 0 0 -1 111 20 0x0 1 0 12 0 1 1 41 1 0 0 0 0 1 0x1 0 0 0 -1 112 21 0x0 1 0 12 0 1 1 41 1 0 0 0 0 1 0x1 0 0 0 -1 123 24 0x0 1 0 12 0 -1 4 278571 32 0 31 31 0 32 0x1 0 0 0 -1 124 28 0x0 1 0 12 0 1 1 41 1 0 0 0 0 1 0x1 0 0 0 -1 125 32 0x0 1 0 12 0 -1 4 278571 32 0 31 31 0 32 0x1 0 0 0 -1 126 36 0x0 1 0 12 0 -1 4 278571 32 0 31 31 0 32 0x1 0 0 0 -1 127 40 0x0 1 0 52 16 1 4 17413 0 0 0 -1 0 0 0x1 0 0 0 -1 128 44 0x0 1 0 12 0 -1 4 278571 32 0 31 31 0 32 0x1 0 0 0 -1 129 48 0x0 1 0 12 0 1 1 41 1 0 0 0 0 1 0x1 0 0 0 -1 130 52 0x0 1 0 12 0 -1 4 278571 32 0 31 31 0 32 0x1 0 0 0 -1 131 56 0x0 1 0 52 16 1 4 17413 0 0 0 -1 0 0 0x1 0 0 0 -1 132 60 0x0 1 0 12 0 1 1 41 1 0 0 0 0 1 0x1 0 0 0 -1 133 64 0x0 1 0 12 0 -1 4 278571 32 0 31 31 0 32 0x1 0 0 0 -1 134 68 0x0 1 0 52 16 1 4 17413 0 0 0 -1 0 0 0x1 0 0 0 -1 135 72 0x0 1 0 52 16 1 4 17413 0 0 0 -1 0 0 0x1 0 0 0 -1 136 76 0x0 1 0 52 16 1 4 17413 0 0 0 -1 0 0 0x1 0 0 0 -1 137 80 0x0 1 0 52 16 1 4 17413 0 0 0 -1 0 0 0x1 0 0 0 -1 138 84 0x0 1 0 52 16 1 4 17413 0 0 0 -1 0 0 0x1 0 0 0 -1 139 88 0x0 1 0 12 0 -1 4 278571 32 0 31 31 0 32 0x1 0 0 0 -1 140 92 0x0 1 0 52 16 1 4 17413 0 0 0 -1 0 0 0x1 0 0 0 -1 141 96 0x0 1 0 12 0 -1 4 278571 32 0 31 31 0 32 0x1 0 0 0 -1 142 100 0x0 1 0 12 0 -1 4 278571 32 0 31 31 0 32 0x1 0 0 0 -1 143 104 0x0 1 0 12 0 -1 4 278571 32 0 31 31 0 32 0x1 0 0 0 -1 144 108 0x0 1 0 12 0 -1 4 278571 32 0 31 31 0 32 0x1 0 0 0 -1 145 112 0x0 1 0 12 0 1 1 41 1 0 0 0 0 1 0x1 0 0 0 -1 0x3 0x1 0x1 51 0 +146 76 +146 -1 147 0x0 1 0 12 0 -1 4096 262187 32768 0 32767 32767 0 32768 0x1 52 0 +148 86 +148 -1 149 0x0 1 0 24 0 1 4 33 32 0 0 0 0 0x0 1 0 22 0 1 8 9 1 0 0 0 0 1 0x1 0x1 53 0 +150 86 +150 -1 151 0x0 1 0 24 0 1 4 33 32 0 0 0 0 0x0 1 0 22 0 1 8 9 1 0 0 0 0 1 0x1 0x1 54 0 +152 86 +152 -1 153 0x0 1 0 24 0 1 4 33 32 0 0 0 0 0x0 1 0 22 0 1 8 9 1 0 0 0 0 1 0x1 0x1 55 0 +154 61 +154 -1 155 0x0 1 0 12 0 -1 4 278571 32 0 31 31 0 32 0x1 56 0 +156 61 +156 -1 157 0x0 1 0 12 0 -1 4 278571 32 0 31 31 0 32 0x1 57 0 +158 61 +158 -1 159 0x0 1 0 12 0 -1 4 278571 32 0 31 31 0 32 0x1 58 0 +160 61 +160 -1 161 0x0 1 0 12 0 -1 8 262185 64 0 63 63 0 64 0x1 59 0 +162 62 +162 -1 163 0x0 1 0 10 0 -1 16 262153 64 0 63 63 0 64 0x1 60 0 +164 57 +164 -1 165 0x0 1 0 12 0 -1 1 262185 8 0 7 7 0 8 0x1 61 0 +166 61 +166 -1 167 0x0 1 0 12 0 -1 4 262185 32 0 31 31 0 32 0x1 62 0 +168 238 +168 -1 169 0x0 1 0 2 0 0 12 1 64 3 3 0 0 0x2 1 3 170 0 0x0 1 0 52 16 1 4 17413 0 0 0 -1 0 0 0x1 0 0 0 -1 171 4 0x0 1 0 12 0 -1 4 278571 32 0 31 31 0 32 0x1 0 0 0 -1 112 8 0x0 1 0 12 0 -1 4 278571 32 0 31 31 0 32 0x1 0 0 0 -1 0x3 0x1 63 0 +172 86 +172 -1 173 0x0 1 0 24 0 1 4 33 32 0 0 0 0 0x0 1 0 22 0 1 8 9 1 0 0 0 0 1 0x1 0x1 64 0 +174 61 +174 -1 175 0x0 1 0 12 0 -1 4 278571 32 0 31 31 0 32 0x1 65 0 +176 61 +176 -1 177 0x0 1 0 12 0 -1 4 278571 32 0 31 31 0 32 0x1 66 0 +178 61 +178 -1 179 0x0 1 0 12 0 -1 4 278571 32 0 31 31 0 32 0x1 67 0 +180 61 +180 -1 181 0x0 1 0 12 0 -1 4 278571 32 0 31 31 0 32 0x1 68 0 +182 61 +182 -1 183 0x0 1 0 12 0 -1 4 278571 32 0 31 31 0 32 0x1 69 0 +184 61 +184 -1 185 0x0 1 0 12 0 -1 4 278571 32 0 31 31 0 32 0x1 70 0 +186 61 +186 -1 187 0x0 1 0 12 0 -1 4 278571 32 0 31 31 0 32 0x1 71 0 +188 61 +188 -1 189 0x0 1 0 12 0 -1 4 278571 32 0 31 31 0 32 0x1 72 0 +190 61 +190 -1 191 0x0 1 0 12 0 -1 4 278571 32 0 31 31 0 32 0x1 73 0 +192 61 +192 -1 193 0x0 1 0 12 0 -1 4 278571 32 0 31 31 0 32 0x1 74 0 +194 86 +194 -1 195 0x0 1 0 24 0 1 4 33 32 0 0 0 0 0x0 1 0 22 0 1 8 9 1 0 0 0 0 1 0x1 0x1 75 0 +196 86 +196 -1 197 0x0 1 0 24 0 1 4 33 32 0 0 0 0 0x0 1 0 22 0 1 8 9 1 0 0 0 0 1 0x1 0x1 76 0 +198 86 +198 -1 199 0x0 1 0 24 0 1 4 33 32 0 0 0 0 0x0 1 0 22 0 1 8 9 1 0 0 0 0 1 0x1 0x1 77 0 +200 86 +200 -1 201 0x0 1 0 24 0 1 4 33 32 0 0 0 0 0x0 1 0 22 0 1 8 9 1 0 0 0 0 1 0x1 0x1 78 0 +202 86 +202 -1 203 0x0 1 0 24 0 1 4 33 32 0 0 0 0 0x0 1 0 22 0 1 8 9 1 0 0 0 0 1 0x1 0x1 79 0 +204 86 +204 -1 205 0x0 1 0 24 0 1 4 33 32 0 0 0 0 0x0 1 0 22 0 1 8 9 1 0 0 0 0 1 0x1 0x1 80 0 +206 86 +206 -1 207 0x0 1 0 24 0 1 4 33 32 0 0 0 0 0x0 1 0 22 0 1 8 9 1 0 0 0 0 1 0x1 0x1 81 0 +208 86 +208 -1 209 0x0 1 0 24 0 1 4 33 32 0 0 0 0 0x0 1 0 22 0 1 8 9 1 0 0 0 0 1 0x1 0x1 82 0 +210 86 +210 -1 211 0x0 1 0 24 0 1 4 33 32 0 0 0 0 0x0 1 0 22 0 1 8 9 1 0 0 0 0 1 0x1 0x1 83 0 +212 86 +212 -1 213 0x0 1 0 24 0 1 4 33 32 0 0 0 0 0x0 1 0 22 0 1 8 9 1 0 0 0 0 1 0x1 0x1 84 0 +214 61 +214 -1 215 0x0 1 0 12 0 -1 4 278571 32 0 31 31 0 32 0x1 85 0 +216 71 +216 -1 217 0x0 1 0 10 0 -1 256 262153 1024 0 1023 1023 0 1024 0x1 86 0 +218 61 +218 -1 219 0x0 1 0 12 0 -1 4 278571 32 0 31 31 0 32 0x1 87 0 +220 86 +220 -1 221 0x0 1 0 24 0 1 4 33 32 0 0 0 0 0x0 1 0 22 0 1 8 9 1 0 0 0 0 1 0x1 0x1 88 0 +222 86 +222 -1 223 0x0 1 0 24 0 1 4 33 32 0 0 0 0 0x0 1 0 22 0 1 8 9 1 0 0 0 0 1 0x1 0x1 89 0 +224 86 +224 -1 225 0x0 1 0 24 0 1 4 33 32 0 0 0 0 0x0 1 0 22 0 1 8 9 1 0 0 0 0 1 0x1 0x1 90 0 +226 86 +226 -1 227 0x0 1 0 24 0 1 4 33 32 0 0 0 0 0x0 1 0 22 0 1 8 9 1 0 0 0 0 1 0x1 0x1 91 0 +228 86 +228 -1 229 0x0 1 0 24 0 1 4 33 32 0 0 0 0 0x0 1 0 22 0 1 8 9 1 0 0 0 0 1 0x1 0x1 92 0 +230 86 +230 -1 231 0x0 1 0 24 0 1 4 33 32 0 0 0 0 0x0 1 0 22 0 1 8 9 1 0 0 0 0 1 0x1 0x1 93 0 +232 86 +232 -1 233 0x0 1 0 24 0 1 4 33 32 0 0 0 0 0x0 1 0 22 0 1 8 9 1 0 0 0 0 1 0x1 0x1 94 0 +234 86 +234 -1 235 0x0 1 0 24 0 1 4 33 32 0 0 0 0 0x0 1 0 22 0 1 8 9 1 0 0 0 0 1 0x1 0x1 95 0 +236 86 +236 -1 237 0x0 1 0 24 0 1 4 33 32 0 0 0 0 0x0 1 0 22 0 1 8 9 1 0 0 0 0 1 0x1 0x1 96 0 +238 86 +238 -1 239 0x0 1 0 24 0 1 4 33 32 0 0 0 0 0x0 1 0 22 0 1 8 9 1 0 0 0 0 1 0x1 0x1 97 0 +240 86 +240 -1 241 0x0 1 0 24 0 1 4 33 32 0 0 0 0 0x0 1 0 22 0 1 8 9 1 0 0 0 0 1 0x1 0x1 98 0 +242 86 +242 -1 243 0x0 1 0 24 0 1 4 33 32 0 0 0 0 0x0 1 0 22 0 1 8 9 1 0 0 0 0 1 0x1 0x1 99 0 +244 87 +244 -1 245 0x0 1 0 24 0 1 4 33 32 0 0 0 0 0x0 1 0 22 0 1 8 9 1 0 0 0 0 1 0x1 0x1 100 0 +TYPEDEF_END +TF_BEGIN 15 +246 41 +246 -1 -1 4 0 1 0 0x0 1 1 1 0x1 1 247 27 +248 41 +248 -1 -1 4 0 1 0 0x0 1 1 1 0x1 1 247 28 +249 41 +249 -1 -1 4 0 1 0 0x0 1 1 1 0x1 1 247 29 +250 94 +250 -1 -1 4 1 1 0 0x0 1 0 25 0 -1 4 278561 32 0 31 31 0 32 0x1 0 251 0x0 1 1 1 0x1 1 1 247 43 +252 117 +252 -1 -1 4 2 1 0 0x0 1 1 29 0x1 0 253 0x0 1 0 25 0 -1 4 278561 32 0 31 31 0 32 0x1 1 0 254 0x0 1 1 1 0x1 1 1 247 44 +255 90 +255 -1 -1 4 1 1 0 0x0 0 0x1 0 253 0x0 1 0 25 0 -1 4 278561 32 0 31 31 0 32 0x1 1 1 247 45 +256 37 +256 -1 -1 4 0 1 0 0x0 0 0x1 1 257 24 +258 63 +258 -1 -1 4 1 1 0 0x0 1 1 1 0x1 0 259 0x0 1 1 1 0x1 1 1 257 25 +260 64 +260 -1 -1 6 1 1 0 0x0 1 1 29 0x1 0 170 0x0 1 1 1 0x1 1 1 261 59 +262 87 +262 -1 -1 6 2 1 0 0x0 1 1 29 0x1 0 170 0x0 1 1 1 0x1 1 0 263 0x0 1 1 86 0x1 1 1 261 67 +264 87 +264 -1 -1 6 2 1 0 0x0 1 1 29 0x1 0 170 0x0 1 1 1 0x1 1 0 263 0x0 1 1 86 0x1 1 1 261 74 +265 88 +265 -1 -1 6 2 1 0 0x0 1 1 29 0x1 0 170 0x0 1 1 1 0x1 1 0 263 0x0 1 1 86 0x1 2 1 261 121 +266 65 +266 -1 -1 6 1 1 0 0x0 1 1 29 0x1 0 170 0x0 1 1 1 0x1 1 1 261 113 +267 88 +267 -1 -1 6 2 1 0 0x0 1 1 29 0x1 0 170 0x0 1 1 1 0x1 1 0 263 0x0 1 1 86 0x1 3 1 261 105 +268 86 +268 -1 -1 4 2 1 0 0x0 1 1 29 0x1 0 269 0x0 1 1 1 0x1 1 0 254 0x0 1 1 1 0x1 1 1 257 23 +TF_END diff --git a/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/project_benches/jtag/sim/work/optimized_batch_top_tb/_lib.qdb b/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/project_benches/jtag/sim/work/optimized_batch_top_tb/_lib.qdb new file mode 100644 index 00000000..dbc1c9da Binary files /dev/null and b/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/project_benches/jtag/sim/work/optimized_batch_top_tb/_lib.qdb differ diff --git a/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/project_benches/jtag/sim/work/optimized_batch_top_tb/_lib1_0.qdb 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a/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/project_benches/jtag/sim/work/optimized_batch_top_tb/_lib5_0.qdb b/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/project_benches/jtag/sim/work/optimized_batch_top_tb/_lib5_0.qdb new file mode 100644 index 00000000..48721350 Binary files /dev/null and b/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/project_benches/jtag/sim/work/optimized_batch_top_tb/_lib5_0.qdb differ diff --git a/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/project_benches/jtag/sim/work/optimized_batch_top_tb/_lib5_0.qpg b/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/project_benches/jtag/sim/work/optimized_batch_top_tb/_lib5_0.qpg new file mode 100644 index 00000000..e69de29b diff --git a/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/project_benches/jtag/sim/work/optimized_batch_top_tb/_lib5_0.qtl b/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/project_benches/jtag/sim/work/optimized_batch_top_tb/_lib5_0.qtl new file mode 100644 index 00000000..2cb2b9b8 Binary files /dev/null and b/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/project_benches/jtag/sim/work/optimized_batch_top_tb/_lib5_0.qtl differ diff --git a/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/project_benches/jtag/sim/work/optimized_debug_top_tb/_dpi/dpi.tfdb b/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/project_benches/jtag/sim/work/optimized_debug_top_tb/_dpi/dpi.tfdb new file mode 100644 index 00000000..578a0377 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/project_benches/jtag/sim/work/optimized_debug_top_tb/_dpi/dpi.tfdb @@ -0,0 +1,777 @@ +VERSION 10 1 1 +SYM_BEGIN 270 +190 10 +uvm_hier_e +252 15 +uvm_dpi_regexec +98 23 +uvm_pkg::uvm_config_int +159 34 +uvm_pkg::uvm_tlm_response_status_e +188 12 +uvm_access_e +103 19 +uvm_objection_cbs_t +152 13 +uvm_report_cb +57 16 +uvm_barrier_pool +192 13 +uvm_predict_e +68 23 +uvm_pkg:: +116 4 +size +181 19 +uvm_pkg::uvm_path_e +216 32 +uvm_default_sequencer_param_type +187 24 +uvm_pkg::uvm_elem_kind_e +110 27 +uvm_pkg::uvm_config_wrapper +266 15 +uvm_hdl_release +100 26 +uvm_pkg::uvm_config_string +191 19 +uvm_pkg::uvm_hier_e +264 13 +uvm_hdl_force +56 53 +uvm_pkg:: +65 23 +uvm_active_passive_enum +201 23 +uvm_pkg::uvm_config_seq +203 30 +uvm_pkg::uvm_virtual_sequencer +91 17 +uvm_id_file_array +207 56 +uvm_pkg:: +240 53 + +36 24 +uvm_pkg::uvm_mem_cb_iter +148 11 +value_width +253 4 +preg +169 26 +uvm_pkg::uvm_reg_byte_en_t +76 22 +uvm_pkg::uvm_verbosity +111 20 +uvm_printer_row_info +24 50 +uvm_pkg:: +101 17 +uvm_config_object +214 23 +uvm_default_driver_type +245 57 +uvm_pkg:: +236 48 + +37 16 +uvm_reg_field_cb +202 21 +uvm_virtual_sequencer +218 17 +uvm_tlm_command_e +21 7 +byte_en +10 22 +uvm_reg_map_addr_range +184 16 +uvm_endianness_e +6 13 +uvm_apprepend +225 49 +uvm_pkg:: +256 17 +uvm_dump_re_cache +108 45 +uvm_pkg:: +32 27 +uvm_pkg::uvm_reg_bd_cb_iter +237 57 +uvm_pkg:: +126 10 +identifier +244 48 + +77 15 +uvm_port_type_e +167 29 +uvm_pkg::uvm_reg_addr_logic_t +41 17 +uvm_vreg_field_cb +55 44 + +255 15 +uvm_dpi_regfree +47 11 +uvm_vreg_cb +247 46 +verilog_src/uvm-1.1d/src/dpi/uvm_svcmd_dpi.svh +165 28 +uvm_pkg::uvm_reg_mem_tests_e +15 14 +uvm_reg_bus_op +263 5 +value +94 33 +uvm_pkg::uvm_id_verbosities_array +208 43 + +194 19 +uvm_objection_event +162 14 +uvm_tlm_sync_e +163 23 +uvm_pkg::uvm_tlm_sync_e +140 9 +oct_radix +74 24 +uvm_pkg::uvm_action_type +70 26 +uvm_pkg::uvm_severity_type +18 4 +addr +267 24 +uvm_hdl_release_and_read +106 44 +uvm_pkg:: +146 10 +type_width +64 34 +uvm_pkg::uvm_recursion_policy_enum +193 22 +uvm_pkg::uvm_predict_e +22 6 +status +97 14 +uvm_config_int +62 23 +uvm_pkg::uvm_radix_enum +114 4 +name +164 19 +uvm_reg_mem_tests_e +54 59 +uvm_pkg:: +178 12 +uvm_status_e +196 19 +uvm_heartbeat_modes +223 55 +uvm_pkg:: +45 49 + +175 6 +offset +160 15 +uvm_tlm_phase_e +150 20 +uvm_pack_bitstream_t +90 29 +uvm_pkg::uvm_phase_transition +61 14 +uvm_radix_enum +119 31 +uvm_pkg::uvm_tree_printer_knobs +31 18 +uvm_reg_bd_cb_iter +204 42 + +89 20 +uvm_phase_transition +238 49 + +227 57 +uvm_pkg:: +79 12 +SEQ_ARB_TYPE +219 26 +uvm_pkg::uvm_tlm_command_e +168 17 +uvm_reg_byte_en_t +142 9 +hex_radix +242 47 + +224 40 + +93 24 +uvm_id_verbosities_array +92 26 +uvm_pkg::uvm_id_file_array +259 4 +glob +28 24 +uvm_pkg::uvm_reg_cb_iter +185 25 +uvm_pkg::uvm_endianness_e +153 22 +uvm_pkg::uvm_report_cb +73 15 +uvm_action_type +50 25 +uvm_pkg::uvm_vreg_cb_iter +176 19 +uvm_reg_cvr_rsrc_db +246 22 +uvm_dpi_get_next_arg_c +63 25 +uvm_recursion_policy_enum +67 14 + +229 51 +uvm_pkg:: +87 15 +uvm_phase_state +35 15 +uvm_mem_cb_iter +199 28 +uvm_pkg::uvm_heartbeat_cbs_t +189 21 +uvm_pkg::uvm_access_e +42 26 +uvm_pkg::uvm_vreg_field_cb +135 9 +separator +85 14 +uvm_phase_type +59 14 + +16 23 +uvm_pkg::uvm_reg_bus_op +115 9 +type_name +136 10 +show_radix +161 24 +uvm_pkg::uvm_tlm_phase_e +210 25 +uvm_default_sequence_type +53 50 + +132 6 +indent +154 18 +uvm_report_cb_iter +220 14 +uvm_hdl_data_t +120 6 +#vtbl# +151 29 +uvm_pkg::uvm_pack_bitstream_t +145 10 +name_width +269 2 +re +209 52 +uvm_pkg:: +230 48 + +228 42 + +88 24 +uvm_pkg::uvm_phase_state +109 18 +uvm_config_wrapper +127 5 +depth +19 4 +data +205 51 +uvm_pkg:: +104 28 +uvm_pkg::uvm_objection_cbs_t +46 58 +uvm_pkg:: +143 9 +max_width +172 18 +uvm_hdl_path_slice +155 27 +uvm_pkg::uvm_report_cb_iter +226 48 + +123 6 +header +11 31 +uvm_pkg::uvm_reg_map_addr_range +2 11 +uvm_wait_op +17 4 +kind +147 10 +size_width +180 10 +uvm_path_e +251 5 +regex +133 9 +show_root +197 28 +uvm_pkg::uvm_heartbeat_modes +20 6 +n_bits +60 23 +uvm_pkg:: +261 40 +verilog_src/uvm-1.1d/src/dpi/uvm_hdl.svh +212 26 +uvm_default_sequencer_type +174 4 +path +72 23 +uvm_pkg:: +249 26 +uvm_dpi_get_tool_version_c +211 34 +uvm_pkg::uvm_default_sequence_type +33 10 +uvm_mem_cb +182 11 +uvm_check_e +138 9 +dec_radix +5 23 +uvm_pkg::uvm_event_pool +81 23 +uvm_sequence_state_enum +8 38 + +260 18 +uvm_hdl_check_path +14 6 +stride +222 46 + +200 14 +uvm_config_seq +195 28 +uvm_pkg::uvm_objection_event +234 46 + +105 35 + +183 20 +uvm_pkg::uvm_check_e +134 3 +mcd +58 25 +uvm_pkg::uvm_barrier_pool +84 30 +uvm_pkg::uvm_sequence_lib_mode +13 3 +max +170 20 +uvm_coverage_model_e +102 26 +uvm_pkg::uvm_config_object +107 36 + +221 23 +uvm_pkg::uvm_hdl_data_t +66 32 +uvm_pkg::uvm_active_passive_enum +158 25 +uvm_tlm_response_status_e +34 19 +uvm_pkg::uvm_mem_cb +206 47 + +99 17 +uvm_config_string +1 23 +uvm_pkg:: +30 22 +uvm_pkg::uvm_reg_bd_cb +86 23 +uvm_pkg::uvm_phase_type +179 21 +uvm_pkg::uvm_status_e +139 9 +bin_radix +0 14 + +122 6 +#ciid# +231 57 +uvm_pkg:: +7 22 +uvm_pkg::uvm_apprepend +213 35 +uvm_pkg::uvm_default_sequencer_type +257 42 +verilog_src/uvm-1.1d/src/dpi/uvm_regex.svh +232 42 + +137 13 +default_radix +173 27 +uvm_pkg::uvm_hdl_path_slice +131 6 +prefix +248 23 +uvm_dpi_get_tool_name_c +235 55 +uvm_pkg:: +118 22 +uvm_tree_printer_knobs +233 51 +uvm_pkg:: +243 56 +uvm_pkg:: +177 28 +uvm_pkg::uvm_reg_cvr_rsrc_db +9 47 +uvm_pkg:: +3 20 +uvm_pkg::uvm_wait_op +217 41 +uvm_pkg::uvm_default_sequencer_param_type +44 31 +uvm_pkg::uvm_vreg_field_cb_iter +43 22 +uvm_vreg_field_cb_iter +130 12 +end_elements +258 14 +uvm_glob_to_re +141 14 +unsigned_radix +71 14 + +38 25 +uvm_pkg::uvm_reg_field_cb +26 19 +uvm_pkg::uvm_reg_cb +27 15 +uvm_reg_cb_iter +157 29 +uvm_pkg::uvm_id_actions_array +75 13 +uvm_verbosity +149 6 +sprint +265 12 +uvm_hdl_read +124 6 +footer +250 15 +uvm_dpi_regcomp +156 20 +uvm_id_actions_array +69 17 +uvm_severity_type +48 20 +uvm_pkg::uvm_vreg_cb +23 41 + +198 19 +uvm_heartbeat_cbs_t +39 21 +uvm_reg_field_cb_iter +96 31 +uvm_pkg::uvm_sev_override_array +166 20 +uvm_reg_addr_logic_t +239 58 +uvm_pkg:: +49 16 +uvm_vreg_cb_iter +12 3 +min +52 52 +uvm_pkg:: +144 10 +truncation +83 21 +uvm_sequence_lib_mode +254 3 +str +112 29 +uvm_pkg::uvm_printer_row_info +40 30 +uvm_pkg::uvm_reg_field_cb_iter +241 62 +uvm_pkg:: +82 32 +uvm_pkg::uvm_sequence_state_enum +80 21 +uvm_pkg::SEQ_ARB_TYPE +95 22 +uvm_sev_override_array +171 29 +uvm_pkg::uvm_coverage_model_e +186 15 +uvm_elem_kind_e +215 32 +uvm_pkg::uvm_default_driver_type +113 5 +level +25 10 +uvm_reg_cb +51 43 + +29 13 +uvm_reg_bd_cb +4 14 +uvm_event_pool +78 24 +uvm_pkg::uvm_port_type_e +121 12 +#rand_state# +117 3 +val +262 15 +uvm_hdl_deposit +268 12 +uvm_re_match +125 9 +full_name +129 14 +begin_elements +128 9 +reference +SYM_END +TYPEDEF_BEGIN 100 +0 52 +0 -1 1 0x0 1 0 52 16 1 4 17413 0 0 0 -1 0 0 0x1 1 0 +2 56 +2 -1 3 0x0 1 0 12 0 -1 4 278571 32 0 31 31 0 32 0x1 2 0 +4 81 +4 -1 5 0x0 1 0 24 0 1 4 33 32 0 0 0 0 0x0 1 0 22 0 1 8 9 1 0 0 0 0 1 0x1 0x1 3 0 +6 56 +6 -1 7 0x0 1 0 12 0 -1 4 278571 32 0 31 31 0 32 0x1 4 0 +8 81 +8 -1 9 0x0 1 0 24 0 1 4 33 32 0 0 0 0 0x0 1 0 22 0 1 8 9 1 0 0 0 0 1 0x1 0x1 5 0 +10 240 +10 -1 11 0x0 1 0 2 0 0 20 41 160 3 3 0 0 0x2 1 3 12 96 0x0 1 0 12 0 -1 8 262185 64 0 63 63 0 64 0x1 0 0 0 -1 13 32 0x0 1 0 12 0 -1 8 262185 64 0 63 63 0 64 0x1 0 0 0 -1 14 0 0x0 1 0 12 0 -1 4 278569 32 0 31 31 0 32 0x1 0 0 0 -1 0x3 0x1 6 0 +15 414 +15 -1 16 0x0 1 0 2 0 0 40 1 232 6 6 0 0 0x2 1 6 17 0 0x0 1 0 12 0 -1 4 278571 32 0 31 31 0 32 0x1 0 0 0 -1 18 8 0x0 1 0 12 0 -1 8 262185 64 0 63 63 0 64 0x1 0 0 0 -1 19 16 0x0 1 0 12 0 -1 8 262185 64 0 63 63 0 64 0x1 0 0 0 -1 20 24 0x0 1 0 12 0 -1 4 278571 32 0 31 31 0 32 0x1 0 0 0 -1 21 28 0x0 1 0 12 0 -1 1 262185 8 0 7 7 0 8 0x1 0 0 0 -1 22 32 0x0 1 0 12 0 -1 4 278571 32 0 31 31 0 32 0x1 0 0 0 -1 0x3 0x1 7 0 +23 83 +23 -1 24 0x0 1 0 24 0 1 4 33 32 0 0 0 0 0x0 1 0 22 0 1 8 9 1 0 0 0 0 1 0x1 0x1 8 0 +25 83 +25 -1 26 0x0 1 0 24 0 1 4 33 32 0 0 0 0 0x0 1 0 22 0 1 8 9 1 0 0 0 0 1 0x1 0x1 9 0 +27 84 +27 -1 28 0x0 1 0 24 0 1 4 33 32 0 0 0 0 0x0 1 0 22 0 1 8 9 1 0 0 0 0 1 0x1 0x1 10 0 +29 84 +29 -1 30 0x0 1 0 24 0 1 4 33 32 0 0 0 0 0x0 1 0 22 0 1 8 9 1 0 0 0 0 1 0x1 0x1 11 0 +31 84 +31 -1 32 0x0 1 0 24 0 1 4 33 32 0 0 0 0 0x0 1 0 22 0 1 8 9 1 0 0 0 0 1 0x1 0x1 12 0 +33 84 +33 -1 34 0x0 1 0 24 0 1 4 33 32 0 0 0 0 0x0 1 0 22 0 1 8 9 1 0 0 0 0 1 0x1 0x1 13 0 +35 84 +35 -1 36 0x0 1 0 24 0 1 4 33 32 0 0 0 0 0x0 1 0 22 0 1 8 9 1 0 0 0 0 1 0x1 0x1 14 0 +37 84 +37 -1 38 0x0 1 0 24 0 1 4 33 32 0 0 0 0 0x0 1 0 22 0 1 8 9 1 0 0 0 0 1 0x1 0x1 15 0 +39 84 +39 -1 40 0x0 1 0 24 0 1 4 33 32 0 0 0 0 0x0 1 0 22 0 1 8 9 1 0 0 0 0 1 0x1 0x1 16 0 +41 84 +41 -1 42 0x0 1 0 24 0 1 4 33 32 0 0 0 0 0x0 1 0 22 0 1 8 9 1 0 0 0 0 1 0x1 0x1 17 0 +43 84 +43 -1 44 0x0 1 0 24 0 1 4 33 32 0 0 0 0 0x0 1 0 22 0 1 8 9 1 0 0 0 0 1 0x1 0x1 18 0 +45 84 +45 -1 46 0x0 1 0 24 0 1 4 33 32 0 0 0 0 0x0 1 0 22 0 1 8 9 1 0 0 0 0 1 0x1 0x1 19 0 +47 84 +47 -1 48 0x0 1 0 24 0 1 4 33 32 0 0 0 0 0x0 1 0 22 0 1 8 9 1 0 0 0 0 1 0x1 0x1 20 0 +49 84 +49 -1 50 0x0 1 0 24 0 1 4 33 32 0 0 0 0 0x0 1 0 22 0 1 8 9 1 0 0 0 0 1 0x1 0x1 21 0 +51 84 +51 -1 52 0x0 1 0 24 0 1 4 33 32 0 0 0 0 0x0 1 0 22 0 1 8 9 1 0 0 0 0 1 0x1 0x1 22 0 +53 84 +53 -1 54 0x0 1 0 24 0 1 4 33 32 0 0 0 0 0x0 1 0 22 0 1 8 9 1 0 0 0 0 1 0x1 0x1 23 0 +55 84 +55 -1 56 0x0 1 0 24 0 1 4 33 32 0 0 0 0 0x0 1 0 22 0 1 8 9 1 0 0 0 0 1 0x1 0x1 24 0 +57 84 +57 -1 58 0x0 1 0 24 0 1 4 33 32 0 0 0 0 0x0 1 0 22 0 1 8 9 1 0 0 0 0 1 0x1 0x1 25 0 +59 70 +59 -1 60 0x0 1 0 10 0 -1 1024 262155 4096 0 4095 4095 0 4096 0x1 26 0 +61 59 +61 -1 62 0x0 1 0 12 0 -1 4 278571 32 0 31 31 0 32 0x1 27 0 +63 59 +63 -1 64 0x0 1 0 12 0 -1 4 278571 32 0 31 31 0 32 0x1 28 0 +65 50 +65 -1 66 0x0 1 0 12 0 1 4 41 1 0 0 0 0 1 0x1 29 0 +67 55 +67 -1 68 0x0 1 0 12 0 -1 1 262185 2 0 1 1 0 2 0x1 30 0 +69 55 +69 -1 70 0x0 1 0 12 0 -1 4 262185 2 0 1 1 0 2 0x1 31 0 +71 59 +71 -1 72 0x0 1 0 12 0 -1 4 278571 32 0 31 31 0 32 0x1 32 0 +73 59 +73 -1 74 0x0 1 0 12 0 -1 4 278571 32 0 31 31 0 32 0x1 33 0 +75 59 +75 -1 76 0x0 1 0 12 0 -1 4 278571 32 0 31 31 0 32 0x1 34 0 +77 59 +77 -1 78 0x0 1 0 12 0 -1 4 278571 32 0 31 31 0 32 0x1 35 0 +79 59 +79 -1 80 0x0 1 0 12 0 -1 4 278571 32 0 31 31 0 32 0x1 36 0 +81 59 +81 -1 82 0x0 1 0 12 0 -1 4 278571 32 0 31 31 0 32 0x1 37 0 +83 59 +83 -1 84 0x0 1 0 12 0 -1 4 278571 32 0 31 31 0 32 0x1 38 0 +85 59 +85 -1 86 0x0 1 0 12 0 -1 4 278571 32 0 31 31 0 32 0x1 39 0 +87 59 +87 -1 88 0x0 1 0 12 0 -1 4 278571 32 0 31 31 0 32 0x1 40 0 +89 59 +89 -1 90 0x0 1 0 12 0 -1 4 278571 32 0 31 31 0 32 0x1 41 0 +91 84 +91 -1 92 0x0 1 0 24 0 1 4 33 32 0 0 0 0 0x0 1 0 22 0 1 8 9 1 0 0 0 0 1 0x1 0x1 42 0 +93 84 +93 -1 94 0x0 1 0 24 0 1 4 33 32 0 0 0 0 0x0 1 0 22 0 1 8 9 1 0 0 0 0 1 0x1 0x1 43 0 +95 84 +95 -1 96 0x0 1 0 24 0 1 4 33 32 0 0 0 0 0x0 1 0 22 0 1 8 9 1 0 0 0 0 1 0x1 0x1 44 0 +97 84 +97 -1 98 0x0 1 0 24 0 1 4 33 32 0 0 0 0 0x0 1 0 22 0 1 8 9 1 0 0 0 0 1 0x1 0x1 45 0 +99 85 +99 -1 100 0x0 1 0 24 0 1 4 33 32 0 0 0 0 0x0 1 0 22 0 1 8 9 1 0 0 0 0 1 0x1 0x1 46 0 +101 86 +101 -1 102 0x0 1 0 24 0 1 4 33 32 0 0 0 0 0x0 1 0 22 0 1 8 9 1 0 0 0 0 1 0x1 0x1 47 0 +103 86 +103 -1 104 0x0 1 0 24 0 1 4 33 32 0 0 0 0 0x0 1 0 22 0 1 8 9 1 0 0 0 0 1 0x1 0x1 48 0 +105 86 +105 -1 106 0x0 1 0 24 0 1 4 33 32 0 0 0 0 0x0 1 0 22 0 1 8 9 1 0 0 0 0 1 0x1 0x1 49 0 +107 86 +107 -1 108 0x0 1 0 24 0 1 4 33 32 0 0 0 0 0x0 1 0 22 0 1 8 9 1 0 0 0 0 1 0x1 0x1 50 0 +109 86 +109 -1 110 0x0 1 0 24 0 1 4 33 32 0 0 0 0 0x0 1 0 22 0 1 8 9 1 0 0 0 0 1 0x1 0x1 51 0 +111 348 +111 -1 112 0x0 1 0 2 0 0 20 1 32 5 5 0 0 0x2 1 5 113 0 0x0 1 0 12 0 -1 4 278571 32 0 31 31 0 32 0x1 0 0 0 -1 114 4 0x0 1 0 52 16 1 4 17413 0 0 0 -1 0 0 0x1 0 0 0 -1 115 8 0x0 1 0 52 16 1 4 17413 0 0 0 -1 0 0 0x1 0 0 0 -1 116 12 0x0 1 0 52 16 1 4 17413 0 0 0 -1 0 0 0x1 0 0 0 -1 117 16 0x0 1 0 52 16 1 4 17413 0 0 0 -1 0 0 0x1 0 0 0 -1 0x3 0x1 52 0 +118 1933 +118 -1 119 0x0 1 0 24 0 1 4 33 32 0 0 0 0 0x0 1 0 2 0 0 120 1 490 32 32 0 0 0x2 1 32 120 0 0x0 1 0 25 0 -1 4 278561 32 0 31 31 0 32 0x1 0 0 0 -1 121 4 0x0 1 0 25 0 -1 4 278561 32 0 31 31 0 32 0x1 0 0 0 -1 122 8 0x0 1 0 12 0 -1 8 278571 64 0 63 63 0 64 0x1 0 0 0 -1 123 16 0x0 1 0 12 0 1 1 41 1 0 0 0 0 1 0x1 0 0 0 -1 124 17 0x0 1 0 12 0 1 1 41 1 0 0 0 0 1 0x1 0 0 0 -1 125 18 0x0 1 0 12 0 1 1 41 1 0 0 0 0 1 0x1 0 0 0 -1 126 19 0x0 1 0 12 0 1 1 41 1 0 0 0 0 1 0x1 0 0 0 -1 115 20 0x0 1 0 12 0 1 1 41 1 0 0 0 0 1 0x1 0 0 0 -1 116 21 0x0 1 0 12 0 1 1 41 1 0 0 0 0 1 0x1 0 0 0 -1 127 24 0x0 1 0 12 0 -1 4 278571 32 0 31 31 0 32 0x1 0 0 0 -1 128 28 0x0 1 0 12 0 1 1 41 1 0 0 0 0 1 0x1 0 0 0 -1 129 32 0x0 1 0 12 0 -1 4 278571 32 0 31 31 0 32 0x1 0 0 0 -1 130 36 0x0 1 0 12 0 -1 4 278571 32 0 31 31 0 32 0x1 0 0 0 -1 131 40 0x0 1 0 52 16 1 4 17413 0 0 0 -1 0 0 0x1 0 0 0 -1 132 44 0x0 1 0 12 0 -1 4 278571 32 0 31 31 0 32 0x1 0 0 0 -1 133 48 0x0 1 0 12 0 1 1 41 1 0 0 0 0 1 0x1 0 0 0 -1 134 52 0x0 1 0 12 0 -1 4 278571 32 0 31 31 0 32 0x1 0 0 0 -1 135 56 0x0 1 0 52 16 1 4 17413 0 0 0 -1 0 0 0x1 0 0 0 -1 136 60 0x0 1 0 12 0 1 1 41 1 0 0 0 0 1 0x1 0 0 0 -1 137 64 0x0 1 0 12 0 -1 4 278571 32 0 31 31 0 32 0x1 0 0 0 -1 138 68 0x0 1 0 52 16 1 4 17413 0 0 0 -1 0 0 0x1 0 0 0 -1 139 72 0x0 1 0 52 16 1 4 17413 0 0 0 -1 0 0 0x1 0 0 0 -1 140 76 0x0 1 0 52 16 1 4 17413 0 0 0 -1 0 0 0x1 0 0 0 -1 141 80 0x0 1 0 52 16 1 4 17413 0 0 0 -1 0 0 0x1 0 0 0 -1 142 84 0x0 1 0 52 16 1 4 17413 0 0 0 -1 0 0 0x1 0 0 0 -1 143 88 0x0 1 0 12 0 -1 4 278571 32 0 31 31 0 32 0x1 0 0 0 -1 144 92 0x0 1 0 52 16 1 4 17413 0 0 0 -1 0 0 0x1 0 0 0 -1 145 96 0x0 1 0 12 0 -1 4 278571 32 0 31 31 0 32 0x1 0 0 0 -1 146 100 0x0 1 0 12 0 -1 4 278571 32 0 31 31 0 32 0x1 0 0 0 -1 147 104 0x0 1 0 12 0 -1 4 278571 32 0 31 31 0 32 0x1 0 0 0 -1 148 108 0x0 1 0 12 0 -1 4 278571 32 0 31 31 0 32 0x1 0 0 0 -1 149 112 0x0 1 0 12 0 1 1 41 1 0 0 0 0 1 0x1 0 0 0 -1 0x3 0x1 0x1 53 0 +150 76 +150 -1 151 0x0 1 0 12 0 -1 4096 262187 32768 0 32767 32767 0 32768 0x1 54 0 +152 86 +152 -1 153 0x0 1 0 24 0 1 4 33 32 0 0 0 0 0x0 1 0 22 0 1 8 9 1 0 0 0 0 1 0x1 0x1 55 0 +154 86 +154 -1 155 0x0 1 0 24 0 1 4 33 32 0 0 0 0 0x0 1 0 22 0 1 8 9 1 0 0 0 0 1 0x1 0x1 56 0 +156 86 +156 -1 157 0x0 1 0 24 0 1 4 33 32 0 0 0 0 0x0 1 0 22 0 1 8 9 1 0 0 0 0 1 0x1 0x1 57 0 +158 61 +158 -1 159 0x0 1 0 12 0 -1 4 278571 32 0 31 31 0 32 0x1 58 0 +160 61 +160 -1 161 0x0 1 0 12 0 -1 4 278571 32 0 31 31 0 32 0x1 59 0 +162 61 +162 -1 163 0x0 1 0 12 0 -1 4 278571 32 0 31 31 0 32 0x1 60 0 +164 61 +164 -1 165 0x0 1 0 12 0 -1 8 262185 64 0 63 63 0 64 0x1 61 0 +166 62 +166 -1 167 0x0 1 0 10 0 -1 16 262153 64 0 63 63 0 64 0x1 62 0 +168 57 +168 -1 169 0x0 1 0 12 0 -1 1 262185 8 0 7 7 0 8 0x1 63 0 +170 61 +170 -1 171 0x0 1 0 12 0 -1 4 262185 32 0 31 31 0 32 0x1 64 0 +172 238 +172 -1 173 0x0 1 0 2 0 0 12 1 64 3 3 0 0 0x2 1 3 174 0 0x0 1 0 52 16 1 4 17413 0 0 0 -1 0 0 0x1 0 0 0 -1 175 4 0x0 1 0 12 0 -1 4 278571 32 0 31 31 0 32 0x1 0 0 0 -1 116 8 0x0 1 0 12 0 -1 4 278571 32 0 31 31 0 32 0x1 0 0 0 -1 0x3 0x1 65 0 +176 86 +176 -1 177 0x0 1 0 24 0 1 4 33 32 0 0 0 0 0x0 1 0 22 0 1 8 9 1 0 0 0 0 1 0x1 0x1 66 0 +178 61 +178 -1 179 0x0 1 0 12 0 -1 4 278571 32 0 31 31 0 32 0x1 67 0 +180 61 +180 -1 181 0x0 1 0 12 0 -1 4 278571 32 0 31 31 0 32 0x1 68 0 +182 61 +182 -1 183 0x0 1 0 12 0 -1 4 278571 32 0 31 31 0 32 0x1 69 0 +184 61 +184 -1 185 0x0 1 0 12 0 -1 4 278571 32 0 31 31 0 32 0x1 70 0 +186 61 +186 -1 187 0x0 1 0 12 0 -1 4 278571 32 0 31 31 0 32 0x1 71 0 +188 61 +188 -1 189 0x0 1 0 12 0 -1 4 278571 32 0 31 31 0 32 0x1 72 0 +190 61 +190 -1 191 0x0 1 0 12 0 -1 4 278571 32 0 31 31 0 32 0x1 73 0 +192 61 +192 -1 193 0x0 1 0 12 0 -1 4 278571 32 0 31 31 0 32 0x1 74 0 +194 61 +194 -1 195 0x0 1 0 12 0 -1 4 278571 32 0 31 31 0 32 0x1 75 0 +196 61 +196 -1 197 0x0 1 0 12 0 -1 4 278571 32 0 31 31 0 32 0x1 76 0 +198 86 +198 -1 199 0x0 1 0 24 0 1 4 33 32 0 0 0 0 0x0 1 0 22 0 1 8 9 1 0 0 0 0 1 0x1 0x1 77 0 +200 86 +200 -1 201 0x0 1 0 24 0 1 4 33 32 0 0 0 0 0x0 1 0 22 0 1 8 9 1 0 0 0 0 1 0x1 0x1 78 0 +202 86 +202 -1 203 0x0 1 0 24 0 1 4 33 32 0 0 0 0 0x0 1 0 22 0 1 8 9 1 0 0 0 0 1 0x1 0x1 79 0 +204 86 +204 -1 205 0x0 1 0 24 0 1 4 33 32 0 0 0 0 0x0 1 0 22 0 1 8 9 1 0 0 0 0 1 0x1 0x1 80 0 +206 86 +206 -1 207 0x0 1 0 24 0 1 4 33 32 0 0 0 0 0x0 1 0 22 0 1 8 9 1 0 0 0 0 1 0x1 0x1 81 0 +208 86 +208 -1 209 0x0 1 0 24 0 1 4 33 32 0 0 0 0 0x0 1 0 22 0 1 8 9 1 0 0 0 0 1 0x1 0x1 82 0 +210 86 +210 -1 211 0x0 1 0 24 0 1 4 33 32 0 0 0 0 0x0 1 0 22 0 1 8 9 1 0 0 0 0 1 0x1 0x1 83 0 +212 86 +212 -1 213 0x0 1 0 24 0 1 4 33 32 0 0 0 0 0x0 1 0 22 0 1 8 9 1 0 0 0 0 1 0x1 0x1 84 0 +214 86 +214 -1 215 0x0 1 0 24 0 1 4 33 32 0 0 0 0 0x0 1 0 22 0 1 8 9 1 0 0 0 0 1 0x1 0x1 85 0 +216 86 +216 -1 217 0x0 1 0 24 0 1 4 33 32 0 0 0 0 0x0 1 0 22 0 1 8 9 1 0 0 0 0 1 0x1 0x1 86 0 +218 61 +218 -1 219 0x0 1 0 12 0 -1 4 278571 32 0 31 31 0 32 0x1 87 0 +220 71 +220 -1 221 0x0 1 0 10 0 -1 256 262153 1024 0 1023 1023 0 1024 0x1 88 0 +222 86 +222 -1 223 0x0 1 0 24 0 1 4 33 32 0 0 0 0 0x0 1 0 22 0 1 8 9 1 0 0 0 0 1 0x1 0x1 89 0 +224 86 +224 -1 225 0x0 1 0 24 0 1 4 33 32 0 0 0 0 0x0 1 0 22 0 1 8 9 1 0 0 0 0 1 0x1 0x1 90 0 +226 86 +226 -1 227 0x0 1 0 24 0 1 4 33 32 0 0 0 0 0x0 1 0 22 0 1 8 9 1 0 0 0 0 1 0x1 0x1 91 0 +228 86 +228 -1 229 0x0 1 0 24 0 1 4 33 32 0 0 0 0 0x0 1 0 22 0 1 8 9 1 0 0 0 0 1 0x1 0x1 92 0 +230 86 +230 -1 231 0x0 1 0 24 0 1 4 33 32 0 0 0 0 0x0 1 0 22 0 1 8 9 1 0 0 0 0 1 0x1 0x1 93 0 +232 86 +232 -1 233 0x0 1 0 24 0 1 4 33 32 0 0 0 0 0x0 1 0 22 0 1 8 9 1 0 0 0 0 1 0x1 0x1 94 0 +234 86 +234 -1 235 0x0 1 0 24 0 1 4 33 32 0 0 0 0 0x0 1 0 22 0 1 8 9 1 0 0 0 0 1 0x1 0x1 95 0 +236 86 +236 -1 237 0x0 1 0 24 0 1 4 33 32 0 0 0 0 0x0 1 0 22 0 1 8 9 1 0 0 0 0 1 0x1 0x1 96 0 +238 86 +238 -1 239 0x0 1 0 24 0 1 4 33 32 0 0 0 0 0x0 1 0 22 0 1 8 9 1 0 0 0 0 1 0x1 0x1 97 0 +240 86 +240 -1 241 0x0 1 0 24 0 1 4 33 32 0 0 0 0 0x0 1 0 22 0 1 8 9 1 0 0 0 0 1 0x1 0x1 98 0 +242 86 +242 -1 243 0x0 1 0 24 0 1 4 33 32 0 0 0 0 0x0 1 0 22 0 1 8 9 1 0 0 0 0 1 0x1 0x1 99 0 +244 87 +244 -1 245 0x0 1 0 24 0 1 4 33 32 0 0 0 0 0x0 1 0 22 0 1 8 9 1 0 0 0 0 1 0x1 0x1 100 0 +TYPEDEF_END +TF_BEGIN 15 +246 41 +246 -1 -1 4 0 1 0 0x0 1 1 1 0x1 1 247 27 +248 41 +248 -1 -1 4 0 1 0 0x0 1 1 1 0x1 1 247 28 +249 41 +249 -1 -1 4 0 1 0 0x0 1 1 1 0x1 1 247 29 +250 94 +250 -1 -1 4 1 1 0 0x0 1 0 25 0 -1 4 278561 32 0 31 31 0 32 0x1 0 251 0x0 1 1 1 0x1 1 1 247 43 +252 117 +252 -1 -1 4 2 1 0 0x0 1 1 32 0x1 0 253 0x0 1 0 25 0 -1 4 278561 32 0 31 31 0 32 0x1 1 0 254 0x0 1 1 1 0x1 1 1 247 44 +255 90 +255 -1 -1 4 1 1 0 0x0 0 0x1 0 253 0x0 1 0 25 0 -1 4 278561 32 0 31 31 0 32 0x1 1 1 247 45 +256 37 +256 -1 -1 4 0 1 0 0x0 0 0x1 1 257 24 +258 63 +258 -1 -1 4 1 1 0 0x0 1 1 1 0x1 0 259 0x0 1 1 1 0x1 1 1 257 25 +260 64 +260 -1 -1 6 1 1 0 0x0 1 1 32 0x1 0 174 0x0 1 1 1 0x1 1 1 261 59 +262 87 +262 -1 -1 6 2 1 0 0x0 1 1 32 0x1 0 174 0x0 1 1 1 0x1 1 0 263 0x0 1 1 88 0x1 1 1 261 67 +264 87 +264 -1 -1 6 2 1 0 0x0 1 1 32 0x1 0 174 0x0 1 1 1 0x1 1 0 263 0x0 1 1 88 0x1 1 1 261 74 +265 88 +265 -1 -1 6 2 1 0 0x0 1 1 32 0x1 0 174 0x0 1 1 1 0x1 1 0 263 0x0 1 1 88 0x1 2 1 261 121 +266 65 +266 -1 -1 6 1 1 0 0x0 1 1 32 0x1 0 174 0x0 1 1 1 0x1 1 1 261 113 +267 88 +267 -1 -1 6 2 1 0 0x0 1 1 32 0x1 0 174 0x0 1 1 1 0x1 1 0 263 0x0 1 1 88 0x1 3 1 261 105 +268 86 +268 -1 -1 4 2 1 0 0x0 1 1 32 0x1 0 269 0x0 1 1 1 0x1 1 0 254 0x0 1 1 1 0x1 1 1 257 23 +TF_END diff --git a/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/project_benches/jtag/sim/work/optimized_debug_top_tb/_lib.qdb b/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/project_benches/jtag/sim/work/optimized_debug_top_tb/_lib.qdb new file mode 100644 index 00000000..1fcaf27e Binary files /dev/null and b/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/project_benches/jtag/sim/work/optimized_debug_top_tb/_lib.qdb differ diff --git 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b/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/project_benches/jtag/sim/xwaves.sigs new file mode 100644 index 00000000..d75f0a57 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/project_benches/jtag/sim/xwaves.sigs @@ -0,0 +1,17 @@ + + + + + +# pragma uvmf custom additional begin + +Group All + +#Top level signals +hdl_top.* +#Add additional levels or individual signals as needed +hdl_top.*.* + +# pragma uvmf custom additional end + + diff --git a/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/project_benches/jtag/tb/parameters/jtag_parameters_pkg.compile b/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/project_benches/jtag/tb/parameters/jtag_parameters_pkg.compile new file mode 100644 index 00000000..aefd4437 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/project_benches/jtag/tb/parameters/jtag_parameters_pkg.compile @@ -0,0 +1,4 @@ +needs: + - $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg_hdl.compile +src: + - jtag_parameters_pkg.sv diff --git a/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/project_benches/jtag/tb/parameters/jtag_parameters_pkg.sv b/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/project_benches/jtag/tb/parameters/jtag_parameters_pkg.sv new file mode 100644 index 00000000..98367aac --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/project_benches/jtag/tb/parameters/jtag_parameters_pkg.sv @@ -0,0 +1,38 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This package contains test level parameters +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// + + +package jtag_parameters_pkg; + + import uvmf_base_pkg_hdl::*; + + // pragma uvmf custom package_imports_additional begin + // pragma uvmf custom package_imports_additional end + + + // These parameters are used to uniquely identify each interface. The monitor_bfm and + // driver_bfm are placed into and retrieved from the uvm_config_db using these string + // names as the field_name. The parameter is also used to enable transaction viewing + // from the command line for selected interfaces using the UVM command line processing. + parameter string jtag_in_BFM = "jtag_in_BFM"; /* [0] */ + parameter string jtag_out_BFM = "jtag_out_BFM"; /* [1] */ + + // pragma uvmf custom package_item_additional begin + // pragma uvmf custom package_item_additional end + +endpackage + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/project_benches/jtag/tb/parameters/jtag_parameters_pkg.vinfo b/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/project_benches/jtag/tb/parameters/jtag_parameters_pkg.vinfo new file mode 100644 index 00000000..31158ff6 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/project_benches/jtag/tb/parameters/jtag_parameters_pkg.vinfo @@ -0,0 +1,2 @@ +@use $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg_hdl.vinfo +jtag_parameters_pkg.sv diff --git a/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/project_benches/jtag/tb/sequences/jtag_sequences_pkg.compile b/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/project_benches/jtag/tb/sequences/jtag_sequences_pkg.compile new file mode 100644 index 00000000..14a0c17e --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/project_benches/jtag/tb/sequences/jtag_sequences_pkg.compile @@ -0,0 +1,7 @@ +needs: + - $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg.compile + - ../../../../verification_ip/interface_packages/jtag_pkg/jtag.compile + - ../../../../verification_ip/environment_packages/jtag_env_pkg/jtag_env_pkg.compile + - ../parameters/jtag_parameters_pkg.compile +src: + - jtag_sequences_pkg.sv diff --git a/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/project_benches/jtag/tb/sequences/jtag_sequences_pkg.sv b/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/project_benches/jtag/tb/sequences/jtag_sequences_pkg.sv new file mode 100644 index 00000000..c2b6a63f --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/project_benches/jtag/tb/sequences/jtag_sequences_pkg.sv @@ -0,0 +1,49 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This package includes all high level sequence classes used +// in the environment. These include utility sequences and top +// level sequences. +// +// CONTAINS: +// - +// - +// +//---------------------------------------------------------------------- +// +//---------------------------------------------------------------------- +// + +package jtag_sequences_pkg; + import uvm_pkg::*; + import uvmf_base_pkg::*; + import jtag_pkg::*; + import jtag_pkg_hdl::*; + import jtag_parameters_pkg::*; + import jtag_env_pkg::*; + `include "uvm_macros.svh" + + // pragma uvmf custom package_imports_additional begin + // pragma uvmf custom package_imports_additional end + + `include "src/jtag_bench_sequence_base.svh" + `include "src/register_test_sequence.svh" + `include "src/example_derived_test_sequence.svh" + + // pragma uvmf custom package_item_additional begin + // UVMF_CHANGE_ME : When adding new sequences to the src directory + // be sure to add the sequence file here so that it will be + // compiled as part of the sequence package. Be sure to place + // the new sequence after any base sequences of the new sequence. + // pragma uvmf custom package_item_additional end + +endpackage + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/project_benches/jtag/tb/sequences/jtag_sequences_pkg.vinfo b/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/project_benches/jtag/tb/sequences/jtag_sequences_pkg.vinfo new file mode 100644 index 00000000..7cdbf933 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/project_benches/jtag/tb/sequences/jtag_sequences_pkg.vinfo @@ -0,0 +1,6 @@ +@use $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg.vinfo +@use $UVMF_VIP_LIBRARY_HOME/interface_packages/jtag_pkg/jtag_pkg.vinfo +@use $UVMF_VIP_LIBRARY_HOME/environment_packages/jtag_env_pkg/jtag_env_pkg.vinfo +@use $UVMF_PROJECT_DIR/tb/parameters/jtag_parameters_pkg.vinfo ++incdir+@vinfodir +jtag_sequences_pkg.sv diff --git a/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/project_benches/jtag/tb/sequences/src/example_derived_test_sequence.svh b/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/project_benches/jtag/tb/sequences/src/example_derived_test_sequence.svh new file mode 100644 index 00000000..ca6db205 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/project_benches/jtag/tb/sequences/src/example_derived_test_sequence.svh @@ -0,0 +1,30 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +// +//---------------------------------------------------------------------- +// +// DESCRIPTION: This file contains the top level sequence used in example_derived_test. +// It is an example of a sequence that is extended from %(benchName)_bench_sequence_base +// and can override %(benchName)_bench_sequence_base. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// + +class example_derived_test_sequence extends jtag_bench_sequence_base; + + `uvm_object_utils( example_derived_test_sequence ); + + function new(string name = "" ); + super.new(name); + endfunction + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/project_benches/jtag/tb/sequences/src/jtag_bench_sequence_base.svh b/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/project_benches/jtag/tb/sequences/src/jtag_bench_sequence_base.svh new file mode 100644 index 00000000..5781865b --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/project_benches/jtag/tb/sequences/src/jtag_bench_sequence_base.svh @@ -0,0 +1,128 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// Description: This file contains the top level and utility sequences +// used by test_top. It can be extended to create derivative top +// level sequences. +// +//---------------------------------------------------------------------- +// +//---------------------------------------------------------------------- +// + + +typedef jtag_env_configuration jtag_env_configuration_t; + +class jtag_bench_sequence_base extends uvmf_sequence_base #(uvm_sequence_item); + + `uvm_object_utils( jtag_bench_sequence_base ); + + // pragma uvmf custom sequences begin + +typedef jtag_env_sequence_base #( + .CONFIG_T(jtag_env_configuration_t) + ) + jtag_env_sequence_base_t; +rand jtag_env_sequence_base_t jtag_env_seq; + + + + // UVMF_CHANGE_ME : Instantiate, construct, and start sequences as needed to create stimulus scenarios. + // Instantiate sequences here + typedef jtag_random_sequence jtag_in_random_seq_t; + jtag_in_random_seq_t jtag_in_random_seq; + typedef jtag_responder_sequence jtag_out_responder_seq_t; + jtag_out_responder_seq_t jtag_out_responder_seq; + // pragma uvmf custom sequences end + + // Sequencer handles for each active interface in the environment + typedef jtag_transaction jtag_in_transaction_t; + uvm_sequencer #(jtag_in_transaction_t) jtag_in_sequencer; + typedef jtag_transaction jtag_out_transaction_t; + uvm_sequencer #(jtag_out_transaction_t) jtag_out_sequencer; + + + // Top level environment configuration handle + jtag_env_configuration_t top_configuration; + + // Configuration handles to access interface BFM's + jtag_configuration jtag_in_config; + jtag_configuration jtag_out_config; + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + // **************************************************************************** + function new( string name = "" ); + super.new( name ); + // Retrieve the configuration handles from the uvm_config_db + + // Retrieve top level configuration handle + if ( !uvm_config_db#(jtag_env_configuration_t)::get(null,UVMF_CONFIGURATIONS, "TOP_ENV_CONFIG",top_configuration) ) begin + `uvm_info("CFG", "*** FATAL *** uvm_config_db::get can not find TOP_ENV_CONFIG. Are you using an older UVMF release than what was used to generate this bench?",UVM_NONE); + `uvm_fatal("CFG", "uvm_config_db#(jtag_env_configuration_t)::get cannot find resource TOP_ENV_CONFIG"); + end + + // Retrieve config handles for all agents + if( !uvm_config_db #( jtag_configuration )::get( null , UVMF_CONFIGURATIONS , jtag_in_BFM , jtag_in_config ) ) + `uvm_fatal("CFG" , "uvm_config_db #( jtag_configuration )::get cannot find resource jtag_in_BFM" ) + if( !uvm_config_db #( jtag_configuration )::get( null , UVMF_CONFIGURATIONS , jtag_out_BFM , jtag_out_config ) ) + `uvm_fatal("CFG" , "uvm_config_db #( jtag_configuration )::get cannot find resource jtag_out_BFM" ) + + // Assign the sequencer handles from the handles within agent configurations + jtag_in_sequencer = jtag_in_config.get_sequencer(); + jtag_out_sequencer = jtag_out_config.get_sequencer(); + + + + // pragma uvmf custom new begin + // pragma uvmf custom new end + + endfunction + + // **************************************************************************** + virtual task body(); + // pragma uvmf custom body begin + + // Construct sequences here + + jtag_env_seq = jtag_env_sequence_base_t::type_id::create("jtag_env_seq"); + + jtag_in_random_seq = jtag_in_random_seq_t::type_id::create("jtag_in_random_seq"); + jtag_out_responder_seq = jtag_out_responder_seq_t::type_id::create("jtag_out_responder_seq"); + fork + jtag_in_config.wait_for_reset(); + jtag_out_config.wait_for_reset(); + join + // Start RESPONDER sequences here + fork + jtag_out_responder_seq.start(jtag_out_sequencer); + join_none + // Start INITIATOR sequences here + fork + repeat (25) jtag_in_random_seq.start(jtag_in_sequencer); + join + +jtag_env_seq.start(top_configuration.vsqr); + + // UVMF_CHANGE_ME : Extend the simulation XXX number of clocks after + // the last sequence to allow for the last sequence item to flow + // through the design. + fork + jtag_in_config.wait_for_num_clocks(400); + jtag_out_config.wait_for_num_clocks(400); + join + + // pragma uvmf custom body end + endtask + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/project_benches/jtag/tb/sequences/src/register_test_sequence.svh b/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/project_benches/jtag/tb/sequences/src/register_test_sequence.svh new file mode 100644 index 00000000..d831df0c --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/project_benches/jtag/tb/sequences/src/register_test_sequence.svh @@ -0,0 +1,57 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This file contains the top level sequence used in register_test. +// It uses the UVM built in register test. Specific UVM built-in tests can be +// selected in the body task. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// + +class register_test_sequence extends jtag_bench_sequence_base; + + `uvm_object_utils( register_test_sequence ); + + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + function new(string name = "" ); + super.new(name); + endfunction + + // **************************************************************************** + virtual task body(); + + // Reset the DUT + fork + // pragma uvmf custom register_test_reset begin + // UVMF_CHANGE_ME + // Select the desired wait_for_reset or provide custom mechanism. + // fork-join for this code block may be unnecessary based on your situation. + jtag_in_config.wait_for_reset(); + jtag_out_config.wait_for_reset(); + // pragma uvmf custom register_test_reset end + join + + // pragma uvmf custom register_test_setup begin + // UVMF_CHANGE_ME perform potentially necessary operations before running the sequence. + // pragma uvmf custom register_test_setup end + + // pragma uvmf custom register_test_operation begin + // UVMF_CHANGE_ME Perform your custom register test + // pragma uvmf custom register_test_operation end + + endtask + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/project_benches/jtag/tb/testbench/hdl_top.compile b/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/project_benches/jtag/tb/testbench/hdl_top.compile new file mode 100644 index 00000000..e6edf28b --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/project_benches/jtag/tb/testbench/hdl_top.compile @@ -0,0 +1,9 @@ +incdir: + - ${uvm_path}/src + - . +needs: + - $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg_hdl.compile + - ../parameters/jtag_parameters_pkg.compile + - ../../../../verification_ip/interface_packages/jtag_pkg/jtag_hdl.compile +src: + - hdl_top.sv diff --git a/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/project_benches/jtag/tb/testbench/hdl_top.sv b/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/project_benches/jtag/tb/testbench/hdl_top.sv new file mode 100644 index 00000000..fe31f4b2 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/project_benches/jtag/tb/testbench/hdl_top.sv @@ -0,0 +1,101 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// Description: This top level module instantiates all synthesizable +// static content. This and tb_top.sv are the two top level modules +// of the simulation. +// +// This module instantiates the following: +// DUT: The Design Under Test +// Interfaces: Signal bundles that contain signals connected to DUT +// Driver BFM's: BFM's that actively drive interface signals +// Monitor BFM's: BFM's that passively monitor interface signals +// +//---------------------------------------------------------------------- + +//---------------------------------------------------------------------- +// + +module hdl_top; + +import jtag_parameters_pkg::*; +import uvmf_base_pkg_hdl::*; + + // pragma attribute hdl_top partition_module_xrtl +// pragma uvmf custom clock_generator begin + bit clk; + // Instantiate a clk driver + // tbx clkgen + initial begin + clk = 0; + #9ns; + forever begin + clk = ~clk; + #5ns; + end + end +// pragma uvmf custom clock_generator end + +// pragma uvmf custom reset_generator begin + bit rst; + // Instantiate a rst driver + // tbx clkgen + initial begin + rst = 0; + #100ns; + rst = 1; + end +// pragma uvmf custom reset_generator end + + // pragma uvmf custom module_item_additional begin + // pragma uvmf custom module_item_additional end + + // Instantiate the signal bundle, monitor bfm and driver bfm for each interface. + // The signal bundle, _if, contains signals to be connected to the DUT. + // The monitor, monitor_bfm, observes the bus, _if, and captures transactions. + // The driver, driver_bfm, drives transactions onto the bus, _if. + jtag_if jtag_in_bus( + // pragma uvmf custom jtag_in_bus_connections begin + .clock(clk), .reset(rst) + // pragma uvmf custom jtag_in_bus_connections end + ); + jtag_if jtag_out_bus( + // pragma uvmf custom jtag_out_bus_connections begin + .clock(clk), .reset(rst) + // pragma uvmf custom jtag_out_bus_connections end + ); + jtag_monitor_bfm jtag_in_mon_bfm(jtag_in_bus.monitor_port); + jtag_monitor_bfm jtag_out_mon_bfm(jtag_out_bus.monitor_port); + jtag_driver_bfm jtag_in_drv_bfm(jtag_in_bus.initiator_port); + jtag_driver_bfm jtag_out_drv_bfm(jtag_out_bus.responder_port); + + // pragma uvmf custom dut_instantiation begin + // UVMF_CHANGE_ME : Add DUT and connect to signals in _bus interfaces listed above + // Instantiate your DUT here + // These DUT's instantiated to show verilog and vhdl instantiation + verilog_dut dut_verilog( .clk(clk), .rst(rst), .in_signal(vhdl_to_verilog_signal), .out_signal(verilog_to_vhdl_signal)); + vhdl_dut dut_vhdl ( .clk(clk), .rst(rst), .in_signal(verilog_to_vhdl_signal), .out_signal(vhdl_to_verilog_signal)); + // pragma uvmf custom dut_instantiation end + + initial begin // tbx vif_binding_block + import uvm_pkg::uvm_config_db; + // The monitor_bfm and driver_bfm for each interface is placed into the uvm_config_db. + // They are placed into the uvm_config_db using the string names defined in the parameters package. + // The string names are passed to the agent configurations by test_top through the top level configuration. + // They are retrieved by the agents configuration class for use by the agent. + uvm_config_db #( virtual jtag_monitor_bfm )::set( null , UVMF_VIRTUAL_INTERFACES , jtag_in_BFM , jtag_in_mon_bfm ); + uvm_config_db #( virtual jtag_monitor_bfm )::set( null , UVMF_VIRTUAL_INTERFACES , jtag_out_BFM , jtag_out_mon_bfm ); + uvm_config_db #( virtual jtag_driver_bfm )::set( null , UVMF_VIRTUAL_INTERFACES , jtag_in_BFM , jtag_in_drv_bfm ); + uvm_config_db #( virtual jtag_driver_bfm )::set( null , UVMF_VIRTUAL_INTERFACES , jtag_out_BFM , jtag_out_drv_bfm ); + end + +endmodule + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/project_benches/jtag/tb/testbench/hdl_top.vinfo b/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/project_benches/jtag/tb/testbench/hdl_top.vinfo new file mode 100644 index 00000000..8629a51a --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/project_benches/jtag/tb/testbench/hdl_top.vinfo @@ -0,0 +1,5 @@ +@use $UVMF_PROJECT_DIR/rtl/verilog/verilog_dut.vinfo +@use $UVMF_PROJECT_DIR/tb/parameters/jtag_parameters_pkg.vinfo +@use $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg_hdl.vinfo +@use $UVMF_VIP_LIBRARY_HOME/interface_packages/jtag_pkg/jtag_bfm.vinfo +hdl_top.sv diff --git a/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/project_benches/jtag/tb/testbench/hvl_top.compile b/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/project_benches/jtag/tb/testbench/hvl_top.compile new file mode 100644 index 00000000..5f90c092 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/project_benches/jtag/tb/testbench/hvl_top.compile @@ -0,0 +1,7 @@ +incdir: + - ${uvm_path}/src + - . +needs: + - ../tests/jtag_tests_pkg.compile +src: + - hvl_top.sv diff --git a/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/project_benches/jtag/tb/testbench/hvl_top.sv b/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/project_benches/jtag/tb/testbench/hvl_top.sv new file mode 100644 index 00000000..ae976ab9 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/project_benches/jtag/tb/testbench/hvl_top.sv @@ -0,0 +1,33 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +// +//---------------------------------------------------------------------- +// +// DESCRIPTION: This module loads the test package and starts the UVM phases. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// + +module hvl_top; + +import uvm_pkg::*; +import jtag_tests_pkg::*; + + // pragma uvmf custom module_item_additional begin + // pragma uvmf custom module_item_additional end + + initial begin + $timeformat(-9,3,"ns",5); + run_test(); + end + +endmodule + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/project_benches/jtag/tb/testbench/hvl_top.vinfo b/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/project_benches/jtag/tb/testbench/hvl_top.vinfo new file mode 100644 index 00000000..dd0ef919 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/project_benches/jtag/tb/testbench/hvl_top.vinfo @@ -0,0 +1,2 @@ +@use $UVMF_PROJECT_DIR/tb/tests/jtag_tests_pkg.vinfo +hvl_top.sv diff --git a/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/project_benches/jtag/tb/testbench/top_filelist_hdl.f b/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/project_benches/jtag/tb/testbench/top_filelist_hdl.f new file mode 100644 index 00000000..1e9dab65 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/project_benches/jtag/tb/testbench/top_filelist_hdl.f @@ -0,0 +1,3 @@ +$UVMF_PROJECT_DIR/tb/testbench/hdl_top.sv +// pragma uvmf custom additional begin +// pragma uvmf custom additional end diff --git a/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/project_benches/jtag/tb/testbench/top_filelist_hvl.f b/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/project_benches/jtag/tb/testbench/top_filelist_hvl.f new file mode 100644 index 00000000..42383ab2 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/project_benches/jtag/tb/testbench/top_filelist_hvl.f @@ -0,0 +1,3 @@ +$UVMF_PROJECT_DIR/tb/testbench/hvl_top.sv +// pragma uvmf custom additional begin +// pragma uvmf custom additional end diff --git a/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/project_benches/jtag/tb/tests/jtag_tests_pkg.compile b/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/project_benches/jtag/tb/tests/jtag_tests_pkg.compile new file mode 100644 index 00000000..fcd2a06b --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/project_benches/jtag/tb/tests/jtag_tests_pkg.compile @@ -0,0 +1,8 @@ +needs: + - $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg.compile + - ../../../../verification_ip/interface_packages/jtag_pkg/jtag.compile + - ../../../../verification_ip/environment_packages/jtag_env_pkg/jtag_env_pkg.compile + - ../parameters/jtag_parameters_pkg.compile + - ../sequences/jtag_sequences_pkg.compile +src: + - jtag_tests_pkg.sv diff --git a/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/project_benches/jtag/tb/tests/jtag_tests_pkg.sv b/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/project_benches/jtag/tb/tests/jtag_tests_pkg.sv new file mode 100644 index 00000000..5a21a795 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/project_benches/jtag/tb/tests/jtag_tests_pkg.sv @@ -0,0 +1,52 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This package contains all tests currently written for +// the simulation project. Once compiled, any test can be selected +// from the vsim command line using +UVM_TESTNAME=yourTestNameHere +// +// CONTAINS: +// - +// - +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// + +package jtag_tests_pkg; + + import uvm_pkg::*; + import uvmf_base_pkg::*; + import jtag_parameters_pkg::*; + import jtag_env_pkg::*; + import jtag_sequences_pkg::*; + import jtag_pkg::*; + import jtag_pkg_hdl::*; + + + `include "uvm_macros.svh" + + // pragma uvmf custom package_imports_additional begin + // pragma uvmf custom package_imports_additional end + + `include "src/test_top.svh" + `include "src/register_test.svh" + `include "src/example_derived_test.svh" + + // pragma uvmf custom package_item_additional begin + // UVMF_CHANGE_ME : When adding new tests to the src directory + // be sure to add the test file here so that it will be + // compiled as part of the test package. Be sure to place + // the new test after any base tests of the new test. + // pragma uvmf custom package_item_additional end + +endpackage + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/project_benches/jtag/tb/tests/jtag_tests_pkg.vinfo b/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/project_benches/jtag/tb/tests/jtag_tests_pkg.vinfo new file mode 100644 index 00000000..65f08e36 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/project_benches/jtag/tb/tests/jtag_tests_pkg.vinfo @@ -0,0 +1,7 @@ +@use $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg.vinfo +@use $UVMF_VIP_LIBRARY_HOME/interface_packages/jtag_pkg/jtag_pkg.vinfo +@use $UVMF_VIP_LIBRARY_HOME/environment_packages/jtag_env_pkg/jtag_env_pkg.vinfo +@use $UVMF_PROJECT_DIR/tb/parameters/jtag_parameters_pkg.vinfo +@use $UVMF_PROJECT_DIR/tb/sequences/jtag_sequences_pkg.vinfo ++incdir+@vinfodir +jtag_tests_pkg.sv diff --git a/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/project_benches/jtag/tb/tests/src/example_derived_test.svh b/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/project_benches/jtag/tb/tests/src/example_derived_test.svh new file mode 100644 index 00000000..c72857b4 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/project_benches/jtag/tb/tests/src/example_derived_test.svh @@ -0,0 +1,43 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This test extends test_top and makes +// changes to test_top using the UVM factory type_override: +// +// Test scenario: +// This is a template test that can be used to create future tests. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// + +class example_derived_test extends test_top; + + `uvm_component_utils( example_derived_test ); + + function new( string name = "", uvm_component parent = null ); + super.new( name, parent ); + endfunction + + virtual function void build_phase(uvm_phase phase); + // The factory override below is an example of how to replace the jtag_bench_sequence_base + // sequence with the example_derived_test_sequence. + jtag_bench_sequence_base::type_id::set_type_override(example_derived_test_sequence::get_type()); + // Execute the build_phase of test_top AFTER all factory overrides have been created. + super.build_phase(phase); + // pragma uvmf custom configuration_settings_post_randomize begin + // UVMF_CHANGE_ME Test specific configuration values can be set here. + // The configuration structure has already been randomized. + // pragma uvmf custom configuration_settings_post_randomize end + endfunction + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/project_benches/jtag/tb/tests/src/register_test.svh b/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/project_benches/jtag/tb/tests/src/register_test.svh new file mode 100644 index 00000000..fe2f36c8 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/project_benches/jtag/tb/tests/src/register_test.svh @@ -0,0 +1,51 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This test extends test_top and makes +// changes to test_top using the UVM factory type_override: +// +// Test scenario: +// This is a template test that can be used to create future tests. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// + +class register_test extends test_top; + + `uvm_component_utils( register_test ); + + function new( string name = "", uvm_component parent = null ); + super.new( name, parent ); + endfunction + + virtual function void build_phase(uvm_phase phase); + // The factory override below replaces the jtag_bench_sequence_base + // sequence with the register_test_sequence. + jtag_bench_sequence_base::type_id::set_type_override(register_test_sequence::get_type()); + // Execute the build_phase of test_top AFTER all factory overrides have been created. + super.build_phase(phase); + endfunction + + virtual function void end_of_elaboration_phase(uvm_phase phase); + super.end_of_elaboration_phase(phase); + // pragma uvmf custom register_test_scoreboard_control begin + + // These UVMF scoreboards may need to be disabled for the register test. + + // environment.jtag_sb.disable_scoreboard(); + // environment.jtag_sb.disable_end_of_test_activity_check(); + + // pragma uvmf custom register_test_scoreboard_control end + endfunction + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/project_benches/jtag/tb/tests/src/test_top.svh b/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/project_benches/jtag/tb/tests/src/test_top.svh new file mode 100644 index 00000000..f7a08afb --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/project_benches/jtag/tb/tests/src/test_top.svh @@ -0,0 +1,78 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// Description: This top level UVM test is the base class for all +// future tests created for this project. +// +// This test class contains: +// Configuration: The top level configuration for the project. +// Environment: The top level environment for the project. +// Top_level_sequence: The top level sequence for the project. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// + +typedef jtag_env_configuration jtag_env_configuration_t; +typedef jtag_environment jtag_environment_t; + +class test_top extends uvmf_test_base #(.CONFIG_T(jtag_env_configuration_t), + .ENV_T(jtag_environment_t), + .TOP_LEVEL_SEQ_T(jtag_bench_sequence_base)); + + `uvm_component_utils( test_top ); + + + + string interface_names[] = { + jtag_in_BFM /* jtag_in [0] */ , + jtag_out_BFM /* jtag_out [1] */ +}; + +uvmf_active_passive_t interface_activities[] = { + ACTIVE /* jtag_in [0] */ , + ACTIVE /* jtag_out [1] */ }; + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + // **************************************************************************** + // FUNCTION: new() + // This is the standard systemVerilog constructor. All components are + // constructed in the build_phase to allow factory overriding. + // + function new( string name = "", uvm_component parent = null ); + super.new( name ,parent ); + endfunction + + + + // **************************************************************************** + // FUNCTION: build_phase() + // The construction of the configuration and environment classes is done in + // the build_phase of uvmf_test_base. Once the configuraton and environment + // classes are built then the initialize call is made to perform the + // following: + // Monitor and driver BFM virtual interface handle passing into agents + // Set the active/passive state for each agent + // Once this build_phase completes, the build_phase of the environment is + // executed which builds the agents. + // + virtual function void build_phase(uvm_phase phase); +// pragma uvmf custom build_phase_pre_super begin +// pragma uvmf custom build_phase_pre_super end + super.build_phase(phase); + // pragma uvmf custom configuration_settings_post_randomize begin + // pragma uvmf custom configuration_settings_post_randomize end + configuration.initialize(NA, "uvm_test_top.environment", interface_names, null, interface_activities); + endfunction + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/project_benches/jtag/yaml/jtag_bench.yaml b/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/project_benches/jtag/yaml/jtag_bench.yaml new file mode 100644 index 00000000..22116a5d --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/project_benches/jtag/yaml/jtag_bench.yaml @@ -0,0 +1,17 @@ +uvmf: + benches: + jtag: + active_passive: + - bfm_name: jtag_in + value: ACTIVE + - bfm_name: jtag_out + value: ACTIVE + active_passive_default: ACTIVE + clock_half_period: 5ns + clock_phase_offset: 9ns + existing_library_component: 'True' + interface_params: [] + reset_assertion_level: 'False' + reset_duration: 100ns + top_env: jtag + use_dpi_link: 'False' diff --git a/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/verification_ip/environment_packages/jtag_env_pkg/.project b/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/verification_ip/environment_packages/jtag_env_pkg/.project new file mode 100644 index 00000000..44e9b9b0 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/verification_ip/environment_packages/jtag_env_pkg/.project @@ -0,0 +1,32 @@ + + + jtag_env_pkg + + + + + + org.python.pydev.PyDevBuilder + + + + + net.sf.sveditor.core.SVProjectBuilder + + + + + + net.sf.sveditor.core.SVNature + org.python.pydev.pythonNature + + + + + + UVMF_VIP_LIBRARY_HOME + $%7BPARENT-2-PROJECT_LOC%7D + + + + diff --git a/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/verification_ip/environment_packages/jtag_env_pkg/.svproject b/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/verification_ip/environment_packages/jtag_env_pkg/.svproject new file mode 100644 index 00000000..94bf6c26 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/verification_ip/environment_packages/jtag_env_pkg/.svproject @@ -0,0 +1,16 @@ + + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/verification_ip/environment_packages/jtag_env_pkg/Makefile b/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/verification_ip/environment_packages/jtag_env_pkg/Makefile new file mode 100644 index 00000000..0f4e4cb9 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/verification_ip/environment_packages/jtag_env_pkg/Makefile @@ -0,0 +1,56 @@ +# jtag environment packages source and make target + +# pragma uvmf custom additional begin +# pragma uvmf custom additional end + +# Include all requisite sub-environment package targets for this bench + +jtag_ENV_PKG =\ + $(UVMF_VIP_LIBRARY_HOME)/environment_packages/jtag_env_pkg/jtag_env_pkg.sv + +COMP_jtag_PKG_TGT_0 = q_comp_jtag_env_pkg +COMP_jtag_PKG_TGT_1 = v_comp_jtag_env_pkg +COMP_jtag_PKG_TGT = $(COMP_jtag_PKG_TGT_$(USE_VELOCE)) + +comp_jtag_env_pkg: $(COMP_jtag_PKG_TGT) + +q_comp_jtag_env_pkg: + $(HVL_COMP_CMD) +incdir+$(UVMF_VIP_LIBRARY_HOME)/environment_packages/jtag_env_pkg $(jtag_ENV_PKG) + +v_comp_jtag_env_pkg: q_comp_jtag_env_pkg + $(VELANALYZE_HVL_CMD) +incdir+$(UVMF_VIP_LIBRARY_HOME)/environment_packages/jtag_env_pkg $(jtag_ENV_PKG) + + + +ifeq ($(MTI_VCO_MODE),64) + GCC_COMP_ARCH = -m64 +else + GCC_COMP_ARCH = -m32 +endif + +export jtag_ENV_DPI_SRC ?= $(UVMF_VIP_LIBRARY_HOME)/environment_packages/jtag_env_pkg/dpi + +C_FILE_COMPILE_LIST_jtag_env_pkg = \ + +O_FILE_COMPILE_LIST_jtag_env_pkg = $(notdir $(C_FILE_COMPILE_LIST_jtag_env_pkg:.c=.o)) + +GCC_COMP_ARGS_jtag_env_pkg += -I$(jtag_ENV_DPI_SRC) \ + -fPIC + +GCC_COMP_ARGS_jtag_env_pkg += $(jtag_ENV_GCC_COMP_ARGUMENTS) + +GCC_LINK_ARGS_jtag_env_pkg += \ + \ + -o .so + +comp_jtag_env_pkg_c_files: + @echo "--------------------------------" + @echo "Compiling Environment C source" + @echo "--------------------------------" + gcc $(GCC_COMP_ARCH) $(GCC_COMP_ARGS_jtag_env_pkg) $(C_FILE_COMPILE_LIST_jtag_env_pkg) + @echo "--------------------------------" + @echo "Linking Environment C objects into a shared object" + @echo "--------------------------------" + gcc $(GCC_COMP_ARCH) $(GCC_LINK_ARGS_jtag_env_pkg) $(O_FILE_COMPILE_LIST_jtag_env_pkg) + @echo "--------------------------------" + diff --git a/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/verification_ip/environment_packages/jtag_env_pkg/compile.do b/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/verification_ip/environment_packages/jtag_env_pkg/compile.do new file mode 100644 index 00000000..79ab183e --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/verification_ip/environment_packages/jtag_env_pkg/compile.do @@ -0,0 +1,12 @@ +# Tcl do file for compile of jtag interface + +# pragma uvmf custom additional begin +# pragma uvmf custom additional end + + + +quietly set cmd [format "vlog -timescale 1ps/1ps +incdir+%s/environment_packages/jtag_env_pkg" $env(UVMF_VIP_LIBRARY_HOME)] +quietly set cmd [format "%s %s/environment_packages/jtag_env_pkg/jtag_env_pkg.sv" $cmd $env(UVMF_VIP_LIBRARY_HOME)] +eval $cmd + + diff --git a/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/verification_ip/environment_packages/jtag_env_pkg/jtag_env_pkg.compile b/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/verification_ip/environment_packages/jtag_env_pkg/jtag_env_pkg.compile new file mode 100644 index 00000000..4da1549e --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/verification_ip/environment_packages/jtag_env_pkg/jtag_env_pkg.compile @@ -0,0 +1,7 @@ +needs: + - $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg.compile + - ../../../verification_ip/interface_packages/jtag_pkg/jtag_hvl.compile + +src: + - jtag_env_pkg.sv + diff --git a/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/verification_ip/environment_packages/jtag_env_pkg/jtag_env_pkg.sv b/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/verification_ip/environment_packages/jtag_env_pkg/jtag_env_pkg.sv new file mode 100644 index 00000000..b2ae476c --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/verification_ip/environment_packages/jtag_env_pkg/jtag_env_pkg.sv @@ -0,0 +1,56 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// PACKAGE: This file defines all of the files contained in the +// environment package that will run on the host simulator. +// +// CONTAINS: +// - +// - +// - +// - +// - +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +package jtag_env_pkg; + + import uvm_pkg::*; + `include "uvm_macros.svh" + import uvmf_base_pkg::*; + import jtag_pkg::*; + import jtag_pkg_hdl::*; + + `uvm_analysis_imp_decl(_jtag_in_ae) + `uvm_analysis_imp_decl(_jtag_cov_ae) + + // pragma uvmf custom package_imports_additional begin + // pragma uvmf custom package_imports_additional end + + // Parameters defined as HVL parameters + + `include "src/jtag_env_typedefs.svh" + `include "src/jtag_env_configuration.svh" + `include "src/jtag_predictor.svh" + `include "src/jtag_coverage.svh" + `include "src/jtag_environment.svh" + `include "src/jtag_env_sequence_base.svh" + + // pragma uvmf custom package_item_additional begin + // UVMF_CHANGE_ME : When adding new environment level sequences to the src directory + // be sure to add the sequence file here so that it will be + // compiled as part of the environment package. Be sure to place + // the new sequence after any base sequence of the new sequence. + // pragma uvmf custom package_item_additional end + +endpackage + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/verification_ip/environment_packages/jtag_env_pkg/jtag_env_pkg.vinfo b/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/verification_ip/environment_packages/jtag_env_pkg/jtag_env_pkg.vinfo new file mode 100644 index 00000000..60cc70b6 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/verification_ip/environment_packages/jtag_env_pkg/jtag_env_pkg.vinfo @@ -0,0 +1,4 @@ +@use $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg.vinfo +@use $UVMF_VIP_LIBRARY_HOME/interface_packages/jtag_pkg/jtag_pkg.vinfo ++incdir+@vinfodir +jtag_env_pkg.sv diff --git a/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/verification_ip/environment_packages/jtag_env_pkg/jtag_env_pkg_sve.F b/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/verification_ip/environment_packages/jtag_env_pkg/jtag_env_pkg_sve.F new file mode 100644 index 00000000..465150c7 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/verification_ip/environment_packages/jtag_env_pkg/jtag_env_pkg_sve.F @@ -0,0 +1,12 @@ + +// UVM ++incdir+${UVM_HOME}/src +${UVM_HOME}/src/uvm_pkg.sv + +// Common UVMF files +-f ${UVMF_HOME}/common/common_sve.f + +// Sub-Environments + ++incdir+. +./jtag_env_pkg.sv diff --git a/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/verification_ip/environment_packages/jtag_env_pkg/src/jtag_coverage.svh b/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/verification_ip/environment_packages/jtag_env_pkg/src/jtag_coverage.svh new file mode 100644 index 00000000..4146c859 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/verification_ip/environment_packages/jtag_env_pkg/src/jtag_coverage.svh @@ -0,0 +1,107 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: +// This component is used to collect functional coverage at the environment level. +// Coverage collection components typically do not have analysis ports for broadcasting +// transactions. They typically only receive transactions and sample functional coverage +// on the transaction variables. +// +// This analysis component has the following analysis_exports that receive the +// listed transaction type. +// +// jtag_cov_ae receives transactions of type jtag_transaction +// +// This analysis component has the following analysis_ports that can broadcast +// the listed transaction type. +// +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// + + +class jtag_coverage #( + type CONFIG_T, + type BASE_T = uvm_component + ) extends BASE_T; + + // Factory registration of this class + `uvm_component_param_utils( jtag_coverage #( + CONFIG_T, + BASE_T + )) + + // Instantiate a handle to the configuration of the environment in which this component resides + CONFIG_T configuration; + + + // Instantiate the analysis exports + uvm_analysis_imp_jtag_cov_ae #(jtag_transaction, jtag_coverage #( + .CONFIG_T(CONFIG_T), + .BASE_T(BASE_T) + )) jtag_cov_ae; + + + + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + +// **************************************************************************** + // UVMF_CHANGE_ME : Add coverage bins, crosses, exclusions, etc. according to coverage needs. + covergroup jtag_coverage_cg; + // pragma uvmf custom covergroup begin + option.auto_bin_max=1024; + option.per_instance=1; + // pragma uvmf custom covergroup end + endgroup + + +// **************************************************************************** + // FUNCTION: new + function new(string name, uvm_component parent); + super.new(name,parent); + jtag_coverage_cg=new; + `uvm_warning("COVERAGE_MODEL_REVIEW", "A covergroup has been constructed which may need review because of either generation or re-generation with merging. Remove this warning after the covergroup has been reviewed.") + // pragma uvmf custom new begin + // pragma uvmf custom new end + endfunction + +// **************************************************************************** + // FUNCTION: build_phase + virtual function void build_phase (uvm_phase phase); + + jtag_coverage_cg.set_inst_name($sformatf("jtag_coverage_cg_%s",get_full_name())); + + jtag_cov_ae = new("jtag_cov_ae", this); + // pragma uvmf custom build_phase begin + // pragma uvmf custom build_phase end + endfunction + + // **************************************************************************** + // FUNCTION: write_jtag_cov_ae + // Transactions received through jtag_cov_ae initiate the execution of this function. + // This function collects functional coverage on variables within the received transaction + virtual function void write_jtag_cov_ae(jtag_transaction t); + // pragma uvmf custom jtag_cov_ae_coverage begin + `uvm_info("COV", "Transaction Received through jtag_cov_ae", UVM_MEDIUM) + `uvm_info("COV", {" Data: ",t.convert2string()}, UVM_FULL) + + // UVMF_CHANGE_ME: Add functional coverage to this component to implement coverage model. + `uvm_info("UNIMPLEMENTED_COVERAGE_MODEL", "******************************************************************************************************",UVM_NONE) + `uvm_info("UNIMPLEMENTED_COVERAGE_MODEL", "UVMF_CHANGE_ME: This component needs to be completed with coverage model",UVM_NONE) + `uvm_info("UNIMPLEMENTED_COVERAGE_MODEL", "******************************************************************************************************",UVM_NONE) + // pragma uvmf custom jtag_cov_ae_coverage end + endfunction + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/verification_ip/environment_packages/jtag_env_pkg/src/jtag_env_configuration.svh b/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/verification_ip/environment_packages/jtag_env_pkg/src/jtag_env_configuration.svh new file mode 100644 index 00000000..e62c565e --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/verification_ip/environment_packages/jtag_env_pkg/src/jtag_env_configuration.svh @@ -0,0 +1,144 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: THis is the configuration for the jtag environment. +// it contains configuration classes for each agent. It also contains +// environment level configuration variables. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class jtag_env_configuration +extends uvmf_environment_configuration_base; + + `uvm_object_utils( jtag_env_configuration ) + + +//Constraints for the configuration variables: + + + covergroup jtag_configuration_cg; + // pragma uvmf custom covergroup begin + option.auto_bin_max=1024; + // pragma uvmf custom covergroup end + endgroup + + + typedef jtag_configuration jtag_in_config_t; + rand jtag_in_config_t jtag_in_config; + + typedef jtag_configuration jtag_out_config_t; + rand jtag_out_config_t jtag_out_config; + + + + + typedef uvmf_virtual_sequencer_base #(.CONFIG_T(jtag_env_configuration)) jtag_vsqr_t; + jtag_vsqr_t vsqr; + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + +// **************************************************************************** +// FUNCTION : new() +// This function is the standard SystemVerilog constructor. +// This function constructs the configuration object for each agent in the environment. +// + function new( string name = "" ); + super.new( name ); + + + jtag_in_config = jtag_in_config_t::type_id::create("jtag_in_config"); + jtag_out_config = jtag_out_config_t::type_id::create("jtag_out_config"); + + + jtag_configuration_cg=new; + `uvm_warning("COVERAGE_MODEL_REVIEW", "A covergroup has been constructed which may need review because of either generation or re-generation with merging. Please note that configuration variables added as a result of re-generation and merging are not automatically added to the covergroup. Remove this warning after the covergroup has been reviewed.") + + // pragma uvmf custom new begin + // pragma uvmf custom new end + endfunction + +// **************************************************************************** +// FUNCTION : set_vsqr() +// This function is used to assign the vsqr handle. + virtual function void set_vsqr( jtag_vsqr_t vsqr); + this.vsqr = vsqr; + endfunction : set_vsqr + +// **************************************************************************** +// FUNCTION: post_randomize() +// This function is automatically called after the randomize() function +// is executed. +// + function void post_randomize(); + super.post_randomize(); + // pragma uvmf custom post_randomize begin + // pragma uvmf custom post_randomize end + endfunction + +// **************************************************************************** +// FUNCTION: convert2string() +// This function converts all variables in this class to a single string for +// logfile reporting. This function concatenates the convert2string result for +// each agent configuration in this configuration class. +// + virtual function string convert2string(); + // pragma uvmf custom convert2string begin + return { + + "\n", jtag_in_config.convert2string, + "\n", jtag_out_config.convert2string + + + }; + // pragma uvmf custom convert2string end + endfunction +// **************************************************************************** +// FUNCTION: initialize(); +// This function configures each interface agents configuration class. The +// sim level determines the active/passive state of the agent. The environment_path +// identifies the hierarchy down to and including the instantiation name of the +// environment for this configuration class. Each instance of the environment +// has its own configuration class. The string interface names are used by +// the agent configurations to identify the virtual interface handle to pull from +// the uvm_config_db. +// + function void initialize(uvmf_sim_level_t sim_level, + string environment_path, + string interface_names[], + uvm_reg_block register_model = null, + uvmf_active_passive_t interface_activity[] = {} + ); + + super.initialize(sim_level, environment_path, interface_names, register_model, interface_activity); + + + + // Interface initialization for local agents + jtag_in_config.initialize( interface_activity[0], {environment_path,".jtag_in"}, interface_names[0]); + jtag_in_config.initiator_responder = INITIATOR; + // jtag_in_config.has_coverage = 1; + jtag_out_config.initialize( interface_activity[1], {environment_path,".jtag_out"}, interface_names[1]); + jtag_out_config.initiator_responder = RESPONDER; + // jtag_out_config.has_coverage = 1; + + + + + + // pragma uvmf custom initialize begin + // pragma uvmf custom initialize end + + endfunction + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/verification_ip/environment_packages/jtag_env_pkg/src/jtag_env_sequence_base.svh b/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/verification_ip/environment_packages/jtag_env_pkg/src/jtag_env_sequence_base.svh new file mode 100644 index 00000000..e2c6c48a --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/verification_ip/environment_packages/jtag_env_pkg/src/jtag_env_sequence_base.svh @@ -0,0 +1,69 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This file contains environment level sequences that will +// be reused from block to top level simulations. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class jtag_env_sequence_base #( + type CONFIG_T + ) extends uvmf_virtual_sequence_base #(.CONFIG_T(CONFIG_T)); + + + `uvm_object_param_utils( jtag_env_sequence_base #( + CONFIG_T + ) ); + + +// This jtag_env_sequence_base contains a handle to a jtag_env_configuration object +// named configuration. This configuration variable contains a handle to each +// sequencer within each agent within this environment and any sub-environments. +// The configuration object handle is automatically assigned in the pre_body in the +// base class of this sequence. The configuration handle is retrieved from the +// virtual sequencer that this sequence is started on. +// Available sequencer handles within the environment configuration: + + // Initiator agent sequencers in jtag_environment: + // configuration.jtag_in_config.sequencer + + // Responder agent sequencers in jtag_environment: + // configuration.jtag_out_config.sequencer + + + typedef jtag_random_sequence jtag_in_random_sequence_t; + jtag_in_random_sequence_t jtag_in_rand_seq; + + + + + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + function new(string name = "" ); + super.new(name); + jtag_in_rand_seq = jtag_in_random_sequence_t::type_id::create("jtag_in_rand_seq"); + + + endfunction + + virtual task body(); + + if ( configuration.jtag_in_config.sequencer != null ) + repeat (25) jtag_in_rand_seq.start(configuration.jtag_in_config.sequencer); + + + endtask + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/verification_ip/environment_packages/jtag_env_pkg/src/jtag_env_typedefs.svh b/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/verification_ip/environment_packages/jtag_env_pkg/src/jtag_env_typedefs.svh new file mode 100644 index 00000000..9814bd58 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/verification_ip/environment_packages/jtag_env_pkg/src/jtag_env_typedefs.svh @@ -0,0 +1,20 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: +// This file contains defines and typedefs to be compiled for use in +// the environment package. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// + + + // pragma uvmf custom additional begin + // pragma uvmf custom additional end + diff --git a/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/verification_ip/environment_packages/jtag_env_pkg/src/jtag_environment.svh b/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/verification_ip/environment_packages/jtag_env_pkg/src/jtag_environment.svh new file mode 100644 index 00000000..53aa582a --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/verification_ip/environment_packages/jtag_env_pkg/src/jtag_environment.svh @@ -0,0 +1,131 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This environment contains all agents, predictors and +// scoreboards required for the block level design. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// + +class jtag_environment extends uvmf_environment_base #( + .CONFIG_T( jtag_env_configuration + )); + `uvm_component_utils( jtag_environment ) + + + + uvm_analysis_port #(jtag_transaction) jtag_in_ap; + uvm_analysis_port #(jtag_transaction) jtag_out_ap; + + + typedef jtag_agent jtag_in_t; + jtag_in_t jtag_in; + + typedef jtag_agent jtag_out_t; + jtag_out_t jtag_out; + + + + + typedef jtag_predictor #( + .CONFIG_T(CONFIG_T) + ) jtag_pred_t; + jtag_pred_t jtag_pred; + typedef jtag_coverage #( + .CONFIG_T(CONFIG_T) + ) jtag_cov_t; + jtag_cov_t jtag_cov; + + typedef uvmf_in_order_race_scoreboard #(.T(jtag_transaction)) jtag_sb_t; + jtag_sb_t jtag_sb; + + + + typedef uvmf_virtual_sequencer_base #(.CONFIG_T(jtag_env_configuration)) jtag_vsqr_t; + jtag_vsqr_t vsqr; + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + +// **************************************************************************** +// FUNCTION : new() +// This function is the standard SystemVerilog constructor. +// + function new( string name = "", uvm_component parent = null ); + super.new( name, parent ); + endfunction + +// **************************************************************************** +// FUNCTION: build_phase() +// This function builds all components within this environment. +// + virtual function void build_phase(uvm_phase phase); +// pragma uvmf custom build_phase_pre_super begin +// pragma uvmf custom build_phase_pre_super end + super.build_phase(phase); + jtag_in_ap = new("jtag_in_ap",this); + jtag_out_ap = new("jtag_out_ap",this); + jtag_in = jtag_in_t::type_id::create("jtag_in",this); + jtag_in.set_config(configuration.jtag_in_config); + jtag_out = jtag_out_t::type_id::create("jtag_out",this); + jtag_out.set_config(configuration.jtag_out_config); + jtag_pred = jtag_pred_t::type_id::create("jtag_pred",this); + jtag_pred.configuration = configuration; + jtag_cov = jtag_cov_t::type_id::create("jtag_cov",this); + jtag_cov.configuration = configuration; + jtag_sb = jtag_sb_t::type_id::create("jtag_sb",this); + + vsqr = jtag_vsqr_t::type_id::create("vsqr", this); + vsqr.set_config(configuration); + configuration.set_vsqr(vsqr); + + // pragma uvmf custom build_phase begin + // pragma uvmf custom build_phase end + endfunction + +// **************************************************************************** +// FUNCTION: connect_phase() +// This function makes all connections within this environment. Connections +// typically inclue agent to predictor, predictor to scoreboard and scoreboard +// to agent. +// + virtual function void connect_phase(uvm_phase phase); +// pragma uvmf custom connect_phase_pre_super begin +// pragma uvmf custom connect_phase_pre_super end + super.connect_phase(phase); + jtag_in.monitored_ap.connect(jtag_pred.jtag_in_ae); + jtag_pred.jtag_sb_ap.connect(jtag_sb.expected_analysis_export); + jtag_out.monitored_ap.connect(jtag_sb.actual_analysis_export); + jtag_in.monitored_ap.connect(jtag_cov.jtag_cov_ae); + jtag_in.monitored_ap.connect(jtag_in_ap); + jtag_out.monitored_ap.connect(jtag_out_ap); + // pragma uvmf custom reg_model_connect_phase begin + // pragma uvmf custom reg_model_connect_phase end + endfunction + +// **************************************************************************** +// FUNCTION: end_of_simulation_phase() +// This function is executed just prior to executing run_phase. This function +// was added to the environment to sample environment configuration settings +// just before the simulation exits time 0. The configuration structure is +// randomized in the build phase before the environment structure is constructed. +// Configuration variables can be customized after randomization in the build_phase +// of the extended test. +// If a sequence modifies values in the configuration structure then the sequence is +// responsible for sampling the covergroup in the configuration if required. +// + virtual function void start_of_simulation_phase(uvm_phase phase); + configuration.jtag_configuration_cg.sample(); + endfunction + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/verification_ip/environment_packages/jtag_env_pkg/src/jtag_predictor.svh b/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/verification_ip/environment_packages/jtag_env_pkg/src/jtag_predictor.svh new file mode 100644 index 00000000..4fbc2d8b --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/verification_ip/environment_packages/jtag_env_pkg/src/jtag_predictor.svh @@ -0,0 +1,114 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +// +//---------------------------------------------------------------------- +// +// DESCRIPTION: This analysis component contains analysis_exports for receiving +// data and analysis_ports for sending data. +// +// This analysis component has the following analysis_exports that receive the +// listed transaction type. +// +// jtag_in_ae receives transactions of type jtag_transaction +// +// This analysis component has the following analysis_ports that can broadcast +// the listed transaction type. +// +// jtag_sb_ap broadcasts transactions of type jtag_transaction +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// + +class jtag_predictor #( + type CONFIG_T, + type BASE_T = uvm_component + ) extends BASE_T; + + // Factory registration of this class + `uvm_component_param_utils( jtag_predictor #( + CONFIG_T, + BASE_T + )) + + + // Instantiate a handle to the configuration of the environment in which this component resides + CONFIG_T configuration; + + + // Instantiate the analysis exports + uvm_analysis_imp_jtag_in_ae #(jtag_transaction, jtag_predictor #( + .CONFIG_T(CONFIG_T), + .BASE_T(BASE_T) + )) jtag_in_ae; + + + // Instantiate the analysis ports + uvm_analysis_port #(jtag_transaction) jtag_sb_ap; + + + // Transaction variable for predicted values to be sent out jtag_sb_ap + // Once a transaction is sent through an analysis_port, another transaction should + // be constructed for the next predicted transaction. + typedef jtag_transaction jtag_sb_ap_output_transaction_t; + jtag_sb_ap_output_transaction_t jtag_sb_ap_output_transaction; + // Code for sending output transaction out through jtag_sb_ap + // jtag_sb_ap.write(jtag_sb_ap_output_transaction); + + // Define transaction handles for debug visibility + jtag_transaction jtag_in_ae_debug; + + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + // FUNCTION: new + function new(string name, uvm_component parent); + super.new(name,parent); + `uvm_warning("PREDICTOR_REVIEW", "This predictor has been created either through generation or re-generation with merging. Remove this warning after the predictor has been reviewed.") + // pragma uvmf custom new begin + // pragma uvmf custom new end + endfunction + + // FUNCTION: build_phase + virtual function void build_phase (uvm_phase phase); + + jtag_in_ae = new("jtag_in_ae", this); + jtag_sb_ap =new("jtag_sb_ap", this ); + // pragma uvmf custom build_phase begin + // pragma uvmf custom build_phase end + endfunction + + // FUNCTION: write_jtag_in_ae + // Transactions received through jtag_in_ae initiate the execution of this function. + // This function performs prediction of DUT output values based on DUT input, configuration and state + virtual function void write_jtag_in_ae(jtag_transaction t); + // pragma uvmf custom jtag_in_ae_predictor begin + jtag_in_ae_debug = t; + `uvm_info("PRED", "Transaction Received through jtag_in_ae", UVM_MEDIUM) + `uvm_info("PRED", {" Data: ",t.convert2string()}, UVM_FULL) + // Construct one of each output transaction type. + jtag_sb_ap_output_transaction = jtag_sb_ap_output_transaction_t::type_id::create("jtag_sb_ap_output_transaction"); + // UVMF_CHANGE_ME: Implement predictor model here. + `uvm_info("UNIMPLEMENTED_PREDICTOR_MODEL", "******************************************************************************************************",UVM_NONE) + `uvm_info("UNIMPLEMENTED_PREDICTOR_MODEL", "UVMF_CHANGE_ME: The jtag_predictor::write_jtag_in_ae function needs to be completed with DUT prediction model",UVM_NONE) + `uvm_info("UNIMPLEMENTED_PREDICTOR_MODEL", "******************************************************************************************************",UVM_NONE) + + // Code for sending output transaction out through jtag_sb_ap + // Please note that each broadcasted transaction should be a different object than previously + // broadcasted transactions. Creation of a different object is done by constructing the transaction + // using either new() or create(). Broadcasting a transaction object more than once to either the + // same subscriber or multiple subscribers will result in unexpected and incorrect behavior. + jtag_sb_ap.write(jtag_sb_ap_output_transaction); + // pragma uvmf custom jtag_in_ae_predictor end + endfunction + + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/verification_ip/environment_packages/jtag_env_pkg/yaml/jtag_environment.yaml b/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/verification_ip/environment_packages/jtag_env_pkg/yaml/jtag_environment.yaml new file mode 100644 index 00000000..19db07fb --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/verification_ip/environment_packages/jtag_env_pkg/yaml/jtag_environment.yaml @@ -0,0 +1,50 @@ +uvmf: + environments: + jtag: + agents: + - initiator_responder: INITIATOR + name: jtag_in + type: jtag + - initiator_responder: RESPONDER + name: jtag_out + type: jtag + analysis_components: + - name: jtag_pred + parameters: [] + type: jtag_predictor + - name: jtag_cov + parameters: [] + type: jtag_coverage + analysis_exports: [] + analysis_ports: + - connected_to: jtag_in.monitored_ap + name: jtag_in_ap + trans_type: jtag_transaction + - connected_to: jtag_out.monitored_ap + name: jtag_out_ap + trans_type: jtag_transaction + config_constraints: [] + config_vars: [] + existing_library_component: 'True' + hvl_pkg_parameters: [] + non_uvmf_components: [] + parameters: [] + qvip_memory_agents: [] + scoreboards: + - name: jtag_sb + sb_type: uvmf_in_order_race_scoreboard + trans_type: jtag_transaction + subenvs: [] + tlm_connections: + - driver: jtag_in.monitored_ap + receiver: jtag_pred.jtag_in_ae + validate: 'True' + - driver: jtag_pred.jtag_sb_ap + receiver: jtag_sb.expected_analysis_export + validate: 'True' + - driver: jtag_out.monitored_ap + receiver: jtag_sb.actual_analysis_export + validate: 'True' + - driver: jtag_in.monitored_ap + receiver: jtag_cov.jtag_cov_ae + validate: 'True' diff --git a/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/verification_ip/environment_packages/jtag_env_pkg/yaml/jtag_util_comp_jtag_coverage.yaml b/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/verification_ip/environment_packages/jtag_env_pkg/yaml/jtag_util_comp_jtag_coverage.yaml new file mode 100644 index 00000000..b917f8af --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/verification_ip/environment_packages/jtag_env_pkg/yaml/jtag_util_comp_jtag_coverage.yaml @@ -0,0 +1,8 @@ +uvmf: + util_components: + jtag_coverage: + analysis_exports: + - name: jtag_cov_ae + type: jtag_transaction + existing_library_component: 'True' + type: coverage diff --git a/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/verification_ip/environment_packages/jtag_env_pkg/yaml/jtag_util_comp_jtag_predictor.yaml b/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/verification_ip/environment_packages/jtag_env_pkg/yaml/jtag_util_comp_jtag_predictor.yaml new file mode 100644 index 00000000..bb68cbb1 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/verification_ip/environment_packages/jtag_env_pkg/yaml/jtag_util_comp_jtag_predictor.yaml @@ -0,0 +1,11 @@ +uvmf: + util_components: + jtag_predictor: + analysis_exports: + - name: jtag_in_ae + type: jtag_transaction + analysis_ports: + - name: jtag_sb_ap + type: jtag_transaction + existing_library_component: 'True' + type: predictor diff --git a/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/verification_ip/interface_packages/jtag_pkg/.project b/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/verification_ip/interface_packages/jtag_pkg/.project new file mode 100644 index 00000000..387ef37d --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/verification_ip/interface_packages/jtag_pkg/.project @@ -0,0 +1,30 @@ + + + jtag_pkg + + + + + + org.python.pydev.PyDevBuilder + + + + + net.sf.sveditor.core.SVProjectBuilder + + + + + + net.sf.sveditor.core.SVNature + org.python.pydev.pythonNature + + + + UVMF_VIP_LIBRARY_HOME + $%7BPARENT-2-PROJECT_LOC%7D + + + + diff --git a/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/verification_ip/interface_packages/jtag_pkg/.svproject b/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/verification_ip/interface_packages/jtag_pkg/.svproject new file mode 100644 index 00000000..780ab8f0 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/verification_ip/interface_packages/jtag_pkg/.svproject @@ -0,0 +1,16 @@ + + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/verification_ip/interface_packages/jtag_pkg/Makefile b/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/verification_ip/interface_packages/jtag_pkg/Makefile new file mode 100644 index 00000000..b73e1e67 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/verification_ip/interface_packages/jtag_pkg/Makefile @@ -0,0 +1,66 @@ +# jtag interface packages source +# pragma uvmf custom additional begin +# pragma uvmf custom additional end + +jtag_PKG = \ + +incdir+$(UVMF_VIP_LIBRARY_HOME)/interface_packages/jtag_pkg \ + -F $(UVMF_VIP_LIBRARY_HOME)/interface_packages/jtag_pkg/jtag_filelist_hvl.f + +jtag_PKG_HDL = \ + +incdir+$(UVMF_VIP_LIBRARY_HOME)/interface_packages/jtag_pkg \ + -F $(UVMF_VIP_LIBRARY_HOME)/interface_packages/jtag_pkg/jtag_filelist_hdl.f + +jtag_PKG_XRTL = \ + +incdir+$(UVMF_VIP_LIBRARY_HOME)/interface_packages/jtag_pkg \ + -F $(UVMF_VIP_LIBRARY_HOME)/interface_packages/jtag_pkg/jtag_filelist_xrtl.f + +COMP_jtag_PKG_TGT_0 = q_comp_jtag_pkg +COMP_jtag_PKG_TGT_1 = v_comp_jtag_pkg +COMP_jtag_PKG_TGT = $(COMP_jtag_PKG_TGT_$(USE_VELOCE)) + +comp_jtag_pkg: $(COMP_jtag_PKG_TGT) + +q_comp_jtag_pkg: + $(HDL_COMP_CMD) $(jtag_PKG_HDL) + $(HVL_COMP_CMD) $(jtag_PKG) + $(HDL_COMP_CMD) $(jtag_PKG_XRTL) + +v_comp_jtag_pkg: + $(HVL_COMP_CMD) $(jtag_PKG_HDL) + $(HVL_COMP_CMD) $(jtag_PKG) + $(VELANALYZE_CMD) $(jtag_PKG_HDL) + $(VELANALYZE_HVL_CMD) $(jtag_PKG) + $(HDL_COMP_CMD) $(jtag_PKG_XRTL) + +ifeq ($(MTI_VCO_MODE),64) + GCC_COMP_ARCH = -m64 +else + GCC_COMP_ARCH = -m32 +endif + +export jtag_IF_DPI_SRC ?= $(UVMF_VIP_LIBRARY_HOME)/interface_packages/jtag_pkg/dpi + +C_FILE_COMPILE_LIST_jtag_pkg = \ + +O_FILE_COMPILE_LIST_jtag_pkg = $(notdir $(C_FILE_COMPILE_LIST_jtag_pkg:.c=.o)) + +GCC_COMP_ARGS_jtag_pkg += -I$(jtag_IF_DPI_SRC) \ + -fPIC + +GCC_COMP_ARGS_jtag_pkg += $(jtag_IF_GCC_COMP_ARGUMENTS) + +GCC_LINK_ARGS_jtag_pkg += \ + \ + -o .so + +comp_jtag_pkg_c_files: + @echo "--------------------------------" + @echo "Compiling Interface C source" + @echo "--------------------------------" + gcc $(GCC_COMP_ARCH) $(GCC_COMP_ARGS_jtag_pkg) $(C_FILE_COMPILE_LIST_jtag_pkg) + @echo "--------------------------------" + @echo "Linking Interface C objects into a shared object" + @echo "--------------------------------" + gcc $(GCC_COMP_ARCH) $(GCC_LINK_ARGS_jtag_pkg) $(O_FILE_COMPILE_LIST_jtag_pkg) + @echo "--------------------------------" + diff --git a/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/verification_ip/interface_packages/jtag_pkg/compile.do b/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/verification_ip/interface_packages/jtag_pkg/compile.do new file mode 100644 index 00000000..5bb67873 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/verification_ip/interface_packages/jtag_pkg/compile.do @@ -0,0 +1,14 @@ +# Tcl do file for compile of jtag interface + +# pragma uvmf custom additional begin +# pragma uvmf custom additional end + + +vlog -sv -timescale 1ps/1ps -suppress 2223,2286 +incdir+$env(UVMF_VIP_LIBRARY_HOME)/interface_packages/jtag_pkg \ + -F $env(UVMF_VIP_LIBRARY_HOME)/interface_packages/jtag_pkg/jtag_filelist_hdl.f + +vlog -sv -timescale 1ps/1ps -suppress 2223,2286 +incdir+$env(UVMF_VIP_LIBRARY_HOME)/interface_packages/jtag_pkg \ + -F $env(UVMF_VIP_LIBRARY_HOME)/interface_packages/jtag_pkg/jtag_filelist_hvl.f + +vlog -sv -timescale 1ps/1ps -suppress 2223,2286 +incdir+$env(UVMF_VIP_LIBRARY_HOME)/interface_packages/jtag_pkg \ + -F $env(UVMF_VIP_LIBRARY_HOME)/interface_packages/jtag_pkg/jtag_filelist_xrtl.f \ No newline at end of file diff --git a/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/verification_ip/interface_packages/jtag_pkg/jtag.compile b/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/verification_ip/interface_packages/jtag_pkg/jtag.compile new file mode 100644 index 00000000..8e85c55c --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/verification_ip/interface_packages/jtag_pkg/jtag.compile @@ -0,0 +1,3 @@ +needs: + - jtag_hvl.compile + - jtag_hdl.compile diff --git a/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/verification_ip/interface_packages/jtag_pkg/jtag_bfm.vinfo b/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/verification_ip/interface_packages/jtag_pkg/jtag_bfm.vinfo new file mode 100644 index 00000000..62cece6f --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/verification_ip/interface_packages/jtag_pkg/jtag_bfm.vinfo @@ -0,0 +1,6 @@ +@use $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg_hdl.vinfo +@use jtag_pkg_hdl.vinfo ++incdir+@vinfodir +src/jtag_if.sv +src/jtag_driver_bfm.sv +src/jtag_monitor_bfm.sv diff --git a/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/verification_ip/interface_packages/jtag_pkg/jtag_common.compile b/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/verification_ip/interface_packages/jtag_pkg/jtag_common.compile new file mode 100644 index 00000000..ca6d9bbe --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/verification_ip/interface_packages/jtag_pkg/jtag_common.compile @@ -0,0 +1,7 @@ +needs: + - $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg_hdl.compile +incdir: + - . + - ${uvm_path}/src +src: + - jtag_pkg_hdl.sv diff --git a/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/verification_ip/interface_packages/jtag_pkg/jtag_filelist_hdl.f b/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/verification_ip/interface_packages/jtag_pkg/jtag_filelist_hdl.f new file mode 100644 index 00000000..5e8cb349 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/verification_ip/interface_packages/jtag_pkg/jtag_filelist_hdl.f @@ -0,0 +1 @@ +$UVMF_VIP_LIBRARY_HOME/interface_packages/jtag_pkg/jtag_pkg_hdl.sv diff --git a/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/verification_ip/interface_packages/jtag_pkg/jtag_filelist_hvl.f b/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/verification_ip/interface_packages/jtag_pkg/jtag_filelist_hvl.f new file mode 100644 index 00000000..6acb81bd --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/verification_ip/interface_packages/jtag_pkg/jtag_filelist_hvl.f @@ -0,0 +1 @@ +$UVMF_VIP_LIBRARY_HOME/interface_packages/jtag_pkg/jtag_pkg.sv \ No newline at end of file diff --git a/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/verification_ip/interface_packages/jtag_pkg/jtag_filelist_xrtl.f b/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/verification_ip/interface_packages/jtag_pkg/jtag_filelist_xrtl.f new file mode 100644 index 00000000..569489e0 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/verification_ip/interface_packages/jtag_pkg/jtag_filelist_xrtl.f @@ -0,0 +1,3 @@ +$UVMF_VIP_LIBRARY_HOME/interface_packages/jtag_pkg/src/jtag_if.sv +$UVMF_VIP_LIBRARY_HOME/interface_packages/jtag_pkg/src/jtag_monitor_bfm.sv +$UVMF_VIP_LIBRARY_HOME/interface_packages/jtag_pkg/src/jtag_driver_bfm.sv diff --git a/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/verification_ip/interface_packages/jtag_pkg/jtag_hdl.compile b/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/verification_ip/interface_packages/jtag_pkg/jtag_hdl.compile new file mode 100644 index 00000000..10b6d827 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/verification_ip/interface_packages/jtag_pkg/jtag_hdl.compile @@ -0,0 +1,9 @@ +needs: + - $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg_hdl.compile + - ./jtag_common.compile +incdir: + - . +src: + - src/jtag_if.sv + - src/jtag_monitor_bfm.sv + - src/jtag_driver_bfm.sv diff --git a/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/verification_ip/interface_packages/jtag_pkg/jtag_hvl.compile b/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/verification_ip/interface_packages/jtag_pkg/jtag_hvl.compile new file mode 100644 index 00000000..59847804 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/verification_ip/interface_packages/jtag_pkg/jtag_hvl.compile @@ -0,0 +1,7 @@ +needs: + - $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg.compile + - ./jtag_common.compile +incdir: + - . +src: + - jtag_pkg.sv diff --git a/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/verification_ip/interface_packages/jtag_pkg/jtag_pkg.sv b/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/verification_ip/interface_packages/jtag_pkg/jtag_pkg.sv new file mode 100644 index 00000000..b8821a03 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/verification_ip/interface_packages/jtag_pkg/jtag_pkg.sv @@ -0,0 +1,77 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// PACKAGE: This file defines all of the files contained in the +// interface package that will run on the host simulator. +// +// CONTAINS: +// - +// - +// - + +// - +// - +// - + +// - +// - +// - + +// - +// - +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +package jtag_pkg; + + import uvm_pkg::*; + import uvmf_base_pkg_hdl::*; + import uvmf_base_pkg::*; + import jtag_pkg_hdl::*; + + `include "uvm_macros.svh" + + // pragma uvmf custom package_imports_additional begin + // pragma uvmf custom package_imports_additional end + `include "src/jtag_macros.svh" + + export jtag_pkg_hdl::*; + + + + // Parameters defined as HVL parameters + + `include "src/jtag_typedefs.svh" + `include "src/jtag_transaction.svh" + + `include "src/jtag_configuration.svh" + `include "src/jtag_driver.svh" + `include "src/jtag_monitor.svh" + + `include "src/jtag_transaction_coverage.svh" + `include "src/jtag_sequence_base.svh" + `include "src/jtag_random_sequence.svh" + + `include "src/jtag_responder_sequence.svh" + `include "src/jtag2reg_adapter.svh" + + `include "src/jtag_agent.svh" + + // pragma uvmf custom package_item_additional begin + // UVMF_CHANGE_ME : When adding new interface sequences to the src directory + // be sure to add the sequence file here so that it will be + // compiled as part of the interface package. Be sure to place + // the new sequence after any base sequences of the new sequence. + // pragma uvmf custom package_item_additional end + +endpackage + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/verification_ip/interface_packages/jtag_pkg/jtag_pkg.vinfo b/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/verification_ip/interface_packages/jtag_pkg/jtag_pkg.vinfo new file mode 100644 index 00000000..5f9af737 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/verification_ip/interface_packages/jtag_pkg/jtag_pkg.vinfo @@ -0,0 +1,4 @@ +@use $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg.vinfo +@use jtag_pkg_hdl.vinfo ++incdir+@vinfodir +jtag_pkg.sv diff --git a/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/verification_ip/interface_packages/jtag_pkg/jtag_pkg_hdl.sv b/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/verification_ip/interface_packages/jtag_pkg/jtag_pkg_hdl.sv new file mode 100644 index 00000000..6a3c9986 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/verification_ip/interface_packages/jtag_pkg/jtag_pkg_hdl.sv @@ -0,0 +1,38 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// PACKAGE: This file defines all of the files contained in the +// interface package that needs to be compiled and synthesized +// for running on Veloce. +// +// CONTAINS: +// - +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +package jtag_pkg_hdl; + + import uvmf_base_pkg_hdl::*; + + // pragma uvmf custom package_imports_additional begin + // pragma uvmf custom package_imports_additional end + + // Parameters defined as HDL parameters + + `include "src/jtag_typedefs_hdl.svh" + `include "src/jtag_macros.svh" + + // pragma uvmf custom package_item_additional begin + // pragma uvmf custom package_item_additional end + +endpackage + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/verification_ip/interface_packages/jtag_pkg/jtag_pkg_hdl.vinfo b/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/verification_ip/interface_packages/jtag_pkg/jtag_pkg_hdl.vinfo new file mode 100644 index 00000000..de7d8813 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/verification_ip/interface_packages/jtag_pkg/jtag_pkg_hdl.vinfo @@ -0,0 +1,2 @@ +@use $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg_hdl.vinfo +jtag_pkg_hdl.sv diff --git a/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/verification_ip/interface_packages/jtag_pkg/jtag_pkg_sve.F b/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/verification_ip/interface_packages/jtag_pkg/jtag_pkg_sve.F new file mode 100644 index 00000000..69ea9fa2 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/verification_ip/interface_packages/jtag_pkg/jtag_pkg_sve.F @@ -0,0 +1,10 @@ +// UVM ++incdir+${UVM_HOME}/src +${UVM_HOME}/src/uvm_pkg.sv + +// Common UVMF files +-f ${UVMF_HOME}/common/common_sve.f + ++incdir+. +-f ${UVMF_VIP_LIBRARY_HOME}/interface_packages/jtag_pkg/jtag_filelist_hdl.f +-f ${UVMF_VIP_LIBRARY_HOME}/interface_packages/jtag_pkg/jtag_filelist_hvl.f diff --git a/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/verification_ip/interface_packages/jtag_pkg/src/jtag2reg_adapter.svh b/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/verification_ip/interface_packages/jtag_pkg/src/jtag2reg_adapter.svh new file mode 100644 index 00000000..f1aac60c --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/verification_ip/interface_packages/jtag_pkg/src/jtag2reg_adapter.svh @@ -0,0 +1,98 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: +// This file contains the UVM register adapter for the jtag interface. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class jtag2reg_adapter extends uvm_reg_adapter; + + `uvm_object_utils( jtag2reg_adapter ) + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + //-------------------------------------------------------------------- + // new + //-------------------------------------------------------------------- + function new (string name = "jtag2reg_adapter" ); + super.new(name); + // pragma uvmf custom new begin + // UVMF_CHANGE_ME : Configure the adapter regarding byte enables and provides response. + + // Does the protocol the Agent is modeling support byte enables? + // 0 = NO + // 1 = YES + supports_byte_enable = 0; + + // Does the Agent's Driver provide separate response sequence items? + // i.e. Does the driver call seq_item_port.put() + // and do the sequences call get_response()? + // 0 = NO + // 1 = YES + provides_responses = 0; + // pragma uvmf custom new end + + endfunction: new + + //-------------------------------------------------------------------- + // reg2bus + //-------------------------------------------------------------------- + virtual function uvm_sequence_item reg2bus(const ref uvm_reg_bus_op rw); + + jtag_transaction trans_h = jtag_transaction ::type_id::create("trans_h"); + + // pragma uvmf custom reg2bus begin + // UVMF_CHANGE_ME : Fill in the reg2bus adapter mapping registe fields to protocol fields. + + //Adapt the following for your sequence item type + // trans_h.op = (rw.kind == UVM_READ) ? WB_READ : WB_WRITE; + //Copy over address + // trans_h.addr = rw.addr; + //Copy over write data + // trans_h.data = rw.data; + + // pragma uvmf custom reg2bus end + + // Return the adapted transaction + return trans_h; + + endfunction: reg2bus + + //-------------------------------------------------------------------- + // bus2reg + //-------------------------------------------------------------------- + virtual function void bus2reg(uvm_sequence_item bus_item, + ref uvm_reg_bus_op rw); + jtag_transaction trans_h; + if (!$cast(trans_h, bus_item)) begin + `uvm_fatal("ADAPT","Provided bus_item is not of the correct type") + return; + end + // pragma uvmf custom bus2reg begin + // UVMF_CHANGE_ME : Fill in the bus2reg adapter mapping protocol fields to register fields. + //Adapt the following for your sequence item type + //Copy over instruction type + // rw.kind = (trans_h.op == WB_WRITE) ? UVM_WRITE : UVM_READ; + //Copy over address + // rw.addr = trans_h.addr; + //Copy over read data + // rw.data = trans_h.data; + //Check for errors on the bus and return UVM_NOT_OK if there is an error + // rw.status = UVM_IS_OK; + // pragma uvmf custom bus2reg end + + endfunction: bus2reg + +endclass : jtag2reg_adapter + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/verification_ip/interface_packages/jtag_pkg/src/jtag_agent.svh b/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/verification_ip/interface_packages/jtag_pkg/src/jtag_agent.svh new file mode 100644 index 00000000..3a3149d3 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/verification_ip/interface_packages/jtag_pkg/src/jtag_agent.svh @@ -0,0 +1,53 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: Protocol specific agent class definition +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class jtag_agent extends uvmf_parameterized_agent #( + .CONFIG_T(jtag_configuration ), + .DRIVER_T(jtag_driver ), + .MONITOR_T(jtag_monitor ), + .COVERAGE_T(jtag_transaction_coverage ), + .TRANS_T(jtag_transaction ) + ); + + `uvm_component_utils( jtag_agent ) + +// pragma uvmf custom class_item_additional begin +// pragma uvmf custom class_item_additional end + +// **************************************************************************** +// FUNCTION : new() +// This function is the standard SystemVerilog constructor. +// + function new( string name = "", uvm_component parent = null ); + super.new( name, parent ); + endfunction + +// **************************************************************************** + // FUNCTION: build_phase + virtual function void build_phase(uvm_phase phase); +// pragma uvmf custom build_phase_pre_super begin +// pragma uvmf custom build_phase_pre_super end + super.build_phase(phase); + if (configuration.active_passive == ACTIVE) begin + // Place sequencer handle into configuration object + // so that it may be retrieved from configuration + // rather than using uvm_config_db + configuration.sequencer = this.sequencer; + end + endfunction + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/verification_ip/interface_packages/jtag_pkg/src/jtag_configuration.svh b/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/verification_ip/interface_packages/jtag_pkg/src/jtag_configuration.svh new file mode 100644 index 00000000..c9010198 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/verification_ip/interface_packages/jtag_pkg/src/jtag_configuration.svh @@ -0,0 +1,185 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This class contains all variables and functions used +// to configure the jtag agent and its bfm's. It gets the +// bfm's from the uvm_config_db for use by the agent. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class jtag_configuration extends uvmf_parameterized_agent_configuration_base #( + .DRIVER_BFM_BIND_T(virtual jtag_driver_bfm ), + .MONITOR_BFM_BIND_T( virtual jtag_monitor_bfm )); + + `uvm_object_utils( jtag_configuration ) + + bit is_active = 1; + bit [3:0] no_of_slaves = 0; + bit has_coverage = 1; + + // Sequencer handle populated by agent + uvm_sequencer #(jtag_transaction ) sequencer; + + //Constraints for the configuration variables: + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + covergroup jtag_configuration_cg; + // pragma uvmf custom covergroup begin + option.auto_bin_max=1024; + coverpoint is_active; + coverpoint no_of_slaves; + coverpoint has_coverage; + // pragma uvmf custom covergroup end + endgroup + + //******************************************************************* + //******************************************************************* + // Structure used to pass configuration variables to monitor and driver BFM's. + // Use to_struct function to pack variables into structure. + // Use from_struct function to unpack variables from structure. + // This structure is defined in jtag_macros.svh + `jtag_CONFIGURATION_STRUCT + jtag_configuration_s jtag_configuration_struct; + //******************************************************************* + // FUNCTION: to_struct() + // This function packs variables into a jtag_configuration_s + // structure. The function returns the handle to the jtag_configuration_struct. + // This function is defined in jtag_macros.svh + `jtag_CONFIGURATION_TO_STRUCT_FUNCTION + //******************************************************************* + // FUNCTION: from_struct() + // This function unpacks the struct provided as an argument into + // variables of this class. + // This function is defined in jtag_macros.svh + `jtag_CONFIGURATION_FROM_STRUCT_FUNCTION + + // **************************************************************************** + // FUNCTION : new() + // This function is the standard SystemVerilog constructor. + // + function new( string name = "" ); + super.new( name ); + // Construct the covergroup for this configuration class + jtag_configuration_cg = new; + endfunction + + // **************************************************************************** + // FUNCTION: post_randomize() + // This function is automatically called after the randomize() function + // is executed. + // + function void post_randomize(); + super.post_randomize(); + jtag_configuration_cg.sample(); + endfunction + + // **************************************************************************** + // FUNCTION: initialize + // This function causes the configuration to retrieve + // its virtual interface handle from the uvm_config_db. + // This function also makes itself available to its + // agent through the uvm_config_db. + // + // ARGUMENTS: + // uvmf_active_passive_t activity: + // This argument identifies the simulation level + // as either BLOCK, CHIP, SIMULATION, etc. + // + // AGENT_PATH: + // This argument identifies the path to this + // configurations agent. This configuration + // makes itself available to the agent specified + // by agent_path by placing itself into the + // uvm_config_db. + // + // INTERFACE_NAME: + // This argument identifies the string name of + // this configurations BFM's. This string + // name is used to retrieve the driver and + // monitor BFM from the uvm_config_db. + // + virtual function void initialize(uvmf_active_passive_t activity, + string agent_path, + string interface_name); + + super.initialize( activity, agent_path, interface_name); + // The covergroup is given the same name as the interface + jtag_configuration_cg.set_inst_name(interface_name); + + // This configuration places itself into the uvm_config_db for the agent, identified by the agent_path variable, to retrieve. + uvm_config_db #( jtag_configuration + )::set( null ,agent_path,UVMF_AGENT_CONFIG, this ); + + // This configuration also places itself in the config db using the same identifier used by the interface. This allows users to access + // configuration variables and the interface through the bfm api class rather than directly accessing the BFM. This is useful for + // accessingthe BFM when using Veloce + uvm_config_db #( jtag_configuration + )::set( null ,UVMF_CONFIGURATIONS, interface_name, this ); + + jtag_configuration_cg.set_inst_name($sformatf("jtag_configuration_cg_%s",get_full_name())); + +// This code is to aid in debugging parameter mismatches between the BFM and its corresponding agent. +// Enable this debug by setting UVM_VERBOSITY to UVM_DEBUG +// Setting UVM_VERBOSITY to UVM_DEBUG causes all BFM's and all agents to display their parameter settings. +// All of the messages from this feature have a UVM messaging id value of "CFG" +// The transcript or run.log can be parsed to ensure BFM parameter settings match its corresponding agents parameter settings. + `uvm_info("CFG", + $psprintf("The agent at '%s' is using interface named %s has the following parameters: ", agent_path, interface_name, ), + UVM_DEBUG) + + // pragma uvmf custom initialize begin + // This controls whether or not the agent returns a transaction handle in the driver when calling + // item_done() back into the sequencer or not. If set to 1, a transaction is sent back which means + // the sequence on the other end must use the get_response() part of the driver/sequence API. If + // this doesn't occur, there will eventually be response_queue overflow errors during the test. + return_transaction_response = 1'b0; + + // pragma uvmf custom initialize end + + endfunction + + // **************************************************************************** + // TASK: wait_for_reset + // *[Required]* Blocks until reset is released. The wait_for_reset operation is performed + // by a task in the monitor bfm. + virtual task wait_for_reset(); + monitor_bfm.wait_for_reset(); + endtask + + // **************************************************************************** + // TASK: wait_for_num_clocks + // *[Required]* Blocks until specified number of clocks have elapsed. The wait_for_num_clocks + // operation is performed by a task in the monitor bfm. + virtual task wait_for_num_clocks(int clocks); + monitor_bfm.wait_for_num_clocks(clocks); + endtask + + // **************************************************************************** + // FUNCTION : convert2string() + // This function is used to convert variables in this class into a string for log messaging. + // + virtual function string convert2string (); + // pragma uvmf custom convert2string begin + return $sformatf("is_active:0x%x no_of_slaves:0x%x has_coverage:0x%x ",is_active,no_of_slaves,has_coverage); + // pragma uvmf custom convert2string end + endfunction + + // **************************************************************************** + // FUNCTION: get_sequencer + function uvm_sequencer #(jtag_transaction) get_sequencer(); + return sequencer; + endfunction + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/verification_ip/interface_packages/jtag_pkg/src/jtag_driver.svh b/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/verification_ip/interface_packages/jtag_pkg/src/jtag_driver.svh new file mode 100644 index 00000000..768d6462 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/verification_ip/interface_packages/jtag_pkg/src/jtag_driver.svh @@ -0,0 +1,91 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This class passes transactions between the sequencer +// and the BFM driver interface. It accesses the driver BFM +// through the bfm handle. This driver +// passes transactions to the driver BFM through the access +// task. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class jtag_driver extends uvmf_driver_base #( + .CONFIG_T(jtag_configuration ), + .BFM_BIND_T(virtual jtag_driver_bfm ), + .REQ(jtag_transaction ), + .RSP(jtag_transaction )); + + `uvm_component_utils( jtag_driver ) +//******************************************************************* +// Macros that define structs located in jtag_macros.svh +//******************************************************************* +// Initiator macro used by jtag_driver and jtag_driver_bfm +// to communicate initiator driven data to jtag_driver_bfm. +`jtag_INITIATOR_STRUCT + jtag_initiator_s jtag_initiator_struct; +//******************************************************************* +// Responder macro used by jtag_driver and jtag_driver_bfm +// to communicate Responder driven data to jtag_driver_bfm. +`jtag_RESPONDER_STRUCT + jtag_responder_s jtag_responder_struct; + +// pragma uvmf custom class_item_additional begin +// pragma uvmf custom class_item_additional end + +// **************************************************************************** +// This function is the standard SystemVerilog constructor. +// + function new( string name = "", uvm_component parent=null ); + super.new( name, parent ); + endfunction + +// **************************************************************************** +// This function sends configuration object variables to the driver BFM +// using the configuration struct. +// + virtual function void configure(input CONFIG_T cfg); + bfm.configure( cfg.to_struct() ); + endfunction + +// **************************************************************************** +// This function places a handle to this class in the proxy variable in the +// driver BFM. This allows the driver BFM to call tasks and function within this class. +// + virtual function void set_bfm_proxy_handle(); + bfm.proxy = this; endfunction + +// **************************************************************************** +// This task is called by the run_phase in uvmf_driver_base. + virtual task access( inout REQ txn ); +// pragma uvmf custom access begin + if (configuration.initiator_responder==RESPONDER) begin + // Complete current transfer and wait for next transfer + bfm.respond_and_wait_for_next_transfer( + jtag_initiator_struct, + txn.to_responder_struct() + ); + // Unpack information about initiated transfer received by this responder + txn.from_initiator_struct(jtag_initiator_struct); + end else begin + // Initiate a transfer and get response + bfm.initiate_and_get_response( + txn.to_initiator_struct(), + jtag_responder_struct + ); + // Unpack transfer response information received by this initiator + txn.from_responder_struct(jtag_responder_struct); + end +// pragma uvmf custom access end + endtask + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/verification_ip/interface_packages/jtag_pkg/src/jtag_driver_bfm.sv b/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/verification_ip/interface_packages/jtag_pkg/src/jtag_driver_bfm.sv new file mode 100644 index 00000000..22f7ca1d --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/verification_ip/interface_packages/jtag_pkg/src/jtag_driver_bfm.sv @@ -0,0 +1,310 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: +// This interface performs the jtag signal driving. It is +// accessed by the uvm jtag driver through a virtual interface +// handle in the jtag configuration. It drives the singals passed +// in through the port connection named bus of type jtag_if. +// +// Input signals from the jtag_if are assigned to an internal input +// signal with a _i suffix. The _i signal should be used for sampling. +// +// The input signal connections are as follows: +// bus.signal -> signal_i +// +// This bfm drives signals with a _o suffix. These signals +// are driven onto signals within jtag_if based on INITIATOR/RESPONDER and/or +// ARBITRATION/GRANT status. +// +// The output signal connections are as follows: +// signal_o -> bus.signal +// +// +// Interface functions and tasks used by UVM components: +// +// configure: +// This function gets configuration attributes from the +// UVM driver to set any required BFM configuration +// variables such as 'initiator_responder'. +// +// initiate_and_get_response: +// This task is used to perform signaling activity for initiating +// a protocol transfer. The task initiates the transfer, using +// input data from the initiator struct. Then the task captures +// response data, placing the data into the response struct. +// The response struct is returned to the driver class. +// +// respond_and_wait_for_next_transfer: +// This task is used to complete a current transfer as a responder +// and then wait for the initiator to start the next transfer. +// The task uses data in the responder struct to drive protocol +// signals to complete the transfer. The task then waits for +// the next transfer. Once the next transfer begins, data from +// the initiator is placed into the initiator struct and sent +// to the responder sequence for processing to determine +// what data to respond with. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +import uvmf_base_pkg_hdl::*; +import jtag_pkg_hdl::*; +`include "src/jtag_macros.svh" + +interface jtag_driver_bfm + (jtag_if bus); + // The following pragma and additional ones in-lined further below are for running this BFM on Veloce + // pragma attribute jtag_driver_bfm partition_interface_xif + +`ifndef XRTL +// This code is to aid in debugging parameter mismatches between the BFM and its corresponding agent. +// Enable this debug by setting UVM_VERBOSITY to UVM_DEBUG +// Setting UVM_VERBOSITY to UVM_DEBUG causes all BFM's and all agents to display their parameter settings. +// All of the messages from this feature have a UVM messaging id value of "CFG" +// The transcript or run.log can be parsed to ensure BFM parameter settings match its corresponding agents parameter settings. +import uvm_pkg::*; +`include "uvm_macros.svh" +initial begin : bfm_vs_agent_parameter_debug + `uvm_info("CFG", + $psprintf("The BFM at '%m' has the following parameters: ", ), + UVM_DEBUG) +end +`endif + + // Config value to determine if this is an initiator or a responder + uvmf_initiator_responder_t initiator_responder; + // Custom configuration variables. + // These are set using the configure function which is called during the UVM connect_phase + bit is_active ; + bit [3:0] no_of_slaves ; + bit has_coverage ; + + tri clock_i; + tri reset_i; + + // Signal list (all signals are capable of being inputs and outputs for the sake + // of supporting both INITIATOR and RESPONDER mode operation. Expectation is that + // directionality in the config file was from the point-of-view of the INITIATOR + + // INITIATOR mode input signals + tri tdo_i; + reg tdo_o = 1'b0; + + // INITIATOR mode output signals + tri tck_i; + reg tck_o = 1'b0; + tri tms_i; + reg tms_o = 1'b0; + tri tdi_i; + reg tdi_o = 1'b0; + + // Bi-directional signals + + + assign clock_i = bus.clock; + assign reset_i = bus.reset; + + // These are signals marked as 'input' by the config file, but the signals will be + // driven by this BFM if put into RESPONDER mode (flipping all signal directions around) + assign tdo_i = bus.tdo; + assign bus.tdo = (initiator_responder == RESPONDER) ? tdo_o : 'bz; + + + // These are signals marked as 'output' by the config file, but the outputs will + // not be driven by this BFM unless placed in INITIATOR mode. + assign bus.tck = (initiator_responder == INITIATOR) ? tck_o : 'bz; + assign tck_i = bus.tck; + assign bus.tms = (initiator_responder == INITIATOR) ? tms_o : 'bz; + assign tms_i = bus.tms; + assign bus.tdi = (initiator_responder == INITIATOR) ? tdi_o : 'bz; + assign tdi_i = bus.tdi; + + // Proxy handle to UVM driver + jtag_pkg::jtag_driver proxy; + // pragma tbx oneway proxy.my_function_name_in_uvm_driver + + // **************************************************************************** + // **************************************************************************** + // Macros that define structs located in jtag_macros.svh + // **************************************************************************** + // Struct for passing configuration data from jtag_driver to this BFM + // **************************************************************************** + `jtag_CONFIGURATION_STRUCT + // **************************************************************************** + // Structs for INITIATOR and RESPONDER data flow + //******************************************************************* + // Initiator macro used by jtag_driver and jtag_driver_bfm + // to communicate initiator driven data to jtag_driver_bfm. + `jtag_INITIATOR_STRUCT + jtag_initiator_s initiator_struct; + // Responder macro used by jtag_driver and jtag_driver_bfm + // to communicate Responder driven data to jtag_driver_bfm. + `jtag_RESPONDER_STRUCT + jtag_responder_s responder_struct; + + // **************************************************************************** +// pragma uvmf custom reset_condition_and_response begin + // Always block used to return signals to reset value upon assertion of reset + always @( posedge reset_i ) + begin + // RESPONDER mode output signals + tdo_o <= 1'b0; + // INITIATOR mode output signals + tck_o <= 1'b0; + tms_o <= 1'b0; + tdi_o <= 1'b0; + // Bi-directional signals + + end +// pragma uvmf custom reset_condition_and_response end + + // pragma uvmf custom interface_item_additional begin + // pragma uvmf custom interface_item_additional end + + //****************************************************************** + // The configure() function is used to pass agent configuration + // variables to the driver BFM. It is called by the driver within + // the agent at the beginning of the simulation. It may be called + // during the simulation if agent configuration variables are updated + // and the driver BFM needs to be aware of the new configuration + // variables. + // + + function void configure(jtag_configuration_s jtag_configuration_arg); // pragma tbx xtf + initiator_responder = jtag_configuration_arg.initiator_responder; + is_active = jtag_configuration_arg.is_active; + no_of_slaves = jtag_configuration_arg.no_of_slaves; + has_coverage = jtag_configuration_arg.has_coverage; + // pragma uvmf custom configure begin + // pragma uvmf custom configure end + endfunction + +// pragma uvmf custom initiate_and_get_response begin +// **************************************************************************** +// UVMF_CHANGE_ME +// This task is used by an initator. The task first initiates a transfer then +// waits for the responder to complete the transfer. + task initiate_and_get_response( + // This argument passes transaction variables used by an initiator + // to perform the initial part of a protocol transfer. The values + // come from a sequence item created in a sequence. + input jtag_initiator_s jtag_initiator_struct, + // This argument is used to send data received from the responder + // back to the sequence item. The sequence item is returned to the sequence. + output jtag_responder_s jtag_responder_struct + );// pragma tbx xtf + // + // Members within the jtag_initiator_struct: + // bit tck ; + // bit tms ; + // bit tdi ; + // bit tdo ; + // Members within the jtag_responder_struct: + // bit tck ; + // bit tms ; + // bit tdi ; + // bit tdo ; + initiator_struct = jtag_initiator_struct; + // + // Reference code; + // How to wait for signal value + // while (control_signal == 1'b1) @(posedge clock_i); + // + // How to assign a responder struct member, named xyz, from a signal. + // All available initiator input and inout signals listed. + // Initiator input signals + // jtag_responder_struct.xyz = tdo_i; // + // Initiator inout signals + // How to assign a signal from an initiator struct member named xyz. + // All available initiator output and inout signals listed. + // Notice the _o. Those are storage variables that allow for procedural assignment. + // Initiator output signals + // tck_o <= jtag_initiator_struct.xyz; // + // tms_o <= jtag_initiator_struct.xyz; // + // tdi_o <= jtag_initiator_struct.xyz; // + // Initiator inout signals + // Initiate a transfer using the data received. + @(posedge clock_i); + @(posedge clock_i); + // Wait for the responder to complete the transfer then place the responder data into + // jtag_responder_struct. + @(posedge clock_i); + @(posedge clock_i); + responder_struct = jtag_responder_struct; + endtask +// pragma uvmf custom initiate_and_get_response end + +// pragma uvmf custom respond_and_wait_for_next_transfer begin +// **************************************************************************** +// The first_transfer variable is used to prevent completing a transfer in the +// first call to this task. For the first call to this task, there is not +// current transfer to complete. +bit first_transfer=1; + +// UVMF_CHANGE_ME +// This task is used by a responder. The task first completes the current +// transfer in progress then waits for the initiator to start the next transfer. + task respond_and_wait_for_next_transfer( + // This argument is used to send data received from the initiator + // back to the sequence item. The sequence determines how to respond. + output jtag_initiator_s jtag_initiator_struct, + // This argument passes transaction variables used by a responder + // to complete a protocol transfer. The values come from a sequence item. + input jtag_responder_s jtag_responder_struct + );// pragma tbx xtf + // Variables within the jtag_initiator_struct: + // bit tck ; + // bit tms ; + // bit tdi ; + // bit tdo ; + // Variables within the jtag_responder_struct: + // bit tck ; + // bit tms ; + // bit tdi ; + // bit tdo ; + // Reference code; + // How to wait for signal value + // while (control_signal == 1'b1) @(posedge clock_i); + // + // How to assign a responder struct member, named xyz, from a signal. + // All available responder input and inout signals listed. + // Responder input signals + // jtag_responder_struct.xyz = tck_i; // + // jtag_responder_struct.xyz = tms_i; // + // jtag_responder_struct.xyz = tdi_i; // + // Responder inout signals + // How to assign a signal, named xyz, from an initiator struct member. + // All available responder output and inout signals listed. + // Notice the _o. Those are storage variables that allow for procedural assignment. + // Responder output signals + // tdo_o <= jtag_initiator_struct.xyz; // + // Responder inout signals + + @(posedge clock_i); + if (!first_transfer) begin + // Perform transfer response here. + // Reply using data recieved in the jtag_responder_struct. + @(posedge clock_i); + // Reply using data recieved in the transaction handle. + @(posedge clock_i); + end + // Wait for next transfer then gather info from intiator about the transfer. + // Place the data into the jtag_initiator_struct. + @(posedge clock_i); + @(posedge clock_i); + first_transfer = 0; + endtask +// pragma uvmf custom respond_and_wait_for_next_transfer end + + +endinterface + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/verification_ip/interface_packages/jtag_pkg/src/jtag_if.sv b/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/verification_ip/interface_packages/jtag_pkg/src/jtag_if.sv new file mode 100644 index 00000000..ef26e5d7 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/verification_ip/interface_packages/jtag_pkg/src/jtag_if.sv @@ -0,0 +1,79 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This interface contains the jtag interface signals. +// It is instantiated once per jtag bus. Bus Functional Models, +// BFM's named jtag_driver_bfm, are used to drive signals on the bus. +// BFM's named jtag_monitor_bfm are used to monitor signals on the +// bus. This interface signal bundle is passed in the port list of +// the BFM in order to give the BFM access to the signals in this +// interface. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// This template can be used to connect a DUT to these signals +// +// .dut_signal_port(jtag_bus.tck), // Agent output +// .dut_signal_port(jtag_bus.tms), // Agent output +// .dut_signal_port(jtag_bus.tdi), // Agent output +// .dut_signal_port(jtag_bus.tdo), // Agent input + +import uvmf_base_pkg_hdl::*; +import jtag_pkg_hdl::*; + +interface jtag_if + + ( + input tri clock, + input tri reset, + inout tri tck, + inout tri tms, + inout tri tdi, + inout tri tdo + ); + +modport monitor_port + ( + input clock, + input reset, + input tck, + input tms, + input tdi, + input tdo + ); + +modport initiator_port + ( + input clock, + input reset, + output tck, + output tms, + output tdi, + input tdo + ); + +modport responder_port + ( + input clock, + input reset, + input tck, + input tms, + input tdi, + output tdo + ); + + +// pragma uvmf custom interface_item_additional begin +// pragma uvmf custom interface_item_additional end + +endinterface + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/verification_ip/interface_packages/jtag_pkg/src/jtag_infact_coverage_strategy.csv b/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/verification_ip/interface_packages/jtag_pkg/src/jtag_infact_coverage_strategy.csv new file mode 100644 index 00000000..1c218e14 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/verification_ip/interface_packages/jtag_pkg/src/jtag_infact_coverage_strategy.csv @@ -0,0 +1,6 @@ +Global +auto_bin_max, 64 + +Name,Type,Include +rand_fields,coverpoint,=rand *.** + diff --git a/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/verification_ip/interface_packages/jtag_pkg/src/jtag_macros.svh b/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/verification_ip/interface_packages/jtag_pkg/src/jtag_macros.svh new file mode 100644 index 00000000..4e09980d --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/verification_ip/interface_packages/jtag_pkg/src/jtag_macros.svh @@ -0,0 +1,157 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This file contains macros used with the jtag package. +// These macros include packed struct definitions. These structs are +// used to pass data between classes, hvl, and BFM's, hdl. Use of +// structs are more efficient and simpler to modify. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// + +// **************************************************************************** +// When changing the contents of this struct, be sure to update the to_struct +// and from_struct methods defined in the macros below that are used in +// the jtag_configuration class. +// + `define jtag_CONFIGURATION_STRUCT \ +typedef struct packed { \ + bit is_active;\ + bit [3:0] no_of_slaves;\ + bit has_coverage;\ + uvmf_active_passive_t active_passive; \ + uvmf_initiator_responder_t initiator_responder; \ + } jtag_configuration_s; + + `define jtag_CONFIGURATION_TO_STRUCT_FUNCTION \ + virtual function jtag_configuration_s to_struct();\ + jtag_configuration_struct = \ + {\ + this.is_active,\ + this.no_of_slaves,\ + this.has_coverage,\ + this.active_passive,\ + this.initiator_responder\ + };\ + return ( jtag_configuration_struct );\ + endfunction + + `define jtag_CONFIGURATION_FROM_STRUCT_FUNCTION \ + virtual function void from_struct(jtag_configuration_s jtag_configuration_struct);\ + {\ + this.is_active,\ + this.no_of_slaves,\ + this.has_coverage,\ + this.active_passive,\ + this.initiator_responder \ + } = jtag_configuration_struct;\ + endfunction + +// **************************************************************************** +// When changing the contents of this struct, be sure to update the to_monitor_struct +// and from_monitor_struct methods of the jtag_transaction class. +// + `define jtag_MONITOR_STRUCT typedef struct packed { \ + bit tck ; \ + bit tms ; \ + bit tdi ; \ + bit tdo ; \ + } jtag_monitor_s; + + `define jtag_TO_MONITOR_STRUCT_FUNCTION \ + virtual function jtag_monitor_s to_monitor_struct();\ + jtag_monitor_struct = \ + { \ + this.tck , \ + this.tms , \ + this.tdi , \ + this.tdo \ + };\ + return ( jtag_monitor_struct);\ + endfunction\ + + `define jtag_FROM_MONITOR_STRUCT_FUNCTION \ + virtual function void from_monitor_struct(jtag_monitor_s jtag_monitor_struct);\ + {\ + this.tck , \ + this.tms , \ + this.tdi , \ + this.tdo \ + } = jtag_monitor_struct;\ + endfunction + +// **************************************************************************** +// When changing the contents of this struct, be sure to update the to_initiator_struct +// and from_initiator_struct methods of the jtag_transaction class. +// Also update the comments in the driver BFM. +// + `define jtag_INITIATOR_STRUCT typedef struct packed { \ + bit tck ; \ + bit tms ; \ + bit tdi ; \ + bit tdo ; \ + } jtag_initiator_s; + + `define jtag_TO_INITIATOR_STRUCT_FUNCTION \ + virtual function jtag_initiator_s to_initiator_struct();\ + jtag_initiator_struct = \ + {\ + this.tck , \ + this.tms , \ + this.tdi , \ + this.tdo \ + };\ + return ( jtag_initiator_struct);\ + endfunction + + `define jtag_FROM_INITIATOR_STRUCT_FUNCTION \ + virtual function void from_initiator_struct(jtag_initiator_s jtag_initiator_struct);\ + {\ + this.tck , \ + this.tms , \ + this.tdi , \ + this.tdo \ + } = jtag_initiator_struct;\ + endfunction + +// **************************************************************************** +// When changing the contents of this struct, be sure to update the to_responder_struct +// and from_responder_struct methods of the jtag_transaction class. +// Also update the comments in the driver BFM. +// + `define jtag_RESPONDER_STRUCT typedef struct packed { \ + bit tck ; \ + bit tms ; \ + bit tdi ; \ + bit tdo ; \ + } jtag_responder_s; + + `define jtag_TO_RESPONDER_STRUCT_FUNCTION \ + virtual function jtag_responder_s to_responder_struct();\ + jtag_responder_struct = \ + {\ + this.tck , \ + this.tms , \ + this.tdi , \ + this.tdo \ + };\ + return ( jtag_responder_struct);\ + endfunction + + `define jtag_FROM_RESPONDER_STRUCT_FUNCTION \ + virtual function void from_responder_struct(jtag_responder_s jtag_responder_struct);\ + {\ + this.tck , \ + this.tms , \ + this.tdi , \ + this.tdo \ + } = jtag_responder_struct;\ + endfunction +// pragma uvmf custom additional begin +// pragma uvmf custom additional end diff --git a/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/verification_ip/interface_packages/jtag_pkg/src/jtag_monitor.svh b/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/verification_ip/interface_packages/jtag_pkg/src/jtag_monitor.svh new file mode 100644 index 00000000..91dddcf6 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/verification_ip/interface_packages/jtag_pkg/src/jtag_monitor.svh @@ -0,0 +1,87 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This class receives jtag transactions observed by the +// jtag monitor BFM and broadcasts them through the analysis port +// on the agent. It accesses the monitor BFM through the monitor +// task. This UVM component captures transactions +// for viewing in the waveform viewer if the +// enable_transaction_viewing flag is set in the configuration. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class jtag_monitor extends uvmf_monitor_base #( + .CONFIG_T(jtag_configuration ), + .BFM_BIND_T(virtual jtag_monitor_bfm ), + .TRANS_T(jtag_transaction )); + + `uvm_component_utils( jtag_monitor ) + +// Structure used to pass data from monitor BFM to monitor class in agent. +// Use to_monitor_struct function to pack transaction variables into structure. +// Use from_monitor_struct function to unpack transaction variables from structure. +`jtag_MONITOR_STRUCT + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + +// **************************************************************************** +// This function is the standard SystemVerilog constructor. +// + function new( string name = "", uvm_component parent = null ); + super.new( name, parent ); + endfunction + +// **************************************************************************** +// This function sends configuration object variables to the monitor BFM +// using the configuration struct. +// + virtual function void configure(input CONFIG_T cfg); + bfm.configure( cfg.to_struct() ); + + endfunction + +// **************************************************************************** +// This function places a handle to this class in the proxy variable in the +// monitor BFM. This allows the monitor BFM to call the notify_transaction +// function within this class. +// + virtual function void set_bfm_proxy_handle(); + bfm.proxy = this; endfunction + +// *************************************************************************** + virtual task run_phase(uvm_phase phase); + // Start monitor BFM thread and don't call super.run() in order to + // override the default monitor proxy 'pull' behavior with the more + // emulation-friendly BFM 'push' approach using the notify_transaction + // function below + bfm.start_monitoring(); + endtask + +// ************************************************************************** + +// This function is called by the monitor BFM. It receives data observed by the +// monitor BFM. Data is passed using the jtag_monitor_struct. + virtual function void notify_transaction(input jtag_monitor_s jtag_monitor_struct); + + + trans = new("trans"); + trans.from_monitor_struct(jtag_monitor_struct); + trans.start_time = time_stamp; + trans.end_time = $time; + time_stamp = trans.end_time; + + analyze(trans); + endfunction + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/verification_ip/interface_packages/jtag_pkg/src/jtag_monitor_bfm.sv b/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/verification_ip/interface_packages/jtag_pkg/src/jtag_monitor_bfm.sv new file mode 100644 index 00000000..a28ea375 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/verification_ip/interface_packages/jtag_pkg/src/jtag_monitor_bfm.sv @@ -0,0 +1,192 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This interface performs the jtag signal monitoring. +// It is accessed by the uvm jtag monitor through a virtual +// interface handle in the jtag configuration. It monitors the +// signals passed in through the port connection named bus of +// type jtag_if. +// +// Input signals from the jtag_if are assigned to an internal input +// signal with a _i suffix. The _i signal should be used for sampling. +// +// The input signal connections are as follows: +// bus.signal -> signal_i +// +// Interface functions and tasks used by UVM components: +// monitor(inout TRANS_T txn); +// This task receives the transaction, txn, from the +// UVM monitor and then populates variables in txn +// from values observed on bus activity. This task +// blocks until an operation on the jtag bus is complete. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +import uvmf_base_pkg_hdl::*; +import jtag_pkg_hdl::*; +`include "src/jtag_macros.svh" + + +interface jtag_monitor_bfm + ( jtag_if bus ); + // The pragma below and additional ones in-lined further down are for running this BFM on Veloce + // pragma attribute jtag_monitor_bfm partition_interface_xif + +`ifndef XRTL +// This code is to aid in debugging parameter mismatches between the BFM and its corresponding agent. +// Enable this debug by setting UVM_VERBOSITY to UVM_DEBUG +// Setting UVM_VERBOSITY to UVM_DEBUG causes all BFM's and all agents to display their parameter settings. +// All of the messages from this feature have a UVM messaging id value of "CFG" +// The transcript or run.log can be parsed to ensure BFM parameter settings match its corresponding agents parameter settings. +import uvm_pkg::*; +`include "uvm_macros.svh" +initial begin : bfm_vs_agent_parameter_debug + `uvm_info("CFG", + $psprintf("The BFM at '%m' has the following parameters: ", ), + UVM_DEBUG) +end +`endif + + + // Structure used to pass transaction data from monitor BFM to monitor class in agent. +`jtag_MONITOR_STRUCT + jtag_monitor_s jtag_monitor_struct; + + // Structure used to pass configuration data from monitor class to monitor BFM. + `jtag_CONFIGURATION_STRUCT + + + // Config value to determine if this is an initiator or a responder + uvmf_initiator_responder_t initiator_responder; + // Custom configuration variables. + // These are set using the configure function which is called during the UVM connect_phase + bit is_active ; + bit [3:0] no_of_slaves ; + bit has_coverage ; + + tri clock_i; + tri reset_i; + tri tck_i; + tri tms_i; + tri tdi_i; + tri tdo_i; + assign clock_i = bus.clock; + assign reset_i = bus.reset; + assign tck_i = bus.tck; + assign tms_i = bus.tms; + assign tdi_i = bus.tdi; + assign tdo_i = bus.tdo; + + // Proxy handle to UVM monitor + jtag_pkg::jtag_monitor proxy; + // pragma tbx oneway proxy.notify_transaction + + // pragma uvmf custom interface_item_additional begin + // pragma uvmf custom interface_item_additional end + + //****************************************************************** + task wait_for_reset();// pragma tbx xtf + @(posedge clock_i) ; + do_wait_for_reset(); + endtask + + // **************************************************************************** + task do_wait_for_reset(); + // pragma uvmf custom reset_condition begin + wait ( reset_i === 0 ) ; + @(posedge clock_i) ; + // pragma uvmf custom reset_condition end + endtask + + //****************************************************************** + + task wait_for_num_clocks(input int unsigned count); // pragma tbx xtf + @(posedge clock_i); + + repeat (count-1) @(posedge clock_i); + endtask + + //****************************************************************** + event go; + function void start_monitoring();// pragma tbx xtf + -> go; + endfunction + + // **************************************************************************** + initial begin + @go; + forever begin + @(posedge clock_i); + do_monitor( jtag_monitor_struct ); + + + proxy.notify_transaction( jtag_monitor_struct ); + + end + end + + //****************************************************************** + // The configure() function is used to pass agent configuration + // variables to the monitor BFM. It is called by the monitor within + // the agent at the beginning of the simulation. It may be called + // during the simulation if agent configuration variables are updated + // and the monitor BFM needs to be aware of the new configuration + // variables. + // + function void configure(jtag_configuration_s jtag_configuration_arg); // pragma tbx xtf + initiator_responder = jtag_configuration_arg.initiator_responder; + is_active = jtag_configuration_arg.is_active; + no_of_slaves = jtag_configuration_arg.no_of_slaves; + has_coverage = jtag_configuration_arg.has_coverage; + // pragma uvmf custom configure begin + // pragma uvmf custom configure end + endfunction + + + // **************************************************************************** + + task do_monitor(output jtag_monitor_s jtag_monitor_struct); + // + // Available struct members: + // // jtag_monitor_struct.tck + // // jtag_monitor_struct.tms + // // jtag_monitor_struct.tdi + // // jtag_monitor_struct.tdo + // // + // Reference code; + // How to wait for signal value + // while (control_signal === 1'b1) @(posedge clock_i); + // + // How to assign a struct member, named xyz, from a signal. + // All available input signals listed. + // jtag_monitor_struct.xyz = tck_i; // + // jtag_monitor_struct.xyz = tms_i; // + // jtag_monitor_struct.xyz = tdi_i; // + // jtag_monitor_struct.xyz = tdo_i; // + // pragma uvmf custom do_monitor begin + // UVMF_CHANGE_ME : Implement protocol monitoring. The commented reference code + // below are examples of how to capture signal values and assign them to + // structure members. All available input signals are listed. The 'while' + // code example shows how to wait for a synchronous flow control signal. This + // task should return when a complete transfer has been observed. Once this task is + // exited with captured values, it is then called again to wait for and observe + // the next transfer. One clock cycle is consumed between calls to do_monitor. + @(posedge clock_i); + @(posedge clock_i); + @(posedge clock_i); + @(posedge clock_i); + // pragma uvmf custom do_monitor end + endtask + + +endinterface + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/verification_ip/interface_packages/jtag_pkg/src/jtag_random_sequence.svh b/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/verification_ip/interface_packages/jtag_pkg/src/jtag_random_sequence.svh new file mode 100644 index 00000000..51a75b4b --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/verification_ip/interface_packages/jtag_pkg/src/jtag_random_sequence.svh @@ -0,0 +1,53 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: +// This sequences randomizes the jtag transaction and sends it +// to the UVM driver. +// +// This sequence constructs and randomizes a jtag_transaction. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class jtag_random_sequence + extends jtag_sequence_base ; + + `uvm_object_utils( jtag_random_sequence ) + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + //***************************************************************** + function new(string name = ""); + super.new(name); + endfunction: new + + // **************************************************************************** + // TASK : body() + // This task is automatically executed when this sequence is started using the + // start(sequencerHandle) task. + // + task body(); + + // Construct the transaction + req=jtag_transaction::type_id::create("req"); + start_item(req); + // Randomize the transaction + if(!req.randomize()) `uvm_fatal("SEQ", "jtag_random_sequence::body()-jtag_transaction randomization failed") + // Send the transaction to the jtag_driver_bfm via the sequencer and jtag_driver. + finish_item(req); + `uvm_info("SEQ", {"Response:",req.convert2string()},UVM_MEDIUM) + + endtask + +endclass: jtag_random_sequence + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/verification_ip/interface_packages/jtag_pkg/src/jtag_responder_sequence.svh b/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/verification_ip/interface_packages/jtag_pkg/src/jtag_responder_sequence.svh new file mode 100644 index 00000000..9722fa34 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/verification_ip/interface_packages/jtag_pkg/src/jtag_responder_sequence.svh @@ -0,0 +1,49 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This class can be used to provide stimulus when an interface +// has been configured to run in a responder mode. It +// will never finish by default, always going back to the driver +// and driver BFM for the next transaction with which to respond. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class jtag_responder_sequence + extends jtag_sequence_base ; + + `uvm_object_utils( jtag_responder_sequence ) + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + function new(string name = "jtag_responder_sequence"); + super.new(name); + endfunction + + task body(); + req=jtag_transaction::type_id::create("req"); + forever begin + start_item(req); + finish_item(req); + // pragma uvmf custom body begin + // UVMF_CHANGE_ME : Do something here with the resulting req item. The + // finish_item() call above will block until the req transaction is ready + // to be handled by the responder sequence. + // If this was an item that required a response, the expectation is + // that the response should be populated within this transaction now. + `uvm_info("SEQ",$sformatf("Processed txn: %s",req.convert2string()),UVM_HIGH) + // pragma uvmf custom body end + end + endtask + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/verification_ip/interface_packages/jtag_pkg/src/jtag_sequence_base.svh b/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/verification_ip/interface_packages/jtag_pkg/src/jtag_sequence_base.svh new file mode 100644 index 00000000..452d2408 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/verification_ip/interface_packages/jtag_pkg/src/jtag_sequence_base.svh @@ -0,0 +1,96 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: +// This file contains the class used as the base class for all sequences +// for this interface. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class jtag_sequence_base extends uvmf_sequence_base #( + .REQ(jtag_transaction ), + .RSP(jtag_transaction )); + + `uvm_object_utils( jtag_sequence_base ) + + // variables + typedef jtag_transaction jtag_transaction_req_t; + jtag_transaction_req_t req; + typedef jtag_transaction jtag_transaction_rsp_t; + jtag_transaction_rsp_t rsp; + + // Event for identifying when a response was received from the sequencer + event new_rsp; + + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + // **************************************************************************** + // TASK : get_responses() + // This task recursively gets sequence item responses from the sequencer. + // + virtual task get_responses(); + fork + begin + // Block until new rsp available + get_response(rsp); + // New rsp received. Indicate to sequence using event. + ->new_rsp; + // Display the received response transaction + `uvm_info("SEQ", {"New response transaction:",rsp.convert2string()}, UVM_MEDIUM) + end + join_none + endtask + + // **************************************************************************** + // TASK : pre_body() + // This task is called automatically when start is called with call_pre_post set to 1 (default). + // By calling get_responses() within pre_body() any derived sequences are automatically + // processing response transactions. Only un-comment this call to get_responses() if you + // have configured the interface driver to utilize the response transaction path by setting + // the configuration variable "return_transaction_response" to 1. Otherwise it is possible + // to impact runtime performance and memory utilization. + // + virtual task pre_body(); + // pragma uvmf custom pre_body begin +// get_responses(); + // pragma uvmf custom pre_body end + endtask + + // **************************************************************************** + // TASK : body() + // This task is called automatically when start is called. This sequence sends + // a req sequence item to the sequencer identified as an argument in the call + // to start. + // + virtual task body(); + // pragma uvmf custom body begin + start_item(req); + finish_item(req); + // pragma uvmf custom body end + endtask + + // **************************************************************************** + // FUNCTION : new() + // This function is the standard SystemVerilog constructor. + // + function new( string name =""); + super.new( name ); + // pragma uvmf custom new begin + req = jtag_transaction_req_t::type_id::create("req"); + rsp = jtag_transaction_rsp_t::type_id::create("rsp"); + // pragma uvmf custom new end + endfunction + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/verification_ip/interface_packages/jtag_pkg/src/jtag_transaction.svh b/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/verification_ip/interface_packages/jtag_pkg/src/jtag_transaction.svh new file mode 100644 index 00000000..7e9d0a74 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/verification_ip/interface_packages/jtag_pkg/src/jtag_transaction.svh @@ -0,0 +1,194 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This class defines the variables required for an jtag +// transaction. Class variables to be displayed in waveform transaction +// viewing are added to the transaction viewing stream in the add_to_wave +// function. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class jtag_transaction extends uvmf_transaction_base; + + `uvm_object_utils( jtag_transaction ) + + rand bit tck ; + rand bit tms ; + rand bit tdi ; + bit tdo ; + + //Constraints for the transaction variables: + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + //******************************************************************* + //******************************************************************* + // Macros that define structs and associated functions are + // located in jtag_macros.svh + + //******************************************************************* + // Monitor macro used by jtag_monitor and jtag_monitor_bfm + // This struct is defined in jtag_macros.svh + `jtag_MONITOR_STRUCT + jtag_monitor_s jtag_monitor_struct; + //******************************************************************* + // FUNCTION: to_monitor_struct() + // This function packs transaction variables into a jtag_monitor_s + // structure. The function returns the handle to the jtag_monitor_struct. + // This function is defined in jtag_macros.svh + `jtag_TO_MONITOR_STRUCT_FUNCTION + //******************************************************************* + // FUNCTION: from_monitor_struct() + // This function unpacks the struct provided as an argument into transaction + // variables of this class. + // This function is defined in jtag_macros.svh + `jtag_FROM_MONITOR_STRUCT_FUNCTION + + //******************************************************************* + // Initiator macro used by jtag_driver and jtag_driver_bfm + // to communicate initiator driven data to jtag_driver_bfm. + // This struct is defined in jtag_macros.svh + `jtag_INITIATOR_STRUCT + jtag_initiator_s jtag_initiator_struct; + //******************************************************************* + // FUNCTION: to_initiator_struct() + // This function packs transaction variables into a jtag_initiator_s + // structure. The function returns the handle to the jtag_initiator_struct. + // This function is defined in jtag_macros.svh + `jtag_TO_INITIATOR_STRUCT_FUNCTION + //******************************************************************* + // FUNCTION: from_initiator_struct() + // This function unpacks the struct provided as an argument into transaction + // variables of this class. + // This function is defined in jtag_macros.svh + `jtag_FROM_INITIATOR_STRUCT_FUNCTION + + //******************************************************************* + // Responder macro used by jtag_driver and jtag_driver_bfm + // to communicate Responder driven data to jtag_driver_bfm. + // This struct is defined in jtag_macros.svh + `jtag_RESPONDER_STRUCT + jtag_responder_s jtag_responder_struct; + //******************************************************************* + // FUNCTION: to_responder_struct() + // This function packs transaction variables into a jtag_responder_s + // structure. The function returns the handle to the jtag_responder_struct. + // This function is defined in jtag_macros.svh + `jtag_TO_RESPONDER_STRUCT_FUNCTION + //******************************************************************* + // FUNCTION: from_responder_struct() + // This function unpacks the struct provided as an argument into transaction + // variables of this class. + // This function is defined in jtag_macros.svh + `jtag_FROM_RESPONDER_STRUCT_FUNCTION + // **************************************************************************** + // FUNCTION : new() + // This function is the standard SystemVerilog constructor. + // + function new( string name = "" ); + super.new( name ); + endfunction + + // **************************************************************************** + // FUNCTION: convert2string() + // This function converts all variables in this class to a single string for + // logfile reporting. + // + virtual function string convert2string(); + // pragma uvmf custom convert2string begin + // UVMF_CHANGE_ME : Customize format if desired. + return $sformatf("tck:0x%x tms:0x%x tdi:0x%x tdo:0x%x ",tck,tms,tdi,tdo); + // pragma uvmf custom convert2string end + endfunction + + //******************************************************************* + // FUNCTION: do_print() + // This function is automatically called when the .print() function + // is called on this class. + // + virtual function void do_print(uvm_printer printer); + // pragma uvmf custom do_print begin + // UVMF_CHANGE_ME : Current contents of do_print allows for the use of UVM 1.1d, 1.2 or P1800.2. + // Update based on your own printing preference according to your preferred UVM version + $display(convert2string()); + // pragma uvmf custom do_print end + endfunction + + //******************************************************************* + // FUNCTION: do_compare() + // This function is automatically called when the .compare() function + // is called on this class. + // + virtual function bit do_compare (uvm_object rhs, uvm_comparer comparer); + jtag_transaction RHS; + if (!$cast(RHS,rhs)) return 0; + // pragma uvmf custom do_compare begin + // UVMF_CHANGE_ME : Eliminate comparison of variables not to be used for compare + return (super.do_compare(rhs,comparer) + &&(this.tck == RHS.tck) + &&(this.tms == RHS.tms) + &&(this.tdi == RHS.tdi) + &&(this.tdo == RHS.tdo) + ); + // pragma uvmf custom do_compare end + endfunction + + //******************************************************************* + // FUNCTION: do_copy() + // This function is automatically called when the .copy() function + // is called on this class. + // + virtual function void do_copy (uvm_object rhs); + jtag_transaction RHS; + assert($cast(RHS,rhs)); + // pragma uvmf custom do_copy begin + super.do_copy(rhs); + this.tck = RHS.tck; + this.tms = RHS.tms; + this.tdi = RHS.tdi; + this.tdo = RHS.tdo; + // pragma uvmf custom do_copy end + endfunction + + // **************************************************************************** + // FUNCTION: add_to_wave() + // This function is used to display variables in this class in the waveform + // viewer. The start_time and end_time variables must be set before this + // function is called. If the start_time and end_time variables are not set + // the transaction will be hidden at 0ns on the waveform display. + // + virtual function void add_to_wave(int transaction_viewing_stream_h); + `ifdef QUESTA + if (transaction_view_h == 0) begin + transaction_view_h = $begin_transaction(transaction_viewing_stream_h,"jtag_transaction",start_time); + end + super.add_to_wave(transaction_view_h); + // pragma uvmf custom add_to_wave begin + // UVMF_CHANGE_ME : Color can be applied to transaction entries based on content, example below + // case() + // 1 : $add_color(transaction_view_h,"red"); + // default : $add_color(transaction_view_h,"grey"); + // endcase + // UVMF_CHANGE_ME : Eliminate transaction variables not wanted in transaction viewing in the waveform viewer + $add_attribute(transaction_view_h,tck,"tck"); + $add_attribute(transaction_view_h,tms,"tms"); + $add_attribute(transaction_view_h,tdi,"tdi"); + $add_attribute(transaction_view_h,tdo,"tdo"); + // pragma uvmf custom add_to_wave end + $end_transaction(transaction_view_h,end_time); + $free_transaction(transaction_view_h); + `endif // QUESTA + endfunction + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/verification_ip/interface_packages/jtag_pkg/src/jtag_transaction_coverage.svh b/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/verification_ip/interface_packages/jtag_pkg/src/jtag_transaction_coverage.svh new file mode 100644 index 00000000..f7b31f77 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/verification_ip/interface_packages/jtag_pkg/src/jtag_transaction_coverage.svh @@ -0,0 +1,73 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This class records jtag transaction information using +// a covergroup named jtag_transaction_cg. An instance of this +// coverage component is instantiated in the uvmf_parameterized_agent +// if the has_coverage flag is set. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class jtag_transaction_coverage extends uvm_subscriber #(.T(jtag_transaction )); + + `uvm_component_utils( jtag_transaction_coverage ) + + T coverage_trans; + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + // **************************************************************************** + covergroup jtag_transaction_cg; + // pragma uvmf custom covergroup begin + // UVMF_CHANGE_ME : Add coverage bins, crosses, exclusions, etc. according to coverage needs. + option.auto_bin_max=1024; + option.per_instance=1; + tck: coverpoint coverage_trans.tck; + tms: coverpoint coverage_trans.tms; + tdi: coverpoint coverage_trans.tdi; + tdo: coverpoint coverage_trans.tdo; + // pragma uvmf custom covergroup end + endgroup + + // **************************************************************************** + // FUNCTION : new() + // This function is the standard SystemVerilog constructor. + // + function new(string name="", uvm_component parent=null); + super.new(name,parent); + jtag_transaction_cg=new; + `uvm_warning("COVERAGE_MODEL_REVIEW", "A covergroup has been constructed which may need review because of either generation or re-generation with merging. Please note that transaction variables added as a result of re-generation and merging are not automatically added to the covergroup. Remove this warning after the covergroup has been reviewed.") + endfunction + + // **************************************************************************** + // FUNCTION : build_phase() + // This function is the standard UVM build_phase. + // + function void build_phase(uvm_phase phase); + jtag_transaction_cg.set_inst_name($sformatf("jtag_transaction_cg_%s",get_full_name())); + endfunction + + // **************************************************************************** + // FUNCTION: write (T t) + // This function is automatically executed when a transaction arrives on the + // analysis_export. It copies values from the variables in the transaction + // to local variables used to collect functional coverage. + // + virtual function void write (T t); + `uvm_info("COV","Received transaction",UVM_HIGH); + coverage_trans = t; + jtag_transaction_cg.sample(); + endfunction + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/verification_ip/interface_packages/jtag_pkg/src/jtag_typedefs.svh b/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/verification_ip/interface_packages/jtag_pkg/src/jtag_typedefs.svh new file mode 100644 index 00000000..43d85640 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/verification_ip/interface_packages/jtag_pkg/src/jtag_typedefs.svh @@ -0,0 +1,20 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: +// This file contains defines and typedefs to be compiled for use in +// the simulation running on the host server when using Veloce. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// + + +// pragma uvmf custom additional begin +// pragma uvmf custom additional end + diff --git a/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/verification_ip/interface_packages/jtag_pkg/src/jtag_typedefs_hdl.svh b/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/verification_ip/interface_packages/jtag_pkg/src/jtag_typedefs_hdl.svh new file mode 100644 index 00000000..74738c8c --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/verification_ip/interface_packages/jtag_pkg/src/jtag_typedefs_hdl.svh @@ -0,0 +1,21 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: +// This file contains defines and typedefs to be compiled for use in +// the simulation running on the emulator when using Veloce. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// + + + +// pragma uvmf custom additional begin +// pragma uvmf custom additional end + diff --git a/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/verification_ip/interface_packages/jtag_pkg/yaml/jtag_interface.yaml b/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/verification_ip/interface_packages/jtag_pkg/yaml/jtag_interface.yaml new file mode 100644 index 00000000..488d4860 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/verification_ip/interface_packages/jtag_pkg/yaml/jtag_interface.yaml @@ -0,0 +1,74 @@ +uvmf: + interfaces: + jtag: + clock: clock + config_constraints: [] + config_vars: + - comment: '' + isrand: 'False' + name: is_active + type: bit + value: '1' + - comment: '' + isrand: 'False' + name: no_of_slaves + type: bit [3:0] + value: '0' + - comment: '' + isrand: 'False' + name: has_coverage + type: bit + value: '1' + existing_library_component: 'True' + gen_inbound_streaming_driver: 'False' + hdl_pkg_parameters: [] + hdl_typedefs: [] + hvl_pkg_parameters: [] + hvl_typedefs: [] + parameters: [] + ports: + - dir: output + name: tck + reset_value: 1'b0 + width: '1' + - dir: output + name: tms + reset_value: 1'b0 + width: '1' + - dir: output + name: tdi + reset_value: 1'b0 + width: '1' + - dir: input + name: tdo + reset_value: 1'b0 + width: '1' + reset: reset + reset_assertion_level: 'True' + transaction_constraints: [] + transaction_vars: + - comment: '' + iscompare: 'True' + isrand: 'True' + name: tck + type: bit + unpacked_dimension: '' + - comment: '' + iscompare: 'True' + isrand: 'True' + name: tms + type: bit + unpacked_dimension: '' + - comment: '' + iscompare: 'True' + isrand: 'True' + name: tdi + type: bit + unpacked_dimension: '' + - comment: '' + iscompare: 'True' + isrand: 'False' + name: tdo + type: bit + unpacked_dimension: '' + use_dpi_link: 'False' diff --git a/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/jtag_bench.yaml b/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/jtag_bench.yaml new file mode 100644 index 00000000..a4821151 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/jtag_bench.yaml @@ -0,0 +1,10 @@ +uvmf: + benches: + "jtag" : + top_env: "jtag" + reset_duration: "100ns" + active_passive: + - bfm_name: "jtag_in" + value: "ACTIVE" + - bfm_name: "jtag_out" + value: "ACTIVE" diff --git a/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/jtag_env.yaml b/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/jtag_env.yaml new file mode 100644 index 00000000..add45700 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/jtag_env.yaml @@ -0,0 +1,52 @@ +uvmf: + environments: + "jtag" : + agents : + - name: "jtag_in" + type: "jtag" + initiator_responder: "INITIATOR" + - name: "jtag_out" + type: "jtag" + initiator_responder: "RESPONDER" + analysis_components : + - name: "jtag_pred" + type: "jtag_predictor" + - name: "jtag_cov" + type: "jtag_coverage" + scoreboards : + - name: "jtag_sb" + sb_type: "uvmf_in_order_race_scoreboard" + trans_type: "jtag_transaction" + analysis_ports : + - name: "jtag_in_ap" + trans_type: "jtag_transaction" + connected_to: "jtag_in.monitored_ap" + - name: "jtag_out_ap" + trans_type: "jtag_transaction" + connected_to: "jtag_out.monitored_ap" + tlm_connections : + - driver: "jtag_in.monitored_ap" + receiver: "jtag_pred.jtag_in_ae" + - driver: "jtag_pred.jtag_sb_ap" + receiver: "jtag_sb.expected_analysis_export" + - driver: "jtag_out.monitored_ap" + receiver: "jtag_sb.actual_analysis_export" + - driver: "jtag_in.monitored_ap" + receiver: "jtag_cov.jtag_cov_ae" + + util_components: + "jtag_predictor": + type: "predictor" + analysis_exports: + - name: "jtag_in_ae" + type: "jtag_transaction" + analysis_ports: + - name: "jtag_sb_ap" + type: "jtag_transaction" + + "jtag_coverage": + type: "coverage" + analysis_exports: + - name: "jtag_cov_ae" + type: "jtag_transaction" + diff --git a/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/jtag_interface_yaml.yaml b/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/jtag_interface_yaml.yaml new file mode 100755 index 00000000..ebb9cf71 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/jtag_interface_yaml.yaml @@ -0,0 +1,55 @@ +uvmf: + interfaces: + "jtag": + clock: "clock" + reset: "reset" + reset_assertion_level: "True" + veloce_ready: "True" + ports: + - name: "tck" + width: "1" + dir: "output" + reset_value: "1'b0" + - name: "tms" + width: "1" + dir: "output" + reset_value: "1'b0" + - name: "tdi" + width: "1" + dir: "output" + reset_value: "1'b0" + - name: "tdo" + width: "1" + dir: "input" + reset_value: "1'b0" + transaction_vars: + - name: "tck" + type: "bit" + isrand: "True" + iscompare: "True" + - name: "tms" + type: "bit" + isrand: "True" + iscompare: "True" + - name: "tdi" + type: "bit" + isrand: "True" + iscompare: "True" + - name: "tdo" + type: "bit" + isrand: "False" + iscompare: "True" + + config_vars: + - name: "is_active" + type: "bit" + isrand: "False" + value: "1" + - name: "no_of_slaves" + type: "bit [3:0]" + value: "0" + - name: "has_coverage" + type: "bit" + value: "1" + + diff --git a/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/yaml2uvmf.py b/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/yaml2uvmf.py new file mode 100755 index 00000000..286bec9b --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/yaml2uvmf.py @@ -0,0 +1,1659 @@ +#! /usr/bin/env python + +############################################################################## +## Copyright 2017 Mentor Graphics +## All Rights Reserved Worldwide +## +## Licensed under the Apache License, Version 2.0 (the "License"); you may +## not use this file except in compliance with the License. You may obtain +## a copy of the License at +## +## http://www.apache.org/license/LICENSE-2.0 +## +## Unless required by applicable law or agreed to in +## writing, software distributed under the License is +## distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +## CONDITIONS OF ANY KIND, either express or implied. See +## the License for the specific language governing +## permissions and limitations under the License. +## +############################################################################## +## +## Mentor Graphics Inc +## +############################################################################## +## +## Created by : Jon Craft & Bob Oden +## Creation date : May 25 2017 +## +############################################################################## +## +## This script utilizes the Python-based generator API to take data structures +## defined in YAML and convert them into UVMF code for interfaces, environments +## and benches. +## +## Run 'yaml2uvmf.py --help' for more information +## +############################################################################## + +import sys +import os +import time +import re +import inspect +import copy +import pprint +from optparse import OptionParser, SUPPRESS_HELP +from fnmatch import fnmatch +import shutil + +# Determine addition to sys.path automatically based on script location +# This means user does not have to explicitly set PYTHONPATH in order for this +# script to work properly. + +sys.path.insert(0,os.path.dirname(os.path.dirname(os.path.realpath(__file__)))+"/templates/python"); +# Only need python2 packages if using python2 +if sys.version_info[0] < 3: + sys.path.insert(0,os.path.dirname(os.path.dirname(os.path.realpath(__file__)))+"/templates/python/python2"); + +from uvmf_yaml import * +import uvmf_gen +from uvmf_gen import (UVMFCommandLineParser,PassThroughOptionParser,UserError,InterfaceClass,EnvironmentClass,BenchClass) +from voluptuous import Invalid, MultipleInvalid +from voluptuous.humanize import humanize_error +from uvmf_version import version + +try: + import yaml +except ImportError: + print("ERROR : yaml package not found. See templates.README for more information") + print("Python version info:\n{}".format(sys.version)) + sys.exit(1) + +def merge_summary(merge,verbose=False): + block_count = sum(len(l) for l in merge.found_blocks.values()) + new_block_count = sum(len(l) for l in merge.new_blocks.values()) + if verbose: + print("============================== Merge Details ==============================") + print(" Parsed {0} original files finding a total of {1} \"pragma uvmf custom\" blocks".format(len(merge.rd), block_count)) + if verbose and (len(merge.found_blocks)>0): + for f in merge.found_blocks: + print(" File: {0}".format(f)) + for l in merge.found_blocks[f]: + print(" \"{0}\"".format(l['name'])) + print(" Copied {0} new files from generated source".format(len(merge.copied_files))) + if verbose and (len(merge.copied_files)>0): + print(" Files found in new output but not in merged source. List of copied file destinations:") + for f in merge.copied_files: + print(" {0}".format(f)) + print(" Found {0} new \"pragma uvmf custom\" blocks in generated source".format(new_block_count)) + if verbose and (len(merge.new_blocks)>0): + print(" Blocks found in new output but not in merged source. List of new blocks and their associated source file locations:") + for f in merge.new_blocks: + print(" File: {0}".format(f)) + for l in merge.new_blocks[f]: + print(" \"{0}\"".format(l)) + if verbose: + print("===========================================================================") + +class ConfigFileReader: + """Reads in a .f file and builds up array of files to parse""" + def __init__(self,fname,relative_to_file=False): + self.fname = fname + self.files = [] + try: + self.fh = open(fname,'r') + except IOError: + raise UserError("Unable to open -f/-F file "+fname) + self.lines = self.fh.readlines() + for line in self.lines: + # Strip comments + line = re.sub(r"(.*?)#.*",r"\1",line.rstrip()).strip() + # Elaborate environment variables + line = os.path.expandvars(line) + if (line != ""): + if relative_to_file: + line = os.path.normpath(os.path.dirname(os.path.abspath(fname))+os.path.sep+line) + self.files.append(line) + self.fh.close() + +class DataClass: + def __init__(self,parser,debug=False): + self.data = {'interfaces':{},'environments':{},'benches':{},'util_components':{},'qvip_environments':{},'qvip_library':{},'global':{}} + self.parser = parser + self.debug = debug + self.validators = {} + self.used_ac_items = [] + + def parseFile(self,fname): + try: + fs = open(fname) + except IOError: + raise UserError("Unable to open config file "+fname) + d = yaml.safe_load(fs) + fs.close() + try: + if 'uvmf' not in d.keys(): + raise UserError("Contents of "+fname+" not valid UVMF info") + except: + raise UserError("Contents of "+fname+" not valid UVMF info") + for k in d['uvmf'].keys(): + if k not in self.data.keys(): + raise UserError("Top-level element \""+k+"\" in "+fname+" is not valid. Allowed entries:\n "+str(self.data.keys())) + for elem in self.data.keys(): + try: self.data[elem].update(d['uvmf'][elem]) + except KeyError: + pass + + ## Validate various data structures against the associated schema + def validate(self): + self.validators = { + 'interfaces':InterfaceValidator(), + 'util_components':ComponentValidator(), + 'qvip_environments':QVIPEnvValidator(), + 'environments':EnvironmentValidator(), + 'benches':BenchValidator(), + 'global':GlobalValidator(), +# 'qvip_library':QVIPLibValidator(), ## Don't validate QVIP library info, for debug purposes only + } + ## Check for any incorrect top-level keys + for t in self.validators.keys(): + for c in self.data[t].keys(): + if (t=='global'): + v = self.data[t] + else: + v = self.data[t][c] + try: + self.validators[t].schema(v) + except MultipleInvalid as e: + resp = humanize_error(v,e).split('\n') + raise UserError("While validating "+t+" YAML '"+c+"':\n"+pprint.pformat(resp,indent=2)) + + def calculateRelativeVipLocation(self,compClass): + ## Determine relative path to "loc" if CWD is bench's "sim" directory + simpath = compClass.bench_location+"/bench_name/sim" + ret = os.path.relpath(compClass.vip_location,simpath) + ## Even on Windows, these need to be forward slashes because they'll be normalized within Tcl. Replace any backslashes with forward ones + ## Can't use pathlib here due to Python2 back-compat, just do a global search/replace + return ret.replace('\\','/') + + def calculateRelativeVipToCwd(self,compClass): + ret = os.path.relpath(os.getcwd(),compClass.vip_location) + return ret.replace('\\','/') + + def calculateRelativeBenchToCwd(self,compClass): + ret = os.path.relpath(os.getcwd(),compClass.bench_location) + return ret.replace('\\','/') + + def calculateRelativeInterfaceToCwd(self,compClass): + ret = os.path.relpath(os.getcwd(),compClass.vip_location+os.path.sep+compClass.interface_location) + return ret.replace('\\','/') + + def calculateRelativeEnvironmentToCwd(self,compClass): + ret = os.path.relpath(os.getcwd(),compClass.vip_location+os.path.sep+compClass.environment_location) + return ret.replace('\\','/') + + def setupGlobalVars(self,compClass): + try: + compClass.header = self.data['global']['header'] + except KeyError: + compClass.header = None + pass + try: + compClass.flat_output = (self.data['global']['flat_output'] == "True") + except KeyError: + compClass.flat_output = False + pass + try: + compClass.vip_location = self.data['global']['vip_location'] + except KeyError: + pass + try: + compClass.interface_location = self.data['global']['interface_location'] + except KeyError: + pass + try: + compClass.environment_location = self.data['global']['environment_location'] + except KeyError: + pass + try: + compClass.bench_location = self.data['global']['bench_location'] + except KeyError: + pass + compClass.relative_vip_from_sim = self.calculateRelativeVipLocation(compClass) + compClass.relative_vip_from_cwd = self.calculateRelativeVipToCwd(compClass) + compClass.relative_bench_from_cwd = self.calculateRelativeBenchToCwd(compClass) + compClass.relative_interface_from_cwd = self.calculateRelativeInterfaceToCwd(compClass) + compClass.relative_environment_from_cwd = self.calculateRelativeEnvironmentToCwd(compClass) + return compClass + + ## Generate everything from the data structures + def buildElements(self,genarray,verify=True,build_existing=False,archive_yaml=True): + count = 0 + self.interfaceDict = {} + try: + arrlen = len(genarray) + except TypeError: + arrlen = 0 + pass + for interface_name in self.data['interfaces']: + if ((arrlen>0) and (interface_name in genarray)) or (arrlen==0): + self.interfaceDict[interface_name] = self.generateInterface(interface_name,build_existing,archive_yaml) + count = count + 1 + self.environmentDict = {} + for environment_name in self.data['environments']: + if ((arrlen>0) and (environment_name in genarray)) or (arrlen==0): + self.environmentDict[environment_name] = self.generateEnvironment(environment_name,build_existing,archive_yaml) + count = count + 1 + self.benchDict = {} + for bench_name in self.data['benches']: + if ((arrlen>0) and (bench_name in genarray)) or (arrlen==0): + self.benchDict[bench_name] = self.generateBench(bench_name,build_existing,archive_yaml) + count = count + 1 + ## Check to see if any utility components were defined but never instantiated, flag that as a warning + for util_comp in self.data['util_components']: + if util_comp not in self.used_ac_items: + print(" WARNING : Utility component \""+util_comp+"\" was defined but never used. It will not be generated.") + ## Verify that something was produced (possible that YAML input was empty or genarray had no matches) + if count==0 and verify: + raise UserError("No output was produced!") + + + def recursion_print(self,recurse_list): + r = "" + for i,s in enumerate(recurse_list): + r = r + s + if i != len(recurse_list)-1: + r = r + " -> " + return r + + ## This method recursively searches all environments from the specified level down for QVIP subenvs, compiling + ## a list of underlying QVIP agents, their subenvironment parent names, their import list and active/passive info + def getQVIPAgents(self,topEnv,recurse_list=[]): + struct = self.data['environments'] + # Check for recursion, error out if detected + if topEnv in recurse_list: + raise UserError("Sub-environment recursion detected within environment \""+topEnv+"\". Tree: \""+self.recursion_print(recurse_list+[topEnv])+"\"") + try: + env = struct[topEnv] + except KeyError: + raise UserError("Unable to find environment \""+topEnv+"\" in defined environments (available list is "+str(struct.keys())) + agent_list = [] + import_list = [] + ## First look for any local QVIP subenvironments and extract those agent names + try: + qvip_subenv_list = env['qvip_subenvs'] + except KeyError: + qvip_subenv_list = [] + pass + for s in qvip_subenv_list: + try: + d = self.data['qvip_environments'][s['type']] + except KeyError: + raise UserError("Definition for QVIP subenvironment \""+s['name']+"\" of type \""+s['type']+"\" is not found") + local_agents = d['agents'] + for a in local_agents: + try: + active_passive = a['active_passive'] + except KeyError: + active_passive = None + agent_list = agent_list + [{ 'name': a['name'], 'parent': s['type'], 'active_passive': active_passive }] + try: + import_list = import_list + a['imports'] + except KeyError: pass + ## Next drill down and call getQVIPAgents on any non-QVIP subenvironments + try: + subenv_list = env['subenvs'] + except KeyError: + subenv_list = [] + pass + for s in subenv_list: + qstruct = self.getQVIPAgents(s['type'],recurse_list+[topEnv]) + agent_list = agent_list + qstruct['alist']; + import_list = import_list + qstruct['ilist']; + ## Finally, uniquify the import list + ilist = import_list + import_list = [] + for i in ilist: + if i not in import_list: + import_list = import_list + [ i ] + return {'alist':agent_list, 'ilist':import_list} + + ## This method will return a list of environments at the provided environment level or recursively. + def getEnvironments(self,topEnv,recursive=True): + struct = self.data['environments'] + try: + env = struct[topEnv] + except KeyError: + raise UserError("Unable to find environment \""+topEnv+"\" in defined environments (available list is "+str(struct.keys())) + envs = [] + try: + envs = env['subenvs'] + except KeyError: pass + if not recursive: + return envs + for subenv in envs: + envs = envs + self.getEnvironments(subenv['type'],recursive=True) + return envs + + ## This method takes a dotted component hierarchy string and returns + ## the same but with underscores. For use in cases where a unique identifier + ## is required. Removes final entry in component hierarchy too. + def getUniqueID(self,val): + l = val.split(".") + return "uvm_test_top."+'.'.join(l[:-1])+"." + + ## This method returns an ordered list of information on ALL BFMs from a given top-level environment, down. + ## The list entries all have the following structure: + ## - BFM Name ('bfm_name') + ## - BFM Type ('bfm_type') + ## - BFM Parent Type ('parent_type') + ## - Environment Path ('env_path') + ## - VIP Library Env Variable Name ('lib_env_var_name') (only valid for non-QVIP) + ## - QVIP/Non-QVIP flag ('is_qvip') + ## - Initiator/Responder info ('initiator_responder') + ## - VeloceReady flag ('veloce_ready') + def getAllAgents(self,env_type,env_inst,isQVIP,envPath): + alist = [] + if (isQVIP==1): + # This environment we've been given is a QVIP environment which is stored + # in a different structure + struct = self.data['qvip_environments'] + try: + env = struct[env_type] + except KeyError: + raise UserError("Unable to find QVIP environment \""+env_type+"\" in defined QVIP environments (available list is "+str(struct.keys())+")") + for a in env['agents']: + ## All we have is the name of each BFM. + alist = alist + [{ 'bfm_name': a['name'], + 'bfm_type': 'unknown', + 'parent_type': env_type, + 'env_path': envPath+"."+a['name'], + 'lib_env_var_name':'unknown', + 'is_qvip': 1 , + 'initiator_responder':'UNKNOWN', + 'veloce_ready':False }] + ## No nesting with QVIP environments so safe to just return here + return alist + else: + struct = self.data['environments'] + try: + env = struct[env_type] + except KeyError: + raise UserError("Unable to find environment \""+env_type+"\" in defined environments (available list is "+str(struct.keys())) + ## We're looking at a non-QVIP environment. This can have underlying QVIP and/or non-QVIP sub-environments as well as local agents. + ## Look for underlying QVIP subenvs first, then non-QVIP sub-envs, then local agents. + try: + qvip_subenvs = env['qvip_subenvs'] + for e in qvip_subenvs: + alist = alist + self.getAllAgents(e['type'],e['name'],1,envPath+"."+e['name']) + except KeyError: pass + try: + subenvs = env['subenvs'] + for e in subenvs: + alist = alist + self.getAllAgents(e['type'],e['name'],0,envPath+"."+e['name']) + except KeyError: pass + try: + agents = env['agents'] + for a in agents: + try: + env_var_name = self.data['interfaces'][a['type']]['vip_lib_env_variable'] + except KeyError: + env_var_name = 'UVMF_VIP_LIBRARY_HOME' + pass + try: + init_resp = a['initiator_responder'] + except KeyError: + init_resp = 'INITIATOR' + pass + try: + veloce_ready = (self.data['interfaces'][a['type']]['veloce_ready']=="True") + except KeyError: + veloce_ready = True + pass + infact_ready = ('infact_ready' in self.data['interfaces'][a['type']].keys() and self.data['interfaces'][a['type']]['infact_ready']) + + alist = alist + [{ 'bfm_name': a['name'], + 'bfm_type': a['type'], + 'parent_type': env_type, + 'env_path': envPath+"."+a['name'], + 'lib_env_var_name':env_var_name, + 'is_qvip': 0, + 'initiator_responder':init_resp , + 'veloce_ready':veloce_ready, + 'infact_ready':infact_ready }] + except KeyError: pass + return alist + + ## This method returns an ordered list of information on ALL BFMs from a given top-level environment, down. + ## The list entries all have the following structure: + ## - BFM Name ('bfm_name') + ## - BFM Type ('bfm_type') + ## - BFM Parent Type ('parent_type') + ## - Environment Path ('env_path') + ## - VIP Library Env Variable Name ('lib_env_var_name') (only valid for non-QVIP) + ## - QVIP/Non-QVIP flag ('is_qvip') + ## - Initiator/Responder info ('initiator_responder') + ## - VeloceReady flag ('veloce_ready') + def getAllScoreboards(self,env_type,env_inst,envPath): + sblist = [] + struct = self.data['environments'] + try: + env = struct[env_type] + except KeyError: + raise UserError("Unable to find environment \""+env_type+"\" in defined environments (available list is "+str(struct.keys())) + try: + subenvs = env['subenvs'] + for e in subenvs: + sblist = sblist + self.getAllScoreboards(e['type'],e['name'],envPath+"."+e['name']) + except KeyError: pass + try: + sbs = env['scoreboards'] + for sb in sbs: + sblist = sblist + [envPath+"."+sb['name']] + except KeyError: pass + return sblist + + ## This method can be employed to return either a list of (non-QVIP) agents at the provided environment + ## level or recursively, searching through all sub-environments and down. + def getAgents(self,topEnv,recursive=True,givePath=False,parentPath=[]): + struct = self.data['environments'] + try: + env = struct[topEnv] + except KeyError: + raise UserError("Unable to find environment \""+topEnv+"\" in defined environments (available list is "+str(struct.keys())) + agents = [] + try: + agents = env['agents'] + except: + agents = [] + pass + if not givePath: + structure = agents + else: + structure = [] + for agent in agents: + try: + vip_lib_env_variable = self.data['interfaces'][agent['type']]['vip_lib_env_variable'] + except KeyError: + vip_lib_env_variable = "UVMF_VIP_LIBRARY_HOME" + structure = structure + [{ 'envpath' : parentPath, 'agent' : agent, 'vip_lib_env_variable' : vip_lib_env_variable }] + if not recursive: + return structure + try: + subEnvs = env['subenvs'] + for subEnv in subEnvs: + structure = structure + self.getAgents(subEnv['type'],recursive=True,givePath=givePath,parentPath=parentPath+[subEnv['name']]) + except KeyError: pass + return structure + + def dataExtract(self,keys,dictionary): + ## Pull the specified keys out of the given structure. If the key + ## does not exist return None for the given value + ret = [] + for key in keys: + try: + ret = ret + [dictionary[key]] + except KeyError: + ret = ret + [None] + pass + return ret + + def generateEnvironment(self,name,build_existing=False,archive_yaml=True): + env = EnvironmentClass(name) + struct = self.data['environments'][name] + qvip_agents_dot = [] + qvip_agents_und = [] + valid_ap_list = [] + valid_ae_list = [] + valid_qsubenv_list = [] + env_has_extdef_items = False + env = self.setupGlobalVars(env) + ## Extract any environment-level parameters and add them + try: + for param in struct['parameters']: + pname,ptype,pval = self.dataExtract(['name','type','value'],param) + env.addParamDef(pname,ptype,pval) + except KeyError: pass + try: + for param in struct['hvl_pkg_parameters']: + pname,ptype,pval = self.dataExtract(['name','type','value'],param) + env.addHvlPkgParamDef(pname,ptype,pval) + except KeyError: pass + ## Extract any configuration variable settings and add them + try: + for cv_val in struct['config_variable_values']: + cvvname,cvvval = self.dataExtract(['name','value'],cv_val) + env.addConfigVariableValue(cvvname,cvvval) + except KeyError: pass + ## Drill down into any QVIP subenvironments for import information, that'll be needed here + qstruct = self.getQVIPAgents(name) + ilist = qstruct['ilist'] + for i in ilist: + env.addImport(i) + ## Call out any locally defined imports + try: + for imp in struct['imports']: + env.addImport(imp['name']) + except KeyError: pass + ## If imp-decl macros are needed, add them + try: + for impdecl in struct ['imp_decls']: + env.addImpDecl(impdecl['name']) + except KeyError: pass + try: + for nonUvmfComps in struct ['non_uvmf_components']: + cname,ctype = self.dataExtract(['name', 'type'],nonUvmfComps) + try: + cextdef = ( nonUvmfComps['extdef'] == 'True' ) + env_has_extdef_items = True + except KeyError: + pass + try: + cparams_array = nonUvmfComps['parameters'] + except KeyError: + cparams_array = {} + pass + cparams = {} + for item in cparams_array: + n,v = self.dataExtract(['name','value'],item) + cparams[n] = v + env.addNonUvmfComponent(cname,ctype,cparams) + except KeyError: pass + try: + for qvipMemAgents in struct ['qvip_memory_agents']: + qmaname,qmatype,qmaqenv = self.dataExtract(['name', 'type','qvip_environment'],qvipMemAgents) + try: + qmaparams_array = qvipMemAgents['parameters'] + except KeyError: + qmaparams_array = {} + pass + qmaparams = {} + for item in qmaparams_array: + n,v = self.dataExtract(['name','value'],item) + qmaparams[n] = v + env.addQvipMemoryAgent(qmaname,qmatype,qmaqenv,qmaparams) + except KeyError: pass + ## The order of the following loops is important. The order in which local agents, sub-environments and QVIP + ## sub-environments are added must match the order in which they will be added at the bench level, otherwise + ## things will be configured out-of-order. + ## The order is as follows: + ## QVIP subenvs + ## Custom sub-environments + ## Locally defined custom interfaces + ## Look for defined QVIP sub-environments and add those + try: + for subenv in struct['qvip_subenvs']: + n,t = self.dataExtract(['name','type'],subenv) + try: + qvipStruct = self.data['qvip_environments'][t] + except KeyError: + raise UserError("QVIP environment \""+t+"\" in environment \""+name+"\" is not defined") + alist = [] + for a in qvipStruct['agents']: + alist = alist + [a['name']] + qvip_agents_dot = qvip_agents_dot + [n+"."+a['name']] + qvip_agents_und = qvip_agents_und + [n+"_"+a['name']] + valid_qsubenv_list = valid_qsubenv_list + [n] + env.addQvipSubEnv(name=n,envPkg=t,agentList=alist) + except KeyError: pass + ## Look for defined sub-environments and add them + try: + for subenv in struct['subenvs']: + ename,etype = self.dataExtract(['name','type'],subenv) + try: + subextdef = ( subenv['extdef'] == 'True' ) + env_has_extdef_items = True + except KeyError: + pass + try: + eparams_array = subenv['parameters'] + except KeyError: + eparams_array = {} + pass + eparams = {} + num = 0 + for item in eparams_array: + n,v = self.dataExtract(['name','value'],item) + eparams[n] = v + num += 1 + ## Determine how many agents are defined in the subenvironment as that is a required argument going into + ## this API call. This is a recursive count of agents. + agents = self.getAgents(etype,recursive=True) + ## Also find any underlying QVIP agents underneath this subenvironment (nested underneath underlying QVIP subenvs) + qvip_agents_struct = self.getQVIPAgents(etype); + qvip_agents = qvip_agents_struct['alist'] + if agents==None: + raise UserError("Sub-environment type \""+etype+"\" used in environment \""+name+"\" is not found") + self.check_parameters('environment',name,'subenv',ename,etype,eparams_array,self.data['environments'][etype]) + ## Check if subenv has a register model defined unless asked explicitly to avoid it + try: + v = subenv['use_register_model']=='True' + except KeyError: + v = True + pass + if v: + try: + rm = self.data['environments'][etype]['register_model'] + except KeyError: + rm = None + pass + else: + rm = None + if not rm: + rm_pkg = None + rm_block_class = None + else: + try: + rm_pkg = rm['reg_model_package'] + except KeyError: + rm_pkg = etype+"_reg_pkg" + pass + try: + rm_block_class = rm['reg_block_class'] + except KeyError: + rm_block_class = etype+"_reg_model" + pass + env.addSubEnv(ename,etype,len(agents)+len(qvip_agents),eparams,rm_pkg,rm_block_class) + env_def = self.data['environments'][etype] + try: + env_ap_list = env_def['analysis_ports'] + for env_ap in env_ap_list: + valid_ap_list = valid_ap_list + [ename+"."+env_ap['name']] + except KeyError: pass + try: + env_ae_list = env_def['analysis_exports'] + for env_ae in env_ae_list: + valid_ae_list = valid_ae_list + [ename+"."+env_ae['name']] + except KeyError: pass + except KeyError: pass + ## Locally defined agent instantiations + try: + for agent in self.getAgents(name,recursive=False): + aname,atype = self.dataExtract(['name','type'],agent) + try: + aextdef = ( agent['extdef'] == 'True' ) + env_has_extdef_items = True + except KeyError: + pass + try: + aparams_list = agent['parameters'] + except KeyError: + aparams_list = [] + pass + aparams = {} + for item in aparams_list: + n,v = self.dataExtract(['name','value'],item) + aparams[n] = v; + try: + intf = self.data['interfaces'][atype] + except KeyError: + raise UserError("Agent type \""+atype+"\" in environment \""+name+"\" is not recognized") + try: + initResp = agent['initiator_responder'] + except KeyError: + initResp = 'INITIATOR' + pass + self.check_parameters('environment',name,'agent',agent['name'],atype,aparams_list,self.data['interfaces'][atype]) + env.addAgent(agent['name'],atype,intf['clock'],intf['reset'],aparams,initResp) + valid_ap_list = valid_ap_list + [agent['name']+".monitored_ap"] + except KeyError: pass + defined_ac_items = [] + try: + ac_items = struct['analysis_components'] + except KeyError: + ac_items = [] + pass + for ac_item in ac_items: + ac_type,ac_name = self.dataExtract(['type','name'],ac_item) + try: + ac_params = ac_item['parameters'] + except KeyError: + ac_params = [] + pass + ## Don't go through the trouble of poking at the definition of the analysis component if it was already + ## used before. Just instantiate it + try: + extdef = (ac_item['extdef'] == 'True') + env_has_extdef_items = True + except KeyError: + extdef = False + pass + if (ac_type not in defined_ac_items) and (not extdef): + try: + definition = self.data['util_components'][ac_type] + except KeyError: + raise UserError("No definition found for component \""+ac_name+"\" of type \""+ac_type) + ac_type_type = definition['type'] + exports = {} + try: + for item in definition['analysis_exports']: + exports[item['name']] = item['type'] + except KeyError: pass + ports = {} + try: + for item in definition['analysis_ports']: + ports[item['name']] = item['type'] + except KeyError: pass + qvip_exports = {} + try: + for item in definition['qvip_analysis_exports']: + qvip_exports[item['name']] = item['type'] + except KeyError: pass + try: + parameters = definition['parameters'] + except KeyError: + parameters = [] + pass + try: + ac_mtlb_ready = definition['mtlb_ready']==True + except KeyError: + ac_mtlb_ready = False + env.defineAnalysisComponent(ac_type_type,ac_type,exports,ports,qvip_exports,parameters,mtlbReady=ac_mtlb_ready) + defined_ac_items = defined_ac_items + [ac_type] + if ac_type not in self.used_ac_items: + self.used_ac_items = self.used_ac_items + [ac_type] + if not extdef: + self.check_parameters('environment',name,ac_type_type,ac_name,ac_type,ac_params,self.data['util_components'][ac_type]) + env.addAnalysisComponent(ac_name,ac_type,ac_params,extdef) + try: ports + except NameError: ports = None + if ports is not None: + for ap in ports: + valid_ap_list = valid_ap_list + [ac_name+"."+ap] + try: exports + except NameError: exports = None + if exports is not None: + for ae in exports: + valid_ae_list = valid_ae_list + [ac_name+"."+ae] + try: qvip_exports + except NameError: qvip_exports = None + if qvip_exports is not None: + for qae in qvip_exports: + valid_ae_list = valid_ae_list + [ac_name+"."+qae] + try: + sb_items = struct['scoreboards'] + except KeyError: + sb_items = [] + pass + for sb_item in sb_items: + sb_name,sb_type,trans_type = self.dataExtract(['name','sb_type','trans_type'],sb_item) + try: + sb_params_list = sb_item['parameters'] + except KeyError: + sb_params_list = [] + pass + sb_params = {} + for item in sb_params_list: + n,v = self.dataExtract(['name','value'],item) + sb_params[n] = v + env.addUvmfScoreboard(sb_name,sb_type,trans_type,sb_params) + valid_ae_list = valid_ae_list + [sb_name+".expected_analysis_export"] + valid_ae_list = valid_ae_list + [sb_name+".actual_analysis_export"] + try: + for item in struct['analysis_ports']: + n,t,c = self.dataExtract(['name','trans_type','connected_to'],item) + if c not in valid_ap_list: + mess = "TLM connected_to entry \""+c+"\" listed in analysis_ports for environment \""+name+"\" not a valid TLM driver name. \nValid names:" + for ap in valid_ap_list: + mess = mess+"\n "+ap + if env_has_extdef_items: + mess = mess+"\nPort may be on externally defined component - Skipping check on this connnection." + print(mess) + else: + raise UserError(mess) + env.addAnalysisPort(n,t,c) + except KeyError: pass + try: + for item in struct['analysis_exports']: + n,t,c = self.dataExtract(['name','trans_type','connected_to'],item) + if c not in valid_ae_list: + mess = "TLM connected_to entry \""+c+"\" listed in analysis_exports for environment \""+name+"\" not a valid TLM receiver name. \nValid names:" + for ae in valid_ae_list: + mess = mess+"\n "+ae + if env_has_extdef_items: + mess = mess+"\nPort may be on externally defined component - Skipping check on this connnection." + print(mess) + else: + raise UserError(mess) + env.addAnalysisExport(n,t,c) + except KeyError: pass + try: + for item in struct['qvip_connections']: + d,r,k,v = self.dataExtract(['driver','receiver','ap_key','validate'],item) + rlist = r.split(".") + ## Allow the driver (QVIP) to contain regular "." hierarchy for clarity. Convert any found + ## to underscores in order to adhere to the API + dm = re.sub(r'\.','_',d) + if not v: + v = 'True' + if v == 'True': + if dm not in qvip_agents_und: + mess = "QVIP TLM Driver name entry \""+d+"\" listed in qvip_connections for environment \""+name+"\" not a valid QVIP agent name. \nValid names:" + for b in qvip_agents_dot: + mess = mess+"\n "+b + mess = mess+"\nNote: Underscores are valid substitutions within YAML for dot delimeters in this list of valid names.\n" + if env_has_extdef_items: + mess = mess+"\nPort may be on externally defined component - Skipping check on this connnection." + print(mess) + else: + raise UserError(mess) + if r not in valid_ae_list: + mess = "QVIP TLM Receiver name entry \""+r+"\" listed in qvip_connections for environment \""+name+"\" not a valid QVIP TLM receiver name. \nValid names:" + for ae in valid_ae_list: + mess = mess+"\n "+ae + if env_has_extdef_items: + mess = mess+"\nPort may be on externally defined component - Skipping check on this connnection." + print(mess) + else: + raise UserError(mess) + env.addQvipConnection(dm,k,'.'.join(rlist[:-1]),rlist[-1],v) + except KeyError: pass + try: + for conn in struct['tlm_connections']: + d,r,v = self.dataExtract(['driver','receiver', 'validate'],conn) + dlist = d.split(".") + rlist = r.split(".") + ## The driver and receiver entries provided need to be split to work with the API in uvmf_gen + if not v: + v = 'True' + if v == 'True': + if d not in valid_ap_list: + mess = "TLM Driver name entry \""+d+"\" listed in tlm_connections for environment \""+name+"\" not a valid TLM driver name. \nValid names:" + for ap in valid_ap_list: + mess = mess+"\n "+ap + if dlist[0] not in valid_qsubenv_list: + if env_has_extdef_items: + mess = mess+"\nPort may be on externally defined component - Skipping check on this connnection." + print(mess) + else: + raise UserError(mess) + if r not in valid_ae_list: + mess = "TLM Receiver name entry \""+r+"\" listed in tlm_connections for environment \""+name+"\" not a valid TLM receiver name. \nValid names:" + for ae in valid_ae_list: + mess = mess+"\n "+ae + if env_has_extdef_items: + mess = mess+"\nPort may be on externally defined component - Skipping check on this connnection." + print(mess) + else: + raise UserError(mess) + env.addConnection('.'.join(dlist[:-1]),dlist[-1],'.'.join(rlist[:-1]),rlist[-1],v) + except KeyError: pass + try: + for cfg_item in struct['config_vars']: + n,t,c = self.dataExtract(['name','type','comment'],cfg_item) + if not c: + c = "" + try: + crand = (cfg_item['isrand']=="True") + except KeyError: + crand = False + pass + cval = '' + try: + cval = cfg_item['value'] + except KeyError: pass + try: + cvud = cfg_item['unpacked_dimension'] + except KeyError: + cvud = "" + pass + env.addConfigVar(n,t,crand,cval,c,cvud) + except KeyError: pass + try: + for item in struct['config_constraints']: + n,v,c = self.dataExtract(['name','value','comment'],item) + if not c: + c = "" + env.addConfigVarConstraint(n,v,c) + except KeyError: pass + try: + regInfo = struct['register_model'] + except KeyError: + regInfo = None + pass + if regInfo != None: + try: + reg_model_pkg = regInfo['reg_model_package'] + except KeyError: + reg_model_pkg = name+"_reg_pkg" + pass + try: + reg_blk_class = regInfo['reg_block_class'] + except KeyError: + reg_blk_class = name+"_reg_model" + pass + try: + maps = regInfo['maps'] + except KeyError: + maps = None + pass + if maps==None: + use_adapter = False + use_explicit_prediction = False + sequencer = None + trans = None + adapter = None + mapName = None + qvip_agent = False + else: + try: + use_adapter = regInfo['use_adapter'] == "True" + except KeyError: + use_adapter = True + try: + use_explicit_prediction = regInfo['use_explicit_prediction'] == "True" + except KeyError: + use_explicit_prediction = True + maps = regInfo['maps'] + ## Currently only support a single map - this will change in the future, hopefully + if len(maps) != 1: + raise UserError("Register model in environment \""+name+"\" can only have one map defined") + ## Extract information regarding the interface we should be attaching to. + ## First, confirm that the name of the agent is a valid instance. This will return a list + ## of structures, each with an 'name' key and 'type' key. The interface we're attaching to + ## must match up with the 'name' key in this list somewhere + try: + qvip_agent = maps[0]['qvip_agent'] + except KeyError: + qvip_agent = "False" + pass + if qvip_agent == "False": + agent_list = self.getAgents(name,recursive=True) + agent_type = "" + for a in agent_list: + if a['name'] == maps[0]['interface']: + ## Testing for a defined type might be thought to be needed here but if it wasn't a + ## valid agent type the above check would never pass + agent_type = a['type'] + try: + agent_params = self.parameterSyntax(a['parameters']) + except KeyError: + agent_params = "" + pass + break + if agent_type == "": + raise UserError("For register map \""+maps[0]['name']+"\" in environment \""+name+"\" no interface \""+maps[0]['interface']+"\" was found") + sequencer = maps[0]['interface'] + trans = agent_type+"_transaction"+agent_params + adapter = agent_type+"2reg_adapter"+agent_params + mapName = maps[0]['name'] + else: + sequencer = maps[0]['interface'] + trans = "uvm_sequence_item" + adapter = "uvm_reg_adapter" + mapName = maps[0]['name'] + env.addRegisterModel( + sequencer=sequencer, + transactionType=trans, + adapterType=adapter, + busMap=mapName, + useAdapter=use_adapter, + useExplicitPrediction=use_explicit_prediction, + qvipAgent=qvip_agent, + regModelPkg=reg_model_pkg, + regBlockClass=reg_blk_class) + try: + dpi_def = struct['dpi_define'] + ca = "" + la = "" + try: + ca = dpi_def['comp_args'] + except KeyError: pass + try: + la = dpi_def['link_args'] + except KeyError: pass + env.setDPISOName(value=dpi_def['name'],compArgs=ca,linkArgs=la) + for f in dpi_def['files']: + env.addDPIFile(f) + try: + for imp in dpi_def['imports']: + sv_args = [] + try: + sv_args = imp['sv_args'] + except KeyError: pass + env.addDPIImport(imp['c_return_type'],imp['sv_return_type'],imp['name'],imp['c_args'],sv_args) + except KeyError: pass + try: + for exp in dpi_def['exports']: + intf.addDPIExport(exp) + except KeyError: pass + except KeyError: pass + try: + typedefs = struct['typedefs'] + for t in typedefs: + n,v = self.dataExtract(['name','type'],t) + env.addTypedef(n,v) + except KeyError: pass + ## UVMC Stuff + try: + env.addUVMCflags(struct['uvmc_flags']) + except KeyError: pass + try: + env.addUVMClinkArgs(struct['uvmc_link_args']) + except KeyError: pass + try: + cpp_files = struct['uvmc_files'] + for f in cpp_files: + env.addUVMCfile(f) + except KeyError: pass + try: + env.mtlbReady = (struct['mtlb_ready']=="True") + except KeyError: + pass + existing_component = False + try: + if not build_existing: + existing_component = (struct['existing_library_component']=="True") + except KeyError: + pass + if (existing_component == True): + print(" Skipping generation of predefined component "+str(name)) + else: + env.create(parser=self.parser,archive_yaml=archive_yaml) + return env + + def parameterSyntax(self,parameterList): + ## Take the parameter list provided and return the SV syntax for a parameterized type + ## This is expected to be of "parameterUseSchema" with 'name' and a 'value' keys + l = [] + for p in parameterList: + s = "."+p['name']+"("+p['value']+")" + l = l + [ s ] + fs = "#("+','.join(l)+")" + return fs + + def generateBench(self,name,build_existing=False,archive_yaml=True): + ## Isolate the YAML structure for this bench + struct = self.data['benches'][name] + ## Get the name of the top-level environment + top_env = struct['top_env'] + ## Confirm top-level environment is defined + if top_env not in self.data['environments']: + raise UserError("Bench \"{}\" top-env of type \"{}\" is not defined".format(name,top_env)) + ## Top-level environment parameters + try: + env_params_list = struct['top_env_params'] + except KeyError: + env_params_list = [] + pass + ## Build up simpler name/value pair dict of env params + env_params = {} + for p in env_params_list: + env_params[p['name']] = p['value'] + ## Check that parameterization is valid for the top-env + self.check_parameters('bench',name,'environment',top_env,'top_env',env_params_list,self.data['environments'][top_env]) + ## With this information we can create the bench class object + ben = BenchClass(name,top_env,env_params) + ben = self.setupGlobalVars(ben) + ## Look for clock and reset control settings (all optional) + try: + ben.clockHalfPeriod = struct['clock_half_period'] + except KeyError: pass + try: + ben.clockPhaseOffset = struct['clock_phase_offset'] + except KeyError: pass + try: + ben.resetAssertionLevel = (struct['reset_assertion_level']=='True') + except KeyError: pass + try: + ben.useDpiLink = (struct['use_dpi_link']=='True') + except KeyError: pass + try: + ben.resetDuration = struct['reset_duration'] + except KeyError: pass + try: + ben.activePassiveDefault = struct['active_passive_default'] + except KeyError: + ben.activePassiveDefault = 'ACTIVE' + pass + ## Check for inFact ready flag + ben.inFactEnabled = ('infact_enabled' in struct.keys() and struct['infact_enabled']=='True') + + ## Use co-emulation clk/rst generator + try: + ben.useCoEmuClkRstGen = (struct['use_coemu_clk_rst_gen']=='True') + except KeyError: pass + ## Set the veloceReady flag for the bench + try: + ben.veloceReady = (struct['veloce_ready'] == "True") + except KeyError: + ben.veloceReady = True + pass + ## Pull out bench-level parameter definitions, if any + try: + for param in struct['parameters']: + pname,ptype,pval = self.dataExtract(['name','type','value'],param) + ben.addParamDef(pname,ptype,pval) + except KeyError: pass + ## Drill down into any QVIP subenvironments for import information, that'll be needed here + qstruct = self.getQVIPAgents(top_env) + ilist = qstruct['ilist'] + for i in ilist: + ben.addImport(i) + ## Imports + try: + for imp in struct['imports']: + ben.addImport(imp['name']) + except KeyError: pass + ## Pull out active/passive list and produce more easily parsed dict keyed by the BFM names + try: + ap_list = struct['active_passive'] + except KeyError: + ap_list = [] + pass + ap_dict = {} + for i in ap_list: + ap_dict[i['bfm_name']] = i['value'] + ## Do the same for interface parameters + try: + ifp_list = struct['interface_params'] + except KeyError: + ifp_list = [] + ifp_dict = {} + for entry in ifp_list: + bfm_name = entry['bfm_name'] + param_list = entry['value'] + ifp_dict[bfm_name] = {} + for p in param_list: + ifp_dict[bfm_name][p['name']] = p['value'] + ## Determine if top_env has a register model associated with it + try: + e = self.data['environments'][top_env] + except KeyError: + raise UserError("Top-level env \""+top_env+"\" is not defined") + try: + rm = e['register_model'] + ben.topEnvHasRegisterModel = True + try: + rm_pkg = rm['reg_model_package'] + ben.regModelPkg = e['register_model']['reg_model_package'] + except KeyError: + ben.regModelPkg = top_env+"_reg_pkg" + pass + try: + ben.regBlockClass = e['register_model']['reg_block_class'] + except KeyError: + ben.regBlockClass = top_env+"_reg_model" + pass + except KeyError: + ben.topEnvHasRegisterModel = False + pass + ## Find BFMs and add those - order is important, must match how we instantiated the components + ## within the environment. Traverse the environment topology in the order in which sub-envs were + ## called out in the YAML. Use getAllAgents to intelligently traverse the topology and build up a list + ## of BFMs (may be a mix of QVIP and non-QVIP BFMs). Each entry in the resulting list will be a structure + ## with the following information: + ## - BFM Name + ## - BFM Type + ## - Environment Path + ## - QVIP/Non-QVIP flag + ## - Active/Passive flag + ## - Initiator/Responder flag + ## - Veloce Ready flag (for checking) + alist = self.getAllAgents(top_env,'environment',0,'environment') + ## Check for Veloce compatibility. If the bench has been flagged for veloce_ready then none of the underlying + ## non-QVIP agents can be flagged differently. QVIP is a different story, for now. + if ben.veloceReady: + for a in alist: + if a['is_qvip']==0: # Don't bother checking QVIP agents + if not a['veloce_ready']: + ## Fatal out if bench veloce_ready is TRUE but any agents underneath are FALSE + raise UserError("Bench \""+name+"\" is flagged veloce_ready True but underlying agent \""+a['env_path']+"\" of type \""+a['bfm_type']+"\" is flagged veloce_ready False") + valid_bfm_names = [] + ## Now that we have an ordered list of BFMs we can call the appropriate API call for each + for a in alist: + if a['env_path'].count('.')==1: + bfm_name = a['bfm_name'] + debugpath = 'environment' + else: + debugpath = re.sub(r'(.*)\.\w+',r'\1',a['env_path']) + bfm_name = re.sub(r'^environment\.','',a['env_path']) + bfm_name = re.sub(r'\.',r'_',bfm_name) + valid_bfm_names = valid_bfm_names + [bfm_name] + try: + active_passive = ap_dict[bfm_name] + except KeyError: + active_passive = ben.activePassiveDefault + if a['is_qvip']==1: + ## Add each QVIP BFM instantiation. Function API is slightly different for QVIP vs. non-QVIP + ben.addQvipBfm(name=a['bfm_name'],ifPkg=a['parent_type'],activity=active_passive,unique_id=self.getUniqueID(a['env_path'])) + else: + ## Name of each BFM is simplified if they live under the top-level env + ## Determine this by inspecting the env_path entry for each item and counting + ## the number of dots (.). If only one, means this BFM lives at the top-most + ## level. + try: + agentDef = self.data['interfaces'][a['bfm_type']] + except: + raise UserError("Definition for interface type \""+a['bfm_type']+"\" for instance \""+a['env_path']+"\" is not found") + try: + aParams = ifp_dict[bfm_name] + except KeyError: + aParams = {} + pass + infact_ready = ('infact_ready' in a.keys() and a['infact_ready']) + try: + port_list = agentDef['ports'] + except KeyError: + port_list = [] + ben.addBfm(name=bfm_name,ifPkg=a['bfm_type'],clk=agentDef['clock'],rst=agentDef['reset'],activity=active_passive,parametersDict=aParams,sub_env_path=debugpath,agentInstName=a['bfm_name'],vipLibEnvVariable=a['lib_env_var_name'],initResp=a['initiator_responder'],inFactReady=infact_ready,portList=port_list) + ## Check that all keys in the ifp_dict and ap_dict match something in the valid_bfm_names list that + ## was based on the actual UVM component hierarchy elements. If not, it probably means we have a typo somewhere in the bench YAML + for k in ifp_dict.keys(): + if k not in valid_bfm_names: + mess = "BFM name entry \""+k+"\" listed in interface_params structure for bench \""+name+"\" but not a valid BFM name. Valid BFM names:" + for b in valid_bfm_names: + mess = mess+"\n "+b + raise UserError(mess) + for k in ap_dict.keys(): + if k not in valid_bfm_names: + mess = "BFM name entry \""+k+"\" listed in active_passive structure for bench \""+name+"\" but not a valid BFM name. Valid BFM names:" + for b in valid_bfm_names: + mess = mess+"\n "+b + raise UserError(mess) + ## Now drill down again but this time find any DPI packages - these could be defined at any + ## interface or environment, so getAgents isn't good enough. Also need to call getEnvironments + dpi_packages = [] + vinfo_interface_dpi_dependencies = [] + vinfo_environment_dpi_dependencies = [] + for agent in self.getAgents(top_env,recursive=True): + try: + dpi_pkg = self.data['interfaces'][agent['type']]['dpi_define']['name'] + if dpi_pkg not in dpi_packages: + dpi_packages.append(dpi_pkg) + #vinfo_interface_dpi_dependencies.append(self.data['interfaces'][agent['type']]['dpi_define']['name']) + vinfo_interface_dpi_dependencies.append(agent['type']) + except KeyError: pass + envs = self.getEnvironments(top_env,recursive=True) + ## Also add the top-environment to the array when searching for DPI + for env in envs+[{'type':top_env}]: + try: + dpi_pkg = self.data['environments'][env['type']]['dpi_define']['name'] + if dpi_pkg not in dpi_packages: + dpi_packages.append(dpi_pkg) + #vinfo_environment_dpi_dependencies.append(self.data['environments'][env['type']]['dpi_define']['name']) + vinfo_environment_dpi_dependencies.append(env['type']) + except KeyError: pass + for d in dpi_packages: + ben.addDPILibName(d) + for d in vinfo_interface_dpi_dependencies: + ben.addVinfoDependency("comp_"+d+"_pkg_c_files") + for d in vinfo_environment_dpi_dependencies: + ben.addVinfoDependency("comp_"+d+"_env_pkg_c_files") + sblist = self.getAllScoreboards(top_env,'environment','environment') + try: sblist + except NameError: sblist = None + if sblist is not None: + for sb in sblist: + ben.addScoreboard(sb) + try: + for t in struct['additional_tops']: + ben.addTopLevel(t) + except KeyError: pass + try: + ben.mtlbReady = (struct['mtlb_ready']=="True") + except KeyError: + pass + try: + ben.useBCR = (struct['use_bcr']=="True") + except KeyError: + ben.useBCR = False + existing_component = False + try: + if not build_existing: + existing_component = (struct['existing_library_component']=="True") + except KeyError: + pass + if (existing_component == True): + print(" Skipping generation of predefined component "+str(name)) + else: + ben.create(parser=self.parser,archive_yaml=archive_yaml) + return ben + + def generateInterface(self,name,build_existing=False,archive_yaml=True): + intf = InterfaceClass(name) + struct = self.data['interfaces'][name] + intf.clock = struct['clock'] + intf.reset = struct['reset'] + intf = self.setupGlobalVars(intf) + try: + intf.resetAssertionLevel = (struct['reset_assertion_level'] == 'True') + except KeyError: pass + try: + intf.useDpiLink = (struct['use_dpi_link']=='True') + except KeyError: pass + try: + intf.genInBoundStreamingDriver = (struct['gen_inbound_streaming_driver']=='True') + except KeyError: pass + try: + intf.vipLibEnvVariable = struct['vip_lib_env_variable'] + except KeyError: pass + try: + for imp in struct['imports']: + intf.addImport(imp['name']) + except KeyError: pass + try: + for item in struct['parameters']: + n,t,v = self.dataExtract(['name','type','value'],item) + intf.addParamDef(n,t,v) + except KeyError: pass + try: + for item in struct['hdl_pkg_parameters']: + n,t,v = self.dataExtract(['name','type','value'],item) + intf.addHdlPkgParamDef(n,t,v) + except KeyError: pass + try: + for item in struct['hvl_pkg_parameters']: + n,t,v = self.dataExtract(['name','type','value'],item) + intf.addHvlPkgParamDef(n,t,v) + except KeyError: pass + try: + for item in struct['hdl_typedefs']: + n,t = self.dataExtract(['name','type'],item) + intf.addHdlTypedef(n,t) + except KeyError: pass + try: + for item in struct['hvl_typedefs']: + n,t = self.dataExtract(['name','type'],item) + intf.addHvlTypedef(n,t) + except KeyError: pass + try: + for port in struct['ports']: + n,w,d = self.dataExtract(['name','width','dir'],port) + if not re.search(r"^(input|output|inout)$",d): + raise UserError("Direction \""+d+"\" invalid for port \""+n+"\" in interface \""+name+"\"") + try: + r = (port['reset_value']) + except KeyError: + r = "'bz" + intf.addPort(n,w,d,r) + except KeyError: pass + try: + for trans in struct['transaction_vars']: + n,t,c = self.dataExtract(['name','type','comment'],trans) + if not c: + c = "" + try: + trand = (trans['isrand']=="True") + except KeyError: + trand = False + pass + try: + tcomp = (trans['iscompare']=="True") + except KeyError: + tcomp = True + pass + try: + ud = trans['unpacked_dimension'] + except KeyError: + ud = "" + pass + intf.addTransVar(n,t,isrand=trand,iscompare=tcomp,unpackedDim=ud,comment=c) + except KeyError: pass + try: + for cfg in struct['config_vars']: + n,t,c = self.dataExtract(['name','type','comment'],cfg) + if not c: + c = "" + try: + crand = (cfg['isrand']=="True") + except KeyError: + crand = False + pass + cval = '' + try: + cval = cfg['value'] + except KeyError: pass + try: + cvud = cfg['unpacked_dimension'] + except KeyError: + cvud = "" + pass + intf.addConfigVar(n,t,crand,cval,c,cvud) + except KeyError: pass + try: + for item in struct['transaction_constraints']: + n,v,c = self.dataExtract(['name','value','comment'],item) + if not c: + c = "" + intf.addTransVarConstraint(n,v,c) + except KeyError: pass + try: + for item in struct['config_constraints']: + n,v,c = self.dataExtract(['name','value','comment'],item) + if not c: + c = "" + intf.addConfigVarConstraint(n,v,c) + except KeyError: pass + try: + response_info = struct['response_info'] + resp_op = response_info['operation'] + intf.specifyResponseOperation(resp_op) + resp_data = response_info['data'] + intf.specifyResponseData(resp_data) + print("Warning: response_info YAML structure deprecated. Slave agent response data now determined by arguments to respond_and_wait_for_next_transfer task within generated driver_bfm.") + except KeyError: pass + try: + dpi_def = struct['dpi_define'] + ca = "" + la = "" + try: + ca = dpi_def['comp_args'] + except KeyError: pass + try: + la = dpi_def['link_args'] + except KeyError: pass + intf.setDPISOName(value=dpi_def['name'],compArgs=ca,linkArgs=la) + for f in dpi_def['files']: + intf.addDPIFile(f) + try: + for imp in dpi_def['imports']: + sv_args = [] + try: + sv_args = imp['sv_args'] + except KeyError: pass + intf.addDPIImport(imp['c_return_type'],imp['sv_return_type'],imp['name'],imp['c_args'],sv_args) + except KeyError: pass + try: + for exp in dpi_def['exports']: + intf.addDPIExport(exp) + except KeyError: pass + except KeyError: pass + intf.inFactReady = ('infact_ready' in struct.keys() and struct['infact_ready']) + try: + intf.mtlbReady = (struct['mtlb_ready']=="True") + except KeyError: + pass + try: + intf.veloceReady = (struct['veloce_ready'] == "True") + except KeyError: + intf.veloceReady = True + pass + try: + intf.enableFunctionalCoverage = (struct['enable_functional_coverage'] == "True") + except KeyError: pass + if intf.veloceReady == True: + try: + for trans in struct['transaction_vars']: + try: + if trans['unpacked_dimension'] != "": + raise UserError("Interface \""+name+"\" flagged to be Veloce ready but transaction variable \""+trans['name']+"\" has specified an unpacked dimension") + except KeyError: pass + except KeyError: + ## If this happens it means there are no transaction variables, which is also illegal + raise UserError("Interface \"{0}\" flagged to be Veloce ready but no transaction variables have been defined. Must define at least one".format(name)) + pass + try: + for cfg in struct['config_vars']: + try: + if cfg['unpacked_dimension'] != "": + raise UserError("Interface \""+name+"\" flagged to be Veloce ready but configuration variable \""+cfg['name']+"\" has specified an unpacked dimension") + except KeyError: pass + except KeyError: pass + ## If this happens it means there are no transaction variables, which is also illegal +# raise UserError("Interface \"{0}\" flagged to be Veloce ready but no transaction variables have been defined. Must define at least one".format(name)) +# pass + ## Also possible that there was a transaction variables array defined but its empty. Also illegal + if len(struct['transaction_vars'])==0: + raise UserError("Interface \"{0}\" flagged to be Veloce ready but no transaction variables have been defined. Must define at least one".format(name)) + existing_component = False + try: + if not build_existing: + existing_component = (struct['existing_library_component']=="True") + except KeyError: + pass + if existing_component == True: + print(" Skipping generation of predefined component "+str(name)) + else: + intf.create(parser=self.parser,archive_yaml=archive_yaml) + return intf + + def check_parameters(self,parentType,parentName,instanceType,instanceName,definitionName,instanceParams,instanceDefinition): + ## Compare the parameters in a given instance to make sure that the names match up with + ## something in the list of parameters given in the definition. Can be used for any component. Pass + ## in the list of parameters for both. If problem found, display debug information + ## including the name of the parent component, the name and type of the instance and the + ## parameter in question. + ## Don't bother checking anything if the instiation was not provided any parameters. + if len(instanceParams) == 0: + return + try: + definitionParams = instanceDefinition['parameters'] + except KeyError: + raise UserError("When instantiating "+instanceType+" \""+instanceName+"\" of type \""+definitionName+"\" inside "+parentType+" \""+parentName+"\", parameters were provided but definition had no parameters") + ipn = [] + dpn = [] + for p in definitionParams: + dpn = dpn + [p['name']] + for p in instanceParams: + if p['name'] not in dpn: + raise UserError("Unable to find parameter \""+p['name']+"\" in definition of "+instanceType+" \""+definitionName+"\" as instance \""+instanceName+"\" in "+parentType+" \""+parentName+"\"") + +def run(): + ## When invoked, this script can read a series of provided YAML-based configuration files and parse them, building + ## up a database of information on the contained components. Each component will have an associated uvmf_gen class + ## created around it based on the contents. + + ## User can specify that a particular element(s) be created with the -g/--generate switch but the default is to produce + ## everything (i.e. call ".create()" against all defined elements). Any item passed in via --generate + ## that matches the name of a defined element will be generated (if environments/benches/interfaces are named the + ## same the script will match all of them) + search_paths = ['.'] + __version__ = version + uvmf_parser = UVMFCommandLineParser(version=__version__,usage="yaml2uvmf.py [options] [yaml_file1 [yaml_fileN]]") + uvmf_parser.parser.add_option("-f","--file",dest="configfile",action="append",help="Specify a file list of YAML configs. Relative paths relative to the invocation directory") + uvmf_parser.parser.add_option("-F","--relfile",dest="rel_configfile",action="append",help="Specify a file list of YAML configs. Relative paths relative to the file list itself") + uvmf_parser.parser.add_option("-g","--generate",dest="gen_name",action="append",help="Specify which elements to generate (default is everything") + uvmf_parser.parser.add_option("--pdb",dest="enable_pdb",action="store_true",help=SUPPRESS_HELP,default=False) + uvmf_parser.parser.add_option("-m","--merge_source",dest="merge_source",action="store",help="Enable auto-merge flow, pulling from the specified source directory") + uvmf_parser.parser.add_option("-s","--merge_skip_missing_blocks",dest="merge_skip_missing",action="store_true",help="Continue merge if unable to locate a custom block that was defined in old source, producing a report at the end. Default behavior is to raise an error",default=False) + uvmf_parser.parser.add_option("--merge_export_yaml",dest="merge_export_yaml",action="store",help=SUPPRESS_HELP,default=None) + uvmf_parser.parser.add_option("--merge_import_yaml",dest="merge_import_yaml",action="store",help=SUPPRESS_HELP,default=None) + uvmf_parser.parser.add_option("--merge_import_yaml_output",dest="merge_import_yaml_output",action="store",help=SUPPRESS_HELP,default="uvmf_template_merged") + uvmf_parser.parser.add_option("--merge_no_backup",dest="merge_no_backup",action="store_true",help="Do not back up original merge source",default=False) + uvmf_parser.parser.add_option("--merge_debug",dest="merge_debug",action="store_true",help="Provide intermediate unmerged output directory for debug purposes. Debug directory can be specified by --dest_dir switch.",default=False) + uvmf_parser.parser.add_option("--merge_verbose",dest="merge_verbose",action="store_true",help="Output more verbose messages during the merge operation for debug purposes.",default=False) + uvmf_parser.parser.add_option("--build_existing_components",dest="build_existing_components",action="store_true",help="Ignore \"existing_library_component\" flags and attempt to build anyway.",default=False) + uvmf_parser.parser.add_option("--no_archive_yaml",dest="no_archive_yaml",action="store_true",default=False,help="Disable YAML archive creation") + (options,args) = uvmf_parser.parser.parse_args() + if options.enable_pdb or options.debug: + print("Python version info:\n"+sys.version) + if options.enable_pdb == True: + import pdb + pdb.set_trace() + elif options.debug == False: + sys.tracebacklimit = 0 + if (len(args) == 0) and (options.configfile == None) and (options.rel_configfile == None) and (options.merge_source == None): + raise UserError("No configurations or config file specified as input. Must provide one or both") + if (options.merge_source != None) and (options.merge_import_yaml != None): + raise UserError("--merge_source and --merge_import_yaml options are mutually exclusive") + dataObj = DataClass(uvmf_parser) + configfiles = [] + if options.configfile != None: + for cf in options.configfile: + cfr = ConfigFileReader(cf) + configfiles = configfiles + cfr.files + if options.rel_configfile != None: + for cf in options.rel_configfile: + cfr = ConfigFileReader(cf,relative_to_file=True) + configfiles = configfiles + cfr.files + try: + configfiles = configfiles + args + except TypeError: + pass + if len(configfiles) == 0: + if not ((options.merge_source != None) and (options.merge_export_yaml)): + raise UserError("No configuration YAML specified to parse, must provide at least one") + if options.merge_source != None: + if os.path.abspath(os.path.normpath(options.dest_dir)) == os.path.abspath(os.path.normpath(options.merge_source)): + raise UserError("Cannot merge changes into source directory \"{0}\" without specifying an alternate output directory with --dest_dir switch".format(os.path.abspath(os.path.normpath(options.dest_dir)))) + for cfg in configfiles: + dataObj.parseFile(cfg) + dataObj.validate() + dataObj.buildElements(options.gen_name,verify=options.merge_export_yaml==None,build_existing=options.build_existing_components,archive_yaml=(not options.no_archive_yaml)) + if options.merge_source or options.merge_import_yaml: + if not options.merge_import_yaml: + if not (options.merge_no_backup or options.merge_export_yaml): + ## Create a backup of the original source. + backup_copy = backup(options.merge_source) + if not options.quiet: + print("Backed up original source to {0}".format(backup_copy)) + if not options.quiet: + print("Parsing customizations from {0} ...".format(options.merge_source)) + # Parse old source for pragma blocks. Resulting object will contain data structure of this activity + parse = Parse(quiet=options.quiet,cleanup=options.merge_import_yaml,root=os.path.abspath(os.path.normpath(options.merge_source))) + # Need to first produce a list of directories in the new output. Only validate files in the merge source + # that are in the equivalent directories (to do otherwise would be a waste of time) + parse.collect_directories(new_root_dir=options.dest_dir,old_root_dir=options.merge_source) + # Traverse through the merged source directory structure. This will only collect data on + # directories that were just re-generated, nothing outside of that area. + parse.traverse_dir(options.merge_source) + old_root = parse.root + if options.merge_export_yaml: + if not options.quiet: + print(" Exporting merge data to {0}".format(options.merge_export_yaml)) + parse.dump(options.merge_export_yaml) + sys.exit(0) + else: + if not options.quiet: + print("Merging custom code in {0} with new output ...".format(options.merge_source)) + else: + if not options.quiet: + print("Pulling in customizations from imported YAML file {0}".format(options.merge_import_yaml)) + old_root = os.path.abspath(os.path.normpath(options.merge_import_yaml_output)) + merge = Merge(outdir=old_root,skip_missing_blocks=options.merge_skip_missing,new_root=os.path.abspath(os.path.normpath(options.dest_dir)),old_root=old_root,quiet=options.quiet) + if options.merge_import_yaml: + merge.load_yaml(options.merge_import_yaml) + # If we're importing the data, copy newly generated source over to desired final location. This will be what we treat as the "original" output directory + from shutil import copytree + try: + copytree(options.dest_dir,options.merge_import_yaml_output) + except: + pass + else: + merge.load_data(parse.data) + merge.traverse_dir(options.dest_dir) + if (not options.merge_debug): + # Remove the intermediate directory unless asked otherwise + if not options.quiet: + print("Deleting intermediate directory {0} after merging data...".format(options.dest_dir)) + try: + shutil.rmtree(options.dest_dir) + except: + raise UserError("Unable to remove intermediate output directory {0}. Permissions issue?".format(options.dest_dir)) + if not options.quiet: + print("Merge complete!") + if options.merge_verbose: + merge_summary(merge,verbose=True) + merge_summary(merge) + if len(merge.missing_blocks)>0: + print("WARNING: Found \"pragma uvmf custom\" blocks in original source that could not be mapped to new output. These require hand-edits:") + for f in merge.missing_blocks: + print (" File: {0}".format(f)) + for l in merge.missing_blocks[f]: + print(" \"{0}\"".format(l)) + print(" Use backup or revision control source to recover the original content of these blocks") + +if __name__ == '__main__': + run() diff --git a/UVM_Framework/UVMF_2022.3/scripts/Makefile b/UVM_Framework/UVMF_2022.3/scripts/Makefile index bac8b10a..e00f6917 100644 --- a/UVM_Framework/UVMF_2022.3/scripts/Makefile +++ b/UVM_Framework/UVMF_2022.3/scripts/Makefile @@ -49,7 +49,7 @@ ifeq ($(DEBUG),1) endif # Control if we wish to use the multi-user coverage mode -MULTIUSER ?= 1 +MULTIUSER ?= 0 #1 # Control whether or not to run at all in debug simulation NO_RUN ?= 0 diff --git a/UVM_Framework/UVMF_2022.3/templates/python/python2/jinja2/__init__.pyc b/UVM_Framework/UVMF_2022.3/templates/python/python2/jinja2/__init__.pyc index 753bb701..b42b15a3 100644 Binary files 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