From 1791d12455431ecfcdb79bcb3196a9e22dddfc61 Mon Sep 17 00:00:00 2001 From: Hemanth Veeramalla Date: Tue, 20 Dec 2022 14:35:55 +0530 Subject: [PATCH 1/2] jtag env and bench yaml with compilation done --- .../project_benches/jtag/.project | 37 + .../project_benches/jtag/.svproject | 16 + .../project_benches/jtag/docs/interfaces.csv | 14 + .../project_benches/jtag/jtag_sve.F | 27 + .../project_benches/jtag/rtl/dut.compile | 6 + .../jtag/rtl/verilog/verilog_dut.v | 21 + .../jtag/rtl/verilog/verilog_dut.vinfo | 1 + .../jtag/rtl/vhdl/vhdl_dut.vhd | 21 + .../project_benches/jtag/sim/Makefile | 198 ++ .../project_benches/jtag/sim/bcr_testlist | 19 + .../jtag/sim/bcr_testlist.yaml | 44 + .../project_benches/jtag/sim/cli_output.txt | 264 +++ .../project_benches/jtag/sim/compile.do | 70 + .../project_benches/jtag/sim/hdl.compile | 5 + .../project_benches/jtag/sim/hdl.vinfo | 1 + .../project_benches/jtag/sim/hvl.compile | 2 + .../project_benches/jtag/sim/hvl.vinfo | 1 + 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100755 UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/yaml2uvmf.py diff --git a/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/project_benches/jtag/.project b/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/project_benches/jtag/.project new file mode 100644 index 00000000..8669c089 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/project_benches/jtag/.project @@ -0,0 +1,37 @@ + + + jtag + + + + + + org.python.pydev.PyDevBuilder + + + + + net.sf.sveditor.core.SVProjectBuilder + + + + + + net.sf.sveditor.core.SVNature + org.python.pydev.pythonNature + + + + verification_ip + 2 + UVMF_VIP_LIBRARY_HOME + + + + + UVMF_VIP_LIBRARY_HOME + $%7BPARENT-2-PROJECT_LOC%7D/verification_ip + + + + diff --git a/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/project_benches/jtag/.svproject b/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/project_benches/jtag/.svproject new file mode 100644 index 00000000..d5250ea5 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/project_benches/jtag/.svproject @@ -0,0 +1,16 @@ + + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/project_benches/jtag/docs/interfaces.csv b/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/project_benches/jtag/docs/interfaces.csv new file mode 100644 index 00000000..f31b9cf5 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/project_benches/jtag/docs/interfaces.csv @@ -0,0 +1,14 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// + +, +Interface Description, Interface Type, Interface Transaction, Interface Name, +jtag_in, jtag_driver_bfm jtag_monitor_bfm, jtag_transaction, jtag_pkg_jtag_in_BFM, +jtag_out, jtag_driver_bfm jtag_monitor_bfm, jtag_transaction, jtag_pkg_jtag_out_BFM, + diff --git a/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/project_benches/jtag/jtag_sve.F b/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/project_benches/jtag/jtag_sve.F new file mode 100644 index 00000000..cd7aee30 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/project_benches/jtag/jtag_sve.F @@ -0,0 +1,27 @@ + +// UVM ++incdir+${UVM_HOME}/src +${UVM_HOME}/src/uvm_pkg.sv + +// Common UVMF files +-f ${UVMF_HOME}/common/common_sve.f + +// BFM Files +-F ${UVMF_VIP_LIBRARY_HOME}/interface_packages/jtag_pkg/jtag_pkg_sve.F + +// Environment Files +-F ${UVMF_VIP_LIBRARY_HOME}/environment_packages/jtag_env_pkg/jtag_env_pkg_sve.F + +// Bench Files ++incdir+./tb/tests +./tb/tests/jtag_tests_pkg.sv + ++incdir+./tb/sequences +./tb/sequences/jtag_sequences_pkg.sv + ++incdir+./tb/parameters +./tb/parameters/jtag_parameters_pkg.sv + +./tb/testbench/hdl_top.sv +./tb/testbench/hvl_top.sv + diff --git a/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/project_benches/jtag/rtl/dut.compile b/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/project_benches/jtag/rtl/dut.compile new file mode 100644 index 00000000..9b0008fc --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/project_benches/jtag/rtl/dut.compile @@ -0,0 +1,6 @@ + +# pragma uvmf custom dut_compile_info begin +src: + - ./vhdl/vhdl_dut.vhd + - ./verilog/verilog_dut.v +# pragma uvmf custom dut_compile_info end diff --git a/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/project_benches/jtag/rtl/verilog/verilog_dut.v b/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/project_benches/jtag/rtl/verilog/verilog_dut.v new file mode 100644 index 00000000..96198441 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/project_benches/jtag/rtl/verilog/verilog_dut.v @@ -0,0 +1,21 @@ +module verilog_dut(clk, rst, in_signal, out_signal); + +input clk; +input rst; +input in_signal; +output out_signal; + +reg out_signal_o; + +always @(posedge clk) begin + if (rst) begin + out_signal_o <= 0; + end + else begin + out_signal_o <= ~in_signal; + end + end + +assign out_signal = out_signal_o; + +endmodule diff --git a/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/project_benches/jtag/rtl/verilog/verilog_dut.vinfo b/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/project_benches/jtag/rtl/verilog/verilog_dut.vinfo new file mode 100644 index 00000000..87e95f36 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/project_benches/jtag/rtl/verilog/verilog_dut.vinfo @@ -0,0 +1 @@ +verilog_dut.v diff --git a/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/project_benches/jtag/rtl/vhdl/vhdl_dut.vhd b/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/project_benches/jtag/rtl/vhdl/vhdl_dut.vhd new file mode 100644 index 00000000..904aa37d --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/project_benches/jtag/rtl/vhdl/vhdl_dut.vhd @@ -0,0 +1,21 @@ +library ieee; +use ieee.std_logic_1164.all ; + +entity vhdl_dut is + port ( clk : in std_logic ; + rst : in std_logic ; + in_signal : in std_logic ; + out_signal :out std_logic + ); +end vhdl_dut; + +architecture rtl of vhdl_dut is + begin + P1: process + variable out_signal_o : std_logic; + begin + wait until clk'event and clk = '1'; + out_signal_o := in_signal; + out_signal <= out_signal_o; + end process; + end rtl; diff --git a/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/project_benches/jtag/sim/Makefile b/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/project_benches/jtag/sim/Makefile new file mode 100644 index 00000000..0a54d158 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/project_benches/jtag/sim/Makefile @@ -0,0 +1,198 @@ + +# +#---------------------------------------------------------------------- +# +# DESCRIPTION: This makefile includes the shared makefile and contains +# bench level make targets. +# +#---------------------------------------------------------------------- + + +# pragma uvmf custom additional begin +# pragma uvmf custom additional end + +# ********************************************************************************************* +# UVMF library directory: +# This variable points to the UVMF release where uvmf_base_pkg directory resides. +# This variable points to release code that is not user modified. +# This variable allows for UVMF release directories to reside independent of project related verification IP and project bench directories. +# This code below looks "upward" for directory starting with UVMF_* and returns first match for use with the release examples. +UVMF_HOME ?= ___PLEASE_SET_AN_ENVIRONMENT_VARIABLE_NAMED_UVMF_HOME_TO_POINT_TO_THE_UVMF_INSTALLATION___ + +# pragma uvmf custom exports begin +# +# Project(s) specific verification IP library: +# Directory where reusable verification packages for interfaces, environments, utilities, etc. reside. +# This variable allows for your verification IP to reside independent of project bench and UVMF release directories. +# For examples deployed with UVMF this will be $(UVMF_HOME)//verification_ip +export UVMF_VIP_LIBRARY_HOME ?= $(PWD)/../../../verification_ip +# +# Project specific bench: +# Directory where bench specific code is located. +# This variable allows for project_benches to reside independent of verification IP and UVMF release directories. +# For examples deployed with UVMF this will be $(UVMF_HOME)//project_benches/ +export UVMF_PROJECT_DIR ?= $(PWD)/.. +# +# +# pragma uvmf custom exports end +# ********************************************************************************************* + +## Check PATH for required vinfo scripts +PVAL := $(shell command -v make_filelist.py 2> /dev/null) +ifndef PVAL + MFLIST = $(UVMF_HOME)/scripts/make_filelist.py +else + MFLIST = make_filelist.py +endif + + +# Set test case specific Variables +TEST_NAME ?= test_top + +TEST_SEED ?= random +UVM_CLI_ARGS = + +# Usage of Veloce, etc. to be input by the user (subject to defaults) +USE_VELOCE ?= 0 + +# Usage of vinfo flow for generating file list +USE_VINFO ?= 0 + +# Usage of Veloce and Questa profilers +USE_VELOCE_PROFILER ?= 0 +USE_QUESTA_PROFILER ?= 0 + + +# Set project Variables +TEST_PLAN_NAME = jtag_TestPlan +REPORTING_DO_FILE = jtag_reports_script + + +# Include makefile that includes targets for UVM_VIP_Library packages +include $(UVMF_HOME)/scripts/Makefile + + + + +# Include all requisite interface package targets for this bench +include $(UVMF_VIP_LIBRARY_HOME)/interface_packages/jtag_pkg/Makefile + +# Include all requisite environment package targets for this bench +include $(UVMF_VIP_LIBRARY_HOME)/environment_packages/jtag_env_pkg/Makefile + + + +# Add to default compile/load/run arguments +VCOM_ARGS += + +# Note: vsim-3009 error can be eliminated by adding -timescale 1ps/1ps to VLOG_ARGS + +VLOG_ARGS += $(UVM_DISABLE_FILE_LINE_CMD) + +VELANALYZE_ARGS += +VELANALYZE_HVL_ARGS += + +BATCH_VOPT_ARGS += +DEBUG_VOPT_ARGS += +EXTRA_VOPT_TOPS += +COMMON_VSIM_ARGS += +COMMON_VSIM_ARGS += + + +BATCH_VSIM_ARGS += #-uvmcontrol=none +DEBUG_VSIM_ARGS += +EXTRA_VSIM_TOPS += + +# pragma uvmf custom additional_args begin +# pragma uvmf custom additional_args end + + +# Project bench package source +jtag_PARAMETERS_PKG ?=\ +$(UVMF_PROJECT_DIR)/tb/parameters/jtag_parameters_pkg.sv + + +jtag_SEQUENCES_PKG ?=\ +$(UVMF_PROJECT_DIR)/tb/sequences/jtag_sequences_pkg.sv + + +jtag_TEST_PKG ?=\ +$(UVMF_PROJECT_DIR)/tb/tests/jtag_tests_pkg.sv + +# pragma uvmf custom dut_files begin +# UVMF_CHANGE_ME : Reference Verilog DUT source. +jtag_VERILOG_DUT ?=\ +$(UVMF_PROJECT_DIR)/rtl/verilog/verilog_dut.v + +# UVMF_CHANGE_ME : Reference VHDL DUT source. +jtag_VHDL_DUT ?=\ +$(UVMF_PROJECT_DIR)/rtl/vhdl/vhdl_dut.vhd +# pragma uvmf custom dut_files end + + +# Project bench package targets +COMP_jtag_PARAMETERS_PKG_TGT_0 = q_comp_jtag_parameters_pkg +COMP_jtag_PARAMETERS_PKG_TGT_1 = v_comp_jtag_parameters_pkg +COMP_jtag_PARAMETERS_PKG_TGT = $(COMP_jtag_PARAMETERS_PKG_TGT_$(USE_VELOCE)) + +comp_jtag_parameters_pkg: $(COMP_jtag_PARAMETERS_PKG_TGT) + +q_comp_jtag_parameters_pkg: + $(HVL_COMP_CMD) +incdir+$(UVMF_PROJECT_DIR)/tb/parameters $(jtag_PARAMETERS_PKG) + +v_comp_jtag_parameters_pkg: q_comp_jtag_parameters_pkg + $(HDL_COMP_CMD) +incdir+$(UVMF_PROJECT_DIR)/tb/parameters $(jtag_PARAMETERS_PKG) + + +comp_jtag_sequence_pkg: + $(HVL_COMP_CMD) +incdir+$(UVMF_PROJECT_DIR)/tb/sequences $(jtag_SEQUENCES_PKG) + +comp_jtag_tests_pkg: + $(HVL_COMP_CMD) +incdir+$(UVMF_PROJECT_DIR)/tb/tests $(jtag_TEST_PKG) + +# pragma uvmf custom dut_compile_make_target begin +# UVMF_CHANGE_ME : Add make target to compile your verilog dut here +comp_jtag_verilog_dut: + echo "Compile your verilog DUT here" + $(HDL_COMP_CMD) $(jtag_VERILOG_DUT) + +# UVMF_CHANGE_ME : Add make target to compile your vhdl dut here +comp_jtag_vhdl_dut: + echo "Compile your vhdl DUT here" + $(HDL_COMP_CMD_VHDL) $(jtag_VHDL_DUT) + +# UVMF_CHANGE_ME : Add make target to compile your dut here +comp_jtag_dut: comp_jtag_vhdl_dut comp_jtag_verilog_dut +# pragma uvmf custom dut_compile_make_target end + + +BUILD_TGT_0 = make_build +BUILD_TGT_1 = vinfo_build +BUILD_TGT = $(BUILD_TGT_$(USE_VINFO)) + + +comp_hvl : comp_hvl_core + + +comp_hvl_core : \ + comp_jtag_pkg \ + comp_jtag_env_pkg \ + comp_jtag_parameters_pkg comp_jtag_sequence_pkg comp_jtag_tests_pkg + +comp_uvmf_core : comp_uvm_pkg comp_uvmf_base_pkg + +make_build: comp_jtag_dut comp_uvmf_core comp_hvl comp_test_bench + +hvl_build: q_comp_jtag_pkg comp_jtag_env_pkg comp_jtag_sequence_pkg comp_jtag_tests_pkg hvl_comp_testbench link optimize + + +vinfo_build: comp_jtag_vhdl_dut build_hdl_vinfo build_hvl_vinfo $(VINFO_TGT) + + $(HDL_COMP_CMD) -F hdl.vf + $(VEL_COMP) + +build: $(BUILD_TGT) + +# pragma uvmf custom additional_targets begin +# pragma uvmf custom additional_targets end + diff --git a/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/project_benches/jtag/sim/bcr_testlist b/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/project_benches/jtag/sim/bcr_testlist new file mode 100644 index 00000000..ee75aff8 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/project_benches/jtag/sim/bcr_testlist @@ -0,0 +1,19 @@ + + + +# Test list for use by RMDB file +# File syntax is +# TB_INFO { } { } +# TB ## All subsequent tests will run on this bench until a different "TB" line is seen +# TEST <1st_seed> ... +# If not enough seeds are provided then random seeds are used to pad +# If no repeat count is given, default is 1 +# pragma uvmf custom tb_info begin +TB_INFO jtag { } { } +# pragma uvmf custom tb_info end +TB jtag +# pragma uvmf custom regression_suite begin +TEST test_top 3 +# pragma uvmf custom regression_suite end + + diff --git a/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/project_benches/jtag/sim/bcr_testlist.yaml b/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/project_benches/jtag/sim/bcr_testlist.yaml new file mode 100644 index 00000000..660b9ebe --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/project_benches/jtag/sim/bcr_testlist.yaml @@ -0,0 +1,44 @@ + + + +# YAML test list for use by RMDB file +# File syntax is +# uvmf_testlist: +# testbenches: +# - name: +# extra_build_options: +# extra_run_options: +# - name: +# ... +# - name: +# tests: +# - name: +# uvm_testname: (defaults to test_name) +# testbench: (defaults to last tb name seen) +# repeat: (defaults to 1) +# seeds: [,,...,] (defaults to all random) +# extra_test_options: +# - name: +# ... +# - name: +# include: +# - (relative path reference is to the including YAML file) +# - +# ... +# - + +uvmf_testlist: + testbenches: +# pragma uvmf custom tb_info begin + - name: jtag + extra_build_options: "" + extra_run_options: "" +# pragma uvmf custom tb_info end + tests: + - testbench: jtag +# pragma uvmf custom regression_suite begin + - name: test_top + repeat: 3 +# pragma uvmf custom regression_suite end + + diff --git a/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/project_benches/jtag/sim/cli_output.txt b/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/project_benches/jtag/sim/cli_output.txt new file mode 100644 index 00000000..607d30f7 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/project_benches/jtag/sim/cli_output.txt @@ -0,0 +1,264 @@ +test -e work || vlib work +echo "Compile your vhdl DUT here" +Compile your vhdl DUT here +vcom /hwetools/work_area/frontend/hemanth_b7/github_dir/UVMF_ch2/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/project_benches/jtag/sim/../rtl/vhdl/vhdl_dut.vhd +Start time: 14:33:16 on Dec 20,2022 +vcom /hwetools/work_area/frontend/hemanth_b7/github_dir/UVMF_ch2/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/project_benches/jtag/sim/../rtl/vhdl/vhdl_dut.vhd +QuestaSim vcom 10.6c Compiler 2017.07 Jul 25 2017 +-- Loading package STANDARD +-- Loading package TEXTIO +-- Loading package std_logic_1164 +-- Compiling entity vhdl_dut +-- Compiling architecture rtl of vhdl_dut +End time: 14:33:17 on Dec 20,2022, Elapsed time: 0:00:01 +Errors: 0, Warnings: 0 +echo "Compile your verilog DUT here" +Compile your verilog DUT here +vlog -sv -suppress 2223 -suppress 2286 +define+UVM_REPORT_DISABLE_FILE_LINE +define+UVM_REPORT_DISABLE_FILE_LINE /hwetools/work_area/frontend/hemanth_b7/github_dir/UVMF_ch2/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/project_benches/jtag/sim/../rtl/verilog/verilog_dut.v +QuestaSim vlog 10.6c Compiler 2017.07 Jul 25 2017 +Start time: 14:33:17 on Dec 20,2022 +vlog -sv -suppress 2223 -suppress 2286 "+define+UVM_REPORT_DISABLE_FILE_LINE" "+define+UVM_REPORT_DISABLE_FILE_LINE" /hwetools/work_area/frontend/hemanth_b7/github_dir/UVMF_ch2/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/project_benches/jtag/sim/../rtl/verilog/verilog_dut.v +-- Compiling module verilog_dut + +Top level modules: + verilog_dut +End time: 14:33:17 on Dec 20,2022, Elapsed time: 0:00:00 +Errors: 0, Warnings: 0 +vlog -sv -suppress 2223 -suppress 2286 +define+UVM_REPORT_DISABLE_FILE_LINE +define+UVM_REPORT_DISABLE_FILE_LINE +incdir+/hwetools/work_area/frontend/hemanth_b7/github_dir/UVMF_ch2/UVM_Framework/UVMF_2022.3/uvmf_base_pkg -F /hwetools/work_area/frontend/hemanth_b7/github_dir/UVMF_ch2/UVM_Framework/UVMF_2022.3/uvmf_base_pkg/uvmf_base_pkg_filelist_hdl.f +QuestaSim vlog 10.6c Compiler 2017.07 Jul 25 2017 +Start time: 14:33:17 on Dec 20,2022 +vlog -sv -suppress 2223 -suppress 2286 "+define+UVM_REPORT_DISABLE_FILE_LINE" "+define+UVM_REPORT_DISABLE_FILE_LINE" "+incdir+/hwetools/work_area/frontend/hemanth_b7/github_dir/UVMF_ch2/UVM_Framework/UVMF_2022.3/uvmf_base_pkg" -F /hwetools/work_area/frontend/hemanth_b7/github_dir/UVMF_ch2/UVM_Framework/UVMF_2022.3/uvmf_base_pkg/uvmf_base_pkg_filelist_hdl.f +-- Compiling package uvmf_base_pkg_hdl + +Top level modules: + --none-- +End time: 14:33:17 on Dec 20,2022, Elapsed time: 0:00:00 +Errors: 0, Warnings: 0 +vlog -sv -suppress 2223 -suppress 2286 +define+UVM_REPORT_DISABLE_FILE_LINE +define+UVM_REPORT_DISABLE_FILE_LINE +incdir+/hwetools/work_area/frontend/hemanth_b7/github_dir/UVMF_ch2/UVM_Framework/UVMF_2022.3/uvmf_base_pkg -F /hwetools/work_area/frontend/hemanth_b7/github_dir/UVMF_ch2/UVM_Framework/UVMF_2022.3/uvmf_base_pkg/uvmf_base_pkg_filelist_hvl.f +QuestaSim vlog 10.6c Compiler 2017.07 Jul 25 2017 +Start time: 14:33:17 on Dec 20,2022 +vlog -sv -suppress 2223 -suppress 2286 "+define+UVM_REPORT_DISABLE_FILE_LINE" "+define+UVM_REPORT_DISABLE_FILE_LINE" "+incdir+/hwetools/work_area/frontend/hemanth_b7/github_dir/UVMF_ch2/UVM_Framework/UVMF_2022.3/uvmf_base_pkg" -F /hwetools/work_area/frontend/hemanth_b7/github_dir/UVMF_ch2/UVM_Framework/UVMF_2022.3/uvmf_base_pkg/uvmf_base_pkg_filelist_hvl.f +-- Compiling package uvmf_base_pkg +-- Importing package mtiUvm.uvm_pkg (uvm-1.1d Built-in) +-- Importing package uvmf_base_pkg_hdl + +Top level modules: + --none-- +End time: 14:33:17 on Dec 20,2022, Elapsed time: 0:00:00 +Errors: 0, Warnings: 0 +vlog -sv -suppress 2223 -suppress 2286 +define+UVM_REPORT_DISABLE_FILE_LINE +define+UVM_REPORT_DISABLE_FILE_LINE +incdir+/hwetools/work_area/frontend/hemanth_b7/github_dir/UVMF_ch2/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/verification_ip/interface_packages/jtag_pkg -F /hwetools/work_area/frontend/hemanth_b7/github_dir/UVMF_ch2/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/verification_ip/interface_packages/jtag_pkg/jtag_filelist_hdl.f +QuestaSim vlog 10.6c Compiler 2017.07 Jul 25 2017 +Start time: 14:33:17 on Dec 20,2022 +vlog -sv -suppress 2223 -suppress 2286 "+define+UVM_REPORT_DISABLE_FILE_LINE" "+define+UVM_REPORT_DISABLE_FILE_LINE" "+incdir+/hwetools/work_area/frontend/hemanth_b7/github_dir/UVMF_ch2/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/verification_ip/interface_packages/jtag_pkg" -F /hwetools/work_area/frontend/hemanth_b7/github_dir/UVMF_ch2/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/verification_ip/interface_packages/jtag_pkg/jtag_filelist_hdl.f +-- Compiling package jtag_pkg_hdl +-- Importing package uvmf_base_pkg_hdl + +Top level modules: + --none-- +End time: 14:33:17 on Dec 20,2022, Elapsed time: 0:00:00 +Errors: 0, Warnings: 0 +vlog -sv -suppress 2223 -suppress 2286 +define+UVM_REPORT_DISABLE_FILE_LINE +define+UVM_REPORT_DISABLE_FILE_LINE +incdir+/hwetools/work_area/frontend/hemanth_b7/github_dir/UVMF_ch2/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/verification_ip/interface_packages/jtag_pkg -F /hwetools/work_area/frontend/hemanth_b7/github_dir/UVMF_ch2/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/verification_ip/interface_packages/jtag_pkg/jtag_filelist_hvl.f +QuestaSim vlog 10.6c Compiler 2017.07 Jul 25 2017 +Start time: 14:33:17 on Dec 20,2022 +vlog -sv -suppress 2223 -suppress 2286 "+define+UVM_REPORT_DISABLE_FILE_LINE" "+define+UVM_REPORT_DISABLE_FILE_LINE" "+incdir+/hwetools/work_area/frontend/hemanth_b7/github_dir/UVMF_ch2/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/verification_ip/interface_packages/jtag_pkg" -F /hwetools/work_area/frontend/hemanth_b7/github_dir/UVMF_ch2/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/verification_ip/interface_packages/jtag_pkg/jtag_filelist_hvl.f +-- Compiling package jtag_pkg +-- Importing package mtiUvm.uvm_pkg (uvm-1.1d Built-in) +-- Importing package uvmf_base_pkg_hdl +-- Importing package uvmf_base_pkg +-- Importing package jtag_pkg_hdl + +Top level modules: + --none-- +End time: 14:33:18 on Dec 20,2022, Elapsed time: 0:00:01 +Errors: 0, Warnings: 0 +vlog -sv -suppress 2223 -suppress 2286 +define+UVM_REPORT_DISABLE_FILE_LINE +define+UVM_REPORT_DISABLE_FILE_LINE +incdir+/hwetools/work_area/frontend/hemanth_b7/github_dir/UVMF_ch2/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/verification_ip/interface_packages/jtag_pkg -F /hwetools/work_area/frontend/hemanth_b7/github_dir/UVMF_ch2/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/verification_ip/interface_packages/jtag_pkg/jtag_filelist_xrtl.f +QuestaSim vlog 10.6c Compiler 2017.07 Jul 25 2017 +Start time: 14:33:18 on Dec 20,2022 +vlog -sv -suppress 2223 -suppress 2286 "+define+UVM_REPORT_DISABLE_FILE_LINE" "+define+UVM_REPORT_DISABLE_FILE_LINE" "+incdir+/hwetools/work_area/frontend/hemanth_b7/github_dir/UVMF_ch2/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/verification_ip/interface_packages/jtag_pkg" -F /hwetools/work_area/frontend/hemanth_b7/github_dir/UVMF_ch2/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/verification_ip/interface_packages/jtag_pkg/jtag_filelist_xrtl.f +-- Compiling package jtag_if_sv_unit +-- Importing package uvmf_base_pkg_hdl +-- Importing package jtag_pkg_hdl +-- Compiling interface jtag_if +-- Compiling package jtag_monitor_bfm_sv_unit +-- Importing package uvmf_base_pkg_hdl +-- Importing package jtag_pkg_hdl +-- Compiling interface jtag_monitor_bfm +-- Importing package mtiUvm.uvm_pkg (uvm-1.1d Built-in) +-- Importing package jtag_pkg +-- Importing package uvmf_base_pkg +-- Compiling package jtag_driver_bfm_sv_unit +-- Importing package uvmf_base_pkg_hdl +-- Importing package jtag_pkg_hdl +-- Compiling interface jtag_driver_bfm +-- Importing package mtiUvm.uvm_pkg (uvm-1.1d Built-in) +-- Importing package jtag_pkg +-- Importing package uvmf_base_pkg + +Top level modules: + --none-- +End time: 14:33:19 on Dec 20,2022, Elapsed time: 0:00:01 +Errors: 0, Warnings: 0 +vlog -sv -suppress 2223 -suppress 2286 +define+UVM_REPORT_DISABLE_FILE_LINE +define+UVM_REPORT_DISABLE_FILE_LINE +incdir+/hwetools/work_area/frontend/hemanth_b7/github_dir/UVMF_ch2/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/verification_ip/environment_packages/jtag_env_pkg /hwetools/work_area/frontend/hemanth_b7/github_dir/UVMF_ch2/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/verification_ip/environment_packages/jtag_env_pkg/jtag_env_pkg.sv +QuestaSim vlog 10.6c Compiler 2017.07 Jul 25 2017 +Start time: 14:33:19 on Dec 20,2022 +vlog -sv -suppress 2223 -suppress 2286 "+define+UVM_REPORT_DISABLE_FILE_LINE" "+define+UVM_REPORT_DISABLE_FILE_LINE" "+incdir+/hwetools/work_area/frontend/hemanth_b7/github_dir/UVMF_ch2/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/verification_ip/environment_packages/jtag_env_pkg" /hwetools/work_area/frontend/hemanth_b7/github_dir/UVMF_ch2/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/verification_ip/environment_packages/jtag_env_pkg/jtag_env_pkg.sv +-- Compiling package jtag_env_pkg +-- Importing package mtiUvm.uvm_pkg (uvm-1.1d Built-in) +-- Importing package uvmf_base_pkg +-- Importing package uvmf_base_pkg_hdl +-- Importing package jtag_pkg +-- Importing package jtag_pkg_hdl + +Top level modules: + --none-- +End time: 14:33:20 on Dec 20,2022, Elapsed time: 0:00:01 +Errors: 0, Warnings: 0 +vlog -sv -suppress 2223 -suppress 2286 +define+UVM_REPORT_DISABLE_FILE_LINE +define+UVM_REPORT_DISABLE_FILE_LINE +incdir+/hwetools/work_area/frontend/hemanth_b7/github_dir/UVMF_ch2/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/project_benches/jtag/sim/../tb/parameters /hwetools/work_area/frontend/hemanth_b7/github_dir/UVMF_ch2/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/project_benches/jtag/sim/../tb/parameters/jtag_parameters_pkg.sv +QuestaSim vlog 10.6c Compiler 2017.07 Jul 25 2017 +Start time: 14:33:20 on Dec 20,2022 +vlog -sv -suppress 2223 -suppress 2286 "+define+UVM_REPORT_DISABLE_FILE_LINE" "+define+UVM_REPORT_DISABLE_FILE_LINE" "+incdir+/hwetools/work_area/frontend/hemanth_b7/github_dir/UVMF_ch2/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/project_benches/jtag/sim/../tb/parameters" /hwetools/work_area/frontend/hemanth_b7/github_dir/UVMF_ch2/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/project_benches/jtag/sim/../tb/parameters/jtag_parameters_pkg.sv +-- Compiling package jtag_parameters_pkg +-- Importing package uvmf_base_pkg_hdl + +Top level modules: + --none-- +End time: 14:33:20 on Dec 20,2022, Elapsed time: 0:00:00 +Errors: 0, Warnings: 0 +vlog -sv -suppress 2223 -suppress 2286 +define+UVM_REPORT_DISABLE_FILE_LINE +define+UVM_REPORT_DISABLE_FILE_LINE +incdir+/hwetools/work_area/frontend/hemanth_b7/github_dir/UVMF_ch2/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/project_benches/jtag/sim/../tb/sequences /hwetools/work_area/frontend/hemanth_b7/github_dir/UVMF_ch2/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/project_benches/jtag/sim/../tb/sequences/jtag_sequences_pkg.sv +QuestaSim vlog 10.6c Compiler 2017.07 Jul 25 2017 +Start time: 14:33:20 on Dec 20,2022 +vlog -sv -suppress 2223 -suppress 2286 "+define+UVM_REPORT_DISABLE_FILE_LINE" "+define+UVM_REPORT_DISABLE_FILE_LINE" "+incdir+/hwetools/work_area/frontend/hemanth_b7/github_dir/UVMF_ch2/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/project_benches/jtag/sim/../tb/sequences" /hwetools/work_area/frontend/hemanth_b7/github_dir/UVMF_ch2/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/project_benches/jtag/sim/../tb/sequences/jtag_sequences_pkg.sv +-- Compiling package jtag_sequences_pkg +-- Importing package mtiUvm.uvm_pkg (uvm-1.1d Built-in) +-- Importing package uvmf_base_pkg +-- Importing package uvmf_base_pkg_hdl +-- Importing package jtag_pkg +-- Importing package jtag_pkg_hdl +-- Importing package jtag_parameters_pkg +-- Importing package jtag_env_pkg + +Top level modules: + --none-- +End time: 14:33:21 on Dec 20,2022, Elapsed time: 0:00:01 +Errors: 0, Warnings: 0 +vlog -sv -suppress 2223 -suppress 2286 +define+UVM_REPORT_DISABLE_FILE_LINE +define+UVM_REPORT_DISABLE_FILE_LINE +incdir+/hwetools/work_area/frontend/hemanth_b7/github_dir/UVMF_ch2/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/project_benches/jtag/sim/../tb/tests /hwetools/work_area/frontend/hemanth_b7/github_dir/UVMF_ch2/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/project_benches/jtag/sim/../tb/tests/jtag_tests_pkg.sv +QuestaSim vlog 10.6c Compiler 2017.07 Jul 25 2017 +Start time: 14:33:21 on Dec 20,2022 +vlog -sv -suppress 2223 -suppress 2286 "+define+UVM_REPORT_DISABLE_FILE_LINE" "+define+UVM_REPORT_DISABLE_FILE_LINE" "+incdir+/hwetools/work_area/frontend/hemanth_b7/github_dir/UVMF_ch2/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/project_benches/jtag/sim/../tb/tests" /hwetools/work_area/frontend/hemanth_b7/github_dir/UVMF_ch2/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/project_benches/jtag/sim/../tb/tests/jtag_tests_pkg.sv +-- Compiling package jtag_tests_pkg +-- Importing package mtiUvm.uvm_pkg (uvm-1.1d Built-in) +-- Importing package uvmf_base_pkg +-- Importing package uvmf_base_pkg_hdl +-- Importing package jtag_parameters_pkg +-- Importing package jtag_env_pkg +-- Importing package jtag_pkg +-- Importing package jtag_pkg_hdl +-- Importing package jtag_sequences_pkg + +Top level modules: + --none-- +End time: 14:33:21 on Dec 20,2022, Elapsed time: 0:00:00 +Errors: 0, Warnings: 0 +vlog -sv -suppress 2223 -suppress 2286 +define+UVM_REPORT_DISABLE_FILE_LINE +define+UVM_REPORT_DISABLE_FILE_LINE +incdir+/questa_mvc_src/sv +incdir+/hwetools/work_area/frontend/hemanth_b7/github_dir/UVMF_ch2/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/project_benches/jtag/sim/../tb/testbench -F /hwetools/work_area/frontend/hemanth_b7/github_dir/UVMF_ch2/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/project_benches/jtag/sim/../tb/testbench/top_filelist_hvl.f +QuestaSim vlog 10.6c Compiler 2017.07 Jul 25 2017 +Start time: 14:33:21 on Dec 20,2022 +vlog -sv -suppress 2223 -suppress 2286 "+define+UVM_REPORT_DISABLE_FILE_LINE" "+define+UVM_REPORT_DISABLE_FILE_LINE" "+incdir+/questa_mvc_src/sv" "+incdir+/hwetools/work_area/frontend/hemanth_b7/github_dir/UVMF_ch2/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/project_benches/jtag/sim/../tb/testbench" -F /hwetools/work_area/frontend/hemanth_b7/github_dir/UVMF_ch2/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/project_benches/jtag/sim/../tb/testbench/top_filelist_hvl.f +-- Compiling module hvl_top +-- Importing package mtiUvm.uvm_pkg (uvm-1.1d Built-in) +-- Importing package jtag_tests_pkg +-- Importing package uvmf_base_pkg +-- Importing package uvmf_base_pkg_hdl +-- Importing package jtag_parameters_pkg +-- Importing package jtag_env_pkg +-- Importing package jtag_pkg +-- Importing package jtag_pkg_hdl +-- Importing package jtag_sequences_pkg + +Top level modules: + hvl_top +End time: 14:33:22 on Dec 20,2022, Elapsed time: 0:00:01 +Errors: 0, Warnings: 0 +vlog -sv -suppress 2223 -suppress 2286 +define+UVM_REPORT_DISABLE_FILE_LINE +define+UVM_REPORT_DISABLE_FILE_LINE +incdir+/hwetools/work_area/frontend/hemanth_b7/github_dir/UVMF_ch2/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/project_benches/jtag/sim/../tb/testbench -F /hwetools/work_area/frontend/hemanth_b7/github_dir/UVMF_ch2/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/project_benches/jtag/sim/../tb/testbench/top_filelist_hdl.f +QuestaSim vlog 10.6c Compiler 2017.07 Jul 25 2017 +Start time: 14:33:22 on Dec 20,2022 +vlog -sv -suppress 2223 -suppress 2286 "+define+UVM_REPORT_DISABLE_FILE_LINE" "+define+UVM_REPORT_DISABLE_FILE_LINE" "+incdir+/hwetools/work_area/frontend/hemanth_b7/github_dir/UVMF_ch2/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/project_benches/jtag/sim/../tb/testbench" -F /hwetools/work_area/frontend/hemanth_b7/github_dir/UVMF_ch2/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/project_benches/jtag/sim/../tb/testbench/top_filelist_hdl.f +-- Compiling module hdl_top +-- Importing package jtag_parameters_pkg +-- Importing package uvmf_base_pkg_hdl +-- Importing package mtiUvm.uvm_pkg (uvm-1.1d Built-in) + +Top level modules: + hdl_top +End time: 14:33:22 on Dec 20,2022, Elapsed time: 0:00:00 +Errors: 0, Warnings: 0 +vopt hvl_top hdl_top -o optimized_batch_top_tb +QuestaSim vopt 10.6c Compiler 2017.07 Jul 25 2017 +Start time: 14:33:22 on Dec 20,2022 +vopt hvl_top hdl_top -o optimized_batch_top_tb + +Top level modules: + hvl_top + hdl_top + +Analyzing design... +-- Loading module hvl_top +-- Importing package mtiUvm.uvm_pkg (uvm-1.1d Built-in) +-- Importing package jtag_tests_pkg +-- Importing package uvmf_base_pkg +-- Importing package uvmf_base_pkg_hdl +-- Importing package jtag_parameters_pkg +-- Importing package jtag_env_pkg +-- Importing package jtag_pkg +-- Importing package jtag_pkg_hdl +-- Importing package jtag_sequences_pkg +-- Loading module hdl_top +-- Loading interface jtag_if +-- Loading interface jtag_monitor_bfm +-- Loading interface jtag_driver_bfm +-- Loading module verilog_dut +-- Loading package STANDARD +-- Loading package TEXTIO +-- Loading package std_logic_1164 +-- Loading entity vhdl_dut +-- Loading architecture rtl of vhdl_dut +-- Loading package mtiUvm.questa_uvm_pkg +Incremental compilation check found no design-units have changed. +Optimized design name is optimized_batch_top_tb +End time: 14:33:23 on Dec 20,2022, Elapsed time: 0:00:01 +Errors: 0, Warnings: 0 +vopt +acc hvl_top hdl_top -o optimized_debug_top_tb +QuestaSim vopt 10.6c Compiler 2017.07 Jul 25 2017 +Start time: 14:33:23 on Dec 20,2022 +vopt "+acc" hvl_top hdl_top -o optimized_debug_top_tb + +Top level modules: + hvl_top + hdl_top + +Analyzing design... +-- Loading module hvl_top +-- Importing package mtiUvm.uvm_pkg (uvm-1.1d Built-in) +-- Importing package jtag_tests_pkg +-- Importing package uvmf_base_pkg +-- Importing package uvmf_base_pkg_hdl +-- Importing package jtag_parameters_pkg +-- Importing package jtag_env_pkg +-- Importing package jtag_pkg +-- Importing package jtag_pkg_hdl +-- Importing package jtag_sequences_pkg +-- Loading module hdl_top +-- Loading interface jtag_if +-- Loading interface jtag_monitor_bfm +-- Loading interface jtag_driver_bfm +-- Loading module verilog_dut +-- Loading package STANDARD +-- Loading package TEXTIO +-- Loading package std_logic_1164 +-- Loading entity vhdl_dut +-- Loading architecture rtl of vhdl_dut +-- Loading package mtiUvm.questa_uvm_pkg +Incremental compilation check found no design-units have changed. +Optimized design name is optimized_debug_top_tb +End time: 14:33:24 on Dec 20,2022, Elapsed time: 0:00:01 +Errors: 0, Warnings: 0 +vsim -c -sv_seed random +UVM_TESTNAME=test_top -permit_unmatched_virtual_intf +notimingchecks -suppress 8887 -solvefaildebug -solvefailtestcase -uvmcontrol=none -printsimstats -do " coverage save -onexit test_top.ucdb; set IterationLimit 140000; set NoQuitOnFinish 1; run -all; quit -f;" optimized_batch_top_tb diff --git a/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/project_benches/jtag/sim/compile.do b/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/project_benches/jtag/sim/compile.do new file mode 100644 index 00000000..6e5ee58a --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/project_benches/jtag/sim/compile.do @@ -0,0 +1,70 @@ + + +################################################################## +## ENVIRONMENT VARIABLES +################################################################## +quietly set ::env(UVMF_VIP_LIBRARY_HOME) ../../../verification_ip +quietly set ::env(UVMF_PROJECT_DIR) .. + +## Using VRM means that the build is occuring several more directories deeper underneath +## the sim directory, need to prepend some more '..' +if {[info exists ::env(VRM_BUILD)]} { + quietly set ::env(UVMF_VIP_LIBRARY_HOME) "../../../../../$::env(UVMF_VIP_LIBRARY_HOME)" + quietly set ::env(UVMF_PROJECT_DIR) "../../../../../$::env(UVMF_PROJECT_DIR)" +} +quietly set ::env(UVMF_VIP_LIBRARY_HOME) [file normalize $::env(UVMF_VIP_LIBRARY_HOME)] +quietly set ::env(UVMF_PROJECT_DIR) [file normalize $::env(UVMF_PROJECT_DIR)] +quietly echo "UVMF_VIP_LIBRARY_HOME = $::env(UVMF_VIP_LIBRARY_HOME)" +quietly echo "UVMF_PROJECT_DIR = $::env(UVMF_PROJECT_DIR)" + + +################################################################### +## HOUSEKEEPING : DELETE FILES THAT WILL BE REGENERATED +################################################################### +file delete -force *~ *.ucdb vsim.dbg *.vstf *.log work *.mem *.transcript.txt certe_dump.xml *.wlf covhtmlreport VRMDATA +file delete -force design.bin qwave.db dpiheader.h visualizer*.ses +file delete -force veloce.med veloce.wave veloce.map tbxbindings.h edsenv velrunopts.ini +file delete -force sv_connect.* + +################################################################### +## COMPILE DUT SOURCE CODE +################################################################### +vlib work +# pragma uvmf custom dut_compile_dofile_target begin +# UVMF_CHANGE_ME : Add commands to compile your dut here, replacing the default examples +vlog -sv -timescale 1ps/1ps -suppress 2223,2286 $env(UVMF_PROJECT_DIR)/rtl/verilog/verilog_dut.v +vcom $env(UVMF_PROJECT_DIR)/rtl/vhdl/vhdl_dut.vhd +# pragma uvmf custom dut_compile_dofile_target end + +################################################################### +## COMPILE UVMF BASE/COMMON SOURCE CODE +################################################################### +vlog -sv -timescale 1ps/1ps -suppress 2223 -suppress 2286 +incdir+$env(UVMF_HOME)/uvmf_base_pkg -F $env(UVMF_HOME)/uvmf_base_pkg/uvmf_base_pkg_filelist_hdl.f +vlog -sv -timescale 1ps/1ps -suppress 2223 -suppress 2286 +incdir+$env(UVMF_HOME)/uvmf_base_pkg -F $env(UVMF_HOME)/uvmf_base_pkg/uvmf_base_pkg_filelist_hvl.f + + +################################################################### +## UVMF INTERFACE COMPILATION +################################################################### +do $env(UVMF_VIP_LIBRARY_HOME)/interface_packages/jtag_pkg/compile.do + +################################################################### +## UVMF ENVIRONMENT COMPILATION +################################################################### +do $env(UVMF_VIP_LIBRARY_HOME)/environment_packages/jtag_env_pkg/compile.do + +################################################################### +## UVMF BENCHES COMPILATION +################################################################### +vlog -sv -timescale 1ps/1ps -suppress 2223 -suppress 2286 +incdir+$env(UVMF_PROJECT_DIR)/tb/parameters $env(UVMF_PROJECT_DIR)/tb/parameters/jtag_parameters_pkg.sv +vlog -sv -timescale 1ps/1ps -suppress 2223 -suppress 2286 +incdir+$env(UVMF_PROJECT_DIR)/tb/sequences $env(UVMF_PROJECT_DIR)/tb/sequences/jtag_sequences_pkg.sv +vlog -sv -timescale 1ps/1ps -suppress 2223 -suppress 2286 +incdir+$env(UVMF_PROJECT_DIR)/tb/tests $env(UVMF_PROJECT_DIR)/tb/tests/jtag_tests_pkg.sv + +vlog -sv -timescale 1ps/1ps -suppress 2223 -suppress 2286 +incdir+$env(UVMF_PROJECT_DIR)/tb/testbench -F $env(UVMF_PROJECT_DIR)/tb/testbench/top_filelist_hdl.f +vlog -sv -timescale 1ps/1ps -suppress 2223 -suppress 2286 +incdir+$env(UVMF_PROJECT_DIR)/tb/testbench -F $env(UVMF_PROJECT_DIR)/tb/testbench/top_filelist_hvl.f + +################################################################### +## OPTIMIZATION +################################################################### +vopt hvl_top hdl_top -o optimized_batch_top_tb +vopt +acc hvl_top hdl_top -o optimized_debug_top_tb diff --git a/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/project_benches/jtag/sim/hdl.compile b/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/project_benches/jtag/sim/hdl.compile new file mode 100644 index 00000000..8e7bd41a --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/project_benches/jtag/sim/hdl.compile @@ -0,0 +1,5 @@ +needs: +# pragma uvmf custom dut_compile_info begin + - ../rtl/dut.compile +# pragma uvmf custom dut_compile_info end + - ../tb/testbench/hdl_top.compile diff --git a/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/project_benches/jtag/sim/hdl.vinfo b/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/project_benches/jtag/sim/hdl.vinfo new file mode 100644 index 00000000..da27ec77 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/project_benches/jtag/sim/hdl.vinfo @@ -0,0 +1 @@ +@use $UVMF_PROJECT_DIR/tb/testbench/hdl_top.vinfo diff --git a/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/project_benches/jtag/sim/hvl.compile b/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/project_benches/jtag/sim/hvl.compile new file mode 100644 index 00000000..ce952549 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/project_benches/jtag/sim/hvl.compile @@ -0,0 +1,2 @@ +needs: + - ../tb/testbench/hvl_top.compile diff --git a/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/project_benches/jtag/sim/hvl.vinfo b/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/project_benches/jtag/sim/hvl.vinfo new file mode 100644 index 00000000..d22eff33 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/project_benches/jtag/sim/hvl.vinfo @@ -0,0 +1 @@ +@use $UVMF_PROJECT_DIR/tb/testbench/hvl_top.vinfo diff --git a/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/project_benches/jtag/sim/run.do b/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/project_benches/jtag/sim/run.do new file mode 100644 index 00000000..101ddc48 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/project_benches/jtag/sim/run.do @@ -0,0 +1,21 @@ + + +quietly set svLibs "" +quietly set extra_vsim_args "" + +################################################################### +## Check for additional vsim arguments passed using env var $UVMF_EXTRA_VSIM_ARGS +################################################################### +if {[info exists ::env(UVMF_EXTRA_VSIM_ARGS)]} { + echo "Adding more args to vsim command" + quietly set extra_vsim_args $::env(UVMF_EXTRA_VSIM_ARGS) +} + +################################################################## +## Launch Questa : generate vsim command line and execute +################################################################## +# pragma uvmf custom dut_run_dofile_target begin +# UVMF_CHANGE_ME : Change the UVM_TESTNAME plusarg to run a different test +quietly set cmd [format "vsim -i -sv_seed random +UVM_TESTNAME=test_top +UVM_VERBOSITY=UVM_HIGH -permit_unmatched_virtual_intf +notimingchecks -suppress 8887 %s %s -uvmcontrol=all -msgmode both -classdebug -assertdebug +uvm_set_config_int=*,enable_transaction_viewing,1 -do { set NoQuitOnFinish 1; onbreak {resume}; run 0; do wave.do; set PrefSource(OpenOnBreak) 0; radix hex showbase; } optimized_debug_top_tb" $svLibs $extra_vsim_args] +# pragma uvmf custom dut_run_dofile_target end +eval $cmd diff --git a/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/project_benches/jtag/sim/tbx.config b/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/project_benches/jtag/sim/tbx.config new file mode 100644 index 00000000..eec58168 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/project_benches/jtag/sim/tbx.config @@ -0,0 +1,10 @@ + + + + + +comp -questa +velsyn -D1S +rtlc -allow_4ST + + diff --git a/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/project_benches/jtag/sim/testlist b/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/project_benches/jtag/sim/testlist new file mode 100644 index 00000000..62d99e25 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/project_benches/jtag/sim/testlist @@ -0,0 +1,20 @@ + + + + +# Test list for use by RMDB file +# File syntax is +# TB_INFO { } { } +# TB ## All subsequent tests will run on this bench until a different "TB" line is seen +# TEST <1st_seed> ... +# If not enough seeds are provided then random seeds are used to pad +# If no repeat count is given, default is 1 +# pragma uvmf custom tb_info begin +TB_INFO jtag { UVMF_VIP_LIBRARY_HOME=../../../../../../../../verification_ip UVMF_PROJECT_DIR=../../../../../../../jtag } { } +# pragma uvmf custom tb_info end +TB jtag +# pragma uvmf custom regression_suite begin +TEST test_top 3 +# pragma uvmf custom regression_suite end + + diff --git a/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/project_benches/jtag/sim/testlist.yaml b/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/project_benches/jtag/sim/testlist.yaml new file mode 100644 index 00000000..ce061ee9 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/project_benches/jtag/sim/testlist.yaml @@ -0,0 +1,44 @@ + + + +# YAML test list for use by RMDB file +# File syntax is +# uvmf_testlist: +# testbenches: +# - name: +# extra_build_options: +# extra_run_options: +# - name: +# ... +# - name: +# tests: +# - name: +# uvm_testname: (defaults to test_name) +# testbench: (defaults to last tb name seen) +# repeat: (defaults to 1) +# seeds: [,,...,] (defaults to all random) +# extra_test_options: +# - name: +# ... +# - name: +# include: +# - (relative path reference is to the including YAML file) +# - +# ... +# - + +uvmf_testlist: + testbenches: +# pragma uvmf custom tb_info begin + - name: jtag + extra_build_options: "UVMF_VIP_LIBRARY_HOME=../../../../../../../../verification_ip UVMF_PROJECT_DIR=../../../../../../../jtag" + extra_run_options: "" +# pragma uvmf custom tb_info end + tests: + - testbench: jtag +# pragma uvmf custom regression_suite begin + - name: test_top + repeat: 3 +# pragma uvmf custom regression_suite end + + diff --git a/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/project_benches/jtag/sim/top.compile b/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/project_benches/jtag/sim/top.compile new file mode 100644 index 00000000..efd51c07 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/project_benches/jtag/sim/top.compile @@ -0,0 +1,3 @@ +needs: + - hvl.compile + - hdl.compile diff --git a/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/project_benches/jtag/sim/veloce.config b/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/project_benches/jtag/sim/veloce.config new file mode 100644 index 00000000..d0975155 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/project_benches/jtag/sim/veloce.config @@ -0,0 +1,26 @@ + + + + + +# pragma uvmf custom additional begin +comp -num_boards 1 +comp -hvl questa +# Please choose the correct emulator type code for +# comp -platform command or else velcomp will fail +# Available types are: +# - Veloce2 Quattro: D2 +# - Veloce2 Maximus: D2M +# - Veloce Strato TiL, Ti, and Mi: Strato +# - Veloce Strato M and Strato T: StratoM +# - comp -platform +comp -platform Strato + +rtlc -enable_tbx_pragma_checks +rtlc -allow_4ST +rtlc -allow_MDR +rtlc -compile_display +rtlc -xwave_siglist xwaves.sigs +# pragma uvmf custom additional end + + diff --git a/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/project_benches/jtag/sim/viswave.do b/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/project_benches/jtag/sim/viswave.do new file mode 100644 index 00000000..33f2de1c --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/project_benches/jtag/sim/viswave.do @@ -0,0 +1,22 @@ + + +onerror resume +wave tags F0 +wave update off + +wave spacer -backgroundcolor Salmon { jtag_in } +wave add uvm_test_top.environment.jtag_in.jtag_in_monitor.txn_stream -radix string -tag F0 +wave group jtag_in_bus +wave add -group jtag_in_bus hdl_top.jtag_in_bus.* -radix hexadecimal -tag F0 +wave group jtag_in_bus -collapse +wave insertion [expr [wave index insertpoint] +1] +wave spacer -backgroundcolor Salmon { jtag_out } +wave add uvm_test_top.environment.jtag_out.jtag_out_monitor.txn_stream -radix string -tag F0 +wave group jtag_out_bus +wave add -group jtag_out_bus hdl_top.jtag_out_bus.* -radix hexadecimal -tag F0 +wave group jtag_out_bus -collapse +wave insertion [expr [wave index insertpoint] +1] + +wave update on +WaveSetStreamView + diff --git a/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/project_benches/jtag/sim/wave.do b/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/project_benches/jtag/sim/wave.do new file mode 100644 index 00000000..11a4bd82 --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/project_benches/jtag/sim/wave.do @@ -0,0 +1,30 @@ + + +onerror {resume} +quietly WaveActivateNextPane {} 0 + +add wave -noupdate -divider jtag_in +add wave -noupdate /uvm_root/uvm_test_top/environment/jtag_in/jtag_in_monitor/txn_stream +add wave -noupdate -group jtag_in_bus /hdl_top/jtag_in_bus/* +add wave -noupdate -divider jtag_out +add wave -noupdate /uvm_root/uvm_test_top/environment/jtag_out/jtag_out_monitor/txn_stream +add wave -noupdate -group jtag_out_bus /hdl_top/jtag_out_bus/* + +TreeUpdate [SetDefaultTree] +quietly wave cursor active 0 +configure wave -namecolwidth 472 +configure wave -valuecolwidth 100 +configure wave -justifyvalue left +configure wave -signalnamewidth 0 +configure wave -snapdistance 10 +configure wave -datasetprefix 0 +configure wave -rowmargin 4 +configure wave -childrowmargin 2 +configure wave -gridoffset 0 +configure wave -gridperiod 1 +configure wave -griddelta 40 +configure wave -timeline 0 +configure wave -timelineunits ns +update +WaveRestoreZoom {27 ns} {168 ns} + diff --git a/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/project_benches/jtag/sim/work/_info b/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/project_benches/jtag/sim/work/_info new file mode 100644 index 00000000..16b26fbb --- /dev/null +++ b/UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/project_benches/jtag/sim/work/_info @@ -0,0 +1,680 @@ +m255 +K4 +z2 +13 +!s112 1.1 +!i10d 8192 +!i10e 25 +!i10f 100 +cModel Technology +Z0 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