| ABC_AREA |
Strategies for Yosys ABC synthesis: Area/Speed. Default ABC_SPEED. |
0 |
|
| ABC_CLOCK_PERIOD_IN_PS |
Clock period to be used by STA during synthesis. Default value read from constraint.sdc. |
|
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| ABC_DRIVER_CELL |
Default driver cell used during ABC synthesis. |
|
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| ABC_LOAD_IN_FF |
During synthesis set_load value used. |
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| ABSTRACT_SOURCE |
Which .odb file to use to create abstract |
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| ADDER_MAP_FILE |
List of adders treated as a black box by Yosys. |
|
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| ADDITIONAL_FILES |
Additional files to be added to make issue archive. |
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| ADDITIONAL_GDS |
Hardened macro GDS files listed here. |
|
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| ADDITIONAL_LEFS |
Hardened macro LEF view files listed here. The LEF information of the macros is immutable and used throughout all stages. Stored in the .odb file. |
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| ADDITIONAL_LIBS |
Hardened macro library files listed here. The library information is immutable and used throughout all stages. Not stored in the .odb file. |
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| BLOCKS |
Blocks used as hard macros in a hierarchical flow. Do note that you have to specify block-specific inputs file in the directory mentioned by Makefile. |
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| CAP_MARGIN |
Specifies a capacitance margin when fixing max capacitance violations. This option allows you to overfix. |
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| CDL_FILES |
Insert additional Circuit Description Language (.cdl) netlist files. |
|
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| CELL_PAD_IN_SITES_DETAIL_PLACEMENT |
Cell padding on both sides in site widths to ease routability in detail placement. |
0 |
|
| CELL_PAD_IN_SITES_GLOBAL_PLACEMENT |
Cell padding on both sides in site widths to ease routability during global placement. |
0 |
|
| CLKGATE_MAP_FILE |
List of cells for gating clock treated as a black box by Yosys. |
|
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| CORE_AREA |
The core area specified as a list of lower-left and upper-right corners in microns (X1 Y1 X2 Y2). |
|
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| CORE_ASPECT_RATIO |
The core aspect ratio (height / width). This value is ignored if CORE_UTILIZATION is undefined. |
|
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| CORE_MARGIN |
The margin between the core area and die area, specified in microns. Allowed values are either one value for all margins or a set of four values, one for each margin. The order of the four values are: {bottom top left right}. This variable is ignored if CORE_UTILIZATION is undefined. |
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| CORE_UTILIZATION |
The core utilization percentage (0-100). |
|
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| CORNER |
PVT corner library selection. Only available for ASAP7 and GF180 PDKs. |
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| CTS_ARGS |
Override clock_tree_synthesis arguments. |
|
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| CTS_BUF_DISTANCE |
Distance (in microns) between buffers. |
|
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| CTS_CLUSTER_DIAMETER |
Maximum diameter (in microns) of sink cluster. |
20 |
|
| CTS_CLUSTER_SIZE |
Maximum number of sinks per cluster. |
50 |
|
| CTS_SNAPSHOT |
Creates ODB/SDC files prior to clock net and setup/hold repair. |
|
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| DESIGN_NAME |
The name of the top-level module of the design. |
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| DESIGN_NICKNAME |
DESIGN_NICKNAME just changes the directory name that ORFS outputs to be DESIGN_NICKNAME instead of DESIGN_NAME in case DESIGN_NAME is unwieldy or conflicts with a different design. |
|
|
| DETAILED_METRICS |
If set, then calls report_metrics prior to repair operations in the CTS and global route stages |
0 |
|
| DETAILED_ROUTE_ARGS |
Add additional arguments for debugging purposes during detail route. |
|
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| DETAILED_ROUTE_END_ITERATION |
Maximum number of iterations. |
64 |
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| DFF_LIB_FILES |
Technology mapping liberty files for flip-flops. |
|
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| DIE_AREA |
The die area specified as a list of lower-left and upper-right corners in microns (X1 Y1 X2 Y2). |
|
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| DONT_USE_CELLS |
Dont use cells eases pin access in detailed routing. |
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| DONT_USE_LIBS |
Set liberty files as dont_use. |
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| DPO_MAX_DISPLACEMENT |
Specifies how far an instance can be moved when optimizing. |
5 1 |
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| ENABLE_DPO |
Enable detail placement with improve_placement feature. |
1 |
|
| EQUIVALENCE_CHECK |
Enable running equivalence checks to verify logical correctness of repair_timing. |
0 |
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| FASTROUTE_TCL |
Specifies a Tcl script with commands to run before FastRoute. |
|
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| FILL_CELLS |
Fill cells are used to fill empty sites. If not set or empty, fill cell insertion is skipped. |
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| FILL_CONFIG |
JSON rule file for metal fill during chip finishing. |
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| FLOORPLAN_DEF |
Use the DEF file to initialize floorplan. |
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| GDS_FILES |
Path to platform GDS files. |
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| GENERATE_ARTIFACTS_ON_FAILURE |
For instance Bazel needs artifacts (.odb and .rpt files) on a failure to allow the user to save hours on re-running the failed step locally, but when working with a Makefile flow, it is more natural to fail the step and leave the user to manually inspect the logs and artifacts directly via the file system. Set to 1 to change the behavior to generate artifacts upon failure to e.g. do a global route. The exit code will still be non-zero on all other failures that aren't covered by the "useful to inspect the artifacts on failure" use-case. Example: just like detailed routing, a global route that fails with congestion, is not a build failure(as in exit code non-zero), it is a successful(as in zero exit code) global route that produce reports detailing the problem. Detailed route will not proceed, if there is global routing congestion This allows build systems, such as bazel, to create artifacts for global and detailed route, even if the operation had problems, without having know about the semantics between global and detailed route. Considering that global and detailed route can run for a long time and use a lot of memory, this allows inspecting results on a laptop for a build that ran on a server. |
0 |
|
| GLOBAL_PLACEMENT_ARGS |
Use additional tuning parameters during global placement other than default args defined in global_place.tcl. |
|
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| GLOBAL_ROUTE_ARGS |
Replaces default arguments for global route. |
-congestion_iterations 30 -congestion_report_iter_step 5 -verbose |
|
| GND_NETS_VOLTAGES |
Used for IR Drop calculation. |
|
|
| GPL_ROUTABILITY_DRIVEN |
Specifies whether the placer should use routability driven placement. |
1 |
|
| GPL_TIMING_DRIVEN |
Specifies whether the placer should use timing driven placement. |
1 |
|
| GUI_TIMING |
Load timing information when opening GUI. For large designs, this can be quite time consuming. Useful to disable when investigating non-timing aspects like floorplan, placement, routing, etc. |
1 |
|
| HOLD_SLACK_MARGIN |
Specifies a time margin for the slack when fixing hold violations. This option allows you to overfix or underfix(negative value, terminate retiming before 0 or positive slack). Use min of HOLD_SLACK_MARGIN and 0(default hold slack margin) in floorplan. This avoids overrepair in floorplan for hold by default, but allows skipping hold repair using a negative HOLD_SLACK_MARGIN. Exiting timing repair early is useful in exploration where the .sdc has a fixed clock period at designs target clock period and where HOLD/SETUP_SLACK_MARGIN is used to avoid overrepair(extremely long running times) when exploring different parameter settings. |
0 |
|
| IO_CONSTRAINTS |
File path to the IO constraints .tcl file. |
|
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| IO_PLACER_H |
The metal layer on which to place the I/O pins horizontally (top and bottom of the die). |
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| IO_PLACER_V |
The metal layer on which to place the I/O pins vertically (sides of the die). |
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| IR_DROP_LAYER |
Default metal layer to report IR drop. |
|
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| KLAYOUT_TECH_FILE |
A mapping from LEF/DEF to GDS using the KLayout tool. |
|
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| LATCH_MAP_FILE |
List of latches treated as a black box by Yosys. |
|
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| LIB_FILES |
A Liberty file of the standard cell library with PVT characterization, input and output characteristics, timing and power definitions for each cell. |
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| MACRO_BLOCKAGE_HALO |
Blockage width overridden from default calculation. |
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| MACRO_EXTENSION |
Sets the number of GCells added to the blockages boundaries from macros. |
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| MACRO_HALO_X |
Set macro halo for x-direction. Only available for ASAP7 PDK. |
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| MACRO_HALO_Y |
Set macro halo for y-direction. Only available for ASAP7 PDK. |
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| MACRO_PLACEMENT |
Specifies the path of a file on how to place certain macros manually using read_macro_placement. |
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| MACRO_PLACEMENT_TCL |
Specifies the path of a TCL file on how to place certain macros manually. |
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| MACRO_PLACE_CHANNEL |
Horizontal/vertical channel width between macros (microns). Used by automatic macro placement. Imagine channel=10 and halo=5. Then macros must be 10 apart but standard cells must be 5 away from a macro. |
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| MACRO_PLACE_HALO |
Horizontal/vertical halo around macros (microns). Used by automatic macro placement. |
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| MACRO_WRAPPERS |
The wrapper file that replaces existing macros with their wrapped version. |
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| MAKE_TRACKS |
Tcl file that defines add routing tracks to a floorplan. |
|
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| MATCH_CELL_FOOTPRINT |
Enforce sizing operations to only swap cells that have the same layout boundary. |
0 |
|
| MAX_ROUTING_LAYER |
The highest metal layer name to be used in routing. |
|
|
| MAX_UNGROUP_SIZE |
For hierarchical synthesis, we ungroup modules of larger area than given by this variable. The default value is > 0 platform specific. |
|
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| MIN_BUF_CELL_AND_PORTS |
Used to insert a buffer cell to pass through wires. Used in synthesis. |
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| MIN_ROUTING_LAYER |
The lowest metal layer name to be used in routing. |
|
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| PDN_TCL |
File path which has a set of power grid policies used by pdn to be applied to the design, such as layers to use, stripe width and spacing to generate the actual metal straps. |
|
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| PLACE_DENSITY |
The desired placement density of cells. It reflects how spread the cells would be on the core area. 1.0 = closely dense. 0.0 = widely spread. |
|
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| PLACE_DENSITY_LB_ADDON |
Check the lower boundary of the PLACE_DENSITY and add PLACE_DENSITY_LB_ADDON if it exists. |
|
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| PLACE_PINS_ARGS |
Arguments to place_pins |
|
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| PLACE_SITE |
Placement site for core cells defined in the technology LEF file. |
|
|
| PLATFORM |
Specifies process design kit or technology node to be used. |
|
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| POST_CTS_TCL |
Specifies a Tcl script with commands to run after CTS is completed. |
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| PRESERVE_CELLS |
Mark modules to keep from getting removed in flattening. |
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| PROCESS |
Technology node or process in use. |
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| PWR_NETS_VOLTAGES |
Used for IR Drop calculation. |
|
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| RCX_RULES |
RC Extraction rules file path. |
|
|
| RECOVER_POWER |
Specifies how many percent of paths with positive slacks can be slowed for power savings [0-100]. |
0 |
|
| REMOVE_ABC_BUFFERS |
Remove abc buffers from the netlist. If timing repair in floorplanning is taking too long, use a SETUP_HOLD_MARGIN to terminate timing repair early instead of using REMOVE_ABC_BUFFERS or set SKIP_LAST_GAST=1. |
|
yes |
| REMOVE_CELLS_FOR_EQY |
String patterns directly passed to write_verilog -remove_cells <> for equivalence checks. |
|
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| REPAIR_PDN_VIA_LAYER |
Remove power grid vias which generate DRC violations after detailed routing. |
|
|
| REPORT_CLOCK_SKEW |
Report clock skew as part of reporting metrics, starting at CTS, before which there is no clock skew. This metric can be quite time-consuming, so it can be useful to disable. |
1 |
|
| RESYNTH_AREA_RECOVER |
Enable re-synthesis for area reclaim. |
0 |
|
| RESYNTH_TIMING_RECOVER |
Enable re-synthesis for timing optimization. |
0 |
|
| ROUTING_LAYER_ADJUSTMENT |
Default routing layer adjustment |
0.5 |
|
| RTLMP_AREA_WT |
Weight for the area of the current floorplan. |
0.1 |
|
| RTLMP_ARGS |
Overrides all other RTL macro placer arguments. |
|
|
| RTLMP_BOUNDARY_WT |
Weight for the boundary or how far the hard macro clusters are from boundaries. |
50.0 |
|
| RTLMP_DEAD_SPACE |
Specifies the target dead space percentage, which influences the utilization of a cluster. |
0.05 |
|
| RTLMP_FENCE_LX |
Defines the lower left X coordinate for the global fence bounding box in microns. |
0.0 |
|
| RTLMP_FENCE_LY |
Defines the lower left Y coordinate for the global fence bounding box in microns. |
0.0 |
|
| RTLMP_FENCE_UX |
Defines the upper right X coordinate for the global fence bounding box in microns. |
100000000.0 |
|
| RTLMP_FENCE_UY |
Defines the upper right Y coordinate for the global fence bounding box in microns. |
100000000.0 |
|
| RTLMP_MAX_INST |
Maximum number of standard cells in a cluster. If unset, rtl_macro_placer will calculate a value based on the design attributes. |
|
|
| RTLMP_MAX_LEVEL |
Maximum depth of the physical hierarchy tree. |
2 |
|
| RTLMP_MAX_MACRO |
Maximum number of macros in a cluster. If unset, rtl_macro_placer will calculate a value based on the design attributes. |
|
|
| RTLMP_MIN_AR |
Specifies the minimum aspect ratio (height/width). |
0.33 |
|
| RTLMP_MIN_INST |
Minimum number of standard cells in a cluster. If unset, rtl_macro_placer will calculate a value based on the design attributes. |
|
|
| RTLMP_MIN_MACRO |
Minimum number of macros in a cluster. If unset, rtl_macro_placer will calculate a value based on the design attributes. |
|
|
| RTLMP_NOTCH_WT |
Weight for the notch, or the existence of dead space that cannot be used for placement and routing. |
10.0 |
|
| RTLMP_OUTLINE_WT |
Weight for violating the fixed outline constraint, meaning that all clusters should be placed within the shape of their parent cluster. |
100.0 |
|
| RTLMP_RPT_DIR |
Path to the directory where reports are saved. |
|
|
| RTLMP_SIGNATURE_NET_THRESHOLD |
Minimum number of connections between two clusters to be identified as connected. |
50 |
|
| RTLMP_WIRELENGTH_WT |
Weight for half-perimiter wirelength. |
100.0 |
|
| SC_LEF |
Path to technology standard cell LEF file. |
|
|
| SDC_FILE |
The path to design constraint (SDC) file. |
|
|
| SDC_GUT |
Load design and remove all internal logic before doing synthesis. This is useful when creating a mock .lef abstract that has a smaller area than the amount of logic would allow. bazel-orfs uses this to mock SRAMs, for instance. |
|
|
| SEAL_GDS |
Seal macro to place around the design. |
|
|
| SETUP_SLACK_MARGIN |
Specifies a time margin for the slack when fixing setup violations. This option allows you to overfix or underfix(negative value, terminate retiming before 0 or positive slack). |
0 |
|
| SET_RC_TCL |
Metal & Via RC definition file path. |
|
|
| SKIP_CTS_REPAIR_TIMING |
Skipping CTS repair, which can take a long time, can be useful in architectural exploration or when getting CI up and running. |
|
|
| SKIP_GATE_CLONING |
Do not use gate cloning transform to fix timing violations (default: use gate cloning). |
|
|
| SKIP_INCREMENTAL_REPAIR |
Skip incremental repair in global route. |
0 |
|
| SKIP_LAST_GASP |
Do not use last gasp optimization to fix timing violations (default: use gate last gasp). |
|
|
| SKIP_PIN_SWAP |
Do not use pin swapping as a transform to fix timing violations (default: use pin swapping). |
|
|
| SKIP_REPORT_METRICS |
If set to 1, then metrics, report_metrics does nothing. Useful to speed up builds. |
|
|
| SLEW_MARGIN |
Specifies a slew margin when fixing max slew violations. This option allows you to overfix. |
|
|
| SYNTH_ARGS |
Optional synthesis variables for yosys. |
-flatten |
|
| SYNTH_GUT |
Load design and remove all internal logic before doing synthesis. This is useful when creating a mock .lef abstract that has a smaller area than the amount of logic would allow. bazel-orfs uses this to mock SRAMs, for instance. |
|
|
| SYNTH_HIERARCHICAL |
Enable to Synthesis hierarchically, otherwise considered flat synthesis. |
0 |
|
| TAPCELL_TCL |
Path to Endcap and Welltie cells file. |
|
|
| TAP_CELL_NAME |
Name of the cell to use in tap cell insertion. |
|
|
| TECH_LEF |
A technology LEF file of the PDK that includes all relevant information regarding metal layers, vias, and spacing requirements. |
|
|
| TIEHI_CELL_AND_PORT |
Tie high cells used in Yosys synthesis to replace a logical 1 in the Netlist. |
|
|
| TIELO_CELL_AND_PORT |
Tie low cells used in Yosys synthesis to replace a logical 0 in the Netlist. |
|
|
| TNS_END_PERCENT |
Default TNS_END_PERCENT value for post CTS timing repair. Try fixing all violating endpoints by default (reduce to 5% for runtime). Specifies how many percent of violating paths to fix [0-100]. Worst path will always be fixed. |
100 |
|
| USE_FILL |
Whether to perform metal density filling. |
0 |
|
| VERILOG_FILES |
The path to the design Verilog files or JSON files providing a description of modules (check yosys -h write_json for more details). |
|
|
| VERILOG_INCLUDE_DIRS |
Specifies the include directories for the Verilog input files. |
|
|
| VERILOG_TOP_PARAMS |
Apply toplevel params (if exist). |
|
|