PR #19 changed core1_rd_data from output reg to output wire. contr_rd_data was NOT converted (line 89 of global_mem_controller.sv). Asymmetry is undocumented. Either: (a) convert contr_rd_data to wire too (then it needs a stability regression test like MAST #22 added for core1), or (b) document the asymmetry rationale (e.g. 'contr_rd path needs registered output because the controller FSM samples it on a different clock domain'). Needs ADR or design-doc paragraph. Refs: MAST PR #19, PR #25. Authored by Agent R (Reviewer).
PR #19 changed core1_rd_data from output reg to output wire. contr_rd_data was NOT converted (line 89 of global_mem_controller.sv). Asymmetry is undocumented. Either: (a) convert contr_rd_data to wire too (then it needs a stability regression test like MAST #22 added for core1), or (b) document the asymmetry rationale (e.g. 'contr_rd path needs registered output because the controller FSM samples it on a different clock domain'). Needs ADR or design-doc paragraph. Refs: MAST PR #19, PR #25. Authored by Agent R (Reviewer).