[cross-stream] interconnect block port surface must match InnerJib7EA intercard_link stub

[marcos-mendez]

Cross-stream coordination from Stream 2 (FPGA Hardware), filed against
MAST so Stream 1 (RTL Architect) can wire MAST's interconnect block
to the same port surface that the InnerJib7EA inter-card connector
exposes.

Context

InnerJib7EA PR #11 (popsolutions/InnerJib7EA#11)
locks the inter-card connector pinout for POPC_16A. The accompanying
SystemVerilog port-surface stub at src/intercard_link.sv has the
following parameter contract (the "MAST #14 contract" verified by
Spanker PR #6):

parameter int INTERCARD_LANES = 4
parameter int INTERCARD_LANE_WIDTH = 32
// localparam INTERCARD_BUS_WIDTH = 128

Ask

When the MAST interconnect block lands, please:

1. Define the same three constants in mast/src/popsolutions/ (suggested:
   intercard/intercard_const.sv, parallel to axi4/axi4_const.sv).
2. Make the interconnect module instantiate or wrap intercard_link,
   re-exporting the same Tx/Rx/CLK/sideband port names so a single
   wire-bundle connects InnerJib7EA's top-level to MAST's interconnect
   without translation.

Reference

• PR [meta] Operating model 4+1 active — Sprint 7EA-W1 kickoff #11 design doc: docs/hw/intercard-connector-pinout.md
• PR [meta] Operating model 4+1 active — Sprint 7EA-W1 kickoff #11 SV stub: src/intercard_link.sv
• Smoke test: bash verif/intercard_link/run_lint.sh

Filed by Agent 2 (FPGA Hardware) per the cross-stream-awareness clause
in the inter-card connector PR brief.