[arch] Amend ADR-001 — DDR3 bandwidth claim 12.8 GB/s is theoretical, real is 1.5-2.4 GB/s on ECP5+open toolchain

[marcos-mendez]

Context

Agent 4's LiteDRAM ECP5 recon (Stays PR #26, 2026-05-06) found ADR-001's claim "DDR3-1600 = 12.8 GB/s" is theoretical and not achievable on the ECP5+open-toolchain stack rev-A targets:

• Theoretical ceiling: 1600 MT/s × 64 bits = 12.8 GB/s
• ecp5ddrphy.py upstream cap: 800 MT/s = 6.4 GB/s on x64 (¼ of the ADR claim already at the PHY)
• Production-reference reality: OrangeCrab/Trellis/Versa-ECP5 run 192-300 MT/s = 1.5-2.4 GB/s (¼-½ of the PHY cap, ⅛-⅙ of the ADR claim)
• Open-toolchain ceiling: the higher rates require Lattice Diamond's closed PHY tooling, which is outside the project's open-FPGA mission per project_mission_and_open_fpga_commitment.md

This is not a bug — it's a recon finding that surfaces during day-1, before silicon comes back.

Action

Amend ADR-001 §DDR3 with:

• Theoretical vs. realistic vs. open-toolchain achievable bandwidth (three numbers, three contexts)
• Cite the production references (OrangeCrab et al.) as the realistic ceiling for rev-A
• Note that going above ~2.4 GB/s would require non-open-toolchain steps and explicit rejection of that path
• Cross-reference the LiteDRAM ECP5 recon doc (Stays/docs/upstream-contributions/2026-05-06-litedram-ecp5.md)

Downstream effects

• Stream 3 (Spanker): scheduler bandwidth model needs the corrected number — separate cross-stream issue filed against Spanker
• Strategic: revisit any project pitch / investor material that quotes 12.8 GB/s as if it were achievable

Acceptance

• ADR-001 amendment PR opened by Stream 1 (with R + human approval per the ADR governance)
• All public docs that quote the 12.8 number are corrected or annotated
• The new realistic-ceiling number lands in project_* memory if it shapes future agent decisions

Refs

• Stays PR chore(rtl): re-apply dead contr_rd_addr_q removal lost in PR #19 squash #26 (2026-05-06): LiteDRAM ECP5 recon §Bandwidth budget reality-check
• project_mission_and_open_fpga_commitment.md (open ecosystem trumps premium specs)

Authored by Agent R (Reviewer), surfaced by Agent 4 recon.

[marcos-mendez]

ADR-001 amendment proposed in popsolutions/Stays#28 — bandwidth claim split into three labeled numbers (theoretical 12.8 GB/s / open-PHY cap 6.4 GB/s / realistic rev-A 1.5-2.4 GB/s), with the closed-PHY path explicitly rejected per the open-FPGA mission. Sits as review-pending until Agent R reviews and Marcos signs off (per ADR-amendment governance).

Cross-stream filing for the Spanker scheduler-constant retuning will be tracked at popsolutions/Spanker#14.

PR URL: popsolutions/Stays#28
Authored by Agent 1 (RTL Architect).