diff --git a/.github/workflows/ci.yml b/.github/workflows/ci.yml
index 44caa63..6d56646 100644
--- a/.github/workflows/ci.yml
+++ b/.github/workflows/ci.yml
@@ -89,3 +89,71 @@ jobs:
               fi
             done
           } >> $GITHUB_STEP_SUMMARY
+
+  yosys-ecp5-smoke:
+    name: yosys synth_ecp5 smoke (closes #36)
+    runs-on: ubuntu-24.04
+    steps:
+      - name: Checkout
+        uses: actions/checkout@v4
+
+      - name: Cache OSS CAD Suite
+        id: oss-cad-cache
+        uses: actions/cache@v4
+        with:
+          path: ~/.local/oss-cad-suite
+          key: oss-cad-suite-2026-05-06-${{ runner.os }}-x64
+
+      - name: Download OSS CAD Suite (only on cache miss)
+        if: steps.oss-cad-cache.outputs.cache-hit != 'true'
+        run: |
+          mkdir -p ~/.local
+          wget -q https://github.com/YosysHQ/oss-cad-suite-build/releases/download/2026-05-06/oss-cad-suite-linux-x64-20260506.tgz \
+            -O /tmp/oss-cad-suite.tgz
+          tar -xzf /tmp/oss-cad-suite.tgz -C ~/.local
+          rm /tmp/oss-cad-suite.tgz
+
+      - name: Add OSS CAD Suite to PATH and verify yosys version
+        run: |
+          echo "$HOME/.local/oss-cad-suite/bin" >> $GITHUB_PATH
+          $HOME/.local/oss-cad-suite/bin/yosys -V
+
+      - name: Run synth_ecp5 smoke pass on src/generated/dadda_32bit32.sv
+        run: |
+          # Smoke-tests the open ECP5 synth path against a rev-A RTL module.
+          #
+          # Target: src/generated/dadda_32bit32.sv — a 1420-line generated
+          # 32x32 → 32-bit Dadda multiplier. Properties that make it the
+          # right smoke target:
+          #   * Self-contained: no module instantiations, no task/function
+          #     calls into other files, no `include, no SV interfaces, no
+          #     packages.
+          #   * Does NOT reference the assert.sv macros, so the yosys
+          #     preprocessor does not walk into the unsupported `__FILE__` /
+          #     `__LINE__` builtins (cf. yosys#1075).
+          #   * Pure combinational logic exercises the LUT4 / carry-chain
+          #     (arith_map_ccu2c.v) primitive coverage on the ECP5 backend
+          #     — exactly the path rev-A's matrix engine will eventually
+          #     stress.
+          #
+          # If this passes, the yosys + lattice techlib half of the open
+          # ECP5 flow is live for rev-A. See cicd/Dockerfile and #36.
+          mkdir -p /tmp/smoke
+          yosys -p "read_verilog -sv src/generated/dadda_32bit32.sv; synth_lattice -family ecp5 -top dadda_32bit32; write_json /tmp/smoke/dadda_32bit32.json" \
+            | tee /tmp/smoke/yosys.log
+          test -s /tmp/smoke/dadda_32bit32.json
+          {
+            echo "## yosys ECP5 smoke result"
+            echo ""
+            echo "- yosys version: \`$(yosys -V | head -1)\`"
+            echo "- top module: \`dadda_32bit32\`"
+            echo "- json size: \`$(wc -c < /tmp/smoke/dadda_32bit32.json) bytes\`"
+          } >> $GITHUB_STEP_SUMMARY
+
+      - name: Upload smoke artefacts
+        if: always()
+        uses: actions/upload-artifact@v4
+        with:
+          name: yosys-ecp5-smoke
+          path: /tmp/smoke/
+          if-no-files-found: warn
diff --git a/cicd/Dockerfile b/cicd/Dockerfile
index 0861396..a3038c7 100644
--- a/cicd/Dockerfile
+++ b/cicd/Dockerfile
@@ -1,3 +1,4 @@
+# SPDX-License-Identifier: CC-BY-SA-4.0
 # this is used for cicd
 
 FROM ubuntu:20.04
@@ -74,13 +75,26 @@ RUN wget ftp://ftp.icarus.com/pub/eda/verilog//v11/verilog-11.0.tar.gz && \
 #     cd .. && \
 #     rm -Rf iverilog
 
-# yosys
-RUN wget https://github.com/YosysHQ/yosys/archive/refs/tags/yosys-0.15.tar.gz && \
-    tar -xf yosys-0.15.tar.gz && cd yosys-yosys-0.15 && \
-    make -j $(nproc) && \
-    make install && \
-    cd .. && \
-    rm -Rf yosys-yosys-0.15
+# yosys + nextpnr-ecp5 + prjtrellis (via OSS CAD Suite)
+#
+# Replaces the 2021-vintage `yosys-0.15.tar.gz` source build (closes #36).
+# OSS CAD Suite ships yosys + nextpnr + prjtrellis (and verilator, iverilog,
+# cocotb-ext) as one date-pinned tarball, which is what every production open-
+# FPGA ECP5 reference (OrangeCrab, Trellis Board, ULX3S, Versa-ECP5, ECPIX-5,
+# LiteX) actually uses. See docs/upstream-contributions/2026-05-06-yosys-ecp5.md
+# (Stays #33) for the day-1 recon that surfaced this upgrade.
+#
+# Pinned to the 2026-05-06 nightly. Bump the date when refreshing — keep the
+# pin so the image is reproducible. yosys version inside this build: v0.64
+# (released 2026-04-09).
+ARG OSS_CAD_SUITE_DATE=2026-05-06
+ARG OSS_CAD_SUITE_DATE_NODASH=20260506
+RUN wget -q "https://github.com/YosysHQ/oss-cad-suite-build/releases/download/${OSS_CAD_SUITE_DATE}/oss-cad-suite-linux-x64-${OSS_CAD_SUITE_DATE_NODASH}.tgz" -O /tmp/oss-cad-suite.tgz && \
+    mkdir -p /opt && \
+    tar -xzf /tmp/oss-cad-suite.tgz -C /opt && \
+    rm /tmp/oss-cad-suite.tgz && \
+    /opt/oss-cad-suite/bin/yosys -V
+ENV PATH="/opt/oss-cad-suite/bin:${PATH}"
 
 # verilator
 RUN git clone https://github.com/verilator/verilator && \