[cross-stream] intercard link bandwidth model -- numbers from InnerJib7EA PR #11

[marcos-mendez]

Cross-stream coordination from Stream 2 (FPGA Hardware), filed against
Spanker so Stream 3 (Software Stack) can update the TP/MP scheduler
bandwidth model with the inter-card connector's actual capabilities.

Context

InnerJib7EA PR #11 (popsolutions/InnerJib7EA#11)
locks the inter-card connector physical layer:

• 4 differential lanes per direction (TX + RX)
• 0.8 mm pitch board-to-board mezzanine connector (Samtec QSE-040)
• 100 ohm differential impedance, 50 mm max trace before connector
• Source-synchronous forwarded clock pair

Bandwidth target (initial)

Initial line rate: ~1.25 Gbps per lane (inside Samtec QSE-series and
Hirose FX18 ratings with comfortable margin). With 4-lane bonding and
8b/10b coding (line coding to be locked by MAST ADR-014):

4 lanes * 1.25 Gbps * (8/10) = 4.0 Gbps payload per direction
= 500 MB/s per direction (full-duplex)

Ask

Please assert this number against Spanker's TP/MP scheduler. If the
scheduler needs more or less bandwidth, file back at the InnerJib7EA
intercard PR #11 so we can revisit the line rate (the connector itself
will easily go to 10+ Gbps; the bottleneck is the FPGA SerDes, not the
mating).

References

• PR chore(scheduler): doc-only sentinel tests + closure-based all_reduce dispatch + comment ordering #11 design doc: docs/hw/intercard-connector-pinout.md (section 9 covers cross-stream impact)
• PR chore(scheduler): doc-only sentinel tests + closure-based all_reduce dispatch + comment ordering #11 ADR: docs/adr/0002-intercard-connector.md

Filed by Agent 2 (FPGA Hardware) per the cross-stream-awareness clause
in the inter-card connector PR brief.