stream-2: schematic capture — ECP5-85F + power tree + JTAG + USB-UART

[marcos-mendez]

Goal

Populate `kicad/innerjib7ea-rev-a/innerjib7ea.kicad_sch` with the core symbols for rev-A:

• Lattice ECP5-85F (LFE5UM5G-85F-8BG756I) symbol with all power, GPIO, DDR3, PCIe, JTAG pins.
• Power tree: 12 V input → 3.3 V (FPGA I/O), 1.8 V (DDR3 controller), 1.5 V (DDR3 main rail), 1.35 V (FPGA core LDO), 0.75 V (DDR3 VTT termination).
• JTAG header (Tigard-compatible 2x5 pinout).
• USB-UART bridge (FT232H or CP2102N — pick the one with the cleaner open-source toolchain story).

Prerequisites

• The KiCad project skeleton issue (above) merged.

Acceptance

• ERC clean (CI `kicad-erc-drc` green).
• Power-tree topology decisions captured in `docs/PCB_DESIGN.md` (rev A subsection).
• USB-UART bridge selection rationale in commit body or a small ADR (your call).
• DCO sign-off, CERN-OHL-S v2 on CAD files.

Authored by Agent 2 (FPGA Hardware).

[marcos-mendez]

Cross-stream spec update — DDR3L (1.35 V SSTL135), not standard DDR3 (1.5 V)

Heads up before this issue is picked up: the rev-A SO-DIMM voltage class is DDR3L (1.35 V, SSTL135), not standard DDR3 (1.5 V). This is locked by #27 and PR #29 (docs/hw/ddr3l-decision.md).

Concretely, the schematic-capture power tree this issue specifies needs to change from:

12 V input → 3.3 V (FPGA I/O), 1.8 V (DDR3 controller), 1.5 V (DDR3 main rail), 1.35 V (FPGA core LDO), 0.75 V (DDR3 VTT termination).

to:

12 V input → 3.3 V (FPGA I/O, non-DDR banks), 2.5 V (SGMII PHY VDDA), 1.8 V (DDR3L controller logic + FPGA aux), 1.35 V (DDR3L module VDD + ECP5 SSTL135 IO bank VCCIO), 1.35 V or chip-spec (FPGA VCCINT — datasheet check), 1.0 V (SGMII PHY VDDC), 0.675 V (DDR3L VTT termination = VDD/2).

The 1.5 V rail disappears entirely (DDR3L collapses the DDR3 module rail and the ECP5 SSTL135 IO bank VCCIO into a single 1.35 V supply). VTT becomes 0.675 V, not 0.75 V.

See docs/hw/ddr3l-decision.md (lands with PR #29) for the full rationale and reference DIMM SKU (Crucial CT4G3S160BM, 4 GB DDR3L-1600).

Authored by Agent 2 (FPGA Hardware).