stream-2: DDR3 SO-DIMM connector + routing-constraint annotation

[marcos-mendez]

Goal

Add the 204-pin DDR3 SO-DIMM connector to the schematic + capture the routing constraints (50 Ω single-ended, 100 Ω diff, byte-lane length-match groups ±5 mil, address-group ±10 mil per `docs/PCB_DESIGN.md`).

Prerequisites

• Schematic-capture issue merged.

Acceptance

• DDR3 SO-DIMM connector symbol present, all data/address/control/clock pins net-named with byte-lane prefix (DQ0–7 in DQS0 group, etc.) so layout grouping is automatic.
• Routing-constraint comment near the connector pointing to the relevant `docs/PCB_DESIGN.md` section.
• Termination network (VTT 0.75 V, parallel terminations on the address group) on the schematic.
• ERC clean.

Authored by Agent 2 (FPGA Hardware).

[marcos-mendez]

Cross-stream spec update — DDR3L (1.35 V SSTL135), not standard DDR3 (1.5 V)

Heads up before this issue is picked up: the rev-A SO-DIMM voltage class is DDR3L (1.35 V, SSTL135), not standard DDR3 (1.5 V). This is locked by #27 and PR #29 (docs/hw/ddr3l-decision.md).

Concrete impact on this issue:

• Connector mechanical envelope is unchanged — 204-pin SO-DIMM, Molex 78171 / TE 1473005 still apply. DDR3 and DDR3L use the same 204-pin connector.
• IO standard for the byte lanes: assign SSTL135_I (single-ended) and SSTL135D_I (differential, DQS / CK pairs) — SSTL15_* is not an option on the ECP5 IO bank used here. Same as the OrangeCrab and Lattice Versa-ECP5 reference targets in litex_boards.
• Termination network: parallel address-group terminations to 0.675 V (= VDD/2 on a 1.35 V module rail), not 0.75 V.
• Routing rules unchanged — 50 Ω SE / 100 Ω diff / ±5 mil byte-lane / ±10 mil address-group all still apply per docs/PCB_DESIGN.md.

Reference SKU: Crucial CT4G3S160BM (4 GB DDR3L-1600 SO-DIMM, 1.35 V); see docs/hw/ddr3l-decision.md for the full SKU candidate list and what not to substitute.

Authored by Agent 2 (FPGA Hardware).