stream-2: 8-layer stackup planning for DDR3 controlled impedance

[marcos-mendez]

Goal

Apply the 8-layer stackup from `docs/PCB_DESIGN.md` to `kicad/innerjib7ea-rev-a/innerjib7ea.kicad_pcb`:

1. Top signal (high-speed)
2. Ground plane
3. Inner signal 1
4. Power plane (3.3 V / 1.8 V split)
5. Power plane (1.5 V / 1.35 V split)
6. Inner signal 2
7. Ground plane
8. Bottom signal

Acceptance

• Stackup configured in KiCad PCB layer manager.
• Controlled-impedance settings configured (50 Ω SE, 100 Ω diff) for at least the DDR3 byte-lane groups and PCIe Gen2 differential pairs.
• DRC rules updated for these impedance/length-match constraints.
• DRC clean (no violations on an empty layout).

Authored by Agent 2 (FPGA Hardware).

[marcos-mendez]

Cross-stream spec update — DDR3L (1.35 V SSTL135), not standard DDR3 (1.5 V)

Heads up before this issue is picked up: the rev-A SO-DIMM voltage class is DDR3L (1.35 V, SSTL135), not standard DDR3 (1.5 V). This is locked by #27 and PR #29 (docs/hw/ddr3l-decision.md).

Concrete impact on this issue:

• The 8-layer stackup as enumerated in this issue body shows:

  4. Power plane (3.3 V / 1.8 V split)
  5. Power plane (1.5 V / 1.35 V split)

  Plane 5 needs updating: under DDR3L the 1.5 V half disappears. The corrected split (per the post-[cross-stream][hw] Verify rev-A SO-DIMM is DDR3L (1.35V SSTL135), not standard DDR3 (1.5V) #27 power tree in docs/PCB_DESIGN.md) is:

  4. Power plane (3.3 V / 2.5 V / 1.8 V split)
  5. Power plane (1.35 V DDR3L + VCCIO / 1.0 V split)

  The 1.35 V pour now feeds both the DDR3L module VDD and the ECP5 IO bank VCCIO (SSTL135) for the SO-DIMM byte lanes — single rail, single pour.

• Controlled-impedance settings (50 Ω SE / 100 Ω diff) are unchanged.

• DRC rules for the byte-lane / address-group length-match groups are unchanged.

See docs/hw/ddr3l-decision.md (lands with PR #29) for the full rationale.

Authored by Agent 2 (FPGA Hardware).