From c78286c33f81d20fe6769d3c90152e04bec575f8 Mon Sep 17 00:00:00 2001 From: "Marcos (Agent 2)" Date: Wed, 6 May 2026 12:03:11 -0300 Subject: [PATCH] fix(hw): VCCINT is 1.2V per ECP5-5G datasheet (closes #30) MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The rev-A power tree previously listed `1.35 V LDO — FPGA core (VCCINT)`. Per the Lattice **ECP5 and ECP5-5G Family Data Sheet FPGA-DS-02012-3.3 (2024)**, §3.2 *Recommended Operating Conditions* (Table 3.2, p. 51), our chosen part `LFE5UM5G-85F-8BG756I` (ECP5-5G family) requires: - VCC (VCCINT core) : 1.14 – 1.26 V (nom 1.20 V) - VCCAUX : 2.375 – 2.625 V (nom 2.5 V) - VCCIO : 1.14 – 3.465 V (per-bank) - VCCA (SerDes ana.): 1.164 – 1.236 V (nom 1.20 V) - VCCAUXA : 2.374 – 2.625 V (nom 2.5 V) - VCCHRX : 0.30 – 1.26 V - VCCHTX : 1.14 – 1.26 V (nom 1.20 V) The 1.35 V value was incorrect (1.09 V above the 1.26 V max of the recommended operating range — would have stressed the part outside spec). Issue #30 (filed by Agent R from Agent 2's review of #27) hypothesised 1.1 V, which is the value for the standard ECP5UM (non-5G) variant. Our chosen part is the 5-Gbps SerDes variant (`LFE5UM5G-...`), which the same datasheet table explicitly specifies at **1.2 V nominal**. Corrections in this PR: 1. Power tree: replace the `1.35 V LDO — FPGA core (VCCINT)` line with a `1.2 V step-down — FPGA core + SerDes (VCC, VCCA, VCCHTX)` entry citing Table 3.2 directly. 2. Power tree: explicit `2.5 V` rail for `VCCAUX` / `VCCAUXA`. The earlier draft's "1.8 V — FPGA aux bank" was wrong about the FPGA aux bank — VCCAUX is 2.5 V per datasheet. The 1.8 V rail remains as DDR3L controller-side logic auxiliary. 3. Layer stackup plane 5: add the 1.2 V VCCINT+SerDes pour alongside the existing 1.35 V DDR3L+VCCIO and 1.0 V splits. 4. LDO → step-down: 1.2 V from 12 V is more efficiently a buck regulator at the expected core current of an LFE5UM5G-85F. 5. Datasheet revision and table citation added to the power-tree subsection so future readers can verify. Out of scope (deferred to schematic capture, Stays #6): part selection for the regulators, decoupling network, and whether VCCINT and the SerDes 1.2 V rails share a single regulator or get independently filtered supplies. Authored by Agent 2 (FPGA Hardware). Closes #30 Refs #27, #29 Signed-off-by: Marcos (Agent 2) --- docs/PCB_DESIGN.md | 60 +++++++++++++++++++++++++++++++++------------- 1 file changed, 44 insertions(+), 16 deletions(-) diff --git a/docs/PCB_DESIGN.md b/docs/PCB_DESIGN.md index b2bdcd4..8a77e84 100644 --- a/docs/PCB_DESIGN.md +++ b/docs/PCB_DESIGN.md @@ -73,11 +73,14 @@ count; power planes re-split to fit the SGMII PHY rails): 2. Ground plane 3. Inner signal 1 4. Power plane (3.3 V / 2.5 V / 1.8 V split) -5. Power plane (1.35 V DDR3L+VCCIO / 1.0 V split — note: a single - 1.35 V rail now feeds both the DDR3L module VDD and the ECP5 IO - bank VCCIO (SSTL135). The earlier draft showed a separate - 1.5 V rail; that rail is removed because rev-A is DDR3L only. - See [`hw/ddr3l-decision.md`](hw/ddr3l-decision.md).) +5. Power plane (1.35 V DDR3L+VCCIO / 1.2 V VCCINT+SerDes / 1.0 V + split — a single 1.35 V rail feeds both the DDR3L module VDD + and the ECP5 IO bank VCCIO (SSTL135); the 1.2 V pour feeds + FPGA core (`VCC`) plus SerDes (`VCCA`, `VCCHTX`) per the + ECP5-5G datasheet (FPGA-DS-02012-3.3, Table 3.2). The earlier + draft showed a separate 1.5 V rail; that rail is removed + because rev-A is DDR3L only. See + [`hw/ddr3l-decision.md`](hw/ddr3l-decision.md).) 6. Inner signal 2 7. Ground plane 8. Bottom signal @@ -97,26 +100,51 @@ count; power planes re-split to fit the SGMII PHY rails): ### Power tree +Voltages below cite the **ECP5 and ECP5-5G Family Data Sheet +FPGA-DS-02012-3.3 (Lattice, 2024)**, §3.2 *Recommended Operating +Conditions* (Table 3.2, p. 51), for the ECP5-5G column — our +chosen part is `LFE5UM5G-85F-8BG756I` per +[ADR-001](adr/0001-fpga-target.md). + - 12 V input (ATX 4-pin or barrel jack) -- 3.3 V step-down — FPGA I/O bank rails (non-DDR banks) -- 2.5 V step-down — SGMII PHY analog supply (KSZ9031RNX VDDA_2V5) -- 1.8 V step-down — DDR3L controller logic, FPGA aux bank +- 3.3 V step-down — FPGA `VCCIO` for 3.3 V banks (non-DDR, non-PHY) +- **2.5 V step-down — FPGA `VCCAUX` *and* `VCCAUXA`** (datasheet + range 2.375–2.625 V, nominal 2.5 V; one rail can feed both per + Table 3.2 footnote 2 since they share voltage); also feeds the + SGMII PHY analog supply (KSZ9031RNX VDDA_2V5). +- 1.8 V step-down — DDR3L controller-side logic auxiliary + (general-purpose 1.8 V rail; **not** the FPGA aux bank — VCCAUX + is 2.5 V per datasheet Table 3.2). - **1.35 V step-down — DDR3L module VDD *and* ECP5 IO bank VCCIO (SSTL135) for the SO-DIMM byte lanes.** This single rail replaces the earlier draft's separate "1.5 V DDR3 main rail" entry. DDR3L consumes 1.35 V (`SSTL135`) for both the module VDD and the FPGA - IO bank that drives it. -- 1.35 V (or chip-spec VCCINT) LDO — FPGA core. Final VCCINT value - to be confirmed against the LFE5UM5G-85F-8BG756I datasheet during - schematic capture (Stays #6); whether VCCINT shares the DDR3L - 1.35 V rail or has a dedicated supply is a schematic-capture - decision, not a doc-only one. + IO bank that drives it. (1.35 V is a legal `VCCIO` per Table 3.2: + range 1.14–3.465 V.) +- **1.2 V step-down — FPGA core (`VCC` / VCCINT) *and* SerDes + power (`VCCA`, `VCCHTX`).** Datasheet ECP5-5G ranges: + `VCC` = 1.14–1.26 V (nom 1.20 V), `VCCA` = 1.164–1.236 V + (nom 1.20 V), `VCCHTX` = 1.14–1.26 V (nom 1.20 V). This + **replaces the earlier draft's incorrect 1.35 V LDO entry** — + 1.35 V is well above the 1.26 V max of the recommended + operating range for `VCC` on ECP5-5G and would have stressed + the part outside spec. Note the standard ECP5UM (non-5G) + variant uses 1.1 V (1.045–1.155 V) per the same table; we are + not using that variant. SerDes input buffer `VCCHRX` (range + 0.30–1.26 V) can share the same 1.2 V rail or be biased + separately per the *ECP5 and ECP5-5G SerDes/PCS Usage Guide* + (FPGA-TN-02206); routing decision deferred to schematic + capture. - 1.0 V step-down — SGMII PHY digital core (KSZ9031RNX VDDC_1V0) - 0.675 V LDO — DDR3L VTT termination (= VDD/2 of the 1.35 V module rail; was 0.75 V in the standard-DDR3 draft). -(Topology specifics — buck-converter part choices, bypass caps, -pour shapes — land in the schematic.) +(Topology specifics — buck-converter / LDO part choices, bypass +caps, pour shapes, and whether VCCINT and the SerDes 1.2 V rails +share a regulator or get separate filtered supplies — land in the +schematic. The earlier draft specified an LDO for the FPGA core; +1.2 V from 12 V is more efficiently a step-down regulator at the +expected core current of an LFE5UM5G-85F.) ### Bring-up checklist