From db2384c5b5c1b74bb9496508c0ace6f7ec7e757e Mon Sep 17 00:00:00 2001 From: yvantor Date: Thu, 30 Oct 2025 08:21:46 +0100 Subject: [PATCH] Make input clocks parametric on chosen configuration. --- hw/astral_wrap.sv | 42 ++++++++------------ hw/carfield.sv | 77 ++++++++++++++++++------------------- hw/carfield_pkg.sv | 41 ++++++++++++++++++-- target/sim/src/astral_tb.sv | 2 +- 4 files changed, 93 insertions(+), 69 deletions(-) diff --git a/hw/astral_wrap.sv b/hw/astral_wrap.sv index 5bc112460..aa99963e2 100644 --- a/hw/astral_wrap.sv +++ b/hw/astral_wrap.sv @@ -101,8 +101,6 @@ module astral_wrap // clock signals logic ref_clk; - // generated clocks - logic host_clk, periph_clk, alt_clk, rt_clk; // secure boot mode signal logic secure_boot; @@ -298,14 +296,6 @@ module astral_wrap // GPI0 22-31 remain unconnected assign gpio_in_s[31:22] = '0; - // soc2pad - // clocks - assign st_soc2pad_signals.periph.fll_host_clk_o = host_clk; - assign st_soc2pad_signals.periph.fll_periph_clk_o = periph_clk; - assign st_soc2pad_signals.periph.fll_alt_clk_o = alt_clk; - assign st_soc2pad_signals.periph.fll_rt_clk_o = rt_clk; - - // soc2pad // uart-- carfield itf // spi @@ -361,7 +351,6 @@ module astral_wrap ////////////////////// // Clock generation // ////////////////////// - logic[carfield_pkg::NumFll-1:0] clk_fll_out; logic[carfield_pkg::NumFll-1:0] clk_fll_e; logic[carfield_pkg::NumFll-1:0] fll_lock; @@ -372,29 +361,29 @@ module astral_wrap logic[carfield_pkg::NumFll-1:0] fll_scan_out; logic[carfield_pkg::NumFll-1:0] fll_scan_jtag_in; logic[carfield_pkg::NumFll-1:0] fll_scan_jtag_out; + logic[carfield_pkg::NumFll-1:0] domain_clk; // ref_clk assign ref_clk = st_pad2soc_signals.periph.ref_clk_i; // power on reset assign pwr_on_rst_n = st_pad2soc_signals.periph.pwr_on_rst_ni; - assign host_clk = clk_fll_out[0]; - assign periph_clk = clk_fll_out[1]; - assign alt_clk = clk_fll_out[2]; - assign secd_clk = clk_fll_out[3]; assign clk_fll_e = '{default: 1'b1}; clk_int_div_static #( .DIV_VALUE ( 100 ), .ENABLE_CLOCK_IN_RESET( 1'b1 ) ) i_rt_clk_div ( - .clk_i ( clk_fll_out[4] ), - .rst_ni ( pwr_on_rst_n ), - .en_i ( 1'b1 ), - .test_mode_en_i ( 1'b0 ), - .clk_o ( rt_clk ) + .clk_i ( clk_fll_out[carfield_pkg::RtClockIdx]), + .rst_ni ( pwr_on_rst_n ), + .en_i ( 1'b1 ), + .test_mode_en_i ( 1'b0 ), + .clk_o ( domain_clk[carfield_pkg::RtClockIdx] ) ); + for (genvar i = 1; i < carfield_pkg::NumFll; i++) + assign domain_clk[i] = clk_fll_out[i]; + assign fll_pwd = '{default: 1'b0}; assign fll_test_mode = '{default: 1'b0}; assign fll_scan_e = '{default: 1'b0}; @@ -477,6 +466,13 @@ module astral_wrap assign dummy_rsp.rdata = 'hCACABABE; `endif + // soc2pad + // clocks + assign st_soc2pad_signals.periph.fll_rt_clk_o = clk_fll_out[carfield_pkg::RtClockIdx]; + assign st_soc2pad_signals.periph.fll_host_clk_o = clk_fll_out[carfield_pkg::HostClockIdx]; + assign st_soc2pad_signals.periph.fll_alt_clk_o = clk_fll_out [carfield_pkg::CarfieldClockIdx.AltClockIdx]; + assign st_soc2pad_signals.periph.fll_periph_clk_o = clk_fll_out [carfield_pkg::CarfieldClockIdx.PeriphClockIdx]; + ////////////////// // Carfield SoC // ////////////////// @@ -488,11 +484,7 @@ module astral_wrap .reg_req_t ( carfield_reg_req_t ), .reg_rsp_t ( carfield_reg_rsp_t ) ) i_dut ( - .host_clk_i ( host_clk ), - .periph_clk_i ( periph_clk ), - .alt_clk_i ( alt_clk ), - .secd_clk_i ( secd_clk ), - .rt_clk_i ( rt_clk ), + .domain_clk_i ( domain_clk[carfield_pkg::NumFll-1:0] ), .pwr_on_rst_ni ( pwr_on_rst_n ), .test_mode_i ( '0 ), .boot_mode_i ( bootmode_host_s[1:0] ), diff --git a/hw/carfield.sv b/hw/carfield.sv index 92e81b014..ec8232f4b 100644 --- a/hw/carfield.sv +++ b/hw/carfield.sv @@ -37,16 +37,7 @@ module carfield localparam int unsigned SlinkNumChan = cheshire_pkg::SlinkNumChan, localparam int unsigned SlinkNumLanes = cheshire_pkg::SlinkNumLanes ) ( - // host clock - input logic host_clk_i, - // peripheral clock - input logic periph_clk_i, - // accelerator and island clock - input logic alt_clk_i, - // secure domain clock - input logic secd_clk_i, - // external reference clock for timers (CLINT, islands) - input logic rt_clk_i, + input logic [carfield_pkg::NumFll-1:0] domain_clk_i, input logic pwr_on_rst_ni, @@ -183,6 +174,8 @@ module carfield `CHESHIRE_TYPEDEF_ALL(carfield_, Cfg) // Clocking and reset strategy +logic rt_clk; +logic host_clk; logic periph_rst_n; logic safety_rst_n; logic security_rst_n; @@ -217,6 +210,10 @@ logic [4:0] car_wdt_intrs; logic car_can_intr; logic car_eth_rx_intr; +// Assign clocks to each domain +assign rt_clk = domain_clk_i[carfield_pkg::RtClockIdx]; +assign host_clk = domain_clk_i[carfield_pkg::HostClockIdx]; + // Carfield peripheral interrupts // Propagate edge-triggered interrupts between periph and host clock domains @@ -226,7 +223,7 @@ for (genvar i=0; i < CarfieldNumAdvTimerIntrs; i++) begin : gen_sync_adv_timer_i .clk_tx_i ( periph_clk ), .rstn_tx_i ( periph_pwr_on_rst_n ), .edge_i ( car_adv_timer_intrs[i] ), - .clk_rx_i ( host_clk_i ), + .clk_rx_i ( host_clk ), .rstn_rx_i ( host_pwr_on_rst_n ), .edge_o ( car_adv_timer_intrs_sync[i] ) ); @@ -237,7 +234,7 @@ for (genvar i=0; i < CarfieldNumAdvTimerEvents; i++) begin : gen_sync_adv_timer_ .clk_tx_i ( periph_clk ), .rstn_tx_i ( periph_pwr_on_rst_n ), .edge_i ( car_adv_timer_events[i] ), - .clk_rx_i ( host_clk_i ), + .clk_rx_i ( host_clk ), .rstn_rx_i ( host_pwr_on_rst_n ), .edge_o ( car_adv_timer_events_sync[i] ) ); @@ -248,7 +245,7 @@ edge_propagator i_sync_sys_timer_lo_intr ( .clk_tx_i ( periph_clk ), .rstn_tx_i ( periph_pwr_on_rst_n ), .edge_i ( car_sys_timer_lo_intr ), - .clk_rx_i ( host_clk_i ), + .clk_rx_i ( host_clk ), .rstn_rx_i ( host_pwr_on_rst_n ), .edge_o ( car_sys_timer_lo_intr_sync ) ); @@ -257,7 +254,7 @@ edge_propagator i_sync_sys_timer_hi_intr ( .clk_tx_i ( periph_clk ), .rstn_tx_i ( periph_pwr_on_rst_n ), .edge_i ( car_sys_timer_hi_intr ), - .clk_rx_i ( host_clk_i ), + .clk_rx_i ( host_clk ), .rstn_rx_i ( host_pwr_on_rst_n ), .edge_o ( car_sys_timer_hi_intr_sync ) ); @@ -492,7 +489,7 @@ end // hard reset is: // periph (periph_clk_i) and accelerators (alt_clk_i) // -// The host is statically always assigned to host_clk_i. +// The host is statically always assigned to host_clk. // // Furthermore we have six reset domains: // host (contained in host clock domain, POR only, no SW reset) @@ -541,12 +538,12 @@ for (genvar i = 0; i < NumDomains; i++) begin : gen_domain_clock_mux clk_mux_glitch_free #( .NUM_INPUTS(carfield_pkg::NumFll-1) ) i_clk_mux ( - .clks_i ( {secd_clk_i, periph_clk_i, alt_clk_i, host_clk_i} ), - .test_clk_i ( 1'b0 ), - .test_en_i ( 1'b0 ), - .async_rstn_i ( host_pwr_on_rst_n ), - .async_sel_i ( domain_clk_sel[i] ), - .clk_o ( domain_clk[i] ) + .clks_i ( domain_clk_i[carfield_pkg::NumFll-1:1] ), + .test_clk_i ( 1'b0 ), + .test_en_i ( 1'b0 ), + .async_rstn_i ( host_pwr_on_rst_n ), + .async_sel_i ( domain_clk_sel[i] ), + .clk_o ( domain_clk[i] ) ); // The register file does not support back pressure directly. I.e the hardware side cannot tell @@ -558,7 +555,7 @@ for (genvar i = 0; i < NumDomains; i++) begin : gen_domain_clock_mux lossy_valid_to_stream #( .T(domain_clk_div_value_t) ) i_decouple ( - .clk_i ( host_clk_i ), // Connected to host clock since the soc_ctr + .clk_i ( host_clk ), // Connected to host clock since the soc_ctr // regs are clocked with it .rst_ni ( host_pwr_on_rst_n ), // See above .valid_i ( domain_clk_div_changed[i] ), @@ -574,7 +571,7 @@ for (genvar i = 0; i < NumDomains; i++) begin : gen_domain_clock_mux .T(domain_clk_div_value_t) ) i_cdc ( .src_rst_ni ( host_pwr_on_rst_n ), - .src_clk_i ( host_clk_i ), + .src_clk_i ( host_clk ), .src_data_i ( domain_clk_div_value_decoupled[i] ), .src_valid_i ( domain_clk_div_decoupled_valid[i] ), .src_ready_o ( domain_clk_div_decoupled_ready[i] ), @@ -608,7 +605,7 @@ end // Reset generation for power-on reset for host domain. For the other domain we // get this from carfield_rstgen rstgen i_host_rstgen ( - .clk_i (host_clk_i), + .clk_i (host_clk), .rst_ni (pwr_on_rst_ni), .test_mode_i, .rst_no (host_pwr_on_rst_n), @@ -666,7 +663,7 @@ for (genvar i=0; i