From 33ecc11542d0c393057db305e7426c0a3f7cefe6 Mon Sep 17 00:00:00 2001 From: Flavien Solt Date: Fri, 8 May 2026 21:42:08 +0800 Subject: [PATCH 1/9] idma_rt_midend: track every arbiter handshake in the choice FIFO The RT midend funnels two request sources -- internal counter-driven events (nd_req_valid_int / nd_req_ready_int) and external bypass events (nd_req_valid_i / nd_req_ready_o) -- into one downstream port through stream_arbiter_bypass. Each outgoing request is tagged with a 1-bit `choice` (1 = ext, 0 = int) which is supposed to be pushed into i_stream_fifo so the response demux can route returning bursts back to the bypass user (choice=1) or discard them at int_valid (choice=0, internal RT events have no consumer). The current push/pop conditions only match the *external* side of the handshake: .valid_i ( nd_req_valid_i & nd_req_ready_o ) .ready_i ( burst_rsp_valid_o & burst_rsp_ready_i ) So an internal RT event passes through stream_arbiter_bypass and reaches the downstream port (nd_req_valid_o), but nothing is pushed into the FIFO. Likewise, when the corresponding response returns and the demux routes it to int_valid, the FIFO is not popped. The FIFO is therefore systematically out of sync with the response stream whenever ext and int events interleave: it contains only ext entries while burst_rsp_valid_i carries a mix. Replace the conditions with the arbiter-output and demux-input handshakes so every outgoing request pushes once and every incoming response pops once: .valid_i ( nd_req_valid_o & nd_req_ready_i ) .ready_i ( burst_rsp_valid_i & burst_rsp_ready_o ) Reproducer (Verilator 5.046, NumEvents=1, NumOutstanding=8): release reset, enable event 0 with event_counts=5, issue an ext bypass, wait for the internal counter to fire, issue a second ext bypass. Send three downstream burst responses tagged 1, 0, 1 (the expected source of each event in issue order). Without the fix, the demux delivers the int-tagged response to burst_rsp_o (corrupting the bypass user's response stream) and silently routes one of the ext-tagged responses to int_valid (lost). With the fix, all three responses arrive at their declared source. The existing testbench (tb_idma_rt_midend.sv) ties the bypass input off (nd_req_valid_i = 1'b0) and leaves burst_rsp_o / burst_rsp_valid_o unconnected, so the mixed-traffic interleaving and the demux output side are never exercised; the bug therefore did not surface in CI. --- src/midend/idma_rt_midend.sv | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/midend/idma_rt_midend.sv b/src/midend/idma_rt_midend.sv index 1ab81cc4..20197ec7 100644 --- a/src/midend/idma_rt_midend.sv +++ b/src/midend/idma_rt_midend.sv @@ -206,11 +206,11 @@ module idma_rt_midend #( .testmode_i ( 1'b0 ), .usage_o ( /* NC */ ), .data_i ( choice ), - .valid_i ( nd_req_valid_i & nd_req_ready_o ), + .valid_i ( nd_req_valid_o & nd_req_ready_i ), .ready_o ( /* HACK: NC */ ), .data_o ( choice_head ), .valid_o ( /* HACK: NC */ ), - .ready_i ( burst_rsp_valid_o & burst_rsp_ready_i ) + .ready_i ( burst_rsp_valid_i & burst_rsp_ready_o ) ); // arbitration of responses From 389d98a7b65063e5e286148794fbcd61b9771fce Mon Sep 17 00:00:00 2001 From: Daniel Keller Date: Sat, 16 May 2026 18:36:51 +0200 Subject: [PATCH 2/9] test: Drop redundant counter init from main initial block From de194023181f1ef5dc6e1119f9bf6ab5e063987c Mon Sep 17 00:00:00 2001 From: Daniel Keller Date: Sat, 16 May 2026 18:32:45 +0200 Subject: [PATCH 3/9] test: Drive rt_midend bypass non-trivially; add Make target tb_idma_rt_midend previously tied off the bypass nd_req input, hiding the choice-FIFO alignment bug (Flavien Solt, PR #96): on master the FIFO records only bypass handshakes while responses pop on any downstream completion, so internal-vs-bypass routing drifts as soon as both streams are active. Extending the smoke TB to drive bypass and count expected routing turns it into a real regression guard. Adds idma_sim_tb_idma_rt_midend Make target for repeatable invocation. --- idma.mk | 8 ++ test/midend/tb_idma_rt_midend.sv | 146 +++++++++++++++++++++++++++---- 2 files changed, 138 insertions(+), 16 deletions(-) diff --git a/idma.mk b/idma.mk index 06d6c4b8..95e8a2e8 100644 --- a/idma.mk +++ b/idma.mk @@ -16,6 +16,7 @@ SPHINXBUILD ?= sphinx-build VCS ?= vcs VERILATOR ?= verilator VLOGAN ?= vlogan +VSIM ?= vsim # Shell SHELL := /bin/bash @@ -308,6 +309,13 @@ endef $(IDMA_VSIM_DIR)/compile.tcl: $(IDMA_BENDER_FILES) $(IDMA_FULL_TB) $(IDMA_FULL_RTL) $(IDMA_INCLUDE_ALL) $(IDMA_WAVE_ALL) $(call idma_generate_vsim, $@, -t sim -t test -t idma_test -t synth -t rtl -t asic -t snitch_cluster,../../..) +.PHONY: idma_sim_tb_idma_rt_midend + +idma_sim_tb_idma_rt_midend: $(IDMA_VSIM_DIR)/compile.tcl + cd $(IDMA_VSIM_DIR); $(VSIM) -c -do "source compile.tcl; quit" + cd $(IDMA_VSIM_DIR); $(VSIM) -c -t 1ps -voptargs=+acc \ + tb_idma_rt_midend -do "run -all; quit" + idma_sim_clean: rm -rf $(IDMA_VSIM_DIR)/compile.tcl rm -rf $(IDMA_VSIM_DIR)/work diff --git a/test/midend/tb_idma_rt_midend.sv b/test/midend/tb_idma_rt_midend.sv index 463a27e2..ec4f62b8 100644 --- a/test/midend/tb_idma_rt_midend.sv +++ b/test/midend/tb_idma_rt_midend.sv @@ -4,17 +4,23 @@ // Authors: // - Thomas Benz +// - Daniel Keller `include "idma/typedef.svh" -/// Sanity testbench for the RT midend +/// Sanity testbench for the RT midend. +/// Drives both the counter-generated (internal) and bypass nd_req streams, +/// then checks that the number of responses routed to the bypass output +/// matches the number of bypass requests issued. A routing mismatch +/// (responses going to the wrong output) indicates a misalignment between +/// the choice FIFO and the arbiter, the bug fixed by Flavien Solt's patch. module tb_idma_rt_midend; logic clk; logic rst_n; localparam int unsigned NumEvents = 5; - localparam int unsigned NumDim = 3; + localparam int unsigned NumDim = 3; typedef logic [5:0] axi_id_t; typedef logic [31:0] tf_len_t; @@ -29,6 +35,29 @@ module tb_idma_rt_midend; tf_len_t [NumEvents-1:0] event_counts = '0; logic [NumEvents-1:0] event_ena = '0; + // Downstream side: drains nd_req_o and supplies burst_rsp. + idma_nd_req_t out_req; + logic out_req_valid; + logic out_req_ready; + + idma_rsp_t out_rsp; + logic out_rsp_valid; + logic out_rsp_ready; + + // Bypass side: driven by this TB. + idma_nd_req_t byp_req; + logic byp_req_valid; + logic byp_req_ready; + + idma_rsp_t byp_rsp; + logic byp_rsp_valid; + logic byp_rsp_ready; + + // Counters to detect routing mismatch. + int unsigned bypass_req_issued; + int unsigned bypass_rsp_seen; + int unsigned internal_rsp_seen; + clk_rst_gen #( .ClkPeriod ( 1ns ), .RstClkCycles ( 1 ) @@ -41,7 +70,7 @@ module tb_idma_rt_midend; idma_rt_midend #( .NumEvents ( NumEvents ), .EventCntWidth ( 32'd32 ), - .NumOutstanding ( 32'd2 ), + .NumOutstanding ( 32'd4 ), .addr_t ( axi_addr_t ), .idma_nd_req_t ( idma_nd_req_t ), .idma_rsp_t ( idma_rsp_t ) @@ -59,26 +88,111 @@ module tb_idma_rt_midend; .dst_2d_stride_i ( '0 ), .num_2d_reps_i ( '0 ), .event_ena_i ( event_ena ), - .event_counts_o (), - .nd_req_o (), - .nd_req_valid_o (), - .nd_req_ready_i ( 1'b1 ), - .burst_rsp_i ( '1 ), - .burst_rsp_valid_i ( 1'b1 ), - .burst_rsp_ready_o (), - .nd_req_i ( '1 ), - .nd_req_ready_o (), - .nd_req_valid_i ( 1'b0 ), - .burst_rsp_o ( ), - .burst_rsp_valid_o ( ), - .burst_rsp_ready_i ( 1'b1 ) + .event_counts_o ( ), + .nd_req_o ( out_req ), + .nd_req_valid_o ( out_req_valid ), + .nd_req_ready_i ( out_req_ready ), + .burst_rsp_i ( out_rsp ), + .burst_rsp_valid_i ( out_rsp_valid ), + .burst_rsp_ready_o ( out_rsp_ready ), + .nd_req_i ( byp_req ), + .nd_req_valid_i ( byp_req_valid ), + .nd_req_ready_o ( byp_req_ready ), + .burst_rsp_o ( byp_rsp ), + .burst_rsp_valid_o ( byp_rsp_valid ), + .burst_rsp_ready_i ( byp_rsp_ready ) ); + // Always accept the downstream request and acknowledge any response stream. + assign out_req_ready = 1'b1; + assign byp_rsp_ready = 1'b1; + + // Drive a "pretend" response one cycle after every accepted request. + // This keeps requests and responses in 1:1 order at the downstream side. + logic out_req_handshake; + assign out_req_handshake = out_req_valid & out_req_ready; + + always_ff @(posedge clk or negedge rst_n) begin + if (!rst_n) begin + out_rsp_valid <= 1'b0; + out_rsp <= '0; + end else begin + // If we already issued a response and it was not yet consumed, keep it. + if (out_rsp_valid && !out_rsp_ready) begin + out_rsp_valid <= 1'b1; + end else begin + out_rsp_valid <= out_req_handshake; + out_rsp <= '1; + end + end + end + + // -- Counters ------------------------------------------------------ + always_ff @(posedge clk or negedge rst_n) begin + if (!rst_n) begin + bypass_req_issued <= '0; + bypass_rsp_seen <= '0; + internal_rsp_seen <= '0; + end else begin + if (byp_req_valid && byp_req_ready) + bypass_req_issued <= bypass_req_issued + 1; + if (byp_rsp_valid && byp_rsp_ready) + bypass_rsp_seen <= bypass_rsp_seen + 1; + // Burst responses consumed by the demux but not routed to bypass + // are "internal" responses (consumed by the internal sink). + if (out_rsp_valid && out_rsp_ready && !byp_rsp_valid) + internal_rsp_seen <= internal_rsp_seen + 1; + end + end + + // -- Bypass stimulus ----------------------------------------------- + initial begin : drive_bypass + byp_req_valid = 1'b0; + byp_req = '0; + // Pre-load a request payload distinguishable from the counters'. + byp_req.burst_req.length = 32'h0000_1000; + byp_req.burst_req.src_addr = 32'hC000_0000; + byp_req.burst_req.dst_addr = 32'hD000_0000; + + wait (rst_n === 1'b1); + @(posedge clk); + + // Issue 8 bypass requests interleaved with the counter traffic. + for (int i = 0; i < 8; i++) begin + // Random spacing to interleave with internal arbitration. + repeat (3 + (i % 4)) @(posedge clk); + byp_req_valid = 1'b1; + byp_req.burst_req.length = 32'h0000_1000 + i; + @(posedge clk); + while (!byp_req_ready) @(posedge clk); + byp_req_valid = 1'b0; + end + end + + // -- Main stimulus ------------------------------------------------- initial begin + bypass_req_issued = '0; + bypass_rsp_seen = '0; + internal_rsp_seen = '0; + event_counts = {32'd17, 32'd300, 32'd800, 32'd1000, 32'd2000}; #10ns; event_ena = {1'd1, 1'd1, 1'd1, 1'd1, 1'd1}; #5000ns; + + // Drain any remaining outstanding bypass responses. + @(posedge clk); + // -- Final check: every bypass request must produce exactly one + // response on the bypass output. A routing mismatch + // would either lose bypass responses (they go to + // the internal sink) or duplicate them. + assert (bypass_rsp_seen == bypass_req_issued) else begin + $error("[tb_idma_rt_midend] routing mismatch: bypass_req_issued=%0d bypass_rsp_seen=%0d", + bypass_req_issued, bypass_rsp_seen); + end + + $display("[tb_idma_rt_midend] bypass requests: %0d, bypass responses: %0d, internal responses: %0d", + bypass_req_issued, bypass_rsp_seen, internal_rsp_seen); $finish(); end From de87a9cb2e5e53fc0ece86c4ba6a8604d5a7e7ad Mon Sep 17 00:00:00 2001 From: Daniel Keller Date: Thu, 21 May 2026 14:11:49 +0200 Subject: [PATCH 4/9] ci: Add Daniel Keller and Flavien Solt to allowed-authors --- .github/authors-cfg.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/.github/authors-cfg.yaml b/.github/authors-cfg.yaml index 3d0098d5..0d5d4f43 100644 --- a/.github/authors-cfg.yaml +++ b/.github/authors-cfg.yaml @@ -41,6 +41,7 @@ allowed-years: allowed-authors: Axel Vanoni: axvanoni@ethz.ch + Daniel Keller: dankeller@iis.ee.ethz.ch Michael Rogenmoser: michaero@iis.ee.ethz.ch Samuel Riedel: sriedel@iis.ee.ethz.ch Thomas Benz: tbenz@iis.ee.ethz.ch From fa042fbd45e769950f368dc9bf4f226c034ccfcc Mon Sep 17 00:00:00 2001 From: Daniel Keller Date: Thu, 21 May 2026 14:53:32 +0200 Subject: [PATCH 5/9] rt_midend: Add choice FIFO backpressure and tighten test drain --- src/midend/idma_rt_midend.sv | 11 +++++++---- test/midend/tb_idma_rt_midend.sv | 13 +++++++++---- 2 files changed, 16 insertions(+), 8 deletions(-) diff --git a/src/midend/idma_rt_midend.sv b/src/midend/idma_rt_midend.sv index 20197ec7..2d11e98b 100644 --- a/src/midend/idma_rt_midend.sv +++ b/src/midend/idma_rt_midend.sv @@ -111,6 +111,9 @@ module idma_rt_midend #( idma_rsp_t int_rsp; logic int_valid; + // choice-FIFO backpressure signal + logic choice_fifo_ready; + // generate the counters timing the events and assemble the transfers for (genvar c = 0; c < NumEvents; c++) begin : gen_counters // counter instance @@ -180,7 +183,7 @@ module idma_rt_midend #( .inp_ready_o ( { nd_req_ready_o, nd_req_ready_int } ), .oup_data_o ( out_req ), .oup_valid_o ( nd_req_valid_o ), - .oup_ready_i ( nd_req_ready_i ) + .oup_ready_i ( nd_req_ready_i & choice_fifo_ready ) ); // assemble arbiter inputs @@ -206,10 +209,10 @@ module idma_rt_midend #( .testmode_i ( 1'b0 ), .usage_o ( /* NC */ ), .data_i ( choice ), - .valid_i ( nd_req_valid_o & nd_req_ready_i ), - .ready_o ( /* HACK: NC */ ), + .valid_i ( nd_req_valid_o & nd_req_ready_i & choice_fifo_ready ), + .ready_o ( choice_fifo_ready ), .data_o ( choice_head ), - .valid_o ( /* HACK: NC */ ), + .valid_o ( /* NC */ ), .ready_i ( burst_rsp_valid_i & burst_rsp_ready_o ) ); diff --git a/test/midend/tb_idma_rt_midend.sv b/test/midend/tb_idma_rt_midend.sv index ec4f62b8..4b3c4db3 100644 --- a/test/midend/tb_idma_rt_midend.sv +++ b/test/midend/tb_idma_rt_midend.sv @@ -180,14 +180,19 @@ module tb_idma_rt_midend; event_ena = {1'd1, 1'd1, 1'd1, 1'd1, 1'd1}; #5000ns; - // Drain any remaining outstanding bypass responses. - @(posedge clk); + // Drain outstanding bypass responses with a bounded wait so lost + // routing doesn't masquerade as "responses haven't arrived yet". + for (int i = 0; i < 1000; i++) begin + if (bypass_rsp_seen >= bypass_req_issued) break; + @(posedge clk); + end + // -- Final check: every bypass request must produce exactly one // response on the bypass output. A routing mismatch // would either lose bypass responses (they go to // the internal sink) or duplicate them. - assert (bypass_rsp_seen == bypass_req_issued) else begin - $error("[tb_idma_rt_midend] routing mismatch: bypass_req_issued=%0d bypass_rsp_seen=%0d", + if (bypass_rsp_seen != bypass_req_issued) begin + $fatal(1, "[tb_idma_rt_midend] routing mismatch: bypass_req_issued=%0d bypass_rsp_seen=%0d", bypass_req_issued, bypass_rsp_seen); end From a26dc0843737e33a5224194b98fde6acd73192dc Mon Sep 17 00:00:00 2001 From: Daniel Keller Date: Wed, 10 Jun 2026 21:19:06 +0200 Subject: [PATCH 6/9] test: Drop redundant rt_midend counter init to fix multi-driver compile bypass_req_issued, bypass_rsp_seen and internal_rsp_seen are reset and incremented in the always_ff counter block. The main-stimulus initial block re-zeroed them, giving each a second driver (vlog-7061), which the CI compile gate flags as a suppressible error and fails on. The always_ff reset already covers initialization, so drop the initial assignments. --- test/midend/tb_idma_rt_midend.sv | 4 ---- 1 file changed, 4 deletions(-) diff --git a/test/midend/tb_idma_rt_midend.sv b/test/midend/tb_idma_rt_midend.sv index 4b3c4db3..e99b4a40 100644 --- a/test/midend/tb_idma_rt_midend.sv +++ b/test/midend/tb_idma_rt_midend.sv @@ -171,10 +171,6 @@ module tb_idma_rt_midend; // -- Main stimulus ------------------------------------------------- initial begin - bypass_req_issued = '0; - bypass_rsp_seen = '0; - internal_rsp_seen = '0; - event_counts = {32'd17, 32'd300, 32'd800, 32'd1000, 32'd2000}; #10ns; event_ena = {1'd1, 1'd1, 1'd1, 1'd1, 1'd1}; From 4a13eee4a272df772bb307b5857b448438385650 Mon Sep 17 00:00:00 2001 From: Daniel Keller Date: Wed, 10 Jun 2026 21:58:29 +0200 Subject: [PATCH 7/9] test: Trim verbose comments in rt_midend testbench --- test/midend/tb_idma_rt_midend.sv | 26 +++++++------------------- 1 file changed, 7 insertions(+), 19 deletions(-) diff --git a/test/midend/tb_idma_rt_midend.sv b/test/midend/tb_idma_rt_midend.sv index e99b4a40..a32f5fb3 100644 --- a/test/midend/tb_idma_rt_midend.sv +++ b/test/midend/tb_idma_rt_midend.sv @@ -8,12 +8,8 @@ `include "idma/typedef.svh" -/// Sanity testbench for the RT midend. -/// Drives both the counter-generated (internal) and bypass nd_req streams, -/// then checks that the number of responses routed to the bypass output -/// matches the number of bypass requests issued. A routing mismatch -/// (responses going to the wrong output) indicates a misalignment between -/// the choice FIFO and the arbiter, the bug fixed by Flavien Solt's patch. +/// Sanity testbench for the RT midend: checks bypass responses are routed +/// to the bypass output, not lost to the internal sink. module tb_idma_rt_midend; logic clk; @@ -107,8 +103,7 @@ module tb_idma_rt_midend; assign out_req_ready = 1'b1; assign byp_rsp_ready = 1'b1; - // Drive a "pretend" response one cycle after every accepted request. - // This keeps requests and responses in 1:1 order at the downstream side. + // Drive a response one cycle after every accepted request (1:1 order). logic out_req_handshake; assign out_req_handshake = out_req_valid & out_req_ready; @@ -117,7 +112,7 @@ module tb_idma_rt_midend; out_rsp_valid <= 1'b0; out_rsp <= '0; end else begin - // If we already issued a response and it was not yet consumed, keep it. + // Hold an unconsumed response. if (out_rsp_valid && !out_rsp_ready) begin out_rsp_valid <= 1'b1; end else begin @@ -138,8 +133,7 @@ module tb_idma_rt_midend; bypass_req_issued <= bypass_req_issued + 1; if (byp_rsp_valid && byp_rsp_ready) bypass_rsp_seen <= bypass_rsp_seen + 1; - // Burst responses consumed by the demux but not routed to bypass - // are "internal" responses (consumed by the internal sink). + // Responses not routed to bypass are internal. if (out_rsp_valid && out_rsp_ready && !byp_rsp_valid) internal_rsp_seen <= internal_rsp_seen + 1; end @@ -149,7 +143,6 @@ module tb_idma_rt_midend; initial begin : drive_bypass byp_req_valid = 1'b0; byp_req = '0; - // Pre-load a request payload distinguishable from the counters'. byp_req.burst_req.length = 32'h0000_1000; byp_req.burst_req.src_addr = 32'hC000_0000; byp_req.burst_req.dst_addr = 32'hD000_0000; @@ -159,7 +152,6 @@ module tb_idma_rt_midend; // Issue 8 bypass requests interleaved with the counter traffic. for (int i = 0; i < 8; i++) begin - // Random spacing to interleave with internal arbitration. repeat (3 + (i % 4)) @(posedge clk); byp_req_valid = 1'b1; byp_req.burst_req.length = 32'h0000_1000 + i; @@ -176,17 +168,13 @@ module tb_idma_rt_midend; event_ena = {1'd1, 1'd1, 1'd1, 1'd1, 1'd1}; #5000ns; - // Drain outstanding bypass responses with a bounded wait so lost - // routing doesn't masquerade as "responses haven't arrived yet". + // Bounded drain for outstanding bypass responses. for (int i = 0; i < 1000; i++) begin if (bypass_rsp_seen >= bypass_req_issued) break; @(posedge clk); end - // -- Final check: every bypass request must produce exactly one - // response on the bypass output. A routing mismatch - // would either lose bypass responses (they go to - // the internal sink) or duplicate them. + // Every bypass request must produce exactly one bypass response. if (bypass_rsp_seen != bypass_req_issued) begin $fatal(1, "[tb_idma_rt_midend] routing mismatch: bypass_req_issued=%0d bypass_rsp_seen=%0d", bypass_req_issued, bypass_rsp_seen); From 5bf734338ca6bb0c0511d98a4cde3c9ac9605ae0 Mon Sep 17 00:00:00 2001 From: Daniel Keller Date: Wed, 10 Jun 2026 21:58:51 +0200 Subject: [PATCH 8/9] test: Wrap rt_midend tb lines to satisfy verible line-length --- test/midend/tb_idma_rt_midend.sv | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/test/midend/tb_idma_rt_midend.sv b/test/midend/tb_idma_rt_midend.sv index a32f5fb3..3b11c1da 100644 --- a/test/midend/tb_idma_rt_midend.sv +++ b/test/midend/tb_idma_rt_midend.sv @@ -176,11 +176,11 @@ module tb_idma_rt_midend; // Every bypass request must produce exactly one bypass response. if (bypass_rsp_seen != bypass_req_issued) begin - $fatal(1, "[tb_idma_rt_midend] routing mismatch: bypass_req_issued=%0d bypass_rsp_seen=%0d", + $fatal(1, "[tb_idma_rt_midend] routing mismatch: issued=%0d seen=%0d", bypass_req_issued, bypass_rsp_seen); end - $display("[tb_idma_rt_midend] bypass requests: %0d, bypass responses: %0d, internal responses: %0d", + $display("[tb_idma_rt_midend] bypass req: %0d, bypass rsp: %0d, internal rsp: %0d", bypass_req_issued, bypass_rsp_seen, internal_rsp_seen); $finish(); end From 03a38454b346c54421bf629d8ac000e895922e27 Mon Sep 17 00:00:00 2001 From: Daniel Keller Date: Wed, 10 Jun 2026 21:59:15 +0200 Subject: [PATCH 9/9] build: Align rt_midend sim target with the nd_midend_b2b convention --- idma.mk | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/idma.mk b/idma.mk index 95e8a2e8..f5e7ed20 100644 --- a/idma.mk +++ b/idma.mk @@ -313,8 +313,7 @@ $(IDMA_VSIM_DIR)/compile.tcl: $(IDMA_BENDER_FILES) $(IDMA_FULL_TB) $(IDMA_FULL_R idma_sim_tb_idma_rt_midend: $(IDMA_VSIM_DIR)/compile.tcl cd $(IDMA_VSIM_DIR); $(VSIM) -c -do "source compile.tcl; quit" - cd $(IDMA_VSIM_DIR); $(VSIM) -c -t 1ps -voptargs=+acc \ - tb_idma_rt_midend -do "run -all; quit" + cd $(IDMA_VSIM_DIR); $(VSIM) -c -t 1ps -voptargs=+acc tb_idma_rt_midend -do "run -all; quit" idma_sim_clean: rm -rf $(IDMA_VSIM_DIR)/compile.tcl