diff --git a/Bender.yml b/Bender.yml index 4a4b7e3..c201aa9 100644 --- a/Bender.yml +++ b/Bender.yml @@ -7,7 +7,7 @@ package: dependencies: hwpe-stream: { git: "https://github.com/pulp-platform/hwpe-stream.git", version: 1.8 } hci: { git: "https://github.com/pulp-platform/hci.git", rev: 7c11cc0e3f18329daabba38b5588e05e53b0497e } # branch: remove-automatic-parameter-prop - hwpe-ctrl: { git: "https://github.com/pulp-platform/hwpe-ctrl.git", rev: "a596620" } + hwpe-ctrl: { git: "https://github.com/pulp-platform/hwpe-ctrl.git", rev: "a4abfef8706b13fad5ea8290c4f96fe9e52b21ee" } # branch: fc/rdl zeroriscy: { git: "https://github.com/yvantor/ibex.git", rev: "bender", target: "neureka_standalone" } # for verification only sources: @@ -27,6 +27,8 @@ sources: - rtl/array/neureka_binconv_col.sv - rtl/array/neureka_binconv_pe.sv - rtl/array/neureka_binconv_array.sv + - rtl/ctrl/regif/neureka_regif_pkg.sv + - rtl/ctrl/regif/neureka_regif.sv - rtl/ctrl/neureka_ctrl_fsm.sv - rtl/ctrl/neureka_ctrl.sv - rtl/neureka_engine.sv diff --git a/Makefile b/Makefile index ddc9fc2..5d8d0bf 100644 --- a/Makefile +++ b/Makefile @@ -42,8 +42,9 @@ gui ?= 0 P_STALL ?= 0.0 # Setup build object dirs -VSIM_INI=$(HW_BUILD_DIR)/modelsim.ini +VSIM_INI=$(HW_BUILD_DIR)/../modelsim.ini VSIM_LIBS=$(HW_BUILD_DIR)/work +VSIM_DESIGNBIN=$(HW_BUILD_DIR)/design.bin # Build implicit rules $(HW_BUILD_DIR): @@ -90,10 +91,10 @@ hw-clean-all: rm -rf .cached_ipdb.json hw-opt: - cd sim; $(QUESTA) vopt +acc=npr -o vopt_tb $(TESTBENCH) -floatparameters+$(TESTBENCH) -work $(HW_BUILD_DIR)/work + cd sim; $(QUESTA) qopt -designfile $(HW_BUILD_DIR)/design.bin -debug,livesim -o qopt_tb $(TESTBENCH) -floatparameters+$(TESTBENCH) -work $(HW_BUILD_DIR)/work hw-compile: - cd sim; $(QUESTA) vsim -c +incdir+$(UVM_HOME) -do 'quit -code [source $(compile_script)]' + cd sim; $(QUESTA) qsim -c +incdir+$(UVM_HOME) -do 'quit -code [source $(compile_script)]' hw-lib: @touch sim/modelsim.ini @@ -165,6 +166,7 @@ $(BUILD_DIR): mkdir -p $@ ln -sfn $(VSIM_INI) $(BUILD_DIR)/ ln -sfn $(VSIM_LIBS) $(BUILD_DIR)/ + ln -sfn $(VSIM_DESIGNBIN) $(BUILD_DIR)/ ln -sfn $(mkfile_path)/waves $(BUILD_DIR) STIMULI=$(BUILD_DIR)/app/gen @@ -275,17 +277,16 @@ VSIM_DEPS=$(CRT) VSIM_PARAMS=-gPROB_STALL=$(P_STALL) \ -gSTIM_INSTR=stim_instr.txt \ -gSTIM_DATA=stim_data.txt \ - -suppress vsim-3009 + -suppress qsim-3009 # Run the simulation run: ifeq ($(gui), 0) cd $(BUILD_DIR); \ - $(QUESTA) vsim -c vopt_tb -do "run -a" \ + $(QUESTA) qsim +designfile+design.bin -c qopt_tb -do "run -a" \ $(VSIM_PARAMS); \ if grep -q 'errors happened' transcript; then exit 1; fi else - cd $(BUILD_DIR); $(QUESTA) vsim vopt_tb \ - -do "add log -r sim:/$(TESTBENCH)/*" \ + cd $(BUILD_DIR); $(QUESTA) qsim +designfile+design.bin qopt_tb \ $(VSIM_PARAMS) endif diff --git a/rtl/ctrl/gen_regif.sh b/rtl/ctrl/gen_regif.sh new file mode 100755 index 0000000..7834e62 --- /dev/null +++ b/rtl/ctrl/gen_regif.sh @@ -0,0 +1,6 @@ +#!/bin/bash +peakrdl regblock neureka_regif.rdl -o regif/ --cpuif obi-flat --default-reset arst_n --hwif-report --addr-width 32 +peakrdl html neureka_regif.rdl -o regif/html/ +peakrdl c-header neureka_regif.rdl -o regif/hwpe_ctrl_target.h +# PeakRDL uses unpacked structs to avoid issues at compile time, which is commendable, but incompatible with FIFOing the output of the job! +sed -i 's/typedef[[:space:]]\+struct\b/typedef struct packed/g' regif/neureka_regif_pkg.sv diff --git a/rtl/ctrl/neureka_ctrl.sv b/rtl/ctrl/neureka_ctrl.sv index 466b3ce..be6a0b4 100644 --- a/rtl/ctrl/neureka_ctrl.sv +++ b/rtl/ctrl/neureka_ctrl.sv @@ -24,7 +24,9 @@ import neureka_package::*; import hwpe_ctrl_package::*; import hci_package::*; -module neureka_ctrl #( +module neureka_ctrl + import neureka_regif_pkg::*; +#( parameter int unsigned N_CORES = NR_CORES, parameter int unsigned ID = ID_WIDTH, parameter int unsigned PE_H = NEUREKA_PE_H_DEFAULT, @@ -61,36 +63,105 @@ module neureka_ctrl #( base_addr_neureka_t base_addr, next_base_addr; logic uloop_prefetch, uloop_prefetch_pulse; - ctrl_slave_t slave_ctrl; - flags_slave_t slave_flags; - ctrl_regfile_t reg_file; - ctrl_engine_t ctrl_engine, ctrl_engine_d, ctrl_engine_q; ctrl_streamer_t ctrl_streamer, ctrl_streamer_d, ctrl_streamer_q; - /* HWPE controller slave port + register file */ - hwpe_ctrl_slave #( - .N_CORES ( N_CORES ), - .N_CONTEXT ( 2 ), - .N_IO_REGS ( 25 ), - .N_GENERIC_REGS ( 0 ), - .ID_WIDTH ( ID ) - ) i_slave ( - .clk_i ( clk_i ), - .rst_ni ( rst_ni ), - .clear_o ( clear_o ), - .cfg ( periph ), - .ctrl_i ( slave_ctrl ), - .flags_o ( slave_flags ), - .reg_file ( reg_file ) + // target signals + logic job_trigger; + logic job_done, job_done_q; + logic [31:0] job_status; + neureka_regif__hwpe_ctrl_job_indep__out_t job_indep_regs; + logic job_dep_regs_valid; + neureka_regif__hwpe_ctrl_job_dep__out_t job_dep_regs; + + // OBI plug target <-> regif + logic target_obi_req; + logic target_obi_gnt; + logic [31:0] target_obi_addr; + logic target_obi_we; + logic [3:0] target_obi_be; + logic [31:0] target_obi_wdata; + logic [ID_WIDTH-1:0] target_obi_aid; + logic target_obi_rvalid; + logic target_obi_rready; + logic [31:0] target_obi_rdata; + logic target_obi_err; + logic [ID_WIDTH-1:0] target_obi_rid; + + neureka_regif__in_t hwif_in; + neureka_regif__out_t hwif_out; + + /* HWPE controller target port */ + hwpe_ctrl_target #( + .NB_CONTEXT ( 2 ), + .ID_WIDTH ( ID ), + .ADDR_WIDTH ( 10 ), + .hwpe_ctrl_regif_in_t ( neureka_regif__in_t ), + .hwpe_ctrl_regif_out_t ( neureka_regif__out_t ), + .hwpe_ctrl_job_indep_t ( neureka_regif__hwpe_ctrl_job_indep__out_t ), + .hwpe_ctrl_job_dep_t ( neureka_regif__hwpe_ctrl_job_dep__out_t ) + ) i_target ( + .clk_i ( clk_i ), + .rst_ni ( rst_ni ), + .clear_o ( clear_o ), + .target ( periph ), + .job_trigger_o ( job_trigger ), + .job_done_i ( job_done ), + .job_status_i ( job_status ), + .job_indep_regs_o ( job_indep_regs ), + .job_dep_regs_valid_o ( job_dep_regs_valid ), + .job_dep_regs_o ( job_dep_regs ), + .target_obi_req_o ( target_obi_req ), + .target_obi_gnt_i ( target_obi_gnt ), + .target_obi_addr_o ( target_obi_addr ), + .target_obi_we_o ( target_obi_we ), + .target_obi_be_o ( target_obi_be ), + .target_obi_wdata_o ( target_obi_wdata ), + .target_obi_aid_o ( target_obi_aid ), + .target_obi_rvalid_i ( target_obi_rvalid ), + .target_obi_rready_o ( target_obi_rready ), + .target_obi_rdata_i ( target_obi_rdata ), + .target_obi_err_i ( target_obi_err ), + .target_obi_rid_i ( target_obi_rid ), + .hwif_in ( hwif_in ), + .hwif_out ( hwif_out ) ); - assign evt_o = slave_flags.evt; - always_comb + + /* NEureka SystemRDL-generated register interface */ + neureka_regif #( + .ID_WIDTH ( ID_WIDTH ) + ) i_regif ( + .clk ( clk_i ), + .arst_n ( rst_ni ), + .s_obi_req ( target_obi_req ), + .s_obi_gnt ( target_obi_gnt ), + .s_obi_addr ( target_obi_addr ), + .s_obi_we ( target_obi_we ), + .s_obi_be ( target_obi_be ), + .s_obi_wdata ( target_obi_wdata ), + .s_obi_aid ( target_obi_aid ), + .s_obi_rvalid ( target_obi_rvalid ), + .s_obi_rready ( target_obi_rready ), + .s_obi_rdata ( target_obi_rdata ), + .s_obi_err ( target_obi_err ), + .s_obi_rid ( target_obi_rid ), + .hwif_in ( hwif_in ), + .hwif_out ( hwif_out ) + ); + + always_ff @(posedge clk_i or negedge rst_ni) begin - slave_ctrl = '0; - slave_ctrl.done = (state==DONE) & state_change; + if(~rst_ni) begin + job_done_q <= '0; + end + else begin + job_done_q <= job_done; + end end - assign busy_o = slave_flags.is_working; + assign evt_o = job_done_q; + assign job_done = (state==DONE) & state_change; + assign job_status = state == IDLE ? '0 : 1; + assign busy_o = state!=IDLE; /* Main FSM driving the NEUREKA */ neureka_ctrl_fsm #( @@ -116,60 +187,60 @@ module neureka_ctrl #( ); /* Binding register file <-> configuration */ - assign config_.weights_ptr = reg_file.hwpe_params[NEUREKA_REG_WEIGHTS_PTR]; - assign config_.infeat_ptr = reg_file.hwpe_params[NEUREKA_REG_INFEAT_PTR]; - assign config_.outfeat_ptr = reg_file.hwpe_params[NEUREKA_REG_OUTFEAT_PTR]; - assign config_.scale_ptr = reg_file.hwpe_params[NEUREKA_REG_SCALE_PTR]; - assign config_.scale_shift_ptr = reg_file.hwpe_params[NEUREKA_REG_SCALE_SHIFT_PTR]; - assign config_.scale_bias_ptr = reg_file.hwpe_params[NEUREKA_REG_SCALE_BIAS_PTR]; - assign config_.streamin_ptr = reg_file.hwpe_params[NEUREKA_REG_STREAMIN_PTR]; - assign config_.subtile_nb_ko = reg_file.hwpe_params[NEUREKA_REG_SUBTILE_NB0] [31:16]; - assign config_.subtile_rem_ko = reg_file.hwpe_params[NEUREKA_REG_SUBTILE_REM0][31:16]; - assign config_.subtile_nb_ki = reg_file.hwpe_params[NEUREKA_REG_SUBTILE_NB0] [15: 0]; - assign config_.subtile_rem_ki = reg_file.hwpe_params[NEUREKA_REG_SUBTILE_REM0][15: 0]; - assign config_.subtile_nb_ho = reg_file.hwpe_params[NEUREKA_REG_SUBTILE_NB1] [31:16]; - assign config_.subtile_rem_ho = reg_file.hwpe_params[NEUREKA_REG_SUBTILE_REM1][31:16]; - assign config_.subtile_nb_wo = reg_file.hwpe_params[NEUREKA_REG_SUBTILE_NB1] [15: 0]; - assign config_.subtile_rem_wo = reg_file.hwpe_params[NEUREKA_REG_SUBTILE_REM1][15: 0]; - assign config_.subtile_rem_hi = reg_file.hwpe_params[NEUREKA_REG_SUBTILE_REM2][31:16]; - assign config_.subtile_rem_wi = reg_file.hwpe_params[NEUREKA_REG_SUBTILE_REM2][15: 0]; - assign config_.infeat_d0_stride = reg_file.hwpe_params[NEUREKA_REG_INFEAT_D0_STRIDE]; - assign config_.infeat_d1_stride = reg_file.hwpe_params[NEUREKA_REG_INFEAT_D1_STRIDE]; - assign config_.infeat_d2_stride = reg_file.hwpe_params[NEUREKA_REG_INFEAT_D2_STRIDE]; - assign config_.weights_d0_stride = reg_file.hwpe_params[NEUREKA_REG_WEIGHTS_D0_STRIDE]; - assign config_.weights_d1_stride = reg_file.hwpe_params[NEUREKA_REG_WEIGHTS_D1_STRIDE]; - assign config_.weights_d2_stride = reg_file.hwpe_params[NEUREKA_REG_WEIGHTS_D2_STRIDE]; - assign config_.outfeat_d0_stride = reg_file.hwpe_params[NEUREKA_REG_OUTFEAT_D0_STRIDE]; - assign config_.outfeat_d1_stride = reg_file.hwpe_params[NEUREKA_REG_OUTFEAT_D1_STRIDE]; - assign config_.outfeat_d2_stride = reg_file.hwpe_params[NEUREKA_REG_OUTFEAT_D2_STRIDE]; - assign config_.padding_top = reg_file.hwpe_params[NEUREKA_REG_PADDING][31:28]; - assign config_.padding_right = reg_file.hwpe_params[NEUREKA_REG_PADDING][27:24]; - assign config_.padding_bottom = reg_file.hwpe_params[NEUREKA_REG_PADDING][23:20]; - assign config_.padding_left = reg_file.hwpe_params[NEUREKA_REG_PADDING][19:16]; - assign config_.padding_value = reg_file.hwpe_params[NEUREKA_REG_PADDING][15:0]; - assign config_.weight_offset_scale = reg_file.hwpe_params[NEUREKA_REG_WEIGHT_OFFSET]; - assign config_.filter_mask_top = reg_file.hwpe_params[NEUREKA_REG_FILTER_MASK][31:24]; - assign config_.filter_mask_right = reg_file.hwpe_params[NEUREKA_REG_FILTER_MASK][23:16]; - assign config_.filter_mask_bottom = reg_file.hwpe_params[NEUREKA_REG_FILTER_MASK][15: 8]; - assign config_.filter_mask_left = reg_file.hwpe_params[NEUREKA_REG_FILTER_MASK][ 7: 0]; - assign config_.feat_broadcast = reg_file.hwpe_params[NEUREKA_REG_CONFIG0][26]; - assign config_.norm_option_bias = reg_file.hwpe_params[NEUREKA_REG_CONFIG0][25]; - assign config_.norm_option_shift = reg_file.hwpe_params[NEUREKA_REG_CONFIG0][24]; - assign config_.relu = ~reg_file.hwpe_params[NEUREKA_REG_CONFIG0][23]; - assign config_.quant_mode = reg_file.hwpe_params[NEUREKA_REG_CONFIG0][22:21]; - assign config_.shift_reqnt = reg_file.hwpe_params[NEUREKA_REG_CONFIG0][20:16]; - assign config_.streamin_mode = reg_file.hwpe_params[NEUREKA_REG_CONFIG0][15]; - assign config_.streamin = reg_file.hwpe_params[NEUREKA_REG_CONFIG0][14]; - assign config_.norm_mode = reg_file.hwpe_params[NEUREKA_REG_CONFIG0][13:12]; - assign config_.use_rounding = ~reg_file.hwpe_params[NEUREKA_REG_CONFIG0][11]; - assign config_.prefetch = reg_file.hwpe_params[NEUREKA_REG_CONFIG0][10]; - assign config_.wmem_sel = reg_file.hwpe_params[NEUREKA_REG_CONFIG0][9]; - assign config_.mode_strided = reg_file.hwpe_params[NEUREKA_REG_CONFIG0][8]; - assign config_.mode_linear = reg_file.hwpe_params[NEUREKA_REG_CONFIG0][7]; // Not supported in this version. Use PW mode instead - assign config_.filter_mode = reg_file.hwpe_params[NEUREKA_REG_CONFIG0][6:5]; - assign config_.streamout_quant = reg_file.hwpe_params[NEUREKA_REG_CONFIG0][4]; - assign config_.weight_bits = {1'b0, reg_file.hwpe_params[NEUREKA_REG_CONFIG0][2:0]} + 1; - assign start = slave_flags.start; + assign config_.weights_ptr = job_dep_regs.weights_ptr.value.value; + assign config_.infeat_ptr = job_dep_regs.infeat_ptr.value.value; + assign config_.outfeat_ptr = job_dep_regs.outfeat_ptr.value.value; + assign config_.scale_ptr = job_dep_regs.scale_ptr.value.value; + assign config_.scale_shift_ptr = job_dep_regs.scale_shift_ptr.value.value; + assign config_.scale_bias_ptr = job_dep_regs.scale_bias_ptr.value.value; + assign config_.streamin_ptr = job_dep_regs.streamin_ptr.value.value; + assign config_.subtile_nb_ko = job_dep_regs.subtile_nb0.ko.value; + assign config_.subtile_rem_ko = job_dep_regs.subtile_rem0.ko.value; + assign config_.subtile_nb_ki = job_dep_regs.subtile_nb0.ki.value; + assign config_.subtile_rem_ki = job_dep_regs.subtile_rem0.ki.value; + assign config_.subtile_nb_ho = job_dep_regs.subtile_nb1.ho.value; + assign config_.subtile_rem_ho = job_dep_regs.subtile_rem1.ho.value; + assign config_.subtile_nb_wo = job_dep_regs.subtile_nb1.wo.value; + assign config_.subtile_rem_wo = job_dep_regs.subtile_rem1.wo.value; + assign config_.subtile_rem_hi = job_dep_regs.subtile_rem2.hi.value; + assign config_.subtile_rem_wi = job_dep_regs.subtile_rem2.wi.value; + assign config_.infeat_d0_stride = job_dep_regs.infeat_d0_str.value.value; + assign config_.infeat_d1_stride = job_dep_regs.infeat_d1_str.value.value; + assign config_.infeat_d2_stride = job_dep_regs.infeat_d2_str.value.value; + assign config_.weights_d0_stride = job_dep_regs.weights_d0_st.value.value; + assign config_.weights_d1_stride = job_dep_regs.weights_d1_st.value.value; + assign config_.weights_d2_stride = job_dep_regs.weights_d2_st.value.value; + assign config_.outfeat_d0_stride = job_dep_regs.outfeat_d0_st.value.value; + assign config_.outfeat_d1_stride = job_dep_regs.outfeat_d1_st.value.value; + assign config_.outfeat_d2_stride = job_dep_regs.outfeat_d2_st.value.value; + assign config_.padding_top = job_dep_regs.padding.top.value; + assign config_.padding_right = job_dep_regs.padding.right.value; + assign config_.padding_bottom = job_dep_regs.padding.bottom.value; + assign config_.padding_left = job_dep_regs.padding.left.value; + assign config_.padding_value = job_dep_regs.padding.value.value; + assign config_.weight_offset_scale = job_dep_regs.weight_offset.value.value; + assign config_.filter_mask_top = job_dep_regs.filter_mask.top.value; + assign config_.filter_mask_right = job_dep_regs.filter_mask.right.value; + assign config_.filter_mask_bottom = job_dep_regs.filter_mask.bottom.value; + assign config_.filter_mask_left = job_dep_regs.filter_mask.left.value; + assign config_.feat_broadcast = job_dep_regs.config0.feat_broadcast.value; + assign config_.norm_option_bias = job_dep_regs.config0.norm_option_bias.value; + assign config_.norm_option_shift = job_dep_regs.config0.norm_option_shift.value; + assign config_.relu = ~job_dep_regs.config0.relu.value; + assign config_.quant_mode = job_dep_regs.config0.quant_mode.value; + assign config_.shift_reqnt = job_dep_regs.config0.shift_reqnt.value; + assign config_.streamin_mode = job_dep_regs.config0.streamin_mode.value; + assign config_.streamin = job_dep_regs.config0.streamin.value; + assign config_.norm_mode = job_dep_regs.config0.norm_mode.value; + assign config_.use_rounding = ~job_dep_regs.config0.rounding.value; + assign config_.prefetch = job_dep_regs.config0.prefetch.value; + assign config_.wmem_sel = job_dep_regs.config0.wmem.value; + assign config_.mode_strided = job_dep_regs.config0.mode_strided.value; + assign config_.mode_linear = job_dep_regs.config0.mode_linear.value; // Not supported in this version. Use PW mode instead + assign config_.filter_mode = job_dep_regs.config0.filter_mode.value; + assign config_.streamout_quant = job_dep_regs.config0.streamout_quant.value; + assign config_.weight_bits = {1'b0, job_dep_regs.config0.wbits.value} + 1; + assign start = job_trigger | job_done_q & job_dep_regs_valid; /* norm variables */ logic [15:0] norm_len; diff --git a/rtl/ctrl/neureka_regif.rdl b/rtl/ctrl/neureka_regif.rdl new file mode 100644 index 0000000..3f9a581 --- /dev/null +++ b/rtl/ctrl/neureka_regif.rdl @@ -0,0 +1,539 @@ +/* + * neureka_regif.rdl + * Francesco Conti + * + * Copyright (C) 2025 ETH Zurich, University of Bologna + * Copyright and related rights are licensed under the Solderpad Hardware + * License, Version 0.51 (the "License"); you may not use this file except in + * compliance with the License. You may obtain a copy of the License at + * http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law + * or agreed to in writing, software, hardware and materials distributed under + * this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR + * CONDITIONS OF ANY KIND, either express or implied. See the License for the + * specific language governing permissions and limitations under the License. + */ + + /* + * This file contains the address map for NEureka, expressed in SystemRDL. + */ + +addrmap neureka_regif { + name = "NEureka register interface"; + desc = ""; + + // Mandatory COMMIT_TRIGGER register. Not to be updated inside HWPEs. + reg hwpe_commit_trigger { + field { + name = "reserved"; + desc = "Reserved."; + hw = r; + sw = r; + } r0[31:2] = 0; + field { + name = "commit_trigger"; + desc = "Write 0 to commit job & start execution, unlock controller; write `0x1` value to commit job & unlock controller without starting execution, which will be started when the next job is committed and triggered; write `0x2` value to trigger the current job queue without committing any new job."; + hw = r; + sw = w; + swacc = true; + } commit_trigger[1:0] = 0; + }; + // Mandatory ACQUIRE register. Not to be updated inside HWPEs. + reg hwpe_acquire { + field { + name = "acquire"; + desc = "On read starts a job offload, locks controller. Returns job ID."; + hw = w; + sw = r; + swacc = true; + } acquire[31:0] = 0; + }; + // Mandatory RESERVED register. Not to be updated inside HWPEs. + reg hwpe_reserved { + field { + name = "reserved"; + desc = "Reserved."; + hw = r; + sw = r; + } reserved[31:0] = 0; + }; + // Mandatory STATUS register. Not to be updated inside HWPEs. + reg hwpe_status { + field { + name = "status"; + desc = "Status of currently running job."; + hw = w; + sw = r; + } status0[31:0] = 0; + }; + // Mandatory RUNNING_JOB register. Not to be updated inside HWPEs. + reg hwpe_running_job { + field { + name = "reserved"; + desc = "Reserved."; + hw = r; + sw = r; + } r0[31:8] = 0; + field { + name = "running_job"; + desc = "Returns ID of currently running job if any job is running; otherwise, of the last job that has been run."; + hw = w; + sw = r; + } running_job[7:0] = 0; + }; + // Mandatory SOFT_CLEAR register. Not to be updated inside HWPEs. + reg hwpe_soft_clear { + field { + name = "reserved"; + desc = "Reserved."; + hw = r; + sw = r; + } r0[31:2] = 0; + field { + name = "soft_clear"; + desc = "Write `0x0` to clear the full status of the accelerator IP, including the register file; write `0x1` to clear the status of the accelerator IP, except for the register file; write `0x2` to clear only the register file."; + hw = r; + sw = w; + swacc = true; + } soft_clear[1:0] = 0; + }; + + // "mandatory" set of HWPE registers (CONTROL regs). Not to be updated inside HWPEs. + regfile hwpe_ctrl_mandatory { + hwpe_commit_trigger commit_trigger @ 0x00; + hwpe_acquire acquire @ 0x04; + hwpe_reserved reserved0 @ 0x08; + hwpe_status status @ 0x0c; + hwpe_running_job running_job @ 0x10; + hwpe_soft_clear soft_clear @ 0x14; + hwpe_reserved reserved1 @ 0x18; + hwpe_reserved reserved2 @ 0x1c; + }; + + // NEureka job-dependent registers + reg weights_ptr { + field { + name = "Weights pointer"; + desc = "Pointer to Weights tensor in memory (d3=Ko, d2=Fy, d1=Fx, d0=Ki)."; + hw = r; + sw = rw; + } value[31:0] = 0; + }; + reg infeat_ptr { + field { + name = "InFeat pointer"; + desc = "Pointer to InFeat tensor in memory (d2=Hi, d1=Wi, d0=Ki)."; + hw = r; + sw = rw; + } value[31:0] = 0; + }; + reg outfeat_ptr { + field { + name = "OutFeat pointer"; + desc = "Pointer to OutFeat tensor in memory (d2=Ho, d1=Wo, d0=Ko)."; + hw = r; + sw = rw; + } value[31:0] = 0; + }; + reg scale_ptr { + field { + name = "Scale pointer"; + desc = "Pointer to Scale parameters in memory (d0=Ko)."; + hw = r; + sw = rw; + } value[31:0] = 0; + }; + reg scale_shift_ptr { + field { + name = "ScaleShift pointer"; + desc = "Pointer to ScaleShift parameters in memory (d0=Ko)."; + hw = r; + sw = rw; + } value[31:0] = 0; + }; + reg scale_bias_ptr { + field { + name = "ScaleBias pointer"; + desc = "Pointer to ScaleBias parameters in memory (d0=Ko)."; + hw = r; + sw = rw; + } value[31:0] = 0; + }; + reg streamin_ptr { + field { + name = "StreamIn pointer"; + desc = "Pointer to StreamIn parameters in memory (d2=Ho, d1=Wo, d0=Ko)."; + hw = r; + sw = rw; + } value[31:0] = 0; + }; + reg infeat_d0_stride { + field { + name = "InFeat d0 stride"; + desc = "InFeat d0 stride."; + hw = r; + sw = rw; + } value[31:0] = 0; + }; + reg infeat_d1_stride { + field { + name = "InFeat d1 stride"; + desc = "InFeat d1 stride."; + hw = r; + sw = rw; + } value[31:0] = 0; + }; + reg infeat_d2_stride { + field { + name = "InFeat d2 stride"; + desc = "InFeat d2 stride."; + hw = r; + sw = rw; + } value[31:0] = 0; + }; + reg outfeat_d0_stride { + field { + name = "OutFeat d0 stride"; + desc = "OutFeat d0 stride."; + hw = r; + sw = rw; + } value[31:0] = 0; + }; + reg outfeat_d1_stride { + field { + name = "OutFeat d1 stride"; + desc = "OutFeat d1 stride."; + hw = r; + sw = rw; + } value[31:0] = 0; + }; + reg outfeat_d2_stride { + field { + name = "OutFeat d2 stride"; + desc = "OutFeat d2 stride."; + hw = r; + sw = rw; + } value[31:0] = 0; + }; + reg weights_d0_stride { + field { + name = "Weights d0 stride"; + desc = "Weights d0 stride."; + hw = r; + sw = rw; + } value[31:0] = 0; + }; + reg weights_d1_stride { + field { + name = "Weights d1 stride"; + desc = "Weights d1 stride."; + hw = r; + sw = rw; + } value[31:0] = 0; + }; + reg weights_d2_stride { + field { + name = "Weights d2 stride"; + desc = "Weights d2 stride."; + hw = r; + sw = rw; + } value[31:0] = 0; + }; + reg subtile_rem0 { + name = "Subtile Remainder 0"; + field { + name = "Ko"; + desc = "Ko subtile remainder."; + hw = r; + sw = rw; + } ko[31:16] = 0; + field { + name = "Ki"; + desc = "Ki subtile remainder."; + hw = r; + sw = rw; + } ki[15:0] = 0; + }; + reg subtile_rem1 { + name = "Subtile Remainder 1"; + field { + name = "Ho"; + desc = "Ho subtile remainder."; + hw = r; + sw = rw; + } ho[31:16] = 0; + field { + name = "Wo"; + desc = "Wo subtile remainder."; + hw = r; + sw = rw; + } wo[15:0] = 0; + }; + reg subtile_rem2 { + name = "Subtile Remainder 2"; + field { + name = "Hi"; + desc = "Hi subtile remainder."; + hw = r; + sw = rw; + } hi[31:16] = 0; + field { + name = "Wi"; + desc = "Wi subtile remainder."; + hw = r; + sw = rw; + } wi[15:0] = 0; + }; + reg subtile_nb0 { + name = "Subtile Number 0"; + field { + name = "Ko"; + desc = "Ko subtile number."; + hw = r; + sw = rw; + } ko[31:16] = 0; + field { + name = "Ki"; + desc = "Ki subtile number."; + hw = r; + sw = rw; + } ki[15:0] = 0; + }; + reg subtile_nb1 { + name = "Subtile Number 0"; + field { + name = "Ho"; + desc = "Ho subtile number."; + hw = r; + sw = rw; + } ho[31:16] = 0; + field { + name = "Wo"; + desc = "Wo subtile number."; + hw = r; + sw = rw; + } wo[15:0] = 0; + }; + reg padding { + name = "Padding"; + field { + name = "Padding Top"; + desc = "Padding on top side."; + hw = r; + sw = rw; + } top[31:28] = 0; + field { + name = "Padding Right"; + desc = "Padding on right side."; + hw = r; + sw = rw; + } right[27:24] = 0; + field { + name = "Padding Bottom"; + desc = "Padding on bottom side."; + hw = r; + sw = rw; + } bottom[23:20] = 0; + field { + name = "Padding Left"; + desc = "Padding on left side."; + hw = r; + sw = rw; + } left[19:16] = 0; + field { + name = "Padding Value"; + desc = "Value to be used for padding."; + hw = r; + sw = rw; + } value[15:0] = 0; + }; + reg weight_offset { + field { + name = "Weight Offset."; + desc = "Weights offset to be considered for asymmetric weight support."; + hw = r; + sw = rw; + } value[31:0] = 0; + }; + reg filter_mask { + name = "Filter mask"; + field { + name = "Filter Mask Top"; + desc = "Filter Mask on top side."; + hw = r; + sw = rw; + } top[31:24] = 0; + field { + name = "Filter Mask Right"; + desc = "Filter Mask on right side."; + hw = r; + sw = rw; + } right[23:16] = 0; + field { + name = "Filter Mask Bottom"; + desc = "Filter Mask on bottom side."; + hw = r; + sw = rw; + } bottom[15:8] = 0; + field { + name = "Filter Mask Left"; + desc = "Filter Mask on left side."; + hw = r; + sw = rw; + } left[7:0] = 0; + }; + reg config0 { + name = "Config 0"; + field { + name = "Reserved"; + desc = "Reserved."; + hw = r; + sw = rw; + } reserved[31:27] = 0; + field { + name = "Feature broadcast"; + desc = "Feature broadcast."; + hw = r; + sw = rw; + } feat_broadcast[26:26] = 0; + field { + name = "Use bias in scaling"; + desc = "Use bias in scaling."; + hw = r; + sw = rw; + } norm_option_bias[25:25] = 0; + field { + name = "Use shift in scaling"; + desc = "Use shift in scaling."; + hw = r; + sw = rw; + } norm_option_shift[24:24] = 0; + field { + name = "Deactivate relu"; + desc = "Deactivate relu."; + hw = r; + sw = rw; + } relu[23:23] = 0; + field { + name = "Quantization mode"; + desc = "Quantization mode."; + hw = r; + sw = rw; + } quant_mode[22:21] = 0; + field { + name = "Shift requant"; + desc = "Shift requant."; + hw = r; + sw = rw; + } shift_reqnt[20:16] = 0; + field { + name = "Streamin mode"; + desc = "Streamin mode."; + hw = r; + sw = rw; + } streamin_mode[15:15] = 0; + field { + name = "Streamin"; + desc = "Streamin."; + hw = r; + sw = rw; + } streamin[14:14] = 0; + field { + name = "Normalization bits"; + desc = "Normalization bits (00=8, 01=16, 10=32)."; + hw = r; + sw = rw; + } norm_mode[13:12] = 0; + field { + name = "Rounding"; + desc = "Rounding (0=round, 1=do not round)."; + hw = r; + sw = rw; + } rounding[11:11] = 0; + field { + name = "Prefetch"; + desc = "Prefetch next inputs to minimize idle time (only with 1x1)."; + hw = r; + sw = rw; + } prefetch[10:10] = 0; + field { + name = "Weight memory"; + desc = "Use dedicated weight memory port for weights."; + hw = r; + sw = rw; + } wmem[9:9] = 0; + field { + name = "Mode strided"; + hw = r; + sw = rw; + } mode_strided[8:8] = 0; + field { + name = "Mode linear"; + hw = r; + sw = rw; + } mode_linear[7:7] = 0; + field { + name = "Filter Mode"; + desc = "Filter Mode (11=linear, 10=1x1, 01=3x3 depthwise, 00=3x3)."; + hw = r; + sw = rw; + } filter_mode[6:5] = 0; + field { + name = "Streamout/Quantization"; + desc = "Streamout/Quantization."; + hw = r; + sw = rw; + } streamout_quant[4:4] = 0; + field { + name = "Reserved"; + desc = "Reserved."; + hw = r; + sw = rw; + } reserved2[3:3] = 0; + field { + name = "Weight bits"; + desc = "Weight bits (minus 1)."; + hw = r; + sw = rw; + } wbits[2:0] = 0; + }; + + // no "job-independent" registers in NEUREKA + regfile hwpe_ctrl_job_indep { + hwpe_reserved reserved; + }; + + // "job-dependent" set of HWPE registers. Update inside HWPEs. + regfile hwpe_ctrl_job_dep { + weights_ptr weights_ptr @ 0x00; + infeat_ptr infeat_ptr @ 0x04; + outfeat_ptr outfeat_ptr @ 0x08; + scale_ptr scale_ptr @ 0x0c; + scale_shift_ptr scale_shift_ptr @ 0x10; + scale_bias_ptr scale_bias_ptr @ 0x14; + infeat_d0_stride infeat_d0_str @ 0x18; + infeat_d1_stride infeat_d1_str @ 0x1c; + infeat_d2_stride infeat_d2_str @ 0x20; + outfeat_d0_stride outfeat_d0_st @ 0x24; + outfeat_d1_stride outfeat_d1_st @ 0x28; + outfeat_d2_stride outfeat_d2_st @ 0x2c; + weights_d0_stride weights_d0_st @ 0x30; + weights_d1_stride weights_d1_st @ 0x34; + weights_d2_stride weights_d2_st @ 0x38; + subtile_rem0 subtile_rem0 @ 0x3c; + subtile_rem1 subtile_rem1 @ 0x40; + subtile_rem2 subtile_rem2 @ 0x44; + subtile_nb0 subtile_nb0 @ 0x48; + subtile_nb1 subtile_nb1 @ 0x4c; + padding padding @ 0x50; + weight_offset weight_offset @ 0x54; + filter_mask filter_mask @ 0x58; + config0 config0 @ 0x5c; + streamin_ptr streamin_ptr @ 0x60; + }; + + // HWPE control address map. Update inside HWPEs + hwpe_ctrl_mandatory hwpe_ctrl @ 0x00; + hwpe_ctrl_job_dep hwpe_job_dep @ 0x20; + hwpe_ctrl_job_indep hwpe_job_indep; + +}; diff --git a/rtl/ctrl/regif/neureka_regif.sv b/rtl/ctrl/regif/neureka_regif.sv new file mode 100644 index 0000000..88cbf36 --- /dev/null +++ b/rtl/ctrl/regif/neureka_regif.sv @@ -0,0 +1,2168 @@ +// Generated by PeakRDL-regblock - A free and open-source SystemVerilog generator +// https://github.com/SystemRDL/PeakRDL-regblock + +module neureka_regif #( + parameter ID_WIDTH = 1 + ) ( + input wire clk, + input wire arst_n, + + input wire s_obi_req, + output logic s_obi_gnt, + input wire [31:0] s_obi_addr, + input wire s_obi_we, + input wire [3:0] s_obi_be, + input wire [31:0] s_obi_wdata, + input wire [ID_WIDTH-1:0] s_obi_aid, + output logic s_obi_rvalid, + input wire s_obi_rready, + output logic [31:0] s_obi_rdata, + output logic s_obi_err, + output logic [ID_WIDTH-1:0] s_obi_rid, + + input neureka_regif_pkg::neureka_regif__in_t hwif_in, + output neureka_regif_pkg::neureka_regif__out_t hwif_out + ); + + //-------------------------------------------------------------------------- + // CPU Bus interface logic + //-------------------------------------------------------------------------- + logic cpuif_req; + logic cpuif_req_is_wr; + logic [31:0] cpuif_addr; + logic [31:0] cpuif_wr_data; + logic [31:0] cpuif_wr_biten; + logic cpuif_req_stall_wr; + logic cpuif_req_stall_rd; + + logic cpuif_rd_ack; + logic cpuif_rd_err; + logic [31:0] cpuif_rd_data; + + logic cpuif_wr_ack; + logic cpuif_wr_err; + + // State & holding regs + logic is_active; // A request is being served (not yet fully responded) + logic gnt_q; // one-cycle grant for A-channel + logic rsp_pending; // response ready but not yet accepted by manager + logic [31:0] rsp_rdata_q; + logic rsp_err_q; + logic [$bits(s_obi_rid)-1:0] rid_q; + + // Latch AID on accept to echo back the response + always_ff @(posedge clk or negedge arst_n) begin + if (~arst_n) begin + is_active <= 1'b0; + gnt_q <= 1'b0; + rsp_pending <= 1'b0; + rsp_rdata_q <= '0; + rsp_err_q <= 1'b0; + rid_q <= '0; + + cpuif_req <= '0; + cpuif_req_is_wr <= '0; + cpuif_addr <= '0; + cpuif_wr_data <= '0; + cpuif_wr_biten <= '0; + end else begin + // defaults + cpuif_req <= 1'b0; + gnt_q <= s_obi_req & ~is_active; + + // Accept new request when idle + if (~is_active) begin + if (s_obi_req) begin + is_active <= 1'b1; + cpuif_req <= 1'b1; + cpuif_req_is_wr <= s_obi_we; + cpuif_addr <= {s_obi_addr[31:2], 2'b0}; + cpuif_wr_data <= s_obi_wdata; + rid_q <= s_obi_aid; + for (int i = 0; i < 4; i++) begin + cpuif_wr_biten[i*8 +: 8] <= {8{ s_obi_be[i] }}; + end + end + end + + // Capture response + if (is_active && (cpuif_rd_ack || cpuif_wr_ack)) begin + rsp_pending <= 1'b1; + rsp_rdata_q <= cpuif_rd_data; + rsp_err_q <= cpuif_rd_err | cpuif_wr_err; + // NOTE: Keep 'is_active' asserted until the external R handshake completes + end + + // Complete external R-channel handshake only if manager ready + if (rsp_pending && s_obi_rvalid && s_obi_rready) begin + rsp_pending <= 1'b0; + is_active <= 1'b0; // free to accept the next request + end + end + end + + // R-channel outputs (held stable while rsp_pending=1) + assign s_obi_rvalid = rsp_pending; + assign s_obi_rdata = rsp_rdata_q; + assign s_obi_err = rsp_err_q; + assign s_obi_rid = rid_q; + + // A-channel grant (registered one-cycle pulse when we accept a request) + assign s_obi_gnt = gnt_q; + + logic cpuif_req_masked; + + // Read & write latencies are balanced. Stalls not required + assign cpuif_req_stall_rd = '0; + assign cpuif_req_stall_wr = '0; + assign cpuif_req_masked = cpuif_req + & !(!cpuif_req_is_wr & cpuif_req_stall_rd) + & !(cpuif_req_is_wr & cpuif_req_stall_wr); + + //-------------------------------------------------------------------------- + // Address Decode + //-------------------------------------------------------------------------- + typedef struct { + struct { + logic commit_trigger; + logic acquire; + logic reserved0; + logic status; + logic running_job; + logic soft_clear; + logic reserved1; + logic reserved2; + } hwpe_ctrl; + struct { + logic weights_ptr; + logic infeat_ptr; + logic outfeat_ptr; + logic scale_ptr; + logic scale_shift_ptr; + logic scale_bias_ptr; + logic infeat_d0_str; + logic infeat_d1_str; + logic infeat_d2_str; + logic outfeat_d0_st; + logic outfeat_d1_st; + logic outfeat_d2_st; + logic weights_d0_st; + logic weights_d1_st; + logic weights_d2_st; + logic subtile_rem0; + logic subtile_rem1; + logic subtile_rem2; + logic subtile_nb0; + logic subtile_nb1; + logic padding; + logic weight_offset; + logic filter_mask; + logic config0; + logic streamin_ptr; + } hwpe_job_dep; + struct { + logic reserved; + } hwpe_job_indep; + } decoded_reg_strb_t; + decoded_reg_strb_t decoded_reg_strb; + logic decoded_err; + logic decoded_req; + logic decoded_req_is_wr; + logic [31:0] decoded_wr_data; + logic [31:0] decoded_wr_biten; + + always_comb begin + automatic logic is_valid_addr; + automatic logic is_invalid_rw; + is_valid_addr = '1; // No error checking on valid address access + is_invalid_rw = '0; + decoded_reg_strb.hwpe_ctrl.commit_trigger = cpuif_req_masked & (cpuif_addr == 32'h0); + decoded_reg_strb.hwpe_ctrl.acquire = cpuif_req_masked & (cpuif_addr == 32'h4) & !cpuif_req_is_wr; + decoded_reg_strb.hwpe_ctrl.reserved0 = cpuif_req_masked & (cpuif_addr == 32'h8) & !cpuif_req_is_wr; + decoded_reg_strb.hwpe_ctrl.status = cpuif_req_masked & (cpuif_addr == 32'hc) & !cpuif_req_is_wr; + decoded_reg_strb.hwpe_ctrl.running_job = cpuif_req_masked & (cpuif_addr == 32'h10) & !cpuif_req_is_wr; + decoded_reg_strb.hwpe_ctrl.soft_clear = cpuif_req_masked & (cpuif_addr == 32'h14); + decoded_reg_strb.hwpe_ctrl.reserved1 = cpuif_req_masked & (cpuif_addr == 32'h18) & !cpuif_req_is_wr; + decoded_reg_strb.hwpe_ctrl.reserved2 = cpuif_req_masked & (cpuif_addr == 32'h1c) & !cpuif_req_is_wr; + decoded_reg_strb.hwpe_job_dep.weights_ptr = cpuif_req_masked & (cpuif_addr == 32'h20); + decoded_reg_strb.hwpe_job_dep.infeat_ptr = cpuif_req_masked & (cpuif_addr == 32'h24); + decoded_reg_strb.hwpe_job_dep.outfeat_ptr = cpuif_req_masked & (cpuif_addr == 32'h28); + decoded_reg_strb.hwpe_job_dep.scale_ptr = cpuif_req_masked & (cpuif_addr == 32'h2c); + decoded_reg_strb.hwpe_job_dep.scale_shift_ptr = cpuif_req_masked & (cpuif_addr == 32'h30); + decoded_reg_strb.hwpe_job_dep.scale_bias_ptr = cpuif_req_masked & (cpuif_addr == 32'h34); + decoded_reg_strb.hwpe_job_dep.infeat_d0_str = cpuif_req_masked & (cpuif_addr == 32'h38); + decoded_reg_strb.hwpe_job_dep.infeat_d1_str = cpuif_req_masked & (cpuif_addr == 32'h3c); + decoded_reg_strb.hwpe_job_dep.infeat_d2_str = cpuif_req_masked & (cpuif_addr == 32'h40); + decoded_reg_strb.hwpe_job_dep.outfeat_d0_st = cpuif_req_masked & (cpuif_addr == 32'h44); + decoded_reg_strb.hwpe_job_dep.outfeat_d1_st = cpuif_req_masked & (cpuif_addr == 32'h48); + decoded_reg_strb.hwpe_job_dep.outfeat_d2_st = cpuif_req_masked & (cpuif_addr == 32'h4c); + decoded_reg_strb.hwpe_job_dep.weights_d0_st = cpuif_req_masked & (cpuif_addr == 32'h50); + decoded_reg_strb.hwpe_job_dep.weights_d1_st = cpuif_req_masked & (cpuif_addr == 32'h54); + decoded_reg_strb.hwpe_job_dep.weights_d2_st = cpuif_req_masked & (cpuif_addr == 32'h58); + decoded_reg_strb.hwpe_job_dep.subtile_rem0 = cpuif_req_masked & (cpuif_addr == 32'h5c); + decoded_reg_strb.hwpe_job_dep.subtile_rem1 = cpuif_req_masked & (cpuif_addr == 32'h60); + decoded_reg_strb.hwpe_job_dep.subtile_rem2 = cpuif_req_masked & (cpuif_addr == 32'h64); + decoded_reg_strb.hwpe_job_dep.subtile_nb0 = cpuif_req_masked & (cpuif_addr == 32'h68); + decoded_reg_strb.hwpe_job_dep.subtile_nb1 = cpuif_req_masked & (cpuif_addr == 32'h6c); + decoded_reg_strb.hwpe_job_dep.padding = cpuif_req_masked & (cpuif_addr == 32'h70); + decoded_reg_strb.hwpe_job_dep.weight_offset = cpuif_req_masked & (cpuif_addr == 32'h74); + decoded_reg_strb.hwpe_job_dep.filter_mask = cpuif_req_masked & (cpuif_addr == 32'h78); + decoded_reg_strb.hwpe_job_dep.config0 = cpuif_req_masked & (cpuif_addr == 32'h7c); + decoded_reg_strb.hwpe_job_dep.streamin_ptr = cpuif_req_masked & (cpuif_addr == 32'h80); + decoded_reg_strb.hwpe_job_indep.reserved = cpuif_req_masked & (cpuif_addr == 32'h84) & !cpuif_req_is_wr; + decoded_err = (~is_valid_addr | is_invalid_rw) & decoded_req; + end + + // Pass down signals to next stage + assign decoded_req = cpuif_req_masked; + assign decoded_req_is_wr = cpuif_req_is_wr; + assign decoded_wr_data = cpuif_wr_data; + assign decoded_wr_biten = cpuif_wr_biten; + + //-------------------------------------------------------------------------- + // Field logic + //-------------------------------------------------------------------------- + typedef struct { + struct { + struct { + struct { + logic [1:0] next; + logic load_next; + } commit_trigger; + } commit_trigger; + struct { + struct { + logic [1:0] next; + logic load_next; + } soft_clear; + } soft_clear; + } hwpe_ctrl; + struct { + struct { + struct { + logic [31:0] next; + logic load_next; + } value; + } weights_ptr; + struct { + struct { + logic [31:0] next; + logic load_next; + } value; + } infeat_ptr; + struct { + struct { + logic [31:0] next; + logic load_next; + } value; + } outfeat_ptr; + struct { + struct { + logic [31:0] next; + logic load_next; + } value; + } scale_ptr; + struct { + struct { + logic [31:0] next; + logic load_next; + } value; + } scale_shift_ptr; + struct { + struct { + logic [31:0] next; + logic load_next; + } value; + } scale_bias_ptr; + struct { + struct { + logic [31:0] next; + logic load_next; + } value; + } infeat_d0_str; + struct { + struct { + logic [31:0] next; + logic load_next; + } value; + } infeat_d1_str; + struct { + struct { + logic [31:0] next; + logic load_next; + } value; + } infeat_d2_str; + struct { + struct { + logic [31:0] next; + logic load_next; + } value; + } outfeat_d0_st; + struct { + struct { + logic [31:0] next; + logic load_next; + } value; + } outfeat_d1_st; + struct { + struct { + logic [31:0] next; + logic load_next; + } value; + } outfeat_d2_st; + struct { + struct { + logic [31:0] next; + logic load_next; + } value; + } weights_d0_st; + struct { + struct { + logic [31:0] next; + logic load_next; + } value; + } weights_d1_st; + struct { + struct { + logic [31:0] next; + logic load_next; + } value; + } weights_d2_st; + struct { + struct { + logic [15:0] next; + logic load_next; + } ki; + struct { + logic [15:0] next; + logic load_next; + } ko; + } subtile_rem0; + struct { + struct { + logic [15:0] next; + logic load_next; + } wo; + struct { + logic [15:0] next; + logic load_next; + } ho; + } subtile_rem1; + struct { + struct { + logic [15:0] next; + logic load_next; + } wi; + struct { + logic [15:0] next; + logic load_next; + } hi; + } subtile_rem2; + struct { + struct { + logic [15:0] next; + logic load_next; + } ki; + struct { + logic [15:0] next; + logic load_next; + } ko; + } subtile_nb0; + struct { + struct { + logic [15:0] next; + logic load_next; + } wo; + struct { + logic [15:0] next; + logic load_next; + } ho; + } subtile_nb1; + struct { + struct { + logic [15:0] next; + logic load_next; + } value; + struct { + logic [3:0] next; + logic load_next; + } left; + struct { + logic [3:0] next; + logic load_next; + } bottom; + struct { + logic [3:0] next; + logic load_next; + } right; + struct { + logic [3:0] next; + logic load_next; + } top; + } padding; + struct { + struct { + logic [31:0] next; + logic load_next; + } value; + } weight_offset; + struct { + struct { + logic [7:0] next; + logic load_next; + } left; + struct { + logic [7:0] next; + logic load_next; + } bottom; + struct { + logic [7:0] next; + logic load_next; + } right; + struct { + logic [7:0] next; + logic load_next; + } top; + } filter_mask; + struct { + struct { + logic [2:0] next; + logic load_next; + } wbits; + struct { + logic next; + logic load_next; + } reserved2; + struct { + logic next; + logic load_next; + } streamout_quant; + struct { + logic [1:0] next; + logic load_next; + } filter_mode; + struct { + logic next; + logic load_next; + } mode_linear; + struct { + logic next; + logic load_next; + } mode_strided; + struct { + logic next; + logic load_next; + } wmem; + struct { + logic next; + logic load_next; + } prefetch; + struct { + logic next; + logic load_next; + } rounding; + struct { + logic [1:0] next; + logic load_next; + } norm_mode; + struct { + logic next; + logic load_next; + } streamin; + struct { + logic next; + logic load_next; + } streamin_mode; + struct { + logic [4:0] next; + logic load_next; + } shift_reqnt; + struct { + logic [1:0] next; + logic load_next; + } quant_mode; + struct { + logic next; + logic load_next; + } relu; + struct { + logic next; + logic load_next; + } norm_option_shift; + struct { + logic next; + logic load_next; + } norm_option_bias; + struct { + logic next; + logic load_next; + } feat_broadcast; + struct { + logic [4:0] next; + logic load_next; + } reserved; + } config0; + struct { + struct { + logic [31:0] next; + logic load_next; + } value; + } streamin_ptr; + } hwpe_job_dep; + } field_combo_t; + field_combo_t field_combo; + + typedef struct { + struct { + struct { + struct { + logic [1:0] value; + } commit_trigger; + } commit_trigger; + struct { + struct { + logic [1:0] value; + } soft_clear; + } soft_clear; + } hwpe_ctrl; + struct { + struct { + struct { + logic [31:0] value; + } value; + } weights_ptr; + struct { + struct { + logic [31:0] value; + } value; + } infeat_ptr; + struct { + struct { + logic [31:0] value; + } value; + } outfeat_ptr; + struct { + struct { + logic [31:0] value; + } value; + } scale_ptr; + struct { + struct { + logic [31:0] value; + } value; + } scale_shift_ptr; + struct { + struct { + logic [31:0] value; + } value; + } scale_bias_ptr; + struct { + struct { + logic [31:0] value; + } value; + } infeat_d0_str; + struct { + struct { + logic [31:0] value; + } value; + } infeat_d1_str; + struct { + struct { + logic [31:0] value; + } value; + } infeat_d2_str; + struct { + struct { + logic [31:0] value; + } value; + } outfeat_d0_st; + struct { + struct { + logic [31:0] value; + } value; + } outfeat_d1_st; + struct { + struct { + logic [31:0] value; + } value; + } outfeat_d2_st; + struct { + struct { + logic [31:0] value; + } value; + } weights_d0_st; + struct { + struct { + logic [31:0] value; + } value; + } weights_d1_st; + struct { + struct { + logic [31:0] value; + } value; + } weights_d2_st; + struct { + struct { + logic [15:0] value; + } ki; + struct { + logic [15:0] value; + } ko; + } subtile_rem0; + struct { + struct { + logic [15:0] value; + } wo; + struct { + logic [15:0] value; + } ho; + } subtile_rem1; + struct { + struct { + logic [15:0] value; + } wi; + struct { + logic [15:0] value; + } hi; + } subtile_rem2; + struct { + struct { + logic [15:0] value; + } ki; + struct { + logic [15:0] value; + } ko; + } subtile_nb0; + struct { + struct { + logic [15:0] value; + } wo; + struct { + logic [15:0] value; + } ho; + } subtile_nb1; + struct { + struct { + logic [15:0] value; + } value; + struct { + logic [3:0] value; + } left; + struct { + logic [3:0] value; + } bottom; + struct { + logic [3:0] value; + } right; + struct { + logic [3:0] value; + } top; + } padding; + struct { + struct { + logic [31:0] value; + } value; + } weight_offset; + struct { + struct { + logic [7:0] value; + } left; + struct { + logic [7:0] value; + } bottom; + struct { + logic [7:0] value; + } right; + struct { + logic [7:0] value; + } top; + } filter_mask; + struct { + struct { + logic [2:0] value; + } wbits; + struct { + logic value; + } reserved2; + struct { + logic value; + } streamout_quant; + struct { + logic [1:0] value; + } filter_mode; + struct { + logic value; + } mode_linear; + struct { + logic value; + } mode_strided; + struct { + logic value; + } wmem; + struct { + logic value; + } prefetch; + struct { + logic value; + } rounding; + struct { + logic [1:0] value; + } norm_mode; + struct { + logic value; + } streamin; + struct { + logic value; + } streamin_mode; + struct { + logic [4:0] value; + } shift_reqnt; + struct { + logic [1:0] value; + } quant_mode; + struct { + logic value; + } relu; + struct { + logic value; + } norm_option_shift; + struct { + logic value; + } norm_option_bias; + struct { + logic value; + } feat_broadcast; + struct { + logic [4:0] value; + } reserved; + } config0; + struct { + struct { + logic [31:0] value; + } value; + } streamin_ptr; + } hwpe_job_dep; + } field_storage_t; + field_storage_t field_storage; + + // Field: neureka_regif.hwpe_ctrl.commit_trigger.commit_trigger + always_comb begin + automatic logic [1:0] next_c; + automatic logic load_next_c; + next_c = field_storage.hwpe_ctrl.commit_trigger.commit_trigger.value; + load_next_c = '0; + if(decoded_reg_strb.hwpe_ctrl.commit_trigger && decoded_req_is_wr) begin // SW write + next_c = (field_storage.hwpe_ctrl.commit_trigger.commit_trigger.value & ~decoded_wr_biten[1:0]) | (decoded_wr_data[1:0] & decoded_wr_biten[1:0]); + load_next_c = '1; + end + field_combo.hwpe_ctrl.commit_trigger.commit_trigger.next = next_c; + field_combo.hwpe_ctrl.commit_trigger.commit_trigger.load_next = load_next_c; + end + always_ff @(posedge clk or negedge arst_n) begin + if(~arst_n) begin + field_storage.hwpe_ctrl.commit_trigger.commit_trigger.value <= 2'h0; + end else begin + if(field_combo.hwpe_ctrl.commit_trigger.commit_trigger.load_next) begin + field_storage.hwpe_ctrl.commit_trigger.commit_trigger.value <= field_combo.hwpe_ctrl.commit_trigger.commit_trigger.next; + end + end + end + assign hwif_out.hwpe_ctrl.commit_trigger.commit_trigger.value = field_storage.hwpe_ctrl.commit_trigger.commit_trigger.value; + assign hwif_out.hwpe_ctrl.commit_trigger.commit_trigger.swacc = decoded_reg_strb.hwpe_ctrl.commit_trigger; + assign hwif_out.hwpe_ctrl.commit_trigger.r0.value = 30'h0; + assign hwif_out.hwpe_ctrl.acquire.acquire.swacc = decoded_reg_strb.hwpe_ctrl.acquire; + assign hwif_out.hwpe_ctrl.reserved0.reserved.value = 32'h0; + assign hwif_out.hwpe_ctrl.running_job.r0.value = 24'h0; + // Field: neureka_regif.hwpe_ctrl.soft_clear.soft_clear + always_comb begin + automatic logic [1:0] next_c; + automatic logic load_next_c; + next_c = field_storage.hwpe_ctrl.soft_clear.soft_clear.value; + load_next_c = '0; + if(decoded_reg_strb.hwpe_ctrl.soft_clear && decoded_req_is_wr) begin // SW write + next_c = (field_storage.hwpe_ctrl.soft_clear.soft_clear.value & ~decoded_wr_biten[1:0]) | (decoded_wr_data[1:0] & decoded_wr_biten[1:0]); + load_next_c = '1; + end + field_combo.hwpe_ctrl.soft_clear.soft_clear.next = next_c; + field_combo.hwpe_ctrl.soft_clear.soft_clear.load_next = load_next_c; + end + always_ff @(posedge clk or negedge arst_n) begin + if(~arst_n) begin + field_storage.hwpe_ctrl.soft_clear.soft_clear.value <= 2'h0; + end else begin + if(field_combo.hwpe_ctrl.soft_clear.soft_clear.load_next) begin + field_storage.hwpe_ctrl.soft_clear.soft_clear.value <= field_combo.hwpe_ctrl.soft_clear.soft_clear.next; + end + end + end + assign hwif_out.hwpe_ctrl.soft_clear.soft_clear.value = field_storage.hwpe_ctrl.soft_clear.soft_clear.value; + assign hwif_out.hwpe_ctrl.soft_clear.soft_clear.swacc = decoded_reg_strb.hwpe_ctrl.soft_clear; + assign hwif_out.hwpe_ctrl.soft_clear.r0.value = 30'h0; + assign hwif_out.hwpe_ctrl.reserved1.reserved.value = 32'h0; + assign hwif_out.hwpe_ctrl.reserved2.reserved.value = 32'h0; + // Field: neureka_regif.hwpe_job_dep.weights_ptr.value + always_comb begin + automatic logic [31:0] next_c; + automatic logic load_next_c; + next_c = field_storage.hwpe_job_dep.weights_ptr.value.value; + load_next_c = '0; + if(decoded_reg_strb.hwpe_job_dep.weights_ptr && decoded_req_is_wr) begin // SW write + next_c = (field_storage.hwpe_job_dep.weights_ptr.value.value & ~decoded_wr_biten[31:0]) | (decoded_wr_data[31:0] & decoded_wr_biten[31:0]); + load_next_c = '1; + end + field_combo.hwpe_job_dep.weights_ptr.value.next = next_c; + field_combo.hwpe_job_dep.weights_ptr.value.load_next = load_next_c; + end + always_ff @(posedge clk or negedge arst_n) begin + if(~arst_n) begin + field_storage.hwpe_job_dep.weights_ptr.value.value <= 32'h0; + end else begin + if(field_combo.hwpe_job_dep.weights_ptr.value.load_next) begin + field_storage.hwpe_job_dep.weights_ptr.value.value <= field_combo.hwpe_job_dep.weights_ptr.value.next; + end + end + end + assign hwif_out.hwpe_job_dep.weights_ptr.value.value = field_storage.hwpe_job_dep.weights_ptr.value.value; + // Field: neureka_regif.hwpe_job_dep.infeat_ptr.value + always_comb begin + automatic logic [31:0] next_c; + automatic logic load_next_c; + next_c = field_storage.hwpe_job_dep.infeat_ptr.value.value; + load_next_c = '0; + if(decoded_reg_strb.hwpe_job_dep.infeat_ptr && decoded_req_is_wr) begin // SW write + next_c = (field_storage.hwpe_job_dep.infeat_ptr.value.value & ~decoded_wr_biten[31:0]) | (decoded_wr_data[31:0] & decoded_wr_biten[31:0]); + load_next_c = '1; + end + field_combo.hwpe_job_dep.infeat_ptr.value.next = next_c; + field_combo.hwpe_job_dep.infeat_ptr.value.load_next = load_next_c; + end + always_ff @(posedge clk or negedge arst_n) begin + if(~arst_n) begin + field_storage.hwpe_job_dep.infeat_ptr.value.value <= 32'h0; + end else begin + if(field_combo.hwpe_job_dep.infeat_ptr.value.load_next) begin + field_storage.hwpe_job_dep.infeat_ptr.value.value <= field_combo.hwpe_job_dep.infeat_ptr.value.next; + end + end + end + assign hwif_out.hwpe_job_dep.infeat_ptr.value.value = field_storage.hwpe_job_dep.infeat_ptr.value.value; + // Field: neureka_regif.hwpe_job_dep.outfeat_ptr.value + always_comb begin + automatic logic [31:0] next_c; + automatic logic load_next_c; + next_c = field_storage.hwpe_job_dep.outfeat_ptr.value.value; + load_next_c = '0; + if(decoded_reg_strb.hwpe_job_dep.outfeat_ptr && decoded_req_is_wr) begin // SW write + next_c = (field_storage.hwpe_job_dep.outfeat_ptr.value.value & ~decoded_wr_biten[31:0]) | (decoded_wr_data[31:0] & decoded_wr_biten[31:0]); + load_next_c = '1; + end + field_combo.hwpe_job_dep.outfeat_ptr.value.next = next_c; + field_combo.hwpe_job_dep.outfeat_ptr.value.load_next = load_next_c; + end + always_ff @(posedge clk or negedge arst_n) begin + if(~arst_n) begin + field_storage.hwpe_job_dep.outfeat_ptr.value.value <= 32'h0; + end else begin + if(field_combo.hwpe_job_dep.outfeat_ptr.value.load_next) begin + field_storage.hwpe_job_dep.outfeat_ptr.value.value <= field_combo.hwpe_job_dep.outfeat_ptr.value.next; + end + end + end + assign hwif_out.hwpe_job_dep.outfeat_ptr.value.value = field_storage.hwpe_job_dep.outfeat_ptr.value.value; + // Field: neureka_regif.hwpe_job_dep.scale_ptr.value + always_comb begin + automatic logic [31:0] next_c; + automatic logic load_next_c; + next_c = field_storage.hwpe_job_dep.scale_ptr.value.value; + load_next_c = '0; + if(decoded_reg_strb.hwpe_job_dep.scale_ptr && decoded_req_is_wr) begin // SW write + next_c = (field_storage.hwpe_job_dep.scale_ptr.value.value & ~decoded_wr_biten[31:0]) | (decoded_wr_data[31:0] & decoded_wr_biten[31:0]); + load_next_c = '1; + end + field_combo.hwpe_job_dep.scale_ptr.value.next = next_c; + field_combo.hwpe_job_dep.scale_ptr.value.load_next = load_next_c; + end + always_ff @(posedge clk or negedge arst_n) begin + if(~arst_n) begin + field_storage.hwpe_job_dep.scale_ptr.value.value <= 32'h0; + end else begin + if(field_combo.hwpe_job_dep.scale_ptr.value.load_next) begin + field_storage.hwpe_job_dep.scale_ptr.value.value <= field_combo.hwpe_job_dep.scale_ptr.value.next; + end + end + end + assign hwif_out.hwpe_job_dep.scale_ptr.value.value = field_storage.hwpe_job_dep.scale_ptr.value.value; + // Field: neureka_regif.hwpe_job_dep.scale_shift_ptr.value + always_comb begin + automatic logic [31:0] next_c; + automatic logic load_next_c; + next_c = field_storage.hwpe_job_dep.scale_shift_ptr.value.value; + load_next_c = '0; + if(decoded_reg_strb.hwpe_job_dep.scale_shift_ptr && decoded_req_is_wr) begin // SW write + next_c = (field_storage.hwpe_job_dep.scale_shift_ptr.value.value & ~decoded_wr_biten[31:0]) | (decoded_wr_data[31:0] & decoded_wr_biten[31:0]); + load_next_c = '1; + end + field_combo.hwpe_job_dep.scale_shift_ptr.value.next = next_c; + field_combo.hwpe_job_dep.scale_shift_ptr.value.load_next = load_next_c; + end + always_ff @(posedge clk or negedge arst_n) begin + if(~arst_n) begin + field_storage.hwpe_job_dep.scale_shift_ptr.value.value <= 32'h0; + end else begin + if(field_combo.hwpe_job_dep.scale_shift_ptr.value.load_next) begin + field_storage.hwpe_job_dep.scale_shift_ptr.value.value <= field_combo.hwpe_job_dep.scale_shift_ptr.value.next; + end + end + end + assign hwif_out.hwpe_job_dep.scale_shift_ptr.value.value = field_storage.hwpe_job_dep.scale_shift_ptr.value.value; + // Field: neureka_regif.hwpe_job_dep.scale_bias_ptr.value + always_comb begin + automatic logic [31:0] next_c; + automatic logic load_next_c; + next_c = field_storage.hwpe_job_dep.scale_bias_ptr.value.value; + load_next_c = '0; + if(decoded_reg_strb.hwpe_job_dep.scale_bias_ptr && decoded_req_is_wr) begin // SW write + next_c = (field_storage.hwpe_job_dep.scale_bias_ptr.value.value & ~decoded_wr_biten[31:0]) | (decoded_wr_data[31:0] & decoded_wr_biten[31:0]); + load_next_c = '1; + end + field_combo.hwpe_job_dep.scale_bias_ptr.value.next = next_c; + field_combo.hwpe_job_dep.scale_bias_ptr.value.load_next = load_next_c; + end + always_ff @(posedge clk or negedge arst_n) begin + if(~arst_n) begin + field_storage.hwpe_job_dep.scale_bias_ptr.value.value <= 32'h0; + end else begin + if(field_combo.hwpe_job_dep.scale_bias_ptr.value.load_next) begin + field_storage.hwpe_job_dep.scale_bias_ptr.value.value <= field_combo.hwpe_job_dep.scale_bias_ptr.value.next; + end + end + end + assign hwif_out.hwpe_job_dep.scale_bias_ptr.value.value = field_storage.hwpe_job_dep.scale_bias_ptr.value.value; + // Field: neureka_regif.hwpe_job_dep.infeat_d0_str.value + always_comb begin + automatic logic [31:0] next_c; + automatic logic load_next_c; + next_c = field_storage.hwpe_job_dep.infeat_d0_str.value.value; + load_next_c = '0; + if(decoded_reg_strb.hwpe_job_dep.infeat_d0_str && decoded_req_is_wr) begin // SW write + next_c = (field_storage.hwpe_job_dep.infeat_d0_str.value.value & ~decoded_wr_biten[31:0]) | (decoded_wr_data[31:0] & decoded_wr_biten[31:0]); + load_next_c = '1; + end + field_combo.hwpe_job_dep.infeat_d0_str.value.next = next_c; + field_combo.hwpe_job_dep.infeat_d0_str.value.load_next = load_next_c; + end + always_ff @(posedge clk or negedge arst_n) begin + if(~arst_n) begin + field_storage.hwpe_job_dep.infeat_d0_str.value.value <= 32'h0; + end else begin + if(field_combo.hwpe_job_dep.infeat_d0_str.value.load_next) begin + field_storage.hwpe_job_dep.infeat_d0_str.value.value <= field_combo.hwpe_job_dep.infeat_d0_str.value.next; + end + end + end + assign hwif_out.hwpe_job_dep.infeat_d0_str.value.value = field_storage.hwpe_job_dep.infeat_d0_str.value.value; + // Field: neureka_regif.hwpe_job_dep.infeat_d1_str.value + always_comb begin + automatic logic [31:0] next_c; + automatic logic load_next_c; + next_c = field_storage.hwpe_job_dep.infeat_d1_str.value.value; + load_next_c = '0; + if(decoded_reg_strb.hwpe_job_dep.infeat_d1_str && decoded_req_is_wr) begin // SW write + next_c = (field_storage.hwpe_job_dep.infeat_d1_str.value.value & ~decoded_wr_biten[31:0]) | (decoded_wr_data[31:0] & decoded_wr_biten[31:0]); + load_next_c = '1; + end + field_combo.hwpe_job_dep.infeat_d1_str.value.next = next_c; + field_combo.hwpe_job_dep.infeat_d1_str.value.load_next = load_next_c; + end + always_ff @(posedge clk or negedge arst_n) begin + if(~arst_n) begin + field_storage.hwpe_job_dep.infeat_d1_str.value.value <= 32'h0; + end else begin + if(field_combo.hwpe_job_dep.infeat_d1_str.value.load_next) begin + field_storage.hwpe_job_dep.infeat_d1_str.value.value <= field_combo.hwpe_job_dep.infeat_d1_str.value.next; + end + end + end + assign hwif_out.hwpe_job_dep.infeat_d1_str.value.value = field_storage.hwpe_job_dep.infeat_d1_str.value.value; + // Field: neureka_regif.hwpe_job_dep.infeat_d2_str.value + always_comb begin + automatic logic [31:0] next_c; + automatic logic load_next_c; + next_c = field_storage.hwpe_job_dep.infeat_d2_str.value.value; + load_next_c = '0; + if(decoded_reg_strb.hwpe_job_dep.infeat_d2_str && decoded_req_is_wr) begin // SW write + next_c = (field_storage.hwpe_job_dep.infeat_d2_str.value.value & ~decoded_wr_biten[31:0]) | (decoded_wr_data[31:0] & decoded_wr_biten[31:0]); + load_next_c = '1; + end + field_combo.hwpe_job_dep.infeat_d2_str.value.next = next_c; + field_combo.hwpe_job_dep.infeat_d2_str.value.load_next = load_next_c; + end + always_ff @(posedge clk or negedge arst_n) begin + if(~arst_n) begin + field_storage.hwpe_job_dep.infeat_d2_str.value.value <= 32'h0; + end else begin + if(field_combo.hwpe_job_dep.infeat_d2_str.value.load_next) begin + field_storage.hwpe_job_dep.infeat_d2_str.value.value <= field_combo.hwpe_job_dep.infeat_d2_str.value.next; + end + end + end + assign hwif_out.hwpe_job_dep.infeat_d2_str.value.value = field_storage.hwpe_job_dep.infeat_d2_str.value.value; + // Field: neureka_regif.hwpe_job_dep.outfeat_d0_st.value + always_comb begin + automatic logic [31:0] next_c; + automatic logic load_next_c; + next_c = field_storage.hwpe_job_dep.outfeat_d0_st.value.value; + load_next_c = '0; + if(decoded_reg_strb.hwpe_job_dep.outfeat_d0_st && decoded_req_is_wr) begin // SW write + next_c = (field_storage.hwpe_job_dep.outfeat_d0_st.value.value & ~decoded_wr_biten[31:0]) | (decoded_wr_data[31:0] & decoded_wr_biten[31:0]); + load_next_c = '1; + end + field_combo.hwpe_job_dep.outfeat_d0_st.value.next = next_c; + field_combo.hwpe_job_dep.outfeat_d0_st.value.load_next = load_next_c; + end + always_ff @(posedge clk or negedge arst_n) begin + if(~arst_n) begin + field_storage.hwpe_job_dep.outfeat_d0_st.value.value <= 32'h0; + end else begin + if(field_combo.hwpe_job_dep.outfeat_d0_st.value.load_next) begin + field_storage.hwpe_job_dep.outfeat_d0_st.value.value <= field_combo.hwpe_job_dep.outfeat_d0_st.value.next; + end + end + end + assign hwif_out.hwpe_job_dep.outfeat_d0_st.value.value = field_storage.hwpe_job_dep.outfeat_d0_st.value.value; + // Field: neureka_regif.hwpe_job_dep.outfeat_d1_st.value + always_comb begin + automatic logic [31:0] next_c; + automatic logic load_next_c; + next_c = field_storage.hwpe_job_dep.outfeat_d1_st.value.value; + load_next_c = '0; + if(decoded_reg_strb.hwpe_job_dep.outfeat_d1_st && decoded_req_is_wr) begin // SW write + next_c = (field_storage.hwpe_job_dep.outfeat_d1_st.value.value & ~decoded_wr_biten[31:0]) | (decoded_wr_data[31:0] & decoded_wr_biten[31:0]); + load_next_c = '1; + end + field_combo.hwpe_job_dep.outfeat_d1_st.value.next = next_c; + field_combo.hwpe_job_dep.outfeat_d1_st.value.load_next = load_next_c; + end + always_ff @(posedge clk or negedge arst_n) begin + if(~arst_n) begin + field_storage.hwpe_job_dep.outfeat_d1_st.value.value <= 32'h0; + end else begin + if(field_combo.hwpe_job_dep.outfeat_d1_st.value.load_next) begin + field_storage.hwpe_job_dep.outfeat_d1_st.value.value <= field_combo.hwpe_job_dep.outfeat_d1_st.value.next; + end + end + end + assign hwif_out.hwpe_job_dep.outfeat_d1_st.value.value = field_storage.hwpe_job_dep.outfeat_d1_st.value.value; + // Field: neureka_regif.hwpe_job_dep.outfeat_d2_st.value + always_comb begin + automatic logic [31:0] next_c; + automatic logic load_next_c; + next_c = field_storage.hwpe_job_dep.outfeat_d2_st.value.value; + load_next_c = '0; + if(decoded_reg_strb.hwpe_job_dep.outfeat_d2_st && decoded_req_is_wr) begin // SW write + next_c = (field_storage.hwpe_job_dep.outfeat_d2_st.value.value & ~decoded_wr_biten[31:0]) | (decoded_wr_data[31:0] & decoded_wr_biten[31:0]); + load_next_c = '1; + end + field_combo.hwpe_job_dep.outfeat_d2_st.value.next = next_c; + field_combo.hwpe_job_dep.outfeat_d2_st.value.load_next = load_next_c; + end + always_ff @(posedge clk or negedge arst_n) begin + if(~arst_n) begin + field_storage.hwpe_job_dep.outfeat_d2_st.value.value <= 32'h0; + end else begin + if(field_combo.hwpe_job_dep.outfeat_d2_st.value.load_next) begin + field_storage.hwpe_job_dep.outfeat_d2_st.value.value <= field_combo.hwpe_job_dep.outfeat_d2_st.value.next; + end + end + end + assign hwif_out.hwpe_job_dep.outfeat_d2_st.value.value = field_storage.hwpe_job_dep.outfeat_d2_st.value.value; + // Field: neureka_regif.hwpe_job_dep.weights_d0_st.value + always_comb begin + automatic logic [31:0] next_c; + automatic logic load_next_c; + next_c = field_storage.hwpe_job_dep.weights_d0_st.value.value; + load_next_c = '0; + if(decoded_reg_strb.hwpe_job_dep.weights_d0_st && decoded_req_is_wr) begin // SW write + next_c = (field_storage.hwpe_job_dep.weights_d0_st.value.value & ~decoded_wr_biten[31:0]) | (decoded_wr_data[31:0] & decoded_wr_biten[31:0]); + load_next_c = '1; + end + field_combo.hwpe_job_dep.weights_d0_st.value.next = next_c; + field_combo.hwpe_job_dep.weights_d0_st.value.load_next = load_next_c; + end + always_ff @(posedge clk or negedge arst_n) begin + if(~arst_n) begin + field_storage.hwpe_job_dep.weights_d0_st.value.value <= 32'h0; + end else begin + if(field_combo.hwpe_job_dep.weights_d0_st.value.load_next) begin + field_storage.hwpe_job_dep.weights_d0_st.value.value <= field_combo.hwpe_job_dep.weights_d0_st.value.next; + end + end + end + assign hwif_out.hwpe_job_dep.weights_d0_st.value.value = field_storage.hwpe_job_dep.weights_d0_st.value.value; + // Field: neureka_regif.hwpe_job_dep.weights_d1_st.value + always_comb begin + automatic logic [31:0] next_c; + automatic logic load_next_c; + next_c = field_storage.hwpe_job_dep.weights_d1_st.value.value; + load_next_c = '0; + if(decoded_reg_strb.hwpe_job_dep.weights_d1_st && decoded_req_is_wr) begin // SW write + next_c = (field_storage.hwpe_job_dep.weights_d1_st.value.value & ~decoded_wr_biten[31:0]) | (decoded_wr_data[31:0] & decoded_wr_biten[31:0]); + load_next_c = '1; + end + field_combo.hwpe_job_dep.weights_d1_st.value.next = next_c; + field_combo.hwpe_job_dep.weights_d1_st.value.load_next = load_next_c; + end + always_ff @(posedge clk or negedge arst_n) begin + if(~arst_n) begin + field_storage.hwpe_job_dep.weights_d1_st.value.value <= 32'h0; + end else begin + if(field_combo.hwpe_job_dep.weights_d1_st.value.load_next) begin + field_storage.hwpe_job_dep.weights_d1_st.value.value <= field_combo.hwpe_job_dep.weights_d1_st.value.next; + end + end + end + assign hwif_out.hwpe_job_dep.weights_d1_st.value.value = field_storage.hwpe_job_dep.weights_d1_st.value.value; + // Field: neureka_regif.hwpe_job_dep.weights_d2_st.value + always_comb begin + automatic logic [31:0] next_c; + automatic logic load_next_c; + next_c = field_storage.hwpe_job_dep.weights_d2_st.value.value; + load_next_c = '0; + if(decoded_reg_strb.hwpe_job_dep.weights_d2_st && decoded_req_is_wr) begin // SW write + next_c = (field_storage.hwpe_job_dep.weights_d2_st.value.value & ~decoded_wr_biten[31:0]) | (decoded_wr_data[31:0] & decoded_wr_biten[31:0]); + load_next_c = '1; + end + field_combo.hwpe_job_dep.weights_d2_st.value.next = next_c; + field_combo.hwpe_job_dep.weights_d2_st.value.load_next = load_next_c; + end + always_ff @(posedge clk or negedge arst_n) begin + if(~arst_n) begin + field_storage.hwpe_job_dep.weights_d2_st.value.value <= 32'h0; + end else begin + if(field_combo.hwpe_job_dep.weights_d2_st.value.load_next) begin + field_storage.hwpe_job_dep.weights_d2_st.value.value <= field_combo.hwpe_job_dep.weights_d2_st.value.next; + end + end + end + assign hwif_out.hwpe_job_dep.weights_d2_st.value.value = field_storage.hwpe_job_dep.weights_d2_st.value.value; + // Field: neureka_regif.hwpe_job_dep.subtile_rem0.ki + always_comb begin + automatic logic [15:0] next_c; + automatic logic load_next_c; + next_c = field_storage.hwpe_job_dep.subtile_rem0.ki.value; + load_next_c = '0; + if(decoded_reg_strb.hwpe_job_dep.subtile_rem0 && decoded_req_is_wr) begin // SW write + next_c = (field_storage.hwpe_job_dep.subtile_rem0.ki.value & ~decoded_wr_biten[15:0]) | (decoded_wr_data[15:0] & decoded_wr_biten[15:0]); + load_next_c = '1; + end + field_combo.hwpe_job_dep.subtile_rem0.ki.next = next_c; + field_combo.hwpe_job_dep.subtile_rem0.ki.load_next = load_next_c; + end + always_ff @(posedge clk or negedge arst_n) begin + if(~arst_n) begin + field_storage.hwpe_job_dep.subtile_rem0.ki.value <= 16'h0; + end else begin + if(field_combo.hwpe_job_dep.subtile_rem0.ki.load_next) begin + field_storage.hwpe_job_dep.subtile_rem0.ki.value <= field_combo.hwpe_job_dep.subtile_rem0.ki.next; + end + end + end + assign hwif_out.hwpe_job_dep.subtile_rem0.ki.value = field_storage.hwpe_job_dep.subtile_rem0.ki.value; + // Field: neureka_regif.hwpe_job_dep.subtile_rem0.ko + always_comb begin + automatic logic [15:0] next_c; + automatic logic load_next_c; + next_c = field_storage.hwpe_job_dep.subtile_rem0.ko.value; + load_next_c = '0; + if(decoded_reg_strb.hwpe_job_dep.subtile_rem0 && decoded_req_is_wr) begin // SW write + next_c = (field_storage.hwpe_job_dep.subtile_rem0.ko.value & ~decoded_wr_biten[31:16]) | (decoded_wr_data[31:16] & decoded_wr_biten[31:16]); + load_next_c = '1; + end + field_combo.hwpe_job_dep.subtile_rem0.ko.next = next_c; + field_combo.hwpe_job_dep.subtile_rem0.ko.load_next = load_next_c; + end + always_ff @(posedge clk or negedge arst_n) begin + if(~arst_n) begin + field_storage.hwpe_job_dep.subtile_rem0.ko.value <= 16'h0; + end else begin + if(field_combo.hwpe_job_dep.subtile_rem0.ko.load_next) begin + field_storage.hwpe_job_dep.subtile_rem0.ko.value <= field_combo.hwpe_job_dep.subtile_rem0.ko.next; + end + end + end + assign hwif_out.hwpe_job_dep.subtile_rem0.ko.value = field_storage.hwpe_job_dep.subtile_rem0.ko.value; + // Field: neureka_regif.hwpe_job_dep.subtile_rem1.wo + always_comb begin + automatic logic [15:0] next_c; + automatic logic load_next_c; + next_c = field_storage.hwpe_job_dep.subtile_rem1.wo.value; + load_next_c = '0; + if(decoded_reg_strb.hwpe_job_dep.subtile_rem1 && decoded_req_is_wr) begin // SW write + next_c = (field_storage.hwpe_job_dep.subtile_rem1.wo.value & ~decoded_wr_biten[15:0]) | (decoded_wr_data[15:0] & decoded_wr_biten[15:0]); + load_next_c = '1; + end + field_combo.hwpe_job_dep.subtile_rem1.wo.next = next_c; + field_combo.hwpe_job_dep.subtile_rem1.wo.load_next = load_next_c; + end + always_ff @(posedge clk or negedge arst_n) begin + if(~arst_n) begin + field_storage.hwpe_job_dep.subtile_rem1.wo.value <= 16'h0; + end else begin + if(field_combo.hwpe_job_dep.subtile_rem1.wo.load_next) begin + field_storage.hwpe_job_dep.subtile_rem1.wo.value <= field_combo.hwpe_job_dep.subtile_rem1.wo.next; + end + end + end + assign hwif_out.hwpe_job_dep.subtile_rem1.wo.value = field_storage.hwpe_job_dep.subtile_rem1.wo.value; + // Field: neureka_regif.hwpe_job_dep.subtile_rem1.ho + always_comb begin + automatic logic [15:0] next_c; + automatic logic load_next_c; + next_c = field_storage.hwpe_job_dep.subtile_rem1.ho.value; + load_next_c = '0; + if(decoded_reg_strb.hwpe_job_dep.subtile_rem1 && decoded_req_is_wr) begin // SW write + next_c = (field_storage.hwpe_job_dep.subtile_rem1.ho.value & ~decoded_wr_biten[31:16]) | (decoded_wr_data[31:16] & decoded_wr_biten[31:16]); + load_next_c = '1; + end + field_combo.hwpe_job_dep.subtile_rem1.ho.next = next_c; + field_combo.hwpe_job_dep.subtile_rem1.ho.load_next = load_next_c; + end + always_ff @(posedge clk or negedge arst_n) begin + if(~arst_n) begin + field_storage.hwpe_job_dep.subtile_rem1.ho.value <= 16'h0; + end else begin + if(field_combo.hwpe_job_dep.subtile_rem1.ho.load_next) begin + field_storage.hwpe_job_dep.subtile_rem1.ho.value <= field_combo.hwpe_job_dep.subtile_rem1.ho.next; + end + end + end + assign hwif_out.hwpe_job_dep.subtile_rem1.ho.value = field_storage.hwpe_job_dep.subtile_rem1.ho.value; + // Field: neureka_regif.hwpe_job_dep.subtile_rem2.wi + always_comb begin + automatic logic [15:0] next_c; + automatic logic load_next_c; + next_c = field_storage.hwpe_job_dep.subtile_rem2.wi.value; + load_next_c = '0; + if(decoded_reg_strb.hwpe_job_dep.subtile_rem2 && decoded_req_is_wr) begin // SW write + next_c = (field_storage.hwpe_job_dep.subtile_rem2.wi.value & ~decoded_wr_biten[15:0]) | (decoded_wr_data[15:0] & decoded_wr_biten[15:0]); + load_next_c = '1; + end + field_combo.hwpe_job_dep.subtile_rem2.wi.next = next_c; + field_combo.hwpe_job_dep.subtile_rem2.wi.load_next = load_next_c; + end + always_ff @(posedge clk or negedge arst_n) begin + if(~arst_n) begin + field_storage.hwpe_job_dep.subtile_rem2.wi.value <= 16'h0; + end else begin + if(field_combo.hwpe_job_dep.subtile_rem2.wi.load_next) begin + field_storage.hwpe_job_dep.subtile_rem2.wi.value <= field_combo.hwpe_job_dep.subtile_rem2.wi.next; + end + end + end + assign hwif_out.hwpe_job_dep.subtile_rem2.wi.value = field_storage.hwpe_job_dep.subtile_rem2.wi.value; + // Field: neureka_regif.hwpe_job_dep.subtile_rem2.hi + always_comb begin + automatic logic [15:0] next_c; + automatic logic load_next_c; + next_c = field_storage.hwpe_job_dep.subtile_rem2.hi.value; + load_next_c = '0; + if(decoded_reg_strb.hwpe_job_dep.subtile_rem2 && decoded_req_is_wr) begin // SW write + next_c = (field_storage.hwpe_job_dep.subtile_rem2.hi.value & ~decoded_wr_biten[31:16]) | (decoded_wr_data[31:16] & decoded_wr_biten[31:16]); + load_next_c = '1; + end + field_combo.hwpe_job_dep.subtile_rem2.hi.next = next_c; + field_combo.hwpe_job_dep.subtile_rem2.hi.load_next = load_next_c; + end + always_ff @(posedge clk or negedge arst_n) begin + if(~arst_n) begin + field_storage.hwpe_job_dep.subtile_rem2.hi.value <= 16'h0; + end else begin + if(field_combo.hwpe_job_dep.subtile_rem2.hi.load_next) begin + field_storage.hwpe_job_dep.subtile_rem2.hi.value <= field_combo.hwpe_job_dep.subtile_rem2.hi.next; + end + end + end + assign hwif_out.hwpe_job_dep.subtile_rem2.hi.value = field_storage.hwpe_job_dep.subtile_rem2.hi.value; + // Field: neureka_regif.hwpe_job_dep.subtile_nb0.ki + always_comb begin + automatic logic [15:0] next_c; + automatic logic load_next_c; + next_c = field_storage.hwpe_job_dep.subtile_nb0.ki.value; + load_next_c = '0; + if(decoded_reg_strb.hwpe_job_dep.subtile_nb0 && decoded_req_is_wr) begin // SW write + next_c = (field_storage.hwpe_job_dep.subtile_nb0.ki.value & ~decoded_wr_biten[15:0]) | (decoded_wr_data[15:0] & decoded_wr_biten[15:0]); + load_next_c = '1; + end + field_combo.hwpe_job_dep.subtile_nb0.ki.next = next_c; + field_combo.hwpe_job_dep.subtile_nb0.ki.load_next = load_next_c; + end + always_ff @(posedge clk or negedge arst_n) begin + if(~arst_n) begin + field_storage.hwpe_job_dep.subtile_nb0.ki.value <= 16'h0; + end else begin + if(field_combo.hwpe_job_dep.subtile_nb0.ki.load_next) begin + field_storage.hwpe_job_dep.subtile_nb0.ki.value <= field_combo.hwpe_job_dep.subtile_nb0.ki.next; + end + end + end + assign hwif_out.hwpe_job_dep.subtile_nb0.ki.value = field_storage.hwpe_job_dep.subtile_nb0.ki.value; + // Field: neureka_regif.hwpe_job_dep.subtile_nb0.ko + always_comb begin + automatic logic [15:0] next_c; + automatic logic load_next_c; + next_c = field_storage.hwpe_job_dep.subtile_nb0.ko.value; + load_next_c = '0; + if(decoded_reg_strb.hwpe_job_dep.subtile_nb0 && decoded_req_is_wr) begin // SW write + next_c = (field_storage.hwpe_job_dep.subtile_nb0.ko.value & ~decoded_wr_biten[31:16]) | (decoded_wr_data[31:16] & decoded_wr_biten[31:16]); + load_next_c = '1; + end + field_combo.hwpe_job_dep.subtile_nb0.ko.next = next_c; + field_combo.hwpe_job_dep.subtile_nb0.ko.load_next = load_next_c; + end + always_ff @(posedge clk or negedge arst_n) begin + if(~arst_n) begin + field_storage.hwpe_job_dep.subtile_nb0.ko.value <= 16'h0; + end else begin + if(field_combo.hwpe_job_dep.subtile_nb0.ko.load_next) begin + field_storage.hwpe_job_dep.subtile_nb0.ko.value <= field_combo.hwpe_job_dep.subtile_nb0.ko.next; + end + end + end + assign hwif_out.hwpe_job_dep.subtile_nb0.ko.value = field_storage.hwpe_job_dep.subtile_nb0.ko.value; + // Field: neureka_regif.hwpe_job_dep.subtile_nb1.wo + always_comb begin + automatic logic [15:0] next_c; + automatic logic load_next_c; + next_c = field_storage.hwpe_job_dep.subtile_nb1.wo.value; + load_next_c = '0; + if(decoded_reg_strb.hwpe_job_dep.subtile_nb1 && decoded_req_is_wr) begin // SW write + next_c = (field_storage.hwpe_job_dep.subtile_nb1.wo.value & ~decoded_wr_biten[15:0]) | (decoded_wr_data[15:0] & decoded_wr_biten[15:0]); + load_next_c = '1; + end + field_combo.hwpe_job_dep.subtile_nb1.wo.next = next_c; + field_combo.hwpe_job_dep.subtile_nb1.wo.load_next = load_next_c; + end + always_ff @(posedge clk or negedge arst_n) begin + if(~arst_n) begin + field_storage.hwpe_job_dep.subtile_nb1.wo.value <= 16'h0; + end else begin + if(field_combo.hwpe_job_dep.subtile_nb1.wo.load_next) begin + field_storage.hwpe_job_dep.subtile_nb1.wo.value <= field_combo.hwpe_job_dep.subtile_nb1.wo.next; + end + end + end + assign hwif_out.hwpe_job_dep.subtile_nb1.wo.value = field_storage.hwpe_job_dep.subtile_nb1.wo.value; + // Field: neureka_regif.hwpe_job_dep.subtile_nb1.ho + always_comb begin + automatic logic [15:0] next_c; + automatic logic load_next_c; + next_c = field_storage.hwpe_job_dep.subtile_nb1.ho.value; + load_next_c = '0; + if(decoded_reg_strb.hwpe_job_dep.subtile_nb1 && decoded_req_is_wr) begin // SW write + next_c = (field_storage.hwpe_job_dep.subtile_nb1.ho.value & ~decoded_wr_biten[31:16]) | (decoded_wr_data[31:16] & decoded_wr_biten[31:16]); + load_next_c = '1; + end + field_combo.hwpe_job_dep.subtile_nb1.ho.next = next_c; + field_combo.hwpe_job_dep.subtile_nb1.ho.load_next = load_next_c; + end + always_ff @(posedge clk or negedge arst_n) begin + if(~arst_n) begin + field_storage.hwpe_job_dep.subtile_nb1.ho.value <= 16'h0; + end else begin + if(field_combo.hwpe_job_dep.subtile_nb1.ho.load_next) begin + field_storage.hwpe_job_dep.subtile_nb1.ho.value <= field_combo.hwpe_job_dep.subtile_nb1.ho.next; + end + end + end + assign hwif_out.hwpe_job_dep.subtile_nb1.ho.value = field_storage.hwpe_job_dep.subtile_nb1.ho.value; + // Field: neureka_regif.hwpe_job_dep.padding.value + always_comb begin + automatic logic [15:0] next_c; + automatic logic load_next_c; + next_c = field_storage.hwpe_job_dep.padding.value.value; + load_next_c = '0; + if(decoded_reg_strb.hwpe_job_dep.padding && decoded_req_is_wr) begin // SW write + next_c = (field_storage.hwpe_job_dep.padding.value.value & ~decoded_wr_biten[15:0]) | (decoded_wr_data[15:0] & decoded_wr_biten[15:0]); + load_next_c = '1; + end + field_combo.hwpe_job_dep.padding.value.next = next_c; + field_combo.hwpe_job_dep.padding.value.load_next = load_next_c; + end + always_ff @(posedge clk or negedge arst_n) begin + if(~arst_n) begin + field_storage.hwpe_job_dep.padding.value.value <= 16'h0; + end else begin + if(field_combo.hwpe_job_dep.padding.value.load_next) begin + field_storage.hwpe_job_dep.padding.value.value <= field_combo.hwpe_job_dep.padding.value.next; + end + end + end + assign hwif_out.hwpe_job_dep.padding.value.value = field_storage.hwpe_job_dep.padding.value.value; + // Field: neureka_regif.hwpe_job_dep.padding.left + always_comb begin + automatic logic [3:0] next_c; + automatic logic load_next_c; + next_c = field_storage.hwpe_job_dep.padding.left.value; + load_next_c = '0; + if(decoded_reg_strb.hwpe_job_dep.padding && decoded_req_is_wr) begin // SW write + next_c = (field_storage.hwpe_job_dep.padding.left.value & ~decoded_wr_biten[19:16]) | (decoded_wr_data[19:16] & decoded_wr_biten[19:16]); + load_next_c = '1; + end + field_combo.hwpe_job_dep.padding.left.next = next_c; + field_combo.hwpe_job_dep.padding.left.load_next = load_next_c; + end + always_ff @(posedge clk or negedge arst_n) begin + if(~arst_n) begin + field_storage.hwpe_job_dep.padding.left.value <= 4'h0; + end else begin + if(field_combo.hwpe_job_dep.padding.left.load_next) begin + field_storage.hwpe_job_dep.padding.left.value <= field_combo.hwpe_job_dep.padding.left.next; + end + end + end + assign hwif_out.hwpe_job_dep.padding.left.value = field_storage.hwpe_job_dep.padding.left.value; + // Field: neureka_regif.hwpe_job_dep.padding.bottom + always_comb begin + automatic logic [3:0] next_c; + automatic logic load_next_c; + next_c = field_storage.hwpe_job_dep.padding.bottom.value; + load_next_c = '0; + if(decoded_reg_strb.hwpe_job_dep.padding && decoded_req_is_wr) begin // SW write + next_c = (field_storage.hwpe_job_dep.padding.bottom.value & ~decoded_wr_biten[23:20]) | (decoded_wr_data[23:20] & decoded_wr_biten[23:20]); + load_next_c = '1; + end + field_combo.hwpe_job_dep.padding.bottom.next = next_c; + field_combo.hwpe_job_dep.padding.bottom.load_next = load_next_c; + end + always_ff @(posedge clk or negedge arst_n) begin + if(~arst_n) begin + field_storage.hwpe_job_dep.padding.bottom.value <= 4'h0; + end else begin + if(field_combo.hwpe_job_dep.padding.bottom.load_next) begin + field_storage.hwpe_job_dep.padding.bottom.value <= field_combo.hwpe_job_dep.padding.bottom.next; + end + end + end + assign hwif_out.hwpe_job_dep.padding.bottom.value = field_storage.hwpe_job_dep.padding.bottom.value; + // Field: neureka_regif.hwpe_job_dep.padding.right + always_comb begin + automatic logic [3:0] next_c; + automatic logic load_next_c; + next_c = field_storage.hwpe_job_dep.padding.right.value; + load_next_c = '0; + if(decoded_reg_strb.hwpe_job_dep.padding && decoded_req_is_wr) begin // SW write + next_c = (field_storage.hwpe_job_dep.padding.right.value & ~decoded_wr_biten[27:24]) | (decoded_wr_data[27:24] & decoded_wr_biten[27:24]); + load_next_c = '1; + end + field_combo.hwpe_job_dep.padding.right.next = next_c; + field_combo.hwpe_job_dep.padding.right.load_next = load_next_c; + end + always_ff @(posedge clk or negedge arst_n) begin + if(~arst_n) begin + field_storage.hwpe_job_dep.padding.right.value <= 4'h0; + end else begin + if(field_combo.hwpe_job_dep.padding.right.load_next) begin + field_storage.hwpe_job_dep.padding.right.value <= field_combo.hwpe_job_dep.padding.right.next; + end + end + end + assign hwif_out.hwpe_job_dep.padding.right.value = field_storage.hwpe_job_dep.padding.right.value; + // Field: neureka_regif.hwpe_job_dep.padding.top + always_comb begin + automatic logic [3:0] next_c; + automatic logic load_next_c; + next_c = field_storage.hwpe_job_dep.padding.top.value; + load_next_c = '0; + if(decoded_reg_strb.hwpe_job_dep.padding && decoded_req_is_wr) begin // SW write + next_c = (field_storage.hwpe_job_dep.padding.top.value & ~decoded_wr_biten[31:28]) | (decoded_wr_data[31:28] & decoded_wr_biten[31:28]); + load_next_c = '1; + end + field_combo.hwpe_job_dep.padding.top.next = next_c; + field_combo.hwpe_job_dep.padding.top.load_next = load_next_c; + end + always_ff @(posedge clk or negedge arst_n) begin + if(~arst_n) begin + field_storage.hwpe_job_dep.padding.top.value <= 4'h0; + end else begin + if(field_combo.hwpe_job_dep.padding.top.load_next) begin + field_storage.hwpe_job_dep.padding.top.value <= field_combo.hwpe_job_dep.padding.top.next; + end + end + end + assign hwif_out.hwpe_job_dep.padding.top.value = field_storage.hwpe_job_dep.padding.top.value; + // Field: neureka_regif.hwpe_job_dep.weight_offset.value + always_comb begin + automatic logic [31:0] next_c; + automatic logic load_next_c; + next_c = field_storage.hwpe_job_dep.weight_offset.value.value; + load_next_c = '0; + if(decoded_reg_strb.hwpe_job_dep.weight_offset && decoded_req_is_wr) begin // SW write + next_c = (field_storage.hwpe_job_dep.weight_offset.value.value & ~decoded_wr_biten[31:0]) | (decoded_wr_data[31:0] & decoded_wr_biten[31:0]); + load_next_c = '1; + end + field_combo.hwpe_job_dep.weight_offset.value.next = next_c; + field_combo.hwpe_job_dep.weight_offset.value.load_next = load_next_c; + end + always_ff @(posedge clk or negedge arst_n) begin + if(~arst_n) begin + field_storage.hwpe_job_dep.weight_offset.value.value <= 32'h0; + end else begin + if(field_combo.hwpe_job_dep.weight_offset.value.load_next) begin + field_storage.hwpe_job_dep.weight_offset.value.value <= field_combo.hwpe_job_dep.weight_offset.value.next; + end + end + end + assign hwif_out.hwpe_job_dep.weight_offset.value.value = field_storage.hwpe_job_dep.weight_offset.value.value; + // Field: neureka_regif.hwpe_job_dep.filter_mask.left + always_comb begin + automatic logic [7:0] next_c; + automatic logic load_next_c; + next_c = field_storage.hwpe_job_dep.filter_mask.left.value; + load_next_c = '0; + if(decoded_reg_strb.hwpe_job_dep.filter_mask && decoded_req_is_wr) begin // SW write + next_c = (field_storage.hwpe_job_dep.filter_mask.left.value & ~decoded_wr_biten[7:0]) | (decoded_wr_data[7:0] & decoded_wr_biten[7:0]); + load_next_c = '1; + end + field_combo.hwpe_job_dep.filter_mask.left.next = next_c; + field_combo.hwpe_job_dep.filter_mask.left.load_next = load_next_c; + end + always_ff @(posedge clk or negedge arst_n) begin + if(~arst_n) begin + field_storage.hwpe_job_dep.filter_mask.left.value <= 8'h0; + end else begin + if(field_combo.hwpe_job_dep.filter_mask.left.load_next) begin + field_storage.hwpe_job_dep.filter_mask.left.value <= field_combo.hwpe_job_dep.filter_mask.left.next; + end + end + end + assign hwif_out.hwpe_job_dep.filter_mask.left.value = field_storage.hwpe_job_dep.filter_mask.left.value; + // Field: neureka_regif.hwpe_job_dep.filter_mask.bottom + always_comb begin + automatic logic [7:0] next_c; + automatic logic load_next_c; + next_c = field_storage.hwpe_job_dep.filter_mask.bottom.value; + load_next_c = '0; + if(decoded_reg_strb.hwpe_job_dep.filter_mask && decoded_req_is_wr) begin // SW write + next_c = (field_storage.hwpe_job_dep.filter_mask.bottom.value & ~decoded_wr_biten[15:8]) | (decoded_wr_data[15:8] & decoded_wr_biten[15:8]); + load_next_c = '1; + end + field_combo.hwpe_job_dep.filter_mask.bottom.next = next_c; + field_combo.hwpe_job_dep.filter_mask.bottom.load_next = load_next_c; + end + always_ff @(posedge clk or negedge arst_n) begin + if(~arst_n) begin + field_storage.hwpe_job_dep.filter_mask.bottom.value <= 8'h0; + end else begin + if(field_combo.hwpe_job_dep.filter_mask.bottom.load_next) begin + field_storage.hwpe_job_dep.filter_mask.bottom.value <= field_combo.hwpe_job_dep.filter_mask.bottom.next; + end + end + end + assign hwif_out.hwpe_job_dep.filter_mask.bottom.value = field_storage.hwpe_job_dep.filter_mask.bottom.value; + // Field: neureka_regif.hwpe_job_dep.filter_mask.right + always_comb begin + automatic logic [7:0] next_c; + automatic logic load_next_c; + next_c = field_storage.hwpe_job_dep.filter_mask.right.value; + load_next_c = '0; + if(decoded_reg_strb.hwpe_job_dep.filter_mask && decoded_req_is_wr) begin // SW write + next_c = (field_storage.hwpe_job_dep.filter_mask.right.value & ~decoded_wr_biten[23:16]) | (decoded_wr_data[23:16] & decoded_wr_biten[23:16]); + load_next_c = '1; + end + field_combo.hwpe_job_dep.filter_mask.right.next = next_c; + field_combo.hwpe_job_dep.filter_mask.right.load_next = load_next_c; + end + always_ff @(posedge clk or negedge arst_n) begin + if(~arst_n) begin + field_storage.hwpe_job_dep.filter_mask.right.value <= 8'h0; + end else begin + if(field_combo.hwpe_job_dep.filter_mask.right.load_next) begin + field_storage.hwpe_job_dep.filter_mask.right.value <= field_combo.hwpe_job_dep.filter_mask.right.next; + end + end + end + assign hwif_out.hwpe_job_dep.filter_mask.right.value = field_storage.hwpe_job_dep.filter_mask.right.value; + // Field: neureka_regif.hwpe_job_dep.filter_mask.top + always_comb begin + automatic logic [7:0] next_c; + automatic logic load_next_c; + next_c = field_storage.hwpe_job_dep.filter_mask.top.value; + load_next_c = '0; + if(decoded_reg_strb.hwpe_job_dep.filter_mask && decoded_req_is_wr) begin // SW write + next_c = (field_storage.hwpe_job_dep.filter_mask.top.value & ~decoded_wr_biten[31:24]) | (decoded_wr_data[31:24] & decoded_wr_biten[31:24]); + load_next_c = '1; + end + field_combo.hwpe_job_dep.filter_mask.top.next = next_c; + field_combo.hwpe_job_dep.filter_mask.top.load_next = load_next_c; + end + always_ff @(posedge clk or negedge arst_n) begin + if(~arst_n) begin + field_storage.hwpe_job_dep.filter_mask.top.value <= 8'h0; + end else begin + if(field_combo.hwpe_job_dep.filter_mask.top.load_next) begin + field_storage.hwpe_job_dep.filter_mask.top.value <= field_combo.hwpe_job_dep.filter_mask.top.next; + end + end + end + assign hwif_out.hwpe_job_dep.filter_mask.top.value = field_storage.hwpe_job_dep.filter_mask.top.value; + // Field: neureka_regif.hwpe_job_dep.config0.wbits + always_comb begin + automatic logic [2:0] next_c; + automatic logic load_next_c; + next_c = field_storage.hwpe_job_dep.config0.wbits.value; + load_next_c = '0; + if(decoded_reg_strb.hwpe_job_dep.config0 && decoded_req_is_wr) begin // SW write + next_c = (field_storage.hwpe_job_dep.config0.wbits.value & ~decoded_wr_biten[2:0]) | (decoded_wr_data[2:0] & decoded_wr_biten[2:0]); + load_next_c = '1; + end + field_combo.hwpe_job_dep.config0.wbits.next = next_c; + field_combo.hwpe_job_dep.config0.wbits.load_next = load_next_c; + end + always_ff @(posedge clk or negedge arst_n) begin + if(~arst_n) begin + field_storage.hwpe_job_dep.config0.wbits.value <= 3'h0; + end else begin + if(field_combo.hwpe_job_dep.config0.wbits.load_next) begin + field_storage.hwpe_job_dep.config0.wbits.value <= field_combo.hwpe_job_dep.config0.wbits.next; + end + end + end + assign hwif_out.hwpe_job_dep.config0.wbits.value = field_storage.hwpe_job_dep.config0.wbits.value; + // Field: neureka_regif.hwpe_job_dep.config0.reserved2 + always_comb begin + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.hwpe_job_dep.config0.reserved2.value; + load_next_c = '0; + if(decoded_reg_strb.hwpe_job_dep.config0 && decoded_req_is_wr) begin // SW write + next_c = (field_storage.hwpe_job_dep.config0.reserved2.value & ~decoded_wr_biten[3:3]) | (decoded_wr_data[3:3] & decoded_wr_biten[3:3]); + load_next_c = '1; + end + field_combo.hwpe_job_dep.config0.reserved2.next = next_c; + field_combo.hwpe_job_dep.config0.reserved2.load_next = load_next_c; + end + always_ff @(posedge clk or negedge arst_n) begin + if(~arst_n) begin + field_storage.hwpe_job_dep.config0.reserved2.value <= 1'h0; + end else begin + if(field_combo.hwpe_job_dep.config0.reserved2.load_next) begin + field_storage.hwpe_job_dep.config0.reserved2.value <= field_combo.hwpe_job_dep.config0.reserved2.next; + end + end + end + assign hwif_out.hwpe_job_dep.config0.reserved2.value = field_storage.hwpe_job_dep.config0.reserved2.value; + // Field: neureka_regif.hwpe_job_dep.config0.streamout_quant + always_comb begin + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.hwpe_job_dep.config0.streamout_quant.value; + load_next_c = '0; + if(decoded_reg_strb.hwpe_job_dep.config0 && decoded_req_is_wr) begin // SW write + next_c = (field_storage.hwpe_job_dep.config0.streamout_quant.value & ~decoded_wr_biten[4:4]) | (decoded_wr_data[4:4] & decoded_wr_biten[4:4]); + load_next_c = '1; + end + field_combo.hwpe_job_dep.config0.streamout_quant.next = next_c; + field_combo.hwpe_job_dep.config0.streamout_quant.load_next = load_next_c; + end + always_ff @(posedge clk or negedge arst_n) begin + if(~arst_n) begin + field_storage.hwpe_job_dep.config0.streamout_quant.value <= 1'h0; + end else begin + if(field_combo.hwpe_job_dep.config0.streamout_quant.load_next) begin + field_storage.hwpe_job_dep.config0.streamout_quant.value <= field_combo.hwpe_job_dep.config0.streamout_quant.next; + end + end + end + assign hwif_out.hwpe_job_dep.config0.streamout_quant.value = field_storage.hwpe_job_dep.config0.streamout_quant.value; + // Field: neureka_regif.hwpe_job_dep.config0.filter_mode + always_comb begin + automatic logic [1:0] next_c; + automatic logic load_next_c; + next_c = field_storage.hwpe_job_dep.config0.filter_mode.value; + load_next_c = '0; + if(decoded_reg_strb.hwpe_job_dep.config0 && decoded_req_is_wr) begin // SW write + next_c = (field_storage.hwpe_job_dep.config0.filter_mode.value & ~decoded_wr_biten[6:5]) | (decoded_wr_data[6:5] & decoded_wr_biten[6:5]); + load_next_c = '1; + end + field_combo.hwpe_job_dep.config0.filter_mode.next = next_c; + field_combo.hwpe_job_dep.config0.filter_mode.load_next = load_next_c; + end + always_ff @(posedge clk or negedge arst_n) begin + if(~arst_n) begin + field_storage.hwpe_job_dep.config0.filter_mode.value <= 2'h0; + end else begin + if(field_combo.hwpe_job_dep.config0.filter_mode.load_next) begin + field_storage.hwpe_job_dep.config0.filter_mode.value <= field_combo.hwpe_job_dep.config0.filter_mode.next; + end + end + end + assign hwif_out.hwpe_job_dep.config0.filter_mode.value = field_storage.hwpe_job_dep.config0.filter_mode.value; + // Field: neureka_regif.hwpe_job_dep.config0.mode_linear + always_comb begin + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.hwpe_job_dep.config0.mode_linear.value; + load_next_c = '0; + if(decoded_reg_strb.hwpe_job_dep.config0 && decoded_req_is_wr) begin // SW write + next_c = (field_storage.hwpe_job_dep.config0.mode_linear.value & ~decoded_wr_biten[7:7]) | (decoded_wr_data[7:7] & decoded_wr_biten[7:7]); + load_next_c = '1; + end + field_combo.hwpe_job_dep.config0.mode_linear.next = next_c; + field_combo.hwpe_job_dep.config0.mode_linear.load_next = load_next_c; + end + always_ff @(posedge clk or negedge arst_n) begin + if(~arst_n) begin + field_storage.hwpe_job_dep.config0.mode_linear.value <= 1'h0; + end else begin + if(field_combo.hwpe_job_dep.config0.mode_linear.load_next) begin + field_storage.hwpe_job_dep.config0.mode_linear.value <= field_combo.hwpe_job_dep.config0.mode_linear.next; + end + end + end + assign hwif_out.hwpe_job_dep.config0.mode_linear.value = field_storage.hwpe_job_dep.config0.mode_linear.value; + // Field: neureka_regif.hwpe_job_dep.config0.mode_strided + always_comb begin + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.hwpe_job_dep.config0.mode_strided.value; + load_next_c = '0; + if(decoded_reg_strb.hwpe_job_dep.config0 && decoded_req_is_wr) begin // SW write + next_c = (field_storage.hwpe_job_dep.config0.mode_strided.value & ~decoded_wr_biten[8:8]) | (decoded_wr_data[8:8] & decoded_wr_biten[8:8]); + load_next_c = '1; + end + field_combo.hwpe_job_dep.config0.mode_strided.next = next_c; + field_combo.hwpe_job_dep.config0.mode_strided.load_next = load_next_c; + end + always_ff @(posedge clk or negedge arst_n) begin + if(~arst_n) begin + field_storage.hwpe_job_dep.config0.mode_strided.value <= 1'h0; + end else begin + if(field_combo.hwpe_job_dep.config0.mode_strided.load_next) begin + field_storage.hwpe_job_dep.config0.mode_strided.value <= field_combo.hwpe_job_dep.config0.mode_strided.next; + end + end + end + assign hwif_out.hwpe_job_dep.config0.mode_strided.value = field_storage.hwpe_job_dep.config0.mode_strided.value; + // Field: neureka_regif.hwpe_job_dep.config0.wmem + always_comb begin + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.hwpe_job_dep.config0.wmem.value; + load_next_c = '0; + if(decoded_reg_strb.hwpe_job_dep.config0 && decoded_req_is_wr) begin // SW write + next_c = (field_storage.hwpe_job_dep.config0.wmem.value & ~decoded_wr_biten[9:9]) | (decoded_wr_data[9:9] & decoded_wr_biten[9:9]); + load_next_c = '1; + end + field_combo.hwpe_job_dep.config0.wmem.next = next_c; + field_combo.hwpe_job_dep.config0.wmem.load_next = load_next_c; + end + always_ff @(posedge clk or negedge arst_n) begin + if(~arst_n) begin + field_storage.hwpe_job_dep.config0.wmem.value <= 1'h0; + end else begin + if(field_combo.hwpe_job_dep.config0.wmem.load_next) begin + field_storage.hwpe_job_dep.config0.wmem.value <= field_combo.hwpe_job_dep.config0.wmem.next; + end + end + end + assign hwif_out.hwpe_job_dep.config0.wmem.value = field_storage.hwpe_job_dep.config0.wmem.value; + // Field: neureka_regif.hwpe_job_dep.config0.prefetch + always_comb begin + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.hwpe_job_dep.config0.prefetch.value; + load_next_c = '0; + if(decoded_reg_strb.hwpe_job_dep.config0 && decoded_req_is_wr) begin // SW write + next_c = (field_storage.hwpe_job_dep.config0.prefetch.value & ~decoded_wr_biten[10:10]) | (decoded_wr_data[10:10] & decoded_wr_biten[10:10]); + load_next_c = '1; + end + field_combo.hwpe_job_dep.config0.prefetch.next = next_c; + field_combo.hwpe_job_dep.config0.prefetch.load_next = load_next_c; + end + always_ff @(posedge clk or negedge arst_n) begin + if(~arst_n) begin + field_storage.hwpe_job_dep.config0.prefetch.value <= 1'h0; + end else begin + if(field_combo.hwpe_job_dep.config0.prefetch.load_next) begin + field_storage.hwpe_job_dep.config0.prefetch.value <= field_combo.hwpe_job_dep.config0.prefetch.next; + end + end + end + assign hwif_out.hwpe_job_dep.config0.prefetch.value = field_storage.hwpe_job_dep.config0.prefetch.value; + // Field: neureka_regif.hwpe_job_dep.config0.rounding + always_comb begin + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.hwpe_job_dep.config0.rounding.value; + load_next_c = '0; + if(decoded_reg_strb.hwpe_job_dep.config0 && decoded_req_is_wr) begin // SW write + next_c = (field_storage.hwpe_job_dep.config0.rounding.value & ~decoded_wr_biten[11:11]) | (decoded_wr_data[11:11] & decoded_wr_biten[11:11]); + load_next_c = '1; + end + field_combo.hwpe_job_dep.config0.rounding.next = next_c; + field_combo.hwpe_job_dep.config0.rounding.load_next = load_next_c; + end + always_ff @(posedge clk or negedge arst_n) begin + if(~arst_n) begin + field_storage.hwpe_job_dep.config0.rounding.value <= 1'h0; + end else begin + if(field_combo.hwpe_job_dep.config0.rounding.load_next) begin + field_storage.hwpe_job_dep.config0.rounding.value <= field_combo.hwpe_job_dep.config0.rounding.next; + end + end + end + assign hwif_out.hwpe_job_dep.config0.rounding.value = field_storage.hwpe_job_dep.config0.rounding.value; + // Field: neureka_regif.hwpe_job_dep.config0.norm_mode + always_comb begin + automatic logic [1:0] next_c; + automatic logic load_next_c; + next_c = field_storage.hwpe_job_dep.config0.norm_mode.value; + load_next_c = '0; + if(decoded_reg_strb.hwpe_job_dep.config0 && decoded_req_is_wr) begin // SW write + next_c = (field_storage.hwpe_job_dep.config0.norm_mode.value & ~decoded_wr_biten[13:12]) | (decoded_wr_data[13:12] & decoded_wr_biten[13:12]); + load_next_c = '1; + end + field_combo.hwpe_job_dep.config0.norm_mode.next = next_c; + field_combo.hwpe_job_dep.config0.norm_mode.load_next = load_next_c; + end + always_ff @(posedge clk or negedge arst_n) begin + if(~arst_n) begin + field_storage.hwpe_job_dep.config0.norm_mode.value <= 2'h0; + end else begin + if(field_combo.hwpe_job_dep.config0.norm_mode.load_next) begin + field_storage.hwpe_job_dep.config0.norm_mode.value <= field_combo.hwpe_job_dep.config0.norm_mode.next; + end + end + end + assign hwif_out.hwpe_job_dep.config0.norm_mode.value = field_storage.hwpe_job_dep.config0.norm_mode.value; + // Field: neureka_regif.hwpe_job_dep.config0.streamin + always_comb begin + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.hwpe_job_dep.config0.streamin.value; + load_next_c = '0; + if(decoded_reg_strb.hwpe_job_dep.config0 && decoded_req_is_wr) begin // SW write + next_c = (field_storage.hwpe_job_dep.config0.streamin.value & ~decoded_wr_biten[14:14]) | (decoded_wr_data[14:14] & decoded_wr_biten[14:14]); + load_next_c = '1; + end + field_combo.hwpe_job_dep.config0.streamin.next = next_c; + field_combo.hwpe_job_dep.config0.streamin.load_next = load_next_c; + end + always_ff @(posedge clk or negedge arst_n) begin + if(~arst_n) begin + field_storage.hwpe_job_dep.config0.streamin.value <= 1'h0; + end else begin + if(field_combo.hwpe_job_dep.config0.streamin.load_next) begin + field_storage.hwpe_job_dep.config0.streamin.value <= field_combo.hwpe_job_dep.config0.streamin.next; + end + end + end + assign hwif_out.hwpe_job_dep.config0.streamin.value = field_storage.hwpe_job_dep.config0.streamin.value; + // Field: neureka_regif.hwpe_job_dep.config0.streamin_mode + always_comb begin + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.hwpe_job_dep.config0.streamin_mode.value; + load_next_c = '0; + if(decoded_reg_strb.hwpe_job_dep.config0 && decoded_req_is_wr) begin // SW write + next_c = (field_storage.hwpe_job_dep.config0.streamin_mode.value & ~decoded_wr_biten[15:15]) | (decoded_wr_data[15:15] & decoded_wr_biten[15:15]); + load_next_c = '1; + end + field_combo.hwpe_job_dep.config0.streamin_mode.next = next_c; + field_combo.hwpe_job_dep.config0.streamin_mode.load_next = load_next_c; + end + always_ff @(posedge clk or negedge arst_n) begin + if(~arst_n) begin + field_storage.hwpe_job_dep.config0.streamin_mode.value <= 1'h0; + end else begin + if(field_combo.hwpe_job_dep.config0.streamin_mode.load_next) begin + field_storage.hwpe_job_dep.config0.streamin_mode.value <= field_combo.hwpe_job_dep.config0.streamin_mode.next; + end + end + end + assign hwif_out.hwpe_job_dep.config0.streamin_mode.value = field_storage.hwpe_job_dep.config0.streamin_mode.value; + // Field: neureka_regif.hwpe_job_dep.config0.shift_reqnt + always_comb begin + automatic logic [4:0] next_c; + automatic logic load_next_c; + next_c = field_storage.hwpe_job_dep.config0.shift_reqnt.value; + load_next_c = '0; + if(decoded_reg_strb.hwpe_job_dep.config0 && decoded_req_is_wr) begin // SW write + next_c = (field_storage.hwpe_job_dep.config0.shift_reqnt.value & ~decoded_wr_biten[20:16]) | (decoded_wr_data[20:16] & decoded_wr_biten[20:16]); + load_next_c = '1; + end + field_combo.hwpe_job_dep.config0.shift_reqnt.next = next_c; + field_combo.hwpe_job_dep.config0.shift_reqnt.load_next = load_next_c; + end + always_ff @(posedge clk or negedge arst_n) begin + if(~arst_n) begin + field_storage.hwpe_job_dep.config0.shift_reqnt.value <= 5'h0; + end else begin + if(field_combo.hwpe_job_dep.config0.shift_reqnt.load_next) begin + field_storage.hwpe_job_dep.config0.shift_reqnt.value <= field_combo.hwpe_job_dep.config0.shift_reqnt.next; + end + end + end + assign hwif_out.hwpe_job_dep.config0.shift_reqnt.value = field_storage.hwpe_job_dep.config0.shift_reqnt.value; + // Field: neureka_regif.hwpe_job_dep.config0.quant_mode + always_comb begin + automatic logic [1:0] next_c; + automatic logic load_next_c; + next_c = field_storage.hwpe_job_dep.config0.quant_mode.value; + load_next_c = '0; + if(decoded_reg_strb.hwpe_job_dep.config0 && decoded_req_is_wr) begin // SW write + next_c = (field_storage.hwpe_job_dep.config0.quant_mode.value & ~decoded_wr_biten[22:21]) | (decoded_wr_data[22:21] & decoded_wr_biten[22:21]); + load_next_c = '1; + end + field_combo.hwpe_job_dep.config0.quant_mode.next = next_c; + field_combo.hwpe_job_dep.config0.quant_mode.load_next = load_next_c; + end + always_ff @(posedge clk or negedge arst_n) begin + if(~arst_n) begin + field_storage.hwpe_job_dep.config0.quant_mode.value <= 2'h0; + end else begin + if(field_combo.hwpe_job_dep.config0.quant_mode.load_next) begin + field_storage.hwpe_job_dep.config0.quant_mode.value <= field_combo.hwpe_job_dep.config0.quant_mode.next; + end + end + end + assign hwif_out.hwpe_job_dep.config0.quant_mode.value = field_storage.hwpe_job_dep.config0.quant_mode.value; + // Field: neureka_regif.hwpe_job_dep.config0.relu + always_comb begin + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.hwpe_job_dep.config0.relu.value; + load_next_c = '0; + if(decoded_reg_strb.hwpe_job_dep.config0 && decoded_req_is_wr) begin // SW write + next_c = (field_storage.hwpe_job_dep.config0.relu.value & ~decoded_wr_biten[23:23]) | (decoded_wr_data[23:23] & decoded_wr_biten[23:23]); + load_next_c = '1; + end + field_combo.hwpe_job_dep.config0.relu.next = next_c; + field_combo.hwpe_job_dep.config0.relu.load_next = load_next_c; + end + always_ff @(posedge clk or negedge arst_n) begin + if(~arst_n) begin + field_storage.hwpe_job_dep.config0.relu.value <= 1'h0; + end else begin + if(field_combo.hwpe_job_dep.config0.relu.load_next) begin + field_storage.hwpe_job_dep.config0.relu.value <= field_combo.hwpe_job_dep.config0.relu.next; + end + end + end + assign hwif_out.hwpe_job_dep.config0.relu.value = field_storage.hwpe_job_dep.config0.relu.value; + // Field: neureka_regif.hwpe_job_dep.config0.norm_option_shift + always_comb begin + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.hwpe_job_dep.config0.norm_option_shift.value; + load_next_c = '0; + if(decoded_reg_strb.hwpe_job_dep.config0 && decoded_req_is_wr) begin // SW write + next_c = (field_storage.hwpe_job_dep.config0.norm_option_shift.value & ~decoded_wr_biten[24:24]) | (decoded_wr_data[24:24] & decoded_wr_biten[24:24]); + load_next_c = '1; + end + field_combo.hwpe_job_dep.config0.norm_option_shift.next = next_c; + field_combo.hwpe_job_dep.config0.norm_option_shift.load_next = load_next_c; + end + always_ff @(posedge clk or negedge arst_n) begin + if(~arst_n) begin + field_storage.hwpe_job_dep.config0.norm_option_shift.value <= 1'h0; + end else begin + if(field_combo.hwpe_job_dep.config0.norm_option_shift.load_next) begin + field_storage.hwpe_job_dep.config0.norm_option_shift.value <= field_combo.hwpe_job_dep.config0.norm_option_shift.next; + end + end + end + assign hwif_out.hwpe_job_dep.config0.norm_option_shift.value = field_storage.hwpe_job_dep.config0.norm_option_shift.value; + // Field: neureka_regif.hwpe_job_dep.config0.norm_option_bias + always_comb begin + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.hwpe_job_dep.config0.norm_option_bias.value; + load_next_c = '0; + if(decoded_reg_strb.hwpe_job_dep.config0 && decoded_req_is_wr) begin // SW write + next_c = (field_storage.hwpe_job_dep.config0.norm_option_bias.value & ~decoded_wr_biten[25:25]) | (decoded_wr_data[25:25] & decoded_wr_biten[25:25]); + load_next_c = '1; + end + field_combo.hwpe_job_dep.config0.norm_option_bias.next = next_c; + field_combo.hwpe_job_dep.config0.norm_option_bias.load_next = load_next_c; + end + always_ff @(posedge clk or negedge arst_n) begin + if(~arst_n) begin + field_storage.hwpe_job_dep.config0.norm_option_bias.value <= 1'h0; + end else begin + if(field_combo.hwpe_job_dep.config0.norm_option_bias.load_next) begin + field_storage.hwpe_job_dep.config0.norm_option_bias.value <= field_combo.hwpe_job_dep.config0.norm_option_bias.next; + end + end + end + assign hwif_out.hwpe_job_dep.config0.norm_option_bias.value = field_storage.hwpe_job_dep.config0.norm_option_bias.value; + // Field: neureka_regif.hwpe_job_dep.config0.feat_broadcast + always_comb begin + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.hwpe_job_dep.config0.feat_broadcast.value; + load_next_c = '0; + if(decoded_reg_strb.hwpe_job_dep.config0 && decoded_req_is_wr) begin // SW write + next_c = (field_storage.hwpe_job_dep.config0.feat_broadcast.value & ~decoded_wr_biten[26:26]) | (decoded_wr_data[26:26] & decoded_wr_biten[26:26]); + load_next_c = '1; + end + field_combo.hwpe_job_dep.config0.feat_broadcast.next = next_c; + field_combo.hwpe_job_dep.config0.feat_broadcast.load_next = load_next_c; + end + always_ff @(posedge clk or negedge arst_n) begin + if(~arst_n) begin + field_storage.hwpe_job_dep.config0.feat_broadcast.value <= 1'h0; + end else begin + if(field_combo.hwpe_job_dep.config0.feat_broadcast.load_next) begin + field_storage.hwpe_job_dep.config0.feat_broadcast.value <= field_combo.hwpe_job_dep.config0.feat_broadcast.next; + end + end + end + assign hwif_out.hwpe_job_dep.config0.feat_broadcast.value = field_storage.hwpe_job_dep.config0.feat_broadcast.value; + // Field: neureka_regif.hwpe_job_dep.config0.reserved + always_comb begin + automatic logic [4:0] next_c; + automatic logic load_next_c; + next_c = field_storage.hwpe_job_dep.config0.reserved.value; + load_next_c = '0; + if(decoded_reg_strb.hwpe_job_dep.config0 && decoded_req_is_wr) begin // SW write + next_c = (field_storage.hwpe_job_dep.config0.reserved.value & ~decoded_wr_biten[31:27]) | (decoded_wr_data[31:27] & decoded_wr_biten[31:27]); + load_next_c = '1; + end + field_combo.hwpe_job_dep.config0.reserved.next = next_c; + field_combo.hwpe_job_dep.config0.reserved.load_next = load_next_c; + end + always_ff @(posedge clk or negedge arst_n) begin + if(~arst_n) begin + field_storage.hwpe_job_dep.config0.reserved.value <= 5'h0; + end else begin + if(field_combo.hwpe_job_dep.config0.reserved.load_next) begin + field_storage.hwpe_job_dep.config0.reserved.value <= field_combo.hwpe_job_dep.config0.reserved.next; + end + end + end + assign hwif_out.hwpe_job_dep.config0.reserved.value = field_storage.hwpe_job_dep.config0.reserved.value; + // Field: neureka_regif.hwpe_job_dep.streamin_ptr.value + always_comb begin + automatic logic [31:0] next_c; + automatic logic load_next_c; + next_c = field_storage.hwpe_job_dep.streamin_ptr.value.value; + load_next_c = '0; + if(decoded_reg_strb.hwpe_job_dep.streamin_ptr && decoded_req_is_wr) begin // SW write + next_c = (field_storage.hwpe_job_dep.streamin_ptr.value.value & ~decoded_wr_biten[31:0]) | (decoded_wr_data[31:0] & decoded_wr_biten[31:0]); + load_next_c = '1; + end + field_combo.hwpe_job_dep.streamin_ptr.value.next = next_c; + field_combo.hwpe_job_dep.streamin_ptr.value.load_next = load_next_c; + end + always_ff @(posedge clk or negedge arst_n) begin + if(~arst_n) begin + field_storage.hwpe_job_dep.streamin_ptr.value.value <= 32'h0; + end else begin + if(field_combo.hwpe_job_dep.streamin_ptr.value.load_next) begin + field_storage.hwpe_job_dep.streamin_ptr.value.value <= field_combo.hwpe_job_dep.streamin_ptr.value.next; + end + end + end + assign hwif_out.hwpe_job_dep.streamin_ptr.value.value = field_storage.hwpe_job_dep.streamin_ptr.value.value; + assign hwif_out.hwpe_job_indep.reserved.reserved.value = 32'h0; + + //-------------------------------------------------------------------------- + // Write response + //-------------------------------------------------------------------------- + assign cpuif_wr_ack = decoded_req & decoded_req_is_wr; + // Writes are always granted with no error response + assign cpuif_wr_err = '0; + + //-------------------------------------------------------------------------- + // Readback + //-------------------------------------------------------------------------- + + logic readback_err; + logic readback_done; + logic [31:0] readback_data; + + // Assign readback values to a flattened array + logic [31:0] readback_array[34]; + assign readback_array[0][1:0] = '0; + assign readback_array[0][31:2] = (decoded_reg_strb.hwpe_ctrl.commit_trigger && !decoded_req_is_wr) ? 30'h0 : '0; + assign readback_array[1][31:0] = (decoded_reg_strb.hwpe_ctrl.acquire && !decoded_req_is_wr) ? hwif_in.hwpe_ctrl.acquire.acquire.next : '0; + assign readback_array[2][31:0] = (decoded_reg_strb.hwpe_ctrl.reserved0 && !decoded_req_is_wr) ? 32'h0 : '0; + assign readback_array[3][31:0] = (decoded_reg_strb.hwpe_ctrl.status && !decoded_req_is_wr) ? hwif_in.hwpe_ctrl.status.status0.next : '0; + assign readback_array[4][7:0] = (decoded_reg_strb.hwpe_ctrl.running_job && !decoded_req_is_wr) ? hwif_in.hwpe_ctrl.running_job.running_job.next : '0; + assign readback_array[4][31:8] = (decoded_reg_strb.hwpe_ctrl.running_job && !decoded_req_is_wr) ? 24'h0 : '0; + assign readback_array[5][1:0] = '0; + assign readback_array[5][31:2] = (decoded_reg_strb.hwpe_ctrl.soft_clear && !decoded_req_is_wr) ? 30'h0 : '0; + assign readback_array[6][31:0] = (decoded_reg_strb.hwpe_ctrl.reserved1 && !decoded_req_is_wr) ? 32'h0 : '0; + assign readback_array[7][31:0] = (decoded_reg_strb.hwpe_ctrl.reserved2 && !decoded_req_is_wr) ? 32'h0 : '0; + assign readback_array[8][31:0] = (decoded_reg_strb.hwpe_job_dep.weights_ptr && !decoded_req_is_wr) ? field_storage.hwpe_job_dep.weights_ptr.value.value : '0; + assign readback_array[9][31:0] = (decoded_reg_strb.hwpe_job_dep.infeat_ptr && !decoded_req_is_wr) ? field_storage.hwpe_job_dep.infeat_ptr.value.value : '0; + assign readback_array[10][31:0] = (decoded_reg_strb.hwpe_job_dep.outfeat_ptr && !decoded_req_is_wr) ? field_storage.hwpe_job_dep.outfeat_ptr.value.value : '0; + assign readback_array[11][31:0] = (decoded_reg_strb.hwpe_job_dep.scale_ptr && !decoded_req_is_wr) ? field_storage.hwpe_job_dep.scale_ptr.value.value : '0; + assign readback_array[12][31:0] = (decoded_reg_strb.hwpe_job_dep.scale_shift_ptr && !decoded_req_is_wr) ? field_storage.hwpe_job_dep.scale_shift_ptr.value.value : '0; + assign readback_array[13][31:0] = (decoded_reg_strb.hwpe_job_dep.scale_bias_ptr && !decoded_req_is_wr) ? field_storage.hwpe_job_dep.scale_bias_ptr.value.value : '0; + assign readback_array[14][31:0] = (decoded_reg_strb.hwpe_job_dep.infeat_d0_str && !decoded_req_is_wr) ? field_storage.hwpe_job_dep.infeat_d0_str.value.value : '0; + assign readback_array[15][31:0] = (decoded_reg_strb.hwpe_job_dep.infeat_d1_str && !decoded_req_is_wr) ? field_storage.hwpe_job_dep.infeat_d1_str.value.value : '0; + assign readback_array[16][31:0] = (decoded_reg_strb.hwpe_job_dep.infeat_d2_str && !decoded_req_is_wr) ? field_storage.hwpe_job_dep.infeat_d2_str.value.value : '0; + assign readback_array[17][31:0] = (decoded_reg_strb.hwpe_job_dep.outfeat_d0_st && !decoded_req_is_wr) ? field_storage.hwpe_job_dep.outfeat_d0_st.value.value : '0; + assign readback_array[18][31:0] = (decoded_reg_strb.hwpe_job_dep.outfeat_d1_st && !decoded_req_is_wr) ? field_storage.hwpe_job_dep.outfeat_d1_st.value.value : '0; + assign readback_array[19][31:0] = (decoded_reg_strb.hwpe_job_dep.outfeat_d2_st && !decoded_req_is_wr) ? field_storage.hwpe_job_dep.outfeat_d2_st.value.value : '0; + assign readback_array[20][31:0] = (decoded_reg_strb.hwpe_job_dep.weights_d0_st && !decoded_req_is_wr) ? field_storage.hwpe_job_dep.weights_d0_st.value.value : '0; + assign readback_array[21][31:0] = (decoded_reg_strb.hwpe_job_dep.weights_d1_st && !decoded_req_is_wr) ? field_storage.hwpe_job_dep.weights_d1_st.value.value : '0; + assign readback_array[22][31:0] = (decoded_reg_strb.hwpe_job_dep.weights_d2_st && !decoded_req_is_wr) ? field_storage.hwpe_job_dep.weights_d2_st.value.value : '0; + assign readback_array[23][15:0] = (decoded_reg_strb.hwpe_job_dep.subtile_rem0 && !decoded_req_is_wr) ? field_storage.hwpe_job_dep.subtile_rem0.ki.value : '0; + assign readback_array[23][31:16] = (decoded_reg_strb.hwpe_job_dep.subtile_rem0 && !decoded_req_is_wr) ? field_storage.hwpe_job_dep.subtile_rem0.ko.value : '0; + assign readback_array[24][15:0] = (decoded_reg_strb.hwpe_job_dep.subtile_rem1 && !decoded_req_is_wr) ? field_storage.hwpe_job_dep.subtile_rem1.wo.value : '0; + assign readback_array[24][31:16] = (decoded_reg_strb.hwpe_job_dep.subtile_rem1 && !decoded_req_is_wr) ? field_storage.hwpe_job_dep.subtile_rem1.ho.value : '0; + assign readback_array[25][15:0] = (decoded_reg_strb.hwpe_job_dep.subtile_rem2 && !decoded_req_is_wr) ? field_storage.hwpe_job_dep.subtile_rem2.wi.value : '0; + assign readback_array[25][31:16] = (decoded_reg_strb.hwpe_job_dep.subtile_rem2 && !decoded_req_is_wr) ? field_storage.hwpe_job_dep.subtile_rem2.hi.value : '0; + assign readback_array[26][15:0] = (decoded_reg_strb.hwpe_job_dep.subtile_nb0 && !decoded_req_is_wr) ? field_storage.hwpe_job_dep.subtile_nb0.ki.value : '0; + assign readback_array[26][31:16] = (decoded_reg_strb.hwpe_job_dep.subtile_nb0 && !decoded_req_is_wr) ? field_storage.hwpe_job_dep.subtile_nb0.ko.value : '0; + assign readback_array[27][15:0] = (decoded_reg_strb.hwpe_job_dep.subtile_nb1 && !decoded_req_is_wr) ? field_storage.hwpe_job_dep.subtile_nb1.wo.value : '0; + assign readback_array[27][31:16] = (decoded_reg_strb.hwpe_job_dep.subtile_nb1 && !decoded_req_is_wr) ? field_storage.hwpe_job_dep.subtile_nb1.ho.value : '0; + assign readback_array[28][15:0] = (decoded_reg_strb.hwpe_job_dep.padding && !decoded_req_is_wr) ? field_storage.hwpe_job_dep.padding.value.value : '0; + assign readback_array[28][19:16] = (decoded_reg_strb.hwpe_job_dep.padding && !decoded_req_is_wr) ? field_storage.hwpe_job_dep.padding.left.value : '0; + assign readback_array[28][23:20] = (decoded_reg_strb.hwpe_job_dep.padding && !decoded_req_is_wr) ? field_storage.hwpe_job_dep.padding.bottom.value : '0; + assign readback_array[28][27:24] = (decoded_reg_strb.hwpe_job_dep.padding && !decoded_req_is_wr) ? field_storage.hwpe_job_dep.padding.right.value : '0; + assign readback_array[28][31:28] = (decoded_reg_strb.hwpe_job_dep.padding && !decoded_req_is_wr) ? field_storage.hwpe_job_dep.padding.top.value : '0; + assign readback_array[29][31:0] = (decoded_reg_strb.hwpe_job_dep.weight_offset && !decoded_req_is_wr) ? field_storage.hwpe_job_dep.weight_offset.value.value : '0; + assign readback_array[30][7:0] = (decoded_reg_strb.hwpe_job_dep.filter_mask && !decoded_req_is_wr) ? field_storage.hwpe_job_dep.filter_mask.left.value : '0; + assign readback_array[30][15:8] = (decoded_reg_strb.hwpe_job_dep.filter_mask && !decoded_req_is_wr) ? field_storage.hwpe_job_dep.filter_mask.bottom.value : '0; + assign readback_array[30][23:16] = (decoded_reg_strb.hwpe_job_dep.filter_mask && !decoded_req_is_wr) ? field_storage.hwpe_job_dep.filter_mask.right.value : '0; + assign readback_array[30][31:24] = (decoded_reg_strb.hwpe_job_dep.filter_mask && !decoded_req_is_wr) ? field_storage.hwpe_job_dep.filter_mask.top.value : '0; + assign readback_array[31][2:0] = (decoded_reg_strb.hwpe_job_dep.config0 && !decoded_req_is_wr) ? field_storage.hwpe_job_dep.config0.wbits.value : '0; + assign readback_array[31][3:3] = (decoded_reg_strb.hwpe_job_dep.config0 && !decoded_req_is_wr) ? field_storage.hwpe_job_dep.config0.reserved2.value : '0; + assign readback_array[31][4:4] = (decoded_reg_strb.hwpe_job_dep.config0 && !decoded_req_is_wr) ? field_storage.hwpe_job_dep.config0.streamout_quant.value : '0; + assign readback_array[31][6:5] = (decoded_reg_strb.hwpe_job_dep.config0 && !decoded_req_is_wr) ? field_storage.hwpe_job_dep.config0.filter_mode.value : '0; + assign readback_array[31][7:7] = (decoded_reg_strb.hwpe_job_dep.config0 && !decoded_req_is_wr) ? field_storage.hwpe_job_dep.config0.mode_linear.value : '0; + assign readback_array[31][8:8] = (decoded_reg_strb.hwpe_job_dep.config0 && !decoded_req_is_wr) ? field_storage.hwpe_job_dep.config0.mode_strided.value : '0; + assign readback_array[31][9:9] = (decoded_reg_strb.hwpe_job_dep.config0 && !decoded_req_is_wr) ? field_storage.hwpe_job_dep.config0.wmem.value : '0; + assign readback_array[31][10:10] = (decoded_reg_strb.hwpe_job_dep.config0 && !decoded_req_is_wr) ? field_storage.hwpe_job_dep.config0.prefetch.value : '0; + assign readback_array[31][11:11] = (decoded_reg_strb.hwpe_job_dep.config0 && !decoded_req_is_wr) ? field_storage.hwpe_job_dep.config0.rounding.value : '0; + assign readback_array[31][13:12] = (decoded_reg_strb.hwpe_job_dep.config0 && !decoded_req_is_wr) ? field_storage.hwpe_job_dep.config0.norm_mode.value : '0; + assign readback_array[31][14:14] = (decoded_reg_strb.hwpe_job_dep.config0 && !decoded_req_is_wr) ? field_storage.hwpe_job_dep.config0.streamin.value : '0; + assign readback_array[31][15:15] = (decoded_reg_strb.hwpe_job_dep.config0 && !decoded_req_is_wr) ? field_storage.hwpe_job_dep.config0.streamin_mode.value : '0; + assign readback_array[31][20:16] = (decoded_reg_strb.hwpe_job_dep.config0 && !decoded_req_is_wr) ? field_storage.hwpe_job_dep.config0.shift_reqnt.value : '0; + assign readback_array[31][22:21] = (decoded_reg_strb.hwpe_job_dep.config0 && !decoded_req_is_wr) ? field_storage.hwpe_job_dep.config0.quant_mode.value : '0; + assign readback_array[31][23:23] = (decoded_reg_strb.hwpe_job_dep.config0 && !decoded_req_is_wr) ? field_storage.hwpe_job_dep.config0.relu.value : '0; + assign readback_array[31][24:24] = (decoded_reg_strb.hwpe_job_dep.config0 && !decoded_req_is_wr) ? field_storage.hwpe_job_dep.config0.norm_option_shift.value : '0; + assign readback_array[31][25:25] = (decoded_reg_strb.hwpe_job_dep.config0 && !decoded_req_is_wr) ? field_storage.hwpe_job_dep.config0.norm_option_bias.value : '0; + assign readback_array[31][26:26] = (decoded_reg_strb.hwpe_job_dep.config0 && !decoded_req_is_wr) ? field_storage.hwpe_job_dep.config0.feat_broadcast.value : '0; + assign readback_array[31][31:27] = (decoded_reg_strb.hwpe_job_dep.config0 && !decoded_req_is_wr) ? field_storage.hwpe_job_dep.config0.reserved.value : '0; + assign readback_array[32][31:0] = (decoded_reg_strb.hwpe_job_dep.streamin_ptr && !decoded_req_is_wr) ? field_storage.hwpe_job_dep.streamin_ptr.value.value : '0; + assign readback_array[33][31:0] = (decoded_reg_strb.hwpe_job_indep.reserved && !decoded_req_is_wr) ? 32'h0 : '0; + + // Reduce the array + always_comb begin + automatic logic [31:0] readback_data_var; + readback_done = decoded_req & ~decoded_req_is_wr; + readback_err = '0; + readback_data_var = '0; + for(int i=0; i<34; i++) readback_data_var |= readback_array[i]; + readback_data = readback_data_var; + end + + assign cpuif_rd_ack = readback_done; + assign cpuif_rd_data = readback_data; + assign cpuif_rd_err = readback_err; +endmodule diff --git a/rtl/ctrl/regif/neureka_regif_pkg.sv b/rtl/ctrl/regif/neureka_regif_pkg.sv new file mode 100644 index 0000000..454c24a --- /dev/null +++ b/rtl/ctrl/regif/neureka_regif_pkg.sv @@ -0,0 +1,493 @@ +// Generated by PeakRDL-regblock - A free and open-source SystemVerilog generator +// https://github.com/SystemRDL/PeakRDL-regblock + +package neureka_regif_pkg; + + localparam NEUREKA_REGIF_DATA_WIDTH = 32; + localparam NEUREKA_REGIF_MIN_ADDR_WIDTH = 32; + localparam NEUREKA_REGIF_SIZE = 'h88; + + typedef struct packed { + logic [31:0] next; + } neureka_regif__hwpe_acquire__acquire__in_t; + + typedef struct packed { + neureka_regif__hwpe_acquire__acquire__in_t acquire; + } neureka_regif__hwpe_acquire__in_t; + + typedef struct packed { + logic [31:0] next; + } neureka_regif__hwpe_status__status0__in_t; + + typedef struct packed { + neureka_regif__hwpe_status__status0__in_t status0; + } neureka_regif__hwpe_status__in_t; + + typedef struct packed { + logic [7:0] next; + } neureka_regif__hwpe_running_job__running_job__in_t; + + typedef struct packed { + neureka_regif__hwpe_running_job__running_job__in_t running_job; + } neureka_regif__hwpe_running_job__in_t; + + typedef struct packed { + neureka_regif__hwpe_acquire__in_t acquire; + neureka_regif__hwpe_status__in_t status; + neureka_regif__hwpe_running_job__in_t running_job; + } neureka_regif__hwpe_ctrl_mandatory__in_t; + + typedef struct packed { + neureka_regif__hwpe_ctrl_mandatory__in_t hwpe_ctrl; + } neureka_regif__in_t; + + typedef struct packed { + logic [1:0] value; + logic swacc; + } neureka_regif__hwpe_commit_trigger__commit_trigger__out_t; + + typedef struct packed { + logic [29:0] value; + } neureka_regif__hwpe_commit_trigger__r0__out_t; + + typedef struct packed { + neureka_regif__hwpe_commit_trigger__commit_trigger__out_t commit_trigger; + neureka_regif__hwpe_commit_trigger__r0__out_t r0; + } neureka_regif__hwpe_commit_trigger__out_t; + + typedef struct packed { + logic swacc; + } neureka_regif__hwpe_acquire__acquire__out_t; + + typedef struct packed { + neureka_regif__hwpe_acquire__acquire__out_t acquire; + } neureka_regif__hwpe_acquire__out_t; + + typedef struct packed { + logic [31:0] value; + } neureka_regif__hwpe_reserved__reserved__out_t; + + typedef struct packed { + neureka_regif__hwpe_reserved__reserved__out_t reserved; + } neureka_regif__hwpe_reserved__out_t; + + typedef struct packed { + logic [23:0] value; + } neureka_regif__hwpe_running_job__r0__out_t; + + typedef struct packed { + neureka_regif__hwpe_running_job__r0__out_t r0; + } neureka_regif__hwpe_running_job__out_t; + + typedef struct packed { + logic [1:0] value; + logic swacc; + } neureka_regif__hwpe_soft_clear__soft_clear__out_t; + + typedef struct packed { + logic [29:0] value; + } neureka_regif__hwpe_soft_clear__r0__out_t; + + typedef struct packed { + neureka_regif__hwpe_soft_clear__soft_clear__out_t soft_clear; + neureka_regif__hwpe_soft_clear__r0__out_t r0; + } neureka_regif__hwpe_soft_clear__out_t; + + typedef struct packed { + neureka_regif__hwpe_commit_trigger__out_t commit_trigger; + neureka_regif__hwpe_acquire__out_t acquire; + neureka_regif__hwpe_reserved__out_t reserved0; + neureka_regif__hwpe_running_job__out_t running_job; + neureka_regif__hwpe_soft_clear__out_t soft_clear; + neureka_regif__hwpe_reserved__out_t reserved1; + neureka_regif__hwpe_reserved__out_t reserved2; + } neureka_regif__hwpe_ctrl_mandatory__out_t; + + typedef struct packed { + logic [31:0] value; + } neureka_regif__weights_ptr__value__out_t; + + typedef struct packed { + neureka_regif__weights_ptr__value__out_t value; + } neureka_regif__weights_ptr__out_t; + + typedef struct packed { + logic [31:0] value; + } neureka_regif__infeat_ptr__value__out_t; + + typedef struct packed { + neureka_regif__infeat_ptr__value__out_t value; + } neureka_regif__infeat_ptr__out_t; + + typedef struct packed { + logic [31:0] value; + } neureka_regif__outfeat_ptr__value__out_t; + + typedef struct packed { + neureka_regif__outfeat_ptr__value__out_t value; + } neureka_regif__outfeat_ptr__out_t; + + typedef struct packed { + logic [31:0] value; + } neureka_regif__scale_ptr__value__out_t; + + typedef struct packed { + neureka_regif__scale_ptr__value__out_t value; + } neureka_regif__scale_ptr__out_t; + + typedef struct packed { + logic [31:0] value; + } neureka_regif__scale_shift_ptr__value__out_t; + + typedef struct packed { + neureka_regif__scale_shift_ptr__value__out_t value; + } neureka_regif__scale_shift_ptr__out_t; + + typedef struct packed { + logic [31:0] value; + } neureka_regif__scale_bias_ptr__value__out_t; + + typedef struct packed { + neureka_regif__scale_bias_ptr__value__out_t value; + } neureka_regif__scale_bias_ptr__out_t; + + typedef struct packed { + logic [31:0] value; + } neureka_regif__infeat_d0_stride__value__out_t; + + typedef struct packed { + neureka_regif__infeat_d0_stride__value__out_t value; + } neureka_regif__infeat_d0_stride__out_t; + + typedef struct packed { + logic [31:0] value; + } neureka_regif__infeat_d1_stride__value__out_t; + + typedef struct packed { + neureka_regif__infeat_d1_stride__value__out_t value; + } neureka_regif__infeat_d1_stride__out_t; + + typedef struct packed { + logic [31:0] value; + } neureka_regif__infeat_d2_stride__value__out_t; + + typedef struct packed { + neureka_regif__infeat_d2_stride__value__out_t value; + } neureka_regif__infeat_d2_stride__out_t; + + typedef struct packed { + logic [31:0] value; + } neureka_regif__outfeat_d0_stride__value__out_t; + + typedef struct packed { + neureka_regif__outfeat_d0_stride__value__out_t value; + } neureka_regif__outfeat_d0_stride__out_t; + + typedef struct packed { + logic [31:0] value; + } neureka_regif__outfeat_d1_stride__value__out_t; + + typedef struct packed { + neureka_regif__outfeat_d1_stride__value__out_t value; + } neureka_regif__outfeat_d1_stride__out_t; + + typedef struct packed { + logic [31:0] value; + } neureka_regif__outfeat_d2_stride__value__out_t; + + typedef struct packed { + neureka_regif__outfeat_d2_stride__value__out_t value; + } neureka_regif__outfeat_d2_stride__out_t; + + typedef struct packed { + logic [31:0] value; + } neureka_regif__weights_d0_stride__value__out_t; + + typedef struct packed { + neureka_regif__weights_d0_stride__value__out_t value; + } neureka_regif__weights_d0_stride__out_t; + + typedef struct packed { + logic [31:0] value; + } neureka_regif__weights_d1_stride__value__out_t; + + typedef struct packed { + neureka_regif__weights_d1_stride__value__out_t value; + } neureka_regif__weights_d1_stride__out_t; + + typedef struct packed { + logic [31:0] value; + } neureka_regif__weights_d2_stride__value__out_t; + + typedef struct packed { + neureka_regif__weights_d2_stride__value__out_t value; + } neureka_regif__weights_d2_stride__out_t; + + typedef struct packed { + logic [15:0] value; + } neureka_regif__subtile_rem0__ki__out_t; + + typedef struct packed { + logic [15:0] value; + } neureka_regif__subtile_rem0__ko__out_t; + + typedef struct packed { + neureka_regif__subtile_rem0__ki__out_t ki; + neureka_regif__subtile_rem0__ko__out_t ko; + } neureka_regif__subtile_rem0__out_t; + + typedef struct packed { + logic [15:0] value; + } neureka_regif__subtile_rem1__wo__out_t; + + typedef struct packed { + logic [15:0] value; + } neureka_regif__subtile_rem1__ho__out_t; + + typedef struct packed { + neureka_regif__subtile_rem1__wo__out_t wo; + neureka_regif__subtile_rem1__ho__out_t ho; + } neureka_regif__subtile_rem1__out_t; + + typedef struct packed { + logic [15:0] value; + } neureka_regif__subtile_rem2__wi__out_t; + + typedef struct packed { + logic [15:0] value; + } neureka_regif__subtile_rem2__hi__out_t; + + typedef struct packed { + neureka_regif__subtile_rem2__wi__out_t wi; + neureka_regif__subtile_rem2__hi__out_t hi; + } neureka_regif__subtile_rem2__out_t; + + typedef struct packed { + logic [15:0] value; + } neureka_regif__subtile_nb0__ki__out_t; + + typedef struct packed { + logic [15:0] value; + } neureka_regif__subtile_nb0__ko__out_t; + + typedef struct packed { + neureka_regif__subtile_nb0__ki__out_t ki; + neureka_regif__subtile_nb0__ko__out_t ko; + } neureka_regif__subtile_nb0__out_t; + + typedef struct packed { + logic [15:0] value; + } neureka_regif__subtile_nb1__wo__out_t; + + typedef struct packed { + logic [15:0] value; + } neureka_regif__subtile_nb1__ho__out_t; + + typedef struct packed { + neureka_regif__subtile_nb1__wo__out_t wo; + neureka_regif__subtile_nb1__ho__out_t ho; + } neureka_regif__subtile_nb1__out_t; + + typedef struct packed { + logic [15:0] value; + } neureka_regif__padding__value__out_t; + + typedef struct packed { + logic [3:0] value; + } neureka_regif__padding__left__out_t; + + typedef struct packed { + logic [3:0] value; + } neureka_regif__padding__bottom__out_t; + + typedef struct packed { + logic [3:0] value; + } neureka_regif__padding__right__out_t; + + typedef struct packed { + logic [3:0] value; + } neureka_regif__padding__top__out_t; + + typedef struct packed { + neureka_regif__padding__value__out_t value; + neureka_regif__padding__left__out_t left; + neureka_regif__padding__bottom__out_t bottom; + neureka_regif__padding__right__out_t right; + neureka_regif__padding__top__out_t top; + } neureka_regif__padding__out_t; + + typedef struct packed { + logic [31:0] value; + } neureka_regif__weight_offset__value__out_t; + + typedef struct packed { + neureka_regif__weight_offset__value__out_t value; + } neureka_regif__weight_offset__out_t; + + typedef struct packed { + logic [7:0] value; + } neureka_regif__filter_mask__left__out_t; + + typedef struct packed { + logic [7:0] value; + } neureka_regif__filter_mask__bottom__out_t; + + typedef struct packed { + logic [7:0] value; + } neureka_regif__filter_mask__right__out_t; + + typedef struct packed { + logic [7:0] value; + } neureka_regif__filter_mask__top__out_t; + + typedef struct packed { + neureka_regif__filter_mask__left__out_t left; + neureka_regif__filter_mask__bottom__out_t bottom; + neureka_regif__filter_mask__right__out_t right; + neureka_regif__filter_mask__top__out_t top; + } neureka_regif__filter_mask__out_t; + + typedef struct packed { + logic [2:0] value; + } neureka_regif__config0__wbits__out_t; + + typedef struct packed { + logic value; + } neureka_regif__config0__reserved2__out_t; + + typedef struct packed { + logic value; + } neureka_regif__config0__streamout_quant__out_t; + + typedef struct packed { + logic [1:0] value; + } neureka_regif__config0__filter_mode__out_t; + + typedef struct packed { + logic value; + } neureka_regif__config0__mode_linear__out_t; + + typedef struct packed { + logic value; + } neureka_regif__config0__mode_strided__out_t; + + typedef struct packed { + logic value; + } neureka_regif__config0__wmem__out_t; + + typedef struct packed { + logic value; + } neureka_regif__config0__prefetch__out_t; + + typedef struct packed { + logic value; + } neureka_regif__config0__rounding__out_t; + + typedef struct packed { + logic [1:0] value; + } neureka_regif__config0__norm_mode__out_t; + + typedef struct packed { + logic value; + } neureka_regif__config0__streamin__out_t; + + typedef struct packed { + logic value; + } neureka_regif__config0__streamin_mode__out_t; + + typedef struct packed { + logic [4:0] value; + } neureka_regif__config0__shift_reqnt__out_t; + + typedef struct packed { + logic [1:0] value; + } neureka_regif__config0__quant_mode__out_t; + + typedef struct packed { + logic value; + } neureka_regif__config0__relu__out_t; + + typedef struct packed { + logic value; + } neureka_regif__config0__norm_option_shift__out_t; + + typedef struct packed { + logic value; + } neureka_regif__config0__norm_option_bias__out_t; + + typedef struct packed { + logic value; + } neureka_regif__config0__feat_broadcast__out_t; + + typedef struct packed { + logic [4:0] value; + } neureka_regif__config0__reserved__out_t; + + typedef struct packed { + neureka_regif__config0__wbits__out_t wbits; + neureka_regif__config0__reserved2__out_t reserved2; + neureka_regif__config0__streamout_quant__out_t streamout_quant; + neureka_regif__config0__filter_mode__out_t filter_mode; + neureka_regif__config0__mode_linear__out_t mode_linear; + neureka_regif__config0__mode_strided__out_t mode_strided; + neureka_regif__config0__wmem__out_t wmem; + neureka_regif__config0__prefetch__out_t prefetch; + neureka_regif__config0__rounding__out_t rounding; + neureka_regif__config0__norm_mode__out_t norm_mode; + neureka_regif__config0__streamin__out_t streamin; + neureka_regif__config0__streamin_mode__out_t streamin_mode; + neureka_regif__config0__shift_reqnt__out_t shift_reqnt; + neureka_regif__config0__quant_mode__out_t quant_mode; + neureka_regif__config0__relu__out_t relu; + neureka_regif__config0__norm_option_shift__out_t norm_option_shift; + neureka_regif__config0__norm_option_bias__out_t norm_option_bias; + neureka_regif__config0__feat_broadcast__out_t feat_broadcast; + neureka_regif__config0__reserved__out_t reserved; + } neureka_regif__config0__out_t; + + typedef struct packed { + logic [31:0] value; + } neureka_regif__streamin_ptr__value__out_t; + + typedef struct packed { + neureka_regif__streamin_ptr__value__out_t value; + } neureka_regif__streamin_ptr__out_t; + + typedef struct packed { + neureka_regif__weights_ptr__out_t weights_ptr; + neureka_regif__infeat_ptr__out_t infeat_ptr; + neureka_regif__outfeat_ptr__out_t outfeat_ptr; + neureka_regif__scale_ptr__out_t scale_ptr; + neureka_regif__scale_shift_ptr__out_t scale_shift_ptr; + neureka_regif__scale_bias_ptr__out_t scale_bias_ptr; + neureka_regif__infeat_d0_stride__out_t infeat_d0_str; + neureka_regif__infeat_d1_stride__out_t infeat_d1_str; + neureka_regif__infeat_d2_stride__out_t infeat_d2_str; + neureka_regif__outfeat_d0_stride__out_t outfeat_d0_st; + neureka_regif__outfeat_d1_stride__out_t outfeat_d1_st; + neureka_regif__outfeat_d2_stride__out_t outfeat_d2_st; + neureka_regif__weights_d0_stride__out_t weights_d0_st; + neureka_regif__weights_d1_stride__out_t weights_d1_st; + neureka_regif__weights_d2_stride__out_t weights_d2_st; + neureka_regif__subtile_rem0__out_t subtile_rem0; + neureka_regif__subtile_rem1__out_t subtile_rem1; + neureka_regif__subtile_rem2__out_t subtile_rem2; + neureka_regif__subtile_nb0__out_t subtile_nb0; + neureka_regif__subtile_nb1__out_t subtile_nb1; + neureka_regif__padding__out_t padding; + neureka_regif__weight_offset__out_t weight_offset; + neureka_regif__filter_mask__out_t filter_mask; + neureka_regif__config0__out_t config0; + neureka_regif__streamin_ptr__out_t streamin_ptr; + } neureka_regif__hwpe_ctrl_job_dep__out_t; + + typedef struct packed { + neureka_regif__hwpe_reserved__out_t reserved; + } neureka_regif__hwpe_ctrl_job_indep__out_t; + + typedef struct packed { + neureka_regif__hwpe_ctrl_mandatory__out_t hwpe_ctrl; + neureka_regif__hwpe_ctrl_job_dep__out_t hwpe_job_dep; + neureka_regif__hwpe_ctrl_job_indep__out_t hwpe_job_indep; + } neureka_regif__out_t; +endpackage diff --git a/rtl/verif/tb_dummy_memory.sv b/rtl/verif/tb_dummy_memory.sv index 7e1f52c..5b8f2b7 100644 --- a/rtl/verif/tb_dummy_memory.sv +++ b/rtl/verif/tb_dummy_memory.sv @@ -61,7 +61,7 @@ module tb_dummy_memory logic clk_delayed; - always_ff @(posedge clk_i) + always @(posedge clk_i) begin : probs_proc for (int i=0; i