diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml
index 9a98fdb8..b179dbff 100644
--- a/.gitlab-ci.yml
+++ b/.gitlab-ci.yml
@@ -15,6 +15,10 @@ stages:
 .init-env:
   before_script:
     - source iis-env.sh
+    # Hard link cached python packages since the UV cache directory
+    # is configured to be on the same filesystem as the build directory in the CI.
+    - export UV_CACHE_DIR=$CI_BUILDS_DIR/../cache/uv
+    - export UV_LINK_MODE=hardlink
 
 ##################
 # Initialization #
@@ -23,6 +27,7 @@ stages:
 init-deps:
   stage: init
   extends:
+    - .init-env
     - .init-deps-tpl
   artifacts:
     paths:
@@ -59,8 +64,8 @@ vsim-compile:
   stage: build
   needs:
     - generate-rtl
-  variables:
-    FLOO_GEN_ARGS: --no-format
+  extends:
+    - .init-env
   script:
     - make vsim-compile | tee compile.log 2>&1
     - '! grep "\*\* Error" compile.log'
diff --git a/.gitlab/common.yml b/.gitlab/common.yml
index 1cc395b4..37ddc6f4 100644
--- a/.gitlab/common.yml
+++ b/.gitlab/common.yml
@@ -3,8 +3,7 @@
 # SPDX-License-Identifier: Apache-2.0
 
 variables:
-  PIP_CACHE_DIR: "$CI_PROJECT_DIR/.cache/pip"
-  PD_COMMIT: "6c72ebfe4cbbc11bba771405212f85fd4ef603c8"
+  PD_COMMIT: "uv" # TODO: Merge in Gitlab
   SPU_COMMIT: "c2e8815487bd713624d74ef3e3e0465196b6d67f"
 
 # Check the cache for bender and python dependencies
@@ -13,31 +12,17 @@ variables:
     key:
       files:
         - Bender.lock
-        - requirements.txt
     paths:
       - .bender
-      - .cache/pip
     policy: pull
 
 # Update the cache with bender and python dependencies
 .init-deps-tpl:
   script:
-    # Check out the biggest bender dependencies serially
-    # to avoid rate limiting issues
-    # TODO(fischeti): Remove once bender supports rate limiting
-    - bender path cheshire
-    - bender path cva6
-    - bender path ibex
-    - bender path floo_noc
-    - bender path idma
-    - bender path cluster_interconnect
-    - bender path snitch_cluster
-    # Collect bender sourcess
-    - bender checkout
-    # Install the python venv
-    - source iis-env.sh
     # Initialize the PD repository
     - make init-pd
+    # Collect bender sources
+    - bender checkout
   cache:
     # inherit all global cache settings
     <<: *global_cache
diff --git a/.python-version b/.python-version
new file mode 100644
index 00000000..2c073331
--- /dev/null
+++ b/.python-version
@@ -0,0 +1 @@
+3.11
diff --git a/Bender.lock b/Bender.lock
index 7dd4d787..d4b721fd 100644
--- a/Bender.lock
+++ b/Bender.lock
@@ -25,7 +25,7 @@ packages:
     - obi_peripherals
     - register_interface
   axi:
-    revision: bec548fa2a9b18cbd7531105bb1fdf481ea8ad49
+    revision: f3bc7865de5eb98c79ce18864d7df5ba67c4f68e
     version: null
     source:
       Git: https://github.com/colluca/axi.git
@@ -88,11 +88,12 @@ packages:
     - common_cells
     - register_interface
   cheshire:
-    revision: 0bebd9a2d6edb4665b00d2db9442c059692c0664
+    revision: 0673c7b193cc787bb645d7db47bee80f22dcc62f
     version: null
     source:
       Git: https://github.com/pulp-platform/cheshire.git
     dependencies:
+    - apb
     - apb_uart
     - axi
     - axi_llc
@@ -113,24 +114,24 @@ packages:
     - serial_link
     - unbent
   clic:
-    revision: 8ed76ffc779a435d0ed034f3068e4c3334fe2ecf
-    version: 2.0.0
+    revision: 6515a71eb4ae3b143ab912d265e79832b3179a76
+    version: 3.0.0
     source:
       Git: https://github.com/pulp-platform/clic.git
     dependencies:
     - common_cells
     - register_interface
   clint:
-    revision: d5390a805c20f9226758a152ba1645f61da73349
-    version: 0.2.0
+    revision: 2318184fc191e94b7069436ba28bfe0f485b8a67
+    version: null
     source:
       Git: https://github.com/pulp-platform/clint.git
     dependencies:
+    - apb
     - common_cells
-    - register_interface
   cluster_icache:
-    revision: 64e21ae455bbdde850c4df13bef86ea55ac42537
-    version: 0.2.0
+    revision: 1642961b9561513f283674efc2c90f24855e8d39
+    version: 0.3.1
     source:
       Git: https://github.com/pulp-platform/cluster_icache.git
     dependencies:
@@ -146,7 +147,7 @@ packages:
     dependencies:
     - common_cells
   common_cells:
-    revision: bab4cea30f1cdfe303a4585db04c1a1f6882b718
+    revision: ca9d577f2fbc45ec557ab4e0905bbfc154441540
     version: null
     source:
       Git: https://github.com/pulp-platform/common_cells.git
@@ -160,7 +161,7 @@ packages:
       Git: https://github.com/pulp-platform/common_verification.git
     dependencies: []
   cv32e40p:
-    revision: 800a09d97a1e9418e127e8bbf1763c1d1097c92f
+    revision: 1a93f340e9dadb9f7c8c471f27a40932c8b1c62e
     version: null
     source:
       Git: https://github.com/pulp-platform/cv32e40p.git
@@ -175,7 +176,7 @@ packages:
       Git: https://github.com/pulp-platform/cv32e40x.git
     dependencies: []
   cva6:
-    revision: 9338c2ca7cf1a47aef54322f89ce867825c3c8d5
+    revision: 4c02b24fe7c04690f626776a92274da24f80d1da
     version: null
     source:
       Git: https://github.com/pulp-platform/cva6.git
@@ -185,10 +186,10 @@ packages:
     - fpnew
     - tech_cells_generic
   datamover:
-    revision: 5df9c9bd9e10ad020763c4291c571adf35ef4ae2
+    revision: 876679af2d1eaa801853b946f43107671f86685f
     version: null
     source:
-      Git: https://github.com/pulp-platform/datamover
+      Git: https://github.com/pulp-platform/datamover.git
     dependencies:
     - hci
     - hwpe-ctrl
@@ -225,7 +226,7 @@ packages:
       Path: .bender/git/checkouts/floo_noc-051cdbf4a4876727/./pd
     dependencies: []
   fpnew:
-    revision: a8e0cba6dd50f357ece73c2c955d96efc3c6c315
+    revision: e5aa6a01b5bbe1675c3aa8872e1203413ded83d1
     version: null
     source:
       Git: https://github.com/pulp-platform/cvfpu.git
@@ -243,7 +244,7 @@ packages:
     revision: fa625bdb824209bc2c0faaa6d99ec15ff981473f
     version: null
     source:
-      Git: https://github.com/pulp-platform/hci
+      Git: https://github.com/pulp-platform/hci.git
     dependencies:
     - cluster_interconnect
     - common_cells
@@ -252,8 +253,8 @@ packages:
     - redundancy_cells
     - register_interface
   hwpe-ctrl:
-    revision: 3690a3c648f120546d8de2bc583d5170c36d2f20
-    version: 2.0.0
+    revision: 0e95510c0f4d43452d21b7723d766ae92e45c101
+    version: null
     source:
       Git: https://github.com/pulp-platform/hwpe-ctrl.git
     dependencies:
@@ -273,8 +274,8 @@ packages:
     dependencies:
     - tech_cells_generic
   idma:
-    revision: 7829f71691a62c1e2e5e3230f370f222c7a83087
-    version: null
+    revision: 28a36e5e07705549e59fc33db96ab681bc1ca88e
+    version: 0.6.5
     source:
       Git: https://github.com/pulp-platform/iDMA.git
     dependencies:
@@ -300,7 +301,7 @@ packages:
       Git: https://github.com/pulp-platform/L2_tcdm_hybrid_interco.git
     dependencies: []
   obi:
-    revision: acfcd0f80c7539aa8da7821a66d9acf2074a5b4e
+    revision: 6a724da5c8d6412b88b6948746e04c1adf39d017
     version: null
     source:
       Git: https://github.com/pulp-platform/obi.git
@@ -334,7 +335,7 @@ packages:
     revision: 6fb7c175a784e1161a6762ab91d9b296697a66f1
     version: null
     source:
-      Git: https://github.com/pulp-platform/redmule
+      Git: https://github.com/pulp-platform/redmule.git
     dependencies:
     - common_cells
     - cv32e40p
@@ -356,8 +357,8 @@ packages:
     - register_interface
     - tech_cells_generic
   register_interface:
-    revision: 5daa85d164cf6b54ad061ea1e4c6f3624556e467
-    version: 0.4.5
+    revision: d6e1d4cdaab7870f4faf3f88a1c788eaf5ac129d
+    version: 0.4.7
     source:
       Git: https://github.com/pulp-platform/register_interface.git
     dependencies:
@@ -374,23 +375,24 @@ packages:
     - common_cells
     - tech_cells_generic
   scm:
-    revision: 472f99affe44ff7b282b519c047a3cfeb35b16c6
-    version: 1.2.0
+    revision: 1976c7efb4979271eee2abe262fde0f9a20e2557
+    version: 1.2.1
     source:
       Git: https://github.com/pulp-platform/scm.git
     dependencies:
     - tech_cells_generic
   serial_link:
-    revision: c55df03a1da06b00e567cf968b1b1a5f40c9f802
-    version: 1.1.2
+    revision: 291ec6f7bab04581317aa4584ce42f2b35e28c2f
+    version: null
     source:
       Git: https://github.com/pulp-platform/serial_link.git
     dependencies:
+    - apb
     - axi
+    - axi_stream
     - common_cells
-    - register_interface
   snitch_cluster:
-    revision: 5d6c957c70e3824e2330d8308eb904724cd41cbe
+    revision: 443a47e753e00d2eed19562d0a89c6769b2b06fb
     version: null
     source:
       Git: https://github.com/pulp-platform/snitch_cluster.git
diff --git a/Bender.yml b/Bender.yml
index 446f4621..dd60976e 100644
--- a/Bender.yml
+++ b/Bender.yml
@@ -7,19 +7,23 @@ package:
   authors:
     - "Tim Fischer <fischeti@iis.ee.ethz.ch>"
 
+remotes:
+  pulp: https://github.com/pulp-platform
+
 dependencies:
-  register_interface: { git: "https://github.com/pulp-platform/register_interface.git", version: "0.4.5"                                }
-  axi:                { git: "https://github.com/pulp-platform/axi.git",                version: "0.39.6"                               }
-  common_cells:       { git: "https://github.com/pulp-platform/common_cells.git",       rev: "snitch"                                   }
-  cheshire:           { git: "https://github.com/pulp-platform/cheshire.git",           rev: "picobello"                                }
-  snitch_cluster:     { git: "https://github.com/pulp-platform/snitch_cluster.git",     rev: "5d6c957c70e3824e2330d8308eb904724cd41cbe" }
-  floo_noc:           { git: "https://github.com/pulp-platform/FlooNoC.git",            version: "0.7.0"                                }
-  obi:                { git: "https://github.com/pulp-platform/obi.git",                rev: "acfcd0f80c7539aa8da7821a66d9acf2074a5b4e" }
-  redmule:            { git: "https://github.com/pulp-platform/redmule.git",            rev: "picobello"                                }
-  hci:                { git: "https://github.com/pulp-platform/hci.git",                rev: "06fcba671e060f2e1b03b7ebe2d3e719f1557099" }
-  datamover:          { git: "https://github.com/pulp-platform/datamover.git",          rev: "5df9c9bd9e10ad020763c4291c571adf35ef4ae2" } # branch: transpose
-  apb:                { git: "https://github.com/pulp-platform/apb.git",                version: "0.2.4"                                }
+  register_interface: "0.4.5"
+  axi: "0.39.6"
+  common_cells: "1.39.0"
+  apb: "0.2.4"
+  floo_noc:           { version: "0.7.0", upstream_name: FlooNoC }
+  cheshire:           { git: "https://github.com/pulp-platform/cheshire.git",           rev: "picobello-but-with-more-rdl"              }
+  snitch_cluster:     { git: "https://github.com/pulp-platform/snitch_cluster.git",     rev: "main"                                     }
+  obi:                { git: "https://github.com/pulp-platform/obi.git",                rev: "main"                                     }
+  redmule:            { git: "https://github.com/pulp-platform/redmule.git",            rev: "picobello_tapeout"                        }
+  hci:                { git: "https://github.com/pulp-platform/hci.git",                rev: "fa625bdb824209bc2c0faaa6d99ec15ff981473f" } # branch: ab/fifo_options
+  datamover:          { git: "https://github.com/pulp-platform/datamover.git",          rev: "876679af2d1eaa801853b946f43107671f86685f" } # branch: master
   apb_fll_if:         { git: "https://github.com/pulp-platform/apb_fll_if.git",         rev: "structs"                                  }
+  FPnew:              { git: "https://github.com/pulp-platform/cvfpu.git",              rev: "pulp-v0.2.3"                              }
   axi_obi:            { path: "hw/axi_obi"                                                                                              }
   picobello-pd:       { path: "./pd"                                                                                                    }
   fhg_spu_cluster:    { path: "./.deps/fhg_spu_cluster"                                                                                 }
@@ -27,6 +31,7 @@ dependencies:
 workspace:
   package_links:
     .deps/snitch_cluster: snitch_cluster
+    .deps/floo_noc: floo_noc
 
 sources:
   # Source files grouped in levels. Files in level 0 have no dependencies on files in this
diff --git a/Makefile b/Makefile
index a18dbf3b..7d9dac46 100644
--- a/Makefile
+++ b/Makefile
@@ -12,7 +12,6 @@ BENDER_ROOT ?= $(PB_ROOT)/.bender
 FLOO_CFG  ?= $(PB_ROOT)/cfg/picobello_noc.yml
 SN_CFG	  ?= $(PB_ROOT)/cfg/snitch_cluster.json
 PLIC_CFG  ?= $(PB_ROOT)/cfg/rv_plic.cfg.hjson
-SLINK_CFG ?= $(PB_ROOT)/cfg/serial_link.hjson
 
 # Root directories of dependencies
 CHS_ROOT  = $(shell $(BENDER) path cheshire)
@@ -20,12 +19,16 @@ SN_ROOT   = $(shell $(BENDER) path snitch_cluster)
 FLOO_ROOT = $(shell $(BENDER) path floo_noc)
 
 # Executables
+PYTHON           ?= python
 BENDER           ?= bender -d $(PB_ROOT)
 FLOO_GEN         ?= floogen
 VERIBLE_FMT      ?= verible-verilog-format
 VERIBLE_FMT_ARGS ?= --flagfile .verilog_format --inplace --verbose
 PEAKRDL          ?= peakrdl
 
+# Get rid of non-existing PD path dependency warnings
+BENDER += --suppress W22
+
 # Tiles configuration
 SN_CLUSTERS = $(shell $(FLOO_GEN) -c $(FLOO_CFG) --query endpoints.cluster.num 2>/dev/null)
 L2_TILES = $(shell $(FLOO_GEN) -c $(FLOO_CFG) --query endpoints.l2_spm.num 2>/dev/null)
@@ -38,7 +41,7 @@ BENDER_LOCK = $(PB_ROOT)/Bender.lock
 # Bender flags #
 ################
 
-COMMON_TARGS += -t rtl -t cva6 -t cv64a6_imafdcsclic_sv39 -t snitch_cluster -t pb_gen_rtl
+COMMON_TARGS += -t rtl -t cva6 -t cv64a6_imafdchsclic_sv39_wb -t snitch_cluster -t pb_gen_rtl
 SIM_TARGS += -t simulation -t test -t idma_test
 
 #############
@@ -89,16 +92,14 @@ pb-addrmap: $(PB_GEN_DIR)/pb_addrmap.h $(PB_GEN_DIR)/pb_addrmap.svh
 ############
 
 CLINTCORES ?= 17
+SLINK_NUM_LANES ?= 8
+
 include $(CHS_ROOT)/cheshire.mk
 
 $(CHS_ROOT)/hw/rv_plic.cfg.hjson: $(OTPROOT)/.generated2
 $(OTPROOT)/.generated2: $(PLIC_CFG)
 	flock -x $@ sh -c "cp $< $(CHS_ROOT)/hw/" && touch $@
 
-$(CHS_ROOT)/hw/serial_link.hjson: $(CHS_SLINK_DIR)/.generated2
-$(CHS_SLINK_DIR)/.generated2:	$(SLINK_CFG)
-	flock -x $@ sh -c "cp $< $(CHS_ROOT)/hw/" && touch $@
-
 ##################
 # Snitch Cluster #
 ##################
@@ -108,7 +109,7 @@ include $(SN_ROOT)/make/common.mk
 include $(SN_ROOT)/make/rtl.mk
 
 $(SN_CFG): $(FLOO_CFG)
-	@sed -i 's/nr_clusters: .*/nr_clusters: $(SN_CLUSTERS),/' $<
+	@sed -i 's/nr_clusters: .*/nr_clusters: $(SN_CLUSTERS),/' $@
 
 .PHONY: sn-hw-clean sn-hw-all
 
@@ -129,7 +130,7 @@ ifeq ($(shell $(VERIBLE_FMT) --version >/dev/null 2>&1 && echo OK),OK)
 endif
 
 floo-hw-all: $(PB_GEN_DIR)/floo_picobello_noc_pkg.sv
-$(PB_GEN_DIR)/floo_picobello_noc_pkg.sv: $(FLOO_CFG) | $(PB_GEN_DIR)
+$(PB_GEN_DIR)/floo_picobello_noc_pkg.sv: $(FLOO_CFG)
 	$(FLOO_GEN) -c $(FLOO_CFG) -o $(PB_GEN_DIR) --only-pkg $(FLOO_GEN_FLAGS)
 
 
@@ -209,26 +210,11 @@ $(call sn_include_deps)
 # Misc #
 ########
 
-BASE_PYTHON ?= python
-PIP_CACHE_DIR ?= $(PB_ROOT)/.cache/pip
-
-.PHONY: dvt-flist python-venv python-venv-clean verible-fmt
+.PHONY: dvt-flist verible-fmt
 
 dvt-flist:
 	$(BENDER) script flist-plus $(COMMON_TARGS) $(SIM_TARGS) > .dvt/default.build
 
-python-venv: .venv
-.venv:
-	$(BASE_PYTHON) -m venv $@
-	. $@/bin/activate && \
-	python -m pip install --upgrade pip setuptools && \
-	python -m pip install --cache-dir $(PIP_CACHE_DIR) -r requirements.txt && \
-	python -m pip install --cache-dir $(PIP_CACHE_DIR) $(shell $(BENDER) path floo_noc) --no-deps && \
-	python -m pip install --cache-dir $(PIP_CACHE_DIR) "$(shell $(BENDER) path snitch_cluster)[kernels]"
-
-python-venv-clean:
-	rm -rf .venv
-
 verible-fmt:
 	$(VERIBLE_FMT) $(VERIBLE_FMT_ARGS) $(shell $(BENDER) script flist $(SIM_TARGS) --no-deps)
 
diff --git a/README.md b/README.md
index a91d7e00..b1978e03 100644
--- a/README.md
+++ b/README.md
@@ -4,7 +4,7 @@
 
 *picobello* is developed as part of the [PULP (Parallel Ultra-Low Power) project](https://pulp-platform.org/), a joint effort between ETH Zurich and the University of Bologna. *picobello* is also supported by the [EUPilot project](https://eupilot.eu), under the name MLS.
 
-## 🚧 Getting started (currently in early development)
+## ⚡ Getting started
 
 ### Environment setup for IIS-members
 
@@ -24,17 +24,15 @@ For non-IIS members, there is some additional setup required to get the environm
 
 The first requirement you need to install is `bender`. Check the [installation page](https://github.com/pulp-platform/bender/tree/master?tab=readme-ov-file#installation) on how to set it up.
 
-#### Virtual Python environment
+#### Python environment
 
-You need to have a python>=3.11 installed, in order to create the virtual python environment:
+To generate certain source files with python you need to have [uv](https://docs.astral.sh/uv/) installed, which will create the virtual environment and install the required dependencies. To set up the environment, run:
 
 ```bash
-make python-venv
+uv sync --locked
 source .venv/bin/activate
 ```
 
-By default, it will use the `python` in your `$PATH`. If you want to use a specific python version, you can set the `BASE_PYTHON` environment variable accordingly.
-
 #### Toolchains
 
 Picobello requires two different toolchains at the moment:
diff --git a/cfg/serial_link.hjson b/cfg/serial_link.hjson
deleted file mode 100644
index 9ae76b47..00000000
--- a/cfg/serial_link.hjson
+++ /dev/null
@@ -1,276 +0,0 @@
-// Copyright 2022 ETH Zurich and University of Bologna.
-// Licensed under the Apache License, Version 2.0, see LICENSE for details.
-// SPDX-License-Identifier: Apache-2.0
-//
-// Author: Tim Fischer <fischeti@iis.ee.ethz.ch>
-
-{
-  name: "serial_link_single_channel",
-  clock_primary: "clk_i"
-  reset_primary: "rst_ni"
-  bus_interfaces: [
-      { protocol: "reg_iface", direction: "device"}
-  ]
-  regwidth: "32",
-  param_list: [
-    { name: "NumChannels",
-      desc: "Number of channels",
-      type: "int",
-      default: "1",
-      local: "true"
-    },
-    { name: "Log2NumChannels",
-      desc: "Number of channels",
-      type: "int",
-      default: "1",
-      local: "true"
-    },
-    { name: "NumBits",
-      desc: "Number of bits transfered in one clock cycle (2 * NumLanes)",
-      type: "int",
-      default: "16",
-      local: "true"
-    },
-    { name: "Log2MaxClkDiv",
-      desc: "Number of bits for clock divider counter",
-      type: "int",
-      default: "10",
-      local: "true"
-    },
-    { name: "Log2RawModeTXFifoDepth",
-      desc: "The depth of the TX FIFO for raw mode operation."
-      type: "int",
-      default: "3",
-      local: "true"
-    }
-  ],
-
-  registers: [
-    {
-      name: "CTRL",
-      desc: "Global clock, isolation and reset control configuration"
-      swaccess: "rw",
-      hwaccess: "hro",
-      // Clock disabled (i.e. gated) by default
-      fields: [
-        {
-          bits: "0",
-          name: "clk_ena",
-          desc: "Clock gate enable for network, link, physical layer. (active-high)",
-          resval: 0,
-        },
-        {
-          bits: "1",
-          name: "reset_n",
-          resval: 1,
-          // *Not* held in reset (i.e. signal high) by default.
-          // Since clock is gated on reset, inner serial link state should *not* change until ungate
-          desc: "SW controlled synchronous reset. (active-low)"
-        },
-        // All channels isolated by default
-        {
-          bits: "8",
-          name: "axi_in_isolate",
-          resval: 1,
-          desc: "Isolate AXI slave in port. (active-high)"
-        },
-        {
-          bits: "9",
-          name: "axi_out_isolate",
-          resval: 1,
-          desc: "Isolate AXI master out port. (active-high)"
-        }
-      ]
-    },
-    {
-      name: "ISOLATED",
-      desc: "Isolation status of AXI ports",
-      swaccess: "ro",
-      hwaccess: "hwo",
-      hwqe: "true",
-      hwext: "true",
-      // All channels isolated by default
-      fields: [
-        {bits: "0:0", name: "axi_in",  resval: 1, desc: "slave in isolation status"},
-        {bits: "1:1", name: "axi_out", resval: 1, desc: "master out isolation status"},
-      ]
-    },
-    { multireg:
-      {
-        name: "TX_PHY_CLK_DIV",
-        desc: "Holds clock divider factor for forwarded clock of the TX Phys",
-        count: "NumChannels",
-        cname: "TX_PHY_CLK_DIV",
-        swaccess: "rw",
-        hwaccess: "hro",
-        compact: false,
-        fields: [
-          { bits: "Log2MaxClkDiv:0",
-            desc: "Clock division factor of TX clock",
-            name: "clk_divs",
-            resval: 8
-          }
-        ]
-      }
-    },
-    { multireg:
-      {
-        name: "TX_PHY_CLK_START",
-        desc: "Controls duty cycle and phase of rising and falling edge in TX Phys",
-        count: "NumChannels",
-        cname: "TX_PHY_CLK_START",
-        compact: false,
-        swaccess: "rw",
-        hwaccess: "hro",
-        fields: [
-          { bits: "Log2MaxClkDiv:0",
-            name: "clk_shift_start",
-            desc: "Positive Edge of divided, shifted clock",
-            resval: 2
-          }
-        ]
-      }
-    },
-    { multireg:
-      {
-        name: "TX_PHY_CLK_END",
-        desc: "Controls duty cycle and phase of falling edge in TX Phys",
-        count: "NumChannels",
-        cname: "TX_PHY_CLK_END",
-        compact: false,
-        swaccess: "rw",
-        hwaccess: "hro",
-        fields: [
-          { bits: "Log2MaxClkDiv:0",
-            name: "clk_shift_end",
-            desc: "Negative Edge of divided, shifted clock",
-            resval: 6
-          }
-        ]
-      }
-    },
-    {
-      name: "RAW_MODE_EN",
-      desc: "Enables Raw mode",
-      swaccess: "wo",
-      hwaccess: "hro",
-      fields: [
-        {bits: "0", resval: 0}
-      ]
-    },
-    {
-      name: "RAW_MODE_IN_CH_SEL",
-      desc: "Receive channel select in RAW mode",
-      swaccess: "wo",
-      hwaccess: "hro",
-      fields: [
-        { bits: "Log2NumChannels-1:0",
-          resval: 0
-        }
-      ]
-    },
-    {
-      name: "RAW_MODE_IN_DATA_VALID",
-      desc: "Mask for valid data in RX FIFOs during RAW mode.",
-      swaccess: "ro",
-      hwaccess: "hwo",
-      hwext: "true",
-      fields: [
-        { bits: "NumChannels-1:0",
-        }
-      ]
-    },
-    {
-      name: "RAW_MODE_IN_DATA",
-      desc: "Data received by the selected channel in RAW mode",
-      swaccess: "ro",
-      hwaccess: "hrw",
-      hwext: "true",
-      hwre: "true",
-      fields: [
-        { bits: "NumBits-1:0",
-        }
-      ]
-    },
-    {
-      name: "RAW_MODE_OUT_CH_MASK",
-      desc: "Selects channels to send out data in RAW mode, '1 corresponds to broadcasting",
-      swaccess: "wo",
-      hwaccess: "hro",
-      fields: [
-        { bits: "NumChannels-1:0",
-          resval: 0
-        }
-      ]
-    },
-    {
-      name: "RAW_MODE_OUT_DATA_FIFO",
-      desc: "Data that will be pushed to the RAW mode output FIFO",
-      swaccess: "wo",
-      hwaccess: "hro",
-      hwqe: "true",
-      fields: [
-        { bits: "NumBits-1:0",
-          resval: 0
-        }
-      ]
-    },
-    {
-      name: "RAW_MODE_OUT_DATA_FIFO_CTRL",
-      desc: "Status and control register for the RAW mode data out FIFO",
-      swaccess: "rw",
-      hwaccess: "hrw",
-      hwext: "true",
-      hwqe: "true",
-      fields: [
-        {
-          bits: "0",
-          name: "clear",
-          swaccess: "wo",
-          hwaccess: "hro",
-          desc: "Clears the raw mode TX FIFO.",
-        },
-        {
-          bits: "8+Log2RawModeTXFifoDepth-1:8",
-          name: "fill_state",
-          swaccess: "ro",
-          hwaccess: "hwo",
-          desc: "The number of elements currently stored in the RAW mode TX FIFO that are ready to be sent.",
-          resval: 0
-        },
-        {
-          bits: "31",
-          name: "is_full",
-          swaccess: "ro",
-          hwaccess: "hwo",
-          desc: "If '1' the FIFO is full and does not accept any more items. Any additional write to the data fill register will be ignored until there is sufficient space again.",
-          resval: 0
-        }
-      ]
-    },
-    {
-      name: "RAW_MODE_OUT_EN",
-      desc: "Enable transmission of data currently hold in the output FIFO",
-      swaccess: "rw",
-      hwaccess: "hro",
-      fields: [
-        { bits: "0",
-          resval: 0
-        }
-      ]
-    },
-    {
-      name: "FLOW_CONTROL_FIFO_CLEAR",
-      desc: "Clears the flow control Fifo",
-      swaccess: "wo",
-      hwaccess: "hro",
-      hwext: "true",
-      hwqe: "true",
-      fields: [
-        { bits: "0",
-          resval: 0
-        }
-      ]
-    },
-  ]
-}
diff --git a/hw/cheshire_tile.sv b/hw/cheshire_tile.sv
index ed406db1..11e85e61 100644
--- a/hw/cheshire_tile.sv
+++ b/hw/cheshire_tile.sv
@@ -366,21 +366,34 @@ module cheshire_tile
   csh_axi_llc_req_t dram_slink_err_req;
   csh_axi_llc_rsp_t dram_slink_err_rsp;
 
-  serial_link #(
-    .axi_req_t  (csh_axi_llc_req_t),
-    .axi_rsp_t  (csh_axi_llc_rsp_t),
-    .cfg_req_t  (csh_reg_req_t),
-    .cfg_rsp_t  (csh_reg_rsp_t),
-    .aw_chan_t  (csh_axi_llc_aw_chan_t),
-    .ar_chan_t  (csh_axi_llc_ar_chan_t),
-    .r_chan_t   (csh_axi_llc_r_chan_t),
-    .w_chan_t   (csh_axi_llc_w_chan_t),
-    .b_chan_t   (csh_axi_llc_b_chan_t),
-    .hw2reg_t   (serial_link_single_channel_reg_pkg::serial_link_single_channel_hw2reg_t),
-    .reg2hw_t   (serial_link_single_channel_reg_pkg::serial_link_single_channel_reg2hw_t),
-    .NumChannels(SlinkNumChan),
-    .NumLanes   (SlinkNumLanes),
-    .MaxClkDiv  (SlinkMaxClkDiv)
+  csh_apb_req_t     dram_link_apb_req;
+  csh_apb_resp_t    dram_link_apb_rsp;
+
+  reg_to_apb #(
+    .reg_req_t(csh_reg_req_t),
+    .reg_rsp_t(csh_reg_rsp_t),
+    .apb_req_t(csh_apb_req_t),
+    .apb_rsp_t(csh_apb_resp_t)
+  ) i_dram_slink_reg_to_apb (
+    .clk_i    (clk_i),
+    .rst_ni   (rst_ni),
+    .reg_req_i(reg_ext_req[CshRegExtDramSerialLink]),
+    .reg_rsp_o(reg_ext_rsp[CshRegExtDramSerialLink]),
+    .apb_req_o(dram_link_apb_req),
+    .apb_rsp_i(dram_link_apb_rsp)
+  );
+
+  slink #(
+    .axi_req_t(csh_axi_llc_req_t),
+    .axi_rsp_t(csh_axi_llc_rsp_t),
+    .apb_req_t(csh_apb_req_t),
+    .apb_rsp_t(csh_apb_resp_t),
+    .aw_chan_t(csh_axi_llc_aw_chan_t),
+    .ar_chan_t(csh_axi_llc_ar_chan_t),
+    .r_chan_t (csh_axi_llc_r_chan_t),
+    .w_chan_t (csh_axi_llc_w_chan_t),
+    .b_chan_t (csh_axi_llc_b_chan_t),
+    .NoRegCdc (1'b1)
   ) i_dram_serial_link (
     .clk_i,
     .rst_ni,
@@ -393,8 +406,8 @@ module cheshire_tile
     .axi_in_rsp_o (axi_llc_rsp),
     .axi_out_req_o(dram_slink_err_req),
     .axi_out_rsp_i(dram_slink_err_rsp),
-    .cfg_req_i    (reg_ext_req[CshRegExtDramSerialLink]),
-    .cfg_rsp_o    (reg_ext_rsp[CshRegExtDramSerialLink]),
+    .apb_req_i    (dram_link_apb_req),
+    .apb_rsp_o    (dram_link_apb_rsp),
     .ddr_rcv_clk_i(dram_slink_rcv_clk_i),
     .ddr_rcv_clk_o(dram_slink_rcv_clk_o),
     .ddr_i        (dram_slink_i),
@@ -424,18 +437,15 @@ module cheshire_tile
     .slv_resp_o(dram_slink_err_rsp)
   );
 
-  // to apb bus (declare type for req and resp)
-  `APB_TYPEDEF_ALL(apb, logic[CheshireCfg.AddrWidth-1:0], logic[31:0], logic[3:0])
-
-  apb_req_t                           csh_apb_req;
-  apb_resp_t                          csh_apb_rsp;
+  csh_apb_req_t                       csh_apb_req;
+  csh_apb_resp_t                      csh_apb_rsp;
   pb_soc_regs_pkg::pb_soc_regs__out_t control_reg;
 
   reg_to_apb #(
     .reg_req_t(csh_reg_req_t),
     .reg_rsp_t(csh_reg_rsp_t),
-    .apb_req_t(apb_req_t),
-    .apb_rsp_t(apb_resp_t)
+    .apb_req_t(csh_apb_req_t),
+    .apb_rsp_t(csh_apb_resp_t)
   ) i_reg_to_apb (
     .clk_i,
     .rst_ni,
diff --git a/hw/cluster_tile.sv b/hw/cluster_tile.sv
index 5d1a229d..84ef6950 100644
--- a/hw/cluster_tile.sv
+++ b/hw/cluster_tile.sv
@@ -70,7 +70,7 @@ module cluster_tile
 
   `AXI_TYPEDEF_ALL(cluster_narrow_out_dw_conv, snitch_cluster_pkg::addr_t,
                    snitch_cluster_pkg::narrow_out_id_t, data_hwpe_ctrl_t, strb_hwpe_ctrl_t,
-                   snitch_cluster_pkg::user_t)
+                   snitch_cluster_pkg::user_narrow_t)
 
   cluster_narrow_out_dw_conv_req_t cluster_narrow_out_dw_conv_req, cluster_narrow_out_cut_req;
   cluster_narrow_out_dw_conv_resp_t cluster_narrow_out_dw_conv_rsp, cluster_narrow_out_cut_rsp;
@@ -105,8 +105,20 @@ module cluster_tile
     .narrow_ext_req_o (cluster_narrow_ext_req),
     .narrow_ext_resp_i(cluster_narrow_ext_rsp),
     .tcdm_ext_req_i   (cluster_tcdm_ext_req_aligned),
-    .tcdm_ext_resp_o  (cluster_tcdm_ext_rsp_aligned)
-  );
+    .tcdm_ext_resp_o  (cluster_tcdm_ext_rsp_aligned),
+    .x_issue_req_o(),
+    .x_issue_resp_i('0),
+    .x_issue_valid_o(),
+    .x_issue_ready_i('0),
+    .x_register_o(),
+    .x_register_valid_o(),
+    .x_register_ready_i('0),
+    .x_commit_o(),
+    .x_commit_valid_o(),
+    .x_result_i('0),
+    .x_result_valid_i('0),
+    .x_result_ready_o()
+    );
 
   if (UseHWPE) begin : gen_hwpe
 
diff --git a/iis-env.sh b/iis-env.sh
index 87dffd81..8f03190d 100644
--- a/iis-env.sh
+++ b/iis-env.sh
@@ -6,17 +6,11 @@
 export VSIM="questa-2023.4 vsim"
 export VOPT="questa-2023.4 vopt"
 export VLIB="questa-2023.4 vlib"
-export BASE_PYTHON=/usr/local/anaconda3/bin/python3.11
 export CHS_SW_GCC_BINROOT=/usr/pack/riscv-1.0-kgf/riscv64-gcc-12.2.0/bin
 export VERIBLE_FMT="oseda -2025.03 verible-verilog-format"
-export SN_LLVM_BINROOT=/usr/scratch2/vulcano/colluca/tools/riscv32-snitch-llvm-almalinux8-15.0.0-snitch-0.2.0/bin
+export SN_LLVM_BINROOT=/usr/scratch2/vulcano/colluca/tools/riscv32-snitch-llvm-almalinux8-15.0.0-snitch-0.5.0/bin
 
-# Create the python venv
-if [ ! -d ".venv" ]; then
-  make python-venv
-fi
+export UV_LINK_MODE=copy
 
-# Activate the python venv only if not already active
-if [ -z "$VIRTUAL_ENV" ] || [ "$VIRTUAL_ENV" != "$(realpath .venv)" ]; then
-  source .venv/bin/activate
-fi
+/usr/local/uv/uv sync --locked
+source .venv/bin/activate
diff --git a/pyproject.toml b/pyproject.toml
new file mode 100644
index 00000000..5121513e
--- /dev/null
+++ b/pyproject.toml
@@ -0,0 +1,29 @@
+# Copyright 2025 ETH Zurich and University of Bologna.
+# Licensed under the Apache License, Version 2.0, see LICENSE for details.
+# SPDX-License-Identifier: Apache-2.0
+
+[project]
+name = "picobello"
+version = "0.1.0"
+description = "whatever it means"
+readme = "README.md"
+requires-python = ">=3.11"
+
+dependencies = [
+    "flatdict>=4.0.1",
+    "floogen",
+    "hjson>=3.1.0",
+    "peakrdl>=1.5.0",
+    "peakrdl-rawheader>=0.2.2",
+    "snitch[kernels]",
+]
+
+[tool.uv.workspace]
+members = [
+    ".deps/floo_noc",
+    ".deps/snitch_cluster",
+]
+
+[tool.uv.sources]
+floogen = { workspace = true, editable = true }
+snitch = { workspace = true, editable = true }
diff --git a/requirements.txt b/requirements.txt
deleted file mode 100644
index 78565385..00000000
--- a/requirements.txt
+++ /dev/null
@@ -1,29 +0,0 @@
-# Copyright 2025 ETH Zurich and University of Bologna.
-# Solderpad Hardware License, Version 0.51, see LICENSE for details.
-# SPDX-License-Identifier: SHL-0.51
-
-# FlooNoC requirements
-click
-mako
-matplotlib
-networkx
-pydantic
-ruamel.yaml
-
-# Snitch cluster requirements
-json5
-jsonref
-jsonschema
-
-# Cheshire requirements
-pyyaml
-flatdict
-tabulate
-
-# Miscellaneous requirements
-hjson  # for reggen
-
-# For peakrdl
-peakrdl
-peakrdl-rawheader @ git+https://github.com/colluca/PeakRDL-rawheader.git@7b8dbc9ad5854dc1cdaf36d4ea024c29ffb00a4c
-peakrdl-markdown
diff --git a/sw/snitch/runtime/src/pb_team.h b/sw/snitch/runtime/src/pb_team.h
index 1fa8d8d0..2e70c8be 100644
--- a/sw/snitch/runtime/src/pb_team.h
+++ b/sw/snitch/runtime/src/pb_team.h
@@ -26,8 +26,8 @@ inline uintptr_t pb_l2_tile_address(uint32_t tile_idx) {
  * @return Address location offset respect to the tile start address
  */
 inline uintptr_t pb_l2_tile_offset(uintptr_t src_addr) {
-    return (src_addr - PICOBELLO_ADDRMAP_L2_SPM_0_BASE_ADDR) %
-        PICOBELLO_ADDRMAP_L2_SPM_0_SIZE;
+    return (src_addr - PICOBELLO_ADDRMAP_L2_SPM_BASE_ADDR(0)) %
+        PICOBELLO_ADDRMAP_L2_SPM_SIZE;
 }
 
 
diff --git a/sw/snitch/runtime/src/snrt.S b/sw/snitch/runtime/src/snrt.S
index 89fa8995..a72e956b 100644
--- a/sw/snitch/runtime/src/snrt.S
+++ b/sw/snitch/runtime/src/snrt.S
@@ -12,7 +12,7 @@
 #define SNRT_CRT0_PARK
 
 #include "pb_raw_addrmap.h"
-#define SNRT_TCDM_START_ADDR PICOBELLO_ADDRMAP_CLUSTER_0_TCDM_BASE_ADDR
+#define SNRT_TCDM_START_ADDR PICOBELLO_ADDRMAP_CLUSTER_BASE_ADDR(0)
 
 #include "snitch_cluster_cfg.h"
 #include "start.S"
diff --git a/sw/snitch/runtime/src/snrt.h b/sw/snitch/runtime/src/snrt.h
index 8959c80a..f629afcb 100644
--- a/sw/snitch/runtime/src/snrt.h
+++ b/sw/snitch/runtime/src/snrt.h
@@ -9,11 +9,11 @@
 
 // Configuration- and system-specific definitions (HAL)
 #include "pb_addrmap.h"
+#include "pb_noc_cfg.h"
+#include "pb_raw_addrmap.h"
 #include "snitch_cluster_cfg.h"
 #include "snitch_cluster_peripheral_addrmap.h"
-#include "pb_raw_addrmap.h"
-#include "pb_noc_cfg.h"
-#define SNRT_TCDM_START_ADDR PICOBELLO_ADDRMAP_CLUSTER_0_TCDM_BASE_ADDR
+#define SNRT_TCDM_START_ADDR PICOBELLO_ADDRMAP_CLUSTER_BASE_ADDR(0)
 
 // TODO: the 40000 stride is hardcoded here, but it would better be
 //       autogenerated by Floogen. At the same time that would be
@@ -44,6 +44,7 @@ typedef snitch_cluster__stride40000_t snitch_cluster_t;
 #include "kmp.h"
 #include "omp.h"
 #include "pb_memory.h"
+#include "pb_team.h"
 #include "perf_cnt.h"
 #include "printf.h"
 #include "riscv.h"
@@ -52,12 +53,11 @@ typedef snitch_cluster__stride40000_t snitch_cluster_t;
 #include "sync.h"
 #include "team.h"
 #include "types.h"
-#include "pb_team.h"
 
 // Accelerators
 #include "datamover/archi_datamover.h"
-#include "datamover/hal_datamover.h"
 #include "datamover/datamover_utils.h"
+#include "datamover/hal_datamover.h"
 #include "redmule/archi_redmule.h"
 #include "redmule/hal_redmule.h"
 #include "redmule/redmule_utils.h"
diff --git a/target/sim/include/tb_picobello_tasks.svh b/target/sim/include/tb_picobello_tasks.svh
index 9158a327..b7385071 100644
--- a/target/sim/include/tb_picobello_tasks.svh
+++ b/target/sim/include/tb_picobello_tasks.svh
@@ -19,34 +19,34 @@ import picobello_pkg::*;
 task automatic jtag_enable_tiles();
   $display("Resetting tiles and enabling clock...");
   fix.vip.jtag_init();
-  fix.vip.jtag_write_reg32(`PICOBELLO_ADDRMAP_CHESHIRE_INTERNAL_PB_SOC_REGS_CLUSTER_RSTS_REG_ADDR, 32'h0000FFFF, 1'b1);
-  fix.vip.jtag_write_reg32(`PICOBELLO_ADDRMAP_CHESHIRE_INTERNAL_PB_SOC_REGS_MEM_TILE_RSTS_REG_ADDR, 32'h000000FF, 1'b1);
-  fix.vip.jtag_write_reg32(`PICOBELLO_ADDRMAP_CHESHIRE_INTERNAL_PB_SOC_REGS_FHG_SPU_RSTS_REG_ADDR, 32'h00000001, 1'b1);
-  fix.vip.jtag_write_reg32(`PICOBELLO_ADDRMAP_CHESHIRE_INTERNAL_PB_SOC_REGS_CLUSTER_RSTS_REG_ADDR, 32'h00000000, 1'b1);
-  fix.vip.jtag_write_reg32(`PICOBELLO_ADDRMAP_CHESHIRE_INTERNAL_PB_SOC_REGS_MEM_TILE_RSTS_REG_ADDR, 32'h00000000, 1'b1);
-  fix.vip.jtag_write_reg32(`PICOBELLO_ADDRMAP_CHESHIRE_INTERNAL_PB_SOC_REGS_FHG_SPU_RSTS_REG_ADDR, 32'h00000000, 1'b1);
-  fix.vip.jtag_write_reg32(`PICOBELLO_ADDRMAP_CHESHIRE_INTERNAL_PB_SOC_REGS_CLUSTER_RSTS_REG_ADDR, 32'h0000FFFF, 1'b1);
-  fix.vip.jtag_write_reg32(`PICOBELLO_ADDRMAP_CHESHIRE_INTERNAL_PB_SOC_REGS_MEM_TILE_RSTS_REG_ADDR, 32'h000000FF, 1'b1);
-  fix.vip.jtag_write_reg32(`PICOBELLO_ADDRMAP_CHESHIRE_INTERNAL_PB_SOC_REGS_FHG_SPU_RSTS_REG_ADDR, 32'h00000001, 1'b1);
-  fix.vip.jtag_write_reg32(`PICOBELLO_ADDRMAP_CHESHIRE_INTERNAL_PB_SOC_REGS_CLUSTER_CLK_ENABLES_REG_ADDR, 32'h0000FFFF, 1'b1);
-  fix.vip.jtag_write_reg32(`PICOBELLO_ADDRMAP_CHESHIRE_INTERNAL_PB_SOC_REGS_MEM_TILE_CLK_ENABLES_REG_ADDR, 32'h000000FF, 1'b1);
-  fix.vip.jtag_write_reg32(`PICOBELLO_ADDRMAP_CHESHIRE_INTERNAL_PB_SOC_REGS_FHG_SPU_CLK_ENABLES_REG_ADDR, 32'h00000001, 1'b1);
+  fix.vip.jtag_write_reg32(`PICOBELLO_ADDRMAP_CHESHIRE_INTERNAL_PB_SOC_REGS_CLUSTER_RSTS_BASE_ADDR, 32'h0000FFFF, 1'b1);
+  fix.vip.jtag_write_reg32(`PICOBELLO_ADDRMAP_CHESHIRE_INTERNAL_PB_SOC_REGS_MEM_TILE_RSTS_BASE_ADDR, 32'h000000FF, 1'b1);
+  fix.vip.jtag_write_reg32(`PICOBELLO_ADDRMAP_CHESHIRE_INTERNAL_PB_SOC_REGS_FHG_SPU_RSTS_BASE_ADDR, 32'h00000001, 1'b1);
+  fix.vip.jtag_write_reg32(`PICOBELLO_ADDRMAP_CHESHIRE_INTERNAL_PB_SOC_REGS_CLUSTER_RSTS_BASE_ADDR, 32'h00000000, 1'b1);
+  fix.vip.jtag_write_reg32(`PICOBELLO_ADDRMAP_CHESHIRE_INTERNAL_PB_SOC_REGS_MEM_TILE_RSTS_BASE_ADDR, 32'h00000000, 1'b1);
+  fix.vip.jtag_write_reg32(`PICOBELLO_ADDRMAP_CHESHIRE_INTERNAL_PB_SOC_REGS_FHG_SPU_RSTS_BASE_ADDR, 32'h00000000, 1'b1);
+  fix.vip.jtag_write_reg32(`PICOBELLO_ADDRMAP_CHESHIRE_INTERNAL_PB_SOC_REGS_CLUSTER_RSTS_BASE_ADDR, 32'h0000FFFF, 1'b1);
+  fix.vip.jtag_write_reg32(`PICOBELLO_ADDRMAP_CHESHIRE_INTERNAL_PB_SOC_REGS_MEM_TILE_RSTS_BASE_ADDR, 32'h000000FF, 1'b1);
+  fix.vip.jtag_write_reg32(`PICOBELLO_ADDRMAP_CHESHIRE_INTERNAL_PB_SOC_REGS_FHG_SPU_RSTS_BASE_ADDR, 32'h00000001, 1'b1);
+  fix.vip.jtag_write_reg32(`PICOBELLO_ADDRMAP_CHESHIRE_INTERNAL_PB_SOC_REGS_CLUSTER_CLK_ENABLES_BASE_ADDR, 32'h0000FFFF, 1'b1);
+  fix.vip.jtag_write_reg32(`PICOBELLO_ADDRMAP_CHESHIRE_INTERNAL_PB_SOC_REGS_MEM_TILE_CLK_ENABLES_BASE_ADDR, 32'h000000FF, 1'b1);
+  fix.vip.jtag_write_reg32(`PICOBELLO_ADDRMAP_CHESHIRE_INTERNAL_PB_SOC_REGS_FHG_SPU_CLK_ENABLES_BASE_ADDR, 32'h00000001, 1'b1);
 endtask
 
 task automatic slink_enable_tiles();
   $display("[SLINK] Resetting tiles and enabling clock...");
-  fix.vip.slink_write_32(`PICOBELLO_ADDRMAP_CHESHIRE_INTERNAL_PB_SOC_REGS_CLUSTER_RSTS_REG_ADDR, 32'h0000FFFF);
-  fix.vip.slink_write_32(`PICOBELLO_ADDRMAP_CHESHIRE_INTERNAL_PB_SOC_REGS_MEM_TILE_RSTS_REG_ADDR, 32'h000000FF);
-  fix.vip.slink_write_32(`PICOBELLO_ADDRMAP_CHESHIRE_INTERNAL_PB_SOC_REGS_FHG_SPU_RSTS_REG_ADDR, 32'h00000001);
-  fix.vip.slink_write_32(`PICOBELLO_ADDRMAP_CHESHIRE_INTERNAL_PB_SOC_REGS_CLUSTER_RSTS_REG_ADDR, 32'h00000000);
-  fix.vip.slink_write_32(`PICOBELLO_ADDRMAP_CHESHIRE_INTERNAL_PB_SOC_REGS_MEM_TILE_RSTS_REG_ADDR, 32'h00000000);
-  fix.vip.slink_write_32(`PICOBELLO_ADDRMAP_CHESHIRE_INTERNAL_PB_SOC_REGS_FHG_SPU_RSTS_REG_ADDR, 32'h00000000);
-  fix.vip.slink_write_32(`PICOBELLO_ADDRMAP_CHESHIRE_INTERNAL_PB_SOC_REGS_CLUSTER_RSTS_REG_ADDR, 32'h0000FFFF);
-  fix.vip.slink_write_32(`PICOBELLO_ADDRMAP_CHESHIRE_INTERNAL_PB_SOC_REGS_MEM_TILE_RSTS_REG_ADDR, 32'h000000FF);
-  fix.vip.slink_write_32(`PICOBELLO_ADDRMAP_CHESHIRE_INTERNAL_PB_SOC_REGS_FHG_SPU_RSTS_REG_ADDR, 32'h00000001);
-  fix.vip.slink_write_32(`PICOBELLO_ADDRMAP_CHESHIRE_INTERNAL_PB_SOC_REGS_CLUSTER_CLK_ENABLES_REG_ADDR, 32'h0000FFFF);
-  fix.vip.slink_write_32(`PICOBELLO_ADDRMAP_CHESHIRE_INTERNAL_PB_SOC_REGS_MEM_TILE_CLK_ENABLES_REG_ADDR, 32'h000000FF);
-  fix.vip.slink_write_32(`PICOBELLO_ADDRMAP_CHESHIRE_INTERNAL_PB_SOC_REGS_FHG_SPU_CLK_ENABLES_REG_ADDR, 32'h00000001);
+  fix.vip.slink_write_32(`PICOBELLO_ADDRMAP_CHESHIRE_INTERNAL_PB_SOC_REGS_CLUSTER_RSTS_BASE_ADDR, 32'h0000FFFF);
+  fix.vip.slink_write_32(`PICOBELLO_ADDRMAP_CHESHIRE_INTERNAL_PB_SOC_REGS_MEM_TILE_RSTS_BASE_ADDR, 32'h000000FF);
+  fix.vip.slink_write_32(`PICOBELLO_ADDRMAP_CHESHIRE_INTERNAL_PB_SOC_REGS_FHG_SPU_RSTS_BASE_ADDR, 32'h00000001);
+  fix.vip.slink_write_32(`PICOBELLO_ADDRMAP_CHESHIRE_INTERNAL_PB_SOC_REGS_CLUSTER_RSTS_BASE_ADDR, 32'h00000000);
+  fix.vip.slink_write_32(`PICOBELLO_ADDRMAP_CHESHIRE_INTERNAL_PB_SOC_REGS_MEM_TILE_RSTS_BASE_ADDR, 32'h00000000);
+  fix.vip.slink_write_32(`PICOBELLO_ADDRMAP_CHESHIRE_INTERNAL_PB_SOC_REGS_FHG_SPU_RSTS_BASE_ADDR, 32'h00000000);
+  fix.vip.slink_write_32(`PICOBELLO_ADDRMAP_CHESHIRE_INTERNAL_PB_SOC_REGS_CLUSTER_RSTS_BASE_ADDR, 32'h0000FFFF);
+  fix.vip.slink_write_32(`PICOBELLO_ADDRMAP_CHESHIRE_INTERNAL_PB_SOC_REGS_MEM_TILE_RSTS_BASE_ADDR, 32'h000000FF);
+  fix.vip.slink_write_32(`PICOBELLO_ADDRMAP_CHESHIRE_INTERNAL_PB_SOC_REGS_FHG_SPU_RSTS_BASE_ADDR, 32'h00000001);
+  fix.vip.slink_write_32(`PICOBELLO_ADDRMAP_CHESHIRE_INTERNAL_PB_SOC_REGS_CLUSTER_CLK_ENABLES_BASE_ADDR, 32'h0000FFFF);
+  fix.vip.slink_write_32(`PICOBELLO_ADDRMAP_CHESHIRE_INTERNAL_PB_SOC_REGS_MEM_TILE_CLK_ENABLES_BASE_ADDR, 32'h000000FF);
+  fix.vip.slink_write_32(`PICOBELLO_ADDRMAP_CHESHIRE_INTERNAL_PB_SOC_REGS_FHG_SPU_CLK_ENABLES_BASE_ADDR, 32'h00000001);
 endtask
 
 // FAST_PRELOAD mode trick with virtual class to write directly to L2 sram module inside various for generate
@@ -155,7 +155,7 @@ task automatic fastmode_elf_preload(input string binary, output cheshire_pkg::do
   $display("[FAST_PRELOAD] Preload complete");
 endtask
 
-// Suitable for loading ELFs with 32b-aligned sections 
+// Suitable for loading ELFs with 32b-aligned sections
 task automatic jtag_32b_elf_preload(input string binary, output bit [63:0] entry);
   longint sec_addr, sec_len;
   dm::sbcs_t sbcs = dm::sbcs_t
diff --git a/target/sim/src/fixture_picobello_top.sv b/target/sim/src/fixture_picobello_top.sv
index 957262f3..5fd54ba5 100644
--- a/target/sim/src/fixture_picobello_top.sv
+++ b/target/sim/src/fixture_picobello_top.sv
@@ -138,21 +138,17 @@ module fixture_picobello_top;
   assign axi_slink_mst_req = '0;
 
   // Mirror instance of serial link, reflecting DRAM on FPGA
-  serial_link #(
-    .axi_req_t  (axi_llc_req_t),
-    .axi_rsp_t  (axi_llc_rsp_t),
-    .cfg_req_t  (reg_req_t),
-    .cfg_rsp_t  (reg_rsp_t),
-    .aw_chan_t  (axi_llc_aw_chan_t),
-    .ar_chan_t  (axi_llc_ar_chan_t),
-    .r_chan_t   (axi_llc_r_chan_t),
-    .w_chan_t   (axi_llc_w_chan_t),
-    .b_chan_t   (axi_llc_b_chan_t),
-    .hw2reg_t   (serial_link_single_channel_reg_pkg::serial_link_single_channel_hw2reg_t),
-    .reg2hw_t   (serial_link_single_channel_reg_pkg::serial_link_single_channel_reg2hw_t),
-    .NumChannels(SlinkNumChan),
-    .NumLanes   (SlinkNumLanes),
-    .MaxClkDiv  (SlinkMaxClkDiv)
+  slink #(
+    .axi_req_t(axi_llc_req_t),
+    .axi_rsp_t(axi_llc_rsp_t),
+    .apb_req_t(csh_apb_req_t),
+    .apb_rsp_t(csh_apb_resp_t),
+    .aw_chan_t(axi_llc_aw_chan_t),
+    .ar_chan_t(axi_llc_ar_chan_t),
+    .r_chan_t (axi_llc_r_chan_t),
+    .w_chan_t (axi_llc_w_chan_t),
+    .b_chan_t (axi_llc_b_chan_t),
+    .NoRegCdc (1'b1)
   ) i_dram_serial_link (
     .clk_i        (clk),
     .rst_ni       (rst_n),
@@ -165,8 +161,8 @@ module fixture_picobello_top;
     .axi_in_rsp_o (),
     .axi_out_req_o(axi_llc_mst_req),
     .axi_out_rsp_i(axi_llc_mst_rsp),
-    .cfg_req_i    ('0),
-    .cfg_rsp_o    (),
+    .apb_req_i    ('0),
+    .apb_rsp_o    (),
     .ddr_rcv_clk_i(dram_slink_rcv_clk_o),
     .ddr_rcv_clk_o(dram_slink_rcv_clk_i),
     .ddr_i        (dram_slink_o),
diff --git a/target/sim/vsim/vsim.mk b/target/sim/vsim/vsim.mk
index 40e0ad30..7ebe816c 100644
--- a/target/sim/vsim/vsim.mk
+++ b/target/sim/vsim/vsim.mk
@@ -57,4 +57,4 @@ vsim-run-batch:
 vsim-run-batch-verify: vsim-run-batch
 ifdef VERIFY_PY
 	$(VERIFY_PY) placeholder $(SN_BINARY) --no-ipc --memdump l2mem.bin --memaddr 0x70000000
-endif
\ No newline at end of file
+endif
diff --git a/uv.lock b/uv.lock
new file mode 100644
index 00000000..24051ff0
--- /dev/null
+++ b/uv.lock
@@ -0,0 +1,2808 @@
+version = 1
+revision = 3
+requires-python = ">=3.11"
+resolution-markers = [
+    "python_full_version >= '3.12' and sys_platform != 'darwin'",
+    "python_full_version >= '3.12' and sys_platform == 'darwin'",
+    "python_full_version < '3.12' and sys_platform != 'darwin'",
+    "python_full_version < '3.12' and sys_platform == 'darwin'",
+]
+
+[manifest]
+members = [
+    "floogen",
+    "picobello",
+    "snitch",
+]
+
+[[package]]
+name = "annotated-types"
+version = "0.7.0"
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