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nightly nightly #3: Scheduled
23h 40m 35s main
main
23h 40m 35s
Add Open External Contributor PRs and Issues to PyTorch Org Project 136 Add Open External Contributor PRs and Issues to PyTorch Org Project 136 #6: Scheduled
7s main
main
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Add Open External Contributor PRs and Issues to PyTorch Org Project 136 Add Open External Contributor PRs and Issues to PyTorch Org Project 136 #5: Scheduled
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Apple Apple #4: Scheduled
21s main
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Android Release Artifacts Android Release Artifacts #2: Scheduled
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Cadence Build & Test Cadence Build & Test #17: Scheduled
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Pico2 Build Validation Pico2 Build Validation #3: Scheduled
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1d 0h 0m 2s
Test ARM Backend Test ARM Backend #13: Scheduled
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nightly nightly #2: Scheduled
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Add Open External Contributor PRs and Issues to PyTorch Org Project 136 Add Open External Contributor PRs and Issues to PyTorch Org Project 136 #4: Scheduled
7s main
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Pin Bump CI Handler Pin Bump CI Handler #11: completed by luhenry
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Pin Bump CI Handler Pin Bump CI Handler #10: completed by luhenry
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Add Open External Contributor PRs and Issues to PyTorch Org Project 136 Add Open External Contributor PRs and Issues to PyTorch Org Project 136 #3: Scheduled
11s main
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Pin Bump CI Handler Pin Bump CI Handler #9: completed by luhenry
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Pin Bump CI Handler Pin Bump CI Handler #8: completed by luhenry
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Apple Apple #3: Scheduled
15s main
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Android Release Artifacts Android Release Artifacts #1: Scheduled
1d 0h 0m 11s main
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1d 0h 0m 11s
Cadence Build & Test Cadence Build & Test #16: Scheduled
1d 0h 0m 3s main
main
1d 0h 0m 3s
Pico2 Build Validation Pico2 Build Validation #2: Scheduled
1d 0h 0m 2s main
main
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Test ARM Backend Test ARM Backend #12: Scheduled
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nightly nightly #1: Scheduled
1d 0h 0m 2s main
main
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Add Open External Contributor PRs and Issues to PyTorch Org Project 136 Add Open External Contributor PRs and Issues to PyTorch Org Project 136 #2: Scheduled
9s main
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Pin Bump CI Handler Pin Bump CI Handler #7: completed by luhenry
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Add RISC-V Phase 1 (QEMU) smoke test Test ARM Backend #11: Pull request #2 synchronize by luhenry
1d 0h 0m 3s riscv-testing
riscv-testing
1d 0h 0m 3s
Add RISC-V Phase 1 (QEMU) smoke test pull #15: Pull request #2 synchronize by luhenry
1d 0h 0m 15s riscv-testing
riscv-testing
1d 0h 0m 15s
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