Hi, I am currently developing an open-source project and evaluating your RISC-V runners for our CI/CD pipeline.
Since our project currently only supports Arm32 and RV32 architectures, I am looking for a environment to validate whether our built RV32 binaries can execute correctly on physical RISC-V hardware.
I noticed in your FAQ that the runners currently support riscv64 only and do not utilize emulation. However, I would like to clarify: Do your runners have the capability to execute riscv32 binaries? For instance, is the kernel configured with the CONFIG_COMPAT option enabled to support 32-bit user-space execution?"
Hi, I am currently developing an open-source project and evaluating your RISC-V runners for our CI/CD pipeline.
Since our project currently only supports Arm32 and RV32 architectures, I am looking for a environment to validate whether our built RV32 binaries can execute correctly on physical RISC-V hardware.
I noticed in your FAQ that the runners currently support riscv64 only and do not utilize emulation. However, I would like to clarify: Do your runners have the capability to execute riscv32 binaries? For instance, is the kernel configured with the
CONFIG_COMPAToption enabled to support 32-bit user-space execution?"