diff --git a/.gitignore b/.gitignore index 1b4fdc8..8f235fb 100644 --- a/.gitignore +++ b/.gitignore @@ -2,6 +2,8 @@ build/ build_sdl/ external/ kernel/kernel -kernel/cherryusb *.o +*.iso +*.img nuklear_cherry_usb +iso_root/ diff --git a/Makefile b/Makefile index 1915b52..a242405 100644 --- a/Makefile +++ b/Makefile @@ -4,42 +4,46 @@ LD = ld CFLAGS = -Wall -Wextra -std=c11 -ffreestanding -fno-stack-protector \ -fno-stack-check -fno-lto -fno-pic -m64 -march=x86-64 -mcmodel=kernel \ -mno-red-zone -fno-asynchronous-unwind-tables \ - -I./include -I./kernel -I./kernel/drivers \ - -I./external/limine \ - -I./external/CherryUSB/common \ - -I./external/CherryUSB/core \ - -I./external/CherryUSB/class/msc \ - -I./external/CherryUSB/class/hid \ - -I./external/CherryUSB/class/hub \ + -I./include -I./kernel -I./kernel/drivers -I./kernel/fatfs \ + -I./kernel/cherryusb/common \ + -I./kernel/cherryusb/core \ + -I./kernel/cherryusb/class/msc \ + -I./kernel/cherryusb/class/hid \ + -I./kernel/cherryusb/class/hub \ -include kernel/usb_config.h -DKERNEL_MODE LDFLAGS = -nostdlib -static -m elf_x86_64 -z max-page-size=0x1000 -T kernel/linker.ld -# All Source Objects -KERNEL_OBJS = kernel/kernel.o src/app_ui.o kernel/nuklear_kernel_impl.o \ - src/nk_software_renderer.o kernel/usb_osal.o \ - kernel/usb_hal_ports.o kernel/storage.o kernel/input.o \ - kernel/usb_hal.o kernel/vfs.o kernel/scheduler.o \ - kernel/i18n.o kernel/uac_policy.o kernel/tgx_impl.o \ - kernel/tlsf_impl.o kernel/math.o kernel/panic.o \ - kernel/malloc_glue.o kernel/storage_hal.o kernel/panic_hal.o \ +KERNEL_OBJS = kernel/kernel.o src/app_ui.o src/chell.o src/lab.o src/installer.o \ + kernel/idt.o kernel/nuklear_kernel_impl.o src/nk_software_renderer.o \ + kernel/usb_osal.o kernel/usb_hal_ports.o \ + kernel/input.o kernel/usb_hal.o kernel/vfs.o \ + kernel/scheduler.o kernel/i18n.o kernel/uac_policy.o \ + kernel/tgx_impl.o kernel/tlsf_impl.o kernel/math.o \ + kernel/panic.o kernel/serial.o kernel/acpi.o kernel/pmm.o kernel/malloc_glue.o kernel/storage.o kernel/device_manager.o kernel/rsl_storage.o \ + kernel/diskio_impl.o kernel/ffsystem_impl.o \ + kernel/ff_partitions.o kernel/fatfs/ff.o kernel/fatfs/ffunicode.o \ kernel/drivers/pci.o kernel/drivers/xhci.o kernel/drivers/ehci.o \ kernel/drivers/nvme.o kernel/drivers/ahci.o \ - external/CherryUSB/core/usbd_core.o \ - external/CherryUSB/core/usbh_core.o \ - external/CherryUSB/class/msc/usbh_msc.o \ - external/CherryUSB/class/hid/usbh_hid.o \ - external/CherryUSB/class/hub/usbh_hub.o \ - external/CherryUSB/port/ehci/usb_hc_ehci.o + kernel/cherryusb/core/usbd_core.o \ + kernel/cherryusb/core/usbh_core.o \ + kernel/cherryusb/class/msc/usbh_msc.o \ + kernel/cherryusb/class/hid/usbh_hid.o \ + kernel/cherryusb/class/hub/usbh_hub.o \ + kernel/cherryusb/port/ehci/usb_hc_ehci.o -.PHONY: all clean environment iso run +.PHONY: all clean iso run environment -all: environment kernel/kernel iso +all: environment hdd.img kernel/kernel iso environment: chmod +x build.sh ./build.sh +hdd.img: + chmod +x scripts/gen_disk.sh + ./scripts/gen_disk.sh + kernel/kernel: $(KERNEL_OBJS) $(LD) $(LDFLAGS) $(KERNEL_OBJS) -o kernel/kernel @@ -47,21 +51,14 @@ kernel/kernel: $(KERNEL_OBJS) $(CC) $(CFLAGS) -c $< -o $@ iso: kernel/kernel - mkdir -p iso_root/boot/sys - cp kernel/kernel iso_root/boot/sys/kernel.elf - cp kernel/limine.conf iso_root/boot/ - cp external/limine/limine-bios.sys iso_root/boot/ - cp external/limine/limine-bios-cd.bin iso_root/boot/ - xorriso -as mkisofs -b boot/limine-bios-cd.bin \ - -no-emul-boot -boot-load-size 4 -boot-info-table \ - iso_root -o os.iso - ./external/limine/limine bios-install os.iso + chmod +x scripts/make_iso.sh + ./scripts/make_iso.sh QEMU = qemu-system-x86_64 QEMU_FLAGS = -m 512M -cdrom os.iso -boot d -device qemu-xhci -device usb-kbd -device usb-mouse -serial stdio -run: iso - $(QEMU) $(QEMU_FLAGS) $(EXTRA_QEMU_FLAGS) +run: all + $(QEMU) $(QEMU_FLAGS) $(EXTRA_QEMU_FLAGS) -drive file=hdd.img,format=raw,if=none,id=dr0 -device nvme,drive=dr0,serial=1234 clean: - rm -rf $(KERNEL_OBJS) kernel/kernel os.iso iso_root/boot/sys/kernel.elf iso_root/boot/limine.conf iso_root/boot/limine-bios.sys iso_root/boot/limine-bios-cd.bin + rm -rf $(KERNEL_OBJS) kernel/kernel os.iso hdd.img iso_root/ diff --git a/error.md b/error.md new file mode 100644 index 0000000..d83ffff --- /dev/null +++ b/error.md @@ -0,0 +1,19 @@ +# Sovereign OS Code Audit & Error Report (Final Hardening) + +This document outlines the state of the kernel after the 4-Stage architectural refactor and high-severity bug fixes. + +## 1. Medium Severity: Future Expansion + +### 1.1 Incomplete ACPI Table Parsing +* **Issue:** Stage 1 currently initializes ACPI by finding the RSDP and RSDT. However, it does not yet parse the MADT to enable multi-core support or the FADT for power management. +* **Consequence:** Limitation to single-core execution and legacy hardware control. + +### 1.2 Fixed PMM Bitmap Placement +* **Issue:** The PMM bitmap is placed in the first available usable memory region found during boot. While functional, it does not account for potentially fragmented memory layouts on certain hardware. +* **Consequence:** Small chance of memory overlap if a machine has extremely sparse usable regions. + +## 2. Low Severity: UI & Polish + +### 2.1 Aesthetic Cursor +* **Issue:** Software cursor is a teal bitmap arrow for better visibility but lacks hardware acceleration. +* **Consequence:** Purely aesthetic. diff --git a/include/app_ui.h b/include/app_ui.h index 7a5f15f..f6b543e 100644 --- a/include/app_ui.h +++ b/include/app_ui.h @@ -1,38 +1,16 @@ #ifndef APP_UI_H #define APP_UI_H - -#include "nuklear_config.h" -#include "nuklear.h" - +#include "pro_os.h" +typedef enum { STATE_LOGIN, STATE_INSTALLER, STATE_DESKTOP, STATE_LAB, STATE_CHELL } app_screen_t; struct app_state { - int current_state; - char username[64]; - char password[64]; - int progress; - int install_started; - - /* Desktop windows */ - int show_terminal; - int show_explorer; - int show_settings; - int show_launcher; - int show_uac; - - /* Permits */ - int perm_net; - int perm_storage; - - /* Metrics */ - int cpu_usage; + app_screen_t current_state; + void* chell; void* lab; void* installer; + int show_launcher; int show_terminal; int show_explorer; int show_settings; int show_uac; + char password[32]; int perm_net; int perm_storage; int cpu_usage; }; - -enum { - STATE_LOGIN, - STATE_INSTALLER, - STATE_DESKTOP -}; - -void ui_render(struct nk_context *ctx, struct app_state *app, int window_width, int window_height); -void ui_init_style(struct nk_context *ctx); - +void ui_init_style(struct nk_context* ctx); +void ui_render(struct nk_context* ctx, struct app_state* app, int width, int height); +void chell_init(void* state); void chell_update(struct nk_context* ctx, void* state); +void lab_init(void* state); void lab_update(struct nk_context* ctx, void* state); +void installer_init(void* state); void installer_update(struct nk_context* ctx, void* state); #endif diff --git a/include/hal.h b/include/hal.h index c0ab493..058b1e6 100644 --- a/include/hal.h +++ b/include/hal.h @@ -1,60 +1,23 @@ #ifndef HAL_H #define HAL_H - #include #include #include -/* --- Input System --- */ -typedef enum { - INPUT_TYPE_KEYBOARD, - INPUT_TYPE_MOUSE -} input_type_t; - -typedef struct { - input_type_t type; - union { - struct { - uint32_t key; - bool down; - } kbd; - struct { - int x, y; - int scroll; - uint32_t buttons; - } mouse; - }; -} input_event_t; - -void hal_input_init(void); -void hal_input_poll(void); -void hal_input_push_event(input_event_t ev); -bool hal_input_pop_event(input_event_t *ev); - -/* --- Storage System --- */ -typedef enum { - STORAGE_TYPE_USB, - STORAGE_TYPE_NVME, - STORAGE_TYPE_SATA, - STORAGE_TYPE_SATAPI -} storage_type_t; - -typedef struct { - const char *name; - storage_type_t type; - uint64_t total_blocks; - uint32_t block_size; - int (*read)(uint64_t lba, void *buffer, uint32_t count); - int (*write)(uint64_t lba, const void *buffer, uint32_t count); -} storage_device_t; - -void hal_storage_init(void); -int hal_storage_register_device(storage_device_t *dev); -int hal_storage_get_device_count(void); -storage_device_t* hal_storage_get_device(int index); - -/* --- USB System --- */ -void hal_usb_init(void); -void hal_usb_poll(void); - +typedef enum { INPUT_TYPE_KEYBOARD, INPUT_TYPE_MOUSE } input_type_t; +typedef struct { input_type_t type; union { struct { uint32_t key; bool down; } kbd; struct { int x, y; int scroll; uint32_t buttons; } mouse; }; } input_event_t; +void hal_input_init(void); void hal_input_poll(void); void hal_input_push_event(input_event_t ev); bool hal_input_pop_event(input_event_t *ev); + +typedef enum { STORAGE_TYPE_USB, STORAGE_TYPE_NVME, STORAGE_TYPE_SATA, STORAGE_TYPE_SATAPI } storage_type_t; +typedef struct storage_device storage_device_t; +struct storage_device { + const char *name; storage_type_t type; uint64_t total_blocks; uint32_t block_size; + int (*read)(storage_device_t* dev, uint64_t lba, void *buffer, uint32_t count); + int (*write)(storage_device_t* dev, uint64_t lba, const void *buffer, uint32_t count); +}; +void hal_storage_init(void); int hal_storage_register_device(storage_device_t *dev); +int hal_storage_get_device_count(void); storage_device_t* hal_storage_get_device(int index); +int hal_storage_read(storage_device_t* dev, uint64_t sector, void* buffer, uint32_t count); +int hal_storage_write(storage_device_t* dev, uint64_t sector, const void* buffer, uint32_t count); +void hal_usb_init(void); void hal_usb_poll(void); #endif diff --git a/include/idt.h b/include/idt.h new file mode 100644 index 0000000..d5eeea3 --- /dev/null +++ b/include/idt.h @@ -0,0 +1,7 @@ +#ifndef IDT_H +#define IDT_H +#include +struct idt_entry { uint16_t isr_low; uint16_t kernel_cs; uint8_t ist; uint8_t attributes; uint16_t isr_mid; uint32_t isr_high; uint32_t reserved; } __attribute__((packed)); +struct idtr { uint16_t limit; uint64_t base; } __attribute__((packed)); +void idt_init(void); +#endif diff --git a/include/pmm.h b/include/pmm.h new file mode 100644 index 0000000..2ee588f --- /dev/null +++ b/include/pmm.h @@ -0,0 +1,9 @@ +#ifndef PMM_H +#define PMM_H +#include +#include +#include "limine.h" +void pmm_init(struct limine_memmap_response* memmap); +void* pmm_alloc(size_t pages); +void pmm_free(void* ptr, size_t pages); +#endif diff --git a/include/pro_os.h b/include/pro_os.h index d4858a1..da92bd7 100644 --- a/include/pro_os.h +++ b/include/pro_os.h @@ -22,6 +22,8 @@ char* strcpy(char* dest, const char* src); int strcmp(const char* s1, const char* s2); int strncmp(const char* s1, const char* s2, size_t n); char* strchr(const char* s, int c); +#include +int vsnprintf(char* str, size_t size, const char* format, va_list ap); int snprintf(char* str, size_t size, const char* format, ...); /* Scheduler / Task Manager */ @@ -39,9 +41,22 @@ void scheduler_init(void); void scheduler_add_task(const char *name, void (*entry)(void)); void scheduler_run(void); +void pci_scan(void); +void vfs_refresh_mounts(void); +void devmgr_register_storage(storage_device_t* d); +int devmgr_get_count(void); +const char* devmgr_get_label(int index); +storage_device_t* devmgr_get_device(int index); +int devmgr_list(char* out, size_t sz); +void acpi_init(void* rsdp_addr); /* VFS */ void vfs_init(void); const char* vfs_resolve(const char *path); +int vfs_ls(const char* path, char* out, size_t sz); +int vfs_cat(const char* path, char* out, size_t sz); +int vfs_mkdir(const char* path); +int vfs_write(const char* path, const char* content); +int vfs_get_mounts(char* out, size_t sz); /* Security / UAC */ typedef struct { diff --git a/include/serial.h b/include/serial.h new file mode 100644 index 0000000..1045d71 --- /dev/null +++ b/include/serial.h @@ -0,0 +1,5 @@ +#ifndef SERIAL_H +#define SERIAL_H +#include +void serial_init(void); void serial_putc(char c); void serial_write(const char* str); void serial_printf(const char* fmt, ...); +#endif diff --git a/include/usb_osal.h b/include/usb_osal.h new file mode 100644 index 0000000..70e2afe --- /dev/null +++ b/include/usb_osal.h @@ -0,0 +1,77 @@ +/* + * Copyright (c) 2022, sakumisu + * + * SPDX-License-Identifier: Apache-2.0 + */ +#ifndef USB_OSAL_H +#define USB_OSAL_H + +#include +#include +#include + +#ifdef __INCLUDE_NUTTX_CONFIG_H +#define CONFIG_USB_OSAL_THREAD_SET_ARGV int argc, char **argv +#define CONFIG_USB_OSAL_THREAD_GET_ARGV ((uintptr_t)strtoul(argv[1], NULL, 16)) +#elif defined(__ZEPHYR__) +#define CONFIG_USB_OSAL_THREAD_SET_ARGV void *p1, void *p2, void *p3 +#define CONFIG_USB_OSAL_THREAD_GET_ARGV ((uintptr_t)p1) +#else +#define CONFIG_USB_OSAL_THREAD_SET_ARGV void *argument +#define CONFIG_USB_OSAL_THREAD_GET_ARGV ((uintptr_t)argument) +#endif + +#define USB_OSAL_WAITING_FOREVER (0xFFFFFFFFU) + +typedef void *usb_osal_thread_t; +typedef void *usb_osal_sem_t; +typedef void *usb_osal_mutex_t; +typedef void *usb_osal_mq_t; +typedef void (*usb_thread_entry_t)(CONFIG_USB_OSAL_THREAD_SET_ARGV); +typedef void (*usb_timer_handler_t)(void *argument); +struct usb_osal_timer { + usb_timer_handler_t handler; + void *argument; + bool is_period; + uint32_t timeout_ms; + void *timer; +}; + +/* + * Task with smaller priority value indicates higher task priority +*/ +usb_osal_thread_t usb_osal_thread_create(const char *name, uint32_t stack_size, uint32_t prio, usb_thread_entry_t entry, void *args); +void usb_osal_thread_delete(usb_osal_thread_t thread); +void usb_osal_thread_schedule_other(void); + +usb_osal_sem_t usb_osal_sem_create(uint32_t initial_count); +usb_osal_sem_t usb_osal_sem_create_counting(uint32_t max_count); +void usb_osal_sem_delete(usb_osal_sem_t sem); +int usb_osal_sem_take(usb_osal_sem_t sem, uint32_t timeout); +int usb_osal_sem_give(usb_osal_sem_t sem); +void usb_osal_sem_reset(usb_osal_sem_t sem); + +usb_osal_mutex_t usb_osal_mutex_create(void); +void usb_osal_mutex_delete(usb_osal_mutex_t mutex); +int usb_osal_mutex_take(usb_osal_mutex_t mutex); +int usb_osal_mutex_give(usb_osal_mutex_t mutex); + +usb_osal_mq_t usb_osal_mq_create(uint32_t max_msgs); +void usb_osal_mq_delete(usb_osal_mq_t mq); +int usb_osal_mq_send(usb_osal_mq_t mq, uintptr_t addr); +int usb_osal_mq_recv(usb_osal_mq_t mq, uintptr_t *addr, uint32_t timeout); + +struct usb_osal_timer *usb_osal_timer_create(const char *name, uint32_t timeout_ms, usb_timer_handler_t handler, void *argument, bool is_period); +void usb_osal_timer_delete(struct usb_osal_timer *timer); +void usb_osal_timer_start(struct usb_osal_timer *timer); +void usb_osal_timer_stop(struct usb_osal_timer *timer); + +size_t usb_osal_enter_critical_section(void); +void usb_osal_leave_critical_section(size_t flag); + +void usb_osal_msleep(uint32_t delay); + +void *usb_osal_malloc(size_t size); +void usb_osal_free(void *ptr); + +#endif /* USB_OSAL_H */ diff --git a/kernel/acpi.c b/kernel/acpi.c new file mode 100644 index 0000000..e110011 --- /dev/null +++ b/kernel/acpi.c @@ -0,0 +1,45 @@ +#include "pro_os.h" +#include "serial.h" +#include + +struct rsdp_descriptor { + char signature[8]; + uint8_t checksum; + char oem_id[6]; + uint8_t revision; + uint32_t rsdt_address; +} __attribute__((packed)); + +struct rsdt_header { + char signature[4]; + uint32_t length; + uint8_t revision; + uint8_t checksum; + char oem_id[6]; + char oem_table_id[8]; + uint32_t oem_revision; + uint32_t creator_id; + uint32_t creator_revision; +} __attribute__((packed)); + +void acpi_init(void* rsdp_addr) { + serial_write("[ACPI] Initializing from RSDP...\n"); + if (!rsdp_addr) { + serial_write("[ACPI] Error: NULL RSDP pointer\n"); + return; + } + + struct rsdp_descriptor* rsdp = (struct rsdp_descriptor*)rsdp_addr; + if (strncmp(rsdp->signature, "RSD PTR ", 8) != 0) { + serial_write("[ACPI] Error: Invalid RSDP signature\n"); + return; + } + + serial_printf("[ACPI] Revision: %d\n", rsdp->revision); + + // Simple RSDT parsing + struct rsdt_header* rsdt = (struct rsdt_header*)((uint64_t)rsdp->rsdt_address + hhdm_offset); + if (strncmp(rsdt->signature, "RSDT", 4) == 0) { + serial_printf("[ACPI] Found RSDT at %x\n", rsdp->rsdt_address); + } +} diff --git a/kernel/audio.c b/kernel/audio.c new file mode 100644 index 0000000..dbc650a --- /dev/null +++ b/kernel/audio.c @@ -0,0 +1,7 @@ +#define MINIAUDIO_IMPLEMENTATION +#include "pro_os.h" +#include "external/miniaudio.h" + +void hal_audio_init(void) { + serial_write("[AUDIO] Initializing Sovereign Audio Engine (Miniaudio)...\n"); +} diff --git a/kernel/cherryusb/class/adb/usbd_adb.c b/kernel/cherryusb/class/adb/usbd_adb.c new file mode 100644 index 0000000..cf7dbe8 --- /dev/null +++ b/kernel/cherryusb/class/adb/usbd_adb.c @@ -0,0 +1,308 @@ +/* + * Copyright (c) 2024, sakumisu + * + * SPDX-License-Identifier: Apache-2.0 + */ +#include "usbd_core.h" +#include "usbd_adb.h" + +#define ADB_OUT_EP_IDX 0 +#define ADB_IN_EP_IDX 1 + +#define ADB_STATE_READ_MSG 0 +#define ADB_STATE_READ_DATA 1 +#define ADB_STATE_WRITE_MSG 2 +#define ADB_STATE_WRITE_DATA 3 +#define ADB_STATE_AWRITE_MSG 4 +#define ADB_STATE_AWRITE_DATA 5 + +#define MAX_PAYLOAD_V1 (4 * 1024) +#define MAX_PAYLOAD_V2 (256 * 1024) +#define MAX_PAYLOAD MAX_PAYLOAD_V1 +#define A_VERSION 0x01000000 + +#define A_SYNC 0x434e5953 +#define A_CNXN 0x4e584e43 +#define A_OPEN 0x4e45504f +#define A_OKAY 0x59414b4f +#define A_CLSE 0x45534c43 +#define A_WRTE 0x45545257 +#define A_AUTH 0x48545541 + +struct adb_msg { + uint32_t command; /* command identifier constant (A_CNXN, ...) */ + uint32_t arg0; /* first argument */ + uint32_t arg1; /* second argument */ + uint32_t data_length; /* length of payload (0 is allowed) */ + uint32_t data_crc32; /* crc32 of data payload */ + uint32_t magic; /* command ^ 0xffffffff */ +}; + +struct adb_packet { + USB_MEM_ALIGNX struct adb_msg msg; + USB_MEM_ALIGNX uint8_t payload[USB_ALIGN_UP(MAX_PAYLOAD, CONFIG_USB_ALIGN_SIZE)]; +}; + +struct usbd_adb { + uint8_t state; + uint8_t common_state; + uint8_t write_state; + bool writable; + uint32_t localid; + uint32_t shell_remoteid; + uint32_t file_remoteid; +} adb_client; + +static struct usbd_endpoint adb_ep_data[2]; + +USB_NOCACHE_RAM_SECTION struct adb_packet tx_packet; +USB_NOCACHE_RAM_SECTION struct adb_packet rx_packet; + +static inline uint32_t adb_packet_checksum(struct adb_packet *packet) +{ + uint32_t sum = 0; + uint32_t i; + + for (i = 0; i < packet->msg.data_length; ++i) { + sum += (uint32_t)(packet->payload[i]); + } + + return sum; +} + +static uint32_t usbd_adb_get_remoteid(uint32_t localid) +{ + if (localid == ADB_SHELL_LOALID) { + return adb_client.shell_remoteid; + } else { + return adb_client.file_remoteid; + } +} + +static void adb_send_msg(struct adb_packet *packet) +{ + adb_client.common_state = ADB_STATE_WRITE_MSG; + + packet->msg.data_crc32 = adb_packet_checksum(packet); + packet->msg.magic = packet->msg.command ^ 0xffffffff; + + usbd_ep_start_write(0, adb_ep_data[ADB_IN_EP_IDX].ep_addr, (uint8_t *)&packet->msg, sizeof(struct adb_msg)); +} + +static void adb_send_okay(struct adb_packet *packet, uint32_t localid) +{ + packet->msg.command = A_OKAY; + packet->msg.arg0 = localid; + packet->msg.arg1 = usbd_adb_get_remoteid(localid); + packet->msg.data_length = 0; + + adb_send_msg(&tx_packet); +} + +static void adb_send_close(struct adb_packet *packet, uint32_t localid, uint32_t remoteid) +{ + packet->msg.command = A_CLSE; + packet->msg.arg0 = localid; + packet->msg.arg1 = remoteid; + packet->msg.data_length = 0; + + adb_send_msg(&tx_packet); +} + +void usbd_adb_bulk_out(uint8_t busid, uint8_t ep, uint32_t nbytes) +{ + (void)ep; + + if (adb_client.common_state == ADB_STATE_READ_MSG) { + USB_ASSERT(nbytes == sizeof(struct adb_msg)); + USB_ASSERT(rx_packet.msg.data_length <= sizeof(rx_packet.payload)); + + USB_LOG_DBG("command:%x arg0:%x arg1:%x len:%d\r\n", + rx_packet.msg.command, + rx_packet.msg.arg0, + rx_packet.msg.arg1, + rx_packet.msg.data_length); + + if (rx_packet.msg.data_length) { + /* setup next out ep read transfer */ + adb_client.common_state = ADB_STATE_READ_DATA; + usbd_ep_start_read(busid, adb_ep_data[ADB_OUT_EP_IDX].ep_addr, rx_packet.payload, rx_packet.msg.data_length); + } else { + if (rx_packet.msg.command == A_CLSE) { + adb_client.writable = false; + usbd_adb_notify_write_done(); + USB_LOG_INFO("Close remoteid:%x\r\n", rx_packet.msg.arg0); + } + adb_client.common_state = ADB_STATE_READ_MSG; + /* setup first out ep read transfer */ + usbd_ep_start_read(busid, adb_ep_data[ADB_OUT_EP_IDX].ep_addr, (uint8_t *)&rx_packet.msg, sizeof(struct adb_msg)); + } + } else if (adb_client.common_state == ADB_STATE_READ_DATA) { + switch (rx_packet.msg.command) { + case A_SYNC: + + break; + case A_CNXN: /* CONNECT(version, maxdata, "system-id-string") */ + char *support_feature = "device::" + "ro.product.name=cherryadb;" + "ro.product.model=cherrysh;" + "ro.product.device=cherryadb;" + "features=cmd,shell_v1"; + + tx_packet.msg.command = A_CNXN; + tx_packet.msg.arg0 = A_VERSION; + tx_packet.msg.arg1 = MAX_PAYLOAD; + tx_packet.msg.data_length = strlen(support_feature); + memcpy(tx_packet.payload, support_feature, strlen(support_feature)); + + adb_send_msg(&tx_packet); + + adb_client.writable = false; + break; + case A_OPEN: /* OPEN(local-id, 0, "destination") */ + rx_packet.payload[rx_packet.msg.data_length] = '\0'; + + if (strncmp((const char *)rx_packet.payload, "shell:", 6) == 0) { + adb_client.localid = ADB_SHELL_LOALID; + adb_client.shell_remoteid = rx_packet.msg.arg0; + adb_send_okay(&tx_packet, ADB_SHELL_LOALID); + + USB_LOG_INFO("Open shell service, remoteid:%x\r\n", rx_packet.msg.arg0); + } else if (strncmp((const char *)rx_packet.payload, "sync:", 5) == 0) { + adb_client.localid = ADB_FILE_LOALID; + adb_client.file_remoteid = rx_packet.msg.arg0; + adb_send_okay(&tx_packet, ADB_FILE_LOALID); + USB_LOG_INFO("Open file service, remoteid:%x\r\n", rx_packet.msg.arg0); + } + break; + case A_OKAY: + + break; + case A_CLSE: + + break; + case A_WRTE: /* WRITE(local-id, remote-id, "data") */ + if ((rx_packet.msg.arg0 == adb_client.shell_remoteid) && (rx_packet.msg.arg1 == ADB_SHELL_LOALID)) { + adb_send_okay(&tx_packet, rx_packet.msg.arg1); + } else if ((rx_packet.msg.arg0 == adb_client.file_remoteid) && (rx_packet.msg.arg1 == ADB_FILE_LOALID)) { + adb_send_okay(&tx_packet, rx_packet.msg.arg1); + } else { + adb_send_close(&tx_packet, 0, rx_packet.msg.arg0); + } + break; + case A_AUTH: + + break; + + default: + break; + } + } +} + +void usbd_adb_bulk_in(uint8_t busid, uint8_t ep, uint32_t nbytes) +{ + (void)ep; + (void)nbytes; + + if (adb_client.common_state == ADB_STATE_WRITE_MSG) { + if (tx_packet.msg.data_length) { + adb_client.common_state = ADB_STATE_WRITE_DATA; + usbd_ep_start_write(busid, adb_ep_data[ADB_IN_EP_IDX].ep_addr, tx_packet.payload, tx_packet.msg.data_length); + } else { + if (rx_packet.msg.command == A_WRTE) { + adb_client.writable = true; + if (adb_client.localid == ADB_SHELL_LOALID) { + usbd_adb_notify_shell_read(rx_packet.payload, rx_packet.msg.data_length); + } else { + } + } + adb_client.common_state = ADB_STATE_READ_MSG; + /* setup first out ep read transfer */ + usbd_ep_start_read(busid, adb_ep_data[ADB_OUT_EP_IDX].ep_addr, (uint8_t *)&rx_packet.msg, sizeof(struct adb_msg)); + } + } else if (adb_client.common_state == ADB_STATE_WRITE_DATA) { + adb_client.common_state = ADB_STATE_READ_MSG; + /* setup first out ep read transfer */ + usbd_ep_start_read(busid, adb_ep_data[ADB_OUT_EP_IDX].ep_addr, (uint8_t *)&rx_packet.msg, sizeof(struct adb_msg)); + } else if (adb_client.write_state == ADB_STATE_AWRITE_MSG) { + if (tx_packet.msg.data_length) { + adb_client.write_state = ADB_STATE_AWRITE_DATA; + usbd_ep_start_write(busid, adb_ep_data[ADB_IN_EP_IDX].ep_addr, tx_packet.payload, tx_packet.msg.data_length); + } else { + } + } else if (adb_client.write_state == ADB_STATE_AWRITE_DATA) { + usbd_adb_notify_write_done(); + } +} + +void adb_notify_handler(uint8_t busid, uint8_t event, void *arg) +{ + (void)arg; + + switch (event) { + case USBD_EVENT_INIT: + break; + case USBD_EVENT_DEINIT: + break; + case USBD_EVENT_RESET: + break; + case USBD_EVENT_CONFIGURED: + adb_client.common_state = ADB_STATE_READ_MSG; + /* setup first out ep read transfer */ + usbd_ep_start_read(busid, adb_ep_data[ADB_OUT_EP_IDX].ep_addr, (uint8_t *)&rx_packet.msg, sizeof(struct adb_msg)); + break; + + default: + break; + } +} + +struct usbd_interface *usbd_adb_init_intf(uint8_t busid, struct usbd_interface *intf, uint8_t in_ep, uint8_t out_ep) +{ + (void)busid; + + intf->class_interface_handler = NULL; + intf->class_endpoint_handler = NULL; + intf->vendor_handler = NULL; + intf->notify_handler = adb_notify_handler; + + adb_ep_data[ADB_OUT_EP_IDX].ep_addr = out_ep; + adb_ep_data[ADB_OUT_EP_IDX].ep_cb = usbd_adb_bulk_out; + adb_ep_data[ADB_IN_EP_IDX].ep_addr = in_ep; + adb_ep_data[ADB_IN_EP_IDX].ep_cb = usbd_adb_bulk_in; + + usbd_add_endpoint(busid, &adb_ep_data[ADB_OUT_EP_IDX]); + usbd_add_endpoint(busid, &adb_ep_data[ADB_IN_EP_IDX]); + + return intf; +} + +bool usbd_adb_can_write(void) +{ + return adb_client.writable; +} + +int usbd_abd_write(uint32_t localid, const uint8_t *data, uint32_t len) +{ + struct adb_packet *packet; + + packet = &tx_packet; + packet->msg.command = A_WRTE; + packet->msg.arg0 = localid; + packet->msg.arg1 = usbd_adb_get_remoteid(localid); + packet->msg.data_length = len; + memcpy(packet->payload, data, len); + + packet->msg.data_crc32 = adb_packet_checksum(packet); + packet->msg.magic = packet->msg.command ^ 0xffffffff; + + adb_client.write_state = ADB_STATE_AWRITE_MSG; + usbd_ep_start_write(0, adb_ep_data[ADB_IN_EP_IDX].ep_addr, (uint8_t *)&packet->msg, sizeof(struct adb_msg)); + return 0; +} + +void usbd_adb_close(uint32_t localid) +{ + adb_send_close(&tx_packet, 0, usbd_adb_get_remoteid(localid)); +} \ No newline at end of file diff --git a/kernel/cherryusb/class/adb/usbd_adb.h b/kernel/cherryusb/class/adb/usbd_adb.h new file mode 100644 index 0000000..4dbc730 --- /dev/null +++ b/kernel/cherryusb/class/adb/usbd_adb.h @@ -0,0 +1,38 @@ +/* + * Copyright (c) 2024, sakumisu + * + * SPDX-License-Identifier: Apache-2.0 + */ +#ifndef USBD_ADB_H +#define USBD_ADB_H + +#include + +#define ADB_SHELL_LOALID 0x01 +#define ADB_FILE_LOALID 0x02 + +// clang-format off +#define ADB_DESCRIPTOR_INIT(bFirstInterface, in_ep, out_ep, wMaxPacketSize) \ + USB_INTERFACE_DESCRIPTOR_INIT(bFirstInterface, 0x00, 0x02, 0xff, 0x42, 0x01, 0x02), \ + USB_ENDPOINT_DESCRIPTOR_INIT(in_ep, 0x02, wMaxPacketSize, 0x00), \ + USB_ENDPOINT_DESCRIPTOR_INIT(out_ep, 0x02, wMaxPacketSize, 0x00) +// clang-format on + +#ifdef __cplusplus +extern "C" { +#endif + +struct usbd_interface *usbd_adb_init_intf(uint8_t busid, struct usbd_interface *intf, uint8_t in_ep, uint8_t out_ep); + +void usbd_adb_notify_shell_read(uint8_t *data, uint32_t len); +void usbd_adb_notify_file_read(uint8_t *data, uint32_t len); +void usbd_adb_notify_write_done(void); +bool usbd_adb_can_write(void); +int usbd_abd_write(uint32_t localid, const uint8_t *data, uint32_t len); +void usbd_adb_close(uint32_t localid); + +#ifdef __cplusplus +} +#endif + +#endif /* USBD_ADB_H */ \ No newline at end of file diff --git a/kernel/cherryusb/class/aoa/usb_aoa.h b/kernel/cherryusb/class/aoa/usb_aoa.h new file mode 100644 index 0000000..6b6c715 --- /dev/null +++ b/kernel/cherryusb/class/aoa/usb_aoa.h @@ -0,0 +1,48 @@ +/* + * Copyright (c) 2024, sakumisu + * + * SPDX-License-Identifier: Apache-2.0 + */ +#ifndef USB_AOA_H +#define USB_AOA_H + +//AOA 1.0 +#define AOA_ACCESSORY_VENDOR_ID 0x18D1 +#define AOA_ACCESSORY_PRODUCT_ID 0x2D00 +#define AOA_ACCESSORY_ADB_PRODUCT_ID 0x2D01 + +//AOA 2.0 +#define AOA_AUDIO_PRODUCT_ID 0x2D02 +#define AOA_AUDIO_ADB_PRODUCT_ID 0x2D03 +#define AOA_ACCESSORY_AUDIO_PRODUCT_ID 0x2D04 +#define AOA_ACCESSORY_AUDIO_ADB_PRODUCT_ID 0x2D05 + +//AOA 1.0 +#define AOA_ACCESSORY_GET_PROTOCOL 51 +#define AOA_ACCESSORY_SEND_STRING 52 +#define AOA_ACCESSORY_START 53 + +//AOA 2.0 +#define AOA_ACCESSORY_REGISTER_HID 54 +#define AOA_ACCESSORY_UNREGISTER_HID 55 +#define AOA_ACCESSORY_SET_HID_REPORT_DESC 56 +#define AOA_ACCESSORY_SEND_HID_EVENT 57 +#define AOA_ACCESSORY_SET_AUDIO_MODE 58 + +#define AOA_ACCESSORY_STRING_MANUFACTURER 0 +#define AOA_ACCESSORY_STRING_MODEL 1 +#define AOA_ACCESSORY_STRING_DESCRIPTION 2 +#define AOA_ACCESSORY_STRING_VERSION 3 +#define AOA_ACCESSORY_STRING_URI 4 +#define AOA_ACCESSORY_STRING_SERIAL 5 + +struct aoa_string_info { + char acc_manufacturer[64]; + char acc_model[64]; + char acc_description[64]; + char acc_version[64]; + char acc_uri[64]; + char acc_serial[64]; +}; + +#endif /* USB_AOA_H */ \ No newline at end of file diff --git a/kernel/cherryusb/class/aoa/usbh_aoa.c b/kernel/cherryusb/class/aoa/usbh_aoa.c new file mode 100644 index 0000000..02d9fab --- /dev/null +++ b/kernel/cherryusb/class/aoa/usbh_aoa.c @@ -0,0 +1,285 @@ +/* + * Copyright (c) 2024, sakumisu + * + * SPDX-License-Identifier: Apache-2.0 + */ +#include "usbh_core.h" +#include "usbh_aoa.h" + +#undef USB_DBG_TAG +#define USB_DBG_TAG "usbh_aoa" +#include "usb_log.h" + +#define DEV_FORMAT "/dev/aoa" + +USB_NOCACHE_RAM_SECTION USB_MEM_ALIGNX uint8_t g_aoa_buffer[USB_ALIGN_UP(128, CONFIG_USB_ALIGN_SIZE)]; + +static struct usbh_aoa g_aoa_class; + +int usbh_aoa_switch(struct usbh_hubport *hport, struct aoa_string_info *info) +{ + struct usb_setup_packet *setup; + int ret; + + setup = hport->setup; + + if (setup == NULL) { + return -USB_ERR_INVAL; + } + + USB_LOG_INFO("Try switch into aoa mode\r\n"); + + setup->bmRequestType = USB_REQUEST_DIR_IN | USB_REQUEST_VENDOR | USB_REQUEST_RECIPIENT_DEVICE; + setup->bRequest = AOA_ACCESSORY_GET_PROTOCOL; + setup->wValue = 0; + setup->wIndex = 0; + setup->wLength = 2; + + ret = usbh_control_transfer(hport, setup, g_aoa_buffer); + if (ret < 0) { + return ret; + } + + USB_LOG_INFO("AOA version: v%d.%d\r\n", g_aoa_buffer[0], g_aoa_buffer[1]); + + setup->bmRequestType = USB_REQUEST_DIR_OUT | USB_REQUEST_VENDOR | USB_REQUEST_RECIPIENT_DEVICE; + setup->bRequest = AOA_ACCESSORY_SEND_STRING; + setup->wValue = 0; + setup->wIndex = AOA_ACCESSORY_STRING_MANUFACTURER; + setup->wLength = strlen(info->acc_manufacturer) + 1; + + memcpy(g_aoa_buffer, info->acc_manufacturer, strlen(info->acc_manufacturer)); + ret = usbh_control_transfer(hport, setup, g_aoa_buffer); + if (ret < 0) { + return ret; + } + + setup->bmRequestType = USB_REQUEST_DIR_OUT | USB_REQUEST_VENDOR | USB_REQUEST_RECIPIENT_DEVICE; + setup->bRequest = AOA_ACCESSORY_SEND_STRING; + setup->wValue = 0; + setup->wIndex = AOA_ACCESSORY_STRING_MODEL; + setup->wLength = strlen(info->acc_model) + 1; + + memcpy(g_aoa_buffer, info->acc_model, strlen(info->acc_model)); + ret = usbh_control_transfer(hport, setup, g_aoa_buffer); + if (ret < 0) { + return ret; + } + + setup->bmRequestType = USB_REQUEST_DIR_OUT | USB_REQUEST_VENDOR | USB_REQUEST_RECIPIENT_DEVICE; + setup->bRequest = AOA_ACCESSORY_SEND_STRING; + setup->wValue = 0; + setup->wIndex = AOA_ACCESSORY_STRING_DESCRIPTION; + setup->wLength = strlen(info->acc_description) + 1; + + memcpy(g_aoa_buffer, info->acc_description, strlen(info->acc_description)); + ret = usbh_control_transfer(hport, setup, g_aoa_buffer); + if (ret < 0) { + return ret; + } + + setup->bmRequestType = USB_REQUEST_DIR_OUT | USB_REQUEST_VENDOR | USB_REQUEST_RECIPIENT_DEVICE; + setup->bRequest = AOA_ACCESSORY_SEND_STRING; + setup->wValue = 0; + setup->wIndex = AOA_ACCESSORY_STRING_VERSION; + setup->wLength = strlen(info->acc_version) + 1; + + memcpy(g_aoa_buffer, info->acc_version, strlen(info->acc_version)); + ret = usbh_control_transfer(hport, setup, g_aoa_buffer); + if (ret < 0) { + return ret; + } + + setup->bmRequestType = USB_REQUEST_DIR_OUT | USB_REQUEST_VENDOR | USB_REQUEST_RECIPIENT_DEVICE; + setup->bRequest = AOA_ACCESSORY_SEND_STRING; + setup->wValue = 0; + setup->wIndex = AOA_ACCESSORY_STRING_URI; + setup->wLength = strlen(info->acc_uri) + 1; + + memcpy(g_aoa_buffer, info->acc_uri, strlen(info->acc_uri)); + ret = usbh_control_transfer(hport, setup, g_aoa_buffer); + if (ret < 0) { + return ret; + } + + setup->bmRequestType = USB_REQUEST_DIR_OUT | USB_REQUEST_VENDOR | USB_REQUEST_RECIPIENT_DEVICE; + setup->bRequest = AOA_ACCESSORY_SEND_STRING; + setup->wValue = 0; + setup->wIndex = AOA_ACCESSORY_STRING_SERIAL; + setup->wLength = strlen(info->acc_serial) + 1; + + memcpy(g_aoa_buffer, info->acc_serial, strlen(info->acc_serial)); + ret = usbh_control_transfer(hport, setup, g_aoa_buffer); + if (ret < 0) { + return ret; + } + + setup->bmRequestType = USB_REQUEST_DIR_OUT | USB_REQUEST_VENDOR | USB_REQUEST_RECIPIENT_DEVICE; + setup->bRequest = AOA_ACCESSORY_START; + setup->wValue = 0; + setup->wIndex = 0; + setup->wLength = 0; + + ret = usbh_control_transfer(hport, setup, NULL); + if (ret < 0) { + return ret; + } + + USB_LOG_INFO("Switch into aoa mode success, wait usb device restart...\r\n"); + return 0; +} + +int usbh_aoa_register_hid(struct usbh_aoa *aoa_class, uint16_t id, uint8_t *report, uint32_t report_len) +{ + struct usb_setup_packet *setup; + int ret; + uint8_t len; + uint32_t offset; + + if (!aoa_class || !aoa_class->hport) { + return -USB_ERR_INVAL; + } + setup = aoa_class->hport->setup; + + setup->bmRequestType = USB_REQUEST_DIR_OUT | USB_REQUEST_VENDOR | USB_REQUEST_RECIPIENT_DEVICE; + setup->bRequest = AOA_ACCESSORY_REGISTER_HID; + setup->wValue = id; + setup->wIndex = report_len; + setup->wLength = 0; + + ret = usbh_control_transfer(aoa_class->hport, setup, NULL); + if (ret < 0) { + return ret; + } + + offset = 0; + while (report_len > 0) { + len = report_len > 64 ? 64 : report_len; + + setup->bmRequestType = USB_REQUEST_DIR_OUT | USB_REQUEST_VENDOR | USB_REQUEST_RECIPIENT_DEVICE; + setup->bRequest = AOA_ACCESSORY_SET_HID_REPORT_DESC; + setup->wValue = id; + setup->wIndex = offset; + setup->wLength = len; + + memcpy(g_aoa_buffer, report + offset, len); + ret = usbh_control_transfer(aoa_class->hport, setup, g_aoa_buffer); + if (ret < 0) { + return ret; + } + offset += len; + report_len -= len; + } + return ret; +} + +int usbh_aoa_send_hid_event(struct usbh_aoa *aoa_class, uint16_t id, uint8_t *event, uint32_t event_len) +{ + struct usb_setup_packet *setup; + + if (!aoa_class || !aoa_class->hport) { + return -USB_ERR_INVAL; + } + setup = aoa_class->hport->setup; + + setup->bmRequestType = USB_REQUEST_DIR_OUT | USB_REQUEST_VENDOR | USB_REQUEST_RECIPIENT_DEVICE; + setup->bRequest = AOA_ACCESSORY_SEND_HID_EVENT; + setup->wValue = id; + setup->wIndex = 0; + setup->wLength = event_len; + + memcpy(g_aoa_buffer, event, event_len); + return usbh_control_transfer(aoa_class->hport, setup, event); +} + +static int usbh_aoa_connect(struct usbh_hubport *hport, uint8_t intf) +{ + struct usb_endpoint_descriptor *ep_desc; + + struct usbh_aoa *aoa_class = &g_aoa_class; + + memset(aoa_class, 0, sizeof(struct usbh_aoa)); + + aoa_class->hport = hport; + aoa_class->intf = intf; + + hport->config.intf[intf].priv = aoa_class; + + for (uint8_t i = 0; i < hport->config.intf[intf].altsetting[0].intf_desc.bNumEndpoints; i++) { + ep_desc = &hport->config.intf[intf].altsetting[0].ep[i].ep_desc; + + if (ep_desc->bEndpointAddress & 0x80) { + USBH_EP_INIT(aoa_class->bulkin, ep_desc); + } else { + USBH_EP_INIT(aoa_class->bulkout, ep_desc); + } + } + + strncpy(hport->config.intf[intf].devname, DEV_FORMAT, CONFIG_USBHOST_DEV_NAMELEN); + + USB_LOG_INFO("Register AOA Class:%s\r\n", hport->config.intf[intf].devname); + + usbh_aoa_run(aoa_class); + return 0; +} + +static int usbh_aoa_disconnect(struct usbh_hubport *hport, uint8_t intf) +{ + int ret = 0; + + struct usbh_aoa *aoa_class = (struct usbh_aoa *)hport->config.intf[intf].priv; + + if (aoa_class) { + if (aoa_class->bulkin) { + usbh_kill_urb(&aoa_class->bulkin_urb); + } + + if (aoa_class->bulkout) { + usbh_kill_urb(&aoa_class->bulkout_urb); + } + + if (hport->config.intf[intf].devname[0] != '\0') { + USB_LOG_INFO("Unregister AOA Class:%s\r\n", hport->config.intf[intf].devname); + usbh_aoa_stop(aoa_class); + } + + memset(aoa_class, 0, sizeof(struct usbh_aoa)); + } + + return ret; +} + +__WEAK void usbh_aoa_run(struct usbh_aoa *aoa_class) +{ + (void)aoa_class; +} + +__WEAK void usbh_aoa_stop(struct usbh_aoa *aoa_class) +{ + (void)aoa_class; +} + +static const uint16_t aoa_id_table[][2] = { + { AOA_ACCESSORY_VENDOR_ID, AOA_ACCESSORY_PRODUCT_ID }, + { AOA_ACCESSORY_VENDOR_ID, AOA_ACCESSORY_ADB_PRODUCT_ID }, + { AOA_ACCESSORY_VENDOR_ID, AOA_AUDIO_PRODUCT_ID }, + { AOA_ACCESSORY_VENDOR_ID, AOA_AUDIO_ADB_PRODUCT_ID }, + { AOA_ACCESSORY_VENDOR_ID, AOA_ACCESSORY_AUDIO_PRODUCT_ID }, + { AOA_ACCESSORY_VENDOR_ID, AOA_ACCESSORY_AUDIO_ADB_PRODUCT_ID }, + { 0, 0 }, +}; + +const struct usbh_class_driver aoa_class_driver = { + .driver_name = "aoa", + .connect = usbh_aoa_connect, + .disconnect = usbh_aoa_disconnect +}; + +CLASS_INFO_DEFINE const struct usbh_class_info aoa_intf_class_info = { + .match_flags = USB_CLASS_MATCH_VID_PID | USB_CLASS_MATCH_INTF_CLASS | USB_CLASS_MATCH_INTF_SUBCLASS, + .bInterfaceClass = 0xff, + .bInterfaceSubClass = 0xff, + .bInterfaceProtocol = 0x00, + .id_table = aoa_id_table, + .class_driver = &aoa_class_driver +}; \ No newline at end of file diff --git a/kernel/cherryusb/class/aoa/usbh_aoa.h b/kernel/cherryusb/class/aoa/usbh_aoa.h new file mode 100644 index 0000000..3b184e8 --- /dev/null +++ b/kernel/cherryusb/class/aoa/usbh_aoa.h @@ -0,0 +1,40 @@ +/* + * Copyright (c) 2024, sakumisu + * + * SPDX-License-Identifier: Apache-2.0 + */ +#ifndef USBH_AOA_H +#define USBH_AOA_H + +#include "usb_aoa.h" + +struct usbh_aoa { + struct usbh_hubport *hport; + struct usb_endpoint_descriptor *bulkin; /* Bulk IN endpoint */ + struct usb_endpoint_descriptor *bulkout; /* Bulk OUT endpoint */ + + struct usbh_urb bulkout_urb; + struct usbh_urb bulkin_urb; + + uint8_t intf; + uint8_t minor; + + void *user_data; +}; + +#ifdef __cplusplus +extern "C" { +#endif + +int usbh_aoa_switch(struct usbh_hubport *hport, struct aoa_string_info *info); +int usbh_aoa_register_hid(struct usbh_aoa *aoa_class, uint16_t id, uint8_t *report, uint32_t report_len); +int usbh_aoa_send_hid_event(struct usbh_aoa *aoa_class, uint16_t id, uint8_t *event, uint32_t event_len); + +void usbh_aoa_run(struct usbh_aoa *aoa_class); +void usbh_aoa_stop(struct usbh_aoa *aoa_class); + +#ifdef __cplusplus +} +#endif + +#endif /* USBH_AOA_H */ \ No newline at end of file diff --git a/kernel/cherryusb/class/audio/usb_audio.h b/kernel/cherryusb/class/audio/usb_audio.h new file mode 100644 index 0000000..6833404 --- /dev/null +++ b/kernel/cherryusb/class/audio/usb_audio.h @@ -0,0 +1,1346 @@ +/* + * Copyright (c) 2022, sakumisu + * + * SPDX-License-Identifier: Apache-2.0 + */ +#ifndef USB_AUDIO_H +#define USB_AUDIO_H + +/** Audio Interface Subclass Codes + * Refer to Table A-2 from audio10.pdf + */ +#define AUDIO_SUBCLASS_UNDEFINED 0x00 +#define AUDIO_SUBCLASS_AUDIOCONTROL 0x01 +#define AUDIO_SUBCLASS_AUDIOSTREAMING 0x02 +#define AUDIO_SUBCLASS_MIDISTREAMING 0x03 + +#define AUDIO_PROTOCOL_UNDEFINED 0x00 +#define AUDIO_PROTOCOLv20 0x20 /* IP version 2.0 */ + +/** Audio Class-Specific Request Codes + * Refer to Table A-9 from audio10.pdf + */ +#define AUDIO_REQUEST_UNDEFINED 0x00 +#define AUDIO_REQUEST_SET_CUR 0x01 +#define AUDIO_REQUEST_GET_CUR 0x81 +#define AUDIO_REQUEST_SET_MIN 0x02 +#define AUDIO_REQUEST_GET_MIN 0x82 +#define AUDIO_REQUEST_SET_MAX 0x03 +#define AUDIO_REQUEST_GET_MAX 0x83 +#define AUDIO_REQUEST_SET_RES 0x04 +#define AUDIO_REQUEST_GET_RES 0x84 +#define AUDIO_REQUEST_SET_MEM 0x05 +#define AUDIO_REQUEST_GET_MEM 0x85 +#define AUDIO_REQUEST_GET_STAT 0xFF + +/** Audio Class-Specific Request Codes + * Refer from audio20_final.pdf + */ +#define AUDIO_REQUEST_CUR 0x01 +#define AUDIO_REQUEST_RANGE 0x02 +/** Audio Class-Specific Control Interface Descriptor Subtypes + * Refer to Table A-5 from audio10.pdf + */ +#define AUDIO_CONTROL_UNDEF 0x01U +#define AUDIO_CONTROL_HEADER 0x01U +#define AUDIO_CONTROL_INPUT_TERMINAL 0x02U +#define AUDIO_CONTROL_OUTPUT_TERMINAL 0x03U +#define AUDIO_CONTROL_MIXER_UNIT 0x04U +#define AUDIO_CONTROL_SELECTOR_UNIT 0x05U +#define AUDIO_CONTROL_FEATURE_UNIT 0x06U +#define AUDIO_CONTROL_EFFECT_UNIT 0x07U +#define AUDIO_CONTROL_PROCESSING_UNIT 0x08U +#define AUDIO_CONTROL_EXTENSION_UNIT 0x09U +#define AUDIO_CONTROL_CLOCK_SOURCE 0x0aU +#define AUDIO_CONTROL_CLOCK_SELECTOR 0x0bU +#define AUDIO_CONTROL_CLOCK_MULTIPLIER 0x0cU +#define AUDIO_CONTROL_SAMPLERATE_CONVERTER 0x0dU + +/** Audio Class-Specific AS Interface Descriptor Subtypes + * Refer to Table A-6 from audio10.pdf + */ +#define AUDIO_STREAMING_UNDEFINED 0x00U +#define AUDIO_STREAMING_GENERAL 0x01U +#define AUDIO_STREAMING_FORMAT_TYPE 0x02U +#define AUDIO_STREAMING_ENCODER 0x03U +#define AUDIO_STREAMING_DECODER 0x04U + +/* Clock Source Descriptor Clock Types */ +#define AUDIO_CLKSRC_EXTERNAL 0x00 /* External clock */ +#define AUDIO_CLKSRC_INTERNAL_FIXED 0x01 /* Internal fixed clock */ +#define AUDIO_CLKSRC_INTERNAL_VAR 0x02 /* Internal variable clock */ +#define AUDIO_CLKSRC_INTERNAL_PROG 0x03 /* Internal programmable clock */ + +/* Effect Unit Effect Types */ +#define AUDIO_EFFECT_UNDEF 0x00 +#define AUDIO_EFFECT_PARAM_EQ_SECTION 0x01 +#define AUDIO_EFFECT_REVERBERATION 0x02 +#define AUDIO_EFFECT_MOD_DELAY 0x03 +#define AUDIO_EFFECT_DYN_RANGE_COMP 0x04 + +/* Processing Unit Process Types */ +#define AUDIO_PROCESS_UNDEFINED 0x00 +#define AUDIO_PROCESS_UPDOWNMIX 0x01 +#define AUDIO_PROCESS_DOLBY_PROLOGIC 0x02 +#define AUDIO_PROCESS_STEREO_EXTENDER 0x03 + +/* Audio Class-Specific Endpoint Descriptor Subtypes */ +#define AUDIO_ENDPOINT_UNDEFINED 0x00U +#define AUDIO_ENDPOINT_GENERAL 0x01U + +/* Encoder Type Codes */ +#define AUDIO_ENCODER_UNDEF 0x00 +#define AUDIO_ENCODER_OTHER 0x01 +#define AUDIO_ENCODER_MPEG 0x02 +#define AUDIO_ENCODER_AC3 0x03 +#define AUDIO_ENCODER_WMA 0x04 +#define AUDIO_ENCODER_DTS 0x05 + +/* Decoder Type Codes */ +#define AUDIO_DECODER_UNDEF 0x00 +#define AUDIO_DECODER_OTHER 0x01 +#define AUDIO_DECODER_MPEG 0x02 +#define AUDIO_DECODER_AC3 0x03 +#define AUDIO_DECODER_WMA 0x04 +#define AUDIO_DECODER_DTS 0x05 + +/* Audio Descriptor Types */ +#define AUDIO_UNDEFINED_DESCRIPTOR_TYPE 0x20 +#define AUDIO_DEVICE_DESCRIPTOR_TYPE 0x21 +#define AUDIO_CONFIGURATION_DESCRIPTOR_TYPE 0x22 +#define AUDIO_STRING_DESCRIPTOR_TYPE 0x23 +#define AUDIO_INTERFACE_DESCRIPTOR_TYPE 0x24 +#define AUDIO_ENDPOINT_DESCRIPTOR_TYPE 0x25 + +/* Audio Data Format Type I Codes */ +#define AUDIO_FORMAT_TYPE_I_UNDEFINED 0x0000 +#define AUDIO_FORMAT_PCM 0x0001 +#define AUDIO_FORMAT_PCM8 0x0002 +#define AUDIO_FORMAT_IEEE_FLOAT 0x0003 +#define AUDIO_FORMAT_ALAW 0x0004 +#define AUDIO_FORMAT_MULAW 0x0005 + +#define AUDIO_V2_FORMAT_PCM 0x00000001 +#define AUDIO_V2_FORMAT_PCM8 0x00000002 +#define AUDIO_V2_FORMAT_IEEE_FLOAT 0x00000004 +#define AUDIO_V2_FORMAT_ALAW 0x00000008 +#define AUDIO_V2_FORMAT_MULAW 0x00000010 + +/* bmChannelConfig: a bitmap field that indicates which spatial locations + * are occupied by the channels present in the cluster. The bit allocations + * are as follows: + */ +#define AUDIO_CHANNEL_M 0 /* Mono */ +#define AUDIO_CHANNEL_FL (1 << 0) /* Front Left */ +#define AUDIO_CHANNEL_FR (1 << 1) /* Front Right */ +#define AUDIO_CHANNEL_FC (1 << 2) /* Front Center */ +#define AUDIO_CHANNEL_LFE (1 << 3) /* Low Frequency Effects */ +#define AUDIO_CHANNEL_BL (1 << 4) /* Back Left */ +#define AUDIO_CHANNEL_BR (1 << 5) /* Back Right */ +#define AUDIO_CHANNEL_FLC (1 << 6) /* Front Left of Center */ +#define AUDIO_CHANNEL_FRC (1 << 7) /* Front Right of Center */ +#define AUDIO_CHANNEL_BC (1 << 8) /* Back Center */ +#define AUDIO_CHANNEL_SL (1 << 9) /* Side Left */ +#define AUDIO_CHANNEL_SR (1 << 10) /* Side Right */ +#define AUDIO_CHANNEL_TC (1 << 11) /* Top Center */ +#define AUDIO_CHANNEL_TFL (1 << 12) /* Top Front Left */ +#define AUDIO_CHANNEL_TFC (1 << 13) /* Top Front Center */ +#define AUDIO_CHANNEL_TFR (1 << 14) /* Top Front Right */ +#define AUDIO_CHANNEL_TBL (1 << 15) /* Top Back Left */ +#define AUDIO_CHANNEL_TBC (1 << 16) /* Top Back Center */ +#define AUDIO_CHANNEL_TBR (1 << 17) /* Top Back Right */ +#define AUDIO_CHANNEL_TFLC (1 << 18) /* Top Front Left of Center */ +#define AUDIO_CHANNEL_TFRC (1 << 19) /* Top Front Right of Center */ +#define AUDIO_CHANNEL_LLFE (1 << 20) /* Left Low Frequency Effects */ +#define AUDIO_CHANNEL_RLFE (1 << 21) /* Right Low Frequency Effects */ +#define AUDIO_CHANNEL_TSL (1 << 22) /* Top Side Left */ +#define AUDIO_CHANNEL_TSR (1 << 23) /* Top Side Right */ +#define AUDIO_CHANNEL_BOC (1 << 24) /* Bottom Center */ +#define AUDIO_CHANNEL_BLC (1 << 25) /* Back Left of Center */ +#define AUDIO_CHANNEL_BRC (1 << 26) /* Back Right of Center */ + /* Bits 27-30: Reserved */ +#define AUDIO_CHANNEL_RD (1 << 31) /* Raw Data */ + +/* Audio Function Category Codes */ +#define AUDIO_CATEGORY_UNDEF 0x00 /* Undefined */ +#define AUDIO_CATEGORY_SPEAKER 0x01 /* Desktop speaker */ +#define AUDIO_CATEGORY_THEATER 0x02 /* Home theater */ +#define AUDIO_CATEGORY_MICROPHONE 0x03 /* Microphone */ +#define AUDIO_CATEGORY_HEADSET 0x04 /* Headset */ +#define AUDIO_CATEGORY_TELEPHONE 0x05 /* Telephone */ +#define AUDIO_CATEGORY_CONVERTER 0x06 /* Converter */ +#define AUDIO_CATEGORY_RECORDER 0x07 /* Voice/Sound recorder */ +#define AUDIO_CATEGORY_IO_BOX 0x08 /* I/O box */ +#define AUDIO_CATEGORY_INSTRUMENT 0x09 /* Musical instrument */ +#define AUDIO_CATEGORY_PROAUDIO 0x0a /* Pro-audio */ +#define AUDIO_CATEGORY_AV 0x0b /* Audio/video */ +#define AUDIO_CATEGORY_CONTROL 0x0c /* Control panel */ +#define AUDIO_CATEGORY_OTHER 0xff + +/* Clock Source Control Selectors */ +#define AUDIO_CS_CONTROL_UNDEF 0x00 +#define AUDIO_CS_CONTROL_SAM_FREQ 0x01 +#define AUDIO_CS_CONTROL_CLOCK_VALID 0x02 + +/* Clock Selector Control Selectors */ +#define AUDIO_CX_CONTROL_UNDEF 0x00 +#define AUDIO_CX_CONTROL_CLOCKSEL 0x01 + +/* Clock Multiplier Control Selectors */ +#define AUDIO_CM_CONTROL_UNDEF 0x00 +#define AUDIO_CM_CONTROL_NUMERATOR 0x01 +#define AUDIO_CM_CONTROL_DENOMINATOR 0x02 + +/* Terminal Control Selectors */ +#define AUDIO_TE_CONTROL_UNDEF 0x00 +#define AUDIO_TE_CONTROL_COPY_PROTECT 0x01 +#define AUDIO_TE_CONTROL_CONNECTOR 0x02 +#define AUDIO_TE_CONTROL_OVERLOAD 0x03 +#define AUDIO_TE_CONTROL_CLUSTER 0x04 +#define AUDIO_TE_CONTROL_UNDERFLOW 0x05 +#define AUDIO_TE_CONTROL_OVERFLOW 0x06 +#define AUDIO_TE_CONTROL_LATENCY 0x07 + +/* Mixer Control Selectors */ +#define AUDIO_MU_CONTROL_UNDEF 0x00 +#define AUDIO_MU_CONTROL_MIXER 0x01 +#define AUDIO_MU_CONTROL_CLUSTER 0x02 +#define AUDIO_MU_CONTROL_UNDERFLOW 0x03 +#define AUDIO_MU_CONTROL_OVERFLOW 0x04 +#define AUDIO_MU_CONTROL_LATENCY 0x05 + +/* Selector Control Selectors */ +#define AUDIO_SU_CONTROL_UNDEFINE 0x00 +#define AUDIO_SU_CONTROL_SELECTOR 0x01 +#define AUDIO_SU_CONTROL_LATENCY 0x02 + +/* Feature Unit Control Selectors */ +#define AUDIO_FU_CONTROL_UNDEF 0x00 +#define AUDIO_FU_CONTROL_MUTE 0x01 +#define AUDIO_FU_CONTROL_VOLUME 0x02 +#define AUDIO_FU_CONTROL_BASS 0x03 +#define AUDIO_FU_CONTROL_MID 0x04 +#define AUDIO_FU_CONTROL_TREBLE 0x05 +#define AUDIO_FU_CONTROL_EQUALIZER 0x06 +#define AUDIO_FU_CONTROL_AGC 0x07 +#define AUDIO_FU_CONTROL_DELAY 0x08 +#define AUDIO_FU_CONTROL_BASS_BOOST 0x09 +#define AUDIO_FU_CONTROL_LOUDNESS 0x0a +#define AUDIO_FU_CONTROL_INP_GAIN 0x0b +#define AUDIO_FU_CONTROL_INP_GAIN_PAD 0x0c +#define AUDIO_FU_CONTROL_PHASE_INVERT 0x0d +#define AUDIO_FU_CONTROL_UNDERFLOW 0x0e +#define AUDIO_FU_CONTROL_OVERFLOW 0x0f +#define AUDIO_FU_CONTROL_LATENCY 0x10 + +/* Feature Unit Control Bits */ +#define AUDIO_CONTROL_MUTE 0x0001 +#define AUDIO_CONTROL_VOLUME 0x0002 +#define AUDIO_CONTROL_BASS 0x0004 +#define AUDIO_CONTROL_MID 0x0008 +#define AUDIO_CONTROL_TREBLE 0x0010 +#define AUDIO_CONTROL_GRAPHIC_EQUALIZER 0x0020 +#define AUDIO_CONTROL_AUTOMATIC_GAIN 0x0040 +#define AUDIO_CONTROL_DEALY 0x0080 +#define AUDIO_CONTROL_BASS_BOOST 0x0100 +#define AUDIO_CONTROL_LOUDNESS 0x0200 + +#define AUDIO_V2_CONTROL_UNDEF 0x00 +#define AUDIO_V2_CONTROL_MUTE (0x03 << 0) +#define AUDIO_V2_CONTROL_VOLUME (0x03 << 2) +#define AUDIO_V2_CONTROL_BASS (0x03 << 4) +#define AUDIO_V2_CONTROL_MID (0x03 << 6) +#define AUDIO_V2_CONTROL_TREBLE (0x03 << 8) +#define AUDIO_V2_CONTROL_EQUALIZER (0x03 << 10) +#define AUDIO_V2_CONTROL_AGC (0x03 << 12) +#define AUDIO_V2_CONTROL_DELAY (0x03 << 14) +#define AUDIO_V2_CONTROL_BASS_BOOST (0x03 << 16) +#define AUDIO_V2_CONTROL_LOUDNESS (0x03 << 18) +#define AUDIO_V2_CONTROL_INP_GAIN (0x03 << 20) +#define AUDIO_V2_CONTROL_INP_GAIN_PAD (0x03 << 22) +#define AUDIO_V2_CONTROL_PHASE_INVERT (0x03 << 24) +#define AUDIO_V2_CONTROL_UNDERFLOW (0x03 << 26) +#define AUDIO_V2_CONTROL_OVERFLOW (0x03 << 28) + +/* Parametric Equalizer Section Effect Unit Control Selectors */ +#define AUDIO_PE_CONTROL_UNDEF 0x00 +#define AUDIO_PE_CONTROL_ENABLE 0x01 +#define AUDIO_PE_CONTROL_CENTERFREQ 0x02 +#define AUDIO_PE_CONTROL_QFACTOR 0x03 +#define AUDIO_PE_CONTROL_GAIN 0x04 +#define AUDIO_PE_CONTROL_UNDERFLOW 0x05 +#define AUDIO_PE_CONTROL_OVERFLOW 0x06 +#define AUDIO_PE_CONTROL_LATENCY 0x07 + +/* Reverberation Effect Unit Control Selectors */ +#define AUDIO_RV_CONTROL_UNDEF 0x00 +#define AUDIO_RV_CONTROL_ENABLE 0x01 +#define AUDIO_RV_CONTROL_TYPE 0x02 +#define AUDIO_RV_CONTROL_LEVEL 0x03 +#define AUDIO_RV_CONTROL_TIME 0x04 +#define AUDIO_RV_CONTROL_FEEDBACK 0x05 +#define AUDIO_RV_CONTROL_PREDELAY 0x06 +#define AUDIO_RV_CONTROL_DENSITY 0x07 +#define AUDIO_RV_CONTROL_HF_ROLLOFF 0x08 +#define AUDIO_RV_CONTROL_UNDERFLOW 0x09 +#define AUDIO_RV_CONTROL_OVERFLOW 0x0a +#define AUDIO_RV_CONTROL_LATENCY 0x0b + +/* Modulation Delay Effect Unit Control Selectors */ +#define AUDIO_MD_CONTROL_UNDEF 0x00 +#define AUDIO_MD_CONTROL_ENABLE 0x01 +#define AUDIO_MD_CONTROL_BALANCE 0x02 +#define AUDIO_MD_CONTROL_RATE 0x03 +#define AUDIO_MD_CONTROL_DEPTH 0x04 +#define AUDIO_MD_CONTROL_TIME 0x05 +#define AUDIO_MD_CONTROL_FEEDBACK 0x06 +#define AUDIO_MD_CONTROL_UNDERFLOW 0x07 +#define AUDIO_MD_CONTROL_OVERFLOW 0x08 +#define AUDIO_MD_CONTROL_LATENCY 0x09 + +/* Dynamic Range Compressor Effect Unit Control Selectors */ +#define AUDIO_DR_CONTROL_UNDEF 0x00 +#define AUDIO_DR_CONTROL_ENABLE 0x01 +#define AUDIO_DR_CONTROL_COMP_RATE 0x02 +#define AUDIO_DR_CONTROL_MAXAMPL 0x03 +#define AUDIO_DR_CONTROL_THRESHOLD 0x04 +#define AUDIO_DR_CONTROL_ATTACK_TIME 0x05 +#define AUDIO_DR_CONTROL_RELEASE_TIME 0x06 +#define AUDIO_DR_CONTROL_UNDERFLOW 0x07 +#define AUDIO_DR_CONTROL_OVERFLOW 0x08 +#define AUDIO_DR_CONTROL_LATENCY 0x09 + +/* Up/Down-mix Processing Unit Control Selectors */ +#define AUDIO_UD_CONTROL_UNDEF 0x00 +#define AUDIO_UD_CONTROL_ENABLE 0x01 +#define AUDIO_UD_CONTROL_MODE_SELECT 0x02 +#define AUDIO_UD_CONTROL_CLUSTER 0x03 +#define AUDIO_UD_CONTROL_UNDERFLOW 0x04 +#define AUDIO_UD_CONTROL_OVERFLOW 0x05 +#define AUDIO_UD_CONTROL_LATENCY 0x06 + +/* Dolby Prologic?Processing Unit Control Selectors */ +#define AUDIO_DP_CONTROL_UNDEF 0x00 +#define AUDIO_DP_CONTROL_ENABLE 0x01 +#define AUDIO_DP_CONTROL_MODE_SELECT 0x02 +#define AUDIO_DP_CONTROL_CLUSTER 0x03 +#define AUDIO_DP_CONTROL_UNDERFLOW 0x04 +#define AUDIO_DP_CONTROL_OVERFLOW 0x05 +#define AUDIO_DP_CONTROL_LATENCY 0x06 + +/* Stereo Extender Processing Unit Control Selectors */ +#define AUDIO_STEXT_CONTROL_UNDEF 0x00 +#define AUDIO_STEXT_CONTROL_ENABLE 0x01 +#define AUDIO_STEXT_CONTROL_WIDTH 0x02 +#define AUDIO_STEXT_CONTROL_UNDERFLOW 0x03 +#define AUDIO_STEXT_CONTROL_OVERFLOW 0x04 +#define AUDIO_STEXT_CONTROL_LATENCY 0x05 + +/* Extension Unit Control Selectors */ + +#define AUDIO_XU_CONTROL_UNDEF 0x00 +#define AUDIO_XU_CONTROL_ENABLE 0x01 +#define AUDIO_XU_CONTROL_CLUSTER 0x02 +#define AUDIO_XU_CONTROL_UNDERFLOW 0x03 +#define AUDIO_XU_CONTROL_OVERFLOW 0x04 +#define AUDIO_XU_CONTROL_LATENCY 0x05 + +/* AudioStreaming Interface Control Selectors */ + +#define AUDIO_AS_CONTROL_UNDEF 0x00 +#define AUDIO_AS_CONTROL_ACT_ALT 0x01 +#define AUDIO_AS_CONTROL_VAL_ALT 0x02 +#define AUDIO_AS_CONTROL_AUDIO_FORMAT 0x03 + +/* Encoder Control Selectors */ + +#define AUDIO_EN_CONTROL_UNDEF 0x00 +#define AUDIO_EN_CONTROL_BIT_RATE 0x01 +#define AUDIO_EN_CONTROL_QUALITY 0x02 +#define AUDIO_EN_CONTROL_VBR 0x03 +#define AUDIO_EN_CONTROL_TYPE 0x04 +#define AUDIO_EN_CONTROL_UNDERFLOW 0x05 +#define AUDIO_EN_CONTROL_OVERFLOW 0x06 +#define AUDIO_EN_CONTROL_ENCODER_ERR 0x07 +#define AUDIO_EN_CONTROL_PARAM1 0x08 +#define AUDIO_EN_CONTROL_PARAM2 0x09 +#define AUDIO_EN_CONTROL_PARAM3 0x0a +#define AUDIO_EN_CONTROL_PARAM4 0x0b +#define AUDIO_EN_CONTROL_PARAM5 0x0c +#define AUDIO_EN_CONTROL_PARAM6 0x0d +#define AUDIO_EN_CONTROL_PARAM7 0x0e +#define AUDIO_EN_CONTROL_PARAM8 0x0f + +/* MPEG Decoder Control Selectors */ + +#define AUDIO_MPGD_CONTROL_UNDEF 0x00 +#define AUDIO_MPGD_CONTROL_DUAL_CHAN 0x01 +#define AUDIO_MPGD_CONTROL_2ND_STEREO 0x02 +#define AUDIO_MPGD_CONTROL_MULTILING 0x03 +#define AUDIO_MPGD_CONTROL_DYN_RANGE 0x04 +#define AUDIO_MPGD_CONTROL_SCALING 0x05 +#define AUDIO_MPGD_CONTROL_HILO_SCALE 0x06 +#define AUDIO_MPGD_CONTROL_UNDERFLOW 0x07 +#define AUDIO_MPGD_CONTROL_OVERFLOW 0x08 +#define AUDIO_MPGD_CONTROL_DECODE_ERR 0x09 + +/* AC-3 Decoder Control Selectors */ + +#define AUDIO_AC3D_CONTROL_UNDEF 0x00 +#define AUDIO_AC3D_CONTROL_MODE 0x01 +#define AUDIO_AC3D_CONTROL_DYN_RANGE 0x02 +#define AUDIO_AC3D_CONTROL_SCALING 0x03 +#define AUDIO_AC3D_CONTROL_HILO_SCALE 0x04 +#define AUDIO_AC3D_CONTROL_UNDERFLOW 0x05 +#define AUDIO_AC3D_CONTROL_OVERFLOW 0x06 +#define AUDIO_AC3D_CONTROL_DECODE_ERR 0x07 + +/* WMA Decoder Control Selectors */ + +#define AUDIO_WMAD_CONTROL_UNDEF 0x00 +#define AUDIO_WMAD_CONTROL_UNDERFLOW 0x01 +#define AUDIO_WMAD_CONTROL_OVERFLOW 0x02 +#define AUDIO_WMAD_CONTROL_DECODE_ERR 0x03 + +/* DTS Decoder Control Selectors */ + +#define AUDIO_DTSD_CONTROL_UNDEF 0x00 +#define AUDIO_DTSD_CONTROL_UNDERFLOW 0x01 +#define AUDIO_DTSD_CONTROL_OVERFLOW 0x02 +#define AUDIO_DTSD_CONTROL_DECODE_ERR 0x03 + +/* Endpoint Control Selectors */ +#define AUDIO_EP_CONTROL_UNDEF 0x00 +#define AUDIO_EP_CONTROL_SAMPLING_FEQ 0x01 +#define AUDIO_EP_CONTROL_PITCH 0x02 + +/* Encoder Error Codes */ + +/* <0: Reserved for vendor extensions */ + +#define AUDIO_ENCODER_SUCCESS 0 /* No Error */ +#define AUDIO_ENCODER_ERROR_NOMEM 1 /* Out of Memory */ +#define AUDIO_ENCODER_ERROR_BW 2 /* Out of Bandwidth */ +#define AUDIO_ENCODER_ERROR_CYCLE 3 /* Out of Processing Cycles */ +#define AUDIO_ENCODER_ERROR_FRAME 4 /* General Format Frame Error */ +#define AUDIO_ENCODER_ERROR_TOOSMALL 5 /* Format Frame Too Small */ +#define AUDIO_ENCODER_ERROR_TOOBIG 6 /* Format Frame Too Large */ +#define AUDIO_ENCODER_ERROR_BADFORMAT 7 /* Bad Data Format */ +#define AUDIO_ENCODER_ERROR_NCHAN 8 /* Incorrect Number of Channels */ +#define AUDIO_ENCODER_ERROR_RATE 9 /* Incorrect Sampling Rate */ +#define AUDIO_ENCODER_ERROR_BITRATE 10 /* Unable to Meet Target Bitrate */ +#define AUDIO_ENCODER_ERROR_PARMS 11 /* Inconsistent Set of Parameters */ +#define AUDIO_ENCODER_ERROR_NOTREADY 12 /* Not Ready */ +#define AUDIO_ENCODER_ERROR_BUSY 13 /* Busy */ + /* >13: Reserved */ + +/* Format Type Codes */ + +#define AUDIO_FORMAT_TYPE_UNDEF 0x00 +#define AUDIO_FORMAT_TYPEI 0x01 +#define AUDIO_FORMAT_TYPEII 0x02 +#define AUDIO_FORMAT_TYPEIII 0x03 +#define AUDIO_FORMAT_TYPEIV 0x04 +#define AUDIO_FORMAT_EXT_TYPEI 0x81 +#define AUDIO_FORMAT_EXT_TYPEII 0x82 +#define AUDIO_FORMAT_EXT_TYPEIII 0x83 + +/* Audio Data Format Type I Bit Allocations */ + +#define AUDIO_FORMAT_TYPEI_PCM (1 << 0) +#define AUDIO_FORMAT_TYPEI_PCM8 (1 << 1) +#define AUDIO_FORMAT_TYPEI_IEEEFLOAT (1 << 2) +#define AUDIO_FORMAT_TYPEI_ALAW (1 << 3) +#define AUDIO_FORMAT_TYPEI_MULAW (1 << 4) +#define AUDIO_FORMAT_TYPEI_RAWDATA (1 << 31) + +/* Audio Data Format Type II Bit Allocations */ + +#define AUDIO_FORMAT_TYPEII_MPEG (1 << 0) +#define AUDIO_FORMAT_TYPEII_AC3 (1 << 1) +#define AUDIO_FORMAT_TYPEII_WMA (1 << 2) +#define AUDIO_FORMAT_TYPEII_DTS (1 << 3) +#define AUDIO_FORMAT_TYPEII_RAWDATA (1 << 31) + +/* Audio Data Format Type III Bit Allocations */ + +#define AUDIO_FORMAT_TYPEIII_IEC61937_AC3 (1 << 0) +#define AUDIO_FORMAT_TYPEIII_IEC61937_MPEG1_L1 (1 << 1) +#define AUDIO_FORMAT_TYPEIII_IEC61937_MPEG1_L2_3 (1 << 1) +#define AUDIO_FORMAT_TYPEIII_IEC61937_MPEG2_NOEXT (1 << 2) +#define AUDIO_FORMAT_TYPEIII_IEC61937_MPEG2_EXT (1 << 3) +#define AUDIO_FORMAT_TYPEIII_IEC61937_MPEG2_AAC_ADTS (1 << 4) +#define AUDIO_FORMAT_TYPEIII_IEC61937_MPEG2_L1_LS (1 << 5) +#define AUDIO_FORMAT_TYPEIII_IEC61937_MPEG2_L2_3_LS (1 << 6) +#define AUDIO_FORMAT_TYPEIII_IEC61937_DTS_I (1 << 7) +#define AUDIO_FORMAT_TYPEIII_IEC61937_DTS_II (1 << 8) +#define AUDIO_FORMAT_TYPEIII_IEC61937_DTS_III (1 << 9) +#define AUDIO_FORMAT_TYPEIII_IEC61937_ATRAC (1 << 10) +#define AUDIO_FORMAT_TYPEIII_IEC61937_ATRAC2_3 (1 << 11) +#define AUDIO_FORMAT_TYPEIII_WMA (1 << 12) + +/* Audio Data Format Type IV Bit Allocations */ + +#define AUDIO_FORMAT_TYPEIV_PCM (1 << 0) +#define AUDIO_FORMAT_TYPEIV_PCM8 (1 << 1) +#define AUDIO_FORMAT_TYPEIV_IEEE_FLOAT (1 << 2) +#define AUDIO_FORMAT_TYPEIV_ALAW (1 << 3) +#define AUDIO_FORMAT_TYPEIV_MULAW (1 << 4) +#define AUDIO_FORMAT_TYPEIV_MPEG (1 << 5) +#define AUDIO_FORMAT_TYPEIV_AC3 (1 << 6) +#define AUDIO_FORMAT_TYPEIV_WMA (1 << 7) +#define AUDIO_FORMAT_TYPEIV_IEC61937_AC3 (1 << 8) +#define AUDIO_FORMAT_TYPEIV_IEC61937_MPEG1_L1 (1 << 9) +#define AUDIO_FORMAT_TYPEIV_IEC61937_MPEG1_L2_3 (1 << 10) +#define AUDIO_FORMAT_TYPEIV_IEC61937_MPEG2_NOEXT (1 << 10) +#define AUDIO_FORMAT_TYPEIV_IEC61937_MPEG2_EXT (1 << 11) +#define AUDIO_FORMAT_TYPEIV_IEC61937_MPEG2_AAC_ADTS (1 << 12) +#define AUDIO_FORMAT_TYPEIV_IEC61937_MPEG2_L1_LS (1 << 13) +#define AUDIO_FORMAT_TYPEIV_IEC61937_MPEG2_L2_3_LS (1 << 14) +#define AUDIO_FORMAT_TYPEIV_IEC61937_DTS_I (1 << 15) +#define AUDIO_FORMAT_TYPEIV_IEC61937_DTS_II (1 << 16) +#define AUDIO_FORMAT_TYPEIV_IEC61937_DTS_III (1 << 17) +#define AUDIO_FORMAT_TYPEIV_IEC61937_ATRAC (1 << 18) +#define AUDIO_FORMAT_TYPEIV_IEC61937_ATRAC2_3 (1 << 19) +#define AUDIO_FORMAT_TYPEIV_TYPE_III_WMA (1 << 20) +#define AUDIO_FORMAT_TYPEIV_IEC60958_PCM (1 << 21) + +/* Side Band Protocol Codes */ +#define AUDIO_SIDEBAND_PROTOCOL_UNDEF 0x00 +#define AUDIO_PRES_TIMESTAMP_PROTOCOL 0x01 + +/** USB Terminal Types + * Refer to Table 2-1 - Table 2-4 from termt10.pdf + */ + +/* USB Terminal Types */ +#define AUDIO_TERMINAL_UNDEF 0x0100 +#define AUDIO_TERMINAL_STREAMING 0x0101 +#define AUDIO_TERMINAL_VENDOR 0x01ff + +/* Input Terminal Types */ +#define AUDIO_INTERM_UNDEF 0x0200 /* Undefined Type */ +#define AUDIO_INTERM_MIC 0x0201 /* A generic microhpone */ +#define AUDIO_INTERM_DESKTOP_MIC 0x0202 /* A desktop microphone */ +#define AUDIO_INTERM_PERSONAL_MIC 0x0203 /* Head-mounted or clip-on microphone */ +#define AUDIO_INTERM_OMNI_MIC 0x0204 /* Omni-directional microphone */ +#define AUDIO_INTERM_MIC_ARRAY 0x0205 /* Microphone array */ +#define AUDIO_INTERM_PROC_MIC_ARRAY 0x0206 /* Microphone array with signal processor */ + +/* Output Terminal Types */ +#define AUDIO_OUTTERM_UNDEF 0x0300 /* Undefined Type */ +#define AUDIO_OUTTERM_SPEAKER 0x0301 /* Generic speakers */ +#define AUDIO_OUTTERM_HEADPHONES 0x0302 /* A head-mounted audio output device */ +#define AUDIO_OUTTERM_HEADDISPLAY 0x0303 /* Head Mounted Display Audio */ +#define AUDIO_OUTTERM_DESKTOP 0x0304 /* Desktop speaker */ +#define AUDIO_OUTTERM_ROOM 0x0305 /* Room speaker */ +#define AUDIO_OUTTERM_COMMS 0x0306 /* Communication speaker */ +#define AUDIO_OUTTERM_LOFREQ 0x0307 /* Low frequency effects speaker */ + +/* Bi-directional Terminal Types */ +#define AUDIO_BIDITERM_UNDEF 0x0400 /* Undefined Type */ +#define AUDIO_BIDITERM_HANDSET 0x0401 /* Hand-held bi-directional audio device */ +#define AUDIO_BIDITERM_HEADSET 0x0402 /* Head-mounted bi-directional audio device */ +#define AUDIO_BIDITERM_SPEAKERPHONE 0x0403 /* Speakerphone, no echo reduction */ +#define AUDIO_BIDITERM_ECHOSUPPRESS 0x0404 /* Echo-suppressing speakerphone */ +#define AUDIO_BIDITERM_ECHOCANCEL 0x0405 /* Echo-canceling speakerphone */ + +/* Telephony Terminal Types */ +#define AUDIO_TELETERM_UNDEF 0x0500 /* Undefined Type */ +#define AUDIO_TELETERM_PHONELINE 0x0501 /* Analog telephone line jack, an ISDN line, + * a proprietary PBX interface, or a wireless link */ +#define AUDIO_TELETERM_TELEPHONE 0x0502 /* Device can be used as a telephone */ +#define AUDIO_TELETERM_DOWNLINE 0x0503 /* Down Line Phone */ + +/* External Terminal Types */ +#define AUDIO_EXTTERM_UNDEF 0x0600 /* Undefined Type */ +#define AUDIO_EXTTERM_ANALOG 0x0601 /* Generic analog connector */ +#define AUDIO_EXTTERM_DIGITAL 0x0602 /* Generic digital audio interface */ +#define AUDIO_EXTTERM_LINE 0x0603 /* Analog connector at standard line levels */ +#define AUDIO_EXTTERM_LEGACY 0x0604 /* Legacy audio line out connector */ +#define AUDIO_EXTTERM_SPDIF 0x0605 /* SPDIF interface */ +#define AUDIO_EXTTERM_1394DA 0x0606 /* 1394 DA stream */ +#define AUDIO_EXTTERM_1394DV 0x0607 /* 1394 DV stream soundtrack */ +#define AUDIO_EXTTERM_ADAT 0x0608 /* ADAT Lightpipe */ +#define AUDIO_EXTTERM_TDIF 0x0609 /* TDIF - Tascam Digital Interface */ +#define AUDIO_EXTTERM_MADI 0x060a /* MADI - Multi-channel Audio Digital Interface (AES) */ + +/* Embedded Function Terminal Types */ +#define AUDIO_EMBEDTERM_UNDEF 0x0700 /* Undefined Type */ +#define AUDIO_EMBEDTERM_CALIBRATION 0x0701 /* Level Calibration Noise Source */ +#define AUDIO_EMBEDTERM_EQUALIZATION 0x0702 /* Equalization Noise */ +#define AUDIO_EMBEDTERM_CD 0x0703 /* CD player */ +#define AUDIO_EMBEDTERM_DAT 0x0704 /* Digital Audio Tape */ +#define AUDIO_EMBEDTERM_DCC 0x0705 /* Digital Compact Cassette */ +#define AUDIO_EMBEDTERM_COMPRESSED 0x0706 /* Compressed Audio Player */ +#define AUDIO_EMBEDTERM_TAPE 0x0707 /* Analog Audio Tape */ +#define AUDIO_EMBEDTERM_PHONOGRAPH 0x0708 /* Analog vinyl record player */ +#define AUDIO_EMBEDTERM_VCR 0x0709 /* Audio track of VCR */ +#define AUDIO_EMBEDTERM_VIDDISC 0x070a /* Audio track of VideoDisc player */ +#define AUDIO_EMBEDTERM_DVD 0x070b /* Audio track of DVD player */ +#define AUDIO_EMBEDTERM_TVTUNER 0x070c /* Audio track of TV tuner */ +#define AUDIO_EMBEDTERM_SATELLITE 0x070d /* Audio track of satellite receiver */ +#define AUDIO_EMBEDTERM_CABLETUNER 0x070e /* Audio track of cable tuner */ +#define AUDIO_EMBEDTERM_DSS 0x070f /* Audio track of DSS receiver */ +#define AUDIO_EMBEDTERM_RADIO 0x0710 /* AM/FM radio receiver */ +#define AUDIO_EMBEDTERM_TRANSMITTER 0x0711 /* AM/FM radio transmitter */ +#define AUDIO_EMBEDTERM_MULTITRACK 0x0712 /* A multi-track recording system */ +#define AUDIO_EMBEDTERM_SYNTHESIZER 0x0713 /* Synthesizer */ +#define AUDIO_EMBEDTERM_PIANO 0x0714 /* Piano */ +#define AUDIO_EMBEDTERM_GUITAR 0x0715 /* Guitar */ +#define AUDIO_EMBEDTERM_PERCUSSON 0x0716 /* Percussion Instrument */ +#define AUDIO_EMBEDTERM_INSTRUMENT 0x0717 /* Other Musical Instrument */ + +#define AUDIO_FORMAT_TYPE_I 0x01 +#define AUDIO_FORMAT_TYPE_II 0x02 +#define AUDIO_FORMAT_TYPE_III 0x03 + +struct audio_cs_if_ac_header_descriptor { + uint8_t bLength; + uint8_t bDescriptorType; + uint8_t bDescriptorSubtype; + uint16_t bcdADC; + uint16_t wTotalLength; + uint8_t bInCollection; + uint8_t baInterfaceNr[]; +} __PACKED; + +#define AUDIO_SIZEOF_AC_HEADER_DESC(bInCollection) (8 + (bInCollection)) + +struct audio_cs_if_ac_input_terminal_descriptor { + uint8_t bLength; + uint8_t bDescriptorType; + uint8_t bDescriptorSubtype; + uint8_t bTerminalID; + uint16_t wTerminalType; + uint8_t bAssocTerminal; + uint8_t bNrChannels; + uint16_t wChannelConfig; + uint8_t iChannelNames; + uint8_t iTerminal; +} __PACKED; + +#define AUDIO_SIZEOF_AC_INPUT_TERMINAL_DESC (12) + +struct audio_cs_if_ac_output_terminal_descriptor { + uint8_t bLength; + uint8_t bDescriptorType; + uint8_t bDescriptorSubtype; + uint8_t bTerminalID; + uint16_t wTerminalType; + uint8_t bAssocTerminal; + uint8_t bSourceID; + uint8_t iTerminal; +} __PACKED; + +#define AUDIO_SIZEOF_AC_OUTPUT_TERMINAL_DESC (9) + +struct audio_cs_if_ac_feature_unit_descriptor { + uint8_t bLength; + uint8_t bDescriptorType; + uint8_t bDescriptorSubtype; + uint8_t bUnitID; + uint8_t bSourceID; + uint8_t bControlSize; + uint8_t bmaControls[33]; // variable + uint8_t iFeature; +} __PACKED; + +#define AUDIO_SIZEOF_AC_FEATURE_UNIT_DESC(bNrChannels, bControlSize) (7 + ((bNrChannels) + 1) * (bControlSize)) + +struct audio_cs_if_ac_selector_unit_descriptor { + uint8_t bLength; + uint8_t bDescriptorType; + uint8_t bDescriptorSubtype; + uint8_t bUnitID; + uint8_t bNrInPins; + uint8_t baSourceID[1]; + uint8_t iSelector; +} __PACKED; + +#define AUDIO_SIZEOF_AC_SELECTOR_UNIT_DESC(bNrInPins) (6 + (bNrInPins)) + +struct audio_cs_if_as_general_descriptor { + uint8_t bLength; + uint8_t bDescriptorType; + uint8_t bDescriptorSubtype; + uint8_t bTerminalLink; + uint8_t bDelay; + uint16_t wFormatTag; +} __PACKED; + +#define AUDIO_SIZEOF_AS_GENERAL_DESC (7) + +struct audio_cs_if_as_format_type_descriptor { + uint8_t bLength; + uint8_t bDescriptorType; + uint8_t bDescriptorSubtype; + uint8_t bFormatType; + uint8_t bNrChannels; + uint8_t bSubframeSize; + uint8_t bBitResolution; + uint8_t bSamFreqType; + uint8_t tSamFreq[3]; +} __PACKED; + +#define AUDIO_SIZEOF_FORMAT_TYPE_DESC(bSamFreqType) (8 + 3 * (bSamFreqType)) + +struct audio_ep_descriptor { + uint8_t bLength; + uint8_t bDescriptorType; + uint8_t bEndpointAddress; + uint8_t bmAttributes; + uint16_t wMaxPacketSize; + uint8_t bInterval; + uint8_t bRefresh; + uint8_t bSynchAddress; +} __PACKED; + +#define AUDIO_SIZEOF_EP_DESC (9) + +struct audio_cs_ep_ep_general_descriptor { + uint8_t bLength; + uint8_t bDescriptorType; + uint8_t bDescriptorSubtype; + uint8_t bmAttributes; + uint8_t bLockDelayUnits; + uint16_t wLockDelay; +} __PACKED; + +#define AUDIO_SIZEOF_CS_EP_GENERAL_DESC (7) + +// clang-format off +#define AUDIO_AC_DESCRIPTOR_INIT(bFirstInterface, bInterfaceCount, wTotalLength, stridx, ...) \ + /* Interface Association Descriptor */ \ + 0x08, \ + USB_DESCRIPTOR_TYPE_INTERFACE_ASSOCIATION, \ + bFirstInterface, \ + bInterfaceCount, \ + USB_DEVICE_CLASS_AUDIO, \ + AUDIO_SUBCLASS_AUDIOCONTROL, \ + AUDIO_PROTOCOL_UNDEFINED, \ + 0x00, \ + /* ------------------ AudioControl Interface ------------------ */\ + 0x09, /* bLength */ \ + USB_DESCRIPTOR_TYPE_INTERFACE, /* bDescriptorType */ \ + bFirstInterface, /* bInterfaceNumber */ \ + 0x00, /* bAlternateSetting */ \ + 0x00, /* bNumEndpoints */ \ + USB_DEVICE_CLASS_AUDIO, /* bInterfaceClass */ \ + AUDIO_SUBCLASS_AUDIOCONTROL, /* bInterfaceSubClass */ \ + AUDIO_PROTOCOL_UNDEFINED, /* bInterfaceProtocol */ \ + stridx, /* iInterface */ \ + 0x08 + PP_NARG(__VA_ARGS__), /* bLength */ \ + AUDIO_INTERFACE_DESCRIPTOR_TYPE, /* bDescriptorType */ \ + AUDIO_CONTROL_HEADER, /* bDescriptorSubtype */ \ + WBVAL(0x0100), /* bcdADC */ \ + WBVAL(wTotalLength), /* wTotalLength */ \ + PP_NARG(__VA_ARGS__), /* bInCollection */ \ + __VA_ARGS__ /* baInterfaceNr */ + +#define AUDIO_AC_DESCRIPTOR_LEN(bInCollection) (0x08 + 0x09 + 0x08 + bInCollection) + +#define AUDIO_AC_INPUT_TERMINAL_DESCRIPTOR_INIT(bTerminalID, wTerminalType, bNrChannels, wChannelConfig) \ + 0x0C, /* bLength */ \ + AUDIO_INTERFACE_DESCRIPTOR_TYPE, /* bDescriptorType */ \ + AUDIO_CONTROL_INPUT_TERMINAL, /* bDescriptorSubtype */ \ + bTerminalID, /* bTerminalID */ \ + WBVAL(wTerminalType), /* wTerminalType : Microphone 0x0201 */ \ + 0x00, /* bAssocTerminal */ \ + bNrChannels, /* bNrChannels */ \ + WBVAL(wChannelConfig), /* wChannelConfig : Mono sets no position bits */ \ + 0x00, /* iChannelNames */ \ + 0x00 /* iTerminal */ + +#define AUDIO_AC_OUTPUT_TERMINAL_DESCRIPTOR_INIT(bTerminalID, wTerminalType, bSourceID) \ + 0x09, /* bLength */ \ + AUDIO_INTERFACE_DESCRIPTOR_TYPE, /* bDescriptorType */ \ + AUDIO_CONTROL_OUTPUT_TERMINAL, /* bDescriptorSubtype */ \ + bTerminalID, /* bTerminalID */ \ + WBVAL(wTerminalType), /* wTerminalType : USB Streaming */ \ + 0x00, /* bAssocTerminal */ \ + bSourceID, /* bSourceID */ \ + 0x00 /* iTerminal */ + +#define AUDIO_AC_FEATURE_UNIT_DESCRIPTOR_INIT(bUnitID, bSourceID, bControlSize, ...) \ + 0x07 + PP_NARG(__VA_ARGS__), /* bLength */ \ + AUDIO_INTERFACE_DESCRIPTOR_TYPE, /* bDescriptorType */ \ + AUDIO_CONTROL_FEATURE_UNIT, /* bDescriptorSubtype */ \ + bUnitID, /* bUnitID */ \ + bSourceID, /* bSourceID */ \ + bControlSize, /* bControlSize */ \ + __VA_ARGS__, /* bmaControls(0) Mute */ \ + 0x00 /* iTerminal */ + +#define AUDIO_AS_DESCRIPTOR_INIT(bInterfaceNumber, bTerminalLink, bNrChannels, bSubFrameSize, bBitResolution, bEndpointAddress, bmAttributes, wMaxPacketSize, bInterval, ...) \ + 0x09, /* bLength */ \ + USB_DESCRIPTOR_TYPE_INTERFACE, /* bDescriptorType */ \ + bInterfaceNumber, /* bInterfaceNumber */ \ + 0x00, /* bAlternateSetting */ \ + 0x00, /* bNumEndpoints */ \ + USB_DEVICE_CLASS_AUDIO, /* bInterfaceClass */ \ + AUDIO_SUBCLASS_AUDIOSTREAMING, /* bInterfaceSubClass */ \ + AUDIO_PROTOCOL_UNDEFINED, /* bInterfaceProtocol */ \ + 0x00, /* iInterface */ \ + 0x09, /* bLength */ \ + USB_DESCRIPTOR_TYPE_INTERFACE, /* bDescriptorType */ \ + bInterfaceNumber, /* bInterfaceNumber */ \ + 0x01, /* bAlternateSetting */ \ + 0x01, /* bNumEndpoints */ \ + USB_DEVICE_CLASS_AUDIO, /* bInterfaceClass */ \ + AUDIO_SUBCLASS_AUDIOSTREAMING, /* bInterfaceSubClass */ \ + AUDIO_PROTOCOL_UNDEFINED, /* bInterfaceProtocol */ \ + 0x00, /* iInterface */ \ + 0x07, /* bLength */ \ + AUDIO_INTERFACE_DESCRIPTOR_TYPE, /* bDescriptorType */ \ + AUDIO_STREAMING_GENERAL, /* bDescriptorSubtype */ \ + bTerminalLink, /* bTerminalLink : Unit ID of the Output Terminal*/ \ + 0x01, /* bDelay */ \ + WBVAL(AUDIO_FORMAT_PCM), /* wFormatTag : AUDIO_FORMAT_PCM */ \ + 0x08 + PP_NARG(__VA_ARGS__), /* bLength */ \ + AUDIO_INTERFACE_DESCRIPTOR_TYPE, /* bDescriptorType */ \ + AUDIO_STREAMING_FORMAT_TYPE, /* bDescriptorSubtype */ \ + AUDIO_FORMAT_TYPE_I, /* bFormatType */ \ + bNrChannels, /* bNrChannels */ \ + bSubFrameSize, /* bSubFrameSize : Bytes per audio subframe */ \ + bBitResolution, /* bBitResolution : bits per sample */ \ + (PP_NARG(__VA_ARGS__)/3), /* bSamFreqType : only one frequency supported */ \ + __VA_ARGS__, /* tSamFreq : Audio sampling frequency coded on 3 bytes */ \ + 0x09, /* bLength */ \ + USB_DESCRIPTOR_TYPE_ENDPOINT, /* bDescriptorType */ \ + bEndpointAddress, /* bEndpointAddress : IN endpoint 1 */ \ + bmAttributes, /* bmAttributes */ \ + WBVAL(wMaxPacketSize), /* wMaxPacketSize */ \ + bInterval, /* bInterval : one packet per frame */ \ + 0x00, /* bRefresh */ \ + 0x00, /* bSynchAddress */ \ + 0x07, /* bLength */ \ + AUDIO_ENDPOINT_DESCRIPTOR_TYPE, /* bDescriptorType */ \ + AUDIO_ENDPOINT_GENERAL, /* bDescriptor */ \ + AUDIO_EP_CONTROL_SAMPLING_FEQ, /* bmAttributes AUDIO_SAMPLING_FREQ_CONTROL */ \ + 0x00, /* bLockDelayUnits */ \ + 0x00, /* wLockDelay */ \ + 0x00 + +#define AUDIO_AS_FEEDBACK_DESCRIPTOR_INIT(bInterfaceNumber, bTerminalLink, bNrChannels, bSubFrameSize, bBitResolution, bEndpointAddress, wMaxPacketSize, bInterval, bFeedbackEndpointAddress, ...) \ + 0x09, /* bLength */ \ + USB_DESCRIPTOR_TYPE_INTERFACE, /* bDescriptorType */ \ + bInterfaceNumber, /* bInterfaceNumber */ \ + 0x00, /* bAlternateSetting */ \ + 0x00, /* bNumEndpoints */ \ + USB_DEVICE_CLASS_AUDIO, /* bInterfaceClass */ \ + AUDIO_SUBCLASS_AUDIOSTREAMING, /* bInterfaceSubClass */ \ + AUDIO_PROTOCOL_UNDEFINED, /* bInterfaceProtocol */ \ + 0x00, /* iInterface */ \ + 0x09, /* bLength */ \ + USB_DESCRIPTOR_TYPE_INTERFACE, /* bDescriptorType */ \ + bInterfaceNumber, /* bInterfaceNumber */ \ + 0x01, /* bAlternateSetting */ \ + 0x02, /* bNumEndpoints */ \ + USB_DEVICE_CLASS_AUDIO, /* bInterfaceClass */ \ + AUDIO_SUBCLASS_AUDIOSTREAMING, /* bInterfaceSubClass */ \ + AUDIO_PROTOCOL_UNDEFINED, /* bInterfaceProtocol */ \ + 0x00, /* iInterface */ \ + 0x07, /* bLength */ \ + AUDIO_INTERFACE_DESCRIPTOR_TYPE, /* bDescriptorType */ \ + AUDIO_STREAMING_GENERAL, /* bDescriptorSubtype */ \ + bTerminalLink, /* bTerminalLink : Unit ID of the Output Terminal*/ \ + 0x01, /* bDelay */ \ + WBVAL(AUDIO_FORMAT_PCM), /* wFormatTag : AUDIO_FORMAT_PCM */ \ + 0x08 + PP_NARG(__VA_ARGS__), /* bLength */ \ + AUDIO_INTERFACE_DESCRIPTOR_TYPE, /* bDescriptorType */ \ + AUDIO_STREAMING_FORMAT_TYPE, /* bDescriptorSubtype */ \ + AUDIO_FORMAT_TYPE_I, /* bFormatType */ \ + bNrChannels, /* bNrChannels */ \ + bSubFrameSize, /* bSubFrameSize : Bytes per audio subframe */ \ + bBitResolution, /* bBitResolution : bits per sample */ \ + (PP_NARG(__VA_ARGS__)/3), /* bSamFreqType : only one frequency supported */ \ + __VA_ARGS__, /* tSamFreq : Audio sampling frequency coded on 3 bytes */ \ + 0x09, /* bLength */ \ + USB_DESCRIPTOR_TYPE_ENDPOINT, /* bDescriptorType */ \ + bEndpointAddress, /* bEndpointAddress : IN endpoint 1 */ \ + 0x05, /* bmAttributes */ \ + WBVAL(wMaxPacketSize), /* wMaxPacketSize */ \ + bInterval, /* bInterval : one packet per frame */ \ + 0x00, /* bRefresh */ \ + bFeedbackEndpointAddress, /* bSynchAddress */ \ + 0x07, /* bLength */ \ + AUDIO_ENDPOINT_DESCRIPTOR_TYPE, /* bDescriptorType */ \ + AUDIO_ENDPOINT_GENERAL, /* bDescriptor */ \ + AUDIO_EP_CONTROL_SAMPLING_FEQ, /* bmAttributes AUDIO_SAMPLING_FREQ_CONTROL */ \ + 0x00, /* bLockDelayUnits */ \ + 0x00, /* wLockDelay */ \ + 0x00, \ + 0x09, /* bLength */ \ + USB_DESCRIPTOR_TYPE_ENDPOINT, /* bDescriptorType */ \ + bFeedbackEndpointAddress, /* bFeedbackEndpointAddress Revise Dir to bEndpointAddress */ \ + 0x11, /* bmAttributes: TransferType=Isochronous SyncType=None EndpointType=Feedback */ \ + WBVAL(4), /* XXXX wMaxPacketSize in Bytes */ \ + bInterval, /* bInterval */ \ + 0x03, /* bRefresh, 8ms */ \ + 0x00 /* bSynchAddress */ + +#define AUDIO_AS_DESCRIPTOR_LEN(bSamFreqType) (0x09 + 0x09 + 0x07 + 0x08 + 3 * (bSamFreqType) + 0x09 + 0x07) +#define AUDIO_AS_FEEDBACK_DESCRIPTOR_LEN(bSamFreqType) (0x09 + 0x09 + 0x07 + 0x08 + 3 * (bSamFreqType) + 0x09 + 0x07 + 0x09) + +#define AUDIO_AS_ALTSETTING_DESCRIPTOR_INIT(bInterfaceNumber, bAlternateSetting, bTerminalLink, bNrChannels, bSubFrameSize, bBitResolution, bEndpointAddress, bmAttributes, wMaxPacketSize, bInterval, ...) \ + 0x09, /* bLength */ \ + USB_DESCRIPTOR_TYPE_INTERFACE, /* bDescriptorType */ \ + bInterfaceNumber, /* bInterfaceNumber */ \ + bAlternateSetting, /* bAlternateSetting */ \ + 0x01, /* bNumEndpoints */ \ + USB_DEVICE_CLASS_AUDIO, /* bInterfaceClass */ \ + AUDIO_SUBCLASS_AUDIOSTREAMING, /* bInterfaceSubClass */ \ + AUDIO_PROTOCOL_UNDEFINED, /* bInterfaceProtocol */ \ + 0x00, /* iInterface */ \ + 0x07, /* bLength */ \ + AUDIO_INTERFACE_DESCRIPTOR_TYPE, /* bDescriptorType */ \ + AUDIO_STREAMING_GENERAL, /* bDescriptorSubtype */ \ + bTerminalLink, /* bTerminalLink : Unit ID of the Output Terminal*/ \ + 0x01, /* bDelay */ \ + WBVAL(AUDIO_FORMAT_PCM), /* wFormatTag : AUDIO_FORMAT_PCM */ \ + 0x08 + PP_NARG(__VA_ARGS__), /* bLength */ \ + AUDIO_INTERFACE_DESCRIPTOR_TYPE, /* bDescriptorType */ \ + AUDIO_STREAMING_FORMAT_TYPE, /* bDescriptorSubtype */ \ + AUDIO_FORMAT_TYPE_I, /* bFormatType */ \ + bNrChannels, /* bNrChannels */ \ + bSubFrameSize, /* bSubFrameSize : Bytes per audio subframe */ \ + bBitResolution, /* bBitResolution : bits per sample */ \ + (PP_NARG(__VA_ARGS__)/3), /* bSamFreqType : only one frequency supported */ \ + __VA_ARGS__, /* tSamFreq : Audio sampling frequency coded on 3 bytes */ \ + 0x09, /* bLength */ \ + USB_DESCRIPTOR_TYPE_ENDPOINT, /* bDescriptorType */ \ + bEndpointAddress, /* bEndpointAddress : IN endpoint 1 */ \ + bmAttributes, /* bmAttributes */ \ + WBVAL(wMaxPacketSize), /* wMaxPacketSize */ \ + bInterval, /* bInterval : one packet per frame */ \ + 0x00, /* bRefresh */ \ + 0x00, /* bSynchAddress */ \ + 0x07, /* bLength */ \ + AUDIO_ENDPOINT_DESCRIPTOR_TYPE, /* bDescriptorType */ \ + AUDIO_ENDPOINT_GENERAL, /* bDescriptor */ \ + AUDIO_EP_CONTROL_SAMPLING_FEQ, /* bmAttributes AUDIO_SAMPLING_FREQ_CONTROL */ \ + 0x00, /* bLockDelayUnits */ \ + 0x00, /* wLockDelay */ \ + 0x00 + +#define AUDIO_AS_ALTSETTING_DESCRIPTOR_LEN(bSamFreqType) (0x09 + 0x07 + 0x08 + 3 * (bSamFreqType) + 0x09 + 0x07) + +#define AUDIO_AS_ALTSETTING0_DESCRIPTOR_INIT(bInterfaceNumber) \ + 0x09, /* bLength */ \ + USB_DESCRIPTOR_TYPE_INTERFACE, /* bDescriptorType */ \ + bInterfaceNumber, /* bInterfaceNumber */ \ + 0x00, /* bAlternateSetting */ \ + 0x01, /* bNumEndpoints */ \ + USB_DEVICE_CLASS_AUDIO, /* bInterfaceClass */ \ + AUDIO_SUBCLASS_AUDIOSTREAMING, /* bInterfaceSubClass */ \ + AUDIO_PROTOCOL_UNDEFINED, /* bInterfaceProtocol */ \ + 0x00 /* iInterface */ + +struct audio_v2_channel_cluster_descriptor { + uint8_t bNrChannels; + uint32_t bmChannelConfig; + uint8_t iChannelNames; +} __PACKED; + +#define AUDIO_V2_SIZEOF_CHANNEL_CLUSTER_DESC (6) + +struct audio_v2_cs_if_ac_header_descriptor { + uint8_t bLength; + uint8_t bDescriptorType; + uint8_t bDescriptorSubtype; + uint16_t bcdADC; + uint8_t bCategory; + uint16_t wTotalLength; + uint8_t bmControls; +} __PACKED; + +#define AUDIO_V2_SIZEOF_AC_HEADER_DESC (9) + +struct audio_v2_cs_if_ac_clock_source_descriptor { + uint8_t bLength; + uint8_t bDescriptorType; + uint8_t bDescriptorSubtype; + uint8_t bClockID; + uint8_t bmAttributes; + uint8_t bmControls; + uint8_t bAssocTerminal; + uint8_t iClockSource; +} __PACKED; + +#define AUDIO_V2_SIZEOF_AC_CLOCK_SOURCE_DESC (8) + +struct audio_v2_cs_if_ac_clock_selector_descriptor { + uint8_t bLength; + uint8_t bDescriptorType; + uint8_t bDescriptorSubtype; + uint8_t bClockID; + uint8_t bNrInPins; + uint8_t baCSourceID[1]; + uint8_t iClockSelector; +} __PACKED; + +#define AUDIO_SIZEOF_AC_CLOCK_SELECTOR_DESC(bNrInPins) (7 + (bNrInPins)) + +struct audio_v2_cs_if_ac_clock_multiplier_descriptor { + uint8_t bLength; + uint8_t bDescriptorType; + uint8_t bDescriptorSubtype; + uint8_t bClockID; + uint8_t bCSourceID; + uint8_t bmControls; + uint8_t iClockMultiplier; +} __PACKED; + +#define AUDIO_SIZEOF_AC_CLOCK_MULTIPLIER_DESC (7) + +struct audio_v2_cs_if_ac_input_terminal_descriptor { + uint8_t bLength; + uint8_t bDescriptorType; + uint8_t bDescriptorSubtype; + uint8_t bTerminalID; + uint16_t wTerminalType; + uint8_t bAssocTerminal; + uint8_t bCSourceID; + uint8_t bNrChannels; + uint32_t wChannelConfig; + uint8_t iChannelNames; + uint16_t bmControls; + uint8_t iTerminal; +} __PACKED; + +#define AUDIO_V2_SIZEOF_AC_INPUT_TERMINAL_DESC (17) + +struct audio_v2_cs_if_ac_output_terminal_descriptor { + uint8_t bLength; + uint8_t bDescriptorType; + uint8_t bDescriptorSubtype; + uint8_t bTerminalID; + uint16_t wTerminalType; + uint8_t bAssocTerminal; + uint8_t bSourceID; + uint8_t bCSourceID; + uint16_t bmControls; + uint8_t iTerminal; +} __PACKED; + +#define AUDIO_V2_SIZEOF_AC_OUTPUT_TERMINAL_DESC (12) + +struct audio_v2_cs_if_ac_feature_unit_descriptor { + uint8_t bLength; + uint8_t bDescriptorType; + uint8_t bDescriptorSubtype; + uint8_t bUnitID; + uint8_t bSourceID; + uint32_t bmaControls[1]; + uint8_t iFeature; +} __PACKED; + +#define AUDIO_V2_SIZEOF_AC_FEATURE_UNIT_DESC(bNrChannels) (6 + ((bNrChannels) + 1) * 4) + +struct audio_v2_cs_if_as_general_descriptor { + uint8_t bLength; + uint8_t bDescriptorType; + uint8_t bDescriptorSubtype; + uint8_t bTerminalLink; + uint8_t bmControls; + uint8_t bFormatType; + uint32_t bmFormats; + uint8_t bNrChannels; + uint32_t bmChannelConfig; + uint8_t iChannelNames; +} __PACKED; + +#define AUDIO_V2_SIZEOF_AS_GENERAL_DESC (16) + +struct audio_v2_control_range1_param_block { + uint16_t wNumSubRanges; + struct + { + uint8_t bMin; + uint8_t bMax; + uint8_t bRes; + }subrange[]; +} __PACKED; + +struct audio_v2_control_range2_param_block { + uint16_t wNumSubRanges; + struct + { + uint16_t wMin; + uint16_t wMax; + uint16_t wRes; + }subrange[]; +} __PACKED; + +struct audio_v2_control_range3_param_block { + uint16_t wNumSubRanges; + struct + { + uint32_t dMin; + uint32_t dMax; + uint32_t dRes; + }subrange[]; +} __PACKED; + +#define AUDIO_V2_AC_DESCRIPTOR_INIT(bFirstInterface, bInterfaceCount, wTotalLength, bCategory, bmControls, stridx) \ + /* Interface Association Descriptor */ \ + 0x08, \ + USB_DESCRIPTOR_TYPE_INTERFACE_ASSOCIATION, \ + bFirstInterface, \ + bInterfaceCount, \ + USB_DEVICE_CLASS_AUDIO, \ + AUDIO_SUBCLASS_UNDEFINED, \ + AUDIO_PROTOCOLv20, \ + 0x00, \ + /* ------------------ AudioControl Interface ------------------ */\ + 0x09, /* bLength */ \ + USB_DESCRIPTOR_TYPE_INTERFACE, /* bDescriptorType */ \ + bFirstInterface, /* bInterfaceNumber */ \ + 0x00, /* bAlternateSetting */ \ + 0x00, /* bNumEndpoints */ \ + USB_DEVICE_CLASS_AUDIO, /* bInterfaceClass */ \ + AUDIO_SUBCLASS_AUDIOCONTROL, /* bInterfaceSubClass */ \ + AUDIO_PROTOCOLv20, /* bInterfaceProtocol */ \ + stridx, /* iInterface */ \ + 0x09, /* bLength */ \ + AUDIO_INTERFACE_DESCRIPTOR_TYPE, /* bDescriptorType */ \ + AUDIO_CONTROL_HEADER, /* bDescriptorSubtype */ \ + WBVAL(0x0200), /* bcdADC */ \ + bCategory, /* bCategory */ \ + WBVAL(wTotalLength), /* wTotalLength */ \ + bmControls /* bmControls */ \ + +#define AUDIO_V2_AC_DESCRIPTOR_LEN (0x08 + 0x09 + 0x09) + +#define AUDIO_V2_AC_CLOCK_SOURCE_DESCRIPTOR_INIT(bClockID, bmAttributes, bmControls) \ + 0x08, /* bLength */ \ + AUDIO_INTERFACE_DESCRIPTOR_TYPE, /* bDescriptorType */ \ + AUDIO_CONTROL_CLOCK_SOURCE, /* bDescriptorSubtype */ \ + bClockID, /* bClockID */ \ + bmAttributes, /* bmAttributes */ \ + bmControls, /* bmControls */ \ + 0x00, /* bAssocTerminal */ \ + 0x00 /* iClockSource */ + +#define AUDIO_V2_AC_INPUT_TERMINAL_DESCRIPTOR_INIT(bTerminalID, wTerminalType, bCSourceID, bNrChannels, wChannelConfig, bmControls) \ + 0x11, /* bLength */ \ + AUDIO_INTERFACE_DESCRIPTOR_TYPE, /* bDescriptorType */ \ + AUDIO_CONTROL_INPUT_TERMINAL, /* bDescriptorSubtype */ \ + bTerminalID, /* bTerminalID */ \ + WBVAL(wTerminalType), /* wTerminalType : Microphone 0x0201 */ \ + 0x00, /* bAssocTerminal */ \ + bCSourceID, /* bCSourceID */ \ + bNrChannels, /* bNrChannels */ \ + DBVAL(wChannelConfig), /* wChannelConfig : Mono sets no position bits */ \ + 0x00, /* iChannelNames */ \ + WBVAL(bmControls), /* bmControls */ \ + 0x00 /* iTerminal */ + +#define AUDIO_V2_AC_OUTPUT_TERMINAL_DESCRIPTOR_INIT(bTerminalID, wTerminalType, bSourceID, bCSourceID, bmControls) \ + 0x0c, /* bLength */ \ + AUDIO_INTERFACE_DESCRIPTOR_TYPE, /* bDescriptorType */ \ + AUDIO_CONTROL_OUTPUT_TERMINAL, /* bDescriptorSubtype */ \ + bTerminalID, /* bTerminalID */ \ + WBVAL(wTerminalType), /* wTerminalType : USB Streaming */ \ + 0x00, /* bAssocTerminal */ \ + bSourceID, /* bSourceID */ \ + bCSourceID, /* bCSourceID */ \ + WBVAL(bmControls), /* bmControls */ \ + 0x00 /* iTerminal */ + +#define AUDIO_V2_AC_FEATURE_UNIT_DESCRIPTOR_INIT(bUnitID, bSourceID, ...) \ + 0x06 + (PP_NARG(__VA_ARGS__)), /* bLength */ \ + AUDIO_INTERFACE_DESCRIPTOR_TYPE, /* bDescriptorType */ \ + AUDIO_CONTROL_FEATURE_UNIT, /* bDescriptorSubtype */ \ + bUnitID, /* bUnitID */ \ + bSourceID, /* bSourceID */ \ + __VA_ARGS__, /* bmaControls(0) Mute */ \ + 0x00 /* iTerminal */ + +#define AUDIO_V2_AS_DESCRIPTOR_INIT(bInterfaceNumber, bTerminalLink, bNrChannels, bmChannelConfig, bSubslotSize, bBitResolution, bEndpointAddress, bmAttributes, wMaxPacketSize, bInterval) \ + 0x09, /* bLength */ \ + USB_DESCRIPTOR_TYPE_INTERFACE, /* bDescriptorType */ \ + bInterfaceNumber, /* bInterfaceNumber */ \ + 0x00, /* bAlternateSetting */ \ + 0x00, /* bNumEndpoints */ \ + USB_DEVICE_CLASS_AUDIO, /* bInterfaceClass */ \ + AUDIO_SUBCLASS_AUDIOSTREAMING, /* bInterfaceSubClass */ \ + AUDIO_PROTOCOLv20, /* bInterfaceProtocol */ \ + 0x00, /* iInterface */ \ + 0x09, /* bLength */ \ + USB_DESCRIPTOR_TYPE_INTERFACE, /* bDescriptorType */ \ + bInterfaceNumber, /* bInterfaceNumber */ \ + 0x01, /* bAlternateSetting */ \ + 0x01, /* bNumEndpoints */ \ + USB_DEVICE_CLASS_AUDIO, /* bInterfaceClass */ \ + AUDIO_SUBCLASS_AUDIOSTREAMING, /* bInterfaceSubClass */ \ + AUDIO_PROTOCOLv20, /* bInterfaceProtocol */ \ + 0x00, /* iInterface */ \ + 0x10, /* bLength */ \ + AUDIO_INTERFACE_DESCRIPTOR_TYPE, /* bDescriptorType */ \ + AUDIO_STREAMING_GENERAL, /* bDescriptorSubtype */ \ + bTerminalLink, /* bTerminalLink : Unit ID of the Output or Input Terminal*/ \ + 0x00, /* bmControls */ \ + AUDIO_FORMAT_TYPE_I, /* bFormatType : AUDIO_FORMAT_TYPE_I */ \ + DBVAL(AUDIO_V2_FORMAT_PCM), /* bmFormats PCM */ \ + bNrChannels, /* bNrChannels */ \ + DBVAL(bmChannelConfig), /* bmChannelConfig */ \ + 0x00, /* iChannelNames */ \ + 0x06, /* bLength */ \ + AUDIO_INTERFACE_DESCRIPTOR_TYPE, /* bDescriptorType */ \ + AUDIO_STREAMING_FORMAT_TYPE, /* bDescriptorSubtype */ \ + AUDIO_FORMAT_TYPE_I, /* bFormatType */ \ + bSubslotSize, /* bSubslotSize */ \ + bBitResolution, /* bBitResolution */ \ + 0x07, /* bLength */ \ + USB_DESCRIPTOR_TYPE_ENDPOINT, /* bDescriptorType */ \ + bEndpointAddress, /* bEndpointAddress 3 out endpoint for Audio */ \ + bmAttributes, /* bmAttributes */ \ + WBVAL(wMaxPacketSize), /* XXXX wMaxPacketSize in Bytes (SampleRate * SlotByteSize * NumChannels) */ \ + bInterval, /* bInterval */ \ + 0x08, /* bLength */ \ + AUDIO_ENDPOINT_DESCRIPTOR_TYPE, /* bDescriptorType */ \ + AUDIO_ENDPOINT_GENERAL, /* bDescriptor */ \ + 0x00, /* bmAttributes */ \ + 0x00, /* bmControls */ \ + 0x00, /* bLockDelayUnits */ \ + 0x00, /* wLockDelay */ \ + 0x00 + +#define AUDIO_V2_AS_ALTSETTING_DESCRIPTOR_INIT(bInterfaceNumber, bAlternateSetting, bTerminalLink, bNrChannels, bmChannelConfig, bSubslotSize, bBitResolution, bEndpointAddress, bmAttributes, wMaxPacketSize, bInterval) \ + 0x09, /* bLength */ \ + USB_DESCRIPTOR_TYPE_INTERFACE, /* bDescriptorType */ \ + bInterfaceNumber, /* bInterfaceNumber */ \ + bAlternateSetting, /* bAlternateSetting */ \ + 0x01, /* bNumEndpoints */ \ + USB_DEVICE_CLASS_AUDIO, /* bInterfaceClass */ \ + AUDIO_SUBCLASS_AUDIOSTREAMING, /* bInterfaceSubClass */ \ + AUDIO_PROTOCOLv20, /* bInterfaceProtocol */ \ + 0x00, /* iInterface */ \ + 0x10, /* bLength */ \ + AUDIO_INTERFACE_DESCRIPTOR_TYPE, /* bDescriptorType */ \ + AUDIO_STREAMING_GENERAL, /* bDescriptorSubtype */ \ + bTerminalLink, /* bTerminalLink : Unit ID of the Output or Input Terminal*/ \ + 0x00, /* bmControls */ \ + AUDIO_FORMAT_TYPE_I, /* bFormatType : AUDIO_FORMAT_TYPE_I */ \ + DBVAL(AUDIO_V2_FORMAT_PCM), /* bmFormats PCM */ \ + bNrChannels, /* bNrChannels */ \ + DBVAL(bmChannelConfig), /* bmChannelConfig */ \ + 0x00, /* iChannelNames */ \ + 0x06, /* bLength */ \ + AUDIO_INTERFACE_DESCRIPTOR_TYPE, /* bDescriptorType */ \ + AUDIO_STREAMING_FORMAT_TYPE, /* bDescriptorSubtype */ \ + AUDIO_FORMAT_TYPE_I, /* bFormatType */ \ + bSubslotSize, /* bSubslotSize */ \ + bBitResolution, /* bBitResolution */ \ + 0x07, /* bLength */ \ + USB_DESCRIPTOR_TYPE_ENDPOINT, /* bDescriptorType */ \ + bEndpointAddress, /* bEndpointAddress 3 out endpoint for Audio */ \ + bmAttributes, /* bmAttributes */ \ + WBVAL(wMaxPacketSize), /* XXXX wMaxPacketSize in Bytes (SampleRate * SlotByteSize * NumChannels) */ \ + bInterval, /* bInterval */ \ + 0x08, /* bLength */ \ + AUDIO_ENDPOINT_DESCRIPTOR_TYPE, /* bDescriptorType */ \ + AUDIO_ENDPOINT_GENERAL, /* bDescriptor */ \ + 0x00, /* bmAttributes */ \ + 0x00, /* bmControls */ \ + 0x00, /* bLockDelayUnits */ \ + 0x00, /* wLockDelay */ \ + 0x00 + +#define AUDIO_V2_AS_ALTSETTING0_DESCRIPTOR_INIT(bInterfaceNumber) \ + 0x09, /* bLength */ \ + USB_DESCRIPTOR_TYPE_INTERFACE, /* bDescriptorType */ \ + bInterfaceNumber, /* bInterfaceNumber */ \ + 0x00, /* bAlternateSetting */ \ + 0x01, /* bNumEndpoints */ \ + USB_DEVICE_CLASS_AUDIO, /* bInterfaceClass */ \ + AUDIO_SUBCLASS_AUDIOSTREAMING, /* bInterfaceSubClass */ \ + AUDIO_PROTOCOLv20, /* bInterfaceProtocol */ \ + 0x00 /* iInterface */ + +#define AUDIO_V2_AS_FEEDBACK_DESCRIPTOR_INIT(bInterfaceNumber, bTerminalLink, bNrChannels, bmChannelConfig, bSubslotSize, bBitResolution, bEndpointAddress, wMaxPacketSize, bInterval, bFeedbackEndpointAddress) \ + 0x09, /* bLength */ \ + USB_DESCRIPTOR_TYPE_INTERFACE, /* bDescriptorType */ \ + bInterfaceNumber, /* bInterfaceNumber */ \ + 0x00, /* bAlternateSetting */ \ + 0x00, /* bNumEndpoints */ \ + USB_DEVICE_CLASS_AUDIO, /* bInterfaceClass */ \ + AUDIO_SUBCLASS_AUDIOSTREAMING, /* bInterfaceSubClass */ \ + AUDIO_PROTOCOLv20, /* bInterfaceProtocol */ \ + 0x00, /* iInterface */ \ + 0x09, /* bLength */ \ + USB_DESCRIPTOR_TYPE_INTERFACE, /* bDescriptorType */ \ + bInterfaceNumber, /* bInterfaceNumber */ \ + 0x01, /* bAlternateSetting */ \ + 0x02, /* bNumEndpoints */ \ + USB_DEVICE_CLASS_AUDIO, /* bInterfaceClass */ \ + AUDIO_SUBCLASS_AUDIOSTREAMING, /* bInterfaceSubClass */ \ + AUDIO_PROTOCOLv20, /* bInterfaceProtocol */ \ + 0x00, /* iInterface */ \ + 0x10, /* bLength */ \ + AUDIO_INTERFACE_DESCRIPTOR_TYPE, /* bDescriptorType */ \ + AUDIO_STREAMING_GENERAL, /* bDescriptorSubtype */ \ + bTerminalLink, /* bTerminalLink : Unit ID of the Output or Input Terminal*/ \ + 0x00, /* bmControls */ \ + AUDIO_FORMAT_TYPE_I, /* bFormatType : AUDIO_FORMAT_TYPE_I */ \ + DBVAL(AUDIO_V2_FORMAT_PCM), /* bmFormats PCM */ \ + bNrChannels, /* bNrChannels */ \ + DBVAL(bmChannelConfig), /* bmChannelConfig */ \ + 0x00, /* iChannelNames */ \ + 0x06, /* bLength */ \ + AUDIO_INTERFACE_DESCRIPTOR_TYPE, /* bDescriptorType */ \ + AUDIO_STREAMING_FORMAT_TYPE, /* bDescriptorSubtype */ \ + AUDIO_FORMAT_TYPE_I, /* bFormatType */ \ + bSubslotSize, /* bSubslotSize */ \ + bBitResolution, /* bBitResolution */ \ + 0x07, /* bLength */ \ + USB_DESCRIPTOR_TYPE_ENDPOINT, /* bDescriptorType */ \ + bEndpointAddress, /* bEndpointAddress 3 out endpoint for Audio */ \ + 0x05, /* bmAttributes: TransferType=Isochronous SyncType=Asynchronous EndpointType=Data*/ \ + WBVAL(wMaxPacketSize), /* XXXX wMaxPacketSize in Bytes (SampleRate * SlotByteSize * NumChannels) */ \ + bInterval, /* bInterval */ \ + 0x08, /* bLength */ \ + AUDIO_ENDPOINT_DESCRIPTOR_TYPE, /* bDescriptorType */ \ + AUDIO_ENDPOINT_GENERAL, /* bDescriptor */ \ + 0x00, /* bmAttributes */ \ + 0x00, /* bmControls */ \ + 0x00, /* bLockDelayUnits */ \ + 0x00, /* wLockDelay */ \ + 0x00, \ + 0x07, /* bLength */ \ + USB_DESCRIPTOR_TYPE_ENDPOINT, /* bDescriptorType */ \ + bFeedbackEndpointAddress, /* bFeedbackEndpointAddress Revise Dir to bEndpointAddress */ \ + 0x11, /* bmAttributes: TransferType=Isochronous SyncType=None EndpointType=Feedback */ \ + WBVAL(4), /* XXXX wMaxPacketSize in Bytes */ \ + bInterval /* bInterval */ + +// clang-format on + +#define AUDIO_V2_AS_DESCRIPTOR_LEN (0x09 + 0x09 + 0x10 + 0x06 + 0x07 + 0x08) +#define AUDIO_V2_AS_ALTSETTING0_DESCRIPTOR_LEN (0x09) +#define AUDIO_V2_AS_ALTSETTING_DESCRIPTOR_LEN (0x09 + 0x10 + 0x06 + 0x07 + 0x08) +#define AUDIO_V2_AS_FEEDBACK_DESCRIPTOR_LEN (0x09 + 0x09 + 0x10 + 0x06 + 0x07 + 0x08 + 0x07) + +#define AUDIO_SAMPLE_FREQ_NUM(num) (uint8_t)(num), (uint8_t)((num >> 8)) +#define AUDIO_SAMPLE_FREQ_3B(frq) (uint8_t)(frq), (uint8_t)((frq >> 8)), (uint8_t)((frq >> 16)) +#define AUDIO_SAMPLE_FREQ_4B(frq) (uint8_t)(frq), (uint8_t)((frq >> 8)), \ + (uint8_t)((frq >> 16)), (uint8_t)((frq >> 24)) + +/* format 10.14 */ +#define AUDIO_FREQ_TO_FEEDBACK_FS(freq) ((freq << 10) / 1000) +#define AUDIO_FEEDBACK_TO_BUF_FS(buf, feedback) \ + buf[0] = ((feedback << 4) & 0xFFU); \ + buf[1] = (((feedback << 4) >> 8U) & 0xFFU); \ + buf[2] = (((feedback << 4) >> 16U) & 0xFFU) + +/* format 16.16 */ +#define AUDIO_FREQ_TO_FEEDBACK_HS(freq) ((freq << 13) / 1000) +#define AUDIO_FEEDBACK_TO_BUF_HS(buf, feedback) \ + buf[0] = (((feedback & 0x00001FFFu) << 3) & 0xFFu); \ + buf[1] = ((((feedback & 0x00001FFFu) << 3) >> 8) & 0xFFu); \ + buf[2] = (((feedback & 0x01FFE000u) >> 13) & 0xFFu); \ + buf[3] = (((feedback & 0x01FFE000u) >> 21) & 0xFFu) + +#endif /* USB_AUDIO_H */ diff --git a/kernel/cherryusb/class/audio/usbd_audio.c b/kernel/cherryusb/class/audio/usbd_audio.c new file mode 100644 index 0000000..9e4e2ac --- /dev/null +++ b/kernel/cherryusb/class/audio/usbd_audio.c @@ -0,0 +1,381 @@ +/* + * Copyright (c) 2022, sakumisu + * + * SPDX-License-Identifier: Apache-2.0 + */ +#include "usbd_core.h" +#include "usbd_audio.h" + +struct audio_entity_param { + uint32_t wCur; + uint32_t wMin; + uint32_t wMax; + uint32_t wRes; +}; + +struct usbd_audio_priv { + struct audio_entity_info *table; + uint8_t num; + uint16_t uac_version; +} g_usbd_audio[CONFIG_USBDEV_MAX_BUS]; + +static int audio_class_endpoint_request_handler(uint8_t busid, struct usb_setup_packet *setup, uint8_t **data, uint32_t *len) +{ + uint8_t control_selector; + uint32_t sampling_freq = 0; + uint8_t ep; + + control_selector = HI_BYTE(setup->wValue); + ep = LO_BYTE(setup->wIndex); + + switch (control_selector) { + case AUDIO_EP_CONTROL_SAMPLING_FEQ: + switch (setup->bRequest) { + case AUDIO_REQUEST_SET_CUR: + memcpy((uint8_t *)&sampling_freq, *data, 3); + USB_LOG_DBG("Set ep:0x%02x %d Hz\r\n", ep, (int)sampling_freq); + usbd_audio_set_sampling_freq(busid, ep, sampling_freq); + break; + case AUDIO_REQUEST_GET_CUR: + case AUDIO_REQUEST_GET_MIN: + case AUDIO_REQUEST_GET_MAX: + case AUDIO_REQUEST_GET_RES: + sampling_freq = usbd_audio_get_sampling_freq(busid, ep); + memcpy(*data, &sampling_freq, 3); + USB_LOG_DBG("Get ep:0x%02x %d Hz\r\n", ep, (int)sampling_freq); + *len = 3; + break; + } + + break; + default: + return -1; + } + return 0; +} + +static int audio_class_interface_request_handler(uint8_t busid, struct usb_setup_packet *setup, uint8_t **data, uint32_t *len) +{ + USB_LOG_DBG("Audio Class request: " + "bRequest 0x%02x\r\n", + setup->bRequest); + + uint8_t entity_id; + uint8_t ep = 0; + uint8_t subtype = 0x01; + uint8_t control_selector; + uint8_t ch; + uint8_t mute; + uint16_t volume; + int volume_db = 0; + uint32_t sampling_freq = 0; + + const char *mute_string[2] = { "off", "on" }; + + entity_id = HI_BYTE(setup->wIndex); + control_selector = HI_BYTE(setup->wValue); + ch = LO_BYTE(setup->wValue); + + ARG_UNUSED(mute_string); + + for (uint8_t i = 0; i < g_usbd_audio[busid].num; i++) { + if (g_usbd_audio[busid].table[i].bEntityId == entity_id) { + subtype = g_usbd_audio[busid].table[i].bDescriptorSubtype; + ep = g_usbd_audio[busid].table[i].ep; + break; + } + } + + if (subtype == 0x01) { + USB_LOG_ERR("Do not find subtype for 0x%02x\r\n", entity_id); + return -1; + } + + USB_LOG_DBG("Audio entity_id:%02x, subtype:%02x, cs:%02x\r\n", entity_id, subtype, control_selector); + + switch (subtype) { + case AUDIO_CONTROL_FEATURE_UNIT: + switch (control_selector) { + case AUDIO_FU_CONTROL_MUTE: + if (g_usbd_audio[busid].uac_version < 0x0200) { + switch (setup->bRequest) { + case AUDIO_REQUEST_SET_CUR: + mute = (*data)[0]; + usbd_audio_set_mute(busid, ep, ch, mute); + break; + case AUDIO_REQUEST_GET_CUR: + (*data)[0] = usbd_audio_get_mute(busid, ep, ch); + *len = 1; + break; + default: + return -1; + } + } else { + switch (setup->bRequest) { + case AUDIO_REQUEST_CUR: + if (setup->bmRequestType & USB_REQUEST_DIR_MASK) { + (*data)[0] = usbd_audio_get_mute(busid, ep, ch); + *len = 1; + } else { + mute = (*data)[0]; + usbd_audio_set_mute(busid, ep, ch, mute); + } + break; + default: + return -1; + } + } + break; + case AUDIO_FU_CONTROL_VOLUME: + if (g_usbd_audio[busid].uac_version < 0x0200) { + switch (setup->bRequest) { + case AUDIO_REQUEST_SET_CUR: + memcpy(&volume, *data, 2); + if (volume < 0x8000) { + volume_db = volume / 256; + } else { + volume_db = (volume - 0x10000) / 256; + } + USB_LOG_DBG("Set ep:0x%02x ch:%d vol_hex:0x%04x, vol_db:%d dB\r\n", ep, ch, volume, volume_db); + usbd_audio_set_volume(busid, ep, ch, volume_db); + break; + case AUDIO_REQUEST_GET_CUR: + volume_db = usbd_audio_get_volume(busid, ep, ch); + if (volume_db >= 0) { + volume = volume_db * 256; + } else { + volume = volume_db * 256 + 0x10000; + } + USB_LOG_DBG("Get ep:0x%02x ch:%d vol_hex:0x%04x, vol_db:%d dB\r\n", ep, ch, volume, volume_db); + memcpy(*data, &volume, 2); + *len = 2; + break; + case AUDIO_REQUEST_GET_MIN: + (*data)[0] = 0x00; /* -100 dB */ + (*data)[1] = 0x9c; + *len = 2; + break; + case AUDIO_REQUEST_GET_MAX: + (*data)[0] = 0x00; /* 0 dB */ + (*data)[1] = 0x00; + *len = 2; + break; + case AUDIO_REQUEST_GET_RES: + (*data)[0] = 0x00; /* 1 dB */ + (*data)[1] = 0x01; + *len = 2; + break; + default: + return -1; + } + } else { + switch (setup->bRequest) { + case AUDIO_REQUEST_CUR: + if (setup->bmRequestType & USB_REQUEST_DIR_MASK) { + volume_db = usbd_audio_get_volume(busid, ep, ch); + if (volume_db >= 0) { + volume = volume_db * 256; + } else { + volume = volume_db * 256 + 0x10000; + } + USB_LOG_DBG("Get ep:0x%02x ch:%d vol_hex:0x%04x, vol_db:%d dB\r\n", ep, ch, volume, volume_db); + memcpy(*data, &volume, 2); + *len = 2; + } else { + memcpy(&volume, *data, 2); + if (volume < 0x8000) { + volume_db = volume / 256; + } else { + volume_db = (volume - 0x10000) / 256; + } + USB_LOG_DBG("Set ep:0x%02x ch:%d vol_hex:0x%04x, vol_db:%d dB\r\n", ep, ch, volume, volume_db); + usbd_audio_set_volume(busid, ep, ch, volume_db); + } + break; + case AUDIO_REQUEST_RANGE: + if (setup->bmRequestType & USB_REQUEST_DIR_MASK) { + *((uint16_t *)(*data + 0)) = 1; + *((uint16_t *)(*data + 2)) = 0x9c00; /* MIN -100 dB */ + *((uint16_t *)(*data + 4)) = 0x0000; /* MAX 0 dB */ + *((uint16_t *)(*data + 6)) = 0x100; /* RES 1 dB */ + *len = 8; + } else { + } + break; + default: + return -1; + } + } + break; + + default: + return -1; + } + break; + case AUDIO_CONTROL_CLOCK_SOURCE: + switch (control_selector) { + case AUDIO_CS_CONTROL_SAM_FREQ: + switch (setup->bRequest) { + case AUDIO_REQUEST_CUR: + if (setup->bmRequestType & USB_REQUEST_DIR_MASK) { + sampling_freq = usbd_audio_get_sampling_freq(busid, ep); + memcpy(*data, &sampling_freq, 4); + USB_LOG_DBG("Get ep:0x%02x %d Hz\r\n", ep, (int)sampling_freq); + *len = 4; + } else { + memcpy(&sampling_freq, *data, 4); + USB_LOG_DBG("Set ep:0x%02x %d Hz\r\n", ep, (int)sampling_freq); + usbd_audio_set_sampling_freq(busid, ep, sampling_freq); + } + break; + case AUDIO_REQUEST_RANGE: + if (setup->bmRequestType & USB_REQUEST_DIR_MASK) { + uint8_t *sampling_freq_table = NULL; + uint16_t num; + + usbd_audio_get_sampling_freq_table(busid, ep, &sampling_freq_table); + num = (uint16_t)((uint16_t)(sampling_freq_table[1] << 8) | ((uint16_t)sampling_freq_table[0])); + memcpy(*data, sampling_freq_table, (12 * num + 2)); + *len = (12 * num + 2); + } else { + } + break; + default: + return -1; + } + break; + case AUDIO_CS_CONTROL_CLOCK_VALID: + if (setup->bmRequestType & USB_REQUEST_DIR_MASK) { + (*data)[0] = 1; + *len = 1; + } else { + return -1; + } + break; + + default: + return -1; + } + break; + + default: + break; + } + return 0; +} + +static void audio_notify_handler(uint8_t busid, uint8_t event, void *arg) +{ + switch (event) { + case USBD_EVENT_RESET: + + break; + + case USBD_EVENT_SET_INTERFACE: { + struct usb_interface_descriptor *intf = (struct usb_interface_descriptor *)arg; + if (intf->bAlternateSetting) { + usbd_audio_open(busid, intf->bInterfaceNumber); + } else { + usbd_audio_close(busid, intf->bInterfaceNumber); + } + } + + break; + + default: + break; + } +} + +struct usbd_interface *usbd_audio_init_intf(uint8_t busid, + struct usbd_interface *intf, + uint16_t uac_version, + struct audio_entity_info *table, + uint8_t num) +{ + if (uac_version < 0x0200) { + intf->class_interface_handler = audio_class_interface_request_handler; + intf->class_endpoint_handler = audio_class_endpoint_request_handler; + intf->vendor_handler = NULL; + intf->notify_handler = audio_notify_handler; + } else { + intf->class_interface_handler = audio_class_interface_request_handler; + intf->class_endpoint_handler = NULL; + intf->vendor_handler = NULL; + intf->notify_handler = audio_notify_handler; + } + + g_usbd_audio[busid].uac_version = uac_version; + g_usbd_audio[busid].table = table; + g_usbd_audio[busid].num = num; + + return intf; +} + +__WEAK void usbd_audio_set_volume(uint8_t busid, uint8_t ep, uint8_t ch, int volume_db) +{ + (void)busid; + (void)ep; + (void)ch; + (void)volume_db; +} + +__WEAK int usbd_audio_get_volume(uint8_t busid, uint8_t ep, uint8_t ch) +{ + (void)busid; + (void)ep; + (void)ch; + + return 0; +} + +__WEAK void usbd_audio_set_mute(uint8_t busid, uint8_t ep, uint8_t ch, bool mute) +{ + (void)busid; + (void)ep; + (void)ch; + (void)mute; +} + +__WEAK bool usbd_audio_get_mute(uint8_t busid, uint8_t ep, uint8_t ch) +{ + (void)busid; + (void)ep; + (void)ch; + + return 0; +} + +__WEAK void usbd_audio_set_sampling_freq(uint8_t busid, uint8_t ep, uint32_t sampling_freq) +{ + (void)busid; + (void)ep; + (void)sampling_freq; +} + +__WEAK uint32_t usbd_audio_get_sampling_freq(uint8_t busid, uint8_t ep) +{ + (void)busid; + (void)ep; + + return 0; +} + +__WEAK void usbd_audio_get_sampling_freq_table(uint8_t busid, uint8_t ep, uint8_t **sampling_freq_table) +{ + (void)busid; + (void)ep; + (void)sampling_freq_table; +} + +__WEAK void usbd_audio_open(uint8_t busid, uint8_t intf) +{ + (void)busid; + (void)intf; +} + +__WEAK void usbd_audio_close(uint8_t busid, uint8_t intf) +{ + (void)busid; + (void)intf; +} \ No newline at end of file diff --git a/kernel/cherryusb/class/audio/usbd_audio.h b/kernel/cherryusb/class/audio/usbd_audio.h new file mode 100644 index 0000000..75a0b17 --- /dev/null +++ b/kernel/cherryusb/class/audio/usbd_audio.h @@ -0,0 +1,43 @@ +/* + * Copyright (c) 2022, sakumisu + * + * SPDX-License-Identifier: Apache-2.0 + */ +#ifndef USBD_AUDIO_H +#define USBD_AUDIO_H + +#include "usb_audio.h" + +#ifdef __cplusplus +extern "C" { +#endif + +struct audio_entity_info { + uint8_t bDescriptorSubtype; + uint8_t bEntityId; + uint8_t ep; +}; + +/* Init audio interface driver */ +struct usbd_interface *usbd_audio_init_intf(uint8_t busid, struct usbd_interface *intf, + uint16_t uac_version, + struct audio_entity_info *table, + uint8_t num); + +void usbd_audio_open(uint8_t busid, uint8_t intf); +void usbd_audio_close(uint8_t busid, uint8_t intf); + +void usbd_audio_set_volume(uint8_t busid, uint8_t ep, uint8_t ch, int volume_db); +int usbd_audio_get_volume(uint8_t busid, uint8_t ep, uint8_t ch); +void usbd_audio_set_mute(uint8_t busid, uint8_t ep, uint8_t ch, bool mute); +bool usbd_audio_get_mute(uint8_t busid, uint8_t ep, uint8_t ch); +void usbd_audio_set_sampling_freq(uint8_t busid, uint8_t ep, uint32_t sampling_freq); +uint32_t usbd_audio_get_sampling_freq(uint8_t busid, uint8_t ep); + +void usbd_audio_get_sampling_freq_table(uint8_t busid, uint8_t ep, uint8_t **sampling_freq_table); + +#ifdef __cplusplus +} +#endif + +#endif /* USBD_AUDIO_H */ diff --git a/kernel/cherryusb/class/audio/usbh_audio.c b/kernel/cherryusb/class/audio/usbh_audio.c new file mode 100644 index 0000000..22f1f19 --- /dev/null +++ b/kernel/cherryusb/class/audio/usbh_audio.c @@ -0,0 +1,681 @@ +/* + * Copyright (c) 2022, sakumisu + * + * SPDX-License-Identifier: Apache-2.0 + */ +#include "usbh_core.h" +#include "usbh_audio.h" + +#undef USB_DBG_TAG +#define USB_DBG_TAG "usbh_audio" +#include "usb_log.h" + +#define DEV_FORMAT "/dev/audio%d" + +/* general descriptor field offsets */ +#define DESC_bLength 0 /** Length offset */ +#define DESC_bDescriptorType 1 /** Descriptor type offset */ +#define DESC_bDescriptorSubType 2 /** Descriptor subtype offset */ + +/* interface descriptor field offsets */ +#define INTF_DESC_bInterfaceNumber 2 /** Interface number offset */ +#define INTF_DESC_bAlternateSetting 3 /** Alternate setting offset */ + +USB_NOCACHE_RAM_SECTION USB_MEM_ALIGNX uint8_t g_audio_buf[USB_ALIGN_UP(128, CONFIG_USB_ALIGN_SIZE)]; + +static struct usbh_audio g_audio_class[CONFIG_USBHOST_MAX_AUDIO_CLASS]; +static uint32_t g_devinuse = 0; + +static struct usbh_audio *usbh_audio_class_alloc(void) +{ + uint8_t devno; + + for (devno = 0; devno < CONFIG_USBHOST_MAX_AUDIO_CLASS; devno++) { + if ((g_devinuse & (1U << devno)) == 0) { + g_devinuse |= (1U << devno); + memset(&g_audio_class[devno], 0, sizeof(struct usbh_audio)); + g_audio_class[devno].minor = devno; + return &g_audio_class[devno]; + } + } + return NULL; +} + +static void usbh_audio_class_free(struct usbh_audio *audio_class) +{ + uint8_t devno = audio_class->minor; + + if (devno < 32) { + g_devinuse &= ~(1U << devno); + } + memset(audio_class, 0, sizeof(struct usbh_audio)); +} + +int usbh_audio_open(struct usbh_audio *audio_class, const char *name, uint32_t samp_freq, uint8_t bitresolution) +{ + struct usb_setup_packet *setup; + struct usb_endpoint_descriptor *ep_desc; + uint8_t mult; + uint16_t mps; + int ret; + uint8_t intf = 0xff; + uint8_t altsetting = 0xff; + + if (!audio_class || !audio_class->hport) { + return -USB_ERR_INVAL; + } + setup = audio_class->hport->setup; + + if (audio_class->is_opened) { + return 0; + } + + for (uint8_t i = 0; i < audio_class->stream_intf_num; i++) { + if (strcmp(name, audio_class->as_msg_table[i].stream_name) == 0) { + intf = audio_class->as_msg_table[i].stream_intf; + for (uint8_t j = 1; j < audio_class->as_msg_table[i].num_of_altsetting; j++) { + if (audio_class->as_msg_table[i].as_format[j].bBitResolution == bitresolution) { + for (uint8_t k = 0; k < audio_class->as_msg_table[i].as_format[j].bSamFreqType; k++) { + uint32_t freq = 0; + + memcpy(&freq, &audio_class->as_msg_table[i].as_format[j].tSamFreq[3 * k], 3); + if (freq == samp_freq) { + altsetting = j; + goto freq_found; + } + } + } + } + } + } + +freq_found: + if(altsetting == 0xff) { + return -USB_ERR_NODEV; + } + + setup->bmRequestType = USB_REQUEST_DIR_OUT | USB_REQUEST_STANDARD | USB_REQUEST_RECIPIENT_INTERFACE; + setup->bRequest = USB_REQUEST_SET_INTERFACE; + setup->wValue = altsetting; + setup->wIndex = intf; + setup->wLength = 0; + + ret = usbh_control_transfer(audio_class->hport, setup, NULL); + if (ret < 0) { + return ret; + } + + ep_desc = &audio_class->hport->config.intf[intf].altsetting[altsetting].ep[0].ep_desc; + + if (audio_class->as_msg_table[intf - audio_class->ctrl_intf - 1].ep_attr & AUDIO_EP_CONTROL_SAMPLING_FEQ) { + setup->bmRequestType = USB_REQUEST_DIR_OUT | USB_REQUEST_CLASS | USB_REQUEST_RECIPIENT_ENDPOINT; + setup->bRequest = AUDIO_REQUEST_SET_CUR; + setup->wValue = (AUDIO_EP_CONTROL_SAMPLING_FEQ << 8) | 0x00; + setup->wIndex = ep_desc->bEndpointAddress; + setup->wLength = 3; + + memcpy(g_audio_buf, &samp_freq, 3); + ret = usbh_control_transfer(audio_class->hport, setup, g_audio_buf); + if (ret < 0) { + return ret; + } + } + + mult = (ep_desc->wMaxPacketSize & USB_MAXPACKETSIZE_ADDITIONAL_TRANSCATION_MASK) >> USB_MAXPACKETSIZE_ADDITIONAL_TRANSCATION_SHIFT; + mps = ep_desc->wMaxPacketSize & USB_MAXPACKETSIZE_MASK; + if (ep_desc->bEndpointAddress & 0x80) { + audio_class->isoin_mps = mps * (mult + 1); + USBH_EP_INIT(audio_class->isoin, ep_desc); + } else { + audio_class->isoout_mps = mps * (mult + 1); + USBH_EP_INIT(audio_class->isoout, ep_desc); + } + + USB_LOG_INFO("Open audio stream :%s, altsetting: %u\r\n", name, altsetting); + audio_class->is_opened = true; + return ret; +} + +int usbh_audio_close(struct usbh_audio *audio_class, const char *name) +{ + struct usb_setup_packet *setup; + struct usb_endpoint_descriptor *ep_desc; + int ret; + uint8_t intf = 0xff; + uint8_t altsetting = 1; + + if (!audio_class || !audio_class->hport) { + return -USB_ERR_INVAL; + } + setup = audio_class->hport->setup; + + for (uint8_t i = 0; i < audio_class->stream_intf_num; i++) { + if (strcmp(name, audio_class->as_msg_table[i].stream_name) == 0) { + intf = audio_class->as_msg_table[i].stream_intf; + goto intf_found; + } + } + +intf_found: + if (intf == 0xff) { + return -USB_ERR_NODEV; + } + + setup->bmRequestType = USB_REQUEST_DIR_OUT | USB_REQUEST_STANDARD | USB_REQUEST_RECIPIENT_INTERFACE; + setup->bRequest = USB_REQUEST_SET_INTERFACE; + setup->wValue = 0; + setup->wIndex = intf; + setup->wLength = 0; + + ret = usbh_control_transfer(audio_class->hport, setup, NULL); + if (ret < 0) { + return ret; + } + USB_LOG_INFO("Close audio stream :%s\r\n", name); + audio_class->is_opened = false; + + ep_desc = &audio_class->hport->config.intf[intf].altsetting[altsetting].ep[0].ep_desc; + if (ep_desc->bEndpointAddress & 0x80) { + if (audio_class->isoin) { + audio_class->isoin = NULL; + } + } else { + if (audio_class->isoout) { + audio_class->isoout = NULL; + } + } + + return ret; +} + +int usbh_audio_set_volume(struct usbh_audio *audio_class, const char *name, uint8_t ch, int volume_db) +{ + struct usb_setup_packet *setup; + int ret; + uint8_t feature_id = 0xff; + uint8_t intf; + uint16_t volume_hex; + int volume_min_db; + int volume_max_db; + + if (!audio_class || !audio_class->hport) { + return -USB_ERR_INVAL; + } + + if ((volume_db > 127) || (volume_db < -127)) { + return -USB_ERR_INVAL; + } + + setup = audio_class->hport->setup; + + for (uint8_t i = 0; i < audio_class->stream_intf_num; i++) { + if (strcmp(name, audio_class->as_msg_table[i].stream_name) == 0) { + feature_id = audio_class->as_msg_table[i].feature_terminal_id; + intf = audio_class->as_msg_table[i].stream_intf; + goto feature_found; + } + } + +feature_found: + if (feature_id == 0xff) { + return -USB_ERR_NODEV; + } + + setup->bmRequestType = USB_REQUEST_DIR_IN | USB_REQUEST_CLASS | USB_REQUEST_RECIPIENT_INTERFACE; + setup->bRequest = AUDIO_REQUEST_GET_CUR; + setup->wValue = (AUDIO_FU_CONTROL_VOLUME << 8) | ch; + setup->wIndex = (feature_id << 8) | audio_class->ctrl_intf; + setup->wLength = 2; + + ret = usbh_control_transfer(audio_class->hport, setup, g_audio_buf); + if (ret < 0) { + return ret; + } + + memcpy(&audio_class->as_msg_table[intf - audio_class->ctrl_intf - 1].volume_cur, g_audio_buf, 2); + + setup->bmRequestType = USB_REQUEST_DIR_IN | USB_REQUEST_CLASS | USB_REQUEST_RECIPIENT_INTERFACE; + setup->bRequest = AUDIO_REQUEST_GET_MIN; + setup->wValue = (AUDIO_FU_CONTROL_VOLUME << 8) | ch; + setup->wIndex = (feature_id << 8) | audio_class->ctrl_intf; + setup->wLength = 2; + + ret = usbh_control_transfer(audio_class->hport, setup, g_audio_buf); + if (ret < 0) { + return ret; + } + + memcpy(&audio_class->as_msg_table[intf - audio_class->ctrl_intf - 1].volume_min, g_audio_buf, 2); + + setup->bmRequestType = USB_REQUEST_DIR_IN | USB_REQUEST_CLASS | USB_REQUEST_RECIPIENT_INTERFACE; + setup->bRequest = AUDIO_REQUEST_GET_MAX; + setup->wValue = (AUDIO_FU_CONTROL_VOLUME << 8) | ch; + setup->wIndex = (feature_id << 8) | audio_class->ctrl_intf; + setup->wLength = 2; + + ret = usbh_control_transfer(audio_class->hport, setup, g_audio_buf); + if (ret < 0) { + return ret; + } + memcpy(&audio_class->as_msg_table[intf - audio_class->ctrl_intf - 1].volume_max, g_audio_buf, 2); + + setup->bmRequestType = USB_REQUEST_DIR_IN | USB_REQUEST_CLASS | USB_REQUEST_RECIPIENT_INTERFACE; + setup->bRequest = AUDIO_REQUEST_GET_RES; + setup->wValue = (AUDIO_FU_CONTROL_VOLUME << 8) | ch; + setup->wIndex = (feature_id << 8) | audio_class->ctrl_intf; + setup->wLength = 2; + + ret = usbh_control_transfer(audio_class->hport, setup, g_audio_buf); + if (ret < 0) { + return ret; + } + memcpy(&audio_class->as_msg_table[intf - audio_class->ctrl_intf - 1].volume_res, g_audio_buf, 2); + + setup->bmRequestType = USB_REQUEST_DIR_OUT | USB_REQUEST_CLASS | USB_REQUEST_RECIPIENT_INTERFACE; + setup->bRequest = AUDIO_REQUEST_SET_CUR; + setup->wValue = (AUDIO_FU_CONTROL_VOLUME << 8) | ch; + setup->wIndex = (feature_id << 8) | audio_class->ctrl_intf; + setup->wLength = 2; + + if (audio_class->as_msg_table[intf - audio_class->ctrl_intf - 1].volume_min < 0x8000) { + volume_min_db = audio_class->as_msg_table[intf - audio_class->ctrl_intf - 1].volume_min / 256; + } else { + volume_min_db = (audio_class->as_msg_table[intf - audio_class->ctrl_intf - 1].volume_min - 0x10000) / 256; + } + + if (audio_class->as_msg_table[intf - audio_class->ctrl_intf - 1].volume_max < 0x8000) { + volume_max_db = audio_class->as_msg_table[intf - audio_class->ctrl_intf - 1].volume_max / 256; + } else { + volume_max_db = (audio_class->as_msg_table[intf - audio_class->ctrl_intf - 1].volume_max - 0x10000) / 256; + } + + USB_LOG_INFO("Get ch:%u dB range: %ddB ~ %ddB\r\n", ch, volume_min_db, volume_max_db); + + if (volume_db >= 0) { + volume_hex = volume_db * 256; + if (volume_hex > audio_class->as_msg_table[intf - audio_class->ctrl_intf - 1].volume_max) { + return -USB_ERR_RANGE; + } + } else { + volume_hex = volume_db * 256 + 0x10000; + if (volume_hex < audio_class->as_msg_table[intf - audio_class->ctrl_intf - 1].volume_min) { + return -USB_ERR_RANGE; + } + } + + memcpy(g_audio_buf, &volume_hex, 2); + ret = usbh_control_transfer(audio_class->hport, setup, g_audio_buf); + if (ret < 0) { + return ret; + } + audio_class->as_msg_table[intf - audio_class->ctrl_intf - 1].volume_cur = volume_hex; + return ret; +} + +int usbh_audio_set_mute(struct usbh_audio *audio_class, const char *name, uint8_t ch, bool mute) +{ + struct usb_setup_packet *setup; + int ret; + uint8_t feature_id = 0xff; + uint8_t intf = 0xff; + + if (!audio_class || !audio_class->hport) { + return -USB_ERR_INVAL; + } + setup = audio_class->hport->setup; + + for (uint8_t i = 0; i < audio_class->stream_intf_num; i++) { + if (strcmp(name, audio_class->as_msg_table[i].stream_name) == 0) { + feature_id = audio_class->as_msg_table[i].feature_terminal_id; + intf = audio_class->as_msg_table[i].stream_intf; + goto feature_found; + } + } + +feature_found: + if (feature_id == 0xff) { + return -USB_ERR_NODEV; + } + + setup->bmRequestType = USB_REQUEST_DIR_OUT | USB_REQUEST_CLASS | USB_REQUEST_RECIPIENT_INTERFACE; + setup->bRequest = AUDIO_REQUEST_SET_CUR; + setup->wValue = (AUDIO_FU_CONTROL_MUTE << 8) | ch; + setup->wIndex = (feature_id << 8) | audio_class->ctrl_intf; + setup->wLength = 1; + + memcpy(g_audio_buf, &mute, 1); + ret = usbh_control_transfer(audio_class->hport, setup, g_audio_buf); + if (ret < 0) { + return ret; + } + audio_class->as_msg_table[intf - audio_class->ctrl_intf - 1].mute = mute; + return ret; +} + +void usbh_audio_list_module(struct usbh_audio *audio_class) +{ + USB_LOG_INFO("============= Audio module information ===================\r\n"); + USB_LOG_RAW("bcdADC :%04x\r\n", audio_class->bcdADC); + USB_LOG_RAW("Num of audio stream :%u\r\n", audio_class->stream_intf_num); + + for (uint8_t i = 0; i < audio_class->stream_intf_num; i++) { + USB_LOG_RAW("\tstream name :%s\r\n", audio_class->as_msg_table[i].stream_name); + USB_LOG_RAW("\tstream intf :%u\r\n", audio_class->as_msg_table[i].stream_intf); + USB_LOG_RAW("\tNum of altsetting :%u\r\n", audio_class->as_msg_table[i].num_of_altsetting); + + for (uint8_t j = 0; j < audio_class->as_msg_table[i].num_of_altsetting; j++) { + if (j == 0) { + USB_LOG_RAW("\t\tIngore altsetting 0\r\n"); + continue; + } + USB_LOG_RAW("\t\tAltsetting :%u\r\n", j); + USB_LOG_RAW("\t\t\tbNrChannels :%u\r\n", audio_class->as_msg_table[i].as_format[j].bNrChannels); + USB_LOG_RAW("\t\t\tbBitResolution :%u\r\n", audio_class->as_msg_table[i].as_format[j].bBitResolution); + USB_LOG_RAW("\t\t\tbSamFreqType :%u\r\n", audio_class->as_msg_table[i].as_format[j].bSamFreqType); + + for (uint8_t k = 0; k < audio_class->as_msg_table[i].as_format[j].bSamFreqType; k++) { + uint32_t freq = 0; + + memcpy(&freq, &audio_class->as_msg_table[i].as_format[j].tSamFreq[3 * k], 3); + USB_LOG_RAW("\t\t\t\tSampleFreq :%u\r\n", freq); + } + } + } + + USB_LOG_INFO("============= Audio module information ===================\r\n"); +} + +static int usbh_audio_ctrl_connect(struct usbh_hubport *hport, uint8_t intf) +{ + int ret; + uint8_t cur_iface = 0; + uint8_t cur_iface_count = 0; + uint8_t cur_alt_setting = 0; + uint8_t input_offset = 0; + uint8_t output_offset = 0; + uint8_t feature_unit_offset = 0; + uint8_t *p; + struct usbh_audio_ac_msg ac_msg_table[CONFIG_USBHOST_AUDIO_MAX_STREAMS]; + + struct usbh_audio *audio_class = usbh_audio_class_alloc(); + if (audio_class == NULL) { + USB_LOG_ERR("Fail to alloc audio_class\r\n"); + return -USB_ERR_NOMEM; + } + + audio_class->hport = hport; + audio_class->ctrl_intf = intf; + hport->config.intf[intf].priv = audio_class; + + p = hport->raw_config_desc; + while (p[DESC_bLength]) { + switch (p[DESC_bDescriptorType]) { + case USB_DESCRIPTOR_TYPE_INTERFACE_ASSOCIATION: + cur_iface_count = p[3]; + USB_ASSERT(cur_iface_count <= CONFIG_USBHOST_AUDIO_MAX_STREAMS); + break; + case USB_DESCRIPTOR_TYPE_INTERFACE: + cur_iface = p[INTF_DESC_bInterfaceNumber]; + cur_alt_setting = p[INTF_DESC_bAlternateSetting]; + break; + case USB_DESCRIPTOR_TYPE_ENDPOINT: + break; + case AUDIO_INTERFACE_DESCRIPTOR_TYPE: + if (cur_iface == audio_class->ctrl_intf) { + switch (p[DESC_bDescriptorSubType]) { + case AUDIO_CONTROL_HEADER: { + struct audio_cs_if_ac_header_descriptor *desc = (struct audio_cs_if_ac_header_descriptor *)p; + audio_class->bcdADC = desc->bcdADC; + audio_class->bInCollection = desc->bInCollection; + } break; + case AUDIO_CONTROL_INPUT_TERMINAL: { + struct audio_cs_if_ac_input_terminal_descriptor *desc = (struct audio_cs_if_ac_input_terminal_descriptor *)p; + + USB_ASSERT(input_offset < CONFIG_USBHOST_AUDIO_MAX_STREAMS); + + memcpy(&ac_msg_table[input_offset].ac_input, desc, sizeof(struct audio_cs_if_ac_input_terminal_descriptor)); + input_offset++; + } break; + case AUDIO_CONTROL_OUTPUT_TERMINAL: { + struct audio_cs_if_ac_output_terminal_descriptor *desc = (struct audio_cs_if_ac_output_terminal_descriptor *)p; + + USB_ASSERT(output_offset < CONFIG_USBHOST_AUDIO_MAX_STREAMS); + + memcpy(&ac_msg_table[output_offset].ac_output, desc, sizeof(struct audio_cs_if_ac_output_terminal_descriptor)); + output_offset++; + } break; + case AUDIO_CONTROL_FEATURE_UNIT: { + struct audio_cs_if_ac_feature_unit_descriptor *desc = (struct audio_cs_if_ac_feature_unit_descriptor *)p; + + USB_ASSERT(feature_unit_offset < CONFIG_USBHOST_AUDIO_MAX_STREAMS); + USB_ASSERT(desc->bControlSize == 1); + USB_ASSERT(desc->bLength <= sizeof(struct audio_cs_if_ac_feature_unit_descriptor)); + + memcpy(&ac_msg_table[feature_unit_offset].ac_feature_unit, desc, desc->bLength); + feature_unit_offset++; + } break; + default: + USB_LOG_ERR("Do not support %02x subtype\r\n", p[DESC_bDescriptorSubType]); + return -USB_ERR_NOTSUPP; + } + } else if ((cur_iface > audio_class->ctrl_intf) && (cur_iface < (audio_class->ctrl_intf + cur_iface_count))) { + switch (p[DESC_bDescriptorSubType]) { + case AUDIO_STREAMING_GENERAL: { + struct audio_cs_if_as_general_descriptor *desc = (struct audio_cs_if_as_general_descriptor *)p; + + /* all altsetting have the same general */ + audio_class->as_msg_table[cur_iface - audio_class->ctrl_intf - 1].stream_intf = cur_iface; + memcpy(&audio_class->as_msg_table[cur_iface - audio_class->ctrl_intf - 1].as_general, desc, sizeof(struct audio_cs_if_as_general_descriptor)); + } break; + case AUDIO_STREAMING_FORMAT_TYPE: { + struct audio_cs_if_as_format_type_descriptor *desc = (struct audio_cs_if_as_format_type_descriptor *)p; + + USB_ASSERT(desc->bSamFreqType == 1); + + audio_class->as_msg_table[cur_iface - audio_class->ctrl_intf - 1].num_of_altsetting = (cur_alt_setting + 1); + memcpy(&audio_class->as_msg_table[cur_iface - audio_class->ctrl_intf - 1].as_format[cur_alt_setting], desc, desc->bLength); + } break; + default: + break; + } + } + break; + case AUDIO_ENDPOINT_DESCRIPTOR_TYPE: + if ((cur_iface > audio_class->ctrl_intf) && (cur_iface < (audio_class->ctrl_intf + cur_iface_count))) { + if (p[DESC_bDescriptorSubType] == AUDIO_ENDPOINT_GENERAL) { + struct audio_cs_ep_ep_general_descriptor *desc = (struct audio_cs_ep_ep_general_descriptor *)p; + + audio_class->as_msg_table[cur_iface - audio_class->ctrl_intf - 1].ep_attr = desc->bmAttributes; + } + } + break; + default: + break; + } + /* skip to next descriptor */ + p += p[DESC_bLength]; + } + + if ((input_offset != output_offset) && (input_offset != feature_unit_offset)) { + USB_LOG_ERR("Audio control descriptor is invalid\r\n"); + return -USB_ERR_INVAL; + } + + if (cur_iface_count == 0xff) { + USB_LOG_ERR("Audio descriptor must have iad descriptor\r\n"); + return -USB_ERR_INVAL; + } + + audio_class->stream_intf_num = input_offset; + + for (uint8_t i = 0; i < audio_class->stream_intf_num; i++) { + /* Search 0x0101 in input or output desc */ + for (uint8_t streamidx = 0; streamidx < audio_class->stream_intf_num; streamidx++) { + if (audio_class->as_msg_table[i].as_general.bTerminalLink == ac_msg_table[streamidx].ac_input.bTerminalID) { + /* INPUT --> FEATURE UNIT --> OUTPUT */ + audio_class->as_msg_table[i].input_terminal_id = ac_msg_table[streamidx].ac_input.bTerminalID; + + /* Search input terminal id in feature desc */ + for (uint8_t featureidx = 0; featureidx < audio_class->stream_intf_num; featureidx++) { + if (ac_msg_table[streamidx].ac_input.bTerminalID == ac_msg_table[featureidx].ac_feature_unit.bSourceID) { + audio_class->as_msg_table[i].feature_terminal_id = ac_msg_table[featureidx].ac_feature_unit.bUnitID; + + /* Search feature unit id in output desc */ + for (uint8_t outputid = 0; outputid < audio_class->stream_intf_num; outputid++) { + if (ac_msg_table[featureidx].ac_feature_unit.bUnitID == ac_msg_table[outputid].ac_output.bSourceID) { + audio_class->as_msg_table[i].output_terminal_id = ac_msg_table[outputid].ac_output.bTerminalID; + + switch (ac_msg_table[outputid].ac_output.wTerminalType) { + case AUDIO_OUTTERM_SPEAKER: + audio_class->as_msg_table[i].stream_name = "speaker"; + break; + case AUDIO_OUTTERM_HEADPHONES: + audio_class->as_msg_table[i].stream_name = "headphoens"; + break; + case AUDIO_OUTTERM_HEADDISPLAY: + audio_class->as_msg_table[i].stream_name = "headdisplay"; + break; + default: + audio_class->as_msg_table[i].stream_name = "unknown"; + break; + } + break; + } + } + break; + } + } + } else if (audio_class->as_msg_table[i].as_general.bTerminalLink == ac_msg_table[streamidx].ac_output.bTerminalID) { + /* OUTPUT --> FEATURE UNIT --> INPUT */ + audio_class->as_msg_table[i].output_terminal_id = ac_msg_table[streamidx].ac_output.bTerminalID; + + /* Search output terminal id in feature desc */ + for (uint8_t featureidx = 0; featureidx < audio_class->stream_intf_num; featureidx++) { + if (ac_msg_table[streamidx].ac_output.bSourceID == ac_msg_table[featureidx].ac_feature_unit.bUnitID) { + audio_class->as_msg_table[i].feature_terminal_id = ac_msg_table[featureidx].ac_feature_unit.bUnitID; + + /* Search feature unit id in input desc */ + for (uint8_t inputid = 0; inputid < audio_class->stream_intf_num; inputid++) { + if (ac_msg_table[featureidx].ac_feature_unit.bSourceID == ac_msg_table[inputid].ac_input.bTerminalID) { + audio_class->as_msg_table[i].input_terminal_id = ac_msg_table[inputid].ac_input.bTerminalID; + + switch (ac_msg_table[inputid].ac_input.wTerminalType) { + case AUDIO_INTERM_MIC: + audio_class->as_msg_table[i].stream_name = "mic"; + break; + default: + audio_class->as_msg_table[i].stream_name = "unknown"; + break; + } + break; + } + } + break; + } + } + } + } + } + + for (uint8_t i = 0; i < audio_class->stream_intf_num; i++) { + if (audio_class->as_msg_table[i].stream_name == NULL) { + USB_LOG_ERR("Audio stream search fail\r\n"); + return -USB_ERR_NODEV; + } + } + + for (uint8_t i = 0; i < audio_class->stream_intf_num; i++) { + ret = usbh_audio_close(audio_class, audio_class->as_msg_table[i].stream_name); + if (ret < 0) { + USB_LOG_ERR("Fail to close audio stream :%s\r\n", audio_class->as_msg_table[i].stream_name); + return ret; + } + } + + usbh_audio_list_module(audio_class); + + snprintf(hport->config.intf[intf].devname, CONFIG_USBHOST_DEV_NAMELEN, DEV_FORMAT, audio_class->minor); + USB_LOG_INFO("Register Audio Class:%s\r\n", hport->config.intf[intf].devname); + + usbh_audio_run(audio_class); + return 0; +} + +static int usbh_audio_ctrl_disconnect(struct usbh_hubport *hport, uint8_t intf) +{ + int ret = 0; + + struct usbh_audio *audio_class = (struct usbh_audio *)hport->config.intf[intf].priv; + + if (audio_class) { + if (audio_class->isoin) { + } + + if (audio_class->isoout) { + } + + if (hport->config.intf[intf].devname[0] != '\0') { + usb_osal_thread_schedule_other(); + USB_LOG_INFO("Unregister Audio Class:%s\r\n", hport->config.intf[intf].devname); + usbh_audio_stop(audio_class); + } + + usbh_audio_class_free(audio_class); + } + + return ret; +} + +static int usbh_audio_data_connect(struct usbh_hubport *hport, uint8_t intf) +{ + (void)hport; + (void)intf; + return 0; +} + +static int usbh_audio_data_disconnect(struct usbh_hubport *hport, uint8_t intf) +{ + (void)hport; + (void)intf; + return 0; +} + +__WEAK void usbh_audio_run(struct usbh_audio *audio_class) +{ + (void)audio_class; +} + +__WEAK void usbh_audio_stop(struct usbh_audio *audio_class) +{ + (void)audio_class; +} + +const struct usbh_class_driver audio_ctrl_class_driver = { + .driver_name = "audio_ctrl", + .connect = usbh_audio_ctrl_connect, + .disconnect = usbh_audio_ctrl_disconnect +}; + +const struct usbh_class_driver audio_streaming_class_driver = { + .driver_name = "audio_streaming", + .connect = usbh_audio_data_connect, + .disconnect = usbh_audio_data_disconnect +}; + +CLASS_INFO_DEFINE const struct usbh_class_info audio_ctrl_intf_class_info = { + .match_flags = USB_CLASS_MATCH_INTF_CLASS | USB_CLASS_MATCH_INTF_SUBCLASS, + .bInterfaceClass = USB_DEVICE_CLASS_AUDIO, + .bInterfaceSubClass = AUDIO_SUBCLASS_AUDIOCONTROL, + .bInterfaceProtocol = 0x00, + .id_table = NULL, + .class_driver = &audio_ctrl_class_driver +}; + +CLASS_INFO_DEFINE const struct usbh_class_info audio_streaming_intf_class_info = { + .match_flags = USB_CLASS_MATCH_INTF_CLASS | USB_CLASS_MATCH_INTF_SUBCLASS, + .bInterfaceClass = USB_DEVICE_CLASS_AUDIO, + .bInterfaceSubClass = AUDIO_SUBCLASS_AUDIOSTREAMING, + .bInterfaceProtocol = 0x00, + .id_table = NULL, + .class_driver = &audio_streaming_class_driver +}; diff --git a/kernel/cherryusb/class/audio/usbh_audio.h b/kernel/cherryusb/class/audio/usbh_audio.h new file mode 100644 index 0000000..2e583ac --- /dev/null +++ b/kernel/cherryusb/class/audio/usbh_audio.h @@ -0,0 +1,72 @@ +/* + * Copyright (c) 2022, sakumisu + * + * SPDX-License-Identifier: Apache-2.0 + */ +#ifndef USBH_AUDIO_H +#define USBH_AUDIO_H + +#include "usb_audio.h" + +#ifndef CONFIG_USBHOST_AUDIO_MAX_STREAMS +#define CONFIG_USBHOST_AUDIO_MAX_STREAMS 3 +#endif + +struct usbh_audio_ac_msg { + struct audio_cs_if_ac_input_terminal_descriptor ac_input; + struct audio_cs_if_ac_feature_unit_descriptor ac_feature_unit; + struct audio_cs_if_ac_output_terminal_descriptor ac_output; +}; + +struct usbh_audio_as_msg { + const char *stream_name; + uint8_t stream_intf; + uint8_t input_terminal_id; + uint8_t feature_terminal_id; + uint8_t output_terminal_id; + uint8_t ep_attr; + uint8_t num_of_altsetting; + uint16_t volume_min; + uint16_t volume_max; + uint16_t volume_res; + uint16_t volume_cur; + bool mute; + struct audio_cs_if_as_general_descriptor as_general; + struct audio_cs_if_as_format_type_descriptor as_format[CONFIG_USBHOST_MAX_INTF_ALTSETTINGS]; +}; + +struct usbh_audio { + struct usbh_hubport *hport; + struct usb_endpoint_descriptor *isoin; /* ISO IN endpoint */ + struct usb_endpoint_descriptor *isoout; /* ISO OUT endpoint */ + + uint8_t ctrl_intf; /* interface number */ + uint8_t minor; + uint16_t isoin_mps; + uint16_t isoout_mps; + bool is_opened; + uint16_t bcdADC; + uint8_t bInCollection; + uint8_t stream_intf_num; + struct usbh_audio_as_msg as_msg_table[CONFIG_USBHOST_AUDIO_MAX_STREAMS]; + + void *user_data; +}; + +#ifdef __cplusplus +extern "C" { +#endif + +int usbh_audio_open(struct usbh_audio *audio_class, const char *name, uint32_t samp_freq, uint8_t bitresolution); +int usbh_audio_close(struct usbh_audio *audio_class, const char *name); +int usbh_audio_set_volume(struct usbh_audio *audio_class, const char *name, uint8_t ch, int volume_db); +int usbh_audio_set_mute(struct usbh_audio *audio_class, const char *name, uint8_t ch, bool mute); + +void usbh_audio_run(struct usbh_audio *audio_class); +void usbh_audio_stop(struct usbh_audio *audio_class); + +#ifdef __cplusplus +} +#endif + +#endif /* USBH_AUDIO_H */ diff --git a/kernel/cherryusb/class/cdc/usb_cdc.h b/kernel/cherryusb/class/cdc/usb_cdc.h new file mode 100644 index 0000000..a21bc3b --- /dev/null +++ b/kernel/cherryusb/class/cdc/usb_cdc.h @@ -0,0 +1,714 @@ +/* + * Copyright (c) 2022, sakumisu + * + * SPDX-License-Identifier: Apache-2.0 + */ +#ifndef USB_CDC_H +#define USB_CDC_H + +/*------------------------------------------------------------------------------ + * Definitions based on usbcdc11.pdf (www.usb.org) + *----------------------------------------------------------------------------*/ +/* Communication device class specification version 1.10 */ +#define CDC_V1_10 0x0110U +// Communication device class specification version 1.2 +#define CDC_V1_2_0 0x0120U + +/* Communication interface class code */ +/* (usbcdc11.pdf, 4.2, Table 15) */ +#define CDC_COMMUNICATION_INTERFACE_CLASS 0x02U + +/* Communication interface class subclass codes */ +/* (usbcdc11.pdf, 4.3, Table 16) */ +#define CDC_SUBCLASS_NONE 0x00 /* Reserved */ +#define CDC_SUBCLASS_DLC 0x01 /* Direct Line Control Model */ +#define CDC_SUBCLASS_ACM 0x02 /* Abstract Control Model */ +#define CDC_SUBCLASS_TCM 0x03 /* Telephone Control Model */ +#define CDC_SUBCLASS_MCM 0x04 /* Multi-Channel Control Model */ +#define CDC_SUBCLASS_CAPI 0x05 /* CAPI Control Model */ +#define CDC_SUBCLASS_ECM 0x06 /* Ethernet Networking Control Model */ +#define CDC_SUBCLASS_ATM 0x07 /* ATM Networking Control Model */ + /* 0x08-0x0d Reserved (future use) */ +#define CDC_SUBCLASS_MBIM 0x0e /* MBIM Control Model */ + /* 0x0f-0x7f Reserved (future use) */ + /* 0x80-0xfe Reserved (vendor specific) */ + +#define CDC_DIRECT_LINE_CONTROL_MODEL 0x01U +#define CDC_ABSTRACT_CONTROL_MODEL 0x02U +#define CDC_TELEPHONE_CONTROL_MODEL 0x03U +#define CDC_MULTI_CHANNEL_CONTROL_MODEL 0x04U +#define CDC_CAPI_CONTROL_MODEL 0x05U +#define CDC_ETHERNET_NETWORKING_CONTROL_MODEL 0x06U +#define CDC_ATM_NETWORKING_CONTROL_MODEL 0x07U +#define CDC_WIRELESS_HANDSET_CONTROL_MODEL 0x08U +#define CDC_DEVICE_MANAGEMENT 0x09U +#define CDC_MOBILE_DIRECT_LINE_MODEL 0x0AU +#define CDC_OBEX 0x0BU +#define CDC_ETHERNET_EMULATION_MODEL 0x0CU +#define CDC_NETWORK_CONTROL_MODEL 0x0DU + +/* Communication interface class control protocol codes */ +/* (usbcdc11.pdf, 4.4, Table 17) */ +#define CDC_COMMON_PROTOCOL_NONE 0x00U +#define CDC_COMMON_PROTOCOL_AT_COMMANDS 0x01U +#define CDC_COMMON_PROTOCOL_AT_COMMANDS_PCCA_101 0x02U +#define CDC_COMMON_PROTOCOL_AT_COMMANDS_PCCA_101_AND_ANNEXO 0x03U +#define CDC_COMMON_PROTOCOL_AT_COMMANDS_GSM_707 0x04U +#define CDC_COMMON_PROTOCOL_AT_COMMANDS_3GPP_27007 0x05U +#define CDC_COMMON_PROTOCOL_AT_COMMANDS_CDMA 0x06U +#define CDC_COMMON_PROTOCOL_ETHERNET_EMULATION_MODEL 0x07U +// NCM Communication Interface Protocol Codes +// (usbncm10.pdf, 4.2, Table 4-2) +#define CDC_NCM_PROTOCOL_NONE 0x00U +#define CDC_NCM_PROTOCOL_OEM 0xFEU + +/* Data interface class code */ +/* (usbcdc11.pdf, 4.5, Table 18) */ +#define CDC_DATA_INTERFACE_CLASS 0x0A + +/* Data Interface Sub-Class Codes ********************************************/ +#define CDC_DATA_SUBCLASS_NONE 0x00 + +/* Data interface class protocol codes */ +/* (usbcdc11.pdf, 4.7, Table 19) */ +#define CDC_DATA_PROTOCOL_ISDN_BRI 0x30 +#define CDC_DATA_PROTOCOL_HDLC 0x31 +#define CDC_DATA_PROTOCOL_TRANSPARENT 0x32 +#define CDC_DATA_PROTOCOL_Q921_MANAGEMENT 0x50 +#define CDC_DATA_PROTOCOL_Q921_DATA_LINK 0x51 +#define CDC_DATA_PROTOCOL_Q921_MULTIPLEXOR 0x52 +#define CDC_DATA_PROTOCOL_V42 0x90 +#define CDC_DATA_PROTOCOL_EURO_ISDN 0x91 +#define CDC_DATA_PROTOCOL_V24_RATE_ADAPTATION 0x92 +#define CDC_DATA_PROTOCOL_CAPI 0x93 +#define CDC_DATA_PROTOCOL_HOST_BASED_DRIVER 0xFD +#define CDC_DATA_PROTOCOL_DESCRIBED_IN_PUFD 0xFE + +/* Type values for bDescriptorType field of functional descriptors */ +/* (usbcdc11.pdf, 5.2.3, Table 24) */ +#define CDC_CS_INTERFACE 0x24 +#define CDC_CS_ENDPOINT 0x25 + +/* Type values for bDescriptorSubtype field of functional descriptors */ +/* (usbcdc11.pdf, 5.2.3, Table 25) */ +#define CDC_FUNC_DESC_HEADER 0x00 +#define CDC_FUNC_DESC_CALL_MANAGEMENT 0x01 +#define CDC_FUNC_DESC_ABSTRACT_CONTROL_MANAGEMENT 0x02 +#define CDC_FUNC_DESC_DIRECT_LINE_MANAGEMENT 0x03 +#define CDC_FUNC_DESC_TELEPHONE_RINGER 0x04 +#define CDC_FUNC_DESC_REPORTING_CAPABILITIES 0x05 +#define CDC_FUNC_DESC_UNION 0x06 +#define CDC_FUNC_DESC_COUNTRY_SELECTION 0x07 +#define CDC_FUNC_DESC_TELEPHONE_OPERATIONAL_MODES 0x08 +#define CDC_FUNC_DESC_USB_TERMINAL 0x09 +#define CDC_FUNC_DESC_NETWORK_CHANNEL 0x0A +#define CDC_FUNC_DESC_PROTOCOL_UNIT 0x0B +#define CDC_FUNC_DESC_EXTENSION_UNIT 0x0C +#define CDC_FUNC_DESC_MULTI_CHANNEL_MANAGEMENT 0x0D +#define CDC_FUNC_DESC_CAPI_CONTROL_MANAGEMENT 0x0E +#define CDC_FUNC_DESC_ETHERNET_NETWORKING 0x0F +#define CDC_FUNC_DESC_ATM_NETWORKING 0x10 +#define CDC_FUNC_DESC_WIRELESS_HANDSET_CONTROL_MODEL 0x11 +#define CDC_FUNC_DESC_MOBILE_DIRECT_LINE_MODEL 0x12 +#define CDC_FUNC_DESC_MOBILE_DIRECT_LINE_MODEL_DETAIL 0x13 +#define CDC_FUNC_DESC_DEVICE_MANAGEMENT_MODEL 0x14 +#define CDC_FUNC_DESC_OBEX 0x15 +#define CDC_FUNC_DESC_COMMAND_SET 0x16 +#define CDC_FUNC_DESC_COMMAND_SET_DETAIL 0x17 +#define CDC_FUNC_DESC_TELEPHONE_CONTROL_MODEL 0x18 +#define CDC_FUNC_DESC_OBEX_SERVICE_IDENTIFIER 0x19 +#define CDC_FUNC_DESC_NCM 0x1A + +/* CDC class-specific request codes */ +/* (usbcdc11.pdf, 6.2, Table 46) */ +/* see Table 45 for info about the specific requests. */ +#define CDC_REQUEST_SEND_ENCAPSULATED_COMMAND 0x00 +#define CDC_REQUEST_GET_ENCAPSULATED_RESPONSE 0x01 +#define CDC_REQUEST_SET_COMM_FEATURE 0x02 +#define CDC_REQUEST_GET_COMM_FEATURE 0x03 +#define CDC_REQUEST_CLEAR_COMM_FEATURE 0x04 +#define CDC_REQUEST_SET_AUX_LINE_STATE 0x10 +#define CDC_REQUEST_SET_HOOK_STATE 0x11 +#define CDC_REQUEST_PULSE_SETUP 0x12 +#define CDC_REQUEST_SEND_PULSE 0x13 +#define CDC_REQUEST_SET_PULSE_TIME 0x14 +#define CDC_REQUEST_RING_AUX_JACK 0x15 +#define CDC_REQUEST_SET_LINE_CODING 0x20 +#define CDC_REQUEST_GET_LINE_CODING 0x21 +#define CDC_REQUEST_SET_CONTROL_LINE_STATE 0x22 +#define CDC_REQUEST_SEND_BREAK 0x23 +#define CDC_REQUEST_SET_RINGER_PARMS 0x30 +#define CDC_REQUEST_GET_RINGER_PARMS 0x31 +#define CDC_REQUEST_SET_OPERATION_PARMS 0x32 +#define CDC_REQUEST_GET_OPERATION_PARMS 0x33 +#define CDC_REQUEST_SET_LINE_PARMS 0x34 +#define CDC_REQUEST_GET_LINE_PARMS 0x35 +#define CDC_REQUEST_DIAL_DIGITS 0x36 +#define CDC_REQUEST_SET_UNIT_PARAMETER 0x37 +#define CDC_REQUEST_GET_UNIT_PARAMETER 0x38 +#define CDC_REQUEST_CLEAR_UNIT_PARAMETER 0x39 +#define CDC_REQUEST_GET_PROFILE 0x3A +#define CDC_REQUEST_SET_ETHERNET_MULTICAST_FILTERS 0x40 +#define CDC_REQUEST_SET_ETHERNET_PMP_FILTER 0x41 +#define CDC_REQUEST_GET_ETHERNET_PMP_FILTER 0x42 +#define CDC_REQUEST_SET_ETHERNET_PACKET_FILTER 0x43 +#define CDC_REQUEST_GET_ETHERNET_STATISTIC 0x44 +#define CDC_REQUEST_SET_ATM_DATA_FORMAT 0x50 +#define CDC_REQUEST_GET_ATM_DEVICE_STATISTICS 0x51 +#define CDC_REQUEST_SET_ATM_DEFAULT_VC 0x52 +#define CDC_REQUEST_GET_ATM_VC_STATISTICS 0x53 +#define CDC_REQUEST_GET_NTB_PARAMETERS 0x80 +#define CDC_REQUEST_GET_NET_ADDRESS 0x81 +#define CDC_REQUEST_SET_NET_ADDRESS 0x82 +#define CDC_REQUEST_GET_NTB_FORMAT 0x83 +#define CDC_REQUEST_SET_NTB_FORMAT 0x84 +#define CDC_REQUEST_GET_NTB_INPUT_SIZE 0x85 +#define CDC_REQUEST_SET_NTB_INPUT_SIZE 0x86 +#define CDC_REQUEST_GET_MAX_DATAGRAM_SIZE 0x87 +#define CDC_REQUEST_SET_MAX_DATAGRAM_SIZE 0x88 +#define CDC_REQUEST_GET_CRC_MODE 0x89 +#define CDC_REQUEST_SET_CRC_MODE 0x90 + +/* Communication feature selector codes */ +/* (usbcdc11.pdf, 6.2.2..6.2.4, Table 47) */ +#define CDC_ABSTRACT_STATE 0x01 +#define CDC_COUNTRY_SETTING 0x02 + +/** Control Signal Bitmap Values for SetControlLineState */ +#define SET_CONTROL_LINE_STATE_RTS 0x02 +#define SET_CONTROL_LINE_STATE_DTR 0x01 + +/* Feature Status returned for ABSTRACT_STATE Selector */ +/* (usbcdc11.pdf, 6.2.3, Table 48) */ +#define CDC_IDLE_SETTING (1 << 0) +#define CDC_DATA_MULTPLEXED_STATE (1 << 1) + +/* Control signal bitmap values for the SetControlLineState request */ +/* (usbcdc11.pdf, 6.2.14, Table 51) */ +#define CDC_DTE_PRESENT (1 << 0) +#define CDC_ACTIVATE_CARRIER (1 << 1) + +/* CDC class-specific notification codes */ +/* (usbcdc11.pdf, 6.3, Table 68) */ +/* see Table 67 for Info about class-specific notifications */ +#define CDC_NOTIFICATION_NETWORK_CONNECTION 0x00 +#define CDC_RESPONSE_AVAILABLE 0x01 +#define CDC_AUX_JACK_HOOK_STATE 0x08 +#define CDC_RING_DETECT 0x09 +#define CDC_NOTIFICATION_SERIAL_STATE 0x20 +#define CDC_CALL_STATE_CHANGE 0x28 +#define CDC_LINE_STATE_CHANGE 0x29 +#define CDC_CONNECTION_SPEED_CHANGE 0x2A + +/* UART state bitmap values (Serial state notification). */ +/* (usbcdc11.pdf, 6.3.5, Table 69) */ +#define CDC_SERIAL_STATE_OVERRUN (1 << 6) /* receive data overrun error has occurred */ +#define CDC_SERIAL_STATE_OVERRUN_Pos (6) +#define CDC_SERIAL_STATE_OVERRUN_Msk (1 << CDC_SERIAL_STATE_OVERRUN_Pos) +#define CDC_SERIAL_STATE_PARITY (1 << 5) /* parity error has occurred */ +#define CDC_SERIAL_STATE_PARITY_Pos (5) +#define CDC_SERIAL_STATE_PARITY_Msk (1 << CDC_SERIAL_STATE_PARITY_Pos) +#define CDC_SERIAL_STATE_FRAMING (1 << 4) /* framing error has occurred */ +#define CDC_SERIAL_STATE_FRAMING_Pos (4) +#define CDC_SERIAL_STATE_FRAMING_Msk (1 << CDC_SERIAL_STATE_FRAMING_Pos) +#define CDC_SERIAL_STATE_RING (1 << 3) /* state of ring signal detection */ +#define CDC_SERIAL_STATE_RING_Pos (3) +#define CDC_SERIAL_STATE_RING_Msk (1 << CDC_SERIAL_STATE_RING_Pos) +#define CDC_SERIAL_STATE_BREAK (1 << 2) /* state of break detection */ +#define CDC_SERIAL_STATE_BREAK_Pos (2) +#define CDC_SERIAL_STATE_BREAK_Msk (1 << CDC_SERIAL_STATE_BREAK_Pos) +#define CDC_SERIAL_STATE_DSR (1 << 1) /* state of transmission carrier */ +#define CDC_SERIAL_STATE_DSR_Pos (1) +#define CDC_SERIAL_STATE_DSR_Msk (1 << CDC_SERIAL_STATE_DSR_Pos) +#define CDC_SERIAL_STATE_DCD (1 << 0) /* state of receiver carrier */ +#define CDC_SERIAL_STATE_DCD_Pos (0) +#define CDC_SERIAL_STATE_DCD_Msk (1 << CDC_SERIAL_STATE_DCD_Pos) + +#define CDC_ECM_XMIT_OK (1 << 0) +#define CDC_ECM_RVC_OK (1 << 1) +#define CDC_ECM_XMIT_ERROR (1 << 2) +#define CDC_ECM_RCV_ERROR (1 << 3) +#define CDC_ECM_RCV_NO_BUFFER (1 << 4) +#define CDC_ECM_DIRECTED_BYTES_XMIT (1 << 5) +#define CDC_ECM_DIRECTED_FRAMES_XMIT (1 << 6) +#define CDC_ECM_MULTICAST_BYTES_XMIT (1 << 7) +#define CDC_ECM_MULTICAST_FRAMES_XMIT (1 << 8) +#define CDC_ECM_BROADCAST_BYTES_XMIT (1 << 9) +#define CDC_ECM_BROADCAST_FRAMES_XMIT (1 << 10) +#define CDC_ECM_DIRECTED_BYTES_RCV (1 << 11) +#define CDC_ECM_DIRECTED_FRAMES_RCV (1 << 12) +#define CDC_ECM_MULTICAST_BYTES_RCV (1 << 13) +#define CDC_ECM_MULTICAST_FRAMES_RCV (1 << 14) +#define CDC_ECM_BROADCAST_BYTES_RCV (1 << 15) +#define CDC_ECM_BROADCAST_FRAMES_RCV (1 << 16) +#define CDC_ECM_RCV_CRC_ERROR (1 << 17) +#define CDC_ECM_TRANSMIT_QUEUE_LENGTH (1 << 18) +#define CDC_ECM_RCV_ERROR_ALIGNMENT (1 << 19) +#define CDC_ECM_XMIT_ONE_COLLISION (1 << 20) +#define CDC_ECM_XMIT_MORE_COLLISIONS (1 << 21) +#define CDC_ECM_XMIT_DEFERRED (1 << 22) +#define CDC_ECM_XMIT_MAX_COLLISIONS (1 << 23) +#define CDC_ECM_RCV_OVERRUN (1 << 24) +#define CDC_ECM_XMIT_UNDERRUN (1 << 25) +#define CDC_ECM_XMIT_HEARTBEAT_FAILURE (1 << 26) +#define CDC_ECM_XMIT_TIMES_CRS_LOST (1 << 27) +#define CDC_ECM_XMIT_LATE_COLLISIONS (1 << 28) + +#define CDC_ECM_MAC_STR_DESC (uint8_t *)"010202030000" +#define CDC_ECM_MAC_ADDR0 0x00U /* 01 */ +#define CDC_ECM_MAC_ADDR1 0x02U /* 02 */ +#define CDC_ECM_MAC_ADDR2 0x02U /* 03 */ +#define CDC_ECM_MAC_ADDR3 0x03U /* 00 */ +#define CDC_ECM_MAC_ADDR4 0x00U /* 00 */ +#define CDC_ECM_MAC_ADDR5 0x00U /* 00 */ + +#define CDC_ECM_NET_DISCONNECTED 0x00U +#define CDC_ECM_NET_CONNECTED 0x01U + +#define CDC_ECM_ETH_STATS_RESERVED 0xE0U +#define CDC_ECM_BMREQUEST_TYPE_ECM 0xA1U + +#define CDC_ECM_CONNECT_SPEED_UPSTREAM 0x004C4B40U /* 5Mbps */ +#define CDC_ECM_CONNECT_SPEED_DOWNSTREAM 0x004C4B40U /* 5Mbps */ + +#define CDC_ECM_NOTIFY_CODE_NETWORK_CONNECTION 0x00 +#define CDC_ECM_NOTIFY_CODE_RESPONSE_AVAILABLE 0x01 +#define CDC_ECM_NOTIFY_CODE_CONNECTION_SPEED_CHANGE 0x2A + +#define CDC_NCM_NTH16_SIGNATURE 0x484D434E +#define CDC_NCM_NDP16_SIGNATURE_NCM0 0x304D434E +#define CDC_NCM_NDP16_SIGNATURE_NCM1 0x314D434E + +/*------------------------------------------------------------------------------ + * Structures based on usbcdc11.pdf (www.usb.org) + *----------------------------------------------------------------------------*/ + +/* Header functional descriptor */ +/* (usbcdc11.pdf, 5.2.3.1) */ +/* This header must precede any list of class-specific descriptors. */ +struct cdc_header_descriptor { + uint8_t bFunctionLength; /* size of this descriptor in bytes */ + uint8_t bDescriptorType; /* CS_INTERFACE descriptor type */ + uint8_t bDescriptorSubtype; /* Header functional descriptor subtype */ + uint16_t bcdCDC; /* USB CDC specification release version */ +} __PACKED; + +/* Call management functional descriptor */ +/* (usbcdc11.pdf, 5.2.3.2) */ +/* Describes the processing of calls for the communication class interface. */ +struct cdc_call_management_descriptor { + uint8_t bFunctionLength; /* size of this descriptor in bytes */ + uint8_t bDescriptorType; /* CS_INTERFACE descriptor type */ + uint8_t bDescriptorSubtype; /* call management functional descriptor subtype */ + uint8_t bmCapabilities; /* capabilities that this configuration supports */ + uint8_t bDataInterface; /* interface number of the data class interface used for call management (optional) */ +} __PACKED; + +/* Abstract control management functional descriptor */ +/* (usbcdc11.pdf, 5.2.3.3) */ +/* Describes the command supported by the communication interface class with the Abstract Control Model subclass code. */ +struct cdc_abstract_control_management_descriptor { + uint8_t bFunctionLength; /* size of this descriptor in bytes */ + uint8_t bDescriptorType; /* CS_INTERFACE descriptor type */ + uint8_t bDescriptorSubtype; /* abstract control management functional descriptor subtype */ + uint8_t bmCapabilities; /* capabilities supported by this configuration */ +} __PACKED; + +/* Union functional descriptors */ +/* (usbcdc11.pdf, 5.2.3.8) */ +/* Describes the relationship between a group of interfaces that can be considered to form a functional unit. */ +struct cdc_union_descriptor { + uint8_t bFunctionLength; /* size of this descriptor in bytes */ + uint8_t bDescriptorType; /* CS_INTERFACE descriptor type */ + uint8_t bDescriptorSubtype; /* union functional descriptor subtype */ + uint8_t bMasterInterface; /* interface number designated as master */ +} __PACKED; + +/* Union functional descriptors with one slave interface */ +/* (usbcdc11.pdf, 5.2.3.8) */ +struct cdc_union_1slave_descriptor { + uint8_t bFunctionLength; + uint8_t bDescriptorType; + uint8_t bDescriptorSubtype; + uint8_t bControlInterface; + uint8_t bSubordinateInterface0; +} __PACKED; + +/* Line coding structure for GET_LINE_CODING / SET_LINE_CODING class requests*/ +/* Format of the data returned when a GetLineCoding request is received */ +/* (usbcdc11.pdf, 6.2.13) */ +struct cdc_line_coding { + uint32_t dwDTERate; /* Data terminal rate in bits per second */ + uint8_t bCharFormat; /* Number of stop bits */ + uint8_t bParityType; /* Parity bit type */ + uint8_t bDataBits; /* Number of data bits */ +} __PACKED; + +/** Data structure for the notification about SerialState */ +struct cdc_acm_notification { + uint8_t bmRequestType; + uint8_t bNotificationType; + uint16_t wValue; + uint16_t wIndex; + uint16_t wLength; + uint16_t data; +} __PACKED; + +/** Ethernet Networking Functional Descriptor */ +struct cdc_eth_descriptor { + uint8_t bFunctionLength; + uint8_t bDescriptorType; + uint8_t bDescriptorSubtype; + uint8_t iMACAddress; + uint32_t bmEthernetStatistics; + uint16_t wMaxSegmentSize; + uint16_t wNumberMCFilters; + uint8_t bNumberPowerFilters; +} __PACKED; + +struct cdc_eth_notification { + uint8_t bmRequestType; + uint8_t bNotificationType; + uint16_t wValue; + uint16_t wIndex; + uint16_t wLength; + uint8_t data[8]; +} __PACKED; + +struct cdc_ncm_ntb_parameters { + uint16_t wLength; + uint16_t bmNtbFormatsSupported; + uint32_t dwNtbInMaxSize; + uint16_t wNdbInDivisor; + uint16_t wNdbInPayloadRemainder; + uint16_t wNdbInAlignment; + uint16_t wReserved; + uint32_t dwNtbOutMaxSize; + uint16_t wNdbOutDivisor; + uint16_t wNdbOutPayloadRemainder; + uint16_t wNdbOutAlignment; + uint16_t wNtbOutMaxDatagrams; +}; + +struct cdc_ncm_nth16 { + uint32_t dwSignature; + uint16_t wHeaderLength; + uint16_t wSequence; + uint16_t wBlockLength; + uint16_t wNdpIndex; +}; + +struct cdc_ncm_ndp16_datagram { + uint16_t wDatagramIndex; + uint16_t wDatagramLength; +}; + +struct cdc_ncm_ndp16 { + uint32_t dwSignature; + uint16_t wLength; + uint16_t wNextNdpIndex; + struct cdc_ncm_ndp16_datagram datagram[]; +}; + +/*Length of template descriptor: 66 bytes*/ +#define CDC_ACM_DESCRIPTOR_LEN (8 + 9 + 5 + 5 + 4 + 5 + 7 + 9 + 7 + 7) +// clang-format off +#define CDC_ACM_DESCRIPTOR_INIT(bFirstInterface, int_ep, out_ep, in_ep, wMaxPacketSize, str_idx) \ + /* Interface Associate */ \ + 0x08, /* bLength */ \ + USB_DESCRIPTOR_TYPE_INTERFACE_ASSOCIATION, /* bDescriptorType */ \ + bFirstInterface, /* bFirstInterface */ \ + 0x02, /* bInterfaceCount */ \ + USB_DEVICE_CLASS_CDC, /* bFunctionClass */ \ + CDC_ABSTRACT_CONTROL_MODEL, /* bFunctionSubClass */ \ + CDC_COMMON_PROTOCOL_NONE, /* bFunctionProtocol */ \ + 0x00, /* iFunction */ \ + 0x09, /* bLength */ \ + USB_DESCRIPTOR_TYPE_INTERFACE, /* bDescriptorType */ \ + bFirstInterface, /* bInterfaceNumber */ \ + 0x00, /* bAlternateSetting */ \ + 0x01, /* bNumEndpoints */ \ + USB_DEVICE_CLASS_CDC, /* bInterfaceClass */ \ + CDC_ABSTRACT_CONTROL_MODEL, /* bInterfaceSubClass */ \ + CDC_COMMON_PROTOCOL_NONE, /* bInterfaceProtocol */ \ + str_idx, /* iInterface */ \ + 0x05, /* bLength */ \ + CDC_CS_INTERFACE, /* bDescriptorType */ \ + CDC_FUNC_DESC_HEADER, /* bDescriptorSubtype */ \ + WBVAL(CDC_V1_10), /* bcdCDC */ \ + 0x05, /* bLength */ \ + CDC_CS_INTERFACE, /* bDescriptorType */ \ + CDC_FUNC_DESC_CALL_MANAGEMENT, /* bDescriptorSubtype */ \ + 0x00, /* bmCapabilities */ \ + (uint8_t)(bFirstInterface + 1), /* bDataInterface */ \ + 0x04, /* bLength */ \ + CDC_CS_INTERFACE, /* bDescriptorType */ \ + CDC_FUNC_DESC_ABSTRACT_CONTROL_MANAGEMENT, /* bDescriptorSubtype */ \ + 0x02, /* bmCapabilities */ \ + 0x05, /* bLength */ \ + CDC_CS_INTERFACE, /* bDescriptorType */ \ + CDC_FUNC_DESC_UNION, /* bDescriptorSubtype */ \ + bFirstInterface, /* bMasterInterface */ \ + (uint8_t)(bFirstInterface + 1), /* bSlaveInterface0 */ \ + 0x07, /* bLength */ \ + USB_DESCRIPTOR_TYPE_ENDPOINT, /* bDescriptorType */ \ + int_ep, /* bEndpointAddress */ \ + 0x03, /* bmAttributes */ \ + 0x08, 0x00, /* wMaxPacketSize */ \ + 0x0a, /* bInterval */ \ + 0x09, /* bLength */ \ + USB_DESCRIPTOR_TYPE_INTERFACE, /* bDescriptorType */ \ + (uint8_t)(bFirstInterface + 1), /* bInterfaceNumber */ \ + 0x00, /* bAlternateSetting */ \ + 0x02, /* bNumEndpoints */ \ + CDC_DATA_INTERFACE_CLASS, /* bInterfaceClass */ \ + 0x00, /* bInterfaceSubClass */ \ + 0x00, /* bInterfaceProtocol */ \ + 0x00, /* iInterface */ \ + 0x07, /* bLength */ \ + USB_DESCRIPTOR_TYPE_ENDPOINT, /* bDescriptorType */ \ + out_ep, /* bEndpointAddress */ \ + 0x02, /* bmAttributes */ \ + WBVAL(wMaxPacketSize), /* wMaxPacketSize */ \ + 0x00, /* bInterval */ \ + 0x07, /* bLength */ \ + USB_DESCRIPTOR_TYPE_ENDPOINT, /* bDescriptorType */ \ + in_ep, /* bEndpointAddress */ \ + 0x02, /* bmAttributes */ \ + WBVAL(wMaxPacketSize), /* wMaxPacketSize */ \ + 0x00 /* bInterval */ +// clang-format on + +/*Length of template descriptor: 66 bytes*/ +#define CDC_RNDIS_DESCRIPTOR_LEN (8 + 9 + 5 + 5 + 4 + 5 + 7 + 9 + 7 + 7) +// clang-format off +#define CDC_RNDIS_DESCRIPTOR_INIT(bFirstInterface, int_ep, out_ep, in_ep, wMaxPacketSize, str_idx) \ + /* Interface Associate */ \ + 0x08, /* bLength */ \ + USB_DESCRIPTOR_TYPE_INTERFACE_ASSOCIATION, /* bDescriptorType */ \ + bFirstInterface, /* bFirstInterface */ \ + 0x02, /* bInterfaceCount */ \ + USB_DEVICE_CLASS_WIRELESS, /* bFunctionClass */ \ + 0x01, /* bFunctionSubClass */ \ + 0x03, /* bFunctionProtocol */ \ + 0x00, /* iFunction */ \ + 0x09, /* bLength */ \ + USB_DESCRIPTOR_TYPE_INTERFACE, /* bDescriptorType */ \ + bFirstInterface, /* bInterfaceNumber */ \ + 0x00, /* bAlternateSetting */ \ + 0x01, /* bNumEndpoints */ \ + USB_DEVICE_CLASS_WIRELESS, /* bInterfaceClass */ \ + 0x01, /* bInterfaceSubClass */ \ + 0x03, /* bInterfaceProtocol */ \ + str_idx, /* iInterface */ \ + 0x05, /* bLength */ \ + CDC_CS_INTERFACE, /* bDescriptorType */ \ + CDC_FUNC_DESC_HEADER, /* bDescriptorSubtype */ \ + WBVAL(CDC_V1_10), /* bcdCDC */ \ + 0x05, /* bLength */ \ + CDC_CS_INTERFACE, /* bDescriptorType */ \ + CDC_FUNC_DESC_CALL_MANAGEMENT, /* bDescriptorSubtype */ \ + 0x00, /* bmCapabilities */ \ + (uint8_t)(bFirstInterface + 1), /* bDataInterface */ \ + 0x04, /* bLength */ \ + CDC_CS_INTERFACE, /* bDescriptorType */ \ + CDC_FUNC_DESC_ABSTRACT_CONTROL_MANAGEMENT, /* bDescriptorSubtype */ \ + 0x00, /* bmCapabilities */ \ + 0x05, /* bLength */ \ + CDC_CS_INTERFACE, /* bDescriptorType */ \ + CDC_FUNC_DESC_UNION, /* bDescriptorSubtype */ \ + bFirstInterface, /* bMasterInterface */ \ + (uint8_t)(bFirstInterface + 1), /* bSlaveInterface0 */ \ + 0x07, /* bLength */ \ + USB_DESCRIPTOR_TYPE_ENDPOINT, /* bDescriptorType */ \ + int_ep, /* bEndpointAddress */ \ + 0x03, /* bmAttributes */ \ + 0x08, 0x00, /* wMaxPacketSize */ \ + 0x05, /* bInterval */ \ + 0x09, /* bLength */ \ + USB_DESCRIPTOR_TYPE_INTERFACE, /* bDescriptorType */ \ + (uint8_t)(bFirstInterface + 1), /* bInterfaceNumber */ \ + 0x00, /* bAlternateSetting */ \ + 0x02, /* bNumEndpoints */ \ + CDC_DATA_INTERFACE_CLASS, /* bInterfaceClass */ \ + 0x00, /* bInterfaceSubClass */ \ + 0x00, /* bInterfaceProtocol */ \ + 0x00, /* iInterface */ \ + 0x07, /* bLength */ \ + USB_DESCRIPTOR_TYPE_ENDPOINT, /* bDescriptorType */ \ + out_ep, /* bEndpointAddress */ \ + 0x02, /* bmAttributes */ \ + WBVAL(wMaxPacketSize), /* wMaxPacketSize */ \ + 0x00, /* bInterval */ \ + 0x07, /* bLength */ \ + USB_DESCRIPTOR_TYPE_ENDPOINT, /* bDescriptorType */ \ + in_ep, /* bEndpointAddress */ \ + 0x02, /* bmAttributes */ \ + WBVAL(wMaxPacketSize), /* wMaxPacketSize */ \ + 0x00 /* bInterval */ +// clang-format on + +#define DBVAL_BE(x) ((x >> 24) & 0xFF), ((x >> 16) & 0xFF), ((x >> 8) & 0xFF), (x & 0xFF) + +/*Length of template descriptor: 79 bytes*/ +#define CDC_ECM_DESCRIPTOR_LEN (8 + 9 + 5 + 5 + 13 + 7 + 9 + 9 + 7 + 7) +// clang-format off +#define CDC_ECM_DESCRIPTOR_INIT(bFirstInterface, int_ep, out_ep, in_ep, wMaxPacketSize, str_idx) \ + /* Interface Associate */ \ + 0x08, /* bLength */ \ + USB_DESCRIPTOR_TYPE_INTERFACE_ASSOCIATION, /* bDescriptorType */ \ + bFirstInterface, /* bFirstInterface */ \ + 0x02, /* bInterfaceCount */ \ + USB_DEVICE_CLASS_CDC, /* bFunctionClass */ \ + CDC_ETHERNET_NETWORKING_CONTROL_MODEL, /* bFunctionSubClass */ \ + CDC_COMMON_PROTOCOL_NONE, /* bFunctionProtocol */ \ + 0x00, /* iFunction */ \ + 0x09, /* bLength */ \ + USB_DESCRIPTOR_TYPE_INTERFACE, /* bDescriptorType */ \ + bFirstInterface, /* bInterfaceNumber */ \ + 0x00, /* bAlternateSetting */ \ + 0x01, /* bNumEndpoints */ \ + USB_DEVICE_CLASS_CDC, /* bInterfaceClass */ \ + CDC_ETHERNET_NETWORKING_CONTROL_MODEL, /* bInterfaceSubClass */ \ + CDC_COMMON_PROTOCOL_NONE, /* bInterfaceProtocol */ \ + str_idx, /* iInterface */ \ + 0x05, /* bLength */ \ + CDC_CS_INTERFACE, /* bDescriptorType */ \ + CDC_FUNC_DESC_HEADER, /* bDescriptorSubtype */ \ + WBVAL(CDC_V1_10), /* bcdCDC */ \ + 0x05, /* bLength */ \ + CDC_CS_INTERFACE, /* bDescriptorType */ \ + CDC_FUNC_DESC_UNION, /* bDescriptorSubtype */ \ + bFirstInterface, /* bMasterInterface */ \ + (uint8_t)(bFirstInterface + 1), /* bSlaveInterface0 */ \ + /* CDC_ECM Functional Descriptor */ \ + 0x0D, /* bFunctionLength */\ + CDC_CS_INTERFACE, /* bDescriptorType: CS_INTERFACE */\ + CDC_FUNC_DESC_ETHERNET_NETWORKING, /* Ethernet Networking functional descriptor subtype */\ + str_idx, /* Device's MAC string index */\ + DBVAL_BE(0x00000000), /* Ethernet statistics (bitmap) */\ + WBVAL(1514), /* wMaxSegmentSize: Ethernet Maximum Segment size, typically 1514 bytes */\ + WBVAL(0), /* wNumberMCFilters: the number of multicast filters */ \ + 0, /* bNumberPowerFilters: the number of wakeup power filters */ \ + 0x07, /* bLength */ \ + USB_DESCRIPTOR_TYPE_ENDPOINT, /* bDescriptorType */ \ + int_ep, /* bEndpointAddress */ \ + 0x03, /* bmAttributes */ \ + 0x10, 0x00, /* wMaxPacketSize */ \ + 0x05, /* bInterval */ \ + 0x09, /* bLength */ \ + USB_DESCRIPTOR_TYPE_INTERFACE, /* bDescriptorType */ \ + (uint8_t)(bFirstInterface + 1), /* bInterfaceNumber */ \ + 0x00, /* bAlternateSetting */ \ + 0x00, /* bNumEndpoints */ \ + CDC_DATA_INTERFACE_CLASS, /* bInterfaceClass */ \ + 0x00, /* bInterfaceSubClass */ \ + 0x00, /* bInterfaceProtocol */ \ + 0x00, /* iInterface */ \ + 0x09, /* bLength */ \ + USB_DESCRIPTOR_TYPE_INTERFACE, /* bDescriptorType */ \ + (uint8_t)(bFirstInterface + 1), /* bInterfaceNumber */ \ + 0x01, /* bAlternateSetting */ \ + 0x02, /* bNumEndpoints */ \ + CDC_DATA_INTERFACE_CLASS, /* bInterfaceClass */ \ + 0x00, /* bInterfaceSubClass */ \ + 0x00, /* bInterfaceProtocol */ \ + 0x00, /* iInterface */ \ + 0x07, /* bLength */ \ + USB_DESCRIPTOR_TYPE_ENDPOINT, /* bDescriptorType */ \ + out_ep, /* bEndpointAddress */ \ + 0x02, /* bmAttributes */ \ + WBVAL(wMaxPacketSize), /* wMaxPacketSize */ \ + 0x00, /* bInterval */ \ + 0x07, /* bLength */ \ + USB_DESCRIPTOR_TYPE_ENDPOINT, /* bDescriptorType */ \ + in_ep, /* bEndpointAddress */ \ + 0x02, /* bmAttributes */ \ + WBVAL(wMaxPacketSize), /* wMaxPacketSize */ \ + 0x00 /* bInterval */ +// clang-format on + +/*Length of template descriptor: 86 bytes*/ +#define CDC_NCM_DESCRIPTOR_LEN (8 + 9 + 5 + 5 + 13 + 6 + 7 + 9 + 9 + 7 + 7) +// clang-format off +#define CDC_NCM_DESCRIPTOR_INIT(bFirstInterface, int_ep, out_ep, in_ep, wMaxPacketSize, str_idx) \ + /* Interface Associate */ \ + 0x08, /* bLength */ \ + USB_DESCRIPTOR_TYPE_INTERFACE_ASSOCIATION, /* bDescriptorType */ \ + bFirstInterface, /* bFirstInterface */ \ + 0x02, /* bInterfaceCount */ \ + USB_DEVICE_CLASS_CDC, /* bFunctionClass */ \ + CDC_NETWORK_CONTROL_MODEL, /* bFunctionSubClass */ \ + CDC_COMMON_PROTOCOL_NONE, /* bFunctionProtocol */ \ + 0x00, /* iFunction */ \ + 0x09, /* bLength */ \ + USB_DESCRIPTOR_TYPE_INTERFACE, /* bDescriptorType */ \ + bFirstInterface, /* bInterfaceNumber */ \ + 0x00, /* bAlternateSetting */ \ + 0x01, /* bNumEndpoints */ \ + USB_DEVICE_CLASS_CDC, /* bInterfaceClass */ \ + CDC_NETWORK_CONTROL_MODEL, /* bInterfaceSubClass */ \ + CDC_COMMON_PROTOCOL_NONE, /* bInterfaceProtocol */ \ + str_idx, /* iInterface */ \ + 0x05, /* bLength */ \ + CDC_CS_INTERFACE, /* bDescriptorType */ \ + CDC_FUNC_DESC_HEADER, /* bDescriptorSubtype */ \ + WBVAL(CDC_V1_10), /* bcdCDC */ \ + 0x05, /* bLength */ \ + CDC_CS_INTERFACE, /* bDescriptorType */ \ + CDC_FUNC_DESC_UNION, /* bDescriptorSubtype */ \ + bFirstInterface, /* bMasterInterface */ \ + (uint8_t)(bFirstInterface + 1), /* bSlaveInterface0 */ \ + /* CDC ETH Functional Descriptor */ \ + 0x0D, /* bFunctionLength */\ + CDC_CS_INTERFACE, /* bDescriptorType: CS_INTERFACE */\ + CDC_FUNC_DESC_ETHERNET_NETWORKING, /* Ethernet Networking functional descriptor subtype */\ + str_idx, /* Device's MAC string index */\ + DBVAL_BE(0x00000000), /* Ethernet statistics (bitmap) */\ + WBVAL(1514), /* wMaxSegmentSize: Ethernet Maximum Segment size, typically 1514 bytes */\ + WBVAL(0), /* wNumberMCFilters: the number of multicast filters */ \ + 0, /* bNumberPowerFilters: the number of wakeup power filters */ \ + 0x06, \ + CDC_CS_INTERFACE, \ + CDC_FUNC_DESC_NCM, \ + 0x00, 0x01, \ + 0x23, \ + 0x07, /* bLength */ \ + USB_DESCRIPTOR_TYPE_ENDPOINT, /* bDescriptorType */ \ + int_ep, /* bEndpointAddress */ \ + 0x03, /* bmAttributes */ \ + 0x10, 0x00, /* wMaxPacketSize */ \ + 0x10, /* bInterval */ \ + 0x09, /* bLength */ \ + USB_DESCRIPTOR_TYPE_INTERFACE, /* bDescriptorType */ \ + (uint8_t)(bFirstInterface + 1), /* bInterfaceNumber */ \ + 0x00, /* bAlternateSetting */ \ + 0x00, /* bNumEndpoints */ \ + CDC_DATA_INTERFACE_CLASS, /* bInterfaceClass */ \ + 0x00, /* bInterfaceSubClass */ \ + 0x00, /* bInterfaceProtocol */ \ + 0x00, /* iInterface */ \ + 0x09, /* bLength */ \ + USB_DESCRIPTOR_TYPE_INTERFACE, /* bDescriptorType */ \ + (uint8_t)(bFirstInterface + 1), /* bInterfaceNumber */ \ + 0x01, /* bAlternateSetting */ \ + 0x02, /* bNumEndpoints */ \ + CDC_DATA_INTERFACE_CLASS, /* bInterfaceClass */ \ + 0x00, /* bInterfaceSubClass */ \ + 0x00, /* bInterfaceProtocol */ \ + 0x00, /* iInterface */ \ + 0x07, /* bLength */ \ + USB_DESCRIPTOR_TYPE_ENDPOINT, /* bDescriptorType */ \ + out_ep, /* bEndpointAddress */ \ + 0x02, /* bmAttributes */ \ + WBVAL(wMaxPacketSize), /* wMaxPacketSize */ \ + 0x00, /* bInterval */ \ + 0x07, /* bLength */ \ + USB_DESCRIPTOR_TYPE_ENDPOINT, /* bDescriptorType */ \ + in_ep, /* bEndpointAddress */ \ + 0x02, /* bmAttributes */ \ + WBVAL(wMaxPacketSize), /* wMaxPacketSize */ \ + 0x00 /* bInterval */ +// clang-format on + +#endif /* USB_CDC_H */ diff --git a/kernel/cherryusb/class/cdc/usbd_cdc.h b/kernel/cherryusb/class/cdc/usbd_cdc.h new file mode 100644 index 0000000..2cf3df1 --- /dev/null +++ b/kernel/cherryusb/class/cdc/usbd_cdc.h @@ -0,0 +1,13 @@ +/* + * Copyright (c) 2024, sakumisu + * + * SPDX-License-Identifier: Apache-2.0 + */ +#ifndef USBD_CDC_H +#define USBD_CDC_H + +// legacy for old version + +#include "usbd_cdc_acm.h" + +#endif \ No newline at end of file diff --git a/kernel/cherryusb/class/cdc/usbd_cdc_acm.c b/kernel/cherryusb/class/cdc/usbd_cdc_acm.c new file mode 100644 index 0000000..0c911c6 --- /dev/null +++ b/kernel/cherryusb/class/cdc/usbd_cdc_acm.c @@ -0,0 +1,133 @@ +/* + * Copyright (c) 2022, sakumisu + * + * SPDX-License-Identifier: Apache-2.0 + */ +#include "usbd_core.h" +#include "usbd_cdc_acm.h" + +const char *stop_name[] = { "1", "1.5", "2" }; +const char *parity_name[] = { "N", "O", "E", "M", "S" }; + +static int cdc_acm_class_interface_request_handler(uint8_t busid, struct usb_setup_packet *setup, uint8_t **data, uint32_t *len) +{ + USB_LOG_DBG("CDC Class request: " + "bRequest 0x%02x\r\n", + setup->bRequest); + + struct cdc_line_coding line_coding; + bool dtr, rts; + uint8_t intf_num = LO_BYTE(setup->wIndex); + + switch (setup->bRequest) { + case CDC_REQUEST_SET_LINE_CODING: + + /*******************************************************************************/ + /* Line Coding Structure */ + /*-----------------------------------------------------------------------------*/ + /* Offset | Field | Size | Value | Description */ + /* 0 | dwDTERate | 4 | Number |Data terminal rate, in bits per second*/ + /* 4 | bCharFormat | 1 | Number | Stop bits */ + /* 0 - 1 Stop bit */ + /* 1 - 1.5 Stop bits */ + /* 2 - 2 Stop bits */ + /* 5 | bParityType | 1 | Number | Parity */ + /* 0 - None */ + /* 1 - Odd */ + /* 2 - Even */ + /* 3 - Mark */ + /* 4 - Space */ + /* 6 | bDataBits | 1 | Number Data bits (5, 6, 7, 8 or 16). */ + /*******************************************************************************/ + memcpy(&line_coding, *data, 7); + USB_LOG_DBG("Set intf:%d linecoding <%d %d %s %s>\r\n", + intf_num, + (unsigned int)line_coding.dwDTERate, + line_coding.bDataBits, + parity_name[line_coding.bParityType], + stop_name[line_coding.bCharFormat]); + + usbd_cdc_acm_set_line_coding(busid, intf_num, &line_coding); + break; + + case CDC_REQUEST_SET_CONTROL_LINE_STATE: + dtr = (setup->wValue & 0x0001); + rts = (setup->wValue & 0x0002); + USB_LOG_DBG("Set intf:%d DTR 0x%x,RTS 0x%x\r\n", + intf_num, + dtr, + rts); + usbd_cdc_acm_set_dtr(busid, intf_num, dtr); + usbd_cdc_acm_set_rts(busid, intf_num, rts); + break; + + case CDC_REQUEST_GET_LINE_CODING: + usbd_cdc_acm_get_line_coding(busid, intf_num, &line_coding); + memcpy(*data, &line_coding, 7); + *len = 7; + USB_LOG_DBG("Get intf:%d linecoding %d %d %d %d\r\n", + intf_num, + (unsigned int)line_coding.dwDTERate, + line_coding.bCharFormat, + line_coding.bParityType, + line_coding.bDataBits); + break; + case CDC_REQUEST_SEND_BREAK: + usbd_cdc_acm_send_break(busid, intf_num); + break; + default: + return -1; + } + + return 0; +} + +struct usbd_interface *usbd_cdc_acm_init_intf(uint8_t busid, struct usbd_interface *intf) +{ + (void)busid; + + intf->class_interface_handler = cdc_acm_class_interface_request_handler; + intf->class_endpoint_handler = NULL; + intf->vendor_handler = NULL; + intf->notify_handler = NULL; + + return intf; +} + +__WEAK void usbd_cdc_acm_set_line_coding(uint8_t busid, uint8_t intf, struct cdc_line_coding *line_coding) +{ + (void)busid; + (void)intf; + (void)line_coding; +} + +__WEAK void usbd_cdc_acm_get_line_coding(uint8_t busid, uint8_t intf, struct cdc_line_coding *line_coding) +{ + (void)busid; + (void)intf; + + line_coding->dwDTERate = 2000000; + line_coding->bDataBits = 8; + line_coding->bParityType = 0; + line_coding->bCharFormat = 0; +} + +__WEAK void usbd_cdc_acm_set_dtr(uint8_t busid, uint8_t intf, bool dtr) +{ + (void)busid; + (void)intf; + (void)dtr; +} + +__WEAK void usbd_cdc_acm_set_rts(uint8_t busid, uint8_t intf, bool rts) +{ + (void)busid; + (void)intf; + (void)rts; +} + +__WEAK void usbd_cdc_acm_send_break(uint8_t busid, uint8_t intf) +{ + (void)busid; + (void)intf; +} diff --git a/kernel/cherryusb/class/cdc/usbd_cdc_acm.h b/kernel/cherryusb/class/cdc/usbd_cdc_acm.h new file mode 100644 index 0000000..662c238 --- /dev/null +++ b/kernel/cherryusb/class/cdc/usbd_cdc_acm.h @@ -0,0 +1,29 @@ +/* + * Copyright (c) 2022, sakumisu + * + * SPDX-License-Identifier: Apache-2.0 + */ +#ifndef USBD_CDC_ACM_H +#define USBD_CDC_ACM_H + +#include "usb_cdc.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* Init cdc acm interface driver */ +struct usbd_interface *usbd_cdc_acm_init_intf(uint8_t busid, struct usbd_interface *intf); + +/* Setup request command callback api */ +void usbd_cdc_acm_set_line_coding(uint8_t busid, uint8_t intf, struct cdc_line_coding *line_coding); +void usbd_cdc_acm_get_line_coding(uint8_t busid, uint8_t intf, struct cdc_line_coding *line_coding); +void usbd_cdc_acm_set_dtr(uint8_t busid, uint8_t intf, bool dtr); +void usbd_cdc_acm_set_rts(uint8_t busid, uint8_t intf, bool rts); +void usbd_cdc_acm_send_break(uint8_t busid, uint8_t intf); + +#ifdef __cplusplus +} +#endif + +#endif /* USBD_CDC_ACM_H */ diff --git a/kernel/cherryusb/class/cdc/usbd_cdc_ecm.c b/kernel/cherryusb/class/cdc/usbd_cdc_ecm.c new file mode 100644 index 0000000..dde4090 --- /dev/null +++ b/kernel/cherryusb/class/cdc/usbd_cdc_ecm.c @@ -0,0 +1,293 @@ +/* + * Copyright (c) 2023, sakumisu + * + * SPDX-License-Identifier: Apache-2.0 + */ +#include "usbd_core.h" +#include "usbd_cdc_ecm.h" + +#define CDC_ECM_OUT_EP_IDX 0 +#define CDC_ECM_IN_EP_IDX 1 +#define CDC_ECM_INT_EP_IDX 2 + +/* Ethernet Maximum Segment size, typically 1514 bytes */ +#define CONFIG_CDC_ECM_ETH_MAX_SEGSZE 1536U + +/* Describe EndPoints configuration */ +static struct usbd_endpoint cdc_ecm_ep_data[3]; + +#ifdef CONFIG_USBDEV_CDC_ECM_USING_LWIP +static USB_NOCACHE_RAM_SECTION USB_MEM_ALIGNX uint8_t g_cdc_ecm_rx_buffer[USB_ALIGN_UP(CONFIG_CDC_ECM_ETH_MAX_SEGSZE, CONFIG_USB_ALIGN_SIZE)]; +static USB_NOCACHE_RAM_SECTION USB_MEM_ALIGNX uint8_t g_cdc_ecm_tx_buffer[USB_ALIGN_UP(CONFIG_CDC_ECM_ETH_MAX_SEGSZE, CONFIG_USB_ALIGN_SIZE)]; +#endif +static USB_NOCACHE_RAM_SECTION USB_MEM_ALIGNX uint8_t g_cdc_ecm_notify_buf[USB_ALIGN_UP(16, CONFIG_USB_ALIGN_SIZE)]; + +volatile uint32_t g_cdc_ecm_rx_data_length = 0; +volatile uint32_t g_cdc_ecm_tx_data_length = 0; + +static volatile uint8_t g_current_net_status = 0; +static volatile uint8_t g_cmd_intf = 0; + +static uint32_t g_connect_speed_table[2] = { CDC_ECM_CONNECT_SPEED_UPSTREAM, + CDC_ECM_CONNECT_SPEED_DOWNSTREAM }; + +void usbd_cdc_ecm_send_notify(uint8_t notifycode, uint8_t value, uint32_t *speed) +{ + struct cdc_eth_notification *notify = (struct cdc_eth_notification *)g_cdc_ecm_notify_buf; + uint8_t bytes2send = 0; + + notify->bmRequestType = CDC_ECM_BMREQUEST_TYPE_ECM; + notify->bNotificationType = notifycode; + + switch (notifycode) { + case CDC_ECM_NOTIFY_CODE_NETWORK_CONNECTION: + notify->wValue = value; + notify->wIndex = g_cmd_intf; + notify->wLength = 0U; + + for (uint8_t i = 0U; i < 8U; i++) { + notify->data[i] = 0U; + } + bytes2send = 8U; + break; + case CDC_ECM_NOTIFY_CODE_RESPONSE_AVAILABLE: + notify->wValue = 0U; + notify->wIndex = g_cmd_intf; + notify->wLength = 0U; + for (uint8_t i = 0U; i < 8U; i++) { + notify->data[i] = 0U; + } + bytes2send = 8U; + break; + case CDC_ECM_NOTIFY_CODE_CONNECTION_SPEED_CHANGE: + notify->wValue = 0U; + notify->wIndex = g_cmd_intf; + notify->wLength = 0x0008U; + bytes2send = 16U; + + memcpy(notify->data, speed, 8); + break; + + default: + break; + } + + if (usb_device_is_configured(0)) { + if (bytes2send) { + usbd_ep_start_write(0, cdc_ecm_ep_data[CDC_ECM_INT_EP_IDX].ep_addr, g_cdc_ecm_notify_buf, bytes2send); + } + } +} + +static int cdc_ecm_class_interface_request_handler(uint8_t busid, struct usb_setup_packet *setup, uint8_t **data, uint32_t *len) +{ + USB_LOG_DBG("CDC ECM Class request: " + "bRequest 0x%02x\r\n", + setup->bRequest); + + (void)busid; + (void)data; + (void)len; + + g_cmd_intf = LO_BYTE(setup->wIndex); + + switch (setup->bRequest) { + case CDC_REQUEST_SET_ETHERNET_PACKET_FILTER: + /* bit0 Promiscuous + * bit1 ALL Multicast + * bit2 Directed + * bit3 Broadcast + * bit4 Multicast + */ +#ifdef CONFIG_USBDEV_CDC_ECM_USING_LWIP + g_connect_speed_table[0] = 100000000; /* 100 Mbps */ + g_connect_speed_table[1] = 100000000; /* 100 Mbps */ + usbd_cdc_ecm_set_connect(true, g_connect_speed_table); +#endif + break; + default: + return -1; + } + + return 0; +} + +void cdc_ecm_notify_handler(uint8_t busid, uint8_t event, void *arg) +{ + (void)busid; + (void)arg; + + switch (event) { + case USBD_EVENT_RESET: + g_current_net_status = 0; + g_cdc_ecm_rx_data_length = 0; + g_cdc_ecm_tx_data_length = 0; + break; + case USBD_EVENT_CONFIGURED: +#ifdef CONFIG_USBDEV_CDC_ECM_USING_LWIP + usbd_cdc_ecm_start_read(g_cdc_ecm_rx_buffer, CONFIG_CDC_ECM_ETH_MAX_SEGSZE); +#endif + break; + + default: + break; + } +} + +void cdc_ecm_bulk_out(uint8_t busid, uint8_t ep, uint32_t nbytes) +{ + (void)busid; + + g_cdc_ecm_rx_data_length = nbytes; + usbd_cdc_ecm_data_recv_done(g_cdc_ecm_rx_data_length); +} + +void cdc_ecm_bulk_in(uint8_t busid, uint8_t ep, uint32_t nbytes) +{ + (void)busid; + + if ((nbytes % usbd_get_ep_mps(0, ep)) == 0 && nbytes) { + /* send zlp */ + usbd_ep_start_write(0, ep, NULL, 0); + } else { + usbd_cdc_ecm_data_send_done(g_cdc_ecm_tx_data_length); + g_cdc_ecm_tx_data_length = 0; + } +} + +void cdc_ecm_int_in(uint8_t busid, uint8_t ep, uint32_t nbytes) +{ + (void)busid; + (void)ep; + (void)nbytes; + + if (g_current_net_status == 2) { + g_current_net_status = 3; + usbd_cdc_ecm_send_notify(CDC_ECM_NOTIFY_CODE_CONNECTION_SPEED_CHANGE, 0, g_connect_speed_table); + } else { + g_current_net_status = 0; + } +} + +int usbd_cdc_ecm_start_write(uint8_t *buf, uint32_t len) +{ + if (!usb_device_is_configured(0)) { + return -USB_ERR_NOTCONN; + } + + if (g_cdc_ecm_tx_data_length > 0) { + return -USB_ERR_BUSY; + } + + g_cdc_ecm_tx_data_length = len; + + USB_LOG_DBG("txlen:%d\r\n", g_cdc_ecm_tx_data_length); + return usbd_ep_start_write(0, cdc_ecm_ep_data[CDC_ECM_IN_EP_IDX].ep_addr, buf, len); +} + +int usbd_cdc_ecm_start_read(uint8_t *buf, uint32_t len) +{ + if (!usb_device_is_configured(0)) { + return -USB_ERR_NOTCONN; + } + + g_cdc_ecm_rx_data_length = 0; + return usbd_ep_start_read(0, cdc_ecm_ep_data[CDC_ECM_OUT_EP_IDX].ep_addr, buf, len); +} + +#ifdef CONFIG_USBDEV_CDC_ECM_USING_LWIP +struct pbuf *usbd_cdc_ecm_eth_rx(void) +{ + struct pbuf *p; + + if (g_cdc_ecm_rx_data_length == 0) { + return NULL; + } + p = pbuf_alloc(PBUF_RAW, g_cdc_ecm_rx_data_length, PBUF_POOL); + if (p == NULL) { + usbd_cdc_ecm_start_read(g_cdc_ecm_rx_buffer, CONFIG_CDC_ECM_ETH_MAX_SEGSZE); + return NULL; + } + usb_memcpy(p->payload, (uint8_t *)g_cdc_ecm_rx_buffer, g_cdc_ecm_rx_data_length); + p->len = g_cdc_ecm_rx_data_length; + + USB_LOG_DBG("rxlen:%d\r\n", g_cdc_ecm_rx_data_length); + usbd_cdc_ecm_start_read(g_cdc_ecm_rx_buffer, CONFIG_CDC_ECM_ETH_MAX_SEGSZE); + return p; +} + +int usbd_cdc_ecm_eth_tx(struct pbuf *p) +{ + struct pbuf *q; + uint8_t *buffer; + + if (!usb_device_is_configured(0)) { + return -USB_ERR_NOTCONN; + } + + if (g_cdc_ecm_tx_data_length > 0) { + return -USB_ERR_BUSY; + } + + if (p->tot_len > sizeof(g_cdc_ecm_tx_buffer)) { + p->tot_len = sizeof(g_cdc_ecm_tx_buffer); + } + + buffer = g_cdc_ecm_tx_buffer; + for (q = p; q != NULL; q = q->next) { + usb_memcpy(buffer, q->payload, q->len); + buffer += q->len; + } + + return usbd_cdc_ecm_start_write(g_cdc_ecm_tx_buffer, p->tot_len); +} +#endif + +struct usbd_interface *usbd_cdc_ecm_init_intf(struct usbd_interface *intf, const uint8_t int_ep, const uint8_t out_ep, const uint8_t in_ep) +{ + intf->class_interface_handler = cdc_ecm_class_interface_request_handler; + intf->class_endpoint_handler = NULL; + intf->vendor_handler = NULL; + intf->notify_handler = cdc_ecm_notify_handler; + + cdc_ecm_ep_data[CDC_ECM_OUT_EP_IDX].ep_addr = out_ep; + cdc_ecm_ep_data[CDC_ECM_OUT_EP_IDX].ep_cb = cdc_ecm_bulk_out; + cdc_ecm_ep_data[CDC_ECM_IN_EP_IDX].ep_addr = in_ep; + cdc_ecm_ep_data[CDC_ECM_IN_EP_IDX].ep_cb = cdc_ecm_bulk_in; + cdc_ecm_ep_data[CDC_ECM_INT_EP_IDX].ep_addr = int_ep; + cdc_ecm_ep_data[CDC_ECM_INT_EP_IDX].ep_cb = cdc_ecm_int_in; + + usbd_add_endpoint(0, &cdc_ecm_ep_data[CDC_ECM_OUT_EP_IDX]); + usbd_add_endpoint(0, &cdc_ecm_ep_data[CDC_ECM_IN_EP_IDX]); + usbd_add_endpoint(0, &cdc_ecm_ep_data[CDC_ECM_INT_EP_IDX]); + + return intf; +} + +int usbd_cdc_ecm_set_connect(bool connect, uint32_t speed[2]) +{ + if (!usb_device_is_configured(0)) { + return -USB_ERR_NOTCONN; + } + + if (connect) { + g_current_net_status = 2; + memcpy(g_connect_speed_table, speed, 8); + usbd_cdc_ecm_send_notify(CDC_ECM_NOTIFY_CODE_NETWORK_CONNECTION, CDC_ECM_NET_CONNECTED, NULL); + } else { + g_current_net_status = 1; + usbd_cdc_ecm_send_notify(CDC_ECM_NOTIFY_CODE_NETWORK_CONNECTION, CDC_ECM_NET_DISCONNECTED, NULL); + } + + return 0; +} + +__WEAK void usbd_cdc_ecm_data_recv_done(uint32_t len) +{ + (void)len; +} + +__WEAK void usbd_cdc_ecm_data_send_done(uint32_t len) +{ + (void)len; +} diff --git a/kernel/cherryusb/class/cdc/usbd_cdc_ecm.h b/kernel/cherryusb/class/cdc/usbd_cdc_ecm.h new file mode 100644 index 0000000..780e7e2 --- /dev/null +++ b/kernel/cherryusb/class/cdc/usbd_cdc_ecm.h @@ -0,0 +1,36 @@ +/* + * Copyright (c) 2022, sakumisu + * + * SPDX-License-Identifier: Apache-2.0 + */ +#ifndef USBD_CDC_ECM_H +#define USBD_CDC_ECM_H + +#include "usb_cdc.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* Init cdc ecm interface driver */ +struct usbd_interface *usbd_cdc_ecm_init_intf(struct usbd_interface *intf, const uint8_t int_ep, const uint8_t out_ep, const uint8_t in_ep); + +int usbd_cdc_ecm_set_connect(bool connect, uint32_t speed[2]); + +void usbd_cdc_ecm_data_recv_done(uint32_t len); +void usbd_cdc_ecm_data_send_done(uint32_t len); +int usbd_cdc_ecm_start_write(uint8_t *buf, uint32_t len); +int usbd_cdc_ecm_start_read(uint8_t *buf, uint32_t len); + +#ifdef CONFIG_USBDEV_CDC_ECM_USING_LWIP +#include "lwip/netif.h" +#include "lwip/pbuf.h" +struct pbuf *usbd_cdc_ecm_eth_rx(void); +int usbd_cdc_ecm_eth_tx(struct pbuf *p); +#endif + +#ifdef __cplusplus +} +#endif + +#endif /* USBD_CDC_ECM_H */ diff --git a/kernel/cherryusb/class/cdc/usbh_cdc_ecm.c b/kernel/cherryusb/class/cdc/usbh_cdc_ecm.c new file mode 100644 index 0000000..0c64ff1 --- /dev/null +++ b/kernel/cherryusb/class/cdc/usbh_cdc_ecm.c @@ -0,0 +1,322 @@ +/* + * Copyright (c) 2024, sakumisu + * + * SPDX-License-Identifier: Apache-2.0 + */ +#include "usbh_core.h" +#include "usbh_cdc_ecm.h" + +#undef USB_DBG_TAG +#define USB_DBG_TAG "usbh_cdc_ecm" +#include "usb_log.h" + +#define DEV_FORMAT "/dev/cdc_ether" + +/* general descriptor field offsets */ +#define DESC_bLength 0 /** Length offset */ +#define DESC_bDescriptorType 1 /** Descriptor type offset */ +#define DESC_bDescriptorSubType 2 /** Descriptor subtype offset */ + +/* interface descriptor field offsets */ +#define INTF_DESC_bInterfaceNumber 2 /** Interface number offset */ +#define INTF_DESC_bAlternateSetting 3 /** Alternate setting offset */ + +#define CONFIG_USBHOST_CDC_ECM_PKT_FILTER 0x000C +#define CONFIG_USBHOST_CDC_ECM_ETH_MAX_SIZE 1514U + +static USB_NOCACHE_RAM_SECTION USB_MEM_ALIGNX uint8_t g_cdc_ecm_rx_buffer[USB_ALIGN_UP(CONFIG_USBHOST_CDC_ECM_ETH_MAX_SIZE, CONFIG_USB_ALIGN_SIZE)]; +static USB_NOCACHE_RAM_SECTION USB_MEM_ALIGNX uint8_t g_cdc_ecm_tx_buffer[USB_ALIGN_UP(CONFIG_USBHOST_CDC_ECM_ETH_MAX_SIZE, CONFIG_USB_ALIGN_SIZE)]; +static USB_NOCACHE_RAM_SECTION USB_MEM_ALIGNX uint8_t g_cdc_ecm_inttx_buffer[USB_ALIGN_UP(16, CONFIG_USB_ALIGN_SIZE)]; + +static struct usbh_cdc_ecm g_cdc_ecm_class; + +static int usbh_cdc_ecm_set_eth_packet_filter(struct usbh_cdc_ecm *cdc_ecm_class, uint16_t filter_value) +{ + struct usb_setup_packet *setup; + + if (!cdc_ecm_class || !cdc_ecm_class->hport) { + return -USB_ERR_INVAL; + } + setup = cdc_ecm_class->hport->setup; + + setup->bmRequestType = USB_REQUEST_DIR_OUT | USB_REQUEST_CLASS | USB_REQUEST_RECIPIENT_INTERFACE; + setup->bRequest = CDC_REQUEST_SET_ETHERNET_PACKET_FILTER; + setup->wValue = filter_value; + setup->wIndex = cdc_ecm_class->ctrl_intf; + setup->wLength = 0; + + return usbh_control_transfer(cdc_ecm_class->hport, setup, NULL); +} + +int usbh_cdc_ecm_get_connect_status(struct usbh_cdc_ecm *cdc_ecm_class) +{ + int ret; + + usbh_int_urb_fill(&cdc_ecm_class->intin_urb, cdc_ecm_class->hport, cdc_ecm_class->intin, g_cdc_ecm_inttx_buffer, 16, USB_OSAL_WAITING_FOREVER, NULL, NULL); + ret = usbh_submit_urb(&cdc_ecm_class->intin_urb); + if (ret < 0) { + return ret; + } + + if (g_cdc_ecm_inttx_buffer[1] == CDC_ECM_NOTIFY_CODE_NETWORK_CONNECTION) { + if (g_cdc_ecm_inttx_buffer[2] == CDC_ECM_NET_CONNECTED) { + cdc_ecm_class->connect_status = true; + } else { + cdc_ecm_class->connect_status = false; + } + } else if (g_cdc_ecm_inttx_buffer[1] == CDC_ECM_NOTIFY_CODE_CONNECTION_SPEED_CHANGE) { + memcpy(cdc_ecm_class->speed, &g_cdc_ecm_inttx_buffer[8], 8); + } + return 0; +} + +static int usbh_cdc_ecm_connect(struct usbh_hubport *hport, uint8_t intf) +{ + struct usb_endpoint_descriptor *ep_desc; + int ret; + uint8_t altsetting = 0; + char mac_buffer[12]; + uint8_t *p; + uint8_t cur_iface = 0xff; + uint8_t mac_str_idx = 0xff; + + struct usbh_cdc_ecm *cdc_ecm_class = &g_cdc_ecm_class; + + memset(cdc_ecm_class, 0, sizeof(struct usbh_cdc_ecm)); + + cdc_ecm_class->hport = hport; + cdc_ecm_class->ctrl_intf = intf; + cdc_ecm_class->data_intf = intf + 1; + + hport->config.intf[intf].priv = cdc_ecm_class; + hport->config.intf[intf + 1].priv = NULL; + + p = hport->raw_config_desc; + while (p[DESC_bLength]) { + switch (p[DESC_bDescriptorType]) { + case USB_DESCRIPTOR_TYPE_INTERFACE: + cur_iface = p[INTF_DESC_bInterfaceNumber]; + //cur_alt_setting = p[INTF_DESC_bAlternateSetting]; + break; + case CDC_CS_INTERFACE: + if ((cur_iface == cdc_ecm_class->ctrl_intf) && p[DESC_bDescriptorSubType] == CDC_FUNC_DESC_ETHERNET_NETWORKING) { + struct cdc_eth_descriptor *desc = (struct cdc_eth_descriptor *)p; + mac_str_idx = desc->iMACAddress; + cdc_ecm_class->max_segment_size = desc->wMaxSegmentSize; + goto get_mac; + } + break; + + default: + break; + } + /* skip to next descriptor */ + p += p[DESC_bLength]; + } + +get_mac: + if (mac_str_idx == 0xff) { + USB_LOG_ERR("Do not find cdc ecm mac string\r\n"); + return -1; + } + + memset(mac_buffer, 0, 12); + ret = usbh_get_string_desc(cdc_ecm_class->hport, mac_str_idx, (uint8_t *)mac_buffer, 12); + if (ret < 0) { + return ret; + } + + for (int i = 0, j = 0; i < 12; i += 2, j++) { + char byte_str[3]; + byte_str[0] = mac_buffer[i]; + byte_str[1] = mac_buffer[i + 1]; + byte_str[2] = '\0'; + + uint32_t byte = strtoul(byte_str, NULL, 16); + cdc_ecm_class->mac[j] = (unsigned char)byte; + } + + USB_LOG_INFO("CDC ECM MAC address %02x:%02x:%02x:%02x:%02x:%02x\r\n", + cdc_ecm_class->mac[0], + cdc_ecm_class->mac[1], + cdc_ecm_class->mac[2], + cdc_ecm_class->mac[3], + cdc_ecm_class->mac[4], + cdc_ecm_class->mac[5]); + + if (cdc_ecm_class->max_segment_size > CONFIG_USBHOST_CDC_ECM_ETH_MAX_SIZE) { + USB_LOG_ERR("CDC ECM Max Segment Size is overflow, default is %u, but now %u\r\n", CONFIG_USBHOST_CDC_ECM_ETH_MAX_SIZE, cdc_ecm_class->max_segment_size); + } else { + USB_LOG_INFO("CDC ECM Max Segment Size:%u\r\n", cdc_ecm_class->max_segment_size); + } + + /* enable int ep */ + ep_desc = &hport->config.intf[intf].altsetting[0].ep[0].ep_desc; + USBH_EP_INIT(cdc_ecm_class->intin, ep_desc); + + if (hport->config.intf[intf + 1].altsetting_num > 1) { + altsetting = hport->config.intf[intf + 1].altsetting_num - 1; + + for (uint8_t i = 0; i < hport->config.intf[intf + 1].altsetting[altsetting].intf_desc.bNumEndpoints; i++) { + ep_desc = &hport->config.intf[intf + 1].altsetting[altsetting].ep[i].ep_desc; + + if (ep_desc->bEndpointAddress & 0x80) { + USBH_EP_INIT(cdc_ecm_class->bulkin, ep_desc); + } else { + USBH_EP_INIT(cdc_ecm_class->bulkout, ep_desc); + } + } + + USB_LOG_INFO("Select cdc ecm altsetting: %d\r\n", altsetting); + usbh_set_interface(cdc_ecm_class->hport, cdc_ecm_class->data_intf, altsetting); + } else { + for (uint8_t i = 0; i < hport->config.intf[intf + 1].altsetting[0].intf_desc.bNumEndpoints; i++) { + ep_desc = &hport->config.intf[intf + 1].altsetting[0].ep[i].ep_desc; + + if (ep_desc->bEndpointAddress & 0x80) { + USBH_EP_INIT(cdc_ecm_class->bulkin, ep_desc); + } else { + USBH_EP_INIT(cdc_ecm_class->bulkout, ep_desc); + } + } + } + + /* bit0 Promiscuous + * bit1 ALL Multicast + * bit2 Directed + * bit3 Broadcast + * bit4 Multicast + */ + ret = usbh_cdc_ecm_set_eth_packet_filter(cdc_ecm_class, CONFIG_USBHOST_CDC_ECM_PKT_FILTER); + if (ret < 0) { + return ret; + } + USB_LOG_INFO("Set CDC ECM packet filter:%04x\r\n", CONFIG_USBHOST_CDC_ECM_PKT_FILTER); + + strncpy(hport->config.intf[intf].devname, DEV_FORMAT, CONFIG_USBHOST_DEV_NAMELEN); + + USB_LOG_INFO("Register CDC ECM Class:%s\r\n", hport->config.intf[intf].devname); + + usbh_cdc_ecm_run(cdc_ecm_class); + return ret; +} + +static int usbh_cdc_ecm_disconnect(struct usbh_hubport *hport, uint8_t intf) +{ + int ret = 0; + + struct usbh_cdc_ecm *cdc_ecm_class = (struct usbh_cdc_ecm *)hport->config.intf[intf].priv; + + if (cdc_ecm_class) { + if (cdc_ecm_class->bulkin) { + usbh_kill_urb(&cdc_ecm_class->bulkin_urb); + } + + if (cdc_ecm_class->bulkout) { + usbh_kill_urb(&cdc_ecm_class->bulkout_urb); + } + + if (cdc_ecm_class->intin) { + usbh_kill_urb(&cdc_ecm_class->intin_urb); + } + + if (hport->config.intf[intf].devname[0] != '\0') { + usb_osal_thread_schedule_other(); + USB_LOG_INFO("Unregister CDC ECM Class:%s\r\n", hport->config.intf[intf].devname); + usbh_cdc_ecm_stop(cdc_ecm_class); + } + + memset(cdc_ecm_class, 0, sizeof(struct usbh_cdc_ecm)); + } + + return ret; +} + +void usbh_cdc_ecm_rx_thread(CONFIG_USB_OSAL_THREAD_SET_ARGV) +{ + uint32_t g_cdc_ecm_rx_length; + int ret; + + (void)CONFIG_USB_OSAL_THREAD_GET_ARGV; + USB_LOG_INFO("Create cdc ecm rx thread\r\n"); + // clang-format off +find_class: + // clang-format on + g_cdc_ecm_class.connect_status = false; + if (usbh_find_class_instance("/dev/cdc_ether") == NULL) { + goto delete; + } + + while (g_cdc_ecm_class.connect_status == false) { + ret = usbh_cdc_ecm_get_connect_status(&g_cdc_ecm_class); + if (ret < 0) { + usb_osal_msleep(100); + goto find_class; + } + usb_osal_msleep(128); + } + + g_cdc_ecm_rx_length = 0; + while (1) { + usbh_bulk_urb_fill(&g_cdc_ecm_class.bulkin_urb, g_cdc_ecm_class.hport, g_cdc_ecm_class.bulkin, g_cdc_ecm_rx_buffer, CONFIG_USBHOST_CDC_ECM_ETH_MAX_SIZE, USB_OSAL_WAITING_FOREVER, NULL, NULL); + ret = usbh_submit_urb(&g_cdc_ecm_class.bulkin_urb); + if (ret < 0) { + goto find_class; + } + + g_cdc_ecm_rx_length = g_cdc_ecm_class.bulkin_urb.actual_length; + + /* A transfer is complete because last packet is a short packet. + * Short packet is not zero, match g_cdc_ecm_rx_length % USB_GET_MAXPACKETSIZE(g_cdc_ecm_class.bulkin->wMaxPacketSize). + * Short packet is zero, check if g_cdc_ecm_class.bulkin_urb.actual_length < transfer_size, for example transfer is complete with size is 512 < 1514. + * This case is always true + */ + if (g_cdc_ecm_rx_length % USB_GET_MAXPACKETSIZE(g_cdc_ecm_class.bulkin->wMaxPacketSize) || + (g_cdc_ecm_class.bulkin_urb.actual_length < CONFIG_USBHOST_CDC_ECM_ETH_MAX_SIZE)) { + USB_LOG_DBG("rxlen:%d\r\n", g_cdc_ecm_rx_length); + + usbh_cdc_ecm_eth_input(g_cdc_ecm_rx_buffer, g_cdc_ecm_rx_length); + + g_cdc_ecm_rx_length = 0; + } else { + /* There's no way to run here. */ + } + } + // clang-format off +delete: + USB_LOG_INFO("Delete cdc ecm rx thread\r\n"); + usb_osal_thread_delete(NULL); + // clang-format on +} + +uint8_t *usbh_cdc_ecm_get_eth_txbuf(void) +{ + return g_cdc_ecm_tx_buffer; +} + +int usbh_cdc_ecm_eth_output(uint32_t buflen) +{ + if (g_cdc_ecm_class.connect_status == false) { + return -USB_ERR_NOTCONN; + } + + USB_LOG_DBG("txlen:%d\r\n", buflen); + + usbh_bulk_urb_fill(&g_cdc_ecm_class.bulkout_urb, g_cdc_ecm_class.hport, g_cdc_ecm_class.bulkout, g_cdc_ecm_tx_buffer, buflen, USB_OSAL_WAITING_FOREVER, NULL, NULL); + return usbh_submit_urb(&g_cdc_ecm_class.bulkout_urb); +} + +const struct usbh_class_driver cdc_ecm_class_driver = { + .driver_name = "cdc_ecm", + .connect = usbh_cdc_ecm_connect, + .disconnect = usbh_cdc_ecm_disconnect +}; + +CLASS_INFO_DEFINE const struct usbh_class_info cdc_ecm_class_info = { + .match_flags = USB_CLASS_MATCH_INTF_CLASS | USB_CLASS_MATCH_INTF_SUBCLASS | USB_CLASS_MATCH_INTF_PROTOCOL, + .bInterfaceClass = USB_DEVICE_CLASS_CDC, + .bInterfaceSubClass = CDC_ETHERNET_NETWORKING_CONTROL_MODEL, + .bInterfaceProtocol = CDC_COMMON_PROTOCOL_NONE, + .id_table = NULL, + .class_driver = &cdc_ecm_class_driver +}; \ No newline at end of file diff --git a/kernel/cherryusb/class/cdc/usbh_cdc_ecm.h b/kernel/cherryusb/class/cdc/usbh_cdc_ecm.h new file mode 100644 index 0000000..a3ab84a --- /dev/null +++ b/kernel/cherryusb/class/cdc/usbh_cdc_ecm.h @@ -0,0 +1,50 @@ +/* + * Copyright (c) 2024, sakumisu + * + * SPDX-License-Identifier: Apache-2.0 + */ +#ifndef USBH_CDC_ECM_H +#define USBH_CDC_ECM_H + +#include "usb_cdc.h" + +struct usbh_cdc_ecm { + struct usbh_hubport *hport; + struct usb_endpoint_descriptor *bulkin; /* Bulk IN endpoint */ + struct usb_endpoint_descriptor *bulkout; /* Bulk OUT endpoint */ + struct usb_endpoint_descriptor *intin; /* Interrupt IN endpoint */ + struct usbh_urb bulkout_urb; /* Bulk out endpoint */ + struct usbh_urb bulkin_urb; /* Bulk IN endpoint */ + struct usbh_urb intin_urb; /* Interrupt IN endpoint */ + + uint8_t ctrl_intf; /* Control interface number */ + uint8_t data_intf; /* Data interface number */ + uint8_t minor; + + uint8_t mac[6]; + bool connect_status; + uint16_t max_segment_size; + uint32_t speed[2]; + + void *user_data; +}; + +#ifdef __cplusplus +extern "C" { +#endif + +int usbh_cdc_ecm_get_connect_status(struct usbh_cdc_ecm *cdc_ecm_class); + +void usbh_cdc_ecm_run(struct usbh_cdc_ecm *cdc_ecm_class); +void usbh_cdc_ecm_stop(struct usbh_cdc_ecm *cdc_ecm_class); + +uint8_t *usbh_cdc_ecm_get_eth_txbuf(void); +int usbh_cdc_ecm_eth_output(uint32_t buflen); +void usbh_cdc_ecm_eth_input(uint8_t *buf, uint32_t buflen); +void usbh_cdc_ecm_rx_thread(CONFIG_USB_OSAL_THREAD_SET_ARGV); + +#ifdef __cplusplus +} +#endif + +#endif /* USBH_CDC_ECM_H */ diff --git a/kernel/cherryusb/class/cdc/usbh_cdc_ncm.c b/kernel/cherryusb/class/cdc/usbh_cdc_ncm.c new file mode 100644 index 0000000..fa2ccc0 --- /dev/null +++ b/kernel/cherryusb/class/cdc/usbh_cdc_ncm.c @@ -0,0 +1,402 @@ +/* + * Copyright (c) 2024, sakumisu + * + * SPDX-License-Identifier: Apache-2.0 + */ +#include "usbh_core.h" +#include "usbh_cdc_ncm.h" + +#undef USB_DBG_TAG +#define USB_DBG_TAG "usbh_cdc_ncm" +#include "usb_log.h" + +#define DEV_FORMAT "/dev/cdc_ncm" + +/* general descriptor field offsets */ +#define DESC_bLength 0 /** Length offset */ +#define DESC_bDescriptorType 1 /** Descriptor type offset */ +#define DESC_bDescriptorSubType 2 /** Descriptor subtype offset */ + +/* interface descriptor field offsets */ +#define INTF_DESC_bInterfaceNumber 2 /** Interface number offset */ +#define INTF_DESC_bAlternateSetting 3 /** Alternate setting offset */ + +#define CONFIG_USBHOST_CDC_NCM_ETH_MAX_SEGSZE 1514U + +static USB_NOCACHE_RAM_SECTION USB_MEM_ALIGNX uint8_t g_cdc_ncm_rx_buffer[CONFIG_USBHOST_CDC_NCM_ETH_MAX_RX_SIZE]; +static USB_NOCACHE_RAM_SECTION USB_MEM_ALIGNX uint8_t g_cdc_ncm_tx_buffer[CONFIG_USBHOST_CDC_NCM_ETH_MAX_TX_SIZE]; +static USB_NOCACHE_RAM_SECTION USB_MEM_ALIGNX uint8_t g_cdc_ncm_inttx_buffer[USB_ALIGN_UP(16, CONFIG_USB_ALIGN_SIZE)]; + +static USB_NOCACHE_RAM_SECTION USB_MEM_ALIGNX uint8_t g_cdc_ncm_buf[USB_ALIGN_UP(32, CONFIG_USB_ALIGN_SIZE)]; + +static struct usbh_cdc_ncm g_cdc_ncm_class; + +static int usbh_cdc_ncm_get_ntb_parameters(struct usbh_cdc_ncm *cdc_ncm_class, struct cdc_ncm_ntb_parameters *param) +{ + struct usb_setup_packet *setup; + int ret; + + if (!cdc_ncm_class || !cdc_ncm_class->hport) { + return -USB_ERR_INVAL; + } + setup = cdc_ncm_class->hport->setup; + + setup->bmRequestType = USB_REQUEST_DIR_IN | USB_REQUEST_CLASS | USB_REQUEST_RECIPIENT_INTERFACE; + setup->bRequest = CDC_REQUEST_GET_NTB_PARAMETERS; + setup->wValue = 0; + setup->wIndex = cdc_ncm_class->ctrl_intf; + setup->wLength = 28; + + ret = usbh_control_transfer(cdc_ncm_class->hport, setup, g_cdc_ncm_buf); + if (ret < 8) { + return ret; + } + + memcpy((uint8_t *)param, g_cdc_ncm_buf, MIN(ret - 8, sizeof(struct cdc_ncm_ntb_parameters))); + return 0; +} + +static void print_ntb_parameters(struct cdc_ncm_ntb_parameters *param) +{ + USB_LOG_RAW("CDC NCM ntb parameters:\r\n"); + USB_LOG_RAW("wLength: 0x%02x \r\n", param->wLength); + USB_LOG_RAW("bmNtbFormatsSupported: %s \r\n", param->bmNtbFormatsSupported ? "NTB16" : "NTB32"); + + USB_LOG_RAW("dwNtbInMaxSize: 0x%08x \r\n", (unsigned int)param->dwNtbInMaxSize); + USB_LOG_RAW("wNdbInDivisor: 0x%02x \r\n", param->wNdbInDivisor); + USB_LOG_RAW("wNdbInPayloadRemainder: 0x%02x \r\n", param->wNdbInPayloadRemainder); + USB_LOG_RAW("wNdbInAlignment: 0x%02x \r\n", param->wNdbInAlignment); + + USB_LOG_RAW("dwNtbOutMaxSize: 0x%08x \r\n", (unsigned int)param->dwNtbOutMaxSize); + USB_LOG_RAW("wNdbOutDivisor: 0x%02x \r\n", param->wNdbOutDivisor); + USB_LOG_RAW("wNdbOutPayloadRemainder: 0x%02x \r\n", param->wNdbOutPayloadRemainder); + USB_LOG_RAW("wNdbOutAlignment: 0x%02x \r\n", param->wNdbOutAlignment); + + USB_LOG_RAW("wNtbOutMaxDatagrams: 0x%02x \r\n", param->wNtbOutMaxDatagrams); +} + +int usbh_cdc_ncm_get_connect_status(struct usbh_cdc_ncm *cdc_ncm_class) +{ + int ret; + + usbh_int_urb_fill(&cdc_ncm_class->intin_urb, cdc_ncm_class->hport, cdc_ncm_class->intin, g_cdc_ncm_inttx_buffer, 16, USB_OSAL_WAITING_FOREVER, NULL, NULL); + ret = usbh_submit_urb(&cdc_ncm_class->intin_urb); + if (ret < 0) { + return ret; + } + + if (g_cdc_ncm_inttx_buffer[1] == CDC_ECM_NOTIFY_CODE_NETWORK_CONNECTION) { + if (g_cdc_ncm_inttx_buffer[2] == CDC_ECM_NET_CONNECTED) { + cdc_ncm_class->connect_status = true; + } else { + cdc_ncm_class->connect_status = false; + } + } else if (g_cdc_ncm_inttx_buffer[1] == CDC_ECM_NOTIFY_CODE_CONNECTION_SPEED_CHANGE) { + memcpy(cdc_ncm_class->speed, &g_cdc_ncm_inttx_buffer[8], 8); + } + return 0; +} + +static int usbh_cdc_ncm_connect(struct usbh_hubport *hport, uint8_t intf) +{ + struct usb_endpoint_descriptor *ep_desc; + int ret; + uint8_t altsetting = 0; + char mac_buffer[12]; + uint8_t *p; + uint8_t cur_iface = 0xff; + uint8_t mac_str_idx = 0xff; + + struct usbh_cdc_ncm *cdc_ncm_class = &g_cdc_ncm_class; + + memset(cdc_ncm_class, 0, sizeof(struct usbh_cdc_ncm)); + + cdc_ncm_class->hport = hport; + cdc_ncm_class->ctrl_intf = intf; + cdc_ncm_class->data_intf = intf + 1; + + hport->config.intf[intf].priv = cdc_ncm_class; + hport->config.intf[intf + 1].priv = NULL; + + p = hport->raw_config_desc; + while (p[DESC_bLength]) { + switch (p[DESC_bDescriptorType]) { + case USB_DESCRIPTOR_TYPE_INTERFACE: + cur_iface = p[INTF_DESC_bInterfaceNumber]; + //cur_alt_setting = p[INTF_DESC_bAlternateSetting]; + break; + case CDC_CS_INTERFACE: + if ((cur_iface == cdc_ncm_class->ctrl_intf) && p[DESC_bDescriptorSubType] == CDC_FUNC_DESC_ETHERNET_NETWORKING) { + struct cdc_eth_descriptor *desc = (struct cdc_eth_descriptor *)p; + mac_str_idx = desc->iMACAddress; + cdc_ncm_class->max_segment_size = desc->wMaxSegmentSize; + goto get_mac; + } + break; + + default: + break; + } + /* skip to next descriptor */ + p += p[DESC_bLength]; + } + +get_mac: + if (mac_str_idx == 0xff) { + USB_LOG_ERR("Do not find cdc ncm mac string\r\n"); + return -1; + } + + memset(mac_buffer, 0, 12); + ret = usbh_get_string_desc(cdc_ncm_class->hport, mac_str_idx, (uint8_t *)mac_buffer, 12); + if (ret < 0) { + return ret; + } + + for (int i = 0, j = 0; i < 12; i += 2, j++) { + char byte_str[3]; + byte_str[0] = mac_buffer[i]; + byte_str[1] = mac_buffer[i + 1]; + byte_str[2] = '\0'; + + uint32_t byte = strtoul(byte_str, NULL, 16); + cdc_ncm_class->mac[j] = (unsigned char)byte; + } + + USB_LOG_INFO("CDC NCM MAC address %02x:%02x:%02x:%02x:%02x:%02x\r\n", + cdc_ncm_class->mac[0], + cdc_ncm_class->mac[1], + cdc_ncm_class->mac[2], + cdc_ncm_class->mac[3], + cdc_ncm_class->mac[4], + cdc_ncm_class->mac[5]); + + if (cdc_ncm_class->max_segment_size > CONFIG_USBHOST_CDC_NCM_ETH_MAX_SEGSZE) { + USB_LOG_ERR("CDC NCM Max Segment Size is overflow, default is %u, but now %u\r\n", CONFIG_USBHOST_CDC_NCM_ETH_MAX_SEGSZE, cdc_ncm_class->max_segment_size); + } else { + USB_LOG_INFO("CDC NCM Max Segment Size:%u\r\n", cdc_ncm_class->max_segment_size); + } + + usbh_cdc_ncm_get_ntb_parameters(cdc_ncm_class, &cdc_ncm_class->ntb_param); + print_ntb_parameters(&cdc_ncm_class->ntb_param); + + /* enable int ep */ + ep_desc = &hport->config.intf[intf].altsetting[0].ep[0].ep_desc; + USBH_EP_INIT(cdc_ncm_class->intin, ep_desc); + + if (hport->config.intf[intf + 1].altsetting_num > 1) { + altsetting = hport->config.intf[intf + 1].altsetting_num - 1; + + for (uint8_t i = 0; i < hport->config.intf[intf + 1].altsetting[altsetting].intf_desc.bNumEndpoints; i++) { + ep_desc = &hport->config.intf[intf + 1].altsetting[altsetting].ep[i].ep_desc; + + if (ep_desc->bEndpointAddress & 0x80) { + USBH_EP_INIT(cdc_ncm_class->bulkin, ep_desc); + } else { + USBH_EP_INIT(cdc_ncm_class->bulkout, ep_desc); + } + } + + USB_LOG_INFO("Select cdc ncm altsetting: %d\r\n", altsetting); + usbh_set_interface(cdc_ncm_class->hport, cdc_ncm_class->data_intf, altsetting); + } else { + for (uint8_t i = 0; i < hport->config.intf[intf + 1].altsetting[0].intf_desc.bNumEndpoints; i++) { + ep_desc = &hport->config.intf[intf + 1].altsetting[0].ep[i].ep_desc; + + if (ep_desc->bEndpointAddress & 0x80) { + USBH_EP_INIT(cdc_ncm_class->bulkin, ep_desc); + } else { + USBH_EP_INIT(cdc_ncm_class->bulkout, ep_desc); + } + } + } + + strncpy(hport->config.intf[intf].devname, DEV_FORMAT, CONFIG_USBHOST_DEV_NAMELEN); + + USB_LOG_INFO("Register CDC NCM Class:%s\r\n", hport->config.intf[intf].devname); + + usbh_cdc_ncm_run(cdc_ncm_class); + return ret; +} + +static int usbh_cdc_ncm_disconnect(struct usbh_hubport *hport, uint8_t intf) +{ + int ret = 0; + + struct usbh_cdc_ncm *cdc_ncm_class = (struct usbh_cdc_ncm *)hport->config.intf[intf].priv; + + if (cdc_ncm_class) { + if (cdc_ncm_class->bulkin) { + usbh_kill_urb(&cdc_ncm_class->bulkin_urb); + } + + if (cdc_ncm_class->bulkout) { + usbh_kill_urb(&cdc_ncm_class->bulkout_urb); + } + + if (cdc_ncm_class->intin) { + usbh_kill_urb(&cdc_ncm_class->intin_urb); + } + + if (hport->config.intf[intf].devname[0] != '\0') { + usb_osal_thread_schedule_other(); + USB_LOG_INFO("Unregister CDC NCM Class:%s\r\n", hport->config.intf[intf].devname); + usbh_cdc_ncm_stop(cdc_ncm_class); + } + + memset(cdc_ncm_class, 0, sizeof(struct usbh_cdc_ncm)); + } + + return ret; +} + +void usbh_cdc_ncm_rx_thread(CONFIG_USB_OSAL_THREAD_SET_ARGV) +{ + uint32_t g_cdc_ncm_rx_length; + int ret; +#if CONFIG_USBHOST_CDC_NCM_ETH_MAX_RX_SIZE <= (16 * 1024) + uint32_t transfer_size = CONFIG_USBHOST_CDC_NCM_ETH_MAX_RX_SIZE; +#else + uint32_t transfer_size = (16 * 1024); +#endif + + (void)CONFIG_USB_OSAL_THREAD_GET_ARGV; + USB_LOG_INFO("Create cdc ncm rx thread\r\n"); + // clang-format off +find_class: + // clang-format on + g_cdc_ncm_class.connect_status = false; + if (usbh_find_class_instance("/dev/cdc_ncm") == NULL) { + goto delete; + } + + while (g_cdc_ncm_class.connect_status == false) { + ret = usbh_cdc_ncm_get_connect_status(&g_cdc_ncm_class); + if (ret < 0) { + usb_osal_msleep(100); + goto find_class; + } + } + + g_cdc_ncm_rx_length = 0; + while (1) { + usbh_bulk_urb_fill(&g_cdc_ncm_class.bulkin_urb, g_cdc_ncm_class.hport, g_cdc_ncm_class.bulkin, &g_cdc_ncm_rx_buffer[g_cdc_ncm_rx_length], transfer_size, USB_OSAL_WAITING_FOREVER, NULL, NULL); + ret = usbh_submit_urb(&g_cdc_ncm_class.bulkin_urb); + if (ret < 0) { + goto find_class; + } + + g_cdc_ncm_rx_length += g_cdc_ncm_class.bulkin_urb.actual_length; + + /* A transfer is complete because last packet is a short packet. + * Short packet is not zero, match g_cdc_ncm_rx_length % USB_GET_MAXPACKETSIZE(g_cdc_ncm_class.bulkin->wMaxPacketSize). + * Short packet is zero, check if g_cdc_ncm_class.bulkin_urb.actual_length < transfer_size, for example transfer is complete with size is 1024 < 2048. + */ + if ((g_cdc_ncm_rx_length % USB_GET_MAXPACKETSIZE(g_cdc_ncm_class.bulkin->wMaxPacketSize)) || + (g_cdc_ncm_class.bulkin_urb.actual_length < transfer_size)) { + USB_LOG_DBG("rxlen:%d\r\n", g_cdc_ncm_rx_length); + + struct cdc_ncm_nth16 *nth16 = (struct cdc_ncm_nth16 *)&g_cdc_ncm_rx_buffer[0]; + if ((nth16->dwSignature != CDC_NCM_NTH16_SIGNATURE) || + (nth16->wHeaderLength != 12) || + (nth16->wBlockLength != g_cdc_ncm_rx_length)) { + USB_LOG_ERR("invalid rx nth16\r\n"); + g_cdc_ncm_rx_length = 0; + continue; + } + + struct cdc_ncm_ndp16 *ndp16 = (struct cdc_ncm_ndp16 *)&g_cdc_ncm_rx_buffer[nth16->wNdpIndex]; + if ((ndp16->dwSignature != CDC_NCM_NDP16_SIGNATURE_NCM0) && (ndp16->dwSignature != CDC_NCM_NDP16_SIGNATURE_NCM1)) { + USB_LOG_ERR("invalid rx ndp16\r\n"); + g_cdc_ncm_rx_length = 0; + continue; + } + + uint16_t datagram_num = (ndp16->wLength - 8) / 4; + + USB_LOG_DBG("datagram num:%02x\r\n", datagram_num); + for (uint16_t i = 0; i < datagram_num; i++) { + struct cdc_ncm_ndp16_datagram *ndp16_datagram = (struct cdc_ncm_ndp16_datagram *)&g_cdc_ncm_rx_buffer[nth16->wNdpIndex + 8 + 4 * i]; + if (ndp16_datagram->wDatagramIndex && ndp16_datagram->wDatagramLength) { + USB_LOG_DBG("ndp16_datagram index:%02x, length:%02x\r\n", ndp16_datagram->wDatagramIndex, ndp16_datagram->wDatagramLength); + + uint8_t *buf = (uint8_t *)&g_cdc_ncm_rx_buffer[ndp16_datagram->wDatagramIndex]; + usbh_cdc_ncm_eth_input(buf, ndp16_datagram->wDatagramLength); + } + } + + g_cdc_ncm_rx_length = 0; + } else { +#if CONFIG_USBHOST_CDC_NCM_ETH_MAX_RX_SIZE <= (16 * 1024) + if (g_cdc_ncm_rx_length == CONFIG_USBHOST_CDC_NCM_ETH_MAX_RX_SIZE) { +#else + if ((g_cdc_ncm_rx_length + (16 * 1024)) > CONFIG_USBHOST_CDC_NCM_ETH_MAX_RX_SIZE) { +#endif + USB_LOG_ERR("Rx packet is overflow, please reduce tcp window size or increase CONFIG_USBHOST_CDC_NCM_ETH_MAX_RX_SIZE\r\n"); + while (1) { + } + } + } + } + // clang-format off +delete: + USB_LOG_INFO("Delete cdc ncm rx thread\r\n"); + usb_osal_thread_delete(NULL); + // clang-format on +} + +uint8_t *usbh_cdc_ncm_get_eth_txbuf(void) +{ + return &g_cdc_ncm_tx_buffer[16]; +} + +int usbh_cdc_ncm_eth_output(uint32_t buflen) +{ + struct cdc_ncm_ndp16_datagram *ndp16_datagram; + + if (g_cdc_ncm_class.connect_status == false) { + return -USB_ERR_NOTCONN; + } + + struct cdc_ncm_nth16 *nth16 = (struct cdc_ncm_nth16 *)&g_cdc_ncm_tx_buffer[0]; + + nth16->dwSignature = CDC_NCM_NTH16_SIGNATURE; + nth16->wHeaderLength = 12; + nth16->wSequence = g_cdc_ncm_class.bulkout_sequence++; + nth16->wBlockLength = 16 + 16 + USB_ALIGN_UP(buflen, 4); + nth16->wNdpIndex = 16 + USB_ALIGN_UP(buflen, 4); + + struct cdc_ncm_ndp16 *ndp16 = (struct cdc_ncm_ndp16 *)&g_cdc_ncm_tx_buffer[nth16->wNdpIndex]; + + ndp16->dwSignature = CDC_NCM_NDP16_SIGNATURE_NCM0; + ndp16->wLength = 16; + ndp16->wNextNdpIndex = 0; + + ndp16_datagram = (struct cdc_ncm_ndp16_datagram *)&g_cdc_ncm_tx_buffer[nth16->wNdpIndex + 8 + 4 * 0]; + ndp16_datagram->wDatagramIndex = 16; + ndp16_datagram->wDatagramLength = buflen; + + ndp16_datagram = (struct cdc_ncm_ndp16_datagram *)&g_cdc_ncm_tx_buffer[nth16->wNdpIndex + 8 + 4 * 1]; + ndp16_datagram->wDatagramIndex = 0; + ndp16_datagram->wDatagramLength = 0; + + USB_LOG_DBG("txlen:%d\r\n", nth16->wBlockLength); + + usbh_bulk_urb_fill(&g_cdc_ncm_class.bulkout_urb, g_cdc_ncm_class.hport, g_cdc_ncm_class.bulkout, g_cdc_ncm_tx_buffer, nth16->wBlockLength, USB_OSAL_WAITING_FOREVER, NULL, NULL); + return usbh_submit_urb(&g_cdc_ncm_class.bulkout_urb); +} + +const struct usbh_class_driver cdc_ncm_class_driver = { + .driver_name = "cdc_ncm", + .connect = usbh_cdc_ncm_connect, + .disconnect = usbh_cdc_ncm_disconnect +}; + +CLASS_INFO_DEFINE const struct usbh_class_info cdc_ncm_class_info = { + .match_flags = USB_CLASS_MATCH_INTF_CLASS | USB_CLASS_MATCH_INTF_SUBCLASS | USB_CLASS_MATCH_INTF_PROTOCOL, + .bInterfaceClass = USB_DEVICE_CLASS_CDC, + .bInterfaceSubClass = CDC_NETWORK_CONTROL_MODEL, + .bInterfaceProtocol = CDC_COMMON_PROTOCOL_NONE, + .id_table = NULL, + .class_driver = &cdc_ncm_class_driver +}; diff --git a/kernel/cherryusb/class/cdc/usbh_cdc_ncm.h b/kernel/cherryusb/class/cdc/usbh_cdc_ncm.h new file mode 100644 index 0000000..b86122a --- /dev/null +++ b/kernel/cherryusb/class/cdc/usbh_cdc_ncm.h @@ -0,0 +1,54 @@ +/* + * Copyright (c) 2024, sakumisu + * + * SPDX-License-Identifier: Apache-2.0 + */ +#ifndef USBH_CDC_NCM_H +#define USBH_CDC_NCM_H + +#include "usb_cdc.h" + +struct usbh_cdc_ncm { + struct usbh_hubport *hport; + struct usb_endpoint_descriptor *bulkin; /* Bulk IN endpoint */ + struct usb_endpoint_descriptor *bulkout; /* Bulk OUT endpoint */ + struct usb_endpoint_descriptor *intin; /* Interrupt IN endpoint */ + struct usbh_urb bulkout_urb; /* Bulk out endpoint */ + struct usbh_urb bulkin_urb; /* Bulk IN endpoint */ + struct usbh_urb intin_urb; /* Interrupt IN endpoint */ + + uint8_t ctrl_intf; /* Control interface number */ + uint8_t data_intf; /* Data interface number */ + uint8_t minor; + + struct cdc_ncm_ntb_parameters ntb_param; + uint16_t bulkin_sequence; + uint16_t bulkout_sequence; + + uint8_t mac[6]; + bool connect_status; + uint16_t max_segment_size; + uint32_t speed[2]; + + void *user_data; +}; + +#ifdef __cplusplus +extern "C" { +#endif + +int usbh_cdc_ncm_get_connect_status(struct usbh_cdc_ncm *cdc_ncm_class); + +void usbh_cdc_ncm_run(struct usbh_cdc_ncm *cdc_ncm_class); +void usbh_cdc_ncm_stop(struct usbh_cdc_ncm *cdc_ncm_class); + +uint8_t *usbh_cdc_ncm_get_eth_txbuf(void); +int usbh_cdc_ncm_eth_output(uint32_t buflen); +void usbh_cdc_ncm_eth_input(uint8_t *buf, uint32_t buflen); +void usbh_cdc_ncm_rx_thread(CONFIG_USB_OSAL_THREAD_SET_ARGV); + +#ifdef __cplusplus +} +#endif + +#endif /* USBH_CDC_NCM_H */ diff --git a/kernel/cherryusb/class/dfu/usb_dfu.h b/kernel/cherryusb/class/dfu/usb_dfu.h new file mode 100644 index 0000000..fd10696 --- /dev/null +++ b/kernel/cherryusb/class/dfu/usb_dfu.h @@ -0,0 +1,140 @@ +/* + * Copyright (c) 2022, sakumisu + * + * SPDX-License-Identifier: Apache-2.0 + */ +#ifndef USB_DFU_H +#define USB_DFU_H + +/**\addtogroup USB_MODULE_DFU USB DFU class + * \brief This module contains USB Device Firmware Upgrade class definitions. + * \details This module based on + * + [USB Device Firmware Upgrade Specification, Revision 1.1] + * (https://www.usb.org/sites/default/files/DFU_1.1.pdf) + * @{ */ + +/** DFU Specification release */ +#define DFU_VERSION 0x0110 + +/** DFU Class Subclass */ +#define DFU_SUBCLASS_DFU 0x01 + +/** DFU Class runtime Protocol */ +#define DFU_PROTOCOL_RUNTIME 0x01 + +/** DFU Class DFU mode Protocol */ +#define DFU_PROTOCOL_DFU 0x02 + +/** + * @brief DFU Class Specific Requests + */ +#define DFU_REQUEST_DETACH 0x00 +#define DFU_REQUEST_DNLOAD 0x01 +#define DFU_REQUEST_UPLOAD 0x02 +#define DFU_REQUEST_GETSTATUS 0x03 +#define DFU_REQUEST_CLRSTATUS 0x04 +#define DFU_REQUEST_GETSTATE 0x05 +#define DFU_REQUEST_ABORT 0x06 + +/** DFU FUNCTIONAL descriptor type */ +#define DFU_FUNC_DESC 0x21 + +/** DFU attributes DFU Functional Descriptor */ +#define DFU_ATTR_WILL_DETACH 0x08 +#define DFU_ATTR_MANIFESTATION_TOLERANT 0x04 +#define DFU_ATTR_CAN_UPLOAD 0x02 +#define DFU_ATTR_CAN_DNLOAD 0x01 + +/** bStatus values for the DFU_GETSTATUS response */ +#define DFU_STATUS_OK 0x00U +#define DFU_STATUS_ERR_TARGET 0x01U +#define DFU_STATUS_ERR_FILE 0x02U +#define DFU_STATUS_ERR_WRITE 0x03U +#define DFU_STATUS_ERR_ERASE 0x04U +#define DFU_STATUS_ERR_CHECK_ERASED 0x05U +#define DFU_STATUS_ERR_PROG 0x06U +#define DFU_STATUS_ERR_VERIFY 0x07U +#define DFU_STATUS_ERR_ADDRESS 0x08U +#define DFU_STATUS_ERR_NOTDONE 0x09U +#define DFU_STATUS_ERR_FIRMWARE 0x0AU +#define DFU_STATUS_ERR_VENDOR 0x0BU +#define DFU_STATUS_ERR_USB 0x0CU +#define DFU_STATUS_ERR_POR 0x0DU +#define DFU_STATUS_ERR_UNKNOWN 0x0EU +#define DFU_STATUS_ERR_STALLEDPKT 0x0FU + +/** bState values for the DFU_GETSTATUS response */ +#define DFU_STATE_APP_IDLE 0U +#define DFU_STATE_APP_DETACH 1U +#define DFU_STATE_DFU_IDLE 2U +#define DFU_STATE_DFU_DNLOAD_SYNC 3U +#define DFU_STATE_DFU_DNLOAD_BUSY 4U +#define DFU_STATE_DFU_DNLOAD_IDLE 5U +#define DFU_STATE_DFU_MANIFEST_SYNC 6U +#define DFU_STATE_DFU_MANIFEST 7U +#define DFU_STATE_DFU_MANIFEST_WAIT_RESET 8U +#define DFU_STATE_DFU_UPLOAD_IDLE 9U +#define DFU_STATE_DFU_ERROR 10U + +/* Define DFU application notification signals. */ +#define DFU_NOTIFICATION_BEGIN_DOWNLOAD 0x1u +#define DFU_NOTIFICATION_END_DOWNLOAD 0x2u +#define DFU_NOTIFICATION_ABORT_DOWNLOAD 0x3u +#define DFU_NOTIFICATION_BEGIN_UPLOAD 0x5u +#define DFU_NOTIFICATION_END_UPLOAD 0x6u +#define DFU_NOTIFICATION_ABORT_UPLOAD 0x7u + +/* Define DFU application notification signals. */ +#define DFU_MEDIA_STATUS_OK 0 +#define DFU_MEDIA_STATUS_BUSY 1 +#define DFU_MEDIA_STATUS_ERROR 2 + +/** Special Commands with Download Request for STM32, wValue = 0 */ +#define DFU_SPECIAL_CMD_SET_ADDRESS_POINTER 0x21U +#define DFU_SPECIAL_CMD_ERASE 0x41U +#define DFU_SPECIAL_READ_UNPROTECT 0x92U + +/** Run-Time Functional Descriptor */ +struct dfu_runtime_descriptor { + uint8_t bLength; /**<\brief Descriptor length in bytes.*/ + uint8_t bDescriptorType; /**<\brief DFU functional descriptor type.*/ + uint8_t bmAttributes; /**<\brief USB DFU capabilities \ref USB_DFU_CAPAB*/ + uint16_t wDetachTimeout; /**<\brief USB DFU detach timeout in ms.*/ + uint16_t wTransferSize; /**<\brief USB DFU maximum transfer block size in bytes.*/ + uint16_t bcdDFUVersion; /**<\brief USB DFU version \ref VERSION_BCD utility macro.*/ +} __PACKED; + +/**\brief Payload packet to response in DFU_GETSTATUS request */ +struct dfu_status { + uint8_t bStatus; /**<\brief An indication of the status resulting from the + * execution of the most recent request.*/ + uint32_t bwPollTimeout; /**<\brief Minimum time in ms, that the host should wait + * before sending a subsequent DFU_GETSTATUS request.*/ + uint8_t bState; /**<\brief An indication of the state that the device is going + * to enter immediately following transmission of this response.*/ + uint8_t iString; /**<\brief Index of the status string descriptor.*/ +}; + +#define DFU_DESCRIPTOR_LEN 18 + +// clang-format off +#define DFU_DESCRIPTOR_INIT(str_idx) \ + 0x09, /* bLength */ \ + USB_DESCRIPTOR_TYPE_INTERFACE, /* bDescriptorType */ \ + 0x00, /* bInterfaceNumber */ \ + 0x00, /* bAlternateSetting */ \ + 0x00, /* bNumEndpoints Default Control Pipe only */ \ + USB_DEVICE_CLASS_APP_SPECIFIC, /* bInterfaceClass */ \ + DFU_SUBCLASS_DFU, /* bInterfaceSubClass Device Firmware Upgrade */ \ + DFU_PROTOCOL_DFU, /* bInterfaceProtocol DFU mode */ \ + str_idx, /* iInterface */ \ + /*!< Device Firmware Update Functional Descriptor */ \ + 0x09, /* bLength */ \ + 0x21, /* DFU Functional Descriptor */ \ + 0x0B, /* bmAttributes */ \ + WBVAL(0x00ff), /* wDetachTimeOut */ \ + WBVAL(CONFIG_USBDEV_REQUEST_BUFFER_LEN), /* wTransferSize */ \ + WBVAL(DFU_VERSION) /* bcdDFUVersion */ +// clang-format on + +#endif /* USB_DFU_H */ diff --git a/kernel/cherryusb/class/dfu/usbd_dfu.c b/kernel/cherryusb/class/dfu/usbd_dfu.c new file mode 100644 index 0000000..4c3e432 --- /dev/null +++ b/kernel/cherryusb/class/dfu/usbd_dfu.c @@ -0,0 +1,360 @@ +/* + * Copyright (c) 2022 ~ 2026, sakumisu + * + * SPDX-License-Identifier: Apache-2.0 + */ +#include "usbd_core.h" +#include "usbd_dfu.h" + +struct usbd_dfu_priv { + uint8_t dfu_state; +} g_usbd_dfu; + +const char *usbd_dfu_state_string[] = { + "APP_IDLE", + "APP_DETACH", + "DFU_IDLE", + "DFU_DNLOAD_SYNC", + "DFU_DNLOAD_BUSY", + "DFU_DNLOAD_IDLE", + "DFU_MANIFEST_SYNC", + "DFU_MANIFEST", + "DFU_MANIFEST_WAIT_RESET", + "DFU_UPLOAD_IDLE", + "DFU_ERROR" +}; + +static int dfu_class_interface_request_handler(uint8_t busid, struct usb_setup_packet *setup, uint8_t **data, uint32_t *len) +{ + USB_LOG_DBG("DFU Class request: " + "bRequest 0x%02x\r\n", + setup->bRequest); + + USB_LOG_DBG("dfu state:%s\r\n", usbd_dfu_state_string[g_usbd_dfu.dfu_state]); + + switch (g_usbd_dfu.dfu_state) { + case DFU_STATE_APP_IDLE: + switch (setup->bRequest) { + case DFU_REQUEST_DETACH: + break; + case DFU_REQUEST_GETSTATUS: + (*data)[0] = DFU_STATUS_OK; /* bStatus */ + (*data)[1] = 0; + (*data)[2] = 0; + (*data)[3] = 0; + (*data)[4] = g_usbd_dfu.dfu_state; + (*data)[5] = 0; /* iString */ + *len = 6; + break; + case DFU_REQUEST_GETSTATE: + (*data)[0] = g_usbd_dfu.dfu_state; + *len = 1; + break; + + default: + return -1; + } + break; + case DFU_STATE_APP_DETACH: + switch (setup->bRequest) { + case DFU_REQUEST_GETSTATUS: + (*data)[0] = DFU_STATUS_OK; /* bStatus */ + (*data)[1] = 0; + (*data)[2] = 0; + (*data)[3] = 0; + (*data)[4] = g_usbd_dfu.dfu_state; + (*data)[5] = 0; /* iString */ + *len = 6; + break; + case DFU_REQUEST_GETSTATE: + (*data)[0] = g_usbd_dfu.dfu_state; + *len = 1; + break; + + default: + return -1; + } + break; + case DFU_STATE_DFU_IDLE: + switch (setup->bRequest) { + case DFU_REQUEST_DNLOAD: + /* We received a DOWNLOAD command. Check the length field of the request. If it is 0, + we are done with the transfer. */ + if (setup->wLength == 0) { + usbd_dfu_end_load(); + g_usbd_dfu.dfu_state = DFU_STATE_DFU_MANIFEST_SYNC; + } else { + usbd_dfu_begin_load(); + if (usbd_dfu_write(setup->wValue, *data, setup->wLength) < 0) { + g_usbd_dfu.dfu_state = DFU_STATE_DFU_ERROR; + return -1; + } else { + g_usbd_dfu.dfu_state = DFU_STATE_DFU_DNLOAD_SYNC; + } + } + break; + case DFU_REQUEST_UPLOAD: + usbd_dfu_begin_load(); + + uint16_t actual_length; + if (usbd_dfu_read(setup->wValue, *data, setup->wLength, &actual_length) < 0) { + g_usbd_dfu.dfu_state = DFU_STATE_DFU_ERROR; + return -1; + } else { + g_usbd_dfu.dfu_state = DFU_STATE_DFU_UPLOAD_IDLE; + } + *len = actual_length; + break; + case DFU_REQUEST_ABORT: + g_usbd_dfu.dfu_state = DFU_STATE_DFU_IDLE; + break; + case DFU_REQUEST_GETSTATUS: + (*data)[0] = DFU_STATUS_OK; /* bStatus */ + (*data)[1] = 0; + (*data)[2] = 0; + (*data)[3] = 0; + (*data)[4] = g_usbd_dfu.dfu_state; + (*data)[5] = 0; /* iString */ + *len = 6; + break; + case DFU_REQUEST_GETSTATE: + (*data)[0] = g_usbd_dfu.dfu_state; + *len = 1; + break; + + default: + return -1; + } + break; + case DFU_STATE_DFU_DNLOAD_SYNC: + switch (setup->bRequest) { + case DFU_REQUEST_GETSTATUS: + g_usbd_dfu.dfu_state = DFU_STATE_DFU_DNLOAD_BUSY; + + (*data)[0] = DFU_STATUS_OK; /* bStatus */ + (*data)[1] = 0; + (*data)[2] = 0; + (*data)[3] = 0; + (*data)[4] = g_usbd_dfu.dfu_state; + (*data)[5] = 0; /* iString */ + *len = 6; + break; + case DFU_REQUEST_GETSTATE: + (*data)[0] = g_usbd_dfu.dfu_state; + *len = 1; + break; + + default: + return -1; + } + break; + case DFU_STATE_DFU_DNLOAD_BUSY: + switch (setup->bRequest) { + case DFU_REQUEST_GETSTATUS: + g_usbd_dfu.dfu_state = DFU_STATE_DFU_DNLOAD_IDLE; + + (*data)[0] = DFU_STATUS_OK; /* bStatus */ + (*data)[1] = 0; + (*data)[2] = 0; + (*data)[3] = 0; + (*data)[4] = g_usbd_dfu.dfu_state; + (*data)[5] = 0; /* iString */ + *len = 6; + break; + case DFU_REQUEST_GETSTATE: + (*data)[0] = g_usbd_dfu.dfu_state; + *len = 1; + break; + + default: + return -1; + } + break; + case DFU_STATE_DFU_DNLOAD_IDLE: + switch (setup->bRequest) { + case DFU_REQUEST_DNLOAD: + /* We received a DOWNLOAD command. Check the length field of the request. If it is 0, + we are done with the transfer. */ + if (setup->wLength == 0) { + usbd_dfu_end_load(); + g_usbd_dfu.dfu_state = DFU_STATE_DFU_MANIFEST_SYNC; + } else { + if (usbd_dfu_write(setup->wValue, *data, setup->wLength) < 0) { + g_usbd_dfu.dfu_state = DFU_STATE_DFU_ERROR; + return -1; + } else { + g_usbd_dfu.dfu_state = DFU_STATE_DFU_DNLOAD_SYNC; + } + } + + break; + case DFU_REQUEST_ABORT: + g_usbd_dfu.dfu_state = DFU_STATE_DFU_IDLE; + break; + case DFU_REQUEST_GETSTATUS: + (*data)[0] = DFU_STATUS_OK; /* bStatus */ + (*data)[1] = 0; + (*data)[2] = 0; + (*data)[3] = 0; + (*data)[4] = g_usbd_dfu.dfu_state; + (*data)[5] = 0; /* iString */ + *len = 6; + break; + case DFU_REQUEST_GETSTATE: + (*data)[0] = g_usbd_dfu.dfu_state; + *len = 1; + break; + + default: + return -1; + } + break; + case DFU_STATE_DFU_UPLOAD_IDLE: + switch (setup->bRequest) { + case DFU_REQUEST_UPLOAD: { + uint16_t actual_length; + if (usbd_dfu_read(setup->wValue, *data, setup->wLength, &actual_length) < 0) { + g_usbd_dfu.dfu_state = DFU_STATE_DFU_ERROR; + return -1; + } else { + if (actual_length < setup->wLength) { + usbd_dfu_end_load(); + g_usbd_dfu.dfu_state = DFU_STATE_DFU_IDLE; + } else { + g_usbd_dfu.dfu_state = DFU_STATE_DFU_UPLOAD_IDLE; + } + } + } break; + case DFU_REQUEST_ABORT: + g_usbd_dfu.dfu_state = DFU_STATE_DFU_IDLE; + break; + case DFU_REQUEST_GETSTATUS: + (*data)[0] = DFU_STATUS_OK; /* bStatus */ + (*data)[1] = 0; + (*data)[2] = 0; + (*data)[3] = 0; + (*data)[4] = g_usbd_dfu.dfu_state; + (*data)[5] = 0; /* iString */ + *len = 6; + break; + case DFU_REQUEST_GETSTATE: + (*data)[0] = g_usbd_dfu.dfu_state; + *len = 1; + break; + + default: + return -1; + } + break; + case DFU_STATE_DFU_MANIFEST_SYNC: + switch (setup->bRequest) { + case DFU_REQUEST_GETSTATUS: + g_usbd_dfu.dfu_state = DFU_STATE_DFU_MANIFEST_WAIT_RESET; + + (*data)[0] = DFU_STATUS_OK; /* bStatus */ + (*data)[1] = 0; + (*data)[2] = 0; + (*data)[3] = 0; + (*data)[4] = g_usbd_dfu.dfu_state; + (*data)[5] = 0; /* iString */ + *len = 6; + + break; + case DFU_REQUEST_GETSTATE: + (*data)[0] = g_usbd_dfu.dfu_state; + *len = 1; + break; + + default: + return -1; + } + break; + case DFU_STATE_DFU_MANIFEST_WAIT_RESET: + switch (setup->bRequest) { + case DFU_REQUEST_GETSTATUS: + + (*data)[0] = DFU_STATUS_OK; /* bStatus */ + (*data)[1] = 0; + (*data)[2] = 0; + (*data)[3] = 0; + (*data)[4] = g_usbd_dfu.dfu_state; + (*data)[5] = 0; /* iString */ + *len = 6; + + usbd_dfu_reset(); + + break; + case DFU_REQUEST_GETSTATE: + (*data)[0] = g_usbd_dfu.dfu_state; + *len = 1; + break; + + default: + return -1; + } + break; + case DFU_STATE_DFU_ERROR: + switch (setup->bRequest) { + case DFU_REQUEST_CLRSTATUS: + g_usbd_dfu.dfu_state = DFU_STATE_DFU_IDLE; + break; + + default: + return -1; + } + break; + + default: + USB_LOG_WRN("Invalid dfu state %s\r\n", usbd_dfu_state_string[g_usbd_dfu.dfu_state]); + return -1; + } + return 0; +} + +static void dfu_notify_handler(uint8_t busid, uint8_t event, void *arg) +{ + switch (event) { + case USBD_EVENT_RESET: + g_usbd_dfu.dfu_state = DFU_STATE_DFU_IDLE; + break; + default: + break; + } +} + +struct usbd_interface *usbd_dfu_init_intf(struct usbd_interface *intf) +{ + intf->class_interface_handler = dfu_class_interface_request_handler; + intf->class_endpoint_handler = NULL; + intf->vendor_handler = NULL; + intf->notify_handler = dfu_notify_handler; + + return intf; +} + +uint8_t usbd_dfu_get_state(void) +{ + return g_usbd_dfu.dfu_state; +} + +__WEAK void usbd_dfu_begin_load(void) +{ +} + +__WEAK void usbd_dfu_end_load(void) +{ +} + +__WEAK void usbd_dfu_reset(void) +{ +} + +__WEAK int usbd_dfu_write(uint16_t value, const uint8_t *data, uint16_t length) +{ + return 0; +} + +__WEAK int usbd_dfu_read(uint16_t value, const uint8_t *data, uint16_t length, uint16_t *actual_length) +{ + return 0; +} \ No newline at end of file diff --git a/kernel/cherryusb/class/dfu/usbd_dfu.h b/kernel/cherryusb/class/dfu/usbd_dfu.h new file mode 100644 index 0000000..cec005c --- /dev/null +++ b/kernel/cherryusb/class/dfu/usbd_dfu.h @@ -0,0 +1,29 @@ +/* + * Copyright (c) 2022 ~ 2026, sakumisu + * + * SPDX-License-Identifier: Apache-2.0 + */ +#ifndef USBD_DFU_H +#define USBD_DFU_H + +#include "usb_dfu.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* Init dfu interface driver */ +struct usbd_interface *usbd_dfu_init_intf(struct usbd_interface *intf); +uint8_t usbd_dfu_get_state(void); + +void usbd_dfu_begin_load(void); +void usbd_dfu_end_load(void); +void usbd_dfu_reset(void); +int usbd_dfu_write(uint16_t value, const uint8_t *data, uint16_t length); +int usbd_dfu_read(uint16_t value, const uint8_t *data, uint16_t length, uint16_t *actual_length); + +#ifdef __cplusplus +} +#endif + +#endif /* USBD_DFU_H */ diff --git a/kernel/cherryusb/class/gamepad/usb_gamepad.h b/kernel/cherryusb/class/gamepad/usb_gamepad.h new file mode 100644 index 0000000..28e2e64 --- /dev/null +++ b/kernel/cherryusb/class/gamepad/usb_gamepad.h @@ -0,0 +1,224 @@ +/* + * Copyright (c) 2026, sakumisu + * + * SPDX-License-Identifier: Apache-2.0 + */ +#ifndef USB_GAMEPAD_H +#define USB_GAMEPAD_H + +#include "usb_hid.h" + +/* + * GAMEPAD BUTTON LAYOUT + * + * ____________________________ __ + * / [__L2__] [__R2__] \ | + * / [__ L1 __] [__ R1 __] \ | Triggers + * __/________________________________\__ __| + * / _ \ | + * / /\ __ (B4) \ | + * / || __ |A1| __ _ _ \ | Main Pad + * | <===DP===> |S1| |S2| (B3) -|- (B2)| | + * \ || ¯¯ ¯¯ _ / | + * /\ \/ / \ / \ (B1) /\ __| + * / \________ | LS | ____ | RS | _______/ \ | + * | / \ \___/ / \ \___/ / \ | | Sticks + * | / \_____/ \_____/ \ | __| + * | / L3 R3 \ | + * \_____/ \_____/ + * + * |________|______| |______|___________| + * D-Pad Left Right Face + * Stick Stick Buttons + * + * Extended: A2=Touchpad/Capture A3=Mute L4/R4=Paddles + */ + +// W3C Gamepad API standard button order +// Bit position = W3C button index (trivial conversion: 1 << index) +// +// Gamepad XInput Switch PS3/4/5 DInput +// ------ ------ ------ ------- ------ + +// Face buttons (right cluster) +#define USB_GAMEPAD_BUTTON_B1 (1 << 0) // A B Cross 2 +#define USB_GAMEPAD_BUTTON_B2 (1 << 1) // B A Circle 3 +#define USB_GAMEPAD_BUTTON_B3 (1 << 2) // X Y Square 1 +#define USB_GAMEPAD_BUTTON_B4 (1 << 3) // Y X Triangle 4 + +// Shoulder buttons +#define USB_GAMEPAD_BUTTON_L1 (1 << 4) // LB L L1 5 +#define USB_GAMEPAD_BUTTON_R1 (1 << 5) // RB R R1 6 +#define USB_GAMEPAD_BUTTON_L2 (1 << 6) // LT ZL L2 7 +#define USB_GAMEPAD_BUTTON_R2 (1 << 7) // RT ZR R2 8 + +// Center cluster +#define USB_GAMEPAD_BUTTON_S1 (1 << 8) // Back - Select 9 +#define USB_GAMEPAD_BUTTON_S2 (1 << 9) // Start + Start 10 + +// Stick clicks +#define USB_GAMEPAD_BUTTON_L3 (1 << 10) // LS LS L3 11 +#define USB_GAMEPAD_BUTTON_R3 (1 << 11) // RS RS R3 12 + +// D-pad +#define USB_GAMEPAD_BUTTON_DU (1 << 12) // D-Up D-Up D-Up Hat +#define USB_GAMEPAD_BUTTON_DD (1 << 13) // D-Down D-Down D-Down Hat +#define USB_GAMEPAD_BUTTON_DL (1 << 14) // D-Left D-Left D-Left Hat +#define USB_GAMEPAD_BUTTON_DR (1 << 15) // D-Right D-Right D-Right Hat + +// Auxiliary +#define USB_GAMEPAD_BUTTON_A1 (1 << 16) // Guide Home PS 13 +#define USB_GAMEPAD_BUTTON_A2 (1 << 17) // - Capture Touchpad 14 +#define USB_GAMEPAD_BUTTON_A3 (1 << 18) // - - Mute - +#define USB_GAMEPAD_BUTTON_A4 (1 << 19) // - - - - + +// Paddles (extended) +#define USB_GAMEPAD_BUTTON_L4 (1 << 20) // P1 - - - +#define USB_GAMEPAD_BUTTON_R4 (1 << 21) // P2 - - - + +#define XINPUT_VID 0x045E // Microsoft +#define XINPUT_PID 0x028E // Xbox 360 Controller +#define XINPUT_BCD_DEVICE 0x0114 // v1.14 + +/* XInput (Xbox 360) USB */ + +// XInput Interface Class/Subclass/Protocol +#define XINPUT_INTERFACE_CLASS 0xFF +#define XINPUT_INTERFACE_SUBCLASS 0x5D +#define XINPUT_INTERFACE_PROTOCOL 0x01 + +#define XINPUT_BUTTON_MASK_UP (1U << 0) +#define XINPUT_BUTTON_MASK_DOWN (1U << 1) +#define XINPUT_BUTTON_MASK_LEFT (1U << 2) +#define XINPUT_BUTTON_MASK_RIGHT (1U << 3) +#define XINPUT_BUTTON_MASK_START (1U << 4) +#define XINPUT_BUTTON_MASK_BACK (1U << 5) +#define XINPUT_BUTTON_MASK_L3 (1U << 6) +#define XINPUT_BUTTON_MASK_R3 (1U << 7) +#define XINPUT_BUTTON_MASK_LB (1U << 8) +#define XINPUT_BUTTON_MASK_RB (1U << 9) +#define XINPUT_BUTTON_MASK_GUIDE (1U << 10) +//#define XINPUT_BUTTON_MASK_UNUSED (1U << 11) +#define XINPUT_BUTTON_MASK_A (1U << 12) +#define XINPUT_BUTTON_MASK_B (1U << 13) +#define XINPUT_BUTTON_MASK_X (1U << 14) +#define XINPUT_BUTTON_MASK_Y (1U << 15) + +// LED patterns for report_id 0x01 +#define XINPUT_LED_OFF 0x00 +#define XINPUT_LED_BLINK 0x01 +#define XINPUT_LED_FLASH_1 0x02 +#define XINPUT_LED_FLASH_2 0x03 +#define XINPUT_LED_FLASH_3 0x04 +#define XINPUT_LED_FLASH_4 0x05 +#define XINPUT_LED_ON_1 0x06 +#define XINPUT_LED_ON_2 0x07 +#define XINPUT_LED_ON_3 0x08 +#define XINPUT_LED_ON_4 0x09 +#define XINPUT_LED_ROTATE 0x0A +#define XINPUT_LED_BLINK_SLOW 0x0B +#define XINPUT_LED_BLINK_SLOW_1 0x0C +#define XINPUT_LED_BLINK_SLOW_2 0x0D + +struct xinput_in_report { + uint8_t report_id; /* Always 0x00 */ + uint8_t report_size; /* Always 0x14 (20) */ + uint16_t buttons; /* DPAD, Start, Back, L3, R3, LB, RB, Guide, A, B, X, Y */ + uint8_t lt; /* Left trigger (0-255) */ + uint8_t rt; /* Right trigger (0-255) */ + int16_t lx; /* Left stick X (-32768 to 32767) */ + int16_t ly; /* Left stick Y (-32768 to 32767) */ + int16_t rx; /* Right stick X (-32768 to 32767) */ + int16_t ry; /* Right stick Y (-32768 to 32767) */ + uint8_t reserved[6]; /* Reserved/padding */ +} __PACKED; + +struct xinput_out_report { + uint8_t report_id; // 0x00 = rumble, 0x01 = LED + uint8_t report_size; // 0x08 + uint8_t led; // LED pattern (0x00 for rumble) + uint8_t rumble_l; // Left motor (large, 0-255) + uint8_t rumble_r; // Right motor (small, 0-255) + uint8_t reserved[3]; // Padding +} __PACKED; + +// clang-format off +#define XINPUT_DESCRIPTOR_LEN (9 + 16 + 7 + 7) + +#define XINPUT_DESCRIPTOR_INIT(bInterfaceNumber, out_ep, in_ep) \ + USB_INTERFACE_DESCRIPTOR_INIT(bInterfaceNumber, 0x00, 0x02, 0xff, 0x5d, 0x01, 0x00), /* XInput proprietary descriptor (0x21) */ \ + 16, 0x21, 0x00, 0x01, 0x01, 0x24, in_ep, 0x14, 0x03, 0x00, 0x03, 0x13, out_ep, 0x00, 0x03, 0x00, \ + USB_ENDPOINT_DESCRIPTOR_INIT(in_ep, 0x03, 32, 0x01), \ + USB_ENDPOINT_DESCRIPTOR_INIT(out_ep, 0x03, 32, 0x08) +// clang-format on + +#define SWITCH_VID 0x0F0D // 0x057E Nintendo Pro Controller +#define SWITCH_PID 0x0092 // 0x2009 +#define SWITCH_BCD_DEVICE 0x0100 // v1.00 + +// Button masks (16-bit) +#define SWITCH_MASK_Y (1U << 0) +#define SWITCH_MASK_B (1U << 1) +#define SWITCH_MASK_A (1U << 2) +#define SWITCH_MASK_X (1U << 3) +#define SWITCH_MASK_L (1U << 4) +#define SWITCH_MASK_R (1U << 5) +#define SWITCH_MASK_ZL (1U << 6) +#define SWITCH_MASK_ZR (1U << 7) +#define SWITCH_MASK_MINUS (1U << 8) +#define SWITCH_MASK_PLUS (1U << 9) +#define SWITCH_MASK_L3 (1U << 10) +#define SWITCH_MASK_R3 (1U << 11) +#define SWITCH_MASK_HOME (1U << 12) +#define SWITCH_MASK_CAPTURE (1U << 13) + +// D-pad / Hat switch values +#define SWITCH_HAT_UP 0x00 +#define SWITCH_HAT_UP_RIGHT 0x01 +#define SWITCH_HAT_RIGHT 0x02 +#define SWITCH_HAT_DOWN_RIGHT 0x03 +#define SWITCH_HAT_DOWN 0x04 +#define SWITCH_HAT_DOWN_LEFT 0x05 +#define SWITCH_HAT_LEFT 0x06 +#define SWITCH_HAT_UP_LEFT 0x07 +#define SWITCH_HAT_CENTER 0x08 + +// Analog stick range +#define SWITCH_JOYSTICK_MIN 0x00 +#define SWITCH_JOYSTICK_MID 0x80 +#define SWITCH_JOYSTICK_MAX 0xFF + +struct switch_in_report { + uint16_t buttons; // 16 button bits + uint8_t hat; // D-pad (hat switch, 0-8) + uint8_t lx; // Left stick X (0-255, 128 = center) + uint8_t ly; // Left stick Y (0-255, 128 = center) + uint8_t rx; // Right stick X (0-255, 128 = center) + uint8_t ry; // Right stick Y (0-255, 128 = center) + uint8_t vendor; // Vendor-specific byte +} __PACKED; + +struct switch_out_report { + uint8_t data[8]; // Vendor-specific rumble data +} __PACKED; + +#define HID_SWITCH_REPORT_DESC_SIZE 86 + +// clang-format off +#define SWITCH_DESCRIPTOR_LEN HID_CUSTOM_INOUT_DESCRIPTOR_LEN + +#define SWITCH_DESCRIPTOR_INIT(bInterfaceNumber, out_ep, in_ep) \ + HID_CUSTOM_INOUT_DESCRIPTOR_INIT(bInterfaceNumber, 0x00, HID_SWITCH_REPORT_DESC_SIZE, out_ep, in_ep, 64, 0x01) +// clang-format on + +struct usb_gamepad_report { + uint32_t buttons; + uint8_t lt; + uint8_t rt; + uint8_t lx; + uint8_t ly; + uint8_t rx; + uint8_t ry; +}; + +#endif /* USB_GAMEPAD_H */ \ No newline at end of file diff --git a/kernel/cherryusb/class/gamepad/usbd_gamepad.c b/kernel/cherryusb/class/gamepad/usbd_gamepad.c new file mode 100644 index 0000000..37eb040 --- /dev/null +++ b/kernel/cherryusb/class/gamepad/usbd_gamepad.c @@ -0,0 +1,209 @@ +/* + * Copyright (c) 2026, sakumisu + * + * SPDX-License-Identifier: Apache-2.0 + */ +#include "usbd_core.h" +#include "usbd_hid.h" +#include "usbd_gamepad.h" + +USB_NOCACHE_RAM_SECTION USB_MEM_ALIGNX uint8_t gamepad_report_buffer[64]; + +static int xinput_vendor_class_request_handler(uint8_t busid, struct usb_setup_packet *setup, uint8_t **data, uint32_t *len) +{ + struct xinput_in_report xinput_report; + + memset(&xinput_report, 0, sizeof(struct xinput_in_report)); + xinput_report.report_size = 20; + + memcpy(*data, &xinput_report, sizeof(struct xinput_in_report)); + *len = sizeof(struct xinput_in_report); + return 0; +} + +int usbd_gamepad_xinput_send_report(uint8_t ep, struct usb_gamepad_report *report) +{ + struct xinput_in_report *xinput_report; + + xinput_report = (struct xinput_in_report *)gamepad_report_buffer; + memset(xinput_report, 0, sizeof(struct xinput_in_report)); + xinput_report->report_size = 20; + + if (report->buttons & USB_GAMEPAD_BUTTON_DU) + xinput_report->buttons |= XINPUT_BUTTON_MASK_UP; + if (report->buttons & USB_GAMEPAD_BUTTON_DD) + xinput_report->buttons |= XINPUT_BUTTON_MASK_DOWN; + if (report->buttons & USB_GAMEPAD_BUTTON_DL) + xinput_report->buttons |= XINPUT_BUTTON_MASK_LEFT; + if (report->buttons & USB_GAMEPAD_BUTTON_DR) + xinput_report->buttons |= XINPUT_BUTTON_MASK_RIGHT; + if (report->buttons & USB_GAMEPAD_BUTTON_S2) + xinput_report->buttons |= XINPUT_BUTTON_MASK_START; + if (report->buttons & USB_GAMEPAD_BUTTON_S1) + xinput_report->buttons |= XINPUT_BUTTON_MASK_BACK; + if (report->buttons & USB_GAMEPAD_BUTTON_L3) + xinput_report->buttons |= XINPUT_BUTTON_MASK_L3; + if (report->buttons & USB_GAMEPAD_BUTTON_R3) + xinput_report->buttons |= XINPUT_BUTTON_MASK_R3; + if (report->buttons & USB_GAMEPAD_BUTTON_L1) + xinput_report->buttons |= XINPUT_BUTTON_MASK_LB; + if (report->buttons & USB_GAMEPAD_BUTTON_R1) + xinput_report->buttons |= XINPUT_BUTTON_MASK_RB; + if (report->buttons & USB_GAMEPAD_BUTTON_A1) + xinput_report->buttons |= XINPUT_BUTTON_MASK_GUIDE; + if (report->buttons & USB_GAMEPAD_BUTTON_B1) + xinput_report->buttons |= XINPUT_BUTTON_MASK_A; + if (report->buttons & USB_GAMEPAD_BUTTON_B2) + xinput_report->buttons |= XINPUT_BUTTON_MASK_B; + if (report->buttons & USB_GAMEPAD_BUTTON_B3) + xinput_report->buttons |= XINPUT_BUTTON_MASK_X; + if (report->buttons & USB_GAMEPAD_BUTTON_B4) + xinput_report->buttons |= XINPUT_BUTTON_MASK_Y; + + // Analog triggers (0-255), fall back to digital if analog is 0 but button pressed + xinput_report->lt = report->lt; + xinput_report->rt = report->rt; + if (xinput_report->lt == 0 && (report->buttons & USB_GAMEPAD_BUTTON_L2)) + xinput_report->lt = 0xFF; + if (xinput_report->rt == 0 && (report->buttons & USB_GAMEPAD_BUTTON_R2)) + xinput_report->rt = 0xFF; + + return usbd_ep_start_write(0, ep, gamepad_report_buffer, sizeof(struct xinput_in_report)); +} + +// Convert gamepad dpad mask to switch hat value +static uint8_t convert_dpad_to_switch_hat(uint32_t buttons) +{ + // Joypad uses active-high (1 = pressed) + uint8_t up = (buttons & USB_GAMEPAD_BUTTON_DU) ? 1 : 0; + uint8_t down = (buttons & USB_GAMEPAD_BUTTON_DD) ? 1 : 0; + uint8_t left = (buttons & USB_GAMEPAD_BUTTON_DL) ? 1 : 0; + uint8_t right = (buttons & USB_GAMEPAD_BUTTON_DR) ? 1 : 0; + + if (up && right) + return SWITCH_HAT_UP_RIGHT; + if (up && left) + return SWITCH_HAT_UP_LEFT; + if (down && right) + return SWITCH_HAT_DOWN_RIGHT; + if (down && left) + return SWITCH_HAT_DOWN_LEFT; + if (up) + return SWITCH_HAT_UP; + if (down) + return SWITCH_HAT_DOWN; + if (left) + return SWITCH_HAT_LEFT; + if (right) + return SWITCH_HAT_RIGHT; + + return SWITCH_HAT_CENTER; +} + +int usbd_gamepad_switch_send_report(uint8_t ep, struct usb_gamepad_report *report) +{ + struct switch_in_report *switch_report; + + switch_report = (struct switch_in_report *)gamepad_report_buffer; + memset(switch_report, 0, sizeof(struct switch_in_report)); + + if (report->buttons & USB_GAMEPAD_BUTTON_S1) + switch_report->buttons |= SWITCH_MASK_MINUS; + if (report->buttons & USB_GAMEPAD_BUTTON_S2) + switch_report->buttons |= SWITCH_MASK_PLUS; + if (report->buttons & USB_GAMEPAD_BUTTON_L1) + switch_report->buttons |= SWITCH_MASK_L; + if (report->buttons & USB_GAMEPAD_BUTTON_R1) + switch_report->buttons |= SWITCH_MASK_R; + if (report->buttons & USB_GAMEPAD_BUTTON_L2) + switch_report->buttons |= SWITCH_MASK_ZL; + if (report->buttons & USB_GAMEPAD_BUTTON_R2) + switch_report->buttons |= SWITCH_MASK_ZR; + if (report->buttons & USB_GAMEPAD_BUTTON_L3) + switch_report->buttons |= SWITCH_MASK_L3; + if (report->buttons & USB_GAMEPAD_BUTTON_R3) + switch_report->buttons |= SWITCH_MASK_R3; + if (report->buttons & USB_GAMEPAD_BUTTON_A1) + switch_report->buttons |= SWITCH_MASK_HOME; + if (report->buttons & USB_GAMEPAD_BUTTON_A2) + switch_report->buttons |= SWITCH_MASK_CAPTURE; + if (report->buttons & USB_GAMEPAD_BUTTON_B1) + switch_report->buttons |= SWITCH_MASK_B; + if (report->buttons & USB_GAMEPAD_BUTTON_B2) + switch_report->buttons |= SWITCH_MASK_A; + if (report->buttons & USB_GAMEPAD_BUTTON_B3) + switch_report->buttons |= SWITCH_MASK_Y; + if (report->buttons & USB_GAMEPAD_BUTTON_B4) + switch_report->buttons |= SWITCH_MASK_X; + + switch_report->hat = convert_dpad_to_switch_hat(report->buttons); + + // Analog sticks (HID convention: 0=up, 255=down - no inversion needed) + switch_report->lx = report->lx; + switch_report->ly = report->ly; + switch_report->rx = report->rx; + switch_report->ry = report->ry; + + switch_report->vendor = 0; + + return usbd_ep_start_write(0, ep, gamepad_report_buffer, sizeof(struct switch_in_report)); +} + +struct usbd_interface *usbd_gamepad_xinput_init_intf(struct usbd_interface *intf) +{ + intf->class_interface_handler = NULL; + intf->class_endpoint_handler = NULL; + intf->vendor_handler = xinput_vendor_class_request_handler; + intf->notify_handler = NULL; + + return intf; +} + +static const uint8_t hid_switch_report_desc[HID_SWITCH_REPORT_DESC_SIZE] = { + 0x05, 0x01, // Usage Page (Generic Desktop Ctrls) + 0x09, 0x05, // Usage (Game Pad) + 0xA1, 0x01, // Collection (Application) + 0x15, 0x00, // Logical Minimum (0) + 0x25, 0x01, // Logical Maximum (1) + 0x35, 0x00, // Physical Minimum (0) + 0x45, 0x01, // Physical Maximum (1) + 0x75, 0x01, // Report Size (1) + 0x95, 0x10, // Report Count (16) + 0x05, 0x09, // Usage Page (Button) + 0x19, 0x01, // Usage Minimum (Button 1) + 0x29, 0x10, // Usage Maximum (Button 16) + 0x81, 0x02, // Input (Data,Var,Abs) + 0x05, 0x01, // Usage Page (Generic Desktop Ctrls) + 0x25, 0x07, // Logical Maximum (7) + 0x46, 0x3B, 0x01, // Physical Maximum (315) + 0x75, 0x04, // Report Size (4) + 0x95, 0x01, // Report Count (1) + 0x65, 0x14, // Unit (Eng Rot:Angular Pos) + 0x09, 0x39, // Usage (Hat switch) + 0x81, 0x42, // Input (Data,Var,Abs,Null) + 0x65, 0x00, // Unit (None) + 0x95, 0x01, // Report Count (1) + 0x81, 0x01, // Input (Const) - 4-bit padding + 0x26, 0xFF, 0x00, // Logical Maximum (255) + 0x46, 0xFF, 0x00, // Physical Maximum (255) + 0x09, 0x30, // Usage (X) - Left Stick X + 0x09, 0x31, // Usage (Y) - Left Stick Y + 0x09, 0x32, // Usage (Z) - Right Stick X + 0x09, 0x35, // Usage (Rz) - Right Stick Y + 0x75, 0x08, // Report Size (8) + 0x95, 0x04, // Report Count (4) + 0x81, 0x02, // Input (Data,Var,Abs) + 0x06, 0x00, 0xFF, // Usage Page (Vendor Defined) + 0x09, 0x20, // Usage (0x20) + 0x95, 0x01, // Report Count (1) + 0x81, 0x02, // Input (Data,Var,Abs) - Vendor byte + 0x0A, 0x21, 0x26, // Usage (0x2621) + 0x95, 0x08, // Report Count (8) + 0x91, 0x02, // Output (Data,Var,Abs) - Rumble + 0xC0, // End Collection +}; + +struct usbd_interface *usbd_gamepad_switch_init_intf(struct usbd_interface *intf) +{ + return usbd_hid_init_intf(0, intf, hid_switch_report_desc, HID_SWITCH_REPORT_DESC_SIZE); +} \ No newline at end of file diff --git a/kernel/cherryusb/class/gamepad/usbd_gamepad.h b/kernel/cherryusb/class/gamepad/usbd_gamepad.h new file mode 100644 index 0000000..8f4f20a --- /dev/null +++ b/kernel/cherryusb/class/gamepad/usbd_gamepad.h @@ -0,0 +1,22 @@ +/* + * Copyright (c) 2026, sakumisu + * + * SPDX-License-Identifier: Apache-2.0 + */ +#ifndef USBD_GAMEPAD_H +#define USBD_GAMEPAD_H + +#include "usb_gamepad.h" + +#define USBD_GAMEPAD_MODE_XINPUT 0 +#define USBD_GAMEPAD_MODE_SWITCH 1 +#define USBD_GAMEPAD_MODE_XBOXONE 2 +#define USBD_GAMEPAD_MODE_PS4 3 + +struct usbd_interface *usbd_gamepad_xinput_init_intf(struct usbd_interface *intf); +struct usbd_interface *usbd_gamepad_switch_init_intf(struct usbd_interface *intf); + +int usbd_gamepad_xinput_send_report(uint8_t ep, struct usb_gamepad_report *report); +int usbd_gamepad_switch_send_report(uint8_t ep, struct usb_gamepad_report *report); + +#endif /* USBD_GAMEPAD_H */ \ No newline at end of file diff --git a/kernel/cherryusb/class/hid/usb_hid.h b/kernel/cherryusb/class/hid/usb_hid.h new file mode 100644 index 0000000..b2bd571 --- /dev/null +++ b/kernel/cherryusb/class/hid/usb_hid.h @@ -0,0 +1,652 @@ +/* + * Copyright (c) 2022, sakumisu + * + * SPDX-License-Identifier: Apache-2.0 + */ +#ifndef USB_HID_H +#define USB_HID_H + +/* Subclass codes (HID 4.2) */ +#define HID_SUBCLASS_NONE 0 /* No subclass */ +#define HID_SUBCLASS_BOOTIF 1 /* Boot Interface Subclass */ + +/* HID Protocol Codes (HID 4.3) */ +#define HID_PROTOCOL_NONE 0x00 +#define HID_PROTOCOL_BOOT 0x00 +#define HID_PROTOCOL_KEYBOARD 0x01 +#define HID_PROTOCOL_REPORT 0x01 +#define HID_PROTOCOL_MOUSE 0x02 + +/* HID Class Descriptor Types (HID 7.1) */ +#define HID_DESCRIPTOR_TYPE_HID 0x21 +#define HID_DESCRIPTOR_TYPE_HID_REPORT 0x22 +#define HID_DESCRIPTOR_TYPE_HID_PHYSICAL 0x23 + +/* HID Class Specific Requests (HID 7.2) */ +#define HID_REQUEST_GET_REPORT 0x01 +#define HID_REQUEST_GET_IDLE 0x02 +#define HID_REQUEST_GET_PROTOCOL 0x03 +#define HID_REQUEST_SET_REPORT 0x09 +#define HID_REQUEST_SET_IDLE 0x0A +#define HID_REQUEST_SET_PROTOCOL 0x0B + +/* Report Type (MS byte of wValue for GET_REPORT) (HID 7.2.1) */ +#define HID_REPORT_INPUT 0x01 +#define HID_REPORT_OUTPUT 0x02 +#define HID_REPORT_FEATURE 0x03 + +/* HID Descriptor */ + +#define HID_COUNTRY_NONE 0x00 /* Not Supported */ +#define HID_COUNTRY_ARABIC 0x01 /* Arabic */ +#define HID_COUNTRY_BELGIAN 0x02 /* Belgian */ +#define HID_COUNTRY_CANADA 0x03 /* Canadian-Bilingual */ +#define HID_COUNTRY_CANADRFR 0x04 /* Canadian-French */ +#define HID_COUNTRY_CZECH 0x05 /* Czech Republic */ +#define HID_COUNTRY_DANISH 0x06 /* Danish */ +#define HID_COUNTRY_FINNISH 0x07 /* Finnish */ +#define HID_COUNTRY_FRENCH 0x08 /* French */ +#define HID_COUNTRY_GERMAN 0x09 /* German */ +#define HID_COUNTRY_GREEK 0x10 /* Greek */ +#define HID_COUNTRY_HEBREW 0x11 /* Hebrew */ +#define HID_COUNTRY_HUNGARY 0x12 /* Hungary */ +#define HID_COUNTRY_ISO 0x13 /* International (ISO) */ +#define HID_COUNTRY_ITALIAN 0x14 /* Italian */ +#define HID_COUNTRY_JAPAN 0x15 /* Japan (Katakana) */ +#define HID_COUNTRY_KOREAN 0x16 /* Korean */ +#define HID_COUNTRY_LATINAM 0x17 /* Latin American */ +#define HID_COUNTRY_DUTCH 0x18 /* Netherlands/Dutch */ +#define HID_COUNTRY_NORWEGIAN 0x19 /* Norwegian */ +#define HID_COUNTRY_PERSIAN 0x20 /* Persian (Farsi) */ +#define HID_COUNTRY_POLAND 0x21 /* Poland */ +#define HID_COUNTRY_PORTUGUESE 0x22 /* Portuguese */ +#define HID_COUNTRY_RUSSIA 0x23 /* Russia */ +#define HID_COUNTRY_SLOVAKIA 0x24 /* Slovakia */ +#define HID_COUNTRY_SPANISH 0x25 /* Spanish */ +#define HID_COUNTRY_SWEDISH 0x26 /* Swedish */ +#define HID_COUNTRY_SWISSFR 0x27 /* Swiss/French */ +#define HID_COUNTRY_SWISSGR 0x28 /* Swiss/German */ +#define HID_COUNTRY_SWITZERLAND 0x29 /* Switzerland */ +#define HID_COUNTRY_TAIWAN 0x30 /* Taiwan */ +#define HID_COUNTRY_TURKISHQ 0x31 /* Turkish-Q */ +#define HID_COUNTRY_UK 0x32 /* UK */ +#define HID_COUNTRY_US 0x33 /* US */ +#define HID_COUNTRY_YUGOSLAVIA 0x34 /* Yugoslavia */ +#define HID_COUNTRY_TURKISHF 0x35 /* Turkish-F */ + +/* HID report See specification at + * https://www.usb.org/sites/default/files/hid1_11.pdf + * https://www.usb.org/sites/default/files/hut1_22.pdf + */ + +#define HID_SIZE_MASK (0x3 << 0) +#define HID_TYPE_MASK (0x3 << 2) +#define HID_TAG_MASK (0xF << 4) + +#define HID_ITEMTYPE_MAIN (0x0 << 2) +#define HID_ITEMTYPE_GLOBAL (0x1 << 2) +#define HID_ITEMTYPE_LOCAL (0x2 << 2) +#define HID_ITEMTYPE_LONG (0x3 << 2) + +/* Main Items (HID 6.2.2.4) */ +#define HID_MAINITEM_TAG_INPUT (0x08 << 4) +#define HID_MAINITEM_TAG_OUTPUT (0x09 << 4) +#define HID_MAINITEM_TAG_COLLECTION (0x0a << 4) +#define HID_MAINITEM_TAG_FEATURE (0x0b << 4) +#define HID_MAINITEM_TAG_ENDCOLLECTION (0x0c << 4) + +#define HID_MAINITEM_CONSTANT (1 << 0) /* Constant(1) vs Data(0) */ +#define HID_MAINITEM_VARIABLE (1 << 1) /* Variable(1) vs Array(0) */ +#define HID_MAINITEM_RELATIVE (1 << 2) /* Relative(1) vs Absolute(0) */ +#define HID_MAINITEM_WRAP (1 << 3) /* Wrap(1) vs No Wrap(0) */ +#define HID_MAINITEM_NONLINEAR (1 << 4) /* Non Linear(1) vs Linear(0) */ +#define HID_MAINITEM_NOPREFERRED (1 << 5) /* No Preferred (1) vs Preferred State(0) */ +#define HID_MAINITEM_NULLSTATE (1 << 6) /* Null state(1) vs No Null position(0) */ +#define HID_MAINITEM_VOLATILE (1 << 7) /* Volatile(1) vs Non volatile(0) */ +#define HID_MAINITEM_BUFFEREDBYTES (1 << 8) /* Buffered Bytes(1) vs Bit Field(0) */ + +#define HID_MAINITEM_COLLECTION_PHYSICAL 0x00 /* Physical (group of axes) */ +#define HID_MAINITEM_COLLECTION_APPL 0x01 /* Application (mouse, keyboard) */ +#define HID_MAINITEM_COLLECTION_LOGICAL 0x02 /* Logical (interrelated data) */ +#define HID_MAINITEM_COLLECTION_REPORT 0x03 /* Report */ +#define HID_MAINITEM_COLLECTION_ARRAY 0x04 /* Named Array */ +#define HID_MAINITEM_COLLECTION_SWITCH 0x05 /* Usage Switch */ +#define HID_MAINITEM_COLLECTION_MODIFIER 0x06 /* Usage Modifier */ + +/* Global Items (HID 6.2.2.7) */ +#define HID_GLOBALITEM_TAG_USAGE_PAGE (0x00 << 4) +#define HID_GLOBALITEM_TAG_LOGICAL_MIN (0x01 << 4) +#define HID_GLOBALITEM_TAG_LOGICAL_MAX (0x02 << 4) +#define HID_GLOBALITEM_TAG_PHYSICAL_MIN (0x03 << 4) +#define HID_GLOBALITEM_TAG_PHYSICAL_MAX (0x04 << 4) +#define HID_GLOBALITEM_TAG_UNIT_EXP (0x05 << 4) +#define HID_GLOBALITEM_TAG_UNIT (0x06 << 4) +#define HID_GLOBALITEM_TAG_REPORT_SIZE (0x07 << 4) +#define HID_GLOBALITEM_TAG_REPORT_ID (0x08 << 4) +#define HID_GLOBALITEM_TAG_REPORT_COUNT (0x09 << 4) +#define HID_GLOBALITEM_TAG_PUSH (0x0a << 4) +#define HID_GLOBALITEM_TAG_POP (0x0b << 4) + +/* Local Items (HID 6.2.2.8) */ +#define HID_LOCALITEM_TAG_USAGE (0x00 << 4) +#define HID_LOCALITEM_TAG_USAGE_MIN (0x01 << 4) +#define HID_LOCALITEM_TAG_USAGE_MAX (0x02 << 4) +#define HID_LOCALITEM_TAG_DESIG_INDEX (0x03 << 4) +#define HID_LOCALITEM_TAG_DESIG_MIN (0x04 << 4) +#define HID_LOCALITEM_TAG_DESIG_MAX (0x05 << 4) +/* No 6 in spec */ +#define HID_LOCALITEM_TAG_STRING_INDEX (0x07 << 4) +#define HID_LOCALITEM_TAG_STRING_MIN (0x08 << 4) +#define HID_LOCALITEM_TAG_STRING_MAX (0x09 << 4) +#define HID_LOCALITEM_TAG_DELIMITER (0x0a << 4) /* Also listed as reserved in spec! */ + +/* Usage pages (HuT 3) */ +#define HID_USAGE_PAGE_UNDEFINED 0x00 /* Undefined */ +#define HID_USAGE_PAGE_GENERIC_DESKTOP_CONTROLS 0x01 /* Generic Desktop Controls */ +#define HID_USAGE_PAGE_SIMULATION_CONTROLS 0x02 /* Simulation Controls */ +#define HID_USAGE_PAGE_VR_CONTROLS 0x03 /* VR Controls */ +#define HID_USAGE_PAGE_SPORT_CONTROLS 0x04 /* Sport Controls */ +#define HID_USAGE_PAGE_GAME_CONTROLS 0x05 /* Game Controls */ +#define HID_USAGE_PAGE_GENERIC_DEVICE_CONTROLS 0x06 /* Generic Device Controls */ +#define HID_USAGE_PAGE_KEYBOARD_KEYPAD 0x07 /* Keyboard/Keypad */ +#define HID_USAGE_PAGE_LED 0x08 /* LEDs */ +#define HID_USAGE_PAGE_BUTTON 0x09 /* Button */ +#define HID_USAGE_PAGE_ORDINAL 0x0a /* Ordinal */ +#define HID_USAGE_PAGE_TELEPHONY 0x0b /* Telephony */ +#define HID_USAGE_PAGE_CONSUMER 0x0c /* Consumer */ +#define HID_USAGE_PAGE_DIGITIZER 0x0d /* Digitizer */ +#define HID_USAGE_PAGE_HAPTICS /* 0x0e Reserved */ +#define HID_USAGE_PAGE_PID 0x0f /* PID Page Physical Interface Device */ +#define HID_USAGE_PAGE_UNICODE 0x10 /* Unicode */ +#define HID_USAGE_PAGE_SOC 0x11 /* Sensor Orientation Category */ +#define HID_USAGE_PAGE_EYE_AND_HEAD_TRACKER 0x12 /* Eye and Head Tracker */ + /* 0x13 Reserved */ +#define HID_USAGE_PAGE_ALPHA_DISPLAY 0x14 /* Alphanumeric Display */ + /* 0x15-3f Reserved */ +#define HID_USAGE_PAGE_MEDICAL 0x40 /* Medical Instruments */ +#define HID_USAGE_PAGE_BRAILLE_DISPLAY 0x41 /* Braille Display */ + /* 0x42-0x58 Reserved */ +#define HID_USAGE_PAGE_LIGHTING_AND_ILLUMINATION 0x59 /* Lighting and Illumination */ + /* 0x5a-0x7f Reserved */ +#define HID_USAGE_PAGE_USB_MONITOR 0x80 /* USB Monitor */ +#define HID_USAGE_PAGE_USB_ENUMERATED_VALUES 0x81 /* USB Enumerated Values */ +#define HID_USAGE_PAGE_VESA_VIRTUAL_CONTROLS 0x82 /* VESA Virtual Controls */ +#define HID_USAGE_PAGE_POWER_DEVICE 0x84 /* Power Device */ +#define HID_USAGE_PAGE_BATTERY_SYSTEM 0x85 /* Battery System */ +#define HID_USAGE_PAGE_BARCODE_SCANNER 0x8c /* Bar Code Scanner page */ +#define HID_USAGE_PAGE_SCALE 0x8d /* Scale page */ +#define HID_USAGE_PAGE_MSR 0x8e /* Magnetic Stripe Reading (MSR) Devices */ +#define HID_USAGE_PAGE_POS 0x8f /* Point of Sale devices */ +#define HID_USAGE_PAGE_CAMERA_CONTROL 0x90 /* Camera Control Page */ +#define HID_USAGE_PAGE_ARCADE 0x91 +#define HID_USAGE_PAGE_GAMING_DEVICE 0x92 +#define HID_USAGE_PAGE_FIDO_ALLIANCE 0xF1D0 +#define HID_USAGE_PAGE_VENDOR_PAGE_HBYTE 0xFF00 + +/* Modifier Keys (HID 8.3) */ +#define HID_MODIFIER_LCTRL (1 << 0) /* Left Ctrl */ +#define HID_MODIFIER_LSHIFT (1 << 1) /* Left Shift */ +#define HID_MODIFIER_LALT (1 << 2) /* Left Alt */ +#define HID_MODIFIER_LGUI (1 << 3) /* Left GUI */ +#define HID_MODIFIER_RCTRL (1 << 4) /* Right Ctrl */ +#define HID_MODIFIER_RSHIFT (1 << 5) /* Right Shift */ +#define HID_MODIFIER_RALT (1 << 6) /* Right Alt */ +#define HID_MODIFIER_RGUI (1 << 7) /* Right GUI */ + +/* Keyboard output report (1 byte) (HID B.1) */ +#define HID_KBD_OUTPUT_REPORT_NUMLOCK (1 << 0) +#define HID_KBD_OUTPUT_REPORT_CAPSLOCK (1 << 1) +#define HID_KBD_OUTPUT_REPORT_SCROLLLOCK (1 << 2) +#define HID_KBD_OUTPUT_REPORT_COMPOSE (1 << 3) +#define HID_KBD_OUTPUT_REPORT_KANA (1 << 4) + +/* Mouse input report (HID B.2) */ +#define HID_MOUSE_INPUT_REPORT_BUTTON1 (1 << 0) +#define HID_MOUSE_INPUT_REPORT_BUTTON2 (1 << 1) +#define HID_MOUSE_INPUT_REPORT_BUTTON3 (1 << 2) +#define HID_MOUSE_INPUT_REPORT_BUTTON_MASK (7) + +#define HID_MOUSE_INPUT_BUTTON_LEFT (1 << 0) +#define HID_MOUSE_INPUT_BUTTON_RIGHT (1 << 1) +#define HID_MOUSE_INPUT_BUTTON_MIDDLE (1 << 2) +#define HID_MOUSE_INPUT_BUTTON_BACKWARD (1 << 3) +#define HID_MOUSE_INPUT_BUTTON_FORWARD (1 << 4) + +/* Joystick input report (4 bytes) (HID D.1) */ +#define HID_JS_INPUT_REPORT_HATSWITCH_SHIFT (0) +#define HID_JS_INPUT_REPORT_HATSWITCH_MASK (15 << HID_JSIN_HATSWITCH_SHIFT) +#define HID_JS_INPUT_REPORT_BUTTON1 (1 << 4) +#define HID_JS_INPUT_REPORT_BUTTON2 (1 << 5) +#define HID_JS_INPUT_REPORT_BUTTON3 (1 << 6) +#define HID_JS_INPUT_REPORT_BUTTON4 (1 << 7) + +/* Generic Desktop Page Usage IDs (HuT 4) */ +#define HID_DESKTOP_USAGE_UNDEFINED 0x00 /* Undefined */ +#define HID_DESKTOP_USAGE_POINTER 0x01 /* Pointer */ +#define HID_DESKTOP_USAGE_MOUSE 0x02 /* Mouse */ + /* 0x03 Reserved */ +#define HID_DESKTOP_USAGE_JOYSTICK 0x04 /* Joystick */ +#define HID_DESKTOP_USAGE_GAMEPAD 0x05 /* Game Pad */ +#define HID_DESKTOP_USAGE_KEYBOARD 0x06 /* Keyboard */ +#define HID_DESKTOP_USAGE_KEYPAD 0x07 /* Keypad */ +#define HID_DESKTOP_USAGE_MULTIAXIS 0x08 /* Multi-axis Controller */ +#define HID_DESKTOP_USAGE_TABLET 0x09 /* Tablet PC System Controls */ + /* 0x0a-2f Reserved */ +#define HID_DESKTOP_USAGE_X 0x30 /* X */ +#define HID_DESKTOP_USAGE_Y 0x31 /* Y */ +#define HID_DESKTOP_USAGE_Z 0x32 /* Z */ +#define HID_DESKTOP_USAGE_RX 0x33 /* Rx */ +#define HID_DESKTOP_USAGE_RY 0x34 /* Ry */ +#define HID_DESKTOP_USAGE_RZ 0x35 /* Rz */ +#define HID_DESKTOP_USAGE_SLIDER 0x36 /* Slider */ +#define HID_DESKTOP_USAGE_DIAL 0x37 /* Dial */ +#define HID_DESKTOP_USAGE_WHEEL 0x38 /* Wheel */ +#define HID_DESKTOP_USAGE_HATSWITCH 0x39 /* Hat switch */ +#define HID_DESKTOP_USAGE_COUNTED 0x3a /* Counted Buffer */ +#define HID_DESKTOP_USAGE_BYTECOUNT 0x3b /* Byte Count */ +#define HID_DESKTOP_USAGE_MOTION 0x3c /* Motion Wakeup */ +#define HID_DESKTOP_USAGE_START 0x3d /* Start */ +#define HID_DESKTOP_USAGE_SELECT 0x3e /* Select */ + /* 0x3f Reserved */ +#define HID_DESKTOP_USAGE_VX 0x40 /* Vx */ +#define HID_DESKTOP_USAGE_VY 0x41 /* Vy */ +#define HID_DESKTOP_USAGE_VZ 0x42 /* Vz */ +#define HID_DESKTOP_USAGE_VBRX 0x43 /* Vbrx */ +#define HID_DESKTOP_USAGE_VBRY 0x44 /* Vbry */ +#define HID_DESKTOP_USAGE_VBRZ 0x45 /* Vbrz */ +#define HID_DESKTOP_USAGE_VNO 0x46 /* Vno */ +#define HID_DESKTOP_USAGE_FEATURE 0x47 /* Feature Notification */ +#define HID_DESKTOP_USAGE_RESOLUTION 0x48 /* Resolution Multiplier */ + /* 0x49-7f Reserved */ +#define HID_DESKTOP_USAGE_CONTROL 0x80 /* System Control */ +#define HID_DESKTOP_USAGE_POWERDOWN 0x81 /* System Power Down */ +#define HID_DESKTOP_USAGE_SLEEP 0x82 /* System Sleep */ +#define HID_DESKTOP_USAGE_WAKEUP 0x83 /* System Wake Up */ +#define HID_DESKTOP_USAGE_CONTEXT_MENU 0x84 /* System Context Menu */ +#define HID_DESKTOP_USAGE_MAIN_MENU 0x85 /* System Main Menu */ +#define HID_DESKTOP_USAGE_APP_MENU 0x86 /* System App Menu */ +#define HID_DESKTOP_USAGE_MENU_HELP 0x87 /* System Menu Help */ +#define HID_DESKTOP_USAGE_MENU_EXIT 0x88 /* System Menu Exit */ +#define HID_DESKTOP_USAGE_MENU_SELECT 0x89 /* System Menu Select */ +#define HID_DESKTOP_USAGE_MENU_RIGHT 0x8a /* System Menu Right */ +#define HID_DESKTOP_USAGE_MENU_LEFT 0x8b /* System Menu Left */ +#define HID_DESKTOP_USAGE_MENU_UP 0x8c /* System Menu Up */ +#define HID_DESKTOP_USAGE_MENU_DOWN 0x8d /* System Menu Down */ +#define HID_DESKTOP_USAGE_COLD_RESTART 0x8e /* System Cold Restart */ +#define HID_DESKTOP_USAGE_WARM_RESTART 0x8f /* System Warm Restart */ +#define HID_DESKTOP_USAGE_DPAD_UP 0x90 /* D-pad Up */ +#define HID_DESKTOP_USAGE_DPAD_DOWN 0x91 /* D-pad Down */ +#define HID_DESKTOP_USAGE_DPAD_RIGHT 0x92 /* D-pad Right */ +#define HID_DESKTOP_USAGE_DPAD_LEFT 0x93 /* D-pad Left */ + /* 0x94-9f Reserved */ +#define HID_DESKTOP_USAGE_DOCK 0xa0 /* System Dock */ +#define HID_DESKTOP_USAGE_UNDOCK 0xa1 /* System Undock */ +#define HID_DESKTOP_USAGE_SETUP 0xa2 /* System Setup */ +#define HID_DESKTOP_USAGE_BREAK 0xa3 /* System Break */ +#define HID_DESKTOP_USAGE_DEBUG_BREAK 0xa4 /* System Debugger Break */ +#define HID_DESKTOP_USAGE_APP_BREAK 0xa5 /* Application Break */ +#define HID_DESKTOP_USAGE_APP_DEBUG_BREAK 0xa6 /* Application Debugger Break */ +#define HID_DESKTOP_USAGE_MUTE 0xa7 /* System Speaker Mute */ +#define HID_DESKTOP_USAGE_HIBERNATE 0xa8 /* System Hibernate */ + /* 0xa9-af Reserved */ +#define HID_DESKTOP_USAGE_DISPLAY_INVERT 0xb0 /* System Display Invert */ +#define HID_DESKTOP_USAGE_DISPALY_INTERNAL 0xb1 /* System Display Internal */ +#define HID_DESKTOP_USAGE_DISPLAY_EXTERNAL 0xb2 /* System Display External */ +#define HID_DESKTOP_USAGE_DISPLAY_BOTH 0xb3 /* System Display Both */ +#define HID_DESKTOP_USAGE_DISPLAY_DUAL 0xb4 /* System Display Dual */ +#define HID_DESKTOP_USAGE_DISPLAY_TOGGLE 0xb5 /* System Display Toggle Int/Ext */ +#define HID_DESKTOP_USAGE_DISPLAY_SWAP 0xb6 /* System Display Swap */ +#define HID_DESKTOP_USAGE_ 0xb7 /* System Display LCD Autoscale */ + /* 0xb8-ffff Reserved */ + +/* Keyboard usage IDs (HuT 10) */ +#define HID_KBD_USAGE_NONE 0x00 /* Reserved (no event indicated) */ +#define HID_KBD_USAGE_ERRORROLLOVER 0x01 /* Keyboard ErrorRollOver */ +#define HID_KBD_USAGE_POSTFAIL 0x02 /* Keyboard POSTFail */ +#define HID_KBD_USAGE_ERRUNDEF 0x03 /* Keyboard ErrorUndefined */ +#define HID_KBD_USAGE_A 0x04 /* Keyboard a or A (B-Z follow) */ +#define HID_KBD_USAGE_1 0x1e /* Keyboard 1 (2-9 follow) */ +#define HID_KBD_USAGE_EXCLAM 0x1e /* Keyboard 1 and ! */ +#define HID_KBD_USAGE_AT 0x1f /* Keyboard 2 and @ */ +#define HID_KBD_USAGE_POUND 0x20 /* Keyboard 3 and # */ +#define HID_KBD_USAGE_DOLLAR 0x21 /* Keyboard 4 and $ */ +#define HID_KBD_USAGE_PERCENT 0x22 /* Keyboard 5 and % */ +#define HID_KBD_USAGE_CARAT 0x23 /* Keyboard 6 and ^ */ +#define HID_KBD_USAGE_AMPERSAND 0x24 /* Keyboard 7 and & */ +#define HID_KBD_USAGE_ASTERISK 0x25 /* Keyboard 8 and * */ +#define HID_KBD_USAGE_LPAREN 0x26 /* Keyboard 9 and ( */ +#define HID_KBD_USAGE_0 0x27 /* Keyboard 0 and ) */ +#define HID_KBD_USAGE_RPAREN 0x27 /* Keyboard 0 and ) */ +#define HID_KBD_USAGE_ENTER 0x28 /* Keyboard Return (ENTER) */ +#define HID_KBD_USAGE_ESCAPE 0x29 /* Keyboard ESCAPE */ +#define HID_KBD_USAGE_DELETE 0x2a /* Keyboard DELETE (Backspace) */ +#define HID_KBD_USAGE_TAB 0x2b /* Keyboard Tab */ +#define HID_KBD_USAGE_SPACE 0x2c /* Keyboard Spacebar */ +#define HID_KBD_USAGE_HYPHEN 0x2d /* Keyboard - and (underscore) */ +#define HID_KBD_USAGE_UNDERSCORE 0x2d /* Keyboard - and (underscore) */ +#define HID_KBD_USAGE_EQUAL 0x2e /* Keyboard = and + */ +#define HID_KBD_USAGE_PLUS 0x2e /* Keyboard = and + */ +#define HID_KBD_USAGE_LBRACKET 0x2f /* Keyboard [ and { */ +#define HID_KBD_USAGE_LBRACE 0x2f /* Keyboard [ and { */ +#define HID_KBD_USAGE_RBRACKET 0x30 /* Keyboard ] and } */ +#define HID_KBD_USAGE_RBRACE 0x30 /* Keyboard ] and } */ +#define HID_KBD_USAGE_BSLASH 0x31 /* Keyboard \ and | */ +#define HID_KBD_USAGE_VERTBAR 0x31 /* Keyboard \ and | */ +#define HID_KBD_USAGE_NONUSPOUND 0x32 /* Keyboard Non-US # and ~ */ +#define HID_KBD_USAGE_TILDE 0x32 /* Keyboard Non-US # and ~ */ +#define HID_KBD_USAGE_SEMICOLON 0x33 /* Keyboard ; and : */ +#define HID_KBD_USAGE_COLON 0x33 /* Keyboard ; and : */ +#define HID_KBD_USAGE_SQUOTE 0x34 /* Keyboard ' and " */ +#define HID_KBD_USAGE_DQUOUTE 0x34 /* Keyboard ' and " */ +#define HID_KBD_USAGE_GACCENT 0x35 /* Keyboard Grave Accent and Tilde */ +#define HID_KBD_USAGE_GTILDE 0x35 /* Keyboard Grave Accent and Tilde */ +#define HID_KBD_USAGE_COMMON 0x36 /* Keyboard , and < */ +#define HID_KBD_USAGE_LT 0x36 /* Keyboard , and < */ +#define HID_KBD_USAGE_PERIOD 0x37 /* Keyboard . and > */ +#define HID_KBD_USAGE_GT 0x37 /* Keyboard . and > */ +#define HID_KBD_USAGE_DIV 0x38 /* Keyboard / and ? */ +#define HID_KBD_USAGE_QUESTION 0x38 /* Keyboard / and ? */ +#define HID_KBD_USAGE_CAPSLOCK 0x39 /* Keyboard Caps Lock */ +#define HID_KBD_USAGE_F1 0x3a /* Keyboard F1 */ +#define HID_KBD_USAGE_F2 0x3b /* Keyboard F2 */ +#define HID_KBD_USAGE_F3 0x3c /* Keyboard F3 */ +#define HID_KBD_USAGE_F4 0x3d /* Keyboard F4 */ +#define HID_KBD_USAGE_F5 0x3e /* Keyboard F5 */ +#define HID_KBD_USAGE_F6 0x3f /* Keyboard F6 */ +#define HID_KBD_USAGE_F7 0x40 /* Keyboard F7 */ +#define HID_KBD_USAGE_F8 0x41 /* Keyboard F8 */ +#define HID_KBD_USAGE_F9 0x42 /* Keyboard F9 */ +#define HID_KBD_USAGE_F10 0x43 /* Keyboard F10 */ +#define HID_KBD_USAGE_F11 0x44 /* Keyboard F11 */ +#define HID_KBD_USAGE_F12 0x45 /* Keyboard F12 */ +#define HID_KBD_USAGE_PRINTSCN 0x46 /* Keyboard PrintScreen */ +#define HID_KBD_USAGE_SCROLLLOCK 0x47 /* Keyboard Scroll Lock */ +#define HID_KBD_USAGE_PAUSE 0x48 /* Keyboard Pause */ +#define HID_KBD_USAGE_INSERT 0x49 /* Keyboard Insert */ +#define HID_KBD_USAGE_HOME 0x4a /* Keyboard Home */ +#define HID_KBD_USAGE_PAGEUP 0x4b /* Keyboard PageUp */ +#define HID_KBD_USAGE_DELFWD 0x4c /* Keyboard Delete Forward */ +#define HID_KBD_USAGE_END 0x4d /* Keyboard End */ +#define HID_KBD_USAGE_PAGEDOWN 0x4e /* Keyboard PageDown */ +#define HID_KBD_USAGE_RIGHT 0x4f /* eyboard RightArrow */ +#define HID_KBD_USAGE_LEFT 0x50 /* Keyboard LeftArrow */ +#define HID_KBD_USAGE_DOWN 0x51 /* Keyboard DownArrow */ +#define HID_KBD_USAGE_UP 0x52 /* Keyboard UpArrow */ +#define HID_KBD_USAGE_KPDNUMLOCK 0x53 /* Keypad Num Lock and Clear */ +#define HID_KBD_USAGE_KPDNUMLOCKCLEAR 0x53 /* Keypad Num Lock and Clear */ +#define HID_KBD_USAGE_KPDDIV 0x54 /* Keypad / */ +#define HID_KBD_USAGE_KPDMUL 0x55 /* Keypad * */ +#define HID_KBD_USAGE_KPDHMINUS 0x56 /* Keypad - */ +#define HID_KBD_USAGE_KPDPLUS 0x57 /* Keypad + */ +#define HID_KBD_USAGE_KPDEMTER 0x58 /* Keypad ENTER */ +#define HID_KBD_USAGE_KPD1 0x59 /* Keypad 1 (2-9 follow) */ +#define HID_KBD_USAGE_KPDEND 0x59 /* Keypad 1 and End */ +#define HID_KBD_USAGE_KPDDOWN 0x5a /* Keypad 2 and Down Arrow */ +#define HID_KBD_USAGE_KPDPAGEDN 0x5b /* Keypad 3 and PageDn */ +#define HID_KBD_USAGE_KPDLEFT 0x5c /* Keypad 4 and Left Arrow */ +#define HID_KBD_USAGE_KPDRIGHT 0x5e /* Keypad 6 and Right Arrow */ +#define HID_KBD_USAGE_KPDHOME 0x5f /* Keypad 7 and Home */ +#define HID_KBD_USAGE_KPDUP 0x60 /* Keypad 8 and Up Arrow */ +#define HID_KBD_USAGE_KPDPAGEUP 0x61 /* Keypad 9 and PageUp */ +#define HID_KBD_USAGE_KPD0 0x62 /* Keypad 0 and Insert */ +#define HID_KBD_USAGE_KPDINSERT 0x62 /* Keypad 0 and Insert */ +#define HID_KBD_USAGE_KPDDECIMALPT 0x63 /* Keypad . and Delete */ +#define HID_KBD_USAGE_KPDDELETE 0x63 /* Keypad . and Delete */ +#define HID_KBD_USAGE_NONSLASH 0x64 /* Keyboard Non-US \ and | */ +#define HID_KBD_USAGE_NONUSVERT 0x64 /* Keyboard Non-US \ and | */ +#define HID_KBD_USAGE_APPLICATION 0x65 /* Keyboard Application */ +#define HID_KBD_USAGE_POWER 0x66 /* Keyboard Power */ +#define HID_KBD_USAGE_KPDEQUAL 0x67 /* Keypad = */ +#define HID_KBD_USAGE_F13 0x68 /* Keyboard F13 */ +#define HID_KBD_USAGE_F14 0x69 /* Keyboard F14 */ +#define HID_KBD_USAGE_F15 0x6a /* Keyboard F15 */ +#define HID_KBD_USAGE_F16 0x6b /* Keyboard F16 */ +#define HID_KBD_USAGE_F17 0x6c /* Keyboard F17 */ +#define HID_KBD_USAGE_F18 0x6d /* Keyboard F18 */ +#define HID_KBD_USAGE_F19 0x6e /* Keyboard F19 */ +#define HID_KBD_USAGE_F20 0x6f /* Keyboard F20 */ +#define HID_KBD_USAGE_F21 0x70 /* Keyboard F21 */ +#define HID_KBD_USAGE_F22 0x71 /* Keyboard F22 */ +#define HID_KBD_USAGE_F23 0x72 /* Keyboard F23 */ +#define HID_KBD_USAGE_F24 0x73 /* Keyboard F24 */ +#define HID_KBD_USAGE_EXECUTE 0x74 /* Keyboard Execute */ +#define HID_KBD_USAGE_HELP 0x75 /* Keyboard Help */ +#define HID_KBD_USAGE_MENU 0x76 /* Keyboard Menu */ +#define HID_KBD_USAGE_SELECT 0x77 /* Keyboard Select */ +#define HID_KBD_USAGE_STOP 0x78 /* Keyboard Stop */ +#define HID_KBD_USAGE_AGAIN 0x79 /* Keyboard Again */ +#define HID_KBD_USAGE_UNDO 0x7a /* Keyboard Undo */ +#define HID_KBD_USAGE_CUT 0x7b /* Keyboard Cut */ +#define HID_KBD_USAGE_COPY 0x7c /* Keyboard Copy */ +#define HID_KBD_USAGE_PASTE 0x7d /* Keyboard Paste */ +#define HID_KBD_USAGE_FIND 0x7e /* Keyboard Find */ +#define HID_KBD_USAGE_MUTE 0x7f /* Keyboard Mute */ +#define HID_KBD_USAGE_VOLUP 0x80 /* Keyboard Volume Up */ +#define HID_KBD_USAGE_VOLDOWN 0x81 /* Keyboard Volume Down */ +#define HID_KBD_USAGE_LCAPSLOCK 0x82 /* Keyboard Locking Caps Lock */ +#define HID_KBD_USAGE_LNUMLOCK 0x83 /* Keyboard Locking Num Lock */ +#define HID_KBD_USAGE_LSCROLLLOCK 0x84 /* Keyboard Locking Scroll Lock */ +#define HID_KBD_USAGE_KPDCOMMA 0x85 /* Keypad Comma */ +#define HID_KBD_USAGE_KPDEQUALSIGN 0x86 /* Keypad Equal Sign */ +#define HID_KBD_USAGE_INTERNATIONAL1 0x87 /* Keyboard International 1 */ +#define HID_KBD_USAGE_INTERNATIONAL2 0x88 /* Keyboard International 2 */ +#define HID_KBD_USAGE_INTERNATIONAL3 0x89 /* Keyboard International 3 */ +#define HID_KBD_USAGE_INTERNATIONAL4 0x8a /* Keyboard International 4 */ +#define HID_KBD_USAGE_INTERNATIONAL5 0x8b /* Keyboard International 5 */ +#define HID_KBD_USAGE_INTERNATIONAL6 0x8c /* Keyboard International 6 */ +#define HID_KBD_USAGE_INTERNATIONAL7 0x8d /* Keyboard International 7 */ +#define HID_KBD_USAGE_INTERNATIONAL8 0x8e /* Keyboard International 8 */ +#define HID_KBD_USAGE_INTERNATIONAL9 0x8f /* Keyboard International 9 */ +#define HID_KBD_USAGE_LANG1 0x90 /* Keyboard LANG1 */ +#define HID_KBD_USAGE_LANG2 0x91 /* Keyboard LANG2 */ +#define HID_KBD_USAGE_LANG3 0x92 /* Keyboard LANG3 */ +#define HID_KBD_USAGE_LANG4 0x93 /* Keyboard LANG4 */ +#define HID_KBD_USAGE_LANG5 0x94 /* Keyboard LANG5 */ +#define HID_KBD_USAGE_LANG6 0x95 /* Keyboard LANG6 */ +#define HID_KBD_USAGE_LANG7 0x96 /* Keyboard LANG7 */ +#define HID_KBD_USAGE_LANG8 0x97 /* Keyboard LANG8 */ +#define HID_KBD_USAGE_LANG9 0x98 /* Keyboard LANG9 */ +#define HID_KBD_USAGE_ALTERASE 0x99 /* Keyboard Alternate Erase */ +#define HID_KBD_USAGE_SYSREQ 0x9a /* Keyboard SysReq/Attention */ +#define HID_KBD_USAGE_CANCEL 0x9b /* Keyboard Cancel */ +#define HID_KBD_USAGE_CLEAR 0x9c /* Keyboard Clear */ +#define HID_KBD_USAGE_PRIOR 0x9d /* Keyboard Prior */ +#define HID_KBD_USAGE_RETURN 0x9e /* Keyboard Return */ +#define HID_KBD_USAGE_SEPARATOR 0x9f /* Keyboard Separator */ +#define HID_KBD_USAGE_OUT 0xa0 /* Keyboard Out */ +#define HID_KBD_USAGE_OPER 0xa1 /* Keyboard Oper */ +#define HID_KBD_USAGE_CLEARAGAIN 0xa2 /* Keyboard Clear/Again */ +#define HID_KBD_USAGE_CLRSEL 0xa3 /* Keyboard CrSel/Props */ +#define HID_KBD_USAGE_EXSEL 0xa4 /* Keyboard ExSel */ +#define HID_KBD_USAGE_KPD00 0xb0 /* Keypad 00 */ +#define HID_KBD_USAGE_KPD000 0xb1 /* Keypad 000 */ +#define HID_KBD_USAGE_THOUSEPARATOR 0xb2 /* Thousands Separator */ +#define HID_KBD_USAGE_DECSEPARATOR 0xb3 /* Decimal Separator */ +#define HID_KBD_USAGE_CURRUNIT 0xb4 /* Currency Unit */ +#define HID_KBD_USAGE_CURRSUBUNIT 0xb5 /* Currency Sub-unit */ +#define HID_KBD_USAGE_KPDLPAREN 0xb6 /* Keypad ( */ +#define HID_KBD_USAGE_KPDRPAREN 0xb7 /* Keypad ) */ +#define HID_KBD_USAGE_KPDLBRACE 0xb8 /* Keypad { */ +#define HID_KBD_USAGE_KPDRBRACE 0xb9 /* Keypad } */ +#define HID_KBD_USAGE_KPDTAB 0xba /* Keypad Tab */ +#define HID_KBD_USAGE_KPDBACKSPACE 0xbb /* Keypad Backspace */ +#define HID_KBD_USAGE_KPDA 0xbc /* Keypad A (B-F follow) */ +#define HID_KBD_USAGE_KPDXOR 0xc2 /* Keypad XOR */ +#define HID_KBD_USAGE_KPDEXP 0xc3 /* Keypad ^ */ +#define HID_KBD_USAGE_KPDPERCENT 0xc4 /* Keypad % */ +#define HID_KBD_USAGE_KPDLT 0xc5 /* Keypad < */ +#define HID_KBD_USAGE_KPDGT 0xc6 /* Keypad > */ +#define HID_KBD_USAGE_KPDAMPERSAND 0xc7 /* Keypad & */ +#define HID_KBD_USAGE_KPDAND 0xc8 /* Keypad && */ +#define HID_KBD_USAGE_KPDVERT 0xc9 /* Keypad | */ +#define HID_KBD_USAGE_KPDOR 0xca /* Keypad || */ +#define HID_KBD_USAGE_KPDCOLON 0xcb /* Keypad : */ +#define HID_KBD_USAGE_KPDPOUND 0xcc /* Keypad # */ +#define HID_KBD_USAGE_KPDSPACE 0xcd /* Keypad Space */ +#define HID_KBD_USAGE_KPDAT 0xce /* Keypad @ */ +#define HID_KBD_USAGE_KPDEXCLAM 0xcf /* Keypad ! */ +#define HID_KBD_USAGE_KPDMEMSTORE 0xd0 /* Keypad Memory Store */ +#define HID_KBD_USAGE_KPDMEMRECALL 0xd1 /* Keypad Memory Recall */ +#define HID_KBD_USAGE_KPDMEMCLEAR 0xd2 /* Keypad Memory Clear */ +#define HID_KBD_USAGE_KPDMEMADD 0xd3 /* Keypad Memory Add */ +#define HID_KBD_USAGE_KPDMEMSUB 0xd4 /* Keypad Memory Subtract */ +#define HID_KBD_USAGE_KPDMEMMULT 0xd5 /* Keypad Memory Multiply */ +#define HID_KBD_USAGE_KPDMEMDIV 0xd6 /* Keypad Memory Divide */ +#define HID_KBD_USAGE_KPDPLUSMINUS 0xd7 /* Keypad +/- */ +#define HID_KBD_USAGE_KPDCLEAR 0xd8 /* Keypad Clear */ +#define HID_KBD_USAGE_KPDCLEARENTRY 0xd9 /* Keypad Clear Entry */ +#define HID_KBD_USAGE_KPDBINARY 0xda /* Keypad Binary */ +#define HID_KBD_USAGE_KPDOCTAL 0xdb /* Keypad Octal */ +#define HID_KBD_USAGE_KPDDECIMAL 0xdc /* Keypad Decimal */ +#define HID_KBD_USAGE_KPDHEXADECIMAL 0xdd /* Keypad Hexadecimal */ +#define HID_KBD_USAGE_LCTRL 0xe0 /* Keyboard LeftControl */ +#define HID_KBD_USAGE_LSHIFT 0xe1 /* Keyboard LeftShift */ +#define HID_KBD_USAGE_LALT 0xe2 /* Keyboard LeftAlt */ +#define HID_KBD_USAGE_LGUI 0xe3 /* Keyboard Left GUI */ +#define HID_KBD_USAGE_RCTRL 0xe4 /* Keyboard RightControl */ +#define HID_KBD_USAGE_RSHIFT 0xe5 /* Keyboard RightShift */ +#define HID_KBD_USAGE_RALT 0xe6 /* Keyboard RightAlt */ +#define HID_KBD_USAGE_RGUI 0xe7 /* Keyboard Right GUI */ + +#define HID_KBD_USAGE_MAX 0xe7 + +/* HID Report Definitions */ +struct usb_hid_class_subdescriptor { + uint8_t bDescriptorType; /* Class descriptor type (See 7.1) */ + uint16_t wDescriptorLength; /* Size of the report descriptor */ +} __PACKED; + +struct usb_hid_descriptor { + uint8_t bLength; /* Size of the HID descriptor */ + uint8_t bDescriptorType; /* HID descriptor type */ + uint16_t bcdHID; /* HID class specification release */ + uint8_t bCountryCode; /* Country code */ + uint8_t bNumDescriptors; /* Number of descriptors (>=1) */ + + /* + * Specification says at least one Class Descriptor needs to + * be present (Report Descriptor). + */ + struct usb_hid_class_subdescriptor subdesc[1]; +} __PACKED; + +/* Standard Reports *********************************************************/ + +/* Keyboard input report (8 bytes) (HID B.1) */ +struct usb_hid_kbd_report { + uint8_t modifier; /* Modifier keys. See HID_MODIFER_* definitions */ + uint8_t reserved; + uint8_t key[6]; /* Keycode 1-6 */ +}; + +/* Keyboard output report (1 byte) (HID B.1), + * see HID_KBD_OUTPUT_* definitions + */ + +/* Mouse input report (HID B.2) */ +struct usb_hid_mouse_report { + uint8_t buttons; /* See HID_MOUSE_INPUT_BUTTON_* definitions */ + int8_t xdisp; /* X displacement */ + int8_t ydisp; /* y displacement */ + /* Device specific additional bytes may follow */ + uint8_t wdisp; /* Wheel displacement */ +}; + +/* Joystick input report (1 bytes) (HID D.1) */ +struct usb_hid_js_report { + int8_t xpos; /* X position */ + int8_t ypos; /* X position */ + uint8_t buttons; /* See USBHID_JSIN_* definitions */ + uint8_t throttle; /* Throttle */ +}; + +// clang-format off +#define HID_MOUSE_DESCRIPTOR_LEN (9 + 9 + 7) + +#define HID_MOUSE_DESCRIPTOR_INIT(bInterfaceNumber, bInterfaceSubClass, wItemLength, int_ep, wMaxPacketSize, bInterval) \ + 0x09, /* bLength: Interface Descriptor size */ \ + USB_DESCRIPTOR_TYPE_INTERFACE, /* bDescriptorType: Interface descriptor type */ \ + bInterfaceNumber, /* bInterfaceNumber: Number of Interface */ \ + 0x00, /* bAlternateSetting: Alternate setting */ \ + 0x01, /* bNumEndpoints */ \ + 0x03, /* bInterfaceClass: HID */ \ + bInterfaceSubClass, /* bInterfaceSubClass : 1=BOOT, 0=no boot */ \ + 0x02, /* nInterfaceProtocol : 0=none, 1=keyboard, 2=mouse */ \ + 0x00, /* iInterface: Index of string descriptor */ \ + 0x09, /* bLength: HID Descriptor size */ \ + HID_DESCRIPTOR_TYPE_HID, /* bDescriptorType: HID */ \ + 0x11, /* bcdHID: HID Class Spec release number */ \ + 0x01, \ + 0x00, /* bCountryCode: Hardware target country */ \ + 0x01, /* bNumDescriptors: Number of HID class descriptors to follow */ \ + 0x22, /* bDescriptorType */ \ + WBVAL(wItemLength), /* wItemLength: Total length of Report descriptor */ \ + 0x07, /* bLength: Endpoint Descriptor size */ \ + USB_DESCRIPTOR_TYPE_ENDPOINT, /* bDescriptorType: */ \ + int_ep, /* bEndpointAddress: Endpoint Address (IN) */ \ + 0x03, /* bmAttributes: Interrupt endpoint */ \ + WBVAL(wMaxPacketSize), /* wMaxPacketSize: x Byte max */ \ + bInterval /* bInterval: Polling Interval */ + +#define HID_KEYBOARD_DESCRIPTOR_LEN (9 + 9 + 7) + +#define HID_KEYBOARD_DESCRIPTOR_INIT(bInterfaceNumber, bInterfaceSubClass, wItemLength, int_ep, wMaxPacketSize, bInterval) \ + 0x09, /* bLength: Interface Descriptor size */ \ + USB_DESCRIPTOR_TYPE_INTERFACE, /* bDescriptorType: Interface descriptor type */ \ + bInterfaceNumber, /* bInterfaceNumber: Number of Interface */ \ + 0x00, /* bAlternateSetting: Alternate setting */ \ + 0x01, /* bNumEndpoints */ \ + 0x03, /* bInterfaceClass: HID */ \ + bInterfaceSubClass, /* bInterfaceSubClass : 1=BOOT, 0=no boot */ \ + 0x01, /* nInterfaceProtocol : 0=none, 1=keyboard, 2=mouse */ \ + 0x00, /* iInterface: Index of string descriptor */ \ + 0x09, /* bLength: HID Descriptor size */ \ + HID_DESCRIPTOR_TYPE_HID, /* bDescriptorType: HID */ \ + 0x11, /* bcdHID: HID Class Spec release number */ \ + 0x01, \ + 0x00, /* bCountryCode: Hardware target country */ \ + 0x01, /* bNumDescriptors: Number of HID class descriptors to follow */ \ + 0x22, /* bDescriptorType */ \ + WBVAL(wItemLength), /* wItemLength: Total length of Report descriptor */ \ + 0x07, /* bLength: Endpoint Descriptor size */ \ + USB_DESCRIPTOR_TYPE_ENDPOINT, /* bDescriptorType: */ \ + int_ep, /* bEndpointAddress: Endpoint Address (IN) */ \ + 0x03, /* bmAttributes: Interrupt endpoint */ \ + WBVAL(wMaxPacketSize), /* wMaxPacketSize: x Byte max */ \ + bInterval /* bInterval: Polling Interval */ + +#define HID_CUSTOM_INOUT_DESCRIPTOR_LEN (9 + 9 + 7 + 7) + +#define HID_CUSTOM_INOUT_DESCRIPTOR_INIT(bInterfaceNumber, bInterfaceSubClass, wItemLength, out_ep, in_ep, wMaxPacketSize, bInterval) \ + 0x09, /* bLength: Interface Descriptor size */ \ + USB_DESCRIPTOR_TYPE_INTERFACE, /* bDescriptorType: Interface descriptor type */ \ + bInterfaceNumber, /* bInterfaceNumber: Number of Interface */ \ + 0x00, /* bAlternateSetting: Alternate setting */ \ + 0x02, /* bNumEndpoints */ \ + 0x03, /* bInterfaceClass: HID */ \ + bInterfaceSubClass, /* bInterfaceSubClass : 1=BOOT, 0=no boot */ \ + 0x00, /* nInterfaceProtocol : 0=none, 1=keyboard, 2=mouse */ \ + 0x00, /* iInterface: Index of string descriptor */ \ + 0x09, /* bLength: HID Descriptor size */ \ + HID_DESCRIPTOR_TYPE_HID, /* bDescriptorType: HID */ \ + 0x11, /* bcdHID: HID Class Spec release number */ \ + 0x01, \ + 0x00, /* bCountryCode: Hardware target country */ \ + 0x01, /* bNumDescriptors: Number of HID class descriptors to follow */ \ + 0x22, /* bDescriptorType */ \ + WBVAL(wItemLength), /* wItemLength: Total length of Report descriptor */ \ + 0x07, /* bLength: Endpoint Descriptor size */ \ + USB_DESCRIPTOR_TYPE_ENDPOINT, /* bDescriptorType: */ \ + out_ep, /* bEndpointAddress: Endpoint Address (OUT) */ \ + 0x03, /* bmAttributes: Interrupt endpoint */ \ + WBVAL(wMaxPacketSize), /* wMaxPacketSize: x Byte max */ \ + bInterval, /* bInterval: Polling Interval */ \ + 0x07, /* bLength: Endpoint Descriptor size */ \ + USB_DESCRIPTOR_TYPE_ENDPOINT, /* bDescriptorType: */ \ + in_ep, /* bEndpointAddress: Endpoint Address (IN) */ \ + 0x03, /* bmAttributes: Interrupt endpoint */ \ + WBVAL(wMaxPacketSize), /* wMaxPacketSize: x Byte max */ \ + bInterval /* bInterval: Polling Interval */ +// clang-format on + +#endif /* USB_HID_H */ diff --git a/kernel/cherryusb/class/hid/usbd_hid.c b/kernel/cherryusb/class/hid/usbd_hid.c new file mode 100644 index 0000000..ad8dfa2 --- /dev/null +++ b/kernel/cherryusb/class/hid/usbd_hid.c @@ -0,0 +1,125 @@ +/* + * Copyright (c) 2022, sakumisu + * + * SPDX-License-Identifier: Apache-2.0 + */ +#include "usbd_core.h" +#include "usbd_hid.h" + +static int hid_class_interface_request_handler(uint8_t busid, struct usb_setup_packet *setup, uint8_t **data, uint32_t *len) +{ + USB_LOG_DBG("HID Class request: " + "bRequest 0x%02x\r\n", + setup->bRequest); + + uint8_t intf_num = LO_BYTE(setup->wIndex); + + switch (setup->bRequest) { + case HID_REQUEST_GET_REPORT: + /* report id ,report type */ + usbd_hid_get_report(busid, intf_num, LO_BYTE(setup->wValue), HI_BYTE(setup->wValue), data, len); + break; + case HID_REQUEST_GET_IDLE: + (*data)[0] = usbd_hid_get_idle(busid, intf_num, LO_BYTE(setup->wValue)); + *len = 1; + break; + case HID_REQUEST_GET_PROTOCOL: + (*data)[0] = usbd_hid_get_protocol(busid, intf_num); + *len = 1; + break; + case HID_REQUEST_SET_REPORT: + /* report id ,report type, report, report len */ + usbd_hid_set_report(busid, intf_num, LO_BYTE(setup->wValue), HI_BYTE(setup->wValue), *data, *len); + break; + case HID_REQUEST_SET_IDLE: + /* report id, duration */ + usbd_hid_set_idle(busid, intf_num, LO_BYTE(setup->wValue), HI_BYTE(setup->wValue)); + break; + case HID_REQUEST_SET_PROTOCOL: + /* protocol */ + usbd_hid_set_protocol(busid, intf_num, LO_BYTE(setup->wValue)); + break; + + default: + return -1; + } + + return 0; +} + +struct usbd_interface *usbd_hid_init_intf(uint8_t busid, struct usbd_interface *intf, const uint8_t *desc, uint32_t desc_len) +{ + (void)busid; + + intf->class_interface_handler = hid_class_interface_request_handler; + intf->class_endpoint_handler = NULL; + intf->vendor_handler = NULL; + intf->notify_handler = NULL; + + intf->hid_report_descriptor = desc; + intf->hid_report_descriptor_len = desc_len; + return intf; +} + +/* + * Appendix G: HID Request Support Requirements + * + * The following table enumerates the requests that need to be supported by various types of HID class devices. + * Device type GetReport SetReport GetIdle SetIdle GetProtocol SetProtocol + * ------------------------------------------------------------------------------------------ + * Boot Mouse Required Optional Optional Optional Required Required + * Non-Boot Mouse Required Optional Optional Optional Optional Optional + * Boot Keyboard Required Optional Required Required Required Required + * Non-Boot Keybrd Required Optional Required Required Optional Optional + * Other Device Required Optional Optional Optional Optional Optional + */ + +__WEAK void usbd_hid_get_report(uint8_t busid, uint8_t intf, uint8_t report_id, uint8_t report_type, uint8_t **data, uint32_t *len) +{ + (void)busid; + (void)intf; + (void)report_id; + (void)report_type; + (*data[0]) = 0; + *len = 1; +} + +__WEAK uint8_t usbd_hid_get_idle(uint8_t busid, uint8_t intf, uint8_t report_id) +{ + (void)busid; + (void)intf; + (void)report_id; + return 0; +} + +__WEAK uint8_t usbd_hid_get_protocol(uint8_t busid, uint8_t intf) +{ + (void)busid; + (void)intf; + return 0; +} + +__WEAK void usbd_hid_set_report(uint8_t busid, uint8_t intf, uint8_t report_id, uint8_t report_type, uint8_t *report, uint32_t report_len) +{ + (void)busid; + (void)intf; + (void)report_id; + (void)report_type; + (void)report; + (void)report_len; +} + +__WEAK void usbd_hid_set_idle(uint8_t busid, uint8_t intf, uint8_t report_id, uint8_t duration) +{ + (void)busid; + (void)intf; + (void)report_id; + (void)duration; +} + +__WEAK void usbd_hid_set_protocol(uint8_t busid, uint8_t intf, uint8_t protocol) +{ + (void)busid; + (void)intf; + (void)protocol; +} \ No newline at end of file diff --git a/kernel/cherryusb/class/hid/usbd_hid.h b/kernel/cherryusb/class/hid/usbd_hid.h new file mode 100644 index 0000000..9ab31b9 --- /dev/null +++ b/kernel/cherryusb/class/hid/usbd_hid.h @@ -0,0 +1,30 @@ +/* + * Copyright (c) 2022, sakumisu + * + * SPDX-License-Identifier: Apache-2.0 + */ +#ifndef USBD_HID_H +#define USBD_HID_H + +#include "usb_hid.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* Init hid interface driver */ +struct usbd_interface *usbd_hid_init_intf(uint8_t busid, struct usbd_interface *intf, const uint8_t *desc, uint32_t desc_len); + +/* Setup request command callback api */ +void usbd_hid_get_report(uint8_t busid, uint8_t intf, uint8_t report_id, uint8_t report_type, uint8_t **data, uint32_t *len); +uint8_t usbd_hid_get_idle(uint8_t busid, uint8_t intf, uint8_t report_id); +uint8_t usbd_hid_get_protocol(uint8_t busid, uint8_t intf); +void usbd_hid_set_report(uint8_t busid, uint8_t intf, uint8_t report_id, uint8_t report_type, uint8_t *report, uint32_t report_len); +void usbd_hid_set_idle(uint8_t busid, uint8_t intf, uint8_t report_id, uint8_t duration); +void usbd_hid_set_protocol(uint8_t busid, uint8_t intf, uint8_t protocol); + +#ifdef __cplusplus +} +#endif + +#endif /* USBD_HID_H */ diff --git a/kernel/cherryusb/class/hid/usbh_hid.c b/kernel/cherryusb/class/hid/usbh_hid.c new file mode 100644 index 0000000..7dddf91 --- /dev/null +++ b/kernel/cherryusb/class/hid/usbh_hid.c @@ -0,0 +1,569 @@ +/* + * Copyright (c) 2022, sakumisu + * + * SPDX-License-Identifier: Apache-2.0 + */ +#include "usbh_core.h" +#include "usbh_hid.h" + +#undef USB_DBG_TAG +#define USB_DBG_TAG "usbh_hid" +#include "usb_log.h" + +#define DEV_FORMAT "/dev/input%d" + +/* general descriptor field offsets */ +#define DESC_bLength 0 /** Length offset */ +#define DESC_bDescriptorType 1 /** Descriptor type offset */ + +/* interface descriptor field offsets */ +#define INTF_DESC_bInterfaceNumber 2 /** Interface number offset */ +#define INTF_DESC_bAlternateSetting 3 /** Alternate setting offset */ + +USB_NOCACHE_RAM_SECTION USB_MEM_ALIGNX uint8_t g_hid_buf[CONFIG_USBHOST_MAX_HID_CLASS][USB_ALIGN_UP(32, CONFIG_USB_ALIGN_SIZE)]; + +static struct usbh_hid g_hid_class[CONFIG_USBHOST_MAX_HID_CLASS]; +static uint32_t g_devinuse = 0; + +static struct usbh_hid *usbh_hid_class_alloc(void) +{ + uint8_t devno; + + for (devno = 0; devno < CONFIG_USBHOST_MAX_HID_CLASS; devno++) { + if ((g_devinuse & (1U << devno)) == 0) { + g_devinuse |= (1U << devno); + memset(&g_hid_class[devno], 0, sizeof(struct usbh_hid)); + g_hid_class[devno].minor = devno; + return &g_hid_class[devno]; + } + } + return NULL; +} + +static void usbh_hid_class_free(struct usbh_hid *hid_class) +{ + uint8_t devno = hid_class->minor; + + if (devno < 32) { + g_devinuse &= ~(1U << devno); + } + memset(hid_class, 0, sizeof(struct usbh_hid)); +} + +int usbh_hid_get_report_descriptor(struct usbh_hid *hid_class, uint8_t *buffer, uint32_t buflen) +{ + struct usb_setup_packet *setup; + + if (!hid_class || !hid_class->hport) { + return -USB_ERR_INVAL; + } + setup = hid_class->hport->setup; + + setup->bmRequestType = USB_REQUEST_DIR_IN | USB_REQUEST_STANDARD | USB_REQUEST_RECIPIENT_INTERFACE; + setup->bRequest = USB_REQUEST_GET_DESCRIPTOR; + setup->wValue = HID_DESCRIPTOR_TYPE_HID_REPORT << 8; + setup->wIndex = hid_class->intf; + setup->wLength = buflen; + + return usbh_control_transfer(hid_class->hport, setup, buffer); +} + +int usbh_hid_set_idle(struct usbh_hid *hid_class, uint8_t report_id, uint8_t duration) +{ + struct usb_setup_packet *setup; + + if (!hid_class || !hid_class->hport) { + return -USB_ERR_INVAL; + } + setup = hid_class->hport->setup; + + setup->bmRequestType = USB_REQUEST_DIR_OUT | USB_REQUEST_CLASS | USB_REQUEST_RECIPIENT_INTERFACE; + setup->bRequest = HID_REQUEST_SET_IDLE; + setup->wValue = (duration << 8) | report_id; + setup->wIndex = hid_class->intf; + setup->wLength = 0; + + return usbh_control_transfer(hid_class->hport, setup, NULL); +} + +int usbh_hid_get_idle(struct usbh_hid *hid_class, uint8_t *buffer) +{ + struct usb_setup_packet *setup; + int ret; + + if (!hid_class || !hid_class->hport) { + return -USB_ERR_INVAL; + } + setup = hid_class->hport->setup; + + setup->bmRequestType = USB_REQUEST_DIR_IN | USB_REQUEST_CLASS | USB_REQUEST_RECIPIENT_INTERFACE; + setup->bRequest = HID_REQUEST_GET_IDLE; + setup->wValue = 0; + setup->wIndex = hid_class->intf; + setup->wLength = 1; + + ret = usbh_control_transfer(hid_class->hport, setup, g_hid_buf[hid_class->minor]); + if (ret < 8) { + return ret; + } + memcpy(buffer, g_hid_buf[hid_class->minor], MIN((uint32_t)ret - 8, 1)); + return ret; +} + +int usbh_hid_set_protocol(struct usbh_hid *hid_class, uint8_t protocol) +{ + struct usb_setup_packet *setup; + + if (!hid_class || !hid_class->hport) { + return -USB_ERR_INVAL; + } + setup = hid_class->hport->setup; + + setup->bmRequestType = USB_REQUEST_DIR_OUT | USB_REQUEST_CLASS | USB_REQUEST_RECIPIENT_INTERFACE; + setup->bRequest = HID_REQUEST_SET_PROTOCOL; + setup->wValue = protocol; + setup->wIndex = 0; + setup->wLength = 0; + + return usbh_control_transfer(hid_class->hport, setup, NULL); +} + +int usbh_hid_get_protocol(struct usbh_hid *hid_class, uint8_t *protocol) +{ + struct usb_setup_packet *setup; + int ret; + + if (!hid_class || !hid_class->hport) { + return -USB_ERR_INVAL; + } + setup = hid_class->hport->setup; + + setup->bmRequestType = USB_REQUEST_DIR_IN | USB_REQUEST_CLASS | USB_REQUEST_RECIPIENT_INTERFACE; + setup->bRequest = HID_REQUEST_GET_PROTOCOL; + setup->wValue = 0; + setup->wIndex = hid_class->intf; + setup->wLength = 1; + + ret = usbh_control_transfer(hid_class->hport, setup, g_hid_buf[hid_class->minor]); + if (ret < 8) { + return ret; + } + memcpy(protocol, g_hid_buf[hid_class->minor], MIN((uint32_t)ret - 8, 1)); + return ret; +} + +int usbh_hid_set_report(struct usbh_hid *hid_class, uint8_t report_type, uint8_t report_id, uint8_t *buffer, uint32_t buflen) +{ + struct usb_setup_packet *setup; + + if (!hid_class || !hid_class->hport) { + return -USB_ERR_INVAL; + } + setup = hid_class->hport->setup; + + setup->bmRequestType = USB_REQUEST_DIR_OUT | USB_REQUEST_CLASS | USB_REQUEST_RECIPIENT_INTERFACE; + setup->bRequest = HID_REQUEST_SET_REPORT; + setup->wValue = (uint16_t)(((uint32_t)report_type << 8U) | (uint32_t)report_id); + setup->wIndex = 0; + setup->wLength = buflen; + + return usbh_control_transfer(hid_class->hport, setup, buffer); +} + +int usbh_hid_get_report(struct usbh_hid *hid_class, uint8_t report_type, uint8_t report_id, uint8_t *buffer, uint32_t buflen) +{ + struct usb_setup_packet *setup; + + if (!hid_class || !hid_class->hport) { + return -USB_ERR_INVAL; + } + setup = hid_class->hport->setup; + + setup->bmRequestType = USB_REQUEST_DIR_IN | USB_REQUEST_CLASS | USB_REQUEST_RECIPIENT_INTERFACE; + setup->bRequest = HID_REQUEST_GET_REPORT; + setup->wValue = (uint16_t)(((uint32_t)report_type << 8U) | (uint32_t)report_id); + setup->wIndex = 0; + setup->wLength = buflen; + + return usbh_control_transfer(hid_class->hport, setup, buffer); +} + +int usbh_hid_connect(struct usbh_hubport *hport, uint8_t intf) +{ + struct usb_endpoint_descriptor *ep_desc; + uint8_t cur_iface = 0xff; + uint8_t *p; + bool found = false; + + struct usbh_hid *hid_class = usbh_hid_class_alloc(); + if (hid_class == NULL) { + USB_LOG_ERR("Fail to alloc hid_class\r\n"); + return -USB_ERR_NOMEM; + } + + hid_class->hport = hport; + hid_class->intf = intf; + + hport->config.intf[intf].priv = hid_class; + + p = hport->raw_config_desc; + while (p[DESC_bLength]) { + switch (p[DESC_bDescriptorType]) { + case USB_DESCRIPTOR_TYPE_INTERFACE: + cur_iface = p[INTF_DESC_bInterfaceNumber]; + if (cur_iface == intf) { + hid_class->protocol = p[7]; + struct usb_hid_descriptor *desc = (struct usb_hid_descriptor *)(p + 9); + + if (desc->bDescriptorType != HID_DESCRIPTOR_TYPE_HID) { + USB_LOG_ERR("HID descriptor not found\r\n"); + return -USB_ERR_INVAL; + } + + if (desc->subdesc[0].bDescriptorType != HID_DESCRIPTOR_TYPE_HID_REPORT) { + USB_LOG_ERR("HID report descriptor not found\r\n"); + return -USB_ERR_INVAL; + } + + hid_class->report_size = desc->subdesc[0].wDescriptorLength; + found = true; + goto found; + } + break; + default: + break; + } + /* skip to next descriptor */ + p += p[DESC_bLength]; + } + + if (found == false) { + USB_LOG_ERR("HID interface not found\r\n"); + return -USB_ERR_INVAL; + } +found: + for (uint8_t i = 0; i < hport->config.intf[intf].altsetting[0].intf_desc.bNumEndpoints; i++) { + ep_desc = &hport->config.intf[intf].altsetting[0].ep[i].ep_desc; + if (ep_desc->bEndpointAddress & 0x80) { + USBH_EP_INIT(hid_class->intin, ep_desc); + } else { + USBH_EP_INIT(hid_class->intout, ep_desc); + } + } + + snprintf(hport->config.intf[intf].devname, CONFIG_USBHOST_DEV_NAMELEN, DEV_FORMAT, hid_class->minor); + + USB_LOG_INFO("Register HID Class:%s\r\n", hport->config.intf[intf].devname); + + usbh_hid_run(hid_class); + return 0; +} + +int usbh_hid_disconnect(struct usbh_hubport *hport, uint8_t intf) +{ + int ret = 0; + + struct usbh_hid *hid_class = (struct usbh_hid *)hport->config.intf[intf].priv; + + if (hid_class) { + if (hid_class->intin) { + usbh_kill_urb(&hid_class->intin_urb); + } + + if (hid_class->intout) { + usbh_kill_urb(&hid_class->intout_urb); + } + + if (hport->config.intf[intf].devname[0] != '\0') { + usb_osal_thread_schedule_other(); + USB_LOG_INFO("Unregister HID Class:%s\r\n", hport->config.intf[intf].devname); + usbh_hid_stop(hid_class); + } + + usbh_hid_class_free(hid_class); + } + + return ret; +} + +static uint32_t hid_get_itemval(const uint8_t *data, unsigned int idx, unsigned int size) +{ + uint32_t value = 0; + + for (unsigned int i = 1; i <= size; i++) + value |= data[idx + i] << (8 * (i - 1)); + + return value; +} + +int usbh_hid_parse_report_descriptor(const uint8_t *report_data, uint32_t report_size, struct usbh_hid_report_info *report_info) +{ + struct usbh_hid_report_item_attribute current_item_attr = { 0 }; + struct usbh_hid_report_item *current_item = NULL; + uint32_t itemtag, itemtype, itemsize, itemval; + uint16_t temp_usage; + uint32_t total_report_size[3] = { 0 }; /* input, output, feature */ + uint32_t i = 0; + + memset(report_info, 0, sizeof(struct usbh_hid_report_info)); + memset(¤t_item_attr, 0, sizeof(struct usbh_hid_report_item_attribute)); + current_item_attr.usage_min = 0xffff; + current_item_attr.usage_max = 0; + + while (i < report_size) { + itemtag = report_data[i] & HID_TAG_MASK; + itemtype = report_data[i] & HID_TYPE_MASK; + itemsize = report_data[i] & HID_SIZE_MASK; + + if (itemsize == 3) /* HID spec: 6.2.2.2 - Short Items */ + itemsize = 4; + + itemval = hid_get_itemval(report_data, i, itemsize); + + USB_LOG_DBG("itemtype 0x%02x, itemtag 0x%02x, itemsize %d, itemval 0x%08x\r\n", + itemtype, itemtag, itemsize, itemval); + + switch (itemtype) { + case HID_ITEMTYPE_MAIN: + switch (itemtag) { + case HID_MAINITEM_TAG_INPUT: + case HID_MAINITEM_TAG_OUTPUT: + case HID_MAINITEM_TAG_FEATURE: + if (report_info->report_item_count == CONFIG_USB_HID_MAX_REPORT_ITEMS) { + goto err; + } + + current_item = &report_info->report_items[report_info->report_item_count]; + current_item->report_flags = itemval; + + if (itemtag == HID_MAINITEM_TAG_INPUT) { + current_item->report_type = HID_REPORT_INPUT; + } else if (itemtag == HID_MAINITEM_TAG_OUTPUT) { + current_item->report_type = HID_REPORT_OUTPUT; + } else { + current_item->report_type = HID_REPORT_FEATURE; + } + + current_item->report_bit_offset = total_report_size[current_item->report_type - 1]; + total_report_size[current_item->report_type - 1] += current_item_attr.report_size * current_item_attr.report_count; + + memcpy(¤t_item->attribute, ¤t_item_attr, sizeof(struct usbh_hid_report_item_attribute)); + report_info->report_item_count++; + + // reset for next item + current_item_attr.usage_min = 0xffff; + current_item_attr.usage_max = 0; + break; + case HID_MAINITEM_TAG_COLLECTION: + // reset for next item + current_item_attr.usage_min = 0xffff; + current_item_attr.usage_max = 0; + break; + case HID_MAINITEM_TAG_ENDCOLLECTION: + break; + default: + goto err; + } + break; + case HID_ITEMTYPE_GLOBAL: + switch (itemtag) { + case HID_GLOBALITEM_TAG_USAGE_PAGE: + current_item_attr.usage_page = (uint16_t)itemval; + break; + case HID_GLOBALITEM_TAG_LOGICAL_MIN: + current_item_attr.logical_min = itemval; + break; + case HID_GLOBALITEM_TAG_LOGICAL_MAX: + current_item_attr.logical_max = itemval; + break; + case HID_GLOBALITEM_TAG_PHYSICAL_MIN: + current_item_attr.physical_min = itemval; + break; + case HID_GLOBALITEM_TAG_PHYSICAL_MAX: + current_item_attr.physical_max = itemval; + break; + case HID_GLOBALITEM_TAG_UNIT_EXP: + current_item_attr.unit_exponent = itemval; + break; + case HID_GLOBALITEM_TAG_UNIT: + current_item_attr.unit = itemval; + break; + case HID_GLOBALITEM_TAG_REPORT_SIZE: + current_item_attr.report_size = itemval; + break; + case HID_GLOBALITEM_TAG_REPORT_COUNT: + current_item_attr.report_count = itemval; + break; + case HID_GLOBALITEM_TAG_REPORT_ID: + current_item_attr.report_id = itemval; + break; + default: + goto err; + } + break; + case HID_ITEMTYPE_LOCAL: + switch (itemtag) { + case HID_LOCALITEM_TAG_USAGE: + if (itemsize == 4) { + temp_usage = (uint16_t)(itemval >> 16); + } else { + temp_usage = (uint16_t)itemval; + } + current_item_attr.usage_min = MIN(current_item_attr.usage_min, temp_usage); + current_item_attr.usage_max = MAX(current_item_attr.usage_max, temp_usage); + + break; + case HID_LOCALITEM_TAG_USAGE_MIN: + current_item_attr.usage_min = (uint16_t)itemval; + break; + case HID_LOCALITEM_TAG_USAGE_MAX: + current_item_attr.usage_max = (uint16_t)itemval; + break; + default: + goto err; + } + break; + default: + goto err; + } + + i += (1 + itemsize); + } + + return 0; +err: + return -1; +} + +int usbh_hid_report_convert(struct usbh_hid_report_item *item, const uint8_t *report_buf, uint32_t *output1, uint8_t **output2, uint32_t *output_len) +{ + const uint8_t *src; + uint32_t bits_len = item->attribute.report_size * item->attribute.report_count; + + if(bits_len == 0) { + return -1; + } + + if (item->report_flags & HID_MAINITEM_CONSTANT) { + return -1; + } + + if (item->attribute.report_id > 0) { + if (report_buf[0] != item->attribute.report_id) { + return -2; /* report id mismatch */ + } + + src = report_buf + 1; /* skip report id */ + } else { + src = report_buf; + } + + if ((bits_len < 32) && (bits_len % 8 != 0)) { + *output1 = 0; + + for (uint32_t i = 0; i < bits_len; i++) { + *output1 |= ((src[item->report_bit_offset / 8] >> ((item->report_bit_offset % 8) + i)) & 0x01) << i; + } + + *output2 = NULL; + *output_len = (bits_len + 7) / 8; + return 0; + } else if (bits_len % 8 == 0) { + if (item->report_bit_offset % 8 != 0) { + /* currently do not support item that is not byte aligned */ + return -3; + } + + uint32_t byte_len = bits_len / 8; + *output2 = (uint8_t *)src + item->report_bit_offset / 8; + *output_len = byte_len; + return 0; + } + return -4; +} + +static void usbh_hid_item_info_print(struct usbh_hid_report_item *item) +{ + USB_LOG_RAW("Item Type: %s\r\n", (unsigned int)item->report_type == HID_REPORT_INPUT ? "Input" : + (unsigned int)item->report_type == HID_REPORT_OUTPUT ? "Output" : + "Feature"); + USB_LOG_RAW("Usage Page: 0x%04x\r\n", (unsigned int)item->attribute.usage_page); + USB_LOG_RAW("Report ID: 0x%04x\r\n", (unsigned int)item->attribute.report_id); + USB_LOG_RAW("Report Size: %ubit\r\n", (unsigned int)item->attribute.report_size); + USB_LOG_RAW("Report Count: %u\r\n", (unsigned int)item->attribute.report_count); + USB_LOG_RAW("Usages(0x%04x ~ 0x%04x)\r\n", (unsigned int)item->attribute.usage_min, (unsigned int)item->attribute.usage_max); + USB_LOG_RAW("Logical Min: %d\r\n", item->attribute.logical_min); + USB_LOG_RAW("Logical Max: %d\r\n", item->attribute.logical_max); + USB_LOG_RAW("Properties: 0x%04x\r\n", (unsigned int)item->report_flags); + USB_LOG_RAW("Bit Offset: 0x%04x\r\n", (unsigned int)item->report_bit_offset); + USB_LOG_RAW("\r\n"); +} + +USB_NOCACHE_RAM_SECTION USB_MEM_ALIGNX uint8_t g_hid_report_desc_buf[2048]; + +int lshid(int argc, char **argv) +{ + struct usbh_hid *hid_class; + int ret; + struct usbh_hid_report_info report_info = { 0 }; + + if (argc < 2) { + USB_LOG_ERR("please input correct command: lshid path\r\n"); + return -1; + } + + hid_class = usbh_find_class_instance(argv[1]); + if (!hid_class) { + USB_LOG_ERR("cannot find hid device\r\n"); + return -1; + } + + if (hid_class->report_size > sizeof(g_hid_report_desc_buf)) { + USB_LOG_ERR("hid report buffer is too small\r\n"); + return -1; + } + + ret = usbh_hid_get_report_descriptor(hid_class, g_hid_report_desc_buf, hid_class->report_size); + if (ret < 0) { + USB_LOG_ERR("get hid report descriptor failed, errcode: %d\r\n", ret); + return -1; + } + + ret = usbh_hid_parse_report_descriptor(g_hid_report_desc_buf, hid_class->report_size, &report_info); + if (ret < 0) { + USB_LOG_ERR("parse hid report descriptor failed\r\n"); + return -1; + } + + USB_LOG_INFO("HID report item count: %u\r\n", report_info.report_item_count); + for (uint32_t i = 0; i < report_info.report_item_count; i++) { + usbh_hid_item_info_print(&report_info.report_items[i]); + } + + return 0; +} + +__WEAK void usbh_hid_run(struct usbh_hid *hid_class) +{ + (void)hid_class; +} + +__WEAK void usbh_hid_stop(struct usbh_hid *hid_class) +{ + (void)hid_class; +} + +const struct usbh_class_driver hid_class_driver = { + .driver_name = "hid", + .connect = usbh_hid_connect, + .disconnect = usbh_hid_disconnect +}; + +CLASS_INFO_DEFINE const struct usbh_class_info hid_custom_class_info = { + .match_flags = USB_CLASS_MATCH_INTF_CLASS, + .bInterfaceClass = USB_DEVICE_CLASS_HID, + .bInterfaceSubClass = 0x00, + .bInterfaceProtocol = 0x00, + .id_table = NULL, + .class_driver = &hid_class_driver +}; diff --git a/kernel/cherryusb/class/hid/usbh_hid.h b/kernel/cherryusb/class/hid/usbh_hid.h new file mode 100644 index 0000000..26b2255 --- /dev/null +++ b/kernel/cherryusb/class/hid/usbh_hid.h @@ -0,0 +1,84 @@ +/* + * Copyright (c) 2022, sakumisu + * + * SPDX-License-Identifier: Apache-2.0 + */ +#ifndef USBH_HID_H +#define USBH_HID_H + +#include "usb_hid.h" + +#ifndef CONFIG_USB_HID_MAX_REPORT_ITEMS +#define CONFIG_USB_HID_MAX_REPORT_ITEMS 16 +#endif + +struct usbh_hid_report_item_attribute { + uint16_t usage_page; + uint16_t usage_min; + uint16_t usage_max; + int32_t logical_min; + int32_t logical_max; + uint32_t physical_min; + uint32_t physical_max; + uint32_t unit_exponent; + uint32_t unit; + uint32_t report_count; + uint8_t report_size; + uint8_t report_id; +}; + +struct usbh_hid_report_item { + uint8_t report_type; /* input, output, feature */ + uint16_t report_flags; + uint32_t report_bit_offset; + + struct usbh_hid_report_item_attribute attribute; +}; + +struct usbh_hid_report_info { + struct usbh_hid_report_item report_items[CONFIG_USB_HID_MAX_REPORT_ITEMS]; + uint32_t report_item_count; + bool using_report_id; +}; + +struct usbh_hid { + struct usbh_hubport *hport; + struct usb_endpoint_descriptor *intin; /* INTR IN endpoint */ + struct usb_endpoint_descriptor *intout; /* INTR OUT endpoint */ + struct usbh_urb intin_urb; /* INTR IN urb */ + struct usbh_urb intout_urb; /* INTR OUT urb */ + + uint16_t report_size; + + uint8_t protocol; + uint8_t intf; /* interface number */ + uint8_t minor; + + void *user_data; +}; + +#ifdef __cplusplus +extern "C" { +#endif + +int usbh_hid_get_report_descriptor(struct usbh_hid *hid_class, uint8_t *buffer, uint32_t buflen); +int usbh_hid_set_idle(struct usbh_hid *hid_class, uint8_t report_id, uint8_t duration); +int usbh_hid_get_idle(struct usbh_hid *hid_class, uint8_t *buffer); +int usbh_hid_set_protocol(struct usbh_hid *hid_class, uint8_t protocol); +int usbh_hid_get_protocol(struct usbh_hid *hid_class, uint8_t *protocol); +int usbh_hid_set_report(struct usbh_hid *hid_class, uint8_t report_type, uint8_t report_id, uint8_t *buffer, uint32_t buflen); +int usbh_hid_get_report(struct usbh_hid *hid_class, uint8_t report_type, uint8_t report_id, uint8_t *buffer, uint32_t buflen); + +int usbh_hid_parse_report_descriptor(const uint8_t *report_data, uint32_t report_size, struct usbh_hid_report_info *report_info); +int usbh_hid_report_convert(struct usbh_hid_report_item *item, const uint8_t *report_buf, uint32_t *output1, uint8_t **output2, uint32_t *output_len); + +void usbh_hid_run(struct usbh_hid *hid_class); +void usbh_hid_stop(struct usbh_hid *hid_class); + +int lshid(int argc, char **argv); + +#ifdef __cplusplus +} +#endif + +#endif /* USBH_HID_H */ diff --git a/kernel/cherryusb/class/hub/usb_hub.h b/kernel/cherryusb/class/hub/usb_hub.h new file mode 100644 index 0000000..68e0ecf --- /dev/null +++ b/kernel/cherryusb/class/hub/usb_hub.h @@ -0,0 +1,169 @@ +/* + * Copyright (c) 2022, sakumisu + * + * SPDX-License-Identifier: Apache-2.0 + */ +#ifndef USB_HUB_H +#define USB_HUB_H + +/* HUB Class Descriptor Types */ +#define HUB_DESCRIPTOR_TYPE_HUB 0x29 +#define HUB_DESCRIPTOR_TYPE_HUB3 0x2A + +#define HUB_MAX_DEPTH 5 + +#define HUB_SUBCLASS 0x00 +#define HUB_PROTOCOL_STT 0x01 +#define HUB_PROTOCOL_MTT 0x02 + +/* Hub class requests */ +#define HUB_REQUEST_GET_STATUS USB_REQUEST_GET_STATUS +#define HUB_REQUEST_CLEAR_FEATURE USB_REQUEST_CLEAR_FEATURE +#define HUB_REQUEST_SET_FEATURE USB_REQUEST_SET_FEATURE +#define HUB_REQUEST_GET_DESCRIPTOR USB_REQUEST_GET_DESCRIPTOR +#define HUB_REQUEST_SET_DESCRIPTOR USB_REQUEST_SET_DESCRIPTOR +#define HUB_REQUEST_CLEAR_TT_BUFFER (0x08) +#define HUB_REQUEST_RESET_TT (0x09) +#define HUB_REQUEST_GET_TT_STATE (0x0a) +#define HUB_REQUEST_STOP_TT (0x0b) +#define HUB_REQUEST_SET_HUB_DEPTH (0x0C) + +/* Hub class features */ +#define HUB_FEATURE_HUB_C_LOCALPOWER (0x0) +#define HUB_FEATURE_HUB_C_OVERCURRENT (0x1) + +/* Port features */ +#define HUB_PORT_FEATURE_CONNECTION (0x00) +#define HUB_PORT_FEATURE_ENABLE (0x01) +#define HUB_PORT_FEATURE_SUSPEND (0x02) +#define HUB_PORT_FEATURE_OVERCURRENT (0x03) +#define HUB_PORT_FEATURE_RESET (0x04) +#define HUB_PORT_FEATURE_L1 (0x05) /* USB 2.0 only */ + +#define HUB_PORT_FEATURE_POWER (0x08) /* USB 2.0 only */ +#define HUB_PORT_FEATURE_POWER_SS (0x09) /* USB 3.0 only */ +/* This is a bit tricky because HUB_PORT_FEATURE_POWER_SS and + HUB_PORT_FEATURE_LOWSPEED share the same bit. */ +#define HUB_PORT_FEATURE_LOWSPEED (0x09) /* USB 2.0 only */ +#define HUB_PORT_FEATURE_HIGHSPEED (0x0a) /* USB 2.0 only */ +#define HUB_PORT_FEATURE_TEST (0x0b) /* USB 2.0 only */ +#define HUB_PORT_FEATURE_INDICATOR (0x0c) /* USB 2.0 only */ + +/* Port status change (wPortChange) */ +#define HUB_PORT_FEATURE_C_CONNECTION (0x10) +#define HUB_PORT_FEATURE_C_ENABLE (0x11) /* USB 2.0 only */ +#define HUB_PORT_FEATURE_C_SUSPEND (0x12) /* USB 2.0 only */ +#define HUB_PORT_FEATURE_C_OVER_CURREN (0x13) +#define HUB_PORT_FEATURE_C_RESET (0x14) +#define HUB_PORT_FEATURE_C_BH_RESET (0x15) /* USB 3.0 only */ +#define HUB_PORT_FEATURE_C_LINK_STATE (0x16) /* USB 3.0 only */ +#define HUB_PORT_FEATURE_C_CONFIG_ERR (0x17) /* USB 3.0 only */ + +/* Hub status */ +#define HUB_STATUS_LOCALPOWER (1 << 0) +#define HUB_STATUS_OVERCURRENT (1 << 1) + +/* Hub status change */ +#define HUB_STATUS_C_LOCALPOWER (1 << 0) +#define HUB_STATUS_C_OVERCURRENT (1 << 1) + +/* Hub port status */ +#define HUB_PORT_STATUS_CONNECTION (1 << 0) +#define HUB_PORT_STATUS_ENABLE (1 << 1) +#define HUB_PORT_STATUS_SUSPEND (1 << 2) /* USB 2.0 only */ +#define HUB_PORT_STATUS_OVERCURRENT (1 << 3) +#define HUB_PORT_STATUS_RESET (1 << 4) +#define HUB_PORT_STATUS_L1 (1 << 5) /* USB 2.0 only */ + +/* Port Link State (PORT_LINK_STATE), USB 3.0 only */ +#define HUB_PORT_STATUS_LS_U0 (0x00 << 5) +#define HUB_PORT_STATUS_LS_U1 (0x01 << 5) +#define HUB_PORT_STATUS_LS_U2 (0x02 << 5) +#define HUB_PORT_STATUS_LS_U3 (0x03 << 5) +#define HUB_PORT_STATUS_LS_SS_DISABLED (0x04 << 5) +#define HUB_PORT_STATUS_LS_RX_DETECT (0x05 << 5) +#define HUB_PORT_STATUS_LS_SS_INACTIVE (0x06 << 5) +#define HUB_PORT_STATUS_LS_POLLING (0x07 << 5) +#define HUB_PORT_STATUS_LS_RECOVERY (0x08 << 5) +#define HUB_PORT_STATUS_LS_HOT_RESET (0x09 << 5) +#define HUB_PORT_STATUS_LS_COMP_MOD (0x0a << 5) +#define HUB_PORT_STATUS_LS_LOOPBACK (0x0b << 5) + +#define HUB_PORT_STATUS_POWER (1 << 8) +#define HUB_PORT_STATUS_POWER_SS (1 << 9) /* USB 3.0 only */ +#define HUB_PORT_STATUS_LOW_SPEED (1 << 9) /* USB 2.0 only */ +#define HUB_PORT_STATUS_HIGH_SPEED (1 << 10) /* USB 2.0 only */ +#define HUB_PORT_STATUS_TEST (1 << 11) /* USB 2.0 only */ +#define HUB_PORT_STATUS_INDICATOR (1 << 12) /* USB 2.0 only */ + +/* Hub port status change */ +#define HUB_PORT_STATUS_C_CONNECTION (1 << 0) +#define HUB_PORT_STATUS_C_ENABLE (1 << 1) /* USB 2.0 only */ +#define HUB_PORT_STATUS_C_SUSPEND (1 << 2) /* USB 2.0 only */ +#define HUB_PORT_STATUS_C_OVERCURRENT (1 << 3) +#define HUB_PORT_STATUS_C_RESET (1 << 4) +#define HUB_PORT_STATUS_C_L1 (1 << 5) /* USB 2.0 only */ +#define HUB_PORT_STATUS_C_BH_RESET (1 << 5) /* USB 3.0 only */ +#define HUB_PORT_STATUS_C_PORTLINK (1 << 6) /* USB 3.0 only */ +#define HUB_PORT_STATUS_C_CONFIGERR (1 << 7) /* USB 3.0 only */ + +/* Hub characteristics */ +#define HUB_CHAR_LPSM_SHIFT (0) /* Bits 0-1: Logical Power Switching Mode */ +#define HUB_CHAR_LPSM_MASK (3 << HUB_CHAR_LPSM_SHIFT) +#define HUB_CHAR_LPSM_GANGED (0 << HUB_CHAR_LPSM_SHIFT) +#define HUB_CHAR_LPSM_INDIVIDUAL (1 << HUB_CHAR_LPSM_SHIFT) +#define HUB_CHAR_COMPOUND (1 << 2) /* Bit 2: Compound device */ +#define HUB_CHAR_OCPM_SHIFT (3) /* Bits 3-4: Over-current Protection Mode */ +#define HUB_CHAR_OCPM_MASK (3 << HUB_CHAR_OCPM_SHIFT) +#define HUB_CHAR_OCPM_GLOBAL (0 << HUB_CHAR_OCPM_SHIFT) +#define HUB_CHAR_OCPM_INDIVIDUAL (1 << HUB_CHAR_OCPM_SHIFT) +#define HUB_CHAR_TTTT_SHIFT (5) /* Bits 5-6: TT Think Time */ +#define HUB_CHAR_TTTT_MASK (3 << HUB_CHAR_TTTT_SHIFT) +#define HUB_CHAR_TTTT_8_BITS (0 << HUB_CHAR_TTTT_SHIFT) +#define HUB_CHAR_TTTT_16_BITS (1 << HUB_CHAR_TTTT_SHIFT) +#define HUB_CHAR_TTTT_24_BITS (2 << HUB_CHAR_TTTT_SHIFT) +#define HUB_CHAR_TTTT_32_BITS (3 << HUB_CHAR_TTTT_SHIFT) +#define HUB_CHAR_PORTIND (1 << 7) /* Bit 7: Port Indicators Supported */ + +/* Hub descriptor */ +struct usb_hub_descriptor { + uint8_t bLength; + uint8_t bDescriptorType; + uint8_t bNbrPorts; + uint16_t wHubCharacteristics; + uint8_t bPwrOn2PwrGood; + uint8_t bHubContrCurrent; + uint8_t DeviceRemovable; + uint8_t PortPwrCtrlMask; +} __PACKED; + +#define USB_SIZEOF_HUB_DESC 9 + +/* Super speed Hub descriptor */ +struct usb_hub_ss_descriptor { + uint8_t bLength; + uint8_t bDescriptorType; + uint8_t bNbrPorts; + uint16_t wHubCharacteristics; + uint8_t bPwrOn2PwrGood; + uint8_t bHubContrCurrent; + uint8_t bHubHdrDecLat; + uint16_t wHubDelay; + uint8_t DeviceRemovable; +} __PACKED; + +#define USB_SIZEOF_HUB_SS_DESC 11 + +/* Hub status */ +struct hub_status { + uint16_t wPortStatus; + uint16_t wPortChange; +}; + +/* Hub port status */ +struct hub_port_status { + uint16_t wPortStatus; + uint16_t wPortChange; +}; + +#endif /* USB_HUB_H */ diff --git a/kernel/cherryusb/class/hub/usbh_hub.c b/kernel/cherryusb/class/hub/usbh_hub.c new file mode 100644 index 0000000..5538de8 --- /dev/null +++ b/kernel/cherryusb/class/hub/usbh_hub.c @@ -0,0 +1,785 @@ +/* + * Copyright (c) 2022, sakumisu + * + * SPDX-License-Identifier: Apache-2.0 + */ +#include "usbh_core.h" +#include "usbh_hub.h" + +#undef USB_DBG_TAG +#define USB_DBG_TAG "usbh_hub" +#include "usb_log.h" + +#define DEV_FORMAT "/dev/hub%d" + +#define HUB_DEBOUNCE_TIMEOUT 1500 +#define HUB_DEBOUNCE_STEP 25 +#define HUB_DEBOUNCE_STABLE 100 +#define DELAY_TIME_AFTER_RESET 200 + +#define EXTHUB_FIRST_INDEX 2 + +USB_NOCACHE_RAM_SECTION USB_MEM_ALIGNX uint8_t g_hub_buf[CONFIG_USBHOST_MAX_BUS][USB_ALIGN_UP(32, CONFIG_USB_ALIGN_SIZE)]; +USB_NOCACHE_RAM_SECTION USB_MEM_ALIGNX uint8_t g_hub_intbuf[CONFIG_USBHOST_MAX_BUS][CONFIG_USBHOST_MAX_EXTHUBS + 1][USB_ALIGN_UP(1, CONFIG_USB_ALIGN_SIZE)]; + +extern int usbh_enumerate(struct usbh_hubport *hport); +extern void usbh_hubport_release(struct usbh_hubport *hport); + +static const char *speed_table[] = { "error-speed", "low-speed", "full-speed", "high-speed", "wireless-speed", "super-speed", "superplus-speed" }; + +#if CONFIG_USBHOST_MAX_EXTHUBS > 0 +static struct usbh_hub g_hub_class[CONFIG_USBHOST_MAX_EXTHUBS]; +static uint32_t g_devinuse = 0; + +static struct usbh_hub *usbh_hub_class_alloc(void) +{ + uint8_t devno; + + for (devno = 0; devno < CONFIG_USBHOST_MAX_EXTHUBS; devno++) { + if ((g_devinuse & (1U << devno)) == 0) { + g_devinuse |= (1U << devno); + memset(&g_hub_class[devno], 0, sizeof(struct usbh_hub)); + g_hub_class[devno].index = EXTHUB_FIRST_INDEX + devno; + return &g_hub_class[devno]; + } + } + return NULL; +} + +static void usbh_hub_class_free(struct usbh_hub *hub_class) +{ + uint8_t devno = hub_class->index - EXTHUB_FIRST_INDEX; + + if (devno < 32) { + g_devinuse &= ~(1U << devno); + } + memset(hub_class, 0, sizeof(struct usbh_hub)); +} + +static int _usbh_hub_get_hub_descriptor(struct usbh_hub *hub, uint8_t *buffer) +{ + struct usb_setup_packet *setup; + int ret; + + setup = hub->parent->setup; + + setup->bmRequestType = USB_REQUEST_DIR_IN | USB_REQUEST_CLASS | USB_REQUEST_RECIPIENT_DEVICE; + setup->bRequest = USB_REQUEST_GET_DESCRIPTOR; + setup->wValue = HUB_DESCRIPTOR_TYPE_HUB << 8; + + setup->wIndex = 0; + setup->wLength = USB_SIZEOF_HUB_DESC; + + ret = usbh_control_transfer(hub->parent, setup, g_hub_buf[hub->bus->busid]); + if (ret < 0) { + return ret; + } + memcpy(buffer, g_hub_buf[hub->bus->busid], USB_SIZEOF_HUB_DESC); + return ret; +} + +static int _usbh_hub_get_hub_ss_descriptor(struct usbh_hub *hub, uint8_t *buffer) +{ + struct usb_setup_packet *setup; + int ret; + + setup = hub->parent->setup; + + setup->bmRequestType = USB_REQUEST_DIR_IN | USB_REQUEST_CLASS | USB_REQUEST_RECIPIENT_DEVICE; + setup->bRequest = USB_REQUEST_GET_DESCRIPTOR; + setup->wValue = HUB_DESCRIPTOR_TYPE_HUB3 << 8; + + setup->wIndex = 0; + setup->wLength = USB_SIZEOF_HUB_SS_DESC; + + ret = usbh_control_transfer(hub->parent, setup, g_hub_buf[hub->bus->busid]); + if (ret < 0) { + return ret; + } + memcpy(buffer, g_hub_buf[hub->bus->busid], USB_SIZEOF_HUB_SS_DESC); + return ret; +} +#endif + +static int _usbh_hub_get_portstatus(struct usbh_hub *hub, uint8_t port, struct hub_port_status *port_status) +{ + struct usb_setup_packet *setup; + int ret; + + setup = hub->parent->setup; + + setup->bmRequestType = USB_REQUEST_DIR_IN | USB_REQUEST_CLASS | USB_REQUEST_RECIPIENT_OTHER; + setup->bRequest = HUB_REQUEST_GET_STATUS; + setup->wValue = 0; + setup->wIndex = port; + setup->wLength = 4; + + ret = usbh_control_transfer(hub->parent, setup, g_hub_buf[hub->bus->busid]); + if (ret < 0) { + return ret; + } + memcpy(port_status, g_hub_buf[hub->bus->busid], 4); + return ret; +} + +static int _usbh_hub_set_feature(struct usbh_hub *hub, uint8_t port, uint8_t feature) +{ + struct usb_setup_packet *setup; + + setup = hub->parent->setup; + + setup->bmRequestType = USB_REQUEST_DIR_OUT | USB_REQUEST_CLASS | USB_REQUEST_RECIPIENT_OTHER; + setup->bRequest = HUB_REQUEST_SET_FEATURE; + setup->wValue = feature; + setup->wIndex = port; + setup->wLength = 0; + + return usbh_control_transfer(hub->parent, setup, NULL); +} + +static int _usbh_hub_clear_feature(struct usbh_hub *hub, uint8_t port, uint8_t feature) +{ + struct usb_setup_packet *setup; + + setup = hub->parent->setup; + + setup->bmRequestType = USB_REQUEST_DIR_OUT | USB_REQUEST_CLASS | USB_REQUEST_RECIPIENT_OTHER; + setup->bRequest = HUB_REQUEST_CLEAR_FEATURE; + setup->wValue = feature; + setup->wIndex = port; + setup->wLength = 0; + + return usbh_control_transfer(hub->parent, setup, NULL); +} + +#if CONFIG_USBHOST_MAX_EXTHUBS > 0 +static int _usbh_hub_set_depth(struct usbh_hub *hub, uint16_t depth) +{ + struct usb_setup_packet *setup; + + setup = hub->parent->setup; + + setup->bmRequestType = USB_REQUEST_DIR_OUT | USB_REQUEST_CLASS | USB_REQUEST_RECIPIENT_DEVICE; + setup->bRequest = HUB_REQUEST_SET_HUB_DEPTH; + setup->wValue = depth; + setup->wIndex = 0; + setup->wLength = 0; + + return usbh_control_transfer(hub->parent, setup, NULL); +} + +static int parse_hub_descriptor(struct usb_hub_descriptor *desc, uint16_t length) +{ + (void)length; + + if (desc->bLength != USB_SIZEOF_HUB_DESC) { + USB_LOG_ERR("invalid device bLength 0x%02x\r\n", desc->bLength); + return -1; + } else if (desc->bDescriptorType != HUB_DESCRIPTOR_TYPE_HUB) { + USB_LOG_ERR("unexpected descriptor 0x%02x\r\n", desc->bDescriptorType); + return -2; + } else { + USB_LOG_DBG("Hub Descriptor:\r\n"); + USB_LOG_DBG("bLength: 0x%02x \r\n", desc->bLength); + USB_LOG_DBG("bDescriptorType: 0x%02x \r\n", desc->bDescriptorType); + USB_LOG_DBG("bNbrPorts: 0x%02x \r\n", desc->bNbrPorts); + USB_LOG_DBG("wHubCharacteristics: 0x%04x \r\n", desc->wHubCharacteristics); + USB_LOG_DBG("bPwrOn2PwrGood: 0x%02x \r\n", desc->bPwrOn2PwrGood); + USB_LOG_DBG("bHubContrCurrent: 0x%02x \r\n", desc->bHubContrCurrent); + USB_LOG_DBG("DeviceRemovable: 0x%02x \r\n", desc->DeviceRemovable); + USB_LOG_DBG("PortPwrCtrlMask: 0x%02x \r\n", desc->PortPwrCtrlMask); + } + return 0; +} + +static int parse_hub_ss_descriptor(struct usb_hub_ss_descriptor *desc, uint16_t length) +{ + (void)length; + + if (desc->bLength < USB_SIZEOF_HUB_SS_DESC) { + USB_LOG_ERR("invalid device bLength 0x%02x\r\n", desc->bLength); + return -1; + } else if (desc->bDescriptorType != HUB_DESCRIPTOR_TYPE_HUB3) { + USB_LOG_ERR("unexpected descriptor 0x%02x\r\n", desc->bDescriptorType); + return -2; + } else { + USB_LOG_DBG("SuperSpeed Hub Descriptor:\r\n"); + USB_LOG_DBG("bLength: 0x%02x \r\n", desc->bLength); + USB_LOG_DBG("bDescriptorType: 0x%02x \r\n", desc->bDescriptorType); + USB_LOG_DBG("bNbrPorts: 0x%02x \r\n", desc->bNbrPorts); + USB_LOG_DBG("wHubCharacteristics: 0x%04x \r\n", desc->wHubCharacteristics); + USB_LOG_DBG("bPwrOn2PwrGood: 0x%02x \r\n", desc->bPwrOn2PwrGood); + USB_LOG_DBG("bHubContrCurrent: 0x%02x \r\n", desc->bHubContrCurrent); + USB_LOG_DBG("DeviceRemovable: 0x%02x \r\n", desc->DeviceRemovable); + } + return 0; +} +#endif + +static int usbh_hub_get_portstatus(struct usbh_hub *hub, uint8_t port, struct hub_port_status *port_status) +{ + struct usb_setup_packet roothub_setup; + struct usb_setup_packet *setup; + + if (hub->is_roothub) { + setup = &roothub_setup; + setup->bmRequestType = USB_REQUEST_DIR_IN | USB_REQUEST_CLASS | USB_REQUEST_RECIPIENT_OTHER; + setup->bRequest = HUB_REQUEST_GET_STATUS; + setup->wValue = 0; + setup->wIndex = port; + setup->wLength = 4; + return usbh_roothub_control(hub->bus, &roothub_setup, (uint8_t *)port_status); + } else { + return _usbh_hub_get_portstatus(hub, port, port_status); + } +} + +int usbh_hub_set_feature(struct usbh_hub *hub, uint8_t port, uint8_t feature) +{ + struct usb_setup_packet roothub_setup; + struct usb_setup_packet *setup; + int ret; + + if (hub->is_roothub) { + setup = &roothub_setup; + setup->bmRequestType = USB_REQUEST_DIR_OUT | USB_REQUEST_CLASS | USB_REQUEST_RECIPIENT_OTHER; + setup->bRequest = HUB_REQUEST_SET_FEATURE; + setup->wValue = feature; + setup->wIndex = port; + setup->wLength = 0; + + ret = usbh_roothub_control(hub->bus, setup, NULL); + + if ((feature == HUB_PORT_FEATURE_RESET) && (ret >= 0)) { + hub->bus->event_handler(hub->bus->busid, hub->index, port, USB_INTERFACE_ANY, USBH_EVENT_DEVICE_RESET); + } + + return ret; + } else { + ret = _usbh_hub_set_feature(hub, port, feature); + + if ((feature == HUB_PORT_FEATURE_RESET) && (ret >= 0)) { + hub->bus->event_handler(hub->bus->busid, hub->index, port, USB_INTERFACE_ANY, USBH_EVENT_DEVICE_RESET); + } + + return ret; + } +} + +int usbh_hub_clear_feature(struct usbh_hub *hub, uint8_t port, uint8_t feature) +{ + struct usb_setup_packet roothub_setup; + struct usb_setup_packet *setup; + + if (hub->is_roothub) { + setup = &roothub_setup; + setup->bmRequestType = USB_REQUEST_DIR_OUT | USB_REQUEST_CLASS | USB_REQUEST_RECIPIENT_OTHER; + setup->bRequest = HUB_REQUEST_CLEAR_FEATURE; + setup->wValue = feature; + setup->wIndex = port; + setup->wLength = 0; + return usbh_roothub_control(hub->bus, setup, NULL); + } else { + return _usbh_hub_clear_feature(hub, port, feature); + } +} + +#if CONFIG_USBHOST_MAX_EXTHUBS > 0 +static int usbh_hub_set_depth(struct usbh_hub *hub, uint16_t depth) +{ + struct usb_setup_packet roothub_setup; + struct usb_setup_packet *setup; + + if (hub->is_roothub) { + setup = &roothub_setup; + setup->bmRequestType = USB_REQUEST_DIR_OUT | USB_REQUEST_CLASS | USB_REQUEST_RECIPIENT_DEVICE; + setup->bRequest = HUB_REQUEST_SET_HUB_DEPTH; + setup->wValue = depth; + setup->wIndex = 0; + setup->wLength = 0; + return usbh_roothub_control(hub->bus, setup, NULL); + } else { + return _usbh_hub_set_depth(hub, depth); + } +} + +static void hub_int_complete_callback(void *arg, int nbytes) +{ + struct usbh_hub *hub = (struct usbh_hub *)arg; + + if (nbytes > 0) { + usbh_hub_thread_wakeup(hub); + } else if (nbytes == -USB_ERR_NAK) { + /* Restart timer to submit urb again */ + USB_LOG_DBG("Restart timer\r\n"); + usb_osal_timer_start(hub->int_timer); + } else { + } +} + +static void hub_int_timeout(void *arg) +{ + struct usbh_hub *hub = (struct usbh_hub *)arg; + + usbh_int_urb_fill(&hub->intin_urb, hub->parent, hub->intin, hub->int_buffer, 1, 0, hub_int_complete_callback, hub); + usbh_submit_urb(&hub->intin_urb); +} + +static int usbh_hub_connect(struct usbh_hubport *hport, uint8_t intf) +{ + struct usb_endpoint_descriptor *ep_desc; + struct hub_port_status port_status; + int ret; + + struct usbh_hub *hub = usbh_hub_class_alloc(); + if (hub == NULL) { + USB_LOG_ERR("Fail to alloc hub_class\r\n"); + return -USB_ERR_NOMEM; + } + + hub->hub_addr = hport->dev_addr; + hub->parent = hport; + hub->bus = hport->bus; + hub->speed = hport->speed; + + hport->self = hub; + hport->config.intf[intf].priv = hub; + + if (hport->depth > HUB_MAX_DEPTH) { + USB_LOG_ERR("Hub depth(%d) is overflow\r\n", hport->depth); + return -USB_ERR_INVAL; + } + + /* + * Super-Speed hubs need to know their depth to be able to + * parse the bits of the route-string that correspond to + * their downstream port number. + * + */ + if ((hport->depth != 0) && (hport->speed == USB_SPEED_SUPER)) { + ret = usbh_hub_set_depth(hub, hport->depth - 1); + if (ret < 0) { + USB_LOG_ERR("Unable to set hub depth \r\n"); + return ret; + } + } + + /* Get hub descriptor. */ + if (hport->speed == USB_SPEED_SUPER) { + ret = _usbh_hub_get_hub_ss_descriptor(hub, (uint8_t *)&hub->hub_ss_desc); + if (ret < 0) { + return ret; + } + + parse_hub_ss_descriptor(&hub->hub_ss_desc, USB_SIZEOF_HUB_SS_DESC); + hub->nports = hub->hub_ss_desc.bNbrPorts; + hub->powerdelay = hub->hub_ss_desc.bPwrOn2PwrGood * 2; + hub->tt_think = 0U; + } else { + ret = _usbh_hub_get_hub_descriptor(hub, (uint8_t *)&hub->hub_desc); + if (ret < 0) { + return ret; + } + + parse_hub_descriptor(&hub->hub_desc, USB_SIZEOF_HUB_DESC); + hub->nports = hub->hub_desc.bNbrPorts; + hub->powerdelay = hub->hub_desc.bPwrOn2PwrGood * 2; + hub->tt_think = ((hub->hub_desc.wHubCharacteristics & HUB_CHAR_TTTT_MASK) >> 5); + } + + if (hub->nports > CONFIG_USBHOST_MAX_EHPORTS) { + USB_LOG_ERR("Hub nports %u overflow\r\n", hub->nports); + return -USB_ERR_NOMEM; + } + + for (uint8_t port = 0; port < hub->nports; port++) { + hub->child[port].port = port + 1; + hub->child[port].parent = hub; + hub->child[port].bus = hport->bus; + } + + if (hport->device_desc.bDeviceProtocol == HUB_PROTOCOL_MTT) { + hub->ismtt = 1; + } else { + hub->ismtt = 0; + } + + ep_desc = &hport->config.intf[intf].altsetting[0].ep[0].ep_desc; + if (ep_desc->bEndpointAddress & 0x80) { + USBH_EP_INIT(hub->intin, ep_desc); + } else { + return -1; + } + + for (uint8_t port = 0; port < hub->nports; port++) { + ret = usbh_hub_set_feature(hub, port + 1, HUB_PORT_FEATURE_POWER); + if (ret < 0) { + return ret; + } + } + + usb_osal_msleep(hub->powerdelay); + + for (uint8_t port = 0; port < hub->nports; port++) { + ret = usbh_hub_get_portstatus(hub, port + 1, &port_status); + USB_LOG_DBG("port %u, status:0x%03x, change:0x%02x\r\n", port + 1, port_status.wPortStatus, port_status.wPortChange); + if (ret < 0) { + return ret; + } + } + + hub->connected = true; + snprintf(hport->config.intf[intf].devname, CONFIG_USBHOST_DEV_NAMELEN, DEV_FORMAT, hub->index); + + USB_LOG_INFO("Register HUB Class:%s\r\n", hport->config.intf[intf].devname); + + hub->int_buffer = g_hub_intbuf[hub->bus->busid][hub->index - 1]; + + hub->int_timer = usb_osal_timer_create("hubint_tim", USBH_GET_URB_INTERVAL(hub->intin->bInterval, hport->speed) / 1000, hub_int_timeout, hub, 0); + if (hub->int_timer == NULL) { + USB_LOG_ERR("No memory to alloc int_timer\r\n"); + return -USB_ERR_NOMEM; + } + usb_osal_timer_start(hub->int_timer); + return 0; +} + +static int usbh_hub_disconnect(struct usbh_hubport *hport, uint8_t intf) +{ + struct usbh_hubport *child; + int ret = 0; + + struct usbh_hub *hub = (struct usbh_hub *)hport->config.intf[intf].priv; + + if (hub) { + if (hub->intin) { + usbh_kill_urb(&hub->intin_urb); + } + + if (hub->int_timer) { + usb_osal_timer_delete(hub->int_timer); + } + + for (uint8_t port = 0; port < hub->nports; port++) { + child = &hub->child[port]; + usbh_hubport_release(child); + child->parent = NULL; + } + + if (hport->config.intf[intf].devname[0] != '\0') { + USB_LOG_INFO("Unregister HUB Class:%s\r\n", hport->config.intf[intf].devname); + } + + usbh_hub_class_free(hub); + } + return ret; +} +#endif + +static void usbh_hub_events(struct usbh_hub *hub) +{ + struct usbh_hubport *child; + struct hub_port_status port_status; + uint16_t portchange_index; + uint16_t portstatus; + uint16_t portchange; + uint16_t mask; + uint16_t feat; + uint8_t speed; + int ret; + size_t flags; + + (void)speed_table; + + if (!hub->connected) { + return; + } + + flags = usb_osal_enter_critical_section(); + memcpy(&portchange_index, hub->int_buffer, 2); + usb_osal_leave_critical_section(flags); + + for (uint8_t port = 0; port < hub->nports; port++) { + USB_LOG_DBG("Port change:0x%02x\r\n", portchange_index); + + if (!(portchange_index & (1 << (port + 1)))) { + continue; + } + portchange_index &= ~(1 << (port + 1)); + USB_LOG_DBG("Port %d change\r\n", port + 1); + + /* Read hub port status */ + ret = usbh_hub_get_portstatus(hub, port + 1, &port_status); + if (ret < 0) { + USB_LOG_ERR("Failed to read port %u status, errorcode: %d\r\n", port + 1, ret); + continue; + } + + portstatus = port_status.wPortStatus; + portchange = port_status.wPortChange; + + USB_LOG_DBG("port %u, status:0x%03x, change:0x%02x\r\n", port + 1, portstatus, portchange); + + /* First, clear all change bits */ + mask = 1; + feat = HUB_PORT_FEATURE_C_CONNECTION; + while (portchange) { + if (portchange & mask) { + ret = usbh_hub_clear_feature(hub, port + 1, feat); + if (ret < 0) { + USB_LOG_ERR("Failed to clear port %u, change mask:%04x, errorcode:%d\r\n", port + 1, mask, ret); + continue; + } + portchange &= (~mask); + } + mask <<= 1; + feat++; + } + + portchange = port_status.wPortChange; + + /* Second, if port changes, debounces first */ + if (portchange & HUB_PORT_STATUS_C_CONNECTION) { + uint16_t connection = 0; + uint16_t debouncestable = 0; + for (uint32_t debouncetime = 0; debouncetime < HUB_DEBOUNCE_TIMEOUT; debouncetime += HUB_DEBOUNCE_STEP) { + /* Read hub port status */ + ret = usbh_hub_get_portstatus(hub, port + 1, &port_status); + if (ret < 0) { + USB_LOG_ERR("Failed to read port %u status, errorcode: %d\r\n", port + 1, ret); + continue; + } + + portstatus = port_status.wPortStatus; + portchange = port_status.wPortChange; + + USB_LOG_DBG("Port %u, status:0x%03x, change:0x%02x\r\n", port + 1, portstatus, portchange); + + if (!(portchange & HUB_PORT_STATUS_C_CONNECTION) && + ((portstatus & HUB_PORT_STATUS_CONNECTION) == connection)) { + debouncestable += HUB_DEBOUNCE_STEP; + if (debouncestable >= HUB_DEBOUNCE_STABLE) { + break; + } + } else { + debouncestable = 0; + connection = portstatus & HUB_PORT_STATUS_CONNECTION; + } + + if (portchange & HUB_PORT_STATUS_C_CONNECTION) { + usbh_hub_clear_feature(hub, port + 1, HUB_PORT_FEATURE_C_CONNECTION); + } + + usb_osal_msleep(HUB_DEBOUNCE_STEP); + } + + /** check if debounce ok */ + if (debouncestable < HUB_DEBOUNCE_STABLE) { + USB_LOG_ERR("Failed to debounce port %u\r\n", port + 1); + break; + } + + /* Last, check connect status */ + if (portstatus & HUB_PORT_STATUS_CONNECTION) { + hub->bus->event_handler(hub->bus->busid, hub->index, port + 1, USB_INTERFACE_ANY, USBH_EVENT_DEVICE_CONNECTED); + + ret = usbh_hub_set_feature(hub, port + 1, HUB_PORT_FEATURE_RESET); + if (ret < 0) { + USB_LOG_ERR("Failed to reset port %u, errorcode: %d\r\n", port + 1, ret); + continue; + } + + usb_osal_msleep(DELAY_TIME_AFTER_RESET); + /* Read hub port status */ + ret = usbh_hub_get_portstatus(hub, port + 1, &port_status); + if (ret < 0) { + USB_LOG_ERR("Failed to read port %u status, errorcode: %d\r\n", port + 1, ret); + continue; + } + + portstatus = port_status.wPortStatus; + portchange = port_status.wPortChange; + + USB_LOG_DBG("Port %u, status:0x%03x, change:0x%02x\r\n", port + 1, portstatus, portchange); + + if (!(portstatus & HUB_PORT_STATUS_RESET) && (portstatus & HUB_PORT_STATUS_ENABLE)) { + if (portchange & HUB_PORT_STATUS_C_RESET) { + ret = usbh_hub_clear_feature(hub, port + 1, HUB_PORT_FEATURE_C_RESET); + if (ret < 0) { + USB_LOG_ERR("Failed to clear port %u reset change, errorcode: %d\r\n", port + 1, ret); + continue; + } + } + + /* + * Figure out device speed. This is a bit tricky because + * HUB_PORT_STATUS_POWER_SS and HUB_PORT_STATUS_LOW_SPEED share the same bit. + */ + if (portstatus & HUB_PORT_STATUS_POWER) { + if (portstatus & HUB_PORT_STATUS_HIGH_SPEED) { + speed = USB_SPEED_HIGH; + } else if (portstatus & HUB_PORT_STATUS_LOW_SPEED) { + speed = USB_SPEED_LOW; + } else { + speed = USB_SPEED_FULL; + } + } else if (portstatus & HUB_PORT_STATUS_POWER_SS) { + speed = USB_SPEED_SUPER; + } else { + USB_LOG_WRN("Port %u does not enable power\r\n", port + 1); + continue; + } + + child = &hub->child[port]; + /** release child sources first */ + usbh_hubport_release(child); + + memset(child, 0, sizeof(struct usbh_hubport)); + child->parent = hub; + child->depth = (hub->parent ? hub->parent->depth : 0) + 1; + child->connected = true; + child->port = port + 1; + child->speed = speed; + child->bus = hub->bus; + child->mutex = usb_osal_mutex_create(); + USB_ASSERT(child->mutex != NULL); + + USB_LOG_INFO("New %s device on Bus %u, Hub %u, Port %u connected\r\n", speed_table[speed], hub->bus->busid, hub->index, port + 1); + + if (usbh_enumerate(child) < 0) { + /** release child sources */ + usbh_hubport_release(child); + USB_LOG_ERR("Port %u enumerate fail\r\n", child->port); + } + } else { + child = &hub->child[port]; + /** release child sources */ + usbh_hubport_release(child); + + /** some USB 3.0 ip may failed to enable USB 2.0 port for USB 3.0 device */ + USB_LOG_WRN("Failed to enable port %u\r\n", port + 1); + + continue; + } + } else { + child = &hub->child[port]; + /** release child sources */ + usbh_hubport_release(child); + } + } + } + + /* Start next hub int transfer */ + if (!hub->is_roothub && hub->connected) { + usb_osal_timer_start(hub->int_timer); + } +} + +static void usbh_hub_thread(CONFIG_USB_OSAL_THREAD_SET_ARGV) +{ + struct usbh_hub *hub; + struct usbh_hubport *hport; + int ret = 0; + + struct usbh_bus *bus = (struct usbh_bus *)CONFIG_USB_OSAL_THREAD_GET_ARGV; + + bus->event_handler(bus->busid, USB_HUB_INDEX_ANY, USB_HUB_PORT_ANY, USB_INTERFACE_ANY, USBH_EVENT_INIT); + usb_hc_init(bus); + + while (1) { + ret = usb_osal_mq_recv(bus->hub_mq, (uintptr_t *)&hub, USB_OSAL_WAITING_FOREVER); + if (ret < 0) { + continue; + } + if (hub == NULL) { + break; + } + usbh_hub_events(hub); + } + + hub = &bus->hcd.roothub; + for (uint8_t port = 0; port < hub->nports; port++) { + hport = &hub->child[port]; + + usbh_hubport_release(hport); + } + usb_hc_deinit(bus); + usb_osal_mq_delete(bus->hub_mq); + usb_osal_sem_give(bus->hub_sem); + usb_osal_thread_delete(NULL); +} + +void usbh_hub_thread_wakeup(struct usbh_hub *hub) +{ + usb_osal_mq_send(hub->bus->hub_mq, (uintptr_t)hub); +} + +int usbh_hub_initialize(struct usbh_bus *bus) +{ + char thread_name[32] = { 0 }; + struct usbh_hub *hub; + + hub = &bus->hcd.roothub; + hub->connected = true; + hub->index = 1; + hub->is_roothub = true; + hub->parent = NULL; + hub->hub_addr = 1; + hub->nports = CONFIG_USBHOST_MAX_RHPORTS; + hub->int_buffer = bus->hcd.roothub_intbuf; + hub->bus = bus; + + bus->hub_mq = usb_osal_mq_create(7); + if (bus->hub_mq == NULL) { + USB_LOG_ERR("Failed to create hub mq\r\n"); + return -1; + } + + bus->hub_sem = usb_osal_sem_create(0); + if (bus->hub_sem == NULL) { + USB_LOG_ERR("Failed to create hub sem\r\n"); + return -1; + } + + snprintf(thread_name, 32, "usbh_hub%u", bus->busid); + bus->hub_thread = usb_osal_thread_create(thread_name, CONFIG_USBHOST_PSC_STACKSIZE, CONFIG_USBHOST_PSC_PRIO, usbh_hub_thread, bus); + if (bus->hub_thread == NULL) { + USB_LOG_ERR("Failed to create hub thread\r\n"); + return -1; + } + return 0; +} + +int usbh_hub_deinitialize(struct usbh_bus *bus) +{ + if (!bus->hub_mq || !bus->hub_sem) { + return -USB_ERR_INVAL; + } + + usb_osal_mq_send(bus->hub_mq, (uintptr_t)NULL); + usb_osal_sem_take(bus->hub_sem, USB_OSAL_WAITING_FOREVER); + usb_osal_sem_delete(bus->hub_sem); + bus->hub_mq = NULL; + bus->hub_sem = NULL; + + bus->event_handler(bus->busid, USB_HUB_INDEX_ANY, USB_HUB_PORT_ANY, USB_INTERFACE_ANY, USBH_EVENT_DEINIT); + + return 0; +} + +#if CONFIG_USBHOST_MAX_EXTHUBS > 0 +const struct usbh_class_driver hub_class_driver = { + .driver_name = "hub", + .connect = usbh_hub_connect, + .disconnect = usbh_hub_disconnect +}; + +CLASS_INFO_DEFINE const struct usbh_class_info hub_class_info = { + .match_flags = USB_CLASS_MATCH_INTF_CLASS, + .bInterfaceClass = USB_DEVICE_CLASS_HUB, + .bInterfaceSubClass = 0, + .bInterfaceProtocol = 0, + .id_table = NULL, + .class_driver = &hub_class_driver +}; +#endif diff --git a/kernel/cherryusb/class/hub/usbh_hub.h b/kernel/cherryusb/class/hub/usbh_hub.h new file mode 100644 index 0000000..dcce660 --- /dev/null +++ b/kernel/cherryusb/class/hub/usbh_hub.h @@ -0,0 +1,29 @@ +/* + * Copyright (c) 2022, sakumisu + * + * SPDX-License-Identifier: Apache-2.0 + */ +#ifndef USBH_HUB_H +#define USBH_HUB_H + +#include "usb_hub.h" + +struct usbh_hub; + +#ifdef __cplusplus +extern "C" { +#endif + +int usbh_hub_set_feature(struct usbh_hub *hub, uint8_t port, uint8_t feature); +int usbh_hub_clear_feature(struct usbh_hub *hub, uint8_t port, uint8_t feature); + +void usbh_hub_thread_wakeup(struct usbh_hub *hub); + +int usbh_hub_initialize(struct usbh_bus *bus); +int usbh_hub_deinitialize(struct usbh_bus *bus); + +#ifdef __cplusplus +} +#endif + +#endif /* USBH_HUB_H */ diff --git a/kernel/cherryusb/class/midi/usb_midi.h b/kernel/cherryusb/class/midi/usb_midi.h new file mode 100644 index 0000000..e68675a --- /dev/null +++ b/kernel/cherryusb/class/midi/usb_midi.h @@ -0,0 +1,255 @@ +/* + * Copyright (c) 2022, sakumisu + * + * SPDX-License-Identifier: Apache-2.0 + */ +#ifndef USB_MIDI_H +#define USB_MIDI_H + +#include "usb_audio.h" + +/* bDescriptorSubType */ +#define MIDI_VC_HEADER_DESCRIPTOR_SUBTYPE 0x01U +#define MIDI_MS_HEADER_DESCRIPTOR_SUBTYPE 0x01U +#define MIDI_MS_GENERAL_DESCRIPTOR_SUBTYPE 0x01U +#define MIDI_MIDI_IN_JACK_DESCRIPTOR_SUBTYPE 0x02U +#define MIDI_MIDI_OUT_JACK_DESCRIPTOR_SUBTYPE 0x03U + +/* bJackType */ +#define MIDI_JACK_TYPE_EMBEDDED 0x01 +#define MIDI_JACK_TYPE_EXTERNAL 0x02 + +#define MIDI_CHANNEL_OMNI 0 +#define MIDI_CHANNEL_OFF 17 + +#define MIDI_PITCHBEND_MIN -8192 +#define MIDI_PITCHBEND_MAX 8191 + +/*! Enumeration of MIDI code index number */ +enum MidiCodeIndexNumber { + MIDI_CIN_MISC = 0, + MIDI_CIN_CABLE_EVENT = 1, + MIDI_CIN_SYSCOM_2BYTE = 2, ///< 2 byte system common message e.g MTC, SongSelect + MIDI_CIN_SYSCOM_3BYTE = 3, ///< 3 byte system common message e.g SPP + MIDI_CIN_SYSEX_START = 4, ///< SysEx starts or continue + MIDI_CIN_SYSEX_END_1BYTE = 5, ///< SysEx ends with 1 data, or 1 byte system common message + MIDI_CIN_SYSEX_END_2BYTE = 6, ///< SysEx ends with 2 data + MIDI_CIN_SYSEX_END_3BYTE = 7, ///< SysEx ends with 3 data + MIDI_CIN_NOTE_OFF = 8, + MIDI_CIN_NOTE_ON = 9, + MIDI_CIN_POLY_KEYPRESS = 10, + MIDI_CIN_CONTROL_CHANGE = 11, + MIDI_CIN_PROGRAM_CHANGE = 12, + MIDI_CIN_CHANNEL_PRESSURE = 13, + MIDI_CIN_PITCH_BEND_CHANGE = 14, + MIDI_CIN_1BYTE_DATA = 15 +}; + +/*! Enumeration of MIDI types */ +enum MidiType { + InvalidType = 0x00, ///< For notifying errors + NoteOff = 0x80, ///< Note Off + NoteOn = 0x90, ///< Note On + AfterTouchPoly = 0xA0, ///< Polyphonic AfterTouch + ControlChange = 0xB0, ///< Control Change / Channel Mode + ProgramChange = 0xC0, ///< Program Change + AfterTouchChannel = 0xD0, ///< Channel (monophonic) AfterTouch + PitchBend = 0xE0, ///< Pitch Bend + SystemExclusive = 0xF0, ///< System Exclusive + TimeCodeQuarterFrame = 0xF1, ///< System Common - MIDI Time Code Quarter Frame + SongPosition = 0xF2, ///< System Common - Song Position Pointer + SongSelect = 0xF3, ///< System Common - Song Select + TuneRequest = 0xF6, ///< System Common - Tune Request + Clock = 0xF8, ///< System Real Time - Timing Clock + Start = 0xFA, ///< System Real Time - Start + Continue = 0xFB, ///< System Real Time - Continue + Stop = 0xFC, ///< System Real Time - Stop + ActiveSensing = 0xFE, ///< System Real Time - Active Sensing + SystemReset = 0xFF, ///< System Real Time - System Reset +}; + +/*! Enumeration of Thru filter modes */ +enum MidiFilterMode { + Off = 0, ///< Thru disabled (nothing passes through). + Full = 1, ///< Fully enabled Thru (every incoming message is sent back). + SameChannel = 2, ///< Only the messages on the Input Channel will be sent back. + DifferentChannel = 3, ///< All the messages but the ones on the Input Channel will be sent back. +}; + +/*! \brief Enumeration of Control Change command numbers. + See the detailed controllers numbers & description here: + http://www.somascape.org/midi/tech/spec.html#ctrlnums + */ +enum MidiControlChangeNumber { + // High resolution Continuous Controllers MSB (+32 for LSB) ---------------- + BankSelect = 0, + ModulationWheel = 1, + BreathController = 2, + // CC3 undefined + FootController = 4, + PortamentoTime = 5, + DataEntry = 6, + ChannelVolume = 7, + Balance = 8, + // CC9 undefined + Pan = 10, + ExpressionController = 11, + EffectControl1 = 12, + EffectControl2 = 13, + // CC14 undefined + // CC15 undefined + GeneralPurposeController1 = 16, + GeneralPurposeController2 = 17, + GeneralPurposeController3 = 18, + GeneralPurposeController4 = 19, + + // Switches ---------------------------------------------------------------- + Sustain = 64, + Portamento = 65, + Sostenuto = 66, + SoftPedal = 67, + Legato = 68, + Hold = 69, + + // Low resolution continuous controllers ----------------------------------- + SoundController1 = 70, ///< Synth: Sound Variation FX: Exciter On/Off + SoundController2 = 71, ///< Synth: Harmonic Content FX: Compressor On/Off + SoundController3 = 72, ///< Synth: Release Time FX: Distortion On/Off + SoundController4 = 73, ///< Synth: Attack Time FX: EQ On/Off + SoundController5 = 74, ///< Synth: Brightness FX: Expander On/Off + SoundController6 = 75, ///< Synth: Decay Time FX: Reverb On/Off + SoundController7 = 76, ///< Synth: Vibrato Rate FX: Delay On/Off + SoundController8 = 77, ///< Synth: Vibrato Depth FX: Pitch Transpose On/Off + SoundController9 = 78, ///< Synth: Vibrato Delay FX: Flange/Chorus On/Off + SoundController10 = 79, ///< Synth: Undefined FX: Special Effects On/Off + GeneralPurposeController5 = 80, + GeneralPurposeController6 = 81, + GeneralPurposeController7 = 82, + GeneralPurposeController8 = 83, + PortamentoControl = 84, + // CC85 to CC90 undefined + Effects1 = 91, ///< Reverb send level + Effects2 = 92, ///< Tremolo depth + Effects3 = 93, ///< Chorus send level + Effects4 = 94, ///< Celeste depth + Effects5 = 95, ///< Phaser depth + + // Channel Mode messages --------------------------------------------------- + AllSoundOff = 120, + ResetAllControllers = 121, + LocalControl = 122, + AllNotesOff = 123, + OmniModeOff = 124, + OmniModeOn = 125, + MonoModeOn = 126, + PolyModeOn = 127 +}; + +struct midi_cs_if_ac_header_descriptor { + uint8_t bLength; + uint8_t bDescriptorType; + uint8_t bDescriptorSubType; + uint16_t bcdADC; + uint16_t wTotalLength; + uint8_t bInCollection; + uint8_t baInterfaceNr[]; +} __PACKED; + +#define MIDI_SIZEOF_AC_HEADER_DESC(n) (8 + n) + +struct midi_cs_if_ms_header_descriptor { + uint8_t bLength; + uint8_t bDescriptorType; + uint8_t bDescriptorSubType; + uint16_t bcdMSC; + uint16_t wTotalLength; +} __PACKED; + +#define MIDI_SIZEOF_MS_HEADER_DESC (7) + +struct midi_cs_if_in_jack_descriptor { + uint8_t bLength; + uint8_t bDescriptorType; + uint8_t bDescriptorSubType; + uint8_t bJackType; + uint8_t bJackId; + uint8_t iJack; +} __PACKED; + +#define MIDI_SIZEOF_IN_JACK_DESC (6) + +struct midi_cs_if_out_jack_descriptor { + uint8_t bLength; + uint8_t bDescriptorType; + uint8_t bDescriptorSubType; + uint8_t bJackType; + uint8_t bJackId; + uint8_t bNrInputPins; + uint8_t baSourceId; + uint8_t baSourcePin; + uint8_t iJack; +} __PACKED; + +#define MIDI_SIZEOF_OUT_JACK_DESC (9) + +struct midi_cs_ep_ms_general_descriptor { + uint8_t bLength; + uint8_t bDescriptorType; + uint8_t bDescriptorSubType; + uint8_t bNumEmbMIDIJack; + uint8_t baAssocJackID[]; +} __PACKED; + +#define MIDI_SIZEOF_MS_GENERAL_DESC(n) (4 + n) + +// clang-format off +#define MIDI_STANDARD_DESCRIPTOR_INIT(bInterfaceNumber, bNumEndpoints) \ + 0x09, /* bLength */ \ + USB_DESCRIPTOR_TYPE_INTERFACE, /* bDescriptorType */ \ + bInterfaceNumber, /* bInterfaceNumber */ \ + 0x00, /* bAlternateSetting */ \ + bNumEndpoints, /* bNumEndpoints */ \ + USB_DEVICE_CLASS_AUDIO, /* bInterfaceClass */ \ + AUDIO_SUBCLASS_MIDISTREAMING, /* bInterfaceSubClass */ \ + AUDIO_PROTOCOL_UNDEFINED, /* bInterfaceProtocol */ \ + 0x00 /* iInterface */ + +#define MIDI_STANDARD_DESCRIPTOR_LEN 0x09 + +#define MIDI_CS_HEADER_DESCRIPTOR_INIT(wTotalLength) \ + 0x07, /* bLength */ \ + USB_CS_DESCRIPTOR_TYPE_INTERFACE, /* bDescriptorType */ \ + MIDI_MS_HEADER_DESCRIPTOR_SUBTYPE, /* bDescriptorSubtype */ \ + WBVAL(0x0100), /* bcdMSC */ \ + WBVAL(wTotalLength) /* wTotalLength */ + +#define MIDI_IN_JACK_DESCRIPTOR_INIT(bJackType, bJackID) \ + 0x06, \ + 0x24, \ + MIDI_MIDI_IN_JACK_DESCRIPTOR_SUBTYPE, \ + bJackType, \ + bJackID, \ + 0x00 + +#define MIDI_OUT_JACK_DESCRIPTOR_INIT(bJackType, bJackID, baSourceID) \ + 0x09, \ + 0x24, \ + MIDI_MIDI_OUT_JACK_DESCRIPTOR_SUBTYPE, \ + bJackType, \ + bJackID, \ + 0x01, \ + baSourceID, \ + 0x01, \ + 0x00 + +#define MIDI_JACK_DESCRIPTOR_INIT(bJackFirstID) \ + MIDI_IN_JACK_DESCRIPTOR_INIT(MIDI_JACK_TYPE_EMBEDDED, bJackFirstID), \ + MIDI_IN_JACK_DESCRIPTOR_INIT(MIDI_JACK_TYPE_EXTERNAL, (bJackFirstID + 1)), \ + MIDI_OUT_JACK_DESCRIPTOR_INIT(MIDI_JACK_TYPE_EMBEDDED, (bJackFirstID + 2), (bJackFirstID + 1)), \ + MIDI_OUT_JACK_DESCRIPTOR_INIT(MIDI_JACK_TYPE_EXTERNAL, (bJackFirstID + 3), (bJackFirstID)) + +#define MIDI_SIZEOF_JACK_DESC (6 + 6 + 9 + 9) + +// clang-format on + +#endif /* USB_MIDI_H */ diff --git a/kernel/cherryusb/class/msc/usb_msc.h b/kernel/cherryusb/class/msc/usb_msc.h new file mode 100644 index 0000000..75187f5 --- /dev/null +++ b/kernel/cherryusb/class/msc/usb_msc.h @@ -0,0 +1,89 @@ +/* + * Copyright (c) 2022, sakumisu + * + * SPDX-License-Identifier: Apache-2.0 + */ +#ifndef USB_MSC_H +#define USB_MSC_H + +/* MSC Subclass Codes */ +#define MSC_SUBCLASS_RBC 0x01 /* Reduced block commands (e.g., flash devices) */ +#define MSC_SUBCLASS_SFF8020I_MMC2 0x02 /* SFF-8020i/MMC-2 (ATAPI) (e.g., C/DVD) */ +#define MSC_SUBCLASS_QIC157 0x03 /* QIC-157 (e.g., tape device) */ +#define MSC_SUBCLASS_UFI 0x04 /* e.g. floppy device */ +#define MSC_SUBCLASS_SFF8070I 0x05 /* SFF-8070i (e.g. floppy disk) */ +#define MSC_SUBCLASS_SCSI 0x06 /* SCSI transparent */ + +/* MSC Protocol Codes */ +#define MSC_PROTOCOL_CBI_INT 0x00 /* CBI transport with command completion interrupt */ +#define MSC_PROTOCOL_CBI_NOINT 0x01 /* CBI transport without command completion interrupt */ +#define MSC_PROTOCOL_BULK_ONLY 0x50 /* Bulk only transport */ + +/* MSC Request Codes */ +#define MSC_REQUEST_RESET 0xFF +#define MSC_REQUEST_GET_MAX_LUN 0xFE + +/** MSC Command Block Wrapper (CBW) Signature */ +#define MSC_CBW_Signature 0x43425355 +/** Bulk-only Command Status Wrapper (CSW) Signature */ +#define MSC_CSW_Signature 0x53425355 + +/** MSC Command Block Status Values */ +#define CSW_STATUS_CMD_PASSED 0x00 +#define CSW_STATUS_CMD_FAILED 0x01 +#define CSW_STATUS_PHASE_ERROR 0x02 + +#define MSC_MAX_CDB_LEN (16) /* Max length of SCSI Command Data Block */ + +/** MSC Bulk-Only Command Block Wrapper (CBW) */ +struct CBW { + uint32_t dSignature; /* 'USBC' = 0x43425355 */ + uint32_t dTag; /* Depends on command id */ + uint32_t dDataLength; /* Number of bytes that host expects to transfer */ + uint8_t bmFlags; /* Bit 7: Direction=IN (other obsolete or reserved) */ + uint8_t bLUN; /* LUN (normally 0) */ + uint8_t bCBLength; /* len of cdb[] */ + uint8_t CB[MSC_MAX_CDB_LEN]; /* Command Data Block */ +} __PACKED; + +#define USB_SIZEOF_MSC_CBW 31 + +/** MSC Bulk-Only Command Status Wrapper (CSW) */ +struct CSW { + uint32_t dSignature; /* 'USBS' = 0x53425355 */ + uint32_t dTag; /* Same tag as original command */ + uint32_t dDataResidue; /* Amount not transferred */ + uint8_t bStatus; /* Status of transfer */ +} __PACKED; + +#define USB_SIZEOF_MSC_CSW 13 + +/*Length of template descriptor: 23 bytes*/ +#define MSC_DESCRIPTOR_LEN (9 + 7 + 7) +// clang-format off +#define MSC_DESCRIPTOR_INIT(bFirstInterface, out_ep, in_ep, wMaxPacketSize, str_idx) \ + /* Interface */ \ + 0x09, /* bLength */ \ + USB_DESCRIPTOR_TYPE_INTERFACE, /* bDescriptorType */ \ + bFirstInterface, /* bInterfaceNumber */ \ + 0x00, /* bAlternateSetting */ \ + 0x02, /* bNumEndpoints */ \ + USB_DEVICE_CLASS_MASS_STORAGE, /* bInterfaceClass */ \ + MSC_SUBCLASS_SCSI, /* bInterfaceSubClass */ \ + MSC_PROTOCOL_BULK_ONLY, /* bInterfaceProtocol */ \ + str_idx, /* iInterface */ \ + 0x07, /* bLength */ \ + USB_DESCRIPTOR_TYPE_ENDPOINT, /* bDescriptorType */ \ + out_ep, /* bEndpointAddress */ \ + 0x02, /* bmAttributes */ \ + WBVAL(wMaxPacketSize), /* wMaxPacketSize */ \ + 0x00, /* bInterval */ \ + 0x07, /* bLength */ \ + USB_DESCRIPTOR_TYPE_ENDPOINT, /* bDescriptorType */ \ + in_ep, /* bEndpointAddress */ \ + 0x02, /* bmAttributes */ \ + WBVAL(wMaxPacketSize), /* wMaxPacketSize */ \ + 0x00 /* bInterval */ +// clang-format on + +#endif /* USB_MSC_H */ diff --git a/kernel/cherryusb/class/msc/usb_scsi.h b/kernel/cherryusb/class/msc/usb_scsi.h new file mode 100644 index 0000000..7eeb50a --- /dev/null +++ b/kernel/cherryusb/class/msc/usb_scsi.h @@ -0,0 +1,972 @@ +/* + * Apache NuttX + * Copyright 2020 The Apache Software Foundation + * + * SPDX-License-Identifier: Apache-2.0 + */ +#ifndef __INCLUDE_NUTTX_SCSI_H +#define __INCLUDE_NUTTX_SCSI_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* SCSI commands ************************************************************/ + +#define SCSI_CMD_TESTUNITREADY 0x00 +#define SCSI_CMD_REZEROUNIT 0x01 +#define SCSI_CMD_REQUESTSENSE 0x03 +#define SCSI_CMD_FORMAT_UNIT 0x04 +#define SCSI_CMD_REASSIGNBLOCKS 0x07 +#define SCSI_CMD_READ6 0x08 +#define SCSI_CMD_WRITE6 0x0a +#define SCSI_CMD_SEEK6 0x0b +#define SCSI_CMD_SPACE6 0x11 +#define SCSI_CMD_INQUIRY 0x12 +#define SCSI_CMD_MODESELECT6 0x15 +#define SCSI_CMD_RESERVE6 0x16 +#define SCSI_CMD_RELEASE6 0x17 +#define SCSI_CMD_COPY 0x18 +#define SCSI_CMD_MODESENSE6 0x1a +#define SCSI_CMD_STARTSTOPUNIT 0x1b +#define SCSI_CMD_RECEIVEDIAGNOSTICRESULTS 0x1c +#define SCSI_CMD_SENDDIAGNOSTIC 0x1d +#define SCSI_CMD_PREVENTMEDIAREMOVAL 0x1e +#define SCSI_CMD_READFORMATCAPACITIES 0x23 +#define SCSI_CMD_READCAPACITY10 0x25 +#define SCSI_CMD_READ10 0x28 +#define SCSI_CMD_WRITE10 0x2a +#define SCSI_CMD_SEEK10 0x2b +#define SCSI_CMD_WRITEANDVERIFY 0x2e +#define SCSI_CMD_VERIFY10 0x2f +#define SCSI_CMD_SEARCHDATAHIGH 0x30 +#define SCSI_CMD_SEARCHDATAEQUAL 0x31 +#define SCSI_CMD_SEARCHDATALOW 0x32 +#define SCSI_CMD_SETLIMITS10 0x33 +#define SCSI_CMD_PREFETCH10 0x34 +#define SCSI_CMD_SYNCHCACHE10 0x35 +#define SCSI_CMD_LOCKCACHE 0x36 +#define SCSI_CMD_READDEFECTDATA10 0x37 +#define SCSI_CMD_COMPARE 0x39 +#define SCSI_CMD_COPYANDVERIFY 0x3a +#define SCSI_CMD_WRITEBUFFER 0x3b +#define SCSI_CMD_READBUFFER 0x3c +#define SCSI_CMD_READLONG10 0x3e +#define SCSI_CMD_WRITELONG10 0x3f +#define SCSI_CMD_CHANGEDEFINITION 0x40 +#define SCSI_CMD_WRITESAME10 0x41 +#define SCSI_CMD_LOGSELECT 0x4c +#define SCSI_CMD_LOGSENSE 0x4d +#define SCSI_CMD_XDWRITE10 0x50 +#define SCSI_CMD_XPWRITE10 0x51 +#define SCSI_CMD_XDREAD10 0x52 +#define SCSI_CMD_MODESELECT10 0x55 +#define SCSI_CMD_RESERVE10 0x56 +#define SCSI_CMD_RELEASE10 0x57 +#define SCSI_CMD_MODESENSE10 0x5a +#define SCSI_CMD_PERSISTENTRESERVEIN 0x5e +#define SCSI_CMD_PERSISTENTRESERVEOUT 0x5f +#define SCSI_CMD_32 0x7f +#define SCSI_CMD_XDWRITEEXTENDED 0x80 +#define SCSI_CMD_REBUILD 0x82 +#define SCSI_CMD_REGENERATE 0x82 +#define SCSI_CMD_EXTENDEDCOPY 0x83 +#define SCSI_CMD_COPYRESULTS 0x84 +#define SCSI_CMD_ACCESSCONTROLIN 0x86 +#define SCSI_CMD_ACCESSCONTROLOUT 0x87 +#define SCSI_CMD_READ16 0x88 +#define SCSI_CMD_WRITE16 0x8a +#define SCSI_CMD_READATTRIBUTE 0x8c +#define SCSI_CMD_WRITEATTRIBUTE 0x8d +#define SCSI_CMD_WRITEANDVERIFY16 0x8e +#define SCSI_CMD_PREFETCH16 0x90 +#define SCSI_CMD_SYNCHCACHE16 0x91 +#define SCSI_CMD_LOCKUNLOCKACACHE 0x92 +#define SCSI_CMD_WRITESAME16 0x93 +#define SCSI_CMD_READCAPACITY16 0x9e +#define SCSI_CMD_READLONG16 0x9e +#define SCSI_CMD_WRITELONG106 0x9f +#define SCSI_CMD_REPORTLUNS 0xa0 +#define SCSI_CMD_MAINTENANCEIN 0xa3 +#define SCSI_CMD_MAINTENANCEOUT 0xa4 +#define SCSI_CMD_MOVEMEDIUM 0xa5 +#define SCSI_CMD_MOVEMEDIUMATTACHED 0xa7 +#define SCSI_CMD_READ12 0xa8 +#define SCSI_CMD_WRITE12 0xaa +#define SCSI_CMD_READMEDIASERIALNUMBER 0xab +#define SCSI_CMD_WRITEANDVERIFY12 0xae +#define SCSI_CMD_VERIFY12 0xaf +#define SCSI_CMD_SETLIMITS12 0xb3 +#define SCSI_CMD_READELEMENTSTATUS 0xb4 +#define SCSI_CMD_READDEFECTDATA12 0xb7 +#define SCSI_CMD_REDUNDANCYGROUPIN 0xba +#define SCSI_CMD_REDUNDANCYGROUPOUT 0xbb +#define SCSI_CMD_SPAREIN 0xbc +#define SCSI_CMD_SPAREOUT 0xbd +#define SCSI_CMD_VOLUMESETIN 0xbe +#define SCSI_CMD_VOLUMESETOUT 0xbf + +/* Common SCSI KCQ values (sense Key/additional sense Code/ASC Qualifier) *** + * + * 0xnn0386 Write Fault Data Corruption + * 0xnn0500 Illegal request + * 0xnn0600 Unit attention + * 0xnn0700 Data protect + * 0xnn0800 LUN communication failure + * 0xnn0801 LUN communication timeout + * 0xnn0802 LUN communication parity error + * 0xnn0803 LUN communication CRC error + * 0xnn0900 vendor specific sense key + * 0xnn0901 servo fault + * 0xnn0904 head select fault + * 0xnn0a00 error log overflow + * 0xnn0b00 aborted command + * 0xnn0c00 write error + * 0xnn0c02 write error - auto-realloc failed + * 0xnn0e00 data miscompare + * 0xnn1200 address mark not founf for ID field + * 0xnn1400 logical block not found + * 0xnn1500 random positioning error + * 0xnn1501 mechanical positioning error + * 0xnn1502 positioning error detected by read of medium + * 0xnn2700 write protected + * 0xnn2900 POR or bus reset occurred + * 0xnn3101 format failed + * 0xnn3191 format corrupted + * 0xnn3201 defect list update error + * 0xnn3202 no spares available + * 0xnn3501 unspecified enclosure services failure + * 0xnn3700 parameter rounded + * 0xnn3d00 invalid bits in identify message + * 0xnn3e00 LUN not self-configured yet + * 0xnn4001 DRAM parity error + * 0xnn4002 DRAM parity error + * 0xnn4200 power-on or self-test failure + * 0xnn4c00 LUN failed self-configuration + * 0xnn5c00 RPL status change + * 0xnn5c01 spindles synchronized + * 0xnn5c02 spindles not synchronized + * 0xnn6500 voltage fault + * 0xnn8000 general firmware error + */ + +/* No sense KCQ values */ + +#define SCSI_KCQ_NOSENSE 0x000000 /* No error */ +#define SCSI_KCQ_PFATHRESHOLDREACHED 0x005c00 /* No sense - PFA threshold reached */ + +/* Soft error KCQ values */ + +#define SCSI_KCQSE_RWENOINDEX 0x010100 /* Recovered Write error - no index */ +#define SCSI_KCQSE_RECOVEREDNOSEEKCOMPLETION 0x010200 /* Recovered no seek completion */ +#define SCSI_KCQSE_RWEWRITEFAULT 0x010300 /* Recovered Write error - write fault */ +#define SCSI_KCQSE_TRACKFOLLOWINGERROR 0x010900 /* Track following error */ +#define SCSI_KCQSE_TEMPERATUREWARNING 0x010b01 /* Temperature warning */ +#define SCSI_KCQSE_RWEWARREALLOCATED 0x010c01 /* Recovered Write error with auto-realloc - reallocated */ +#define SCSI_KCQSE_RWERECOMMENDREASSIGN 0x010c03 /* Recovered Write error - recommend reassign */ +#define SCSI_KCQSE_RDWOEUSINGPREVLBI 0x011201 /* Recovered data without ECC using prev logical block ID */ +#define SCSI_KCQSE_RDWEUSINGPREVLBI 0x011202 /* Recovered data with ECC using prev logical block ID */ +#define SCSI_KCQSE_RECOVEREDRECORDNOTFOUND 0x011401 /* Recovered Record Not Found */ +#define SCSI_KCQSE_RWEDSME 0x011600 /* Recovered Write error - Data Sync Mark Error */ +#define SCSI_KCQSE_RWEDSEDATAREWRITTEN 0x011601 /* Recovered Write error - Data Sync Error - data rewritten */ +#define SCSI_KCQSE_RWEDSERECOMMENDREWRITE 0x011602 /* Recovered Write error - Data Sync Error - recommend rewrite */ +#define SCSI_KCQSE_RWEDSEDATAAUTOREALLOCATED 0x011603 /* Recovered Write error - Data Sync Error - data auto-reallocated */ +#define SCSI_KCQSE_RWEDSERECOMMENDREASSIGNMENT 0x011604 /* Recovered Write error - Data Sync Error - recommend reassignment */ +#define SCSI_KCQSE_RDWNECORRECTIONAPPLIED 0x011700 /* Recovered data with no error correction applied */ +#define SCSI_KCQSE_RREWITHRETRIES 0x011701 /* Recovered Read error - with retries */ +#define SCSI_KCQSE_RDUSINGPOSITIVEOFFSET 0x011702 /* Recovered data using positive offset */ +#define SCSI_KCQSE_RDUSINGNEGATIVEOFFSET 0x011703 /* Recovered data using negative offset */ +#define SCSI_KCQSE_RDUSINGPREVIOUSLBI 0x011705 /* Recovered data using previous logical block ID */ +#define SCSI_KCQSE_RREWOEAUTOREALLOCATED 0x011706 /* Recovered Read error - without ECC, auto reallocated */ +#define SCSI_KCQSE_RREWOERECOMMENDREASSIGN 0x011707 /* Recovered Read error - without ECC, recommend reassign */ +#define SCSI_KCQSE_RREWOERECOMMENDREWRITE 0x011708 /* Recovered Read error - without ECC, recommend rewrite */ +#define SCSI_KCQSE_RREWOEDATAREWRITTEN 0x011709 /* Recovered Read error - without ECC, data rewritten */ +#define SCSI_KCQSE_RREWE 0x011800 /* Recovered Read error - with ECC */ +#define SCSI_KCQSE_RDWEANDRETRIES 0x011801 /* Recovered data with ECC and retries */ +#define SCSI_KCQSE_RREWEAUTOREALLOCATED 0x011802 /* Recovered Read error - with ECC, auto reallocated */ +#define SCSI_KCQSE_RREWERECOMMENDREASSIGN 0x011805 /* Recovered Read error - with ECC, recommend reassign */ +#define SCSI_KCQSE_RDUSINGECCANDOFFSETS 0x011806 /* Recovered data using ECC and offsets */ +#define SCSI_KCQSE_RREWEDATAREWRITTEN 0x011807 /* Recovered Read error - with ECC, data rewritten */ +#define SCSI_KCQSE_DLNOTFOUND 0x011c00 /* Defect List not found */ +#define SCSI_KCQSE_PRIMARYDLNOTFOUND 0x011c01 /* Primary defect list not found */ +#define SCSI_KCQSE_GROWNDLNOTFOUND 0x011c02 /* Grown defect list not found */ +#define SCSI_KCQSE_PARTIALDLTRANSFERRED 0x011f00 /* Partial defect list transferred */ +#define SCSI_KCQSE_INTERNALTARGETFAILURE 0x014400 /* Internal target failure */ +#define SCSI_KCQSE_PFATHRESHOLDREACHED 0x015d00 /* PFA threshold reached */ +#define SCSI_KCQSE_PFATESTWARNING 0x015dff /* PFA test warning */ +#define SCSI_KCQSE_INTERNALLOGICFAILURE 0x018100 /* Internal logic failure */ + +/* Not Ready / Diagnostic Failure KCQ values */ + +#define SCSI_KCQNR_CAUSENOTREPORTABLE 0x020400 /* Not Ready - Cause not reportable. */ +#define SCSI_KCQNR_BECOMINGREADY 0x020401 /* Not Ready - becoming ready */ +#define SCSI_KCQNR_NEEDINITIALIZECOMMAND 0x020402 /* Not Ready - need initialize command (start unit) */ +#define SCSI_KCQNR_MANUALINTERVENTIONREQUIRED 0x020403 /* Not Ready - manual intervention required */ +#define SCSI_KCQNR_FORMATINPROGRESS 0x020404 /* Not Ready - format in progress */ +#define SCSI_KCQNR_SELFTESTINPROGRESS 0x020409 /* Not Ready - self-test in progress */ +#define SCSI_KCQNR_MEDIUMFORMATCORRUPTED 0x023100 /* Not Ready - medium format corrupted */ +#define SCSI_KCQNR_FORMATCOMMANDFAILED 0x023101 /* Not Ready - format command failed */ +#define SCSI_KCQNR_ESUNAVAILABLE 0x023502 /* Not Ready - enclosure services unavailable */ +#define SCSI_KCQNR_MEDIANOTPRESENT 0x023a00 /* Not Ready - media not present */ +#define SCSI_KCQDF_BRINGUPFAILORDEGRADEDMODE 0x024080 /* Diagnostic Failure - bring-up fail or degraded mode */ +#define SCSI_KCQDF_HARDDISKCONTROLLER 0x024081 /* Diagnostic Failure - Hard Disk Controller */ +#define SCSI_KCQDF_RAMMICROCODENOTLOADED 0x024085 /* Diagnostic Failure - RAM microcode not loaded */ +#define SCSI_KCQDF_RROCALIBRATION 0x024090 /* Diagnostic Failure - RRO Calibration */ +#define SCSI_KCQDF_CHANNELCALIBRATION 0x024091 /* Diagnostic Failure - Channel Calibration */ +#define SCSI_KCQDF_HEADLOAD 0x024092 /* Diagnostic Failure - Head Load */ +#define SCSI_KCQDF_WRITEAE 0x024093 /* Diagnostic Failure - Write AE */ +#define SCSI_KCQDF_12VOVERCURRENT 0x024094 /* Diagnostic Failure - 12V over current */ +#define SCSI_KCQDF_OTHERSPINDLEFAILURE 0x024095 /* Diagnostic Failure - Other spindle failure */ +#define SCSI_KCQDF_SELFRESET 0x0240b0 /* Diagnostic Failure - self-reset */ +#define SCSI_KCQDF_CONFIGNOTLOADED 0x024c00 /* Diagnostic Failure - config not loaded */ + +/* Medium error KCQ values */ + +#define SCSI_KCQME_WRITEFAULT 0x030300 /* Medium Error - write fault */ +#define SCSI_KCQME_WRITEFAULTAUTOREALLOCFAILED 0x030c02 /* Medium Error - write error - auto-realloc failed */ +#define SCSI_KCQME_WRITERTLIMITEXCEEDED 0x030cbb /* Medium Error - write recovery time limit exceeded */ +#define SCSI_KCQME_IDCRCERROR 0x031000 /* Medium Error - ID CRC error */ +#define SCSI_KCQME_UNRRE1 0x031100 /* Medium Error - unrecovered read error */ +#define SCSI_KCQME_READRETRIESEXHAUSTED 0x031101 /* Medium Error - read retries exhausted */ +#define SCSI_KCQME_ERRORTOOLONGTOCORRECT 0x031102 /* Medium Error - error too long to correct */ +#define SCSI_KCQME_UREAUTOREALLOCFAILED 0x031104 /* Medium Error - unrecovered read error - auto re-alloc failed */ +#define SCSI_KCQME_URERECOMMENDREASSIGN 0x03110b /* Medium Error - unrecovered read error - recommend reassign */ +#define SCSI_KCQME_READRTLIMITEXCEEDED 0x0311ff /* Medium Error - read recovery time limit exceeded */ +#define SCSI_KCQME_RECORDNOTFOUND 0x031401 /* Medium Error - record not found */ +#define SCSI_KCQME_DSME 0x031600 /* Medium Error - Data Sync Mark error */ +#define SCSI_KCQME_DSERECOMMENDREASSIGN 0x031604 /* Medium Error - Data Sync Error - recommend reassign */ +#define SCSI_KCQME_DLE 0x031900 /* Medium Error - defect list error */ +#define SCSI_KCQME_DLNOTAVAILABLE 0x031901 /* Medium Error - defect list not available */ +#define SCSI_KCQME_DLEINPRIMARYLIST 0x031902 /* Medium Error - defect list error in primary list */ +#define SCSI_KCQME_DLEINGROWNLIST 0x031903 /* Medium Error - defect list error in grown list */ +#define SCSI_KCQME_FEWERTHAN50PCTDLCOPIES 0x03190e /* Medium Error - fewer than 50% defect list copies */ +#define SCSI_KCQME_MEDIUMFORMATCORRUPTED 0x033100 /* Medium Error - medium format corrupted */ +#define SCSI_KCQME_FORMATCOMMANDFAILED 0x033101 /* Medium Error - format command failed */ +#define SCSI_KCQME_DATAAUTOREALLOCATED 0x038000 /* Medium Error - data auto-reallocated */ + +/* Hardware Error KCQ values */ + +#define SCSI_KCQHE_NOINDEXORSECTOR 0x040100 /* Hardware Error - no index or sector */ +#define SCSI_KCQHE_NOSEEKCOMPLETE 0x040200 /* Hardware Error - no seek complete */ +#define SCSI_KCQHE_WRITEFAULT 0x040300 /* Hardware Error - write fault */ +#define SCSI_KCQHE_COMMUNICATIONFAILURE 0x040800 /* Hardware Error - communication failure */ +#define SCSI_KCQHE_TRACKFOLLOWINGERROR 0x040900 /* Hardware Error - track following error */ +#define SCSI_KCQHE_UREINRESERVEDAREA 0x041100 /* Hardware Error - unrecovered read error in reserved area */ +#define SCSI_KCQHE_DSMEINRESERVEDAREA 0x041600 /* Hardware Error - Data Sync Mark error in reserved area */ +#define SCSI_KCQHE_DLE 0x041900 /* Hardware Error - defect list error */ +#define SCSI_KCQHE_DLEINPRIMARYLIST 0x041902 /* Hardware Error - defect list error in Primary List */ +#define SCSI_KCQHE_DLEINGROWNLIST 0x041903 /* Hardware Error - defect list error in Grown List */ +#define SCSI_KCQHE_REASSIGNFAILED 0x043100 /* Hardware Error - reassign failed */ +#define SCSI_KCQHE_NODEFECTSPAREAVAILABLE 0x043200 /* Hardware Error - no defect spare available */ +#define SCSI_KCQHE_UNSUPPORTEDENCLOSUREFUNCTION 0x043501 /* Hardware Error - unsupported enclosure function */ +#define SCSI_KCQHE_ESUNAVAILABLE 0x043502 /* Hardware Error - enclosure services unavailable */ +#define SCSI_KCQHE_ESTRANSFERFAILURE 0x043503 /* Hardware Error - enclosure services transfer failure */ +#define SCSI_KCQHE_ESREFUSED 0x043504 /* Hardware Error - enclosure services refused */ +#define SCSI_KCQHE_SELFTESTFAILED 0x043e03 /* Hardware Error - self-test failed */ +#define SCSI_KCQHE_UNABLETOUPDATESELFTEST 0x043e04 /* Hardware Error - unable to update self-test */ +#define SCSI_KCQHE_DMDIAGNOSTICFAIL 0x044080 /* Hardware Error - Degrade Mode. Diagnostic Fail */ +#define SCSI_KCQHE_DMHWERROR 0x044081 /* Hardware Error - Degrade Mode. H/W Error */ +#define SCSI_KCQHE_DMRAMMICROCODENOTLOADED 0x044085 /* Hardware Error - Degrade Mode. RAM microcode not loaded */ +#define SCSI_KCQHE_SEEKTESTFAILURE 0x044090 /* Hardware Error - seek test failure */ +#define SCSI_KCQHE_READWRITETESTFAILURE 0x0440a0 /* Hardware Error - read/write test failure */ +#define SCSI_KCQHE_DEVICESELFRESET 0x0440b0 /* Hardware Error - device self-reset */ +#define SCSI_KCQHE_COMPONENTMISMATCH 0x0440d0 /* Hardware Error - component mismatch */ +#define SCSI_KCQHE_INTERNALTARGETFAILURE 0x044400 /* Hardware Error - internal target failure */ +#define SCSI_KCQHE_INTERNALLOGICERROR 0x048100 /* Hardware Error - internal logic error */ +#define SCSI_KCQHE_COMMANDTIMEOUT 0x048200 /* Hardware Error - command timeout */ + +/* Illegal Request KCQ values */ + +#define SCSI_KCQIR_PARMLISTLENGTHERROR 0x051a00 /* Illegal Request - parm list length error */ +#define SCSI_KCQIR_INVALIDCOMMAND 0x052000 /* Illegal Request - invalid/unsupported command code */ +#define SCSI_KCQIR_LBAOUTOFRANGE 0x052100 /* Illegal Request - LBA out of range */ +#define SCSI_KCQIR_INVALIDFIELDINCBA 0x052400 /* Illegal Request - invalid field in CDB (Command Descriptor Block) */ +#define SCSI_KCQIR_INVALIDLUN 0x052500 /* Illegal Request - invalid LUN */ +#define SCSI_KCQIR_INVALIDFIELDSINPARMLIST 0x052600 /* Illegal Request - invalid fields in parm list */ +#define SCSI_KCQIR_PARAMETERNOTSUPPORTED 0x052601 /* Illegal Request - parameter not supported */ +#define SCSI_KCQIR_INVALIDPARMVALUE 0x052602 /* Illegal Request - invalid parm value */ +#define SCSI_KCQIR_IFPTHRESHOLDPARAMETER 0x052603 /* Illegal Request - invalid field parameter - threshold parameter */ +#define SCSI_KCQIR_INVALIDRELEASEOFPR 0x052604 /* Illegal Request - invalid release of persistent reservation */ +#define SCSI_KCQIR_IFPTMSFIRMWARETAG 0x052697 /* Illegal Request - invalid field parameter - TMS firmware tag */ +#define SCSI_KCQIR_IFPCHECKSUM 0x052698 /* Illegal Request - invalid field parameter - check sum */ +#define SCSI_KCQIR_IFPFIRMWARETAG 0x052699 /* Illegal Request - invalid field parameter - firmware tag */ +#define SCSI_KCQIR_COMMANDSEQUENCEERROR 0x052c00 /* Illegal Request - command sequence error */ +#define SCSI_KCQIR_UNSUPPORTEDENCLOSUREFUNCTION 0x053501 /* Illegal Request - unsupported enclosure function */ +#define SCSI_KCQIR_SAVINGPARMSNOTSUPPORTED 0x053900 /* Illegal Request - Saving parameters not supported */ +#define SCSI_KCQIR_INVALIDMESSAGE 0x054900 /* Illegal Request - invalid message */ +#define SCSI_KCQIR_MEDIALOADOREJECTFAILED 0x055300 /* Illegal Request - media load or eject failed */ +#define SCSI_KCQIR_UNLOADTAPEFAILURE 0x055301 /* Illegal Request - unload tape failure */ +#define SCSI_KCQIR_MEDIUMREMOVALPREVENTED 0x055302 /* Illegal Request - medium removal prevented */ +#define SCSI_KCQIR_SYSTEMRESOURCEFAILURE 0x055500 /* Illegal Request - system resource failure */ +#define SCSI_KCQIR_SYSTEMBUFFERFULL 0x055501 /* Illegal Request - system buffer full */ +#define SCSI_KCQIR_INSUFFICIENTRR 0x055504 /* Illegal Request - Insufficient Registration Resources */ + +/* Unit Attention KCQ values */ + +#define SCSI_KCQUA_NOTREADYTOTRANSITION 0x062800 /* Unit Attention - not-ready to ready transition (format complete) */ +#define SCSI_KCQUA_DEVICERESETOCCURRED 0x062900 /* Unit Attention - POR or device reset occurred */ +#define SCSI_KCQUA_POROCCURRED 0x062901 /* Unit Attention - POR occurred */ +#define SCSI_KCQUA_SCSIBUSRESETOCCURRED 0x062902 /* Unit Attention - SCSI bus reset occurred */ +#define SCSI_KCQUA_TARGETRESETOCCURRED 0x062903 /* Unit Attention - TARGET RESET occurred */ +#define SCSI_KCQUA_SELFINITIATEDRESETOCCURRED 0x062904 /* Unit Attention - self-initiated-reset occurred */ +#define SCSI_KCQUA_TRANSCEIVERMODECHANGETOSE 0x062905 /* Unit Attention - transceiver mode change to SE */ +#define SCSI_KCQUA_TRANSCEIVERMODECHANGETOLVD 0x062906 /* Unit Attention - transceiver mode change to LVD */ +#define SCSI_KCQUA_PARAMETERSCHANGED 0x062a00 /* Unit Attention - parameters changed */ +#define SCSI_KCQUA_MODEPARAMETERSCHANGED 0x062a01 /* Unit Attention - mode parameters changed */ +#define SCSI_KCQUA_LOGSELECTPARMSCHANGED 0x062a02 /* Unit Attention - log select parms changed */ +#define SCSI_KCQUA_RESERVATIONSPREEMPTED 0x062a03 /* Unit Attention - Reservations pre-empted */ +#define SCSI_KCQUA_RESERVATIONSRELEASED 0x062a04 /* Unit Attention - Reservations released */ +#define SCSI_KCQUA_REGISTRATIONSPREEMPTED 0x062a05 /* Unit Attention - Registrations pre-empted */ +#define SCSI_KCQUA_COMMANDSCLEARED 0x062f00 /* Unit Attention - commands cleared by another initiator */ +#define SCSI_KCQUA_OPERATINGCONDITIONSCHANGED 0x063f00 /* Unit Attention - target operating conditions have changed */ +#define SCSI_KCQUA_MICROCODECHANGED 0x063f01 /* Unit Attention - microcode changed */ +#define SCSI_KCQUA_CHANGEDOPERATINGDEFINITION 0x063f02 /* Unit Attention - changed operating definition */ +#define SCSI_KCQUA_INQUIRYPARAMETERSCHANGED 0x063f03 /* Unit Attention - inquiry parameters changed */ +#define SCSI_KCQUA_DEVICEIDENTIFIERCHANGED 0x063f05 /* Unit Attention - device identifier changed */ +#define SCSI_KCQUA_INVALIDAPMPARAMETERS 0x063f90 /* Unit Attention - invalid APM parameters */ +#define SCSI_KCQUA_WORLDWIDENAMEMISMATCH 0x063f91 /* Unit Attention - world-wide name mismatch */ +#define SCSI_KCQUA_PFATHRESHOLDREACHED 0x065d00 /* Unit Attention - PFA threshold reached */ +#define SCSI_KCQUA_PFATHRESHOLDEXCEEDED 0x065dff /* Unit Attention - PFA threshold exceeded */ + +/* Write Protect KCQ values */ + +#define SCSI_KCQWP_COMMANDNOTALLOWED 0x072700 /* Write Protect - command not allowed */ + +/* Aborted Command KCQ values */ + +#define SCSI_KCQAC_NOADDITIONALSENSECODE 0x0b0000 /* Aborted Command - no additional sense code */ +#define SCSI_KCQAC_SYNCDATATRANSFERERROR 0x0b1b00 /* Aborted Command - sync data transfer error (extra ACK) */ +#define SCSI_KCQAC_UNSUPPORTEDLUN 0x0b2500 /* Aborted Command - unsupported LUN */ +#define SCSI_KCQAC_ECHOBUFFEROVERWRITTEN 0x0b3f0f /* Aborted Command - echo buffer overwritten */ +#define SCSI_KCQAC_MESSAGEREJECTERROR 0x0b4300 /* Aborted Command - message reject error */ +#define SCSI_KCQAC_INTERNALTARGETFAILURE 0x0b4400 /* Aborted Command - internal target failure */ +#define SCSI_KCQAC_SELECTIONFAILURE 0x0b4500 /* Aborted Command - Selection/Reselection failure */ +#define SCSI_KCQAC_SCSIPARITYERROR 0x0b4700 /* Aborted Command - SCSI parity error */ +#define SCSI_KCQAC_INITIATORDETECTEDERRORECEIVED 0x0b4800 /* Aborted Command - initiator-detected error message received */ +#define SCSI_KCQAC_ILLEGALMESSAGE 0x0b4900 /* Aborted Command - inappropriate/illegal message */ +#define SCSI_KCQAC_DATAPHASEERROR 0x0b4b00 /* Aborted Command - data phase error */ +#define SCSI_KCQAC_OVERLAPPEDCOMMANDSATTEMPTED 0x0b4e00 /* Aborted Command - overlapped commands attempted */ +#define SCSI_KCQAC_LOOPINITIALIZATION 0x0b4f00 /* Aborted Command - due to loop initialization */ + +/* Other KCQ values: */ + +#define SCSO_KCQOTHER_MISCOMPARE 0x0e1d00 /* Miscompare - during verify byte check operation */ + +/* SSCSI Status Codes *******************************************************/ + +#define SCSI_STATUS_OK 0x00 /* OK */ +#define SCSI_STATUS_CHECKCONDITION 0x02 /* Check condition */ +#define SCSI_STATUS_CONDITIONMET 0x04 /* Condition met */ +#define SCSI_STATUS_BUSY 0x08 /* Busy */ +#define SCSI_STATUS_INTERMEDIATE 0x10 /* Intermediate */ +#define SCSI_STATUS_DATAOVERUNDERRUN 0x12 /* Data Under/Over Run? */ +#define SCSI_STATUS_INTERMEDIATECONDITIONMET 0x14 /* Intermediate - Condition met */ +#define SCSI_STATUS_RESERVATIONCONFLICT 0x18 /* Reservation conflict */ +#define SCSI_STATUS_COMMANDTERMINATED 0x22 /* Command terminated */ +#define SCSI_STATUS_QUEUEFULL 0x28 /* Queue (task set) full */ +#define SCSI_STATUS_ACAACTIVE 0x30 /* ACA active */ +#define SCSI_STATUS_TASKABORTED 0x40 /* Task aborted */ + +/* Definitions for selected SCSI commands ***********************************/ + +/* Inquiry */ + +#define SCSICMD_INQUIRYFLAGS_EVPD 0x01 /* Bit 0: EVPD */ + /* Bits 5-7: Peripheral Qualifier */ +#define SCSIRESP_INQUIRYPQ_CONNECTED 0x00 /* 000: Device is connected */ +#define SCSIRESP_INQUIRYPQ_NOTCONNECTED 0x20 /* 001: Device is NOT connected */ +#define SCSIRESP_INQUIRYPQ_NOTCAPABLE 0x60 /* 011: LUN not supported */ + /* Bits 0-4: Peripheral Device */ +#define SCSIRESP_INQUIRYPD_DIRECTACCESS 0x00 /* Direct-access block device */ +#define SCSIRESP_INQUIRYPD_SEQUENTIALACCESS 0x01 /* Sequential-access block device */ +#define SCSIRESP_INQUIRYPD_PRINTER 0x02 /* Printer device */ +#define SCSIRESP_INQUIRYPD_PROCESSOR 0x03 /* Processor device */ +#define SCSIRESP_INQUIRYPD_WRONCE 0x04 /* Write once device */ +#define SCSIRESP_INQUIRYPD_CDDVD 0x05 /* CD/DVD device */ +#define SCSIRESP_INQUIRYPD_SCANNER 0x06 /* Scanner device (obsolete) */ +#define SCSIRESP_INQUIRYPD_OPTICAL 0x07 /* Optical memory device */ +#define SCSIRESP_INQUIRYPD_MEDIUMCHANGER 0x08 /* Medium changer device (Jukebox) */ +#define SCSIRESP_INQUIRYPD_COMMUNICATIONS 0x09 /* Communications device (obsolete) */ +#define SCSIRESP_INQUIRYPD_STORAGEARRAY 0x0c /* Storage array controller device */ +#define SCSIRESP_INQUIRYPD_ENCLOSURESERVICES 0x0d /* Enclosure services device */ +#define SCSIRESP_INQUIRYPD_RBC 0x0e /* Simplified direct-access device */ +#define SCSIRESP_INQUIRYPD_OCRW 0x0f /* Optical reader/writer device */ +#define SCSIRESP_INQUIRYPD_BCC 0x10 /* Bridge controller commands */ +#define SCSIRESP_INQUIRYPD_OSD 0x11 /* Object-based storage device */ +#define SCSIRESP_INQUIRYPD_ADC 0x12 /* Automation/drive interface */ +#define SCSIRESP_INQUIRYPD_WKLU 0x1e /* Well-known logical unit */ +#define SCSIRESP_INQUIRYPD_UNKNOWN 0x1f /* Direct-access block device */ + +#define SCSIRESP_INQUIRYFLAGS1_RMB 0x80 /* Bit 7: RMB */ +#define SCSIRESP_INQUIRYFLAGS2_NORMACA 0x20 /* Bit 5: NormACA */ +#define SCSIRESP_INQUIRYFLAGS2_HISUP 0x10 /* Bit 4: HiSup */ +#define SCSIRESP_INQUIRYFLAGS2_FMTMASK 0x0f /* Bits 0-3: Response data format */ + +#define SCSIRESP_INQUIRYFLAGS3_SCCS 0x80 /* Bit 8: SCCS */ +#define SCSIRESP_INQUIRYFLAGS3_ACC 0x40 /* Bit 7: ACC */ +#define SCSIRESP_INQUIRYFLAGS3_TPGSMASK 0x30 /* Bits 4-5: TPGS */ +#define SCSIRESP_INQUIRYFLAGS3_3PC 0x08 /* Bit 3: 3PC */ +#define SCSIRESP_INQUIRYFLAGS3_PROTECT 0x01 /* Bit 0: Protect */ + +#define SCSIRESP_INQUIRYFLAGS4_BQUE 0x80 /* Bit 7: BQue */ +#define SCSIRESP_INQUIRYFLAGS4_ENCSERV 0x40 /* Bit 6: EncServ */ +#define SCSIRESP_INQUIRYFLAGS4_VS 0x20 /* Bit 5: VS */ +#define SCSIRESP_INQUIRYFLAGS4_MULTIP 0x10 /* Bit 4: MultIP */ +#define SCSIRESP_INQUIRYFLAGS4_MCHNGR 0x08 /* Bit 3: MChngr */ +#define SCSIRESP_INQUIRYFLAGS4_ADDR16 0x01 /* Bit 0: Addr16 */ + +#define SCSIRESP_INQUIRYFLAGS5_WBUS16 0x20 /* Bit 5: WBus16 */ +#define SCSIRESP_INQUIRYFLAGS5_SYNC 0x10 /* Bit 4: SYNC */ +#define SCSIRESP_INQUIRYFLAGS5_LINKED 0x08 /* Bit 3: LINKED */ +#define SCSIRESP_INQUIRYFLAGS5_CMDQUEUE 0x02 /* Bit 1: CmdQue */ +#define SCSIRESP_INQUIRYFLAGS5_VS 0x01 /* Bit 0: VS */ + +#define SCSIRESP_INQUIRYFLAGS6_CLOCKINGMASK 0xc0 /* Bits 2-3: Clocking */ +#define SCSIRESP_INQUIRYFLAGS6_QAS 0x02 /* Bit 1: QAS */ +#define SCSIRESP_INQUIRYFLAGS6_IUS 0x01 /* Bit 0: IUS */ + +/* Sense data */ + +/* Sense data response codes */ + +#define SCSIRESP_SENSEDATA_CURRENTFIXED 0x70 /* Byte 1 is always the response code */ +#define SCSIRESP_SENSEDATA_DEFERREDFIXED 0x71 +#define SCSIRESP_SENSEDATA_CURRENTDESC 0x72 +#define SCSIRESP_SENSEDATA_DEFERREDDESC 0x73 + +#define SCSIRESP_SENSEDATA_RESPVALID 0x80 + +/* Fixed sense data flags */ + +#define SCSIRESP_SENSEDATA_FILEMARK 0x80 /* Bit 7: FileMark */ +#define SCSIRESP_SENSEDATA_EOM 0x40 /* Bit 6: EOM */ +#define SCSIRESP_SENSEDATA_ILI 0x20 /* Bit 5: ILI */ +#define SCSIRESP_SENSEDATA_SENSEKEYMASK 0x0f /* Bits 0-3: Sense key */ +#define SCSIRESP_SENSEDATA_NOSENSE 0x00 /* Nothing to be reported */ +#define SCSIRESP_SENSEDATA_RECOVEREDERROR 0x01 /* Successful after recovery action */ +#define SCSIRESP_SENSEDATA_NOTREADY 0x02 /* Logical unit is not accessible */ +#define SCSIRESP_SENSEDATA_MEDIUMERROR 0x03 /* Error possibly caused by flaw in medium */ +#define SCSIRESP_SENSEDATA_HARDWAREERROR 0x04 /* Non-recoverable hardware error */ +#define SCSIRESP_SENSEDATA_ILLEGALREQUEST 0x05 /* Error in received request */ +#define SCSIRESP_SENSEDATA_UNITATTENTION 0x06 /* Unit attention condition */ +#define SCSIRESP_SENSEDATA_DATAPROTECT 0x07 /* Action failed, medium protected */ +#define SCSIRESP_SENSEDATA_BLANKCHECK 0x08 /* Encountered blank media */ +#define SCSIRESP_SENSEDATA_VENDORSPECIFIC 0x09 /* Vendor specific condition */ +#define SCSIRESP_SENSEDATA_ABORTEDCOMMAND 0x0b /* Command was aborted */ + +#define SCSIRESP_SENSEDATA_KEYVALID 0x80 /* Sense-specific data valid */ + +/* Mode Select 6 */ + +#define SCSICMD_MODESELECT6_PF 0x10 /* Bit 4: PF */ +#define SCSICMD_MODESELECT6_SP 0x01 /* Bit 0: SP */ + +/* Mode Sense 6 */ + +#define SCSICMD_MODESENSE6_DBD 0x08 /* Bit 3: PF */ + +#define SCSICMD_MODESENSE_PCMASK 0xc0 /* Bits 6-7: Page control (PC) */ +#define SCSICMD_MODESENSE_PCCURRENT 0x00 /* Current values */ +#define SCSICMD_MODESENSE_PCCHANGEABLE 0x40 /* Changeable values */ +#define SCSICMD_MODESENSE_PCDEFAULT 0x80 /* Default values */ +#define SCSICMD_MODESENSE_PCSAVED 0xc0 /* Saved values */ +#define SCSICMD_MODESENSE_PGCODEMASK 0x3f /* Bits 0-5: Page code */ + +#define SCSICMD_MODESENSE6_PCDEFAULT 0x80 /* Default values */ + /* Direct-access device page codes */ +#define SCSIRESP_MODESENSE_PGCCODE_VENDOR 0x00 /* Vendor-specific */ +#define SCSIRESP_MODESENSE_PGCCODE_RWERROR 0x01 /* Read/Write error recovery mode page */ +#define SCSIRESP_MODESENSE_PGCCODE_RECONNECT 0x02 /* Disconnect-reconnect mode page */ +#define SCSIRESP_MODESENSE_PGCCODE_FORMATDEV 0x03 /* Format device mode page (obsolete) */ +#define SCSIRESP_MODESENSE_PGCCODE_RIGID 0x04 /* Rigid disk geometry mode page (obsolete) */ +#define SCSIRESP_MODESENSE_PGCCODE_FLEXIBLE 0x05 /* Flexible disk geometry mode page (obsolete) */ +#define SCSIRESP_MODESENSE_PGCCODE_VERIFY 0x07 /* Verify error recovery mode page */ +#define SCSIRESP_MODESENSE_PGCCODE_CACHING 0x08 /* Caching mode page */ +#define SCSIRESP_MODESENSE_PGCCODE_CONTROL 0x0a /* Control mode page (0x0a/0x00) */ +#define SCSIRESP_MODESENSE_PGCCODE_CONTROLEXT 0x0a /* Control extension mode page (0x0a/0x01) */ +#define SCSIRESP_MODESENSE_PGCCODE_MEDIUMTYPES 0x0b /* Medum types supported mode page (obsolete) */ +#define SCSIRESP_MODESENSE_PGCCODE_NP 0x0c /* Notch and partition mode page (obsolete) */ +#define SCSIRESP_MODESENSE_PGCCODE_XOR 0x10 /* XOR control mode page */ +#define SCSIRESP_MODESENSE_PGCCODE_ES 0x14 /* Enclosure services mode page */ +#define SCSIRESP_MODESENSE_PGCCODE_PSLUN 0x18 /* Protocol-specific LUN mode page */ +#define SCSIRESP_MODESENSE_PGCCODE_PSPORT 0x19 /* Protocol-specific port mode page */ +#define SCSIRESP_MODESENSE_PGCCODE_POWER 0x1a /* Power condition mode page */ +#define SCSIRESP_MODESENSE_PGCCODE_IE 0x1c /* Informational exceptions control mode page (0x1c/0x00) */ +#define SCSIRESP_MODESENSE_PGCCODE_BC 0x1c /* Background control mode page (0x1c/0x01) */ +#define SCSIRESP_MODESENSE_PGCCODE_RETURNALL 0x3f /* Return all mode pages */ + /* Direct-access caching mode page */ +#define SCSIRESP_CACHINGMODEPG_PS 0x80 /* Byte 0, Bit 7: PS */ +#define SCSIRESP_CACHINGMODEPG_SPF 0x60 /* Byte 0, Bit 6: SPF */ +#define SCSIRESP_CACHINGMODEPG_IC 0x80 /* Byte 2, Bit 7: IC */ +#define SCSIRESP_CACHINGMODEPG_ABPF 0x40 /* Byte 2, Bit 6: ABPF */ +#define SCSIRESP_CACHINGMODEPG_CAP 0x20 /* Byte 2, Bit 5: CAP */ +#define SCSIRESP_CACHINGMODEPG_DISC 0x10 /* Byte 2, Bit 4: DISC */ +#define SCSIRESP_CACHINGMODEPG_SIZE 0x08 /* Byte 2, Bit 3: SIZE */ +#define SCSIRESP_CACHINGMODEPG_WCE 0x04 /* Byte 2, Bit 2: Write cache enable (WCE) */ +#define SCSIRESP_CACHINGMODEPG_MF 0x02 /* Byte 2, Bit 1: MF */ +#define SCSIRESP_CACHINGMODEPG_RCD 0x01 /* Byte 2, Bit 0: Read cache disable (RCD) */ + +#define SCSIRESP_MODEPARMHDR_DAPARM_WP 0x80 /* Bit 7: WP (Direct-access block devices only) */ +#define SCSIRESP_MODEPARMHDR_DAPARM_DBPFUA 0x10 /* Bit 4: DBOFUA (Direct-access block devices only) */ + +#define SCSIRESP_PAGEFMT_PS 0x80 /* Bit 7: PS */ +#define SCSIRESP_PAGEFMT_SPF 0x40 /* Bit 6: SPF */ +#define SCSIRESP_PAGEFMT_PGCODEMASK 0x3f /* Bits 0-5: Page code */ + +/* Prevent / Allow Medium Removal */ + +#define SCSICMD_PREVENTMEDIUMREMOVAL_TRANSPORT 0x01 /* Removal prohibited from data transport */ +#define SCSICMD_PREVENTMEDIUMREMOVAL_MCHANGER 0x02 /* Removal prohibited from medium changer */ + +/* Read format capacities */ + +#define SCIRESP_RDFMTCAPACITIES_UNFORMATED 0x01 /* Unformatted media */ +#define SCIRESP_RDFMTCAPACITIES_FORMATED 0x02 /* Formatted media */ +#define SCIRESP_RDFMTCAPACITIES_NOMEDIA 0x03 /* No media */ + +/* Read 6 */ + +#define SCSICMD_READ6_MSLBAMASK 0x1f + +/* Write 6 */ + +#define SCSICMD_WRITE6_MSLBAMASK 0x1f + +/* Mode Select 10 */ + +#define SCSICMD_MODESELECT10_PF 0x10 /* Bit 4: PF */ +#define SCSICMD_MODESELECT10_SP 0x01 /* Bit 0: SP */ + +/* Mode Sense 10 */ + +#define SCSICMD_MODESENSE10_LLBAA 0x10 /* Bit 4: LLBAA */ +#define SCSICMD_MODESENSE10_DBD 0x08 /* Bit 3: PF */ + +/* Read 10 */ + +#define SCSICMD_READ10FLAGS_RDPROTECTMASK 0xe0 +#define SCSICMD_READ10FLAGS_DPO 0x10 /* Disable Page Out */ +#define SCSICMD_READ10FLAGS_FUA 0x08 +#define SCSICMD_READ10FLAGS_FUANV 0x02 + +/* Write 10 */ + +#define SCSICMD_WRITE10FLAGS_WRPROTECTMASK 0xe0 +#define SCSICMD_WRITE10FLAGS_DPO 0x10 /* Disable Page Out */ +#define SCSICMD_WRITE10FLAGS_FUA 0x08 +#define SCSICMD_WRITE10FLAGS_FUANV 0x02 + +/* Verify 10 */ + +#define SCSICMD_VERIFY10_VRPROTECTMASK 0xe0 /* Byte 1: Bits 5-7: VRPROTECT */ +#define SCSICMD_VERIFY10_DPO 0x10 /* Byte 1: Bit 4: Disable Page Out (DPO) */ +#define SCSICMD_VERIFY10_BYTCHK 0x02 /* Byte 1: Bit 2: BytChk */ + +/* Read 12 */ + +#define SCSICMD_READ12FLAGS_RDPROTECTMASK 0xe0 +#define SCSICMD_READ12FLAGS_DPO 0x10 /* Disable Page Out */ +#define SCSICMD_READ12FLAGS_FUA 0x08 +#define SCSICMD_READ12FLAGS_FUANV 0x02 + +/* Write 12 */ + +#define SCSICMD_WRITE12FLAGS_WRPROTECTMASK 0xe0 +#define SCSICMD_WRITE12FLAGS_DPO 0x10 /* Disable Page Out */ +#define SCSICMD_WRITE12FLAGS_FUA 0x08 +#define SCSICMD_WRITE12FLAGS_FUANV 0x02 + +/* Verify 12 */ + +#define SCSICMD_VERIFY12_VRPROTECTMASK 0xe0 /* Byte 1: Bits 5-7: VRPROTECT */ +#define SCSICMD_VERIFY12_DPO 0x10 /* Byte 1: Bit 4: Disable Page Out (DPO) */ +#define SCSICMD_VERIFY12_BYTCHK 0x02 /* Byte 1: Bit 2: BytChk */ + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +/* Format structures for selected SCSI primary commands */ + +#define SCSICMD_TESTUNITREADY_SIZEOF 6 + +struct scsicmd_requestsense_s +{ + uint8_t opcode; /* 0: 0x03 */ + uint8_t flags; /* 1: See SCSICMD_REQUESTSENSE_FLAGS_* */ + uint8_t reserved[2]; /* 2-3: Reserved */ + uint8_t alloclen; /* 4: Allocation length */ + uint8_t control; /* 5: Control */ +}; +#define SCSICMD_REQUESTSENSE_SIZEOF 6 +#define SCSICMD_REQUESTSENSE_MSSIZEOF 12 /* MS-Windows REQUEST SENSE with cbw->cdblen == 12 */ + +struct scsiresp_fixedsensedata_s +{ + uint8_t code; /* 0: Response code See SCSIRESP_SENSEDATA_*FIXED defns */ + uint8_t obsolete; /* 1: */ + uint8_t flags; /* 2: See SCSIRESP_SENSEDATA_* definitions */ + uint8_t info[4]; /* 3-6: Information */ + uint8_t len; /* 7: Additional length */ + uint8_t cmdinfo[4]; /* 8-11: Command-specific information */ + uint8_t code2; /* 12: Additional sense code */ + uint8_t qual2; /* 13: Additional sense code qualifier */ + uint8_t fru; /* 14: Field replacement unit code */ + uint8_t key[3]; /* 15-17: Sense key specific */ + /* 18-: Additional bytes may follow */ +}; +#define SCSIRESP_FIXEDSENSEDATA_SIZEOF 18 /* Minimum size */ + +struct scscicmd_inquiry_s +{ + uint8_t opcode; /* 0: 0x12 */ + uint8_t flags; /* 1: See SCSICMD_INQUIRY_FLAGS_* */ + uint8_t pagecode; /* 2: Page code */ + uint8_t alloclen[2]; /* 3-4: Allocation length */ + uint8_t control; /* 5: Control */ +}; +#define SCSICMD_INQUIRY_SIZEOF 6 + +struct scsiresp_inquiry_s +{ + /* Mandatory */ + + uint8_t qualtype; /* 0: Bits 5-7: Peripheral qualifier; Bits 0-4: Peripheral device type */ + uint8_t flags1; /* 1: See SCSIRESP_INQUIRY_FLAGS1_* */ + uint8_t version; /* 2: Version */ + uint8_t flags2; /* 3: See SCSIRESP_INQUIRY_FLAGS2_* */ + uint8_t len; /* 4: Additional length */ + uint8_t flags3; /* 5: See SCSIRESP_INQUIRY_FLAGS3_* */ + uint8_t flags4; /* 6: See SCSIRESP_INQUIRY_FLAGS4_* */ + uint8_t flags5; /* 7: See SCSIRESP_INQUIRY_FLAGS5_* */ + uint8_t vendorid[8]; /* 8-15: T10 Vendor Identification */ + uint8_t productid[16]; /* 16-31: Product Identification */ + uint8_t revision[4]; /* 32-35: Product Revision Level */ + + /* Optional */ + + uint8_t vendor[20]; /* 36-55: Vendor specific */ + uint8_t flags6; /* 56: See SCSIRESP_INQUIRY_FLAGS6_* */ + uint8_t reserved1; /* 57: Reserved */ + uint8_t version1[2]; /* 58-59: Version Descriptor 1 */ + uint8_t version2[2]; /* 60-61: Version Descriptor 2 */ + uint8_t version3[2]; /* 62-63: Version Descriptor 3 */ + uint8_t version4[2]; /* 64-65: Version Descriptor 4 */ + uint8_t version5[2]; /* 66-67: Version Descriptor 5 */ + uint8_t version6[2]; /* 68-69: Version Descriptor 6 */ + uint8_t version7[2]; /* 70-71: Version Descriptor 7 */ + uint8_t version8[2]; /* 72-73: Version Descriptor 8 */ + uint8_t reserved2[22]; /* 74-95: Reserved */ + /* 96-: Vendor-specific parameters may follow */ +}; +#define SCSIRESP_INQUIRY_SIZEOF 36 /* Minimum size */ + +struct scsicmd_modeselect6_s +{ + uint8_t opcode; /* 0x15 */ + uint8_t flags; /* 1: See SCSICMD_MODESELECT6_FLAGS_* */ + uint8_t reserved[2]; /* 2-3: Reserved */ + uint8_t plen; /* 4: Parameter list length */ + uint8_t control; /* 5: Control */ +}; +#define SCSICMD_MODESELECT6_SIZEOF 6 + +struct scsicmd_modesense6_s +{ + uint8_t opcode; /* 0x1a */ + uint8_t flags; /* 1: See SCSICMD_MODESENSE6_FLAGS_* */ + uint8_t pcpgcode; /* 2: Bits 6-7: PC, bits 0-5: page code */ + uint8_t subpgcode; /* 3: subpage code */ + uint8_t alloclen; /* 4: Allocation length */ + uint8_t control; /* 5: Control */ +}; +#define SCSICMD_MODESENSE6_SIZEOF 6 + +struct scsiresp_modeparameterhdr6_s +{ + uint8_t mdlen; /* 0: Mode data length */ + uint8_t type; /* 1: Medium type */ + uint8_t param; /* 2: Device-specific parameter */ + uint8_t bdlen; /* 3: Block descriptor length */ +}; +#define SCSIRESP_MODEPARAMETERHDR6_SIZEOF 4 + +struct scsiresp_blockdesc_s +{ + uint8_t density; /* 0: density code */ + uint8_t nblocks[3]; /* 1-3: Number of blocks */ + uint8_t reserved; /* 4: reserved */ + uint8_t blklen[3]; /* 5-7: Block len */ +}; +#define SCSIRESP_BLOCKDESC_SIZEOF 8 + +struct scsiresp_pageformat_s +{ + uint8_t pgcode; /* 0: See SCSIRESP_PAGEFMT_* definitions */ + uint8_t pglen; /* 1: Page length (n-1) */ + uint8_t parms[1]; /* 2-n: Mode parameters */ +}; + +struct scsiresp_subpageformat_s +{ + uint8_t pgcode; /* 0: See SCSIRESP_PAGEFMT_* definitions */ + uint8_t subpgcode; /* 1: sub-page code */ + uint8_t pglen[2]; /* 2-3: Page length (n-3) */ + uint8_t parms[1]; /* 4-n: Mode parameters */ +}; + +struct scsiresp_cachingmodepage_s +{ + uint8_t pgcode; /* 0: Bit 7: PS; Bit 6: SPF, Bits 0-5: page code == 8 */ + uint8_t len; /* 1: Page length (18) */ + uint8_t flags1; /* 2: See SCSIRESP_CACHINGMODEPG_* definitions */ + uint8_t priority; /* 3: Bits 4-7: Demand read retention priority; Bits 0-3: Write retention priority */ + uint8_t dpflen[2]; /* 4-5: Disable prefetch transfer length */ + uint8_t minpf[2]; /* 6-7: Minimum pre-fetch */ + uint8_t maxpf[2]; /* 8-9: Maximum pre-fetch */ + uint8_t maxpfc[2]; /* 10-11: Maximum pref-fetch ceiling */ + uint8_t flags2; /* 12: See SCSIRESP_CACHINGMODEPG_* definitions */ + uint8_t nsegments; /* 13: Number of cache segments */ + uint8_t segsize[2]; /* 14-15: Cache segment size */ + uint8_t reserved; /* 16: Reserved */ + uint8_t obsolete[3]; /* 17-19: Obsolete */ +}; + +/* Format structures for selected SCSI block commands */ + +struct scsicmd_read6_s +{ + uint8_t opcode; /* 0: 0x08 */ + uint8_t mslba; /* 1: Bits 5-7: reserved; Bits 0-6: MS Logical Block Address (LBA) */ + uint8_t lslba[2]; /* 2-3: LS Logical Block Address (LBA) */ + uint8_t xfrlen; /* 4: Transfer length (in contiguous logical blocks) */ + uint8_t control; /* 5: Control */ +}; +#define SCSICMD_READ6_SIZEOF 6 + +struct scsicmd_write6_s +{ + uint8_t opcode; /* 0: 0x0a */ + uint8_t mslba; /* 1: Bits 5-7: reserved; Bits 0-6: MS Logical Block Address (LBA) */ + uint8_t lslba[2]; /* 2-3: LS Logical Block Address (LBA) */ + uint8_t xfrlen; /* 4: Transfer length (in contiguous logical blocks) */ + uint8_t control; /* 5: Control */ +}; +#define SCSICMD_WRITE6_SIZEOF 6 + +struct scsicmd_startstopunit_s +{ + uint8_t opcode; /* 0: 0x1b */ + uint8_t immed; /* 1: Bits 2-7: Reserved, Bit 0: Immed */ + uint8_t reserved; /* 2: reserved */ + uint8_t pcm; /* 3: Bits 4-7: Reserved, Bits 0-3: Power condition modifier */ + uint8_t pc; /* 4: Bits 4-7: Power condition, Bit 2: NO_FLUSH, Bit 1: LOEJ, Bit 0: START */ + uint8_t control; /* 5: Control */ +}; +#define SCSICMD_STARTSTOPUNIT_SIZEOF 6 + +struct scsicmd_preventmediumremoval_s +{ + uint8_t opcode; /* 0: 0x1e */ + uint8_t reserved[3]; /* 1-3: Reserved */ + uint8_t prevent; /* 4: Bits 2-7: Reserved, Bits 0:1: prevent */ + uint8_t control; /* 5: Control */ +}; +#define SCSICMD_PREVENTMEDIUMREMOVAL_SIZEOF 6 + +struct scsicmd_readformatcapcacities_s +{ + uint8_t opcode; /* 0: 0x23 */ + uint8_t reserved[6]; /* 1-6: Reserved */ + uint8_t alloclen[2]; /* 7-8: Allocation length */ + uint8_t control; /* 9: Control */ +}; +#define SCSICMD_READFORMATCAPACITIES_SIZEOF 10 + +struct scsiresp_readformatcapacities_s +{ + /* Current capacity header */ + + uint8_t reserved[3]; /* 0-2: Reserved */ + uint8_t listlen; /* 3: Capacity list length */ + + /* Current/Maximum Capacity Descriptor (actually a separate structure) */ + + uint8_t nblocks[4]; /* 4-7: Number of blocks */ + uint8_t type; /* 8: Bits 2-7: Reserved, Bits 0-1: Descriptor type */ + uint8_t blocklen[3]; /* 9-11: Block length */ +}; +#define SCSIRESP_READFORMATCAPACITIES_SIZEOF 12 +#define SCSIRESP_CURRCAPACITYDESC_SIZEOF 8 + +struct scsiresp_formattedcapacitydesc_s +{ + uint8_t nblocks[4]; /* 0-3: Number of blocks */ + uint8_t type; /* 4: Bits 2-7: Type, bits 0-1, reserved */ + uint8_t param[3]; /* 5-7: Type dependent parameter */ +}; +#define SCSIRESP_FORMATTEDCAPACITYDESC_SIZEOF 8 + +struct scsicmd_readcapacity10_s +{ + uint8_t opcode; /* 0: 0x25 */ + uint8_t reserved1; /* 1: Bits 1-7: Reserved, Bit 0: Obsolete */ + uint8_t lba[4]; /* 2-5: Logical block address (LBA) */ + uint8_t reserved2[2]; /* 6-7: Reserved */ + uint8_t pmi; /* 8: Bits 1-7 Reserved; Bit 0: PMI */ + uint8_t control; /* 9: Control */ +}; +#define SCSICMD_READCAPACITY10_SIZEOF 10 + +struct scsiresp_readcapacity10_s +{ + uint8_t lba[4]; /* 0-3: Returned logical block address (LBA) */ + uint8_t blklen[4]; /* 4-7: Logical block length (in bytes) */ +}; +#define SCSIRESP_READCAPACITY10_SIZEOF 8 + +struct scsicmd_read10_s +{ + uint8_t opcode; /* 0: 0x28 */ + uint8_t flags; /* 1: See SCSICMD_READ10FLAGS_* */ + uint8_t lba[4]; /* 2-5: Logical Block Address (LBA) */ + uint8_t groupno; /* 6: Bits 5-7: reserved; Bits 0-6: group number */ + uint8_t xfrlen[2]; /* 7-8: Transfer length (in contiguous logical blocks) */ + uint8_t control; /* 9: Control */ +}; +#define SCSICMD_READ10_SIZEOF 10 + +struct scsicmd_write10_s +{ + uint8_t opcode; /* 0: 0x2a */ + uint8_t flags; /* 1: See SCSICMD_WRITE10FLAGS_* */ + uint8_t lba[4]; /* 2-5: Logical Block Address (LBA) */ + uint8_t groupno; /* 6: Bits 5-7: reserved; Bits 0-6: group number */ + uint8_t xfrlen[2]; /* 7-8: Transfer length (in contiguous logical blocks) */ + uint8_t control; /* 9: Control */ +}; +#define SCSICMD_WRITE10_SIZEOF 10 + +struct scsicmd_verify10_s +{ + uint8_t opcode; /* 0: 0x2f */ + uint8_t flags; /* 1: See SCSICMD_VERIFY10_* definitions */ + uint8_t lba[4]; /* 2-5: Logical block address (LBA) */ + uint8_t groupno; /* 6: Bit 7: restricted; Bits 5-6: Reserved, Bits 0-4: Group number */ + uint8_t len[2]; /* 7-8: Verification length (in blocks) */ + uint8_t control; /* 9: Control */ +}; +#define SCSICMD_VERIFY10_SIZEOF 10 + +struct scsicmd_synchronizecache10_s +{ + uint8_t opcode; /* 0: 0x35 */ + uint8_t flags; /* 1: See SCSICMD_SYNCHRONIZECACHE10_* definitions */ + uint8_t lba[4]; /* 2-5: Logical block address (LBA) */ + uint8_t groupno; /* 6: Bit 7: restricted; Bits 5-6: Reserved, Bits 0-4: Group number */ + uint8_t len[2]; /* 7-8: Number of logical blocks */ + uint8_t control; /* 9: Control */ +}; +#define SCSICMD_SYNCHRONIZECACHE10_SIZEOF 10 + +struct scsicmd_modeselect10_s +{ + uint8_t opcode; /* 0: 0x55 */ + uint8_t flags; /* 1: See SCSICMD_MODESELECT10_FLAGS_* */ + uint8_t reserved[5]; /* 2-6: Reserved */ + uint8_t parmlen[2]; /* 7-8: Parameter list length */ + uint8_t control; /* 9: Control */ +}; +#define SCSICMD_MODESELECT10_SIZEOF 10 + +struct scsiresp_modeparameterhdr10_s +{ + uint8_t mdlen[2]; /* 0-1: Mode data length */ + uint8_t type; /* 2: Medium type */ + uint8_t param; /* 3: Device-specific parameter */ + uint8_t reserved[2]; /* 4-5: reserved */ + uint8_t bdlen[2]; /* 6-7: Block descriptor length */ +}; +#define SCSIRESP_MODEPARAMETERHDR10_SIZEOF 8 + +struct scsicmd_modesense10_s +{ + uint8_t opcode; /* O: 0x5a */ + uint8_t flags; /* 1: See SCSICMD_MODESENSE10_FLAGS_* */ + uint8_t pcpgcode; /* 2: Bits 6-7: PC, bits 0-5: page code */ + uint8_t subpgcode; /* 3: subpage code */ + uint8_t reserved[3]; /* 4-6: reserved */ + uint8_t alloclen[2]; /* 7-8: Allocation length */ + uint8_t control; /* 9: Control */ +}; +#define SCSICMD_MODESENSE10_SIZEOF 10 + +struct scsicmd_readcapacity16_s +{ + uint8_t opcode; /* 0: 0x9e */ + uint8_t action; /* 1: Bits 5-7: Reserved, Bits 0-4: Service action */ + uint8_t lba[8]; /* 2-9: Logical block address (LBA) */ + uint8_t len[4]; /* 10-13: Allocation length */ + uint8_t reserved; /* 14: Reserved */ + uint8_t control; /* 15: Control */ +}; +#define SCSICMD_READCAPACITY16_SIZEOF 16 + +struct scsicmd_read12_s +{ + uint8_t opcode; /* 0: 0xa8 */ + uint8_t flags; /* 1: See SCSICMD_READ12FLAGS_* */ + uint8_t lba[4]; /* 2-5: Logical Block Address (LBA) */ + uint8_t xfrlen[4]; /* 6-9: Transfer length (in contiguous logical blocks) */ + uint8_t groupno; /* 10: Bit 7: restricted; Bits 5-6: reserved; Bits 0-6: group number */ + uint8_t control; /* 11: Control */ +}; +#define SCSICMD_READ12_SIZEOF 12 + +struct scsicmd_write12_s +{ + uint8_t opcode; /* 0: 0xaa */ + uint8_t flags; /* 1: See SCSICMD_WRITE12FLAGS_* */ + uint8_t lba[4]; /* 2-5: Logical Block Address (LBA) */ + uint8_t xfrlen[4]; /* 6-9: Transfer length (in contiguous logical blocks) */ + uint8_t groupno; /* 10: Bit 7: restricted; Bits 5-6: reserved; Bits 0-6: group number */ + uint8_t control; /* 11: Control */ +}; +#define SCSICMD_WRITE12_SIZEOF 12 + +struct scsicmd_verify12_s +{ + uint8_t opcode; /* 0: 0xaf */ + uint8_t flags; /* 1: See SCSICMD_VERIFY12_* definitions */ + uint8_t lba[4]; /* 2-5: Logical block address (LBA) */ + uint8_t len[4]; /* 6-9: Verification length */ + uint8_t groupno; /* 10: Bit 7: restricted; Bits 5-6: Reserved, Bits 0-4: Group number */ + uint8_t control; /* 11: Control */ +}; +#define SCSICMD_VERIFY12_SIZEOF 12 + +/**************************************************************************** + * Public Functions Definitions + ****************************************************************************/ + +#undef EXTERN +#if defined(__cplusplus) +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +#undef EXTERN +#if defined(__cplusplus) +} +#endif + +#endif /* __INCLUDE_NUTTX_SCSI_H */ diff --git a/kernel/cherryusb/class/msc/usbd_msc.c b/kernel/cherryusb/class/msc/usbd_msc.c new file mode 100644 index 0000000..6523ffb --- /dev/null +++ b/kernel/cherryusb/class/msc/usbd_msc.c @@ -0,0 +1,963 @@ +/* + * Copyright (c) 2022, sakumisu + * Copyright (c) 2024, zhihong chen + * + * SPDX-License-Identifier: Apache-2.0 + */ +#include "usbd_core.h" +#include "usbd_msc.h" +#include "usb_scsi.h" + +#undef USB_DBG_TAG +#define USB_DBG_TAG "usbd_msc" +#include "usb_log.h" + +#define MSD_OUT_EP_IDX 0 +#define MSD_IN_EP_IDX 1 + +/* Describe EndPoints configuration */ +static struct usbd_endpoint mass_ep_data[CONFIG_USBDEV_MAX_BUS][2]; + +/* MSC Bulk-only Stage */ +enum Stage { + MSC_READ_CBW = 0, /* Command Block Wrapper */ + MSC_DATA_OUT = 1, /* Data Out Phase */ + MSC_DATA_IN = 2, /* Data In Phase */ + MSC_SEND_CSW = 3, /* Command Status Wrapper */ + MSC_WAIT_CSW = 4, /* Command Status Wrapper */ +}; + +/* Device data structure */ +USB_NOCACHE_RAM_SECTION struct usbd_msc_priv { + /* state of the bulk-only state machine */ + enum Stage stage; + USB_MEM_ALIGNX struct CBW cbw; + USB_MEM_ALIGNX struct CSW csw; + + USB_MEM_ALIGNX bool readonly; + bool popup; + uint8_t sKey; /* Sense key */ + uint8_t ASC; /* Additional Sense Code */ + uint8_t ASQ; /* Additional Sense Qualifier */ + uint8_t max_lun; + uint32_t start_sector; + uint32_t nsectors; + uint32_t scsi_blk_size[CONFIG_USBDEV_MSC_MAX_LUN]; + uint32_t scsi_blk_nbr[CONFIG_USBDEV_MSC_MAX_LUN]; + + USB_MEM_ALIGNX uint8_t block_buffer[CONFIG_USBDEV_MSC_MAX_BUFSIZE]; + +#if defined(CONFIG_USBDEV_MSC_THREAD) + usb_osal_mq_t usbd_msc_mq; + usb_osal_thread_t usbd_msc_thread; + uint32_t nbytes; +#elif defined(CONFIG_USBDEV_MSC_POLLING) + uint32_t event; + uint32_t nbytes; +#endif +} g_usbd_msc[CONFIG_USBDEV_MAX_BUS]; + +#ifdef CONFIG_USBDEV_MSC_THREAD +static void usbdev_msc_thread(CONFIG_USB_OSAL_THREAD_SET_ARGV); +#endif + +static void usdb_msc_set_max_lun(uint8_t busid) +{ + g_usbd_msc[busid].max_lun = CONFIG_USBDEV_MSC_MAX_LUN - 1u; +} + +static void usbd_msc_reset(uint8_t busid) +{ + g_usbd_msc[busid].stage = MSC_READ_CBW; +} + +static int msc_storage_class_interface_request_handler(uint8_t busid, struct usb_setup_packet *setup, uint8_t **data, uint32_t *len) +{ + USB_LOG_DBG("MSC Class request: " + "bRequest 0x%02x\r\n", + setup->bRequest); + + switch (setup->bRequest) { + case MSC_REQUEST_RESET: + usbd_msc_reset(busid); + break; + + case MSC_REQUEST_GET_MAX_LUN: + (*data)[0] = g_usbd_msc[busid].max_lun; + *len = 1; + break; + + default: + return -1; + } + + return 0; +} + +void msc_storage_notify_handler(uint8_t busid, uint8_t event, void *arg) +{ + (void)arg; + + switch (event) { + case USBD_EVENT_INIT: +#if defined(CONFIG_USBDEV_MSC_THREAD) + g_usbd_msc[busid].usbd_msc_mq = usb_osal_mq_create(1); + if (g_usbd_msc[busid].usbd_msc_mq == NULL) { + USB_LOG_ERR("No memory to alloc for g_usbd_msc[busid].usbd_msc_mq\r\n"); + } + g_usbd_msc[busid].usbd_msc_thread = usb_osal_thread_create("usbd_msc", CONFIG_USBDEV_MSC_STACKSIZE, CONFIG_USBDEV_MSC_PRIO, usbdev_msc_thread, (void *)(uint32_t)busid); + if (g_usbd_msc[busid].usbd_msc_thread == NULL) { + USB_LOG_ERR("No memory to alloc for g_usbd_msc[busid].usbd_msc_thread\r\n"); + } +#elif defined(CONFIG_USBDEV_MSC_POLLING) + g_usbd_msc[busid].event = 0; +#endif + break; + case USBD_EVENT_DEINIT: +#if defined(CONFIG_USBDEV_MSC_THREAD) + if (g_usbd_msc[busid].usbd_msc_mq) { + usb_osal_mq_delete(g_usbd_msc[busid].usbd_msc_mq); + } + if (g_usbd_msc[busid].usbd_msc_thread) { + usb_osal_thread_delete(g_usbd_msc[busid].usbd_msc_thread); + } +#endif + break; + case USBD_EVENT_RESET: + usbd_msc_reset(busid); + break; + case USBD_EVENT_CONFIGURED: + USB_LOG_DBG("Start reading cbw\r\n"); + usbd_ep_start_read(busid, mass_ep_data[busid][MSD_OUT_EP_IDX].ep_addr, (uint8_t *)&g_usbd_msc[busid].cbw, USB_SIZEOF_MSC_CBW); + break; + + default: + break; + } +} + +static void usbd_msc_bot_abort(uint8_t busid) +{ + if ((g_usbd_msc[busid].cbw.bmFlags == 0) && (g_usbd_msc[busid].cbw.dDataLength != 0)) { + usbd_ep_set_stall(busid, mass_ep_data[busid][MSD_OUT_EP_IDX].ep_addr); + } + usbd_ep_set_stall(busid, mass_ep_data[busid][MSD_IN_EP_IDX].ep_addr); + usbd_ep_start_read(busid, mass_ep_data[busid][0].ep_addr, (uint8_t *)&g_usbd_msc[busid].cbw, USB_SIZEOF_MSC_CBW); +} + +static void usbd_msc_send_csw(uint8_t busid, uint8_t CSW_Status) +{ + g_usbd_msc[busid].csw.dSignature = MSC_CSW_Signature; + g_usbd_msc[busid].csw.bStatus = CSW_Status; + + /* updating the State Machine , so that we wait CSW when this + * transfer is complete, ie when we get a bulk in callback + */ + g_usbd_msc[busid].stage = MSC_WAIT_CSW; + + USB_LOG_DBG("Send csw\r\n"); + usbd_ep_start_write(busid, mass_ep_data[busid][MSD_IN_EP_IDX].ep_addr, (uint8_t *)&g_usbd_msc[busid].csw, sizeof(struct CSW)); +} + +static void usbd_msc_send_info(uint8_t busid, uint8_t *buffer, uint8_t size) +{ + size = MIN(size, g_usbd_msc[busid].cbw.dDataLength); + + /* updating the State Machine , so that we send CSW when this + * transfer is complete, ie when we get a bulk in callback + */ + g_usbd_msc[busid].stage = MSC_SEND_CSW; + + usbd_ep_start_write(busid, mass_ep_data[busid][MSD_IN_EP_IDX].ep_addr, buffer, size); + + g_usbd_msc[busid].csw.dDataResidue -= size; + g_usbd_msc[busid].csw.bStatus = CSW_STATUS_CMD_PASSED; +} + +static bool SCSI_processWrite(uint8_t busid, uint32_t nbytes); +static bool SCSI_processRead(uint8_t busid); + +/** +* @brief SCSI_SetSenseData +* Load the last error code in the error list +* @param sKey: Sense Key +* @param ASC: Additional Sense Code +* @retval none + +*/ +static void SCSI_SetSenseData(uint8_t busid, uint32_t KCQ) +{ + g_usbd_msc[busid].sKey = (uint8_t)(KCQ >> 16); + g_usbd_msc[busid].ASC = (uint8_t)(KCQ >> 8); + g_usbd_msc[busid].ASQ = (uint8_t)(KCQ); +} + +/** + * @brief SCSI Command list + * + */ + +static bool SCSI_testUnitReady(uint8_t busid, uint8_t **data, uint32_t *len) +{ + if (g_usbd_msc[busid].cbw.dDataLength != 0U) { + SCSI_SetSenseData(busid, SCSI_KCQIR_INVALIDCOMMAND); + return false; + } + *data = NULL; + *len = 0; + return true; +} + +static bool SCSI_requestSense(uint8_t busid, uint8_t **data, uint32_t *len) +{ + uint8_t data_len = SCSIRESP_FIXEDSENSEDATA_SIZEOF; + if (g_usbd_msc[busid].cbw.dDataLength == 0U) { + SCSI_SetSenseData(busid, SCSI_KCQIR_INVALIDCOMMAND); + return false; + } + + if (g_usbd_msc[busid].cbw.CB[4] < SCSIRESP_FIXEDSENSEDATA_SIZEOF) { + data_len = g_usbd_msc[busid].cbw.CB[4]; + } + + uint8_t request_sense[SCSIRESP_FIXEDSENSEDATA_SIZEOF] = { + 0x70, + 0x00, + 0x00, /* Sense Key */ + 0x00, + 0x00, + 0x00, + 0x00, + SCSIRESP_FIXEDSENSEDATA_SIZEOF - 8, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, /* Additional Sense Code */ + 0x00, /* Additional Sense Request */ + 0x00, + 0x00, + 0x00, + 0x00, + }; + + request_sense[2] = g_usbd_msc[busid].sKey; + request_sense[12] = g_usbd_msc[busid].ASC; + request_sense[13] = g_usbd_msc[busid].ASQ; +#if 0 + request_sense[ 2] = 0x06; /* UNIT ATTENTION */ + request_sense[12] = 0x28; /* Additional Sense Code: Not ready to ready transition */ + request_sense[13] = 0x00; /* Additional Sense Code Qualifier */ +#endif +#if 0 + request_sense[ 2] = 0x02; /* NOT READY */ + request_sense[12] = 0x3A; /* Additional Sense Code: Medium not present */ + request_sense[13] = 0x00; /* Additional Sense Code Qualifier */ +#endif +#if 0 + request_sense[ 2] = 0x05; /* ILLEGAL REQUEST */ + request_sense[12] = 0x20; /* Additional Sense Code: Invalid command */ + request_sense[13] = 0x00; /* Additional Sense Code Qualifier */ +#endif +#if 0 + request_sense[ 2] = 0x00; /* NO SENSE */ + request_sense[12] = 0x00; /* Additional Sense Code: No additional code */ + request_sense[13] = 0x00; /* Additional Sense Code Qualifier */ +#endif + + memcpy(*data, (uint8_t *)request_sense, data_len); + *len = data_len; + return true; +} + +static bool SCSI_inquiry(uint8_t busid, uint8_t **data, uint32_t *len) +{ + uint8_t data_len = SCSIRESP_INQUIRY_SIZEOF; + + uint8_t inquiry00[6] = { + 0x00, + 0x00, + 0x00, + (0x06 - 4U), + 0x00, + 0x80 + }; + + /* USB Mass storage VPD Page 0x80 Inquiry Data for Unit Serial Number */ + uint8_t inquiry80[8] = { + 0x00, + 0x80, + 0x00, + (0x08 - 4U), + 0x20, /* Put Product Serial number */ + 0x20, + 0x20, + 0x20 + }; + + uint8_t inquiry[SCSIRESP_INQUIRY_SIZEOF] = { + /* 36 */ + + /* LUN 0 */ + 0x00, + 0x80, + 0x02, + 0x02, + (SCSIRESP_INQUIRY_SIZEOF - 5), + 0x00, + 0x00, + 0x00, + ' ', ' ', ' ', ' ', ' ', ' ', ' ', ' ', /* Manufacturer : 8 bytes */ + ' ', ' ', ' ', ' ', ' ', ' ', ' ', ' ', /* Product : 16 Bytes */ + ' ', ' ', ' ', ' ', ' ', ' ', ' ', ' ', + ' ', ' ', ' ', ' ' /* Version : 4 Bytes */ + }; + + memcpy(&inquiry[8], CONFIG_USBDEV_MSC_MANUFACTURER_STRING, strlen(CONFIG_USBDEV_MSC_MANUFACTURER_STRING)); + memcpy(&inquiry[16], CONFIG_USBDEV_MSC_PRODUCT_STRING, strlen(CONFIG_USBDEV_MSC_PRODUCT_STRING)); + memcpy(&inquiry[32], CONFIG_USBDEV_MSC_VERSION_STRING, strlen(CONFIG_USBDEV_MSC_VERSION_STRING)); + + if (g_usbd_msc[busid].cbw.dDataLength == 0U) { + SCSI_SetSenseData(busid, SCSI_KCQIR_INVALIDCOMMAND); + return false; + } + + if ((g_usbd_msc[busid].cbw.CB[1] & 0x01U) != 0U) { /* Evpd is set */ + if (g_usbd_msc[busid].cbw.CB[2] == 0U) { /* Request for Supported Vital Product Data Pages*/ + data_len = 0x06; + memcpy(*data, (uint8_t *)inquiry00, data_len); + } else if (g_usbd_msc[busid].cbw.CB[2] == 0x80U) { /* Request for VPD page 0x80 Unit Serial Number */ + data_len = 0x08; + memcpy(*data, (uint8_t *)inquiry80, data_len); + } else { /* Request Not supported */ + SCSI_SetSenseData(busid, SCSI_KCQIR_INVALIDFIELDINCBA); + return false; + } + } else { + if (g_usbd_msc[busid].cbw.CB[4] < SCSIRESP_INQUIRY_SIZEOF) { + data_len = g_usbd_msc[busid].cbw.CB[4]; + } + memcpy(*data, (uint8_t *)inquiry, data_len); + } + + *len = data_len; + return true; +} + +static bool SCSI_startStopUnit(uint8_t busid, uint8_t **data, uint32_t *len) +{ + if (g_usbd_msc[busid].cbw.dDataLength != 0U) { + SCSI_SetSenseData(busid, SCSI_KCQIR_INVALIDCOMMAND); + return false; + } + + if ((g_usbd_msc[busid].cbw.CB[4] & 0x3U) == 0x1U) /* START=1 */ + { + //SCSI_MEDIUM_UNLOCKED; + } else if ((g_usbd_msc[busid].cbw.CB[4] & 0x3U) == 0x2U) /* START=0 and LOEJ Load Eject=1 */ + { + //SCSI_MEDIUM_EJECTED; + g_usbd_msc[busid].popup = true; + } else if ((g_usbd_msc[busid].cbw.CB[4] & 0x3U) == 0x3U) /* START=1 and LOEJ Load Eject=1 */ + { + //SCSI_MEDIUM_UNLOCKED; + } else { + } + + *data = NULL; + *len = 0; + return true; +} + +static bool SCSI_preventAllowMediaRemoval(uint8_t busid, uint8_t **data, uint32_t *len) +{ + if (g_usbd_msc[busid].cbw.dDataLength != 0U) { + SCSI_SetSenseData(busid, SCSI_KCQIR_INVALIDCOMMAND); + return false; + } + if (g_usbd_msc[busid].cbw.CB[4] == 0U) { + //SCSI_MEDIUM_UNLOCKED; + } else { + //SCSI_MEDIUM_LOCKED; + } + *data = NULL; + *len = 0; + return true; +} + +static bool SCSI_modeSense6(uint8_t busid, uint8_t **data, uint32_t *len) +{ + uint8_t data_len = 4; + if (g_usbd_msc[busid].cbw.dDataLength == 0U) { + SCSI_SetSenseData(busid, SCSI_KCQIR_INVALIDCOMMAND); + return false; + } + if (g_usbd_msc[busid].cbw.CB[4] < SCSIRESP_MODEPARAMETERHDR6_SIZEOF) { + data_len = g_usbd_msc[busid].cbw.CB[4]; + } + + uint8_t sense6[SCSIRESP_MODEPARAMETERHDR6_SIZEOF] = { 0x03, 0x00, 0x00, 0x00 }; + + if (g_usbd_msc[busid].readonly) { + sense6[2] = 0x80; + } + memcpy(*data, (uint8_t *)sense6, data_len); + *len = data_len; + return true; +} + +static bool SCSI_modeSense10(uint8_t busid, uint8_t **data, uint32_t *len) +{ + uint8_t data_len = 27; + if (g_usbd_msc[busid].cbw.dDataLength == 0U) { + SCSI_SetSenseData(busid, SCSI_KCQIR_INVALIDCOMMAND); + return false; + } + + if (g_usbd_msc[busid].cbw.CB[8] < 27) { + data_len = g_usbd_msc[busid].cbw.CB[8]; + } + + uint8_t sense10[27] = { + 0x00, + 0x26, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x08, + 0x12, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00 + }; + + memcpy(*data, (uint8_t *)sense10, data_len); + *len = data_len; + return true; +} + +static bool SCSI_readFormatCapacity(uint8_t busid, uint8_t **data, uint32_t *len) +{ + if (g_usbd_msc[busid].cbw.dDataLength == 0U) { + SCSI_SetSenseData(busid, SCSI_KCQIR_INVALIDCOMMAND); + return false; + } + uint8_t format_capacity[SCSIRESP_READFORMATCAPACITIES_SIZEOF] = { + 0x00, + 0x00, + 0x00, + 0x08, /* Capacity List Length */ + (uint8_t)((g_usbd_msc[busid].scsi_blk_nbr[g_usbd_msc[busid].cbw.bLUN] >> 24) & 0xff), + (uint8_t)((g_usbd_msc[busid].scsi_blk_nbr[g_usbd_msc[busid].cbw.bLUN] >> 16) & 0xff), + (uint8_t)((g_usbd_msc[busid].scsi_blk_nbr[g_usbd_msc[busid].cbw.bLUN] >> 8) & 0xff), + (uint8_t)((g_usbd_msc[busid].scsi_blk_nbr[g_usbd_msc[busid].cbw.bLUN] >> 0) & 0xff), + + 0x02, /* Descriptor Code: Formatted Media */ + 0x00, + (uint8_t)((g_usbd_msc[busid].scsi_blk_size[g_usbd_msc[busid].cbw.bLUN] >> 8) & 0xff), + (uint8_t)((g_usbd_msc[busid].scsi_blk_size[g_usbd_msc[busid].cbw.bLUN] >> 0) & 0xff), + }; + + memcpy(*data, (uint8_t *)format_capacity, SCSIRESP_READFORMATCAPACITIES_SIZEOF); + *len = SCSIRESP_READFORMATCAPACITIES_SIZEOF; + return true; +} + +static bool SCSI_readCapacity10(uint8_t busid, uint8_t **data, uint32_t *len) +{ + if (g_usbd_msc[busid].cbw.dDataLength == 0U) { + SCSI_SetSenseData(busid, SCSI_KCQIR_INVALIDCOMMAND); + return false; + } + + uint8_t capacity10[SCSIRESP_READCAPACITY10_SIZEOF] = { + (uint8_t)(((g_usbd_msc[busid].scsi_blk_nbr[g_usbd_msc[busid].cbw.bLUN] - 1) >> 24) & 0xff), + (uint8_t)(((g_usbd_msc[busid].scsi_blk_nbr[g_usbd_msc[busid].cbw.bLUN] - 1) >> 16) & 0xff), + (uint8_t)(((g_usbd_msc[busid].scsi_blk_nbr[g_usbd_msc[busid].cbw.bLUN] - 1) >> 8) & 0xff), + (uint8_t)(((g_usbd_msc[busid].scsi_blk_nbr[g_usbd_msc[busid].cbw.bLUN] - 1) >> 0) & 0xff), + + (uint8_t)((g_usbd_msc[busid].scsi_blk_size[g_usbd_msc[busid].cbw.bLUN] >> 24) & 0xff), + (uint8_t)((g_usbd_msc[busid].scsi_blk_size[g_usbd_msc[busid].cbw.bLUN] >> 16) & 0xff), + (uint8_t)((g_usbd_msc[busid].scsi_blk_size[g_usbd_msc[busid].cbw.bLUN] >> 8) & 0xff), + (uint8_t)((g_usbd_msc[busid].scsi_blk_size[g_usbd_msc[busid].cbw.bLUN] >> 0) & 0xff), + }; + + memcpy(*data, (uint8_t *)capacity10, SCSIRESP_READCAPACITY10_SIZEOF); + *len = SCSIRESP_READCAPACITY10_SIZEOF; + return true; +} + +static bool SCSI_read10(uint8_t busid, uint8_t **data, uint32_t *len) +{ + (void)data; + (void)len; + + if (((g_usbd_msc[busid].cbw.bmFlags & 0x80U) != 0x80U) || (g_usbd_msc[busid].cbw.dDataLength == 0U)) { + SCSI_SetSenseData(busid, SCSI_KCQIR_INVALIDCOMMAND); + return false; + } + + g_usbd_msc[busid].start_sector = GET_BE32(&g_usbd_msc[busid].cbw.CB[2]); /* Logical Block Address of First Block */ + g_usbd_msc[busid].nsectors = GET_BE16(&g_usbd_msc[busid].cbw.CB[7]); /* Number of Blocks to transfer */ + + if ((g_usbd_msc[busid].start_sector + g_usbd_msc[busid].nsectors) > g_usbd_msc[busid].scsi_blk_nbr[g_usbd_msc[busid].cbw.bLUN]) { + SCSI_SetSenseData(busid, SCSI_KCQIR_LBAOUTOFRANGE); + return false; + } + + if (g_usbd_msc[busid].cbw.dDataLength != (g_usbd_msc[busid].nsectors * g_usbd_msc[busid].scsi_blk_size[g_usbd_msc[busid].cbw.bLUN])) { + return false; + } + g_usbd_msc[busid].stage = MSC_DATA_IN; +#if defined(CONFIG_USBDEV_MSC_THREAD) + usb_osal_mq_send(g_usbd_msc[busid].usbd_msc_mq, MSC_DATA_IN); + return true; +#elif defined(CONFIG_USBDEV_MSC_POLLING) + g_usbd_msc[busid].event = MSC_DATA_IN; + return true; +#else + return SCSI_processRead(busid); +#endif +} + +static bool SCSI_read12(uint8_t busid, uint8_t **data, uint32_t *len) +{ + (void)data; + (void)len; + + if (((g_usbd_msc[busid].cbw.bmFlags & 0x80U) != 0x80U) || (g_usbd_msc[busid].cbw.dDataLength == 0U)) { + SCSI_SetSenseData(busid, SCSI_KCQIR_INVALIDCOMMAND); + return false; + } + + g_usbd_msc[busid].start_sector = GET_BE32(&g_usbd_msc[busid].cbw.CB[2]); /* Logical Block Address of First Block */ + g_usbd_msc[busid].nsectors = GET_BE32(&g_usbd_msc[busid].cbw.CB[6]); /* Number of Blocks to transfer */ + + if ((g_usbd_msc[busid].start_sector + g_usbd_msc[busid].nsectors) > g_usbd_msc[busid].scsi_blk_nbr[g_usbd_msc[busid].cbw.bLUN]) { + SCSI_SetSenseData(busid, SCSI_KCQIR_LBAOUTOFRANGE); + return false; + } + + if (g_usbd_msc[busid].cbw.dDataLength != (g_usbd_msc[busid].nsectors * g_usbd_msc[busid].scsi_blk_size[g_usbd_msc[busid].cbw.bLUN])) { + return false; + } + g_usbd_msc[busid].stage = MSC_DATA_IN; +#if defined(CONFIG_USBDEV_MSC_THREAD) + usb_osal_mq_send(g_usbd_msc[busid].usbd_msc_mq, MSC_DATA_IN); + return true; +#elif defined(CONFIG_USBDEV_MSC_POLLING) + g_usbd_msc[busid].event = MSC_DATA_IN; + return true; +#else + return SCSI_processRead(busid); +#endif +} + +static bool SCSI_write10(uint8_t busid, uint8_t **data, uint32_t *len) +{ + uint32_t data_len = 0; + + (void)data; + (void)len; + + if (((g_usbd_msc[busid].cbw.bmFlags & 0x80U) != 0x00U) || (g_usbd_msc[busid].cbw.dDataLength == 0U)) { + SCSI_SetSenseData(busid, SCSI_KCQIR_INVALIDCOMMAND); + return false; + } + + g_usbd_msc[busid].start_sector = GET_BE32(&g_usbd_msc[busid].cbw.CB[2]); /* Logical Block Address of First Block */ + g_usbd_msc[busid].nsectors = GET_BE16(&g_usbd_msc[busid].cbw.CB[7]); /* Number of Blocks to transfer */ + + data_len = g_usbd_msc[busid].nsectors * g_usbd_msc[busid].scsi_blk_size[g_usbd_msc[busid].cbw.bLUN]; + if ((g_usbd_msc[busid].start_sector + g_usbd_msc[busid].nsectors) > g_usbd_msc[busid].scsi_blk_nbr[g_usbd_msc[busid].cbw.bLUN]) { + return false; + } + + if (g_usbd_msc[busid].cbw.dDataLength != data_len) { + return false; + } + g_usbd_msc[busid].stage = MSC_DATA_OUT; + data_len = MIN(data_len, CONFIG_USBDEV_MSC_MAX_BUFSIZE); + usbd_ep_start_read(busid, mass_ep_data[busid][MSD_OUT_EP_IDX].ep_addr, g_usbd_msc[busid].block_buffer, data_len); + return true; +} + +static bool SCSI_write12(uint8_t busid, uint8_t **data, uint32_t *len) +{ + uint32_t data_len = 0; + + (void)data; + (void)len; + + if (((g_usbd_msc[busid].cbw.bmFlags & 0x80U) != 0x00U) || (g_usbd_msc[busid].cbw.dDataLength == 0U)) { + SCSI_SetSenseData(busid, SCSI_KCQIR_INVALIDCOMMAND); + return false; + } + + g_usbd_msc[busid].start_sector = GET_BE32(&g_usbd_msc[busid].cbw.CB[2]); /* Logical Block Address of First Block */ + g_usbd_msc[busid].nsectors = GET_BE32(&g_usbd_msc[busid].cbw.CB[6]); /* Number of Blocks to transfer */ + + data_len = g_usbd_msc[busid].nsectors * g_usbd_msc[busid].scsi_blk_size[g_usbd_msc[busid].cbw.bLUN]; + if ((g_usbd_msc[busid].start_sector + g_usbd_msc[busid].nsectors) > g_usbd_msc[busid].scsi_blk_nbr[g_usbd_msc[busid].cbw.bLUN]) { + return false; + } + + if (g_usbd_msc[busid].cbw.dDataLength != data_len) { + return false; + } + g_usbd_msc[busid].stage = MSC_DATA_OUT; + data_len = MIN(data_len, CONFIG_USBDEV_MSC_MAX_BUFSIZE); + usbd_ep_start_read(busid, mass_ep_data[busid][MSD_OUT_EP_IDX].ep_addr, g_usbd_msc[busid].block_buffer, data_len); + return true; +} + +static bool SCSI_processRead(uint8_t busid) +{ + uint32_t transfer_len; + + USB_LOG_DBG("read lba:%d\r\n", g_usbd_msc[busid].start_sector); + + transfer_len = MIN(g_usbd_msc[busid].nsectors * g_usbd_msc[busid].scsi_blk_size[g_usbd_msc[busid].cbw.bLUN], CONFIG_USBDEV_MSC_MAX_BUFSIZE); + + if (usbd_msc_sector_read(busid, g_usbd_msc[busid].cbw.bLUN, g_usbd_msc[busid].start_sector, g_usbd_msc[busid].block_buffer, transfer_len) != 0) { + SCSI_SetSenseData(busid, SCSI_KCQHE_UREINRESERVEDAREA); + return false; + } + + g_usbd_msc[busid].start_sector += (transfer_len / g_usbd_msc[busid].scsi_blk_size[g_usbd_msc[busid].cbw.bLUN]); + g_usbd_msc[busid].nsectors -= (transfer_len / g_usbd_msc[busid].scsi_blk_size[g_usbd_msc[busid].cbw.bLUN]); + g_usbd_msc[busid].csw.dDataResidue -= transfer_len; + + if (g_usbd_msc[busid].nsectors == 0) { + g_usbd_msc[busid].stage = MSC_SEND_CSW; + } + + usbd_ep_start_write(busid, mass_ep_data[busid][MSD_IN_EP_IDX].ep_addr, g_usbd_msc[busid].block_buffer, transfer_len); + + return true; +} + +static bool SCSI_processWrite(uint8_t busid, uint32_t nbytes) +{ + uint32_t data_len = 0; + + USB_LOG_DBG("write lba:%d\r\n", g_usbd_msc[busid].start_sector); + + if (usbd_msc_sector_write(busid, g_usbd_msc[busid].cbw.bLUN, g_usbd_msc[busid].start_sector, g_usbd_msc[busid].block_buffer, nbytes) != 0) { + SCSI_SetSenseData(busid, SCSI_KCQHE_WRITEFAULT); + return false; + } + + g_usbd_msc[busid].start_sector += (nbytes / g_usbd_msc[busid].scsi_blk_size[g_usbd_msc[busid].cbw.bLUN]); + g_usbd_msc[busid].nsectors -= (nbytes / g_usbd_msc[busid].scsi_blk_size[g_usbd_msc[busid].cbw.bLUN]); + g_usbd_msc[busid].csw.dDataResidue -= nbytes; + + if (g_usbd_msc[busid].nsectors == 0) { + usbd_msc_send_csw(busid, CSW_STATUS_CMD_PASSED); + } else { + data_len = MIN(g_usbd_msc[busid].nsectors * g_usbd_msc[busid].scsi_blk_size[g_usbd_msc[busid].cbw.bLUN], CONFIG_USBDEV_MSC_MAX_BUFSIZE); + usbd_ep_start_read(busid, mass_ep_data[busid][MSD_OUT_EP_IDX].ep_addr, g_usbd_msc[busid].block_buffer, data_len); + } + + return true; +} + +static bool SCSI_CBWDecode(uint8_t busid, uint32_t nbytes) +{ + uint8_t *buf2send = g_usbd_msc[busid].block_buffer; + uint32_t len2send = 0; + bool ret = false; + + if (nbytes != sizeof(struct CBW)) { + USB_LOG_ERR("size != sizeof(cbw)\r\n"); + SCSI_SetSenseData(busid, SCSI_KCQIR_INVALIDCOMMAND); + return false; + } + + g_usbd_msc[busid].csw.dTag = g_usbd_msc[busid].cbw.dTag; + g_usbd_msc[busid].csw.dDataResidue = g_usbd_msc[busid].cbw.dDataLength; + + if ((g_usbd_msc[busid].cbw.dSignature != MSC_CBW_Signature) || (g_usbd_msc[busid].cbw.bCBLength < 1) || (g_usbd_msc[busid].cbw.bCBLength > 16)) { + SCSI_SetSenseData(busid, SCSI_KCQIR_INVALIDCOMMAND); + return false; + } else { + USB_LOG_DBG("Decode CB:0x%02x\r\n", g_usbd_msc[busid].cbw.CB[0]); + switch (g_usbd_msc[busid].cbw.CB[0]) { + case SCSI_CMD_TESTUNITREADY: + ret = SCSI_testUnitReady(busid, &buf2send, &len2send); + break; + case SCSI_CMD_REQUESTSENSE: + ret = SCSI_requestSense(busid, &buf2send, &len2send); + break; + case SCSI_CMD_INQUIRY: + ret = SCSI_inquiry(busid, &buf2send, &len2send); + break; + case SCSI_CMD_STARTSTOPUNIT: + ret = SCSI_startStopUnit(busid, &buf2send, &len2send); + break; + case SCSI_CMD_PREVENTMEDIAREMOVAL: + ret = SCSI_preventAllowMediaRemoval(busid, &buf2send, &len2send); + break; + case SCSI_CMD_MODESENSE6: + ret = SCSI_modeSense6(busid, &buf2send, &len2send); + break; + case SCSI_CMD_MODESENSE10: + ret = SCSI_modeSense10(busid, &buf2send, &len2send); + break; + case SCSI_CMD_READFORMATCAPACITIES: + ret = SCSI_readFormatCapacity(busid, &buf2send, &len2send); + break; + case SCSI_CMD_READCAPACITY10: + ret = SCSI_readCapacity10(busid, &buf2send, &len2send); + break; + case SCSI_CMD_READ10: + ret = SCSI_read10(busid, NULL, 0); + break; + case SCSI_CMD_READ12: + ret = SCSI_read12(busid, NULL, 0); + break; + case SCSI_CMD_WRITE10: + ret = SCSI_write10(busid, NULL, 0); + break; + case SCSI_CMD_WRITE12: + ret = SCSI_write12(busid, NULL, 0); + break; + case SCSI_CMD_VERIFY10: + ret = false; + break; + case SCSI_CMD_SYNCHCACHE10: + ret = true; + break; + default: + SCSI_SetSenseData(busid, SCSI_KCQIR_INVALIDCOMMAND); + ret = false; + break; + } + } + if (ret) { + if (g_usbd_msc[busid].stage == MSC_READ_CBW) { + if (len2send) { + USB_LOG_DBG("Send info len: %d\r\n", len2send); + usbd_msc_send_info(busid, buf2send, len2send); + } else { + usbd_msc_send_csw(busid, CSW_STATUS_CMD_PASSED); + } + } + } + return ret; +} + +void mass_storage_bulk_out(uint8_t busid, uint8_t ep, uint32_t nbytes) +{ + (void)ep; + + switch (g_usbd_msc[busid].stage) { + case MSC_READ_CBW: + if (SCSI_CBWDecode(busid, nbytes) == false) { + USB_LOG_ERR("Command: 0x%02x decode err\r\n", g_usbd_msc[busid].cbw.CB[0]); + usbd_msc_bot_abort(busid); + return; + } + break; + case MSC_DATA_OUT: + switch (g_usbd_msc[busid].cbw.CB[0]) { + case SCSI_CMD_WRITE10: + case SCSI_CMD_WRITE12: +#if defined(CONFIG_USBDEV_MSC_THREAD) + g_usbd_msc[busid].nbytes = nbytes; + usb_osal_mq_send(g_usbd_msc[busid].usbd_msc_mq, MSC_DATA_OUT); +#elif defined(CONFIG_USBDEV_MSC_POLLING) + g_usbd_msc[busid].nbytes = nbytes; + g_usbd_msc[busid].event = MSC_DATA_OUT; +#else + if (SCSI_processWrite(busid, nbytes) == false) { + usbd_msc_send_csw(busid, CSW_STATUS_CMD_FAILED); /* send fail status to host,and the host will retry*/ + } +#endif + break; + default: + break; + } + break; + default: + break; + } +} + +void mass_storage_bulk_in(uint8_t busid, uint8_t ep, uint32_t nbytes) +{ + (void)ep; + (void)nbytes; + + switch (g_usbd_msc[busid].stage) { + case MSC_DATA_IN: + switch (g_usbd_msc[busid].cbw.CB[0]) { + case SCSI_CMD_READ10: + case SCSI_CMD_READ12: +#if defined(CONFIG_USBDEV_MSC_THREAD) + usb_osal_mq_send(g_usbd_msc[busid].usbd_msc_mq, MSC_DATA_IN); +#elif defined(CONFIG_USBDEV_MSC_POLLING) + g_usbd_msc[busid].event = MSC_DATA_IN; +#else + if (SCSI_processRead(busid) == false) { + usbd_msc_send_csw(busid, CSW_STATUS_CMD_FAILED); /* send fail status to host,and the host will retry*/ + return; + } +#endif + break; + default: + break; + } + break; + /*the device has to send a CSW*/ + case MSC_SEND_CSW: + usbd_msc_send_csw(busid, CSW_STATUS_CMD_PASSED); + break; + + /*the host has received the CSW*/ + case MSC_WAIT_CSW: + g_usbd_msc[busid].stage = MSC_READ_CBW; + USB_LOG_DBG("Start reading cbw\r\n"); + usbd_ep_start_read(busid, mass_ep_data[busid][MSD_OUT_EP_IDX].ep_addr, (uint8_t *)&g_usbd_msc[busid].cbw, USB_SIZEOF_MSC_CBW); + break; + + default: + break; + } +} + +#if defined(CONFIG_USBDEV_MSC_THREAD) +static void usbdev_msc_thread(CONFIG_USB_OSAL_THREAD_SET_ARGV) +{ + uintptr_t event; + int ret; + uint8_t busid = (uint8_t)CONFIG_USB_OSAL_THREAD_GET_ARGV; + + while (1) { + ret = usb_osal_mq_recv(g_usbd_msc[busid].usbd_msc_mq, (uintptr_t *)&event, USB_OSAL_WAITING_FOREVER); + if (ret < 0) { + continue; + } + if (event == MSC_DATA_OUT) { + if (SCSI_processWrite(busid, g_usbd_msc[busid].nbytes) == false) { + usbd_msc_send_csw(busid, CSW_STATUS_CMD_FAILED); /* send fail status to host,and the host will retry*/ + } + } else if (event == MSC_DATA_IN) { + if (SCSI_processRead(busid) == false) { + usbd_msc_send_csw(busid, CSW_STATUS_CMD_FAILED); /* send fail status to host,and the host will retry*/ + } + } else { + } + } +} +#elif defined(CONFIG_USBDEV_MSC_POLLING) +void usbd_msc_polling(uint8_t busid) +{ + uint8_t event; + + event = g_usbd_msc[busid].event; + + if (event != 0) { + g_usbd_msc[busid].event = 0; + if (event == MSC_DATA_OUT) { + if (SCSI_processWrite(busid, g_usbd_msc[busid].nbytes) == false) { + usbd_msc_send_csw(busid, CSW_STATUS_CMD_FAILED); /* send fail status to host,and the host will retry*/ + } + } else if (event == MSC_DATA_IN) { + if (SCSI_processRead(busid) == false) { + usbd_msc_send_csw(busid, CSW_STATUS_CMD_FAILED); /* send fail status to host,and the host will retry*/ + } + } else { + } + } +} +#endif + +struct usbd_interface *usbd_msc_init_intf(uint8_t busid, struct usbd_interface *intf, const uint8_t out_ep, const uint8_t in_ep) +{ + intf->class_interface_handler = msc_storage_class_interface_request_handler; + intf->class_endpoint_handler = NULL; + intf->vendor_handler = NULL; + intf->notify_handler = msc_storage_notify_handler; + + mass_ep_data[busid][MSD_OUT_EP_IDX].ep_addr = out_ep; + mass_ep_data[busid][MSD_OUT_EP_IDX].ep_cb = mass_storage_bulk_out; + mass_ep_data[busid][MSD_IN_EP_IDX].ep_addr = in_ep; + mass_ep_data[busid][MSD_IN_EP_IDX].ep_cb = mass_storage_bulk_in; + + usbd_add_endpoint(busid, &mass_ep_data[busid][MSD_OUT_EP_IDX]); + usbd_add_endpoint(busid, &mass_ep_data[busid][MSD_IN_EP_IDX]); + + memset((uint8_t *)&g_usbd_msc[busid], 0, sizeof(struct usbd_msc_priv)); + + usdb_msc_set_max_lun(busid); + for (uint8_t i = 0u; i <= g_usbd_msc[busid].max_lun; i++) { + usbd_msc_get_cap(busid, i, &g_usbd_msc[busid].scsi_blk_nbr[i], &g_usbd_msc[busid].scsi_blk_size[i]); + + if (CONFIG_USBDEV_MSC_MAX_BUFSIZE % g_usbd_msc[busid].scsi_blk_size[i]) { + USB_LOG_ERR("CONFIG_USBDEV_MSC_MAX_BUFSIZE must be a multiple of block size\r\n"); + while (1) { + } + } + } + + return intf; +} + +void usbd_msc_set_readonly(uint8_t busid, bool readonly) +{ + g_usbd_msc[busid].readonly = readonly; +} + +bool usbd_msc_get_popup(uint8_t busid) +{ + return g_usbd_msc[busid].popup; +} + +__WEAK void usbd_msc_get_cap(uint8_t busid, uint8_t lun, uint32_t *block_num, uint32_t *block_size) +{ + (void)busid; + (void)lun; + + *block_num = 0; + *block_size = 0; +} + +__WEAK int usbd_msc_sector_read(uint8_t busid, uint8_t lun, uint32_t sector, uint8_t *buffer, uint32_t length) +{ + (void)busid; + (void)lun; + (void)sector; + (void)buffer; + (void)length; + + return 0; +} + +__WEAK int usbd_msc_sector_write(uint8_t busid, uint8_t lun, uint32_t sector, uint8_t *buffer, uint32_t length) +{ + (void)busid; + (void)lun; + (void)sector; + (void)buffer; + (void)length; + + return 0; +} \ No newline at end of file diff --git a/kernel/cherryusb/class/msc/usbd_msc.h b/kernel/cherryusb/class/msc/usbd_msc.h new file mode 100644 index 0000000..63a8752 --- /dev/null +++ b/kernel/cherryusb/class/msc/usbd_msc.h @@ -0,0 +1,34 @@ +/* + * Copyright (c) 2022, sakumisu + * Copyright (c) 2024, zhihong chen + * + * SPDX-License-Identifier: Apache-2.0 + */ +#ifndef USBD_MSC_H +#define USBD_MSC_H + +#include "usb_msc.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* Init msc interface driver */ +struct usbd_interface *usbd_msc_init_intf(uint8_t busid, struct usbd_interface *intf, + const uint8_t out_ep, + const uint8_t in_ep); + +void usbd_msc_get_cap(uint8_t busid, uint8_t lun, uint32_t *block_num, uint32_t *block_size); +int usbd_msc_sector_read(uint8_t busid, uint8_t lun, uint32_t sector, uint8_t *buffer, uint32_t length); +int usbd_msc_sector_write(uint8_t busid, uint8_t lun, uint32_t sector, uint8_t *buffer, uint32_t length); + +void usbd_msc_set_readonly(uint8_t busid, bool readonly); +bool usbd_msc_get_popup(uint8_t busid); + +void usbd_msc_polling(uint8_t busid); + +#ifdef __cplusplus +} +#endif + +#endif /* USBD_MSC_H */ diff --git a/kernel/cherryusb/class/msc/usbh_msc.c b/kernel/cherryusb/class/msc/usbh_msc.c new file mode 100644 index 0000000..12a4f67 --- /dev/null +++ b/kernel/cherryusb/class/msc/usbh_msc.c @@ -0,0 +1,468 @@ +/* + * Copyright (c) 2022, sakumisu + * + * SPDX-License-Identifier: Apache-2.0 + */ +#include "usbh_core.h" +#include "usbh_msc.h" +#include "usb_scsi.h" + +#undef USB_DBG_TAG +#define USB_DBG_TAG "usbh_msc" +#include "usb_log.h" + +#define DEV_FORMAT "/dev/sd%c" + +#ifndef CONFIG_USBHOST_MSC_READY_CHECK_TIMES +#define CONFIG_USBHOST_MSC_READY_CHECK_TIMES 10 +#endif + +USB_NOCACHE_RAM_SECTION USB_MEM_ALIGNX uint8_t g_msc_cbw_csw[CONFIG_USBHOST_MAX_MSC_CLASS][USB_ALIGN_UP(64, CONFIG_USB_ALIGN_SIZE)]; +USB_NOCACHE_RAM_SECTION USB_MEM_ALIGNX uint8_t g_msc_buf[CONFIG_USBHOST_MAX_MSC_CLASS][USB_ALIGN_UP(64, CONFIG_USB_ALIGN_SIZE)]; + +static struct usbh_msc g_msc_class[CONFIG_USBHOST_MAX_MSC_CLASS]; +static uint32_t g_devinuse = 0; +static struct usbh_msc_modeswitch_config *g_msc_modeswitch_config = NULL; + +static struct usbh_msc *usbh_msc_class_alloc(void) +{ + uint8_t devno; + + for (devno = 0; devno < CONFIG_USBHOST_MAX_MSC_CLASS; devno++) { + if ((g_devinuse & (1U << devno)) == 0) { + g_devinuse |= (1U << devno); + memset(&g_msc_class[devno], 0, sizeof(struct usbh_msc)); + g_msc_class[devno].sdchar = 'a' + devno; + return &g_msc_class[devno]; + } + } + return NULL; +} + +static void usbh_msc_class_free(struct usbh_msc *msc_class) +{ + uint8_t devno = msc_class->sdchar - 'a'; + + if (devno < 32) { + g_devinuse &= ~(1U << devno); + } + memset(msc_class, 0, sizeof(struct usbh_msc)); +} + +static int usbh_msc_get_maxlun(struct usbh_msc *msc_class, uint8_t *buffer) +{ + struct usb_setup_packet *setup; + + if (!msc_class || !msc_class->hport) { + return -USB_ERR_INVAL; + } + setup = msc_class->hport->setup; + + setup->bmRequestType = USB_REQUEST_DIR_IN | USB_REQUEST_CLASS | USB_REQUEST_RECIPIENT_INTERFACE; + setup->bRequest = MSC_REQUEST_GET_MAX_LUN; + setup->wValue = 0; + setup->wIndex = msc_class->intf; + setup->wLength = 1; + + return usbh_control_transfer(msc_class->hport, setup, buffer); +} + +static void usbh_msc_cbw_dump(struct CBW *cbw) +{ + int i; + + USB_LOG_DBG("CBW:\r\n"); + USB_LOG_DBG(" signature: 0x%08x\r\n", (unsigned int)cbw->dSignature); + USB_LOG_DBG(" tag: 0x%08x\r\n", (unsigned int)cbw->dTag); + USB_LOG_DBG(" datlen: 0x%08x\r\n", (unsigned int)cbw->dDataLength); + USB_LOG_DBG(" flags: 0x%02x\r\n", cbw->bmFlags); + USB_LOG_DBG(" lun: 0x%02x\r\n", cbw->bLUN); + USB_LOG_DBG(" cblen: 0x%02x\r\n", cbw->bCBLength); + + USB_LOG_DBG("CB:\r\n"); + for (i = 0; i < cbw->bCBLength; i += 8) { + USB_LOG_DBG(" 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x\r\n", + cbw->CB[i], cbw->CB[i + 1], cbw->CB[i + 2], + cbw->CB[i + 3], cbw->CB[i + 4], cbw->CB[i + 5], + cbw->CB[i + 6], cbw->CB[i + 7]); + } +} + +static void usbh_msc_csw_dump(struct CSW *csw) +{ + (void)csw; + + USB_LOG_DBG("CSW:\r\n"); + USB_LOG_DBG(" signature: 0x%08x\r\n", (unsigned int)csw->dSignature); + USB_LOG_DBG(" tag: 0x%08x\r\n", (unsigned int)csw->dTag); + USB_LOG_DBG(" residue: 0x%08x\r\n", (unsigned int)csw->dDataResidue); + USB_LOG_DBG(" status: 0x%02x\r\n", csw->bStatus); +} + +static inline int usbh_msc_bulk_in_transfer(struct usbh_msc *msc_class, uint8_t *buffer, uint32_t buflen, uint32_t timeout) +{ + int ret; + struct usbh_urb *urb = &msc_class->bulkin_urb; + + usbh_bulk_urb_fill(urb, msc_class->hport, msc_class->bulkin, buffer, buflen, timeout, NULL, NULL); + ret = usbh_submit_urb(urb); + if (ret == 0) { + ret = urb->actual_length; + } + return ret; +} + +static inline int usbh_msc_bulk_out_transfer(struct usbh_msc *msc_class, uint8_t *buffer, uint32_t buflen, uint32_t timeout) +{ + int ret; + struct usbh_urb *urb = &msc_class->bulkout_urb; + + usbh_bulk_urb_fill(urb, msc_class->hport, msc_class->bulkout, buffer, buflen, timeout, NULL, NULL); + ret = usbh_submit_urb(urb); + if (ret == 0) { + ret = urb->actual_length; + } + return ret; +} + +static int usbh_bulk_cbw_csw_xfer(struct usbh_msc *msc_class, struct CBW *cbw, struct CSW *csw, uint8_t *buffer, uint32_t timeout) +{ + int nbytes; + + usbh_msc_cbw_dump(cbw); + + /* Send the CBW */ + nbytes = usbh_msc_bulk_out_transfer(msc_class, (uint8_t *)cbw, USB_SIZEOF_MSC_CBW, timeout); + if (nbytes < 0) { + USB_LOG_ERR("cbw transfer error: %d\r\n", nbytes); + goto __err_exit; + } + + if (cbw->dDataLength != 0) { + if (cbw->CB[0] == SCSI_CMD_WRITE10) { + nbytes = usbh_msc_bulk_out_transfer(msc_class, buffer, cbw->dDataLength, timeout); + } else if (cbw->CB[0] == SCSI_CMD_READCAPACITY10) { + nbytes = usbh_msc_bulk_in_transfer(msc_class, buffer, cbw->dDataLength, timeout); + if (nbytes >= 0) { + /* Save the capacity information */ + msc_class->blocknum = GET_BE32(&buffer[0]) + 1; + msc_class->blocksize = GET_BE32(&buffer[4]); + } + } else { + nbytes = usbh_msc_bulk_in_transfer(msc_class, buffer, cbw->dDataLength, timeout); + } + + if (nbytes < 0) { + USB_LOG_ERR("msc data transfer error: %d\r\n", nbytes); + goto __err_exit; + } + } + + /* Receive the CSW */ + memset(csw, 0, USB_SIZEOF_MSC_CSW); + nbytes = usbh_msc_bulk_in_transfer(msc_class, (uint8_t *)csw, USB_SIZEOF_MSC_CSW, timeout); + if (nbytes < 0) { + USB_LOG_ERR("csw transfer error: %d\r\n", nbytes); + goto __err_exit; + } + + usbh_msc_csw_dump(csw); + + /* check csw status */ + if (csw->dSignature != MSC_CSW_Signature) { + USB_LOG_ERR("csw signature error\r\n"); + return -USB_ERR_INVAL; + } + + if (csw->bStatus != 0) { + USB_LOG_ERR("csw bStatus %d\r\n", csw->bStatus); + return -USB_ERR_INVAL; + } +__err_exit: + return nbytes < 0 ? (int)nbytes : 0; +} + +static inline int usbh_msc_scsi_testunitready(struct usbh_msc *msc_class) +{ + struct CBW *cbw; + + /* Construct the CBW */ + cbw = (struct CBW *)g_msc_cbw_csw[msc_class->sdchar - 'a']; + memset(cbw, 0, USB_SIZEOF_MSC_CBW); + cbw->dSignature = MSC_CBW_Signature; + + cbw->bCBLength = SCSICMD_TESTUNITREADY_SIZEOF; + cbw->CB[0] = SCSI_CMD_TESTUNITREADY; + + return usbh_bulk_cbw_csw_xfer(msc_class, cbw, (struct CSW *)g_msc_cbw_csw[msc_class->sdchar - 'a'], NULL, CONFIG_USBHOST_MSC_TIMEOUT); +} + +static inline int usbh_msc_scsi_requestsense(struct usbh_msc *msc_class) +{ + struct CBW *cbw; + + /* Construct the CBW */ + cbw = (struct CBW *)g_msc_cbw_csw[msc_class->sdchar - 'a']; + memset(cbw, 0, USB_SIZEOF_MSC_CBW); + cbw->dSignature = MSC_CBW_Signature; + + cbw->bmFlags = 0x80; + cbw->dDataLength = SCSIRESP_FIXEDSENSEDATA_SIZEOF; + cbw->bCBLength = SCSICMD_REQUESTSENSE_SIZEOF; + cbw->CB[0] = SCSI_CMD_REQUESTSENSE; + cbw->CB[4] = SCSIRESP_FIXEDSENSEDATA_SIZEOF; + + return usbh_bulk_cbw_csw_xfer(msc_class, cbw, (struct CSW *)g_msc_cbw_csw[msc_class->sdchar - 'a'], g_msc_buf[msc_class->sdchar - 'a'], CONFIG_USBHOST_MSC_TIMEOUT); +} + +static inline int usbh_msc_scsi_inquiry(struct usbh_msc *msc_class) +{ + struct CBW *cbw; + + /* Construct the CBW */ + cbw = (struct CBW *)g_msc_cbw_csw[msc_class->sdchar - 'a']; + memset(cbw, 0, USB_SIZEOF_MSC_CBW); + cbw->dSignature = MSC_CBW_Signature; + + cbw->dDataLength = SCSIRESP_INQUIRY_SIZEOF; + cbw->bmFlags = 0x80; + cbw->bCBLength = SCSICMD_INQUIRY_SIZEOF; + cbw->CB[0] = SCSI_CMD_INQUIRY; + cbw->CB[4] = SCSIRESP_INQUIRY_SIZEOF; + + return usbh_bulk_cbw_csw_xfer(msc_class, cbw, (struct CSW *)g_msc_cbw_csw[msc_class->sdchar - 'a'], g_msc_buf[msc_class->sdchar - 'a'], CONFIG_USBHOST_MSC_TIMEOUT); +} + +static inline int usbh_msc_scsi_readcapacity10(struct usbh_msc *msc_class) +{ + struct CBW *cbw; + + /* Construct the CBW */ + cbw = (struct CBW *)g_msc_cbw_csw[msc_class->sdchar - 'a']; + memset(cbw, 0, USB_SIZEOF_MSC_CBW); + cbw->dSignature = MSC_CBW_Signature; + + cbw->dDataLength = SCSIRESP_READCAPACITY10_SIZEOF; + cbw->bmFlags = 0x80; + cbw->bCBLength = SCSICMD_READCAPACITY10_SIZEOF; + cbw->CB[0] = SCSI_CMD_READCAPACITY10; + + return usbh_bulk_cbw_csw_xfer(msc_class, cbw, (struct CSW *)g_msc_cbw_csw[msc_class->sdchar - 'a'], g_msc_buf[msc_class->sdchar - 'a'], CONFIG_USBHOST_MSC_TIMEOUT); +} + +static inline void usbh_msc_modeswitch(struct usbh_msc *msc_class, const uint8_t *message) +{ + struct CBW *cbw; + + /* Construct the CBW */ + cbw = (struct CBW *)g_msc_cbw_csw[msc_class->sdchar - 'a']; + + memcpy(g_msc_cbw_csw[msc_class->sdchar - 'a'], message, 31); + + usbh_bulk_cbw_csw_xfer(msc_class, cbw, (struct CSW *)g_msc_cbw_csw[msc_class->sdchar - 'a'], NULL, CONFIG_USBHOST_MSC_TIMEOUT); +} + +static int usbh_msc_connect(struct usbh_hubport *hport, uint8_t intf) +{ + struct usb_endpoint_descriptor *ep_desc; + struct usbh_msc_modeswitch_config *config; + int ret; + + struct usbh_msc *msc_class = usbh_msc_class_alloc(); + if (msc_class == NULL) { + USB_LOG_ERR("Fail to alloc msc_class\r\n"); + return -USB_ERR_NOMEM; + } + + msc_class->hport = hport; + msc_class->intf = intf; + + hport->config.intf[intf].priv = msc_class; + + ret = usbh_msc_get_maxlun(msc_class, g_msc_buf[msc_class->sdchar - 'a']); + if (ret < 0) { + if (ret == -USB_ERR_STALL) { + USB_LOG_WRN("Device does not support multiple LUNs\r\n"); + g_msc_buf[msc_class->sdchar - 'a'][0] = 0; + ret = 0; + } else { + return ret; + } + } + + USB_LOG_INFO("Get max LUN:%u\r\n", g_msc_buf[msc_class->sdchar - 'a'][0] + 1); + + for (uint8_t i = 0; i < hport->config.intf[intf].altsetting[0].intf_desc.bNumEndpoints; i++) { + ep_desc = &hport->config.intf[intf].altsetting[0].ep[i].ep_desc; + if (ep_desc->bEndpointAddress & 0x80) { + USBH_EP_INIT(msc_class->bulkin, ep_desc); + } else { + USBH_EP_INIT(msc_class->bulkout, ep_desc); + } + } + + if (g_msc_modeswitch_config) { + uint8_t num = 0; + while (1) { + config = &g_msc_modeswitch_config[num]; + if (config && config->name) { + if ((hport->device_desc.idVendor == config->vid) && + (hport->device_desc.idProduct == config->pid)) { + USB_LOG_INFO("%s usb_modeswitch enable\r\n", config->name); + usbh_msc_modeswitch(msc_class, config->message_content); + return 0; + } + num++; + } else { + break; + } + } + } + + snprintf(hport->config.intf[intf].devname, CONFIG_USBHOST_DEV_NAMELEN, DEV_FORMAT, msc_class->sdchar); + + USB_LOG_INFO("Register MSC Class:%s\r\n", hport->config.intf[intf].devname); + + usbh_msc_run(msc_class); + return ret; +} + +static int usbh_msc_disconnect(struct usbh_hubport *hport, uint8_t intf) +{ + int ret = 0; + + struct usbh_msc *msc_class = (struct usbh_msc *)hport->config.intf[intf].priv; + + if (msc_class) { + if (msc_class->bulkin) { + usbh_kill_urb(&msc_class->bulkin_urb); + } + + if (msc_class->bulkout) { + usbh_kill_urb(&msc_class->bulkout_urb); + } + + if (hport->config.intf[intf].devname[0] != '\0') { + usb_osal_thread_schedule_other(); + USB_LOG_INFO("Unregister MSC Class:%s\r\n", hport->config.intf[intf].devname); + usbh_msc_stop(msc_class); + } + + usbh_msc_class_free(msc_class); + } + + return ret; +} + +int usbh_msc_scsi_init(struct usbh_msc *msc_class) +{ + int ret; + uint16_t cnt; + + cnt = 0; + while (usbh_msc_scsi_testunitready(msc_class) < 0) { + USB_LOG_WRN("Device not ready, try again...\r\n"); + ret = usbh_msc_scsi_requestsense(msc_class); + if (ret < 0) { + USB_LOG_ERR("Fail to scsi_testunitready\r\n"); + } + cnt++; + if (cnt > CONFIG_USBHOST_MSC_READY_CHECK_TIMES) { + return -USB_ERR_NODEV; + } + } + ret = usbh_msc_scsi_inquiry(msc_class); + if (ret < 0) { + USB_LOG_ERR("Fail to scsi_inquiry\r\n"); + return ret; + } + + ret = usbh_msc_scsi_readcapacity10(msc_class); + if (ret < 0) { + USB_LOG_ERR("Fail to scsi_readcapacity10\r\n"); + return ret; + } + + if (msc_class->blocksize > 0) { + USB_LOG_INFO("Capacity info:\r\n"); + USB_LOG_INFO("Block num:%d,block size:%d\r\n", (unsigned int)msc_class->blocknum, (unsigned int)msc_class->blocksize); + } else { + USB_LOG_ERR("Invalid block size\r\n"); + return -USB_ERR_RANGE; + } + + return 0; +} + +int usbh_msc_scsi_write10(struct usbh_msc *msc_class, uint32_t start_sector, const uint8_t *buffer, uint32_t nsectors) +{ + struct CBW *cbw; + + /* Construct the CBW */ + cbw = (struct CBW *)g_msc_cbw_csw[msc_class->sdchar - 'a']; + memset(cbw, 0, USB_SIZEOF_MSC_CBW); + cbw->dSignature = MSC_CBW_Signature; + + cbw->dDataLength = (msc_class->blocksize * nsectors); + cbw->bCBLength = SCSICMD_WRITE10_SIZEOF; + cbw->CB[0] = SCSI_CMD_WRITE10; + + SET_BE32(&cbw->CB[2], start_sector); + SET_BE16(&cbw->CB[7], nsectors); + + return usbh_bulk_cbw_csw_xfer(msc_class, cbw, (struct CSW *)g_msc_cbw_csw[msc_class->sdchar - 'a'], (uint8_t *)buffer, CONFIG_USBHOST_MSC_TIMEOUT); +} + +int usbh_msc_scsi_read10(struct usbh_msc *msc_class, uint32_t start_sector, const uint8_t *buffer, uint32_t nsectors) +{ + struct CBW *cbw; + + /* Construct the CBW */ + cbw = (struct CBW *)g_msc_cbw_csw[msc_class->sdchar - 'a']; + memset(cbw, 0, USB_SIZEOF_MSC_CBW); + cbw->dSignature = MSC_CBW_Signature; + + cbw->dDataLength = (msc_class->blocksize * nsectors); + cbw->bmFlags = 0x80; + cbw->bCBLength = SCSICMD_READ10_SIZEOF; + cbw->CB[0] = SCSI_CMD_READ10; + + SET_BE32(&cbw->CB[2], start_sector); + SET_BE16(&cbw->CB[7], nsectors); + + return usbh_bulk_cbw_csw_xfer(msc_class, cbw, (struct CSW *)g_msc_cbw_csw[msc_class->sdchar - 'a'], (uint8_t *)buffer, CONFIG_USBHOST_MSC_TIMEOUT); +} + +void usbh_msc_modeswitch_enable(struct usbh_msc_modeswitch_config *config) +{ + if (config) { + g_msc_modeswitch_config = config; + } else { + g_msc_modeswitch_config = NULL; + } +} + +__WEAK void usbh_msc_run(struct usbh_msc *msc_class) +{ + (void)msc_class; +} + +__WEAK void usbh_msc_stop(struct usbh_msc *msc_class) +{ + (void)msc_class; +} + +const struct usbh_class_driver msc_class_driver = { + .driver_name = "msc", + .connect = usbh_msc_connect, + .disconnect = usbh_msc_disconnect +}; + +CLASS_INFO_DEFINE const struct usbh_class_info msc_class_info = { + .match_flags = USB_CLASS_MATCH_INTF_CLASS | USB_CLASS_MATCH_INTF_SUBCLASS | USB_CLASS_MATCH_INTF_PROTOCOL, + .bInterfaceClass = USB_DEVICE_CLASS_MASS_STORAGE, + .bInterfaceSubClass = MSC_SUBCLASS_SCSI, + .bInterfaceProtocol = MSC_PROTOCOL_BULK_ONLY, + .id_table = NULL, + .class_driver = &msc_class_driver +}; diff --git a/kernel/cherryusb/class/msc/usbh_msc.h b/kernel/cherryusb/class/msc/usbh_msc.h new file mode 100644 index 0000000..c4aee8a --- /dev/null +++ b/kernel/cherryusb/class/msc/usbh_msc.h @@ -0,0 +1,50 @@ +/* + * Copyright (c) 2022, sakumisu + * + * SPDX-License-Identifier: Apache-2.0 + */ +#ifndef USBH_MSC_H +#define USBH_MSC_H + +#include "usb_msc.h" +#include "usb_scsi.h" + +struct usbh_msc { + struct usbh_hubport *hport; + struct usb_endpoint_descriptor *bulkin; /* Bulk IN endpoint */ + struct usb_endpoint_descriptor *bulkout; /* Bulk OUT endpoint */ + struct usbh_urb bulkin_urb; /* Bulk IN urb */ + struct usbh_urb bulkout_urb; /* Bulk OUT urb */ + + uint8_t intf; /* Data interface number */ + uint8_t sdchar; + uint32_t blocknum; /* Number of blocks on the USB mass storage device */ + uint16_t blocksize; /* Block size of USB mass storage device */ + + void *user_data; +}; + +struct usbh_msc_modeswitch_config { + const char *name; + uint16_t vid; /* Vendor ID (for vendor/product specific devices) */ + uint16_t pid; /* Product ID (for vendor/product specific devices) */ + const uint8_t *message_content; +}; + +void usbh_msc_modeswitch_enable(struct usbh_msc_modeswitch_config *config); +int usbh_msc_scsi_init(struct usbh_msc *msc_class); +int usbh_msc_scsi_write10(struct usbh_msc *msc_class, uint32_t start_sector, const uint8_t *buffer, uint32_t nsectors); +int usbh_msc_scsi_read10(struct usbh_msc *msc_class, uint32_t start_sector, const uint8_t *buffer, uint32_t nsectors); + +void usbh_msc_run(struct usbh_msc *msc_class); +void usbh_msc_stop(struct usbh_msc *msc_class); + +#ifdef __cplusplus +extern "C" { +#endif + +#ifdef __cplusplus +} +#endif + +#endif /* USBH_MSC_H */ diff --git a/kernel/cherryusb/class/mtp/usb_mtp.h b/kernel/cherryusb/class/mtp/usb_mtp.h new file mode 100644 index 0000000..6616cf0 --- /dev/null +++ b/kernel/cherryusb/class/mtp/usb_mtp.h @@ -0,0 +1,682 @@ +/* + * Copyright (C) 2010 The Android Open Source Project + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* + * Copyright (c) 2025, sakumisu + * + * SPDX-License-Identifier: Apache-2.0 + */ +#ifndef USB_MTP_H +#define USB_MTP_H + +// clang-format off +#define MTP_STANDARD_VERSION 100 + +// Container Types +#define MTP_CONTAINER_TYPE_UNDEFINED 0 +#define MTP_CONTAINER_TYPE_COMMAND 1 +#define MTP_CONTAINER_TYPE_DATA 2 +#define MTP_CONTAINER_TYPE_RESPONSE 3 +#define MTP_CONTAINER_TYPE_EVENT 4 + +// Container Offsets +#define MTP_CONTAINER_LENGTH_OFFSET 0 +#define MTP_CONTAINER_TYPE_OFFSET 4 +#define MTP_CONTAINER_CODE_OFFSET 6 +#define MTP_CONTAINER_TRANSACTION_ID_OFFSET 8 +#define MTP_CONTAINER_PARAMETER_OFFSET 12 +#define MTP_CONTAINER_HEADER_SIZE 12 + +// Maximum buffer size for a MTP packet. +#define MTP_BUFFER_SIZE 16384 + +// MTP Data Types +#define MTP_TYPE_UNDEFINED 0x0000 // Undefined +#define MTP_TYPE_INT8 0x0001 // Signed 8-bit integer +#define MTP_TYPE_UINT8 0x0002 // Unsigned 8-bit integer +#define MTP_TYPE_INT16 0x0003 // Signed 16-bit integer +#define MTP_TYPE_UINT16 0x0004 // Unsigned 16-bit integer +#define MTP_TYPE_INT32 0x0005 // Signed 32-bit integer +#define MTP_TYPE_UINT32 0x0006 // Unsigned 32-bit integer +#define MTP_TYPE_INT64 0x0007 // Signed 64-bit integer +#define MTP_TYPE_UINT64 0x0008 // Unsigned 64-bit integer +#define MTP_TYPE_INT128 0x0009 // Signed 128-bit integer +#define MTP_TYPE_UINT128 0x000A // Unsigned 128-bit integer +#define MTP_TYPE_AINT8 0x4001 // Array of signed 8-bit integers +#define MTP_TYPE_AUINT8 0x4002 // Array of unsigned 8-bit integers +#define MTP_TYPE_AINT16 0x4003 // Array of signed 16-bit integers +#define MTP_TYPE_AUINT16 0x4004 // Array of unsigned 16-bit integers +#define MTP_TYPE_AINT32 0x4005 // Array of signed 32-bit integers +#define MTP_TYPE_AUINT32 0x4006 // Array of unsigned 32-bit integers +#define MTP_TYPE_AINT64 0x4007 // Array of signed 64-bit integers +#define MTP_TYPE_AUINT64 0x4008 // Array of unsigned 64-bit integers +#define MTP_TYPE_AINT128 0x4009 // Array of signed 128-bit integers +#define MTP_TYPE_AUINT128 0x400A // Array of unsigned 128-bit integers +#define MTP_TYPE_STR 0xFFFF // Variable-length Unicode string + +// MTP Format Codes +#define MTP_FORMAT_UNDEFINED 0x3000 // Undefined object +#define MTP_FORMAT_ASSOCIATION 0x3001 // Association (for example, a folder) +#define MTP_FORMAT_SCRIPT 0x3002 // Device model-specific script +#define MTP_FORMAT_EXECUTABLE 0x3003 // Device model-specific binary executable +#define MTP_FORMAT_TEXT 0x3004 // Text file +#define MTP_FORMAT_HTML 0x3005 // Hypertext Markup Language file (text) +#define MTP_FORMAT_DPOF 0x3006 // Digital Print Order Format file (text) +#define MTP_FORMAT_AIFF 0x3007 // Audio clip +#define MTP_FORMAT_WAV 0x3008 // Audio clip +#define MTP_FORMAT_MP3 0x3009 // Audio clip +#define MTP_FORMAT_AVI 0x300A // Video clip +#define MTP_FORMAT_MPEG 0x300B // Video clip +#define MTP_FORMAT_ASF 0x300C // Microsoft Advanced Streaming Format (video) +#define MTP_FORMAT_DEFINED 0x3800 // Unknown image object +#define MTP_FORMAT_EXIF_JPEG 0x3801 // Exchangeable File Format, JEIDA standard +#define MTP_FORMAT_TIFF_EP 0x3802 // Tag Image File Format for Electronic Photography +#define MTP_FORMAT_FLASHPIX 0x3803 // Structured Storage Image Format +#define MTP_FORMAT_BMP 0x3804 // Microsoft Windows Bitmap file +#define MTP_FORMAT_CIFF 0x3805 // Canon Camera Image File Format +#define MTP_FORMAT_GIF 0x3807 // Graphics Interchange Format +#define MTP_FORMAT_JFIF 0x3808 // JPEG File Interchange Format +#define MTP_FORMAT_CD 0x3809 // PhotoCD Image Pac +#define MTP_FORMAT_PICT 0x380A // Quickdraw Image Format +#define MTP_FORMAT_PNG 0x380B // Portable Network Graphics +#define MTP_FORMAT_TIFF 0x380D // Tag Image File Format +#define MTP_FORMAT_TIFF_IT 0x380E // Tag Image File Format for Information Technology (graphic arts) +#define MTP_FORMAT_JP2 0x380F // JPEG2000 Baseline File Format +#define MTP_FORMAT_JPX 0x3810 // JPEG2000 Extended File Format +#define MTP_FORMAT_DNG 0x3811 // Digital Negative +#define MTP_FORMAT_HEIF 0x3812 // HEIF images +#define MTP_FORMAT_UNDEFINED_FIRMWARE 0xB802 +#define MTP_FORMAT_WINDOWS_IMAGE_FORMAT 0xB881 +#define MTP_FORMAT_UNDEFINED_AUDIO 0xB900 +#define MTP_FORMAT_WMA 0xB901 +#define MTP_FORMAT_OGG 0xB902 +#define MTP_FORMAT_AAC 0xB903 +#define MTP_FORMAT_AUDIBLE 0xB904 +#define MTP_FORMAT_FLAC 0xB906 +#define MTP_FORMAT_UNDEFINED_VIDEO 0xB980 +#define MTP_FORMAT_WMV 0xB981 +#define MTP_FORMAT_MP4_CONTAINER 0xB982 // ISO 14496-1 +#define MTP_FORMAT_MP2 0xB983 +#define MTP_FORMAT_3GP_CONTAINER 0xB984 // 3GPP file format. Details: http://www.3gpp.org/ftp/Specs/html-info/26244.htm (page title - \u201cTransparent end-to-end packet switched streaming service, 3GPP file format\u201d). +#define MTP_FORMAT_UNDEFINED_COLLECTION 0xBA00 +#define MTP_FORMAT_ABSTRACT_MULTIMEDIA_ALBUM 0xBA01 +#define MTP_FORMAT_ABSTRACT_IMAGE_ALBUM 0xBA02 +#define MTP_FORMAT_ABSTRACT_AUDIO_ALBUM 0xBA03 +#define MTP_FORMAT_ABSTRACT_VIDEO_ALBUM 0xBA04 +#define MTP_FORMAT_ABSTRACT_AV_PLAYLIST 0xBA05 +#define MTP_FORMAT_ABSTRACT_CONTACT_GROUP 0xBA06 +#define MTP_FORMAT_ABSTRACT_MESSAGE_FOLDER 0xBA07 +#define MTP_FORMAT_ABSTRACT_CHAPTERED_PRODUCTION 0xBA08 +#define MTP_FORMAT_ABSTRACT_AUDIO_PLAYLIST 0xBA09 +#define MTP_FORMAT_ABSTRACT_VIDEO_PLAYLIST 0xBA0A +#define MTP_FORMAT_ABSTRACT_MEDIACAST 0xBA0B // For use with mediacasts; references multimedia enclosures of RSS feeds or episodic content +#define MTP_FORMAT_WPL_PLAYLIST 0xBA10 +#define MTP_FORMAT_M3U_PLAYLIST 0xBA11 +#define MTP_FORMAT_MPL_PLAYLIST 0xBA12 +#define MTP_FORMAT_ASX_PLAYLIST 0xBA13 +#define MTP_FORMAT_PLS_PLAYLIST 0xBA14 +#define MTP_FORMAT_UNDEFINED_DOCUMENT 0xBA80 +#define MTP_FORMAT_ABSTRACT_DOCUMENT 0xBA81 +#define MTP_FORMAT_XML_DOCUMENT 0xBA82 +#define MTP_FORMAT_MS_WORD_DOCUMENT 0xBA83 +#define MTP_FORMAT_MHT_COMPILED_HTML_DOCUMENT 0xBA84 +#define MTP_FORMAT_MS_EXCEL_SPREADSHEET 0xBA85 +#define MTP_FORMAT_MS_POWERPOINT_PRESENTATION 0xBA86 +#define MTP_FORMAT_UNDEFINED_MESSAGE 0xBB00 +#define MTP_FORMAT_ABSTRACT_MESSSAGE 0xBB01 +#define MTP_FORMAT_UNDEFINED_CONTACT 0xBB80 +#define MTP_FORMAT_ABSTRACT_CONTACT 0xBB81 +#define MTP_FORMAT_VCARD_2 0xBB82 + +// MTP Object Property Codes +#define MTP_PROPERTY_STORAGE_ID 0xDC01 +#define MTP_PROPERTY_OBJECT_FORMAT 0xDC02 +#define MTP_PROPERTY_PROTECTION_STATUS 0xDC03 +#define MTP_PROPERTY_OBJECT_SIZE 0xDC04 +#define MTP_PROPERTY_ASSOCIATION_TYPE 0xDC05 +#define MTP_PROPERTY_ASSOCIATION_DESC 0xDC06 +#define MTP_PROPERTY_OBJECT_FILE_NAME 0xDC07 +#define MTP_PROPERTY_DATE_CREATED 0xDC08 +#define MTP_PROPERTY_DATE_MODIFIED 0xDC09 +#define MTP_PROPERTY_KEYWORDS 0xDC0A +#define MTP_PROPERTY_PARENT_OBJECT 0xDC0B +#define MTP_PROPERTY_ALLOWED_FOLDER_CONTENTS 0xDC0C +#define MTP_PROPERTY_HIDDEN 0xDC0D +#define MTP_PROPERTY_SYSTEM_OBJECT 0xDC0E +#define MTP_PROPERTY_PERSISTENT_UID 0xDC41 +#define MTP_PROPERTY_SYNC_ID 0xDC42 +#define MTP_PROPERTY_PROPERTY_BAG 0xDC43 +#define MTP_PROPERTY_NAME 0xDC44 +#define MTP_PROPERTY_CREATED_BY 0xDC45 +#define MTP_PROPERTY_ARTIST 0xDC46 +#define MTP_PROPERTY_DATE_AUTHORED 0xDC47 +#define MTP_PROPERTY_DESCRIPTION 0xDC48 +#define MTP_PROPERTY_URL_REFERENCE 0xDC49 +#define MTP_PROPERTY_LANGUAGE_LOCALE 0xDC4A +#define MTP_PROPERTY_COPYRIGHT_INFORMATION 0xDC4B +#define MTP_PROPERTY_SOURCE 0xDC4C +#define MTP_PROPERTY_ORIGIN_LOCATION 0xDC4D +#define MTP_PROPERTY_DATE_ADDED 0xDC4E +#define MTP_PROPERTY_NON_CONSUMABLE 0xDC4F +#define MTP_PROPERTY_CORRUPT_UNPLAYABLE 0xDC50 +#define MTP_PROPERTY_PRODUCER_SERIAL_NUMBER 0xDC51 +#define MTP_PROPERTY_REPRESENTATIVE_SAMPLE_FORMAT 0xDC81 +#define MTP_PROPERTY_REPRESENTATIVE_SAMPLE_SIZE 0xDC82 +#define MTP_PROPERTY_REPRESENTATIVE_SAMPLE_HEIGHT 0xDC83 +#define MTP_PROPERTY_REPRESENTATIVE_SAMPLE_WIDTH 0xDC84 +#define MTP_PROPERTY_REPRESENTATIVE_SAMPLE_DURATION 0xDC85 +#define MTP_PROPERTY_REPRESENTATIVE_SAMPLE_DATA 0xDC86 +#define MTP_PROPERTY_WIDTH 0xDC87 +#define MTP_PROPERTY_HEIGHT 0xDC88 +#define MTP_PROPERTY_DURATION 0xDC89 +#define MTP_PROPERTY_RATING 0xDC8A +#define MTP_PROPERTY_TRACK 0xDC8B +#define MTP_PROPERTY_GENRE 0xDC8C +#define MTP_PROPERTY_CREDITS 0xDC8D +#define MTP_PROPERTY_LYRICS 0xDC8E +#define MTP_PROPERTY_SUBSCRIPTION_CONTENT_ID 0xDC8F +#define MTP_PROPERTY_PRODUCED_BY 0xDC90 +#define MTP_PROPERTY_USE_COUNT 0xDC91 +#define MTP_PROPERTY_SKIP_COUNT 0xDC92 +#define MTP_PROPERTY_LAST_ACCESSED 0xDC93 +#define MTP_PROPERTY_PARENTAL_RATING 0xDC94 +#define MTP_PROPERTY_META_GENRE 0xDC95 +#define MTP_PROPERTY_COMPOSER 0xDC96 +#define MTP_PROPERTY_EFFECTIVE_RATING 0xDC97 +#define MTP_PROPERTY_SUBTITLE 0xDC98 +#define MTP_PROPERTY_ORIGINAL_RELEASE_DATE 0xDC99 +#define MTP_PROPERTY_ALBUM_NAME 0xDC9A +#define MTP_PROPERTY_ALBUM_ARTIST 0xDC9B +#define MTP_PROPERTY_MOOD 0xDC9C +#define MTP_PROPERTY_DRM_STATUS 0xDC9D +#define MTP_PROPERTY_SUB_DESCRIPTION 0xDC9E +#define MTP_PROPERTY_IS_CROPPED 0xDCD1 +#define MTP_PROPERTY_IS_COLOUR_CORRECTED 0xDCD2 +#define MTP_PROPERTY_IMAGE_BIT_DEPTH 0xDCD3 +#define MTP_PROPERTY_F_NUMBER 0xDCD4 +#define MTP_PROPERTY_EXPOSURE_TIME 0xDCD5 +#define MTP_PROPERTY_EXPOSURE_INDEX 0xDCD6 +#define MTP_PROPERTY_TOTAL_BITRATE 0xDE91 +#define MTP_PROPERTY_BITRATE_TYPE 0xDE92 +#define MTP_PROPERTY_SAMPLE_RATE 0xDE93 +#define MTP_PROPERTY_NUMBER_OF_CHANNELS 0xDE94 +#define MTP_PROPERTY_AUDIO_BIT_DEPTH 0xDE95 +#define MTP_PROPERTY_SCAN_TYPE 0xDE97 +#define MTP_PROPERTY_AUDIO_WAVE_CODEC 0xDE99 +#define MTP_PROPERTY_AUDIO_BITRATE 0xDE9A +#define MTP_PROPERTY_VIDEO_FOURCC_CODEC 0xDE9B +#define MTP_PROPERTY_VIDEO_BITRATE 0xDE9C +#define MTP_PROPERTY_FRAMES_PER_THOUSAND_SECONDS 0xDE9D +#define MTP_PROPERTY_KEYFRAME_DISTANCE 0xDE9E +#define MTP_PROPERTY_BUFFER_SIZE 0xDE9F +#define MTP_PROPERTY_ENCODING_QUALITY 0xDEA0 +#define MTP_PROPERTY_ENCODING_PROFILE 0xDEA1 +#define MTP_PROPERTY_DISPLAY_NAME 0xDCE0 +#define MTP_PROPERTY_BODY_TEXT 0xDCE1 +#define MTP_PROPERTY_SUBJECT 0xDCE2 +#define MTP_PROPERTY_PRIORITY 0xDCE3 +#define MTP_PROPERTY_GIVEN_NAME 0xDD00 +#define MTP_PROPERTY_MIDDLE_NAMES 0xDD01 +#define MTP_PROPERTY_FAMILY_NAME 0xDD02 +#define MTP_PROPERTY_PREFIX 0xDD03 +#define MTP_PROPERTY_SUFFIX 0xDD04 +#define MTP_PROPERTY_PHONETIC_GIVEN_NAME 0xDD05 +#define MTP_PROPERTY_PHONETIC_FAMILY_NAME 0xDD06 +#define MTP_PROPERTY_EMAIL_PRIMARY 0xDD07 +#define MTP_PROPERTY_EMAIL_PERSONAL_1 0xDD08 +#define MTP_PROPERTY_EMAIL_PERSONAL_2 0xDD09 +#define MTP_PROPERTY_EMAIL_BUSINESS_1 0xDD0A +#define MTP_PROPERTY_EMAIL_BUSINESS_2 0xDD0B +#define MTP_PROPERTY_EMAIL_OTHERS 0xDD0C +#define MTP_PROPERTY_PHONE_NUMBER_PRIMARY 0xDD0D +#define MTP_PROPERTY_PHONE_NUMBER_PERSONAL 0xDD0E +#define MTP_PROPERTY_PHONE_NUMBER_PERSONAL_2 0xDD0F +#define MTP_PROPERTY_PHONE_NUMBER_BUSINESS 0xDD10 +#define MTP_PROPERTY_PHONE_NUMBER_BUSINESS_2 0xDD11 +#define MTP_PROPERTY_PHONE_NUMBER_MOBILE 0xDD12 +#define MTP_PROPERTY_PHONE_NUMBER_MOBILE_2 0xDD13 +#define MTP_PROPERTY_FAX_NUMBER_PRIMARY 0xDD14 +#define MTP_PROPERTY_FAX_NUMBER_PERSONAL 0xDD15 +#define MTP_PROPERTY_FAX_NUMBER_BUSINESS 0xDD16 +#define MTP_PROPERTY_PAGER_NUMBER 0xDD17 +#define MTP_PROPERTY_PHONE_NUMBER_OTHERS 0xDD18 +#define MTP_PROPERTY_PRIMARY_WEB_ADDRESS 0xDD19 +#define MTP_PROPERTY_PERSONAL_WEB_ADDRESS 0xDD1A +#define MTP_PROPERTY_BUSINESS_WEB_ADDRESS 0xDD1B +#define MTP_PROPERTY_INSTANT_MESSANGER_ADDRESS 0xDD1C +#define MTP_PROPERTY_INSTANT_MESSANGER_ADDRESS_2 0xDD1D +#define MTP_PROPERTY_INSTANT_MESSANGER_ADDRESS_3 0xDD1E +#define MTP_PROPERTY_POSTAL_ADDRESS_PERSONAL_FULL 0xDD1F +#define MTP_PROPERTY_POSTAL_ADDRESS_PERSONAL_LINE_1 0xDD20 +#define MTP_PROPERTY_POSTAL_ADDRESS_PERSONAL_LINE_2 0xDD21 +#define MTP_PROPERTY_POSTAL_ADDRESS_PERSONAL_CITY 0xDD22 +#define MTP_PROPERTY_POSTAL_ADDRESS_PERSONAL_REGION 0xDD23 +#define MTP_PROPERTY_POSTAL_ADDRESS_PERSONAL_POSTAL_CODE 0xDD24 +#define MTP_PROPERTY_POSTAL_ADDRESS_PERSONAL_COUNTRY 0xDD25 +#define MTP_PROPERTY_POSTAL_ADDRESS_BUSINESS_FULL 0xDD26 +#define MTP_PROPERTY_POSTAL_ADDRESS_BUSINESS_LINE_1 0xDD27 +#define MTP_PROPERTY_POSTAL_ADDRESS_BUSINESS_LINE_2 0xDD28 +#define MTP_PROPERTY_POSTAL_ADDRESS_BUSINESS_CITY 0xDD29 +#define MTP_PROPERTY_POSTAL_ADDRESS_BUSINESS_REGION 0xDD2A +#define MTP_PROPERTY_POSTAL_ADDRESS_BUSINESS_POSTAL_CODE 0xDD2B +#define MTP_PROPERTY_POSTAL_ADDRESS_BUSINESS_COUNTRY 0xDD2C +#define MTP_PROPERTY_POSTAL_ADDRESS_OTHER_FULL 0xDD2D +#define MTP_PROPERTY_POSTAL_ADDRESS_OTHER_LINE_1 0xDD2E +#define MTP_PROPERTY_POSTAL_ADDRESS_OTHER_LINE_2 0xDD2F +#define MTP_PROPERTY_POSTAL_ADDRESS_OTHER_CITY 0xDD30 +#define MTP_PROPERTY_POSTAL_ADDRESS_OTHER_REGION 0xDD31 +#define MTP_PROPERTY_POSTAL_ADDRESS_OTHER_POSTAL_CODE 0xDD32 +#define MTP_PROPERTY_POSTAL_ADDRESS_OTHER_COUNTRY 0xDD33 +#define MTP_PROPERTY_ORGANIZATION_NAME 0xDD34 +#define MTP_PROPERTY_PHONETIC_ORGANIZATION_NAME 0xDD35 +#define MTP_PROPERTY_ROLE 0xDD36 +#define MTP_PROPERTY_BIRTHDATE 0xDD37 +#define MTP_PROPERTY_MESSAGE_TO 0xDD40 +#define MTP_PROPERTY_MESSAGE_CC 0xDD41 +#define MTP_PROPERTY_MESSAGE_BCC 0xDD42 +#define MTP_PROPERTY_MESSAGE_READ 0xDD43 +#define MTP_PROPERTY_MESSAGE_RECEIVED_TIME 0xDD44 +#define MTP_PROPERTY_MESSAGE_SENDER 0xDD45 +#define MTP_PROPERTY_ACTIVITY_BEGIN_TIME 0xDD50 +#define MTP_PROPERTY_ACTIVITY_END_TIME 0xDD51 +#define MTP_PROPERTY_ACTIVITY_LOCATION 0xDD52 +#define MTP_PROPERTY_ACTIVITY_REQUIRED_ATTENDEES 0xDD54 +#define MTP_PROPERTY_ACTIVITY_OPTIONAL_ATTENDEES 0xDD55 +#define MTP_PROPERTY_ACTIVITY_RESOURCES 0xDD56 +#define MTP_PROPERTY_ACTIVITY_ACCEPTED 0xDD57 +#define MTP_PROPERTY_ACTIVITY_TENTATIVE 0xDD58 +#define MTP_PROPERTY_ACTIVITY_DECLINED 0xDD59 +#define MTP_PROPERTY_ACTIVITY_REMAINDER_TIME 0xDD5A +#define MTP_PROPERTY_ACTIVITY_OWNER 0xDD5B +#define MTP_PROPERTY_ACTIVITY_STATUS 0xDD5C +#define MTP_PROPERTY_OWNER 0xDD5D +#define MTP_PROPERTY_EDITOR 0xDD5E +#define MTP_PROPERTY_WEBMASTER 0xDD5F +#define MTP_PROPERTY_URL_SOURCE 0xDD60 +#define MTP_PROPERTY_URL_DESTINATION 0xDD61 +#define MTP_PROPERTY_TIME_BOOKMARK 0xDD62 +#define MTP_PROPERTY_OBJECT_BOOKMARK 0xDD63 +#define MTP_PROPERTY_BYTE_BOOKMARK 0xDD64 +#define MTP_PROPERTY_LAST_BUILD_DATE 0xDD70 +#define MTP_PROPERTY_TIME_TO_LIVE 0xDD71 +#define MTP_PROPERTY_MEDIA_GUID 0xDD72 + +// MTP Device Property Codes +#define MTP_DEVICE_PROPERTY_UNDEFINED 0x5000 +#define MTP_DEVICE_PROPERTY_BATTERY_LEVEL 0x5001 +#define MTP_DEVICE_PROPERTY_FUNCTIONAL_MODE 0x5002 +#define MTP_DEVICE_PROPERTY_IMAGE_SIZE 0x5003 +#define MTP_DEVICE_PROPERTY_COMPRESSION_SETTING 0x5004 +#define MTP_DEVICE_PROPERTY_WHITE_BALANCE 0x5005 +#define MTP_DEVICE_PROPERTY_RGB_GAIN 0x5006 +#define MTP_DEVICE_PROPERTY_F_NUMBER 0x5007 +#define MTP_DEVICE_PROPERTY_FOCAL_LENGTH 0x5008 +#define MTP_DEVICE_PROPERTY_FOCUS_DISTANCE 0x5009 +#define MTP_DEVICE_PROPERTY_FOCUS_MODE 0x500A +#define MTP_DEVICE_PROPERTY_EXPOSURE_METERING_MODE 0x500B +#define MTP_DEVICE_PROPERTY_FLASH_MODE 0x500C +#define MTP_DEVICE_PROPERTY_EXPOSURE_TIME 0x500D +#define MTP_DEVICE_PROPERTY_EXPOSURE_PROGRAM_MODE 0x500E +#define MTP_DEVICE_PROPERTY_EXPOSURE_INDEX 0x500F +#define MTP_DEVICE_PROPERTY_EXPOSURE_BIAS_COMPENSATION 0x5010 +#define MTP_DEVICE_PROPERTY_DATETIME 0x5011 +#define MTP_DEVICE_PROPERTY_CAPTURE_DELAY 0x5012 +#define MTP_DEVICE_PROPERTY_STILL_CAPTURE_MODE 0x5013 +#define MTP_DEVICE_PROPERTY_CONTRAST 0x5014 +#define MTP_DEVICE_PROPERTY_SHARPNESS 0x5015 +#define MTP_DEVICE_PROPERTY_DIGITAL_ZOOM 0x5016 +#define MTP_DEVICE_PROPERTY_EFFECT_MODE 0x5017 +#define MTP_DEVICE_PROPERTY_BURST_NUMBER 0x5018 +#define MTP_DEVICE_PROPERTY_BURST_INTERVAL 0x5019 +#define MTP_DEVICE_PROPERTY_TIMELAPSE_NUMBER 0x501A +#define MTP_DEVICE_PROPERTY_TIMELAPSE_INTERVAL 0x501B +#define MTP_DEVICE_PROPERTY_FOCUS_METERING_MODE 0x501C +#define MTP_DEVICE_PROPERTY_UPLOAD_URL 0x501D +#define MTP_DEVICE_PROPERTY_ARTIST 0x501E +#define MTP_DEVICE_PROPERTY_COPYRIGHT_INFO 0x501F +#define MTP_DEVICE_PROPERTY_SYNCHRONIZATION_PARTNER 0xD401 +#define MTP_DEVICE_PROPERTY_DEVICE_FRIENDLY_NAME 0xD402 +#define MTP_DEVICE_PROPERTY_VOLUME 0xD403 +#define MTP_DEVICE_PROPERTY_SUPPORTED_FORMATS_ORDERED 0xD404 +#define MTP_DEVICE_PROPERTY_DEVICE_ICON 0xD405 +#define MTP_DEVICE_PROPERTY_PLAYBACK_RATE 0xD410 +#define MTP_DEVICE_PROPERTY_PLAYBACK_OBJECT 0xD411 +#define MTP_DEVICE_PROPERTY_PLAYBACK_CONTAINER_INDEX 0xD412 +#define MTP_DEVICE_PROPERTY_SESSION_INITIATOR_VERSION_INFO 0xD406 +#define MTP_DEVICE_PROPERTY_PERCEIVED_DEVICE_TYPE 0xD407 + +// MTP Operation Codes +#define MTP_OPERATION_GET_DEVICE_INFO 0x1001 +#define MTP_OPERATION_OPEN_SESSION 0x1002 +#define MTP_OPERATION_CLOSE_SESSION 0x1003 +#define MTP_OPERATION_GET_STORAGE_IDS 0x1004 +#define MTP_OPERATION_GET_STORAGE_INFO 0x1005 +#define MTP_OPERATION_GET_NUM_OBJECTS 0x1006 +#define MTP_OPERATION_GET_OBJECT_HANDLES 0x1007 +#define MTP_OPERATION_GET_OBJECT_INFO 0x1008 +#define MTP_OPERATION_GET_OBJECT 0x1009 +#define MTP_OPERATION_GET_THUMB 0x100A +#define MTP_OPERATION_DELETE_OBJECT 0x100B +#define MTP_OPERATION_SEND_OBJECT_INFO 0x100C +#define MTP_OPERATION_SEND_OBJECT 0x100D +#define MTP_OPERATION_INITIATE_CAPTURE 0x100E +#define MTP_OPERATION_FORMAT_STORE 0x100F +#define MTP_OPERATION_RESET_DEVICE 0x1010 +#define MTP_OPERATION_SELF_TEST 0x1011 +#define MTP_OPERATION_SET_OBJECT_PROTECTION 0x1012 +#define MTP_OPERATION_POWER_DOWN 0x1013 +#define MTP_OPERATION_GET_DEVICE_PROP_DESC 0x1014 +#define MTP_OPERATION_GET_DEVICE_PROP_VALUE 0x1015 +#define MTP_OPERATION_SET_DEVICE_PROP_VALUE 0x1016 +#define MTP_OPERATION_RESET_DEVICE_PROP_VALUE 0x1017 +#define MTP_OPERATION_TERMINATE_OPEN_CAPTURE 0x1018 +#define MTP_OPERATION_MOVE_OBJECT 0x1019 +#define MTP_OPERATION_COPY_OBJECT 0x101A +#define MTP_OPERATION_GET_PARTIAL_OBJECT 0x101B +#define MTP_OPERATION_INITIATE_OPEN_CAPTURE 0x101C +#define MTP_OPERATION_GET_OBJECT_PROPS_SUPPORTED 0x9801 +#define MTP_OPERATION_GET_OBJECT_PROP_DESC 0x9802 +#define MTP_OPERATION_GET_OBJECT_PROP_VALUE 0x9803 +#define MTP_OPERATION_SET_OBJECT_PROP_VALUE 0x9804 +#define MTP_OPERATION_GET_OBJECT_PROP_LIST 0x9805 +#define MTP_OPERATION_SET_OBJECT_PROP_LIST 0x9806 +#define MTP_OPERATION_GET_INTERDEPENDENT_PROP_DESC 0x9807 +#define MTP_OPERATION_SEND_OBJECT_PROP_LIST 0x9808 +#define MTP_OPERATION_GET_OBJECT_REFERENCES 0x9810 +#define MTP_OPERATION_SET_OBJECT_REFERENCES 0x9811 +#define MTP_OPERATION_SKIP 0x9820 + +// Android extensions for direct file IO + +// Same as GetPartialObject, but with 64 bit offset +#define MTP_OPERATION_GET_PARTIAL_OBJECT_64 0x95C1 +// Same as GetPartialObject64, but copying host to device +#define MTP_OPERATION_SEND_PARTIAL_OBJECT 0x95C2 +// Truncates file to 64 bit length +#define MTP_OPERATION_TRUNCATE_OBJECT 0x95C3 +// Must be called before using SendPartialObject and TruncateObject +#define MTP_OPERATION_BEGIN_EDIT_OBJECT 0x95C4 +// Called to commit changes made by SendPartialObject and TruncateObject +#define MTP_OPERATION_END_EDIT_OBJECT 0x95C5 + +// MTP Response Codes +#define MTP_RESPONSE_UNDEFINED 0x2000 +#define MTP_RESPONSE_OK 0x2001 +#define MTP_RESPONSE_GENERAL_ERROR 0x2002 +#define MTP_RESPONSE_SESSION_NOT_OPEN 0x2003 +#define MTP_RESPONSE_INVALID_TRANSACTION_ID 0x2004 +#define MTP_RESPONSE_OPERATION_NOT_SUPPORTED 0x2005 +#define MTP_RESPONSE_PARAMETER_NOT_SUPPORTED 0x2006 +#define MTP_RESPONSE_INCOMPLETE_TRANSFER 0x2007 +#define MTP_RESPONSE_INVALID_STORAGE_ID 0x2008 +#define MTP_RESPONSE_INVALID_OBJECT_HANDLE 0x2009 +#define MTP_RESPONSE_DEVICE_PROP_NOT_SUPPORTED 0x200A +#define MTP_RESPONSE_INVALID_OBJECT_FORMAT_CODE 0x200B +#define MTP_RESPONSE_STORAGE_FULL 0x200C +#define MTP_RESPONSE_OBJECT_WRITE_PROTECTED 0x200D +#define MTP_RESPONSE_STORE_READ_ONLY 0x200E +#define MTP_RESPONSE_ACCESS_DENIED 0x200F +#define MTP_RESPONSE_NO_THUMBNAIL_PRESENT 0x2010 +#define MTP_RESPONSE_SELF_TEST_FAILED 0x2011 +#define MTP_RESPONSE_PARTIAL_DELETION 0x2012 +#define MTP_RESPONSE_STORE_NOT_AVAILABLE 0x2013 +#define MTP_RESPONSE_SPECIFICATION_BY_FORMAT_UNSUPPORTED 0x2014 +#define MTP_RESPONSE_NO_VALID_OBJECT_INFO 0x2015 +#define MTP_RESPONSE_INVALID_CODE_FORMAT 0x2016 +#define MTP_RESPONSE_UNKNOWN_VENDOR_CODE 0x2017 +#define MTP_RESPONSE_CAPTURE_ALREADY_TERMINATED 0x2018 +#define MTP_RESPONSE_DEVICE_BUSY 0x2019 +#define MTP_RESPONSE_INVALID_PARENT_OBJECT 0x201A +#define MTP_RESPONSE_INVALID_DEVICE_PROP_FORMAT 0x201B +#define MTP_RESPONSE_INVALID_DEVICE_PROP_VALUE 0x201C +#define MTP_RESPONSE_INVALID_PARAMETER 0x201D +#define MTP_RESPONSE_SESSION_ALREADY_OPEN 0x201E +#define MTP_RESPONSE_TRANSACTION_CANCELLED 0x201F +#define MTP_RESPONSE_SPECIFICATION_OF_DESTINATION_UNSUPPORTED 0x2020 +#define MTP_RESPONSE_INVALID_OBJECT_PROP_CODE 0xA801 +#define MTP_RESPONSE_INVALID_OBJECT_PROP_FORMAT 0xA802 +#define MTP_RESPONSE_INVALID_OBJECT_PROP_VALUE 0xA803 +#define MTP_RESPONSE_INVALID_OBJECT_REFERENCE 0xA804 +#define MTP_RESPONSE_GROUP_NOT_SUPPORTED 0xA805 +#define MTP_RESPONSE_INVALID_DATASET 0xA806 +#define MTP_RESPONSE_SPECIFICATION_BY_GROUP_UNSUPPORTED 0xA807 +#define MTP_RESPONSE_SPECIFICATION_BY_DEPTH_UNSUPPORTED 0xA808 +#define MTP_RESPONSE_OBJECT_TOO_LARGE 0xA809 +#define MTP_RESPONSE_OBJECT_PROP_NOT_SUPPORTED 0xA80A +#define MTP_RESPONSE_NO_RESPONSE 0xFFFF + +// MTP Event Codes +#define MTP_EVENT_UNDEFINED 0x4000 +#define MTP_EVENT_CANCEL_TRANSACTION 0x4001 +#define MTP_EVENT_OBJECT_ADDED 0x4002 +#define MTP_EVENT_OBJECT_REMOVED 0x4003 +#define MTP_EVENT_STORE_ADDED 0x4004 +#define MTP_EVENT_STORE_REMOVED 0x4005 +#define MTP_EVENT_DEVICE_PROP_CHANGED 0x4006 +#define MTP_EVENT_OBJECT_INFO_CHANGED 0x4007 +#define MTP_EVENT_DEVICE_INFO_CHANGED 0x4008 +#define MTP_EVENT_REQUEST_OBJECT_TRANSFER 0x4009 +#define MTP_EVENT_STORE_FULL 0x400A +#define MTP_EVENT_DEVICE_RESET 0x400B +#define MTP_EVENT_STORAGE_INFO_CHANGED 0x400C +#define MTP_EVENT_CAPTURE_COMPLETE 0x400D +#define MTP_EVENT_UNREPORTED_STATUS 0x400E +#define MTP_EVENT_OBJECT_PROP_CHANGED 0xC801 +#define MTP_EVENT_OBJECT_PROP_DESC_CHANGED 0xC802 +#define MTP_EVENT_OBJECT_REFERENCES_CHANGED 0xC803 + +// Storage Type +#define MTP_STORAGE_FIXED_ROM 0x0001 +#define MTP_STORAGE_REMOVABLE_ROM 0x0002 +#define MTP_STORAGE_FIXED_RAM 0x0003 +#define MTP_STORAGE_REMOVABLE_RAM 0x0004 + +// Storage File System +#define MTP_STORAGE_FILESYSTEM_FLAT 0x0001 +#define MTP_STORAGE_FILESYSTEM_HIERARCHICAL 0x0002 +#define MTP_STORAGE_FILESYSTEM_DCF 0x0003 + +// Storage Access Capability +#define MTP_STORAGE_READ_WRITE 0x0000 +#define MTP_STORAGE_READ_ONLY_WITHOUT_DELETE 0x0001 +#define MTP_STORAGE_READ_ONLY_WITH_DELETE 0x0002 + +// Association Type +#define MTP_ASSOCIATION_TYPE_UNDEFINED 0x0000 +#define MTP_ASSOCIATION_TYPE_GENERIC_FOLDER 0x0001 + +// MTP class reqeusts +#define MTP_REQUEST_CANCEL 0x64 +#define MTP_REQUEST_GET_EXT_EVENT_DATA 0x65 +#define MTP_REQUEST_RESET 0x66 +#define MTP_REQUEST_GET_DEVICE_STATUS 0x67 +// clang-format on + +#define USB_MTP_CLASS 0x06 + +#define USB_MTP_SUB_CLASS 0x01U +#define USB_MTP_PROTOCOL 0x01U + +struct mtp_header { + uint32_t conlen; + uint16_t contype; + uint16_t code; + uint32_t trans_id; + uint32_t param[]; +}; + +struct mtp_string { + uint8_t len; + uint16_t string[255]; +}; + +struct mtp_device_info { + uint16_t StandardVersion; + uint32_t VendorExtensionID; + uint16_t VendorExtensionVersion; + uint8_t VendorExtensionDesc_len; + uint16_t VendorExtensionDesc[255]; + uint16_t FunctionalMode; + uint32_t OperationsSupported_len; + uint16_t OperationsSupported[255]; + uint32_t EventsSupported_len; + uint16_t EventsSupported[255]; + uint32_t DevicePropertiesSupported_len; + uint16_t DevicePropertiesSupported[255]; + uint32_t CaptureFormats_len; + uint16_t CaptureFormats[255]; + uint32_t ImageFormats_len; + uint16_t ImageFormats[255]; + uint8_t Manufacturer_len; + uint16_t Manufacturer[255]; + uint8_t Model_len; + uint16_t Model[255]; + uint8_t DeviceVersion_len; + uint16_t DeviceVersion[255]; + uint8_t SerialNumber_len; + uint16_t SerialNumber[255]; +} __PACKED; + +struct mtp_object_props_support { + uint32_t ObjectPropCode_len; + uint16_t ObjectPropCode[255]; +} __PACKED; + +struct mtp_device_prop_desc { + uint16_t DevicePropertyCode; + uint16_t DataType; + uint8_t GetSet; + uint16_t DefaultValue[1]; + uint16_t CurrentValue[1]; + uint8_t FormFlag; +} __PACKED; + +struct mtp_storage_id { + uint32_t StorageIDS_len; + uint32_t StorageIDS[255]; +} __PACKED; + +struct mtp_storage_info { + uint16_t StorageType; + uint16_t FilesystemType; + uint16_t AccessCapability; + uint64_t MaxCapability; + uint64_t FreeSpaceInBytes; + uint32_t FreeSpaceInObjects; + uint8_t StorageDescription_len; + uint8_t StorageDescription[255]; + uint8_t VolumeIdentifier_len; + uint8_t VolumeIdentifier[255]; +} __PACKED; + +struct mtp_object_handles { + uint32_t ObjectHandle_len; + uint32_t ObjectHandle[255]; +} __PACKED; + +struct mtp_object_prop_desc { + uint16_t ObjectPropertyCode; + uint16_t DataType; + uint8_t GetSet; + uint8_t DefValue[16]; + uint32_t GroupCode; + uint8_t FormFlag; +} __PACKED; + +struct mtp_object_prop_element { + uint32_t ObjectHandle; + uint16_t PropertyCode; + uint16_t Datatype; + uint8_t value[8]; +} __PACKED; + +struct mtp_object_prop_list { + uint32_t element_len; + struct mtp_object_prop_element element[1]; +} __PACKED; + +struct mtp_object_info { + uint32_t StorageId; + uint16_t ObjectFormat; + uint16_t ProtectionStatus; + uint32_t ObjectCompressedSize; + uint16_t ThumbFormat; + uint32_t ThumbCompressedSize; + uint32_t ThumbPixWidth; + uint32_t ThumbPixHeight; + uint32_t ImagePixWidth; + uint32_t ImagePixHeight; + uint32_t ImageBitDepth; + uint32_t ParentObject; + uint16_t AssociationType; + uint32_t AssociationDesc; + uint32_t SequenceNumber; + uint8_t Filename_len; + uint16_t Filename[CONFIG_USBDEV_MTP_MAX_PATHNAME]; + uint8_t CaptureDate[6]; + uint8_t ModificationDate[6]; +} __PACKED; + +struct mtp_object { + uint32_t storage_id; + uint32_t handle; + uint32_t parent_handle; + uint16_t format; + bool is_dir; + bool is_readonly; + bool is_hidden; + uint32_t file_size; + uint32_t file_full_name_length; + char file_full_name[CONFIG_USBDEV_MTP_MAX_PATHNAME]; + bool in_use; +}; + +/*Length of template descriptor: 30 bytes*/ +#define MTP_DESCRIPTOR_LEN (9 + 7 + 7 + 7) + +// clang-format off +#define MTP_DESCRIPTOR_INIT(bFirstInterface, out_ep, in_ep, int_ep, wMaxPacketSize, str_idx) \ + /* Interface */ \ + 0x09, /* bLength */ \ + USB_DESCRIPTOR_TYPE_INTERFACE, /* bDescriptorType */ \ + bFirstInterface, /* bInterfaceNumber */ \ + 0x00, /* bAlternateSetting */ \ + 0x03, /* bNumEndpoints */ \ + USB_DEVICE_CLASS_IMAGE, /* bInterfaceClass */ \ + USB_MTP_SUB_CLASS, /* bInterfaceSubClass */ \ + USB_MTP_PROTOCOL, /* bInterfaceProtocol */ \ + str_idx, /* iInterface */ \ + 0x07, /* bLength */ \ + USB_DESCRIPTOR_TYPE_ENDPOINT, /* bDescriptorType */ \ + out_ep, /* bEndpointAddress */ \ + 0x02, /* bmAttributes */ \ + WBVAL(wMaxPacketSize), /* wMaxPacketSize */ \ + 0x00, /* bInterval */ \ + 0x07, /* bLength */ \ + USB_DESCRIPTOR_TYPE_ENDPOINT, /* bDescriptorType */ \ + in_ep, /* bEndpointAddress */ \ + 0x02, /* bmAttributes */ \ + WBVAL(wMaxPacketSize), /* wMaxPacketSize */ \ + 0x00, /* bInterval */ \ + 0x07, /* bLength */ \ + USB_DESCRIPTOR_TYPE_ENDPOINT, /* bDescriptorType */ \ + int_ep, /* bEndpointAddress */ \ + 0x03, /* bmAttributes */ \ + WBVAL(0x1c), /* wMaxPacketSize */ \ + 0x06 /* bInterval */ +// clang-format on + +#endif \ No newline at end of file diff --git a/kernel/cherryusb/class/mtp/usbd_mtp.h b/kernel/cherryusb/class/mtp/usbd_mtp.h new file mode 100644 index 0000000..b7c9aa4 --- /dev/null +++ b/kernel/cherryusb/class/mtp/usbd_mtp.h @@ -0,0 +1,65 @@ +/* + * Copyright (c) 2025, sakumisu + * + * SPDX-License-Identifier: Apache-2.0 + */ +#ifndef USBD_MTP_H +#define USBD_MTP_H + +#include "usb_mtp.h" +#include +#include + +/* gcc toolchain does not implement dirent.h, so we define our own MTP_DIR and mtp_dirent */ + +typedef void MTP_DIR; + +struct mtp_statfs { + size_t f_bsize; /* block size */ + size_t f_blocks; /* total data blocks in file system */ + size_t f_bfree; /* free blocks in file system */ +}; + +struct mtp_dirent { + uint8_t d_type; /* The type of the file */ + uint8_t d_namlen; /* The length of the not including the terminating null file name */ + uint16_t d_reclen; /* length of this record */ + char d_name[CONFIG_USBDEV_MTP_MAX_PATHNAME]; /* The null-terminated file name */ +}; + +#ifdef __cplusplus +extern "C" { +#endif + +struct usbd_interface *usbd_mtp_init_intf(struct usbd_interface *intf, + const uint8_t out_ep, + const uint8_t in_ep, + const uint8_t int_ep); + +int usbd_mtp_notify_object_add(const char *path); +int usbd_mtp_notify_object_remove(const char *path); + +const char *usbd_mtp_fs_root_path(void); +const char *usbd_mtp_fs_description(void); + +int usbd_mtp_mkdir(const char *path); +int usbd_mtp_rmdir(const char *path); +MTP_DIR *usbd_mtp_opendir(const char *name); +int usbd_mtp_closedir(MTP_DIR *d); +struct mtp_dirent *usbd_mtp_readdir(MTP_DIR *d); + +int usbd_mtp_statfs(const char *path, struct mtp_statfs *buf); +int usbd_mtp_stat(const char *file, struct stat *buf); + +int usbd_mtp_open(const char *path, uint8_t mode); +int usbd_mtp_close(int fd); +int usbd_mtp_read(int fd, void *buf, size_t len); +int usbd_mtp_write(int fd, const void *buf, size_t len); + +int usbd_mtp_unlink(const char *path); + +#ifdef __cplusplus +} +#endif + +#endif /* USBD_MTP_H */ diff --git a/kernel/cherryusb/class/mtp/usbd_mtp_support.h b/kernel/cherryusb/class/mtp/usbd_mtp_support.h new file mode 100644 index 0000000..9281ec3 --- /dev/null +++ b/kernel/cherryusb/class/mtp/usbd_mtp_support.h @@ -0,0 +1,312 @@ +/* + * Copyright (c) 2025, sakumisu + * + * SPDX-License-Identifier: Apache-2.0 + */ +#ifndef USBD_MTP_SUPPORT_H +#define USBD_MTP_SUPPORT_H + +#define MTP_VERSION 100 + +typedef struct _profile_property { + uint16_t prop_code; + uint16_t data_type; + uint8_t getset; + uint64_t default_value; + uint32_t group_code; + uint8_t form_flag; + uint16_t format_code; +} profile_property; + +typedef struct _format_property { + uint16_t format_code; + uint16_t *properties; +} formats_property; + +const char mtp_extension_string[] = "microsoft.com: 1.0; android.com: 1.0;"; + +const uint16_t supported_op[] = { + MTP_OPERATION_GET_DEVICE_INFO, //0x1001 + MTP_OPERATION_OPEN_SESSION, //0x1002 + MTP_OPERATION_CLOSE_SESSION, //0x1003 + MTP_OPERATION_GET_STORAGE_IDS, //0x1004 + MTP_OPERATION_GET_STORAGE_INFO, //0x1005 + //MTP_OPERATION_GET_NUM_OBJECTS ,//0x1006 + MTP_OPERATION_GET_OBJECT_HANDLES, //0x1007 + MTP_OPERATION_GET_OBJECT_INFO, //0x1008 + MTP_OPERATION_GET_OBJECT, //0x1009 + //MTP_OPERATION_GET_THUMB ,//0x100A + MTP_OPERATION_DELETE_OBJECT, //0x100B + MTP_OPERATION_SEND_OBJECT_INFO, //0x100C + MTP_OPERATION_SEND_OBJECT, //0x100D + MTP_OPERATION_GET_DEVICE_PROP_DESC, //0x1014 + // MTP_OPERATION_GET_DEVICE_PROP_VALUE ,//0x1015 + // MTP_OPERATION_SET_DEVICE_PROP_VALUE ,//0x1016 + //MTP_OPERATION_RESET_DEVICE_PROP_VALUE ,//0x1017 + // MTP_OPERATION_GET_PARTIAL_OBJECT ,//0x101B + MTP_OPERATION_GET_OBJECT_PROPS_SUPPORTED, //0x9801 + // MTP_OPERATION_GET_OBJECT_PROP_DESC, //0x9802 + // MTP_OPERATION_GET_OBJECT_PROP_VALUE ,//0x9803 + // MTP_OPERATION_SET_OBJECT_PROP_VALUE ,//0x9804 + // MTP_OPERATION_GET_OBJECT_PROP_LIST ,//0x9805 + //MTP_OPERATION_GET_OBJECT_REFERENCES ,//0x9810 + //MTP_OPERATION_SET_OBJECT_REFERENCES ,//0x9811 + // MTP_OPERATION_GET_PARTIAL_OBJECT_64 ,//0x95C1 + // MTP_OPERATION_SEND_PARTIAL_OBJECT ,//0x95C2 + // MTP_OPERATION_TRUNCATE_OBJECT ,//0x95C3 + // MTP_OPERATION_BEGIN_EDIT_OBJECT ,//0x95C4 + // MTP_OPERATION_END_EDIT_OBJECT //0x95C5 +}; + +int supported_op_size = sizeof(supported_op); + +const uint16_t supported_event[] = { + MTP_EVENT_OBJECT_ADDED, // 0x4002 + MTP_EVENT_OBJECT_REMOVED, // 0x4003 + MTP_EVENT_STORE_ADDED, // 0x4004 + MTP_EVENT_STORE_REMOVED, // 0x4005 + MTP_EVENT_STORAGE_INFO_CHANGED, // 0x400C + MTP_EVENT_OBJECT_INFO_CHANGED, // 0x4007 + MTP_EVENT_DEVICE_PROP_CHANGED, // 0x4006 + MTP_EVENT_OBJECT_PROP_CHANGED // 0xC801 +}; + +int supported_event_size = sizeof(supported_event); + +const formats_property support_format_properties[] = { + // format code prop code + { MTP_FORMAT_UNDEFINED, (uint16_t[]){ MTP_PROPERTY_STORAGE_ID, MTP_PROPERTY_OBJECT_FORMAT, MTP_PROPERTY_PROTECTION_STATUS, MTP_PROPERTY_OBJECT_SIZE, + MTP_PROPERTY_OBJECT_FILE_NAME, MTP_PROPERTY_DATE_MODIFIED, MTP_PROPERTY_PARENT_OBJECT, MTP_PROPERTY_PERSISTENT_UID, + MTP_PROPERTY_NAME, MTP_PROPERTY_DISPLAY_NAME, MTP_PROPERTY_DATE_CREATED, + 0xFFFF } }, + { MTP_FORMAT_ASSOCIATION, (uint16_t[]){ MTP_PROPERTY_STORAGE_ID, MTP_PROPERTY_OBJECT_FORMAT, MTP_PROPERTY_PROTECTION_STATUS, MTP_PROPERTY_OBJECT_SIZE, + MTP_PROPERTY_OBJECT_FILE_NAME, MTP_PROPERTY_DATE_MODIFIED, MTP_PROPERTY_PARENT_OBJECT, MTP_PROPERTY_PERSISTENT_UID, + MTP_PROPERTY_NAME, MTP_PROPERTY_DISPLAY_NAME, MTP_PROPERTY_DATE_CREATED, + 0xFFFF } } +#if 0 + { MTP_FORMAT_TEXT , (uint16_t[]){ MTP_PROPERTY_STORAGE_ID, MTP_PROPERTY_OBJECT_FORMAT, MTP_PROPERTY_PROTECTION_STATUS, MTP_PROPERTY_OBJECT_SIZE, + MTP_PROPERTY_OBJECT_FILE_NAME, MTP_PROPERTY_DATE_MODIFIED, MTP_PROPERTY_PARENT_OBJECT, MTP_PROPERTY_PERSISTENT_UID, + MTP_PROPERTY_NAME, MTP_PROPERTY_DISPLAY_NAME, MTP_PROPERTY_DATE_CREATED, + 0xFFFF} + }, + { MTP_FORMAT_HTML , (uint16_t[]){ MTP_PROPERTY_STORAGE_ID, MTP_PROPERTY_OBJECT_FORMAT, MTP_PROPERTY_PROTECTION_STATUS, MTP_PROPERTY_OBJECT_SIZE, + MTP_PROPERTY_OBJECT_FILE_NAME, MTP_PROPERTY_DATE_MODIFIED, MTP_PROPERTY_PARENT_OBJECT, MTP_PROPERTY_PERSISTENT_UID, + MTP_PROPERTY_NAME, MTP_PROPERTY_DISPLAY_NAME, MTP_PROPERTY_DATE_CREATED, + 0xFFFF} + }, + { MTP_FORMAT_MP4_CONTAINER, (uint16_t[]){ MTP_PROPERTY_STORAGE_ID, MTP_PROPERTY_OBJECT_FORMAT, MTP_PROPERTY_PROTECTION_STATUS, MTP_PROPERTY_OBJECT_SIZE, + MTP_PROPERTY_OBJECT_FILE_NAME, MTP_PROPERTY_DATE_MODIFIED, MTP_PROPERTY_PARENT_OBJECT, MTP_PROPERTY_PERSISTENT_UID, + MTP_PROPERTY_NAME, MTP_PROPERTY_DISPLAY_NAME, MTP_PROPERTY_DATE_CREATED, MTP_PROPERTY_ARTIST, MTP_PROPERTY_ALBUM_NAME, + MTP_PROPERTY_DURATION, MTP_PROPERTY_DESCRIPTION, MTP_PROPERTY_WIDTH, MTP_PROPERTY_HEIGHT, MTP_PROPERTY_DATE_AUTHORED, + 0xFFFF} + }, + { MTP_FORMAT_3GP_CONTAINER, (uint16_t[]){ MTP_PROPERTY_STORAGE_ID, MTP_PROPERTY_OBJECT_FORMAT, MTP_PROPERTY_PROTECTION_STATUS, MTP_PROPERTY_OBJECT_SIZE, + MTP_PROPERTY_OBJECT_FILE_NAME, MTP_PROPERTY_DATE_MODIFIED, MTP_PROPERTY_PARENT_OBJECT, MTP_PROPERTY_PERSISTENT_UID, + MTP_PROPERTY_NAME, MTP_PROPERTY_DISPLAY_NAME, MTP_PROPERTY_DATE_CREATED, MTP_PROPERTY_ARTIST, MTP_PROPERTY_ALBUM_NAME, + MTP_PROPERTY_DURATION, MTP_PROPERTY_DESCRIPTION, MTP_PROPERTY_WIDTH, MTP_PROPERTY_HEIGHT, MTP_PROPERTY_DATE_AUTHORED, + 0xFFFF} + }, + { MTP_FORMAT_WAV , (uint16_t[]){ MTP_PROPERTY_STORAGE_ID, MTP_PROPERTY_OBJECT_FORMAT, MTP_PROPERTY_PROTECTION_STATUS, MTP_PROPERTY_OBJECT_SIZE, + MTP_PROPERTY_OBJECT_FILE_NAME, MTP_PROPERTY_DATE_MODIFIED, MTP_PROPERTY_PARENT_OBJECT, MTP_PROPERTY_PERSISTENT_UID, + MTP_PROPERTY_NAME, MTP_PROPERTY_DISPLAY_NAME, MTP_PROPERTY_DATE_CREATED,MTP_PROPERTY_ARTIST,MTP_PROPERTY_ALBUM_NAME, + MTP_PROPERTY_ALBUM_ARTIST, MTP_PROPERTY_TRACK, MTP_PROPERTY_ORIGINAL_RELEASE_DATE, MTP_PROPERTY_GENRE, MTP_PROPERTY_COMPOSER, + MTP_PROPERTY_AUDIO_WAVE_CODEC, MTP_PROPERTY_BITRATE_TYPE, MTP_PROPERTY_AUDIO_BITRATE, MTP_PROPERTY_NUMBER_OF_CHANNELS,MTP_PROPERTY_SAMPLE_RATE, + 0xFFFF} + }, + { MTP_FORMAT_MP3 , (uint16_t[]){ MTP_PROPERTY_STORAGE_ID, MTP_PROPERTY_OBJECT_FORMAT, MTP_PROPERTY_PROTECTION_STATUS, MTP_PROPERTY_OBJECT_SIZE, + MTP_PROPERTY_OBJECT_FILE_NAME, MTP_PROPERTY_DATE_MODIFIED, MTP_PROPERTY_PARENT_OBJECT, MTP_PROPERTY_PERSISTENT_UID, + MTP_PROPERTY_NAME, MTP_PROPERTY_DISPLAY_NAME, MTP_PROPERTY_DATE_CREATED,MTP_PROPERTY_ARTIST,MTP_PROPERTY_ALBUM_NAME, + MTP_PROPERTY_ALBUM_ARTIST, MTP_PROPERTY_TRACK, MTP_PROPERTY_ORIGINAL_RELEASE_DATE, MTP_PROPERTY_GENRE, MTP_PROPERTY_COMPOSER, + MTP_PROPERTY_AUDIO_WAVE_CODEC, MTP_PROPERTY_BITRATE_TYPE, MTP_PROPERTY_AUDIO_BITRATE, MTP_PROPERTY_NUMBER_OF_CHANNELS,MTP_PROPERTY_SAMPLE_RATE, + 0xFFFF} + }, + { MTP_FORMAT_MPEG , (uint16_t[]){ MTP_PROPERTY_STORAGE_ID, MTP_PROPERTY_OBJECT_FORMAT, MTP_PROPERTY_PROTECTION_STATUS, MTP_PROPERTY_OBJECT_SIZE, + MTP_PROPERTY_OBJECT_FILE_NAME, MTP_PROPERTY_DATE_MODIFIED, MTP_PROPERTY_PARENT_OBJECT, MTP_PROPERTY_PERSISTENT_UID, + MTP_PROPERTY_NAME, MTP_PROPERTY_DISPLAY_NAME, MTP_PROPERTY_DATE_CREATED, MTP_PROPERTY_ARTIST, MTP_PROPERTY_ALBUM_NAME, + MTP_PROPERTY_DURATION, MTP_PROPERTY_DESCRIPTION, MTP_PROPERTY_WIDTH, MTP_PROPERTY_HEIGHT, MTP_PROPERTY_DATE_AUTHORED, + 0xFFFF} + }, + { MTP_FORMAT_EXIF_JPEG , (uint16_t[]){ MTP_PROPERTY_STORAGE_ID, MTP_PROPERTY_OBJECT_FORMAT, MTP_PROPERTY_PROTECTION_STATUS, MTP_PROPERTY_OBJECT_SIZE, + MTP_PROPERTY_OBJECT_FILE_NAME, MTP_PROPERTY_DATE_MODIFIED, MTP_PROPERTY_PARENT_OBJECT, MTP_PROPERTY_PERSISTENT_UID, + MTP_PROPERTY_NAME, MTP_PROPERTY_DISPLAY_NAME, MTP_PROPERTY_DATE_CREATED, MTP_PROPERTY_DESCRIPTION, MTP_PROPERTY_WIDTH, + MTP_PROPERTY_HEIGHT, MTP_PROPERTY_DATE_AUTHORED, + 0xFFFF} + }, + { MTP_FORMAT_BMP , (uint16_t[]){ MTP_PROPERTY_STORAGE_ID, MTP_PROPERTY_OBJECT_FORMAT, MTP_PROPERTY_PROTECTION_STATUS, MTP_PROPERTY_OBJECT_SIZE, + MTP_PROPERTY_OBJECT_FILE_NAME, MTP_PROPERTY_DATE_MODIFIED, MTP_PROPERTY_PARENT_OBJECT, MTP_PROPERTY_PERSISTENT_UID, + MTP_PROPERTY_NAME, MTP_PROPERTY_DISPLAY_NAME, MTP_PROPERTY_DATE_CREATED, MTP_PROPERTY_DESCRIPTION, MTP_PROPERTY_WIDTH, + MTP_PROPERTY_HEIGHT, MTP_PROPERTY_DATE_AUTHORED, + 0xFFFF} + }, + { MTP_FORMAT_GIF , (uint16_t[]){ MTP_PROPERTY_STORAGE_ID, MTP_PROPERTY_OBJECT_FORMAT, MTP_PROPERTY_PROTECTION_STATUS, MTP_PROPERTY_OBJECT_SIZE, + MTP_PROPERTY_OBJECT_FILE_NAME, MTP_PROPERTY_DATE_MODIFIED, MTP_PROPERTY_PARENT_OBJECT, MTP_PROPERTY_PERSISTENT_UID, + MTP_PROPERTY_NAME, MTP_PROPERTY_DISPLAY_NAME, MTP_PROPERTY_DATE_CREATED, MTP_PROPERTY_DESCRIPTION, MTP_PROPERTY_WIDTH, + MTP_PROPERTY_HEIGHT, MTP_PROPERTY_DATE_AUTHORED, + 0xFFFF} + }, + { MTP_FORMAT_JFIF , (uint16_t[]){ MTP_PROPERTY_STORAGE_ID, MTP_PROPERTY_OBJECT_FORMAT, MTP_PROPERTY_PROTECTION_STATUS, MTP_PROPERTY_OBJECT_SIZE, + MTP_PROPERTY_OBJECT_FILE_NAME, MTP_PROPERTY_DATE_MODIFIED, MTP_PROPERTY_PARENT_OBJECT, MTP_PROPERTY_PERSISTENT_UID, + MTP_PROPERTY_NAME, MTP_PROPERTY_DISPLAY_NAME, MTP_PROPERTY_DATE_CREATED, MTP_PROPERTY_DESCRIPTION, MTP_PROPERTY_WIDTH, + MTP_PROPERTY_HEIGHT, MTP_PROPERTY_DATE_AUTHORED, + 0xFFFF} + }, + { MTP_FORMAT_WMA , (uint16_t[]){ MTP_PROPERTY_STORAGE_ID, MTP_PROPERTY_OBJECT_FORMAT, MTP_PROPERTY_PROTECTION_STATUS, MTP_PROPERTY_OBJECT_SIZE, + MTP_PROPERTY_OBJECT_FILE_NAME, MTP_PROPERTY_DATE_MODIFIED, MTP_PROPERTY_PARENT_OBJECT, MTP_PROPERTY_PERSISTENT_UID, + MTP_PROPERTY_NAME, MTP_PROPERTY_DISPLAY_NAME, MTP_PROPERTY_DATE_CREATED, MTP_PROPERTY_ARTIST, MTP_PROPERTY_ALBUM_NAME, + MTP_PROPERTY_ALBUM_ARTIST, MTP_PROPERTY_TRACK, MTP_PROPERTY_ORIGINAL_RELEASE_DATE, MTP_PROPERTY_DURATION, MTP_PROPERTY_DESCRIPTION, + MTP_PROPERTY_GENRE, MTP_PROPERTY_COMPOSER, MTP_PROPERTY_AUDIO_WAVE_CODEC, MTP_PROPERTY_BITRATE_TYPE, MTP_PROPERTY_AUDIO_BITRATE, + MTP_PROPERTY_NUMBER_OF_CHANNELS, MTP_PROPERTY_SAMPLE_RATE, + 0xFFFF} + }, + { MTP_FORMAT_OGG , (uint16_t[]){ MTP_PROPERTY_STORAGE_ID, MTP_PROPERTY_OBJECT_FORMAT, MTP_PROPERTY_PROTECTION_STATUS, MTP_PROPERTY_OBJECT_SIZE, + MTP_PROPERTY_OBJECT_FILE_NAME, MTP_PROPERTY_DATE_MODIFIED, MTP_PROPERTY_PARENT_OBJECT, MTP_PROPERTY_PERSISTENT_UID, + MTP_PROPERTY_NAME, MTP_PROPERTY_DISPLAY_NAME, MTP_PROPERTY_DATE_CREATED, MTP_PROPERTY_ARTIST, MTP_PROPERTY_ALBUM_NAME, + MTP_PROPERTY_ALBUM_ARTIST, MTP_PROPERTY_TRACK, MTP_PROPERTY_ORIGINAL_RELEASE_DATE, MTP_PROPERTY_DURATION, MTP_PROPERTY_DESCRIPTION, + MTP_PROPERTY_GENRE, MTP_PROPERTY_COMPOSER, MTP_PROPERTY_AUDIO_WAVE_CODEC, MTP_PROPERTY_BITRATE_TYPE, MTP_PROPERTY_AUDIO_BITRATE, + MTP_PROPERTY_NUMBER_OF_CHANNELS, MTP_PROPERTY_SAMPLE_RATE, + 0xFFFF} + }, + { MTP_FORMAT_AAC , (uint16_t[]){ MTP_PROPERTY_STORAGE_ID, MTP_PROPERTY_OBJECT_FORMAT, MTP_PROPERTY_PROTECTION_STATUS, MTP_PROPERTY_OBJECT_SIZE, + MTP_PROPERTY_OBJECT_FILE_NAME, MTP_PROPERTY_DATE_MODIFIED, MTP_PROPERTY_PARENT_OBJECT, MTP_PROPERTY_PERSISTENT_UID, + MTP_PROPERTY_NAME, MTP_PROPERTY_DISPLAY_NAME, MTP_PROPERTY_DATE_CREATED, MTP_PROPERTY_ARTIST, MTP_PROPERTY_ALBUM_NAME, + MTP_PROPERTY_ALBUM_ARTIST, MTP_PROPERTY_TRACK, MTP_PROPERTY_ORIGINAL_RELEASE_DATE, MTP_PROPERTY_DURATION, MTP_PROPERTY_DESCRIPTION, + MTP_PROPERTY_GENRE, MTP_PROPERTY_COMPOSER, MTP_PROPERTY_AUDIO_WAVE_CODEC, MTP_PROPERTY_BITRATE_TYPE, MTP_PROPERTY_AUDIO_BITRATE, + MTP_PROPERTY_NUMBER_OF_CHANNELS, MTP_PROPERTY_SAMPLE_RATE, + 0xFFFF} + }, + { MTP_FORMAT_ABSTRACT_AV_PLAYLIST, (uint16_t[]){ MTP_PROPERTY_STORAGE_ID, MTP_PROPERTY_OBJECT_FORMAT, MTP_PROPERTY_PROTECTION_STATUS, MTP_PROPERTY_OBJECT_SIZE, + MTP_PROPERTY_OBJECT_FILE_NAME, MTP_PROPERTY_DATE_MODIFIED, MTP_PROPERTY_PARENT_OBJECT, MTP_PROPERTY_PERSISTENT_UID, + MTP_PROPERTY_NAME, MTP_PROPERTY_DISPLAY_NAME, MTP_PROPERTY_DATE_CREATED, + 0xFFFF} + }, + { MTP_FORMAT_WPL_PLAYLIST, (uint16_t[]){ MTP_PROPERTY_STORAGE_ID, MTP_PROPERTY_OBJECT_FORMAT, MTP_PROPERTY_PROTECTION_STATUS, MTP_PROPERTY_OBJECT_SIZE, + MTP_PROPERTY_OBJECT_FILE_NAME, MTP_PROPERTY_DATE_MODIFIED, MTP_PROPERTY_PARENT_OBJECT, MTP_PROPERTY_PERSISTENT_UID, + MTP_PROPERTY_NAME, MTP_PROPERTY_DISPLAY_NAME, MTP_PROPERTY_DATE_CREATED, + 0xFFFF} + }, + { MTP_FORMAT_M3U_PLAYLIST, (uint16_t[]){ MTP_PROPERTY_STORAGE_ID, MTP_PROPERTY_OBJECT_FORMAT, MTP_PROPERTY_PROTECTION_STATUS, MTP_PROPERTY_OBJECT_SIZE, + MTP_PROPERTY_OBJECT_FILE_NAME, MTP_PROPERTY_DATE_MODIFIED, MTP_PROPERTY_PARENT_OBJECT, MTP_PROPERTY_PERSISTENT_UID, + MTP_PROPERTY_NAME, MTP_PROPERTY_DISPLAY_NAME, MTP_PROPERTY_DATE_CREATED, + 0xFFFF} + }, + { MTP_FORMAT_PLS_PLAYLIST, (uint16_t[]){ MTP_PROPERTY_STORAGE_ID, MTP_PROPERTY_OBJECT_FORMAT, MTP_PROPERTY_PROTECTION_STATUS, MTP_PROPERTY_OBJECT_SIZE, + MTP_PROPERTY_OBJECT_FILE_NAME, MTP_PROPERTY_DATE_MODIFIED, MTP_PROPERTY_PARENT_OBJECT, MTP_PROPERTY_PERSISTENT_UID, + MTP_PROPERTY_NAME, MTP_PROPERTY_DISPLAY_NAME, MTP_PROPERTY_DATE_CREATED, + 0xFFFF} + }, + { MTP_FORMAT_XML_DOCUMENT, (uint16_t[]){ MTP_PROPERTY_STORAGE_ID, MTP_PROPERTY_OBJECT_FORMAT, MTP_PROPERTY_PROTECTION_STATUS, MTP_PROPERTY_OBJECT_SIZE, + MTP_PROPERTY_OBJECT_FILE_NAME, MTP_PROPERTY_DATE_MODIFIED, MTP_PROPERTY_PARENT_OBJECT, MTP_PROPERTY_PERSISTENT_UID, + MTP_PROPERTY_NAME, MTP_PROPERTY_DISPLAY_NAME, MTP_PROPERTY_DATE_CREATED, + 0xFFFF} + }, + { MTP_FORMAT_FLAC , (uint16_t[]){ MTP_PROPERTY_STORAGE_ID, MTP_PROPERTY_OBJECT_FORMAT, MTP_PROPERTY_PROTECTION_STATUS, MTP_PROPERTY_OBJECT_SIZE, + MTP_PROPERTY_OBJECT_FILE_NAME, MTP_PROPERTY_DATE_MODIFIED, MTP_PROPERTY_PARENT_OBJECT, MTP_PROPERTY_PERSISTENT_UID, + MTP_PROPERTY_NAME, MTP_PROPERTY_DISPLAY_NAME, MTP_PROPERTY_DATE_CREATED, + 0xFFFF} + }, + { MTP_FORMAT_AVI , (uint16_t[]){ MTP_PROPERTY_STORAGE_ID, MTP_PROPERTY_OBJECT_FORMAT, MTP_PROPERTY_PROTECTION_STATUS, MTP_PROPERTY_OBJECT_SIZE, + MTP_PROPERTY_OBJECT_FILE_NAME, MTP_PROPERTY_DATE_MODIFIED, MTP_PROPERTY_PARENT_OBJECT, MTP_PROPERTY_PERSISTENT_UID, + MTP_PROPERTY_NAME, MTP_PROPERTY_DISPLAY_NAME, MTP_PROPERTY_DATE_CREATED, MTP_PROPERTY_ARTIST, MTP_PROPERTY_ALBUM_NAME, + MTP_PROPERTY_DURATION, MTP_PROPERTY_DESCRIPTION, MTP_PROPERTY_WIDTH, MTP_PROPERTY_HEIGHT, MTP_PROPERTY_DATE_AUTHORED, + 0xFFFF} + }, + { MTP_FORMAT_ASF , (uint16_t[]){ MTP_PROPERTY_STORAGE_ID, MTP_PROPERTY_OBJECT_FORMAT, MTP_PROPERTY_PROTECTION_STATUS, MTP_PROPERTY_OBJECT_SIZE, + MTP_PROPERTY_OBJECT_FILE_NAME, MTP_PROPERTY_DATE_MODIFIED, MTP_PROPERTY_PARENT_OBJECT, MTP_PROPERTY_PERSISTENT_UID, + MTP_PROPERTY_NAME, MTP_PROPERTY_DISPLAY_NAME, MTP_PROPERTY_DATE_CREATED, MTP_PROPERTY_ARTIST, MTP_PROPERTY_ALBUM_NAME, + MTP_PROPERTY_DURATION, MTP_PROPERTY_DESCRIPTION, MTP_PROPERTY_WIDTH, MTP_PROPERTY_HEIGHT, MTP_PROPERTY_DATE_AUTHORED, + 0xFFFF} + }, + { MTP_FORMAT_MS_WORD_DOCUMENT, (uint16_t[]){ MTP_PROPERTY_STORAGE_ID, MTP_PROPERTY_OBJECT_FORMAT, MTP_PROPERTY_PROTECTION_STATUS, MTP_PROPERTY_OBJECT_SIZE, + MTP_PROPERTY_OBJECT_FILE_NAME, MTP_PROPERTY_DATE_MODIFIED, MTP_PROPERTY_PARENT_OBJECT, MTP_PROPERTY_PERSISTENT_UID, + MTP_PROPERTY_NAME, MTP_PROPERTY_DISPLAY_NAME, MTP_PROPERTY_DATE_CREATED, + 0xFFFF} + }, + { MTP_FORMAT_MS_EXCEL_SPREADSHEET, (uint16_t[]){ MTP_PROPERTY_STORAGE_ID, MTP_PROPERTY_OBJECT_FORMAT, MTP_PROPERTY_PROTECTION_STATUS, MTP_PROPERTY_OBJECT_SIZE, + MTP_PROPERTY_OBJECT_FILE_NAME, MTP_PROPERTY_DATE_MODIFIED, MTP_PROPERTY_PARENT_OBJECT, MTP_PROPERTY_PERSISTENT_UID, + MTP_PROPERTY_NAME, MTP_PROPERTY_DISPLAY_NAME, MTP_PROPERTY_DATE_CREATED, + 0xFFFF} + }, + { MTP_FORMAT_MS_POWERPOINT_PRESENTATION, (uint16_t[]){ MTP_PROPERTY_STORAGE_ID, MTP_PROPERTY_OBJECT_FORMAT, MTP_PROPERTY_PROTECTION_STATUS, MTP_PROPERTY_OBJECT_SIZE, + MTP_PROPERTY_OBJECT_FILE_NAME, MTP_PROPERTY_DATE_MODIFIED, MTP_PROPERTY_PARENT_OBJECT, MTP_PROPERTY_PERSISTENT_UID, + MTP_PROPERTY_NAME, MTP_PROPERTY_DISPLAY_NAME, MTP_PROPERTY_DATE_CREATED, + 0xFFFF} + } +#endif + , + + { 0xFFFF, (uint16_t[]){ 0xFFFF } } + +}; + +const profile_property support_object_properties[] = { + // prop_code data_type getset default_value group_code form_flag format_code + { MTP_PROPERTY_STORAGE_ID, MTP_TYPE_UINT32, 0x00, 0x00000000, 0x000000001, 0x00, 0xFFFF }, + { MTP_PROPERTY_OBJECT_FORMAT, MTP_TYPE_UINT16, 0x00, MTP_FORMAT_UNDEFINED, 0x000000000, 0x00, MTP_FORMAT_UNDEFINED }, + { MTP_PROPERTY_OBJECT_FORMAT, MTP_TYPE_UINT16, 0x00, MTP_FORMAT_ASSOCIATION, 0x000000000, 0x00, MTP_FORMAT_ASSOCIATION }, + { MTP_PROPERTY_OBJECT_FORMAT, MTP_TYPE_UINT16, 0x00, MTP_FORMAT_TEXT, 0x000000000, 0x00, MTP_FORMAT_TEXT }, + { MTP_PROPERTY_OBJECT_FORMAT, MTP_TYPE_UINT16, 0x00, MTP_FORMAT_HTML, 0x000000000, 0x00, MTP_FORMAT_HTML }, + { MTP_PROPERTY_OBJECT_FORMAT, MTP_TYPE_UINT16, 0x00, MTP_FORMAT_WAV, 0x000000000, 0x00, MTP_FORMAT_WAV }, + { MTP_PROPERTY_OBJECT_FORMAT, MTP_TYPE_UINT16, 0x00, MTP_FORMAT_MP3, 0x000000000, 0x00, MTP_FORMAT_MP3 }, + { MTP_PROPERTY_OBJECT_FORMAT, MTP_TYPE_UINT16, 0x00, MTP_FORMAT_MPEG, 0x000000000, 0x00, MTP_FORMAT_MPEG }, + { MTP_PROPERTY_OBJECT_FORMAT, MTP_TYPE_UINT16, 0x00, MTP_FORMAT_EXIF_JPEG, 0x000000000, 0x00, MTP_FORMAT_EXIF_JPEG }, + { MTP_PROPERTY_OBJECT_FORMAT, MTP_TYPE_UINT16, 0x00, MTP_FORMAT_BMP, 0x000000000, 0x00, MTP_FORMAT_BMP }, + { MTP_PROPERTY_OBJECT_FORMAT, MTP_TYPE_UINT16, 0x00, MTP_FORMAT_AIFF, 0x000000000, 0x00, MTP_FORMAT_AIFF }, + { MTP_PROPERTY_OBJECT_FORMAT, MTP_TYPE_UINT16, 0x00, MTP_FORMAT_MPEG, 0x000000000, 0x00, MTP_FORMAT_MPEG }, + { MTP_PROPERTY_OBJECT_FORMAT, MTP_TYPE_UINT16, 0x00, MTP_FORMAT_WMA, 0x000000000, 0x00, MTP_FORMAT_WMA }, + { MTP_PROPERTY_OBJECT_FORMAT, MTP_TYPE_UINT16, 0x00, MTP_FORMAT_OGG, 0x000000000, 0x00, MTP_FORMAT_OGG }, + { MTP_PROPERTY_OBJECT_FORMAT, MTP_TYPE_UINT16, 0x00, MTP_FORMAT_AAC, 0x000000000, 0x00, MTP_FORMAT_AAC }, + { MTP_PROPERTY_OBJECT_FORMAT, MTP_TYPE_UINT16, 0x00, MTP_FORMAT_MP4_CONTAINER, 0x000000000, 0x00, MTP_FORMAT_MP4_CONTAINER }, + { MTP_PROPERTY_OBJECT_FORMAT, MTP_TYPE_UINT16, 0x00, MTP_FORMAT_3GP_CONTAINER, 0x000000000, 0x00, MTP_FORMAT_3GP_CONTAINER }, + { MTP_PROPERTY_OBJECT_FORMAT, MTP_TYPE_UINT16, 0x00, MTP_FORMAT_ABSTRACT_AV_PLAYLIST, 0x000000000, 0x00, MTP_FORMAT_ABSTRACT_AV_PLAYLIST }, + { MTP_PROPERTY_OBJECT_FORMAT, MTP_TYPE_UINT16, 0x00, MTP_FORMAT_WPL_PLAYLIST, 0x000000000, 0x00, MTP_FORMAT_WPL_PLAYLIST }, + { MTP_PROPERTY_OBJECT_FORMAT, MTP_TYPE_UINT16, 0x00, MTP_FORMAT_M3U_PLAYLIST, 0x000000000, 0x00, MTP_FORMAT_M3U_PLAYLIST }, + { MTP_PROPERTY_OBJECT_FORMAT, MTP_TYPE_UINT16, 0x00, MTP_FORMAT_PLS_PLAYLIST, 0x000000000, 0x00, MTP_FORMAT_PLS_PLAYLIST }, + { MTP_PROPERTY_OBJECT_FORMAT, MTP_TYPE_UINT16, 0x00, MTP_FORMAT_XML_DOCUMENT, 0x000000000, 0x00, MTP_FORMAT_XML_DOCUMENT }, + { MTP_PROPERTY_OBJECT_FORMAT, MTP_TYPE_UINT16, 0x00, MTP_FORMAT_FLAC, 0x000000000, 0x00, MTP_FORMAT_FLAC }, + { MTP_PROPERTY_OBJECT_FORMAT, MTP_TYPE_UINT16, 0x00, MTP_FORMAT_AVI, 0x000000000, 0x00, MTP_FORMAT_AVI }, + { MTP_PROPERTY_OBJECT_FORMAT, MTP_TYPE_UINT16, 0x00, MTP_FORMAT_ASF, 0x000000000, 0x00, MTP_FORMAT_ASF }, + { MTP_PROPERTY_OBJECT_FORMAT, MTP_TYPE_UINT16, 0x00, MTP_FORMAT_MS_WORD_DOCUMENT, 0x000000000, 0x00, MTP_FORMAT_MS_WORD_DOCUMENT }, + { MTP_PROPERTY_OBJECT_FORMAT, MTP_TYPE_UINT16, 0x00, MTP_FORMAT_MS_EXCEL_SPREADSHEET, 0x000000000, 0x00, MTP_FORMAT_MS_EXCEL_SPREADSHEET }, + { MTP_PROPERTY_OBJECT_FORMAT, MTP_TYPE_UINT16, 0x00, MTP_FORMAT_MS_POWERPOINT_PRESENTATION, 0x000000000, 0x00, MTP_FORMAT_MS_POWERPOINT_PRESENTATION }, + + { MTP_PROPERTY_OBJECT_SIZE, MTP_TYPE_UINT64, 0x00, 0x0000000000000000, 0x000000000, 0x00, MTP_FORMAT_ASSOCIATION }, + { MTP_PROPERTY_STORAGE_ID, MTP_TYPE_UINT32, 0x00, 0x00000000, 0x000000000, 0x00, MTP_FORMAT_ASSOCIATION }, + { MTP_PROPERTY_PROTECTION_STATUS, MTP_TYPE_UINT16, 0x00, 0x0000, 0x000000000, 0x00, MTP_FORMAT_ASSOCIATION }, + { MTP_PROPERTY_DISPLAY_NAME, MTP_TYPE_STR, 0x00, 0x0000, 0x000000000, 0x00, MTP_FORMAT_ASSOCIATION }, + { MTP_PROPERTY_OBJECT_FILE_NAME, MTP_TYPE_STR, 0x01, 0x0000, 0x000000000, 0x00, MTP_FORMAT_ASSOCIATION }, + { MTP_PROPERTY_DATE_CREATED, MTP_TYPE_STR, 0x00, 0x00, 0x000000000, 0x00, MTP_FORMAT_ASSOCIATION }, + { MTP_PROPERTY_DATE_MODIFIED, MTP_TYPE_STR, 0x00, 0x00, 0x000000000, 0x00, MTP_FORMAT_ASSOCIATION }, + { MTP_PROPERTY_PARENT_OBJECT, MTP_TYPE_UINT32, 0x00, 0x00000000, 0x000000000, 0x00, MTP_FORMAT_ASSOCIATION }, + { MTP_PROPERTY_PERSISTENT_UID, MTP_TYPE_UINT128, 0x00, 0x00, 0x000000000, 0x00, MTP_FORMAT_ASSOCIATION }, + { MTP_PROPERTY_NAME, MTP_TYPE_STR, 0x00, 0x00, 0x000000000, 0x00, MTP_FORMAT_ASSOCIATION }, + + { MTP_PROPERTY_OBJECT_SIZE, MTP_TYPE_UINT64, 0x00, 0x0000000000000000, 0x000000000, 0x00, MTP_FORMAT_UNDEFINED }, + { MTP_PROPERTY_STORAGE_ID, MTP_TYPE_UINT32, 0x00, 0x00000000, 0x000000000, 0x00, MTP_FORMAT_UNDEFINED }, + { MTP_PROPERTY_PROTECTION_STATUS, MTP_TYPE_UINT16, 0x00, 0x0000, 0x000000000, 0x00, MTP_FORMAT_UNDEFINED }, + { MTP_PROPERTY_DISPLAY_NAME, MTP_TYPE_STR, 0x00, 0x0000, 0x000000000, 0x00, MTP_FORMAT_UNDEFINED }, + { MTP_PROPERTY_OBJECT_FILE_NAME, MTP_TYPE_STR, 0x01, 0x0000, 0x000000000, 0x00, MTP_FORMAT_UNDEFINED }, + { MTP_PROPERTY_DATE_CREATED, MTP_TYPE_STR, 0x00, 0x00, 0x000000000, 0x00, MTP_FORMAT_UNDEFINED }, + { MTP_PROPERTY_DATE_MODIFIED, MTP_TYPE_STR, 0x00, 0x00, 0x000000000, 0x00, MTP_FORMAT_UNDEFINED }, + { MTP_PROPERTY_PARENT_OBJECT, MTP_TYPE_UINT32, 0x00, 0x00000000, 0x000000000, 0x00, MTP_FORMAT_UNDEFINED }, + { MTP_PROPERTY_PERSISTENT_UID, MTP_TYPE_UINT128, 0x00, 0x00, 0x000000000, 0x00, MTP_FORMAT_UNDEFINED }, + { MTP_PROPERTY_NAME, MTP_TYPE_STR, 0x00, 0x00, 0x000000000, 0x00, MTP_FORMAT_UNDEFINED }, + + //{MTP_PROPERTY_ASSOCIATION_TYPE, MTP_TYPE_UINT16, 0x00, 0x0001 , 0x000000000 , 0x00 , 0xFFFF }, + { MTP_PROPERTY_ASSOCIATION_DESC, MTP_TYPE_UINT32, 0x00, 0x00000000, 0x000000000, 0x00, 0xFFFF }, + { MTP_PROPERTY_PROTECTION_STATUS, MTP_TYPE_UINT16, 0x00, 0x0000, 0x000000000, 0x00, 0xFFFF }, + { MTP_PROPERTY_HIDDEN, MTP_TYPE_UINT16, 0x00, 0x0000, 0x000000000, 0x00, 0xFFFF }, + + { 0xFFFF, MTP_TYPE_UINT32, 0x00, 0x00000000, 0x000000000, 0x00 } +}; + +const profile_property support_device_properties[] = { + // prop_code data_type getset default_value group_code form_flag + //{MTP_DEVICE_PROPERTY_SYNCHRONIZATION_PARTNER, MTP_TYPE_UINT32, 0x00, 0x00000000 , 0x000000000 , 0x00 }, + //{MTP_DEVICE_PROPERTY_IMAGE_SIZE, MTP_TYPE_UINT32, 0x00, 0x00000000 , 0x000000000 , 0x00 }, + { MTP_DEVICE_PROPERTY_BATTERY_LEVEL, MTP_TYPE_UINT16, 0x00, 0x00000000, 0x000000000, 0x00 }, + { MTP_DEVICE_PROPERTY_DEVICE_FRIENDLY_NAME, MTP_TYPE_STR, 0x00, 0x00000000, 0x000000000, 0x00 }, + + { 0xFFFF, MTP_TYPE_UINT32, 0x00, 0x00000000, 0x000000000, 0x00 } +}; + +#endif \ No newline at end of file diff --git a/kernel/cherryusb/class/serial/usbh_cdc_acm.c b/kernel/cherryusb/class/serial/usbh_cdc_acm.c new file mode 100644 index 0000000..cf5363e --- /dev/null +++ b/kernel/cherryusb/class/serial/usbh_cdc_acm.c @@ -0,0 +1,266 @@ +/* + * Copyright (c) 2022 ~ 2025, sakumisu + * + * SPDX-License-Identifier: Apache-2.0 + */ +#include "usbh_core.h" +#include "usbh_serial.h" +#include "usbh_cdc_acm.h" + +#undef USB_DBG_TAG +#define USB_DBG_TAG "usbh_cdc_acm" +#include "usb_log.h" + +struct usbh_cdc_acm { + struct usb_endpoint_descriptor *intin; + struct usbh_urb intin_urb; + struct usb_osal_timer *modem_timer; + uint16_t modem_status; +}; + +static int usbh_cdc_acm_attach(struct usbh_serial *serial) +{ + struct usb_endpoint_descriptor *ep_desc; + int ret; + + struct usbh_cdc_acm *cdc_acm_class = usb_osal_malloc(sizeof(struct usbh_cdc_acm)); + if (!cdc_acm_class) { + USB_LOG_ERR("No memory for cdc_acm_class\r\n"); + return -USB_ERR_NOMEM; + } + memset(cdc_acm_class, 0, sizeof(struct usbh_cdc_acm)); + serial->priv = cdc_acm_class; + + for (uint8_t i = 0; i < serial->hport->config.intf[serial->intf].altsetting[0].intf_desc.bNumEndpoints; i++) { + ep_desc = &serial->hport->config.intf[serial->intf].altsetting[0].ep[i].ep_desc; + + if (USB_GET_ENDPOINT_TYPE(ep_desc->bmAttributes) == USB_ENDPOINT_TYPE_INTERRUPT) { + if (ep_desc->bEndpointAddress & 0x80) { + USBH_EP_INIT(cdc_acm_class->intin, ep_desc); + break; + } else { + } + } + } + + if (!cdc_acm_class->intin) { + USB_LOG_ERR("Failed to find interrupt endpoint\r\n"); + ret = -USB_ERR_NODEV; + goto errout; + } + return 0; +errout: + serial->priv = NULL; + usb_osal_free(cdc_acm_class); + return ret; +} + +static void usbh_cdc_acm_detach(struct usbh_serial *serial) +{ + struct usbh_cdc_acm *cdc_acm_class; + + if (!serial || !serial->priv) { + return; + } + + cdc_acm_class = (struct usbh_cdc_acm *)serial->priv; + if (cdc_acm_class->intin) { + usbh_kill_urb(&cdc_acm_class->intin_urb); + } + serial->priv = NULL; + usb_osal_free(cdc_acm_class); +} + +static int usbh_cdc_acm_set_line_coding(struct usbh_serial *serial, struct cdc_line_coding *line_coding) +{ + struct usb_setup_packet *setup; + + if (!serial || !serial->hport) { + return -USB_ERR_INVAL; + } + setup = serial->hport->setup; + + setup->bmRequestType = USB_REQUEST_DIR_OUT | USB_REQUEST_CLASS | USB_REQUEST_RECIPIENT_INTERFACE; + setup->bRequest = CDC_REQUEST_SET_LINE_CODING; + setup->wValue = 0; + setup->wIndex = serial->intf; + setup->wLength = 7; + + memcpy(serial->iobuffer, line_coding, sizeof(struct cdc_line_coding)); + + return usbh_control_transfer(serial->hport, setup, serial->iobuffer); +} + +static int usbh_cdc_acm_get_line_coding(struct usbh_serial *serial, struct cdc_line_coding *line_coding) +{ + struct usb_setup_packet *setup; + int ret; + + if (!serial || !serial->hport) { + return -USB_ERR_INVAL; + } + setup = serial->hport->setup; + + setup->bmRequestType = USB_REQUEST_DIR_IN | USB_REQUEST_CLASS | USB_REQUEST_RECIPIENT_INTERFACE; + setup->bRequest = CDC_REQUEST_GET_LINE_CODING; + setup->wValue = 0; + setup->wIndex = serial->intf; + setup->wLength = 7; + + ret = usbh_control_transfer(serial->hport, setup, serial->iobuffer); + if (ret < 0) { + return ret; + } + memcpy(line_coding, serial->iobuffer, sizeof(struct cdc_line_coding)); + return ret; +} + +static int usbh_cdc_acm_set_line_state(struct usbh_serial *serial, bool dtr, bool rts) +{ + struct usb_setup_packet *setup; + + if (!serial || !serial->hport) { + return -USB_ERR_INVAL; + } + setup = serial->hport->setup; + + setup->bmRequestType = USB_REQUEST_DIR_OUT | USB_REQUEST_CLASS | USB_REQUEST_RECIPIENT_INTERFACE; + setup->bRequest = CDC_REQUEST_SET_CONTROL_LINE_STATE; + setup->wValue = (dtr << 0) | (rts << 1); + setup->wIndex = serial->intf; + setup->wLength = 0; + + return usbh_control_transfer(serial->hport, setup, NULL); +} + +static int usbh_cdc_acm_get_modem_status(struct usbh_serial *serial) +{ + struct usbh_cdc_acm *cdc_acm_class; + uintptr_t flags; + uint16_t status; + + if (!serial || !serial->hport || !serial->priv) { + return -USB_ERR_INVAL; + } + + flags = usb_osal_enter_critical_section(); + + cdc_acm_class = (struct usbh_cdc_acm *)serial->priv; + + status = (cdc_acm_class->modem_status & CDC_SERIAL_STATE_DSR ? USBH_SERIAL_TIOCM_DSR : 0) | + (cdc_acm_class->modem_status & CDC_SERIAL_STATE_RING ? USBH_SERIAL_TIOCM_RI : 0) | + (cdc_acm_class->modem_status & CDC_SERIAL_STATE_DCD ? USBH_SERIAL_TIOCM_CD : 0) | + (serial->line_state & USBH_SERIAL_TIOCM_DTR ? USBH_SERIAL_TIOCM_DTR : 0) | + (serial->line_state & USBH_SERIAL_TIOCM_RTS ? USBH_SERIAL_TIOCM_RTS : 0); + + usb_osal_leave_critical_section(flags); + + return status; +} + +#ifdef CONFIG_USBH_SERIAL_GET_MODEM_STATUS +static int __usbh_cdc_acm_get_modem_status(struct usbh_serial *serial) +{ + struct usbh_cdc_acm *cdc_acm_class; + struct cdc_acm_notification *notification; + uint16_t difference; + uintptr_t flags; + int ret; + + if (!serial || !serial->hport || !serial->priv) { + return -USB_ERR_INVAL; + } + cdc_acm_class = (struct usbh_cdc_acm *)serial->priv; + + usbh_int_urb_fill(&cdc_acm_class->intin_urb, serial->hport, cdc_acm_class->intin, &serial->iobuffer[USBH_SERIAL_INT_NOCACHE_OFFSET], cdc_acm_class->intin->wMaxPacketSize, 0xffffffff, NULL, NULL); + ret = usbh_submit_urb(&cdc_acm_class->intin_urb); + if (ret < 0) { + return ret; + } + + if (cdc_acm_class->intin_urb.actual_length < sizeof(struct cdc_acm_notification)) { + return -USB_ERR_INVAL; + } + + notification = (struct cdc_acm_notification *)&serial->iobuffer[USBH_SERIAL_INT_NOCACHE_OFFSET]; + if (notification->bNotificationType != CDC_NOTIFICATION_SERIAL_STATE) { + return -USB_ERR_INVAL; + } + + flags = usb_osal_enter_critical_section(); + + difference = cdc_acm_class->modem_status ^ notification->data; + cdc_acm_class->modem_status = notification->data; + + if (difference & CDC_SERIAL_STATE_DSR) + serial->iocount.dsr++; + if (difference & CDC_SERIAL_STATE_DCD) + serial->iocount.dcd++; + if (notification->data & CDC_SERIAL_STATE_BREAK) + serial->iocount.brk++; + if (notification->data & CDC_SERIAL_STATE_FRAMING) + serial->iocount.frame++; + if (notification->data & CDC_SERIAL_STATE_PARITY) + serial->iocount.parity++; + if (notification->data & CDC_SERIAL_STATE_OVERRUN) + serial->iocount.overrun++; + + usb_osal_leave_critical_section(flags); + + return ret; +} +#endif + +static const struct usbh_serial_driver cdc_acm_driver = { + .driver_name = "cdc_acm", + + .ignore_rx_header = 0, + .ignore_tx_header = 0, + + .attach = usbh_cdc_acm_attach, + .detach = usbh_cdc_acm_detach, + .set_flow_control = NULL, + .set_line_coding = usbh_cdc_acm_set_line_coding, + .get_line_coding = usbh_cdc_acm_get_line_coding, + .set_line_state = usbh_cdc_acm_set_line_state, + .get_modem_status = usbh_cdc_acm_get_modem_status, +}; + +static int usbh_cdc_acm_connect(struct usbh_hubport *hport, uint8_t intf) +{ + return usbh_serial_probe(hport, intf, &cdc_acm_driver) ? 0 : -USB_ERR_NOMEM; +} + +static int usbh_cdc_acm_disconnect(struct usbh_hubport *hport, uint8_t intf) +{ + struct usbh_serial *serial = (struct usbh_serial *)hport->config.intf[intf].priv; + + if (serial) { + usbh_serial_remove(serial); + } + return 0; +} + +const struct usbh_class_driver cdc_acm_class_driver = { + .driver_name = "cdc_acm", + .connect = usbh_cdc_acm_connect, + .disconnect = usbh_cdc_acm_disconnect +}; + +CLASS_INFO_DEFINE const struct usbh_class_info cdc_acm_none_class_info = { + .match_flags = USB_CLASS_MATCH_INTF_CLASS | USB_CLASS_MATCH_INTF_SUBCLASS | USB_CLASS_MATCH_INTF_PROTOCOL, + .bInterfaceClass = USB_DEVICE_CLASS_CDC, + .bInterfaceSubClass = CDC_ABSTRACT_CONTROL_MODEL, + .bInterfaceProtocol = CDC_COMMON_PROTOCOL_NONE, + .id_table = NULL, + .class_driver = &cdc_acm_class_driver +}; + +CLASS_INFO_DEFINE const struct usbh_class_info cdc_acm_at_class_info = { + .match_flags = USB_CLASS_MATCH_INTF_CLASS | USB_CLASS_MATCH_INTF_SUBCLASS | USB_CLASS_MATCH_INTF_PROTOCOL, + .bInterfaceClass = USB_DEVICE_CLASS_CDC, + .bInterfaceSubClass = CDC_ABSTRACT_CONTROL_MODEL, + .bInterfaceProtocol = CDC_COMMON_PROTOCOL_AT_COMMANDS, + .id_table = NULL, + .class_driver = &cdc_acm_class_driver +}; diff --git a/kernel/cherryusb/class/serial/usbh_cdc_acm.h b/kernel/cherryusb/class/serial/usbh_cdc_acm.h new file mode 100644 index 0000000..2940cd9 --- /dev/null +++ b/kernel/cherryusb/class/serial/usbh_cdc_acm.h @@ -0,0 +1,19 @@ +/* + * Copyright (c) 2022 ~ 2025, sakumisu + * + * SPDX-License-Identifier: Apache-2.0 + */ +#ifndef USBH_CDC_ACM_H +#define USBH_CDC_ACM_H + +#include "usb_cdc.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#ifdef __cplusplus +} +#endif + +#endif /* USBH_CDC_ACM_H */ diff --git a/kernel/cherryusb/class/serial/usbh_ch34x.c b/kernel/cherryusb/class/serial/usbh_ch34x.c new file mode 100644 index 0000000..4595bca --- /dev/null +++ b/kernel/cherryusb/class/serial/usbh_ch34x.c @@ -0,0 +1,409 @@ +/* + * Copyright (c) 2024 ~ 2025, sakumisu + * + * SPDX-License-Identifier: Apache-2.0 + */ +#include "usbh_core.h" +#include "usbh_serial.h" +#include "usbh_ch34x.h" + +#undef USB_DBG_TAG +#define USB_DBG_TAG "usbh_ch34x" +#include "usb_log.h" + +struct usbh_ch34x { + struct usb_endpoint_descriptor *intin; + struct usbh_urb intin_urb; + struct usb_osal_timer *modem_timer; + uint16_t modem_status; +}; + +/* refer to https://github.com/WCHSoftGroup/ch341ser_linux/blob/main/driver/ch341.c */ + +static int usbh_ch34x_get_baudrate_div(uint32_t baudrate, uint8_t *factor, uint8_t *divisor) +{ + uint8_t a; + uint8_t b; + uint32_t c; + + switch (baudrate) { + case 921600: + a = 0xf3; + b = 7; + break; + + case 307200: + a = 0xd9; + b = 7; + break; + + default: + if (baudrate > 6000000 / 255) { + b = 3; + c = 6000000; + } else if (baudrate > 750000 / 255) { + b = 2; + c = 750000; + } else if (baudrate > 93750 / 255) { + b = 1; + c = 93750; + } else { + b = 0; + c = 11719; + } + a = (uint8_t)(c / baudrate); + if (a == 0 || a == 0xFF) { + return -USB_ERR_INVAL; + } + if ((c / a - baudrate) > (baudrate - c / (a + 1))) { + a++; + } + a = (uint8_t)(256 - a); + break; + } + + *factor = a; + *divisor = b; + + return 0; +} + +static int usbh_ch34x_control_out(struct usbh_serial *serial, uint8_t bRequest, uint16_t wValue, uint16_t wIndex) +{ + struct usb_setup_packet *setup; + + if (!serial || !serial->hport) { + return -USB_ERR_INVAL; + } + setup = serial->hport->setup; + + setup->bmRequestType = USB_REQUEST_DIR_OUT | USB_REQUEST_VENDOR | USB_REQUEST_RECIPIENT_DEVICE; + setup->bRequest = bRequest; + setup->wValue = wValue; + setup->wIndex = wIndex; + setup->wLength = 0; + + return usbh_control_transfer(serial->hport, setup, NULL); +} + +static int usbh_ch34x_control_in(struct usbh_serial *serial, uint8_t bRequest, uint16_t wValue, uint16_t wIndex, uint8_t *data, uint16_t size) +{ + struct usb_setup_packet *setup; + int ret; + + if (!serial || !serial->hport) { + return -USB_ERR_INVAL; + } + setup = serial->hport->setup; + + setup->bmRequestType = USB_REQUEST_DIR_IN | USB_REQUEST_VENDOR | USB_REQUEST_RECIPIENT_DEVICE; + setup->bRequest = bRequest; + setup->wValue = wValue; + setup->wIndex = wIndex; + setup->wLength = size; + + ret = usbh_control_transfer(serial->hport, setup, serial->iobuffer); + if (ret < 0) { + return ret; + } + memcpy(data, serial->iobuffer, size); + + return ret; +} + +static int usbh_ch34x_get_version(struct usbh_serial *serial) +{ + int ret; + uint8_t buf[2]; + + ret = usbh_ch34x_control_in(serial, CH34X_READ_VERSION, 0, 0, buf, 2); + if (ret < 0) { + return ret; + } + + USB_LOG_INFO("chip version: 0x%02x\r\n", buf[0]); + return ret; +} + +static int usbh_ch34x_attach(struct usbh_serial *serial) +{ + struct usb_endpoint_descriptor *ep_desc; + int ret; + + struct usbh_ch34x *ch34x_class = usb_osal_malloc(sizeof(struct usbh_ch34x)); + if (!ch34x_class) { + USB_LOG_ERR("No memory for ch34x_class\r\n"); + return -USB_ERR_NOMEM; + } + memset(ch34x_class, 0, sizeof(struct usbh_ch34x)); + serial->priv = ch34x_class; + + for (uint8_t i = 0; i < serial->hport->config.intf[serial->intf].altsetting[0].intf_desc.bNumEndpoints; i++) { + ep_desc = &serial->hport->config.intf[serial->intf].altsetting[0].ep[i].ep_desc; + + if (USB_GET_ENDPOINT_TYPE(ep_desc->bmAttributes) == USB_ENDPOINT_TYPE_INTERRUPT) { + if (ep_desc->bEndpointAddress & 0x80) { + USBH_EP_INIT(ch34x_class->intin, ep_desc); + break; + } else { + } + } + } + + if (!ch34x_class->intin) { + USB_LOG_ERR("Failed to find interrupt endpoint\r\n"); + ret = -USB_ERR_NODEV; + goto errout; + } + + ret = usbh_ch34x_get_version(serial); + ret |= usbh_ch34x_control_out(serial, CH34X_SERIAL_INIT, 0, 0); + ret |= usbh_ch34x_control_out(serial, CH34X_WRITE_REG, 0x1312, 0xd982); + ret |= usbh_ch34x_control_out(serial, CH34X_WRITE_REG, 0x0f2c, 0x0007); + if (ret < 0) { + goto errout; + } + + return 0; +errout: + serial->priv = NULL; + usb_osal_free(ch34x_class); + return ret; +} + +static void usbh_ch34x_detach(struct usbh_serial *serial) +{ + struct usbh_ch34x *ch34x_class; + + if (!serial || !serial->priv) { + return; + } + + ch34x_class = (struct usbh_ch34x *)serial->priv; + if (ch34x_class->intin) { + usbh_kill_urb(&ch34x_class->intin_urb); + } + serial->priv = NULL; + usb_osal_free(ch34x_class); +} + +static int usbh_ch34x_set_flow_ctrl(struct usbh_serial *serial, bool hardctrl) +{ + return usbh_ch34x_control_out(serial, CH34X_WRITE_REG, 0x2727, hardctrl ? 0x0101 : 0x0000); +} + +static int usbh_ch34x_set_line_coding(struct usbh_serial *serial, struct cdc_line_coding *line_coding) +{ + uint16_t reg_value = 0; + uint16_t value = 0; + uint16_t index = 0; + uint8_t factor = 0; + uint8_t divisor = 0; + + switch (line_coding->bParityType) { + case 0: + break; + case 1: + reg_value |= CH341_L_PO; + break; + case 2: + reg_value |= CH341_L_PE; + break; + case 3: + reg_value |= CH341_L_PM; + break; + case 4: + reg_value |= CH341_L_PS; + break; + default: + return -USB_ERR_INVAL; + } + + switch (line_coding->bDataBits) { + case 5: + reg_value |= CH341_L_D5; + break; + case 6: + reg_value |= CH341_L_D6; + break; + case 7: + reg_value |= CH341_L_D7; + break; + case 8: + reg_value |= CH341_L_D8; + break; + default: + return -USB_ERR_INVAL; + } + + if (line_coding->bCharFormat == 2) { + reg_value |= CH341_L_SB; + } + + usbh_ch34x_get_baudrate_div(line_coding->dwDTERate, &factor, &divisor); + + reg_value |= 0xC0; + value |= 0x9c; + value |= reg_value << 8; + index |= 0x80 | divisor; + index |= (uint16_t)factor << 8; + + return usbh_ch34x_control_out(serial, CH34X_SERIAL_INIT, value, index); +} + +static int usbh_ch34x_set_line_state(struct usbh_serial *serial, bool dtr, bool rts) +{ + uint16_t value = 0; + uint8_t control = 0; + + control = (dtr << 5) | (rts << 6); + value = (uint8_t)~control; + + return usbh_ch34x_control_out(serial, CH34X_MODEM_CTRL, value, 0x0000); +} + +static int usbh_ch34x_get_modem_status(struct usbh_serial *serial) +{ + struct usbh_ch34x *ch34x_class; + uintptr_t flags; + uint16_t status; + + if (!serial || !serial->hport || !serial->priv) { + return -USB_ERR_INVAL; + } + + flags = usb_osal_enter_critical_section(); + + ch34x_class = (struct usbh_ch34x *)serial->priv; + + status = (ch34x_class->modem_status & CH341_CTI_DS ? USBH_SERIAL_TIOCM_DSR : 0) | + (ch34x_class->modem_status & CH341_CTI_C ? USBH_SERIAL_TIOCM_CTS : 0) | + (ch34x_class->modem_status & CH341_CTRL_RI ? USBH_SERIAL_TIOCM_RI : 0) | + (ch34x_class->modem_status & CH341_CTI_DC ? USBH_SERIAL_TIOCM_CD : 0) | + (serial->line_state & USBH_SERIAL_TIOCM_DTR ? USBH_SERIAL_TIOCM_DTR : 0) | + (serial->line_state & USBH_SERIAL_TIOCM_RTS ? USBH_SERIAL_TIOCM_RTS : 0); + + usb_osal_leave_critical_section(flags); + + return status; +} + +#ifdef CONFIG_USBH_SERIAL_GET_MODEM_STATUS +static int __usbh_ch34x_get_modem_status(struct usbh_serial *serial, uint16_t *status) +{ + struct usbh_ch34x *ch34x_class; + uint8_t type = 0; + uint8_t data = 0; + uint16_t difference; + uintptr_t flags; + int ret; + + if (!serial || !serial->hport || !serial->priv) { + return -USB_ERR_INVAL; + } + ch34x_class = (struct usbh_ch34x *)serial->priv; + + usbh_int_urb_fill(&ch34x_class->intin_urb, serial->hport, ch34x_class->intin, &serial->iobuffer[USBH_SERIAL_INT_NOCACHE_OFFSET], ch34x_class->intin->wMaxPacketSize, 0xffffffff, NULL, NULL); + ret = usbh_submit_urb(&ch34x_class->intin_urb); + if (ret < 0) { + return ret; + } + + if (ret < 4) { + return -USB_ERR_INVAL; + } + + flags = usb_osal_enter_critical_section(); + + type = serial->iobuffer[USBH_SERIAL_INT_NOCACHE_OFFSET]; + if (type & CH341_CTT_M) { + data = ~serial->iobuffer[USBH_SERIAL_INT_NOCACHE_OFFSET + 2] & CH341_CTI_ST; + difference = data ^ (ch34x_class->modem_status & CH341_CTI_ST); + ch34x_class->modem_status = data; + + if (difference) { + if (difference & CH341_CTI_C) { + serial->iocount.cts++; + } + if (difference & CH341_CTI_DS) { + serial->iocount.dsr++; + } + if (difference & CH341_CTRL_RI) { + serial->iocount.rng++; + } + if (difference & CH341_CTI_DC) { + serial->iocount.dcd++; + } + } + } + + if (type & CH341_CTT_O) { + serial->iocount.overrun++; + } + if ((type & CH341_CTT_F) == CH341_CTT_F) { + serial->iocount.frame++; + } + if (type & CH341_CTT_P) { + serial->iocount.parity++; + } + + usb_osal_leave_critical_section(flags); + + return ret; +} +#endif + +static const struct usbh_serial_driver ch34x_driver = { + .driver_name = "ch34x", + + .ignore_rx_header = 0, + .ignore_tx_header = 0, + + .attach = usbh_ch34x_attach, + .detach = usbh_ch34x_detach, + .set_flow_control = usbh_ch34x_set_flow_ctrl, + .set_line_coding = usbh_ch34x_set_line_coding, + .get_line_coding = NULL, + .set_line_state = usbh_ch34x_set_line_state, + .get_modem_status = usbh_ch34x_get_modem_status, +}; + +static int usbh_ch34x_connect(struct usbh_hubport *hport, uint8_t intf) +{ + return usbh_serial_probe(hport, intf, &ch34x_driver) ? 0 : -USB_ERR_NOMEM; +} + +static int usbh_ch34x_disconnect(struct usbh_hubport *hport, uint8_t intf) +{ + struct usbh_serial *serial = (struct usbh_serial *)hport->config.intf[intf].priv; + + if (serial) { + usbh_serial_remove(serial); + } + + return 0; +} + +static const uint16_t ch34x_id_table[][2] = { + { 0x1A86, 0x7523 }, /* ch340 chip */ + { 0x1A86, 0x7522 }, /* ch340k chip */ + { 0x1A86, 0x5523 }, /* ch341 chip */ + { 0x1A86, 0xe523 }, /* ch330 chip */ + { 0x4348, 0x5523 }, /* ch340 custom chip */ + { 0, 0 }, +}; + +const struct usbh_class_driver ch34x_class_driver = { + .driver_name = "ch34x", + .connect = usbh_ch34x_connect, + .disconnect = usbh_ch34x_disconnect +}; + +CLASS_INFO_DEFINE const struct usbh_class_info ch34x_class_info = { + .match_flags = USB_CLASS_MATCH_VID_PID | USB_CLASS_MATCH_INTF_CLASS, + .bInterfaceClass = 0xff, + .bInterfaceSubClass = 0x00, + .bInterfaceProtocol = 0x00, + .id_table = ch34x_id_table, + .class_driver = &ch34x_class_driver +}; \ No newline at end of file diff --git a/kernel/cherryusb/class/serial/usbh_ch34x.h b/kernel/cherryusb/class/serial/usbh_ch34x.h new file mode 100644 index 0000000..21e4810 --- /dev/null +++ b/kernel/cherryusb/class/serial/usbh_ch34x.h @@ -0,0 +1,56 @@ +/* + * Copyright (c) 2024 ~ 2025, sakumisu + * + * SPDX-License-Identifier: Apache-2.0 + */ +#ifndef USBH_CH34X_H +#define USBH_CH34X_H + +#include "usb_cdc.h" + +/* Requests */ +#define CH34X_READ_VERSION 0x5F +#define CH34X_WRITE_REG 0x9A +#define CH34X_READ_REG 0x95 +#define CH34X_SERIAL_INIT 0xA1 +#define CH34X_MODEM_CTRL 0xA4 + +// modem control bits +#define CH34X_BIT_RTS (1 << 6) +#define CH34X_BIT_DTR (1 << 5) + +#define CH341_CTO_O 0x10 +#define CH341_CTO_D 0x20 +#define CH341_CTO_R 0x40 +#define CH341_CTI_C 0x01 +#define CH341_CTI_DS 0x02 +#define CH341_CTRL_RI 0x04 +#define CH341_CTI_DC 0x08 +#define CH341_CTI_ST 0x0f + +#define CH341_CTT_M BIT(3) +#define CH341_CTT_F (BIT(2) | BIT(6)) +#define CH341_CTT_P BIT(2) +#define CH341_CTT_O BIT(1) + +#define CH341_L_ER 0x80 +#define CH341_L_ET 0x40 +#define CH341_L_PS 0x38 +#define CH341_L_PM 0x28 +#define CH341_L_PE 0x18 +#define CH341_L_PO 0x08 +#define CH341_L_SB 0x04 +#define CH341_L_D8 0x03 +#define CH341_L_D7 0x02 +#define CH341_L_D6 0x01 +#define CH341_L_D5 0x00 + +#ifdef __cplusplus +extern "C" { +#endif + +#ifdef __cplusplus +} +#endif + +#endif /* USBH_CH34X_H */ diff --git a/kernel/cherryusb/class/serial/usbh_cp210x.c b/kernel/cherryusb/class/serial/usbh_cp210x.c new file mode 100644 index 0000000..7b240e2 --- /dev/null +++ b/kernel/cherryusb/class/serial/usbh_cp210x.c @@ -0,0 +1,507 @@ +/* + * Copyright (c) 2024 ~ 2025, sakumisu + * + * SPDX-License-Identifier: Apache-2.0 + */ +#include "usbh_core.h" +#include "usbh_serial.h" +#include "usbh_cp210x.h" + +#undef USB_DBG_TAG +#define USB_DBG_TAG "usbh_cp210x" +#include "usb_log.h" + +struct usbh_cp210x { + uint8_t partnum; + uint32_t fw_version; + uint32_t min_speed; + uint32_t max_speed; + bool use_actual_rate; + bool no_flow_control; + bool no_event_mode; +}; + +struct cp210x_rate { + uint32_t rate; + uint32_t high; +}; + +static const struct cp210x_rate cp210x_an205_table1[] = { + { 300, 300 }, + { 600, 600 }, + { 1200, 1200 }, + { 1800, 1800 }, + { 2400, 2400 }, + { 4000, 4000 }, + { 4800, 4803 }, + { 7200, 7207 }, + { 9600, 9612 }, + { 14400, 14428 }, + { 16000, 16062 }, + { 19200, 19250 }, + { 28800, 28912 }, + { 38400, 38601 }, + { 51200, 51558 }, + { 56000, 56280 }, + { 57600, 58053 }, + { 64000, 64111 }, + { 76800, 77608 }, + { 115200, 117028 }, + { 128000, 129347 }, + { 153600, 156868 }, + { 230400, 237832 }, + { 250000, 254234 }, + { 256000, 273066 }, + { 460800, 491520 }, + { 500000, 567138 }, + { 576000, 670254 }, + { 921600, 0xffffffff } +}; + +/* + * Quantises the baud rate as per AN205 Table 1 + */ +static uint32_t cp210x_get_an205_rate(uint32_t baud) +{ + int i; + + for (i = 0; i < ARRAY_SIZE(cp210x_an205_table1); ++i) { + if (baud <= cp210x_an205_table1[i].high) + break; + } + + return cp210x_an205_table1[i].rate; +} + +static uint32_t cp210x_get_actual_rate(uint32_t baud) +{ + unsigned int prescale = 1; + unsigned int div; + + if (baud <= 365) + prescale = 4; + + div = DIV_ROUND_CLOSEST(48000000, 2 * prescale * baud); + baud = 48000000 / (2 * prescale * div); + + return baud; +} + +static void usbh_cp210x_init_max_speed(struct usbh_serial *serial) +{ + struct usbh_cp210x *cp210x_class; + + if (!serial || !serial->hport || !serial->priv) { + return; + } + + cp210x_class = (struct usbh_cp210x *)serial->priv; + + bool use_actual_rate = false; + uint32_t min = 300; + uint32_t max; + + switch (cp210x_class->partnum) { + case CP210X_PARTNUM_CP2101: + max = 921600; + break; + case CP210X_PARTNUM_CP2102: + case CP210X_PARTNUM_CP2103: + max = 1000000; + break; + case CP210X_PARTNUM_CP2104: + use_actual_rate = true; + max = 2000000; + break; + case CP210X_PARTNUM_CP2108: + max = 2000000; + break; + case CP210X_PARTNUM_CP2105: + if (serial->intf == 0) { + use_actual_rate = true; + max = 2000000; /* ECI */ + } else { + min = 2400; + max = 921600; /* SCI */ + } + break; + case CP210X_PARTNUM_CP2102N_QFN28: + case CP210X_PARTNUM_CP2102N_QFN24: + case CP210X_PARTNUM_CP2102N_QFN20: + use_actual_rate = true; + max = 3000000; + break; + default: + max = 2000000; + break; + } + + cp210x_class->min_speed = min; + cp210x_class->max_speed = max; + cp210x_class->use_actual_rate = use_actual_rate; +} + +static int usbh_cp210x_control_out(struct usbh_serial *serial, uint8_t bRequest, uint16_t wValue, uint16_t wIndex, uint8_t *data, uint16_t size) +{ + struct usb_setup_packet *setup; + + if (!serial || !serial->hport) { + return -USB_ERR_INVAL; + } + setup = serial->hport->setup; + + setup->bmRequestType = USB_REQUEST_DIR_OUT | USB_REQUEST_VENDOR | USB_REQUEST_RECIPIENT_DEVICE; + setup->bRequest = bRequest; + setup->wValue = wValue; + setup->wIndex = wIndex; + setup->wLength = size; + + if (data && size) { + memcpy(serial->iobuffer, data, size); + return usbh_control_transfer(serial->hport, setup, serial->iobuffer); + } else { + return usbh_control_transfer(serial->hport, setup, NULL); + } +} + +static int usbh_cp210x_control_in(struct usbh_serial *serial, uint8_t bRequest, uint16_t wValue, uint16_t wIndex, uint8_t *data, uint16_t size) +{ + struct usb_setup_packet *setup; + int ret; + + if (!serial || !serial->hport) { + return -USB_ERR_INVAL; + } + setup = serial->hport->setup; + + setup->bmRequestType = USB_REQUEST_DIR_IN | USB_REQUEST_VENDOR | USB_REQUEST_RECIPIENT_DEVICE; + setup->bRequest = bRequest; + setup->wValue = wValue; + setup->wIndex = wIndex; + setup->wLength = size; + + ret = usbh_control_transfer(serial->hport, setup, serial->iobuffer); + if (ret < 0) { + return ret; + } + memcpy(data, serial->iobuffer, size); + + return ret; +} + +static int usbh_cp210x_get_partnum(struct usbh_serial *serial) +{ + uint8_t version[3]; + struct usbh_cp210x *cp210x_class; + int ret; + + if (!serial || !serial->hport || !serial->priv) { + return -USB_ERR_INVAL; + } + + cp210x_class = (struct usbh_cp210x *)serial->priv; + + ret = usbh_cp210x_control_in(serial, CP210X_VENDOR_SPECIFIC, CP210X_GET_PARTNUM, serial->intf, (uint8_t *)&cp210x_class->partnum, 1); + if (ret < 0) { + return ret; + } + + USB_LOG_INFO("chip partnum: 0x%02x\r\n", cp210x_class->partnum); + + switch (cp210x_class->partnum) { + case CP210X_PARTNUM_CP2102: + break; + case CP210X_PARTNUM_CP2105: + case CP210X_PARTNUM_CP2108: + ret = usbh_cp210x_control_in(serial, CP210X_VENDOR_SPECIFIC, CP210X_GET_FW_VER_2N, serial->intf, version, 3); + if (ret < 0) { + return ret; + } + cp210x_class->fw_version = version[0] << 16 | version[1] << 8 | version[2]; + break; + case CP210X_PARTNUM_CP2102N_QFN28: + case CP210X_PARTNUM_CP2102N_QFN24: + case CP210X_PARTNUM_CP2102N_QFN20: + ret = usbh_cp210x_control_in(serial, CP210X_VENDOR_SPECIFIC, CP210X_GET_FW_VER_2N, serial->intf, version, 3); + if (ret < 0) { + return ret; + } + cp210x_class->fw_version = version[0] << 16 | version[1] << 8 | version[2]; + if (cp210x_class->fw_version <= 0x10004) + cp210x_class->no_flow_control = true; + break; + default: + break; + } + return ret; +} + +static int usbh_cp210x_enable(struct usbh_serial *serial) +{ + return usbh_cp210x_control_out(serial, CP210X_IFC_ENABLE, 1, serial->intf, NULL, 0); +} + +static int usbh_cp210x_set_chars(struct usbh_serial *serial) +{ + struct cp210x_special_chars chars = { 0 }; + + return usbh_cp210x_control_out(serial, CP210X_SET_CHARS, 0, serial->intf, (uint8_t *)&chars, sizeof(struct cp210x_special_chars)); +} + +// static int usbh_cp210x_get_common_status(struct usbh_serial *serial, struct cp210x_comm_status *status) +// { +// return usbh_cp210x_control_in(serial, CP210X_GET_COMM_STATUS, 0, serial->intf, (uint8_t *)status, sizeof(struct cp210x_comm_status)); +// } + +static int usbh_cp210x_set_baudrate(struct usbh_serial *serial, uint32_t baudrate) +{ + struct usb_setup_packet *setup; + struct usbh_cp210x *cp210x_class; + + if (!serial || !serial->hport || !serial->priv) { + return -USB_ERR_INVAL; + } + setup = serial->hport->setup; + cp210x_class = (struct usbh_cp210x *)serial->priv; + + setup->bmRequestType = USB_REQUEST_DIR_OUT | USB_REQUEST_VENDOR | USB_REQUEST_RECIPIENT_INTERFACE; + setup->bRequest = CP210X_SET_BAUDRATE; + setup->wValue = 0; + setup->wIndex = serial->intf; + setup->wLength = 4; + + if (cp210x_class->use_actual_rate) + baudrate = cp210x_get_actual_rate(baudrate); + else if (baudrate < 1000000) + baudrate = cp210x_get_an205_rate(baudrate); + + memcpy(serial->iobuffer, (uint8_t *)&baudrate, 4); + return usbh_control_transfer(serial->hport, setup, serial->iobuffer); +} + +static int usbh_cp210x_set_data_format(struct usbh_serial *serial, uint8_t databits, uint8_t parity, uint8_t stopbits) +{ + struct usb_setup_packet *setup; + uint16_t value; + + if (!serial || !serial->hport) { + return -USB_ERR_INVAL; + } + setup = serial->hport->setup; + + value = ((databits & 0x0F) << 8) | ((parity & 0x0f) << 4) | ((stopbits & 0x03) << 0); + + setup->bmRequestType = USB_REQUEST_DIR_OUT | USB_REQUEST_VENDOR | USB_REQUEST_RECIPIENT_INTERFACE; + setup->bRequest = CP210X_SET_LINE_CTL; + setup->wValue = value; + setup->wIndex = serial->intf; + setup->wLength = 0; + + return usbh_control_transfer(serial->hport, setup, NULL); +} + +static int usbh_cp210x_attach(struct usbh_serial *serial) +{ + int ret; + + struct usbh_cp210x *cp210x_class = usb_osal_malloc(sizeof(struct usbh_cp210x)); + if (!cp210x_class) { + return -USB_ERR_NOMEM; + } + memset(cp210x_class, 0, sizeof(struct usbh_cp210x)); + serial->priv = cp210x_class; + + ret = usbh_cp210x_get_partnum(serial); + usbh_cp210x_init_max_speed(serial); + ret |= usbh_cp210x_enable(serial); + ret |= usbh_cp210x_set_chars(serial); + if (ret < 0) { + goto errout; + } + return 0; +errout: + serial->priv = NULL; + usb_osal_free(cp210x_class); + return ret; +} + +static void usbh_cp210x_detach(struct usbh_serial *serial) +{ + if (serial && serial->priv) { + serial->priv = NULL; + usb_osal_free(serial->priv); + } +} + +int usbh_cp210x_set_flow_ctrl(struct usbh_serial *serial, bool enable) +{ + struct cp210x_flow_ctl flow_ctl = { 0 }; + uint32_t flow_repl; + uint32_t ctl_hs; + int ret; + + ret = usbh_cp210x_control_in(serial, CP210X_GET_FLOW, 0, serial->intf, (uint8_t *)&flow_ctl, sizeof(struct cp210x_flow_ctl)); + if (ret < 0) { + return ret; + } + + ctl_hs = flow_ctl.lControlHandshake; + flow_repl = flow_ctl.lFlowReplace; + + ctl_hs &= ~CP210X_SERIAL_DSR_HANDSHAKE; + ctl_hs &= ~CP210X_SERIAL_DCD_HANDSHAKE; + ctl_hs &= ~CP210X_SERIAL_DSR_SENSITIVITY; + ctl_hs &= ~CP210X_SERIAL_DTR_MASK; + ctl_hs |= CP210X_SERIAL_DTR_INACTIVE; + + flow_repl &= ~CP210X_SERIAL_RTS_MASK; + flow_repl &= ~CP210X_SERIAL_AUTO_RECEIVE; + flow_repl &= ~CP210X_SERIAL_AUTO_TRANSMIT; + flow_repl |= CP210X_SERIAL_RTS_INACTIVE; + + flow_repl &= ~CP210X_SERIAL_RTS_MASK; + if (enable) { + ctl_hs |= CP210X_SERIAL_CTS_HANDSHAKE; + } else { + ctl_hs &= ~CP210X_SERIAL_CTS_HANDSHAKE; + } + flow_ctl.lControlHandshake = ctl_hs; + flow_ctl.lFlowReplace = flow_repl; + + return usbh_cp210x_control_out(serial, CP210X_SET_FLOW, 0, serial->intf, (uint8_t *)&flow_ctl, sizeof(struct cp210x_flow_ctl)); +} + +int usbh_cp210x_set_line_coding(struct usbh_serial *serial, struct cdc_line_coding *line_coding) +{ + int ret; + + ret = usbh_cp210x_set_baudrate(serial, line_coding->dwDTERate); + if (ret < 0) { + return ret; + } + return usbh_cp210x_set_data_format(serial, line_coding->bDataBits, line_coding->bParityType, line_coding->bCharFormat); +} + +int usbh_cp210x_set_line_state(struct usbh_serial *serial, bool dtr, bool rts) +{ + struct cp210x_flow_ctl flow_ctl = { 0 }; + uint32_t flow_repl; + uint32_t ctl_hs; + uint16_t control = 0; + int ret; + + if (!serial || !serial->hport || !serial->priv) { + return -USB_ERR_INVAL; + } + + if (serial->rtscts) { + ret = usbh_cp210x_control_in(serial, CP210X_GET_FLOW, 0, serial->intf, (uint8_t *)&flow_ctl, sizeof(struct cp210x_flow_ctl)); + if (ret < 0) { + return ret; + } + ctl_hs = flow_ctl.lControlHandshake; + flow_repl = flow_ctl.lFlowReplace; + + ctl_hs &= ~CP210X_SERIAL_DTR_MASK; + if (dtr) + ctl_hs |= CP210X_SERIAL_DTR_ACTIVE; + else + ctl_hs |= CP210X_SERIAL_DTR_INACTIVE; + + flow_repl &= ~CP210X_SERIAL_RTS_MASK; + if (rts) + flow_repl |= CP210X_SERIAL_RTS_FLOW_CTL; + else + flow_repl |= CP210X_SERIAL_RTS_INACTIVE; + + flow_ctl.lControlHandshake = ctl_hs; + flow_ctl.lFlowReplace = flow_repl; + + return usbh_cp210x_control_out(serial, CP210X_SET_FLOW, 0, serial->intf, (uint8_t *)&flow_ctl, sizeof(struct cp210x_flow_ctl)); + } else { + if (dtr) { + control |= CP210X_CONTROL_DTR; + } + if (rts) { + control |= CP210X_CONTROL_RTS; + } + control |= CP210X_CONTROL_WRITE_DTR; + control |= CP210X_CONTROL_WRITE_RTS; + return usbh_cp210x_control_out(serial, CP210X_SET_MHS, control, serial->intf, NULL, 0); + } +} + +static int usbh_cp210x_get_modem_status(struct usbh_serial *serial) +{ + int ret; + uint8_t control; + uint16_t status; + + if (!serial || !serial->hport) { + return -USB_ERR_INVAL; + } + + ret = usbh_cp210x_control_in(serial, CP210X_GET_MDMSTS, 0, serial->intf, (uint8_t *)&control, 1); + if (ret < 0) { + return ret; + } + + status = ((control & CP210X_CONTROL_DTR) ? USBH_SERIAL_TIOCM_DTR : 0) | + ((control & CP210X_CONTROL_RTS) ? USBH_SERIAL_TIOCM_RTS : 0) | + ((control & CP210X_CONTROL_CTS) ? USBH_SERIAL_TIOCM_CTS : 0) | + ((control & CP210X_CONTROL_DSR) ? USBH_SERIAL_TIOCM_DSR : 0) | + ((control & CP210X_CONTROL_RING) ? USBH_SERIAL_TIOCM_RI : 0) | + ((control & CP210X_CONTROL_DCD) ? USBH_SERIAL_TIOCM_CD : 0); + + return status; +} + +static const struct usbh_serial_driver cp210x_driver = { + .driver_name = "cp210x", + + .ignore_rx_header = 0, + .ignore_tx_header = 0, + + .attach = usbh_cp210x_attach, + .detach = usbh_cp210x_detach, + .set_flow_control = usbh_cp210x_set_flow_ctrl, + .set_line_coding = usbh_cp210x_set_line_coding, + .get_line_coding = NULL, + .set_line_state = usbh_cp210x_set_line_state, + .get_modem_status = usbh_cp210x_get_modem_status, +}; + +static int usbh_cp210x_connect(struct usbh_hubport *hport, uint8_t intf) +{ + return usbh_serial_probe(hport, intf, &cp210x_driver) ? 0 : -USB_ERR_NOMEM; +} + +static int usbh_cp210x_disconnect(struct usbh_hubport *hport, uint8_t intf) +{ + struct usbh_serial *serial = (struct usbh_serial *)hport->config.intf[intf].priv; + + if (serial) { + usbh_serial_remove(serial); + } + return 0; +} + +static const uint16_t cp210x_id_table[][2] = { + { 0x10C4, 0xEA60 }, + { 0, 0 }, +}; + +const struct usbh_class_driver cp210x_class_driver = { + .driver_name = "cp210x", + .connect = usbh_cp210x_connect, + .disconnect = usbh_cp210x_disconnect +}; + +CLASS_INFO_DEFINE const struct usbh_class_info cp210x_class_info = { + .match_flags = USB_CLASS_MATCH_VID_PID | USB_CLASS_MATCH_INTF_CLASS, + .bInterfaceClass = 0xff, + .bInterfaceSubClass = 0x00, + .bInterfaceProtocol = 0x00, + .id_table = cp210x_id_table, + .class_driver = &cp210x_class_driver +}; \ No newline at end of file diff --git a/kernel/cherryusb/class/serial/usbh_cp210x.h b/kernel/cherryusb/class/serial/usbh_cp210x.h new file mode 100644 index 0000000..6bd0206 --- /dev/null +++ b/kernel/cherryusb/class/serial/usbh_cp210x.h @@ -0,0 +1,187 @@ +/* + * Copyright (c) 2024 ~ 2025, sakumisu + * + * SPDX-License-Identifier: Apache-2.0 + */ +#ifndef USBH_CP210X_H +#define USBH_CP210X_H + +#include "usb_cdc.h" + +/* Requests */ +#define CP210X_IFC_ENABLE 0x00 +#define CP210X_SET_BAUDDIV 0x01 +#define CP210X_GET_BAUDDIV 0x02 +#define CP210X_SET_LINE_CTL 0x03 // Set parity, data bits, stop bits +#define CP210X_GET_LINE_CTL 0x04 +#define CP210X_SET_BREAK 0x05 +#define CP210X_IMM_CHAR 0x06 +#define CP210X_SET_MHS 0x07 // Set DTR, RTS +#define CP210X_GET_MDMSTS 0x08 +#define CP210X_SET_XON 0x09 +#define CP210X_SET_XOFF 0x0A +#define CP210X_SET_EVENTMASK 0x0B +#define CP210X_GET_EVENTMASK 0x0C +#define CP210X_SET_CHAR 0x0D +#define CP210X_GET_CHARS 0x0E +#define CP210X_GET_PROPS 0x0F +#define CP210X_GET_COMM_STATUS 0x10 +#define CP210X_RESET 0x11 +#define CP210X_PURGE 0x12 +#define CP210X_SET_FLOW 0x13 +#define CP210X_GET_FLOW 0x14 +#define CP210X_EMBED_EVENTS 0x15 +#define CP210X_GET_EVENTSTATE 0x16 +#define CP210X_SET_CHARS 0x19 +#define CP210X_GET_BAUDRATE 0x1D +#define CP210X_SET_BAUDRATE 0x1E // Set baudrate +#define CP210X_VENDOR_SPECIFIC 0xFF + +/* CP210X_VENDOR_SPECIFIC values */ +#define CP210X_GET_FW_VER 0x000E +#define CP210X_READ_2NCONFIG 0x000E +#define CP210X_GET_FW_VER_2N 0x0010 +#define CP210X_READ_LATCH 0x00C2 +#define CP210X_GET_PARTNUM 0x370B +#define CP210X_GET_PORTCONFIG 0x370C +#define CP210X_GET_DEVICEMODE 0x3711 +#define CP210X_WRITE_LATCH 0x37E1 + +/* CP210X_IFC_ENABLE */ +#define CP210X_UART_ENABLE 0x0001 +#define CP210X_UART_DISABLE 0x0000 + +/* CP210X_(SET|GET)_BAUDDIV */ +#define CP210X_BAUD_RATE_GEN_FREQ 0x384000 + +/* CP210X_(SET|GET)_LINE_CTL */ +#define CP210X_BITS_DATA_MASK 0X0f00 +#define CP210X_BITS_DATA_5 0X0500 +#define CP210X_BITS_DATA_6 0X0600 +#define CP210X_BITS_DATA_7 0X0700 +#define CP210X_BITS_DATA_8 0X0800 +#define CP210X_BITS_DATA_9 0X0900 + +#define CP210X_BITS_PARITY_MASK 0x00f0 +#define CP210X_BITS_PARITY_NONE 0x0000 +#define CP210X_BITS_PARITY_ODD 0x0010 +#define CP210X_BITS_PARITY_EVEN 0x0020 +#define CP210X_BITS_PARITY_MARK 0x0030 +#define CP210X_BITS_PARITY_SPACE 0x0040 + +#define CP210X_BITS_STOP_MASK 0x000f +#define CP210X_BITS_STOP_1 0x0000 +#define CP210X_BITS_STOP_1_5 0x0001 +#define CP210X_BITS_STOP_2 0x0002 + +/* CP210X_SET_BREAK */ +#define CP210X_BREAK_ON 0x0001 +#define CP210X_BREAK_OFF 0x0000 + +/* CP210X_(SET_MHS|GET_MDMSTS) */ +#define CP210X_CONTROL_DTR 0x0001 +#define CP210X_CONTROL_RTS 0x0002 +#define CP210X_CONTROL_CTS 0x0010 +#define CP210X_CONTROL_DSR 0x0020 +#define CP210X_CONTROL_RING 0x0040 +#define CP210X_CONTROL_DCD 0x0080 +#define CP210X_CONTROL_WRITE_DTR 0x0100 +#define CP210X_CONTROL_WRITE_RTS 0x0200 + +/* CP210X_(GET|SET)_CHARS */ +struct cp210x_special_chars { + uint8_t bEofChar; + uint8_t bErrorChar; + uint8_t bBreakChar; + uint8_t bEventChar; + uint8_t bXonChar; + uint8_t bXoffChar; +}; + +/* CP210X_GET_COMM_STATUS returns these 0x13 bytes */ +struct cp210x_comm_status { + uint32_t ulErrors; + uint32_t ulHoldReasons; + uint32_t ulAmountInInQueue; + uint32_t ulAmountInOutQueue; + uint8_t bEofReceived; + uint8_t bWaitForImmediate; + uint8_t bReserved; +} __PACKED; + +/* + * CP210X_PURGE - 16 bits passed in wValue of USB request. + * SiLabs app note AN571 gives a strange description of the 4 bits: + * bit 0 or bit 2 clears the transmit queue and 1 or 3 receive. + * writing 1 to all, however, purges cp2108 well enough to avoid the hang. + */ +#define PURGE_ALL 0x000f + +/* CP210X_EMBED_EVENTS */ +#define CP210X_ESCCHAR 0xec + +#define CP210X_LSR_OVERRUN BIT(1) +#define CP210X_LSR_PARITY BIT(2) +#define CP210X_LSR_FRAME BIT(3) +#define CP210X_LSR_BREAK BIT(4) + +/* CP210X_GET_FLOW/CP210X_SET_FLOW read/write these 0x10 bytes */ +struct cp210x_flow_ctl { + uint32_t lControlHandshake; + uint32_t lFlowReplace; + uint32_t lXonLimit; + uint32_t lXoffLimit; +}; + +/* cp210x_flow_ctl::ulControlHandshake */ +#define CP210X_SERIAL_DTR_MASK (0x03 << 0) +#define CP210X_SERIAL_DTR_INACTIVE (0 << 0) +#define CP210X_SERIAL_DTR_ACTIVE (1 << 0) +#define CP210X_SERIAL_DTR_FLOW_CTL (2 << 0) +#define CP210X_SERIAL_CTS_HANDSHAKE BIT(3) +#define CP210X_SERIAL_DSR_HANDSHAKE BIT(4) +#define CP210X_SERIAL_DCD_HANDSHAKE BIT(5) +#define CP210X_SERIAL_DSR_SENSITIVITY BIT(6) + +/* cp210x_flow_ctl::ulFlowReplace */ +#define CP210X_SERIAL_AUTO_TRANSMIT BIT(0) +#define CP210X_SERIAL_AUTO_RECEIVE BIT(1) +#define CP210X_SERIAL_ERROR_CHAR BIT(2) +#define CP210X_SERIAL_NULL_STRIPPING BIT(3) +#define CP210X_SERIAL_BREAK_CHAR BIT(4) +#define CP210X_SERIAL_RTS_MASK (0x03 << 6) +#define CP210X_SERIAL_RTS_INACTIVE (0 << 6) +#define CP210X_SERIAL_RTS_ACTIVE (1 << 6) +#define CP210X_SERIAL_RTS_FLOW_CTL (2 << 6) +#define CP210X_SERIAL_XOFF_CONTINUE BIT(31) + +/* CP210X_VENDOR_SPECIFIC, CP210X_GET_DEVICEMODE call reads these 0x2 bytes. */ +struct cp210x_pin_mode { + uint8_t eci; + uint8_t sci; +}; + +#define CP210X_PIN_MODE_MODEM 0 +#define CP210X_PIN_MODE_GPIO BIT(0) + +/* Part number definitions */ +#define CP210X_PARTNUM_CP2101 0x01 +#define CP210X_PARTNUM_CP2102 0x02 +#define CP210X_PARTNUM_CP2103 0x03 +#define CP210X_PARTNUM_CP2104 0x04 +#define CP210X_PARTNUM_CP2105 0x05 +#define CP210X_PARTNUM_CP2108 0x08 +#define CP210X_PARTNUM_CP2102N_QFN28 0x20 +#define CP210X_PARTNUM_CP2102N_QFN24 0x21 +#define CP210X_PARTNUM_CP2102N_QFN20 0x22 +#define CP210X_PARTNUM_UNKNOWN 0xFF + +#ifdef __cplusplus +extern "C" { +#endif + +#ifdef __cplusplus +} +#endif + +#endif /* USBH_CP210X_H */ diff --git a/kernel/cherryusb/class/serial/usbh_ftdi.c b/kernel/cherryusb/class/serial/usbh_ftdi.c new file mode 100644 index 0000000..c2d3a77 --- /dev/null +++ b/kernel/cherryusb/class/serial/usbh_ftdi.c @@ -0,0 +1,407 @@ +/* + * Copyright (c) 2024 ~ 2025, sakumisu + * + * SPDX-License-Identifier: Apache-2.0 + */ +#include "usbh_core.h" +#include "usbh_serial.h" +#include "usbh_ftdi.h" + +#undef USB_DBG_TAG +#define USB_DBG_TAG "usbh_ftdi" +#include "usb_log.h" + +enum ftdi_chip_type { + SIO, + FT232A, + FT232B, + FT2232C, + FT232R, + FT232H, + FT2232H, + FT4232H, + FT4232HA, + FT232HP, + FT233HP, + FT2232HP, + FT2233HP, + FT4232HP, + FT4233HP, + FTX, +}; + +static const char *ftdi_chip_name[] = { + [SIO] = "SIO", /* the serial part of FT8U100AX */ + [FT232A] = "FT232A", + [FT232B] = "FT232B", + [FT2232C] = "FT2232C/D", + [FT232R] = "FT232R", + [FT232H] = "FT232H", + [FT2232H] = "FT2232H", + [FT4232H] = "FT4232H", + [FT4232HA] = "FT4232HA", + [FT232HP] = "FT232HP", + [FT233HP] = "FT233HP", + [FT2232HP] = "FT2232HP", + [FT2233HP] = "FT2233HP", + [FT4232HP] = "FT4232HP", + [FT4233HP] = "FT4233HP", + [FTX] = "FT-X", +}; + +struct usbh_ftdi { + enum ftdi_chip_type chip_type; +}; + +static uint32_t ftdi_232bm_baud_base_to_divisor(uint32_t baud, int base) +{ + static const unsigned char divfrac[8] = { 0, 3, 2, 4, 1, 5, 6, 7 }; + uint32_t divisor; + /* divisor shifted 3 bits to the left */ + int divisor3 = DIV_ROUND_CLOSEST(base, 2 * baud); + divisor = divisor3 >> 3; + divisor |= (uint32_t)divfrac[divisor3 & 0x7] << 14; + /* Deal with special cases for highest baud rates. */ + if (divisor == 1) /* 1.0 */ + divisor = 0; + else if (divisor == 0x4001) /* 1.5 */ + divisor = 1; + return divisor; +} + +static uint32_t ftdi_232bm_baud_to_divisor(uint32_t baud) +{ + return ftdi_232bm_baud_base_to_divisor(baud, 48000000); +} + +static uint32_t ftdi_2232h_baud_base_to_divisor(uint32_t baud, int base) +{ + static const unsigned char divfrac[8] = { 0, 3, 2, 4, 1, 5, 6, 7 }; + uint32_t divisor; + int divisor3; + + /* hi-speed baud rate is 10-bit sampling instead of 16-bit */ + divisor3 = DIV_ROUND_CLOSEST(8 * base, 10 * baud); + + divisor = divisor3 >> 3; + divisor |= (uint32_t)divfrac[divisor3 & 0x7] << 14; + /* Deal with special cases for highest baud rates. */ + if (divisor == 1) /* 1.0 */ + divisor = 0; + else if (divisor == 0x4001) /* 1.5 */ + divisor = 1; + /* + * Set this bit to turn off a divide by 2.5 on baud rate generator + * This enables baud rates up to 12Mbaud but cannot reach below 1200 + * baud with this bit set + */ + divisor |= 0x00020000; + return divisor; +} + +static uint32_t ftdi_2232h_baud_to_divisor(uint32_t baud) +{ + return ftdi_2232h_baud_base_to_divisor(baud, 120000000); +} + +int usbh_ftdi_reset(struct usbh_serial *serial) +{ + struct usb_setup_packet *setup; + + if (!serial || !serial->hport) { + return -USB_ERR_INVAL; + } + setup = serial->hport->setup; + + setup->bmRequestType = USB_REQUEST_DIR_OUT | USB_REQUEST_VENDOR | USB_REQUEST_RECIPIENT_DEVICE; + setup->bRequest = FTDI_SIO_RESET; + setup->wValue = 0; + setup->wIndex = serial->intf; + setup->wLength = 0; + + return usbh_control_transfer(serial->hport, setup, NULL); +} + +static int usbh_ftdi_set_baudrate(struct usbh_serial *serial, uint32_t baudrate) +{ + struct usb_setup_packet *setup; + struct usbh_ftdi *ftdi_class; + uint32_t div_value; + uint16_t value; + uint8_t baudrate_high; + + if (!serial || !serial->hport || !serial->priv) { + return -USB_ERR_INVAL; + } + setup = serial->hport->setup; + ftdi_class = (struct usbh_ftdi *)serial->priv; + + switch (ftdi_class->chip_type) { + case FT232B: + case FT2232C: + case FT232R: + if (baudrate > 3000000) { + return -USB_ERR_INVAL; + } + div_value = ftdi_232bm_baud_to_divisor(baudrate); + break; + default: + if ((baudrate <= 12000000) && (baudrate >= 1200)) { + div_value = ftdi_2232h_baud_to_divisor(baudrate); + } else if (baudrate < 1200) { + div_value = ftdi_232bm_baud_to_divisor(baudrate); + } else { + return -USB_ERR_INVAL; + } + break; + } + + value = div_value & 0xFFFF; + baudrate_high = (div_value >> 16) & 0xff; + + setup->bmRequestType = USB_REQUEST_DIR_OUT | USB_REQUEST_VENDOR | USB_REQUEST_RECIPIENT_DEVICE; + setup->bRequest = FTDI_SIO_SET_BAUDRATE; + setup->wValue = value; + setup->wIndex = (baudrate_high << 8) | serial->intf; + setup->wLength = 0; + + return usbh_control_transfer(serial->hport, setup, NULL); +} + +static int usbh_ftdi_set_data_format(struct usbh_serial *serial, uint8_t databits, uint8_t parity, uint8_t stopbits, uint8_t isbreak) +{ + /** + * D0-D7 databits BITS_7=7, BITS_8=8 + * D8-D10 parity NONE=0, ODD=1, EVEN=2, MARK=3, SPACE=4 + * D11-D12 STOP_BIT_1=0, STOP_BIT_15=1, STOP_BIT_2=2 + * D14 BREAK_OFF=0, BREAK_ON=1 + **/ + struct usb_setup_packet *setup; + uint16_t value; + + if (!serial || !serial->hport) { + return -USB_ERR_INVAL; + } + setup = serial->hport->setup; + + value = ((isbreak & 0x01) << 14) | ((stopbits & 0x03) << 11) | ((parity & 0x0f) << 8) | (databits & 0x0f); + + setup->bmRequestType = USB_REQUEST_DIR_OUT | USB_REQUEST_VENDOR | USB_REQUEST_RECIPIENT_DEVICE; + setup->bRequest = FTDI_SIO_SET_DATA; + setup->wValue = value; + setup->wIndex = serial->intf; + setup->wLength = 0; + + return usbh_control_transfer(serial->hport, setup, NULL); +} + +static int usbh_ftdi_set_latency_timer(struct usbh_serial *serial, uint16_t value) +{ + struct usb_setup_packet *setup; + + if (!serial || !serial->hport) { + return -USB_ERR_INVAL; + } + setup = serial->hport->setup; + + setup->bmRequestType = USB_REQUEST_DIR_OUT | USB_REQUEST_VENDOR | USB_REQUEST_RECIPIENT_DEVICE; + setup->bRequest = FTDI_SIO_SET_LATENCY_TIMER; + setup->wValue = value; + setup->wIndex = serial->intf; + setup->wLength = 0; + + return usbh_control_transfer(serial->hport, setup, NULL); +} + +static int usbh_ftdi_attach(struct usbh_serial *serial) +{ + uint16_t version; + uint8_t chip_type; + int ret; + + version = serial->hport->device_desc.bcdDevice; + + switch (version) { + case 0x400: + chip_type = FT232B; + break; + case 0x500: + chip_type = FT2232C; + break; + case 0x600: + chip_type = FT232R; + break; + case 0x700: + chip_type = FT2232H; + break; + case 0x900: + chip_type = FT232H; + break; + + default: + USB_LOG_ERR("Unsupported FTDI chip version: 0x%04x\r\n", version); + return -USB_ERR_NOTSUPP; + } + + USB_LOG_INFO("chip name: %s\r\n", ftdi_chip_name[chip_type]); + + struct usbh_ftdi *ftdi_class = usb_osal_malloc(sizeof(struct usbh_ftdi)); + if (!ftdi_class) { + USB_LOG_ERR("No memory for ftdi_class\r\n"); + return -USB_ERR_NOMEM; + } + memset(ftdi_class, 0, sizeof(struct usbh_ftdi)); + serial->priv = ftdi_class; + + ftdi_class->chip_type = chip_type; + ret = usbh_ftdi_set_latency_timer(serial, 0x10); + if (ret < 0) { + goto errout; + } + return 0; +errout: + serial->priv = NULL; + usb_osal_free(ftdi_class); + return ret; +} + +static void usbh_ftdi_detach(struct usbh_serial *serial) +{ + if (serial && serial->priv) { + serial->priv = NULL; + usb_osal_free(serial->priv); + } +} + +static int usbh_ftdi_set_flow_ctrl(struct usbh_serial *serial, bool hardctrl) +{ + struct usb_setup_packet *setup; + + if (!serial || !serial->hport) { + return -USB_ERR_INVAL; + } + setup = serial->hport->setup; + + setup->bmRequestType = USB_REQUEST_DIR_OUT | USB_REQUEST_VENDOR | USB_REQUEST_RECIPIENT_DEVICE; + setup->bRequest = FTDI_SIO_SET_FLOW_CTRL; + setup->wValue = hardctrl ? FTDI_SIO_RTS_CTS_HS : FTDI_SIO_DISABLE_FLOW_CTRL; + setup->wIndex = serial->intf; + setup->wLength = 0; + + return usbh_control_transfer(serial->hport, setup, NULL); +} + +static int usbh_ftdi_set_line_coding(struct usbh_serial *serial, struct cdc_line_coding *line_coding) +{ + int ret = usbh_ftdi_set_baudrate(serial, line_coding->dwDTERate); + if (ret < 0) { + return ret; + } + return usbh_ftdi_set_data_format(serial, line_coding->bDataBits, line_coding->bParityType, line_coding->bCharFormat, 0); +} + +static int usbh_ftdi_set_line_state(struct usbh_serial *serial, bool dtr, bool rts) +{ + struct usb_setup_packet *setup; + uint16_t value = 0; + + if (!serial || !serial->hport) { + return -USB_ERR_INVAL; + } + setup = serial->hport->setup; + + value = ((dtr ? FTDI_SIO_SET_DTR_HIGH : FTDI_SIO_SET_DTR_LOW) | (rts ? FTDI_SIO_SET_RTS_HIGH : FTDI_SIO_SET_RTS_LOW)); + + setup->bmRequestType = USB_REQUEST_DIR_OUT | USB_REQUEST_VENDOR | USB_REQUEST_RECIPIENT_DEVICE; + setup->bRequest = FTDI_SIO_SET_MODEM_CTRL; + setup->wValue = value; + setup->wIndex = serial->intf; + setup->wLength = 0; + + return usbh_control_transfer(serial->hport, setup, NULL); +} + +static int usbh_ftdi_get_modem_status(struct usbh_serial *serial) +{ + struct usb_setup_packet *setup; + uint16_t status = 0; + int ret; + + if (!serial || !serial->hport) { + return -USB_ERR_INVAL; + } + + setup = serial->hport->setup; + + setup->bmRequestType = USB_REQUEST_DIR_IN | USB_REQUEST_VENDOR | USB_REQUEST_RECIPIENT_DEVICE; + setup->bRequest = FTDI_SIO_GET_MODEM_STATUS; + setup->wValue = 0x0000; + setup->wIndex = serial->intf; + setup->wLength = 2; + + ret = usbh_control_transfer(serial->hport, setup, serial->iobuffer); + if (ret < 0) { + return 0; + } + + status = (serial->iobuffer[0] & FTDI_SIO_DSR_MASK ? USBH_SERIAL_TIOCM_DSR : 0) | + (serial->iobuffer[0] & FTDI_SIO_CTS_MASK ? USBH_SERIAL_TIOCM_CTS : 0) | + (serial->iobuffer[0] & FTDI_SIO_RI_MASK ? USBH_SERIAL_TIOCM_RI : 0) | + (serial->iobuffer[0] & FTDI_SIO_RLSD_MASK ? USBH_SERIAL_TIOCM_CD : 0) | + (serial->line_state & USBH_SERIAL_TIOCM_DTR ? USBH_SERIAL_TIOCM_DTR : 0) | + (serial->line_state & USBH_SERIAL_TIOCM_RTS ? USBH_SERIAL_TIOCM_RTS : 0); + + return status; +} + +static const struct usbh_serial_driver ftdi_driver = { + .driver_name = "ftdi", + + .ignore_rx_header = 2, + .ignore_tx_header = 0, + + .attach = usbh_ftdi_attach, + .detach = usbh_ftdi_detach, + .set_flow_control = usbh_ftdi_set_flow_ctrl, + .set_line_coding = usbh_ftdi_set_line_coding, + .get_line_coding = NULL, + .set_line_state = usbh_ftdi_set_line_state, + .get_modem_status = usbh_ftdi_get_modem_status, +}; + +static int usbh_ftdi_connect(struct usbh_hubport *hport, uint8_t intf) +{ + return usbh_serial_probe(hport, intf, &ftdi_driver) ? 0 : -USB_ERR_NOMEM; +} + +static int usbh_ftdi_disconnect(struct usbh_hubport *hport, uint8_t intf) +{ + struct usbh_serial *serial = (struct usbh_serial *)hport->config.intf[intf].priv; + + if (serial) { + usbh_serial_remove(serial); + } + return 0; +} + +static const uint16_t ftdi_id_table[][2] = { + { 0x0403, 0x6001 }, + { 0x0403, 0x6010 }, + { 0x0403, 0x6014 }, + { 0, 0 }, +}; + +const struct usbh_class_driver ftdi_class_driver = { + .driver_name = "ftdi", + .connect = usbh_ftdi_connect, + .disconnect = usbh_ftdi_disconnect +}; + +CLASS_INFO_DEFINE const struct usbh_class_info ftdi_class_info = { + .match_flags = USB_CLASS_MATCH_VID_PID | USB_CLASS_MATCH_INTF_CLASS, + .bInterfaceClass = 0xff, + .bInterfaceSubClass = 0x00, + .bInterfaceProtocol = 0x00, + .id_table = ftdi_id_table, + .class_driver = &ftdi_class_driver +}; diff --git a/kernel/cherryusb/class/serial/usbh_ftdi.h b/kernel/cherryusb/class/serial/usbh_ftdi.h new file mode 100644 index 0000000..0d17629 --- /dev/null +++ b/kernel/cherryusb/class/serial/usbh_ftdi.h @@ -0,0 +1,341 @@ +/* + * Copyright (c) 2024 ~ 2025, sakumisu + * + * SPDX-License-Identifier: Apache-2.0 + */ +#ifndef USBH_FTDI_H +#define USBH_FTDI_H + +#include "usb_cdc.h" + +#define FTDI_VID 0x0403 /* Vendor Id */ + +/* FTDI device PIDs */ +#define FTDI_8U232AM_PID 0x6001 /* Similar device to SIO above */ +#define FTDI_8U232AM_ALT_PID 0x6006 /* FTDI's alternate PID for above */ +#define FTDI_8U2232C_PID 0x6010 /* Dual channel device */ +#define FTDI_4232H_PID 0x6011 /* Quad channel hi-speed device */ +#define FTDI_232H_PID 0x6014 /* Single channel hi-speed device */ +#define FTDI_FTX_PID 0x6015 /* FT-X series (FT201X, FT230X, FT231X, etc) */ +#define FTDI_FT2233HP_PID 0x6040 /* Dual channel hi-speed device with PD */ +#define FTDI_FT4233HP_PID 0x6041 /* Quad channel hi-speed device with PD */ +#define FTDI_FT2232HP_PID 0x6042 /* Dual channel hi-speed device with PD */ +#define FTDI_FT4232HP_PID 0x6043 /* Quad channel hi-speed device with PD */ +#define FTDI_FT233HP_PID 0x6044 /* Dual channel hi-speed device with PD */ +#define FTDI_FT232HP_PID 0x6045 /* Dual channel hi-speed device with PD */ +#define FTDI_FT4232HA_PID 0x6048 /* Quad channel automotive grade hi-speed device */ +#define FTDI_SIO_PID 0x8372 /* Product Id SIO application of 8U100AX */ +#define FTDI_232RL_PID 0xFBFA /* Product ID for FT232RL */ + +/* Requests */ +#define FTDI_SIO_RESET 0x00 /* Reset the port */ +#define FTDI_SIO_SET_MODEM_CTRL 0x01 /* Set the modem control register */ +#define FTDI_SIO_SET_FLOW_CTRL 0x02 /* Set flow control register */ +#define FTDI_SIO_SET_BAUDRATE 0x03 /* Set baud rate */ +#define FTDI_SIO_SET_DATA 0x04 /* Set the data characteristics of the port */ +#define FTDI_SIO_GET_MODEM_STATUS 0x05 +#define FTDI_SIO_SET_EVENT_CHAR 0x06 +#define FTDI_SIO_SET_ERROR_CHAR 0x07 +#define FTDI_SIO_SET_LATENCY_TIMER 0x09 +#define FTDI_SIO_GET_LATENCY_TIMER 0x0A +#define FTDI_SIO_SET_BITMODE 0x0B +#define FTDI_SIO_READ_PINS 0x0C +#define FTDI_SIO_READ_EEPROM 0x90 +#define FTDI_SIO_WRITE_EEPROM 0x91 +#define FTDI_SIO_ERASE_EEPROM 0x92 + +/* Channel indices for FT2232, FT2232H and FT4232H devices */ +#define FTDI_SIO_CHANNEL_A 1 +#define FTDI_SIO_CHANNEL_B 2 +#define FTDI_SIO_CHANNEL_C 3 +#define FTDI_SIO_CHANNEL_D 4 + +/* + * BmRequestType: 0100 0000B + * bRequest: FTDI_SIO_RESET + * wValue: Control Value + * 0 = Reset SIO + * 1 = Purge RX buffer + * 2 = Purge TX buffer + * wIndex: Port + * wLength: 0 + * Data: None + * + * The Reset SIO command has this effect: + * + * Sets flow control set to 'none' + * Event char = $0D + * Event trigger = disabled + * Purge RX buffer + * Purge TX buffer + * Clear DTR + * Clear RTS + * baud and data format not reset + * + * The Purge RX and TX buffer commands affect nothing except the buffers + * + */ + +#define FTDI_SIO_RESET_SIO 0 +#define FTDI_SIO_RESET_PURGE_RX 1 +#define FTDI_SIO_RESET_PURGE_TX 2 + +/* + * BmRequestType: 0100 0000B + * bRequest: FTDI_SIO_SET_BAUDRATE + * wValue: BaudDivisor value - see below + * wIndex: Port + * wLength: 0 + * Data: None + * The BaudDivisor values are calculated as follows: + * - BaseClock is either 12000000 or 48000000 depending on the device. + * FIXME: I wish I knew how to detect old chips to select proper base clock! + * - BaudDivisor is a fixed point number encoded in a funny way. + * (--WRONG WAY OF THINKING--) + * BaudDivisor is a fixed point number encoded with following bit weighs: + * (-2)(-1)(13..0). It is a radical with a denominator of 4, so values + * end with 0.0 (00...), 0.25 (10...), 0.5 (01...), and 0.75 (11...). + * (--THE REALITY--) + * The both-bits-set has quite different meaning from 0.75 - the chip + * designers have decided it to mean 0.125 instead of 0.75. + * This info looked up in FTDI application note "FT8U232 DEVICES \ Data Rates + * and Flow Control Consideration for USB to RS232". + * - BaudDivisor = (BaseClock / 16) / BaudRate, where the (=) operation should + * automagically re-encode the resulting value to take fractions into + * consideration. + * As all values are integers, some bit twiddling is in order: + * BaudDivisor = (BaseClock / 16 / BaudRate) | + * (((BaseClock / 2 / BaudRate) & 4) ? 0x4000 // 0.5 + * : ((BaseClock / 2 / BaudRate) & 2) ? 0x8000 // 0.25 + * : ((BaseClock / 2 / BaudRate) & 1) ? 0xc000 // 0.125 + * : 0) + * + * For the FT232BM, a 17th divisor bit was introduced to encode the multiples + * of 0.125 missing from the FT8U232AM. Bits 16 to 14 are coded as follows + * (the first four codes are the same as for the FT8U232AM, where bit 16 is + * always 0): + * 000 - add .000 to divisor + * 001 - add .500 to divisor + * 010 - add .250 to divisor + * 011 - add .125 to divisor + * 100 - add .375 to divisor + * 101 - add .625 to divisor + * 110 - add .750 to divisor + * 111 - add .875 to divisor + * Bits 15 to 0 of the 17-bit divisor are placed in the urb value. Bit 16 is + * placed in bit 0 of the urb index. + * + * Note that there are a couple of special cases to support the highest baud + * rates. If the calculated divisor value is 1, this needs to be replaced with + * 0. Additionally for the FT232BM, if the calculated divisor value is 0x4001 + * (1.5), this needs to be replaced with 0x0001 (1) (but this divisor value is + * not supported by the FT8U232AM). + */ + +enum ftdi_sio_baudrate { + ftdi_sio_b300 = 0, + ftdi_sio_b600 = 1, + ftdi_sio_b1200 = 2, + ftdi_sio_b2400 = 3, + ftdi_sio_b4800 = 4, + ftdi_sio_b9600 = 5, + ftdi_sio_b19200 = 6, + ftdi_sio_b38400 = 7, + ftdi_sio_b57600 = 8, + ftdi_sio_b115200 = 9 +}; + +/* + * BmRequestType: 0100 0000B + * bRequest: FTDI_SIO_SET_DATA + * wValue: Data characteristics (see below) + * wIndex: Port + * wLength: 0 + * Data: No + * + * Data characteristics + * + * B0..7 Number of data bits + * B8..10 Parity + * 0 = None + * 1 = Odd + * 2 = Even + * 3 = Mark + * 4 = Space + * B11..13 Stop Bits + * 0 = 1 + * 1 = 1.5 + * 2 = 2 + * B14 + * 1 = TX ON (break) + * 0 = TX OFF (normal state) + * B15 Reserved + * + */ + +#define FTDI_SIO_SET_DATA_PARITY_NONE (0x0 << 8) +#define FTDI_SIO_SET_DATA_PARITY_ODD (0x1 << 8) +#define FTDI_SIO_SET_DATA_PARITY_EVEN (0x2 << 8) +#define FTDI_SIO_SET_DATA_PARITY_MARK (0x3 << 8) +#define FTDI_SIO_SET_DATA_PARITY_SPACE (0x4 << 8) +#define FTDI_SIO_SET_DATA_STOP_BITS_1 (0x0 << 11) +#define FTDI_SIO_SET_DATA_STOP_BITS_15 (0x1 << 11) +#define FTDI_SIO_SET_DATA_STOP_BITS_2 (0x2 << 11) +#define FTDI_SIO_SET_BREAK (0x1 << 14) + +/* + * BmRequestType: 0100 0000B + * bRequest: FTDI_SIO_MODEM_CTRL + * wValue: ControlValue (see below) + * wIndex: Port + * wLength: 0 + * Data: None + * + * NOTE: If the device is in RTS/CTS flow control, the RTS set by this + * command will be IGNORED without an error being returned + * Also - you can not set DTR and RTS with one control message + * + * ControlValue + * B0 DTR state + * 0 = reset + * 1 = set + * B1 RTS state + * 0 = reset + * 1 = set + * B2..7 Reserved + * B8 DTR state enable + * 0 = ignore + * 1 = use DTR state + * B9 RTS state enable + * 0 = ignore + * 1 = use RTS state + * B10..15 Reserved + * + */ + +#define FTDI_SIO_SET_DTR_MASK 0x1 +#define FTDI_SIO_SET_DTR_HIGH ((FTDI_SIO_SET_DTR_MASK << 8) | 1) +#define FTDI_SIO_SET_DTR_LOW ((FTDI_SIO_SET_DTR_MASK << 8) | 0) +#define FTDI_SIO_SET_RTS_MASK 0x2 +#define FTDI_SIO_SET_RTS_HIGH ((FTDI_SIO_SET_RTS_MASK << 8) | 2) +#define FTDI_SIO_SET_RTS_LOW ((FTDI_SIO_SET_RTS_MASK << 8) | 0) + +/* + * BmRequestType: 0100 0000b + * bRequest: FTDI_SIO_SET_FLOW_CTRL + * wValue: Xoff/Xon + * wIndex: Protocol/Port - hIndex is protocol / lIndex is port + * wLength: 0 + * Data: None + * + * hIndex protocol is: + * B0 Output handshaking using RTS/CTS + * 0 = disabled + * 1 = enabled + * B1 Output handshaking using DTR/DSR + * 0 = disabled + * 1 = enabled + * B2 Xon/Xoff handshaking + * 0 = disabled + * 1 = enabled + * + * A value of zero in the hIndex field disables handshaking + * + * If Xon/Xoff handshaking is specified, the hValue field should contain the + * XOFF character and the lValue field contains the XON character. + */ + +#define FTDI_SIO_DISABLE_FLOW_CTRL 0x0 +#define FTDI_SIO_RTS_CTS_HS (0x1 << 8) +#define FTDI_SIO_DTR_DSR_HS (0x2 << 8) +#define FTDI_SIO_XON_XOFF_HS (0x4 << 8) + +/* + * BmRequestType: 1100 0000b + * bRequest: FTDI_SIO_GET_MODEM_STATUS + * wValue: zero + * wIndex: Port + * wLength: 1 + * Data: Status + * + * One byte of data is returned + * B0..3 0 + * B4 CTS + * 0 = inactive + * 1 = active + * B5 DSR + * 0 = inactive + * 1 = active + * B6 Ring Indicator (RI) + * 0 = inactive + * 1 = active + * B7 Receive Line Signal Detect (RLSD) + * 0 = inactive + * 1 = active + */ + +#define FTDI_SIO_CTS_MASK 0x10 +#define FTDI_SIO_DSR_MASK 0x20 +#define FTDI_SIO_RI_MASK 0x40 +#define FTDI_SIO_RLSD_MASK 0x80 + +/* Possible bitmodes for FTDI_SIO_SET_BITMODE_REQUEST */ +#define FTDI_SIO_BITMODE_RESET 0x00 +#define FTDI_SIO_BITMODE_CBUS 0x20 + +/* + * IN Endpoint + * + * The device reserves the first two bytes of data on this endpoint to contain + * the current values of the modem and line status registers. In the absence of + * data, the device generates a message consisting of these two status bytes + * every 40 ms + * + * Byte 0: Modem Status + * + * Offset Description + * B0 Reserved - must be 1 + * B1 Reserved - must be 0 + * B2 Reserved - must be 0 + * B3 Reserved - must be 0 + * B4 Clear to Send (CTS) + * B5 Data Set Ready (DSR) + * B6 Ring Indicator (RI) + * B7 Receive Line Signal Detect (RLSD) + * + * Byte 1: Line Status + * + * Offset Description + * B0 Data Ready (DR) + * B1 Overrun Error (OE) + * B2 Parity Error (PE) + * B3 Framing Error (FE) + * B4 Break Interrupt (BI) + * B5 Transmitter Holding Register (THRE) + * B6 Transmitter Empty (TEMT) + * B7 Error in RCVR FIFO + * + */ +#define FTDI_RS0_CTS (1 << 4) +#define FTDI_RS0_DSR (1 << 5) +#define FTDI_RS0_RI (1 << 6) +#define FTDI_RS0_RLSD (1 << 7) + +#define FTDI_RS_DR 1 +#define FTDI_RS_OE (1 << 1) +#define FTDI_RS_PE (1 << 2) +#define FTDI_RS_FE (1 << 3) +#define FTDI_RS_BI (1 << 4) +#define FTDI_RS_THRE (1 << 5) +#define FTDI_RS_TEMT (1 << 6) +#define FTDI_RS_FIFO (1 << 7) + +#ifdef __cplusplus +extern "C" { +#endif + +#ifdef __cplusplus +} +#endif + +#endif /* USBH_FTDI_H */ diff --git a/kernel/cherryusb/class/serial/usbh_gsm.c b/kernel/cherryusb/class/serial/usbh_gsm.c new file mode 100644 index 0000000..6341873 --- /dev/null +++ b/kernel/cherryusb/class/serial/usbh_gsm.c @@ -0,0 +1,131 @@ +/* + * Copyright (c) 2025, sakumisu + * + * SPDX-License-Identifier: Apache-2.0 + */ +#include "usbh_core.h" +#include "usbh_serial.h" + +#undef USB_DBG_TAG +#define USB_DBG_TAG "usbh_gsm" +#include "usb_log.h" + +struct usbh_gsm { + struct usb_endpoint_descriptor *intin; + struct usbh_urb intin_urb; + struct usb_osal_timer *modem_timer; + uint16_t modem_status; +}; + +static int usbh_gsm_attach(struct usbh_serial *serial) +{ + struct usb_endpoint_descriptor *ep_desc; + + struct usbh_gsm *gsm_class = usb_osal_malloc(sizeof(struct usbh_gsm)); + if (!gsm_class) { + USB_LOG_ERR("No memory for gsm_class\r\n"); + return -USB_ERR_NOMEM; + } + memset(gsm_class, 0, sizeof(struct usbh_gsm)); + serial->priv = gsm_class; + + for (uint8_t i = 0; i < serial->hport->config.intf[serial->intf].altsetting[0].intf_desc.bNumEndpoints; i++) { + ep_desc = &serial->hport->config.intf[serial->intf].altsetting[0].ep[i].ep_desc; + + if (USB_GET_ENDPOINT_TYPE(ep_desc->bmAttributes) == USB_ENDPOINT_TYPE_INTERRUPT) { + if (ep_desc->bEndpointAddress & 0x80) { + USBH_EP_INIT(gsm_class->intin, ep_desc); + break; + } else { + } + } + } + + if (!gsm_class->intin) { + USB_LOG_WRN("Do not find interrupt endpoint, so disable modem status monitor\r\n"); + } + return 0; +} + +static void usbh_gsm_detach(struct usbh_serial *serial) +{ + struct usbh_gsm *gsm_class; + + if (!serial || !serial->priv) { + return; + } + + gsm_class = (struct usbh_gsm *)serial->priv; + if (gsm_class->intin) { + usbh_kill_urb(&gsm_class->intin_urb); + } + serial->priv = NULL; + usb_osal_free(gsm_class); +} + +static int usbh_gsm_set_line_coding(struct usbh_serial *serial, struct cdc_line_coding *line_coding) +{ + return 0; +} + +static int usbh_gsm_set_line_state(struct usbh_serial *serial, bool dtr, bool rts) +{ + return 0; +} + +static const struct usbh_serial_driver gsm_driver = { + .driver_name = "gsm", + + .ignore_rx_header = 0, + .ignore_tx_header = 0, + + .attach = usbh_gsm_attach, + .detach = usbh_gsm_detach, + .set_flow_control = NULL, + .set_line_coding = usbh_gsm_set_line_coding, + .get_line_coding = NULL, + .set_line_state = usbh_gsm_set_line_state, + .get_modem_status = NULL, +}; + +static int usbh_gsm_connect(struct usbh_hubport *hport, uint8_t intf) +{ + return usbh_serial_probe(hport, intf, &gsm_driver) ? 0 : -USB_ERR_NOMEM; +} + +static int usbh_gsm_disconnect(struct usbh_hubport *hport, uint8_t intf) +{ + struct usbh_serial *serial = (struct usbh_serial *)hport->config.intf[intf].priv; + + if (serial) { + usbh_serial_remove(serial); + } + return 0; +} + +const struct usbh_class_driver gsm_class_driver = { + .driver_name = "gsm", + .connect = usbh_gsm_connect, + .disconnect = usbh_gsm_disconnect +}; + +static const uint16_t gsm_id_table[][2] = { + { 0x2C7C, 0x0120 }, /* Quectel EC20 */ + { 0x2C7C, 0x0121 }, /* Quectel EC21 */ + { 0x2C7C, 0x0125 }, /* Quectel EC25 */ + { 0x2C7C, 0x0191 }, /* Quectel EG91 */ + { 0x2C7C, 0x0195 }, /* Quectel EG95 */ + { 0x2C7C, 0x6002 }, /* Quectel EC200/EC600/EC800/EG91x */ + { 0x1E0E, 0x9001 }, /* SIMCOM SIM7600 */ + { 0x2ECC, 0x3012 }, /* Chinamobile ML307R */ + { 0, 0 }, +}; + +CLASS_INFO_DEFINE const struct usbh_class_info gsm_class_info = { + .match_flags = USB_CLASS_MATCH_VID_PID | USB_CLASS_MATCH_INTF_CLASS | USB_CLASS_MATCH_INTF_SUBCLASS | USB_CLASS_MATCH_INTF_PROTOCOL, + .bInterfaceClass = 0xff, + .bInterfaceSubClass = 0x00, + .bInterfaceProtocol = 0x00, + .id_table = gsm_id_table, + .class_driver = &gsm_class_driver +}; diff --git a/kernel/cherryusb/class/serial/usbh_pl2303.c b/kernel/cherryusb/class/serial/usbh_pl2303.c new file mode 100644 index 0000000..062f812 --- /dev/null +++ b/kernel/cherryusb/class/serial/usbh_pl2303.c @@ -0,0 +1,726 @@ +/* + * Copyright (c) 2024 ~ 2025, sakumisu + * Copyright (c) 2024, Derek Konigsberg + * + * SPDX-License-Identifier: Apache-2.0 + */ +#include "usbh_core.h" +#include "usbh_serial.h" +#include "usbh_pl2303.h" + +#undef USB_DBG_TAG +#define USB_DBG_TAG "usbh_pl2303" +#include "usb_log.h" + +#define UART_STATE_INDEX 8 +#define UART_STATE_MSR_MASK 0x8b +#define UART_STATE_TRANSIENT_MASK 0x74 +#define UART_DCD 0x01 +#define UART_DSR 0x02 +#define UART_BREAK_ERROR 0x04 +#define UART_RING 0x08 +#define UART_FRAME_ERROR 0x10 +#define UART_PARITY_ERROR 0x20 +#define UART_OVERRUN_ERROR 0x40 +#define UART_CTS 0x80 + +struct pl2303_type_data { + const char *name; + uint32_t max_baud_rate; + unsigned long quirks; + unsigned int no_autoxonxoff : 1; + unsigned int no_divisors : 1; + unsigned int alt_divisors : 1; +}; + +enum pl2303_type { + TYPE_H, + TYPE_HX, + TYPE_TA, + TYPE_TB, + TYPE_HXD, + TYPE_HXN, + TYPE_COUNT +}; + +struct usbh_pl2303 { + enum pl2303_type chip_type; + uint32_t quirks; + struct usb_endpoint_descriptor *intin; + struct usbh_urb intin_urb; + struct usb_osal_timer *modem_timer; + uint16_t modem_status; +}; + +static const struct pl2303_type_data pl2303_type_data[TYPE_COUNT] = { + [TYPE_H] = { + .name = "PL2303H", + .max_baud_rate = 1228800, + .quirks = PL2303_QUIRK_LEGACY, + .no_autoxonxoff = true, + }, + [TYPE_HX] = { + .name = "PL2303HX", + .max_baud_rate = 6000000, + }, + [TYPE_TA] = { + .name = "PL2303TA", + .max_baud_rate = 6000000, + .alt_divisors = true, + }, + [TYPE_TB] = { + .name = "PL2303TB", + .max_baud_rate = 12000000, + .alt_divisors = true, + }, + [TYPE_HXD] = { + .name = "PL2303HXD", + .max_baud_rate = 12000000, + }, + [TYPE_HXN] = { + .name = "PL2303G", + .max_baud_rate = 12000000, + .no_divisors = true, + }, +}; + +/* + * Returns the nearest supported baud rate that can be set directly without + * using divisors. + */ +static uint32_t pl2303_get_supported_baud_rate(uint32_t baud) +{ + static const uint32_t baud_sup[] = { + 75, 150, 300, 600, 1200, 1800, 2400, 3600, 4800, 7200, 9600, + 14400, 19200, 28800, 38400, 57600, 115200, 230400, 460800, + 614400, 921600, 1228800, 2457600, 3000000, 6000000 + }; + + unsigned i; + + for (i = 0; i < ARRAY_SIZE(baud_sup); ++i) { + if (baud_sup[i] > baud) + break; + } + + if (i == ARRAY_SIZE(baud_sup)) + baud = baud_sup[i - 1]; + else if (i > 0 && (baud_sup[i] - baud) > (baud - baud_sup[i - 1])) + baud = baud_sup[i - 1]; + else + baud = baud_sup[i]; + + return baud; +} + +/* + * NOTE: If unsupported baud rates are set directly, the PL2303 seems to + * use 9600 baud. + */ +static uint32_t pl2303_encode_baud_rate_direct(unsigned char buf[4], + uint32_t baud) +{ + memcpy(buf, &baud, 4); + + return baud; +} + +static uint32_t pl2303_encode_baud_rate_divisor_alt(unsigned char buf[4], + uint32_t baud) +{ + unsigned int baseline, mantissa, exponent; + + /* + * Apparently, for the TA version the formula is: + * baudrate = 12M * 32 / (mantissa * 2^exponent) + * where + * mantissa = buf[10:0] + * exponent = buf[15:13 16] + */ + baseline = 12000000 * 32; + mantissa = baseline / baud; + if (mantissa == 0) + mantissa = 1; /* Avoid dividing by zero if baud > 32*12M. */ + exponent = 0; + while (mantissa >= 2048) { + if (exponent < 15) { + mantissa >>= 1; /* divide by 2 */ + exponent++; + } else { + /* Exponent is maxed. Trim mantissa and leave. */ + mantissa = 2047; + break; + } + } + + buf[3] = 0x80; + buf[2] = exponent & 0x01; + buf[1] = (exponent & ~0x01) << 4 | mantissa >> 8; + buf[0] = mantissa & 0xff; + + /* Calculate and return the exact baud rate. */ + baud = (baseline / mantissa) >> exponent; + + return baud; +} + +static uint32_t pl2303_encode_baud_rate_divisor(unsigned char buf[4], + uint32_t baud) +{ + unsigned int baseline, mantissa, exponent; + + /* + * Apparently the formula is: + * baudrate = 12M * 32 / (mantissa * 4^exponent) + * where + * mantissa = buf[8:0] + * exponent = buf[11:9] + */ + baseline = 12000000 * 32; + mantissa = baseline / baud; + if (mantissa == 0) + mantissa = 1; /* Avoid dividing by zero if baud > 32*12M. */ + exponent = 0; + while (mantissa >= 512) { + if (exponent < 7) { + mantissa >>= 2; /* divide by 4 */ + exponent++; + } else { + /* Exponent is maxed. Trim mantissa and leave. */ + mantissa = 511; + break; + } + } + + buf[3] = 0x80; + buf[2] = 0; + buf[1] = exponent << 1 | mantissa >> 8; + buf[0] = mantissa & 0xff; + + /* Calculate and return the exact baud rate. */ + baud = (baseline / mantissa) >> (exponent << 1); + + return baud; +} + +static int pl2303_vendor_write(struct usbh_serial *serial, uint16_t wValue, uint16_t wIndex) +{ + struct usb_setup_packet *setup; + struct usbh_pl2303 *pl2303_class; + + if (!serial || !serial->hport || !serial->priv) { + return -USB_ERR_INVAL; + } + setup = serial->hport->setup; + pl2303_class = (struct usbh_pl2303 *)serial->priv; + + setup->bmRequestType = USB_REQUEST_DIR_OUT | USB_REQUEST_VENDOR | USB_REQUEST_RECIPIENT_DEVICE; + setup->bRequest = pl2303_class->chip_type == TYPE_HXN ? PL2303_VENDOR_WRITE_NREQUEST : PL2303_VENDOR_WRITE_REQUEST; + setup->wValue = wValue; + setup->wIndex = wIndex; + setup->wLength = 0; + + return usbh_control_transfer(serial->hport, setup, NULL); +} + +static int pl2303_vendor_read(struct usbh_serial *serial, uint16_t wValue, uint8_t *data) +{ + struct usb_setup_packet *setup; + struct usbh_pl2303 *pl2303_class; + int ret; + + if (!serial || !serial->hport || !serial->priv) { + return -USB_ERR_INVAL; + } + setup = serial->hport->setup; + pl2303_class = (struct usbh_pl2303 *)serial->priv; + + setup->bmRequestType = USB_REQUEST_DIR_IN | USB_REQUEST_VENDOR | USB_REQUEST_RECIPIENT_DEVICE; + setup->bRequest = pl2303_class->chip_type == TYPE_HXN ? PL2303_VENDOR_READ_NREQUEST : PL2303_VENDOR_READ_REQUEST; + setup->wValue = wValue; + setup->wIndex = 0; + setup->wLength = 1; + + ret = usbh_control_transfer(serial->hport, setup, serial->iobuffer); + if (ret < 0) { + return ret; + } + memcpy(data, serial->iobuffer, 1); + + return ret; +} + +static bool pl2303_supports_hx_status(struct usbh_serial *serial) +{ + int ret; + uint8_t buf; + + ret = pl2303_vendor_read(serial, PL2303_READ_TYPE_HX_STATUS, &buf); + if (ret < 0) { + return false; + } + + return true; +} + +static bool pl2303_is_hxd_clone(struct usbh_serial *serial) +{ + struct usb_setup_packet *setup; + int ret; + + if (!serial || !serial->hport) { + return -USB_ERR_INVAL; + } + setup = serial->hport->setup; + + setup->bmRequestType = USB_REQUEST_DIR_IN | USB_REQUEST_CLASS | USB_REQUEST_RECIPIENT_DEVICE; + setup->bRequest = CDC_REQUEST_GET_LINE_CODING; + setup->wValue = 0; + setup->wIndex = 0; + setup->wLength = 7; + + ret = usbh_control_transfer(serial->hport, setup, serial->iobuffer); + if (ret < 0) { + return false; + } + return true; +} + +static int pl2303_update_reg(struct usbh_serial *serial, uint8_t reg, uint8_t mask, uint8_t val) +{ + int ret; + uint8_t buf[1]; + struct usbh_pl2303 *pl2303_class; + + if (!serial || !serial->hport || !serial->priv) { + return -USB_ERR_INVAL; + } + + pl2303_class = (struct usbh_pl2303 *)serial->priv; + + if (pl2303_class->chip_type == TYPE_HXN) + ret = pl2303_vendor_read(serial, reg, buf); + else + ret = pl2303_vendor_read(serial, reg | 0x80, buf); + + if (ret < 0) { + return ret; + } + + *buf &= ~mask; + *buf |= val & mask; + + return pl2303_vendor_write(serial, reg, *buf); +} + +static int usbh_pl2303_get_chiptype(struct usbh_serial *serial) +{ + if (serial->hport->device_desc.bDeviceClass == 0x02) { + return TYPE_H; /* variant 0 */ + } + + if (serial->hport->device_desc.bMaxPacketSize0 != 0x40) { + if (serial->hport->device_desc.bDeviceClass == 0x00 || serial->hport->device_desc.bDeviceClass == 0xff) + return TYPE_H; /* variant 1 */ + + return TYPE_H; /* variant 0 */ + } + + switch (serial->hport->device_desc.bcdUSB) { + case 0x101: + /* USB 1.0.1? Let's assume they meant 1.1... */ + case 0x110: + switch (serial->hport->device_desc.bcdDevice) { + case 0x300: + return TYPE_HX; + case 0x400: + return TYPE_HXD; + default: + return TYPE_HX; + } + break; + case 0x200: + switch (serial->hport->device_desc.bcdDevice) { + case 0x100: /* GC */ + case 0x105: + return TYPE_HXN; + case 0x300: /* GT / TA */ + if (pl2303_supports_hx_status(serial)) + return TYPE_TA; + __attribute__((fallthrough)); + case 0x305: + case 0x400: /* GL */ + case 0x405: + return TYPE_HXN; + case 0x500: /* GE / TB */ + if (pl2303_supports_hx_status(serial)) + return TYPE_TB; + __attribute__((fallthrough)); + case 0x505: + case 0x600: /* GS */ + case 0x605: + case 0x700: /* GR */ + case 0x705: + case 0x905: /* GT-2AB */ + case 0x1005: /* GC-Q20 */ + return TYPE_HXN; + } + break; + } + + USB_LOG_ERR("Unsupported PL2303 Device\r\n"); + return -USB_ERR_NOTSUPP; +} + +static int usbh_pl2303_attach(struct usbh_serial *serial) +{ + struct usbh_pl2303 *pl2303_class; + struct usb_endpoint_descriptor *ep_desc; + uint8_t type; + int ret; + + ret = usbh_pl2303_get_chiptype(serial); + if (ret < 0) { + return ret; + } + + pl2303_class = usb_osal_malloc(sizeof(struct usbh_pl2303)); + if (pl2303_class == NULL) { + USB_LOG_ERR("Fail to alloc pl2303_class\r\n"); + return -USB_ERR_NOMEM; + } + memset(pl2303_class, 0, sizeof(struct usbh_pl2303)); + serial->priv = pl2303_class; + + for (uint8_t i = 0; i < serial->hport->config.intf[serial->intf].altsetting[0].intf_desc.bNumEndpoints; i++) { + ep_desc = &serial->hport->config.intf[serial->intf].altsetting[0].ep[i].ep_desc; + + if (USB_GET_ENDPOINT_TYPE(ep_desc->bmAttributes) == USB_ENDPOINT_TYPE_INTERRUPT) { + if (ep_desc->bEndpointAddress & 0x80) { + USBH_EP_INIT(pl2303_class->intin, ep_desc); + break; + } else { + } + } + } + + if (!pl2303_class->intin) { + USB_LOG_ERR("Failed to find interrupt endpoint\r\n"); + ret = -USB_ERR_NODEV; + goto errout; + } + + type = (uint8_t)ret; + pl2303_class->chip_type = type; + pl2303_class->quirks = pl2303_type_data[pl2303_class->chip_type].quirks; + + USB_LOG_INFO("chip type: %s\r\n", pl2303_type_data[pl2303_class->chip_type].name); + + if (type == TYPE_HXD && pl2303_is_hxd_clone(serial)) { + pl2303_class->quirks |= PL2303_QUIRK_NO_BREAK_GETLINE; + } + + if (type != TYPE_HXN) { + uint8_t buf[1]; + ret = pl2303_vendor_read(serial, 0x8484, buf); + ret |= pl2303_vendor_write(serial, 0x0404, 0); + ret |= pl2303_vendor_read(serial, 0x8484, buf); + ret |= pl2303_vendor_read(serial, 0x8383, buf); + ret |= pl2303_vendor_read(serial, 0x8484, buf); + ret |= pl2303_vendor_write(serial, 0x0404, 1); + ret |= pl2303_vendor_read(serial, 0x8484, buf); + ret |= pl2303_vendor_read(serial, 0x8383, buf); + ret |= pl2303_vendor_write(serial, 0, 1); + ret |= pl2303_vendor_write(serial, 1, 0); + if (pl2303_class->quirks & PL2303_QUIRK_LEGACY) + ret |= pl2303_vendor_write(serial, 2, 0x24); + else + ret |= pl2303_vendor_write(serial, 2, 0x44); + } else { + ret = 0; + } + + if (ret < 0) { + USB_LOG_ERR("pl2303 init failed\r\n"); + goto errout; + } + + return 0; +errout: + serial->priv = NULL; + usb_osal_free(pl2303_class); + return ret; +} + +static void usbh_pl2303_detach(struct usbh_serial *serial) +{ + struct usbh_pl2303 *pl2303_class; + + if (!serial || !serial->priv) { + return; + } + + pl2303_class = (struct usbh_pl2303 *)serial->priv; + if (pl2303_class->intin) { + usbh_kill_urb(&pl2303_class->intin_urb); + } + serial->priv = NULL; + usb_osal_free(pl2303_class); +} + +static int usbh_pl2303_set_flow_ctrl(struct usbh_serial *serial, bool hardctrl) +{ + struct usbh_pl2303 *pl2303_class; + + if (!serial || !serial->hport || !serial->priv) { + return -USB_ERR_INVAL; + } + + pl2303_class = (struct usbh_pl2303 *)serial->priv; + + if (hardctrl) { + if (pl2303_class->quirks & PL2303_QUIRK_LEGACY) { + return pl2303_update_reg(serial, 0, PL2303_FLOWCTRL_MASK, 0x40); + } else if (pl2303_class->chip_type == TYPE_HXN) { + return pl2303_update_reg(serial, PL2303_HXN_FLOWCTRL_REG, + PL2303_HXN_FLOWCTRL_MASK, + PL2303_HXN_FLOWCTRL_RTS_CTS); + } else { + return pl2303_update_reg(serial, 0, PL2303_FLOWCTRL_MASK, 0x60); + } + } else { + if (pl2303_class->chip_type == TYPE_HXN) { + return pl2303_update_reg(serial, PL2303_HXN_FLOWCTRL_REG, + PL2303_HXN_FLOWCTRL_MASK, + PL2303_HXN_FLOWCTRL_NONE); + } else { + return pl2303_update_reg(serial, 0, PL2303_FLOWCTRL_MASK, 0); + } + } +} + +static int usbh_pl2303_set_line_coding(struct usbh_serial *serial, struct cdc_line_coding *line_coding) +{ + struct usb_setup_packet *setup; + struct usbh_pl2303 *pl2303_class; + uint32_t baud; + uint32_t baud_sup; + uint8_t buf[7]; + + if (!serial || !serial->hport || !serial->priv) { + return -USB_ERR_INVAL; + } + + setup = serial->hport->setup; + pl2303_class = (struct usbh_pl2303 *)serial->priv; + + setup->bmRequestType = USB_REQUEST_DIR_OUT | USB_REQUEST_CLASS | USB_REQUEST_RECIPIENT_INTERFACE; + setup->bRequest = CDC_REQUEST_SET_LINE_CODING; + setup->wValue = 0; + setup->wIndex = serial->intf; + setup->wLength = 7; + + baud = line_coding->dwDTERate; + if (pl2303_type_data[pl2303_class->chip_type].max_baud_rate) { + baud = MIN(baud, pl2303_type_data[pl2303_class->chip_type].max_baud_rate); + } + /* + * Use direct method for supported baud rates, otherwise use divisors. + * Newer chip types do not support divisor encoding. + */ + if (pl2303_type_data[pl2303_class->chip_type].no_divisors) + baud_sup = baud; + else + baud_sup = pl2303_get_supported_baud_rate(baud); + + if (baud == baud_sup) + baud = pl2303_encode_baud_rate_direct(buf, baud); + else if (pl2303_type_data[pl2303_class->chip_type].alt_divisors) + baud = pl2303_encode_baud_rate_divisor_alt(buf, baud); + else + baud = pl2303_encode_baud_rate_divisor(buf, baud); + + buf[4] = line_coding->bCharFormat; + buf[5] = line_coding->bParityType; + buf[6] = line_coding->bDataBits; + + memcpy(serial->iobuffer, buf, sizeof(struct cdc_line_coding)); + + return usbh_control_transfer(serial->hport, setup, serial->iobuffer); +} + +static int usbh_pl2303_get_line_coding(struct usbh_serial *serial, struct cdc_line_coding *line_coding) +{ + struct usb_setup_packet *setup; + int ret; + + if (!serial || !serial->hport) { + return -USB_ERR_INVAL; + } + setup = serial->hport->setup; + + setup->bmRequestType = USB_REQUEST_DIR_IN | USB_REQUEST_CLASS | USB_REQUEST_RECIPIENT_INTERFACE; + setup->bRequest = CDC_REQUEST_GET_LINE_CODING; + setup->wValue = 0; + setup->wIndex = serial->intf; + setup->wLength = 7; + + ret = usbh_control_transfer(serial->hport, setup, serial->iobuffer); + if (ret < 0) { + return ret; + } + memcpy(line_coding, serial->iobuffer, sizeof(struct cdc_line_coding)); + return ret; +} + +static int usbh_pl2303_set_line_state(struct usbh_serial *serial, bool dtr, bool rts) +{ + struct usb_setup_packet *setup; + + if (!serial || !serial->hport) { + return -USB_ERR_INVAL; + } + setup = serial->hport->setup; + + setup->bmRequestType = USB_REQUEST_DIR_OUT | USB_REQUEST_CLASS | USB_REQUEST_RECIPIENT_INTERFACE; + setup->bRequest = CDC_REQUEST_SET_CONTROL_LINE_STATE; + setup->wValue = (dtr << 0) | (rts << 1); + setup->wIndex = serial->intf; + setup->wLength = 0; + + return usbh_control_transfer(serial->hport, setup, NULL); +} + +static int usbh_pl2303_get_modem_status(struct usbh_serial *serial) +{ + struct usbh_pl2303 *pl2303_class; + uintptr_t flags; + uint16_t status; + + if (!serial || !serial->hport || !serial->priv) { + return -USB_ERR_INVAL; + } + + flags = usb_osal_enter_critical_section(); + pl2303_class = (struct usbh_pl2303 *)serial->priv; + + status = (pl2303_class->modem_status & UART_DSR ? USBH_SERIAL_TIOCM_DSR : 0) | + (pl2303_class->modem_status & UART_CTS ? USBH_SERIAL_TIOCM_CTS : 0) | + (pl2303_class->modem_status & UART_RING ? USBH_SERIAL_TIOCM_RI : 0) | + (pl2303_class->modem_status & UART_DCD ? USBH_SERIAL_TIOCM_CD : 0) | + (serial->line_state & USBH_SERIAL_TIOCM_DTR ? USBH_SERIAL_TIOCM_DTR : 0) | + (serial->line_state & USBH_SERIAL_TIOCM_RTS ? USBH_SERIAL_TIOCM_RTS : 0); + + usb_osal_leave_critical_section(flags); + + return status; +} + +#ifdef CONFIG_USBH_SERIAL_GET_MODEM_STATUS +static int __usbh_pl2303_get_modem_status(struct usbh_serial *serial) +{ + struct usbh_pl2303 *pl2303_class; + uint8_t status = 0; + uint16_t difference; + uintptr_t flags; + int ret; + + if (!serial || !serial->hport || !serial->priv) { + return -USB_ERR_INVAL; + } + pl2303_class = (struct usbh_pl2303 *)serial->priv; + + usbh_int_urb_fill(&pl2303_class->intin_urb, serial->hport, pl2303_class->intin, &serial->iobuffer[USBH_SERIAL_INT_NOCACHE_OFFSET], pl2303_class->intin->wMaxPacketSize, 0xffffffff, NULL, NULL); + ret = usbh_submit_urb(&pl2303_class->intin_urb); + if (ret < 0) { + return ret; + } + + if (ret < 1) { + return -USB_ERR_INVAL; + } + + flags = usb_osal_enter_critical_section(); + + status = serial->iobuffer[USBH_SERIAL_INT_NOCACHE_OFFSET]; + difference = pl2303_class->modem_status ^ status; + pl2303_class->modem_status = status; + + if (status & UART_BREAK_ERROR) + serial->iocount.brk++; + + if (difference & UART_STATE_MSR_MASK) { + if (difference & UART_CTS) + serial->iocount.cts++; + if (difference & UART_DSR) + serial->iocount.dsr++; + if (difference & UART_RING) + serial->iocount.rng++; + if (difference & UART_DCD) { + serial->iocount.dcd++; + } + } + + usb_osal_leave_critical_section(flags); + + return ret; +} +#endif + +static const struct usbh_serial_driver pl2303_driver = { + .driver_name = "pl2303", + + .ignore_rx_header = 0, + .ignore_tx_header = 0, + + .attach = usbh_pl2303_attach, + .detach = usbh_pl2303_detach, + .set_flow_control = usbh_pl2303_set_flow_ctrl, + .set_line_coding = usbh_pl2303_set_line_coding, + .get_line_coding = usbh_pl2303_get_line_coding, + .set_line_state = usbh_pl2303_set_line_state, + .get_modem_status = usbh_pl2303_get_modem_status, +}; + +static int usbh_pl2303_connect(struct usbh_hubport *hport, uint8_t intf) +{ + return usbh_serial_probe(hport, intf, &pl2303_driver) ? 0 : -USB_ERR_NOMEM; +} + +static int usbh_pl2303_disconnect(struct usbh_hubport *hport, uint8_t intf) +{ + struct usbh_serial *serial = (struct usbh_serial *)hport->config.intf[intf].priv; + + if (serial) { + usbh_serial_remove(serial); + } + + return 0; +} + +static const uint16_t pl2303_id_table[][2] = { + { 0x067B, 0x2303 }, // PL2303 Serial (ATEN/IOGEAR UC232A) + { 0x067B, 0x2304 }, // PL2303HXN Serial, type TB + { 0x067B, 0x23A3 }, // PL2303HXN Serial, type GC + { 0x067B, 0x23B3 }, // PL2303HXN Serial, type GB + { 0x067B, 0x23C3 }, // PL2303HXN Serial, type GT + { 0x067B, 0x23D3 }, // PL2303HXN Serial, type GL + { 0x067B, 0x23E3 }, // PL2303HXN Serial, type GE + { 0x067B, 0x23F3 }, // PL2303HXN Serial, type GS + { 0, 0 }, +}; + +const struct usbh_class_driver pl2303_class_driver = { + .driver_name = "pl2303", + .connect = usbh_pl2303_connect, + .disconnect = usbh_pl2303_disconnect +}; + +CLASS_INFO_DEFINE const struct usbh_class_info pl2303_class_info = { + .match_flags = USB_CLASS_MATCH_VID_PID | USB_CLASS_MATCH_INTF_CLASS, + .bInterfaceClass = 0xff, + .bInterfaceSubClass = 0x00, + .bInterfaceProtocol = 0x00, + .id_table = pl2303_id_table, + .class_driver = &pl2303_class_driver +}; \ No newline at end of file diff --git a/kernel/cherryusb/class/serial/usbh_pl2303.h b/kernel/cherryusb/class/serial/usbh_pl2303.h new file mode 100644 index 0000000..83391c1 --- /dev/null +++ b/kernel/cherryusb/class/serial/usbh_pl2303.h @@ -0,0 +1,43 @@ +/* + * Copyright (c) 2024 ~ 2025, sakumisu + * + * SPDX-License-Identifier: Apache-2.0 + */ +#ifndef USBH_PL2303_H +#define USBH_PL2303_H + +#include "usb_cdc.h" + +#define PL2303_VENDOR_WRITE_REQUEST 0x01 +#define PL2303_VENDOR_WRITE_NREQUEST 0x80 +#define PL2303_VENDOR_READ_REQUEST 0x01 +#define PL2303_VENDOR_READ_NREQUEST 0x81 + +#define PL2303_FLOWCTRL_MASK 0xf0 + +#define PL2303_READ_TYPE_HX_STATUS 0x8080 + +#define PL2303_HXN_RESET_REG 0x07 +#define PL2303_HXN_RESET_UPSTREAM_PIPE 0x02 +#define PL2303_HXN_RESET_DOWNSTREAM_PIPE 0x01 + +#define PL2303_HXN_FLOWCTRL_REG 0x0a +#define PL2303_HXN_FLOWCTRL_MASK 0x1c +#define PL2303_HXN_FLOWCTRL_NONE 0x1c +#define PL2303_HXN_FLOWCTRL_RTS_CTS 0x18 +#define PL2303_HXN_FLOWCTRL_XON_XOFF 0x0c + +#define PL2303_QUIRK_UART_STATE_IDX0 BIT(0) +#define PL2303_QUIRK_LEGACY BIT(1) +#define PL2303_QUIRK_ENDPOINT_HACK BIT(2) +#define PL2303_QUIRK_NO_BREAK_GETLINE BIT(3) + +#ifdef __cplusplus +extern "C" { +#endif + +#ifdef __cplusplus +} +#endif + +#endif /* USBH_PL2303_H */ diff --git a/kernel/cherryusb/class/serial/usbh_serial.c b/kernel/cherryusb/class/serial/usbh_serial.c new file mode 100644 index 0000000..b0bedc3 --- /dev/null +++ b/kernel/cherryusb/class/serial/usbh_serial.c @@ -0,0 +1,655 @@ +/* + * Copyright (c) 2025, sakumisu + * Copyright (c) 2025, MDLZCOOL + * + * SPDX-License-Identifier: Apache-2.0 + */ +#include "usbh_core.h" +#include "usbh_serial.h" + +#undef USB_DBG_TAG +#define USB_DBG_TAG "usbh_serial" +#include "usb_log.h" + +#define DEV_FORMAT_VENDOR "/dev/ttyUSB%d" +#define DEV_FORMAT_CDC_ACM "/dev/ttyACM%d" + +#define CONFIG_USBHOST_MAX_SERIAL_CLASS 4 + +static struct usbh_serial g_serial_class[CONFIG_USBHOST_MAX_SERIAL_CLASS]; + +static uint32_t g_devinuse = 0; +static uint32_t g_cdcacm_devinuse = 0; + +USB_NOCACHE_RAM_SECTION USB_MEM_ALIGNX uint8_t g_serial_iobuffer[CONFIG_USBHOST_MAX_SERIAL_CLASS][USB_ALIGN_UP((USBH_SERIAL_RX2_NOCACHE_OFFSET + USBH_SERIAL_RX2_NOCACHE_SIZE), CONFIG_USB_ALIGN_SIZE)]; + +static struct usbh_serial *usbh_serial_alloc(bool is_cdcacm) +{ + uint8_t devno; + uint8_t devno2; + + for (devno = 0; devno < CONFIG_USBHOST_MAX_SERIAL_CLASS; devno++) { + if ((g_devinuse & (1U << devno)) == 0) { + g_devinuse |= (1U << devno); + memset(&g_serial_class[devno], 0, sizeof(struct usbh_serial)); + g_serial_class[devno].minor = devno; + g_serial_class[devno].cdc_minor = -1; + g_serial_class[devno].iobuffer = g_serial_iobuffer[devno]; + g_serial_class[devno].rx_complete_sem = usb_osal_sem_create(0); + + if (is_cdcacm) { + for (devno2 = 0; devno2 < CONFIG_USBHOST_MAX_SERIAL_CLASS; devno2++) { + if ((g_cdcacm_devinuse & (1U << devno2)) == 0) { + g_cdcacm_devinuse |= (1U << devno2); + g_serial_class[devno].cdc_minor = devno2; + return &g_serial_class[devno]; + } + } + + g_devinuse &= ~(1U << devno); + return NULL; + } else { + return &g_serial_class[devno]; + } + } + } + return NULL; +} + +static void usbh_serial_free(struct usbh_serial *serial) +{ + uint8_t devno = serial->minor; + if (devno < 32) { + g_devinuse &= ~(1U << devno); + } + + if (serial->cdc_minor >= 0) { + g_cdcacm_devinuse &= ~(1U << serial->cdc_minor); + } + + if (g_serial_class[devno].rx_complete_sem) { + usb_osal_sem_delete(g_serial_class[devno].rx_complete_sem); + } +} + +static void usbh_serial_callback(void *arg, int nbytes) +{ + struct usbh_serial *serial = (struct usbh_serial *)arg; + int ret; + + if (nbytes < 0) { + if (nbytes != -USB_ERR_SHUTDOWN) { + USB_LOG_ERR("serial transfer error: %d\n", nbytes); + } + serial->rx_errorcode = nbytes; + usb_osal_sem_give(serial->rx_complete_sem); + return; + } + + if (nbytes < serial->driver->ignore_rx_header) { + USB_LOG_ERR("serial rx short packet: %d\n", nbytes); + serial->rx_errorcode = -USB_ERR_IO; + usb_osal_sem_give(serial->rx_complete_sem); + return; + } + + if (nbytes >= serial->driver->ignore_rx_header) { + /* resubmit the read urb */ + usbh_bulk_urb_fill(&serial->bulkin_urb, serial->hport, serial->bulkin, &serial->iobuffer[serial->rx_buf_index ? USBH_SERIAL_RX_NOCACHE_OFFSET : USBH_SERIAL_RX2_NOCACHE_OFFSET], serial->bulkin->wMaxPacketSize, + 0, usbh_serial_callback, serial); + ret = usbh_submit_urb(&serial->bulkin_urb); + if (ret < 0) { + USB_LOG_ERR("serial submit failed: %d\n", ret); + serial->rx_errorcode = ret; + usb_osal_sem_give(serial->rx_complete_sem); + return; + } + + usb_ringbuffer_write(&serial->rx_rb, + &serial->iobuffer[(serial->rx_buf_index ? USBH_SERIAL_RX2_NOCACHE_OFFSET : USBH_SERIAL_RX_NOCACHE_OFFSET) + serial->driver->ignore_rx_header], + (nbytes - serial->driver->ignore_rx_header)); + + if (serial->rx_complete_callback) { + serial->rx_complete_callback(serial, nbytes - serial->driver->ignore_rx_header); + } + serial->rx_buf_index ^= 1; + serial->rx_errorcode = 0; + usb_osal_sem_give(serial->rx_complete_sem); + } +} + +struct usbh_serial *usbh_serial_probe(struct usbh_hubport *hport, uint8_t intf, + const struct usbh_serial_driver *driver) +{ + struct usb_endpoint_descriptor *ep_desc; + struct usbh_serial *serial; + bool is_cdcacm = false; + int ret; + + if (strcmp(driver->driver_name, "cdc_acm") == 0) { + is_cdcacm = true; + } + + serial = usbh_serial_alloc(is_cdcacm); + if (serial == NULL) { + USB_LOG_ERR("Fail to alloc serial class\r\n"); + return NULL; + } + + serial->hport = hport; + serial->intf = intf; + serial->driver = driver; + + if (driver->attach) { + ret = driver->attach(serial); + if (ret < 0) { + USB_LOG_ERR("Serial attach failed: %d\r\n", ret); + usbh_serial_free(serial); + return NULL; + } + } + + if (is_cdcacm) { + intf = intf + 1; /* data interface */ + } + + for (uint8_t i = 0; i < hport->config.intf[intf].altsetting[0].intf_desc.bNumEndpoints; i++) { + ep_desc = &hport->config.intf[intf].altsetting[0].ep[i].ep_desc; + + if (USB_GET_ENDPOINT_TYPE(ep_desc->bmAttributes) == USB_ENDPOINT_TYPE_BULK) { + if (ep_desc->bEndpointAddress & 0x80) { + USBH_EP_INIT(serial->bulkin, ep_desc); + } else { + USBH_EP_INIT(serial->bulkout, ep_desc); + } + } + } + + if (is_cdcacm) { + intf = intf - 1; /* data interface */ + } + + if (!serial->bulkin || !serial->bulkout) { + USB_LOG_ERR("Serial bulk in/out endpoint not found\r\n"); + usbh_serial_free(serial); + return NULL; + } + + if (is_cdcacm) { + snprintf(hport->config.intf[intf].devname, CONFIG_USBHOST_DEV_NAMELEN, DEV_FORMAT_CDC_ACM, serial->cdc_minor); + } else { + snprintf(hport->config.intf[intf].devname, CONFIG_USBHOST_DEV_NAMELEN, DEV_FORMAT_VENDOR, serial->minor); + } + + hport->config.intf[intf].priv = serial; + USB_LOG_INFO("Register Serial Class: %s (%s)\r\n", hport->config.intf[intf].devname, driver->driver_name); + + usbh_serial_run(serial); + + return serial; +} + +void usbh_serial_remove(struct usbh_serial *serial) +{ + if (!serial || !serial->hport) + return; + + usbh_serial_close(serial); + + if (serial->driver && serial->driver->detach) { + serial->driver->detach(serial); + } + + if (serial->hport->config.intf[serial->intf].priv) { + usb_osal_thread_schedule_other(); + USB_LOG_INFO("Unregister Serial Class: %s (%s)\r\n", serial->hport->config.intf[serial->intf].devname, serial->driver->driver_name); + usbh_serial_stop(serial); + } + + usbh_serial_free(serial); +} + +struct usbh_serial *usbh_serial_open(const char *devname, uint32_t open_flags) +{ + struct usbh_serial *serial; + int ret; + + serial = usbh_find_class_instance(devname); + if (!serial) { + return NULL; + } + + if (serial->ref_count != 0) { + USB_LOG_ERR("Device busy: %s\r\n", devname); + return NULL; + } + + if (serial && serial->driver && serial->driver->open) { + ret = serial->driver->open(serial); + if (ret < 0) { + return NULL; + } + } + + usb_ringbuffer_init(&serial->rx_rb, serial->rx_rb_pool, CONFIG_USBHOST_SERIAL_RX_SIZE); + + serial->ref_count++; + serial->open_flags = open_flags; + + return serial; +} + +int usbh_serial_close(struct usbh_serial *serial) +{ + if (!serial || !serial->hport) { + return -USB_ERR_INVAL; + } + + if (serial->ref_count == 0) { + return 0; + } + + if (serial->bulkin) { + usbh_kill_urb(&serial->bulkin_urb); + } + if (serial->bulkout) { + usbh_kill_urb(&serial->bulkout_urb); + } + + if (serial && serial->driver && serial->driver->set_flow_control && serial->rtscts) { + serial->driver->set_flow_control(serial, false); + } + + if (serial && serial->driver && serial->driver->close) { + serial->driver->close(serial); + } + + serial->ref_count--; + serial->rtscts = false; + + return 0; +} + +static int usbh_serial_tiocmset(struct usbh_serial *serial, uint32_t set, uint32_t clear) +{ + int ret; + uint16_t line_state; + bool dtr; + bool rts; + + if (!serial || !serial->hport || !serial->hport->connected) { + return -USB_ERR_INVAL; + } + + if (serial->ref_count == 0) { + return -USB_ERR_NODEV; + } + + line_state = serial->line_state; + clear &= ~set; /* 'set' takes precedence over 'clear' */ + + if (set & USBH_SERIAL_TIOCM_DTR) { + line_state |= USBH_SERIAL_TIOCM_DTR; + } + if (set & USBH_SERIAL_TIOCM_RTS) { + line_state |= USBH_SERIAL_TIOCM_RTS; + } + if (clear & USBH_SERIAL_TIOCM_DTR) { + line_state &= ~USBH_SERIAL_TIOCM_DTR; + } + if (clear & USBH_SERIAL_TIOCM_RTS) { + line_state &= ~USBH_SERIAL_TIOCM_RTS; + } + + dtr = (line_state & USBH_SERIAL_TIOCM_DTR) ? true : false; + rts = (line_state & USBH_SERIAL_TIOCM_RTS) ? true : false; + + if (serial && serial->driver && serial->driver->set_line_state) { + ret = serial->driver->set_line_state(serial, dtr, rts); + } else { + return -USB_ERR_NOTSUPP; + } + serial->line_state = line_state; + + return ret; +} + +int usbh_serial_control(struct usbh_serial *serial, int cmd, void *arg) +{ + int ret; + + if (!serial || !serial->hport || !serial->hport->connected) { + return -USB_ERR_INVAL; + } + + if (serial->ref_count == 0) { + return -USB_ERR_NODEV; + } + + switch (cmd) { + case USBH_SERIAL_CMD_SET_ATTR: { + struct usbh_serial_termios *termios = (struct usbh_serial_termios *)arg; + struct cdc_line_coding line_coding; + + line_coding.dwDTERate = termios->baudrate; + line_coding.bCharFormat = termios->stopbits; + line_coding.bParityType = termios->parity; + line_coding.bDataBits = termios->databits; + + if (serial->bulkin) { + usbh_kill_urb(&serial->bulkin_urb); + } + if (serial->bulkout) { + usbh_kill_urb(&serial->bulkout_urb); + } + + if (serial && serial->driver && serial->driver->set_line_coding) { + ret = serial->driver->set_line_coding(serial, &line_coding); + if (ret < 0) { + return ret; + } + } else { + return -USB_ERR_NOTSUPP; + } + + memcpy(&serial->line_coding, &line_coding, sizeof(struct cdc_line_coding)); + + if (serial && serial->driver && serial->driver->set_flow_control) { + ret = serial->driver->set_flow_control(serial, termios->rtscts); + } + + serial->rtscts = termios->rtscts; + serial->rx_timeout_ms = termios->rx_timeout; + + ret = usbh_serial_tiocmset(serial, USBH_SERIAL_TIOCM_DTR | USBH_SERIAL_TIOCM_RTS, 0); + if (ret < 0) { + return ret; + } + + usb_ringbuffer_reset(&serial->rx_rb); + usb_osal_sem_reset(serial->rx_complete_sem); + serial->rx_buf_index = 0; + usbh_bulk_urb_fill(&serial->bulkin_urb, serial->hport, serial->bulkin, &serial->iobuffer[serial->rx_buf_index ? USBH_SERIAL_RX2_NOCACHE_OFFSET : USBH_SERIAL_RX_NOCACHE_OFFSET], serial->bulkin->wMaxPacketSize, + 0, usbh_serial_callback, serial); + ret = usbh_submit_urb(&serial->bulkin_urb); + + return ret; + } break; + case USBH_SERIAL_CMD_GET_ATTR: { + struct usbh_serial_termios *termios = (struct usbh_serial_termios *)arg; + struct cdc_line_coding line_coding; + + if (serial && serial->driver && serial->driver->get_line_coding) { + return serial->driver->get_line_coding(serial, &line_coding); + } else { + memcpy(&line_coding, &serial->line_coding, sizeof(struct cdc_line_coding)); + } + + termios->baudrate = line_coding.dwDTERate; + termios->stopbits = line_coding.bCharFormat; + termios->parity = line_coding.bParityType; + termios->databits = line_coding.bDataBits; + termios->rtscts = serial->rtscts; + termios->rx_timeout = serial->rx_timeout_ms; + return 0; + } break; + case USBH_SERIAL_CMD_IOCMBIS: { + uint32_t flags = *(uint32_t *)arg; + + return usbh_serial_tiocmset(serial, flags, 0); + } break; + case USBH_SERIAL_CMD_IOCMBIC: { + uint32_t flags = *(uint32_t *)arg; + + return usbh_serial_tiocmset(serial, 0, flags); + } break; + case USBH_SERIAL_CMD_TIOCMSET: { + uint32_t flags = *(uint32_t *)arg; + + uint32_t set = 0; + uint32_t clear = 0; + + set |= (flags & USBH_SERIAL_TIOCM_DTR) ? USBH_SERIAL_TIOCM_DTR : 0; + set |= (flags & USBH_SERIAL_TIOCM_RTS) ? USBH_SERIAL_TIOCM_RTS : 0; + clear |= !(flags & USBH_SERIAL_TIOCM_DTR) ? USBH_SERIAL_TIOCM_DTR : 0; + clear |= !(flags & USBH_SERIAL_TIOCM_RTS) ? USBH_SERIAL_TIOCM_RTS : 0; + + return usbh_serial_tiocmset(serial, set, clear); + } break; + case USBH_SERIAL_CMD_TIOCMGET: { + uint32_t *flags = (uint32_t *)arg; + int status; + + if (serial && serial->driver && serial->driver->get_modem_status) { + status = serial->driver->get_modem_status(serial); + if (status < 0) { + return status; + } + } else { + return -USB_ERR_NOTSUPP; + } + *flags = status; + } break; + default: + break; + } + + return -USB_ERR_NOTSUPP; +} + +int usbh_serial_write(struct usbh_serial *serial, const void *buffer, uint32_t buflen) +{ + int ret; + struct usbh_urb *urb; + + if (!serial || !serial->hport || !serial->hport->connected || !serial->bulkout) { + return -USB_ERR_INVAL; + } + + if (serial->ref_count == 0) { + return -USB_ERR_NODEV; + } + + urb = &serial->bulkout_urb; + + usbh_bulk_urb_fill(urb, serial->hport, serial->bulkout, (uint8_t *)buffer, buflen, 0xffffffff, NULL, NULL); + ret = usbh_submit_urb(urb); + if (ret == 0) { + ret = urb->actual_length; + } + return ret; +} + +int usbh_serial_read(struct usbh_serial *serial, void *buffer, uint32_t buflen) +{ + int ret; + + if (!serial || !serial->hport || !serial->hport->connected || !serial->bulkin || !serial->line_coding.dwDTERate) { + return -USB_ERR_INVAL; + } + + if (serial->ref_count == 0) { + return -USB_ERR_NODEV; + } + + if (serial->open_flags & USBH_SERIAL_O_NONBLOCK) { + return usb_ringbuffer_read(&serial->rx_rb, buffer, buflen); + } else { + if (usb_ringbuffer_get_used(&serial->rx_rb) == 0) { + ret = usb_osal_sem_take(serial->rx_complete_sem, serial->rx_timeout_ms == 0 ? USB_OSAL_WAITING_FOREVER : serial->rx_timeout_ms); + if (ret < 0) { + return ret; + } + if (serial->rx_errorcode < 0) { + return serial->rx_errorcode; + } + } + return usb_ringbuffer_read(&serial->rx_rb, buffer, buflen); + } +} + +int usbh_serial_cdc_write_async(struct usbh_serial *serial, uint8_t *buffer, uint32_t buflen, usbh_complete_callback_t complete, void *arg) +{ + struct usbh_urb *urb; + + if (!serial || !serial->hport || !serial->hport->connected || !serial->bulkout || !complete || serial->line_coding.dwDTERate) { + return -USB_ERR_INVAL; + } + + if (serial->ref_count == 0) { + return -USB_ERR_NODEV; + } + + urb = &serial->bulkout_urb; + + usbh_bulk_urb_fill(urb, serial->hport, serial->bulkout, buffer, buflen, + 0, complete, serial); + return usbh_submit_urb(urb); +} + +int usbh_serial_cdc_read_async(struct usbh_serial *serial, uint8_t *buffer, uint32_t buflen, usbh_complete_callback_t complete, void *arg) +{ + struct usbh_urb *urb; + + if (!serial || !serial->hport || !serial->hport->connected || !serial->bulkin || !complete || serial->line_coding.dwDTERate) { + return -USB_ERR_INVAL; + } + + if (serial->ref_count == 0) { + return -USB_ERR_NODEV; + } + + if (buflen % serial->bulkin->wMaxPacketSize) { + return -USB_ERR_INVAL; + } + + urb = &serial->bulkin_urb; + + usbh_bulk_urb_fill(urb, serial->hport, serial->bulkin, buffer, MIN(buflen, serial->bulkin->wMaxPacketSize), + 0, complete, serial); + return usbh_submit_urb(urb); +} + +void usbh_serial_help(void) +{ + USB_LOG_RAW("USB host serial test\r\n" + "Usage: usbh_serial [options]...\r\n" + "\r\n" + "-b set serial baudrate\r\n" + "-t set rts and dtr\r\n" + "-w string write string\r\n" + "-r read data and dump\r\n" + "-x close serial device\r\n" + "\r\n"); +} + +static USB_NOCACHE_RAM_SECTION USB_MEM_ALIGNX uint8_t g_serial_testbuffer[512]; + +int usbh_serial(int argc, char **argv) +{ + static struct usbh_serial *serial; + int ret; + + if (argc < 3) { + usbh_serial_help(); + return 0; + } + + if (serial) { + if (!serial->hport || !serial->hport->connected) { + serial = NULL; + } + } + + if (!serial) { + serial = usbh_serial_open(argv[1], USBH_SERIAL_O_RDWR | USBH_SERIAL_O_NONBLOCK); + if (!serial) { + USB_LOG_ERR("Fail to open serial device: %s\r\n", argv[1]); + return -USB_ERR_INVAL; + } + } + + if (strncmp(argv[2], "-b", 2) == 0 && argc >= 4) { + struct usbh_serial_termios termios; + + memset(&termios, 0, sizeof(termios)); + termios.baudrate = atoi(argv[3]); + termios.stopbits = 0; + termios.parity = 0; + termios.databits = 8; + termios.rtscts = false; + termios.rx_timeout = 0; + usbh_serial_control(serial, USBH_SERIAL_CMD_SET_ATTR, &termios); + } else if (strncmp(argv[2], "-t", 2) == 0 && argc >= 5) { + uint32_t flags; + + flags = atoi(argv[3]) ? USBH_SERIAL_TIOCM_DTR : 0; + flags |= atoi(argv[4]) ? USBH_SERIAL_TIOCM_RTS : 0; + + usbh_serial_control(serial, USBH_SERIAL_CMD_TIOCMSET, &flags); + USB_LOG_INFO("Set DTR: %d, RTS: %d\r\n", atoi(argv[3]), atoi(argv[4])); + } else if (strncmp(argv[2], "-w", 2) == 0 && argc >= 4) { + memcpy(g_serial_testbuffer, argv[3], MIN(strlen(argv[3]), sizeof(g_serial_testbuffer))); + uint32_t len = snprintf((char *)g_serial_testbuffer, sizeof(g_serial_testbuffer), "%s\r\n", argv[3]); + ret = usbh_serial_write(serial, g_serial_testbuffer, len); + if (ret >= 0) { + USB_LOG_INFO("Write %d bytes\r\n", ret); + } else { + USB_LOG_ERR("Write failed: %d\r\n", ret); + } + } else if (strncmp(argv[2], "-r", 2) == 0) { + ret = usbh_serial_read(serial, g_serial_testbuffer, sizeof(g_serial_testbuffer)); + if (ret >= 0) { + usb_hexdump(g_serial_testbuffer, ret); + USB_LOG_INFO("Read %d bytes\r\n", ret); + } else { + USB_LOG_ERR("Read failed: %d\r\n", ret); + } + } else if (strncmp(argv[2], "-x", 2) == 0) { + usbh_serial_close(serial); + serial = NULL; + } else { + usbh_serial_help(); + } + + return 0; +} + +__WEAK void usbh_serial_run(struct usbh_serial *serial) +{ + (void)serial; +} + +__WEAK void usbh_serial_stop(struct usbh_serial *serial) +{ + (void)serial; +} + +static int usbh_cdc_data_connect(struct usbh_hubport *hport, uint8_t intf) +{ + (void)hport; + (void)intf; + return 0; +} + +static int usbh_cdc_data_disconnect(struct usbh_hubport *hport, uint8_t intf) +{ + (void)hport; + (void)intf; + return 0; +} + +const struct usbh_class_driver cdc_data_class_driver = { + .driver_name = "cdc_data", + .connect = usbh_cdc_data_connect, + .disconnect = usbh_cdc_data_disconnect +}; + +CLASS_INFO_DEFINE const struct usbh_class_info cdc_data_class_info = { + .match_flags = USB_CLASS_MATCH_INTF_CLASS, + .bInterfaceClass = USB_DEVICE_CLASS_CDC_DATA, + .bInterfaceSubClass = 0x00, + .bInterfaceProtocol = 0x00, + .id_table = NULL, + .class_driver = &cdc_data_class_driver +}; \ No newline at end of file diff --git a/kernel/cherryusb/class/serial/usbh_serial.h b/kernel/cherryusb/class/serial/usbh_serial.h new file mode 100644 index 0000000..06a3170 --- /dev/null +++ b/kernel/cherryusb/class/serial/usbh_serial.h @@ -0,0 +1,175 @@ +/* + * Copyright (c) 2025, sakumisu + * Copyright (c) 2025, MDLZCOOL + * + * SPDX-License-Identifier: Apache-2.0 + */ +#ifndef USBH_SERIAL_H +#define USBH_SERIAL_H + +#include "usb_cdc.h" + +#define USBH_SERIAL_CTRL_NOCACHE_OFFSET 0 +#define USBH_SERIAL_CTRL_NOCACHE_SIZE 32 +#define USBH_SERIAL_INT_NOCACHE_OFFSET USB_ALIGN_UP(USBH_SERIAL_CTRL_NOCACHE_SIZE, CONFIG_USB_ALIGN_SIZE) +#define USBH_SERIAL_INT_NOCACHE_SIZE 32 +#define USBH_SERIAL_RX_NOCACHE_OFFSET USB_ALIGN_UP((USBH_SERIAL_INT_NOCACHE_OFFSET + USBH_SERIAL_INT_NOCACHE_SIZE), CONFIG_USB_ALIGN_SIZE) +#define USBH_SERIAL_RX_NOCACHE_SIZE 512 +#define USBH_SERIAL_RX2_NOCACHE_OFFSET USB_ALIGN_UP((USBH_SERIAL_RX_NOCACHE_OFFSET + USBH_SERIAL_RX_NOCACHE_SIZE), CONFIG_USB_ALIGN_SIZE) +#define USBH_SERIAL_RX2_NOCACHE_SIZE 512 + +#define USBH_SERIAL_DATABITS_5 5 +#define USBH_SERIAL_DATABITS_6 6 +#define USBH_SERIAL_DATABITS_7 7 +#define USBH_SERIAL_DATABITS_8 8 + +#define USBH_SERIAL_PARITY_NONE 0 +#define USBH_SERIAL_PARITY_ODD 1 +#define USBH_SERIAL_PARITY_EVEN 2 +#define USBH_SERIAL_PARITY_MARK 3 +#define USBH_SERIAL_PARITY_SPACE 4 + +#define USBH_SERIAL_STOPBITS_1 0 +#define USBH_SERIAL_STOPBITS_1_5 1 +#define USBH_SERIAL_STOPBITS_2 2 + +/* modem lines */ +#define USBH_SERIAL_TIOCM_LE 0x001 /* line enable */ +#define USBH_SERIAL_TIOCM_DTR 0x002 /* data terminal ready */ +#define USBH_SERIAL_TIOCM_RTS 0x004 /* request to send */ +#define USBH_SERIAL_TIOCM_ST 0x010 /* secondary transmit */ +#define USBH_SERIAL_TIOCM_SR 0x020 /* secondary receive */ +#define USBH_SERIAL_TIOCM_CTS 0x040 /* clear to send */ +#define USBH_SERIAL_TIOCM_CAR 0x100 /* carrier detect */ +#define USBH_SERIAL_TIOCM_CD USBH_SERIAL_TIOCM_CAR +#define USBH_SERIAL_TIOCM_RNG 0x200 /* ring */ +#define USBH_SERIAL_TIOCM_RI USBH_SERIAL_TIOCM_RNG +#define USBH_SERIAL_TIOCM_DSR 0x400 /* data set ready */ +#define USBH_SERIAL_TIOCM_OUT1 0x2000 +#define USBH_SERIAL_TIOCM_OUT2 0x4000 +#define USBH_SERIAL_TIOCM_LOOP 0x8000 + +#define USBH_SERIAL_O_RDONLY 0x0000 /* open for reading only */ +#define USBH_SERIAL_O_WRONLY 0x0001 /* open for writing only */ +#define USBH_SERIAL_O_RDWR 0x0002 /* open for reading and writing */ + +#define USBH_SERIAL_O_ACCMODE 0x0003 /* mask for above modes, from 4.4BSD https://minnie.tuhs.org/cgi-bin/utree.pl?file=4.4BSD/usr/include/sys/fcntl.h */ +#define USBH_SERIAL_O_NONBLOCK 0x0004 /* non-blocking I/O, from BSD apple https://opensource.apple.com/source/xnu/xnu-1228.0.2/bsd/sys/fcntl.h */ + +#define USBH_SERIAL_CMD_SET_ATTR 0 +#define USBH_SERIAL_CMD_GET_ATTR 1 +#define USBH_SERIAL_CMD_IOCMBIS 2 +#define USBH_SERIAL_CMD_IOCMBIC 3 +#define USBH_SERIAL_CMD_TIOCMSET 4 +#define USBH_SERIAL_CMD_TIOCMGET 5 + +#ifdef __cplusplus +extern "C" { +#endif + +/* + * Counters of the input lines (CTS, DSR, RI, CD) interrupts + */ + +struct usbh_serial_async_icount { + uint32_t cts, dsr, rng, dcd, tx, rx; + uint32_t frame, parity, overrun, brk; + uint32_t buf_overrun; +}; + +struct usbh_serial_termios { + uint32_t baudrate; + uint8_t databits; + uint8_t parity; + uint8_t stopbits; + bool rtscts; /* hardware flow control */ + uint32_t rx_timeout; +}; + +struct usbh_serial; + +typedef void (*usbh_serial_rx_complete_callback_t)(struct usbh_serial *serial, int nbytes); + +/** + * @brief Serial Driver Operations + */ +struct usbh_serial_driver { + const char *driver_name; + + uint8_t ignore_tx_header; + uint8_t ignore_rx_header; + + int (*attach)(struct usbh_serial *serial); + void (*detach)(struct usbh_serial *serial); + + int (*open)(struct usbh_serial *serial); + void (*close)(struct usbh_serial *serial); + int (*set_flow_control)(struct usbh_serial *serial, bool enable); + int (*set_line_coding)(struct usbh_serial *serial, struct cdc_line_coding *line_coding); + int (*get_line_coding)(struct usbh_serial *serial, struct cdc_line_coding *line_coding); + int (*set_line_state)(struct usbh_serial *serial, bool dtr, bool rts); + int (*get_modem_status)(struct usbh_serial *serial); +}; + +/** + * @brief Serial Instance + */ +struct usbh_serial { + struct usbh_hubport *hport; + uint8_t intf; /* Interface Number */ + int minor; /* Serial Port Number (/dev/ttyUSBx or /dev/ttyACMx) */ + int cdc_minor; /* Serial Port Number (/dev/ttyACMx) */ + uint8_t *iobuffer; /* I/O buffer for serial transfers */ + uint8_t ref_count; /* Reference Count */ + uint32_t open_flags; + uint32_t rx_timeout_ms; + + struct cdc_line_coding line_coding; + uint16_t line_state; + bool rtscts; /* hardware flow control */ + struct usbh_serial_async_icount iocount; + + struct usb_endpoint_descriptor *bulkin; /* Bulk IN endpoint */ + struct usb_endpoint_descriptor *bulkout; /* Bulk OUT endpoint */ + struct usbh_urb bulkout_urb; + struct usbh_urb bulkin_urb; + + const struct usbh_serial_driver *driver; + + usb_ringbuffer_t rx_rb; + uint8_t rx_rb_pool[CONFIG_USBHOST_SERIAL_RX_SIZE]; + usb_osal_sem_t rx_complete_sem; + uint8_t rx_buf_index; + int rx_errorcode; + usbh_serial_rx_complete_callback_t rx_complete_callback; + + void *priv; /* Private Data */ + void *user_data; /* User Data */ +}; + +/* internal api */ +struct usbh_serial *usbh_serial_probe(struct usbh_hubport *hport, uint8_t intf, const struct usbh_serial_driver *driver); +void usbh_serial_remove(struct usbh_serial *serial); + +/* public api */ +struct usbh_serial *usbh_serial_open(const char *devname, uint32_t open_flags); +int usbh_serial_close(struct usbh_serial *serial); +int usbh_serial_control(struct usbh_serial *serial, int cmd, void *arg); +int usbh_serial_write(struct usbh_serial *serial, const void *buffer, uint32_t buflen); +int usbh_serial_read(struct usbh_serial *serial, void *buffer, uint32_t buflen); + +/* cdc only api */ +int usbh_serial_cdc_write_async(struct usbh_serial *serial, uint8_t *buffer, uint32_t buflen, usbh_complete_callback_t complete, void *arg); +int usbh_serial_cdc_read_async(struct usbh_serial *serial, uint8_t *buffer, uint32_t buflen, usbh_complete_callback_t complete, void *arg); + +/* public weak api */ +void usbh_serial_run(struct usbh_serial *serial); +void usbh_serial_stop(struct usbh_serial *serial); + +int usbh_serial(int argc, char **argv); + +#ifdef __cplusplus +} +#endif + +#endif /* USBH_SERIAL_H */ \ No newline at end of file diff --git a/kernel/cherryusb/class/template/usb_xxx.h b/kernel/cherryusb/class/template/usb_xxx.h new file mode 100644 index 0000000..d883c8b --- /dev/null +++ b/kernel/cherryusb/class/template/usb_xxx.h @@ -0,0 +1,4 @@ +#ifndef _USB_XXX_H +#define _USB_XXX_H + +#endif \ No newline at end of file diff --git a/kernel/cherryusb/class/template/usbd_xxx.c b/kernel/cherryusb/class/template/usbd_xxx.c new file mode 100644 index 0000000..aa4bc01 --- /dev/null +++ b/kernel/cherryusb/class/template/usbd_xxx.c @@ -0,0 +1,39 @@ +#include "usbd_core.h" +#include "usbd_xxx.h" + +static int xxx_class_interface_request_handler(uint8_t busid, struct usb_setup_packet *setup, uint8_t **data, uint32_t *len) +{ + USB_LOG_WRN("XXX Class request: " + "bRequest 0x%02x\r\n", + setup->bRequest); + + switch (setup->bRequest) { + default: + USB_LOG_WRN("Unhandled XXX Class bRequest 0x%02x\r\n", setup->bRequest); + return -1; + } + + return 0; +} + +static void xxx_notify_handler(uint8_t busid, uint8_t event, void *arg) +{ + switch (event) { + case USBD_EVENT_RESET: + + break; + + default: + break; + } +} + +struct usbd_interface *usbd_xxx_init_intf(uint8_t busid, struct usbd_interface *intf) +{ + intf->class_interface_handler = xxx_class_interface_request_handler; + intf->class_endpoint_handler = NULL; + intf->vendor_handler = NULL; + intf->notify_handler = xxx_notify_handler; + + return intf; +} diff --git a/kernel/cherryusb/class/template/usbd_xxx.h b/kernel/cherryusb/class/template/usbd_xxx.h new file mode 100644 index 0000000..8230c30 --- /dev/null +++ b/kernel/cherryusb/class/template/usbd_xxx.h @@ -0,0 +1,16 @@ +#ifndef _USBD_XXX_H_ +#define _USBD_XXX_H_ + +#include "usb_xxx.h" + +#ifdef __cplusplus +extern "C" { +#endif + +struct usbd_interface *usbd_xxx_init_intf(uint8_t busid, struct usbd_interface *intf); + +#ifdef __cplusplus +} +#endif + +#endif /* _USBD_XXX_H_ */ diff --git a/kernel/cherryusb/class/template/usbh_xxx.c b/kernel/cherryusb/class/template/usbh_xxx.c new file mode 100644 index 0000000..4456b3c --- /dev/null +++ b/kernel/cherryusb/class/template/usbh_xxx.c @@ -0,0 +1,97 @@ +#include "usbh_core.h" +#include "usbh_xxx.h" + +#define DEV_FORMAT "/dev/xxx" + +#define CONFIG_USBHOST_MAX_CUSTOM_CLASS 1 +static struct usbh_xxx g_xxx_class[CONFIG_USBHOST_MAX_CUSTOM_CLASS]; +static uint32_t g_devinuse = 0; + +static struct usbh_xxx *usbh_xxx_class_alloc(void) +{ + uint8_t devno; + + for (devno = 0; devno < CONFIG_USBHOST_MAX_CUSTOM_CLASS; devno++) { + if ((g_devinuse & (1U << devno)) == 0) { + g_devinuse |= (1U << devno); + memset(&g_xxx_class[devno], 0, sizeof(struct usbh_xxx)); + g_xxx_class[devno].minor = devno; + return &g_xxx_class[devno]; + } + } + return NULL; +} + +static void usbh_xxx_class_free(struct usbh_xxx *xxx_class) +{ + uint8_t devno = xxx_class->minor; + + if (devno < 32) { + g_devinuse &= ~(1U << devno); + } + memset(xxx_class, 0, sizeof(struct usbh_xxx)); +} + +static int usbh_xxx_connect(struct usbh_hubport *hport, uint8_t intf) +{ + struct usb_endpoint_descriptor *ep_desc; + int ret; + + struct usbh_xxx *xxx_class = usbh_xxx_class_alloc(); + if (xxx_class == NULL) { + USB_LOG_ERR("Fail to alloc xxx_class\r\n"); + return -USB_ERR_NOMEM; + } + + return ret; +} + + +static int usbh_xxx_disconnect(struct usbh_hubport *hport, uint8_t intf) +{ + int ret = 0; + + struct usbh_xxx *xxx_class = (struct usbh_xxx *)hport->config.intf[intf].priv; + + if (xxx_class) { + if (xxx_class->xxxin) { + usbh_kill_urb(&xxx_class->xxxin_urb); + } + + if (xxx_class->xxxout) { + usbh_kill_urb(&xxx_class->xxxout_urb); + } + + if (hport->config.intf[intf].devname[0] != '\0') { + USB_LOG_INFO("Unregister xxx Class:%s\r\n", hport->config.intf[intf].devname); + usbh_xxx_stop(xxx_class); + } + + usbh_xxx_class_free(xxx_class); + } + + return ret; +} + +__WEAK void usbh_xxx_run(struct usbh_xxx *xxx_class) +{ +} + +__WEAK void usbh_xxx_stop(struct usbh_xxx *xxx_class) +{ +} + +static const struct usbh_class_driver xxx_class_driver = { + .driver_name = "xxx", + .connect = usbh_xxx_connect, + .disconnect = usbh_xxx_disconnect +}; + +CLASS_INFO_DEFINE const struct usbh_class_info xxx_class_info = { + .match_flags = USB_CLASS_MATCH_INTF_CLASS | USB_CLASS_MATCH_INTF_SUBCLASS | USB_CLASS_MATCH_INTF_PROTOCOL, + .bInterfaceClass = 0, + .bInterfaceSubClass = 0, + .bInterfaceProtocol = 0, + .id_table = NULL, + .class_driver = &xxx_class_driver +}; diff --git a/kernel/cherryusb/class/template/usbh_xxx.h b/kernel/cherryusb/class/template/usbh_xxx.h new file mode 100644 index 0000000..0858f51 --- /dev/null +++ b/kernel/cherryusb/class/template/usbh_xxx.h @@ -0,0 +1,22 @@ +#ifndef _USBH_XXX_H +#define _USBH_XXX_H + +#include "usb_xxx.h" + +struct usbh_xxx { + struct usbh_hubport *hport; + struct usb_endpoint_descriptor *xxxin; + struct usb_endpoint_descriptor *xxxout; + struct usbh_urb xxxin_urb; + struct usbh_urb xxxout_urb; + + uint8_t intf; /* interface number */ + uint8_t minor; + + void *user_data; +}; + +void usbh_xxx_run(struct usbh_xxx *xxx_class); +void usbh_xxx_stop(struct usbh_xxx *xxx_class); + +#endif \ No newline at end of file diff --git a/kernel/cherryusb/class/vendor/display/usbd_display.c b/kernel/cherryusb/class/vendor/display/usbd_display.c new file mode 100644 index 0000000..181da6e --- /dev/null +++ b/kernel/cherryusb/class/vendor/display/usbd_display.c @@ -0,0 +1,172 @@ +/* + * Copyright (c) 2026, sakumisu + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "usbd_core.h" +#include "usbd_display.h" + +struct usbd_display_priv { + struct usb_mempool pool; + struct usbd_endpoint out_ep; + struct usbd_endpoint in_ep; + struct usbd_display_frame *current_frame; +} g_usbd_display; + +int usbd_display_frame_create(struct usbd_display_frame *frame, uint32_t count) +{ + return usb_mempool_create(&g_usbd_display.pool, frame, sizeof(struct usbd_display_frame), count); +} + +struct usbd_display_frame *usbd_display_frame_alloc(void) +{ + return (struct usbd_display_frame *)usb_mempool_alloc(&g_usbd_display.pool); +} + +int usbd_display_frame_free(struct usbd_display_frame *frame) +{ + return usb_mempool_free(&g_usbd_display.pool, (uintptr_t *)frame); +} + +int usbd_display_frame_send(struct usbd_display_frame *frame) +{ + return usb_mempool_send(&g_usbd_display.pool, (uintptr_t *)frame); +} + +int usbd_display_frame_recv(struct usbd_display_frame **frame, uint32_t timeout) +{ + return usb_mempool_recv(&g_usbd_display.pool, (uintptr_t **)frame, timeout); +} + +uint8_t usb_dispay_dummy[512]; +volatile uint32_t usb_display_buf_offset; +volatile bool usb_display_ignore_frame; + +static void display_notify_handler(uint8_t busid, uint8_t event, void *arg) +{ + switch (event) { + case USBD_EVENT_RESET: + break; + case USBD_EVENT_CONFIGURED: + usb_display_buf_offset = 0; + usb_display_ignore_frame = true; + g_usbd_display.current_frame = NULL; + usb_mempool_reset(&g_usbd_display.pool); + usbd_ep_start_read(busid, g_usbd_display.out_ep.ep_addr, usb_dispay_dummy, usbd_get_ep_mps(0, g_usbd_display.out_ep.ep_addr)); + break; + default: + break; + } +} + +void usbd_display_bulk_out(uint8_t busid, uint8_t ep, uint32_t nbytes) +{ + if (usb_display_ignore_frame) { + // alloc frame for next at the end of current frame + if ((nbytes % usbd_get_ep_mps(0, g_usbd_display.out_ep.ep_addr)) || (nbytes == 0)) { + if (g_usbd_display.current_frame == NULL) { + g_usbd_display.current_frame = usbd_display_frame_alloc(); + if (g_usbd_display.current_frame) { + usb_display_ignore_frame = false; + usb_display_buf_offset = 0; + + goto get_frame; + } else { + goto drop_frame; + } + } else { + usb_display_ignore_frame = false; + usb_display_buf_offset = 0; + + goto get_frame; + } + } else { + goto drop_frame; + } + } else { + struct usbd_disp_frame_header *header = (struct usbd_disp_frame_header *)&g_usbd_display.current_frame->frame_buf[0]; + struct usbd_display_frame *frame; + + if (header->payload_total > g_usbd_display.current_frame->frame_bufsize) { + USB_LOG_ERR("frame overflow, drop it\r\n"); + usb_display_ignore_frame = true; + + goto drop_frame; + } + + usb_display_buf_offset += nbytes; + + if ((nbytes % usbd_get_ep_mps(0, g_usbd_display.out_ep.ep_addr)) || (nbytes == 0)) { + frame = g_usbd_display.current_frame; + g_usbd_display.current_frame = NULL; + + frame->frame_format = header->type; + frame->frame_size = header->payload_total; + usbd_display_frame_send(frame); + + g_usbd_display.current_frame = usbd_display_frame_alloc(); + if (g_usbd_display.current_frame) { + usb_display_ignore_frame = false; + usb_display_buf_offset = 0; + + goto get_frame; + } else { + usb_display_ignore_frame = true; + + goto drop_frame; + } + } else { + goto get_frame; + } + } + return; + +drop_frame: + // drop current frame + usbd_ep_start_read(busid, g_usbd_display.out_ep.ep_addr, usb_dispay_dummy, usbd_get_ep_mps(0, g_usbd_display.out_ep.ep_addr)); + return; +get_frame: + usbd_ep_start_read(busid, g_usbd_display.out_ep.ep_addr, &g_usbd_display.current_frame->frame_buf[usb_display_buf_offset], 16384); + return; +} + +void usbd_display_bulk_in(uint8_t busid, uint8_t ep, uint32_t nbytes) +{ +} + +struct usbd_interface *usbd_display_init_intf(struct usbd_interface *intf, + const uint8_t out_ep, + const uint8_t in_ep, + struct usbd_display_frame *frame, + uint32_t count) +{ + intf->class_interface_handler = NULL; + intf->class_endpoint_handler = NULL; + intf->vendor_handler = NULL; + intf->notify_handler = display_notify_handler; + + g_usbd_display.out_ep.ep_addr = out_ep; + g_usbd_display.out_ep.ep_cb = usbd_display_bulk_out; + g_usbd_display.in_ep.ep_addr = in_ep; + g_usbd_display.in_ep.ep_cb = usbd_display_bulk_in; + usbd_add_endpoint(0, &g_usbd_display.out_ep); + usbd_add_endpoint(0, &g_usbd_display.in_ep); + + for (uint32_t i = 0; i < count; i++) { + USB_ASSERT_MSG(frame[i].frame_bufsize % 16384, "frame_bufsize must be the multiple of 16384"); + } + + usbd_display_frame_create(frame, count); + return intf; +} + +int usbd_display_dequeue(struct usbd_display_frame **frame, uint32_t timeout) +{ + return usbd_display_frame_recv(frame, timeout); +} + +int usbd_display_enqueue(struct usbd_display_frame *frame) +{ + return usbd_display_frame_free(frame); +} \ No newline at end of file diff --git a/kernel/cherryusb/class/vendor/display/usbd_display.h b/kernel/cherryusb/class/vendor/display/usbd_display.h new file mode 100644 index 0000000..9b7c47e --- /dev/null +++ b/kernel/cherryusb/class/vendor/display/usbd_display.h @@ -0,0 +1,51 @@ +/* + * Copyright (c) 2026, sakumisu + * + * SPDX-License-Identifier: Apache-2.0 + */ +#ifndef USBD_DISPLAY_H +#define USBD_DISPLAY_H + +#define USBD_DISPLAY_TYPE_RGB565 0 +#define USBD_DISPLAY_TYPE_RGB888 1 +#define USBD_DISPLAY_TYPE_YUV420 2 +#define USBD_DISPLAY_TYPE_JPG 3 + +struct usbd_disp_frame_header { + uint16_t crc16; //payload crc16 + uint8_t type; //raw rgb,yuv,jpg,other + uint8_t cmd; + uint16_t x; //32bit + uint16_t y; + uint16_t width; //32bit + uint16_t height; + uint32_t frame_id : 10; + uint32_t payload_total : 22; //payload max 4MB +} __PACKED; + +struct usbd_display_frame { + uint8_t *frame_buf; + uint32_t frame_bufsize; + uint32_t frame_format; + uint32_t frame_size; +}; + +#ifdef __cplusplus +extern "C" { +#endif + +/* Init display interface driver */ +struct usbd_interface *usbd_display_init_intf(struct usbd_interface *intf, + const uint8_t out_ep, + const uint8_t in_ep, + struct usbd_display_frame *frame, + uint32_t count); + +int usbd_display_dequeue(struct usbd_display_frame **frame, uint32_t timeout); +int usbd_display_enqueue(struct usbd_display_frame *frame); + +#ifdef __cplusplus +} +#endif + +#endif /* USBD_DISPLAY_H */ diff --git a/kernel/cherryusb/class/vendor/net/usbh_asix.c b/kernel/cherryusb/class/vendor/net/usbh_asix.c new file mode 100644 index 0000000..ffa1ed5 --- /dev/null +++ b/kernel/cherryusb/class/vendor/net/usbh_asix.c @@ -0,0 +1,817 @@ +/* + * Copyright (c) 2024, sakumisu + * + * SPDX-License-Identifier: Apache-2.0 + */ +#include "usbh_core.h" +#include "usbh_asix.h" +#include "usb_cdc.h" + +#undef USB_DBG_TAG +#define USB_DBG_TAG "asix" +#include "usb_log.h" + +#define DEV_FORMAT "/dev/asix" + +static struct usbh_asix g_asix_class; + +static USB_NOCACHE_RAM_SECTION USB_MEM_ALIGNX uint8_t g_asix_rx_buffer[USB_ALIGN_UP(CONFIG_USBHOST_ASIX_ETH_MAX_TX_SIZE, CONFIG_USB_ALIGN_SIZE)]; +static USB_NOCACHE_RAM_SECTION USB_MEM_ALIGNX uint8_t g_asix_tx_buffer[USB_ALIGN_UP(CONFIG_USBHOST_ASIX_ETH_MAX_RX_SIZE, CONFIG_USB_ALIGN_SIZE)]; +static USB_NOCACHE_RAM_SECTION USB_MEM_ALIGNX uint8_t g_asix_inttx_buffer[USB_ALIGN_UP(16, CONFIG_USB_ALIGN_SIZE)]; + +static USB_NOCACHE_RAM_SECTION USB_MEM_ALIGNX uint8_t g_asix_buf[USB_ALIGN_UP(32, CONFIG_USB_ALIGN_SIZE)]; + +#define ETH_ALEN 6 + +#define PHY_MODE_MARVELL 0x0000 +#define MII_MARVELL_LED_CTRL 0x0018 +#define MII_MARVELL_STATUS 0x001b +#define MII_MARVELL_CTRL 0x0014 + +#define MARVELL_LED_MANUAL 0x0019 + +#define MARVELL_STATUS_HWCFG 0x0004 + +#define MARVELL_CTRL_TXDELAY 0x0002 +#define MARVELL_CTRL_RXDELAY 0x0080 + +#define PHY_MODE_RTL8211CL 0x000C + +#define AX88772A_PHY14H 0x14 +#define AX88772A_PHY14H_DEFAULT 0x442C + +#define AX88772A_PHY15H 0x15 +#define AX88772A_PHY15H_DEFAULT 0x03C8 + +#define AX88772A_PHY16H 0x16 +#define AX88772A_PHY16H_DEFAULT 0x4044 + +#define SPEED_100 0 +#define SPEED_10 1 + +static int usbh_asix_read_cmd(struct usbh_asix *asix_class, + uint8_t cmd, + uint16_t value, + uint16_t index, + void *data, + uint16_t size) +{ + struct usb_setup_packet *setup; + int ret; + + if (!asix_class || !asix_class->hport) { + return -USB_ERR_INVAL; + } + setup = asix_class->hport->setup; + + setup->bmRequestType = USB_REQUEST_DIR_IN | USB_REQUEST_VENDOR | USB_REQUEST_RECIPIENT_DEVICE; + setup->bRequest = cmd; + setup->wValue = value; + setup->wIndex = index; + setup->wLength = size; + + ret = usbh_control_transfer(asix_class->hport, setup, g_asix_buf); + if (ret < 8) { + return ret; + } + memcpy(data, g_asix_buf, MIN(ret - 8, size)); + + return ret; +} + +static int usbh_asix_write_cmd(struct usbh_asix *asix_class, + uint8_t cmd, + uint16_t value, + uint16_t index, + void *data, + uint16_t size) +{ + struct usb_setup_packet *setup; + + if (!asix_class || !asix_class->hport) { + return -USB_ERR_INVAL; + } + setup = asix_class->hport->setup; + + setup->bmRequestType = USB_REQUEST_DIR_OUT | USB_REQUEST_VENDOR | USB_REQUEST_RECIPIENT_DEVICE; + setup->bRequest = cmd; + setup->wValue = value; + setup->wIndex = index; + setup->wLength = size; + + if (data && size) { + memcpy(g_asix_buf, data, size); + return usbh_control_transfer(asix_class->hport, setup, g_asix_buf); + } else { + return usbh_control_transfer(asix_class->hport, setup, NULL); + } +} + +static int usbh_asix_mdio_write(struct usbh_asix *asix_class, int phy_id, int loc, int val) +{ + uint8_t smsr; + uint16_t res = (uint16_t)val; + int ret; + + for (uint8_t i = 0; i < 10; i++) { + ret = usbh_asix_write_cmd(asix_class, AX_CMD_SET_SW_MII, 0, 0, NULL, 0); + if (ret < 0) { + return ret; + } + usb_osal_msleep(1); + ret = usbh_asix_read_cmd(asix_class, AX_CMD_STATMNGSTS_REG, 0, 0, &smsr, 1); + if (ret < 0) { + return ret; + } + + if (smsr & AX_HOST_EN) { + break; + } + } + + ret = usbh_asix_write_cmd(asix_class, AX_CMD_WRITE_MII_REG, phy_id, loc, &res, 2); + if (ret < 0) { + return ret; + } + + ret = usbh_asix_write_cmd(asix_class, AX_CMD_SET_HW_MII, 0, 0, NULL, 0); + if (ret < 0) { + return ret; + } + return 0; +} + +static int usbh_asix_mdio_read(struct usbh_asix *asix_class, int phy_id, int loc) +{ + uint8_t smsr; + uint16_t res; + int ret; + + for (uint8_t i = 0; i < 10; i++) { + ret = usbh_asix_write_cmd(asix_class, AX_CMD_SET_SW_MII, 0, 0, NULL, 0); + if (ret < 0) { + return ret; + } + usb_osal_msleep(1); + ret = usbh_asix_read_cmd(asix_class, AX_CMD_STATMNGSTS_REG, 0, 0, &smsr, 1); + if (ret < 0) { + return ret; + } + + if (smsr & AX_HOST_EN) { + break; + } + } + + ret = usbh_asix_read_cmd(asix_class, AX_CMD_READ_MII_REG, phy_id, loc, &res, 2); + if (ret < 0) { + return ret; + } + + ret = usbh_asix_write_cmd(asix_class, AX_CMD_SET_HW_MII, 0, 0, NULL, 0); + if (ret < 0) { + return ret; + } + return res; +} + +static int usbh_asix_read_phy_addr(struct usbh_asix *asix_class, bool internal) +{ + int ret, offset; + uint8_t buf[2]; + + ret = usbh_asix_read_cmd(asix_class, AX_CMD_READ_PHY_ID, 0, 0, buf, 2); + if (ret < 0) { + return ret; + } + + offset = (internal ? 1 : 0); + ret = buf[offset]; + + USB_LOG_INFO("%s PHY address 0x%x\r\n", internal ? "internal" : "external", ret); + + return ret; +} + +static int usbh_asix_sw_reset(struct usbh_asix *asix_class, uint8_t flags) +{ + int ret; + + ret = usbh_asix_write_cmd(asix_class, AX_CMD_SW_RESET, flags, 0, NULL, 0); + if (ret < 0) + USB_LOG_ERR("Failed to send software reset: %d\r\n", ret); + + return ret; +} + +static uint16_t usbh_asix_read_rx_ctl(struct usbh_asix *asix_class) +{ + uint16_t v; + int ret = usbh_asix_read_cmd(asix_class, AX_CMD_READ_RX_CTL, 0, 0, &v, 2); + if (ret < 0) { + return ret; + } + return v; +} + +static int usbh_asix_write_rx_ctl(struct usbh_asix *asix_class, uint16_t mode) +{ + int ret; + + USB_LOG_DBG("asix_write_rx_ctl() - mode = 0x%04x\r\n", mode); + ret = usbh_asix_write_cmd(asix_class, AX_CMD_WRITE_RX_CTL, mode, 0, NULL, 0); + if (ret < 0) + USB_LOG_ERR("Failed to write RX_CTL mode to 0x%04x: %02x\r\n", + mode, ret); + + return ret; +} + +static uint16_t usbh_asix_read_medium_status(struct usbh_asix *asix_class) +{ + uint16_t v; + int ret = usbh_asix_read_cmd(asix_class, AX_CMD_READ_MEDIUM_STATUS, 0, 0, &v, 2); + + if (ret < 0) { + USB_LOG_ERR("Error reading Medium Status register: %02x\r\n", + ret); + return ret; /* TODO: callers not checking for error ret */ + } + + return v; +} + +static int usbh_asix_write_medium_mode(struct usbh_asix *asix_class, uint16_t mode) +{ + int ret; + + USB_LOG_DBG("asix_write_medium_mode() - mode = 0x%04x\r\n", mode); + ret = usbh_asix_write_cmd(asix_class, AX_CMD_WRITE_MEDIUM_MODE, mode, 0, NULL, 0); + if (ret < 0) + USB_LOG_ERR("Failed to write Medium Mode mode to 0x%04x: %02x\r\n", + mode, ret); + + return ret; +} + +static int usbh_asix_write_gpio(struct usbh_asix *asix_class, uint16_t value, int sleep) +{ + int ret; + + USB_LOG_DBG("asix_write_gpio() - value = 0x%04x\r\n", value); + ret = usbh_asix_write_cmd(asix_class, AX_CMD_WRITE_GPIOS, value, 0, NULL, 0); + if (ret < 0) + USB_LOG_ERR("Failed to write GPIO value 0x%04x: %d\r\n", + value, ret); + + if (sleep) + usb_osal_msleep(sleep); + + return ret; +} + +/* + * AX88772 & AX88178 have a 16-bit RX_CTL value + */ +static void usbh_asix_set_multicast(struct usbh_asix *asix_class) +{ + uint16_t rx_ctl = AX_DEFAULT_RX_CTL | AX_RX_CTL_AM; +#if CONFIG_USBHOST_ASIX_ETH_MAX_RX_SIZE == 4096 + rx_ctl |= AX_RX_CTL_MFB_4096; +#elif CONFIG_USBHOST_ASIX_ETH_MAX_RX_SIZE == 8192 + rx_ctl |= AX_RX_CTL_MFB_8192; +#elif CONFIG_USBHOST_ASIX_ETH_MAX_RX_SIZE == 16384 + rx_ctl |= AX_RX_CTL_MFB_16384; +#else + rx_ctl |= AX_RX_CTL_MFB_2048; +#endif + const uint8_t multi_filter[] = { 0x00, 0x00, 0x20, 0x80, 0x00, 0x00, 0x00, 0x40 }; + + usbh_asix_write_cmd(asix_class, AX_CMD_WRITE_MULTI_FILTER, 0, 0, (uint8_t *)multi_filter, AX_MCAST_FILTER_SIZE); + usbh_asix_write_cmd(asix_class, AX_CMD_WRITE_RX_CTL, rx_ctl, 0, NULL, 0); +} + +static int usbh_ax88772_hw_reset(struct usbh_asix *asix_class) +{ + uint16_t rx_ctl; + int ret; + + ret = usbh_asix_write_gpio(asix_class, AX_GPIO_RSE | AX_GPIO_GPO_2 | AX_GPIO_GPO2EN, 5); + if (ret < 0) + goto out; + + ret = usbh_asix_write_cmd(asix_class, AX_CMD_SW_PHY_SELECT, asix_class->embd_phy, + 0, NULL, 0); + if (ret < 0) { + USB_LOG_ERR("Select PHY #1 failed: %d\r\n", ret); + goto out; + } + + if (asix_class->embd_phy) { + ret = usbh_asix_sw_reset(asix_class, AX_SWRESET_IPPD); + if (ret < 0) + goto out; + + usb_osal_msleep(10); + + ret = usbh_asix_sw_reset(asix_class, AX_SWRESET_CLEAR); + if (ret < 0) + goto out; + + usb_osal_msleep(60); + + ret = usbh_asix_sw_reset(asix_class, AX_SWRESET_IPRL | AX_SWRESET_PRL); + if (ret < 0) + goto out; + } else { + ret = usbh_asix_sw_reset(asix_class, AX_SWRESET_IPPD | AX_SWRESET_PRL); + if (ret < 0) + goto out; + } + + usb_osal_msleep(150); + + ret = usbh_asix_write_rx_ctl(asix_class, AX_DEFAULT_RX_CTL); + if (ret < 0) + goto out; + + ret = usbh_asix_write_medium_mode(asix_class, AX88772_MEDIUM_DEFAULT); + if (ret < 0) + goto out; + + ret = usbh_asix_write_cmd(asix_class, AX_CMD_WRITE_IPG0, + AX88772_IPG0_DEFAULT | AX88772_IPG1_DEFAULT, + AX88772_IPG2_DEFAULT, NULL, 0); + if (ret < 0) { + USB_LOG_ERR("Write IPG,IPG1,IPG2 failed: %d\r\n", ret); + goto out; + } + + /* Rewrite MAC address */ + ret = usbh_asix_write_cmd(asix_class, AX_CMD_WRITE_NODE_ID, 0, 0, asix_class->mac, ETH_ALEN); + if (ret < 0) + goto out; + + /* Set RX_CTL to default values with 2k buffer, and enable cactus */ + ret = usbh_asix_write_rx_ctl(asix_class, AX_DEFAULT_RX_CTL); + if (ret < 0) + goto out; + + rx_ctl = usbh_asix_read_rx_ctl(asix_class); + USB_LOG_INFO("RX_CTL is 0x%04x after all initializations\r\n", + rx_ctl); + + rx_ctl = usbh_asix_read_medium_status(asix_class); + USB_LOG_INFO("Medium Status is 0x%04x after all initializations\r\n", + rx_ctl); + + return 0; + +out: + return ret; +} + +static int usbh_ax88772a_hw_reset(struct usbh_asix *asix_class) +{ + uint16_t rx_ctl, phy14h, phy15h, phy16h; + int ret; + + ret = usbh_asix_write_gpio(asix_class, AX_GPIO_RSE, 5); + if (ret < 0) + goto out; + + ret = usbh_asix_write_cmd(asix_class, AX_CMD_SW_PHY_SELECT, asix_class->embd_phy | AX_PHYSEL_SSEN, 0, NULL, 0); + if (ret < 0) { + USB_LOG_ERR("Select PHY #1 failed: %d\r\n", ret); + goto out; + } + usb_osal_msleep(10); + + ret = usbh_asix_sw_reset(asix_class, AX_SWRESET_IPPD | AX_SWRESET_IPRL); + if (ret < 0) + goto out; + + usb_osal_msleep(10); + + ret = usbh_asix_sw_reset(asix_class, AX_SWRESET_IPRL); + if (ret < 0) + goto out; + + usb_osal_msleep(160); + + ret = usbh_asix_sw_reset(asix_class, AX_SWRESET_CLEAR); + if (ret < 0) + goto out; + + ret = usbh_asix_sw_reset(asix_class, AX_SWRESET_IPRL); + if (ret < 0) + goto out; + + usb_osal_msleep(200); + + if (asix_class->chipcode == AX_AX88772B_CHIPCODE) { + ret = usbh_asix_write_cmd(asix_class, AX_QCTCTRL, 0x8000, 0x8001, NULL, 0); + if (ret < 0) { + USB_LOG_ERR("Write BQ setting failed: %d\r\n", ret); + goto out; + } + } else if (asix_class->chipcode == AX_AX88772A_CHIPCODE) { + /* Check if the PHY registers have default settings */ + phy14h = usbh_asix_mdio_read(asix_class, asix_class->phy_addr, + AX88772A_PHY14H); + phy15h = usbh_asix_mdio_read(asix_class, asix_class->phy_addr, + AX88772A_PHY15H); + phy16h = usbh_asix_mdio_read(asix_class, asix_class->phy_addr, + AX88772A_PHY16H); + + USB_LOG_DBG("772a_hw_reset: MR20=0x%x MR21=0x%x MR22=0x%x\r\n", + phy14h, phy15h, phy16h); + + /* Restore PHY registers default setting if not */ + if (phy14h != AX88772A_PHY14H_DEFAULT) + usbh_asix_mdio_write(asix_class, asix_class->phy_addr, + AX88772A_PHY14H, + AX88772A_PHY14H_DEFAULT); + if (phy15h != AX88772A_PHY15H_DEFAULT) + usbh_asix_mdio_write(asix_class, asix_class->phy_addr, + AX88772A_PHY15H, + AX88772A_PHY15H_DEFAULT); + if (phy16h != AX88772A_PHY16H_DEFAULT) + usbh_asix_mdio_write(asix_class, asix_class->phy_addr, + AX88772A_PHY16H, + AX88772A_PHY16H_DEFAULT); + } + + ret = usbh_asix_write_cmd(asix_class, AX_CMD_WRITE_IPG0, + AX88772_IPG0_DEFAULT | AX88772_IPG1_DEFAULT, + AX88772_IPG2_DEFAULT, NULL, 0); + if (ret < 0) { + USB_LOG_ERR("Write IPG,IPG1,IPG2 failed: %d\r\n", ret); + goto out; + } + + /* Rewrite MAC address */ + ret = usbh_asix_write_cmd(asix_class, AX_CMD_WRITE_NODE_ID, 0, 0, asix_class->mac, ETH_ALEN); + if (ret < 0) + goto out; + + /* Set RX_CTL to default values with 2k buffer, and enable cactus */ + ret = usbh_asix_write_rx_ctl(asix_class, AX_DEFAULT_RX_CTL); + if (ret < 0) + goto out; + + ret = usbh_asix_write_medium_mode(asix_class, AX88772_MEDIUM_DEFAULT); + if (ret < 0) + return ret; + + /* Set RX_CTL to default values with 2k buffer, and enable cactus */ + ret = usbh_asix_write_rx_ctl(asix_class, AX_DEFAULT_RX_CTL); + if (ret < 0) + goto out; + + rx_ctl = usbh_asix_read_rx_ctl(asix_class); + USB_LOG_INFO("RX_CTL is 0x%04x after all initializations\r\n", rx_ctl); + + rx_ctl = usbh_asix_read_medium_status(asix_class); + USB_LOG_INFO("Medium Status is 0x%04x after all initializations\r\n", rx_ctl); + + return 0; + +out: + return ret; +} + +static void usbh_ax88772_mac_link_down(struct usbh_asix *asix_class) +{ + usbh_asix_write_medium_mode(asix_class, 0); +} + +static void usbh_ax88772_mac_link_up(struct usbh_asix *asix_class, int speed, int duplex, bool tx_pause, bool rx_pause) +{ + uint16_t m = AX_MEDIUM_AC | AX_MEDIUM_RE; + + m |= duplex ? AX_MEDIUM_FD : 0; + + switch (speed) { + case SPEED_100: + m |= AX_MEDIUM_PS; + break; + case SPEED_10: + break; + default: + return; + } + + if (tx_pause) + m |= AX_MEDIUM_TFC; + + if (rx_pause) + m |= AX_MEDIUM_RFC; + + usbh_asix_write_medium_mode(asix_class, m); +} + +static int usbh_asix_connect(struct usbh_hubport *hport, uint8_t intf) +{ + struct usb_endpoint_descriptor *ep_desc; + int ret; + + struct usbh_asix *asix_class = &g_asix_class; + + memset(asix_class, 0, sizeof(struct usbh_asix)); + + asix_class->hport = hport; + asix_class->intf = intf; + + hport->config.intf[intf].priv = asix_class; + + if ((hport->device_desc.idVendor == 0x0b95) && (hport->device_desc.idProduct == 0x772b)) { + asix_class->name = "ASIX AX88772B"; + } else if ((hport->device_desc.idVendor == 0x0b95) && (hport->device_desc.idProduct == 0x7720)) { + asix_class->name = "ASIX AX88772"; + } else if ((hport->device_desc.idVendor == 0x0b95) && (hport->device_desc.idProduct == 0x1780)) { + asix_class->name = "ASIX AX88178"; + } + + for (uint8_t i = 0; i < (ETH_ALEN >> 1); i++) { + ret = usbh_asix_read_cmd(asix_class, AX_CMD_READ_EEPROM, + 0x04 + i, 0, &asix_class->mac[i * 2], 2); + if (ret < 0) { + return ret; + } + } + + USB_LOG_INFO("asix MAC address %02x:%02x:%02x:%02x:%02x:%02x\r\n", + asix_class->mac[0], + asix_class->mac[1], + asix_class->mac[2], + asix_class->mac[3], + asix_class->mac[4], + asix_class->mac[5]); + + ret = usbh_asix_read_phy_addr(asix_class, true); + if (ret < 0) { + USB_LOG_ERR("Failed to read phy addr: %d\r\n", ret); + return ret; + } + asix_class->phy_addr = ret; + asix_class->embd_phy = ((ret & 0x1f) == AX_EMBD_PHY_ADDR); + + ret = usbh_asix_read_cmd(asix_class, AX_CMD_STATMNGSTS_REG, 0, 0, &asix_class->chipcode, 1); + if (ret < 0) { + USB_LOG_ERR("Failed to read STATMNGSTS_REG: %d\r\n", ret); + return ret; + } + + asix_class->chipcode &= AX_CHIPCODE_MASK; + USB_LOG_INFO("asix chipcode 0x%x\r\n", asix_class->chipcode); + + if (asix_class->chipcode == AX_AX88772_CHIPCODE) { + usbh_ax88772_hw_reset(asix_class); + } else { + usbh_ax88772a_hw_reset(asix_class); + } + for (uint8_t i = 0; i < hport->config.intf[intf].altsetting[0].intf_desc.bNumEndpoints; i++) { + ep_desc = &hport->config.intf[intf].altsetting[0].ep[i].ep_desc; + + if (USB_GET_ENDPOINT_TYPE(ep_desc->bmAttributes) == USB_ENDPOINT_TYPE_INTERRUPT) { + if (ep_desc->bEndpointAddress & 0x80) { + USBH_EP_INIT(asix_class->intin, ep_desc); + } else { + return -USB_ERR_NOTSUPP; + } + } else { + if (ep_desc->bEndpointAddress & 0x80) { + USBH_EP_INIT(asix_class->bulkin, ep_desc); + } else { + USBH_EP_INIT(asix_class->bulkout, ep_desc); + } + } + } + + if (asix_class->chipcode == AX_AX88772B_CHIPCODE) { + usbh_asix_mdio_write(asix_class, asix_class->phy_addr, 0, 0); + usbh_asix_mdio_read(asix_class, asix_class->phy_addr, 0); + + usbh_asix_mdio_write(asix_class, asix_class->phy_addr, 0, 0x8200); + usbh_asix_mdio_read(asix_class, asix_class->phy_addr, 0); + + usbh_asix_mdio_write(asix_class, asix_class->phy_addr, 0, 0x3900); + usbh_asix_mdio_read(asix_class, asix_class->phy_addr, 0); + + usbh_asix_mdio_write(asix_class, asix_class->phy_addr, 0, 0x3100); + usbh_asix_mdio_read(asix_class, asix_class->phy_addr, 4); + + usbh_asix_mdio_write(asix_class, asix_class->phy_addr, 4, 0x01e1); + usbh_asix_mdio_read(asix_class, asix_class->phy_addr, 1); + + usbh_asix_mdio_write(asix_class, asix_class->phy_addr, 0, 0x3300); + usbh_asix_mdio_read(asix_class, asix_class->phy_addr, 0); + } + + USB_LOG_INFO("Init %s done\r\n", asix_class->name); + + strncpy(hport->config.intf[intf].devname, DEV_FORMAT, CONFIG_USBHOST_DEV_NAMELEN); + + USB_LOG_INFO("Register ASIX Class:%s\r\n", hport->config.intf[intf].devname); + usbh_asix_run(asix_class); + return ret; +} + +static int usbh_asix_disconnect(struct usbh_hubport *hport, uint8_t intf) +{ + int ret = 0; + + struct usbh_asix *asix_class = (struct usbh_asix *)hport->config.intf[intf].priv; + + if (asix_class) { + if (asix_class->bulkin) { + usbh_kill_urb(&asix_class->bulkin_urb); + } + + if (asix_class->bulkout) { + usbh_kill_urb(&asix_class->bulkout_urb); + } + + if (asix_class->intin) { + usbh_kill_urb(&asix_class->intin_urb); + } + + if (hport->config.intf[intf].devname[0] != '\0') { + usb_osal_thread_schedule_other(); + USB_LOG_INFO("Unregister ASIX Class:%s\r\n", hport->config.intf[intf].devname); + usbh_asix_stop(asix_class); + } + + memset(asix_class, 0, sizeof(struct usbh_asix)); + } + + return ret; +} + +int usbh_asix_get_connect_status(struct usbh_asix *asix_class) +{ + int ret; + + usbh_int_urb_fill(&asix_class->intin_urb, asix_class->hport, asix_class->intin, g_asix_inttx_buffer, 8, USB_OSAL_WAITING_FOREVER, NULL, NULL); + ret = usbh_submit_urb(&asix_class->intin_urb); + if (ret < 0) { + return ret; + } + + if (g_asix_inttx_buffer[1] == 0x00) { + if (g_asix_inttx_buffer[2] & 0x01) { + asix_class->connect_status = true; + usbh_ax88772_mac_link_up(asix_class, SPEED_100, 1, 1, 1); + usbh_asix_set_multicast(asix_class); + } else { + asix_class->connect_status = false; + usbh_ax88772_mac_link_down(asix_class); + } + } + return 0; +} + +void usbh_asix_rx_thread(CONFIG_USB_OSAL_THREAD_SET_ARGV) +{ + uint32_t g_asix_rx_length; + int ret; + uint16_t len; + uint16_t len_crc; + uint32_t data_offset; +#if CONFIG_USBHOST_ASIX_ETH_MAX_RX_SIZE <= (16 * 1024) + uint32_t transfer_size = CONFIG_USBHOST_ASIX_ETH_MAX_RX_SIZE; +#else + uint32_t transfer_size = (16 * 1024); +#endif + + (void)CONFIG_USB_OSAL_THREAD_GET_ARGV; + USB_LOG_INFO("Create asix rx thread\r\n"); + // clang-format off +find_class: + // clang-format on + g_asix_class.connect_status = false; + if (usbh_find_class_instance("/dev/asix") == NULL) { + goto delete; + } + + while (g_asix_class.connect_status == false) { + ret = usbh_asix_get_connect_status(&g_asix_class); + if (ret < 0) { + usb_osal_msleep(100); + goto find_class; + } + usb_osal_msleep(128); + } + + g_asix_rx_length = 0; + while (1) { + usbh_bulk_urb_fill(&g_asix_class.bulkin_urb, g_asix_class.hport, g_asix_class.bulkin, &g_asix_rx_buffer[g_asix_rx_length], transfer_size, USB_OSAL_WAITING_FOREVER, NULL, NULL); + ret = usbh_submit_urb(&g_asix_class.bulkin_urb); + if (ret < 0) { + goto find_class; + } + + g_asix_rx_length += g_asix_class.bulkin_urb.actual_length; + + /* A transfer is complete because last packet is a short packet. + * Short packet is not zero, match g_asix_rx_length % USB_GET_MAXPACKETSIZE(g_asix_class.bulkin->wMaxPacketSize). + * Short packet is zero, check if g_asix_class.bulkin_urb.actual_length < transfer_size, for example transfer is complete with size is 1024 < 2048. + */ + if (g_asix_rx_length % USB_GET_MAXPACKETSIZE(g_asix_class.bulkin->wMaxPacketSize) || + (g_asix_class.bulkin_urb.actual_length < transfer_size)) { + USB_LOG_DBG("rxlen:%d\r\n", g_asix_rx_length); + + data_offset = 0; + while (g_asix_rx_length > 0) { + len = ((uint16_t)g_asix_rx_buffer[data_offset + 0] | ((uint16_t)(g_asix_rx_buffer[data_offset + 1]) << 8)) & 0x7ff; + len_crc = g_asix_rx_buffer[data_offset + 2] | ((uint16_t)(g_asix_rx_buffer[data_offset + 3]) << 8); + + if (len != (~len_crc & 0x7ff)) { + USB_LOG_ERR("rx header error\r\n"); + g_asix_rx_length = 0; + continue; + } + + uint8_t *buf = (uint8_t *)&g_asix_rx_buffer[data_offset + 4]; + usbh_asix_eth_input(buf, len); + g_asix_rx_length -= (len + 4); + data_offset += (len + 4); + + if (g_asix_rx_length < 4) { + g_asix_rx_length = 0; + } + } + } else { +#if CONFIG_USBHOST_ASIX_ETH_MAX_RX_SIZE <= (16 * 1024) + if (g_asix_rx_length == CONFIG_USBHOST_ASIX_ETH_MAX_RX_SIZE) { +#else + if ((g_asix_rx_length + (16 * 1024)) > CONFIG_USBHOST_ASIX_ETH_MAX_RX_SIZE) { +#endif + USB_LOG_ERR("Rx packet is overflow, please reduce tcp window size or increase CONFIG_USBHOST_ASIX_ETH_MAX_RX_SIZE\r\n"); + while (1) { + } + } + } + } + // clang-format off +delete: + USB_LOG_INFO("Delete asix rx thread\r\n"); + usb_osal_thread_delete(NULL); + // clang-format on +} + +uint8_t *usbh_asix_get_eth_txbuf(void) +{ + return &g_asix_tx_buffer[4]; +} + +int usbh_asix_eth_output(uint32_t buflen) +{ + uint16_t actual_len; + + if (g_asix_class.connect_status == false) { + return -USB_ERR_NOTCONN; + } + + g_asix_tx_buffer[0] = buflen & 0xff; + g_asix_tx_buffer[1] = (buflen >> 8) & 0xff; + g_asix_tx_buffer[2] = ~g_asix_tx_buffer[0]; + g_asix_tx_buffer[3] = ~g_asix_tx_buffer[1]; + + if (!(buflen + 4) % USB_GET_MAXPACKETSIZE(g_asix_class.bulkout->wMaxPacketSize)) { + USB_LOG_DBG("txlen:%d\r\n", buflen + 8); + g_asix_tx_buffer[buflen + 4 + 0] = 0x00; + g_asix_tx_buffer[buflen + 4 + 1] = 0x00; + g_asix_tx_buffer[buflen + 4 + 2] = 0xff; + g_asix_tx_buffer[buflen + 4 + 3] = 0xff; + actual_len = buflen + 8; + } else { + USB_LOG_DBG("txlen:%d\r\n", buflen + 4); + actual_len = buflen + 4; + } + + usbh_bulk_urb_fill(&g_asix_class.bulkout_urb, g_asix_class.hport, g_asix_class.bulkout, g_asix_tx_buffer, actual_len, USB_OSAL_WAITING_FOREVER, NULL, NULL); + return usbh_submit_urb(&g_asix_class.bulkout_urb); +} + +static const uint16_t asix_id_table[][2] = { + { 0x0B95, 0x772B }, + { 0x0B95, 0x7720 }, + { 0, 0 }, +}; + +static const struct usbh_class_driver asix_class_driver = { + .driver_name = "asix", + .connect = usbh_asix_connect, + .disconnect = usbh_asix_disconnect +}; + +CLASS_INFO_DEFINE const struct usbh_class_info asix_class_info = { + .match_flags = USB_CLASS_MATCH_VID_PID | USB_CLASS_MATCH_INTF_CLASS, + .bInterfaceClass = 0xff, + .bInterfaceSubClass = 0x00, + .bInterfaceProtocol = 0x00, + .id_table = asix_id_table, + .class_driver = &asix_class_driver +}; \ No newline at end of file diff --git a/kernel/cherryusb/class/vendor/net/usbh_asix.h b/kernel/cherryusb/class/vendor/net/usbh_asix.h new file mode 100644 index 0000000..bdeb0e3 --- /dev/null +++ b/kernel/cherryusb/class/vendor/net/usbh_asix.h @@ -0,0 +1,177 @@ +/* + * Copyright (c) 2024, sakumisu + * + * SPDX-License-Identifier: Apache-2.0 + */ +#ifndef USBH_ASIX_H +#define USBH_ASIX_H + +/* ASIX AX8817X based USB 2.0 Ethernet Devices */ + +#define AX_CMD_SET_SW_MII 0x06 +#define AX_CMD_READ_MII_REG 0x07 +#define AX_CMD_WRITE_MII_REG 0x08 +#define AX_CMD_STATMNGSTS_REG 0x09 +#define AX_CMD_SET_HW_MII 0x0a +#define AX_CMD_READ_EEPROM 0x0b +#define AX_CMD_WRITE_EEPROM 0x0c +#define AX_CMD_WRITE_ENABLE 0x0d +#define AX_CMD_WRITE_DISABLE 0x0e +#define AX_CMD_READ_RX_CTL 0x0f +#define AX_CMD_WRITE_RX_CTL 0x10 +#define AX_CMD_READ_IPG012 0x11 +#define AX_CMD_WRITE_IPG0 0x12 +#define AX_CMD_WRITE_IPG1 0x13 +#define AX_CMD_READ_NODE_ID 0x13 +#define AX_CMD_WRITE_NODE_ID 0x14 +#define AX_CMD_WRITE_IPG2 0x14 +#define AX_CMD_WRITE_MULTI_FILTER 0x16 +#define AX88172_CMD_READ_NODE_ID 0x17 +#define AX_CMD_READ_PHY_ID 0x19 +#define AX_CMD_READ_MEDIUM_STATUS 0x1a +#define AX_CMD_WRITE_MEDIUM_MODE 0x1b +#define AX_CMD_READ_MONITOR_MODE 0x1c +#define AX_CMD_WRITE_MONITOR_MODE 0x1d +#define AX_CMD_READ_GPIOS 0x1e +#define AX_CMD_WRITE_GPIOS 0x1f +#define AX_CMD_SW_RESET 0x20 +#define AX_CMD_SW_PHY_STATUS 0x21 +#define AX_CMD_SW_PHY_SELECT 0x22 +#define AX_QCTCTRL 0x2A + +#define AX_CHIPCODE_MASK 0x70 +#define AX_AX88772_CHIPCODE 0x00 +#define AX_AX88772A_CHIPCODE 0x10 +#define AX_AX88772B_CHIPCODE 0x20 +#define AX_HOST_EN 0x01 + +#define AX_PHYSEL_PSEL 0x01 +#define AX_PHYSEL_SSMII 0 +#define AX_PHYSEL_SSEN 0x10 + +#define AX_PHY_SELECT_MASK (BIT(3) | BIT(2)) +#define AX_PHY_SELECT_INTERNAL 0 +#define AX_PHY_SELECT_EXTERNAL BIT(2) + +#define AX_MONITOR_MODE 0x01 +#define AX_MONITOR_LINK 0x02 +#define AX_MONITOR_MAGIC 0x04 +#define AX_MONITOR_HSFS 0x10 + +/* AX88172 Medium Status Register values */ +#define AX88172_MEDIUM_FD 0x02 +#define AX88172_MEDIUM_TX 0x04 +#define AX88172_MEDIUM_FC 0x10 +#define AX88172_MEDIUM_DEFAULT \ + (AX88172_MEDIUM_FD | AX88172_MEDIUM_TX | AX88172_MEDIUM_FC) + +#define AX_MCAST_FILTER_SIZE 8 +#define AX_MAX_MCAST 64 + +#define AX_SWRESET_CLEAR 0x00 +#define AX_SWRESET_RR 0x01 +#define AX_SWRESET_RT 0x02 +#define AX_SWRESET_PRTE 0x04 +#define AX_SWRESET_PRL 0x08 +#define AX_SWRESET_BZ 0x10 +#define AX_SWRESET_IPRL 0x20 +#define AX_SWRESET_IPPD 0x40 + +#define AX88772_IPG0_DEFAULT 0x15 +#define AX88772_IPG1_DEFAULT 0x0c +#define AX88772_IPG2_DEFAULT 0x12 + +/* AX88772 & AX88178 Medium Mode Register */ +#define AX_MEDIUM_PF 0x0080 +#define AX_MEDIUM_JFE 0x0040 +#define AX_MEDIUM_TFC 0x0020 +#define AX_MEDIUM_RFC 0x0010 +#define AX_MEDIUM_ENCK 0x0008 +#define AX_MEDIUM_AC 0x0004 +#define AX_MEDIUM_FD 0x0002 +#define AX_MEDIUM_GM 0x0001 +#define AX_MEDIUM_SM 0x1000 +#define AX_MEDIUM_SBP 0x0800 +#define AX_MEDIUM_PS 0x0200 +#define AX_MEDIUM_RE 0x0100 + +#define AX88178_MEDIUM_DEFAULT \ + (AX_MEDIUM_PS | AX_MEDIUM_FD | AX_MEDIUM_AC | \ + AX_MEDIUM_RFC | AX_MEDIUM_TFC | AX_MEDIUM_JFE | \ + AX_MEDIUM_RE) + +#define AX88772_MEDIUM_DEFAULT \ + (AX_MEDIUM_FD | AX_MEDIUM_PS | \ + AX_MEDIUM_AC | AX_MEDIUM_RE) + +/* AX88772 & AX88178 RX_CTL values */ +#define AX_RX_CTL_SO 0x0080 +#define AX_RX_CTL_AP 0x0020 +#define AX_RX_CTL_AM 0x0010 +#define AX_RX_CTL_AB 0x0008 +#define AX_RX_CTL_SEP 0x0004 +#define AX_RX_CTL_AMALL 0x0002 +#define AX_RX_CTL_PRO 0x0001 +#define AX_RX_CTL_MFB_2048 0x0000 +#define AX_RX_CTL_MFB_4096 0x0100 +#define AX_RX_CTL_MFB_8192 0x0200 +#define AX_RX_CTL_MFB_16384 0x0300 + +#define AX_DEFAULT_RX_CTL (AX_RX_CTL_SO | AX_RX_CTL_AB) + +/* GPIO 0 .. 2 toggles */ +#define AX_GPIO_GPO0EN 0x01 /* GPIO0 Output enable */ +#define AX_GPIO_GPO_0 0x02 /* GPIO0 Output value */ +#define AX_GPIO_GPO1EN 0x04 /* GPIO1 Output enable */ +#define AX_GPIO_GPO_1 0x08 /* GPIO1 Output value */ +#define AX_GPIO_GPO2EN 0x10 /* GPIO2 Output enable */ +#define AX_GPIO_GPO_2 0x20 /* GPIO2 Output value */ +#define AX_GPIO_RESERVED 0x40 /* Reserved */ +#define AX_GPIO_RSE 0x80 /* Reload serial EEPROM */ + +#define AX_EEPROM_MAGIC 0xdeadbeef +#define AX_EEPROM_LEN 0x200 + +#define AX_EMBD_PHY_ADDR 0x10 + +struct usbh_asix { + struct usbh_hubport *hport; + struct usb_endpoint_descriptor *bulkin; /* Bulk IN endpoint */ + struct usb_endpoint_descriptor *bulkout; /* Bulk OUT endpoint */ + struct usb_endpoint_descriptor *intin; /* INTR IN endpoint */ + struct usbh_urb bulkout_urb; + struct usbh_urb bulkin_urb; + struct usbh_urb intin_urb; + + uint8_t intf; + char *name; + uint8_t phy_addr; + uint8_t embd_phy; + uint8_t chipcode; + uint16_t mac_capabilities; + + bool connect_status; + uint8_t mac[6]; + + void *user_data; +}; + +#ifdef __cplusplus +extern "C" { +#endif + +int usbh_asix_get_connect_status(struct usbh_asix *asix_class); + +void usbh_asix_run(struct usbh_asix *asix_class); +void usbh_asix_stop(struct usbh_asix *asix_class); + +uint8_t *usbh_asix_get_eth_txbuf(void); +int usbh_asix_eth_output(uint32_t buflen); +void usbh_asix_eth_input(uint8_t *buf, uint32_t buflen); +void usbh_asix_rx_thread(CONFIG_USB_OSAL_THREAD_SET_ARGV); + +#ifdef __cplusplus +} +#endif + +#endif /* USBH_ASIX_H */ \ No newline at end of file diff --git a/kernel/cherryusb/class/vendor/net/usbh_rtl8152.c b/kernel/cherryusb/class/vendor/net/usbh_rtl8152.c new file mode 100644 index 0000000..50269f2 --- /dev/null +++ b/kernel/cherryusb/class/vendor/net/usbh_rtl8152.c @@ -0,0 +1,2272 @@ +/* + * Copyright (c) 2024, sakumisu + * + * SPDX-License-Identifier: Apache-2.0 + */ +#include "usbh_core.h" +#include "usbh_rtl8152.h" + +#undef USB_DBG_TAG +#define USB_DBG_TAG "rtl8152" +#include "usb_log.h" + +#define DEV_FORMAT "/dev/rtl8152" + +static USB_NOCACHE_RAM_SECTION USB_MEM_ALIGNX uint8_t g_rtl8152_rx_buffer[USB_ALIGN_UP(CONFIG_USBHOST_RTL8152_ETH_MAX_RX_SIZE, CONFIG_USB_ALIGN_SIZE)]; +static USB_NOCACHE_RAM_SECTION USB_MEM_ALIGNX uint8_t g_rtl8152_tx_buffer[USB_ALIGN_UP(CONFIG_USBHOST_RTL8152_ETH_MAX_TX_SIZE, CONFIG_USB_ALIGN_SIZE)]; +static USB_NOCACHE_RAM_SECTION USB_MEM_ALIGNX uint8_t g_rtl8152_inttx_buffer[USB_ALIGN_UP(2, CONFIG_USB_ALIGN_SIZE)]; + +static USB_NOCACHE_RAM_SECTION USB_MEM_ALIGNX uint8_t g_rtl8152_buf[USB_ALIGN_UP(32, CONFIG_USB_ALIGN_SIZE)]; + +static struct usbh_rtl8152 g_rtl8152_class; + +#define RTL8152_REQ_GET_REGS 0x05 +#define RTL8152_REQ_SET_REGS 0x05 + +#define BYTE_EN_DWORD 0xff +#define BYTE_EN_WORD 0x33 +#define BYTE_EN_BYTE 0x11 +#define BYTE_EN_SIX_BYTES 0x3f +#define BYTE_EN_START_MASK 0x0f +#define BYTE_EN_END_MASK 0xf0 + +#define MCU_TYPE_PLA 0x0100 +#define MCU_TYPE_USB 0x0000 + +/* Define these values to match your device */ +#define VENDOR_ID_REALTEK 0x0bda +#define VENDOR_ID_MICROSOFT 0x045e +#define VENDOR_ID_SAMSUNG 0x04e8 +#define VENDOR_ID_LENOVO 0x17ef +#define VENDOR_ID_LINKSYS 0x13b1 +#define VENDOR_ID_NVIDIA 0x0955 +#define VENDOR_ID_TPLINK 0x2357 +#define VENDOR_ID_DLINK 0x2001 +#define VENDOR_ID_ASUS 0x0b05 + +#define R8152_PHY_ID 32 + +#define PLA_IDR 0xc000 +#define PLA_RCR 0xc010 +#define PLA_RCR1 0xc012 +#define PLA_RMS 0xc016 +#define PLA_RXFIFO_CTRL0 0xc0a0 +#define PLA_RXFIFO_FULL 0xc0a2 +#define PLA_RXFIFO_CTRL1 0xc0a4 +#define PLA_RX_FIFO_FULL 0xc0a6 +#define PLA_RXFIFO_CTRL2 0xc0a8 +#define PLA_RX_FIFO_EMPTY 0xc0aa +#define PLA_DMY_REG0 0xc0b0 +#define PLA_FMC 0xc0b4 +#define PLA_CFG_WOL 0xc0b6 +#define PLA_TEREDO_CFG 0xc0bc +#define PLA_TEREDO_WAKE_BASE 0xc0c4 +#define PLA_MAR 0xcd00 +#define PLA_BACKUP 0xd000 +#define PLA_BDC_CR 0xd1a0 +#define PLA_TEREDO_TIMER 0xd2cc +#define PLA_REALWOW_TIMER 0xd2e8 +#define PLA_UPHY_TIMER 0xd388 +#define PLA_SUSPEND_FLAG 0xd38a +#define PLA_INDICATE_FALG 0xd38c +#define PLA_MACDBG_PRE 0xd38c /* RTL_VER_04 only */ +#define PLA_MACDBG_POST 0xd38e /* RTL_VER_04 only */ +#define PLA_EXTRA_STATUS 0xd398 +#define PLA_GPHY_CTRL 0xd3ae +#define PLA_POL_GPIO_CTRL 0xdc6a +#define PLA_EFUSE_DATA 0xdd00 +#define PLA_EFUSE_CMD 0xdd02 +#define PLA_LEDSEL 0xdd90 +#define PLA_LED_FEATURE 0xdd92 +#define PLA_PHYAR 0xde00 +#define PLA_BOOT_CTRL 0xe004 +#define PLA_LWAKE_CTRL_REG 0xe007 +#define PLA_GPHY_INTR_IMR 0xe022 +#define PLA_EEE_CR 0xe040 +#define PLA_EEE_TXTWSYS 0xe04c +#define PLA_EEE_TXTWSYS_2P5G 0xe058 +#define PLA_EEEP_CR 0xe080 +#define PLA_MAC_PWR_CTRL 0xe0c0 +#define PLA_MAC_PWR_CTRL2 0xe0ca +#define PLA_MAC_PWR_CTRL3 0xe0cc +#define PLA_MAC_PWR_CTRL4 0xe0ce +#define PLA_WDT6_CTRL 0xe428 +#define PLA_TCR0 0xe610 +#define PLA_TCR1 0xe612 +#define PLA_MTPS 0xe615 +#define PLA_TXFIFO_CTRL 0xe618 +#define PLA_TXFIFO_FULL 0xe61a +#define PLA_RSTTALLY 0xe800 +#define PLA_CR 0xe813 +#define PLA_CRWECR 0xe81c +#define PLA_CONFIG12 0xe81e /* CONFIG1, CONFIG2 */ +#define PLA_CONFIG34 0xe820 /* CONFIG3, CONFIG4 */ +#define PLA_CONFIG5 0xe822 +#define PLA_PHY_PWR 0xe84c +#define PLA_OOB_CTRL 0xe84f +#define PLA_CPCR 0xe854 +#define PLA_MISC_0 0xe858 +#define PLA_MISC_1 0xe85a +#define PLA_OCP_GPHY_BASE 0xe86c +#define PLA_TALLYCNT 0xe890 +#define PLA_SFF_STS_7 0xe8de +#define PLA_PHYSTATUS 0xe908 +#define PLA_CONFIG6 0xe90a /* CONFIG6 */ +#define PLA_USB_CFG 0xe952 +#define PLA_BP_BA 0xfc26 +#define PLA_BP_0 0xfc28 +#define PLA_BP_1 0xfc2a +#define PLA_BP_2 0xfc2c +#define PLA_BP_3 0xfc2e +#define PLA_BP_4 0xfc30 +#define PLA_BP_5 0xfc32 +#define PLA_BP_6 0xfc34 +#define PLA_BP_7 0xfc36 +#define PLA_BP_EN 0xfc38 + +#define USB_USB2PHY 0xb41e +#define USB_SSPHYLINK1 0xb426 +#define USB_SSPHYLINK2 0xb428 +#define USB_L1_CTRL 0xb45e +#define USB_U2P3_CTRL 0xb460 +#define USB_CSR_DUMMY1 0xb464 +#define USB_CSR_DUMMY2 0xb466 +#define USB_DEV_STAT 0xb808 +#define USB_CONNECT_TIMER 0xcbf8 +#define USB_MSC_TIMER 0xcbfc +#define USB_BURST_SIZE 0xcfc0 +#define USB_FW_FIX_EN0 0xcfca +#define USB_FW_FIX_EN1 0xcfcc +#define USB_LPM_CONFIG 0xcfd8 +#define USB_ECM_OPTION 0xcfee +#define USB_CSTMR 0xcfef /* RTL8153A */ +#define USB_MISC_2 0xcfff +#define USB_ECM_OP 0xd26b +#define USB_GPHY_CTRL 0xd284 +#define USB_SPEED_OPTION 0xd32a +#define USB_FW_CTRL 0xd334 /* RTL8153B */ +#define USB_FC_TIMER 0xd340 +#define USB_USB_CTRL 0xd406 +#define USB_PHY_CTRL 0xd408 +#define USB_TX_AGG 0xd40a +#define USB_RX_BUF_TH 0xd40c +#define USB_USB_TIMER 0xd428 +#define USB_RX_EARLY_TIMEOUT 0xd42c +#define USB_RX_EARLY_SIZE 0xd42e +#define USB_PM_CTRL_STATUS 0xd432 /* RTL8153A */ +#define USB_RX_EXTRA_AGGR_TMR 0xd432 /* RTL8153B */ +#define USB_TX_DMA 0xd434 +#define USB_UPT_RXDMA_OWN 0xd437 +#define USB_UPHY3_MDCMDIO 0xd480 +#define USB_TOLERANCE 0xd490 +#define USB_LPM_CTRL 0xd41a +#define USB_BMU_RESET 0xd4b0 +#define USB_BMU_CONFIG 0xd4b4 +#define USB_U1U2_TIMER 0xd4da +#define USB_FW_TASK 0xd4e8 /* RTL8153B */ +#define USB_RX_AGGR_NUM 0xd4ee +#define USB_UPS_CTRL 0xd800 +#define USB_POWER_CUT 0xd80a +#define USB_MISC_0 0xd81a +#define USB_MISC_1 0xd81f +#define USB_AFE_CTRL2 0xd824 +#define USB_UPHY_XTAL 0xd826 +#define USB_UPS_CFG 0xd842 +#define USB_UPS_FLAGS 0xd848 +#define USB_WDT1_CTRL 0xe404 +#define USB_WDT11_CTRL 0xe43c +#define USB_BP_BA PLA_BP_BA +#define USB_BP_0 PLA_BP_0 +#define USB_BP_1 PLA_BP_1 +#define USB_BP_2 PLA_BP_2 +#define USB_BP_3 PLA_BP_3 +#define USB_BP_4 PLA_BP_4 +#define USB_BP_5 PLA_BP_5 +#define USB_BP_6 PLA_BP_6 +#define USB_BP_7 PLA_BP_7 +#define USB_BP_EN PLA_BP_EN /* RTL8153A */ +#define USB_BP_8 0xfc38 /* RTL8153B */ +#define USB_BP_9 0xfc3a +#define USB_BP_10 0xfc3c +#define USB_BP_11 0xfc3e +#define USB_BP_12 0xfc40 +#define USB_BP_13 0xfc42 +#define USB_BP_14 0xfc44 +#define USB_BP_15 0xfc46 +#define USB_BP2_EN 0xfc48 + +/* OCP Registers */ +#define OCP_ALDPS_CONFIG 0x2010 +#define OCP_EEE_CONFIG1 0x2080 +#define OCP_EEE_CONFIG2 0x2092 +#define OCP_EEE_CONFIG3 0x2094 +#define OCP_BASE_MII 0xa400 +#define OCP_EEE_AR 0xa41a +#define OCP_EEE_DATA 0xa41c +#define OCP_PHY_STATUS 0xa420 +#define OCP_INTR_EN 0xa424 +#define OCP_NCTL_CFG 0xa42c +#define OCP_POWER_CFG 0xa430 +#define OCP_EEE_CFG 0xa432 +#define OCP_SRAM_ADDR 0xa436 +#define OCP_SRAM_DATA 0xa438 +#define OCP_DOWN_SPEED 0xa442 +#define OCP_EEE_ABLE 0xa5c4 +#define OCP_EEE_ADV 0xa5d0 +#define OCP_EEE_LPABLE 0xa5d2 +#define OCP_10GBT_CTRL 0xa5d4 +#define OCP_10GBT_STAT 0xa5d6 +#define OCP_EEE_ADV2 0xa6d4 +#define OCP_PHY_STATE 0xa708 /* nway state for 8153 */ +#define OCP_PHY_PATCH_STAT 0xb800 +#define OCP_PHY_PATCH_CMD 0xb820 +#define OCP_PHY_LOCK 0xb82e +#define OCP_ADC_IOFFSET 0xbcfc +#define OCP_ADC_CFG 0xbc06 +#define OCP_SYSCLK_CFG 0xc416 + +/* SRAM Register */ +#define SRAM_GREEN_CFG 0x8011 +#define SRAM_LPF_CFG 0x8012 +#define SRAM_GPHY_FW_VER 0x801e +#define SRAM_10M_AMP1 0x8080 +#define SRAM_10M_AMP2 0x8082 +#define SRAM_IMPEDANCE 0x8084 +#define SRAM_PHY_LOCK 0xb82e + +/* PLA_RCR */ +#define RCR_AAP 0x00000001 +#define RCR_APM 0x00000002 +#define RCR_AM 0x00000004 +#define RCR_AB 0x00000008 +#define RCR_ACPT_ALL (RCR_AAP | RCR_APM | RCR_AM | RCR_AB) +#define SLOT_EN BIT(11) + +/* PLA_RCR1 */ +#define OUTER_VLAN BIT(7) +#define INNER_VLAN BIT(6) + +/* PLA_RXFIFO_CTRL0 */ +#define RXFIFO_THR1_NORMAL 0x00080002 +#define RXFIFO_THR1_OOB 0x01800003 + +/* PLA_RXFIFO_FULL */ +#define RXFIFO_FULL_MASK 0xfff + +/* PLA_RXFIFO_CTRL1 */ +#define RXFIFO_THR2_FULL 0x00000060 +#define RXFIFO_THR2_HIGH 0x00000038 +#define RXFIFO_THR2_OOB 0x0000004a +#define RXFIFO_THR2_NORMAL 0x00a0 + +/* PLA_RXFIFO_CTRL2 */ +#define RXFIFO_THR3_FULL 0x00000078 +#define RXFIFO_THR3_HIGH 0x00000048 +#define RXFIFO_THR3_OOB 0x0000005a +#define RXFIFO_THR3_NORMAL 0x0110 + +/* PLA_TXFIFO_CTRL */ +#define TXFIFO_THR_NORMAL 0x00400008 +#define TXFIFO_THR_NORMAL2 0x01000008 + +/* PLA_DMY_REG0 */ +#define ECM_ALDPS 0x0002 + +/* PLA_FMC */ +#define FMC_FCR_MCU_EN 0x0001 + +/* PLA_EEEP_CR */ +#define EEEP_CR_EEEP_TX 0x0002 + +/* PLA_WDT6_CTRL */ +#define WDT6_SET_MODE 0x0010 + +/* PLA_TCR0 */ +#define TCR0_TX_EMPTY 0x0800 +#define TCR0_AUTO_FIFO 0x0080 + +/* PLA_TCR1 */ +#define VERSION_MASK 0x7cf0 +#define IFG_MASK (BIT(3) | BIT(9) | BIT(8)) +#define IFG_144NS BIT(9) +#define IFG_96NS (BIT(9) | BIT(8)) + +/* PLA_MTPS */ +#define MTPS_JUMBO (12 * 1024 / 64) +#define MTPS_DEFAULT (6 * 1024 / 64) + +/* PLA_RSTTALLY */ +#define TALLY_RESET 0x0001 + +/* PLA_CR */ +#define CR_RST 0x10 +#define CR_RE 0x08 +#define CR_TE 0x04 + +/* PLA_CRWECR */ +#define CRWECR_NORAML 0x00 +#define CRWECR_CONFIG 0xc0 + +/* PLA_OOB_CTRL */ +#define NOW_IS_OOB 0x80 +#define TXFIFO_EMPTY 0x20 +#define RXFIFO_EMPTY 0x10 +#define LINK_LIST_READY 0x02 +#define DIS_MCU_CLROOB 0x01 +#define FIFO_EMPTY (TXFIFO_EMPTY | RXFIFO_EMPTY) + +/* PLA_MISC_1 */ +#define RXDY_GATED_EN 0x0008 + +/* PLA_SFF_STS_7 */ +#define RE_INIT_LL 0x8000 +#define MCU_BORW_EN 0x4000 + +/* PLA_CPCR */ +#define FLOW_CTRL_EN BIT(0) +#define CPCR_RX_VLAN 0x0040 + +/* PLA_CFG_WOL */ +#define MAGIC_EN 0x0001 + +/* PLA_TEREDO_CFG */ +#define TEREDO_SEL 0x8000 +#define TEREDO_WAKE_MASK 0x7f00 +#define TEREDO_RS_EVENT_MASK 0x00fe +#define OOB_TEREDO_EN 0x0001 + +/* PLA_BDC_CR */ +#define ALDPS_PROXY_MODE 0x0001 + +/* PLA_EFUSE_CMD */ +#define EFUSE_READ_CMD BIT(15) +#define EFUSE_DATA_BIT16 BIT(7) + +/* PLA_CONFIG34 */ +#define LINK_ON_WAKE_EN 0x0010 +#define LINK_OFF_WAKE_EN 0x0008 + +/* PLA_CONFIG6 */ +#define LANWAKE_CLR_EN BIT(0) + +/* PLA_USB_CFG */ +#define EN_XG_LIP BIT(1) +#define EN_G_LIP BIT(2) + +/* PLA_CONFIG5 */ +#define BWF_EN 0x0040 +#define MWF_EN 0x0020 +#define UWF_EN 0x0010 +#define LAN_WAKE_EN 0x0002 + +/* PLA_LED_FEATURE */ +#define LED_MODE_MASK 0x0700 + +/* PLA_PHY_PWR */ +#define TX_10M_IDLE_EN 0x0080 +#define PFM_PWM_SWITCH 0x0040 +#define TEST_IO_OFF BIT(4) + +/* PLA_MAC_PWR_CTRL */ +#define D3_CLK_GATED_EN 0x00004000 +#define MCU_CLK_RATIO 0x07010f07 +#define MCU_CLK_RATIO_MASK 0x0f0f0f0f +#define ALDPS_SPDWN_RATIO 0x0f87 + +/* PLA_MAC_PWR_CTRL2 */ +#define EEE_SPDWN_RATIO 0x8007 +#define MAC_CLK_SPDWN_EN BIT(15) +#define EEE_SPDWN_RATIO_MASK 0xff + +/* PLA_MAC_PWR_CTRL3 */ +#define PLA_MCU_SPDWN_EN BIT(14) +#define PKT_AVAIL_SPDWN_EN 0x0100 +#define SUSPEND_SPDWN_EN 0x0004 +#define U1U2_SPDWN_EN 0x0002 +#define L1_SPDWN_EN 0x0001 + +/* PLA_MAC_PWR_CTRL4 */ +#define PWRSAVE_SPDWN_EN 0x1000 +#define RXDV_SPDWN_EN 0x0800 +#define TX10MIDLE_EN 0x0100 +#define IDLE_SPDWN_EN BIT(6) +#define TP100_SPDWN_EN 0x0020 +#define TP500_SPDWN_EN 0x0010 +#define TP1000_SPDWN_EN 0x0008 +#define EEE_SPDWN_EN 0x0001 + +/* PLA_GPHY_INTR_IMR */ +#define GPHY_STS_MSK 0x0001 +#define SPEED_DOWN_MSK 0x0002 +#define SPDWN_RXDV_MSK 0x0004 +#define SPDWN_LINKCHG_MSK 0x0008 + +/* PLA_PHYAR */ +#define PHYAR_FLAG 0x80000000 + +/* PLA_EEE_CR */ +#define EEE_RX_EN 0x0001 +#define EEE_TX_EN 0x0002 + +/* PLA_BOOT_CTRL */ +#define AUTOLOAD_DONE 0x0002 + +/* PLA_LWAKE_CTRL_REG */ +#define LANWAKE_PIN BIT(7) + +/* PLA_SUSPEND_FLAG */ +#define LINK_CHG_EVENT BIT(0) + +/* PLA_INDICATE_FALG */ +#define UPCOMING_RUNTIME_D3 BIT(0) + +/* PLA_MACDBG_PRE and PLA_MACDBG_POST */ +#define DEBUG_OE BIT(0) +#define DEBUG_LTSSM 0x0082 + +/* PLA_EXTRA_STATUS */ +#define CUR_LINK_OK BIT(15) +#define U3P3_CHECK_EN BIT(7) /* RTL_VER_05 only */ +#define LINK_CHANGE_FLAG BIT(8) +#define POLL_LINK_CHG BIT(0) + +/* PLA_GPHY_CTRL */ +#define GPHY_FLASH BIT(1) + +/* PLA_POL_GPIO_CTRL */ +#define DACK_DET_EN BIT(15) +#define POL_GPHY_PATCH BIT(4) + +/* USB_USB2PHY */ +#define USB2PHY_SUSPEND 0x0001 +#define USB2PHY_L1 0x0002 + +/* USB_SSPHYLINK1 */ +#define DELAY_PHY_PWR_CHG BIT(1) + +/* USB_SSPHYLINK2 */ +#define pwd_dn_scale_mask 0x3ffe +#define pwd_dn_scale(x) ((x) << 1) + +/* USB_CSR_DUMMY1 */ +#define DYNAMIC_BURST 0x0001 + +/* USB_CSR_DUMMY2 */ +#define EP4_FULL_FC 0x0001 + +/* USB_DEV_STAT */ +#define STAT_SPEED_MASK 0x0006 +#define STAT_SPEED_HIGH 0x0000 +#define STAT_SPEED_FULL 0x0002 + +/* USB_FW_FIX_EN0 */ +#define FW_FIX_SUSPEND BIT(14) + +/* USB_FW_FIX_EN1 */ +#define FW_IP_RESET_EN BIT(9) + +/* USB_LPM_CONFIG */ +#define LPM_U1U2_EN BIT(0) + +/* USB_TX_AGG */ +#define TX_AGG_MAX_THRESHOLD 0x03 + +/* USB_RX_BUF_TH */ +#define RX_THR_SUPPER 0x0c350180 +#define RX_THR_HIGH 0x7a120180 +#define RX_THR_SLOW 0xffff0180 +#define RX_THR_B 0x00010001 + +/* USB_TX_DMA */ +#define TEST_MODE_DISABLE 0x00000001 +#define TX_SIZE_ADJUST1 0x00000100 + +/* USB_BMU_RESET */ +#define BMU_RESET_EP_IN 0x01 +#define BMU_RESET_EP_OUT 0x02 + +/* USB_BMU_CONFIG */ +#define ACT_ODMA BIT(1) + +/* USB_UPT_RXDMA_OWN */ +#define OWN_UPDATE BIT(0) +#define OWN_CLEAR BIT(1) + +/* USB_FW_TASK */ +#define FC_PATCH_TASK BIT(1) + +/* USB_RX_AGGR_NUM */ +#define RX_AGGR_NUM_MASK 0x1ff + +/* USB_UPS_CTRL */ +#define POWER_CUT 0x0100 + +/* USB_PM_CTRL_STATUS */ +#define RESUME_INDICATE 0x0001 + +/* USB_ECM_OPTION */ +#define BYPASS_MAC_RESET BIT(5) + +/* USB_CSTMR */ +#define FORCE_SUPER BIT(0) + +/* USB_MISC_2 */ +#define UPS_FORCE_PWR_DOWN BIT(0) + +/* USB_ECM_OP */ +#define EN_ALL_SPEED BIT(0) + +/* USB_GPHY_CTRL */ +#define GPHY_PATCH_DONE BIT(2) +#define BYPASS_FLASH BIT(5) +#define BACKUP_RESTRORE BIT(6) + +/* USB_SPEED_OPTION */ +#define RG_PWRDN_EN BIT(8) +#define ALL_SPEED_OFF BIT(9) + +/* USB_FW_CTRL */ +#define FLOW_CTRL_PATCH_OPT BIT(1) +#define AUTO_SPEEDUP BIT(3) +#define FLOW_CTRL_PATCH_2 BIT(8) + +/* USB_FC_TIMER */ +#define CTRL_TIMER_EN BIT(15) + +/* USB_USB_CTRL */ +#define CDC_ECM_EN BIT(3) +#define RX_AGG_DISABLE 0x0010 +#define RX_ZERO_EN 0x0080 + +/* USB_U2P3_CTRL */ +#define U2P3_ENABLE 0x0001 +#define RX_DETECT8 BIT(3) + +/* USB_POWER_CUT */ +#define PWR_EN 0x0001 +#define PHASE2_EN 0x0008 +#define UPS_EN BIT(4) +#define USP_PREWAKE BIT(5) + +/* USB_MISC_0 */ +#define PCUT_STATUS 0x0001 + +/* USB_RX_EARLY_TIMEOUT */ +#define COALESCE_SUPER 85000U +#define COALESCE_HIGH 250000U +#define COALESCE_SLOW 524280U + +/* USB_WDT1_CTRL */ +#define WTD1_EN BIT(0) + +/* USB_WDT11_CTRL */ +#define TIMER11_EN 0x0001 + +/* USB_LPM_CTRL */ +/* bit 4 ~ 5: fifo empty boundary */ +#define FIFO_EMPTY_1FB 0x30 /* 0x1fb * 64 = 32448 bytes */ +/* bit 2 ~ 3: LMP timer */ +#define LPM_TIMER_MASK 0x0c +#define LPM_TIMER_500MS 0x04 /* 500 ms */ +#define LPM_TIMER_500US 0x0c /* 500 us */ +#define ROK_EXIT_LPM 0x02 + +/* USB_AFE_CTRL2 */ +#define SEN_VAL_MASK 0xf800 +#define SEN_VAL_NORMAL 0xa000 +#define SEL_RXIDLE 0x0100 + +/* USB_UPHY_XTAL */ +#define OOBS_POLLING BIT(8) + +/* USB_UPS_CFG */ +#define SAW_CNT_1MS_MASK 0x0fff +#define MID_REVERSE BIT(5) /* RTL8156A */ + +/* USB_UPS_FLAGS */ +#define UPS_FLAGS_R_TUNE BIT(0) +#define UPS_FLAGS_EN_10M_CKDIV BIT(1) +#define UPS_FLAGS_250M_CKDIV BIT(2) +#define UPS_FLAGS_EN_ALDPS BIT(3) +#define UPS_FLAGS_CTAP_SHORT_DIS BIT(4) +#define UPS_FLAGS_SPEED_MASK (0xf << 16) +#define ups_flags_speed(x) ((x) << 16) +#define UPS_FLAGS_EN_EEE BIT(20) +#define UPS_FLAGS_EN_500M_EEE BIT(21) +#define UPS_FLAGS_EN_EEE_CKDIV BIT(22) +#define UPS_FLAGS_EEE_PLLOFF_100 BIT(23) +#define UPS_FLAGS_EEE_PLLOFF_GIGA BIT(24) +#define UPS_FLAGS_EEE_CMOD_LV_EN BIT(25) +#define UPS_FLAGS_EN_GREEN BIT(26) +#define UPS_FLAGS_EN_FLOW_CTR BIT(27) + +enum spd_duplex { + NWAY_10M_HALF, + NWAY_10M_FULL, + NWAY_100M_HALF, + NWAY_100M_FULL, + NWAY_1000M_FULL, + FORCE_10M_HALF, + FORCE_10M_FULL, + FORCE_100M_HALF, + FORCE_100M_FULL, + FORCE_1000M_FULL, + NWAY_2500M_FULL, +}; + +/* OCP_ALDPS_CONFIG */ +#define ENPWRSAVE 0x8000 +#define ENPDNPS 0x0200 +#define LINKENA 0x0100 +#define DIS_SDSAVE 0x0010 + +/* OCP_PHY_STATUS */ +#define PHY_STAT_MASK 0x0007 +#define PHY_STAT_EXT_INIT 2 +#define PHY_STAT_LAN_ON 3 +#define PHY_STAT_PWRDN 5 + +/* OCP_INTR_EN */ +#define INTR_SPEED_FORCE BIT(3) + +/* OCP_NCTL_CFG */ +#define PGA_RETURN_EN BIT(1) + +/* OCP_POWER_CFG */ +#define EEE_CLKDIV_EN 0x8000 +#define EN_ALDPS 0x0004 +#define EN_10M_PLLOFF 0x0001 + +/* OCP_EEE_CONFIG1 */ +#define RG_TXLPI_MSK_HFDUP 0x8000 +#define RG_MATCLR_EN 0x4000 +#define EEE_10_CAP 0x2000 +#define EEE_NWAY_EN 0x1000 +#define TX_QUIET_EN 0x0200 +#define RX_QUIET_EN 0x0100 +#define sd_rise_time_mask 0x0070 +#define sd_rise_time(x) (MIN(x, 7) << 4) /* bit 4 ~ 6 */ +#define RG_RXLPI_MSK_HFDUP 0x0008 +#define SDFALLTIME 0x0007 /* bit 0 ~ 2 */ + +/* OCP_EEE_CONFIG2 */ +#define RG_LPIHYS_NUM 0x7000 /* bit 12 ~ 15 */ +#define RG_DACQUIET_EN 0x0400 +#define RG_LDVQUIET_EN 0x0200 +#define RG_CKRSEL 0x0020 +#define RG_EEEPRG_EN 0x0010 + +/* OCP_EEE_CONFIG3 */ +#define fast_snr_mask 0xff80 +#define fast_snr(x) (MIN(x, 0x1ff) << 7) /* bit 7 ~ 15 */ +#define RG_LFS_SEL 0x0060 /* bit 6 ~ 5 */ +#define MSK_PH 0x0006 /* bit 0 ~ 3 */ + +/* OCP_EEE_AR */ +/* bit[15:14] function */ +#define FUN_ADDR 0x0000 +#define FUN_DATA 0x4000 +/* bit[4:0] device addr */ + +/* OCP_EEE_CFG */ +#define CTAP_SHORT_EN 0x0040 +#define EEE10_EN 0x0010 + +/* OCP_DOWN_SPEED */ +#define EN_EEE_CMODE BIT(14) +#define EN_EEE_1000 BIT(13) +#define EN_EEE_100 BIT(12) +#define EN_10M_CLKDIV BIT(11) +#define EN_10M_BGOFF 0x0080 + +/* OCP_10GBT_CTRL */ +#define RTL_ADV2_5G_F_R BIT(5) /* Advertise 2.5GBASE-T fast-retrain */ + +/* OCP_PHY_STATE */ +#define TXDIS_STATE 0x01 +#define ABD_STATE 0x02 + +/* OCP_PHY_PATCH_STAT */ +#define PATCH_READY BIT(6) + +/* OCP_PHY_PATCH_CMD */ +#define PATCH_REQUEST BIT(4) + +/* OCP_PHY_LOCK */ +#define PATCH_LOCK BIT(0) + +/* OCP_ADC_CFG */ +#define CKADSEL_L 0x0100 +#define ADC_EN 0x0080 +#define EN_EMI_L 0x0040 + +/* OCP_SYSCLK_CFG */ +#define sysclk_div_expo(x) (MIN(x, 5) << 8) +#define clk_div_expo(x) (MIN(x, 5) << 4) + +/* SRAM_GREEN_CFG */ +#define GREEN_ETH_EN BIT(15) +#define R_TUNE_EN BIT(11) + +/* SRAM_LPF_CFG */ +#define LPF_AUTO_TUNE 0x8000 + +/* SRAM_10M_AMP1 */ +#define GDAC_IB_UPALL 0x0008 + +/* SRAM_10M_AMP2 */ +#define AMP_DN 0x0200 + +/* SRAM_IMPEDANCE */ +#define RX_DRIVING_MASK 0x6000 + +/* SRAM_PHY_LOCK */ +#define PHY_PATCH_LOCK 0x0001 + +/* MAC PASSTHRU */ +#define AD_MASK 0xfee0 +#define BND_MASK 0x0004 +#define BD_MASK 0x0001 +#define EFUSE 0xcfdb +#define PASS_THRU_MASK 0x1 + +#define BP4_SUPER_ONLY 0x1578 /* RTL_VER_04 only */ + +enum rtl_register_content { + _2500bps = BIT(10), + _1250bps = BIT(9), + _500bps = BIT(8), + _tx_flow = BIT(6), + _rx_flow = BIT(5), + _1000bps = 0x10, + _100bps = 0x08, + _10bps = 0x04, + LINK_STATUS = 0x02, + FULL_DUP = 0x01, +}; + +#define is_speed_2500(_speed) (((_speed) & (_2500bps | LINK_STATUS)) == (_2500bps | LINK_STATUS)) +#define is_flow_control(_speed) (((_speed) & (_tx_flow | _rx_flow)) == (_tx_flow | _rx_flow)) + +#define RTL8152_MAX_TX 4 +#define RTL8152_MAX_RX 10 +#define INTBUFSIZE 2 +#define TX_ALIGN 4 +#define RX_ALIGN 8 + +#define RTL8152_RX_MAX_PENDING 4096 +#define RTL8152_RXFG_HEADSZ 256 + +#define INTR_LINK 0x0004 + +#define VLAN_ETH_HLEN 18 +#define ETH_FCS_LEN 4 +#define VLAN_ETH_FRAME_LEN 1514 + +#define RTL8152_RMS (VLAN_ETH_FRAME_LEN + ETH_FCS_LEN) +#define RTL8153_RMS RTL8153_MAX_PACKET +#define mtu_to_size(m) ((m) + VLAN_ETH_HLEN + ETH_FCS_LEN) +#define size_to_mtu(s) ((s)-VLAN_ETH_HLEN - ETH_FCS_LEN) +#define rx_reserved_size(x) (mtu_to_size(x) + sizeof(struct rx_desc) + RX_ALIGN) + +struct rx_desc { + uint32_t opts1; +#define RD_CRC BIT(15) +#define RX_LEN_MASK 0x7fff + + uint32_t opts2; +#define RD_UDP_CS BIT(23) +#define RD_TCP_CS BIT(22) +#define RD_IPV6_CS BIT(20) +#define RD_IPV4_CS BIT(19) + + uint32_t opts3; +#define IPF BIT(23) /* IP checksum fail */ +#define UDPF BIT(22) /* UDP checksum fail */ +#define TCPF BIT(21) /* TCP checksum fail */ +#define RX_VLAN_TAG BIT(16) + + uint32_t opts4; + uint32_t opts5; + uint32_t opts6; +}; + +struct tx_desc { + uint32_t opts1; +#define TX_FS BIT(31) /* First segment of a packet */ +#define TX_LS BIT(30) /* Final segment of a packet */ +#define LGSEND BIT(29) +#define GTSENDV4 BIT(28) +#define GTSENDV6 BIT(27) +#define GTTCPHO_SHIFT 18 +#define GTTCPHO_MAX 0x7fU +#define TX_LEN_MAX 0x3ffffU + + uint32_t opts2; +#define UDP_CS BIT(31) /* Calculate UDP/IP checksum */ +#define TCP_CS BIT(30) /* Calculate TCP/IP checksum */ +#define IPV4_CS BIT(29) /* Calculate IPv4 checksum */ +#define IPV6_CS BIT(28) /* Calculate IPv6 checksum */ +#define MSS_SHIFT 17 +#define MSS_MAX 0x7ffU +#define TCPHO_SHIFT 17 +#define TCPHO_MAX 0x7ffU +#define TX_VLAN_TAG BIT(16) +}; + +enum rtl_version { + RTL_VER_UNKNOWN = 0, + RTL_VER_01, + RTL_VER_02, + RTL_VER_03, + RTL_VER_04, + RTL_VER_05, + RTL_VER_06, + RTL_VER_07, + RTL_VER_08, + RTL_VER_09, + + RTL_TEST_01, + RTL_VER_10, + RTL_VER_11, + RTL_VER_12, + RTL_VER_13, + RTL_VER_14, + RTL_VER_15, + + RTL_VER_MAX +}; + +/* mii.h */ +/* Generic MII registers. */ +#define MII_BMCR 0x00 /* Basic mode control register */ +#define MII_BMSR 0x01 /* Basic mode status register */ +#define MII_PHYSID1 0x02 /* PHYS ID 1 */ +#define MII_PHYSID2 0x03 /* PHYS ID 2 */ +#define MII_ADVERTISE 0x04 /* Advertisement control reg */ +#define MII_LPA 0x05 /* Link partner ability reg */ +#define MII_EXPANSION 0x06 /* Expansion register */ +#define MII_CTRL1000 0x09 /* 1000BASE-T control */ +#define MII_STAT1000 0x0a /* 1000BASE-T status */ +#define MII_MMD_CTRL 0x0d /* MMD Access Control Register */ +#define MII_MMD_DATA 0x0e /* MMD Access Data Register */ +#define MII_ESTATUS 0x0f /* Extended Status */ +#define MII_DCOUNTER 0x12 /* Disconnect counter */ +#define MII_FCSCOUNTER 0x13 /* False carrier counter */ +#define MII_NWAYTEST 0x14 /* N-way auto-neg test reg */ +#define MII_RERRCOUNTER 0x15 /* Receive error counter */ +#define MII_SREVISION 0x16 /* Silicon revision */ +#define MII_RESV1 0x17 /* Reserved... */ +#define MII_LBRERROR 0x18 /* Lpback, rx, bypass error */ +#define MII_PHYADDR 0x19 /* PHY address */ +#define MII_RESV2 0x1a /* Reserved... */ +#define MII_TPISTATUS 0x1b /* TPI status for 10mbps */ +#define MII_NCONFIG 0x1c /* Network interface config */ + +/* Basic mode control register. */ +#define BMCR_RESV 0x003f /* Unused... */ +#define BMCR_SPEED1000 0x0040 /* MSB of Speed (1000) */ +#define BMCR_CTST 0x0080 /* Collision test */ +#define BMCR_FULLDPLX 0x0100 /* Full duplex */ +#define BMCR_ANRESTART 0x0200 /* Auto negotiation restart */ +#define BMCR_ISOLATE 0x0400 /* Isolate data paths from MII */ +#define BMCR_PDOWN 0x0800 /* Enable low power state */ +#define BMCR_ANENABLE 0x1000 /* Enable auto negotiation */ +#define BMCR_SPEED100 0x2000 /* Select 100Mbps */ +#define BMCR_LOOPBACK 0x4000 /* TXD loopback bits */ +#define BMCR_RESET 0x8000 /* Reset to default state */ +#define BMCR_SPEED10 0x0000 /* Select 10Mbps */ + +/* Basic mode status register. */ +#define BMSR_ERCAP 0x0001 /* Ext-reg capability */ +#define BMSR_JCD 0x0002 /* Jabber detected */ +#define BMSR_LSTATUS 0x0004 /* Link status */ +#define BMSR_ANEGCAPABLE 0x0008 /* Able to do auto-negotiation */ +#define BMSR_RFAULT 0x0010 /* Remote fault detected */ +#define BMSR_ANEGCOMPLETE 0x0020 /* Auto-negotiation complete */ +#define BMSR_RESV 0x00c0 /* Unused... */ +#define BMSR_ESTATEN 0x0100 /* Extended Status in R15 */ +#define BMSR_100HALF2 0x0200 /* Can do 100BASE-T2 HDX */ +#define BMSR_100FULL2 0x0400 /* Can do 100BASE-T2 FDX */ +#define BMSR_10HALF 0x0800 /* Can do 10mbps, half-duplex */ +#define BMSR_10FULL 0x1000 /* Can do 10mbps, full-duplex */ +#define BMSR_100HALF 0x2000 /* Can do 100mbps, half-duplex */ +#define BMSR_100FULL 0x4000 /* Can do 100mbps, full-duplex */ +#define BMSR_100BASE4 0x8000 /* Can do 100mbps, 4k packets */ + +/* Advertisement control register. */ +#define ADVERTISE_SLCT 0x001f /* Selector bits */ +#define ADVERTISE_CSMA 0x0001 /* Only selector supported */ +#define ADVERTISE_10HALF 0x0020 /* Try for 10mbps half-duplex */ +#define ADVERTISE_1000XFULL 0x0020 /* Try for 1000BASE-X full-duplex */ +#define ADVERTISE_10FULL 0x0040 /* Try for 10mbps full-duplex */ +#define ADVERTISE_1000XHALF 0x0040 /* Try for 1000BASE-X half-duplex */ +#define ADVERTISE_100HALF 0x0080 /* Try for 100mbps half-duplex */ +#define ADVERTISE_1000XPAUSE 0x0080 /* Try for 1000BASE-X pause */ +#define ADVERTISE_100FULL 0x0100 /* Try for 100mbps full-duplex */ +#define ADVERTISE_1000XPSE_ASYM 0x0100 /* Try for 1000BASE-X asym pause */ +#define ADVERTISE_100BASE4 0x0200 /* Try for 100mbps 4k packets */ +#define ADVERTISE_PAUSE_CAP 0x0400 /* Try for pause */ +#define ADVERTISE_PAUSE_ASYM 0x0800 /* Try for asymetric pause */ +#define ADVERTISE_RESV 0x1000 /* Unused... */ +#define ADVERTISE_RFAULT 0x2000 /* Say we can detect faults */ +#define ADVERTISE_LPACK 0x4000 /* Ack link partners response */ +#define ADVERTISE_NPAGE 0x8000 /* Next page bit */ + +#define ADVERTISE_FULL (ADVERTISE_100FULL | ADVERTISE_10FULL | \ + ADVERTISE_CSMA) +#define ADVERTISE_ALL (ADVERTISE_10HALF | ADVERTISE_10FULL | \ + ADVERTISE_100HALF | ADVERTISE_100FULL) + +/* 1000BASE-T Control register */ +#define ADVERTISE_1000FULL 0x0200 /* Advertise 1000BASE-T full duplex */ +#define ADVERTISE_1000HALF 0x0100 /* Advertise 1000BASE-T half duplex */ +#define CTL1000_AS_MASTER 0x0800 +#define CTL1000_ENABLE_MASTER 0x1000 + +/* ethtool.h */ +/* The forced speed, 10Mb, 100Mb, gigabit. */ +#define SPEED_10 10 +#define SPEED_100 100 +#define SPEED_1000 1000 + +#define SPEED_UNKNOWN -1 + +/* Duplex, half or full. */ +#define DUPLEX_HALF 0x00 +#define DUPLEX_FULL 0x01 +#define DUPLEX_UNKNOWN 0xff + +/* Enable or disable autonegotiation. */ +#define AUTONEG_DISABLE 0x00 +#define AUTONEG_ENABLE 0x01 + +static int usbh_rtl8152_read_regs(struct usbh_rtl8152 *rtl8152_class, + uint16_t value, + uint16_t index, + uint16_t size, + void *data) +{ + struct usb_setup_packet *setup; + int ret; + + if (!rtl8152_class || !rtl8152_class->hport) { + return -USB_ERR_INVAL; + } + setup = rtl8152_class->hport->setup; + + setup->bmRequestType = USB_REQUEST_DIR_IN | USB_REQUEST_VENDOR | USB_REQUEST_RECIPIENT_DEVICE; + setup->bRequest = RTL8152_REQ_GET_REGS; + setup->wValue = value; + setup->wIndex = index; + setup->wLength = size; + + ret = usbh_control_transfer(rtl8152_class->hport, setup, g_rtl8152_buf); + if (ret < 8) { + return ret; + } + memcpy(data, g_rtl8152_buf, MIN(ret - 8, size)); + + return ret; +} + +static int usbh_rtl8152_write_regs(struct usbh_rtl8152 *rtl8152_class, + uint16_t value, + uint16_t index, + uint16_t size, + void *data) +{ + struct usb_setup_packet *setup; + + if (!rtl8152_class || !rtl8152_class->hport) { + return -USB_ERR_INVAL; + } + setup = rtl8152_class->hport->setup; + + setup->bmRequestType = USB_REQUEST_DIR_OUT | USB_REQUEST_VENDOR | USB_REQUEST_RECIPIENT_DEVICE; + setup->bRequest = RTL8152_REQ_SET_REGS; + setup->wValue = value; + setup->wIndex = index; + setup->wLength = size; + + memcpy(g_rtl8152_buf, data, size); + return usbh_control_transfer(rtl8152_class->hport, setup, g_rtl8152_buf); +} + +static int generic_ocp_read(struct usbh_rtl8152 *tp, uint16_t index, uint16_t size, + void *data, uint16_t type) +{ + uint16_t limit = 64; + int ret = 0; + uint8_t *buf = data; + + /* both size and indix must be 4 bytes align */ + if ((size & 3) || !size || (index & 3) || !buf) + return -USB_ERR_INVAL; + + if ((uint32_t)index + (uint32_t)size > 0xffff) + return -USB_ERR_INVAL; + + while (size) { + if (size > limit) { + ret = usbh_rtl8152_read_regs(tp, index, type, limit, buf); + if (ret < 0) + break; + + index += limit; + buf += limit; + size -= limit; + } else { + ret = usbh_rtl8152_read_regs(tp, index, type, size, buf); + if (ret < 0) + break; + + index += size; + buf += size; + size = 0; + break; + } + } + + return ret; +} + +static int generic_ocp_write(struct usbh_rtl8152 *tp, uint16_t index, uint16_t byteen, + uint16_t size, void *data, uint16_t type) +{ + int ret = -USB_ERR_INVAL; + uint16_t byteen_start, byteen_end, byen; + uint16_t limit = 512; + uint8_t *buf = data; + + /* both size and indix must be 4 bytes align */ + if ((size & 3) || !size || (index & 3) || !buf) + return ret; + + if ((uint32_t)index + (uint32_t)size > 0xffff) + return ret; + + byteen_start = byteen & BYTE_EN_START_MASK; + byteen_end = byteen & BYTE_EN_END_MASK; + + byen = byteen_start | (byteen_start << 4); + + /* Split the first DWORD if the byte_en is not 0xff */ + if (byen != BYTE_EN_DWORD) { + ret = usbh_rtl8152_write_regs(tp, index, type | byen, 4, buf); + if (ret < 0) + goto error1; + + index += 4; + buf += 4; + size -= 4; + } + + if (size) { + byen = byteen_end | (byteen_end >> 4); + + /* Split the last DWORD if the byte_en is not 0xff */ + if (byen != BYTE_EN_DWORD) + size -= 4; + + while (size) { + if (size > limit) { + ret = usbh_rtl8152_write_regs(tp, index, + type | BYTE_EN_DWORD, + limit, buf); + if (ret < 0) + goto error1; + + index += limit; + buf += limit; + size -= limit; + } else { + ret = usbh_rtl8152_write_regs(tp, index, + type | BYTE_EN_DWORD, + size, buf); + if (ret < 0) + goto error1; + + index += size; + buf += size; + size = 0; + break; + } + } + + /* Set the last DWORD */ + if (byen != BYTE_EN_DWORD) + ret = usbh_rtl8152_write_regs(tp, index, type | byen, 4, buf); + } + +error1: + + return ret; +} + +static inline int pla_ocp_read(struct usbh_rtl8152 *tp, uint16_t index, uint16_t size, void *data) +{ + return generic_ocp_read(tp, index, size, data, MCU_TYPE_PLA); +} + +static inline int pla_ocp_write(struct usbh_rtl8152 *tp, uint16_t index, uint16_t byteen, uint16_t size, void *data) +{ + return generic_ocp_write(tp, index, byteen, size, data, MCU_TYPE_PLA); +} + +static inline int usb_ocp_write(struct usbh_rtl8152 *tp, uint16_t index, uint16_t byteen, uint16_t size, void *data) +{ + return generic_ocp_write(tp, index, byteen, size, data, MCU_TYPE_USB); +} + +static uint32_t ocp_read_dword(struct usbh_rtl8152 *tp, uint16_t type, uint16_t index) +{ + uint32_t data = 0; + + generic_ocp_read(tp, index, sizeof(data), &data, type); + + return data; +} + +static void ocp_write_dword(struct usbh_rtl8152 *tp, uint16_t type, uint16_t index, uint32_t data) +{ + uint32_t tmp = data; + + generic_ocp_write(tp, index, BYTE_EN_DWORD, sizeof(tmp), &tmp, type); +} + +static uint16_t ocp_read_word(struct usbh_rtl8152 *tp, uint16_t type, uint16_t index) +{ + uint32_t data; + uint32_t tmp = 0; + uint16_t byen = BYTE_EN_WORD; + uint8_t shift = index & 2; + + index &= ~3; + byen <<= shift; + + generic_ocp_read(tp, index, sizeof(tmp), &tmp, type | byen); + + data = tmp; + data >>= (shift * 8); + data &= 0xffff; + + return (uint16_t)data; +} + +static void ocp_write_word(struct usbh_rtl8152 *tp, uint16_t type, uint16_t index, uint32_t data) +{ + uint32_t mask = 0xffff; + uint32_t tmp; + uint16_t byen = BYTE_EN_WORD; + uint8_t shift = index & 2; + + data &= mask; + + if (index & 2) { + byen <<= shift; + mask <<= (shift * 8); + data <<= (shift * 8); + index &= ~3; + } + + tmp = data; + + generic_ocp_write(tp, index, byen, sizeof(tmp), &tmp, type); +} + +static uint8_t ocp_read_byte(struct usbh_rtl8152 *tp, uint16_t type, uint16_t index) +{ + uint32_t data; + uint32_t tmp = 0; + uint8_t shift = index & 3; + + index &= ~3; + + generic_ocp_read(tp, index, sizeof(tmp), &tmp, type); + + data = tmp; + data >>= (shift * 8); + data &= 0xff; + + return (uint8_t)data; +} + +static void ocp_write_byte(struct usbh_rtl8152 *tp, uint16_t type, uint16_t index, uint32_t data) +{ + uint32_t mask = 0xff; + uint32_t tmp; + uint16_t byen = BYTE_EN_BYTE; + uint8_t shift = index & 3; + + data &= mask; + + if (index & 3) { + byen <<= shift; + mask <<= (shift * 8); + data <<= (shift * 8); + index &= ~3; + } + + tmp = data; + + generic_ocp_write(tp, index, byen, sizeof(tmp), &tmp, type); +} + +static uint16_t ocp_reg_read(struct usbh_rtl8152 *tp, uint16_t addr) +{ + uint16_t ocp_base, ocp_index; + + ocp_base = addr & 0xf000; + if (ocp_base != tp->ocp_base) { + ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, ocp_base); + tp->ocp_base = ocp_base; + } + + ocp_index = (addr & 0x0fff) | 0xb000; + return ocp_read_word(tp, MCU_TYPE_PLA, ocp_index); +} + +static void ocp_reg_write(struct usbh_rtl8152 *tp, uint16_t addr, uint16_t data) +{ + uint16_t ocp_base, ocp_index; + + ocp_base = addr & 0xf000; + if (ocp_base != tp->ocp_base) { + ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, ocp_base); + tp->ocp_base = ocp_base; + } + + ocp_index = (addr & 0x0fff) | 0xb000; + ocp_write_word(tp, MCU_TYPE_PLA, ocp_index, data); +} + +static inline void r8152_mdio_write(struct usbh_rtl8152 *tp, uint32_t reg_addr, uint32_t value) +{ + ocp_reg_write(tp, OCP_BASE_MII + reg_addr * 2, value); +} + +static inline int r8152_mdio_read(struct usbh_rtl8152 *tp, uint32_t reg_addr) +{ + return ocp_reg_read(tp, OCP_BASE_MII + reg_addr * 2); +} + +static uint8_t usbh_rtl8152_get_version(struct usbh_rtl8152 *rtl8152_class) +{ + uint8_t version; + uint32_t temp = 0; + uint32_t ocp_data; + + usbh_rtl8152_read_regs(rtl8152_class, PLA_TCR0, MCU_TYPE_PLA, 4, &temp); + + ocp_data = (temp >> 16) & VERSION_MASK; + switch (ocp_data) { + case 0x4c00: + version = RTL_VER_01; + break; + case 0x4c10: + version = RTL_VER_02; + break; + case 0x5c00: + version = RTL_VER_03; + break; + case 0x5c10: + version = RTL_VER_04; + break; + case 0x5c20: + version = RTL_VER_05; + break; + case 0x5c30: + version = RTL_VER_06; + break; + case 0x4800: + version = RTL_VER_07; + break; + case 0x6000: + version = RTL_VER_08; + break; + case 0x6010: + version = RTL_VER_09; + break; + case 0x7010: + version = RTL_TEST_01; + break; + case 0x7020: + version = RTL_VER_10; + break; + case 0x7030: + version = RTL_VER_11; + break; + case 0x7400: + version = RTL_VER_12; + break; + case 0x7410: + version = RTL_VER_13; + break; + case 0x6400: + version = RTL_VER_14; + break; + case 0x7420: + version = RTL_VER_15; + break; + default: + version = RTL_VER_UNKNOWN; + break; + } + + return version; +} + +#define WAKE_PHY (1 << 0) +#define WAKE_UCAST (1 << 1) +#define WAKE_MCAST (1 << 2) +#define WAKE_BCAST (1 << 3) +#define WAKE_ARP (1 << 4) +#define WAKE_MAGIC (1 << 5) +#define WAKE_MAGICSECURE (1 << 6) /* only meaningful if WAKE_MAGIC */ +#define WAKE_FILTER (1 << 7) + +#define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST) + +static uint32_t __rtl_get_wol(struct usbh_rtl8152 *tp) +{ + uint32_t ocp_data; + uint32_t wolopts = 0; + + ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34); + if (ocp_data & LINK_ON_WAKE_EN) + wolopts |= WAKE_PHY; + + ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG5); + if (ocp_data & UWF_EN) + wolopts |= WAKE_UCAST; + if (ocp_data & BWF_EN) + wolopts |= WAKE_BCAST; + if (ocp_data & MWF_EN) + wolopts |= WAKE_MCAST; + + ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL); + if (ocp_data & MAGIC_EN) + wolopts |= WAKE_MAGIC; + + return wolopts; +} + +static void r8152_aldps_en(struct usbh_rtl8152 *tp, bool enable) +{ + if (enable) { + ocp_reg_write(tp, OCP_ALDPS_CONFIG, ENPWRSAVE | ENPDNPS | LINKENA | DIS_SDSAVE); + } else { + ocp_reg_write(tp, OCP_ALDPS_CONFIG, ENPDNPS | LINKENA | DIS_SDSAVE); + usb_osal_msleep(20); + } +} + +static void r8152_power_cut_en(struct usbh_rtl8152 *tp, bool enable) +{ + uint32_t ocp_data; + + ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_UPS_CTRL); + if (enable) + ocp_data |= POWER_CUT; + else + ocp_data &= ~POWER_CUT; + ocp_write_word(tp, MCU_TYPE_USB, USB_UPS_CTRL, ocp_data); + + ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_PM_CTRL_STATUS); + ocp_data &= ~RESUME_INDICATE; + ocp_write_word(tp, MCU_TYPE_USB, USB_PM_CTRL_STATUS, ocp_data); +} + +static void rtl_tally_reset(struct usbh_rtl8152 *tp) +{ + uint32_t ocp_data; + + ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_RSTTALLY); + ocp_data |= TALLY_RESET; + ocp_write_word(tp, MCU_TYPE_PLA, PLA_RSTTALLY, ocp_data); +} + +static void r8152b_reset_packet_filter(struct usbh_rtl8152 *tp) +{ + uint32_t ocp_data; + + ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_FMC); + ocp_data &= ~FMC_FCR_MCU_EN; + ocp_write_word(tp, MCU_TYPE_PLA, PLA_FMC, ocp_data); + ocp_data |= FMC_FCR_MCU_EN; + ocp_write_word(tp, MCU_TYPE_PLA, PLA_FMC, ocp_data); +} + +static inline void r8153b_rx_agg_chg_indicate(struct usbh_rtl8152 *tp) +{ + ocp_write_byte(tp, MCU_TYPE_USB, USB_UPT_RXDMA_OWN, + OWN_UPDATE | OWN_CLEAR); +} + +static void rxdy_gated_en(struct usbh_rtl8152 *tp, bool enable) +{ + uint32_t ocp_data; + + ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MISC_1); + if (enable) + ocp_data |= RXDY_GATED_EN; + else + ocp_data &= ~RXDY_GATED_EN; + ocp_write_word(tp, MCU_TYPE_PLA, PLA_MISC_1, ocp_data); +} + +static inline uint16_t rtl8152_get_speed(struct usbh_rtl8152 *tp) +{ + return ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHYSTATUS); +} + +static void rtl_eee_plus_en(struct usbh_rtl8152 *tp, bool enable) +{ + uint32_t ocp_data; + + ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR); + if (enable) + ocp_data |= EEEP_CR_EEEP_TX; + else + ocp_data &= ~EEEP_CR_EEEP_TX; + ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR, ocp_data); +} + +static void rtl_set_eee_plus(struct usbh_rtl8152 *tp) +{ + if (rtl8152_get_speed(tp) & _10bps) + rtl_eee_plus_en(tp, true); + else + rtl_eee_plus_en(tp, false); +} + +static void rtl8152_nic_reset(struct usbh_rtl8152 *tp) +{ + uint32_t ocp_data; + int i; + + switch (tp->version) { + case RTL_TEST_01: + case RTL_VER_10: + case RTL_VER_11: + ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CR); + ocp_data &= ~CR_TE; + ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, ocp_data); + + ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_BMU_RESET); + ocp_data &= ~BMU_RESET_EP_IN; + ocp_write_word(tp, MCU_TYPE_USB, USB_BMU_RESET, ocp_data); + + ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL); + ocp_data |= CDC_ECM_EN; + ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data); + + ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CR); + ocp_data &= ~CR_RE; + ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, ocp_data); + + ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_BMU_RESET); + ocp_data |= BMU_RESET_EP_IN; + ocp_write_word(tp, MCU_TYPE_USB, USB_BMU_RESET, ocp_data); + + ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL); + ocp_data &= ~CDC_ECM_EN; + ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data); + break; + + default: + ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, CR_RST); + + for (i = 0; i < 1000; i++) { + if (!(ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CR) & CR_RST)) + break; + usb_osal_msleep(400); + } + break; + } +} + +static void rtl_disable(struct usbh_rtl8152 *tp) +{ + uint32_t ocp_data; + int i; + + ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR); + ocp_data &= ~RCR_ACPT_ALL; + ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data); + + rxdy_gated_en(tp, true); + + for (i = 0; i < 1000; i++) { + ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); + if ((ocp_data & FIFO_EMPTY) == FIFO_EMPTY) + break; + usb_osal_msleep(1); + } + + for (i = 0; i < 1000; i++) { + if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0) & TCR0_TX_EMPTY) + break; + usb_osal_msleep(1); + } + + rtl8152_nic_reset(tp); +} + +static void rtl_rx_vlan_en(struct usbh_rtl8152 *tp, bool enable) +{ + uint32_t ocp_data; + + switch (tp->version) { + case RTL_VER_01: + case RTL_VER_02: + case RTL_VER_03: + case RTL_VER_04: + case RTL_VER_05: + case RTL_VER_06: + case RTL_VER_07: + case RTL_VER_08: + case RTL_VER_09: + case RTL_VER_14: + ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CPCR); + if (enable) + ocp_data |= CPCR_RX_VLAN; + else + ocp_data &= ~CPCR_RX_VLAN; + ocp_write_word(tp, MCU_TYPE_PLA, PLA_CPCR, ocp_data); + break; + + case RTL_TEST_01: + case RTL_VER_10: + case RTL_VER_11: + case RTL_VER_12: + case RTL_VER_13: + case RTL_VER_15: + default: + ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_RCR1); + if (enable) + ocp_data |= OUTER_VLAN | INNER_VLAN; + else + ocp_data &= ~(OUTER_VLAN | INNER_VLAN); + ocp_write_word(tp, MCU_TYPE_PLA, PLA_RCR1, ocp_data); + break; + } +} + +static void wait_oob_link_list_ready(struct usbh_rtl8152 *tp) +{ + uint32_t ocp_data; + int i; + + for (i = 0; i < 1000; i++) { + ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); + if (ocp_data & LINK_LIST_READY) + break; + usb_osal_msleep(1); + } +} + +static void r8153_teredo_off(struct usbh_rtl8152 *tp) +{ + uint32_t ocp_data; + + switch (tp->version) { + case RTL_VER_01: + case RTL_VER_02: + case RTL_VER_03: + case RTL_VER_04: + case RTL_VER_05: + case RTL_VER_06: + case RTL_VER_07: + ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG); + ocp_data &= ~(TEREDO_SEL | TEREDO_RS_EVENT_MASK | + OOB_TEREDO_EN); + ocp_write_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG, ocp_data); + break; + + case RTL_VER_08: + case RTL_VER_09: + case RTL_TEST_01: + case RTL_VER_10: + case RTL_VER_11: + case RTL_VER_12: + case RTL_VER_13: + case RTL_VER_14: + case RTL_VER_15: + default: + /* The bit 0 ~ 7 are relative with teredo settings. They are + * W1C (write 1 to clear), so set all 1 to disable it. + */ + ocp_write_byte(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG, 0xff); + break; + } + + ocp_write_word(tp, MCU_TYPE_PLA, PLA_WDT6_CTRL, WDT6_SET_MODE); + ocp_write_word(tp, MCU_TYPE_PLA, PLA_REALWOW_TIMER, 0); + ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TEREDO_TIMER, 0); +} + +static void r8152b_exit_oob(struct usbh_rtl8152 *tp) +{ + uint32_t ocp_data; + + ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR); + ocp_data &= ~RCR_ACPT_ALL; + ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data); + + rxdy_gated_en(tp, true); + r8153_teredo_off(tp); + ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML); + ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, 0x00); + + ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); + ocp_data &= ~NOW_IS_OOB; + ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data); + + ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7); + ocp_data &= ~MCU_BORW_EN; + ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data); + + wait_oob_link_list_ready(tp); + + ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7); + ocp_data |= RE_INIT_LL; + ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data); + + wait_oob_link_list_ready(tp); + + rtl8152_nic_reset(tp); + + /* rx share fifo credit full threshold */ + ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_NORMAL); + + if (tp->hport->speed == USB_SPEED_FULL || + tp->hport->speed == USB_SPEED_LOW) { + /* rx share fifo credit near full threshold */ + ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, + RXFIFO_THR2_FULL); + ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, + RXFIFO_THR3_FULL); + } else { + /* rx share fifo credit near full threshold */ + ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, + RXFIFO_THR2_HIGH); + ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, + RXFIFO_THR3_HIGH); + } + + /* TX share fifo free credit full threshold */ + ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TXFIFO_CTRL, TXFIFO_THR_NORMAL2); + + ocp_write_byte(tp, MCU_TYPE_USB, USB_TX_AGG, TX_AGG_MAX_THRESHOLD); + ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_BUF_TH, RX_THR_HIGH); + ocp_write_dword(tp, MCU_TYPE_USB, USB_TX_DMA, + TEST_MODE_DISABLE | TX_SIZE_ADJUST1); + + rtl_rx_vlan_en(tp, true); + + ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8152_RMS); + + ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0); + ocp_data |= TCR0_AUTO_FIFO; + ocp_write_word(tp, MCU_TYPE_PLA, PLA_TCR0, ocp_data); +} + +static void r8152b_enter_oob(struct usbh_rtl8152 *tp) +{ + uint32_t ocp_data; + + ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); + ocp_data &= ~NOW_IS_OOB; + ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data); + + ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_OOB); + ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, RXFIFO_THR2_OOB); + ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, RXFIFO_THR3_OOB); + + rtl_disable(tp); + + wait_oob_link_list_ready(tp); + + ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7); + ocp_data |= RE_INIT_LL; + ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data); + + wait_oob_link_list_ready(tp); + + ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8152_RMS); + + rtl_rx_vlan_en(tp, true); + + ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_BDC_CR); + ocp_data |= ALDPS_PROXY_MODE; + ocp_write_word(tp, MCU_TYPE_PLA, PLA_BDC_CR, ocp_data); + + ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); + ocp_data |= NOW_IS_OOB | DIS_MCU_CLROOB; + ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data); + + rxdy_gated_en(tp, false); + + ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR); + ocp_data |= RCR_APM | RCR_AM | RCR_AB; + ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data); +} + +static void r8152b_init(struct usbh_rtl8152 *tp) +{ + uint32_t ocp_data; + uint16_t data; + + data = r8152_mdio_read(tp, MII_BMCR); + if (data & BMCR_PDOWN) { + data &= ~BMCR_PDOWN; + r8152_mdio_write(tp, MII_BMCR, data); + } + + r8152_aldps_en(tp, false); + + if (tp->version == RTL_VER_01) { + ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE); + ocp_data &= ~LED_MODE_MASK; + ocp_write_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE, ocp_data); + } + + r8152_power_cut_en(tp, false); + + ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR); + ocp_data |= TX_10M_IDLE_EN | PFM_PWM_SWITCH; + ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data); + ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL); + ocp_data &= ~MCU_CLK_RATIO_MASK; + ocp_data |= MCU_CLK_RATIO | D3_CLK_GATED_EN; + ocp_write_dword(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL, ocp_data); + ocp_data = GPHY_STS_MSK | SPEED_DOWN_MSK | + SPDWN_RXDV_MSK | SPDWN_LINKCHG_MSK; + ocp_write_word(tp, MCU_TYPE_PLA, PLA_GPHY_INTR_IMR, ocp_data); + + rtl_tally_reset(tp); + + /* enable rx aggregation */ + ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL); + ocp_data &= ~(RX_AGG_DISABLE | RX_ZERO_EN); + ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data); +} + +static int rtl_enable(struct usbh_rtl8152 *tp) +{ + uint32_t ocp_data; + + r8152b_reset_packet_filter(tp); + + ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CR); + ocp_data |= CR_RE | CR_TE; + ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, ocp_data); + + switch (tp->version) { + case RTL_VER_01: + case RTL_VER_02: + case RTL_VER_03: + case RTL_VER_04: + case RTL_VER_05: + case RTL_VER_06: + case RTL_VER_07: + break; + default: + r8153b_rx_agg_chg_indicate(tp); + break; + } + + rxdy_gated_en(tp, false); + + return 0; +} + +static int rtl8152_enable(struct usbh_rtl8152 *tp) +{ + rtl_set_eee_plus(tp); + + return rtl_enable(tp); +} + +static void rtl8152_disable(struct usbh_rtl8152 *tp) +{ + r8152_aldps_en(tp, false); + rtl_disable(tp); + r8152_aldps_en(tp, true); +} + +static void rtl8152_up(struct usbh_rtl8152 *tp) +{ + r8152_aldps_en(tp, false); + r8152b_exit_oob(tp); + r8152_aldps_en(tp, true); +} + +static void rtl8152_down(struct usbh_rtl8152 *tp) +{ + r8152_power_cut_en(tp, false); + r8152_aldps_en(tp, false); + r8152b_enter_oob(tp); + r8152_aldps_en(tp, true); +} + +static int rtl_ops_init(struct usbh_rtl8152 *tp) +{ + struct rtl_ops *ops = &tp->rtl_ops; + int ret = 0; + + switch (tp->version) { + case RTL_VER_01: + case RTL_VER_02: + case RTL_VER_07: + ops->init = r8152b_init; + ops->enable = rtl8152_enable; + ops->disable = rtl8152_disable; + ops->up = rtl8152_up; + ops->down = rtl8152_down; + // ops->unload = rtl8152_unload; + // ops->eee_get = r8152_get_eee; + // ops->eee_set = r8152_set_eee; + // ops->in_nway = rtl8152_in_nway; + // ops->hw_phy_cfg = r8152b_hw_phy_cfg; + // ops->autosuspend_en = rtl_runtime_suspend_enable; + tp->rx_buf_sz = 16 * 1024; + tp->eee_en = true; + //tp->eee_adv = MDIO_EEE_100TX; + break; + + // case RTL_VER_03: + // case RTL_VER_04: + // case RTL_VER_05: + // case RTL_VER_06: + // break; + + // case RTL_VER_08: + // case RTL_VER_09: + // break; + + // case RTL_VER_11: + // case RTL_VER_10: + // break; + + // case RTL_VER_12: + // case RTL_VER_13: + // case RTL_VER_15: + // break; + + // case RTL_VER_14: + // break; + + default: + ret = -USB_ERR_NODEV; + USB_LOG_ERR("Unsupport rtl version:%d\r\n", tp->version); + break; + } + + return ret; +} + +static void rtl8152_set_rx_mode(struct usbh_rtl8152 *tp) +{ + uint32_t ocp_data; + uint32_t mc_filter[2]; + + ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR); + ocp_data &= ~RCR_ACPT_ALL; + ocp_data |= RCR_AB | RCR_APM; + + ocp_data |= RCR_AM; + mc_filter[1] = 0xffffffff; + mc_filter[0] = 0xffffffff; + + pla_ocp_write(tp, PLA_MAR, BYTE_EN_DWORD, sizeof(mc_filter), mc_filter); + ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data); +} + +static int rtl8152_set_speed(struct usbh_rtl8152 *tp, uint8_t autoneg, uint16_t speed, uint8_t duplex) +{ + uint16_t bmcr, anar, gbcr; + + anar = r8152_mdio_read(tp, MII_ADVERTISE); + anar &= ~(ADVERTISE_10HALF | ADVERTISE_10FULL | + ADVERTISE_100HALF | ADVERTISE_100FULL); + if (tp->supports_gmii) { + gbcr = r8152_mdio_read(tp, MII_CTRL1000); + gbcr &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF); + } else { + gbcr = 0; + } + + if (autoneg == AUTONEG_DISABLE) { + if (speed == SPEED_10) { + bmcr = 0; + anar |= ADVERTISE_10HALF | ADVERTISE_10FULL; + } else if (speed == SPEED_100) { + bmcr = BMCR_SPEED100; + anar |= ADVERTISE_100HALF | ADVERTISE_100FULL; + } else if (speed == SPEED_1000 && tp->supports_gmii) { + bmcr = BMCR_SPEED1000; + gbcr |= ADVERTISE_1000FULL | ADVERTISE_1000HALF; + } else { + return -USB_ERR_INVAL; + } + + if (duplex == DUPLEX_FULL) + bmcr |= BMCR_FULLDPLX; + } else { + if (speed == SPEED_10) { + if (duplex == DUPLEX_FULL) + anar |= ADVERTISE_10HALF | ADVERTISE_10FULL; + else + anar |= ADVERTISE_10HALF; + } else if (speed == SPEED_100) { + if (duplex == DUPLEX_FULL) { + anar |= ADVERTISE_10HALF | ADVERTISE_10FULL; + anar |= ADVERTISE_100HALF | ADVERTISE_100FULL; + } else { + anar |= ADVERTISE_10HALF; + anar |= ADVERTISE_100HALF; + } + } else if (speed == SPEED_1000 && tp->supports_gmii) { + if (duplex == DUPLEX_FULL) { + anar |= ADVERTISE_10HALF | ADVERTISE_10FULL; + anar |= ADVERTISE_100HALF | ADVERTISE_100FULL; + gbcr |= ADVERTISE_1000FULL | ADVERTISE_1000HALF; + } else { + anar |= ADVERTISE_10HALF; + anar |= ADVERTISE_100HALF; + gbcr |= ADVERTISE_1000HALF; + } + } else { + return -USB_ERR_INVAL; + } + + bmcr = BMCR_ANENABLE | BMCR_ANRESTART | BMCR_RESET; + } + + if (tp->supports_gmii) + r8152_mdio_write(tp, MII_CTRL1000, gbcr); + + r8152_mdio_write(tp, MII_ADVERTISE, anar); + r8152_mdio_write(tp, MII_BMCR, bmcr); + + return 0; +} + +int r8152_write_hwaddr(struct usbh_rtl8152 *tp, unsigned char *mac) +{ + unsigned char enetaddr[8] = { 0 }; + memcpy(enetaddr, mac, 6); + ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG); + pla_ocp_write(tp, PLA_IDR, BYTE_EN_SIX_BYTES, 8, enetaddr); + ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML); + return 0; +} + +int usbh_rtl8152_get_connect_status(struct usbh_rtl8152 *rtl8152_class) +{ + int ret; + + usbh_int_urb_fill(&rtl8152_class->intin_urb, rtl8152_class->hport, rtl8152_class->intin, g_rtl8152_inttx_buffer, 2, USB_OSAL_WAITING_FOREVER, NULL, NULL); + ret = usbh_submit_urb(&rtl8152_class->intin_urb); + if (ret < 0) { + return ret; + } + + if (g_rtl8152_inttx_buffer[0] & INTR_LINK) { + rtl8152_class->connect_status = true; + } else { + rtl8152_class->connect_status = false; + } + return 0; +} + +static int usbh_rtl8152_connect(struct usbh_hubport *hport, uint8_t intf) +{ + struct usb_endpoint_descriptor *ep_desc; + char mac_buffer[12]; + int ret; + + struct usbh_rtl8152 *rtl8152_class = &g_rtl8152_class; + + memset(rtl8152_class, 0, sizeof(struct usbh_rtl8152)); + + rtl8152_class->hport = hport; + rtl8152_class->intf = intf; + + hport->config.intf[intf].priv = rtl8152_class; + + rtl8152_class->version = usbh_rtl8152_get_version(rtl8152_class); + + if (rtl8152_class->version == RTL_VER_UNKNOWN) { + USB_LOG_ERR("Unknown version 0x%04x\r\n", rtl8152_class->version); + return -USB_ERR_NOTSUPP; + } else { + USB_LOG_INFO("rtl8152 version 0x%04x\r\n", rtl8152_class->version); + } + + /* MTU range: 68 - 1500 or 9194 */ + rtl8152_class->min_mtu = 68; + switch (rtl8152_class->version) { + case RTL_VER_03: + case RTL_VER_04: + case RTL_VER_05: + case RTL_VER_06: + case RTL_VER_08: + case RTL_VER_09: + case RTL_VER_14: + rtl8152_class->max_mtu = size_to_mtu(9 * 1024); + break; + case RTL_VER_10: + case RTL_VER_11: + rtl8152_class->max_mtu = size_to_mtu(15 * 1024); + break; + case RTL_VER_12: + case RTL_VER_13: + case RTL_VER_15: + rtl8152_class->max_mtu = size_to_mtu(16 * 1024); + break; + case RTL_VER_01: + case RTL_VER_02: + case RTL_VER_07: + default: + rtl8152_class->max_mtu = 1500; + break; + } + + rtl8152_class->saved_wolopts = __rtl_get_wol(rtl8152_class); + if (rtl_ops_init(rtl8152_class) < 0) { + return -USB_ERR_NODEV; + } + + rtl8152_class->rtl_ops.init(rtl8152_class); + rtl8152_class->rtl_ops.up(rtl8152_class); + + if (rtl8152_class->rx_buf_sz > CONFIG_USBHOST_RTL8152_ETH_MAX_RX_SIZE) { + USB_LOG_ERR("rx_buf_sz is overflow, default is %d\r\n", (unsigned int)CONFIG_USBHOST_RTL8152_ETH_MAX_RX_SIZE); + return -USB_ERR_NOMEM; + } + + memset(mac_buffer, 0, 12); + ret = usbh_get_string_desc(rtl8152_class->hport, 3, (uint8_t *)mac_buffer, 12); + if (ret < 0) { + return ret; + } + + for (int i = 0, j = 0; i < 12; i += 2, j++) { + char byte_str[3]; + byte_str[0] = mac_buffer[i]; + byte_str[1] = mac_buffer[i + 1]; + byte_str[2] = '\0'; + + uint32_t byte = strtoul(byte_str, NULL, 16); + rtl8152_class->mac[j] = (unsigned char)byte; + } + + r8152_write_hwaddr(rtl8152_class, rtl8152_class->mac); + + USB_LOG_INFO("RTL8152 MAC address %02x:%02x:%02x:%02x:%02x:%02x\r\n", + rtl8152_class->mac[0], + rtl8152_class->mac[1], + rtl8152_class->mac[2], + rtl8152_class->mac[3], + rtl8152_class->mac[4], + rtl8152_class->mac[5]); + + for (uint8_t i = 0; i < hport->config.intf[intf].altsetting[0].intf_desc.bNumEndpoints; i++) { + ep_desc = &hport->config.intf[intf].altsetting[0].ep[i].ep_desc; + + if (USB_GET_ENDPOINT_TYPE(ep_desc->bmAttributes) == USB_ENDPOINT_TYPE_INTERRUPT) { + if (ep_desc->bEndpointAddress & 0x80) { + USBH_EP_INIT(rtl8152_class->intin, ep_desc); + } else { + return -USB_ERR_NOTSUPP; + } + } else { + if (ep_desc->bEndpointAddress & 0x80) { + USBH_EP_INIT(rtl8152_class->bulkin, ep_desc); + } else { + USBH_EP_INIT(rtl8152_class->bulkout, ep_desc); + } + } + } + + strncpy(hport->config.intf[intf].devname, DEV_FORMAT, CONFIG_USBHOST_DEV_NAMELEN); + + USB_LOG_INFO("Register RTL8152 Class:%s\r\n", hport->config.intf[intf].devname); + + usbh_rtl8152_run(rtl8152_class); + return 0; +} + +static int usbh_rtl8152_disconnect(struct usbh_hubport *hport, uint8_t intf) +{ + int ret = 0; + + struct usbh_rtl8152 *rtl8152_class = (struct usbh_rtl8152 *)hport->config.intf[intf].priv; + + if (rtl8152_class) { + if (rtl8152_class->bulkin) { + usbh_kill_urb(&rtl8152_class->bulkin_urb); + } + + if (rtl8152_class->bulkout) { + usbh_kill_urb(&rtl8152_class->bulkout_urb); + } + + if (rtl8152_class->intin) { + usbh_kill_urb(&rtl8152_class->intin_urb); + } + + if (hport->config.intf[intf].devname[0] != '\0') { + usb_osal_thread_schedule_other(); + USB_LOG_INFO("Unregister rtl8152 Class:%s\r\n", hport->config.intf[intf].devname); + usbh_rtl8152_stop(rtl8152_class); + } + + memset(rtl8152_class, 0, sizeof(struct usbh_rtl8152)); + } + + return ret; +} + +void usbh_rtl8152_rx_thread(CONFIG_USB_OSAL_THREAD_SET_ARGV) +{ + uint32_t g_rtl8152_rx_length; + int ret; + uint16_t len; + uint16_t data_offset; +#if CONFIG_USBHOST_RTL8152_ETH_MAX_RX_SIZE <= (16 * 1024) + uint32_t transfer_size = CONFIG_USBHOST_RTL8152_ETH_MAX_RX_SIZE; +#else + uint32_t transfer_size = (16 * 1024); +#endif + + (void)CONFIG_USB_OSAL_THREAD_GET_ARGV; + USB_LOG_INFO("Create rtl8152 rx thread\r\n"); + // clang-format off +find_class: + // clang-format on + g_rtl8152_class.connect_status = false; + if (usbh_find_class_instance("/dev/rtl8152") == NULL) { + goto delete; + } + + while (g_rtl8152_class.connect_status == false) { + ret = usbh_rtl8152_get_connect_status(&g_rtl8152_class); + if (ret < 0) { + usb_osal_msleep(100); + goto find_class; + } + usb_osal_msleep(128); + } + + if (g_rtl8152_class.rtl_ops.enable) { + g_rtl8152_class.rtl_ops.enable(&g_rtl8152_class); + } else { + goto delete; + } + + rtl8152_set_rx_mode(&g_rtl8152_class); + rtl8152_set_speed(&g_rtl8152_class, AUTONEG_ENABLE, g_rtl8152_class.supports_gmii ? SPEED_1000 : SPEED_100, DUPLEX_FULL); + + g_rtl8152_rx_length = 0; + while (1) { + usbh_bulk_urb_fill(&g_rtl8152_class.bulkin_urb, g_rtl8152_class.hport, g_rtl8152_class.bulkin, &g_rtl8152_rx_buffer[g_rtl8152_rx_length], transfer_size, USB_OSAL_WAITING_FOREVER, NULL, NULL); + ret = usbh_submit_urb(&g_rtl8152_class.bulkin_urb); + if (ret < 0) { + goto find_class; + } + + g_rtl8152_rx_length += g_rtl8152_class.bulkin_urb.actual_length; + + /* A transfer is complete because last packet is a short packet. + * Short packet is not zero, match g_rtl8152_rx_length % USB_GET_MAXPACKETSIZE(g_rtl8152_class.bulkin->wMaxPacketSize). + * Short packet is zero, check if g_rtl8152_class.bulkin_urb.actual_length < transfer_size, for example transfer is complete with size is 1024 < 2048. + */ + if (g_rtl8152_rx_length % USB_GET_MAXPACKETSIZE(g_rtl8152_class.bulkin->wMaxPacketSize) || + (g_rtl8152_class.bulkin_urb.actual_length < transfer_size)) { + data_offset = 0; + + USB_LOG_DBG("rxlen:%d\r\n", g_rtl8152_rx_length); + while (g_rtl8152_rx_length > 0) { + struct rx_desc *rx_desc = (struct rx_desc *)&g_rtl8152_rx_buffer[data_offset]; + + len = rx_desc->opts1 & RX_LEN_MASK; + + USB_LOG_DBG("data_offset:%d, eth len:%d\r\n", data_offset, len); + + uint8_t *buf = (uint8_t *)&g_rtl8152_rx_buffer[data_offset + sizeof(struct rx_desc)]; + usbh_rtl8152_eth_input(buf, len); + + data_offset += (len + sizeof(struct rx_desc)); + g_rtl8152_rx_length -= (len + sizeof(struct rx_desc)); + + if (len & (RX_ALIGN - 1)) { + data_offset += (RX_ALIGN - (len & (RX_ALIGN - 1))); + g_rtl8152_rx_length -= (RX_ALIGN - (len & (RX_ALIGN - 1))); + } + } + } else { +#if CONFIG_USBHOST_RTL8152_ETH_MAX_RX_SIZE <= (16 * 1024) + if (g_rtl8152_rx_length == CONFIG_USBHOST_RTL8152_ETH_MAX_RX_SIZE) { +#else + if ((g_rtl8152_rx_length + (16 * 1024)) > CONFIG_USBHOST_RTL8152_ETH_MAX_RX_SIZE) { +#endif + USB_LOG_ERR("Rx packet is overflow, please reduce tcp window size or increase CONFIG_USBHOST_RTL8152_ETH_MAX_RX_SIZE\r\n"); + while (1) { + } + } + } + } + // clang-format off +delete: + USB_LOG_INFO("Delete rtl8152 rx thread\r\n"); + usb_osal_thread_delete(NULL); + // clang-format on +} + +uint8_t *usbh_rtl8152_get_eth_txbuf(void) +{ + return (g_rtl8152_tx_buffer + sizeof(struct tx_desc)); +} + +int usbh_rtl8152_eth_output(uint32_t buflen) +{ + struct tx_desc *tx_desc; + + if (g_rtl8152_class.connect_status == false) { + return -USB_ERR_NOTCONN; + } + + tx_desc = (struct tx_desc *)g_rtl8152_tx_buffer; + tx_desc->opts1 = buflen | TX_FS | TX_LS; + tx_desc->opts2 = 0; + + USB_LOG_DBG("txlen:%d\r\n", buflen + sizeof(struct tx_desc)); + + usbh_bulk_urb_fill(&g_rtl8152_class.bulkout_urb, g_rtl8152_class.hport, g_rtl8152_class.bulkout, g_rtl8152_tx_buffer, buflen + sizeof(struct tx_desc), USB_OSAL_WAITING_FOREVER, NULL, NULL); + return usbh_submit_urb(&g_rtl8152_class.bulkout_urb); +} + +static const uint16_t rtl_id_table[][2] = { + { 0x0BDA, 0x8152 }, + { 0, 0 }, +}; + +static const struct usbh_class_driver rtl8152_class_driver = { + .driver_name = "rtl8152", + .connect = usbh_rtl8152_connect, + .disconnect = usbh_rtl8152_disconnect +}; + +CLASS_INFO_DEFINE const struct usbh_class_info rtl8152_class_info = { + .match_flags = USB_CLASS_MATCH_VID_PID | USB_CLASS_MATCH_INTF_CLASS, + .bInterfaceClass = 0xff, + .bInterfaceSubClass = 0x00, + .bInterfaceProtocol = 0x00, + .id_table = rtl_id_table, + .class_driver = &rtl8152_class_driver +}; diff --git a/kernel/cherryusb/class/vendor/net/usbh_rtl8152.h b/kernel/cherryusb/class/vendor/net/usbh_rtl8152.h new file mode 100644 index 0000000..171fa0b --- /dev/null +++ b/kernel/cherryusb/class/vendor/net/usbh_rtl8152.h @@ -0,0 +1,68 @@ +/* + * Copyright (c) 2024, sakumisu + * + * SPDX-License-Identifier: Apache-2.0 + */ +#ifndef USBH_RTL8152_H +#define USBH_RTL8152_H + +struct usbh_rtl8152 { + struct usbh_hubport *hport; + struct usb_endpoint_descriptor *bulkin; /* Bulk IN endpoint */ + struct usb_endpoint_descriptor *bulkout; /* Bulk OUT endpoint */ + struct usb_endpoint_descriptor *intin; /* INTR IN endpoint */ + struct usbh_urb bulkout_urb; + struct usbh_urb bulkin_urb; + struct usbh_urb intin_urb; + + uint8_t intf; + + uint8_t mac[6]; + bool connect_status; + uint32_t speed[2]; + + uint8_t version; + uint8_t eee_adv; + uint8_t eee_en; + uint8_t supports_gmii; + uint16_t min_mtu; + uint16_t max_mtu; + uint16_t ocp_base; + uint32_t saved_wolopts; + uint32_t rx_buf_sz; + + struct rtl_ops { + void (*init)(struct usbh_rtl8152 *tp); + int (*enable)(struct usbh_rtl8152 *tp); + void (*disable)(struct usbh_rtl8152 *tp); + void (*up)(struct usbh_rtl8152 *tp); + void (*down)(struct usbh_rtl8152 *tp); + void (*unload)(struct usbh_rtl8152 *tp); + bool (*in_nway)(struct usbh_rtl8152 *tp); + void (*hw_phy_cfg)(struct usbh_rtl8152 *tp); + void (*autosuspend_en)(struct usbh_rtl8152 *tp, bool enable); + void (*change_mtu)(struct usbh_rtl8152 *tp); + } rtl_ops; + + void *user_data; +}; + +#ifdef __cplusplus +extern "C" { +#endif + +int usbh_rtl8152_get_connect_status(struct usbh_rtl8152 *rtl8152_class); + +void usbh_rtl8152_run(struct usbh_rtl8152 *rtl8152_class); +void usbh_rtl8152_stop(struct usbh_rtl8152 *rtl8152_class); + +uint8_t *usbh_rtl8152_get_eth_txbuf(void); +int usbh_rtl8152_eth_output(uint32_t buflen); +void usbh_rtl8152_eth_input(uint8_t *buf, uint32_t buflen); +void usbh_rtl8152_rx_thread(CONFIG_USB_OSAL_THREAD_SET_ARGV); + +#ifdef __cplusplus +} +#endif + +#endif /* USBH_RTL8152_H */ \ No newline at end of file diff --git a/kernel/cherryusb/class/vendor/wifi/.gitkeep b/kernel/cherryusb/class/vendor/wifi/.gitkeep new file mode 100644 index 0000000..e69de29 diff --git a/kernel/cherryusb/class/vendor/xbox/usbh_xbox.c b/kernel/cherryusb/class/vendor/xbox/usbh_xbox.c new file mode 100644 index 0000000..364ca27 --- /dev/null +++ b/kernel/cherryusb/class/vendor/xbox/usbh_xbox.c @@ -0,0 +1,229 @@ +/* + * Copyright (c) 2024 Till Harbaum + * + * SPDX-License-Identifier: Apache-2.0 + */ +#include "usbh_core.h" +#include "usbh_xbox.h" + +#define DEV_FORMAT "/dev/xbox%d" + +USB_NOCACHE_RAM_SECTION USB_MEM_ALIGNX uint8_t g_xbox_buf[128]; + +static struct usbh_xbox g_xbox_class[CONFIG_USBHOST_MAX_XBOX_CLASS]; +static uint32_t g_devinuse = 0; + +static struct usbh_xbox *usbh_xbox_class_alloc(void) +{ + uint8_t devno; + + for (devno = 0; devno < CONFIG_USBHOST_MAX_XBOX_CLASS; devno++) { + if ((g_devinuse & (1U << devno)) == 0) { + g_devinuse |= (1U << devno); + memset(&g_xbox_class[devno], 0, sizeof(struct usbh_xbox)); + g_xbox_class[devno].minor = devno; + return &g_xbox_class[devno]; + } + } + return NULL; +} + +static void usbh_xbox_class_free(struct usbh_xbox *xbox_class) +{ + uint8_t devno = xbox_class->minor; + + if (devno < 32) { + g_devinuse &= ~(1U << devno); + } + memset(xbox_class, 0, sizeof(struct usbh_xbox)); +} + +int usbh_xbox_connect(struct usbh_hubport *hport, uint8_t intf) +{ + struct usb_endpoint_descriptor *ep_desc; + + struct usbh_xbox *xbox_class = usbh_xbox_class_alloc(); + if (xbox_class == NULL) { + USB_LOG_ERR("Fail to alloc xbox_class\r\n"); + return -USB_ERR_NOMEM; + } + + xbox_class->hport = hport; + xbox_class->intf = intf; + + hport->config.intf[intf].priv = xbox_class; + + for (uint8_t i = 0; i < hport->config.intf[intf].altsetting[0].intf_desc.bNumEndpoints; i++) { + ep_desc = &hport->config.intf[intf].altsetting[0].ep[i].ep_desc; + if (ep_desc->bEndpointAddress & 0x80) { + USBH_EP_INIT(xbox_class->intin, ep_desc); + } else { + USBH_EP_INIT(xbox_class->intout, ep_desc); + } + } + + snprintf(hport->config.intf[intf].devname, CONFIG_USBHOST_DEV_NAMELEN, DEV_FORMAT, xbox_class->minor); + + USB_LOG_INFO("Register XBOX Class:%s\r\n", hport->config.intf[intf].devname); + + usbh_xbox_run(xbox_class); + return 0; +} + +int usbh_xbox_disconnect(struct usbh_hubport *hport, uint8_t intf) +{ + int ret = 0; + + struct usbh_xbox *xbox_class = (struct usbh_xbox *)hport->config.intf[intf].priv; + + if (xbox_class) { + if (xbox_class->intin) { + usbh_kill_urb(&xbox_class->intin_urb); + } + + if (xbox_class->intout) { + usbh_kill_urb(&xbox_class->intout_urb); + } + + if (hport->config.intf[intf].devname[0] != '\0') { + usb_osal_thread_schedule_other(); + USB_LOG_INFO("Unregister XBOX Class:%s\r\n", hport->config.intf[intf].devname); + usbh_xbox_stop(xbox_class); + } + + usbh_xbox_class_free(xbox_class); + } + + return ret; +} + +__WEAK void usbh_xbox_run(struct usbh_xbox *xbox_class) +{ +} + +__WEAK void usbh_xbox_stop(struct usbh_xbox *xbox_class) +{ +} + +const struct usbh_class_driver xbox_class_driver = { + .driver_name = "xbox", + .connect = usbh_xbox_connect, + .disconnect = usbh_xbox_disconnect +}; + +static const uint16_t xbox_id_table[][2] = { + { 0x0079, 0x18d4 }, // GPD Win 2 X-Box Controller + { 0x03eb, 0xff01 }, // Wooting One (Legacy) + { 0x03eb, 0xff02 }, // Wooting Two (Legacy) + { 0x044f, 0xb326 }, // Thrustmaster Gamepad GP XID + { 0x045e, 0x028e }, // Microsoft X-Box 360 pad + { 0x045e, 0x028f }, // Microsoft X-Box 360 pad v2 + { 0x046d, 0xc21d }, // Logitech Gamepad F310 + { 0x046d, 0xc21e }, // Logitech Gamepad F510 + { 0x046d, 0xc21f }, // Logitech Gamepad F710 + { 0x046d, 0xc242 }, // Logitech Chillstream Controller + { 0x046d, 0xcaa3 }, // Logitech DriveFx Racing Wheel + { 0x056e, 0x2004 }, // Elecom JC-U3613M + { 0x06a3, 0xf51a }, // Saitek P3600 + { 0x0738, 0x4716 }, // Mad Catz Wired Xbox 360 Controller + { 0x0738, 0x4718 }, // Mad Catz Street Fighter IV FightStick SE + { 0x0738, 0x4726 }, // Mad Catz Xbox 360 Controller + { 0x0738, 0x4736 }, // Mad Catz MicroCon Gamepad + { 0x0738, 0x4740 }, // Mad Catz Beat Pad + { 0x0738, 0x9871 }, // Mad Catz Portable Drum + { 0x0738, 0xb726 }, // Mad Catz Xbox controller - MW2 + { 0x0738, 0xbeef }, // Mad Catz JOYTECH NEO SE Advanced GamePad + { 0x0738, 0xcb02 }, // Saitek Cyborg Rumble Pad - PC/Xbox 360 + { 0x0738, 0xcb03 }, // Saitek P3200 Rumble Pad - PC/Xbox 360 + { 0x0738, 0xcb29 }, // Saitek Aviator Stick AV8R02 + { 0x0738, 0xf738 }, // Super SFIV FightStick TE S + { 0x07ff, 0xffff }, // Mad Catz GamePad + { 0x0e6f, 0x0113 }, // Afterglow AX.1 Gamepad for Xbox 360 + { 0x0e6f, 0x011f }, // Rock Candy Gamepad Wired Controller + { 0x0e6f, 0x0131 }, // PDP EA Sports Controller + { 0x0e6f, 0x0133 }, // Xbox 360 Wired Controller + { 0x0e6f, 0x0201 }, // Pelican PL-3601 'TSZ' Wired Xbox 360 Controller + { 0x0e6f, 0x0213 }, // Afterglow Gamepad for Xbox 360 + { 0x0e6f, 0x021f }, // Rock Candy Gamepad for Xbox 360 + { 0x0e6f, 0x0301 }, // Logic3 Controller + { 0x0e6f, 0x0401 }, // Logic3 Controller + { 0x0e6f, 0x0413 }, // Afterglow AX.1 Gamepad for Xbox 360 + { 0x0e6f, 0x0501 }, // PDP Xbox 360 Controller + { 0x0e6f, 0xf900 }, // PDP Afterglow AX.1 + { 0x0f0d, 0x000a }, // Hori Co. DOA4 FightStick + { 0x0f0d, 0x000c }, // Hori PadEX Turbo + { 0x1038, 0x1430 }, // SteelSeries Stratus Duo + { 0x1038, 0x1431 }, // SteelSeries Stratus Duo + { 0x11c9, 0x55f0 }, // Nacon GC-100XF + { 0x1209, 0x2882 }, // Ardwiino Controller + { 0x12ab, 0x0301 }, // PDP AFTERGLOW AX.1 + { 0x1430, 0x4748 }, // RedOctane Guitar Hero X-plorer + { 0x1430, 0xf801 }, // RedOctane Controller + { 0x146b, 0x0601 }, // BigBen Interactive XBOX 360 Controller + { 0x1532, 0x0037 }, // Razer Sabertooth + { 0x15e4, 0x3f00 }, // Power A Mini Pro Elite + { 0x15e4, 0x3f0a }, // Xbox Airflo wired controller + { 0x15e4, 0x3f10 }, // Batarang Xbox 360 controller + { 0x162e, 0xbeef }, // Joytech Neo-Se Take2 + { 0x1689, 0xfd00 }, // Razer Onza Tournament Edition + { 0x1689, 0xfd01 }, // Razer Onza Classic Edition + { 0x1689, 0xfe00 }, // Razer Sabertooth + { 0x1949, 0x041a }, // Amazon Game Controller + { 0x1bad, 0x0002 }, // Harmonix Rock Band Guitar + { 0x1bad, 0xf016 }, // Mad Catz Xbox 360 Controller + { 0x1bad, 0xf021 }, // Mad Cats Ghost Recon FS GamePad + { 0x1bad, 0xf023 }, // MLG Pro Circuit Controller (Xbox) + { 0x1bad, 0xf025 }, // Mad Catz Call Of Duty + { 0x1bad, 0xf027 }, // Mad Catz FPS Pro + { 0x1bad, 0xf028 }, // Street Fighter IV FightPad + { 0x1bad, 0xf030 }, // Mad Catz Xbox 360 MC2 MicroCon Racing Wheel + { 0x1bad, 0xf036 }, // Mad Catz MicroCon GamePad Pro + { 0x1bad, 0xf038 }, // Street Fighter IV FightStick TE + { 0x1bad, 0xf501 }, // HoriPad EX2 Turbo + { 0x1bad, 0xf506 }, // Hori Real Arcade Pro.EX Premium VLX + { 0x1bad, 0xf900 }, // Harmonix Xbox 360 Controller + { 0x1bad, 0xf901 }, // Gamestop Xbox 360 Controller + { 0x1bad, 0xf903 }, // Tron Xbox 360 controller + { 0x1bad, 0xf904 }, // PDP Versus Fighting Pad + { 0x1bad, 0xfa01 }, // MadCatz GamePad + { 0x1bad, 0xfd00 }, // Razer Onza TE + { 0x1bad, 0xfd01 }, // Razer Onza + { 0x20d6, 0x2001 }, // BDA Xbox Series X Wired Controller + { 0x20d6, 0x281f }, // PowerA Wired Controller For Xbox 360 + { 0x24c6, 0x5300 }, // PowerA MINI PROEX Controller + { 0x24c6, 0x5303 }, // Xbox Airflo wired controller + { 0x24c6, 0x530a }, // Xbox 360 Pro EX Controller + { 0x24c6, 0x531a }, // PowerA Pro Ex + { 0x24c6, 0x5397 }, // FUS1ON Tournament Controller + { 0x24c6, 0x5500 }, // Hori XBOX 360 EX 2 with Turbo + { 0x24c6, 0x5501 }, // Hori Real Arcade Pro VX-SA + { 0x24c6, 0x5506 }, // Hori SOULCALIBUR V Stick + { 0x24c6, 0x550d }, // Hori GEM Xbox controller + { 0x24c6, 0x5b00 }, // ThrustMaster Ferrari 458 Racing Wheel + { 0x24c6, 0x5b02 }, // Thrustmaster, Inc. GPX Controller + { 0x24c6, 0x5b03 }, // Thrustmaster Ferrari 458 Racing Wheel + { 0x24c6, 0x5d04 }, // Razer Sabertooth + { 0x24c6, 0xfafe }, // Rock Candy Gamepad for Xbox 360 + { 0x2563, 0x058d }, // OneXPlayer Gamepad + { 0x2dc8, 0x3106 }, // 8BitDo Ultimate Wireless / Pro 2 Wired Controller + { 0x2dc8, 0x3109 }, // 8BitDo Ultimate Wireless Bluetooth + { 0x31e3, 0x1100 }, // Wooting One + { 0x31e3, 0x1200 }, // Wooting Two + { 0x31e3, 0x1210 }, // Wooting Lekker + { 0x31e3, 0x1220 }, // Wooting Two HE + { 0x31e3, 0x1230 }, // Wooting Two HE (ARM) + { 0x31e3, 0x1300 }, // Wooting 60HE (AVR) + { 0x31e3, 0x1310 }, // Wooting 60HE (ARM) + { 0x3285, 0x0607 }, // Nacon GC-100 + { 0x413d, 0x2104 }, // Black Shark Green Ghost Gamepad + { 0x0000, 0x0000 } // end of list +}; + +CLASS_INFO_DEFINE const struct usbh_class_info xbox_custom_class_info = { + .match_flags = USB_CLASS_MATCH_VID_PID | USB_CLASS_MATCH_INTF_CLASS | USB_CLASS_MATCH_INTF_SUBCLASS | USB_CLASS_MATCH_INTF_PROTOCOL, + .bInterfaceClass = USB_DEVICE_CLASS_VEND_SPECIFIC, + .bInterfaceSubClass = 0x5d, + .bInterfaceProtocol = 0x01, + .id_table = xbox_id_table, + .class_driver = &xbox_class_driver +}; diff --git a/kernel/cherryusb/class/vendor/xbox/usbh_xbox.h b/kernel/cherryusb/class/vendor/xbox/usbh_xbox.h new file mode 100644 index 0000000..85d4672 --- /dev/null +++ b/kernel/cherryusb/class/vendor/xbox/usbh_xbox.h @@ -0,0 +1,31 @@ +/* + * Copyright (c) 2024, Till Harbaum + * + * SPDX-License-Identifier: Apache-2.0 + */ +#ifndef USBH_XBOX_H +#define USBH_XBOX_H + +struct usbh_xbox { + struct usbh_hubport *hport; + struct usb_endpoint_descriptor *intin; /* INTR IN endpoint */ + struct usb_endpoint_descriptor *intout; /* INTR OUT endpoint */ + struct usbh_urb intin_urb; /* INTR IN urb */ + struct usbh_urb intout_urb; /* INTR OUT urb */ + + uint8_t intf; /* interface number */ + uint8_t minor; +}; + +#ifdef __cplusplus +extern "C" { +#endif + +void usbh_xbox_run(struct usbh_xbox *xbox_class); +void usbh_xbox_stop(struct usbh_xbox *xbox_class); + +#ifdef __cplusplus +} +#endif + +#endif /* USBH_XBOX_H */ diff --git a/kernel/cherryusb/class/video/usb_video.h b/kernel/cherryusb/class/video/usb_video.h new file mode 100644 index 0000000..8f95992 --- /dev/null +++ b/kernel/cherryusb/class/video/usb_video.h @@ -0,0 +1,1380 @@ +/* + * Copyright (c) 2022, sakumisu + * + * SPDX-License-Identifier: Apache-2.0 + */ +#ifndef USB_VIDEO_H +#define USB_VIDEO_H + +#define USB_DEVICE_VIDEO_CLASS_VERSION_1_5 0 + +/*! @brief Video device subclass code */ +#define VIDEO_SC_UNDEFINED 0x00U +#define VIDEO_SC_VIDEOCONTROL 0x01U +#define VIDEO_SC_VIDEOSTREAMING 0x02U +#define VIDEO_SC_VIDEO_INTERFACE_COLLECTION 0x03U + +/*! @brief Video device protocol code */ +#define VIDEO_PC_PROTOCOL_UNDEFINED 0x00U +#define VIDEO_PC_PROTOCOL_15 0x01U + +/*! @brief Video device class-specific descriptor type */ +#define VIDEO_CS_UNDEFINED_DESCRIPTOR_TYPE 0x20U +#define VIDEO_CS_DEVICE_DESCRIPTOR_TYPE 0x21U +#define VIDEO_CS_CONFIGURATION_DESCRIPTOR_TYPE 0x22U +#define VIDEO_CS_STRING_DESCRIPTOR_TYPE 0x23U +#define VIDEO_CS_INTERFACE_DESCRIPTOR_TYPE 0x24U +#define VIDEO_CS_ENDPOINT_DESCRIPTOR_TYPE 0x25U + +/*! @brief Video device class-specific VC interface descriptor subtype */ +#define VIDEO_VC_DESCRIPTOR_UNDEFINED_DESCRIPTOR_SUBTYPE 0x00U +#define VIDEO_VC_HEADER_DESCRIPTOR_SUBTYPE 0x01U +#define VIDEO_VC_INPUT_TERMINAL_DESCRIPTOR_SUBTYPE 0x02U +#define VIDEO_VC_OUTPUT_TERMINAL_DESCRIPTOR_SUBTYPE 0x03U +#define VIDEO_VC_SELECTOR_UNIT_DESCRIPTOR_SUBTYPE 0x04U +#define VIDEO_VC_PROCESSING_UNIT_DESCRIPTOR_SUBTYPE 0x05U +#define VIDEO_VC_EXTENSION_UNIT_DESCRIPTOR_SUBTYPE 0x06U +#define VIDEO_VC_ENCODING_UNIT_DESCRIPTOR_SUBTYPE 0x07U + +/*! @brief Video device class-specific VS interface descriptor subtype */ +#define VIDEO_VS_UNDEFINED_DESCRIPTOR_SUBTYPE 0x00U +#define VIDEO_VS_INPUT_HEADER_DESCRIPTOR_SUBTYPE 0x01U +#define VIDEO_VS_OUTPUT_HEADER_DESCRIPTOR_SUBTYPE 0x02U +#define VIDEO_VS_STILL_IMAGE_FRAME_DESCRIPTOR_SUBTYPE 0x03U +#define VIDEO_VS_FORMAT_UNCOMPRESSED_DESCRIPTOR_SUBTYPE 0x04U +#define VIDEO_VS_FRAME_UNCOMPRESSED_DESCRIPTOR_SUBTYPE 0x05U +#define VIDEO_VS_FORMAT_MJPEG_DESCRIPTOR_SUBTYPE 0x06U +#define VIDEO_VS_FRAME_MJPEG_DESCRIPTOR_SUBTYPE 0x07U +#define VIDEO_VS_FORMAT_MPEG2TS_DESCRIPTOR_SUBTYPE 0x0AU +#define VIDEO_VS_FORMAT_DV_DESCRIPTOR_SUBTYPE 0x0CU +#define VIDEO_VS_COLORFORMAT_DESCRIPTOR_SUBTYPE 0x0DU +#define VIDEO_VS_FORMAT_FRAME_BASED_DESCRIPTOR_SUBTYPE 0x10U +#define VIDEO_VS_FRAME_FRAME_BASED_DESCRIPTOR_SUBTYPE 0x11U +#define VIDEO_VS_FORMAT_STREAM_BASED_DESCRIPTOR_SUBTYPE 0x12U +#define VIDEO_VS_FORMAT_H264_DESCRIPTOR_SUBTYPE 0x13U +#define VIDEO_VS_FRAME_H264_DESCRIPTOR_SUBTYPE 0x14U +#define VIDEO_VS_FORMAT_H264_SIMULCAST_DESCRIPTOR_SUBTYPE 0x15U +#define VIDEO_VS_FORMAT_VP8_DESCRIPTOR_SUBTYPE 0x16U +#define VIDEO_VS_FRAME_VP8_DESCRIPTOR_SUBTYPE 0x17U +#define VIDEO_VS_FORMAT_VP8_SIMULCAST_DESCRIPTOR_SUBTYPE 0x18U + +/*! @brief Video device class-specific VC endpoint descriptor subtype */ +#define VIDEO_EP_UNDEFINED_DESCRIPTOR_SUBTYPE 0x00U +#define VIDEO_EP_GENERAL_DESCRIPTOR_SUBTYPE 0x01U +#define VIDEO_EP_ENDPOINT_DESCRIPTOR_SUBTYPE 0x02U +#define VIDEO_EP_INTERRUPT_DESCRIPTOR_SUBTYPE 0x03U + +/*! @brief Video device class-specific request code */ +#define VIDEO_REQUEST_UNDEFINED 0x00U +#define VIDEO_REQUEST_SET_CUR 0x01U +#define VIDEO_REQUEST_SET_CUR_ALL 0x11U +#define VIDEO_REQUEST_GET_CUR 0x81U +#define VIDEO_REQUEST_GET_MIN 0x82U +#define VIDEO_REQUEST_GET_MAX 0x83U +#define VIDEO_REQUEST_GET_RES 0x84U +#define VIDEO_REQUEST_GET_LEN 0x85U +#define VIDEO_REQUEST_GET_INFO 0x86U +#define VIDEO_REQUEST_GET_DEF 0x87U +#define VIDEO_REQUEST_GET_CUR_ALL 0x91U +#define VIDEO_REQUEST_GET_MIN_ALL 0x92U +#define VIDEO_REQUEST_GET_MAX_ALL 0x93U +#define VIDEO_REQUEST_GET_RES_ALL 0x94U +#define VIDEO_REQUEST_GET_DEF_ALL 0x97U + +/*! @brief Video device class-specific VideoControl interface control selector */ +#define VIDEO_VC_CONTROL_UNDEFINED 0x00U +#define VIDEO_VC_VIDEO_POWER_MODE_CONTROL 0x01U +#define VIDEO_VC_REQUEST_ERROR_CODE_CONTROL 0x02U + +/*! @brief Video device class-specific Terminal control selector */ +#define VIDEO_TE_CONTROL_UNDEFINED 0x00U + +/*! @brief Video device class-specific Selector Unit control selector */ +#define VIDEO_SU_CONTROL_UNDEFINED 0x00U +#define VIDEO_SU_INPUT_SELECT_CONTROL 0x01U + +/*! @brief Video device class-specific Camera Terminal control selector */ +#define VIDEO_CT_CONTROL_UNDEFINED 0x00U +#define VIDEO_CT_SCANNING_MODE_CONTROL 0x01U +#define VIDEO_CT_AE_MODE_CONTROL 0x02U +#define VIDEO_CT_AE_PRIORITY_CONTROL 0x03U +#define VIDEO_CT_EXPOSURE_TIME_ABSOLUTE_CONTROL 0x04U +#define VIDEO_CT_EXPOSURE_TIME_RELATIVE_CONTROL 0x05U +#define VIDEO_CT_FOCUS_ABSOLUTE_CONTROL 0x06U +#define VIDEO_CT_FOCUS_RELATIVE_CONTROL 0x07U +#define VIDEO_CT_FOCUS_AUTO_CONTROL 0x08U +#define VIDEO_CT_IRIS_ABSOLUTE_CONTROL 0x09U +#define VIDEO_CT_IRIS_RELATIVE_CONTROL 0x0AU +#define VIDEO_CT_ZOOM_ABSOLUTE_CONTROL 0x0BU +#define VIDEO_CT_ZOOM_RELATIVE_CONTROL 0x0CU +#define VIDEO_CT_PANTILT_ABSOLUTE_CONTROL 0x0DU +#define VIDEO_CT_PANTILT_RELATIVE_CONTROL 0x0EU +#define VIDEO_CT_ROLL_ABSOLUTE_CONTROL 0x0FU +#define VIDEO_CT_ROLL_RELATIVE_CONTROL 0x10U +#define VIDEO_CT_PRIVACY_CONTROL 0x11U +#define VIDEO_CT_FOCUS_SIMPLE_CONTROL 0x12U +#define VIDEO_CT_WINDOW_CONTROL 0x13U +#define VIDEO_CT_REGION_OF_INTEREST_CONTROL 0x14U + +/*! @brief Video device class-specific Processing Unit control selector */ +#define VIDEO_PU_CONTROL_UNDEFINED 0x00U +#define VIDEO_PU_BACKLIGHT_COMPENSATION_CONTROL 0x01U +#define VIDEO_PU_BRIGHTNESS_CONTROL 0x02U +#define VIDEO_PU_CONTRAST_CONTROL 0x03U +#define VIDEO_PU_GAIN_CONTROL 0x04U +#define VIDEO_PU_POWER_LINE_FREQUENCY_CONTROL 0x05U +#define VIDEO_PU_HUE_CONTROL 0x06U +#define VIDEO_PU_SATURATION_CONTROL 0x07U +#define VIDEO_PU_SHARPNESS_CONTROL 0x08U +#define VIDEO_PU_GAMMA_CONTROL 0x09U +#define VIDEO_PU_WHITE_BALANCE_TEMPERATURE_CONTROL 0x0AU +#define VIDEO_PU_WHITE_BALANCE_TEMPERATURE_AUTO_CONTROL 0x0BU +#define VIDEO_PU_WHITE_BALANCE_COMPONENT_CONTROL 0x0CU +#define VIDEO_PU_WHITE_BALANCE_COMPONENT_AUTO_CONTROL 0x0DU +#define VIDEO_PU_DIGITAL_MULTIPLIER_CONTROL 0x0EU +#define VIDEO_PU_DIGITAL_MULTIPLIER_LIMIT_CONTROL 0x0FU +#define VIDEO_PU_HUE_AUTO_CONTROL 0x10U +#define VIDEO_PU_ANALOG_VIDEO_STANDARD_CONTROL 0x11U +#define VIDEO_PU_ANALOG_LOCK_STATUS_CONTROL 0x12U +#define VIDEO_PU_CONTRAST_AUTO_CONTROL 0x13U + +/*! @brief Video device class-specific Encoding Unit control selector */ +#define VIDEO_EU_CONTROL_UNDEFINED 0x00U +#define VIDEO_EU_SELECT_LAYER_CONTROL 0x01U +#define VIDEO_EU_PROFILE_TOOLSET_CONTROL 0x02U +#define VIDEO_EU_VIDEO_RESOLUTION_CONTROL 0x03U +#define VIDEO_EU_MIN_FRAME_INTERVAL_CONTROL 0x04U +#define VIDEO_EU_SLICE_MODE_CONTROL 0x05U +#define VIDEO_EU_RATE_CONTROL_MODE_CONTROL 0x06U +#define VIDEO_EU_AVERAGE_BITRATE_CONTROL 0x07U +#define VIDEO_EU_CPB_SIZE_CONTROL 0x08U +#define VIDEO_EU_PEAK_BIT_RATE_CONTROL 0x09U +#define VIDEO_EU_QUANTIZATION_PARAMS_CONTROL 0x0AU +#define VIDEO_EU_SYNC_REF_FRAME_CONTROL 0x0BU +#define VIDEO_EU_LTR_BUFFER_CONTROL 0x0CU +#define VIDEO_EU_LTR_PICTURE_CONTROL 0x0DU +#define VIDEO_EU_LTR_VALIDATION_CONTROL 0x0EU +#define VIDEO_EU_LEVEL_IDC_LIMIT_CONTROL 0x0FU +#define VIDEO_EU_SEI_PAYLOADTYPE_CONTROL 0x10U +#define VIDEO_EU_QP_RANGE_CONTROL 0x11U +#define VIDEO_EU_PRIORITY_CONTROL 0x12U +#define VIDEO_EU_START_OR_STOP_LAYER_CONTROL 0x13U +#define VIDEO_EU_ERROR_RESILIENCY_CONTROL 0x14U + +/*! @brief Video device class-specific Extension Unit control selector */ +#define VIDEO_XU_CONTROL_UNDEFINED 0x00U + +/*! @brief Video device class-specific VideoStreaming Interface control selector */ +#define VIDEO_VS_CONTROL_UNDEFINED 0x00U +#define VIDEO_VS_PROBE_CONTROL 0x01U +#define VIDEO_VS_COMMIT_CONTROL 0x02U +#define VIDEO_VS_STILL_PROBE_CONTROL 0x03U +#define VIDEO_VS_STILL_COMMIT_CONTROL 0x04U +#define VIDEO_VS_STILL_IMAGE_TRIGGER_CONTROL 0x05U +#define VIDEO_VS_STREAM_ERROR_CODE_CONTROL 0x06U +#define VIDEO_VS_GENERATE_KEY_FRAME_CONTROL 0x07U +#define VIDEO_VS_UPDATE_FRAME_SEGMENT_CONTROL 0x08U +#define VIDEO_VS_SYNCH_DELAY_CONTROL 0x09U + +/*! @}*/ + +/*! + * @name USB Video class terminal types + * @{ + */ + +/*! @brief Video device USB terminal type */ +#define VIDEO_TT_VENDOR_SPECIFIC 0x0100U +#define VIDEO_TT_STREAMING 0x0101U + +/*! @brief Video device input terminal type */ +#define VIDEO_ITT_VENDOR_SPECIFIC 0x0200U +#define VIDEO_ITT_CAMERA 0x0201U +#define VIDEO_ITT_MEDIA_TRANSPORT_INPUT 0x0202U + +/*! @brief Video device output terminal type */ +#define VIDEO_OTT_VENDOR_SPECIFIC 0x0300U +#define VIDEO_OTT_DISPLAY 0x0301U +#define VIDEO_OTT_MEDIA_TRANSPORT_OUTPUT 0x0302U + +/*! @brief Video device external terminal type */ +#define VIDEO_ET_VENDOR_SPECIFIC 0x0400U +#define VIDEO_ET_COMPOSITE_CONNECTOR 0x0401U +#define VIDEO_ET_SVIDEO_CONNECTOR 0x0402U +#define VIDEO_ET_COMPONENT_CONNECTOR 0x0403U + +/*! @}*/ + +/*! + * @name USB Video class setup request types + * @{ + */ + +/*! @brief Video device class setup request set type */ +#define VIDEO_SET_REQUEST_INTERFACE 0x21U +#define VIDEO_SET_REQUEST_ENDPOINT 0x22U + +/*! @brief Video device class setup request get type */ +#define VIDEO_GET_REQUEST_INTERFACE 0xA1U +#define VIDEO_GET_REQUEST_ENDPOINT 0xA2U + +/*! @}*/ + +/*! @brief Video device still image trigger control */ +#define VIDEO_STILL_IMAGE_TRIGGER_NORMAL_OPERATION 0x00U +#define VIDEO_STILL_IMAGE_TRIGGER_TRANSMIT_STILL_IMAGE 0x01U +#define VIDEO_STILL_IMAGE_TRIGGER_TRANSMIT_STILL_IMAGE_VS_DEDICATED_BULK_PIPE 0x02U +#define VIDEO_STILL_IMAGE_TRIGGER_ABORT_STILL_IMAGE_TRANSMISSION 0x03U + +/*! + * @name USB Video device class-specific request commands + * @{ + */ + +/*! @brief Video device class-specific request GET CUR COMMAND */ +#define VIDEO_GET_CUR_VC_POWER_MODE_CONTROL 0x8101U +#define VIDEO_GET_CUR_VC_ERROR_CODE_CONTROL 0x8102U + +#define VIDEO_GET_CUR_PU_BACKLIGHT_COMPENSATION_CONTROL 0x8121U +#define VIDEO_GET_CUR_PU_BRIGHTNESS_CONTROL 0x8122U +#define VIDEO_GET_CUR_PU_CONTRACT_CONTROL 0x8123U +#define VIDEO_GET_CUR_PU_GAIN_CONTROL 0x8124U +#define VIDEO_GET_CUR_PU_POWER_LINE_FREQUENCY_CONTROL 0x8125U +#define VIDEO_GET_CUR_PU_HUE_CONTROL 0x8126U +#define VIDEO_GET_CUR_PU_SATURATION_CONTROL 0x8127U +#define VIDEO_GET_CUR_PU_SHARRNESS_CONTROL 0x8128U +#define VIDEO_GET_CUR_PU_GAMMA_CONTROL 0x8129U +#define VIDEO_GET_CUR_PU_WHITE_BALANCE_TEMPERATURE_CONTROL 0x812AU +#define VIDEO_GET_CUR_PU_WHITE_BALANCE_TEMPERATURE_AUTO_CONTROL 0x812BU +#define VIDEO_GET_CUR_PU_WHITE_BALANCE_COMPONENT_CONTROL 0x812CU +#define VIDEO_GET_CUR_PU_WHITE_BALANCE_COMPONENT_AUTO_CONTROL 0x812DU +#define VIDEO_GET_CUR_PU_DIGITAL_MULTIPLIER_CONTROL 0x812EU +#define VIDEO_GET_CUR_PU_DIGITAL_MULTIPLIER_LIMIT_CONTROL 0x812FU +#define VIDEO_GET_CUR_PU_HUE_AUTO_CONTROL 0x8130U +#define VIDEO_GET_CUR_PU_ANALOG_VIDEO_STANDARD_CONTROL 0x8131U +#define VIDEO_GET_CUR_PU_ANALOG_LOCK_STATUS_CONTROL 0x8132U +#if defined(USB_DEVICE_VIDEO_CLASS_VERSION_1_5) && USB_DEVICE_VIDEO_CLASS_VERSION_1_5 +#define VIDEO_GET_CUR_PU_CONTRAST_AUTO_CONTROL 0x8133U +#endif + +#define VIDEO_GET_CUR_CT_SCANNING_MODE_CONTROL 0x8141U +#define VIDEO_GET_CUR_CT_AE_MODE_CONTROL 0x8142U +#define VIDEO_GET_CUR_CT_AE_PRIORITY_CONTROL 0x8143U +#define VIDEO_GET_CUR_CT_EXPOSURE_TIME_ABSOLUTE_CONTROL 0x8144U +#define VIDEO_GET_CUR_CT_EXPOSURE_TIME_RELATIVE_CONTROL 0x8145U +#define VIDEO_GET_CUR_CT_FOCUS_ABSOLUTE_CONTROL 0x8146U +#define VIDEO_GET_CUR_CT_FOCUS_RELATIVE_CONTROL 0x8147U +#define VIDEO_GET_CUR_CT_FOCUS_AUTO_CONTROL 0x8148U +#define VIDEO_GET_CUR_CT_IRIS_ABSOLUTE_CONTROL 0x8149U +#define VIDEO_GET_CUR_CT_IRIS_RELATIVE_CONTROL 0x814AU +#define VIDEO_GET_CUR_CT_ZOOM_ABSOLUTE_CONTROL 0x814BU +#define VIDEO_GET_CUR_CT_ZOOM_RELATIVE_CONTROL 0x814CU +#define VIDEO_GET_CUR_CT_PANTILT_ABSOLUTE_CONTROL 0x814DU +#define VIDEO_GET_CUR_CT_PANTILT_RELATIVE_CONTROL 0x814EU +#define VIDEO_GET_CUR_CT_ROLL_ABSOLUTE_CONTROL 0x814FU +#define VIDEO_GET_CUR_CT_ROLL_RELATIVE_CONTROL 0x8150U +#define VIDEO_GET_CUR_CT_PRIVACY_CONTROL 0x8151U +#if defined(USB_DEVICE_VIDEO_CLASS_VERSION_1_5) && USB_DEVICE_VIDEO_CLASS_VERSION_1_5 +#define VIDEO_GET_CUR_CT_FOCUS_SIMPLE_CONTROL 0x8152U +#define VIDEO_GET_CUR_CT_DIGITAL_WINDOW_CONTROL 0x8153U +#define VIDEO_GET_CUR_CT_REGION_OF_INTEREST_CONTROL 0x8154U +#endif + +#define VIDEO_GET_CUR_VS_PROBE_CONTROL 0x8161U +#define VIDEO_GET_CUR_VS_COMMIT_CONTROL 0x8162U +#define VIDEO_GET_CUR_VS_STILL_PROBE_CONTROL 0x8163U +#define VIDEO_GET_CUR_VS_STILL_COMMIT_CONTROL 0x8164U +#define VIDEO_GET_CUR_VS_STILL_IMAGE_TRIGGER_CONTROL 0x8165U +#define VIDEO_GET_CUR_VS_STREAM_ERROR_CODE_CONTROL 0x8166U +#define VIDEO_GET_CUR_VS_GENERATE_KEY_FRAME_CONTROL 0x8167U +#define VIDEO_GET_CUR_VS_UPDATE_FRAME_SEGMENT_CONTROL 0x8168U +#define VIDEO_GET_CUR_VS_SYNCH_DELAY_CONTROL 0x8169U + +#if defined(USB_DEVICE_VIDEO_CLASS_VERSION_1_5) && USB_DEVICE_VIDEO_CLASS_VERSION_1_5 +#define VIDEO_GET_CUR_EU_SELECT_LAYER_CONTROL 0x8181U +#define VIDEO_GET_CUR_EU_PROFILE_TOOLSET_CONTROL 0x8182U +#define VIDEO_GET_CUR_EU_VIDEO_RESOLUTION_CONTROL 0x8183U +#define VIDEO_GET_CUR_EU_MIN_FRAME_INTERVAL_CONTROL 0x8184U +#define VIDEO_GET_CUR_EU_SLICE_MODE_CONTROL 0x8185U +#define VIDEO_GET_CUR_EU_RATE_CONTROL_MODE_CONTROL 0x8186U +#define VIDEO_GET_CUR_EU_AVERAGE_BITRATE_CONTROL 0x8187U +#define VIDEO_GET_CUR_EU_CPB_SIZE_CONTROL 0x8188U +#define VIDEO_GET_CUR_EU_PEAK_BIT_RATE_CONTROL 0x8189U +#define VIDEO_GET_CUR_EU_QUANTIZATION_PARAMS_CONTROL 0x818AU +#define VIDEO_GET_CUR_EU_SYNC_REF_FRAME_CONTROL 0x818BU +#define VIDEO_GET_CUR_EU_LTR_BUFFER_CONTROL 0x818CU +#define VIDEO_GET_CUR_EU_LTR_PICTURE_CONTROL 0x818DU +#define VIDEO_GET_CUR_EU_LTR_VALIDATION_CONTROL 0x818EU +#define VIDEO_GET_CUR_EU_LEVEL_IDC_LIMIT_CONTROL 0x818FU +#define VIDEO_GET_CUR_EU_SEI_PAYLOADTYPE_CONTROL 0x8190U +#define VIDEO_GET_CUR_EU_QP_RANGE_CONTROL 0x8191U +#define VIDEO_GET_CUR_EU_PRIORITY_CONTROL 0x8192U +#define VIDEO_GET_CUR_EU_START_OR_STOP_LAYER_CONTROL 0x8193U +#define VIDEO_GET_CUR_EU_ERROR_RESILIENCY_CONTROL 0x8194U +#endif + +/*! @brief Video device class-specific request GET MIN COMMAND */ +#define VIDEO_GET_MIN_PU_BACKLIGHT_COMPENSATION_CONTROL 0x8221U +#define VIDEO_GET_MIN_PU_BRIGHTNESS_CONTROL 0x8222U +#define VIDEO_GET_MIN_PU_CONTRACT_CONTROL 0x8223U +#define VIDEO_GET_MIN_PU_GAIN_CONTROL 0x8224U +#define VIDEO_GET_MIN_PU_HUE_CONTROL 0x8226U +#define VIDEO_GET_MIN_PU_SATURATION_CONTROL 0x8227U +#define VIDEO_GET_MIN_PU_SHARRNESS_CONTROL 0x8228U +#define VIDEO_GET_MIN_PU_GAMMA_CONTROL 0x8229U +#define VIDEO_GET_MIN_PU_WHITE_BALANCE_TEMPERATURE_CONTROL 0x822AU +#define VIDEO_GET_MIN_PU_WHITE_BALANCE_COMPONENT_CONTROL 0x822CU +#define VIDEO_GET_MIN_PU_DIGITAL_MULTIPLIER_CONTROL 0x822EU +#define VIDEO_GET_MIN_PU_DIGITAL_MULTIPLIER_LIMIT_CONTROL 0x822FU + +#define VIDEO_GET_MIN_CT_EXPOSURE_TIME_ABSOLUTE_CONTROL 0x8244U +#define VIDEO_GET_MIN_CT_FOCUS_ABSOLUTE_CONTROL 0x8246U +#define VIDEO_GET_MIN_CT_FOCUS_RELATIVE_CONTROL 0x8247U +#define VIDEO_GET_MIN_CT_IRIS_ABSOLUTE_CONTROL 0x8249U +#define VIDEO_GET_MIN_CT_ZOOM_ABSOLUTE_CONTROL 0x824BU +#define VIDEO_GET_MIN_CT_ZOOM_RELATIVE_CONTROL 0x824CU +#define VIDEO_GET_MIN_CT_PANTILT_ABSOLUTE_CONTROL 0x824DU +#define VIDEO_GET_MIN_CT_PANTILT_RELATIVE_CONTROL 0x824EU +#define VIDEO_GET_MIN_CT_ROLL_ABSOLUTE_CONTROL 0x824FU +#define VIDEO_GET_MIN_CT_ROLL_RELATIVE_CONTROL 0x8250U +#if defined(USB_DEVICE_VIDEO_CLASS_VERSION_1_5) && USB_DEVICE_VIDEO_CLASS_VERSION_1_5 +#define VIDEO_GET_MIN_CT_DIGITAL_WINDOW_CONTROL 0x8251U +#define VIDEO_GET_MIN_CT_REGION_OF_INTEREST_CONTROL 0x8252U +#endif + +#define VIDEO_GET_MIN_VS_PROBE_CONTROL 0x8261U +#define VIDEO_GET_MIN_VS_STILL_PROBE_CONTROL 0x8263U +#define VIDEO_GET_MIN_VS_UPDATE_FRAME_SEGMENT_CONTROL 0x8268U +#define VIDEO_GET_MIN_VS_SYNCH_DELAY_CONTROL 0x8269U + +#if defined(USB_DEVICE_VIDEO_CLASS_VERSION_1_5) && USB_DEVICE_VIDEO_CLASS_VERSION_1_5 +#define VIDEO_GET_MIN_EU_VIDEO_RESOLUTION_CONTROL 0x8283U +#define VIDEO_GET_MIN_EU_MIN_FRAME_INTERVAL_CONTROL 0x8284U +#define VIDEO_GET_MIN_EU_SLICE_MODE_CONTROL 0x8285U +#define VIDEO_GET_MIN_EU_AVERAGE_BITRATE_CONTROL 0x8287U +#define VIDEO_GET_MIN_EU_CPB_SIZE_CONTROL 0x8288U +#define VIDEO_GET_MIN_EU_PEAK_BIT_RATE_CONTROL 0x8289U +#define VIDEO_GET_MIN_EU_QUANTIZATION_PARAMS_CONTROL 0x828AU +#define VIDEO_GET_MIN_EU_SYNC_REF_FRAME_CONTROL 0x828BU +#define VIDEO_GET_MIN_EU_LEVEL_IDC_LIMIT_CONTROL 0x828FU +#define VIDEO_GET_MIN_EU_SEI_PAYLOADTYPE_CONTROL 0x8290U +#define VIDEO_GET_MIN_EU_QP_RANGE_CONTROL 0x8291U +#endif + +/*! @brief Video device class-specific request GET MAX COMMAND */ +#define VIDEO_GET_MAX_PU_BACKLIGHT_COMPENSATION_CONTROL 0x8321U +#define VIDEO_GET_MAX_PU_BRIGHTNESS_CONTROL 0x8322U +#define VIDEO_GET_MAX_PU_CONTRACT_CONTROL 0x8323U +#define VIDEO_GET_MAX_PU_GAIN_CONTROL 0x8324U +#define VIDEO_GET_MAX_PU_HUE_CONTROL 0x8326U +#define VIDEO_GET_MAX_PU_SATURATION_CONTROL 0x8327U +#define VIDEO_GET_MAX_PU_SHARRNESS_CONTROL 0x8328U +#define VIDEO_GET_MAX_PU_GAMMA_CONTROL 0x8329U +#define VIDEO_GET_MAX_PU_WHITE_BALANCE_TEMPERATURE_CONTROL 0x832AU +#define VIDEO_GET_MAX_PU_WHITE_BALANCE_COMPONENT_CONTROL 0x832CU +#define VIDEO_GET_MAX_PU_DIGITAL_MULTIPLIER_CONTROL 0x832EU +#define VIDEO_GET_MAX_PU_DIGITAL_MULTIPLIER_LIMIT_CONTROL 0x832FU + +#define VIDEO_GET_MAX_CT_EXPOSURE_TIME_ABSOLUTE_CONTROL 0x8344U +#define VIDEO_GET_MAX_CT_FOCUS_ABSOLUTE_CONTROL 0x8346U +#define VIDEO_GET_MAX_CT_FOCUS_RELATIVE_CONTROL 0x8347U +#define VIDEO_GET_MAX_CT_IRIS_ABSOLUTE_CONTROL 0x8349U +#define VIDEO_GET_MAX_CT_ZOOM_ABSOLUTE_CONTROL 0x834BU +#define VIDEO_GET_MAX_CT_ZOOM_RELATIVE_CONTROL 0x834CU +#define VIDEO_GET_MAX_CT_PANTILT_ABSOLUTE_CONTROL 0x834DU +#define VIDEO_GET_MAX_CT_PANTILT_RELATIVE_CONTROL 0x834EU +#define VIDEO_GET_MAX_CT_ROLL_ABSOLUTE_CONTROL 0x834FU +#define VIDEO_GET_MAX_CT_ROLL_RELATIVE_CONTROL 0x8350U +#if defined(USB_DEVICE_VIDEO_CLASS_VERSION_1_5) && USB_DEVICE_VIDEO_CLASS_VERSION_1_5 +#define VIDEO_GET_MAX_CT_DIGITAL_WINDOW_CONTROL 0x8351U +#define VIDEO_GET_MAX_CT_REGION_OF_INTEREST_CONTROL 0x8352U +#endif + +#define VIDEO_GET_MAX_VS_PROBE_CONTROL 0x8361U +#define VIDEO_GET_MAX_VS_STILL_PROBE_CONTROL 0x8363U +#define VIDEO_GET_MAX_VS_UPDATE_FRAME_SEGMENT_CONTROL 0x8368U +#define VIDEO_GET_MAX_VS_SYNCH_DELAY_CONTROL 0x8369U + +#if defined(USB_DEVICE_VIDEO_CLASS_VERSION_1_5) && USB_DEVICE_VIDEO_CLASS_VERSION_1_5 +#define VIDEO_GET_MAX_EU_VIDEO_RESOLUTION_CONTROL 0x8383U +#define VIDEO_GET_MAX_EU_MIN_FRAME_INTERVAL_CONTROL 0x8384U +#define VIDEO_GET_MAX_EU_SLICE_MODE_CONTROL 0x8385U +#define VIDEO_GET_MAX_EU_AVERAGE_BITRATE_CONTROL 0x8387U +#define VIDEO_GET_MAX_EU_CPB_SIZE_CONTROL 0x8388U +#define VIDEO_GET_MAX_EU_PEAK_BIT_RATE_CONTROL 0x8389U +#define VIDEO_GET_MAX_EU_QUANTIZATION_PARAMS_CONTROL 0x838AU +#define VIDEO_GET_MAX_EU_SYNC_REF_FRAME_CONTROL 0x838BU +#define VIDEO_GET_MAX_EU_LTR_BUFFER_CONTROL 0x838CU +#define VIDEO_GET_MAX_EU_LEVEL_IDC_LIMIT_CONTROL 0x838FU +#define VIDEO_GET_MAX_EU_SEI_PAYLOADTYPE_CONTROL 0x8390U +#define VIDEO_GET_MAX_EU_QP_RANGE_CONTROL 0x8391U +#endif + +/*! @brief Video device class-specific request GET RES COMMAND */ +#define VIDEO_GET_RES_PU_BACKLIGHT_COMPENSATION_CONTROL 0x8421U +#define VIDEO_GET_RES_PU_BRIGHTNESS_CONTROL 0x8422U +#define VIDEO_GET_RES_PU_CONTRACT_CONTROL 0x8423U +#define VIDEO_GET_RES_PU_GAIN_CONTROL 0x8424U +#define VIDEO_GET_RES_PU_HUE_CONTROL 0x8426U +#define VIDEO_GET_RES_PU_SATURATION_CONTROL 0x8427U +#define VIDEO_GET_RES_PU_SHARRNESS_CONTROL 0x8428U +#define VIDEO_GET_RES_PU_GAMMA_CONTROL 0x8429U +#define VIDEO_GET_RES_PU_WHITE_BALANCE_TEMPERATURE_CONTROL 0x842AU +#define VIDEO_GET_RES_PU_WHITE_BALANCE_COMPONENT_CONTROL 0x842CU +#define VIDEO_GET_RES_PU_DIGITAL_MULTIPLIER_CONTROL 0x842EU +#define VIDEO_GET_RES_PU_DIGITAL_MULTIPLIER_LIMIT_CONTROL 0x842FU + +#define VIDEO_GET_RES_CT_AE_MODE_CONTROL 0x8442U +#define VIDEO_GET_RES_CT_EXPOSURE_TIME_ABSOLUTE_CONTROL 0x8444U +#define VIDEO_GET_RES_CT_FOCUS_ABSOLUTE_CONTROL 0x8446U +#define VIDEO_GET_RES_CT_FOCUS_RELATIVE_CONTROL 0x8447U +#define VIDEO_GET_RES_CT_IRIS_ABSOLUTE_CONTROL 0x8449U +#define VIDEO_GET_RES_CT_ZOOM_ABSOLUTE_CONTROL 0x844BU +#define VIDEO_GET_RES_CT_ZOOM_RELATIVE_CONTROL 0x844CU +#define VIDEO_GET_RES_CT_PANTILT_ABSOLUTE_CONTROL 0x844DU +#define VIDEO_GET_RES_CT_PANTILT_RELATIVE_CONTROL 0x844EU +#define VIDEO_GET_RES_CT_ROLL_ABSOLUTE_CONTROL 0x844FU +#define VIDEO_GET_RES_CT_ROLL_RELATIVE_CONTROL 0x8450U + +#define VIDEO_GET_RES_VS_PROBE_CONTROL 0x8461U +#define VIDEO_GET_RES_VS_STILL_PROBE_CONTROL 0x8463U +#define VIDEO_GET_RES_VS_UPDATE_FRAME_SEGMENT_CONTROL 0x8468U +#define VIDEO_GET_RES_VS_SYNCH_DELAY_CONTROL 0x8469U + +#if defined(USB_DEVICE_VIDEO_CLASS_VERSION_1_5) && USB_DEVICE_VIDEO_CLASS_VERSION_1_5 +#define VIDEO_GET_RES_EU_AVERAGE_BITRATE_CONTROL 0x8487U +#define VIDEO_GET_RES_EU_CPB_SIZE_CONTROL 0x8488U +#define VIDEO_GET_RES_EU_PEAK_BIT_RATE_CONTROL 0x8489U +#define VIDEO_GET_RES_EU_QUANTIZATION_PARAMS_CONTROL 0x848AU +#define VIDEO_GET_RES_EU_ERROR_RESILIENCY_CONTROL 0x8494U +#endif + +/*! @brief Video device class-specific request GET LEN COMMAND */ + +#define VIDEO_GET_LEN_VS_PROBE_CONTROL 0x8561U +#define VIDEO_GET_LEN_VS_COMMIT_CONTROL 0x8562U +#define VIDEO_GET_LEN_VS_STILL_PROBE_CONTROL 0x8563U +#define VIDEO_GET_LEN_VS_STILL_COMMIT_CONTROL 0x8564U + +#if defined(USB_DEVICE_VIDEO_CLASS_VERSION_1_5) && USB_DEVICE_VIDEO_CLASS_VERSION_1_5 +#define VIDEO_GET_LEN_EU_SELECT_LAYER_CONTROL 0x8581U +#define VIDEO_GET_LEN_EU_PROFILE_TOOLSET_CONTROL 0x8582U +#define VIDEO_GET_LEN_EU_VIDEO_RESOLUTION_CONTROL 0x8583U +#define VIDEO_GET_LEN_EU_MIN_FRAME_INTERVAL_CONTROL 0x8584U +#define VIDEO_GET_LEN_EU_SLICE_MODE_CONTROL 0x8585U +#define VIDEO_GET_LEN_EU_RATE_CONTROL_MODE_CONTROL 0x8586U +#define VIDEO_GET_LEN_EU_AVERAGE_BITRATE_CONTROL 0x8587U +#define VIDEO_GET_LEN_EU_CPB_SIZE_CONTROL 0x8588U +#define VIDEO_GET_LEN_EU_PEAK_BIT_RATE_CONTROL 0x8589U +#define VIDEO_GET_LEN_EU_QUANTIZATION_PARAMS_CONTROL 0x858AU +#define VIDEO_GET_LEN_EU_SYNC_REF_FRAME_CONTROL 0x858BU +#define VIDEO_GET_LEN_EU_LTR_BUFFER_CONTROL 0x858CU +#define VIDEO_GET_LEN_EU_LTR_PICTURE_CONTROL 0x858DU +#define VIDEO_GET_LEN_EU_LTR_VALIDATION_CONTROL 0x858EU +#define VIDEO_GET_LEN_EU_QP_RANGE_CONTROL 0x8591U +#define VIDEO_GET_LEN_EU_PRIORITY_CONTROL 0x8592U +#define VIDEO_GET_LEN_EU_START_OR_STOP_LAYER_CONTROL 0x8593U +#endif + +/*! @brief Video device class-specific request GET INFO COMMAND */ +#define VIDEO_GET_INFO_VC_POWER_MODE_CONTROL 0x8601U +#define VIDEO_GET_INFO_VC_ERROR_CODE_CONTROL 0x8602U + +#define VIDEO_GET_INFO_PU_BACKLIGHT_COMPENSATION_CONTROL 0x8621U +#define VIDEO_GET_INFO_PU_BRIGHTNESS_CONTROL 0x8622U +#define VIDEO_GET_INFO_PU_CONTRACT_CONTROL 0x8623U +#define VIDEO_GET_INFO_PU_GAIN_CONTROL 0x8624U +#define VIDEO_GET_INFO_PU_POWER_LINE_FREQUENCY_CONTROL 0x8625U +#define VIDEO_GET_INFO_PU_HUE_CONTROL 0x8626U +#define VIDEO_GET_INFO_PU_SATURATION_CONTROL 0x8627U +#define VIDEO_GET_INFO_PU_SHARRNESS_CONTROL 0x8628U +#define VIDEO_GET_INFO_PU_GAMMA_CONTROL 0x8629U +#define VIDEO_GET_INFO_PU_WHITE_BALANCE_TEMPERATURE_CONTROL 0x862AU +#define VIDEO_GET_INFO_PU_WHITE_BALANCE_TEMPERATURE_AUTO_CONTROL 0x862BU +#define VIDEO_GET_INFO_PU_WHITE_BALANCE_COMPONENT_CONTROL 0x862CU +#define VIDEO_GET_INFO_PU_WHITE_BALANCE_COMPONENT_AUTO_CONTROL 0x862DU +#define VIDEO_GET_INFO_PU_DIGITAL_MULTIPLIER_CONTROL 0x862EU +#define VIDEO_GET_INFO_PU_DIGITAL_MULTIPLIER_LIMIT_CONTROL 0x862FU +#define VIDEO_GET_INFO_PU_HUE_AUTO_CONTROL 0x8630U +#define VIDEO_GET_INFO_PU_ANALOG_VIDEO_STANDARD_CONTROL 0x8631U +#define VIDEO_GET_INFO_PU_ANALOG_LOCK_STATUS_CONTROL 0x8632U +#if defined(USB_DEVICE_VIDEO_CLASS_VERSION_1_5) && USB_DEVICE_VIDEO_CLASS_VERSION_1_5 +#define VIDEO_GET_INFO_PU_CONTRAST_AUTO_CONTROL 0x8633U +#endif + +#define VIDEO_GET_INFO_CT_SCANNING_MODE_CONTROL 0x8641U +#define VIDEO_GET_INFO_CT_AE_MODE_CONTROL 0x8642U +#define VIDEO_GET_INFO_CT_AE_PRIORITY_CONTROL 0x8643U +#define VIDEO_GET_INFO_CT_EXPOSURE_TIME_ABSOLUTE_CONTROL 0x8644U +#define VIDEO_GET_INFO_CT_EXPOSURE_TIME_RELATIVE_CONTROL 0x8645U +#define VIDEO_GET_INFO_CT_FOCUS_ABSOLUTE_CONTROL 0x8646U +#define VIDEO_GET_INFO_CT_FOCUS_RELATIVE_CONTROL 0x8647U +#define VIDEO_GET_INFO_CT_FOCUS_AUTO_CONTROL 0x8648U +#define VIDEO_GET_INFO_CT_IRIS_ABSOLUTE_CONTROL 0x8649U +#define VIDEO_GET_INFO_CT_IRIS_RELATIVE_CONTROL 0x864AU +#define VIDEO_GET_INFO_CT_ZOOM_ABSOLUTE_CONTROL 0x864BU +#define VIDEO_GET_INFO_CT_ZOOM_RELATIVE_CONTROL 0x864CU +#define VIDEO_GET_INFO_CT_PANTILT_ABSOLUTE_CONTROL 0x864DU +#define VIDEO_GET_INFO_CT_PANTILT_RELATIVE_CONTROL 0x864EU +#define VIDEO_GET_INFO_CT_ROLL_ABSOLUTE_CONTROL 0x864FU +#define VIDEO_GET_INFO_CT_ROLL_RELATIVE_CONTROL 0x8650U +#define VIDEO_GET_INFO_CT_PRIVACY_CONTROL 0x8651U +#if defined(USB_DEVICE_VIDEO_CLASS_VERSION_1_5) && USB_DEVICE_VIDEO_CLASS_VERSION_1_5 +#define VIDEO_GET_INFO_CT_FOCUS_SIMPLE_CONTROL 0x8652U +#endif + +#define VIDEO_GET_INFO_VS_PROBE_CONTROL 0x8661U +#define VIDEO_GET_INFO_VS_COMMIT_CONTROL 0x8662U +#define VIDEO_GET_INFO_VS_STILL_PROBE_CONTROL 0x8663U +#define VIDEO_GET_INFO_VS_STILL_COMMIT_CONTROL 0x8664U +#define VIDEO_GET_INFO_VS_STILL_IMAGE_TRIGGER_CONTROL 0x8665U +#define VIDEO_GET_INFO_VS_STREAM_ERROR_CODE_CONTROL 0x8666U +#define VIDEO_GET_INFO_VS_GENERATE_KEY_FRAME_CONTROL 0x8667U +#define VIDEO_GET_INFO_VS_UPDATE_FRAME_SEGMENT_CONTROL 0x8668U +#define VIDEO_GET_INFO_VS_SYNCH_DELAY_CONTROL 0x8669U + +#if defined(USB_DEVICE_VIDEO_CLASS_VERSION_1_5) && USB_DEVICE_VIDEO_CLASS_VERSION_1_5 +#define VIDEO_GET_INFO_EU_SELECT_LAYER_CONTROL 0x8681U +#define VIDEO_GET_INFO_EU_PROFILE_TOOLSET_CONTROL 0x8682U +#define VIDEO_GET_INFO_EU_VIDEO_RESOLUTION_CONTROL 0x8683U +#define VIDEO_GET_INFO_EU_MIN_FRAME_INTERVAL_CONTROL 0x8684U +#define VIDEO_GET_INFO_EU_SLICE_MODE_CONTROL 0x8685U +#define VIDEO_GET_INFO_EU_RATE_CONTROL_MODE_CONTROL 0x8686U +#define VIDEO_GET_INFO_EU_AVERAGE_BITRATE_CONTROL 0x8687U +#define VIDEO_GET_INFO_EU_CPB_SIZE_CONTROL 0x8688U +#define VIDEO_GET_INFO_EU_PEAK_BIT_RATE_CONTROL 0x8689U +#define VIDEO_GET_INFO_EU_QUANTIZATION_PARAMS_CONTROL 0x868AU +#define VIDEO_GET_INFO_EU_SYNC_REF_FRAME_CONTROL 0x868BU +#define VIDEO_GET_INFO_EU_LTR_BUFFER_CONTROL 0x868CU +#define VIDEO_GET_INFO_EU_LTR_PICTURE_CONTROL 0x868DU +#define VIDEO_GET_INFO_EU_LTR_VALIDATION_CONTROL 0x868EU +#define VIDEO_GET_INFO_EU_SEI_PAYLOADTYPE_CONTROL 0x8690U +#define VIDEO_GET_INFO_EU_QP_RANGE_CONTROL 0x8691U +#define VIDEO_GET_INFO_EU_PRIORITY_CONTROL 0x8692U +#define VIDEO_GET_INFO_EU_START_OR_STOP_LAYER_CONTROL 0x8693U +#endif + +/*! @brief Video device class-specific request GET DEF COMMAND */ +#define VIDEO_GET_DEF_PU_BACKLIGHT_COMPENSATION_CONTROL 0x8721U +#define VIDEO_GET_DEF_PU_BRIGHTNESS_CONTROL 0x8722U +#define VIDEO_GET_DEF_PU_CONTRACT_CONTROL 0x8723U +#define VIDEO_GET_DEF_PU_GAIN_CONTROL 0x8724U +#define VIDEO_GET_DEF_PU_POWER_LINE_FREQUENCY_CONTROL 0x8725U +#define VIDEO_GET_DEF_PU_HUE_CONTROL 0x8726U +#define VIDEO_GET_DEF_PU_SATURATION_CONTROL 0x8727U +#define VIDEO_GET_DEF_PU_SHARRNESS_CONTROL 0x8728U +#define VIDEO_GET_DEF_PU_GAMMA_CONTROL 0x8729U +#define VIDEO_GET_DEF_PU_WHITE_BALANCE_TEMPERATURE_CONTROL 0x872AU +#define VIDEO_GET_DEF_PU_WHITE_BALANCE_TEMPERATURE_AUTO_CONTROL 0x872BU +#define VIDEO_GET_DEF_PU_WHITE_BALANCE_COMPONENT_CONTROL 0x872CU +#define VIDEO_GET_DEF_PU_WHITE_BALANCE_COMPONENT_AUTO_CONTROL 0x872DU +#define VIDEO_GET_DEF_PU_DIGITAL_MULTIPLIER_CONTROL 0x872EU +#define VIDEO_GET_DEF_PU_DIGITAL_MULTIPLIER_LIMIT_CONTROL 0x872FU +#define VIDEO_GET_DEF_PU_HUE_AUTO_CONTROL 0x8730U +#if defined(USB_DEVICE_VIDEO_CLASS_VERSION_1_5) && USB_DEVICE_VIDEO_CLASS_VERSION_1_5 +#define VIDEO_GET_DEF_PU_CONTRAST_AUTO_CONTROL 0x8731U +#endif + +#define VIDEO_GET_DEF_CT_AE_MODE_CONTROL 0x8742U +#define VIDEO_GET_DEF_CT_EXPOSURE_TIME_ABSOLUTE_CONTROL 0x8744U +#define VIDEO_GET_DEF_CT_FOCUS_ABSOLUTE_CONTROL 0x8746U +#define VIDEO_GET_DEF_CT_FOCUS_RELATIVE_CONTROL 0x8747U +#define VIDEO_GET_DEF_CT_FOCUS_AUTO_CONTROL 0x8748U +#define VIDEO_GET_DEF_CT_IRIS_ABSOLUTE_CONTROL 0x8749U +#define VIDEO_GET_DEF_CT_ZOOM_ABSOLUTE_CONTROL 0x874BU +#define VIDEO_GET_DEF_CT_ZOOM_RELATIVE_CONTROL 0x874CU +#define VIDEO_GET_DEF_CT_PANTILT_ABSOLUTE_CONTROL 0x874DU +#define VIDEO_GET_DEF_CT_PANTILT_RELATIVE_CONTROL 0x874EU +#define VIDEO_GET_DEF_CT_ROLL_ABSOLUTE_CONTROL 0x874FU +#define VIDEO_GET_DEF_CT_ROLL_RELATIVE_CONTROL 0x8750U +#if defined(USB_DEVICE_VIDEO_CLASS_VERSION_1_5) && USB_DEVICE_VIDEO_CLASS_VERSION_1_5 +#define VIDEO_GET_DEF_CT_FOCUS_SIMPLE_CONTROL 0x8751U +#define VIDEO_GET_DEF_CT_DIGITAL_WINDOW_CONTROL 0x8752U +#define VIDEO_GET_DEF_CT_REGION_OF_INTEREST_CONTROL 0x8753U +#endif + +#define VIDEO_GET_DEF_VS_PROBE_CONTROL 0x8761U +#define VIDEO_GET_DEF_VS_STILL_PROBE_CONTROL 0x8763U +#define VIDEO_GET_DEF_VS_UPDATE_FRAME_SEGMENT_CONTROL 0x8768U +#define VIDEO_GET_DEF_VS_SYNCH_DELAY_CONTROL 0x8769U + +#if defined(USB_DEVICE_VIDEO_CLASS_VERSION_1_5) && USB_DEVICE_VIDEO_CLASS_VERSION_1_5 +#define VIDEO_GET_DEF_EU_PROFILE_TOOLSET_CONTROL 0x8782U +#define VIDEO_GET_DEF_EU_VIDEO_RESOLUTION_CONTROL 0x8783U +#define VIDEO_GET_DEF_EU_MIN_FRAME_INTERVAL_CONTROL 0x8784U +#define VIDEO_GET_DEF_EU_SLICE_MODE_CONTROL 0x8785U +#define VIDEO_GET_DEF_EU_RATE_CONTROL_MODE_CONTROL 0x8786U +#define VIDEO_GET_DEF_EU_AVERAGE_BITRATE_CONTROL 0x8787U +#define VIDEO_GET_DEF_EU_CPB_SIZE_CONTROL 0x8788U +#define VIDEO_GET_DEF_EU_PEAK_BIT_RATE_CONTROL 0x8789U +#define VIDEO_GET_DEF_EU_QUANTIZATION_PARAMS_CONTROL 0x878AU +#define VIDEO_GET_DEF_EU_LTR_BUFFER_CONTROL 0x878CU +#define VIDEO_GET_DEF_EU_LTR_PICTURE_CONTROL 0x878DU +#define VIDEO_GET_DEF_EU_LTR_VALIDATION_CONTROL 0x878EU +#define VIDEO_GET_DEF_EU_LEVEL_IDC_LIMIT_CONTROL 0x878FU +#define VIDEO_GET_DEF_EU_SEI_PAYLOADTYPE_CONTROL 0x8790U +#define VIDEO_GET_DEF_EU_QP_RANGE_CONTROL 0x8791U +#define VIDEO_GET_DEF_EU_ERROR_RESILIENCY_CONTROL 0x8794U +#endif + +/*! @brief Video device class-specific request SET CUR COMMAND */ +#define VIDEO_SET_CUR_VC_POWER_MODE_CONTROL 0x0101U + +#define VIDEO_SET_CUR_PU_BACKLIGHT_COMPENSATION_CONTROL 0x0121U +#define VIDEO_SET_CUR_PU_BRIGHTNESS_CONTROL 0x0122U +#define VIDEO_SET_CUR_PU_CONTRACT_CONTROL 0x0123U +#define VIDEO_SET_CUR_PU_GAIN_CONTROL 0x0124U +#define VIDEO_SET_CUR_PU_POWER_LINE_FREQUENCY_CONTROL 0x0125U +#define VIDEO_SET_CUR_PU_HUE_CONTROL 0x0126U +#define VIDEO_SET_CUR_PU_SATURATION_CONTROL 0x0127U +#define VIDEO_SET_CUR_PU_SHARRNESS_CONTROL 0x0128U +#define VIDEO_SET_CUR_PU_GAMMA_CONTROL 0x0129U +#define VIDEO_SET_CUR_PU_WHITE_BALANCE_TEMPERATURE_CONTROL 0x012AU +#define VIDEO_SET_CUR_PU_WHITE_BALANCE_TEMPERATURE_AUTO_CONTROL 0x012BU +#define VIDEO_SET_CUR_PU_WHITE_BALANCE_COMPONENT_CONTROL 0x012CU +#define VIDEO_SET_CUR_PU_WHITE_BALANCE_COMPONENT_AUTO_CONTROL 0x012DU +#define VIDEO_SET_CUR_PU_DIGITAL_MULTIPLIER_CONTROL 0x012EU +#define VIDEO_SET_CUR_PU_DIGITAL_MULTIPLIER_LIMIT_CONTROL 0x012FU +#define VIDEO_SET_CUR_PU_HUE_AUTO_CONTROL 0x0130U +#if defined(USB_DEVICE_VIDEO_CLASS_VERSION_1_5) && USB_DEVICE_VIDEO_CLASS_VERSION_1_5 +#define VIDEO_SET_CUR_PU_CONTRAST_AUTO_CONTROL 0x0131U +#endif + +#define VIDEO_SET_CUR_CT_SCANNING_MODE_CONTROL 0x0141U +#define VIDEO_SET_CUR_CT_AE_MODE_CONTROL 0x0142U +#define VIDEO_SET_CUR_CT_AE_PRIORITY_CONTROL 0x0143U +#define VIDEO_SET_CUR_CT_EXPOSURE_TIME_ABSOLUTE_CONTROL 0x0144U +#define VIDEO_SET_CUR_CT_EXPOSURE_TIME_RELATIVE_CONTROL 0x0145U +#define VIDEO_SET_CUR_CT_FOCUS_ABSOLUTE_CONTROL 0x0146U +#define VIDEO_SET_CUR_CT_FOCUS_RELATIVE_CONTROL 0x0147U +#define VIDEO_SET_CUR_CT_FOCUS_AUTO_CONTROL 0x0148U +#define VIDEO_SET_CUR_CT_IRIS_ABSOLUTE_CONTROL 0x0149U +#define VIDEO_SET_CUR_CT_IRIS_RELATIVE_CONTROL 0x014AU +#define VIDEO_SET_CUR_CT_ZOOM_ABSOLUTE_CONTROL 0x014BU +#define VIDEO_SET_CUR_CT_ZOOM_RELATIVE_CONTROL 0x014CU +#define VIDEO_SET_CUR_CT_PANTILT_ABSOLUTE_CONTROL 0x014DU +#define VIDEO_SET_CUR_CT_PANTILT_RELATIVE_CONTROL 0x014EU +#define VIDEO_SET_CUR_CT_ROLL_ABSOLUTE_CONTROL 0x014FU +#define VIDEO_SET_CUR_CT_ROLL_RELATIVE_CONTROL 0x0150U +#define VIDEO_SET_CUR_CT_PRIVACY_CONTROL 0x0151U +#if defined(USB_DEVICE_VIDEO_CLASS_VERSION_1_5) && USB_DEVICE_VIDEO_CLASS_VERSION_1_5 +#define VIDEO_SET_CUR_CT_FOCUS_SIMPLE_CONTROL 0x0152U +#define VIDEO_SET_CUR_CT_DIGITAL_WINDOW_CONTROL 0x0153U +#define VIDEO_SET_CUR_CT_REGION_OF_INTEREST_CONTROL 0x0154U +#endif + +#define VIDEO_SET_CUR_VS_PROBE_CONTROL 0x0161U +#define VIDEO_SET_CUR_VS_COMMIT_CONTROL 0x0162U +#define VIDEO_SET_CUR_VS_STILL_PROBE_CONTROL 0x0163U +#define VIDEO_SET_CUR_VS_STILL_COMMIT_CONTROL 0x0164U +#define VIDEO_SET_CUR_VS_STILL_IMAGE_TRIGGER_CONTROL 0x0165U +#define VIDEO_SET_CUR_VS_STREAM_ERROR_CODE_CONTROL 0x0166U +#define VIDEO_SET_CUR_VS_GENERATE_KEY_FRAME_CONTROL 0x0167U +#define VIDEO_SET_CUR_VS_UPDATE_FRAME_SEGMENT_CONTROL 0x0168U +#define VIDEO_SET_CUR_VS_SYNCH_DELAY_CONTROL 0x0169U + +#if defined(USB_DEVICE_VIDEO_CLASS_VERSION_1_5) && USB_DEVICE_VIDEO_CLASS_VERSION_1_5 +#define VIDEO_SET_CUR_EU_SELECT_LAYER_CONTROL 0x0181U +#define VIDEO_SET_CUR_EU_PROFILE_TOOLSET_CONTROL 0x0182U +#define VIDEO_SET_CUR_EU_VIDEO_RESOLUTION_CONTROL 0x0183U +#define VIDEO_SET_CUR_EU_MIN_FRAME_INTERVAL_CONTROL 0x0184U +#define VIDEO_SET_CUR_EU_SLICE_MODE_CONTROL 0x0185U +#define VIDEO_SET_CUR_EU_RATE_CONTROL_MODE_CONTROL 0x0186U +#define VIDEO_SET_CUR_EU_AVERAGE_BITRATE_CONTROL 0x0187U +#define VIDEO_SET_CUR_EU_CPB_SIZE_CONTROL 0x0188U +#define VIDEO_SET_CUR_EU_PEAK_BIT_RATE_CONTROL 0x0189U +#define VIDEO_SET_CUR_EU_QUANTIZATION_PARAMS_CONTROL 0x018AU +#define VIDEO_SET_CUR_EU_SYNC_REF_FRAME_CONTROL 0x018BU +#define VIDEO_SET_CUR_EU_LTR_BUFFER_CONTROL 0x018CU +#define VIDEO_SET_CUR_EU_LTR_PICTURE_CONTROL 0x018DU +#define VIDEO_SET_CUR_EU_LTR_VALIDATION_CONTROL 0x018EU +#define VIDEO_SET_CUR_EU_LEVEL_IDC_LIMIT_CONTROL 0x018FU +#define VIDEO_SET_CUR_EU_SEI_PAYLOADTYPE_CONTROL 0x0190U +#define VIDEO_SET_CUR_EU_QP_RANGE_CONTROL 0x0191U +#define VIDEO_SET_CUR_EU_PRIORITY_CONTROL 0x0192U +#define VIDEO_SET_CUR_EU_START_OR_STOP_LAYER_CONTROL 0x0193U +#define VIDEO_SET_CUR_EU_ERROR_RESILIENCY_CONTROL 0x0194U +#endif + +/*! @brief The payload header structure. */ +struct video_payload_header { + uint8_t bHeaderLength; /*!< The payload header length. */ + union { + uint8_t bmheaderInfo; /*!< The payload header bitmap field. */ + struct + { + uint8_t frameIdentifier : 1U; /*!< Frame Identifier. This bit toggles at each frame start boundary and stays + constant for the rest of the frame.*/ + uint8_t endOfFrame : 1U; /*!< End of Frame. This bit indicates the end of a video frame and is set in the + last video sample that belongs to a frame.*/ + uint8_t + presentationTimeStamp : 1U; /*!< Presentation Time Stamp. This bit, when set, indicates the presence of + a PTS field.*/ + uint8_t sourceClockReference : 1U; /*!< Source Clock Reference. This bit, when set, indicates the presence + of a SCR field.*/ + uint8_t reserved : 1U; /*!< Reserved. Set to 0. */ + uint8_t stillImage : 1U; /*!< Still Image. This bit, when set, identifies a video sample that belongs to a + still image.*/ + uint8_t errorBit : 1U; /*!< Error Bit. This bit, when set, indicates an error in the device streaming.*/ + uint8_t endOfHeader : 1U; /*!< End of Header. This bit, when set, indicates the end of the BFH fields.*/ + } headerInfoBits; + struct + { + uint8_t FID : 1U; /*!< Frame Identifier. This bit toggles at each frame start boundary and stays constant + for the rest of the frame.*/ + uint8_t EOI : 1U; /*!< End of Frame. This bit indicates the end of a video frame and is set in the last + video sample that belongs to a frame.*/ + uint8_t PTS : 1U; /*!< Presentation Time Stamp. This bit, when set, indicates the presence of a PTS field.*/ + uint8_t SCR : 1U; /*!< Source Clock Reference. This bit, when set, indicates the presence of a SCR field.*/ + uint8_t RES : 1U; /*!< Reserved. Set to 0. */ + uint8_t STI : 1U; /*!< Still Image. This bit, when set, identifies a video sample that belongs to a still + image.*/ + uint8_t ERR : 1U; /*!< Error Bit. This bit, when set, indicates an error in the device streaming.*/ + uint8_t EOH : 1U; /*!< End of Header. This bit, when set, indicates the end of the BFH fields.*/ + } headerInfoBitmap; + } headerInfoUnion; + uint32_t dwPresentationTime; /*!< Presentation time stamp (PTS) field.*/ + uint8_t bSourceClockReference[6]; /*!< Source clock reference (SCR) field.*/ +} __PACKED; + +/*! @brief The Video probe and commit controls structure.*/ +struct video_probe_and_commit_controls { + union { + uint8_t bmHint; /*!< Bit-field control indicating to the function what fields shall be kept fixed. */ + struct + { + uint8_t dwFrameInterval : 1U; /*!< dwFrameInterval field.*/ + uint8_t wKeyFrameRate : 1U; /*!< wKeyFrameRate field.*/ + uint8_t wPFrameRate : 1U; /*!< wPFrameRate field.*/ + uint8_t wCompQuality : 1U; /*!< wCompQuality field.*/ + uint8_t wCompWindowSize : 1U; /*!< wCompWindowSize field.*/ + uint8_t reserved : 3U; /*!< Reserved field.*/ + } hintBitmap; + } hintUnion; + union { + uint8_t bmHint; /*!< Bit-field control indicating to the function what fields shall be kept fixed. */ + struct + { + uint8_t reserved : 8U; /*!< Reserved field.*/ + } hintBitmap; + } hintUnion1; + uint8_t bFormatIndex; /*!< Video format index from a format descriptor.*/ + uint8_t bFrameIndex; /*!< Video frame index from a frame descriptor.*/ + uint32_t dwFrameInterval; /*!< Frame interval in 100ns units.*/ + uint16_t wKeyFrameRate; /*!< Key frame rate in key-frame per video-frame units.*/ + uint16_t wPFrameRate; /*!< PFrame rate in PFrame/key frame units.*/ + uint16_t wCompQuality; /*!< Compression quality control in abstract units 0U (lowest) to 10000U (highest).*/ + uint16_t wCompWindowSize; /*!< Window size for average bit rate control.*/ + uint16_t wDelay; /*!< Internal video streaming interface latency in ms from video data capture to presentation on + the USB.*/ + uint32_t dwMaxVideoFrameSize; /*!< Maximum video frame or codec-specific segment size in bytes.*/ + uint32_t dwMaxPayloadTransferSize; /*!< Specifies the maximum number of bytes that the device can transmit or + receive in a single payload transfer.*/ + uint32_t dwClockFrequency; /*!< The device clock frequency in Hz for the specified format. This specifies the + units used for the time information fields in the Video Payload Headers in the data + stream.*/ + uint8_t bmFramingInfo; /*!< Bit-field control supporting the following values: D0 Frame ID, D1 EOF.*/ + uint8_t bPreferedVersion; /*!< The preferred payload format version supported by the host or device for the + specified bFormatIndex value.*/ + uint8_t bMinVersion; /*!< The minimum payload format version supported by the device for the specified bFormatIndex + value.*/ + uint8_t bMaxVersion; /*!< The maximum payload format version supported by the device for the specified bFormatIndex + value.*/ +#if defined(USB_DEVICE_VIDEO_CLASS_VERSION_1_5) && USB_DEVICE_VIDEO_CLASS_VERSION_1_5 + uint8_t bUsage; /*!< This bitmap enables features reported by the bmUsages field of the Video Frame Descriptor.*/ + uint8_t + bBitDepthLuma; /*!< Represents bit_depth_luma_minus8 + 8U, which must be the same as bit_depth_chroma_minus8 + + 8.*/ + uint8_t bmSettings; /*!< A bitmap of flags that is used to discover and control specific features of a temporally + encoded video stream.*/ + uint8_t bMaxNumberOfRefFramesPlus1; /*!< Host indicates the maximum number of frames stored for use as references.*/ + uint16_t bmRateControlModes; /*!< This field contains 4U sub-fields, each of which is a 4U bit number.*/ + uint64_t bmLayoutPerStream; /*!< This field contains 4U sub-fields, each of which is a 2U byte number.*/ +#endif +} __PACKED; + +/*! @brief The Video still probe and still commit controls structure.*/ +struct video_still_probe_and_commit_controls { + uint8_t bFormatIndex; /*!< Video format index from a format descriptor.*/ + uint8_t bFrameIndex; /*!< Video frame index from a frame descriptor.*/ + uint8_t bCompressionIndex; /*!< Compression index from a frame descriptor.*/ + uint32_t dwMaxVideoFrameSize; /*!< Maximum still image size in bytes.*/ + uint32_t dwMaxPayloadTransferSize; /*!< Specifies the maximum number of bytes that the device can transmit or + receive in a single payload transfer.*/ +} __PACKED; + +struct video_cs_if_vc_header_descriptor { + uint8_t bLength; + uint8_t bDescriptorType; + uint8_t bDescriptorSubType; + uint16_t bcdUVC; + uint16_t wTotalLength; + uint32_t dwClockFrequency; + uint8_t bInCollection; + uint8_t baInterfaceNr[]; +} __PACKED; + +#define VIDEO_SIZEOF_VC_HEADER_DESC(n) (12 + n) + +struct video_cs_if_vc_input_terminal_descriptor { + uint8_t bLength; + uint8_t bDescriptorType; + uint8_t bDescriptorSubType; + uint8_t bTerminalID; + uint16_t wTerminalType; + uint8_t bAssocTerminal; + uint8_t iTerminal; + uint16_t wObjectiveFocalLenMin; + uint16_t wObjectiveFocalLenMax; + uint16_t wOcularFocalLength; + uint8_t bControlSize; + uint8_t bmaControls[]; +} __PACKED; + +#define VIDEO_SIZEOF_VC_INPUT_TERMINAL_DESC(n) (15 + n) + +struct video_cs_if_vc_processing_unit_descriptor { + uint8_t bLength; + uint8_t bDescriptorType; + uint8_t bDescriptorSubType; + uint8_t bUnitID; + uint8_t bSourceID; + uint16_t wMaxMultiplier; + uint8_t bControlSize; + // uint8_t bmaControls[]; + uint8_t iProcessing; + uint8_t bmVideoStandards; +} __PACKED; + +#define VIDEO_SIZEOF_VC_PROCESSING_UNIT_DESC(n) (10 + n) + +struct video_cs_if_vc_output_terminal_descriptor { + uint8_t bLength; + uint8_t bDescriptorType; + uint8_t bDescriptorSubType; + uint8_t bTerminalID; + uint16_t wTerminalType; + uint8_t bAssocTerminal; + uint8_t bSourceID; + uint8_t iTerminal; +} __PACKED; + +#define VIDEO_SIZEOF_VC_OUTPUT_TERMINAL_DESC 9 + +struct video_cs_if_vc_extension_unit_descriptor { + uint8_t bLength; + uint8_t bDescriptorType; + uint8_t bDescriptorSubType; + uint8_t bUnitID; + uint8_t guidExtensionCode[16]; + uint8_t bNumControls; + uint8_t bNrInPins; + // uint8_t baSourceID[]; + uint8_t bControlSize; + // uint8_t bmControls[] + uint8_t iExtension; +} __PACKED; + +#define VIDEO_SIZEOF_VC_EXTENSION_UNIT_DESC(p, n) (24 + p + n) + +struct video_cs_ep_vc_ep_descriptor { + uint8_t bLength; + uint8_t bDescriptorType; + uint8_t bDescriptorSubType; + uint16_t wMaxTransferSize; +} __PACKED; + +#define VIDEO_SIZEOF_VC_EP_DESC 5 + +struct video_cs_if_vs_input_header_descriptor { + uint8_t bLength; + uint8_t bDescriptorType; + uint8_t bDescriptorSubType; + uint8_t bNumFormats; + uint16_t wTotalLength; + uint8_t bEndpointAddress; + uint8_t bmInfo; + uint8_t bTerminalLink; + uint8_t bStillCaptureMethod; + uint8_t bTriggerSupport; + uint8_t bTriggerUsage; + uint8_t bControlSize; + uint8_t bmaControls[]; +} __PACKED; + +#define VIDEO_SIZEOF_VS_INPUT_HEADER_DESC(p, n) (13 + p * n) + +struct video_cs_if_vs_output_header_descriptor { + uint8_t bLength; + uint8_t bDescriptorType; + uint8_t bDescriptorSubType; + uint8_t bNumFormats; + uint16_t wTotalLength; + uint8_t bEndpointAddress; + uint8_t bTerminalLink; + uint8_t bControlSize; + uint8_t bmaControls[]; +} __PACKED; + +#define VIDEO_SIZEOF_VS_OUTPUT_TERMINAL_DESC(p, n) (9 + p * n) + +struct video_cs_if_vs_format_uncompressed_descriptor { + uint8_t bLength; + uint8_t bDescriptorType; + uint8_t bDescriptorSubType; + uint8_t bFormatIndex; + uint8_t bNumFrameDescriptors; + uint8_t guidFormat[16]; + uint8_t bBitsPerPixel; + uint8_t bDefaultFrameIndex; + uint8_t bAspectRatioX; + uint8_t bAspectRatioY; + uint8_t bmInterlaceFlags; + uint8_t bCopyProtect; +} __PACKED; + +#define VIDEO_SIZEOF_VS_FORMAT_UNCOMPRESSED_DESC (27) + +struct video_cs_if_vs_frame_uncompressed_descriptor { + uint8_t bLength; + uint8_t bDescriptorType; + uint8_t bDescriptorSubType; + uint8_t bFrameIndex; + uint8_t bmCapabilities; + uint16_t wWidth; + uint16_t wHeight; + uint32_t dwMinBitRate; + uint32_t dwMaxBitRate; + uint32_t dwMaxVideoFrameBufferSize; + uint32_t dwDefaultFrameInterval; + uint8_t bFrameIntervalType; + uint32_t dwFrameInterval[]; +} __PACKED; + +#define VIDEO_SIZEOF_VS_FRAME_UNCOMPRESSED_DESC(n) (26 + 4 * (n)) + +struct video_cs_if_vs_format_mjpeg_descriptor { + uint8_t bLength; + uint8_t bDescriptorType; + uint8_t bDescriptorSubType; + uint8_t bFormatIndex; + uint8_t bNumFrameDescriptors; + uint8_t bmFlags; + uint8_t bDefaultFrameIndex; + uint8_t bAspectRatioX; + uint8_t bAspectRatioY; + uint8_t bmInterlaceFlags; + uint8_t bCopyProtect; +} __PACKED; + +#define VIDEO_SIZEOF_VS_FORMAT_MJPEG_DESC 11 + +struct video_cs_if_vs_frame_mjpeg_descriptor { + uint8_t bLength; + uint8_t bDescriptorType; + uint8_t bDescriptorSubType; + uint8_t bFrameIndex; + uint8_t bmCapabilities; + uint16_t wWidth; + uint16_t wHeight; + uint32_t dwMinBitRate; + uint32_t dwMaxBitRate; + uint32_t dwMaxVideoFrameBufferSize; + uint32_t dwDefaultFrameInterval; + uint8_t bFrameIntervalType; + uint32_t dwFrameInterval[]; +} __PACKED; + +#define VIDEO_SIZEOF_VS_FRAME_MJPEG_DESC(n) (26 + 4 * (n)) + +/* H264 Payload - 3.1.1. H264 Video Format Descriptor */ +struct video_cs_if_vs_format_h26x_descriptor { + uint8_t bLength; + uint8_t bDescriptorType; + uint8_t bDescriptorSubType; + uint8_t bFormatIndex; + uint8_t bNumFrameDescriptors; + uint8_t guidFormat[16]; + uint8_t bBitsPerPixel; + uint8_t bDefaultFrameIndex; + uint8_t bAspectRatioX; + uint8_t bAspectRatioY; + uint8_t bmInterfaceFlags; + uint8_t bCopyProtect; + uint8_t bVariableSize; +} __PACKED; + +#define VIDEO_SIZEOF_VS_FORMAT_H264_DESC 28 + +/* H264 Payload - 3.1.2. H264 Video Frame Descriptor */ +struct video_cs_if_vs_frame_h26x_descriptor { + uint8_t bLength; + uint8_t bDescriptorType; + uint8_t bDescriptorSubType; + uint8_t bFrameIndex; + uint8_t bmCapabilities; + uint16_t wWidth; + uint16_t wHeight; + uint32_t dwMinBitRate; + uint32_t dwMaxBitRate; + uint32_t dwDefaultFrameInterval; + uint8_t bFrameIntervalType; + uint32_t dwBytesPerLine; + uint32_t dwFrameInterval[]; +} __PACKED; + +#define VIDEO_SIZEOF_VS_FRAME_H264_DESC(n) (26 + 4 * (n)) + +struct video_cs_if_vs_colorformat_descriptor { + uint8_t bLength; + uint8_t bDescriptorType; + uint8_t bDescriptorSubType; + uint8_t bColorPrimaries; + uint8_t bXferCharacteristics; + uint8_t bMatrixCoefficients; +} __PACKED; + +#define VIDEO_SIZEOF_VS_COLORFORMAT_DESC 6 + +struct video_vc_input_terminal_bmcontrol_bitmap { + uint32_t scanning_mode : 1; + uint32_t auto_exposure_mode : 1; + uint32_t auto_exposure_priority : 1; + uint32_t exposure_time_absolute : 1; + uint32_t exposure_time_relative : 1; + uint32_t focus_absolute : 1; + uint32_t focus_relative : 1; + uint32_t iris_absolute : 1; + uint32_t iris_relative : 1; + uint32_t zoom_absolute : 1; + uint32_t zoom_relative : 1; + uint32_t pantilt_absolute : 1; + uint32_t pantilt_relative : 1; + uint32_t roll_absolute : 1; + uint32_t roll_relative : 1; + uint32_t reserved : 2; + uint32_t focus_auto : 1; + uint32_t pricvcy : 1; +}; + +struct video_vc_processing_unit_bmcontrol_bitmap { + uint16_t brightness : 1; + uint16_t contrast : 1; + uint16_t hue : 1; + uint16_t saturation : 1; + uint16_t sharpness : 1; + uint16_t gamma : 1; + uint16_t white_bal_temp : 1; + uint16_t white_bal_comp : 1; + uint16_t backlight_comp : 1; + uint16_t gain : 1; + uint16_t power_line_freq : 1; + uint16_t hue_auto : 1; + uint16_t white_bal_temp_auto : 1; + uint16_t white_bal_comp_auto : 1; + uint16_t digital_mult : 1; + uint16_t digital_mult_limit : 1; +}; + +struct video_camera_capabilities { + uint8_t support_get_request : 1; + uint8_t support_set_request : 1; + uint8_t disabled_by_automatic_mode : 1; + uint8_t auto_update_control : 1; + uint8_t async_control : 1; + uint8_t reserved : 3; +}; + +struct video_autoexposure_mode { + uint8_t manual_mode : 1; + uint8_t auto_mode : 1; + uint8_t shutter_priority_mode : 1; + uint8_t aperture_priority_mode : 1; + uint8_t reserved : 4; +}; + +#define VIDEO_GUID_YUY2 0x59, 0x55, 0x59, 0x32, 0x00, 0x00, 0x10, 0x00, 0x80, 0x00, 0x00, 0xAA, 0x00, 0x38, 0x9B, 0x71 +#define VIDEO_GUID_NV12 0x4E, 0x56, 0x31, 0x32, 0x00, 0x00, 0x10, 0x00, 0x80, 0x00, 0x00, 0xAA, 0x00, 0x38, 0x9B, 0x71 +#define VIDEO_GUID_NV21 0x4E, 0x56, 0x32, 0x31, 0x00, 0x00, 0x10, 0x00, 0x80, 0x00, 0x00, 0xAA, 0x00, 0x38, 0x9B, 0x71 +#define VIDEO_GUID_M420 0x4D, 0x34, 0x32, 0x30, 0x00, 0x00, 0x10, 0x00, 0x80, 0x00, 0x00, 0xAA, 0x00, 0x38, 0x9B, 0x71 +#define VIDEO_GUID_I420 0x49, 0x34, 0x32, 0x30, 0x00, 0x00, 0x10, 0x00, 0x80, 0x00, 0x00, 0xAA, 0x00, 0x38, 0x9B, 0x71 +#define VIDEO_GUID_H264 0x48, 0x32, 0x36, 0x34, 0x00, 0x00, 0x10, 0x00, 0x80, 0x00, 0x00, 0xAA, 0x00, 0x38, 0x9B, 0x71 + +#define VIDEO_VC_TERMINAL_LEN (13 + 18 + 12 + 9) + +/*Length of template descriptor: 81 bytes*/ +#define VIDEO_VC_DESCRIPTOR_LEN (8 + 9 + VIDEO_VC_TERMINAL_LEN + 7 + 5) +#define VIDEO_VC_NOEP_DESCRIPTOR_LEN (8 + 9 + VIDEO_VC_TERMINAL_LEN) + +// clang-format off +#define VIDEO_VC_DESCRIPTOR_INIT(bFirstInterface, bEndpointAddress, bcdUVC, wTotalLength, dwClockFrequency, stridx) \ + /* Interface Association Descriptor */ \ + 0x08, \ + USB_DESCRIPTOR_TYPE_INTERFACE_ASSOCIATION, \ + bFirstInterface, \ + 0x02, \ + USB_DEVICE_CLASS_VIDEO, \ + VIDEO_SC_VIDEO_INTERFACE_COLLECTION, \ + 0x00, \ + 0x00, /* VideoControl Interface Descriptor */ \ + 0x09, /* bLength */ \ + USB_DESCRIPTOR_TYPE_INTERFACE, /* bDescriptorType */ \ + 0x00, /* bInterfaceNumber */ \ + 0x00, /* bAlternateSetting */ \ + 0x01, /* bNumEndpoints:1 endpoint (interrupt endpoint) */ \ + USB_DEVICE_CLASS_VIDEO, /* bInterfaceClass : CC_VIDEO */ \ + VIDEO_SC_VIDEOCONTROL, /* bInterfaceSubClass : SC_VIDEOCONTROL */ \ + VIDEO_PC_PROTOCOL_UNDEFINED, /* bInterfaceProtocol : PC_PROTOCOL_UNDEFINED */ \ + stridx, /* iInterface:Index to string descriptor that contains the string */ /*Class-specific VideoControl Interface Descriptor */ \ + 0x0d, /* bLength */ \ + 0x24, /* bDescriptorType : CS_INTERFACE */ \ + VIDEO_VC_HEADER_DESCRIPTOR_SUBTYPE, /* bDescriptorSubType : VC_HEADER subtype */ \ + WBVAL(bcdUVC), /* bcdUVC : Revision of class specification that this device is based upon.*/ \ + WBVAL(wTotalLength), /* wTotalLength */ \ + DBVAL(dwClockFrequency), /* dwClockFrequency : 0x005b8d80 -> 6,000,000 == 6MHz*/ \ + 0x01, /* bInCollection : Number of streaming interfaces. */ \ + (uint8_t)(bFirstInterface + 1), /* baInterfaceNr(0) : VideoStreaming interface 1 belongs to this VideoControl interface.*/ /* Input Terminal 1 -> Processing Unit 2 -> Output Terminal 3 */ \ + 0x12, \ + 0x24, \ + VIDEO_VC_INPUT_TERMINAL_DESCRIPTOR_SUBTYPE, \ + 0x01, /* bTerminalID */ \ + WBVAL(VIDEO_ITT_CAMERA), /* wTerminalType : 0x0201 Camera Sensor*/ \ + 0x00, /* bAssocTerminal */ \ + 0x00, /* iTerminal */ \ + WBVAL(0x0000), /* wObjectiveFocalLengthMin */ \ + WBVAL(0x0000), /* wObjectiveFocalLengthMax */ \ + WBVAL(0x0000), /* wOcularFocalLength */ \ + 0x03, /* bControlSize */ \ + 0x00, 0x00, 0x00, /* bmControls */ \ + 0x0c, \ + 0x24, \ + VIDEO_VC_PROCESSING_UNIT_DESCRIPTOR_SUBTYPE, \ + 0x02, /* bUnitID */ \ + 0x01, /* bSourceID */ \ + 0x00, 0x00, /* wMaxMultiplier */ \ + 0x02, /* bControlSize */ \ + 0x00, 0x00, /* bmControls */ \ + 0x00, /* iProcessing */ \ + 0x00, /* bmVideoStandards */ \ + 0x09, \ + 0x24, \ + VIDEO_VC_OUTPUT_TERMINAL_DESCRIPTOR_SUBTYPE, \ + 0x03, /* bTerminalID */ \ + WBVAL(VIDEO_TT_STREAMING), \ + 0x00, /* bAssocTerminal */ \ + 0x02, /* bSourceID */ \ + 0x00, /* iTerminal */ \ + 0x07, /* bLength */ \ + USB_DESCRIPTOR_TYPE_ENDPOINT, /* bDescriptorType */ \ + bEndpointAddress, /* bEndpointAddress */ \ + 0x03, /* bmAttributes */ \ + 0x10, 0x00, /* wMaxPacketSize */ \ + 0x08, /* bInterval */ \ + /* Class-specific VC Interrupt Endpoint Descriptor */ \ + 0x05, 0x25, 0x03, 0x10, 0x00 + +#define VIDEO_VC_NOEP_DESCRIPTOR_INIT(bFirstInterface, bEndpointAddress, bcdUVC, wTotalLength, dwClockFrequency, stridx) \ + /* Interface Association Descriptor */ \ + 0x08, \ + USB_DESCRIPTOR_TYPE_INTERFACE_ASSOCIATION, \ + bFirstInterface, \ + 0x02, \ + USB_DEVICE_CLASS_VIDEO, \ + VIDEO_SC_VIDEO_INTERFACE_COLLECTION, \ + 0x00, \ + 0x00, /* VideoControl Interface Descriptor */ \ + 0x09, /* bLength */ \ + USB_DESCRIPTOR_TYPE_INTERFACE, /* bDescriptorType */ \ + 0x00, /* bInterfaceNumber */ \ + 0x00, /* bAlternateSetting */ \ + 0x00, /* bNumEndpoints:1 endpoint (interrupt endpoint) */ \ + USB_DEVICE_CLASS_VIDEO, /* bInterfaceClass : CC_VIDEO */ \ + VIDEO_SC_VIDEOCONTROL, /* bInterfaceSubClass : SC_VIDEOCONTROL */ \ + VIDEO_PC_PROTOCOL_UNDEFINED, /* bInterfaceProtocol : PC_PROTOCOL_UNDEFINED */ \ + stridx, /* iInterface:Index to string descriptor that contains the string */ /*Class-specific VideoControl Interface Descriptor */ \ + 0x0d, /* bLength */ \ + 0x24, /* bDescriptorType : CS_INTERFACE */ \ + VIDEO_VC_HEADER_DESCRIPTOR_SUBTYPE, /* bDescriptorSubType : VC_HEADER subtype */ \ + WBVAL(bcdUVC), /* bcdUVC : Revision of class specification that this device is based upon.*/ \ + WBVAL(wTotalLength), /* wTotalLength */ \ + DBVAL(dwClockFrequency), /* dwClockFrequency : 0x005b8d80 -> 6,000,000 == 6MHz*/ \ + 0x01, /* bInCollection : Number of streaming interfaces. */ \ + (uint8_t)(bFirstInterface + 1), /* baInterfaceNr(0) : VideoStreaming interface 1 belongs to this VideoControl interface.*/ /* Input Terminal 1 -> Processing Unit 2 -> Output Terminal 3 */ \ + 0x12, \ + 0x24, \ + VIDEO_VC_INPUT_TERMINAL_DESCRIPTOR_SUBTYPE, \ + 0x01, /* bTerminalID */ \ + WBVAL(VIDEO_ITT_CAMERA), /* wTerminalType : 0x0201 Camera Sensor*/ \ + 0x00, /* bAssocTerminal */ \ + 0x00, /* iTerminal */ \ + WBVAL(0x0000), /* wObjectiveFocalLengthMin */ \ + WBVAL(0x0000), /* wObjectiveFocalLengthMax */ \ + WBVAL(0x0000), /* wOcularFocalLength */ \ + 0x03, /* bControlSize */ \ + 0x00, 0x00, 0x00, /* bmControls */ \ + 0x0c, \ + 0x24, \ + VIDEO_VC_PROCESSING_UNIT_DESCRIPTOR_SUBTYPE, \ + 0x02, /* bUnitID */ \ + 0x01, /* bSourceID */ \ + 0x00, 0x00, /* wMaxMultiplier */ \ + 0x02, /* bControlSize */ \ + 0x00, 0x00, /* bmControls */ \ + 0x00, /* iProcessing */ \ + 0x00, /* bmVideoStandards */ \ + 0x09, \ + 0x24, \ + VIDEO_VC_OUTPUT_TERMINAL_DESCRIPTOR_SUBTYPE, \ + 0x03, /* bTerminalID */ \ + WBVAL(VIDEO_TT_STREAMING), \ + 0x00, /* bAssocTerminal */ \ + 0x02, /* bSourceID */ \ + 0x00 /* iTerminal */ \ + +#define VIDEO_VS_DESCRIPTOR_INIT(bInterfaceNumber, bAlternateSetting, bNumEndpoints) \ + /* Video Streaming (VS) Interface Descriptor */ \ + 0x09, /* bLength */ \ + USB_DESCRIPTOR_TYPE_INTERFACE, /* bDescriptorType : INTERFACE */ \ + bInterfaceNumber, /* bInterfaceNumber: Index of this interface */ \ + bAlternateSetting, /* bAlternateSetting: Index of this alternate setting */ \ + bNumEndpoints, /* bNumEndpoints : 0 endpoints, no bandwidth used*/ \ + 0x0e, /* bInterfaceClass : CC_VIDEO */ \ + 0x02, /* bInterfaceSubClass : SC_VIDEOSTREAMING */ \ + 0x00, /* bInterfaceProtocol : PC_PROTOCOL_UNDEFINED */ \ + 0x00 /* iInterface : unused */ + +#define VIDEO_VS_INPUT_HEADER_DESCRIPTOR_INIT(bNumFormats, wTotalLength, bEndpointAddress, ...) \ + /*Class-specific VideoStream Header Descriptor (Input) */ \ + 0x0d + PP_NARG(__VA_ARGS__), \ + 0x24, \ + VIDEO_VS_INPUT_HEADER_DESCRIPTOR_SUBTYPE, \ + bNumFormats, /* bNumFormats : One format descriptor follows. */ \ + WBVAL(wTotalLength), \ + bEndpointAddress, \ + 0x00, /* bmInfo : No dynamic format change supported. */ \ + 0x03, /* bTerminalLink : This VideoStreaming interface supplies terminal ID 2 (Output Terminal). */ \ + 0x00, /* bStillCaptureMethod : Device supports still image capture method 0. */ \ + 0x00, /* bTriggerSupport : Hardware trigger supported for still image capture */ \ + 0x00, /* bTriggerUsage : Hardware trigger should initiate a still image capture. */ \ + 0x01, /* bControlSize : Size of the bmaControls field */ \ + __VA_ARGS__ /* bmaControls : No VideoStreaming specific controls are supported.*/ + +#define VIDEO_VS_OUTPUT_HEADER_DESCRIPTOR_INIT(bNumFormats, wTotalLength, bEndpointAddress, ...) \ + /*Class-specific VideoStream Header Descriptor (Input) */ \ + 0x0d + PP_NARG(__VA_ARGS__), \ + 0x24, \ + VIDEO_VS_OUTPUT_HEADER_DESCRIPTOR_SUBTYPE, \ + bNumFormats, /* bNumFormats : One format descriptor follows. */ \ + WBVAL(wTotalLength), \ + bEndpointAddress, \ + 0x00, /* bmInfo : No dynamic format change supported. */ \ + 0x03, /* bTerminalLink : This VideoStreaming interface supplies terminal ID 2 (Output Terminal). */ \ + 0x00, /* bStillCaptureMethod : Device supports still image capture method 0. */ \ + 0x00, /* bTriggerSupport : Hardware trigger supported for still image capture */ \ + 0x00, /* bTriggerUsage : Hardware trigger should initiate a still image capture. */ \ + PP_NARG(__VA_ARGS__), /* bControlSize : Size of the bmaControls field */ \ + __VA_ARGS__ /* bmaControls : No VideoStreaming specific controls are supported.*/ + +#define VIDEO_VS_FORMAT_UNCOMPRESSED_DESCRIPTOR_INIT(bFormatIndex, bNumFrameDescriptors, GUIDFormat) \ + /*Payload Format(UNCOMPRESSED) Descriptor */ \ + 0x1b, \ + 0x24, \ + VIDEO_VS_FORMAT_UNCOMPRESSED_DESCRIPTOR_SUBTYPE, /* bDescriptorSubType : VS_FORMAT_UNCOMPRESSED subtype */ \ + bFormatIndex, /* bFormatIndex : First (and only) format descriptor */ \ + bNumFrameDescriptors, /* bNumFrameDescriptors : One frame descriptor for this format follows. */ \ + GUIDFormat, /* GUID Format YUY2 {32595559-0000-0010-8000-00AA00389B71} */ \ + 0x10, /* bBitsPerPixel : Number of bits per pixel used to specify color in the decoded video frame - 16 for yuy2*/ \ + 0x01, /* bDefaultFrameIndex : Default frame index is 1. */ \ + 0x00, /* bAspectRatioX : Non-interlaced stream not required. */ \ + 0x00, /* bAspectRatioY : Non-interlaced stream not required. */ \ + 0x00, /* bmInterlaceFlags : Non-interlaced stream */ \ + 0x00 /* bCopyProtect : No restrictions imposed on the duplication of this video stream. */ + +#define VIDEO_VS_FRAME_UNCOMPRESSED_DESCRIPTOR_INIT(bFrameIndex, wWidth, wHeight, dwMinBitRate, dwMaxBitRate, \ + dwMaxVideoFrameBufferSize, dwDefaultFrameInterval, bFrameIntervalType, ...) \ + 0x1a + PP_NARG(__VA_ARGS__), \ + 0x24, \ + VIDEO_VS_FRAME_UNCOMPRESSED_DESCRIPTOR_SUBTYPE, \ + bFrameIndex, \ + 0x00, \ + WBVAL(wWidth), \ + WBVAL(wHeight), \ + DBVAL(dwMinBitRate), \ + DBVAL(dwMaxBitRate), \ + DBVAL(dwMaxVideoFrameBufferSize), \ + dwDefaultFrameInterval, /* dwDefaultFrameInterval : 1,000,000 * 100ns -> 10 FPS */ \ + bFrameIntervalType, /* bFrameIntervalType : Indicates how the frame interval can be programmed. 0: Continuous frame interval 1..255: The number of discrete frame */ \ + __VA_ARGS__ + +#define VIDEO_VS_FORMAT_MJPEG_DESCRIPTOR_INIT(bFormatIndex, bNumFrameDescriptors) \ + /*Payload Format(MJPEG) Descriptor */ \ + 0x0b, /* bLength */ \ + 0x24, /* bDescriptorType : CS_INTERFACE */ \ + 0x06, /* bDescriptorSubType : VS_FORMAT_MJPEG subtype */ \ + bFormatIndex, /* bFormatIndex : First (and only) format descriptor */ \ + bNumFrameDescriptors, /* bNumFrameDescriptors : One frame descriptor for this format follows. */ \ + 0x00, /* bmFlags : Uses fixed size samples.. */ \ + 0x01, /* bDefaultFrameIndex : Default frame index is 1. */ \ + 0x00, /* bAspectRatioX : Non-interlaced stream, not required. */ \ + 0x00, /* bAspectRatioY : Non-interlaced stream, not required. */ \ + 0x00, /* bmInterlaceFlags : Non-interlaced stream */ \ + 0x00 /* bCopyProtect : No restrictions imposed on the duplication of this video stream. */ + +#define VIDEO_VS_FRAME_MJPEG_DESCRIPTOR_INIT(bFrameIndex, wWidth, wHeight, dwMinBitRate, dwMaxBitRate, \ + dwMaxVideoFrameBufferSize, dwDefaultFrameInterval, bFrameIntervalType, ...) \ + 0x1a + PP_NARG(__VA_ARGS__), /* bLength */ \ + 0x24, /* bDescriptorType : CS_INTERFACE */ \ + VIDEO_VS_FRAME_MJPEG_DESCRIPTOR_SUBTYPE, /* bDescriptorSubType : VS_FRAME_MJPEG */ \ + bFrameIndex, /* bFrameIndex : First (and only) frame descriptor */ \ + 0x00, /* bmCapabilities : Still images using capture method 0 are supported at this frame setting.D1: Fixed frame-rate. */ \ + WBVAL(wWidth), /* wWidth (2bytes): Width of frame is 128 pixels. */ \ + WBVAL(wHeight), /* wHeight (2bytes): Height of frame is 64 pixels. */ \ + DBVAL(dwMinBitRate), /* dwMinBitRate (4bytes): Min bit rate in bits/s */ \ + DBVAL(dwMaxBitRate), /* dwMaxBitRate (4bytes): Max bit rate in bits/s */ \ + DBVAL(dwMaxVideoFrameBufferSize), /* dwMaxVideoFrameBufSize (4bytes): Maximum video or still frame size, in bytes. */ \ + dwDefaultFrameInterval, /* dwDefaultFrameInterval : 1,000,000 * 100ns -> 10 FPS */ \ + bFrameIntervalType, /* bFrameIntervalType : Indicates how the frame interval can be programmed. 0: Continuous frame interval 1..255: The number of discrete frame */ \ + __VA_ARGS__ + +#define VIDEO_VS_FORMAT_H264_DESCRIPTOR_INIT(bFormatIndex, bNumFrameDescriptors) \ + /*Payload Format(H.264) Descriptor */ \ + 0x1c, /* bLength */ \ + 0x24, /* bDescriptorType : CS_INTERFACE */ \ + VIDEO_VS_FORMAT_FRAME_BASED_DESCRIPTOR_SUBTYPE, /* bDescriptorSubType : VS_FORMAT_FRAME_BASED subtype */\ + bFormatIndex, /* bFormatIndex : First (and only) format descriptor */ \ + bNumFrameDescriptors, /* bNumFrameDescriptors : One frame descriptor for this format follows. */ \ + VIDEO_GUID_H264, \ + 0x00, /* bmFlags : Uses fixed size samples.. */ \ + 0x01, /* bDefaultFrameIndex : Default frame index is 1. */ \ + 0x00, /* bAspectRatioX : Non-interlaced stream, not required. */ \ + 0x00, /* bAspectRatioY : Non-interlaced stream, not required. */ \ + 0x00, /* bmInterlaceFlags : Non-interlaced stream */ \ + 0x00, /* bCopyProtect : No restrictions imposed on the duplication of this video stream. */ \ + 0x00 /* Variable size: False */ + +#define VIDEO_VS_FRAME_H264_DESCRIPTOR_INIT(bFrameIndex, wWidth, wHeight, dwMinBitRate, dwMaxBitRate, \ + dwDefaultFrameInterval, bFrameIntervalType, ...) \ + 0x1a + PP_NARG(__VA_ARGS__), /* bLength */ \ + 0x24, /* bDescriptorType : CS_INTERFACE */ \ + VIDEO_VS_FRAME_FRAME_BASED_DESCRIPTOR_SUBTYPE, /* bDescriptorSubType : VS_FRAME_BASED */ \ + bFrameIndex, /* bFrameIndex : First (and only) frame descriptor */ \ + 0x00, /* bmCapabilities : Still images using capture method 0 are supported at this frame setting.D1: Fixed frame-rate. */ \ + WBVAL(wWidth), /* wWidth (2bytes): Width of frame is 128 pixels. */ \ + WBVAL(wHeight), /* wHeight (2bytes): Height of frame is 64 pixels. */ \ + DBVAL(dwMinBitRate), /* dwMinBitRate (4bytes): Min bit rate in bits/s */ \ + DBVAL(dwMaxBitRate), /* dwMaxBitRate (4bytes): Max bit rate in bits/s */ \ + dwDefaultFrameInterval, /* dwDefaultFrameInterval : 1,000,000 * 100ns -> 10 FPS */ \ + bFrameIntervalType, /* bFrameIntervalType : Indicates how the frame interval can be programmed. 0: Continuous frame interval 1..255: The number of discrete frame */ \ + DBVAL(0x00), /* dwBytesPerLine (4bytes) */ \ + __VA_ARGS__ + +#define VIDEO_VS_COLOR_MATCHING_DESCRIPTOR_INIT() \ + 0x06, /* bLength */ \ + 0x24, /* bDescriptorType : CS_INTERFACE */ \ + VIDEO_VS_COLORFORMAT_DESCRIPTOR_SUBTYPE, /* bDescriptorSubType : VS_COLORFORMAT */ \ + 0x01, /* bColorPrimaries */ \ + 0x01, /* bTransferCharacteristics */ \ + 0x04 /* bMatrixCoefficients */ + +// clang-format on +#endif /*USB_VIDEO_H */ \ No newline at end of file diff --git a/kernel/cherryusb/class/video/usbd_video.c b/kernel/cherryusb/class/video/usbd_video.c new file mode 100644 index 0000000..3ed6ff8 --- /dev/null +++ b/kernel/cherryusb/class/video/usbd_video.c @@ -0,0 +1,852 @@ +/* + * Copyright (c) 2022, sakumisu + * + * SPDX-License-Identifier: Apache-2.0 + */ +#include "usbd_core.h" +#include "usbd_video.h" + +struct video_entity_info { + uint8_t bDescriptorSubtype; + uint8_t bEntityId; + uint16_t wTerminalType; +}; + +struct usbd_video_priv { + struct video_probe_and_commit_controls probe; + struct video_probe_and_commit_controls commit; + uint8_t power_mode; + uint8_t error_code; + struct video_entity_info info[3]; + uint8_t *ep_buf; + bool stream_finish; + uint8_t *stream_buf; + uint32_t stream_len; + uint32_t stream_offset; + uint8_t stream_frameid; + uint32_t stream_headerlen; + bool do_copy; +} g_usbd_video[CONFIG_USBDEV_MAX_BUS]; + +static int usbd_video_control_request_handler(uint8_t busid, struct usb_setup_packet *setup, uint8_t **data, uint32_t *len) +{ + uint8_t control_selector = (uint8_t)(setup->wValue >> 8); + + (void)busid; + + switch (control_selector) { + case VIDEO_VC_VIDEO_POWER_MODE_CONTROL: + switch (setup->bRequest) { + case VIDEO_REQUEST_SET_CUR: + break; + case VIDEO_REQUEST_GET_CUR: + break; + case VIDEO_REQUEST_GET_INFO: + break; + default: + return -1; + } + + break; + case VIDEO_VC_REQUEST_ERROR_CODE_CONTROL: + switch (setup->bRequest) { + case VIDEO_REQUEST_GET_CUR: + (*data)[0] = 0x06; + *len = 1; + break; + case VIDEO_REQUEST_GET_INFO: + break; + default: + return -1; + } + + break; + default: + break; + } + + return 0; +} + +static int usbd_video_control_unit_terminal_request_handler(uint8_t busid, struct usb_setup_packet *setup, uint8_t **data, uint32_t *len) +{ + uint8_t entity_id = (uint8_t)(setup->wIndex >> 8); + uint8_t control_selector = (uint8_t)(setup->wValue >> 8); + + for (uint8_t i = 0; i < 3; i++) { + struct video_entity_info *entity_info = &g_usbd_video[busid].info[i]; + if (entity_info->bEntityId == entity_id) { + switch (entity_info->bDescriptorSubtype) { + case VIDEO_VC_HEADER_DESCRIPTOR_SUBTYPE: + break; + case VIDEO_VC_INPUT_TERMINAL_DESCRIPTOR_SUBTYPE: + if (entity_info->wTerminalType == VIDEO_ITT_CAMERA) { + switch (control_selector) { + case VIDEO_CT_AE_MODE_CONTROL: + switch (setup->bRequest) { + case VIDEO_REQUEST_GET_CUR: + (*data)[0] = 0x08; + *len = 1; + break; + default: + return -1; + } + break; + case VIDEO_CT_EXPOSURE_TIME_ABSOLUTE_CONTROL: + switch (setup->bRequest) { + case VIDEO_REQUEST_GET_CUR: { + uint32_t dwExposureTimeAbsolute = 2500; + memcpy(*data, (uint8_t *)&dwExposureTimeAbsolute, 4); + *len = 4; + } break; + case VIDEO_REQUEST_GET_MIN: { + uint32_t dwExposureTimeAbsolute = 5; //0.0005sec + memcpy(*data, (uint8_t *)&dwExposureTimeAbsolute, 4); + *len = 4; + } break; + case VIDEO_REQUEST_GET_MAX: { + uint32_t dwExposureTimeAbsolute = 2500; //0.2500sec + memcpy(*data, (uint8_t *)&dwExposureTimeAbsolute, 4); + *len = 4; + } break; + case VIDEO_REQUEST_GET_RES: { + uint32_t dwExposureTimeAbsolute = 5; //0.0005sec + memcpy(*data, (uint8_t *)&dwExposureTimeAbsolute, 4); + *len = 4; + } break; + case VIDEO_REQUEST_GET_INFO: + (*data)[0] = 0x03; //struct video_camera_capabilities + *len = 1; + break; + case VIDEO_REQUEST_GET_DEF: { + uint32_t dwExposureTimeAbsolute = 2500; //0.2500sec + memcpy(*data, (uint8_t *)&dwExposureTimeAbsolute, 4); + *len = 4; + } break; + default: + return -1; + } + break; + case VIDEO_CT_FOCUS_ABSOLUTE_CONTROL: + switch (setup->bRequest) { + case VIDEO_REQUEST_GET_CUR: { + uint16_t wFocusAbsolute = 0x0080; + memcpy(*data, (uint8_t *)&wFocusAbsolute, 2); + *len = 2; + } break; + case VIDEO_REQUEST_GET_MIN: { + uint16_t wFocusAbsolute = 0; + memcpy(*data, (uint8_t *)&wFocusAbsolute, 2); + *len = 2; + } break; + case VIDEO_REQUEST_GET_MAX: { + uint16_t wFocusAbsolute = 0x00ff; + memcpy(*data, (uint8_t *)&wFocusAbsolute, 2); + *len = 2; + } break; + case VIDEO_REQUEST_GET_RES: { + uint16_t wFocusAbsolute = 0x0001; + memcpy(*data, (uint8_t *)&wFocusAbsolute, 2); + *len = 2; + } break; + case VIDEO_REQUEST_GET_INFO: + (*data)[0] = 0x03; //struct video_camera_capabilities + *len = 1; + break; + case VIDEO_REQUEST_GET_DEF: { + uint16_t wFocusAbsolute = 0x0080; + memcpy(*data, (uint8_t *)&wFocusAbsolute, 2); + *len = 2; + } break; + default: + return -1; + } + break; + case VIDEO_CT_ZOOM_ABSOLUTE_CONTROL: + switch (setup->bRequest) { + case VIDEO_REQUEST_GET_CUR: { + uint16_t wObjectiveFocalLength = 0x0064; + memcpy(*data, (uint8_t *)&wObjectiveFocalLength, 2); + *len = 2; + } break; + case VIDEO_REQUEST_GET_MIN: { + uint16_t wObjectiveFocalLength = 0x0064; + memcpy(*data, (uint8_t *)&wObjectiveFocalLength, 2); + *len = 2; + } break; + case VIDEO_REQUEST_GET_MAX: { + uint16_t wObjectiveFocalLength = 0x00c8; + memcpy(*data, (uint8_t *)&wObjectiveFocalLength, 2); + *len = 2; + } break; + case VIDEO_REQUEST_GET_RES: { + uint16_t wObjectiveFocalLength = 0x0001; + memcpy(*data, (uint8_t *)&wObjectiveFocalLength, 2); + *len = 2; + } break; + case VIDEO_REQUEST_GET_INFO: + (*data)[0] = 0x03; //struct video_camera_capabilities + *len = 1; + break; + case VIDEO_REQUEST_GET_DEF: { + uint16_t wObjectiveFocalLength = 0x0064; + memcpy(*data, (uint8_t *)&wObjectiveFocalLength, 2); + *len = 2; + } break; + default: + return -1; + } + break; + case VIDEO_CT_ROLL_ABSOLUTE_CONTROL: + switch (setup->bRequest) { + case VIDEO_REQUEST_GET_CUR: { + uint16_t wRollAbsolute = 0x0000; + memcpy(*data, (uint8_t *)&wRollAbsolute, 2); + *len = 2; + } break; + case VIDEO_REQUEST_GET_MIN: { + uint16_t wRollAbsolute = 0x0000; + memcpy(*data, (uint8_t *)&wRollAbsolute, 2); + *len = 2; + } break; + case VIDEO_REQUEST_GET_MAX: { + uint16_t wRollAbsolute = 0x00ff; + memcpy(*data, (uint8_t *)&wRollAbsolute, 2); + *len = 2; + } break; + case VIDEO_REQUEST_GET_RES: { + uint16_t wRollAbsolute = 0x0001; + memcpy(*data, (uint8_t *)&wRollAbsolute, 2); + *len = 2; + } break; + case VIDEO_REQUEST_GET_INFO: + (*data)[0] = 0x03; //struct video_camera_capabilities + *len = 1; + break; + case VIDEO_REQUEST_GET_DEF: { + uint16_t wRollAbsolute = 0x0000; + memcpy(*data, (uint8_t *)&wRollAbsolute, 2); + *len = 2; + } break; + default: + return -1; + } + break; + case VIDEO_CT_FOCUS_AUTO_CONTROL: + switch (setup->bRequest) { + case VIDEO_REQUEST_GET_CUR: { + uint16_t wFocusAuto = 0x0000; + memcpy(*data, (uint8_t *)&wFocusAuto, 2); + *len = 2; + } break; + default: + return -1; + } + break; + default: + return -1; + } + } else { + return -2; + } + break; + case VIDEO_VC_OUTPUT_TERMINAL_DESCRIPTOR_SUBTYPE: + break; + case VIDEO_VC_SELECTOR_UNIT_DESCRIPTOR_SUBTYPE: + break; + case VIDEO_VC_PROCESSING_UNIT_DESCRIPTOR_SUBTYPE: + switch (control_selector) { + case VIDEO_PU_BACKLIGHT_COMPENSATION_CONTROL: + switch (setup->bRequest) { + case VIDEO_REQUEST_GET_CUR: { + uint16_t wBacklightCompensation = 0x0004; + memcpy(*data, (uint8_t *)&wBacklightCompensation, 2); + *len = 2; + } break; + case VIDEO_REQUEST_GET_MIN: { + uint16_t wBacklightCompensation = 0; + memcpy(*data, (uint8_t *)&wBacklightCompensation, 2); + *len = 2; + } break; + case VIDEO_REQUEST_GET_MAX: { + uint16_t wBacklightCompensation = 8; + memcpy(*data, (uint8_t *)&wBacklightCompensation, 2); + *len = 2; + } break; + case VIDEO_REQUEST_GET_RES: { + uint16_t wBacklightCompensation = 1; + memcpy(*data, (uint8_t *)&wBacklightCompensation, 2); + *len = 2; + } break; + case VIDEO_REQUEST_GET_INFO: + (*data)[0] = 0x03; //struct video_camera_capabilities + *len = 1; + break; + case VIDEO_REQUEST_GET_DEF: { + uint16_t wBacklightCompensation = 4; + memcpy(*data, (uint8_t *)&wBacklightCompensation, 2); + *len = 2; + } break; + default: + return -1; + } + break; + case VIDEO_PU_BRIGHTNESS_CONTROL: + switch (setup->bRequest) { + case VIDEO_REQUEST_SET_CUR: { + //uint16_t wBrightness = (uint16_t)(*data)[1] << 8 | (uint16_t)(*data)[0]; + } break; + case VIDEO_REQUEST_GET_CUR: { + uint16_t wBrightness = 0x0080; + memcpy(*data, (uint8_t *)&wBrightness, 2); + *len = 2; + } break; + case VIDEO_REQUEST_GET_MIN: { + uint16_t wBrightness = 0x0001; + memcpy(*data, (uint8_t *)&wBrightness, 2); + *len = 2; + } break; + case VIDEO_REQUEST_GET_MAX: { + uint16_t wBrightness = 0x00ff; + memcpy(*data, (uint8_t *)&wBrightness, 2); + *len = 2; + } break; + case VIDEO_REQUEST_GET_RES: { + uint16_t wBrightness = 0x0001; + memcpy(*data, (uint8_t *)&wBrightness, 2); + *len = 2; + } break; + case VIDEO_REQUEST_GET_INFO: + (*data)[0] = 0x03; //struct video_camera_capabilities + *len = 1; + break; + case VIDEO_REQUEST_GET_DEF: { + uint16_t wBrightness = 0x0080; + memcpy(*data, (uint8_t *)&wBrightness, 2); + *len = 2; + } break; + default: + return -1; + } + break; + case VIDEO_PU_CONTRAST_CONTROL: + switch (setup->bRequest) { + case VIDEO_REQUEST_GET_CUR: { + uint16_t wContrast = 0x0080; + memcpy(*data, (uint8_t *)&wContrast, 2); + *len = 2; + } break; + case VIDEO_REQUEST_GET_MIN: { + uint16_t wContrast = 0x0001; + memcpy(*data, (uint8_t *)&wContrast, 2); + *len = 2; + } break; + case VIDEO_REQUEST_GET_MAX: { + uint16_t wContrast = 0x00ff; + memcpy(*data, (uint8_t *)&wContrast, 2); + *len = 2; + } break; + case VIDEO_REQUEST_GET_RES: { + uint16_t wContrast = 0x0001; + memcpy(*data, (uint8_t *)&wContrast, 2); + *len = 2; + } break; + case VIDEO_REQUEST_GET_INFO: + (*data)[0] = 0x03; //struct video_camera_capabilities + *len = 1; + break; + case VIDEO_REQUEST_GET_DEF: { + uint16_t wContrast = 0x0080; + memcpy(*data, (uint8_t *)&wContrast, 2); + *len = 2; + } break; + default: + return -1; + } + break; + case VIDEO_PU_HUE_CONTROL: + switch (setup->bRequest) { + case VIDEO_REQUEST_GET_CUR: { + uint16_t wHue = 0x0080; + memcpy(*data, (uint8_t *)&wHue, 2); + *len = 2; + } break; + case VIDEO_REQUEST_GET_MIN: { + uint16_t wHue = 0x0001; + memcpy(*data, (uint8_t *)&wHue, 2); + *len = 2; + } break; + case VIDEO_REQUEST_GET_MAX: { + uint16_t wHue = 0x00ff; + memcpy(*data, (uint8_t *)&wHue, 2); + *len = 2; + } break; + case VIDEO_REQUEST_GET_RES: { + uint16_t wHue = 0x0001; + memcpy(*data, (uint8_t *)&wHue, 2); + *len = 2; + } break; + case VIDEO_REQUEST_GET_INFO: + (*data)[0] = 0x03; //struct video_camera_capabilities + *len = 1; + break; + case VIDEO_REQUEST_GET_DEF: { + uint16_t wHue = 0x0080; + memcpy(*data, (uint8_t *)&wHue, 2); + *len = 2; + } break; + default: + return -1; + } + break; + case VIDEO_PU_SATURATION_CONTROL: + switch (setup->bRequest) { + case VIDEO_REQUEST_GET_MIN: { + uint16_t wSaturation = 0x0001; + memcpy(*data, (uint8_t *)&wSaturation, 2); + *len = 2; + } break; + case VIDEO_REQUEST_GET_MAX: { + uint16_t wSaturation = 0x00ff; + memcpy(*data, (uint8_t *)&wSaturation, 2); + *len = 2; + } break; + case VIDEO_REQUEST_GET_RES: { + uint16_t wSaturation = 0x0001; + memcpy(*data, (uint8_t *)&wSaturation, 2); + *len = 2; + } break; + case VIDEO_REQUEST_GET_INFO: + (*data)[0] = 0x03; //struct video_camera_capabilities + *len = 1; + break; + case VIDEO_REQUEST_GET_DEF: { + uint16_t wSaturation = 0x0080; + memcpy(*data, (uint8_t *)&wSaturation, 2); + *len = 2; + } break; + default: + return -1; + } + break; + case VIDEO_PU_SHARPNESS_CONTROL: + switch (setup->bRequest) { + case VIDEO_REQUEST_GET_MIN: { + uint16_t wSharpness = 0x0001; + memcpy(*data, (uint8_t *)&wSharpness, 2); + *len = 2; + } break; + case VIDEO_REQUEST_GET_MAX: { + uint16_t wSharpness = 0x00ff; + memcpy(*data, (uint8_t *)&wSharpness, 2); + *len = 2; + } break; + case VIDEO_REQUEST_GET_RES: { + uint16_t wSharpness = 0x0001; + memcpy(*data, (uint8_t *)&wSharpness, 2); + *len = 2; + } break; + case VIDEO_REQUEST_GET_INFO: + (*data)[0] = 0x03; //struct video_camera_capabilities + *len = 1; + break; + case VIDEO_REQUEST_GET_DEF: { + uint16_t wSharpness = 0x0080; + memcpy(*data, (uint8_t *)&wSharpness, 2); + *len = 2; + } break; + default: + return -1; + } + break; + case VIDEO_PU_GAIN_CONTROL: + switch (setup->bRequest) { + case VIDEO_REQUEST_GET_MIN: { + uint16_t wGain = 0; + memcpy(*data, (uint8_t *)&wGain, 2); + *len = 2; + } break; + case VIDEO_REQUEST_GET_MAX: { + uint16_t wGain = 255; + memcpy(*data, (uint8_t *)&wGain, 2); + *len = 2; + } break; + case VIDEO_REQUEST_GET_RES: { + uint16_t wGain = 1; + memcpy(*data, (uint8_t *)&wGain, 2); + *len = 2; + } break; + case VIDEO_REQUEST_GET_INFO: + (*data)[0] = 0x03; //struct video_camera_capabilities + *len = 1; + break; + case VIDEO_REQUEST_GET_DEF: { + uint16_t wGain = 255; + memcpy(*data, (uint8_t *)&wGain, 2); + *len = 2; + } break; + default: + return -1; + } + break; + case VIDEO_PU_WHITE_BALANCE_TEMPERATURE_CONTROL: + switch (setup->bRequest) { + case VIDEO_REQUEST_GET_CUR: { + uint16_t wWhiteBalance_Temprature = 417; + memcpy(*data, (uint8_t *)&wWhiteBalance_Temprature, 2); + *len = 2; + } break; + case VIDEO_REQUEST_GET_MIN: { + uint16_t wWhiteBalance_Temprature = 300; + memcpy(*data, (uint8_t *)&wWhiteBalance_Temprature, 2); + *len = 2; + } break; + case VIDEO_REQUEST_GET_MAX: { + uint16_t wWhiteBalance_Temprature = 600; + memcpy(*data, (uint8_t *)&wWhiteBalance_Temprature, 2); + *len = 2; + } break; + case VIDEO_REQUEST_GET_RES: { + uint16_t wWhiteBalance_Temprature = 1; + memcpy(*data, (uint8_t *)&wWhiteBalance_Temprature, 2); + *len = 2; + } break; + case VIDEO_REQUEST_GET_INFO: + (*data)[0] = 0x03; //struct video_camera_capabilities + *len = 1; + break; + case VIDEO_REQUEST_GET_DEF: { + uint16_t wWhiteBalance_Temprature = 417; + memcpy(*data, (uint8_t *)&wWhiteBalance_Temprature, 2); + *len = 2; + } break; + default: + return -1; + } + break; + case VIDEO_PU_WHITE_BALANCE_TEMPERATURE_AUTO_CONTROL: + switch (setup->bRequest) { + case VIDEO_REQUEST_GET_CUR: { + uint16_t wWhiteBalance_Temprature_Auto = 1; + memcpy(*data, (uint8_t *)&wWhiteBalance_Temprature_Auto, 1); + *len = 1; + } break; + default: + return -1; + } + break; + default: + g_usbd_video[busid].error_code = 0x06; + return -1; + } + break; + case VIDEO_VC_EXTENSION_UNIT_DESCRIPTOR_SUBTYPE: + break; + case VIDEO_VC_ENCODING_UNIT_DESCRIPTOR_SUBTYPE: + break; + + default: + break; + } + } + } + return 0; +} + +static int usbd_video_stream_request_handler(uint8_t busid, struct usb_setup_packet *setup, uint8_t **data, uint32_t *len) +{ + uint8_t control_selector = (uint8_t)(setup->wValue >> 8); + + switch (control_selector) { + case VIDEO_VS_PROBE_CONTROL: + switch (setup->bRequest) { + case VIDEO_REQUEST_SET_CUR: + //memcpy((uint8_t *)&g_usbd_video[busid].probe, *data, setup->wLength); + break; + case VIDEO_REQUEST_GET_CUR: + memcpy(*data, (uint8_t *)&g_usbd_video[busid].probe, setup->wLength); + *len = sizeof(struct video_probe_and_commit_controls); + break; + + case VIDEO_REQUEST_GET_MIN: + case VIDEO_REQUEST_GET_MAX: + case VIDEO_REQUEST_GET_RES: + case VIDEO_REQUEST_GET_DEF: + memcpy(*data, (uint8_t *)&g_usbd_video[busid].probe, setup->wLength); + *len = sizeof(struct video_probe_and_commit_controls); + break; + case VIDEO_REQUEST_GET_LEN: + (*data)[0] = sizeof(struct video_probe_and_commit_controls); + *len = 1; + break; + + case VIDEO_REQUEST_GET_INFO: + (*data)[0] = 0x03; + *len = 1; + break; + + default: + return -1; + } + break; + case VIDEO_VS_COMMIT_CONTROL: + switch (setup->bRequest) { + case VIDEO_REQUEST_SET_CUR: + //memcpy((uint8_t *)&g_usbd_video[busid].commit, *data, setup->wLength); + break; + case VIDEO_REQUEST_GET_CUR: + memcpy(*data, (uint8_t *)&g_usbd_video[busid].commit, setup->wLength); + *len = sizeof(struct video_probe_and_commit_controls); + break; + case VIDEO_REQUEST_GET_MIN: + case VIDEO_REQUEST_GET_MAX: + case VIDEO_REQUEST_GET_RES: + case VIDEO_REQUEST_GET_DEF: + memcpy(*data, (uint8_t *)&g_usbd_video[busid].commit, setup->wLength); + *len = sizeof(struct video_probe_and_commit_controls); + break; + + case VIDEO_REQUEST_GET_LEN: + (*data)[0] = sizeof(struct video_probe_and_commit_controls); + *len = 1; + break; + + case VIDEO_REQUEST_GET_INFO: + (*data)[0] = 0x03; + *len = 1; + break; + + default: + return -1; + } + break; + case VIDEO_VS_STREAM_ERROR_CODE_CONTROL: + switch (setup->bRequest) { + case VIDEO_REQUEST_GET_CUR: + (*data)[0] = g_usbd_video[busid].error_code; + *len = 1; + break; + case VIDEO_REQUEST_GET_INFO: + (*data)[0] = 0x01; + *len = 1; + break; + default: + return -1; + } + break; + default: + break; + } + + return 0; +} + +static int video_class_interface_request_handler(uint8_t busid, struct usb_setup_packet *setup, uint8_t **data, uint32_t *len) +{ + USB_LOG_DBG("Video Class request: " + "bRequest 0x%02x\r\n", + setup->bRequest); + + uint8_t intf_num = (uint8_t)setup->wIndex; + uint8_t entity_id = (uint8_t)(setup->wIndex >> 8); + + if (intf_num == 0) { /* Video Control Interface */ + if (entity_id == 0) { + return usbd_video_control_request_handler(busid, setup, data, len); /* Interface Control Requests */ + } else { + return usbd_video_control_unit_terminal_request_handler(busid, setup, data, len); /* Unit and Terminal Requests */ + } + } else if (intf_num == 1) { /* Video Stream Inteface */ + return usbd_video_stream_request_handler(busid, setup, data, len); /* Interface Stream Requests */ + } + return -1; +} + +static void video_notify_handler(uint8_t busid, uint8_t event, void *arg) +{ + switch (event) { + case USBD_EVENT_RESET: + g_usbd_video[busid].error_code = 0; + g_usbd_video[busid].power_mode = 0; + break; + + case USBD_EVENT_SET_INTERFACE: { + struct usb_interface_descriptor *intf = (struct usb_interface_descriptor *)arg; + if (intf->bAlternateSetting == 1) { + usbd_video_open(busid, intf->bInterfaceNumber); + } else { + usbd_video_close(busid, intf->bInterfaceNumber); + } + } + + break; + default: + break; + } +} + +static void usbd_video_probe_and_commit_controls_init(uint8_t busid, uint32_t dwFrameInterval, uint32_t dwMaxVideoFrameSize, uint32_t dwMaxPayloadTransferSize) +{ + g_usbd_video[busid].probe.hintUnion.bmHint = 0x01; + g_usbd_video[busid].probe.hintUnion1.bmHint = 0; + g_usbd_video[busid].probe.bFormatIndex = 1; + g_usbd_video[busid].probe.bFrameIndex = 1; + g_usbd_video[busid].probe.dwFrameInterval = dwFrameInterval; + g_usbd_video[busid].probe.wKeyFrameRate = 0; + g_usbd_video[busid].probe.wPFrameRate = 0; + g_usbd_video[busid].probe.wCompQuality = 0; + g_usbd_video[busid].probe.wCompWindowSize = 0; + g_usbd_video[busid].probe.wDelay = 0; + g_usbd_video[busid].probe.dwMaxVideoFrameSize = dwMaxVideoFrameSize; + g_usbd_video[busid].probe.dwMaxPayloadTransferSize = dwMaxPayloadTransferSize; + g_usbd_video[busid].probe.dwClockFrequency = 0; + g_usbd_video[busid].probe.bmFramingInfo = 0; + g_usbd_video[busid].probe.bPreferedVersion = 0; + g_usbd_video[busid].probe.bMinVersion = 0; + g_usbd_video[busid].probe.bMaxVersion = 0; + + g_usbd_video[busid].commit.hintUnion.bmHint = 0x01; + g_usbd_video[busid].commit.hintUnion1.bmHint = 0; + g_usbd_video[busid].commit.bFormatIndex = 1; + g_usbd_video[busid].commit.bFrameIndex = 1; + g_usbd_video[busid].commit.dwFrameInterval = dwFrameInterval; + g_usbd_video[busid].commit.wKeyFrameRate = 0; + g_usbd_video[busid].commit.wPFrameRate = 0; + g_usbd_video[busid].commit.wCompQuality = 0; + g_usbd_video[busid].commit.wCompWindowSize = 0; + g_usbd_video[busid].commit.wDelay = 0; + g_usbd_video[busid].commit.dwMaxVideoFrameSize = dwMaxVideoFrameSize; + g_usbd_video[busid].commit.dwMaxPayloadTransferSize = dwMaxPayloadTransferSize; + g_usbd_video[busid].commit.dwClockFrequency = 0; + g_usbd_video[busid].commit.bmFramingInfo = 0; + g_usbd_video[busid].commit.bPreferedVersion = 0; + g_usbd_video[busid].commit.bMinVersion = 0; + g_usbd_video[busid].commit.bMaxVersion = 0; + + g_usbd_video[busid].stream_frameid = 0; + g_usbd_video[busid].stream_headerlen = 12; +} + +struct usbd_interface *usbd_video_init_intf(uint8_t busid, + struct usbd_interface *intf, + uint32_t dwFrameInterval, + uint32_t dwMaxVideoFrameSize, + uint32_t dwMaxPayloadTransferSize) +{ + intf->class_interface_handler = video_class_interface_request_handler; + intf->class_endpoint_handler = NULL; + intf->vendor_handler = NULL; + intf->notify_handler = video_notify_handler; + + g_usbd_video[busid].info[0].bDescriptorSubtype = VIDEO_VC_INPUT_TERMINAL_DESCRIPTOR_SUBTYPE; + g_usbd_video[busid].info[0].bEntityId = 0x01; + g_usbd_video[busid].info[0].wTerminalType = VIDEO_ITT_CAMERA; + g_usbd_video[busid].info[1].bDescriptorSubtype = VIDEO_VC_OUTPUT_TERMINAL_DESCRIPTOR_SUBTYPE; + g_usbd_video[busid].info[1].bEntityId = 0x03; + g_usbd_video[busid].info[1].wTerminalType = 0x00; + g_usbd_video[busid].info[2].bDescriptorSubtype = VIDEO_VC_PROCESSING_UNIT_DESCRIPTOR_SUBTYPE; + g_usbd_video[busid].info[2].bEntityId = 0x02; + g_usbd_video[busid].info[2].wTerminalType = 0x00; + + usbd_video_probe_and_commit_controls_init(busid, dwFrameInterval, dwMaxVideoFrameSize, dwMaxPayloadTransferSize); + return intf; +} + +bool usbd_video_stream_split_transfer(uint8_t busid, uint8_t ep) +{ + struct video_payload_header *header; + static uint32_t offset = 0; + static uint32_t len = 0; + + if (g_usbd_video[busid].stream_finish) { + g_usbd_video[busid].stream_finish = false; + return true; + } + + offset = g_usbd_video[busid].stream_offset; + + len = MIN(g_usbd_video[busid].stream_len, + g_usbd_video[busid].probe.dwMaxPayloadTransferSize - + g_usbd_video[busid].stream_headerlen); + + if (g_usbd_video[busid].do_copy) { + header = (struct video_payload_header *)&g_usbd_video[busid].ep_buf[0]; + usb_memcpy(&g_usbd_video[busid].ep_buf[g_usbd_video[busid].stream_headerlen], &g_usbd_video[busid].stream_buf[offset], len); + } else { + header = (struct video_payload_header *)&g_usbd_video[busid].stream_buf[offset - g_usbd_video[busid].stream_headerlen]; + } + + memset(header, 0, g_usbd_video[busid].stream_headerlen); + header->bHeaderLength = g_usbd_video[busid].stream_headerlen; + header->headerInfoUnion.bmheaderInfo = 0; + header->headerInfoUnion.headerInfoBits.endOfHeader = 1; + header->headerInfoUnion.headerInfoBits.endOfFrame = 0; + header->headerInfoUnion.headerInfoBits.frameIdentifier = g_usbd_video[busid].stream_frameid; + + g_usbd_video[busid].stream_offset += len; + g_usbd_video[busid].stream_len -= len; + + if (g_usbd_video[busid].stream_len == 0) { + header->headerInfoUnion.headerInfoBits.endOfFrame = 1; + g_usbd_video[busid].stream_frameid ^= 1; + g_usbd_video[busid].stream_finish = true; + } + + if (g_usbd_video[busid].do_copy) { + usbd_ep_start_write(busid, ep, + g_usbd_video[busid].ep_buf, + g_usbd_video[busid].stream_headerlen + len); + } else { + usbd_ep_start_write(busid, ep, + &g_usbd_video[busid].stream_buf[offset - g_usbd_video[busid].stream_headerlen], + g_usbd_video[busid].stream_headerlen + len); + } + + return false; +} + +int usbd_video_stream_start_write(uint8_t busid, uint8_t ep, uint8_t *ep_buf, uint8_t *stream_buf, uint32_t stream_len, bool do_copy) +{ + struct video_payload_header *header; + + if ((usb_device_is_configured(busid) == 0) || (stream_len == 0)) { + return -1; + } + + g_usbd_video[busid].ep_buf = ep_buf; + g_usbd_video[busid].stream_buf = stream_buf; + g_usbd_video[busid].stream_len = stream_len; + g_usbd_video[busid].stream_offset = 0; + g_usbd_video[busid].stream_finish = false; + g_usbd_video[busid].do_copy = do_copy; + + uint32_t len = MIN(g_usbd_video[busid].stream_len, + g_usbd_video[busid].probe.dwMaxPayloadTransferSize - + g_usbd_video[busid].stream_headerlen); + + header = (struct video_payload_header *)&ep_buf[0]; + header->bHeaderLength = g_usbd_video[busid].stream_headerlen; + header->headerInfoUnion.bmheaderInfo = 0; + header->headerInfoUnion.headerInfoBits.endOfHeader = 1; + header->headerInfoUnion.headerInfoBits.endOfFrame = 0; + header->headerInfoUnion.headerInfoBits.frameIdentifier = g_usbd_video[busid].stream_frameid; + + usb_memcpy(&ep_buf[g_usbd_video[busid].stream_headerlen], stream_buf, len); + g_usbd_video[busid].stream_offset += len; + g_usbd_video[busid].stream_len -= len; + + usbd_ep_start_write(busid, ep, ep_buf, g_usbd_video[busid].stream_headerlen + len); + return 0; +} + +__WEAK void usbd_video_open(uint8_t busid, uint8_t intf) +{ + (void)busid; + (void)intf; +} + +__WEAK void usbd_video_close(uint8_t busid, uint8_t intf) +{ + (void)busid; + (void)intf; +} \ No newline at end of file diff --git a/kernel/cherryusb/class/video/usbd_video.h b/kernel/cherryusb/class/video/usbd_video.h new file mode 100644 index 0000000..a2061fd --- /dev/null +++ b/kernel/cherryusb/class/video/usbd_video.h @@ -0,0 +1,31 @@ +/* + * Copyright (c) 2022, sakumisu + * + * SPDX-License-Identifier: Apache-2.0 + */ +#ifndef USBD_VIDEO_H +#define USBD_VIDEO_H + +#include "usb_video.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* Init video interface driver */ +struct usbd_interface *usbd_video_init_intf(uint8_t busid, struct usbd_interface *intf, + uint32_t dwFrameInterval, + uint32_t dwMaxVideoFrameSize, + uint32_t dwMaxPayloadTransferSize); + +void usbd_video_open(uint8_t busid, uint8_t intf); +void usbd_video_close(uint8_t busid, uint8_t intf); + +bool usbd_video_stream_split_transfer(uint8_t busid, uint8_t ep); +int usbd_video_stream_start_write(uint8_t busid, uint8_t ep, uint8_t *ep_buf, uint8_t *stream_buf, uint32_t stream_len, bool do_copy); + +#ifdef __cplusplus +} +#endif + +#endif /* USBD_VIDEO_H */ diff --git a/kernel/cherryusb/class/video/usbh_video.c b/kernel/cherryusb/class/video/usbh_video.c new file mode 100644 index 0000000..8b7863c --- /dev/null +++ b/kernel/cherryusb/class/video/usbh_video.c @@ -0,0 +1,576 @@ +/* + * Copyright (c) 2022, sakumisu + * + * SPDX-License-Identifier: Apache-2.0 + */ +#include "usbh_core.h" +#include "usbh_video.h" + +#undef USB_DBG_TAG +#define USB_DBG_TAG "usbh_video" +#include "usb_log.h" + +#define DEV_FORMAT "/dev/video%d" + +/* general descriptor field offsets */ +#define DESC_bLength 0 /** Length offset */ +#define DESC_bDescriptorType 1 /** Descriptor type offset */ +#define DESC_bDescriptorSubType 2 /** Descriptor subtype offset */ +#define DESC_bNumFormats 3 /** Descriptor numformat offset */ +#define DESC_bNumFrameDescriptors 4 /** Descriptor numframe offset */ +#define DESC_bFormatIndex 3 /** Descriptor format index offset */ +#define DESC_bFrameIndex 3 /** Descriptor frame index offset */ + +/* interface descriptor field offsets */ +#define INTF_DESC_bInterfaceNumber 2 /** Interface number offset */ +#define INTF_DESC_bAlternateSetting 3 /** Alternate setting offset */ + +USB_NOCACHE_RAM_SECTION USB_MEM_ALIGNX uint8_t g_video_buf[USB_ALIGN_UP(128, CONFIG_USB_ALIGN_SIZE)]; + +static const char *format_type[] = { "uncompressed", "mjpeg" }; + +static struct usbh_video g_video_class[CONFIG_USBHOST_MAX_VIDEO_CLASS]; +static uint32_t g_devinuse = 0; + +static struct usbh_video *usbh_video_class_alloc(void) +{ + uint8_t devno; + + for (devno = 0; devno < CONFIG_USBHOST_MAX_VIDEO_CLASS; devno++) { + if ((g_devinuse & (1U << devno)) == 0) { + g_devinuse |= (1U << devno); + memset(&g_video_class[devno], 0, sizeof(struct usbh_video)); + g_video_class[devno].minor = devno; + return &g_video_class[devno]; + } + } + return NULL; +} + +static void usbh_video_class_free(struct usbh_video *video_class) +{ + uint8_t devno = video_class->minor; + + if (devno < 32) { + g_devinuse &= ~(1U << devno); + } + memset(video_class, 0, sizeof(struct usbh_video)); +} + +int usbh_video_get(struct usbh_video *video_class, uint8_t request, uint8_t intf, uint8_t entity_id, uint8_t cs, uint8_t *buf, uint16_t len) +{ + struct usb_setup_packet *setup; + int ret; + uint8_t retry; + + if (!video_class || !video_class->hport) { + return -USB_ERR_INVAL; + } + setup = video_class->hport->setup; + + setup->bmRequestType = USB_REQUEST_DIR_IN | USB_REQUEST_CLASS | USB_REQUEST_RECIPIENT_INTERFACE; + setup->bRequest = request; + setup->wValue = cs << 8; + setup->wIndex = (entity_id << 8) | intf; + setup->wLength = len; + + retry = 0; + while (1) { + ret = usbh_control_transfer(video_class->hport, setup, g_video_buf); + if (ret > 0) { + break; + } + retry++; + + if (retry == 3) { + return ret; + } + } + + if (buf) { + memcpy(buf, g_video_buf, len); + } + + return ret; +} + +int usbh_video_set(struct usbh_video *video_class, uint8_t request, uint8_t intf, uint8_t entity_id, uint8_t cs, uint8_t *buf, uint16_t len) +{ + struct usb_setup_packet *setup; + int ret; + + if (!video_class || !video_class->hport) { + return -USB_ERR_INVAL; + } + setup = video_class->hport->setup; + + setup->bmRequestType = USB_REQUEST_DIR_OUT | USB_REQUEST_CLASS | USB_REQUEST_RECIPIENT_INTERFACE; + setup->bRequest = request; + setup->wValue = cs << 8; + setup->wIndex = (entity_id << 8) | intf; + setup->wLength = len; + + memcpy(g_video_buf, buf, len); + + ret = usbh_control_transfer(video_class->hport, setup, g_video_buf); + usb_osal_msleep(50); + return ret; +} + +int usbh_videostreaming_get_cur_probe(struct usbh_video *video_class) +{ + return usbh_video_get(video_class, VIDEO_REQUEST_GET_CUR, video_class->data_intf, 0x00, VIDEO_VS_PROBE_CONTROL, (uint8_t *)&video_class->probe, 26); +} + +int usbh_videostreaming_set_cur_probe(struct usbh_video *video_class, uint8_t formatindex, uint8_t frameindex, uint32_t dwFrameInterval) +{ + video_class->probe.bFormatIndex = formatindex; + video_class->probe.bFrameIndex = frameindex; + video_class->probe.dwMaxPayloadTransferSize = 0; + video_class->probe.dwFrameInterval = dwFrameInterval; + return usbh_video_set(video_class, VIDEO_REQUEST_SET_CUR, video_class->data_intf, 0x00, VIDEO_VS_PROBE_CONTROL, (uint8_t *)&video_class->probe, 26); +} + +int usbh_videostreaming_set_cur_commit(struct usbh_video *video_class, uint8_t formatindex, uint8_t frameindex) +{ + memcpy(&video_class->commit, &video_class->probe, sizeof(struct video_probe_and_commit_controls)); + video_class->commit.bFormatIndex = formatindex; + video_class->commit.bFrameIndex = frameindex; + return usbh_video_set(video_class, VIDEO_REQUEST_SET_CUR, video_class->data_intf, 0x00, VIDEO_VS_COMMIT_CONTROL, (uint8_t *)&video_class->commit, 26); +} + +int usbh_video_open(struct usbh_video *video_class, + uint8_t format_type, + uint16_t wWidth, + uint16_t wHeight, + uint8_t altsetting) +{ + struct usb_setup_packet *setup; + struct usb_endpoint_descriptor *ep_desc; + uint8_t mult; + uint16_t mps; + int ret; + bool found = false; + uint8_t formatidx = 0; + uint8_t frameidx = 0; + uint32_t dwDefaultFrameInterval = 0; + uint8_t step; + + if (!video_class || !video_class->hport) { + return -USB_ERR_INVAL; + } + setup = video_class->hport->setup; + + if (video_class->is_opened) { + return 0; + } + + for (uint8_t i = 0; i < video_class->num_of_formats; i++) { + if (format_type == video_class->format[i].format_type) { + formatidx = i + 1; + for (uint8_t j = 0; j < video_class->format[i].num_of_frames; j++) { + if ((wWidth == video_class->format[i].frame[j].wWidth) && + (wHeight == video_class->format[i].frame[j].wHeight)) { + frameidx = j + 1; + dwDefaultFrameInterval = video_class->format[i].frame[j].dwDefaultFrameInterval; + found = true; + goto dev_found; + } + } + } + } + +dev_found: + if (found == false) { + return -USB_ERR_NODEV; + } + + if (altsetting > (video_class->num_of_intf_altsettings - 1)) { + return -USB_ERR_INVAL; + } + + /* Open video step: + * Get CUR request (probe) + * Set CUR request (probe) + * Get CUR request (probe) + * Get MAX request (probe) + * Get MIN request (probe) + * Get CUR request (probe) + * Set CUR request (commit) + * + */ + step = 0; + ret = usbh_videostreaming_get_cur_probe(video_class); + if (ret < 0) { + goto errout; + } + + step = 1; + ret = usbh_videostreaming_set_cur_probe(video_class, formatidx, frameidx, dwDefaultFrameInterval); + if (ret < 0) { + goto errout; + } + + step = 2; + ret = usbh_videostreaming_get_cur_probe(video_class); + if (ret < 0) { + goto errout; + } + + step = 3; + ret = usbh_video_get(video_class, VIDEO_REQUEST_GET_MAX, video_class->data_intf, 0x00, VIDEO_VS_PROBE_CONTROL, NULL, 26); + if (ret < 0) { + goto errout; + } + + step = 4; + ret = usbh_video_get(video_class, VIDEO_REQUEST_GET_MIN, video_class->data_intf, 0x00, VIDEO_VS_PROBE_CONTROL, NULL, 26); + if (ret < 0) { + goto errout; + } + + step = 5; + ret = usbh_videostreaming_set_cur_probe(video_class, formatidx, frameidx, dwDefaultFrameInterval); + if (ret < 0) { + goto errout; + } + + step = 6; + ret = usbh_videostreaming_get_cur_probe(video_class); + if (ret < 0) { + goto errout; + } + + step = 7; + ret = usbh_videostreaming_set_cur_commit(video_class, formatidx, frameidx); + if (ret < 0) { + goto errout; + } + + step = 8; + if (!video_class->is_bulk) { + setup->bmRequestType = USB_REQUEST_DIR_OUT | USB_REQUEST_STANDARD | USB_REQUEST_RECIPIENT_INTERFACE; + setup->bRequest = USB_REQUEST_SET_INTERFACE; + setup->wValue = altsetting; + setup->wIndex = video_class->data_intf; + setup->wLength = 0; + + ret = usbh_control_transfer(video_class->hport, setup, NULL); + if (ret < 0) { + goto errout; + } + + ep_desc = &video_class->hport->config.intf[video_class->data_intf].altsetting[altsetting].ep[0].ep_desc; + mult = (ep_desc->wMaxPacketSize & USB_MAXPACKETSIZE_ADDITIONAL_TRANSCATION_MASK) >> USB_MAXPACKETSIZE_ADDITIONAL_TRANSCATION_SHIFT; + mps = ep_desc->wMaxPacketSize & USB_MAXPACKETSIZE_MASK; + if (ep_desc->bEndpointAddress & 0x80) { + video_class->isoin_mps = mps * (mult + 1); + USBH_EP_INIT(video_class->isoin, ep_desc); + } else { + return -USB_ERR_NODEV; + } + } else { + ep_desc = &video_class->hport->config.intf[video_class->data_intf].altsetting[0].ep[0].ep_desc; + USBH_EP_INIT(video_class->bulkin, ep_desc); + } + + USB_LOG_INFO("Open video and select formatidx:%u, frameidx:%u, altsetting:%u\r\n", formatidx, frameidx, altsetting); + video_class->is_opened = true; + video_class->current_format = format_type; + return ret; + +errout: + USB_LOG_ERR("Fail to open video in step %u\r\n", step); + return ret; +} + +int usbh_video_close(struct usbh_video *video_class) +{ + struct usb_setup_packet *setup; + int ret = 0; + + if (!video_class || !video_class->hport) { + return -USB_ERR_INVAL; + } + setup = video_class->hport->setup; + + USB_LOG_INFO("Close video device\r\n"); + + video_class->is_opened = false; + + if (video_class->is_bulk) { + setup->bmRequestType = USB_REQUEST_DIR_OUT | USB_REQUEST_STANDARD | USB_REQUEST_RECIPIENT_ENDPOINT; + setup->bRequest = USB_REQUEST_CLEAR_FEATURE; + setup->wValue = USB_FEATURE_ENDPOINT_HALT; + setup->wIndex = video_class->bulkin->bEndpointAddress; + setup->wLength = 0; + } else { + setup->bmRequestType = USB_REQUEST_DIR_OUT | USB_REQUEST_STANDARD | USB_REQUEST_RECIPIENT_INTERFACE; + setup->bRequest = USB_REQUEST_SET_INTERFACE; + setup->wValue = 0; + setup->wIndex = video_class->data_intf; + setup->wLength = 0; + } + + ret = usbh_control_transfer(video_class->hport, setup, NULL); + if (ret < 0) { + return ret; + } + + return ret; +} + +void usbh_video_list_info(struct usbh_video *video_class) +{ + struct usb_endpoint_descriptor *ep_desc; + + USB_LOG_INFO("============= Video device information ===================\r\n"); + USB_LOG_RAW("bcdVDC:%04x\r\n", video_class->bcdVDC); + USB_LOG_RAW("Num of altsettings:%u (%s mode)\r\n", video_class->num_of_intf_altsettings, video_class->num_of_intf_altsettings == 1 ? "bulk" : "iso"); + + video_class->is_bulk = video_class->num_of_intf_altsettings == 1 ? true : false; + + if (video_class->is_bulk) { + ep_desc = &video_class->hport->config.intf[video_class->data_intf].altsetting[0].ep[0].ep_desc; + USB_LOG_RAW("Ep=%02x Attr=%02u Mps=%d Interval=%02u Mult=%02u\r\n", + ep_desc->bEndpointAddress, + ep_desc->bmAttributes, + USB_GET_MAXPACKETSIZE(ep_desc->wMaxPacketSize), + ep_desc->bInterval, + USB_GET_MULT(ep_desc->wMaxPacketSize)); + } else { + for (uint8_t i = 0; i < video_class->num_of_intf_altsettings; i++) { + if (i == 0) { + USB_LOG_RAW("Ingore altsetting 0\r\n"); + continue; + } + ep_desc = &video_class->hport->config.intf[video_class->data_intf].altsetting[i].ep[0].ep_desc; + + USB_LOG_RAW("Altsetting:%u, Ep=%02x Attr=%02u Mps=%d Interval=%02u Mult=%02u\r\n", + i, + ep_desc->bEndpointAddress, + ep_desc->bmAttributes, + USB_GET_MAXPACKETSIZE(ep_desc->wMaxPacketSize), + ep_desc->bInterval, + USB_GET_MULT(ep_desc->wMaxPacketSize)); + } + } + + USB_LOG_RAW("bNumFormats:%u\r\n", video_class->num_of_formats); + for (uint8_t i = 0; i < video_class->num_of_formats; i++) { + USB_LOG_RAW(" FormatIndex:%u\r\n", i + 1); + USB_LOG_RAW(" FormatType:%s\r\n", format_type[video_class->format[i].format_type]); + USB_LOG_RAW(" bNumFrames:%u\r\n", video_class->format[i].num_of_frames); + USB_LOG_RAW(" Resolution:\r\n"); + for (uint8_t j = 0; j < video_class->format[i].num_of_frames; j++) { + USB_LOG_RAW(" FrameIndex:%u\r\n", j + 1); + USB_LOG_RAW(" wWidth: %d, wHeight: %d, fps: %d\r\n", + video_class->format[i].frame[j].wWidth, + video_class->format[i].frame[j].wHeight, + (1000 / (video_class->format[i].frame[j].dwDefaultFrameInterval / 10000))); + } + } + + USB_LOG_INFO("============= Video device information ===================\r\n"); +} + +static int usbh_video_ctrl_connect(struct usbh_hubport *hport, uint8_t intf) +{ + int ret; + uint8_t cur_iface = 0xff; + // uint8_t cur_alt_setting = 0xff; + uint8_t frame_index = 0xff; + uint8_t format_index = 0xff; + uint8_t num_of_frames = 0xff; + uint8_t *p; + + struct usbh_video *video_class = usbh_video_class_alloc(); + if (video_class == NULL) { + USB_LOG_ERR("Fail to alloc video_class\r\n"); + return -USB_ERR_NOMEM; + } + + video_class->hport = hport; + video_class->ctrl_intf = intf; + video_class->data_intf = intf + 1; + video_class->num_of_intf_altsettings = hport->config.intf[intf + 1].altsetting_num; + + hport->config.intf[intf].priv = video_class; + + ret = usbh_video_close(video_class); + if (ret < 0) { + USB_LOG_ERR("Fail to close video device\r\n"); + return ret; + } + + p = hport->raw_config_desc; + while (p[DESC_bLength]) { + switch (p[DESC_bDescriptorType]) { + case USB_DESCRIPTOR_TYPE_INTERFACE: + cur_iface = p[INTF_DESC_bInterfaceNumber]; + //cur_alt_setting = p[INTF_DESC_bAlternateSetting]; + break; + case USB_DESCRIPTOR_TYPE_ENDPOINT: + //ep_desc = (struct usb_endpoint_descriptor *)p; + break; + case VIDEO_CS_INTERFACE_DESCRIPTOR_TYPE: + if (cur_iface == video_class->ctrl_intf) { + switch (p[DESC_bDescriptorSubType]) { + case VIDEO_VC_HEADER_DESCRIPTOR_SUBTYPE: + video_class->bcdVDC = ((uint16_t)p[4] << 8) | (uint16_t)p[3]; + break; + case VIDEO_VC_INPUT_TERMINAL_DESCRIPTOR_SUBTYPE: + break; + case VIDEO_VC_OUTPUT_TERMINAL_DESCRIPTOR_SUBTYPE: + break; + case VIDEO_VC_PROCESSING_UNIT_DESCRIPTOR_SUBTYPE: + break; + + default: + break; + } + } else if (cur_iface == video_class->data_intf) { + switch (p[DESC_bDescriptorSubType]) { + case VIDEO_VS_INPUT_HEADER_DESCRIPTOR_SUBTYPE: + video_class->num_of_formats = p[DESC_bNumFormats]; + break; + case VIDEO_VS_FORMAT_UNCOMPRESSED_DESCRIPTOR_SUBTYPE: + format_index = p[DESC_bFormatIndex]; + num_of_frames = p[DESC_bNumFrameDescriptors]; + + USB_ASSERT(format_index != 0); + USB_ASSERT(format_index <= CONFIG_USBHOST_VIDEO_MAX_FORMATS); + + video_class->format[format_index - 1].num_of_frames = num_of_frames; + video_class->format[format_index - 1].format_type = USBH_VIDEO_FORMAT_UNCOMPRESSED; + break; + case VIDEO_VS_FORMAT_MJPEG_DESCRIPTOR_SUBTYPE: + format_index = p[DESC_bFormatIndex]; + num_of_frames = p[DESC_bNumFrameDescriptors]; + + USB_ASSERT(format_index != 0); + USB_ASSERT(format_index <= CONFIG_USBHOST_VIDEO_MAX_FORMATS); + + video_class->format[format_index - 1].num_of_frames = num_of_frames; + video_class->format[format_index - 1].format_type = USBH_VIDEO_FORMAT_MJPEG; + break; + case VIDEO_VS_FRAME_UNCOMPRESSED_DESCRIPTOR_SUBTYPE: + frame_index = p[DESC_bFrameIndex]; + + USB_ASSERT(format_index != 0); + USB_ASSERT(frame_index != 0); + USB_ASSERT(format_index <= CONFIG_USBHOST_VIDEO_MAX_FORMATS); + USB_ASSERT(frame_index <= CONFIG_USBHOST_VIDEO_MAX_FRAMES); + + video_class->format[format_index - 1].frame[frame_index - 1].wWidth = ((struct video_cs_if_vs_frame_uncompressed_descriptor *)p)->wWidth; + video_class->format[format_index - 1].frame[frame_index - 1].wHeight = ((struct video_cs_if_vs_frame_uncompressed_descriptor *)p)->wHeight; + video_class->format[format_index - 1].frame[frame_index - 1].dwDefaultFrameInterval = ((struct video_cs_if_vs_frame_uncompressed_descriptor *)p)->dwDefaultFrameInterval; + break; + case VIDEO_VS_FRAME_MJPEG_DESCRIPTOR_SUBTYPE: + frame_index = p[DESC_bFrameIndex]; + + USB_ASSERT(format_index != 0); + USB_ASSERT(frame_index != 0); + USB_ASSERT(format_index <= CONFIG_USBHOST_VIDEO_MAX_FORMATS); + USB_ASSERT(frame_index <= CONFIG_USBHOST_VIDEO_MAX_FRAMES); + + video_class->format[format_index - 1].frame[frame_index - 1].wWidth = ((struct video_cs_if_vs_frame_mjpeg_descriptor *)p)->wWidth; + video_class->format[format_index - 1].frame[frame_index - 1].wHeight = ((struct video_cs_if_vs_frame_mjpeg_descriptor *)p)->wHeight; + video_class->format[format_index - 1].frame[frame_index - 1].dwDefaultFrameInterval = ((struct video_cs_if_vs_frame_mjpeg_descriptor *)p)->dwDefaultFrameInterval; + break; + default: + break; + } + } + + break; + + default: + break; + } + /* skip to next descriptor */ + p += p[DESC_bLength]; + } + + usbh_video_list_info(video_class); + + snprintf(hport->config.intf[intf].devname, CONFIG_USBHOST_DEV_NAMELEN, DEV_FORMAT, video_class->minor); + + USB_LOG_INFO("Register Video Class:%s\r\n", hport->config.intf[intf].devname); + + usbh_video_run(video_class); + return ret; +} + +static int usbh_video_ctrl_disconnect(struct usbh_hubport *hport, uint8_t intf) +{ + int ret = 0; + + struct usbh_video *video_class = (struct usbh_video *)hport->config.intf[intf].priv; + + if (video_class) { + if (hport->config.intf[intf].devname[0] != '\0') { + usb_osal_thread_schedule_other(); + USB_LOG_INFO("Unregister Video Class:%s\r\n", hport->config.intf[intf].devname); + usbh_video_stop(video_class); + } + + usbh_video_class_free(video_class); + } + + return ret; +} + +static int usbh_video_streaming_connect(struct usbh_hubport *hport, uint8_t intf) +{ + (void)hport; + (void)intf; + return 0; +} + +static int usbh_video_streaming_disconnect(struct usbh_hubport *hport, uint8_t intf) +{ + (void)hport; + (void)intf; + return 0; +} + +__WEAK void usbh_video_run(struct usbh_video *video_class) +{ + (void)video_class; +} + +__WEAK void usbh_video_stop(struct usbh_video *video_class) +{ + (void)video_class; +} + +const struct usbh_class_driver video_ctrl_class_driver = { + .driver_name = "video_ctrl", + .connect = usbh_video_ctrl_connect, + .disconnect = usbh_video_ctrl_disconnect +}; + +const struct usbh_class_driver video_streaming_class_driver = { + .driver_name = "video_streaming", + .connect = usbh_video_streaming_connect, + .disconnect = usbh_video_streaming_disconnect +}; + +CLASS_INFO_DEFINE const struct usbh_class_info video_ctrl_class_info = { + .match_flags = USB_CLASS_MATCH_INTF_CLASS | USB_CLASS_MATCH_INTF_SUBCLASS | USB_CLASS_MATCH_INTF_PROTOCOL, + .bInterfaceClass = USB_DEVICE_CLASS_VIDEO, + .bInterfaceSubClass = VIDEO_SC_VIDEOCONTROL, + .bInterfaceProtocol = VIDEO_PC_PROTOCOL_UNDEFINED, + .id_table = NULL, + .class_driver = &video_ctrl_class_driver +}; + +CLASS_INFO_DEFINE const struct usbh_class_info video_streaming_class_info = { + .match_flags = USB_CLASS_MATCH_INTF_CLASS | USB_CLASS_MATCH_INTF_SUBCLASS | USB_CLASS_MATCH_INTF_PROTOCOL, + .bInterfaceClass = USB_DEVICE_CLASS_VIDEO, + .bInterfaceSubClass = VIDEO_SC_VIDEOSTREAMING, + .bInterfaceProtocol = VIDEO_PC_PROTOCOL_UNDEFINED, + .id_table = NULL, + .class_driver = &video_streaming_class_driver +}; diff --git a/kernel/cherryusb/class/video/usbh_video.h b/kernel/cherryusb/class/video/usbh_video.h new file mode 100644 index 0000000..b1ae438 --- /dev/null +++ b/kernel/cherryusb/class/video/usbh_video.h @@ -0,0 +1,94 @@ +/* + * Copyright (c) 2022, sakumisu + * + * SPDX-License-Identifier: Apache-2.0 + */ +#ifndef USBH_VIDEO_H +#define USBH_VIDEO_H + +#include "usb_video.h" + +#define USBH_VIDEO_FORMAT_UNCOMPRESSED 0 +#define USBH_VIDEO_FORMAT_MJPEG 1 + +#ifndef CONFIG_USBHOST_VIDEO_MAX_FRAMES +#define CONFIG_USBHOST_VIDEO_MAX_FRAMES 12 +#endif + +#ifndef CONFIG_USBHOST_VIDEO_MAX_FORMATS +#define CONFIG_USBHOST_VIDEO_MAX_FORMATS 3 +#endif + +struct usbh_video_resolution { + uint16_t wWidth; + uint16_t wHeight; + uint32_t dwDefaultFrameInterval; +}; + +struct usbh_video_format { + struct usbh_video_resolution frame[CONFIG_USBHOST_VIDEO_MAX_FRAMES]; + uint8_t format_type; + uint8_t num_of_frames; +}; + +struct usbh_videoframe { + uint8_t *frame_buf; + uint32_t frame_bufsize; + uint32_t frame_format; + uint32_t frame_size; +}; + +struct usbh_videostreaming { + struct usbh_videoframe *frame; + uint32_t frame_format; + uint32_t bufoffset; + uint16_t width; + uint16_t height; +}; + +struct usbh_video { + struct usbh_hubport *hport; + struct usb_endpoint_descriptor *isoin; /* ISO IN endpoint */ + struct usb_endpoint_descriptor *bulkin; /* Bulk IN endpoint */ + + uint8_t ctrl_intf; /* interface number */ + uint8_t data_intf; /* interface number */ + uint8_t minor; + struct video_probe_and_commit_controls probe; + struct video_probe_and_commit_controls commit; + uint16_t isoin_mps; + bool is_opened; + uint8_t current_format; + bool is_bulk; + uint16_t bcdVDC; + uint8_t num_of_intf_altsettings; + uint8_t num_of_formats; + struct usbh_video_format format[CONFIG_USBHOST_VIDEO_MAX_FORMATS]; + + void *user_data; +}; + +#ifdef __cplusplus +extern "C" { +#endif + +int usbh_video_get(struct usbh_video *video_class, uint8_t request, uint8_t intf, uint8_t entity_id, uint8_t cs, uint8_t *buf, uint16_t len); +int usbh_video_set(struct usbh_video *video_class, uint8_t request, uint8_t intf, uint8_t entity_id, uint8_t cs, uint8_t *buf, uint16_t len); + +int usbh_video_open(struct usbh_video *video_class, + uint8_t format_type, + uint16_t wWidth, + uint16_t wHeight, + uint8_t altsetting); +int usbh_video_close(struct usbh_video *video_class); + +void usbh_video_list_info(struct usbh_video *video_class); + +void usbh_video_run(struct usbh_video *video_class); +void usbh_video_stop(struct usbh_video *video_class); + +#ifdef __cplusplus +} +#endif + +#endif /* USBH_VIDEO_H */ diff --git a/kernel/cherryusb/class/wireless/ndis.h b/kernel/cherryusb/class/wireless/ndis.h new file mode 100644 index 0000000..80a6e66 --- /dev/null +++ b/kernel/cherryusb/class/wireless/ndis.h @@ -0,0 +1,270 @@ +/* This file has been prepared for Doxygen automatic documentation generation.*/ +/*! \file ndis.h *************************************************************** + * + * \brief + * This file contains the possible external configuration of the USB. + * + * \addtogroup usbstick + * + * + ******************************************************************************/ + +/** + \ingroup usbstick + \defgroup RNDIS RNDIS Support + @{ + */ + +/* + * ndis.h + * + * Modified by Colin O'Flynn + * ntddndis.h modified by Benedikt Spranger + * + * Thanks to the cygwin development team, + * espacially to Casper S. Hornstrup + * + * THIS SOFTWARE IS NOT COPYRIGHTED + * + * This source code is offered for use in the public domain. You may + * use, modify or distribute it freely. + * + * This code is distributed in the hope that it will be useful but + * WITHOUT ANY WARRANTY. ALL WARRANTIES, EXPRESS OR IMPLIED ARE HEREBY + * DISCLAIMED. This includes but is not limited to warranties of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. + * + */ + +#ifndef _LINUX_NDIS_H +#define _LINUX_NDIS_H + +#define NDIS_STATUS_MULTICAST_FULL 0xC0010009 +#define NDIS_STATUS_MULTICAST_EXISTS 0xC001000A +#define NDIS_STATUS_MULTICAST_NOT_FOUND 0xC001000B + +/* from drivers/net/sk98lin/h/skgepnmi.h */ +#define OID_PNP_CAPABILITIES 0xFD010100 +#define OID_PNP_SET_POWER 0xFD010101 +#define OID_PNP_QUERY_POWER 0xFD010102 +#define OID_PNP_ADD_WAKE_UP_PATTERN 0xFD010103 +#define OID_PNP_REMOVE_WAKE_UP_PATTERN 0xFD010104 +#define OID_PNP_ENABLE_WAKE_UP 0xFD010106 + +enum NDIS_DEVICE_POWER_STATE { + NdisDeviceStateUnspecified = 0, + NdisDeviceStateD0, + NdisDeviceStateD1, + NdisDeviceStateD2, + NdisDeviceStateD3, + NdisDeviceStateMaximum +}; + +struct NDIS_PM_WAKE_UP_CAPABILITIES { + enum NDIS_DEVICE_POWER_STATE MinMagicPacketWakeUp; + enum NDIS_DEVICE_POWER_STATE MinPatternWakeUp; + enum NDIS_DEVICE_POWER_STATE MinLinkChangeWakeUp; +}; + +/* NDIS_PNP_CAPABILITIES.Flags constants */ +#define NDIS_DEVICE_WAKE_UP_ENABLE 0x00000001 +#define NDIS_DEVICE_WAKE_ON_PATTERN_MATCH_ENABLE 0x00000002 +#define NDIS_DEVICE_WAKE_ON_MAGIC_PACKET_ENABLE 0x00000004 + +/* +struct NDIS_PNP_CAPABILITIES { + __le32 Flags; + struct NDIS_PM_WAKE_UP_CAPABILITIES WakeUpCapabilities; +}; + +struct NDIS_PM_PACKET_PATTERN { + __le32 Priority; + __le32 Reserved; + __le32 MaskSize; + __le32 PatternOffset; + __le32 PatternSize; + __le32 PatternFlags; +}; +*/ + +/* Required Object IDs (OIDs) */ +#define OID_GEN_SUPPORTED_LIST 0x00010101 +#define OID_GEN_HARDWARE_STATUS 0x00010102 +#define OID_GEN_MEDIA_SUPPORTED 0x00010103 +#define OID_GEN_MEDIA_IN_USE 0x00010104 +#define OID_GEN_MAXIMUM_LOOKAHEAD 0x00010105 +#define OID_GEN_MAXIMUM_FRAME_SIZE 0x00010106 +#define OID_GEN_LINK_SPEED 0x00010107 +#define OID_GEN_TRANSMIT_BUFFER_SPACE 0x00010108 +#define OID_GEN_RECEIVE_BUFFER_SPACE 0x00010109 +#define OID_GEN_TRANSMIT_BLOCK_SIZE 0x0001010A +#define OID_GEN_RECEIVE_BLOCK_SIZE 0x0001010B +#define OID_GEN_VENDOR_ID 0x0001010C +#define OID_GEN_VENDOR_DESCRIPTION 0x0001010D +#define OID_GEN_CURRENT_PACKET_FILTER 0x0001010E +#define OID_GEN_CURRENT_LOOKAHEAD 0x0001010F +#define OID_GEN_DRIVER_VERSION 0x00010110 +#define OID_GEN_MAXIMUM_TOTAL_SIZE 0x00010111 +#define OID_GEN_PROTOCOL_OPTIONS 0x00010112 +#define OID_GEN_MAC_OPTIONS 0x00010113 +#define OID_GEN_MEDIA_CONNECT_STATUS 0x00010114 +#define OID_GEN_MAXIMUM_SEND_PACKETS 0x00010115 +#define OID_GEN_VENDOR_DRIVER_VERSION 0x00010116 +#define OID_GEN_SUPPORTED_GUIDS 0x00010117 +#define OID_GEN_NETWORK_LAYER_ADDRESSES 0x00010118 +#define OID_GEN_TRANSPORT_HEADER_OFFSET 0x00010119 +#define OID_GEN_MACHINE_NAME 0x0001021A +#define OID_GEN_RNDIS_CONFIG_PARAMETER 0x0001021B +#define OID_GEN_VLAN_ID 0x0001021C + +/* Optional OIDs */ +#define OID_GEN_MEDIA_CAPABILITIES 0x00010201 +#define OID_GEN_PHYSICAL_MEDIUM 0x00010202 + +/* Required statistics OIDs */ +#define OID_GEN_XMIT_OK 0x00020101 +#define OID_GEN_RCV_OK 0x00020102 +#define OID_GEN_XMIT_ERROR 0x00020103 +#define OID_GEN_RCV_ERROR 0x00020104 +#define OID_GEN_RCV_NO_BUFFER 0x00020105 + +/* Optional statistics OIDs */ +#define OID_GEN_DIRECTED_BYTES_XMIT 0x00020201 +#define OID_GEN_DIRECTED_FRAMES_XMIT 0x00020202 +#define OID_GEN_MULTICAST_BYTES_XMIT 0x00020203 +#define OID_GEN_MULTICAST_FRAMES_XMIT 0x00020204 +#define OID_GEN_BROADCAST_BYTES_XMIT 0x00020205 +#define OID_GEN_BROADCAST_FRAMES_XMIT 0x00020206 +#define OID_GEN_DIRECTED_BYTES_RCV 0x00020207 +#define OID_GEN_DIRECTED_FRAMES_RCV 0x00020208 +#define OID_GEN_MULTICAST_BYTES_RCV 0x00020209 +#define OID_GEN_MULTICAST_FRAMES_RCV 0x0002020A +#define OID_GEN_BROADCAST_BYTES_RCV 0x0002020B +#define OID_GEN_BROADCAST_FRAMES_RCV 0x0002020C +#define OID_GEN_RCV_CRC_ERROR 0x0002020D +#define OID_GEN_TRANSMIT_QUEUE_LENGTH 0x0002020E +#define OID_GEN_GET_TIME_CAPS 0x0002020F +#define OID_GEN_GET_NETCARD_TIME 0x00020210 +#define OID_GEN_NETCARD_LOAD 0x00020211 +#define OID_GEN_DEVICE_PROFILE 0x00020212 +#define OID_GEN_INIT_TIME_MS 0x00020213 +#define OID_GEN_RESET_COUNTS 0x00020214 +#define OID_GEN_MEDIA_SENSE_COUNTS 0x00020215 +#define OID_GEN_FRIENDLY_NAME 0x00020216 +#define OID_GEN_MINIPORT_INFO 0x00020217 +#define OID_GEN_RESET_VERIFY_PARAMETERS 0x00020218 + +/* IEEE 802.3 (Ethernet) OIDs */ +#define NDIS_802_3_MAC_OPTION_PRIORITY 0x00000001 + +#define OID_802_3_PERMANENT_ADDRESS 0x01010101 +#define OID_802_3_CURRENT_ADDRESS 0x01010102 +#define OID_802_3_MULTICAST_LIST 0x01010103 +#define OID_802_3_MAXIMUM_LIST_SIZE 0x01010104 +#define OID_802_3_MAC_OPTIONS 0x01010105 +#define OID_802_3_RCV_ERROR_ALIGNMENT 0x01020101 +#define OID_802_3_XMIT_ONE_COLLISION 0x01020102 +#define OID_802_3_XMIT_MORE_COLLISIONS 0x01020103 +#define OID_802_3_XMIT_DEFERRED 0x01020201 +#define OID_802_3_XMIT_MAX_COLLISIONS 0x01020202 +#define OID_802_3_RCV_OVERRUN 0x01020203 +#define OID_802_3_XMIT_UNDERRUN 0x01020204 +#define OID_802_3_XMIT_HEARTBEAT_FAILURE 0x01020205 +#define OID_802_3_XMIT_TIMES_CRS_LOST 0x01020206 +#define OID_802_3_XMIT_LATE_COLLISIONS 0x01020207 + +/* Wireless LAN OIDs */ +/* Mandatory */ +#define OID_802_11_BSSID 0x0D010101 /* Q S */ +#define OID_802_11_SSID 0x0D010102 /* Q S */ +#define OID_802_11_NETWORK_TYPE_IN_USE 0x0D010204 /* Q S */ +#define OID_802_11_RSSI 0x0D010206 /* Q I */ +#define OID_802_11_BSSID_LIST 0x0D010217 /* Q */ +#define OID_802_11_BSSID_LIST_SCAN 0x0D01011A /* S */ +#define OID_802_11_INFRASTRUCTURE_MODE 0x0D010108 /* Q S */ +#define OID_802_11_SUPPORTED_RATES 0x0D01020E /* Q */ +#define OID_802_11_CONFIGURATION 0x0D010211 /* Q S */ +#define OID_802_11_ADD_WEP 0x0D010113 /* S */ +#define OID_802_11_WEP_STATUS 0x0D01011B /* Q S */ +#define OID_802_11_REMOVE_WEP 0x0D010114 /* S */ +#define OID_802_11_DISASSOCIATE 0x0D010115 /* S */ +#define OID_802_11_AUTHENTICATION_MODE 0x0D010118 /* Q S */ +#define OID_802_11_RELOAD_DEFAULTS 0x0D01011C /* S */ + +/* OID_GEN_MINIPORT_INFO constants */ +#define NDIS_MINIPORT_BUS_MASTER 0x00000001 +#define NDIS_MINIPORT_WDM_DRIVER 0x00000002 +#define NDIS_MINIPORT_SG_LIST 0x00000004 +#define NDIS_MINIPORT_SUPPORTS_MEDIA_QUERY 0x00000008 +#define NDIS_MINIPORT_INDICATES_PACKETS 0x00000010 +#define NDIS_MINIPORT_IGNORE_PACKET_QUEUE 0x00000020 +#define NDIS_MINIPORT_IGNORE_REQUEST_QUEUE 0x00000040 +#define NDIS_MINIPORT_IGNORE_TOKEN_RING_ERRORS 0x00000080 +#define NDIS_MINIPORT_INTERMEDIATE_DRIVER 0x00000100 +#define NDIS_MINIPORT_IS_NDIS_5 0x00000200 +#define NDIS_MINIPORT_IS_CO 0x00000400 +#define NDIS_MINIPORT_DESERIALIZE 0x00000800 +#define NDIS_MINIPORT_REQUIRES_MEDIA_POLLING 0x00001000 +#define NDIS_MINIPORT_SUPPORTS_MEDIA_SENSE 0x00002000 +#define NDIS_MINIPORT_NETBOOT_CARD 0x00004000 +#define NDIS_MINIPORT_PM_SUPPORTED 0x00008000 +#define NDIS_MINIPORT_SUPPORTS_MAC_ADDRESS_OVERWRITE 0x00010000 +#define NDIS_MINIPORT_USES_SAFE_BUFFER_APIS 0x00020000 +#define NDIS_MINIPORT_HIDDEN 0x00040000 +#define NDIS_MINIPORT_SWENUM 0x00080000 +#define NDIS_MINIPORT_SURPRISE_REMOVE_OK 0x00100000 +#define NDIS_MINIPORT_NO_HALT_ON_SUSPEND 0x00200000 +#define NDIS_MINIPORT_HARDWARE_DEVICE 0x00400000 +#define NDIS_MINIPORT_SUPPORTS_CANCEL_SEND_PACKETS 0x00800000 +#define NDIS_MINIPORT_64BITS_DMA 0x01000000 + +#define NDIS_MEDIUM_802_3 0x00000000 +#define NDIS_MEDIUM_802_5 0x00000001 +#define NDIS_MEDIUM_FDDI 0x00000002 +#define NDIS_MEDIUM_WAN 0x00000003 +#define NDIS_MEDIUM_LOCAL_TALK 0x00000004 +#define NDIS_MEDIUM_DIX 0x00000005 +#define NDIS_MEDIUM_ARCENT_RAW 0x00000006 +#define NDIS_MEDIUM_ARCENT_878_2 0x00000007 +#define NDIS_MEDIUM_ATM 0x00000008 +#define NDIS_MEDIUM_WIRELESS_LAN 0x00000009 +#define NDIS_MEDIUM_IRDA 0x0000000A +#define NDIS_MEDIUM_BPC 0x0000000B +#define NDIS_MEDIUM_CO_WAN 0x0000000C +#define NDIS_MEDIUM_1394 0x0000000D + +#define NDIS_PACKET_TYPE_DIRECTED 0x00000001 +#define NDIS_PACKET_TYPE_MULTICAST 0x00000002 +#define NDIS_PACKET_TYPE_ALL_MULTICAST 0x00000004 +#define NDIS_PACKET_TYPE_BROADCAST 0x00000008 +#define NDIS_PACKET_TYPE_SOURCE_ROUTING 0x00000010 +#define NDIS_PACKET_TYPE_PROMISCUOUS 0x00000020 +#define NDIS_PACKET_TYPE_SMT 0x00000040 +#define NDIS_PACKET_TYPE_ALL_LOCAL 0x00000080 +#define NDIS_PACKET_TYPE_GROUP 0x00000100 +#define NDIS_PACKET_TYPE_ALL_FUNCTIONAL 0x00000200 +#define NDIS_PACKET_TYPE_FUNCTIONAL 0x00000400 +#define NDIS_PACKET_TYPE_MAC_FRAME 0x00000800 + +#define NDIS_MEDIA_STATE_CONNECTED 0x00000000 +#define NDIS_MEDIA_STATE_DISCONNECTED 0x00000001 + +#define NDIS_MAC_OPTION_COPY_LOOKAHEAD_DATA 0x00000001 +#define NDIS_MAC_OPTION_RECEIVE_SERIALIZED 0x00000002 +#define NDIS_MAC_OPTION_TRANSFERS_NOT_PEND 0x00000004 +#define NDIS_MAC_OPTION_NO_LOOPBACK 0x00000008 +#define NDIS_MAC_OPTION_FULL_DUPLEX 0x00000010 +#define NDIS_MAC_OPTION_EOTX_INDICATION 0x00000020 +#define NDIS_MAC_OPTION_8021P_PRIORITY 0x00000040 +#define NDIS_MAC_OPTION_RESERVED 0x80000000 + +/** Hardware status of the underlying NIC */ +#define NDIS_HW_STS_READY 0x00000000UL +#define NDIS_HW_STS_INITIALIZING 0x00000001UL +#define NDIS_HW_STS_RESET 0x00000002UL +#define NDIS_HW_STS_CLOSING 0x00000003UL +#define NDIS_HW_STS_NOT_READY 0x00000004UL + +#endif /* _LINUX_NDIS_H */ + +/** @} */ diff --git a/kernel/cherryusb/class/wireless/rndis_protocol.h b/kernel/cherryusb/class/wireless/rndis_protocol.h new file mode 100644 index 0000000..54b4ebf --- /dev/null +++ b/kernel/cherryusb/class/wireless/rndis_protocol.h @@ -0,0 +1,302 @@ +/** + * \file rndis_protocol.h + * RNDIS Defines + * + * \author + * Colin O'Flynn + * + * \addtogroup usbstick + */ + +/* Copyright (c) 2008 Colin O'Flynn + + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in + the documentation and/or other materials provided with the + distribution. + * Neither the name of the copyright holders nor the names of + contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. +*/ + +#ifndef _RNDIS_H +#define _RNDIS_H + +/** + \addtogroup RNDIS + @{ + */ + +#include + +#define RNDIS_MAJOR_VERSION 1 +#define RNDIS_MINOR_VERSION 0 + +#define RNDIS_STATUS_SUCCESS 0X00000000 +#define RNDIS_STATUS_FAILURE 0XC0000001 +#define RNDIS_STATUS_INVALID_DATA 0XC0010015 +#define RNDIS_STATUS_NOT_SUPPORTED 0XC00000BB +#define RNDIS_STATUS_MEDIA_CONNECT 0X4001000B +#define RNDIS_STATUS_MEDIA_DISCONNECT 0X4001000C + +/* Message set for Connectionless (802.3) Devices */ +#define REMOTE_NDIS_PACKET_MSG 0x00000001 +#define REMOTE_NDIS_INITIALIZE_MSG 0X00000002 +#define REMOTE_NDIS_HALT_MSG 0X00000003 +#define REMOTE_NDIS_QUERY_MSG 0X00000004 +#define REMOTE_NDIS_SET_MSG 0X00000005 +#define REMOTE_NDIS_RESET_MSG 0X00000006 +#define REMOTE_NDIS_INDICATE_STATUS_MSG 0X00000007 +#define REMOTE_NDIS_KEEPALIVE_MSG 0X00000008 +#define REMOTE_NDIS_INITIALIZE_CMPLT 0X80000002 +#define REMOTE_NDIS_QUERY_CMPLT 0X80000004 +#define REMOTE_NDIS_SET_CMPLT 0X80000005 +#define REMOTE_NDIS_RESET_CMPLT 0X80000006 +#define REMOTE_NDIS_KEEPALIVE_CMPLT 0X80000008 + +typedef uint32_t rndis_MessageType_t; +typedef uint32_t rndis_MessageLength_t; +typedef uint32_t rndis_RequestId_t; +typedef uint32_t rndis_MajorVersion_t; +typedef uint32_t rndis_MinorVersion_t; +typedef uint32_t rndis_MaxTransferSize_t; +typedef uint32_t rndis_Status_t; + +/* Device Flags */ +#define RNDIS_DF_CONNECTIONLESS 0x00000001 +#define RNDIS_DF_CONNECTION_ORIENTED 0x00000002 +typedef uint32_t rndis_DeviceFlags_t; + +/* Mediums */ +#define RNDIS_MEDIUM_802_3 0x00000000 +typedef uint32_t rndis_Medium_t; + +typedef uint32_t rndis_MaxPacketsPerTransfer_t; +typedef uint32_t rndis_PacketAlignmentFactor_t; +typedef uint32_t rndis_AfListOffset_t; +typedef uint32_t rndis_AfListSize_t; + +/*** Remote NDIS Generic Message type ***/ +typedef struct { + rndis_MessageType_t MessageType; + rndis_MessageLength_t MessageLength; +} rndis_generic_msg_t; + +/*** Remote NDIS Initialize Message ***/ +typedef struct { + rndis_MessageType_t MessageType; + rndis_MessageLength_t MessageLength; + rndis_RequestId_t RequestId; + rndis_MajorVersion_t MajorVersion; + rndis_MinorVersion_t MinorVersion; + rndis_MaxTransferSize_t MaxTransferSize; +} rndis_initialize_msg_t; + +/* Response: */ +typedef struct { + rndis_MessageType_t MessageType; + rndis_MessageLength_t MessageLength; + rndis_RequestId_t RequestId; + rndis_Status_t Status; + rndis_MajorVersion_t MajorVersion; + rndis_MinorVersion_t MinorVersion; + rndis_DeviceFlags_t DeviceFlags; + rndis_Medium_t Medium; + rndis_MaxPacketsPerTransfer_t MaxPacketsPerTransfer; + rndis_MaxTransferSize_t MaxTransferSize; + rndis_PacketAlignmentFactor_t PacketAlignmentFactor; + rndis_AfListOffset_t AfListOffset; + rndis_AfListSize_t AfListSize; +} rndis_initialize_cmplt_t; + +/*** Remote NDIS Halt Message ***/ +typedef struct { + rndis_MessageType_t MessageType; + rndis_MessageLength_t MessageLength; + rndis_RequestId_t RequestId; +} rndis_halt_msg_t; + +typedef uint32_t rndis_Oid_t; +typedef uint32_t rndis_InformationBufferLength_t; +typedef uint32_t rndis_InformationBufferOffset_t; +typedef uint32_t rndis_DeviceVcHandle_t; + +/*** Remote NDIS Query Message ***/ +typedef struct { + rndis_MessageType_t MessageType; + rndis_MessageLength_t MessageLength; + rndis_RequestId_t RequestId; + rndis_Oid_t Oid; + rndis_InformationBufferLength_t InformationBufferLength; + rndis_InformationBufferOffset_t InformationBufferOffset; + rndis_DeviceVcHandle_t DeviceVcHandle; +} rndis_query_msg_t; + +/* Response: */ + +typedef struct { + rndis_MessageType_t MessageType; + rndis_MessageLength_t MessageLength; + rndis_RequestId_t RequestId; + rndis_Status_t Status; + rndis_InformationBufferLength_t InformationBufferLength; + rndis_InformationBufferOffset_t InformationBufferOffset; +} rndis_query_cmplt_t; + +/*** Remote NDIS Set Message ***/ +typedef struct { + rndis_MessageType_t MessageType; + rndis_MessageLength_t MessageLength; + rndis_RequestId_t RequestId; + rndis_Oid_t Oid; + rndis_InformationBufferLength_t InformationBufferLength; + rndis_InformationBufferOffset_t InformationBufferOffset; + rndis_DeviceVcHandle_t DeviceVcHandle; +} rndis_set_msg_t; + +/* Response */ +typedef struct { + rndis_MessageType_t MessageType; + rndis_MessageLength_t MessageLength; + rndis_RequestId_t RequestId; + rndis_Status_t Status; +} rndis_set_cmplt_t; + +/* Information buffer layout for OID_GEN_RNDIS_CONFIG_PARAMETER */ +typedef uint32_t rndis_ParameterNameOffset_t; +typedef uint32_t rndis_ParameterNameLength_t; +typedef uint32_t rndis_ParameterType_t; +typedef uint32_t rndis_ParameterValueOffset_t; +typedef uint32_t rndis_ParameterValueLength_t; + +#define PARAMETER_TYPE_STRING 2 +#define PARAMETER_TYPE_NUMERICAL 0 + +typedef struct { + rndis_ParameterNameOffset_t ParameterNameOffset; + rndis_ParameterNameLength_t ParameterNameLength; + rndis_ParameterType_t ParameterType; + rndis_ParameterValueOffset_t ParameterValueOffset; + rndis_ParameterValueLength_t ParameterValueLength; +} rndis_config_parameter_t; + +typedef uint32_t rndis_Reserved_t; + +/*** Remote NDIS Soft Reset Message ***/ +typedef struct { + rndis_MessageType_t MessageType; + rndis_MessageLength_t MessageLength; + rndis_Reserved_t Reserved; +} rndis_reset_msg_t; + +typedef uint32_t rndis_AddressingReset_t; + +/* Response: */ +typedef struct { + rndis_MessageType_t MessageType; + rndis_MessageLength_t MessageLength; + rndis_Status_t Status; + rndis_AddressingReset_t AddressingReset; +} rndis_reset_cmplt_t; + +/*** Remote NDIS Indicate Status Message ***/ +typedef struct { + rndis_MessageType_t MessageType; + rndis_MessageLength_t MessageLength; + rndis_Status_t Status; + rndis_Status_t StatusBufferLength; + rndis_Status_t StatusBufferOffset; +} rndis_indicate_status_t; + +typedef uint32_t rndis_DiagStatus_t; +typedef uint32_t rndis_ErrorOffset_t; + +typedef struct { + rndis_DiagStatus_t DiagStatus; + rndis_ErrorOffset_t ErrorOffset; +} rndis_diagnostic_info_t; + +/*** Remote NDIS Keepalive Message */ +typedef struct { + rndis_MessageType_t MessageType; + rndis_MessageLength_t MessageLength; + rndis_RequestId_t RequestId; +} rndis_keepalive_msg_t; + +/* Response: */ +typedef struct { + rndis_MessageType_t MessageType; + rndis_MessageLength_t MessageLength; + rndis_RequestId_t RequestId; + rndis_Status_t Status; +} rndis_keepalive_cmplt_t; + +/*** Remote NDIS Data Packet ***/ + +typedef uint32_t rndis_DataOffset_t; +typedef uint32_t rndis_DataLength_t; +typedef uint32_t rndis_OOBDataOffset_t; +typedef uint32_t rndis_OOBDataLength_t; +typedef uint32_t rndis_NumOOBDataElements_t; +typedef uint32_t rndis_PerPacketInfoOffset_t; +typedef uint32_t rndis_PerPacketInfoLength_t; + +typedef struct { + rndis_MessageType_t MessageType; + rndis_MessageLength_t MessageLength; + rndis_DataOffset_t DataOffset; + rndis_DataLength_t DataLength; + rndis_OOBDataOffset_t OOBDataOffset; + rndis_OOBDataLength_t OOBDataLength; + rndis_NumOOBDataElements_t NumOOBDataElements; + rndis_PerPacketInfoOffset_t PerPacketInfoOffset; + rndis_PerPacketInfoLength_t PerPacketInfoLength; + rndis_DeviceVcHandle_t DeviceVcHandle; + rndis_Reserved_t Reserved; +} rndis_data_packet_t; + +typedef uint32_t rndis_ClassInformationOffset_t; +typedef uint32_t rndis_Size_t; +typedef uint32_t rndis_Type_t; + +typedef struct { + rndis_Size_t Size; + rndis_Type_t Type; + rndis_ClassInformationOffset_t ClassInformationType; +} rndis_OOB_packet_t; + +#include "ndis.h" + +typedef enum rnids_state_e { + rndis_uninitialized, + rndis_initialized, + rndis_data_initialized +} rndis_state_t; + +typedef struct { + uint32_t txok; + uint32_t rxok; + uint32_t txbad; + uint32_t rxbad; +} usb_eth_stat_t; + +#endif /* _RNDIS_H */ + +/** @} */ diff --git a/kernel/cherryusb/class/wireless/usbd_rndis.c b/kernel/cherryusb/class/wireless/usbd_rndis.c new file mode 100644 index 0000000..dffeb20 --- /dev/null +++ b/kernel/cherryusb/class/wireless/usbd_rndis.c @@ -0,0 +1,662 @@ +/* + * Copyright (c) 2022, sakumisu + * + * SPDX-License-Identifier: Apache-2.0 + */ +#include "usbd_core.h" +#include "usbd_rndis.h" +#include "rndis_protocol.h" + +#define RNDIS_OUT_EP_IDX 0 +#define RNDIS_IN_EP_IDX 1 +#define RNDIS_INT_EP_IDX 2 + +/* Describe EndPoints configuration */ +static struct usbd_endpoint rndis_ep_data[3]; + +#define RNDIS_INQUIRY_PUT(src, len) (memcpy(infomation_buffer, src, len)) +#define RNDIS_INQUIRY_PUT_LE32(value) (*(uint32_t *)infomation_buffer = (value)) + +/* Device data structure */ +struct usbd_rndis_priv { + uint32_t drv_version; + uint32_t link_status; + uint32_t net_filter; + usb_eth_stat_t eth_state; + rndis_state_t init_state; + bool set_rsp_get; + uint8_t mac[6]; +} g_usbd_rndis; + +#if CONFIG_USBDEV_RNDIS_RESP_BUFFER_SIZE < 140 +#undef CONFIG_USBDEV_RNDIS_RESP_BUFFER_SIZE +#define CONFIG_USBDEV_RNDIS_RESP_BUFFER_SIZE 156 +#endif + +#if CONFIG_USBDEV_RNDIS_ETH_MAX_FRAME_SIZE < 1580 +#undef CONFIG_USBDEV_RNDIS_ETH_MAX_FRAME_SIZE +#define CONFIG_USBDEV_RNDIS_ETH_MAX_FRAME_SIZE 1580 +#endif + +#ifdef CONFIG_USBDEV_RNDIS_USING_LWIP +static USB_NOCACHE_RAM_SECTION USB_MEM_ALIGNX uint8_t g_rndis_rx_buffer[USB_ALIGN_UP(CONFIG_USBDEV_RNDIS_ETH_MAX_FRAME_SIZE, CONFIG_USB_ALIGN_SIZE)]; +static USB_NOCACHE_RAM_SECTION USB_MEM_ALIGNX uint8_t g_rndis_tx_buffer[USB_ALIGN_UP(CONFIG_USBDEV_RNDIS_ETH_MAX_FRAME_SIZE, CONFIG_USB_ALIGN_SIZE)]; +#endif + +static USB_NOCACHE_RAM_SECTION USB_MEM_ALIGNX uint8_t rndis_encapsulated_resp_buffer[USB_ALIGN_UP(CONFIG_USBDEV_RNDIS_RESP_BUFFER_SIZE, CONFIG_USB_ALIGN_SIZE)]; +static USB_NOCACHE_RAM_SECTION USB_MEM_ALIGNX uint8_t NOTIFY_RESPONSE_AVAILABLE[USB_ALIGN_UP(8, CONFIG_USB_ALIGN_SIZE)]; + +volatile uint8_t *g_rndis_rx_data_buffer; +volatile uint32_t g_rndis_rx_data_length; +volatile uint32_t g_rndis_rx_total_length; +volatile uint32_t g_rndis_tx_data_length; + +/* RNDIS options list */ +const uint32_t oid_supported_list[] = { + /* General OIDs */ + OID_GEN_SUPPORTED_LIST, + OID_GEN_HARDWARE_STATUS, + OID_GEN_MEDIA_SUPPORTED, + OID_GEN_MEDIA_IN_USE, + OID_GEN_MAXIMUM_FRAME_SIZE, + OID_GEN_LINK_SPEED, + OID_GEN_TRANSMIT_BLOCK_SIZE, + OID_GEN_RECEIVE_BLOCK_SIZE, + OID_GEN_VENDOR_ID, + OID_GEN_VENDOR_DESCRIPTION, + OID_GEN_VENDOR_DRIVER_VERSION, + OID_GEN_CURRENT_PACKET_FILTER, + OID_GEN_MAXIMUM_TOTAL_SIZE, + OID_GEN_MEDIA_CONNECT_STATUS, + + OID_GEN_PHYSICAL_MEDIUM, + + /* General Statistic OIDs */ + OID_GEN_XMIT_OK, + OID_GEN_RCV_OK, + OID_GEN_XMIT_ERROR, + OID_GEN_RCV_ERROR, + OID_GEN_RCV_NO_BUFFER, + + /* Please configure us */ + OID_GEN_RNDIS_CONFIG_PARAMETER, + + /* 802.3 OIDs */ + OID_802_3_PERMANENT_ADDRESS, + OID_802_3_CURRENT_ADDRESS, + OID_802_3_MULTICAST_LIST, + OID_802_3_MAXIMUM_LIST_SIZE, + + /* 802.3 Statistic OIDs */ + OID_802_3_RCV_ERROR_ALIGNMENT, + OID_802_3_XMIT_ONE_COLLISION, + OID_802_3_XMIT_MORE_COLLISIONS, + + OID_802_3_MAC_OPTIONS, +}; + +static int rndis_encapsulated_cmd_handler(uint8_t *data, uint32_t len); + +static void rndis_notify_rsp(void) +{ + memset(NOTIFY_RESPONSE_AVAILABLE, 0, 8); + NOTIFY_RESPONSE_AVAILABLE[0] = 0x01; + usbd_ep_start_write(0, rndis_ep_data[RNDIS_INT_EP_IDX].ep_addr, NOTIFY_RESPONSE_AVAILABLE, 8); +} + +static int rndis_class_interface_request_handler(uint8_t busid, struct usb_setup_packet *setup, uint8_t **data, uint32_t *len) +{ + (void)busid; + + switch (setup->bRequest) { + case CDC_REQUEST_SEND_ENCAPSULATED_COMMAND: + g_usbd_rndis.set_rsp_get = true; + + rndis_encapsulated_cmd_handler(*data, setup->wLength); + break; + case CDC_REQUEST_GET_ENCAPSULATED_RESPONSE: + g_usbd_rndis.set_rsp_get = false; + + *data = rndis_encapsulated_resp_buffer; + *len = ((rndis_generic_msg_t *)rndis_encapsulated_resp_buffer)->MessageLength; + break; + + default: + return -1; + } + + return 0; +} + +static int rndis_init_cmd_handler(uint8_t *data, uint32_t len); +static int rndis_halt_cmd_handler(uint8_t *data, uint32_t len); +static int rndis_query_cmd_handler(uint8_t *data, uint32_t len); +static int rndis_set_cmd_handler(uint8_t *data, uint32_t len); +static int rndis_reset_cmd_handler(uint8_t *data, uint32_t len); +static int rndis_keepalive_cmd_handler(uint8_t *data, uint32_t len); + +static int rndis_encapsulated_cmd_handler(uint8_t *data, uint32_t len) +{ + switch (((rndis_generic_msg_t *)data)->MessageType) { + case REMOTE_NDIS_INITIALIZE_MSG: + return rndis_init_cmd_handler(data, len); + case REMOTE_NDIS_HALT_MSG: + return rndis_halt_cmd_handler(data, len); + case REMOTE_NDIS_QUERY_MSG: + return rndis_query_cmd_handler(data, len); + case REMOTE_NDIS_SET_MSG: + return rndis_set_cmd_handler(data, len); + case REMOTE_NDIS_RESET_MSG: + return rndis_reset_cmd_handler(data, len); + case REMOTE_NDIS_KEEPALIVE_MSG: + return rndis_keepalive_cmd_handler(data, len); + + default: + break; + } + return -1; +} + +static int rndis_init_cmd_handler(uint8_t *data, uint32_t len) +{ + rndis_initialize_msg_t *cmd = (rndis_initialize_msg_t *)data; + rndis_initialize_cmplt_t *resp; + + (void)len; + + resp = ((rndis_initialize_cmplt_t *)rndis_encapsulated_resp_buffer); + resp->RequestId = cmd->RequestId; + resp->MessageType = REMOTE_NDIS_INITIALIZE_CMPLT; + resp->MessageLength = sizeof(rndis_initialize_cmplt_t); + resp->MajorVersion = RNDIS_MAJOR_VERSION; + resp->MinorVersion = RNDIS_MINOR_VERSION; + resp->Status = RNDIS_STATUS_SUCCESS; + resp->DeviceFlags = RNDIS_DF_CONNECTIONLESS; + resp->Medium = RNDIS_MEDIUM_802_3; + resp->MaxPacketsPerTransfer = CONFIG_USBDEV_RNDIS_ETH_MAX_FRAME_SIZE / 1580; + resp->MaxTransferSize = CONFIG_USBDEV_RNDIS_ETH_MAX_FRAME_SIZE; + resp->PacketAlignmentFactor = 0; + resp->AfListOffset = 0; + resp->AfListSize = 0; + + g_usbd_rndis.init_state = rndis_initialized; + + rndis_notify_rsp(); + return 0; +} + +static int rndis_halt_cmd_handler(uint8_t *data, uint32_t len) +{ + rndis_halt_msg_t *resp; + + (void)data; + (void)len; + + resp = ((rndis_halt_msg_t *)rndis_encapsulated_resp_buffer); + resp->MessageLength = 0; + + g_usbd_rndis.init_state = rndis_uninitialized; + + return 0; +} + +static int rndis_query_cmd_handler(uint8_t *data, uint32_t len) +{ + rndis_query_msg_t *cmd = (rndis_query_msg_t *)data; + rndis_query_cmplt_t *resp; + uint8_t *infomation_buffer; + uint32_t infomation_len = 0; + + (void)len; + + resp = ((rndis_query_cmplt_t *)rndis_encapsulated_resp_buffer); + resp->MessageType = REMOTE_NDIS_QUERY_CMPLT; + resp->RequestId = cmd->RequestId; + resp->InformationBufferOffset = sizeof(rndis_query_cmplt_t) - sizeof(rndis_generic_msg_t); + resp->Status = RNDIS_STATUS_SUCCESS; + + infomation_buffer = (uint8_t *)resp + sizeof(rndis_query_cmplt_t); + + switch (cmd->Oid) { + case OID_GEN_SUPPORTED_LIST: + RNDIS_INQUIRY_PUT(oid_supported_list, sizeof(oid_supported_list)); + infomation_len = sizeof(oid_supported_list); + break; + case OID_GEN_HARDWARE_STATUS: + RNDIS_INQUIRY_PUT_LE32(NDIS_HW_STS_READY); + infomation_len = 4; + break; + case OID_GEN_MEDIA_SUPPORTED: + case OID_GEN_MEDIA_IN_USE: + RNDIS_INQUIRY_PUT_LE32(NDIS_MEDIUM_802_3); + infomation_len = 4; + break; + case OID_GEN_MAXIMUM_FRAME_SIZE: + case OID_GEN_TRANSMIT_BLOCK_SIZE: + case OID_GEN_RECEIVE_BLOCK_SIZE: + RNDIS_INQUIRY_PUT_LE32(0x05DC); /* mtu 1500 */ + infomation_len = 4; + break; + case OID_GEN_VENDOR_ID: + RNDIS_INQUIRY_PUT_LE32(CONFIG_USBDEV_RNDIS_VENDOR_ID); + infomation_len = 4; + break; + case OID_GEN_VENDOR_DRIVER_VERSION: + RNDIS_INQUIRY_PUT_LE32(0x0001); + infomation_len = 4; + break; + case OID_GEN_VENDOR_DESCRIPTION: + RNDIS_INQUIRY_PUT(CONFIG_USBDEV_RNDIS_VENDOR_DESC, strlen(CONFIG_USBDEV_RNDIS_VENDOR_DESC)); + infomation_len = (strlen(CONFIG_USBDEV_RNDIS_VENDOR_DESC) + 1); + break; + case OID_802_3_CURRENT_ADDRESS: + case OID_802_3_PERMANENT_ADDRESS: + RNDIS_INQUIRY_PUT(g_usbd_rndis.mac, 6); + infomation_len = 6; + break; + case OID_GEN_PHYSICAL_MEDIUM: + RNDIS_INQUIRY_PUT_LE32(NDIS_MEDIUM_802_3); + infomation_len = 4; + break; + case OID_GEN_LINK_SPEED: + if (usbd_get_ep_mps(0, rndis_ep_data[RNDIS_OUT_EP_IDX].ep_addr) > 64) { + RNDIS_INQUIRY_PUT_LE32(480000000 / 100); + } else { + RNDIS_INQUIRY_PUT_LE32(12000000 / 100); + } + + infomation_len = 4; + break; + case OID_GEN_CURRENT_PACKET_FILTER: + RNDIS_INQUIRY_PUT_LE32(g_usbd_rndis.net_filter); + infomation_len = 4; + break; + case OID_GEN_MAXIMUM_TOTAL_SIZE: + RNDIS_INQUIRY_PUT_LE32(0x0616); /* 1514 + 44 */ + infomation_len = 4; + break; + case OID_GEN_MEDIA_CONNECT_STATUS: + RNDIS_INQUIRY_PUT_LE32(NDIS_MEDIA_STATE_CONNECTED); + infomation_len = 4; + break; + case OID_GEN_RNDIS_CONFIG_PARAMETER: + RNDIS_INQUIRY_PUT_LE32(0); + infomation_len = 4; + break; + case OID_802_3_MAXIMUM_LIST_SIZE: + RNDIS_INQUIRY_PUT_LE32(1); /* one address */ + infomation_len = 4; + break; + case OID_802_3_MULTICAST_LIST: + //RNDIS_INQUIRY_PUT_LE32(0xE0000000); /* 224.0.0.0 */ + resp->Status = RNDIS_STATUS_NOT_SUPPORTED; + RNDIS_INQUIRY_PUT_LE32(0); + infomation_len = 4; + break; + case OID_802_3_MAC_OPTIONS: + // infomation_len = 0; + resp->Status = RNDIS_STATUS_NOT_SUPPORTED; + RNDIS_INQUIRY_PUT_LE32(0); + infomation_len = 4; + break; + case OID_GEN_MAC_OPTIONS: + RNDIS_INQUIRY_PUT_LE32(0); + infomation_len = 4; + break; + case OID_802_3_RCV_ERROR_ALIGNMENT: + RNDIS_INQUIRY_PUT_LE32(0); + infomation_len = 4; + break; + case OID_802_3_XMIT_ONE_COLLISION: + RNDIS_INQUIRY_PUT_LE32(0); + infomation_len = 4; + break; + case OID_802_3_XMIT_MORE_COLLISIONS: + RNDIS_INQUIRY_PUT_LE32(0); + infomation_len = 4; + break; + case OID_GEN_XMIT_OK: + RNDIS_INQUIRY_PUT_LE32(g_usbd_rndis.eth_state.txok); + infomation_len = 4; + break; + case OID_GEN_RCV_OK: + RNDIS_INQUIRY_PUT_LE32(g_usbd_rndis.eth_state.rxok); + infomation_len = 4; + break; + case OID_GEN_RCV_ERROR: + RNDIS_INQUIRY_PUT_LE32(g_usbd_rndis.eth_state.rxbad); + infomation_len = 4; + break; + case OID_GEN_XMIT_ERROR: + RNDIS_INQUIRY_PUT_LE32(g_usbd_rndis.eth_state.txbad); + infomation_len = 4; + break; + case OID_GEN_RCV_NO_BUFFER: + RNDIS_INQUIRY_PUT_LE32(0); + infomation_len = 4; + break; + default: + resp->Status = RNDIS_STATUS_FAILURE; + infomation_len = 0; + USB_LOG_WRN("Unhandled query for Object ID 0x%x\r\n", cmd->Oid); + break; + } + + resp->MessageLength = sizeof(rndis_query_cmplt_t) + infomation_len; + resp->InformationBufferLength = infomation_len; + + rndis_notify_rsp(); + return 0; +} + +static int rndis_set_cmd_handler(uint8_t *data, uint32_t len) +{ + rndis_set_msg_t *cmd = (rndis_set_msg_t *)data; + rndis_set_cmplt_t *resp; + rndis_config_parameter_t *param; + + (void)len; + + resp = ((rndis_set_cmplt_t *)rndis_encapsulated_resp_buffer); + resp->RequestId = cmd->RequestId; + resp->MessageType = REMOTE_NDIS_SET_CMPLT; + resp->MessageLength = sizeof(rndis_set_cmplt_t); + resp->Status = RNDIS_STATUS_SUCCESS; + + switch (cmd->Oid) { + case OID_GEN_RNDIS_CONFIG_PARAMETER: + break; + case OID_GEN_CURRENT_PACKET_FILTER: + if (cmd->InformationBufferLength < sizeof(g_usbd_rndis.net_filter)) { + resp->Status = RNDIS_STATUS_INVALID_DATA; + } else { + uint32_t *filter; + /* Parameter starts at offset buf_offset of the req_id field */ + filter = (uint32_t *)((uint8_t *)&(cmd->RequestId) + cmd->InformationBufferOffset); + + //g_usbd_rndis.net_filter = param->ParameterNameOffset; + g_usbd_rndis.net_filter = *(uint32_t *)filter; + if (g_usbd_rndis.net_filter) { + g_usbd_rndis.init_state = rndis_data_initialized; + } else { + g_usbd_rndis.init_state = rndis_initialized; + } + } + break; + case OID_GEN_CURRENT_LOOKAHEAD: + break; + case OID_GEN_PROTOCOL_OPTIONS: + break; + case OID_802_3_MULTICAST_LIST: + break; + case OID_PNP_ADD_WAKE_UP_PATTERN: + case OID_PNP_REMOVE_WAKE_UP_PATTERN: + case OID_PNP_ENABLE_WAKE_UP: + default: + resp->Status = RNDIS_STATUS_FAILURE; + USB_LOG_WRN("Unhandled query for Object ID 0x%x\r\n", cmd->Oid); + break; + } + + rndis_notify_rsp(); + + return 0; +} + +static int rndis_reset_cmd_handler(uint8_t *data, uint32_t len) +{ + // rndis_reset_msg_t *cmd = (rndis_reset_msg_t *)data; + rndis_reset_cmplt_t *resp; + + (void)data; + (void)len; + + resp = ((rndis_reset_cmplt_t *)rndis_encapsulated_resp_buffer); + resp->MessageType = REMOTE_NDIS_RESET_CMPLT; + resp->MessageLength = sizeof(rndis_reset_cmplt_t); + resp->Status = RNDIS_STATUS_SUCCESS; + resp->AddressingReset = 1; + + g_usbd_rndis.init_state = rndis_uninitialized; + + rndis_notify_rsp(); + + return 0; +} + +static int rndis_keepalive_cmd_handler(uint8_t *data, uint32_t len) +{ + rndis_keepalive_msg_t *cmd = (rndis_keepalive_msg_t *)data; + rndis_keepalive_cmplt_t *resp; + + (void)len; + + resp = ((rndis_keepalive_cmplt_t *)rndis_encapsulated_resp_buffer); + resp->RequestId = cmd->RequestId; + resp->MessageType = REMOTE_NDIS_KEEPALIVE_CMPLT; + resp->MessageLength = sizeof(rndis_keepalive_cmplt_t); + resp->Status = RNDIS_STATUS_SUCCESS; + + rndis_notify_rsp(); + + return 0; +} + +static void rndis_notify_handler(uint8_t busid, uint8_t event, void *arg) +{ + (void)busid; + (void)arg; + + switch (event) { + case USBD_EVENT_RESET: + g_usbd_rndis.link_status = NDIS_MEDIA_STATE_DISCONNECTED; + g_rndis_rx_data_length = 0; + g_rndis_tx_data_length = 0; + break; + case USBD_EVENT_CONFIGURED: +#ifdef CONFIG_USBDEV_RNDIS_USING_LWIP + g_usbd_rndis.link_status = NDIS_MEDIA_STATE_CONNECTED; + usbd_rndis_start_read(g_rndis_rx_buffer, sizeof(g_rndis_rx_buffer)); +#endif + break; + + default: + break; + } +} + +void rndis_bulk_out(uint8_t busid, uint8_t ep, uint32_t nbytes) +{ + rndis_data_packet_t *hdr; + + (void)busid; + (void)ep; + + hdr = (rndis_data_packet_t *)g_rndis_rx_data_buffer; + if ((hdr->MessageType != REMOTE_NDIS_PACKET_MSG) || (nbytes < hdr->MessageLength)) { + usbd_rndis_start_read((uint8_t *)g_rndis_rx_data_buffer, g_rndis_rx_total_length); + return; + } + + /* Point to the payload and update the message length */ + g_rndis_rx_data_buffer += hdr->DataOffset + sizeof(rndis_generic_msg_t); + g_rndis_rx_data_length = hdr->DataLength; + + usbd_rndis_data_recv_done(g_rndis_rx_data_length); +} + +void rndis_bulk_in(uint8_t busid, uint8_t ep, uint32_t nbytes) +{ + (void)busid; + + if ((nbytes % usbd_get_ep_mps(0, ep)) == 0 && nbytes) { + /* send zlp */ + usbd_ep_start_write(0, ep, NULL, 0); + } else { + usbd_rndis_data_send_done(g_rndis_tx_data_length); + g_rndis_tx_data_length = 0; + } +} + +void rndis_int_in(uint8_t busid, uint8_t ep, uint32_t nbytes) +{ + (void)busid; + (void)ep; + (void)nbytes; + + //USB_LOG_DBG("len:%d\r\n", nbytes); +} + +int usbd_rndis_start_write(uint8_t *buf, uint32_t len) +{ + if (!usb_device_is_configured(0)) { + return -USB_ERR_NOTCONN; + } + + if (g_rndis_tx_data_length > 0) { + return -USB_ERR_BUSY; + } + + g_rndis_tx_data_length = len; + + USB_LOG_DBG("txlen:%d\r\n", g_rndis_tx_data_length); + return usbd_ep_start_write(0, rndis_ep_data[RNDIS_IN_EP_IDX].ep_addr, buf, len); +} + +int usbd_rndis_start_read(uint8_t *buf, uint32_t len) +{ + if (!usb_device_is_configured(0)) { + return -USB_ERR_NOTCONN; + } + + g_rndis_rx_data_buffer = buf; + g_rndis_rx_total_length = len; + g_rndis_rx_data_length = 0; + return usbd_ep_start_read(0, rndis_ep_data[RNDIS_OUT_EP_IDX].ep_addr, buf, len); +} + +#ifdef CONFIG_USBDEV_RNDIS_USING_LWIP +#include + +struct pbuf *usbd_rndis_eth_rx(void) +{ + struct pbuf *p; + + if (g_rndis_rx_data_length == 0) { + return NULL; + } + p = pbuf_alloc(PBUF_RAW, g_rndis_rx_data_length, PBUF_POOL); + if (p == NULL) { + usbd_rndis_start_read(g_rndis_rx_buffer, sizeof(g_rndis_rx_buffer)); + return NULL; + } + usb_memcpy(p->payload, (uint8_t *)g_rndis_rx_data_buffer, g_rndis_rx_data_length); + p->len = g_rndis_rx_data_length; + + USB_LOG_DBG("rxlen:%d\r\n", g_rndis_rx_data_length); + usbd_rndis_start_read(g_rndis_rx_buffer, sizeof(g_rndis_rx_buffer)); + return p; +} + +int usbd_rndis_eth_tx(struct pbuf *p) +{ + struct pbuf *q; + uint8_t *buffer; + rndis_data_packet_t *hdr; + + if (!usb_device_is_configured(0)) { + return -USB_ERR_NOTCONN; + } + + if (g_rndis_tx_data_length > 0) { + return -USB_ERR_BUSY; + } + + if (p->tot_len > sizeof(g_rndis_tx_buffer)) { + p->tot_len = sizeof(g_rndis_tx_buffer); + } + + buffer = (uint8_t *)(g_rndis_tx_buffer + sizeof(rndis_data_packet_t)); + for (q = p; q != NULL; q = q->next) { + usb_memcpy(buffer, q->payload, q->len); + buffer += q->len; + } + + hdr = (rndis_data_packet_t *)g_rndis_tx_buffer; + + memset(hdr, 0, sizeof(rndis_data_packet_t)); + hdr->MessageType = REMOTE_NDIS_PACKET_MSG; + hdr->MessageLength = sizeof(rndis_data_packet_t) + p->tot_len; + hdr->DataOffset = sizeof(rndis_data_packet_t) - sizeof(rndis_generic_msg_t); + hdr->DataLength = p->tot_len; + + return usbd_rndis_start_write(g_rndis_tx_buffer, sizeof(rndis_data_packet_t) + p->tot_len); +} +#endif +struct usbd_interface *usbd_rndis_init_intf(struct usbd_interface *intf, + const uint8_t out_ep, + const uint8_t in_ep, + const uint8_t int_ep, uint8_t mac[6]) +{ + memcpy(g_usbd_rndis.mac, mac, 6); + + g_usbd_rndis.drv_version = 0x0001; + g_usbd_rndis.link_status = NDIS_MEDIA_STATE_DISCONNECTED; + + rndis_ep_data[RNDIS_OUT_EP_IDX].ep_addr = out_ep; + rndis_ep_data[RNDIS_OUT_EP_IDX].ep_cb = rndis_bulk_out; + rndis_ep_data[RNDIS_IN_EP_IDX].ep_addr = in_ep; + rndis_ep_data[RNDIS_IN_EP_IDX].ep_cb = rndis_bulk_in; + rndis_ep_data[RNDIS_INT_EP_IDX].ep_addr = int_ep; + rndis_ep_data[RNDIS_INT_EP_IDX].ep_cb = rndis_int_in; + + usbd_add_endpoint(0, &rndis_ep_data[RNDIS_OUT_EP_IDX]); + usbd_add_endpoint(0, &rndis_ep_data[RNDIS_IN_EP_IDX]); + usbd_add_endpoint(0, &rndis_ep_data[RNDIS_INT_EP_IDX]); + + intf->class_interface_handler = rndis_class_interface_request_handler; + intf->class_endpoint_handler = NULL; + intf->vendor_handler = NULL; + intf->notify_handler = rndis_notify_handler; + + return intf; +} + +int usbd_rndis_set_connect(bool connect) +{ + if (!usb_device_is_configured(0)) { + return -USB_ERR_NOTCONN; + } + + if(g_usbd_rndis.set_rsp_get) + return -USB_ERR_BUSY; + + rndis_indicate_status_t *resp; + + resp = ((rndis_indicate_status_t *)rndis_encapsulated_resp_buffer); + resp->MessageType = REMOTE_NDIS_INDICATE_STATUS_MSG; + resp->MessageLength = sizeof(rndis_indicate_status_t); + if(connect) { + resp->Status = RNDIS_STATUS_MEDIA_CONNECT; + g_usbd_rndis.link_status = NDIS_MEDIA_STATE_CONNECTED; + } else { + resp->Status = RNDIS_STATUS_MEDIA_DISCONNECT; + g_usbd_rndis.link_status = NDIS_MEDIA_STATE_DISCONNECTED; + } + resp->StatusBufferLength = 0; + resp->StatusBufferOffset = 0; + + rndis_notify_rsp(); + + return 0; +} + +__WEAK void usbd_rndis_data_recv_done(uint32_t len) +{ + (void)len; +} + +__WEAK void usbd_rndis_data_send_done(uint32_t len) +{ + (void)len; +} \ No newline at end of file diff --git a/kernel/cherryusb/class/wireless/usbd_rndis.h b/kernel/cherryusb/class/wireless/usbd_rndis.h new file mode 100644 index 0000000..8f4847b --- /dev/null +++ b/kernel/cherryusb/class/wireless/usbd_rndis.h @@ -0,0 +1,37 @@ +/* + * Copyright (c) 2022, sakumisu + * + * SPDX-License-Identifier: Apache-2.0 + */ +#ifndef USBD_RNDIS_H +#define USBD_RNDIS_H + +#include "usb_cdc.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* Init rndis interface driver */ +struct usbd_interface *usbd_rndis_init_intf(struct usbd_interface *intf, + const uint8_t out_ep, + const uint8_t in_ep, + const uint8_t int_ep, uint8_t mac[6]); + +int usbd_rndis_set_connect(bool connect); + +void usbd_rndis_data_recv_done(uint32_t len); +void usbd_rndis_data_send_done(uint32_t len); +int usbd_rndis_start_write(uint8_t *buf, uint32_t len); +int usbd_rndis_start_read(uint8_t *buf, uint32_t len); + +#ifdef CONFIG_USBDEV_RNDIS_USING_LWIP +struct pbuf *usbd_rndis_eth_rx(void); +int usbd_rndis_eth_tx(struct pbuf *p); +#endif + +#ifdef __cplusplus +} +#endif + +#endif /* USBD_RNDIS_H */ diff --git a/kernel/cherryusb/class/wireless/usbh_bluetooth.c b/kernel/cherryusb/class/wireless/usbh_bluetooth.c new file mode 100644 index 0000000..af7167c --- /dev/null +++ b/kernel/cherryusb/class/wireless/usbh_bluetooth.c @@ -0,0 +1,412 @@ +/* + * Copyright (c) 2024, sakumisu + * + * SPDX-License-Identifier: Apache-2.0 + */ +#include "usbh_core.h" +#include "usbh_bluetooth.h" + +#undef USB_DBG_TAG +#define USB_DBG_TAG "usbh_bluetooth" +#include "usb_log.h" + +#define DEV_FORMAT "/dev/bluetooth" + +static struct usbh_bluetooth g_bluetooth_class; + +#ifdef CONFIG_USBHOST_BLUETOOTH_HCI_H4 +USB_NOCACHE_RAM_SECTION USB_MEM_ALIGNX uint8_t g_bluetooth_tx_buf[USB_ALIGN_UP(CONFIG_USBHOST_BLUETOOTH_TX_SIZE, CONFIG_USB_ALIGN_SIZE)]; +USB_NOCACHE_RAM_SECTION USB_MEM_ALIGNX uint8_t g_bluetooth_rx_buf[USB_ALIGN_UP(CONFIG_USBHOST_BLUETOOTH_RX_SIZE, CONFIG_USB_ALIGN_SIZE)]; +#else +USB_NOCACHE_RAM_SECTION USB_MEM_ALIGNX uint8_t g_bluetooth_cmd_buf[USB_ALIGN_UP(256, CONFIG_USB_ALIGN_SIZE)]; +USB_NOCACHE_RAM_SECTION USB_MEM_ALIGNX uint8_t g_bluetooth_evt_buf[USB_ALIGN_UP(256, CONFIG_USB_ALIGN_SIZE)]; +USB_NOCACHE_RAM_SECTION USB_MEM_ALIGNX uint8_t g_bluetooth_tx_buf[USB_ALIGN_UP(CONFIG_USBHOST_BLUETOOTH_TX_SIZE, CONFIG_USB_ALIGN_SIZE)]; +USB_NOCACHE_RAM_SECTION USB_MEM_ALIGNX uint8_t g_bluetooth_rx_buf[USB_ALIGN_UP(CONFIG_USBHOST_BLUETOOTH_RX_SIZE, CONFIG_USB_ALIGN_SIZE)]; +#endif + +static int usbh_bluetooth_connect(struct usbh_hubport *hport, uint8_t intf) +{ + struct usb_endpoint_descriptor *ep_desc; + int ret = 0; +#ifndef CONFIG_USBHOST_BLUETOOTH_HCI_H4 + uint8_t mult; + uint16_t mps; +#endif + + struct usbh_bluetooth *bluetooth_class = &g_bluetooth_class; + +#ifndef CONFIG_USBHOST_BLUETOOTH_HCI_H4 + if (intf != 0) { + return 0; + } +#endif + + memset(bluetooth_class, 0, sizeof(struct usbh_bluetooth)); + + bluetooth_class->hport = hport; + bluetooth_class->intf = intf; +#ifndef CONFIG_USBHOST_BLUETOOTH_HCI_H4 + bluetooth_class->num_of_intf_altsettings = hport->config.intf[intf + 1].altsetting_num; +#endif + hport->config.intf[intf].priv = bluetooth_class; + + for (uint8_t i = 0; i < hport->config.intf[intf].altsetting[0].intf_desc.bNumEndpoints; i++) { + ep_desc = &hport->config.intf[intf].altsetting[0].ep[i].ep_desc; +#ifndef CONFIG_USBHOST_BLUETOOTH_HCI_H4 + if (USB_GET_ENDPOINT_TYPE(ep_desc->bmAttributes) == USB_ENDPOINT_TYPE_INTERRUPT) { + if (ep_desc->bEndpointAddress & 0x80) { + USBH_EP_INIT(bluetooth_class->intin, ep_desc); + } else { + return -USB_ERR_NOTSUPP; + } + } else { +#endif + if (ep_desc->bEndpointAddress & 0x80) { + USBH_EP_INIT(bluetooth_class->bulkin, ep_desc); + } else { + USBH_EP_INIT(bluetooth_class->bulkout, ep_desc); + } +#ifndef CONFIG_USBHOST_BLUETOOTH_HCI_H4 + } +#endif + } +#ifndef CONFIG_USBHOST_BLUETOOTH_HCI_H4 + USB_LOG_INFO("Num of altsettings:%u\r\n", bluetooth_class->num_of_intf_altsettings); + + for (uint8_t i = 0; i < bluetooth_class->num_of_intf_altsettings; i++) { + USB_LOG_INFO("Altsetting:%u\r\n", i); + for (uint8_t j = 0; j < hport->config.intf[intf + 1].altsetting[i].intf_desc.bNumEndpoints; j++) { + ep_desc = &bluetooth_class->hport->config.intf[intf + 1].altsetting[i].ep[j].ep_desc; + + mult = USB_GET_MULT(ep_desc->wMaxPacketSize); + mps = USB_GET_MAXPACKETSIZE(ep_desc->wMaxPacketSize); + + USB_LOG_INFO("\tEp=%02x Attr=%02u Mps=%d Interval=%02u Mult=%02u\r\n", + ep_desc->bEndpointAddress, + ep_desc->bmAttributes, + mps, + ep_desc->bInterval, + mult); + } + } + + ret = usbh_set_interface(hport, intf, 0); + if (ret < 0) { + return ret; + } + USB_LOG_INFO("Bluetooth select altsetting 0\r\n"); +#endif + strncpy(hport->config.intf[intf].devname, DEV_FORMAT, CONFIG_USBHOST_DEV_NAMELEN); + USB_LOG_INFO("Register Bluetooth Class:%s\r\n", hport->config.intf[intf].devname); + usbh_bluetooth_run(bluetooth_class); + return ret; +} + +static int usbh_bluetooth_disconnect(struct usbh_hubport *hport, uint8_t intf) +{ + int ret = 0; + + struct usbh_bluetooth *bluetooth_class = (struct usbh_bluetooth *)hport->config.intf[intf].priv; + + if (hport->config.config_desc.bNumInterfaces == (intf + 1)) { + return 0; + } + + if (bluetooth_class) { + if (bluetooth_class->bulkin) { + usbh_kill_urb(&bluetooth_class->bulkin_urb); + } + + if (bluetooth_class->bulkout) { + usbh_kill_urb(&bluetooth_class->bulkout_urb); + } +#ifndef CONFIG_USBHOST_BLUETOOTH_HCI_H4 + if (bluetooth_class->intin) { + usbh_kill_urb(&bluetooth_class->intin_urb); + } + + // if (bluetooth_class->isoin) { + // usbh_kill_urb(&bluetooth_class->isoin_urb); + // } + + // if (bluetooth_class->isoin) { + // usbh_kill_urb(&bluetooth_class->isoinin_urb); + // } +#endif + if (hport->config.intf[intf].devname[0] != '\0') { + usb_osal_thread_schedule_other(); + USB_LOG_INFO("Unregister Bluetooth Class:%s\r\n", hport->config.intf[intf].devname); + usbh_bluetooth_stop(bluetooth_class); + } + + memset(bluetooth_class, 0, sizeof(struct usbh_bluetooth)); + } + + return ret; +} + +#ifdef CONFIG_USBHOST_BLUETOOTH_HCI_LOG +static void usbh_bluetooth_hci_dump(uint8_t *data, uint32_t len) +{ + uint32_t i = 0; + + for (i = 0; i < len; i++) { + if (i % 16 == 0) { + USB_LOG_RAW("\r\n"); + } + + USB_LOG_RAW("%02x ", data[i]); + } + + USB_LOG_RAW("\r\n"); +} +#else +#define usbh_bluetooth_hci_dump(data, len) +#endif + +static int usbh_bluetooth_hci_bulk_out(uint8_t *buffer, uint32_t buflen) +{ + struct usbh_bluetooth *bluetooth_class = &g_bluetooth_class; + struct usbh_urb *urb = &bluetooth_class->bulkout_urb; + int ret; + + usbh_bulk_urb_fill(urb, bluetooth_class->hport, bluetooth_class->bulkout, buffer, buflen, USB_OSAL_WAITING_FOREVER, NULL, NULL); + ret = usbh_submit_urb(urb); + if (ret == 0) { + ret = urb->actual_length; + } + return ret; +} + +#ifdef CONFIG_USBHOST_BLUETOOTH_HCI_H4 +int usbh_bluetooth_hci_write(uint8_t hci_type, uint8_t *buffer, uint32_t buflen) +{ + int ret; + + g_bluetooth_tx_buf[0] = hci_type; + memcpy(&g_bluetooth_tx_buf[1], buffer, buflen); + usbh_bluetooth_hci_dump(g_bluetooth_tx_buf, buflen + 1); + ret = usbh_bluetooth_hci_bulk_out(g_bluetooth_tx_buf, buflen + 1); + return ret; +} + +void usbh_bluetooth_hci_rx_thread(CONFIG_USB_OSAL_THREAD_SET_ARGV) +{ + int ret; + uint32_t ep_mps; + uint8_t retry = 0; + uint16_t actual_len = 0; + + ep_mps = USB_GET_MAXPACKETSIZE(g_bluetooth_class.bulkin->wMaxPacketSize); + + USB_LOG_INFO("Create hc rx thread\r\n"); + while (1) { + usbh_bulk_urb_fill(&g_bluetooth_class.bulkin_urb, g_bluetooth_class.hport, g_bluetooth_class.bulkin, &g_bluetooth_rx_buf[actual_len], ep_mps, USB_OSAL_WAITING_FOREVER, NULL, NULL); + ret = usbh_submit_urb(&g_bluetooth_class.bulkin_urb); + if (ret < 0) { + if (ret == -USB_ERR_SHUTDOWN) { + goto delete; + } else { + retry++; + if (retry == 3) { + retry = 0; + goto delete; + } + continue; + } + } + actual_len += g_bluetooth_class.bulkin_urb.actual_length; + if (g_bluetooth_class.bulkin_urb.actual_length != ep_mps) { + usbh_bluetooth_hci_dump(g_bluetooth_rx_buf, actual_len); + usbh_bluetooth_hci_read_callback(g_bluetooth_rx_buf, actual_len); + actual_len = 0; + } else { + /* read continue util read short packet */ + } + } + // clang-format off +delete : + USB_LOG_INFO("Delete hc acl rx thread\r\n"); + usb_osal_thread_delete(NULL); + // clang-format on +} + +#else +static int usbh_bluetooth_hci_cmd(uint8_t *buffer, uint32_t buflen) +{ + struct usbh_bluetooth *bluetooth_class = &g_bluetooth_class; + struct usb_setup_packet *setup; + + if (!bluetooth_class || !bluetooth_class->hport) { + return -USB_ERR_INVAL; + } + setup = bluetooth_class->hport->setup; + + setup->bmRequestType = USB_REQUEST_DIR_OUT | USB_REQUEST_CLASS | USB_REQUEST_RECIPIENT_DEVICE; + setup->bRequest = 0x00; + setup->wValue = 0; + setup->wIndex = bluetooth_class->intf; + setup->wLength = buflen; + + return usbh_control_transfer(bluetooth_class->hport, setup, buffer); +} + +int usbh_bluetooth_hci_write(uint8_t hci_type, uint8_t *buffer, uint32_t buflen) +{ + int ret; + + if (hci_type == USB_BLUETOOTH_HCI_CMD) { + g_bluetooth_cmd_buf[0] = USB_BLUETOOTH_HCI_CMD; + memcpy(&g_bluetooth_cmd_buf[1], buffer, buflen); + usbh_bluetooth_hci_dump(g_bluetooth_cmd_buf, buflen + 1); + ret = usbh_bluetooth_hci_cmd(&g_bluetooth_cmd_buf[1], buflen); + } else if (hci_type == USB_BLUETOOTH_HCI_ACL) { + g_bluetooth_tx_buf[0] = USB_BLUETOOTH_HCI_ACL; + memcpy(&g_bluetooth_tx_buf[1], buffer, buflen); + usbh_bluetooth_hci_dump(g_bluetooth_tx_buf, buflen + 1); + ret = usbh_bluetooth_hci_bulk_out(&g_bluetooth_tx_buf[1], buflen); + } else { + ret = -1; + } + + return ret; +} + +void usbh_bluetooth_hci_evt_rx_thread(CONFIG_USB_OSAL_THREAD_SET_ARGV) +{ + int ret; + uint32_t ep_mps; + uint32_t interval; + uint8_t retry = 0; + uint16_t actual_len = 0; + + ep_mps = USB_GET_MAXPACKETSIZE(g_bluetooth_class.intin->wMaxPacketSize); + interval = g_bluetooth_class.intin->bInterval; + + USB_LOG_INFO("Create hc event rx thread\r\n"); + while (1) { + usbh_int_urb_fill(&g_bluetooth_class.intin_urb, g_bluetooth_class.hport, g_bluetooth_class.intin, &g_bluetooth_evt_buf[1 + actual_len], ep_mps, USB_OSAL_WAITING_FOREVER, NULL, NULL); + ret = usbh_submit_urb(&g_bluetooth_class.intin_urb); + if (ret < 0) { + if (ret == -USB_ERR_SHUTDOWN) { + goto delete; + } else if (ret == -USB_ERR_NAK) { + usb_osal_msleep(interval); + continue; + } else { + retry++; + if (retry == 3) { + retry = 0; + goto delete; + } + usb_osal_msleep(interval); + continue; + } + } + actual_len += g_bluetooth_class.intin_urb.actual_length; + if (g_bluetooth_class.intin_urb.actual_length != ep_mps) { + g_bluetooth_evt_buf[0] = USB_BLUETOOTH_HCI_EVT; + usbh_bluetooth_hci_dump(g_bluetooth_evt_buf, actual_len + 1); + usbh_bluetooth_hci_read_callback(g_bluetooth_evt_buf, actual_len + 1); + actual_len = 0; + } else { + /* read continue util read short packet */ + } + usb_osal_msleep(interval); + } + // clang-format off +delete : + USB_LOG_INFO("Delete hc event rx thread\r\n"); + usb_osal_thread_delete(NULL); + // clang-format on +} + +void usbh_bluetooth_hci_acl_rx_thread(CONFIG_USB_OSAL_THREAD_SET_ARGV) +{ + int ret; + uint32_t ep_mps; + uint8_t retry = 0; + uint16_t actual_len = 0; + + ep_mps = USB_GET_MAXPACKETSIZE(g_bluetooth_class.bulkin->wMaxPacketSize); + + USB_LOG_INFO("Create hc acl rx thread\r\n"); + while (1) { + usbh_bulk_urb_fill(&g_bluetooth_class.bulkin_urb, g_bluetooth_class.hport, g_bluetooth_class.bulkin, &g_bluetooth_rx_buf[1 + actual_len], ep_mps, USB_OSAL_WAITING_FOREVER, NULL, NULL); + ret = usbh_submit_urb(&g_bluetooth_class.bulkin_urb); + if (ret < 0) { + if (ret == -USB_ERR_SHUTDOWN) { + goto delete; + } else { + retry++; + if (retry == 3) { + retry = 0; + goto delete; + } + continue; + } + } + actual_len += g_bluetooth_class.bulkin_urb.actual_length; + if (g_bluetooth_class.bulkin_urb.actual_length != ep_mps) { + g_bluetooth_rx_buf[0] = USB_BLUETOOTH_HCI_ACL; + usbh_bluetooth_hci_dump(g_bluetooth_rx_buf, actual_len + 1); + usbh_bluetooth_hci_read_callback(g_bluetooth_rx_buf, actual_len + 1); + actual_len = 0; + } else { + /* read continue util read short packet */ + } + } + // clang-format off +delete : + USB_LOG_INFO("Delete hc acl rx thread\r\n"); + usb_osal_thread_delete(NULL); + // clang-format on +} +#endif + +__WEAK void usbh_bluetooth_hci_read_callback(uint8_t *data, uint32_t len) +{ + (void)data; + (void)len; +} + +__WEAK void usbh_bluetooth_run(struct usbh_bluetooth *bluetooth_class) +{ + (void)bluetooth_class; +} + +__WEAK void usbh_bluetooth_stop(struct usbh_bluetooth *bluetooth_class) +{ + (void)bluetooth_class; +} + +static const struct usbh_class_driver bluetooth_class_driver = { + .driver_name = "bluetooth", + .connect = usbh_bluetooth_connect, + .disconnect = usbh_bluetooth_disconnect +}; + +#ifdef CONFIG_USBHOST_BLUETOOTH_HCI_H4 +static const uint16_t bluetooth_id_table[][2] = { + { 0x2fe3, 0x000c }, + { 0, 0 }, +}; + +CLASS_INFO_DEFINE const struct usbh_class_info bluetooth_h4_nrf_class_info = { + .match_flags = USB_CLASS_MATCH_VID_PID | USB_CLASS_MATCH_INTF_CLASS, + .bInterfaceClass = 0xff, + .bInterfaceSubClass = 0x00, + .bInterfaceProtocol = 0x00, + .id_table = bluetooth_id_table, + .class_driver = &bluetooth_class_driver +}; +#else +CLASS_INFO_DEFINE const struct usbh_class_info bluetooth_class_info = { + .match_flags = USB_CLASS_MATCH_INTF_CLASS | USB_CLASS_MATCH_INTF_SUBCLASS | USB_CLASS_MATCH_INTF_PROTOCOL, + .bInterfaceClass = USB_DEVICE_CLASS_WIRELESS, + .bInterfaceSubClass = 0x01, + .bInterfaceProtocol = 0x01, + .id_table = NULL, + .class_driver = &bluetooth_class_driver +}; +#endif diff --git a/kernel/cherryusb/class/wireless/usbh_bluetooth.h b/kernel/cherryusb/class/wireless/usbh_bluetooth.h new file mode 100644 index 0000000..87eb02a --- /dev/null +++ b/kernel/cherryusb/class/wireless/usbh_bluetooth.h @@ -0,0 +1,56 @@ +/* + * Copyright (c) 2024, sakumisu + * + * SPDX-License-Identifier: Apache-2.0 + */ +#ifndef USBH_BLUETOOTH_H +#define USBH_BLUETOOTH_H + +#define USB_BLUETOOTH_HCI_NONE 0x00 +#define USB_BLUETOOTH_HCI_CMD 0x01 +#define USB_BLUETOOTH_HCI_ACL 0x02 +#define USB_BLUETOOTH_HCI_SCO 0x03 +#define USB_BLUETOOTH_HCI_EVT 0x04 +#define USB_BLUETOOTH_HCI_ISO 0x05 + +struct usbh_bluetooth { + struct usbh_hubport *hport; + uint8_t intf; + struct usb_endpoint_descriptor *bulkin; /* Bulk IN endpoint */ + struct usb_endpoint_descriptor *bulkout; /* Bulk OUT endpoint */ + struct usbh_urb bulkin_urb; /* Bulk IN urb */ + struct usbh_urb bulkout_urb; /* Bulk OUT urb */ +#ifndef CONFIG_USBHOST_BLUETOOTH_HCI_H4 + struct usb_endpoint_descriptor *intin; /* INTR endpoint */ + struct usb_endpoint_descriptor *isoin; /* Bulk IN endpoint */ + struct usb_endpoint_descriptor *isoout; /* Bulk OUT endpoint */ + struct usbh_urb intin_urb; /* INTR IN urb */ + struct usbh_urb *isoin_urb; /* Bulk IN urb */ + struct usbh_urb *isoout_urb; /* Bulk OUT urb */ + uint8_t num_of_intf_altsettings; +#endif + + void *user_data; +}; + +#ifdef __cplusplus +extern "C" { +#endif + +int usbh_bluetooth_hci_write(uint8_t hci_type, uint8_t *buffer, uint32_t buflen); +void usbh_bluetooth_hci_read_callback(uint8_t *data, uint32_t len); +#ifdef CONFIG_USBHOST_BLUETOOTH_HCI_H4 +void usbh_bluetooth_hci_rx_thread(CONFIG_USB_OSAL_THREAD_SET_ARGV); +#else +void usbh_bluetooth_hci_evt_rx_thread(CONFIG_USB_OSAL_THREAD_SET_ARGV); +void usbh_bluetooth_hci_acl_rx_thread(CONFIG_USB_OSAL_THREAD_SET_ARGV); +#endif + +void usbh_bluetooth_run(struct usbh_bluetooth *bluetooth_class); +void usbh_bluetooth_stop(struct usbh_bluetooth *bluetooth_class); + +#ifdef __cplusplus +} +#endif + +#endif /* USBH_BLUETOOTH_H */ diff --git a/kernel/cherryusb/class/wireless/usbh_rndis.c b/kernel/cherryusb/class/wireless/usbh_rndis.c new file mode 100644 index 0000000..709630c --- /dev/null +++ b/kernel/cherryusb/class/wireless/usbh_rndis.c @@ -0,0 +1,603 @@ +/* + * Copyright (c) 2022, sakumisu + * + * SPDX-License-Identifier: Apache-2.0 + */ +#include "usbh_core.h" +#include "usbh_rndis.h" +#include "rndis_protocol.h" + +#undef USB_DBG_TAG +#define USB_DBG_TAG "usbh_rndis" +#include "usb_log.h" + +#define DEV_FORMAT "/dev/rndis" + +USB_NOCACHE_RAM_SECTION USB_MEM_ALIGNX uint8_t g_rndis_buf[512]; + +#define CONFIG_USBHOST_RNDIS_ETH_MAX_FRAME_SIZE 1514 +#define CONFIG_USBHOST_RNDIS_ETH_MSG_SIZE (CONFIG_USBHOST_RNDIS_ETH_MAX_FRAME_SIZE + 44) + +static USB_NOCACHE_RAM_SECTION USB_MEM_ALIGNX uint8_t g_rndis_rx_buffer[USB_ALIGN_UP(CONFIG_USBHOST_RNDIS_ETH_MAX_RX_SIZE, CONFIG_USB_ALIGN_SIZE)]; +static USB_NOCACHE_RAM_SECTION USB_MEM_ALIGNX uint8_t g_rndis_tx_buffer[USB_ALIGN_UP(CONFIG_USBHOST_RNDIS_ETH_MAX_TX_SIZE, CONFIG_USB_ALIGN_SIZE)]; +// static USB_NOCACHE_RAM_SECTION USB_MEM_ALIGNX uint8_t g_rndis_inttx_buffer[USB_ALIGN_UP(16, CONFIG_USB_ALIGN_SIZE)]; + +static struct usbh_rndis g_rndis_class; + +static int usbh_rndis_get_notification(struct usbh_rndis *rndis_class) +{ + (void)rndis_class; + // int ret; + // struct usbh_urb *urb = &rndis_class->intin_urb; + + // usbh_int_urb_fill(urb, rndis_class->hport, rndis_class->intin, g_rndis_inttx_buffer, rndis_class->intin->wMaxPacketSize, USB_OSAL_WAITING_FOREVER, NULL, NULL); + // ret = usbh_submit_urb(urb); + // if (ret == 0) { + // ret = urb->actual_length; + // } + // return ret; + return 0; +} + +static int usbh_rndis_init_msg_transfer(struct usbh_rndis *rndis_class) +{ + struct usb_setup_packet *setup; + int ret = 0; + rndis_initialize_msg_t *cmd; + rndis_initialize_cmplt_t *resp; + + if (!rndis_class || !rndis_class->hport) { + return -USB_ERR_INVAL; + } + setup = rndis_class->hport->setup; + + cmd = (rndis_initialize_msg_t *)g_rndis_buf; + + cmd->MessageType = REMOTE_NDIS_INITIALIZE_MSG; + cmd->MessageLength = sizeof(rndis_initialize_msg_t); + cmd->RequestId = rndis_class->request_id++; + cmd->MajorVersion = 1; + cmd->MinorVersion = 0; + cmd->MaxTransferSize = 0x4000; + + setup->bmRequestType = USB_REQUEST_DIR_OUT | USB_REQUEST_CLASS | USB_REQUEST_RECIPIENT_INTERFACE; + setup->bRequest = CDC_REQUEST_SEND_ENCAPSULATED_COMMAND; + setup->wValue = 0; + setup->wIndex = 0; + setup->wLength = sizeof(rndis_initialize_msg_t); + + ret = usbh_control_transfer(rndis_class->hport, setup, (uint8_t *)cmd); + if (ret < 0) { + USB_LOG_ERR("init send error, ret: %d\r\n", ret); + return ret; + } + + usbh_rndis_get_notification(rndis_class); + + resp = (rndis_initialize_cmplt_t *)g_rndis_buf; + + setup->bmRequestType = USB_REQUEST_DIR_IN | USB_REQUEST_CLASS | USB_REQUEST_RECIPIENT_INTERFACE; + setup->bRequest = CDC_REQUEST_GET_ENCAPSULATED_RESPONSE; + setup->wValue = 0; + setup->wIndex = 0; + setup->wLength = sizeof(g_rndis_buf); + + ret = usbh_control_transfer(rndis_class->hport, setup, (uint8_t *)resp); + if (ret < 0) { + USB_LOG_ERR("init recv error, ret: %d\r\n", ret); + return ret; + } + + rndis_class->max_transfer_pkts = resp->MaxPacketsPerTransfer; + rndis_class->max_transfer_size = resp->MaxTransferSize; + USB_LOG_INFO("MaxPacketsPerTransfer: %u\r\n", (unsigned int)resp->MaxPacketsPerTransfer); + USB_LOG_INFO("MaxTransferSize: %u\r\n", (unsigned int)resp->MaxTransferSize); + + return ret; +} + +int usbh_rndis_query_msg_transfer(struct usbh_rndis *rndis_class, uint32_t oid, uint32_t query_len, uint8_t *info, uint32_t *info_len) +{ + struct usb_setup_packet *setup; + int ret = 0; + rndis_query_msg_t *cmd; + rndis_query_cmplt_t *resp; + + if (!rndis_class || !rndis_class->hport) { + return -USB_ERR_INVAL; + } + setup = rndis_class->hport->setup; + + cmd = (rndis_query_msg_t *)g_rndis_buf; + + cmd->MessageType = REMOTE_NDIS_QUERY_MSG; + cmd->MessageLength = query_len + sizeof(rndis_query_msg_t); + cmd->RequestId = rndis_class->request_id++; + cmd->Oid = oid; + cmd->InformationBufferLength = query_len; + cmd->InformationBufferOffset = 20; + cmd->DeviceVcHandle = 0; + + setup->bmRequestType = USB_REQUEST_DIR_OUT | USB_REQUEST_CLASS | USB_REQUEST_RECIPIENT_INTERFACE; + setup->bRequest = CDC_REQUEST_SEND_ENCAPSULATED_COMMAND; + setup->wValue = 0; + setup->wIndex = 0; + setup->wLength = query_len + sizeof(rndis_query_msg_t); + + ret = usbh_control_transfer(rndis_class->hport, setup, (uint8_t *)cmd); + if (ret < 0) { + USB_LOG_ERR("oid:%08x send error, ret: %d\r\n", (unsigned int)oid, ret); + return ret; + } + + usbh_rndis_get_notification(rndis_class); + + resp = (rndis_query_cmplt_t *)g_rndis_buf; + + setup->bmRequestType = USB_REQUEST_DIR_IN | USB_REQUEST_CLASS | USB_REQUEST_RECIPIENT_INTERFACE; + setup->bRequest = CDC_REQUEST_GET_ENCAPSULATED_RESPONSE; + setup->wValue = 0; + setup->wIndex = 0; + setup->wLength = sizeof(g_rndis_buf); + + ret = usbh_control_transfer(rndis_class->hport, setup, (uint8_t *)resp); + if (ret < 0) { + USB_LOG_ERR("oid:%08x recv error, ret: %d\r\n", (unsigned int)oid, ret); + return ret; + } + + memcpy(info, ((uint8_t *)resp + sizeof(rndis_query_cmplt_t)), resp->InformationBufferLength); + *info_len = resp->InformationBufferLength; + + return ret; +} + +static int usbh_rndis_set_msg_transfer(struct usbh_rndis *rndis_class, uint32_t oid, uint8_t *info, uint32_t info_len) +{ + struct usb_setup_packet *setup; + int ret = 0; + rndis_set_msg_t *cmd; + rndis_set_cmplt_t *resp; + + if (!rndis_class || !rndis_class->hport) { + return -USB_ERR_INVAL; + } + setup = rndis_class->hport->setup; + + cmd = (rndis_set_msg_t *)g_rndis_buf; + + cmd->MessageType = REMOTE_NDIS_SET_MSG; + cmd->MessageLength = info_len + sizeof(rndis_set_msg_t); + cmd->RequestId = rndis_class->request_id++; + cmd->Oid = oid; + cmd->InformationBufferLength = info_len; + cmd->InformationBufferOffset = 20; + cmd->DeviceVcHandle = 0; + + memcpy(((uint8_t *)cmd + sizeof(rndis_set_msg_t)), info, info_len); + setup->bmRequestType = USB_REQUEST_DIR_OUT | USB_REQUEST_CLASS | USB_REQUEST_RECIPIENT_INTERFACE; + setup->bRequest = CDC_REQUEST_SEND_ENCAPSULATED_COMMAND; + setup->wValue = 0; + setup->wIndex = 0; + setup->wLength = info_len + sizeof(rndis_set_msg_t); + + ret = usbh_control_transfer(rndis_class->hport, setup, (uint8_t *)cmd); + if (ret < 0) { + USB_LOG_ERR("oid:%08x send error, ret: %d\r\n", (unsigned int)oid, ret); + return ret; + } + + usbh_rndis_get_notification(rndis_class); + + resp = (rndis_set_cmplt_t *)g_rndis_buf; + + setup->bmRequestType = USB_REQUEST_DIR_IN | USB_REQUEST_CLASS | USB_REQUEST_RECIPIENT_INTERFACE; + setup->bRequest = CDC_REQUEST_GET_ENCAPSULATED_RESPONSE; + setup->wValue = 0; + setup->wIndex = 0; + setup->wLength = sizeof(g_rndis_buf); + + ret = usbh_control_transfer(rndis_class->hport, setup, (uint8_t *)resp); + if (ret < 0) { + USB_LOG_ERR("oid:%08x recv error, ret: %d\r\n", (unsigned int)oid, ret); + return ret; + } + + return ret; +} + +int usbh_rndis_get_connect_status(struct usbh_rndis *rndis_class) +{ + int ret; + uint8_t data[32]; + uint32_t data_len; + + ret = usbh_rndis_query_msg_transfer(rndis_class, OID_GEN_MEDIA_CONNECT_STATUS, 4, data, &data_len); + if (ret < 0) { + return ret; + } + if (NDIS_MEDIA_STATE_CONNECTED == data[0]) { + rndis_class->connect_status = true; + } else { + rndis_class->connect_status = false; + } + return 0; +} + +int usbh_rndis_keepalive(struct usbh_rndis *rndis_class) +{ + struct usb_setup_packet *setup; + int ret = 0; + rndis_keepalive_msg_t *cmd; + rndis_keepalive_cmplt_t *resp; + + if (!rndis_class || !rndis_class->hport) { + return -USB_ERR_INVAL; + } + setup = rndis_class->hport->setup; + + cmd = (rndis_keepalive_msg_t *)g_rndis_buf; + + cmd->MessageType = REMOTE_NDIS_KEEPALIVE_MSG; + cmd->MessageLength = sizeof(rndis_keepalive_msg_t); + cmd->RequestId = rndis_class->request_id++; + + setup->bmRequestType = USB_REQUEST_DIR_OUT | USB_REQUEST_CLASS | USB_REQUEST_RECIPIENT_INTERFACE; + setup->bRequest = CDC_REQUEST_SEND_ENCAPSULATED_COMMAND; + setup->wValue = 0; + setup->wIndex = 0; + setup->wLength = sizeof(rndis_keepalive_msg_t); + + ret = usbh_control_transfer(rndis_class->hport, setup, (uint8_t *)cmd); + if (ret < 0) { + USB_LOG_ERR("keepalive send error, ret: %d\r\n", ret); + return ret; + } + + usbh_rndis_get_notification(rndis_class); + + resp = (rndis_keepalive_cmplt_t *)g_rndis_buf; + + setup->bmRequestType = USB_REQUEST_DIR_IN | USB_REQUEST_CLASS | USB_REQUEST_RECIPIENT_INTERFACE; + setup->bRequest = CDC_REQUEST_GET_ENCAPSULATED_RESPONSE; + setup->wValue = 0; + setup->wIndex = 0; + setup->wLength = sizeof(g_rndis_buf); + + ret = usbh_control_transfer(rndis_class->hport, setup, (uint8_t *)resp); + if (ret < 0) { + USB_LOG_ERR("keepalive recv error, ret: %d\r\n", ret); + return ret; + } + + return ret; +} + +static int usbh_rndis_connect(struct usbh_hubport *hport, uint8_t intf) +{ + struct usb_endpoint_descriptor *ep_desc; + int ret; + uint32_t *oid_support_list; + uint32_t oid = 0; + uint32_t oid_num = 0; + uint32_t data_len; + uint8_t tmp_buffer[512]; + uint8_t data[32]; + + struct usbh_rndis *rndis_class = &g_rndis_class; + + memset(rndis_class, 0, sizeof(struct usbh_rndis)); + + rndis_class->hport = hport; + rndis_class->ctrl_intf = intf; + rndis_class->data_intf = intf + 1; + + hport->config.intf[intf].priv = rndis_class; + hport->config.intf[intf + 1].priv = NULL; + + // ep_desc = &hport->config.intf[intf].altsetting[0].ep[0].ep_desc; + // USBH_EP_INIT(rndis_class->intin, ep_desc); + + for (uint8_t i = 0; i < hport->config.intf[intf + 1].altsetting[0].intf_desc.bNumEndpoints; i++) { + ep_desc = &hport->config.intf[intf + 1].altsetting[0].ep[i].ep_desc; + + if (ep_desc->bEndpointAddress & 0x80) { + USBH_EP_INIT(rndis_class->bulkin, ep_desc); + } else { + USBH_EP_INIT(rndis_class->bulkout, ep_desc); + } + } + + ret = usbh_rndis_init_msg_transfer(rndis_class); + if (ret < 0) { + return ret; + } + + ret = usbh_rndis_query_msg_transfer(rndis_class, OID_GEN_SUPPORTED_LIST, 0, tmp_buffer, &data_len); + if (ret < 0) { + return ret; + } + oid_num = (data_len / 4); + USB_LOG_INFO("rndis query OID_GEN_SUPPORTED_LIST success,oid num: %u\r\n", (unsigned int)oid_num); + + oid_support_list = (uint32_t *)tmp_buffer; + + for (uint8_t i = 0; i < oid_num; i++) { + oid = oid_support_list[i]; + switch (oid) { + case OID_GEN_PHYSICAL_MEDIUM: + ret = usbh_rndis_query_msg_transfer(rndis_class, OID_GEN_PHYSICAL_MEDIUM, 4, data, &data_len); + if (ret < 0) { + goto query_errorout; + } + break; + case OID_GEN_MAXIMUM_FRAME_SIZE: + ret = usbh_rndis_query_msg_transfer(rndis_class, OID_GEN_MAXIMUM_FRAME_SIZE, 4, data, &data_len); + if (ret < 0) { + goto query_errorout; + } + break; + case OID_GEN_LINK_SPEED: + ret = usbh_rndis_query_msg_transfer(rndis_class, OID_GEN_LINK_SPEED, 4, data, &data_len); + if (ret < 0) { + goto query_errorout; + } + + memcpy(&rndis_class->link_speed, data, 4); + break; + case OID_GEN_MEDIA_CONNECT_STATUS: + ret = usbh_rndis_query_msg_transfer(rndis_class, OID_GEN_MEDIA_CONNECT_STATUS, 4, data, &data_len); + if (ret < 0) { + goto query_errorout; + } + if (NDIS_MEDIA_STATE_CONNECTED == data[0]) { + rndis_class->connect_status = true; + } else { + rndis_class->connect_status = false; + } + break; + case OID_802_3_MAXIMUM_LIST_SIZE: + ret = usbh_rndis_query_msg_transfer(rndis_class, OID_802_3_MAXIMUM_LIST_SIZE, 4, data, &data_len); + if (ret < 0) { + goto query_errorout; + } + break; + case OID_802_3_CURRENT_ADDRESS: + ret = usbh_rndis_query_msg_transfer(rndis_class, OID_802_3_CURRENT_ADDRESS, 6, data, &data_len); + if (ret < 0) { + goto query_errorout; + } + + for (uint8_t j = 0; j < 6; j++) { + rndis_class->mac[j] = data[j]; + } + break; + case OID_802_3_PERMANENT_ADDRESS: + ret = usbh_rndis_query_msg_transfer(rndis_class, OID_802_3_PERMANENT_ADDRESS, 6, data, &data_len); + if (ret < 0) { + goto query_errorout; + } + break; + default: + break; + } + } + + uint32_t packet_filter = 0x0f; + ret = usbh_rndis_set_msg_transfer(rndis_class, OID_GEN_CURRENT_PACKET_FILTER, (uint8_t *)&packet_filter, 4); + if (ret < 0) { + return ret; + } + + uint8_t multicast_list[6] = { 0x01, 0x00, 0x5E, 0x00, 0x00, 0x01 }; + ret = usbh_rndis_set_msg_transfer(rndis_class, OID_802_3_MULTICAST_LIST, multicast_list, 6); + if (ret < 0) { + return ret; + } + + USB_LOG_INFO("rndis MAC address %02x:%02x:%02x:%02x:%02x:%02x\r\n", + rndis_class->mac[0], + rndis_class->mac[1], + rndis_class->mac[2], + rndis_class->mac[3], + rndis_class->mac[4], + rndis_class->mac[5]); + + strncpy(hport->config.intf[intf].devname, DEV_FORMAT, CONFIG_USBHOST_DEV_NAMELEN); + + USB_LOG_INFO("Register RNDIS Class:%s\r\n", hport->config.intf[intf].devname); + usbh_rndis_run(rndis_class); + return ret; +query_errorout: + USB_LOG_ERR("rndis query iod:%08x error\r\n", (unsigned int)oid); + return ret; +} + +static int usbh_rndis_disconnect(struct usbh_hubport *hport, uint8_t intf) +{ + int ret = 0; + + struct usbh_rndis *rndis_class = (struct usbh_rndis *)hport->config.intf[intf].priv; + + if (rndis_class) { + if (rndis_class->bulkin) { + usbh_kill_urb(&rndis_class->bulkin_urb); + } + + if (rndis_class->bulkout) { + usbh_kill_urb(&rndis_class->bulkout_urb); + } + + // if (rndis_class->intin) { + // usbh_kill_urb(&rndis_class->intin_urb); + // } + + if (hport->config.intf[intf].devname[0] != '\0') { + usb_osal_thread_schedule_other(); + USB_LOG_INFO("Unregister RNDIS Class:%s\r\n", hport->config.intf[intf].devname); + usbh_rndis_stop(rndis_class); + } + + memset(rndis_class, 0, sizeof(struct usbh_rndis)); + } + + return ret; +} + +void usbh_rndis_rx_thread(CONFIG_USB_OSAL_THREAD_SET_ARGV) +{ + uint32_t g_rndis_rx_length; + int ret; + uint32_t pmg_offset; + rndis_data_packet_t *pmsg; + rndis_data_packet_t temp; +#if CONFIG_USBHOST_RNDIS_ETH_MAX_RX_SIZE <= (16 * 1024) + uint32_t transfer_size = CONFIG_USBHOST_RNDIS_ETH_MAX_RX_SIZE; +#else + uint32_t transfer_size = (16 * 1024); +#endif + + (void)CONFIG_USB_OSAL_THREAD_GET_ARGV; + + USB_LOG_INFO("Create rndis rx thread\r\n"); + // clang-format off +find_class: + // clang-format on + g_rndis_class.connect_status = false; + if (usbh_find_class_instance("/dev/rndis") == NULL) { + goto delete; + } + + while (g_rndis_class.connect_status == false) { + ret = usbh_rndis_get_connect_status(&g_rndis_class); + if (ret < 0) { + usb_osal_msleep(100); + goto find_class; + } + usb_osal_msleep(128); + } + + g_rndis_rx_length = 0; + while (1) { + usbh_bulk_urb_fill(&g_rndis_class.bulkin_urb, g_rndis_class.hport, g_rndis_class.bulkin, &g_rndis_rx_buffer[g_rndis_rx_length], transfer_size, USB_OSAL_WAITING_FOREVER, NULL, NULL); + ret = usbh_submit_urb(&g_rndis_class.bulkin_urb); + if (ret < 0) { + break; + } + + g_rndis_rx_length += g_rndis_class.bulkin_urb.actual_length; + + /* A transfer is complete because last packet is a short packet. + * Short packet is not zero, match g_rndis_rx_length % USB_GET_MAXPACKETSIZE(g_rndis_class.bulkin->wMaxPacketSize). + * Short packet cannot be zero. + */ + if (g_rndis_rx_length % USB_GET_MAXPACKETSIZE(g_rndis_class.bulkin->wMaxPacketSize)) { + pmg_offset = 0; + + uint32_t total_len = g_rndis_rx_length; + + while (g_rndis_rx_length > 0) { + USB_LOG_DBG("rxlen:%u\r\n", (unsigned int)g_rndis_rx_length); + + pmsg = (rndis_data_packet_t *)(g_rndis_rx_buffer + pmg_offset); + + /* Not word-aligned case */ + if (pmg_offset & 0x3) { + usb_memcpy(&temp, pmsg, sizeof(rndis_data_packet_t)); + pmsg = &temp; + } + + if (pmsg->MessageType == REMOTE_NDIS_PACKET_MSG) { + uint8_t *buf = (uint8_t *)(g_rndis_rx_buffer + pmg_offset + sizeof(rndis_generic_msg_t) + pmsg->DataOffset); + + usbh_rndis_eth_input(buf, pmsg->DataLength); + pmg_offset += pmsg->MessageLength; + g_rndis_rx_length -= pmsg->MessageLength; + + /* drop the last dummy byte, it is a short packet to tell us we have received a multiple of wMaxPacketSize */ + if (g_rndis_rx_length < 4) { + g_rndis_rx_length = 0; + } + } else { + USB_LOG_ERR("offset:%u,remain:%u,total:%u\r\n", (unsigned int)pmg_offset, (unsigned int)g_rndis_rx_length, (unsigned int)total_len); + g_rndis_rx_length = 0; + USB_LOG_ERR("Error rndis packet message\r\n"); + } + } + } else { +#if CONFIG_USBHOST_RNDIS_ETH_MAX_RX_SIZE <= (16 * 1024) + if (g_rndis_rx_length == CONFIG_USBHOST_RNDIS_ETH_MAX_RX_SIZE) { +#else + if ((g_rndis_rx_length + (16 * 1024)) > CONFIG_USBHOST_RNDIS_ETH_MAX_RX_SIZE) { +#endif + USB_LOG_ERR("Rx packet is overflow, please reduce tcp window size or increase CONFIG_USBHOST_RNDIS_ETH_MAX_RX_SIZE\r\n"); + while (1) { + } + } + } + } + + // clang-format off +delete: + USB_LOG_INFO("Delete rndis rx thread\r\n"); + usb_osal_thread_delete(NULL); + // clang-format on +} + +uint8_t *usbh_rndis_get_eth_txbuf(void) +{ + return (g_rndis_tx_buffer + sizeof(rndis_data_packet_t)); +} + +int usbh_rndis_eth_output(uint32_t buflen) +{ + rndis_data_packet_t *hdr; + uint32_t len; + + if (g_rndis_class.connect_status == false) { + return -USB_ERR_NOTCONN; + } + + hdr = (rndis_data_packet_t *)g_rndis_tx_buffer; + memset(hdr, 0, sizeof(rndis_data_packet_t)); + + hdr->MessageType = REMOTE_NDIS_PACKET_MSG; + hdr->MessageLength = sizeof(rndis_data_packet_t) + buflen; + hdr->DataOffset = sizeof(rndis_data_packet_t) - sizeof(rndis_generic_msg_t); + hdr->DataLength = buflen; + + len = hdr->MessageLength; + /* if message length is the multiple of wMaxPacketSize, we should add a short packet to tell device transfer is over. */ + if (!(len % g_rndis_class.bulkout->wMaxPacketSize)) { + len += 1; + } + + USB_LOG_DBG("txlen:%d\r\n", len); + + usbh_bulk_urb_fill(&g_rndis_class.bulkout_urb, g_rndis_class.hport, g_rndis_class.bulkout, g_rndis_tx_buffer, len, USB_OSAL_WAITING_FOREVER, NULL, NULL); + return usbh_submit_urb(&g_rndis_class.bulkout_urb); +} + +static const struct usbh_class_driver rndis_class_driver = { + .driver_name = "rndis", + .connect = usbh_rndis_connect, + .disconnect = usbh_rndis_disconnect +}; + +CLASS_INFO_DEFINE const struct usbh_class_info rndis_class_info = { + .match_flags = USB_CLASS_MATCH_INTF_CLASS | USB_CLASS_MATCH_INTF_SUBCLASS | USB_CLASS_MATCH_INTF_PROTOCOL, + .bInterfaceClass = USB_DEVICE_CLASS_WIRELESS, + .bInterfaceSubClass = 0x01, + .bInterfaceProtocol = 0x03, + .id_table = NULL, + .class_driver = &rndis_class_driver +}; + +CLASS_INFO_DEFINE const struct usbh_class_info rndis_cdcacm_class_info = { + .match_flags = USB_CLASS_MATCH_INTF_CLASS | USB_CLASS_MATCH_INTF_SUBCLASS | USB_CLASS_MATCH_INTF_PROTOCOL, + .bInterfaceClass = USB_DEVICE_CLASS_CDC, + .bInterfaceSubClass = CDC_ABSTRACT_CONTROL_MODEL, + .bInterfaceProtocol = 0xff, + .id_table = NULL, + .class_driver = &rndis_class_driver +}; diff --git a/kernel/cherryusb/class/wireless/usbh_rndis.h b/kernel/cherryusb/class/wireless/usbh_rndis.h new file mode 100644 index 0000000..505a07a --- /dev/null +++ b/kernel/cherryusb/class/wireless/usbh_rndis.h @@ -0,0 +1,55 @@ +/* + * Copyright (c) 2022, sakumisu + * + * SPDX-License-Identifier: Apache-2.0 + */ +#ifndef USBH_RNDIS_H +#define USBH_RNDIS_H + +#include "usb_cdc.h" + +struct usbh_rndis { + struct usbh_hubport *hport; + struct usb_endpoint_descriptor *bulkin; /* Bulk IN endpoint */ + struct usb_endpoint_descriptor *bulkout; /* Bulk OUT endpoint */ + struct usb_endpoint_descriptor *intin; /* INTR endpoint */ + struct usbh_urb bulkin_urb; /* Bulk IN urb */ + struct usbh_urb bulkout_urb; /* Bulk OUT urb */ + struct usbh_urb intin_urb; /* INTR IN urb */ + + uint8_t ctrl_intf; /* Control interface number */ + uint8_t data_intf; /* Data interface number */ + uint8_t minor; + + uint32_t request_id; + uint32_t tx_offset; + uint32_t max_transfer_pkts; /* max packets in one transfer */ + uint32_t max_transfer_size; /* max size in one transfer */ + + uint32_t link_speed; + bool connect_status; + uint8_t mac[6]; + + void *user_data; +}; + +#ifdef __cplusplus +extern "C" { +#endif + +int usbh_rndis_get_connect_status(struct usbh_rndis *rndis_class); +int usbh_rndis_keepalive(struct usbh_rndis *rndis_class); + +void usbh_rndis_run(struct usbh_rndis *rndis_class); +void usbh_rndis_stop(struct usbh_rndis *rndis_class); + +uint8_t *usbh_rndis_get_eth_txbuf(void); +int usbh_rndis_eth_output(uint32_t buflen); +void usbh_rndis_eth_input(uint8_t *buf, uint32_t buflen); +void usbh_rndis_rx_thread(CONFIG_USB_OSAL_THREAD_SET_ARGV); + +#ifdef __cplusplus +} +#endif + +#endif /* USBH_RNDIS_H */ diff --git a/kernel/cherryusb/common/usb_dc.h b/kernel/cherryusb/common/usb_dc.h new file mode 100644 index 0000000..42a332e --- /dev/null +++ b/kernel/cherryusb/common/usb_dc.h @@ -0,0 +1,209 @@ +/* + * Copyright (c) 2022, sakumisu + * + * SPDX-License-Identifier: Apache-2.0 + */ +#ifndef USB_DC_H +#define USB_DC_H + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief init device controller registers. + * @return On success will return 0, and others indicate fail. + */ +int usb_dc_init(uint8_t busid); + +/** + * @brief deinit device controller registers. + * @return On success will return 0, and others indicate fail. + */ +int usb_dc_deinit(uint8_t busid); + +/** + * @brief Set USB device address + * + * @param[in] addr Device address + * + * @return On success will return 0, and others indicate fail. + */ +int usbd_set_address(uint8_t busid, const uint8_t addr); + +/** + * @brief Set remote wakeup feature + * + * @return On success will return 0, and others indicate fail. + */ +int usbd_set_remote_wakeup(uint8_t busid); + +/** + * @brief Get USB device speed + * + * @param[in] busid bus index + * + * @return port speed, USB_SPEED_LOW or USB_SPEED_FULL or USB_SPEED_HIGH + */ +uint8_t usbd_get_port_speed(uint8_t busid); + +/** + * @brief configure and enable endpoint. + * + * @param [in] ep_cfg Endpoint config. + * + * @return On success will return 0, and others indicate fail. + */ +int usbd_ep_open(uint8_t busid, const struct usb_endpoint_descriptor *ep); + +/** + * @brief Disable the selected endpoint + * + * @param[in] ep Endpoint address + * + * @return On success will return 0, and others indicate fail. + */ +int usbd_ep_close(uint8_t busid, const uint8_t ep); + +/** + * @brief Set stall condition for the selected endpoint + * + * @param[in] ep Endpoint address + * + * + * @return On success will return 0, and others indicate fail. + */ +int usbd_ep_set_stall(uint8_t busid, const uint8_t ep); + +/** + * @brief Clear stall condition for the selected endpoint + * + * @param[in] ep Endpoint address corresponding to the one + * listed in the device configuration table + * + * @return On success will return 0, and others indicate fail. + */ +int usbd_ep_clear_stall(uint8_t busid, const uint8_t ep); + +/** + * @brief Check if the selected endpoint is stalled + * + * @param[in] ep Endpoint address + * + * @param[out] stalled Endpoint stall status + * + * @return On success will return 0, and others indicate fail. + */ +int usbd_ep_is_stalled(uint8_t busid, const uint8_t ep, uint8_t *stalled); + +/** + * @brief Setup in ep transfer setting and start transfer. + * + * This function is asynchronous. + * This function is similar to uart with tx dma. + * + * This function is called to write data to the specified endpoint. The + * supplied usbd_endpoint_callback function will be called when data is transmitted + * out. + * + * @param[in] ep Endpoint address corresponding to the one + * listed in the device configuration table + * @param[in] data Pointer to data to write + * @param[in] data_len Length of the data requested to write. This may + * be zero for a zero length status packet. + * @return 0 on success, negative errno code on fail. + */ +int usbd_ep_start_write(uint8_t busid, const uint8_t ep, const uint8_t *data, uint32_t data_len); + +/** + * @brief Setup out ep transfer setting and start transfer. + * + * This function is asynchronous. + * This function is similar to uart with rx dma. + * + * This function is called to read data to the specified endpoint. The + * supplied usbd_endpoint_callback function will be called when data is received + * in. + * + * @param[in] ep Endpoint address corresponding to the one + * listed in the device configuration table + * @param[in] data Pointer to data to read + * @param[in] data_len Max length of the data requested to read. + * + * @return 0 on success, negative errno code on fail. + */ +int usbd_ep_start_read(uint8_t busid, const uint8_t ep, uint8_t *data, uint32_t data_len); + +/* usb dcd irq callback, called by user */ + +/** + * @brief Usb sof irq callback. + */ +void usbd_event_sof_handler(uint8_t busid); + +/** + * @brief Usb connect irq callback. + */ +void usbd_event_connect_handler(uint8_t busid); + +/** + * @brief Usb disconnect irq callback. + */ +void usbd_event_disconnect_handler(uint8_t busid); + +/** + * @brief Usb resume irq callback. + */ +void usbd_event_resume_handler(uint8_t busid); + +/** + * @brief Usb suspend irq callback. + */ +void usbd_event_suspend_handler(uint8_t busid); + +/** + * @brief Usb reset irq callback. + */ +void usbd_event_reset_handler(uint8_t busid); + +/** + * @brief Usb setup packet recv irq callback. + * @param[in] psetup setup packet. + */ +void usbd_event_ep0_setup_complete_handler(uint8_t busid, uint8_t *psetup); + +/** + * @brief In ep transfer complete irq callback. + * @param[in] ep Endpoint address corresponding to the one + * listed in the device configuration table + * @param[in] nbytes How many nbytes have transferred. + */ +void usbd_event_ep_in_complete_handler(uint8_t busid, uint8_t ep, uint32_t nbytes); + +/** + * @brief Out ep transfer complete irq callback. + * @param[in] ep Endpoint address corresponding to the one + * listed in the device configuration table + * @param[in] nbytes How many nbytes have transferred. + */ +void usbd_event_ep_out_complete_handler(uint8_t busid, uint8_t ep, uint32_t nbytes); + +#ifdef CONFIG_USBDEV_TEST_MODE +/** + * @brief Usb execute test mode + * @param[in] busid device busid + * @param[in] test_mode usb test mode + */ +void usbd_execute_test_mode(uint8_t busid, uint8_t test_mode); +#endif + +/* called by user */ +void USBD_IRQHandler(uint8_t busid); + +#ifdef __cplusplus +} +#endif + +#endif /* USB_DC_H */ diff --git a/kernel/cherryusb/common/usb_dcache.h b/kernel/cherryusb/common/usb_dcache.h new file mode 100644 index 0000000..f53efd9 --- /dev/null +++ b/kernel/cherryusb/common/usb_dcache.h @@ -0,0 +1,22 @@ +/* + * Copyright (c) 2024, sakumisu + * + * SPDX-License-Identifier: Apache-2.0 + */ +#ifndef USB_DCACHE_H +#define USB_DCACHE_H + +#ifdef CONFIG_USB_DCACHE_ENABLE +#if CONFIG_USB_ALIGN_SIZE % 32 +#error "CONFIG_USB_ALIGN_SIZE must be multiple of 32" +#endif +void usb_dcache_clean(uintptr_t addr, size_t size); +void usb_dcache_invalidate(uintptr_t addr, size_t size); +void usb_dcache_flush(uintptr_t addr, size_t size); +#else +#define usb_dcache_clean(addr, size) +#define usb_dcache_invalidate(addr, size) +#define usb_dcache_flush(addr, size) +#endif + +#endif /* USB_DCACHE_H */ diff --git a/kernel/cherryusb/common/usb_def.h b/kernel/cherryusb/common/usb_def.h new file mode 100644 index 0000000..be5ab06 --- /dev/null +++ b/kernel/cherryusb/common/usb_def.h @@ -0,0 +1,844 @@ +/* + * Copyright (c) 2022, sakumisu + * + * SPDX-License-Identifier: Apache-2.0 + */ +#ifndef USB_DEF_H +#define USB_DEF_H + +/* Useful define */ +#define USB_1_1 0x0110 +#define USB_2_0 0x0200 +/* Set USB version to 2.1 so that the host will request the BOS descriptor */ +#define USB_2_1 0x0210 +#define USB_3_0 0x0300 +#define USB_3_1 0x0310 +#define USB_3_2 0x0320 + +/* Device speeds */ +#define USB_SPEED_UNKNOWN 0 /* Transfer rate not yet set */ +#define USB_SPEED_LOW 1 /* USB 1.1 */ +#define USB_SPEED_FULL 2 /* USB 1.1 */ +#define USB_SPEED_HIGH 3 /* USB 2.0 */ +#define USB_SPEED_WIRELESS 4 /* Wireless USB 2.5 */ +#define USB_SPEED_SUPER 5 /* USB 3.0 */ +#define USB_SPEED_SUPER_PLUS 6 /* USB 3.1 */ + +/* Maximum number of devices per controller */ +#define USB_MAX_DEVICES (127) + +/* Default USB control EP, always 0 and 0x80 */ +#define USB_CONTROL_OUT_EP0 0 +#define USB_CONTROL_IN_EP0 0x80 + +/**< maximum packet size (MPS) for EP 0 */ +#define USB_CTRL_EP_MPS 64 + +/**< maximum packet size (MPS) for bulk EP */ +#define USB_BULK_EP_MPS_HS 512 +#define USB_BULK_EP_MPS_FS 64 + +/* USB PID Types */ +#define USB_PID_OUT (0x01) /* Tokens */ +#define USB_PID_IN (0x09) +#define USB_PID_SOF (0x05) +#define USB_PID_SETUP (0x0d) + +#define USB_PID_DATA0 (0x03) /* Data */ +#define USB_PID_DATA1 (0x0b) +#define USB_PID_DATA2 (0x07) +#define USB_PID_MDATA (0x0f) + +#define USB_PID_ACK (0x02) /* Handshake */ +#define USB_PID_NAK (0x0a) +#define USB_PID_STALL (0x0e) +#define USB_PID_NYET (0x06) + +#define USB_PID_PRE (0x0c) /* Special */ +#define USB_PID_ERR (0x0c) +#define USB_PID_SPLIT (0x08) +#define USB_PID_PING (0x04) +#define USB_PID_RESERVED (0x00) + +#define USB_REQUEST_DIR_SHIFT 7U /* Bits 7: Request dir */ +#define USB_REQUEST_DIR_OUT (0U << USB_REQUEST_DIR_SHIFT) /* Bit 7=0: Host-to-device */ +#define USB_REQUEST_DIR_IN (1U << USB_REQUEST_DIR_SHIFT) /* Bit 7=1: Device-to-host */ +#define USB_REQUEST_DIR_MASK (1U << USB_REQUEST_DIR_SHIFT) /* Bit 7=1: Direction bit */ + +#define USB_REQUEST_TYPE_SHIFT 5U /* Bits 5:6: Request type */ +#define USB_REQUEST_STANDARD (0U << USB_REQUEST_TYPE_SHIFT) +#define USB_REQUEST_CLASS (1U << USB_REQUEST_TYPE_SHIFT) +#define USB_REQUEST_VENDOR (2U << USB_REQUEST_TYPE_SHIFT) +#define USB_REQUEST_RESERVED (3U << USB_REQUEST_TYPE_SHIFT) +#define USB_REQUEST_TYPE_MASK (3U << USB_REQUEST_TYPE_SHIFT) + +#define USB_REQUEST_RECIPIENT_SHIFT 0U /* Bits 0:4: Recipient */ +#define USB_REQUEST_RECIPIENT_DEVICE (0U << USB_REQUEST_RECIPIENT_SHIFT) +#define USB_REQUEST_RECIPIENT_INTERFACE (1U << USB_REQUEST_RECIPIENT_SHIFT) +#define USB_REQUEST_RECIPIENT_ENDPOINT (2U << USB_REQUEST_RECIPIENT_SHIFT) +#define USB_REQUEST_RECIPIENT_OTHER (3U << USB_REQUEST_RECIPIENT_SHIFT) +#define USB_REQUEST_RECIPIENT_MASK (3U << USB_REQUEST_RECIPIENT_SHIFT) + +/* USB Standard Request Codes */ +#define USB_REQUEST_GET_STATUS 0x00 +#define USB_REQUEST_CLEAR_FEATURE 0x01 +#define USB_REQUEST_SET_FEATURE 0x03 +#define USB_REQUEST_SET_ADDRESS 0x05 +#define USB_REQUEST_GET_DESCRIPTOR 0x06 +#define USB_REQUEST_SET_DESCRIPTOR 0x07 +#define USB_REQUEST_GET_CONFIGURATION 0x08 +#define USB_REQUEST_SET_CONFIGURATION 0x09 +#define USB_REQUEST_GET_INTERFACE 0x0A +#define USB_REQUEST_SET_INTERFACE 0x0B +#define USB_REQUEST_SYNCH_FRAME 0x0C +#define USB_REQUEST_SET_ENCRYPTION 0x0D +#define USB_REQUEST_GET_ENCRYPTION 0x0E +#define USB_REQUEST_RPIPE_ABORT 0x0E +#define USB_REQUEST_SET_HANDSHAKE 0x0F +#define USB_REQUEST_RPIPE_RESET 0x0F +#define USB_REQUEST_GET_HANDSHAKE 0x10 +#define USB_REQUEST_SET_CONNECTION 0x11 +#define USB_REQUEST_SET_SECURITY_DATA 0x12 +#define USB_REQUEST_GET_SECURITY_DATA 0x13 +#define USB_REQUEST_SET_WUSB_DATA 0x14 +#define USB_REQUEST_LOOPBACK_DATA_WRITE 0x15 +#define USB_REQUEST_LOOPBACK_DATA_READ 0x16 +#define USB_REQUEST_SET_INTERFACE_DS 0x17 + +/* USB Standard Feature selectors */ +#define USB_FEATURE_ENDPOINT_HALT 0 +#define USB_FEATURE_SELF_POWERED 0 +#define USB_FEATURE_REMOTE_WAKEUP 1 +#define USB_FEATURE_TEST_MODE 2 +#define USB_FEATURE_BATTERY 2 +#define USB_FEATURE_BHNPENABLE 3 +#define USB_FEATURE_WUSBDEVICE 3 +#define USB_FEATURE_AHNPSUPPORT 4 +#define USB_FEATURE_AALTHNPSUPPORT 5 +#define USB_FEATURE_DEBUGMODE 6 + +/* USB GET_STATUS Bit Values */ +#define USB_GETSTATUS_ENDPOINT_HALT 0x01 +#define USB_GETSTATUS_SELF_POWERED 0x01 +#define USB_GETSTATUS_REMOTE_WAKEUP 0x02 + +/* USB Descriptor Types */ +#define USB_DESCRIPTOR_TYPE_DEVICE 0x01U +#define USB_DESCRIPTOR_TYPE_CONFIGURATION 0x02U +#define USB_DESCRIPTOR_TYPE_STRING 0x03U +#define USB_DESCRIPTOR_TYPE_INTERFACE 0x04U +#define USB_DESCRIPTOR_TYPE_ENDPOINT 0x05U +#define USB_DESCRIPTOR_TYPE_DEVICE_QUALIFIER 0x06U +#define USB_DESCRIPTOR_TYPE_OTHER_SPEED 0x07U +#define USB_DESCRIPTOR_TYPE_INTERFACE_POWER 0x08U +#define USB_DESCRIPTOR_TYPE_OTG 0x09U +#define USB_DESCRIPTOR_TYPE_DEBUG 0x0AU +#define USB_DESCRIPTOR_TYPE_INTERFACE_ASSOCIATION 0x0BU +#define USB_DESCRIPTOR_TYPE_BINARY_OBJECT_STORE 0x0FU +#define USB_DESCRIPTOR_TYPE_DEVICE_CAPABILITY 0x10U +#define USB_DESCRIPTOR_TYPE_WIRELESS_ENDPOINTCOMP 0x11U + +/* Class Specific Descriptor */ +#define USB_CS_DESCRIPTOR_TYPE_DEVICE 0x21U +#define USB_CS_DESCRIPTOR_TYPE_CONFIGURATION 0x22U +#define USB_CS_DESCRIPTOR_TYPE_STRING 0x23U +#define USB_CS_DESCRIPTOR_TYPE_INTERFACE 0x24U +#define USB_CS_DESCRIPTOR_TYPE_ENDPOINT 0x25U + +#define USB_DESCRIPTOR_TYPE_SUPERSPEED_ENDPOINT_COMPANION 0x30U +#define USB_DESCRIPTOR_TYPE_SUPERSPEED_ISO_ENDPOINT_COMPANION 0x31U + +/* USB Device Classes */ +#define USB_DEVICE_CLASS_RESERVED 0x00 +#define USB_DEVICE_CLASS_AUDIO 0x01 +#define USB_DEVICE_CLASS_CDC 0x02 +#define USB_DEVICE_CLASS_HID 0x03 +#define USB_DEVICE_CLASS_MONITOR 0x04 +#define USB_DEVICE_CLASS_PHYSICAL 0x05 +#define USB_DEVICE_CLASS_IMAGE 0x06 +#define USB_DEVICE_CLASS_PRINTER 0x07 +#define USB_DEVICE_CLASS_MASS_STORAGE 0x08 +#define USB_DEVICE_CLASS_HUB 0x09 +#define USB_DEVICE_CLASS_CDC_DATA 0x0a +#define USB_DEVICE_CLASS_SMART_CARD 0x0b +#define USB_DEVICE_CLASS_SECURITY 0x0d +#define USB_DEVICE_CLASS_VIDEO 0x0e +#define USB_DEVICE_CLASS_HEALTHCARE 0x0f +#define USB_DEVICE_CLASS_DIAG_DEVICE 0xdc +#define USB_DEVICE_CLASS_WIRELESS 0xe0 +#define USB_DEVICE_CLASS_MISC 0xef +#define USB_DEVICE_CLASS_APP_SPECIFIC 0xfe +#define USB_DEVICE_CLASS_VEND_SPECIFIC 0xff + +/* usb string index define */ +#define USB_STRING_LANGID_INDEX 0x00 +#define USB_STRING_MFC_INDEX 0x01 +#define USB_STRING_PRODUCT_INDEX 0x02 +#define USB_STRING_SERIAL_INDEX 0x03 +#define USB_STRING_CONFIG_INDEX 0x04 +#define USB_STRING_INTERFACE_INDEX 0x05 +#define USB_STRING_OS_INDEX 0x06 +#define USB_STRING_MAX USB_STRING_OS_INDEX +/* + * Devices supporting Microsoft OS Descriptors store special string + * descriptor at fixed index (0xEE). It is read when a new device is + * attached to a computer for the first time. + */ +#define USB_OSDESC_STRING_DESC_INDEX 0xEE + +/* bmAttributes in Configuration Descriptor */ +#define USB_CONFIG_REMOTE_WAKEUP 0x20 +#define USB_CONFIG_POWERED_MASK 0x40 +#define USB_CONFIG_BUS_POWERED 0x80 +#define USB_CONFIG_SELF_POWERED 0xC0 + +/* bMaxPower in Configuration Descriptor */ +#define USB_CONFIG_POWER_MA(mA) ((mA) / 2) + +/* bEndpointAddress in Endpoint Descriptor */ +#define USB_ENDPOINT_DIRECTION_MASK 0x80 +#define USB_ENDPOINT_OUT(addr) ((addr) | 0x00) +#define USB_ENDPOINT_IN(addr) ((addr) | 0x80) + +/** + * USB endpoint direction and number. + */ +#define USB_EP_DIR_MASK 0x80U +#define USB_EP_DIR_IN 0x80U +#define USB_EP_DIR_OUT 0x00U + +/** Get endpoint index (number) from endpoint address */ +#define USB_EP_GET_IDX(ep) ((ep) & ~USB_EP_DIR_MASK) +/** Get direction from endpoint address */ +#define USB_EP_GET_DIR(ep) ((ep)&USB_EP_DIR_MASK) +/** Get endpoint address from endpoint index and direction */ +#define USB_EP_GET_ADDR(idx, dir) ((idx) | ((dir)&USB_EP_DIR_MASK)) +/** True if the endpoint is an IN endpoint */ +#define USB_EP_DIR_IS_IN(ep) (USB_EP_GET_DIR(ep) == USB_EP_DIR_IN) +/** True if the endpoint is an OUT endpoint */ +#define USB_EP_DIR_IS_OUT(ep) (USB_EP_GET_DIR(ep) == USB_EP_DIR_OUT) + +/* bmAttributes in Endpoint Descriptor */ +#define USB_ENDPOINT_TYPE_SHIFT 0 +#define USB_ENDPOINT_TYPE_CONTROL (0 << USB_ENDPOINT_TYPE_SHIFT) +#define USB_ENDPOINT_TYPE_ISOCHRONOUS (1 << USB_ENDPOINT_TYPE_SHIFT) +#define USB_ENDPOINT_TYPE_BULK (2 << USB_ENDPOINT_TYPE_SHIFT) +#define USB_ENDPOINT_TYPE_INTERRUPT (3 << USB_ENDPOINT_TYPE_SHIFT) +#define USB_ENDPOINT_TYPE_MASK (3 << USB_ENDPOINT_TYPE_SHIFT) +#define USB_GET_ENDPOINT_TYPE(x) ((x & USB_ENDPOINT_TYPE_MASK) >> USB_ENDPOINT_TYPE_SHIFT) + +#define USB_ENDPOINT_SYNC_SHIFT 2 +#define USB_ENDPOINT_SYNC_NO_SYNCHRONIZATION (0 << USB_ENDPOINT_SYNC_SHIFT) +#define USB_ENDPOINT_SYNC_ASYNCHRONOUS (1 << USB_ENDPOINT_SYNC_SHIFT) +#define USB_ENDPOINT_SYNC_ADAPTIVE (2 << USB_ENDPOINT_SYNC_SHIFT) +#define USB_ENDPOINT_SYNC_SYNCHRONOUS (3 << USB_ENDPOINT_SYNC_SHIFT) +#define USB_ENDPOINT_SYNC_MASK (3 << USB_ENDPOINT_SYNC_SHIFT) + +#define USB_ENDPOINT_USAGE_SHIFT 4 +#define USB_ENDPOINT_USAGE_DATA (0 << USB_ENDPOINT_USAGE_SHIFT) +#define USB_ENDPOINT_USAGE_FEEDBACK (1 << USB_ENDPOINT_USAGE_SHIFT) +#define USB_ENDPOINT_USAGE_IMPLICIT_FEEDBACK (2 << USB_ENDPOINT_USAGE_SHIFT) +#define USB_ENDPOINT_USAGE_MASK (3 << USB_ENDPOINT_USAGE_SHIFT) + +#define USB_ENDPOINT_MAX_ADJUSTABLE (1 << 7) + +/* wMaxPacketSize in Endpoint Descriptor */ +#define USB_MAXPACKETSIZE_SHIFT 0 +#define USB_MAXPACKETSIZE_MASK (0x7ff << USB_MAXPACKETSIZE_SHIFT) +#define USB_MAXPACKETSIZE_ADDITIONAL_TRANSCATION_SHIFT 11 +#define USB_MAXPACKETSIZE_ADDITIONAL_TRANSCATION_NONE (0 << USB_MAXPACKETSIZE_ADDITIONAL_TRANSCATION_SHIFT) +#define USB_MAXPACKETSIZE_ADDITIONAL_TRANSCATION_ONE (1 << USB_MAXPACKETSIZE_ADDITIONAL_TRANSCATION_SHIFT) +#define USB_MAXPACKETSIZE_ADDITIONAL_TRANSCATION_TWO (2 << USB_MAXPACKETSIZE_ADDITIONAL_TRANSCATION_SHIFT) +#define USB_MAXPACKETSIZE_ADDITIONAL_TRANSCATION_MASK (3 << USB_MAXPACKETSIZE_ADDITIONAL_TRANSCATION_SHIFT) +#define USB_GET_MAXPACKETSIZE(x) ((x & USB_MAXPACKETSIZE_MASK) >> USB_MAXPACKETSIZE_SHIFT) +#define USB_GET_MULT(x) ((x & USB_MAXPACKETSIZE_ADDITIONAL_TRANSCATION_MASK) >> USB_MAXPACKETSIZE_ADDITIONAL_TRANSCATION_SHIFT) + +/* bDevCapabilityType in Device Capability Descriptor */ +#define USB_DEVICE_CAPABILITY_WIRELESS_USB 1 +#define USB_DEVICE_CAPABILITY_USB_2_0_EXTENSION 2 +#define USB_DEVICE_CAPABILITY_SUPERSPEED_USB 3 +#define USB_DEVICE_CAPABILITY_CONTAINER_ID 4 +#define USB_DEVICE_CAPABILITY_PLATFORM 5 +#define USB_DEVICE_CAPABILITY_POWER_DELIVERY_CAPABILITY 6 +#define USB_DEVICE_CAPABILITY_BATTERY_INFO_CAPABILITY 7 +#define USB_DEVICE_CAPABILITY_PD_CONSUMER_PORT_CAPABILITY 8 +#define USB_DEVICE_CAPABILITY_PD_PROVIDER_PORT_CAPABILITY 9 +#define USB_DEVICE_CAPABILITY_SUPERSPEED_PLUS 10 +#define USB_DEVICE_CAPABILITY_PRECISION_TIME_MEASUREMENT 11 +#define USB_DEVICE_CAPABILITY_WIRELESS_USB_EXT 12 + +#define USB_BOS_CAPABILITY_EXTENSION 0x02 +#define USB_BOS_CAPABILITY_PLATFORM 0x05 + +/* OTG SET FEATURE Constants */ +#define USB_OTG_FEATURE_B_HNP_ENABLE 3 /* Enable B device to perform HNP */ +#define USB_OTG_FEATURE_A_HNP_SUPPORT 4 /* A device supports HNP */ +#define USB_OTG_FEATURE_A_ALT_HNP_SUPPORT 5 /* Another port on the A device supports HNP */ + +/* WinUSB Microsoft OS 2.0 descriptor request codes */ +#define WINUSB_REQUEST_GET_DESCRIPTOR_SET 0x07 +#define WINUSB_REQUEST_SET_ALT_ENUM 0x08 + +/* WinUSB Microsoft OS 2.0 descriptor sizes */ +#define WINUSB_DESCRIPTOR_SET_HEADER_SIZE 10 +#define WINUSB_FUNCTION_SUBSET_HEADER_SIZE 8 +#define WINUSB_FEATURE_COMPATIBLE_ID_SIZE 20 + +/* WinUSB Microsoft OS 2.0 Descriptor Types */ +#define WINUSB_SET_HEADER_DESCRIPTOR_TYPE 0x00 +#define WINUSB_SUBSET_HEADER_CONFIGURATION_TYPE 0x01 +#define WINUSB_SUBSET_HEADER_FUNCTION_TYPE 0x02 +#define WINUSB_FEATURE_COMPATIBLE_ID_TYPE 0x03 +#define WINUSB_FEATURE_REG_PROPERTY_TYPE 0x04 +#define WINUSB_FEATURE_MIN_RESUME_TIME_TYPE 0x05 +#define WINUSB_FEATURE_MODEL_ID_TYPE 0x06 +#define WINUSB_FEATURE_CCGP_DEVICE_TYPE 0x07 + +#define WINUSB_PROP_DATA_TYPE_REG_SZ 0x01 +#define WINUSB_PROP_DATA_TYPE_REG_MULTI_SZ 0x07 + +/* WebUSB Descriptor Types */ +#define WEBUSB_DESCRIPTOR_SET_HEADER_TYPE 0x00 +#define WEBUSB_CONFIGURATION_SUBSET_HEADER_TYPE 0x01 +#define WEBUSB_FUNCTION_SUBSET_HEADER_TYPE 0x02 +#define WEBUSB_URL_TYPE 0x03 + +/* WebUSB Request Codes */ +#define WEBUSB_REQUEST_GET_URL 0x02 + +/* bScheme in URL descriptor */ +#define WEBUSB_URL_SCHEME_HTTP 0x00 +#define WEBUSB_URL_SCHEME_HTTPS 0x01 + +/* WebUSB Descriptor sizes */ +#define WEBUSB_DESCRIPTOR_SET_HEADER_SIZE 5 +#define WEBUSB_CONFIGURATION_SUBSET_HEADER_SIZE 4 +#define WEBUSB_FUNCTION_SUBSET_HEADER_SIZE 3 + +/* Setup packet definition used to read raw data from USB line */ +struct usb_setup_packet { + /** Request type. Bits 0:4 determine recipient, see + * \ref usb_request_recipient. Bits 5:6 determine type, see + * \ref usb_request_type. Bit 7 determines data transfer direction, see + * \ref usb_endpoint_direction. + */ + uint8_t bmRequestType; + + /** Request. If the type bits of bmRequestType are equal to + * \ref usb_request_type::LIBUSB_REQUEST_TYPE_STANDARD + * "USB_REQUEST_TYPE_STANDARD" then this field refers to + * \ref usb_standard_request. For other cases, use of this field is + * application-specific. */ + uint8_t bRequest; + + /** Value. Varies according to request */ + uint16_t wValue; + + /** Index. Varies according to request, typically used to pass an index + * or offset */ + uint16_t wIndex; + + /** Number of bytes to transfer */ + uint16_t wLength; +} __PACKED; + +#define USB_SIZEOF_SETUP_PACKET 8 + +/** Standard Device Descriptor */ +struct usb_device_descriptor { + uint8_t bLength; /* Descriptor size in bytes = 18 */ + uint8_t bDescriptorType; /* DEVICE descriptor type = 1 */ + uint16_t bcdUSB; /* USB spec in BCD, e.g. 0x0200 */ + uint8_t bDeviceClass; /* Class code, if 0 see interface */ + uint8_t bDeviceSubClass; /* Sub-Class code, 0 if class = 0 */ + uint8_t bDeviceProtocol; /* Protocol, if 0 see interface */ + uint8_t bMaxPacketSize0; /* Endpoint 0 max. size */ + uint16_t idVendor; /* Vendor ID per USB-IF */ + uint16_t idProduct; /* Product ID per manufacturer */ + uint16_t bcdDevice; /* Device release # in BCD */ + uint8_t iManufacturer; /* Index to manufacturer string */ + uint8_t iProduct; /* Index to product string */ + uint8_t iSerialNumber; /* Index to serial number string */ + uint8_t bNumConfigurations; /* Number of possible configurations */ +} __PACKED; + +#define USB_SIZEOF_DEVICE_DESC 18 + +/** Standard Configuration Descriptor */ +struct usb_configuration_descriptor { + uint8_t bLength; /* Descriptor size in bytes = 9 */ + uint8_t bDescriptorType; /* CONFIGURATION type = 2 or 7 */ + uint16_t wTotalLength; /* Length of concatenated descriptors */ + uint8_t bNumInterfaces; /* Number of interfaces, this config. */ + uint8_t bConfigurationValue; /* Value to set this config. */ + uint8_t iConfiguration; /* Index to configuration string */ + uint8_t bmAttributes; /* Config. characteristics */ + uint8_t bMaxPower; /* Max.power from bus, 2mA units */ +} __PACKED; + +#define USB_SIZEOF_CONFIG_DESC 9 + +/** Standard Interface Descriptor */ +struct usb_interface_descriptor { + uint8_t bLength; /* Descriptor size in bytes = 9 */ + uint8_t bDescriptorType; /* INTERFACE descriptor type = 4 */ + uint8_t bInterfaceNumber; /* Interface no.*/ + uint8_t bAlternateSetting; /* Value to select this IF */ + uint8_t bNumEndpoints; /* Number of endpoints excluding 0 */ + uint8_t bInterfaceClass; /* Class code, 0xFF = vendor */ + uint8_t bInterfaceSubClass; /* Sub-Class code, 0 if class = 0 */ + uint8_t bInterfaceProtocol; /* Protocol, 0xFF = vendor */ + uint8_t iInterface; /* Index to interface string */ +} __PACKED; + +#define USB_SIZEOF_INTERFACE_DESC 9 + +/** Standard Endpoint Descriptor */ +struct usb_endpoint_descriptor { + uint8_t bLength; /* Descriptor size in bytes = 7 */ + uint8_t bDescriptorType; /* ENDPOINT descriptor type = 5 */ + uint8_t bEndpointAddress; /* Endpoint # 0 - 15 | IN/OUT */ + uint8_t bmAttributes; /* Transfer type */ + uint16_t wMaxPacketSize; /* Bits 10:0 = max. packet size */ + uint8_t bInterval; /* Polling interval in (micro) frames */ +} __PACKED; + +#define USB_SIZEOF_ENDPOINT_DESC 7 + +/** Unicode (UTF16LE) String Descriptor */ +struct usb_string_descriptor { + uint8_t bLength; + uint8_t bDescriptorType; + uint16_t bString; +} __PACKED; + +#define USB_SIZEOF_STRING_LANGID_DESC 4 + +/* USB Interface Association Descriptor */ +struct usb_interface_association_descriptor { + uint8_t bLength; + uint8_t bDescriptorType; + uint8_t bFirstInterface; + uint8_t bInterfaceCount; + uint8_t bFunctionClass; + uint8_t bFunctionSubClass; + uint8_t bFunctionProtocol; + uint8_t iFunction; +} __PACKED; + +#define USB_SIZEOF_IAD_DESC 8 + +/** USB device_qualifier descriptor */ +struct usb_device_qualifier_descriptor { + uint8_t bLength; /* Descriptor size in bytes = 10 */ + uint8_t bDescriptorType; /* DEVICE QUALIFIER type = 6 */ + uint16_t bcdUSB; /* USB spec in BCD, e.g. 0x0200 */ + uint8_t bDeviceClass; /* Class code, if 0 see interface */ + uint8_t bDeviceSubClass; /* Sub-Class code, 0 if class = 0 */ + uint8_t bDeviceProtocol; /* Protocol, if 0 see interface */ + uint8_t bMaxPacketSize; /* Endpoint 0 max. size */ + uint8_t bNumConfigurations; /* Number of possible configurations */ + uint8_t bReserved; /* Reserved = 0 */ +} __PACKED; + +#define USB_SIZEOF_DEVICE_QUALIFIER_DESC 10 + +/* Microsoft OS function descriptor. + * This can be used to request a specific driver (such as WINUSB) to be + * loaded on Windows. Unlike other descriptors, it is requested by a special + * request USB_REQ_GETMSFTOSDESCRIPTOR. + * More details: + * https://msdn.microsoft.com/en-us/windows/hardware/gg463179 + * And excellent explanation: + * https://github.com/pbatard/libwdi/wiki/WCID-Devices + * + * The device will have exactly one "Extended Compat ID Feature Descriptor", + * which may contain multiple "Function Descriptors" associated with + * different interfaces. + */ + +/* MS OS 1.0 string descriptor */ +struct usb_msosv1_string_descriptor { + uint8_t bLength; + uint8_t bDescriptorType; + uint8_t bString[14]; + uint8_t bMS_VendorCode; /* Vendor Code, used for a control request */ + uint8_t bPad; /* Padding byte for VendorCode look as UTF16 */ +} __PACKED; + +/* MS OS 1.0 Header descriptor */ +struct usb_msosv1_compat_id_header_descriptor { + uint32_t dwLength; + uint16_t bcdVersion; + uint16_t wIndex; + uint8_t bCount; + uint8_t reserved[7]; +} __PACKED; + +/* MS OS 1.0 Function descriptor */ +struct usb_msosv1_comp_id_function_descriptor { + uint8_t bFirstInterfaceNumber; + uint8_t reserved1; + uint8_t compatibleID[8]; + uint8_t subCompatibleID[8]; + uint8_t reserved2[6]; +} __PACKED; + +#define usb_msosv1_comp_id_create(x) \ + struct usb_msosv1_comp_id { \ + struct usb_msosv1_compat_id_header_descriptor compat_id_header; \ + struct usb_msosv1_comp_id_function_descriptor compat_id_function[x]; \ + }; + +struct usb_msosv1_descriptor { + const uint8_t *string; + uint8_t vendor_code; + const uint8_t *compat_id; + const uint8_t **comp_id_property; +}; + +/* MS OS 2.0 Header descriptor */ +struct usb_msosv2_header_descriptor { + uint32_t dwLength; + uint16_t bcdVersion; + uint16_t wIndex; + uint8_t bCount; +} __PACKED; + +/*Microsoft OS 2.0 set header descriptor*/ +struct usb_msosv2_set_header_descriptor { + uint16_t wLength; + uint16_t wDescriptorType; + uint32_t dwWindowsVersion; + uint16_t wDescriptorSetTotalLength; +} __PACKED; + +/* Microsoft OS 2.0 compatibleID descriptor*/ +struct usb_msosv2_comp_id_descriptor { + uint16_t wLength; + uint16_t wDescriptorType; + uint8_t compatibleID[8]; + uint8_t subCompatibleID[8]; +} __PACKED; + +/* MS OS 2.0 property descriptor */ +struct usb_msosv2_property_descriptor { + uint16_t wLength; + uint16_t wDescriptorType; + uint32_t dwPropertyDataType; + uint16_t wPropertyNameLength; + const char *bPropertyName; + uint32_t dwPropertyDataLength; + const char *bPropertyData; +}; + +/* Microsoft OS 2.0 subset function descriptor */ +struct usb_msosv2_subset_function_descriptor { + uint16_t wLength; + uint16_t wDescriptorType; + uint8_t bFirstInterface; + uint8_t bReserved; + uint16_t wSubsetLength; +} __PACKED; + +struct usb_msosv2_descriptor { + const uint8_t *compat_id; + uint16_t compat_id_len; + uint8_t vendor_code; +}; + +/* BOS header Descriptor */ +struct usb_bos_header_descriptor { + uint8_t bLength; + uint8_t bDescriptorType; + uint16_t wTotalLength; + uint8_t bNumDeviceCaps; +} __PACKED; + +/* BOS Capability platform Descriptor */ +struct usb_bos_capability_platform_common_descriptor { + uint8_t bLength; + uint8_t bDescriptorType; + uint8_t bDevCapabilityType; + uint8_t bReserved; + uint8_t PlatformCapabilityUUID[16]; +} __PACKED; + +/* Microsoft OS 2.0 Platform Capability Descriptor +* See https://docs.microsoft.com/en-us/windows-hardware/drivers/usbcon/ +* microsoft-defined-usb-descriptors +* Adapted from the source: +* https://github.com/sowbug/weblight/blob/master/firmware/webusb.c +* (BSD-2) Thanks http://janaxelson.com/files/ms_os_20_descriptors.c +*/ +struct usb_bos_capability_platform_winusb_descriptor { + struct usb_bos_capability_platform_common_descriptor common; + uint32_t dwWindowsVersion; + uint16_t wMSOSDescriptorSetTotalLength; + uint8_t bVendorCode; + uint8_t bAltEnumCode; +} __PACKED; + +/* WebUSB Platform Capability Descriptor: +* https://wicg.github.io/webusb/#webusb-platform-capability-descriptor +*/ +struct usb_bos_capability_platform_webusb_descriptor { + struct usb_bos_capability_platform_common_descriptor common; + uint16_t bcdVersion; + uint8_t bVendorCode; + uint8_t iLandingPage; +} __PACKED; + +/* BOS Capability extension Descriptor*/ +struct usb_bos_capability_extension_descriptor { + uint8_t bLength; + uint8_t bDescriptorType; + uint8_t bDevCapabilityType; + uint32_t bmAttributes; +} __PACKED; + +struct usb_webusb_url_descriptor { + uint8_t bLength; + uint8_t bDescriptorType; + uint8_t bScheme; + char URL[]; +} __PACKED; + +struct usb_webusb_descriptor { + uint8_t vendor_code; + const uint8_t *string; + uint32_t string_len; +} __PACKED; + +struct usb_bos_descriptor { + const uint8_t *string; + uint32_t string_len; +}; + +/** USB descriptor header */ +struct usb_desc_header { + uint8_t bLength; /**< descriptor length */ + uint8_t bDescriptorType; /**< descriptor type */ +}; + +// clang-format off +#define USB_DEVICE_DESCRIPTOR_INIT(bcdUSB, bDeviceClass, bDeviceSubClass, bDeviceProtocol, idVendor, idProduct, bcdDevice, bNumConfigurations) \ + 0x12, /* bLength */ \ + USB_DESCRIPTOR_TYPE_DEVICE, /* bDescriptorType */ \ + WBVAL(bcdUSB), /* bcdUSB */ \ + bDeviceClass, /* bDeviceClass */ \ + bDeviceSubClass, /* bDeviceSubClass */ \ + bDeviceProtocol, /* bDeviceProtocol */ \ + 0x40, /* bMaxPacketSize */ \ + WBVAL(idVendor), /* idVendor */ \ + WBVAL(idProduct), /* idProduct */ \ + WBVAL(bcdDevice), /* bcdDevice */ \ + USB_STRING_MFC_INDEX, /* iManufacturer */ \ + USB_STRING_PRODUCT_INDEX, /* iProduct */ \ + USB_STRING_SERIAL_INDEX, /* iSerial */ \ + bNumConfigurations /* bNumConfigurations */ + +#define USB_CONFIG_DESCRIPTOR_INIT(wTotalLength, bNumInterfaces, bConfigurationValue, bmAttributes, bMaxPower) \ + 0x09, /* bLength */ \ + USB_DESCRIPTOR_TYPE_CONFIGURATION, /* bDescriptorType */ \ + WBVAL(wTotalLength), /* wTotalLength */ \ + bNumInterfaces, /* bNumInterfaces */ \ + bConfigurationValue, /* bConfigurationValue */ \ + 0x00, /* iConfiguration */ \ + bmAttributes, /* bmAttributes */ \ + USB_CONFIG_POWER_MA(bMaxPower) /* bMaxPower */ + +#define USB_DEVICE_QUALIFIER_DESCRIPTOR_INIT(bcdUSB, bDeviceClass, bDeviceSubClass, bDeviceProtocol, bNumConfigurations) \ + 0x0A, /* bLength */ \ + USB_DESCRIPTOR_TYPE_DEVICE_QUALIFIER, /* bDescriptorType */ \ + WBVAL(bcdUSB), /* bcdUSB */ \ + bDeviceClass, /* bDeviceClass */ \ + bDeviceSubClass, /* bDeviceSubClass */ \ + bDeviceProtocol, /* bDeviceProtocol */ \ + 0x40, /* bMaxPacketSize */ \ + bNumConfigurations, /* bNumConfigurations */ \ + 0x00 /* bReserved */ + +#define USB_OTHER_SPEED_CONFIG_DESCRIPTOR_INIT(wTotalLength, bNumInterfaces, bConfigurationValue, bmAttributes, bMaxPower) \ + 0x09, /* bLength */ \ + USB_DESCRIPTOR_TYPE_OTHER_SPEED, /* bDescriptorType */ \ + WBVAL(wTotalLength), /* wTotalLength */ \ + bNumInterfaces, /* bNumInterfaces */ \ + bConfigurationValue, /* bConfigurationValue */ \ + 0x00, /* iConfiguration */ \ + bmAttributes, /* bmAttributes */ \ + USB_CONFIG_POWER_MA(bMaxPower) /* bMaxPower */ + +#define USB_INTERFACE_DESCRIPTOR_INIT(bInterfaceNumber, bAlternateSetting, bNumEndpoints, \ + bInterfaceClass, bInterfaceSubClass, bInterfaceProtocol, iInterface) \ + 0x09, /* bLength */ \ + USB_DESCRIPTOR_TYPE_INTERFACE, /* bDescriptorType */ \ + bInterfaceNumber, /* bInterfaceNumber */ \ + bAlternateSetting, /* bAlternateSetting */ \ + bNumEndpoints, /* bNumEndpoints */ \ + bInterfaceClass, /* bInterfaceClass */ \ + bInterfaceSubClass, /* bInterfaceSubClass */ \ + bInterfaceProtocol, /* bInterfaceProtocol */ \ + iInterface /* iInterface */ + +#define USB_ENDPOINT_DESCRIPTOR_INIT(bEndpointAddress, bmAttributes, wMaxPacketSize, bInterval) \ + 0x07, /* bLength */ \ + USB_DESCRIPTOR_TYPE_ENDPOINT, /* bDescriptorType */ \ + bEndpointAddress, /* bEndpointAddress */ \ + bmAttributes, /* bmAttributes */ \ + WBVAL(wMaxPacketSize), /* wMaxPacketSize */ \ + bInterval /* bInterval */ + +#define USB_IAD_DESCRIPTOR_INIT(bFirstInterface, bInterfaceCount, bFunctionClass, bFunctionSubClass, bFunctionProtocol) \ + 0x08, /* bLength */ \ + USB_DESCRIPTOR_TYPE_INTERFACE_ASSOCIATION, /* bDescriptorType */ \ + bFirstInterface, /* bFirstInterface */ \ + bInterfaceCount, /* bInterfaceCount */ \ + bFunctionClass, /* bFunctionClass */ \ + bFunctionSubClass, /* bFunctionSubClass */ \ + bFunctionProtocol, /* bFunctionProtocol */ \ + 0x00 /* iFunction */ + +#define USB_LANGID_INIT(id) \ + 0x04, /* bLength */ \ + USB_DESCRIPTOR_TYPE_STRING, /* bDescriptorType */ \ + WBVAL(id) /* wLangID0 */ + +#define USB_BOS_HEADER_DESCRIPTOR_INIT(wTotalLength, bNumDeviceCaps) \ + 0x05, /* bLength */ \ + USB_DESCRIPTOR_TYPE_BINARY_OBJECT_STORE, /* bDescriptorType */\ + WBVAL(wTotalLength), /* wTotalLength */ \ + bNumDeviceCaps /* bNumDeviceCaps */ + +#define USB_BOS_CAP_PLATFORM_WEBUSB_DESCRIPTOR_INIT(bVendorCode, iLandingPage) \ + 0x18, /* bLength */ \ + USB_DESCRIPTOR_TYPE_DEVICE_CAPABILITY, /* bDescriptorType */ \ + USB_DEVICE_CAPABILITY_PLATFORM, /* bDevCapabilityType */ \ + 0x00, /* bReserved */ \ + 0x38, 0xB6, 0x08, 0x34, 0xA9, 0x09, 0xA0, 0x47, /* PlatformCapabilityUUID */ \ + 0x8B, 0xFD, 0xA0, 0x76, 0x88, 0x15, 0xB6, 0x65, \ + WBVAL(0x0100), /* bcdVersion */ \ + bVendorCode, /* bVendorCode */ \ + iLandingPage /* iLandingPage */ + +#define USB_BOS_CAP_PLATFORM_WINUSB_DESCRIPTOR_INIT(bVendorCode, wMSOSDescriptorSetTotalLength) \ + 0x1C, /* bLength */ \ + USB_DESCRIPTOR_TYPE_DEVICE_CAPABILITY, /* bDescriptorType */ \ + USB_DEVICE_CAPABILITY_PLATFORM, /* bDevCapabilityType */ \ + 0x00, /* bReserved */ \ + 0xDF, 0x60, 0xDD, 0xD8, 0x89, 0x45, 0xC7, 0x4C, /* PlatformCapabilityUUID */ \ + 0x9C, 0xD2, 0x65, 0x9D, 0x9E, 0x64, 0x8A, 0x9F, \ + DBVAL(0x06030000), /* dwWindowsVersion */ \ + WBVAL(wMSOSDescriptorSetTotalLength), /* wMSOSDescriptorSetTotalLength */ \ + bVendorCode, /* bVendorCode */ \ + 0x00 /* bAltEnumCode */ + +#define USB_BOS_CAP_PLATFORM_WEBUSB_DESCRIPTOR_LEN 24 +#define USB_BOS_CAP_PLATFORM_WINUSB_DESCRIPTOR_LEN 28 + +#define USB_MSOSV1_STRING_DESCRIPTOR_INIT(vendor_code) \ + 0x12, /* bLength */ \ + USB_DESCRIPTOR_TYPE_STRING, /* bDescriptorType */ \ + 'M', 0, /* bString[0] */ \ + 'S', 0, /* bString[1] */ \ + 'F', 0, /* bString[2] */ \ + 'T', 0, /* bString[3] */ \ + '1', 0, /* bString[4] */ \ + '0', 0, /* bString[5] */ \ + '0', 0, /* bString[6] */ \ + vendor_code, /* bMS_VendorCode */ \ + 0x00 /* bPad */ + +#define USB_MSOSV1_COMP_ID_HEADER_DESCRIPTOR_INIT(bCount) \ + DBVAL((sizeof(struct usb_msosv1_compat_id_header_descriptor) + sizeof(struct usb_msosv1_comp_id_function_descriptor) * bCount)), /* dwLength */ \ + WBVAL(0x0100), /* bcdVersion */ \ + WBVAL(0x0004), /* wIndex */ \ + bCount, /* bCount */ \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 /* reserved[7] */ + +#define USB_MSOSV1_COMP_ID_FUNCTION_WINUSB_DESCRIPTOR_INIT(bFirstInterfaceNumber) \ + bFirstInterfaceNumber, /* bFirstInterfaceNumber */\ + 0x01, /* reserved1 */ \ + 'W', 'I', 'N', 'U', 'S', 'B', 0x00, 0x00, /* compatibleID[8] */ \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* subCompatibleID[8] */ \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 /* reserved2[6] */ + +#define USB_MSOSV1_COMP_ID_FUNCTION_MTP_DESCRIPTOR_INIT(bFirstInterfaceNumber)\ + bFirstInterfaceNumber, /* bFirstInterfaceNumber */\ + 0x01, /* reserved1 */ \ + 'M', 'T', 'P', 'U', 'S', 'B', 0x00, 0x00, /* compatibleID[8] */ \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* subCompatibleID[8] */ \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 /* reserved2[6] */ + +#define USB_MSOSV1_COMP_ID_FUNCTION_ADB_DESCRIPTOR_INIT(bFirstInterfaceNumber)\ + bFirstInterfaceNumber, * bFirstInterfaceNumber */\ + 0x01, /* reserved1 */ \ + 'A', 'D', 'B', 0x00, 0x00, 0x00, 0x00, 0x00, /* compatibleID[8] */ \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* subCompatibleID[8] */ \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 /* reserved2[6] */ + +#define USB_MSOSV1_COMP_ID_DESCRIPTOR_LEN(bCount) \ + (sizeof(struct usb_msosv1_compat_id_header_descriptor) + sizeof(struct usb_msosv1_comp_id_function_descriptor) * (bCount)) + +#define USB_MSOSV2_COMP_ID_SET_HEADER_DESCRIPTOR_INIT(wDescriptorSetTotalLength) \ + WBVAL(WINUSB_DESCRIPTOR_SET_HEADER_SIZE), /* wLength */ \ + WBVAL(WINUSB_SET_HEADER_DESCRIPTOR_TYPE), /* wDescriptorType */ \ + DBVAL(0x06030000), /* dwWindowsVersion */ \ + WBVAL(wDescriptorSetTotalLength) /* wDescriptorSetTotalLength */ + +#define USB_MSOSV2_COMP_ID_FUNCTION_WINUSB_SINGLE_DESCRIPTOR_INIT() \ + WBVAL(WINUSB_FEATURE_COMPATIBLE_ID_SIZE), /* wLength */ \ + WBVAL(WINUSB_FEATURE_COMPATIBLE_ID_TYPE), /* wDescriptorType */ \ + 'W', 'I', 'N', 'U', 'S', 'B', 0, 0, /* CompatibleId*/ \ + 0, 0, 0, 0, 0, 0, 0, 0, /* SubCompatibleId*/ \ + WBVAL(132), /* wLength */ \ + WBVAL(WINUSB_FEATURE_REG_PROPERTY_TYPE), /* wDescriptorType */ \ + WBVAL(WINUSB_PROP_DATA_TYPE_REG_SZ), /* wPropertyDataType */ \ + WBVAL(42), /* wPropertyNameLength bPropertyName: "DeviceInterfaceGUID" */ \ + 'D', 0, 'e', 0, 'v', 0, 'i', 0, 'c', 0, 'e', 0, \ + 'I', 0, 'n', 0, 't', 0, 'e', 0, 'r', 0, 'f', 0, 'a', 0, 'c', 0, 'e', 0, \ + 'G', 0, 'U', 0, 'I', 0, 'D', 0, 's', 0, 0, 0, \ + WBVAL(80), /* wPropertyDataLength */ \ + '{', 0, \ + 'C', 0, 'D', 0, 'B', 0, '3', 0, 'B', 0, '5', 0, 'A', 0, 'D', 0, '-', 0, \ + '2', 0, '9', 0, '3', 0, 'B', 0, '-', 0, \ + '4', 0, '6', 0, '6', 0, '3', 0, '-', 0, \ + 'A', 0, 'A', 0, '3', 0, '6', 0, '-', \ + 0, '1', 0, 'A', 0, 'A', 0, 'E', 0, '4', 0, '6', 0, '4', 0, '6', 0, '3', 0, '7', 0, '7', 0, '6', 0, \ + '}', 0, 0, 0, 0, 0 + +#define USB_MSOSV2_COMP_ID_FUNCTION_WINUSB_SINGLE_DESCRIPTOR_LEN \ + (WINUSB_FEATURE_COMPATIBLE_ID_SIZE + 132) + +#define USB_MSOSV2_COMP_ID_FUNCTION_WINUSB_MULTI_DESCRIPTOR_INIT(bFirstInterfaceNumber) \ + WBVAL(WINUSB_FUNCTION_SUBSET_HEADER_SIZE), /* wLength */ \ + WBVAL(WINUSB_SUBSET_HEADER_FUNCTION_TYPE), /* wDescriptorType */ \ + bFirstInterfaceNumber, /* bFirstInterface*/ \ + 0, /* bReserved */ \ + WBVAL((WINUSB_FUNCTION_SUBSET_HEADER_SIZE + WINUSB_FEATURE_COMPATIBLE_ID_SIZE + 132)), /* wSubsetLength */\ + WBVAL(WINUSB_FEATURE_COMPATIBLE_ID_SIZE), /* wLength */ \ + WBVAL(WINUSB_FEATURE_COMPATIBLE_ID_TYPE), /* wDescriptorType */ \ + 'W', 'I', 'N', 'U', 'S', 'B', 0, 0, /* CompatibleId*/ \ + 0, 0, 0, 0, 0, 0, 0, 0, /* SubCompatibleId*/ \ + WBVAL(132), /* wLength */ \ + WBVAL(WINUSB_FEATURE_REG_PROPERTY_TYPE), /* wDescriptorType */ \ + WBVAL(WINUSB_PROP_DATA_TYPE_REG_MULTI_SZ), /* wPropertyDataType */ \ + WBVAL(42), /* wPropertyNameLength bPropertyName: "DeviceInterfaceGUID" */ \ + 'D', 0, 'e', 0, 'v', 0, 'i', 0, 'c', 0, 'e', 0, \ + 'I', 0, 'n', 0, 't', 0, 'e', 0, 'r', 0, 'f', 0, 'a', 0, 'c', 0, 'e', 0, \ + 'G', 0, 'U', 0, 'I', 0, 'D', 0, 's', 0, 0, 0, \ + WBVAL(80), /* wPropertyDataLength */ \ + '{', 0, \ + 'C', 0, 'D', 0, 'B', 0, '3', 0, 'B', 0, '5', 0, 'A', 0, 'D', 0, '-', 0, \ + '2', 0, '9', 0, '3', 0, 'B', 0, '-', 0, \ + '4', 0, '6', 0, '6', 0, '3', 0, '-', 0, \ + 'A', 0, 'A', 0, '3', 0, '6', 0, '-', \ + 0, '1', 0, 'A', 0, 'A', 0, 'E', 0, '4', 0, '6', 0, '4', 0, '6', 0, '3', 0, '7', 0, '7', 0, '6', 0, \ + '}', 0, 0, 0, 0, 0 + +#define USB_MSOSV2_COMP_ID_FUNCTION_WINUSB_MULTI_DESCRIPTOR_LEN \ + (WINUSB_FUNCTION_SUBSET_HEADER_SIZE + WINUSB_FEATURE_COMPATIBLE_ID_SIZE + 132) + +// clang-format on + +#endif /* USB_DEF_H */ diff --git a/kernel/cherryusb/common/usb_errno.h b/kernel/cherryusb/common/usb_errno.h new file mode 100644 index 0000000..284020a --- /dev/null +++ b/kernel/cherryusb/common/usb_errno.h @@ -0,0 +1,24 @@ +/* + * Copyright (c) 2023, sakumisu + * + * SPDX-License-Identifier: Apache-2.0 + */ +#ifndef USB_ERRNO_H +#define USB_ERRNO_H + +#define USB_ERR_NOMEM 1 +#define USB_ERR_INVAL 2 +#define USB_ERR_NODEV 3 +#define USB_ERR_NOTCONN 4 +#define USB_ERR_NOTSUPP 5 +#define USB_ERR_BUSY 6 +#define USB_ERR_RANGE 7 +#define USB_ERR_STALL 8 +#define USB_ERR_BABBLE 9 +#define USB_ERR_NAK 10 /* only for dwc2 buffer dma mode */ +#define USB_ERR_DT 11 +#define USB_ERR_IO 12 +#define USB_ERR_SHUTDOWN 13 +#define USB_ERR_TIMEOUT 14 + +#endif /* USB_ERRNO_H */ diff --git a/kernel/cherryusb/common/usb_hc.h b/kernel/cherryusb/common/usb_hc.h new file mode 100644 index 0000000..aa411ee --- /dev/null +++ b/kernel/cherryusb/common/usb_hc.h @@ -0,0 +1,118 @@ +/* + * Copyright (c) 2022, sakumisu + * + * SPDX-License-Identifier: Apache-2.0 + */ +#ifndef USB_HC_H +#define USB_HC_H + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +typedef void (*usbh_complete_callback_t)(void *arg, int nbytes); + +struct usbh_bus; + +/** + * @brief USB Iso Configuration. + * + * Structure containing the USB Iso configuration. + */ +struct usbh_iso_frame_packet { + uint8_t *transfer_buffer; + uint32_t transfer_buffer_length; + uint32_t actual_length; + int errorcode; +}; + +/** + * @brief USB Urb Configuration. + * + * Structure containing the USB Urb configuration. + */ +struct usbh_urb { + usb_slist_t list; + void *hcpriv; + struct usbh_hubport *hport; + struct usb_endpoint_descriptor *ep; + uint8_t data_toggle; + uint32_t interval; + struct usb_setup_packet *setup; + uint8_t *transfer_buffer; + uint32_t transfer_buffer_length; + int transfer_flags; + uint32_t actual_length; + uint32_t timeout; + int errorcode; + uint32_t num_of_iso_packets; + uint32_t start_frame; + usbh_complete_callback_t complete; + void *arg; +#if defined(__ICCARM__) || defined(__ICCRISCV__) || defined(__ICCRX__) + struct usbh_iso_frame_packet *iso_packet; +#else + struct usbh_iso_frame_packet iso_packet[0]; +#endif +}; + +/** + * @brief usb host controller hardware init. + * + * @return On success will return 0, and others indicate fail. + */ +int usb_hc_init(struct usbh_bus *bus); + +/** + * @brief usb host controller hardware deinit. + * + * @return On success will return 0, and others indicate fail. + */ +int usb_hc_deinit(struct usbh_bus *bus); + +/** + * @brief Get frame number. + * + * @return frame number. + */ +uint16_t usbh_get_frame_number(struct usbh_bus *bus); +/** + * @brief control roothub. + * + * @param setup setup request buffer. + * @param buf buf for reading response or write data. + * @return On success will return 0, and others indicate fail. + */ +int usbh_roothub_control(struct usbh_bus *bus, struct usb_setup_packet *setup, uint8_t *buf); + +/** + * @brief Submit a usb transfer request to an endpoint. + * + * If timeout is not zero, this function will be in poll transfer mode, + * otherwise will be in async transfer mode. + * + * @param urb Usb request block. + * @return On success will return 0, and others indicate fail. + */ +int usbh_submit_urb(struct usbh_urb *urb); + +/** + * @brief Cancel a transfer request. + * + * This function will call When calls usbh_submit_urb and return -USB_ERR_TIMEOUT or -USB_ERR_SHUTDOWN. + * + * @param urb Usb request block. + * @return On success will return 0, and others indicate fail. + */ +int usbh_kill_urb(struct usbh_urb *urb); + +/* called by user */ +void USBH_IRQHandler(uint8_t busid); + +#ifdef __cplusplus +} +#endif + +#endif /* USB_HC_H */ diff --git a/kernel/cherryusb/common/usb_list.h b/kernel/cherryusb/common/usb_list.h new file mode 100644 index 0000000..3078a1f --- /dev/null +++ b/kernel/cherryusb/common/usb_list.h @@ -0,0 +1,459 @@ +/* + * Copyright (c) 2022, sakumisu + * + * SPDX-License-Identifier: Apache-2.0 + */ +#ifndef USB_LIST_H +#define USB_LIST_H + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * usb_container_of - return the member address of ptr, if the type of ptr is the + * struct type. + */ +#define usb_container_of(ptr, type, member) \ + ((type *)((char *)(ptr) - (unsigned long)(&((type *)0)->member))) + +/** + * Single List structure + */ +struct usb_slist_node { + struct usb_slist_node *next; /**< point to next node. */ +}; +typedef struct usb_slist_node usb_slist_t; /**< Type for single list. */ + +/** + * @brief initialize a single list + * + * @param l the single list to be initialized + */ +static inline void usb_slist_init(usb_slist_t *l) +{ + l->next = NULL; +} + +static inline void usb_slist_add_head(usb_slist_t *l, usb_slist_t *n) +{ + n->next = l->next; + l->next = n; +} + +static inline void usb_slist_add_tail(usb_slist_t *l, usb_slist_t *n) +{ + usb_slist_t *tmp = l; + + while (tmp->next) { + tmp = tmp->next; + } + + /* append the node to the tail */ + tmp->next = n; + n->next = NULL; +} + +static inline void usb_slist_insert(usb_slist_t *l, usb_slist_t *next, usb_slist_t *n) +{ + if (!next) { + usb_slist_add_tail(next, l); + return; + } + + while (l->next) { + if (l->next == next) { + l->next = n; + n->next = next; + } + + l = l->next; + } +} + +static inline usb_slist_t *usb_slist_remove(usb_slist_t *l, usb_slist_t *n) +{ + usb_slist_t *tmp = l; + /* remove slist head */ + while (tmp->next && tmp->next != n) { + tmp = tmp->next; + } + + /* remove node */ + if (tmp->next != (usb_slist_t *)0) { + tmp->next = tmp->next->next; + } + + return l; +} + +static inline unsigned int usb_slist_len(const usb_slist_t *l) +{ + unsigned int len = 0; + const usb_slist_t *list = l->next; + + while (list != NULL) { + list = list->next; + len++; + } + + return len; +} + +static inline unsigned int usb_slist_contains(usb_slist_t *l, usb_slist_t *n) +{ + while (l->next) { + if (l->next == n) { + return 0; + } + + l = l->next; + } + + return 1; +} + +static inline usb_slist_t *usb_slist_head(usb_slist_t *l) +{ + return l->next; +} + +static inline usb_slist_t *usb_slist_tail(usb_slist_t *l) +{ + while (l->next) { + l = l->next; + } + + return l; +} + +static inline usb_slist_t *usb_slist_next(usb_slist_t *n) +{ + return n->next; +} + +static inline int usb_slist_isempty(usb_slist_t *l) +{ + return l->next == NULL; +} + +/** + * @brief initialize a slist object + */ +#define USB_SLIST_OBJECT_INIT(object) \ + { \ + NULL \ + } + +/** + * @brief initialize a slist object + */ +#define USB_SLIST_DEFINE(slist) \ + usb_slist_t slist = { NULL } + +/** + * @brief get the struct for this single list node + * @param node the entry point + * @param type the type of structure + * @param member the name of list in structure + */ +#define usb_slist_entry(node, type, member) \ + usb_container_of(node, type, member) + +/** + * usb_slist_first_entry - get the first element from a slist + * @ptr: the slist head to take the element from. + * @type: the type of the struct this is embedded in. + * @member: the name of the slist_struct within the struct. + * + * Note, that slist is expected to be not empty. + */ +#define usb_slist_first_entry(ptr, type, member) \ + usb_slist_entry((ptr)->next, type, member) + +/** + * usb_slist_tail_entry - get the tail element from a slist + * @ptr: the slist head to take the element from. + * @type: the type of the struct this is embedded in. + * @member: the name of the slist_struct within the struct. + * + * Note, that slist is expected to be not empty. + */ +#define usb_slist_tail_entry(ptr, type, member) \ + usb_slist_entry(usb_slist_tail(ptr), type, member) + +/** + * usb_slist_first_entry_or_null - get the first element from a slist + * @ptr: the slist head to take the element from. + * @type: the type of the struct this is embedded in. + * @member: the name of the slist_struct within the struct. + * + * Note, that slist is expected to be not empty. + */ +#define usb_slist_first_entry_or_null(ptr, type, member) \ + (usb_slist_isempty(ptr) ? NULL : usb_slist_first_entry(ptr, type, member)) + +/** + * usb_slist_for_each - iterate over a single list + * @pos: the usb_slist_t * to use as a loop cursor. + * @head: the head for your single list. + */ +#define usb_slist_for_each(pos, head) \ + for (pos = (head)->next; pos != NULL; pos = pos->next) + +#define usb_slist_for_each_safe(pos, next, head) \ + for (pos = (head)->next, next = pos->next; pos; \ + pos = next, next = pos->next) + +/** + * usb_slist_for_each_entry - iterate over single list of given type + * @pos: the type * to use as a loop cursor. + * @head: the head for your single list. + * @member: the name of the list_struct within the struct. + */ +#define usb_slist_for_each_entry(pos, head, member) \ + for (pos = usb_slist_entry((head)->next, typeof(*pos), member); \ + &pos->member != (NULL); \ + pos = usb_slist_entry(pos->member.next, typeof(*pos), member)) + +#define usb_slist_for_each_entry_safe(pos, n, head, member) \ + for (pos = usb_slist_entry((head)->next, typeof(*pos), member), \ + n = usb_slist_entry(pos->member.next, typeof(*pos), member); \ + &pos->member != (NULL); \ + pos = n, n = usb_slist_entry(pos->member.next, typeof(*pos), member)) + +/** + * Double List structure + */ +struct usb_dlist_node { + struct usb_dlist_node *next; /**< point to next node. */ + struct usb_dlist_node *prev; /**< point to prev node. */ +}; +typedef struct usb_dlist_node usb_dlist_t; /**< Type for lists. */ + +/** + * @brief initialize a list + * + * @param l list to be initialized + */ +static inline void usb_dlist_init(usb_dlist_t *l) +{ + l->next = l->prev = l; +} + +/** + * @brief insert a node after a list + * + * @param l list to insert it + * @param n new node to be inserted + */ +static inline void usb_dlist_insert_after(usb_dlist_t *l, usb_dlist_t *n) +{ + l->next->prev = n; + n->next = l->next; + + l->next = n; + n->prev = l; +} + +/** + * @brief insert a node before a list + * + * @param n new node to be inserted + * @param l list to insert it + */ +static inline void usb_dlist_insert_before(usb_dlist_t *l, usb_dlist_t *n) +{ + l->prev->next = n; + n->prev = l->prev; + + l->prev = n; + n->next = l; +} + +/** + * @brief remove node from list. + * @param n the node to remove from the list. + */ +static inline void usb_dlist_remove(usb_dlist_t *n) +{ + n->next->prev = n->prev; + n->prev->next = n->next; + + n->next = n->prev = n; +} + +/** + * @brief move node from list. + * @param n the node to remove from the list. + */ +static inline void usb_dlist_move_head(usb_dlist_t *l, usb_dlist_t *n) +{ + usb_dlist_remove(n); + usb_dlist_insert_after(l, n); +} + +/** + * @brief move node from list. + * @param n the node to remove from the list. + */ +static inline void usb_dlist_move_tail(usb_dlist_t *l, usb_dlist_t *n) +{ + usb_dlist_remove(n); + usb_dlist_insert_before(l, n); +} + +/** + * @brief tests whether a list is empty + * @param l the list to test. + */ +static inline int usb_dlist_isempty(const usb_dlist_t *l) +{ + return l->next == l; +} + +/** + * @brief get the list length + * @param l the list to get. + */ +static inline unsigned int usb_dlist_len(const usb_dlist_t *l) +{ + unsigned int len = 0; + const usb_dlist_t *p = l; + + while (p->next != l) { + p = p->next; + len++; + } + + return len; +} + +/** + * @brief initialize a dlist object + */ +#define USB_DLIST_OBJECT_INIT(object) \ + { \ + &(object), &(object) \ + } +/** + * @brief initialize a dlist object + */ +#define USB_DLIST_DEFINE(list) \ + usb_dlist_t list = { &(list), &(list) } + +/** + * @brief get the struct for this entry + * @param node the entry point + * @param type the type of structure + * @param member the name of list in structure + */ +#define usb_dlist_entry(node, type, member) \ + usb_container_of(node, type, member) + +/** + * dlist_first_entry - get the first element from a list + * @ptr: the list head to take the element from. + * @type: the type of the struct this is embedded in. + * @member: the name of the list_struct within the struct. + * + * Note, that list is expected to be not empty. + */ +#define usb_dlist_first_entry(ptr, type, member) \ + usb_dlist_entry((ptr)->next, type, member) +/** + * dlist_first_entry_or_null - get the first element from a list + * @ptr: the list head to take the element from. + * @type: the type of the struct this is embedded in. + * @member: the name of the list_struct within the struct. + * + * Note, that list is expected to be not empty. + */ +#define usb_dlist_first_entry_or_null(ptr, type, member) \ + (usb_dlist_isempty(ptr) ? NULL : usb_dlist_first_entry(ptr, type, member)) + +/** + * usb_dlist_for_each - iterate over a list + * @pos: the usb_dlist_t * to use as a loop cursor. + * @head: the head for your list. + */ +#define usb_dlist_for_each(pos, head) \ + for (pos = (head)->next; pos != (head); pos = pos->next) + +/** + * usb_dlist_for_each_prev - iterate over a list + * @pos: the dlist_t * to use as a loop cursor. + * @head: the head for your list. + */ +#define usb_dlist_for_each_prev(pos, head) \ + for (pos = (head)->prev; pos != (head); pos = pos->prev) + +/** + * usb_dlist_for_each_safe - iterate over a list safe against removal of list entry + * @pos: the dlist_t * to use as a loop cursor. + * @n: another dlist_t * to use as temporary storage + * @head: the head for your list. + */ +#define usb_dlist_for_each_safe(pos, n, head) \ + for (pos = (head)->next, n = pos->next; pos != (head); \ + pos = n, n = pos->next) + +#define usb_dlist_for_each_prev_safe(pos, n, head) \ + for (pos = (head)->prev, n = pos->prev; pos != (head); \ + pos = n, n = pos->prev) +/** + * usb_dlist_for_each_entry - iterate over list of given type + * @pos: the type * to use as a loop cursor. + * @head: the head for your list. + * @member: the name of the list_struct within the struct. + */ +#define usb_dlist_for_each_entry(pos, head, member) \ + for (pos = usb_dlist_entry((head)->next, typeof(*pos), member); \ + &pos->member != (head); \ + pos = usb_dlist_entry(pos->member.next, typeof(*pos), member)) + +/** + * usb_usb_dlist_for_each_entry_reverse - iterate over list of given type + * @pos: the type * to use as a loop cursor. + * @head: the head for your list. + * @member: the name of the list_struct within the struct. + */ +#define usb_dlist_for_each_entry_reverse(pos, head, member) \ + for (pos = usb_dlist_entry((head)->prev, typeof(*pos), member); \ + &pos->member != (head); \ + pos = usb_dlist_entry(pos->member.prev, typeof(*pos), member)) + +/** + * usb_usb_dlist_for_each_entry_safe - iterate over list of given type safe against removal of list entry + * @pos: the type * to use as a loop cursor. + * @n: another type * to use as temporary storage + * @head: the head for your list. + * @member: the name of the list_struct within the struct. + */ +#define usb_dlist_for_each_entry_safe(pos, n, head, member) \ + for (pos = usb_dlist_entry((head)->next, typeof(*pos), member), \ + n = usb_dlist_entry(pos->member.next, typeof(*pos), member); \ + &pos->member != (head); \ + pos = n, n = usb_dlist_entry(n->member.next, typeof(*n), member)) + +/** + * usb_usb_dlist_for_each_entry_safe - iterate over list of given type safe against removal of list entry + * @pos: the type * to use as a loop cursor. + * @n: another type * to use as temporary storage + * @head: the head for your list. + * @member: the name of the list_struct within the struct. + */ +#define usb_dlist_for_each_entry_safe_reverse(pos, n, head, member) \ + for (pos = usb_dlist_entry((head)->prev, typeof(*pos), field), \ + n = usb_dlist_entry(pos->member.prev, typeof(*pos), member); \ + &pos->member != (head); \ + pos = n, n = usb_dlist_entry(pos->member.prev, typeof(*pos), member)) + +#ifdef __cplusplus +} +#endif + +#endif /* USB_LIST_H */ diff --git a/kernel/cherryusb/common/usb_log.h b/kernel/cherryusb/common/usb_log.h new file mode 100644 index 0000000..ca03af5 --- /dev/null +++ b/kernel/cherryusb/common/usb_log.h @@ -0,0 +1,131 @@ +/* + * Copyright (c) 2022, sakumisu + * + * SPDX-License-Identifier: Apache-2.0 + */ +#ifndef USB_LOG_H +#define USB_LOG_H + +#include + +/* DEBUG level */ +#define USB_DBG_ERROR 0 +#define USB_DBG_WARNING 1 +#define USB_DBG_INFO 2 +#define USB_DBG_LOG 3 + +#ifndef USB_DBG_TAG +#define USB_DBG_TAG "USB" +#endif +/* + * The color for terminal (foreground) + * BLACK 30 + * RED 31 + * GREEN 32 + * YELLOW 33 + * BLUE 34 + * PURPLE 35 + * CYAN 36 + * WHITE 37 + */ + +#ifdef CONFIG_USB_PRINTF_COLOR_ENABLE +#define _USB_DBG_COLOR(n) CONFIG_USB_PRINTF("\033[" #n "m") +#define _USB_DBG_LOG_HDR(lvl_name, color_n) \ + CONFIG_USB_PRINTF("\033[" #color_n "m[" lvl_name "/" USB_DBG_TAG "] ") +#define _USB_DBG_LOG_X_END \ + CONFIG_USB_PRINTF("\033[0m") +#else +#define _USB_DBG_COLOR(n) +#define _USB_DBG_LOG_HDR(lvl_name, color_n) \ + CONFIG_USB_PRINTF("[" lvl_name "/" USB_DBG_TAG "] ") +#define _USB_DBG_LOG_X_END +#endif + +#define usb_dbg_log_line(lvl, color_n, fmt, ...) \ + do { \ + _USB_DBG_LOG_HDR(lvl, color_n); \ + CONFIG_USB_PRINTF(fmt, ##__VA_ARGS__); \ + _USB_DBG_LOG_X_END; \ + } while (0) + +#if (CONFIG_USB_DBG_LEVEL >= USB_DBG_LOG) +#define USB_LOG_DBG(fmt, ...) usb_dbg_log_line("D", 0, fmt, ##__VA_ARGS__) +#else +#define USB_LOG_DBG(...) {} +#endif + +#if (CONFIG_USB_DBG_LEVEL >= USB_DBG_INFO) +#define USB_LOG_INFO(fmt, ...) usb_dbg_log_line("I", 32, fmt, ##__VA_ARGS__) +#else +#define USB_LOG_INFO(...) {} +#endif + +#if (CONFIG_USB_DBG_LEVEL >= USB_DBG_WARNING) +#define USB_LOG_WRN(fmt, ...) usb_dbg_log_line("W", 33, fmt, ##__VA_ARGS__) +#else +#define USB_LOG_WRN(...) {} +#endif + +#if (CONFIG_USB_DBG_LEVEL >= USB_DBG_ERROR) +#define USB_LOG_ERR(fmt, ...) usb_dbg_log_line("E", 31, fmt, ##__VA_ARGS__) +#else +#define USB_LOG_ERR(...) {} +#endif + +#define USB_LOG_RAW(...) CONFIG_USB_PRINTF(__VA_ARGS__) + +#ifndef CONFIG_USB_ASSERT_DISABLE +#define USB_ASSERT(f) \ + do { \ + if (!(f)) { \ + USB_LOG_ERR("ASSERT FAIL [%s] @ %s:%d\r\n", #f, __FILE__, __LINE__); \ + while (1) { \ + } \ + } \ + } while (false) + +#define USB_ASSERT_MSG(f, fmt, ...) \ + do { \ + if (!(f)) { \ + USB_LOG_ERR("ASSERT FAIL [%s] @ %s:%d\r\n", #f, __FILE__, __LINE__); \ + USB_LOG_ERR(fmt "\r\n", ##__VA_ARGS__); \ + while (1) { \ + } \ + } \ + } while (false) +#else +#define USB_ASSERT(f) {} +#define USB_ASSERT_MSG(f, fmt, ...) {} +#endif + +#define ___is_print(ch) ((unsigned int)((ch) - ' ') < 127u - ' ') +static inline void usb_hexdump(const void *ptr, uint32_t buflen) +{ + unsigned char *buf = (unsigned char *)ptr; + unsigned int i, j; + + (void)buf; + + for (i = 0; i < buflen; i += 16) { + CONFIG_USB_PRINTF("%08x:", i); + + for (j = 0; j < 16; j++) + if (i + j < buflen) { + if ((j % 8) == 0) { + CONFIG_USB_PRINTF(" "); + } + + CONFIG_USB_PRINTF("%02X ", buf[i + j]); + } else + CONFIG_USB_PRINTF(" "); + CONFIG_USB_PRINTF(" "); + + for (j = 0; j < 16; j++) + if (i + j < buflen) + CONFIG_USB_PRINTF("%c", ___is_print(buf[i + j]) ? buf[i + j] : '.'); + CONFIG_USB_PRINTF("\n"); + } +} + +#endif /* USB_LOG_H */ diff --git a/kernel/cherryusb/common/usb_memcpy.h b/kernel/cherryusb/common/usb_memcpy.h new file mode 100644 index 0000000..ed028e6 --- /dev/null +++ b/kernel/cherryusb/common/usb_memcpy.h @@ -0,0 +1,96 @@ +/* + * Copyright (c) 2024, sakumisu + * + * SPDX-License-Identifier: Apache-2.0 + */ +#ifndef USB_MEMCPY_H +#define USB_MEMCPY_H + +#include +#include + +#define ALIGN_UP_DWORD(x) ((uint32_t)(uintptr_t)(x) & (sizeof(uint32_t) - 1)) + +static inline void dword2array(char *addr, uint32_t w) +{ + addr[0] = w; + addr[1] = w >> 8; + addr[2] = w >> 16; + addr[3] = w >> 24; +} + +static inline void *usb_memcpy(void *s1, const void *s2, size_t n) +{ + char *b1 = (char *)s1; + const char *b2 = (const char *)s2; + uint32_t *w1; + const uint32_t *w2; + + if (ALIGN_UP_DWORD(b1) == ALIGN_UP_DWORD(b2)) { + while (ALIGN_UP_DWORD(b1) != 0 && n > 0) { + *b1++ = *b2++; + --n; + } + + w1 = (uint32_t *)b1; + w2 = (const uint32_t *)b2; + + while (n >= 4 * sizeof(uint32_t)) { + *w1++ = *w2++; + *w1++ = *w2++; + *w1++ = *w2++; + *w1++ = *w2++; + n -= 4 * sizeof(uint32_t); + } + + while (n >= sizeof(uint32_t)) { + *w1++ = *w2++; + n -= sizeof(uint32_t); + } + + b1 = (char *)w1; + b2 = (const char *)w2; + + while (n--) { + *b1++ = *b2++; + } + } else { + while (n > 0 && ALIGN_UP_DWORD(b2) != 0) { + *b1++ = *b2++; + --n; + } + + w2 = (const uint32_t *)b2; + + while (n >= 4 * sizeof(uint32_t)) { + dword2array(b1, *w2++); + b1 += sizeof(uint32_t); + dword2array(b1, *w2++); + b1 += sizeof(uint32_t); + dword2array(b1, *w2++); + b1 += sizeof(uint32_t); + dword2array(b1, *w2++); + b1 += sizeof(uint32_t); + n -= 4 * sizeof(uint32_t); + } + + while (n >= sizeof(uint32_t)) { + dword2array(b1, *w2++); + b1 += sizeof(uint32_t); + n -= sizeof(uint32_t); + } + + b2 = (const char *)w2; + + while (n--) { + *b1++ = *b2++; + } + } + return s1; +} + +#ifndef CONFIG_USB_MEMCPY_DISABLE +#define memcpy usb_memcpy +#endif + +#endif diff --git a/kernel/cherryusb/common/usb_mempool.h b/kernel/cherryusb/common/usb_mempool.h new file mode 100644 index 0000000..d14d69d --- /dev/null +++ b/kernel/cherryusb/common/usb_mempool.h @@ -0,0 +1,148 @@ +/* + * Copyright (c) 2022, sakumisu + * + * SPDX-License-Identifier: Apache-2.0 + */ +#ifndef USB_MEMPOOL_H +#define USB_MEMPOOL_H + +#include "usb_osal.h" +#include "usb_ringbuffer.h" + +#ifndef CONFIG_USB_MEMPOOL_MAX_BLOCK_COUNT +#define CONFIG_USB_MEMPOOL_MAX_BLOCK_COUNT 16 +#endif + +struct usb_mempool { + usb_ringbuffer_t in; + usb_ringbuffer_t out; + usb_osal_sem_t out_sem; + + void *block; + uint32_t block_size; + uint32_t block_count; + uint8_t in_buf[sizeof(uintptr_t) * CONFIG_USB_MEMPOOL_MAX_BLOCK_COUNT]; + uint8_t out_buf[sizeof(uintptr_t) * CONFIG_USB_MEMPOOL_MAX_BLOCK_COUNT]; +}; + +#define usb_mempool_osal_sem_create(max_count) usb_osal_sem_create_counting(max_count) +#define usb_mempool_osal_sem_delete(sem) usb_osal_sem_delete(sem) +#define usb_mempool_osal_sem_take(sem, timeout) usb_osal_sem_take(sem, timeout) +#define usb_mempool_osal_sem_give(sem) usb_osal_sem_give(sem) + +#ifdef __cplusplus +extern "C" { +#endif + +static inline int usb_mempool_create(struct usb_mempool *pool, void *block, uint32_t block_size, uint32_t block_count) +{ + uintptr_t *item; + uint32_t addr; + + if (block_count > CONFIG_USB_MEMPOOL_MAX_BLOCK_COUNT) { + return -1; + } + + if (block_size % 4) { + return -1; + } + + if (usb_ringbuffer_init(&pool->in, pool->in_buf, sizeof(uintptr_t) * block_count) == -1) { + return -1; + } + + if (usb_ringbuffer_init(&pool->out, pool->out_buf, sizeof(uintptr_t) * block_count) == -1) { + return -1; + } + + pool->out_sem = usb_mempool_osal_sem_create(block_count); + if (pool->out_sem == NULL) { + return -1; + } + + pool->block = block; + pool->block_size = block_size; + pool->block_count = block_count; + + for (uint32_t i = 0; i < pool->block_count; i++) { + item = (uintptr_t *)((uint8_t *)pool->block + i * pool->block_size); + addr = (uintptr_t)item; + usb_ringbuffer_write(&pool->in, &addr, sizeof(uintptr_t)); + } + + return 0; +} + +static inline void usb_mempool_delete(struct usb_mempool *pool) +{ + usb_ringbuffer_reset(&pool->in); + usb_ringbuffer_reset(&pool->out); + usb_mempool_osal_sem_delete(pool->out_sem); +} + +static inline uintptr_t *usb_mempool_alloc(struct usb_mempool *pool) +{ + uintptr_t *addr; + uint32_t len; + + len = usb_ringbuffer_read(&pool->in, (uintptr_t *)&addr, sizeof(uintptr_t)); + if (len == 0) { + return NULL; + } else { + return addr; + } +} + +static inline int usb_mempool_free(struct usb_mempool *pool, uintptr_t *item) +{ + uintptr_t addr; + + addr = (uintptr_t)item; + return usb_ringbuffer_write(&pool->in, &addr, sizeof(uintptr_t)); +} + +static inline int usb_mempool_send(struct usb_mempool *pool, uintptr_t *item) +{ + uintptr_t addr; + + addr = (uintptr_t)item; + usb_ringbuffer_write(&pool->out, &addr, sizeof(uintptr_t)); + return usb_mempool_osal_sem_give(pool->out_sem); +} + +static inline int usb_mempool_recv(struct usb_mempool *pool, uintptr_t **item, uint32_t timeout) +{ + uint32_t len; + int ret; + + ret = usb_mempool_osal_sem_take(pool->out_sem, timeout); + if (ret < 0) { + return -1; + } + + len = usb_ringbuffer_read(&pool->out, (uintptr_t *)item, sizeof(uintptr_t)); + if (len == 0) { + return -1; + } else { + return 0; + } +} + +static inline void usb_mempool_reset(struct usb_mempool *pool) +{ + uintptr_t *item; + + usb_ringbuffer_reset(&pool->in); + usb_ringbuffer_reset(&pool->out); + + for (uint32_t i = 0; i < pool->block_count; i++) { + item = (uintptr_t *)((uint8_t *)pool->block + i * pool->block_size); + usb_mempool_free(pool, item); + } +} + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/kernel/cherryusb/common/usb_osal.h b/kernel/cherryusb/common/usb_osal.h new file mode 100644 index 0000000..70e2afe --- /dev/null +++ b/kernel/cherryusb/common/usb_osal.h @@ -0,0 +1,77 @@ +/* + * Copyright (c) 2022, sakumisu + * + * SPDX-License-Identifier: Apache-2.0 + */ +#ifndef USB_OSAL_H +#define USB_OSAL_H + +#include +#include +#include + +#ifdef __INCLUDE_NUTTX_CONFIG_H +#define CONFIG_USB_OSAL_THREAD_SET_ARGV int argc, char **argv +#define CONFIG_USB_OSAL_THREAD_GET_ARGV ((uintptr_t)strtoul(argv[1], NULL, 16)) +#elif defined(__ZEPHYR__) +#define CONFIG_USB_OSAL_THREAD_SET_ARGV void *p1, void *p2, void *p3 +#define CONFIG_USB_OSAL_THREAD_GET_ARGV ((uintptr_t)p1) +#else +#define CONFIG_USB_OSAL_THREAD_SET_ARGV void *argument +#define CONFIG_USB_OSAL_THREAD_GET_ARGV ((uintptr_t)argument) +#endif + +#define USB_OSAL_WAITING_FOREVER (0xFFFFFFFFU) + +typedef void *usb_osal_thread_t; +typedef void *usb_osal_sem_t; +typedef void *usb_osal_mutex_t; +typedef void *usb_osal_mq_t; +typedef void (*usb_thread_entry_t)(CONFIG_USB_OSAL_THREAD_SET_ARGV); +typedef void (*usb_timer_handler_t)(void *argument); +struct usb_osal_timer { + usb_timer_handler_t handler; + void *argument; + bool is_period; + uint32_t timeout_ms; + void *timer; +}; + +/* + * Task with smaller priority value indicates higher task priority +*/ +usb_osal_thread_t usb_osal_thread_create(const char *name, uint32_t stack_size, uint32_t prio, usb_thread_entry_t entry, void *args); +void usb_osal_thread_delete(usb_osal_thread_t thread); +void usb_osal_thread_schedule_other(void); + +usb_osal_sem_t usb_osal_sem_create(uint32_t initial_count); +usb_osal_sem_t usb_osal_sem_create_counting(uint32_t max_count); +void usb_osal_sem_delete(usb_osal_sem_t sem); +int usb_osal_sem_take(usb_osal_sem_t sem, uint32_t timeout); +int usb_osal_sem_give(usb_osal_sem_t sem); +void usb_osal_sem_reset(usb_osal_sem_t sem); + +usb_osal_mutex_t usb_osal_mutex_create(void); +void usb_osal_mutex_delete(usb_osal_mutex_t mutex); +int usb_osal_mutex_take(usb_osal_mutex_t mutex); +int usb_osal_mutex_give(usb_osal_mutex_t mutex); + +usb_osal_mq_t usb_osal_mq_create(uint32_t max_msgs); +void usb_osal_mq_delete(usb_osal_mq_t mq); +int usb_osal_mq_send(usb_osal_mq_t mq, uintptr_t addr); +int usb_osal_mq_recv(usb_osal_mq_t mq, uintptr_t *addr, uint32_t timeout); + +struct usb_osal_timer *usb_osal_timer_create(const char *name, uint32_t timeout_ms, usb_timer_handler_t handler, void *argument, bool is_period); +void usb_osal_timer_delete(struct usb_osal_timer *timer); +void usb_osal_timer_start(struct usb_osal_timer *timer); +void usb_osal_timer_stop(struct usb_osal_timer *timer); + +size_t usb_osal_enter_critical_section(void); +void usb_osal_leave_critical_section(size_t flag); + +void usb_osal_msleep(uint32_t delay); + +void *usb_osal_malloc(size_t size); +void usb_osal_free(void *ptr); + +#endif /* USB_OSAL_H */ diff --git a/kernel/cherryusb/common/usb_otg.h b/kernel/cherryusb/common/usb_otg.h new file mode 100644 index 0000000..032d2e9 --- /dev/null +++ b/kernel/cherryusb/common/usb_otg.h @@ -0,0 +1,39 @@ +/* + * Copyright (c) 2025, sakumisu + * + * SPDX-License-Identifier: Apache-2.0 + */ +#ifndef USB_OTG_H +#define USB_OTG_H + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#define USBOTG_MODE_HOST 0 +#define USBOTG_MODE_DEVICE 1 +#define USBOTG_MODE_OTG 2 + +/** + * @brief usb otg controller hardware or gpio id simulator init. + * + * @return On success will return 0, and others indicate fail. + */ +int usb_otg_init(uint8_t busid); +/** + * @brief usb otg controller hardware or gpio id simulator deinit. + * + * @return On success will return 0, and others indicate fail. + */ +int usb_otg_deinit(uint8_t busid); + +/* called by user */ +void USBOTG_IRQHandler(uint8_t busid); + +#ifdef __cplusplus +} +#endif + +#endif /* USB_OTG_H */ \ No newline at end of file diff --git a/kernel/cherryusb/common/usb_ringbuffer.h b/kernel/cherryusb/common/usb_ringbuffer.h new file mode 100644 index 0000000..3a0afe9 --- /dev/null +++ b/kernel/cherryusb/common/usb_ringbuffer.h @@ -0,0 +1,494 @@ +/* + * Copyright (c) 2022, Egahp + * + * SPDX-License-Identifier: Apache-2.0 + */ +#ifndef USB_RINGBUFFER_H +#define USB_RINGBUFFER_H + +#include +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +typedef struct { + uint32_t in; /*!< Define the write pointer. */ + uint32_t out; /*!< Define the read pointer. */ + uint32_t mask; /*!< Define the write and read pointer mask. */ + void *pool; /*!< Define the memory pointer. */ +} usb_ringbuffer_t; + +/***************************************************************************** +* @brief init ringbuffer +* +* @param[in] rb ringbuffer instance +* @param[in] pool memory pool address +* @param[in] size memory size in byte, +* must be power of 2 !!! +* +* @retval int 0:Success -1:Error +*****************************************************************************/ +static inline int usb_ringbuffer_init(usb_ringbuffer_t *rb, void *pool, uint32_t size) +{ + if (NULL == rb) { + return -1; + } + + if (NULL == pool) { + return -1; + } + + if ((size < 2) || (size & (size - 1))) { + return -1; + } + + rb->in = 0; + rb->out = 0; + rb->mask = size - 1; + rb->pool = pool; + + return 0; +} + +/***************************************************************************** +* @brief reset ringbuffer, clean all data, +* should be add lock in multithread +* +* @param[in] rb ringbuffer instance +* +*****************************************************************************/ +static inline void usb_ringbuffer_reset(usb_ringbuffer_t *rb) +{ + rb->in = 0; + rb->out = 0; +} + +/***************************************************************************** +* @brief reset ringbuffer, clean all data, +* should be add lock in multithread, +* in single read thread not need lock +* +* @param[in] rb ringbuffer instance +* +*****************************************************************************/ +static inline void usb_ringbuffer_reset_read(usb_ringbuffer_t *rb) +{ + rb->out = rb->in; +} + +/***************************************************************************** +* @brief get ringbuffer total size in byte +* +* @param[in] rb ringbuffer instance +* +* @retval uint32_t total size in byte +*****************************************************************************/ +static inline uint32_t usb_ringbuffer_get_size(usb_ringbuffer_t *rb) +{ + return rb->mask + 1; +} + +/***************************************************************************** +* @brief get ringbuffer used size in byte +* +* @param[in] rb ringbuffer instance +* +* @retval uint32_t used size in byte +*****************************************************************************/ +static inline uint32_t usb_ringbuffer_get_used(usb_ringbuffer_t *rb) +{ + return rb->in - rb->out; +} + +/***************************************************************************** +* @brief get ringbuffer free size in byte +* +* @param[in] rb ringbuffer instance +* +* @retval uint32_t free size in byte +*****************************************************************************/ +static inline uint32_t usb_ringbuffer_get_free(usb_ringbuffer_t *rb) +{ + return (rb->mask + 1) - (rb->in - rb->out); +} + +/***************************************************************************** +* @brief check if ringbuffer is full +* +* @param[in] rb ringbuffer instance +* +* @retval true full +* @retval false not full +*****************************************************************************/ +static inline bool usb_ringbuffer_check_full(usb_ringbuffer_t *rb) +{ + return usb_ringbuffer_get_used(rb) > rb->mask; +} + +/***************************************************************************** +* @brief check if ringbuffer is empty +* +* @param[in] rb ringbuffer instance +* +* @retval true empty +* @retval false not empty +*****************************************************************************/ +static inline bool usb_ringbuffer_check_empty(usb_ringbuffer_t *rb) +{ + return rb->in == rb->out; +} + +/***************************************************************************** +* @brief write one byte to ringbuffer, +* should be add lock in multithread, +* in single write thread not need lock +* +* @param[in] rb ringbuffer instance +* @param[in] byte data +* +* @retval true Success +* @retval false ringbuffer is full +*****************************************************************************/ +static inline bool usb_ringbuffer_write_byte(usb_ringbuffer_t *rb, uint8_t byte) +{ + if (usb_ringbuffer_check_full(rb)) { + return false; + } + + ((uint8_t *)(rb->pool))[rb->in & rb->mask] = byte; + rb->in++; + return true; +} + +/***************************************************************************** +* @brief overwrite one byte to ringbuffer, drop oldest data, +* should be add lock always +* +* @param[in] rb ringbuffer instance +* @param[in] byte data +* +* @retval true Success +* @retval false always return true +*****************************************************************************/ +static inline bool usb_ringbuffer_overwrite_byte(usb_ringbuffer_t *rb, uint8_t byte) +{ + if (usb_ringbuffer_check_full(rb)) { + rb->out++; + } + + ((uint8_t *)(rb->pool))[rb->in & rb->mask] = byte; + rb->in++; + return true; +} + +/***************************************************************************** +* @brief peek one byte from ringbuffer, +* should be add lock in multithread, +* in single read thread not need lock +* +* @param[in] rb ringbuffer instance +* @param[in] byte pointer to save data +* +* @retval true Success +* @retval false ringbuffer is empty +*****************************************************************************/ +static inline bool usb_ringbuffer_peek_byte(usb_ringbuffer_t *rb, uint8_t *byte) +{ + if (usb_ringbuffer_check_empty(rb)) { + return false; + } + + *byte = ((uint8_t *)(rb->pool))[rb->out & rb->mask]; + return true; +} + +/***************************************************************************** +* @brief read one byte from ringbuffer, +* should be add lock in multithread, +* in single read thread not need lock +* +* @param[in] rb ringbuffer instance +* @param[in] byte pointer to save data +* +* @retval true Success +* @retval false ringbuffer is empty +*****************************************************************************/ +static inline bool usb_ringbuffer_read_byte(usb_ringbuffer_t *rb, uint8_t *byte) +{ + bool ret; + ret = usb_ringbuffer_peek_byte(rb, byte); + rb->out += ret; + return ret; +} + +/***************************************************************************** +* @brief drop one byte from ringbuffer, +* should be add lock in multithread, +* in single read thread not need lock +* +* @param[in] rb ringbuffer instance +* +* @retval true Success +* @retval false ringbuffer is empty +*****************************************************************************/ +static inline bool usb_ringbuffer_drop_byte(usb_ringbuffer_t *rb) +{ + if (usb_ringbuffer_check_empty(rb)) { + return false; + } + + rb->out += 1; + return true; +} + +/***************************************************************************** +* @brief write data to ringbuffer, +* should be add lock in multithread, +* in single write thread not need lock +* +* @param[in] rb ringbuffer instance +* @param[in] data data pointer +* @param[in] size size in byte +* +* @retval uint32_t actual write size in byte +*****************************************************************************/ +static inline uint32_t usb_ringbuffer_write(usb_ringbuffer_t *rb, void *data, uint32_t size) +{ + uint32_t unused; + uint32_t offset; + uint32_t remain; + + unused = (rb->mask + 1) - (rb->in - rb->out); + + if (size > unused) { + size = unused; + } + + offset = rb->in & rb->mask; + + remain = rb->mask + 1 - offset; + remain = remain > size ? size : remain; + + memcpy(((uint8_t *)(rb->pool)) + offset, data, remain); + memcpy(rb->pool, (uint8_t *)data + remain, size - remain); + + rb->in += size; + + return size; +} + +/***************************************************************************** +* @brief write data to ringbuffer, +* should be add lock always +* +* @param[in] rb ringbuffer instance +* @param[in] data data pointer +* @param[in] size size in byte +* +* @retval uint32_t actual write size in byte +*****************************************************************************/ +static inline uint32_t usb_ringbuffer_overwrite(usb_ringbuffer_t *rb, void *data, uint32_t size) +{ + uint32_t unused; + uint32_t offset; + uint32_t remain; + + unused = (rb->mask + 1) - (rb->in - rb->out); + + if (size > unused) { + if (size > (rb->mask + 1)) { + size = rb->mask + 1; + } + + rb->out += size - unused; + } + + offset = rb->in & rb->mask; + + remain = rb->mask + 1 - offset; + remain = remain > size ? size : remain; + + memcpy(((uint8_t *)(rb->pool)) + offset, data, remain); + memcpy(rb->pool, (uint8_t *)data + remain, size - remain); + + rb->in += size; + + return size; +} + +/***************************************************************************** +* @brief peek data from ringbuffer +* should be add lock in multithread, +* in single read thread not need lock +* +* @param[in] rb ringbuffer instance +* @param[in] data data pointer +* @param[in] size size in byte +* +* @retval uint32_t actual peek size in byte +*****************************************************************************/ +static inline uint32_t usb_ringbuffer_peek(usb_ringbuffer_t *rb, void *data, uint32_t size) +{ + uint32_t used; + uint32_t offset; + uint32_t remain; + + used = rb->in - rb->out; + if (size > used) { + size = used; + } + + offset = rb->out & rb->mask; + + remain = rb->mask + 1 - offset; + remain = remain > size ? size : remain; + + memcpy(data, ((uint8_t *)(rb->pool)) + offset, remain); + memcpy((uint8_t *)data + remain, rb->pool, size - remain); + + return size; +} + +/***************************************************************************** +* @brief read data from ringbuffer +* should be add lock in multithread, +* in single read thread not need lock +* +* @param[in] rb ringbuffer instance +* @param[in] data data pointer +* @param[in] size size in byte +* +* @retval uint32_t actual read size in byte +*****************************************************************************/ +static inline uint32_t usb_ringbuffer_read(usb_ringbuffer_t *rb, void *data, uint32_t size) +{ + size = usb_ringbuffer_peek(rb, data, size); + rb->out += size; + return size; +} + +/***************************************************************************** +* @brief drop data from ringbuffer +* should be add lock in multithread, +* in single read thread not need lock +* +* @param[in] rb ringbuffer instance +* @param[in] size size in byte +* +* @retval uint32_t actual drop size in byte +*****************************************************************************/ +static inline uint32_t usb_ringbuffer_drop(usb_ringbuffer_t *rb, uint32_t size) +{ + uint32_t used; + + used = rb->in - rb->out; + if (size > used) { + size = used; + } + + rb->out += size; + return size; +} + +/***************************************************************************** +* @brief linear write setup, get write pointer and max linear size. +* +* @param[in] rb ringbuffer instance +* @param[in] size pointer to store max linear size in byte +* +* @retval void* write memory pointer +*****************************************************************************/ +static inline void *usb_ringbuffer_linear_write_setup(usb_ringbuffer_t *rb, uint32_t *size) +{ + uint32_t unused; + uint32_t offset; + uint32_t remain; + + unused = (rb->mask + 1) - (rb->in - rb->out); + + offset = rb->in & rb->mask; + + remain = rb->mask + 1 - offset; + remain = remain > unused ? unused : remain; + + if (remain) { + *size = remain; + return ((uint8_t *)(rb->pool)) + offset; + } else { + *size = unused - remain; + return rb->pool; + } +} + +/***************************************************************************** +* @brief linear read setup, get read pointer and max linear size. +* +* @param[in] rb ringbuffer instance +* @param[in] size pointer to store max linear size in byte +* +* @retval void* +*****************************************************************************/ +static inline void *usb_ringbuffer_linear_read_setup(usb_ringbuffer_t *rb, uint32_t *size) +{ + uint32_t used; + uint32_t offset; + uint32_t remain; + + used = rb->in - rb->out; + + offset = rb->out & rb->mask; + + remain = rb->mask + 1 - offset; + remain = remain > used ? used : remain; + + if (remain) { + *size = remain; + return ((uint8_t *)(rb->pool)) + offset; + } else { + *size = used - remain; + return rb->pool; + } +} + +/***************************************************************************** +* @brief linear write done, add write pointer only +* +* @param[in] rb ringbuffer instance +* @param[in] size write size in byte +* +* @retval uint32_t actual write size in byte +*****************************************************************************/ +static inline uint32_t usb_ringbuffer_linear_write_done(usb_ringbuffer_t *rb, uint32_t size) +{ + uint32_t unused; + + unused = (rb->mask + 1) - (rb->in - rb->out); + if (size > unused) { + size = unused; + } + rb->in += size; + + return size; +} + +/***************************************************************************** +* @brief linear read done, add read pointer only +* +* @param[in] rb ringbuffer instance +* @param[in] size read size in byte +* +* @retval uint32_t actual read size in byte +*****************************************************************************/ +static inline uint32_t usb_ringbuffer_linear_read_done(usb_ringbuffer_t *rb, uint32_t size) +{ + return usb_ringbuffer_drop(rb, size); +} + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/kernel/cherryusb/common/usb_util.h b/kernel/cherryusb/common/usb_util.h new file mode 100644 index 0000000..521bf27 --- /dev/null +++ b/kernel/cherryusb/common/usb_util.h @@ -0,0 +1,242 @@ +/* + * Copyright (c) 2022-2023, sakumisu + * + * SPDX-License-Identifier: Apache-2.0 + */ +#ifndef USB_UTIL_H +#define USB_UTIL_H + +#if defined(__CC_ARM) +#ifndef __USED +#define __USED __attribute__((used)) +#endif +#ifndef __WEAK +#define __WEAK __attribute__((weak)) +#endif +#ifndef __PACKED +#define __PACKED __attribute__((packed)) +#endif +#ifndef __PACKED_STRUCT +#define __PACKED_STRUCT __packed struct +#endif +#ifndef __PACKED_UNION +#define __PACKED_UNION __packed union +#endif +#ifndef __ALIGNED +#define __ALIGNED(x) __attribute__((aligned(x))) +#endif +#elif defined(__GNUC__) +#ifndef __USED +#define __USED __attribute__((used)) +#endif +#ifndef __WEAK +#define __WEAK __attribute__((weak)) +#endif +#ifndef __PACKED +#define __PACKED __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_STRUCT +#define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_UNION +#define __PACKED_UNION union __attribute__((packed, aligned(1))) +#endif +#ifndef __ALIGNED +#define __ALIGNED(x) __attribute__((aligned(x))) +#endif +#elif defined(__ICCARM__) || defined(__ICCRX__) || defined(__ICCRISCV__) +#if (__VER__ >= 8000000) + #define __ICCARM_V8 1 +#else + #define __ICCARM_V8 0 +#endif + +#ifndef __USED +#if defined(__ICCARM_V8) || defined(__ICCRISCV__) +#define __USED __attribute__((used)) +#else +#define __USED __root +#endif +#endif + +#ifndef __WEAK +#if defined(__ICCARM_V8) || defined(__ICCRISCV__) +#define __WEAK __attribute__((weak)) +#else +#define __WEAK _Pragma("__weak") +#endif +#endif + +#ifndef __PACKED +#if defined(__ICCARM_V8) || defined(__ICCRISCV__) +#define __PACKED __attribute__((packed, aligned(1))) +#else +/* Needs IAR language extensions */ +#define __PACKED __packed +#endif +#endif + +#ifndef __PACKED_STRUCT +#if defined(__ICCARM_V8) || defined(__ICCRISCV__) +#define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) +#else +/* Needs IAR language extensions */ +#define __PACKED_STRUCT __packed struct +#endif +#endif + +#ifndef __PACKED_UNION +#if defined(__ICCARM_V8) || defined(__ICCRISCV__) +#define __PACKED_UNION union __attribute__((packed, aligned(1))) +#else +/* Needs IAR language extensions */ +#define __PACKED_UNION __packed union +#endif +#endif + +#ifndef __ALIGNED +#if defined(__ICCARM_V8) || defined(__ICCRISCV__) +#define __ALIGNED(x) __attribute__((aligned(x))) +#elif (__VER__ >= 7080000) +/* Needs IAR language extensions */ +#define __ALIGNED(x) __attribute__((aligned(x))) +#else +#warning No compiler specific solution for __ALIGNED.__ALIGNED is ignored. +#define __ALIGNED(x) +#endif +#endif + +#endif + +#ifndef __ALIGN_BEGIN +#define __ALIGN_BEGIN +#endif +#ifndef __ALIGN_END +#define __ALIGN_END __attribute__((aligned(4))) +#endif + +#ifndef ARG_UNUSED +#define ARG_UNUSED(x) (void)(x) +#endif + +#ifndef LO_BYTE +#define LO_BYTE(x) ((uint8_t)(x & 0x00FF)) +#endif + +#ifndef HI_BYTE +#define HI_BYTE(x) ((uint8_t)((x & 0xFF00) >> 8)) +#endif + +#ifndef MAX +#define MAX(a, b) (((a) > (b)) ? (a) : (b)) +#endif + +#ifndef MIN +#define MIN(a, b) (((a) < (b)) ? (a) : (b)) +#endif + +#ifndef BCD +#define BCD(x) ((((x) / 10) << 4) | ((x) % 10)) +#endif + +#ifdef BIT +#undef BIT +#define BIT(n) (1UL << (n)) +#else +#define BIT(n) (1UL << (n)) +#endif + +#ifndef ARRAY_SIZE +#define ARRAY_SIZE(array) \ + ((int)((sizeof(array) / sizeof((array)[0])))) +#endif + +#ifndef BSWAP16 +#define BSWAP16(u16) (__builtin_bswap16(u16)) +#endif +#ifndef BSWAP32 +#define BSWAP32(u32) (__builtin_bswap32(u32)) +#endif + +#define GET_BE16(field) \ + (((uint16_t)(field)[0] << 8) | ((uint16_t)(field)[1])) + +#define GET_BE32(field) \ + (((uint32_t)(field)[0] << 24) | ((uint32_t)(field)[1] << 16) | ((uint32_t)(field)[2] << 8) | ((uint32_t)(field)[3] << 0)) + +#define SET_BE16(field, value) \ + do { \ + (field)[0] = (uint8_t)((value) >> 8); \ + (field)[1] = (uint8_t)((value) >> 0); \ + } while (0) + +#define SET_BE24(field, value) \ + do { \ + (field)[0] = (uint8_t)((value) >> 16); \ + (field)[1] = (uint8_t)((value) >> 8); \ + (field)[2] = (uint8_t)((value) >> 0); \ + } while (0) + +#define SET_BE32(field, value) \ + do { \ + (field)[0] = (uint8_t)((value) >> 24); \ + (field)[1] = (uint8_t)((value) >> 16); \ + (field)[2] = (uint8_t)((value) >> 8); \ + (field)[3] = (uint8_t)((value) >> 0); \ + } while (0) + +#define WBVAL(x) ((x) & 0xFF), (((x) >> 8) & 0xFF) +#define DBVAL(x) ((x) & 0xFF), (((x) >> 8) & 0xFF), (((x) >> 16) & 0xFF), (((x) >> 24) & 0xFF) + +#define PP_NARG(...) \ + PP_NARG_(__VA_ARGS__, PP_RSEQ_N()) +#define PP_NARG_(...) \ + PP_ARG_N(__VA_ARGS__) +#define PP_ARG_N( \ + _1, _2, _3, _4, _5, _6, _7, _8, _9, _10, \ + _11, _12, _13, _14, _15, _16, _17, _18, _19, _20, \ + _21, _22, _23, _24, _25, _26, _27, _28, _29, _30, \ + _31, _32, _33, _34, _35, _36, _37, _38, _39, _40, \ + _41, _42, _43, _44, _45, _46, _47, _48, _49, _50, \ + _51, _52, _53, _54, _55, _56, _57, _58, _59, _60, \ + _61, _62, _63, N, ...) N +#define PP_RSEQ_N() \ + 63, 62, 61, 60, \ + 59, 58, 57, 56, 55, 54, 53, 52, 51, 50, \ + 49, 48, 47, 46, 45, 44, 43, 42, 41, 40, \ + 39, 38, 37, 36, 35, 34, 33, 32, 31, 30, \ + 29, 28, 27, 26, 25, 24, 23, 22, 21, 20, \ + 19, 18, 17, 16, 15, 14, 13, 12, 11, 10, \ + 9, 8, 7, 6, 5, 4, 3, 2, 1, 0 + +/* + * Divide positive or negative dividend by positive or negative divisor + * and round to closest integer. Result is undefined for negative + * divisors if the dividend variable type is unsigned and for negative + * dividends if the divisor variable type is unsigned. + */ +#define DIV_ROUND_CLOSEST(x, divisor) ( \ + { \ + typeof(x) __x = x; \ + typeof(divisor) __d = divisor; \ + (((typeof(x))-1) > 0 || \ + ((typeof(divisor))-1) > 0 || \ + (((__x) > 0) == ((__d) > 0))) ? \ + (((__x) + ((__d) / 2)) / (__d)) : \ + (((__x) - ((__d) / 2)) / (__d)); \ + }) + +#define USB_MEM_ALIGNX __attribute__((aligned(CONFIG_USB_ALIGN_SIZE))) + +#define USB_ALIGN_UP(size, align) (((size) + (align)-1) & ~((align)-1)) +#define USB_ALIGN_DOWN(size, align) ((size) & ~((align)-1)) + +#ifndef usb_phyaddr2ramaddr +#define usb_phyaddr2ramaddr(addr) (addr) +#endif + +#ifndef usb_ramaddr2phyaddr +#define usb_ramaddr2phyaddr(addr) (addr) +#endif + +#endif /* USB_UTIL_H */ diff --git a/kernel/cherryusb/common/usb_version.h b/kernel/cherryusb/common/usb_version.h new file mode 100644 index 0000000..5c59978 --- /dev/null +++ b/kernel/cherryusb/common/usb_version.h @@ -0,0 +1,21 @@ +/* + * Copyright (c) 2024, sakumisu + * + * SPDX-License-Identifier: Apache-2.0 + */ +#ifndef USB_VERSION_H +#define USB_VERSION_H + +#ifdef CHERRYUSB_VERSION +#warning "Please do not define CHERRYUSB_VERSION in usb_config.h" +#undef CHERRYUSB_VERSION +#endif +#ifdef CHERRYUSB_VERSION_STR +#warning "Please do not define CHERRYUSB_VERSION_STR in usb_config.h" +#undef CHERRYUSB_VERSION_STR +#endif + +#define CHERRYUSB_VERSION 0x010601 +#define CHERRYUSB_VERSION_STR "v1.6.1" + +#endif \ No newline at end of file diff --git a/kernel/cherryusb/core/usbd_core.c b/kernel/cherryusb/core/usbd_core.c new file mode 100644 index 0000000..a9ad67c --- /dev/null +++ b/kernel/cherryusb/core/usbd_core.c @@ -0,0 +1,1389 @@ +/* + * Copyright (c) 2022, sakumisu + * + * SPDX-License-Identifier: Apache-2.0 + */ +#include "usbd_core.h" +#ifdef CONFIG_USBDEV_EP0_THREAD +#include "usb_osal.h" + +#define USB_EP0_STATE_SETUP 0 +#define USB_EP0_STATE_IN 1 +#define USB_EP0_STATE_OUT 2 +#endif + +#undef USB_DBG_TAG +#define USB_DBG_TAG "usbd_core" +#include "usb_log.h" + +/* general descriptor field offsets */ +#define DESC_bLength 0 /** Length offset */ +#define DESC_bDescriptorType 1 /** Descriptor type offset */ + +/* config descriptor field offsets */ +#define CONF_DESC_wTotalLength 2 /** Total length offset */ +#define CONF_DESC_bConfigurationValue 5 /** Configuration value offset */ +#define CONF_DESC_bmAttributes 7 /** configuration characteristics */ + +/* interface descriptor field offsets */ +#define INTF_DESC_bInterfaceNumber 2 /** Interface number offset */ +#define INTF_DESC_bAlternateSetting 3 /** Alternate setting offset */ + +struct usbd_tx_rx_msg { + uint8_t ep; + uint8_t ep_mult; + uint16_t ep_mps; + uint32_t nbytes; + usbd_endpoint_callback cb; +}; + +USB_NOCACHE_RAM_SECTION struct usbd_core_priv { + /** Setup packet */ + USB_MEM_ALIGNX struct usb_setup_packet setup; + /** Pointer to data buffer */ + USB_MEM_ALIGNX uint8_t *ep0_data_buf; + /** Remaining bytes in buffer */ + uint32_t ep0_data_buf_residue; + /** Total length of control transfer */ + uint32_t ep0_data_buf_len; + /** Zero length packet flag of control transfer */ + bool zlp_flag; + + /** Pointer to registered descriptors */ + const struct usb_descriptor *descriptors; + + /* Buffer used for storing standard, class and vendor request data */ + USB_MEM_ALIGNX uint8_t req_data[USB_ALIGN_UP(CONFIG_USBDEV_REQUEST_BUFFER_LEN, CONFIG_USB_ALIGN_SIZE)]; + + /** Currently selected configuration */ + uint8_t configuration; + uint8_t device_address; + uint8_t ep0_next_state; + bool self_powered; + bool remote_wakeup_support; + bool remote_wakeup_enabled; + bool is_suspend; + uint8_t speed; +#ifdef CONFIG_USBDEV_TEST_MODE + bool test_req; +#endif +#ifdef CONFIG_USBDEV_EP0_THREAD + usb_osal_mq_t usbd_ep0_mq; + usb_osal_thread_t usbd_ep0_thread; +#endif + struct usbd_interface *intf[16]; + uint8_t intf_altsetting[16]; + uint8_t intf_offset; + + struct usbd_tx_rx_msg tx_msg[16]; + struct usbd_tx_rx_msg rx_msg[16]; + + void (*event_handler)(uint8_t busid, uint8_t event); +} g_usbd_core[CONFIG_USBDEV_MAX_BUS]; + +struct usbd_bus g_usbdev_bus[CONFIG_USBDEV_MAX_BUS]; + +static void usbd_class_event_notify_handler(uint8_t busid, uint8_t event, void *arg); + +static void usbd_print_setup(struct usb_setup_packet *setup) +{ + USB_LOG_ERR("Setup: " + "bmRequestType 0x%02x, bRequest 0x%02x, wValue 0x%04x, wIndex 0x%04x, wLength 0x%04x\r\n", + setup->bmRequestType, + setup->bRequest, + setup->wValue, + setup->wIndex, + setup->wLength); +} + +#if (CONFIG_USB_DBG_LEVEL >= USB_DBG_LOG) +static const char *usb_ep0_state_string[] = { + "setup", + "indata", + "outdata", + "instatus", + "outstatus" +}; +#endif + +static bool is_device_configured(uint8_t busid) +{ + return (g_usbd_core[busid].configuration != 0); +} + +/** + * @brief configure and enable endpoint + * + * This function sets endpoint configuration according to one specified in USB + * endpoint descriptor and then enables it for data transfers. + * + * @param [in] busid busid + * @param [in] ep Endpoint descriptor byte array + * + * @return true if successfully configured and enabled + */ +static bool usbd_set_endpoint(uint8_t busid, const struct usb_endpoint_descriptor *ep) +{ + USB_LOG_DBG("Open ep:0x%02x type:%u mps:%u\r\n", + ep->bEndpointAddress, + USB_GET_ENDPOINT_TYPE(ep->bmAttributes), + USB_GET_MAXPACKETSIZE(ep->wMaxPacketSize)); + + if (ep->bEndpointAddress & 0x80) { + g_usbd_core[busid].tx_msg[ep->bEndpointAddress & 0x7f].ep_mps = USB_GET_MAXPACKETSIZE(ep->wMaxPacketSize); + g_usbd_core[busid].tx_msg[ep->bEndpointAddress & 0x7f].ep_mult = USB_GET_MULT(ep->wMaxPacketSize); + } else { + g_usbd_core[busid].rx_msg[ep->bEndpointAddress & 0x7f].ep_mps = USB_GET_MAXPACKETSIZE(ep->wMaxPacketSize); + g_usbd_core[busid].rx_msg[ep->bEndpointAddress & 0x7f].ep_mult = USB_GET_MULT(ep->wMaxPacketSize); + } + + return usbd_ep_open(busid, ep) == 0 ? true : false; +} +/** + * @brief Disable endpoint for transferring data + * + * This function cancels transfers that are associated with endpoint and + * disabled endpoint itself. + * + * @param [in] busid busid + * @param [in] ep Endpoint descriptor byte array + * + * @return true if successfully deconfigured and disabled + */ +static bool usbd_reset_endpoint(uint8_t busid, const struct usb_endpoint_descriptor *ep) +{ + USB_LOG_DBG("Close ep:0x%02x type:%u\r\n", + ep->bEndpointAddress, + USB_GET_ENDPOINT_TYPE(ep->bmAttributes)); + + return usbd_ep_close(busid, ep->bEndpointAddress) == 0 ? true : false; +} + +/** + * @brief get specified USB descriptor + * + * This function parses the list of installed USB descriptors and attempts + * to find the specified USB descriptor. + * + * @param [in] busid busid + * @param [in] type_index Type and index of the descriptor + * @param [out] data Descriptor data + * @param [out] len Descriptor length + * + * @return true if the descriptor was found, false otherwise + */ +static bool usbd_get_descriptor(uint8_t busid, uint16_t type_index, uint8_t **data, uint32_t *len) +{ + uint8_t type = 0U; + uint8_t index = 0U; + bool found = true; + uint32_t desc_len = 0; + const char *string = NULL; + const uint8_t *desc = NULL; + + type = HI_BYTE(type_index); + index = LO_BYTE(type_index); + + switch (type) { + case USB_DESCRIPTOR_TYPE_DEVICE: + g_usbd_core[busid].speed = usbd_get_port_speed(busid); /* before we get device descriptor, we have known steady port speed */ + + if (g_usbd_core[busid].descriptors->device_descriptor_callback == NULL) { + found = false; + break; + } + desc = g_usbd_core[busid].descriptors->device_descriptor_callback(g_usbd_core[busid].speed); + if (desc == NULL) { + found = false; + break; + } + desc_len = desc[0]; + break; + case USB_DESCRIPTOR_TYPE_CONFIGURATION: + if (g_usbd_core[busid].descriptors->config_descriptor_callback == NULL) { + found = false; + break; + } + desc = g_usbd_core[busid].descriptors->config_descriptor_callback(g_usbd_core[busid].speed); + if (desc == NULL) { + found = false; + break; + } + desc_len = ((desc[CONF_DESC_wTotalLength]) | (desc[CONF_DESC_wTotalLength + 1] << 8)); + + g_usbd_core[busid].self_powered = (desc[7] & USB_CONFIG_POWERED_MASK) ? true : false; + g_usbd_core[busid].remote_wakeup_support = (desc[7] & USB_CONFIG_REMOTE_WAKEUP) ? true : false; + break; + case USB_DESCRIPTOR_TYPE_STRING: + if (index == USB_OSDESC_STRING_DESC_INDEX) { + if (!g_usbd_core[busid].descriptors->msosv1_descriptor) { + found = false; + break; + } + + desc = (uint8_t *)g_usbd_core[busid].descriptors->msosv1_descriptor->string; + desc_len = g_usbd_core[busid].descriptors->msosv1_descriptor->string[0]; + } else { + if (g_usbd_core[busid].descriptors->string_descriptor_callback == NULL) { + found = false; + break; + } + string = g_usbd_core[busid].descriptors->string_descriptor_callback(g_usbd_core[busid].speed, index); + if (string == NULL) { + found = false; + break; + } + + if (index == USB_STRING_LANGID_INDEX) { + (*data)[0] = 4; + (*data)[1] = USB_DESCRIPTOR_TYPE_STRING; + (*data)[2] = string[0]; + (*data)[3] = string[1]; + + *len = 4; + return true; + } + + uint16_t str_size = strlen(string); + uint16_t total_size = 2 * str_size + 2; + if (total_size > CONFIG_USBDEV_REQUEST_BUFFER_LEN) { + USB_LOG_ERR("string size overflow\r\n"); + return false; + } + + (*data)[0] = total_size; + (*data)[1] = USB_DESCRIPTOR_TYPE_STRING; + + for (uint16_t i = 0; i < str_size; i++) { + (*data)[2 * i + 2] = string[i]; + (*data)[2 * i + 3] = 0x00; + } + + *len = total_size; + return true; + } + break; + case USB_DESCRIPTOR_TYPE_DEVICE_QUALIFIER: +#ifndef CONFIG_USB_HS + return false; +#else + if (g_usbd_core[busid].descriptors->device_quality_descriptor_callback == NULL) { + found = false; + break; + } + desc = g_usbd_core[busid].descriptors->device_quality_descriptor_callback(g_usbd_core[busid].speed); + if (desc == NULL) { + found = false; + break; + } + desc_len = desc[0]; + break; +#endif + case USB_DESCRIPTOR_TYPE_OTHER_SPEED: + if (g_usbd_core[busid].descriptors->other_speed_descriptor_callback == NULL) { + found = false; + break; + } + desc = g_usbd_core[busid].descriptors->other_speed_descriptor_callback(g_usbd_core[busid].speed); + if (desc == NULL) { + found = false; + break; + } + desc_len = ((desc[CONF_DESC_wTotalLength]) | (desc[CONF_DESC_wTotalLength + 1] << 8)); + break; + + case USB_DESCRIPTOR_TYPE_BINARY_OBJECT_STORE: + if (!g_usbd_core[busid].descriptors->bos_descriptor) { + found = false; + break; + } + + desc = (uint8_t *)g_usbd_core[busid].descriptors->bos_descriptor->string; + desc_len = g_usbd_core[busid].descriptors->bos_descriptor->string_len; + break; + + default: + found = false; + break; + } + + if (found == false) { + /* nothing found */ + USB_LOG_ERR("descriptor not found!\r\n", type, index); + } else { + *data = (uint8_t *)desc; + //memcpy(*data, desc, desc_len); + *len = desc_len; + } + return found; +} + +/** + * @brief set USB configuration + * + * This function configures the device according to the specified configuration + * index and alternate setting by parsing the installed USB descriptor list. + * A configuration index of 0 unconfigures the device. + * + * @param [in] busid busid + * @param [in] config_index Configuration index + * @param [in] alt_setting Alternate setting number + * + * @return true if successfully configured false if error or unconfigured + */ +static bool usbd_set_configuration(uint8_t busid, uint8_t config_index, uint8_t alt_setting) +{ + uint8_t cur_alt_setting = 0xFF; + uint8_t cur_config = 0xFF; + bool found = false; + const uint8_t *p; + uint32_t desc_len = 0; + uint32_t current_desc_len = 0; + + p = g_usbd_core[busid].descriptors->config_descriptor_callback(g_usbd_core[busid].speed); + + /* configure endpoints for this configuration/altsetting */ + while (p[DESC_bLength] != 0U) { + switch (p[DESC_bDescriptorType]) { + case USB_DESCRIPTOR_TYPE_CONFIGURATION: + /* remember current configuration index */ + cur_config = p[CONF_DESC_bConfigurationValue]; + + if (cur_config == config_index) { + found = true; + + current_desc_len = 0; + desc_len = (p[CONF_DESC_wTotalLength]) | + (p[CONF_DESC_wTotalLength + 1] << 8); + } + + break; + + case USB_DESCRIPTOR_TYPE_INTERFACE: + /* remember current alternate setting */ + cur_alt_setting = + p[INTF_DESC_bAlternateSetting]; + break; + + case USB_DESCRIPTOR_TYPE_ENDPOINT: + if ((cur_config != config_index) || + (cur_alt_setting != alt_setting)) { + break; + } + + found = usbd_set_endpoint(busid, (struct usb_endpoint_descriptor *)p); + break; + + default: + break; + } + + /* skip to next descriptor */ + current_desc_len += p[DESC_bLength]; + p += p[DESC_bLength]; + if (current_desc_len >= desc_len && desc_len) { + break; + } + } + + return found; +} + +/** + * @brief set USB interface + * + * @param [in] busid busid + * @param [in] iface Interface index + * @param [in] alt_setting Alternate setting number + * + * @return true if successfully configured false if error or unconfigured + */ +static bool usbd_set_interface(uint8_t busid, uint8_t iface, uint8_t alt_setting) +{ + const uint8_t *if_desc = NULL; + struct usb_endpoint_descriptor *ep_desc; + uint8_t cur_alt_setting = 0xFF; + uint8_t cur_iface = 0xFF; + bool ret = false; + const uint8_t *p; + uint32_t desc_len = 0; + uint32_t current_desc_len = 0; + + p = g_usbd_core[busid].descriptors->config_descriptor_callback(g_usbd_core[busid].speed); + + USB_LOG_DBG("iface %u alt_setting %u\r\n", iface, alt_setting); + + while (p[DESC_bLength] != 0U) { + switch (p[DESC_bDescriptorType]) { + case USB_DESCRIPTOR_TYPE_CONFIGURATION: + current_desc_len = 0; + desc_len = (p[CONF_DESC_wTotalLength]) | + (p[CONF_DESC_wTotalLength + 1] << 8); + + break; + + case USB_DESCRIPTOR_TYPE_INTERFACE: + /* remember current alternate setting */ + cur_alt_setting = p[INTF_DESC_bAlternateSetting]; + cur_iface = p[INTF_DESC_bInterfaceNumber]; + + if (cur_iface == iface && + cur_alt_setting == alt_setting) { + if_desc = (void *)p; + } + + break; + + case USB_DESCRIPTOR_TYPE_ENDPOINT: + if (cur_iface == iface) { + ep_desc = (struct usb_endpoint_descriptor *)p; + + if (alt_setting == 0) { + ret = usbd_reset_endpoint(busid, ep_desc); + } else if (cur_alt_setting == alt_setting) { + ret = usbd_set_endpoint(busid, ep_desc); + } else { + } + } + + break; + + default: + break; + } + + /* skip to next descriptor */ + current_desc_len += p[DESC_bLength]; + p += p[DESC_bLength]; + if (current_desc_len >= desc_len && desc_len) { + break; + } + } + + usbd_class_event_notify_handler(busid, USBD_EVENT_SET_INTERFACE, (void *)if_desc); + + return ret; +} + +/** + * @brief handle a standard device request + * + * @param [in] busid busid + * @param [in] setup The setup packet + * @param [in,out] data Data buffer + * @param [in,out] len Pointer to data length + * + * @return true if the request was handled successfully + */ +static bool usbd_std_device_req_handler(uint8_t busid, struct usb_setup_packet *setup, uint8_t **data, uint32_t *len) +{ + uint16_t value = setup->wValue; + bool ret = true; + + switch (setup->bRequest) { + case USB_REQUEST_GET_STATUS: + /* bit 0: self-powered */ + /* bit 1: remote wakeup */ + (*data)[0] = 0x00; + if (g_usbd_core[busid].self_powered) { + (*data)[0] |= USB_GETSTATUS_SELF_POWERED; + } + if (g_usbd_core[busid].remote_wakeup_enabled) { + (*data)[0] |= USB_GETSTATUS_REMOTE_WAKEUP; + } + (*data)[1] = 0x00; + *len = 2; + break; + + case USB_REQUEST_CLEAR_FEATURE: + case USB_REQUEST_SET_FEATURE: + if (value == USB_FEATURE_REMOTE_WAKEUP) { + if (setup->bRequest == USB_REQUEST_SET_FEATURE) { + g_usbd_core[busid].remote_wakeup_enabled = true; + g_usbd_core[busid].event_handler(busid, USBD_EVENT_SET_REMOTE_WAKEUP); + } else { + g_usbd_core[busid].remote_wakeup_enabled = false; + g_usbd_core[busid].event_handler(busid, USBD_EVENT_CLR_REMOTE_WAKEUP); + } + } else if (value == USB_FEATURE_TEST_MODE) { +#ifdef CONFIG_USBDEV_TEST_MODE + g_usbd_core[busid].test_req = true; +#endif + } + *len = 0; + break; + + case USB_REQUEST_SET_ADDRESS: + g_usbd_core[busid].device_address = value; + usbd_set_address(busid, value); + *len = 0; + break; + + case USB_REQUEST_GET_DESCRIPTOR: + ret = usbd_get_descriptor(busid, value, data, len); + break; + + case USB_REQUEST_SET_DESCRIPTOR: + ret = false; + break; + + case USB_REQUEST_GET_CONFIGURATION: + (*data)[0] = g_usbd_core[busid].configuration; + *len = 1; + break; + + case USB_REQUEST_SET_CONFIGURATION: + value &= 0xFF; + + if (value == 0) { + g_usbd_core[busid].configuration = 0; + } else if (!usbd_set_configuration(busid, value, 0)) { + ret = false; + } else { + g_usbd_core[busid].configuration = value; + g_usbd_core[busid].is_suspend = false; + usbd_class_event_notify_handler(busid, USBD_EVENT_CONFIGURED, NULL); + g_usbd_core[busid].event_handler(busid, USBD_EVENT_CONFIGURED); + } + *len = 0; + break; + + case USB_REQUEST_GET_INTERFACE: + case USB_REQUEST_SET_INTERFACE: + ret = false; + break; + + default: + ret = false; + break; + } + + return ret; +} + +/** + * @brief handle a standard interface request + * + * @param [in] busid busid + * @param [in] setup The setup packet + * @param [in,out] data Data buffer + * @param [in,out] len Pointer to data length + * + * @return true if the request was handled successfully + */ +static bool usbd_std_interface_req_handler(uint8_t busid, struct usb_setup_packet *setup, uint8_t **data, uint32_t *len) +{ + uint8_t type = HI_BYTE(setup->wValue); + uint8_t intf_num = LO_BYTE(setup->wIndex); + bool ret = true; + const uint8_t *p; + uint32_t desc_len = 0; + uint32_t current_desc_len = 0; + uint8_t cur_iface = 0xFF; + + p = g_usbd_core[busid].descriptors->config_descriptor_callback(g_usbd_core[busid].speed); + + /* Only when device is configured, then interface requests can be valid. */ + if (!is_device_configured(busid)) { + return false; + } + + switch (setup->bRequest) { + case USB_REQUEST_GET_STATUS: + (*data)[0] = 0x00; + (*data)[1] = 0x00; + *len = 2; + break; + + case USB_REQUEST_GET_DESCRIPTOR: + if (type == 0x21) { /* HID_DESCRIPTOR_TYPE_HID */ + while (p[DESC_bLength] != 0U) { + switch (p[DESC_bDescriptorType]) { + case USB_DESCRIPTOR_TYPE_CONFIGURATION: + current_desc_len = 0; + desc_len = (p[CONF_DESC_wTotalLength]) | + (p[CONF_DESC_wTotalLength + 1] << 8); + + break; + + case USB_DESCRIPTOR_TYPE_INTERFACE: + cur_iface = p[INTF_DESC_bInterfaceNumber]; + break; + case 0x21: + if (cur_iface == intf_num) { + *data = (uint8_t *)p; + //memcpy(*data, p, p[DESC_bLength]); + *len = p[DESC_bLength]; + return true; + } + break; + default: + break; + } + + /* skip to next descriptor */ + current_desc_len += p[DESC_bLength]; + p += p[DESC_bLength]; + if (current_desc_len >= desc_len && desc_len) { + break; + } + } + } else if (type == 0x22) { /* HID_DESCRIPTOR_TYPE_HID_REPORT */ + for (uint8_t i = 0; i < g_usbd_core[busid].intf_offset; i++) { + struct usbd_interface *intf = g_usbd_core[busid].intf[i]; + + if (intf && (intf->intf_num == intf_num)) { + *data = (uint8_t *)intf->hid_report_descriptor; + //memcpy(*data, intf->hid_report_descriptor, intf->hid_report_descriptor_len); + *len = intf->hid_report_descriptor_len; + return true; + } + } + } + ret = false; + break; + case USB_REQUEST_CLEAR_FEATURE: + case USB_REQUEST_SET_FEATURE: + ret = false; + break; + case USB_REQUEST_GET_INTERFACE: + (*data)[0] = g_usbd_core[busid].intf_altsetting[intf_num]; + *len = 1; + break; + + case USB_REQUEST_SET_INTERFACE: + g_usbd_core[busid].intf_altsetting[intf_num] = LO_BYTE(setup->wValue); + usbd_set_interface(busid, setup->wIndex, setup->wValue); + *len = 0; + break; + + default: + ret = false; + break; + } + + return ret; +} + +/** + * @brief handle a standard endpoint request + * + * @param [in] busid busid + * @param [in] setup The setup packet + * @param [in,out] data Data buffer + * @param [in,out] len Pointer to data length + * + * @return true if the request was handled successfully + */ +static bool usbd_std_endpoint_req_handler(uint8_t busid, struct usb_setup_packet *setup, uint8_t **data, uint32_t *len) +{ + uint8_t ep = (uint8_t)setup->wIndex; + bool ret = true; + uint8_t stalled; + + /* Only when device is configured, then endpoint requests can be valid. */ + if (!is_device_configured(busid)) { + return false; + } + + switch (setup->bRequest) { + case USB_REQUEST_GET_STATUS: + usbd_ep_is_stalled(busid, ep, &stalled); + if (stalled) { + (*data)[0] = 0x01; + } else { + (*data)[0] = 0x00; + } + (*data)[1] = 0x00; + *len = 2; + break; + case USB_REQUEST_CLEAR_FEATURE: + if (setup->wValue == USB_FEATURE_ENDPOINT_HALT) { + USB_LOG_ERR("ep:%02x clear halt\r\n", ep); + + usbd_ep_clear_stall(busid, ep); + break; + } else { + ret = false; + } + *len = 0; + break; + case USB_REQUEST_SET_FEATURE: + if (setup->wValue == USB_FEATURE_ENDPOINT_HALT) { + USB_LOG_ERR("ep:%02x set halt\r\n", ep); + + usbd_ep_set_stall(busid, ep); + } else { + ret = false; + } + *len = 0; + break; + + case USB_REQUEST_SYNCH_FRAME: + ret = false; + break; + default: + ret = false; + break; + } + + return ret; +} + +/** + * @brief handle standard requests (list in chapter 9) + * + * @param [in] busid busid + * @param [in] setup The setup packet + * @param [in,out] data Data buffer + * @param [in,out] len Pointer to data length + * + * @return true if the request was handled successfully + */ +static int usbd_standard_request_handler(uint8_t busid, struct usb_setup_packet *setup, uint8_t **data, uint32_t *len) +{ + int rc = 0; + + switch (setup->bmRequestType & USB_REQUEST_RECIPIENT_MASK) { + case USB_REQUEST_RECIPIENT_DEVICE: + if (usbd_std_device_req_handler(busid, setup, data, len) == false) { + rc = -1; + } + + break; + + case USB_REQUEST_RECIPIENT_INTERFACE: + if (usbd_std_interface_req_handler(busid, setup, data, len) == false) { + rc = -1; + } + + break; + + case USB_REQUEST_RECIPIENT_ENDPOINT: + if (usbd_std_endpoint_req_handler(busid, setup, data, len) == false) { + rc = -1; + } + + break; + + default: + rc = -1; + break; + } + + return rc; +} + +/** + * @brief handler for class requests + * + * @param [in] busid busid + * @param [in] setup The setup packet + * @param [in,out] data Data buffer + * @param [in,out] len Pointer to data length + * + * @return true if the request was handled successfully + */ +static int usbd_class_request_handler(uint8_t busid, struct usb_setup_packet *setup, uint8_t **data, uint32_t *len) +{ + if ((setup->bmRequestType & USB_REQUEST_RECIPIENT_MASK) == USB_REQUEST_RECIPIENT_INTERFACE) { + for (uint8_t i = 0; i < g_usbd_core[busid].intf_offset; i++) { + struct usbd_interface *intf = g_usbd_core[busid].intf[i]; + + if (intf && intf->class_interface_handler && (intf->intf_num == (setup->wIndex & 0xFF))) { + return intf->class_interface_handler(busid, setup, data, len); + } + } + } else if ((setup->bmRequestType & USB_REQUEST_RECIPIENT_MASK) == USB_REQUEST_RECIPIENT_ENDPOINT) { + for (uint8_t i = 0; i < g_usbd_core[busid].intf_offset; i++) { + struct usbd_interface *intf = g_usbd_core[busid].intf[i]; + + if (intf && intf->class_endpoint_handler) { + return intf->class_endpoint_handler(busid, setup, data, len); + } + } + } + return -1; +} + +/** + * @brief handler for vendor requests + * + * @param [in] busid busid + * @param [in] setup The setup packet + * @param [in,out] data Data buffer + * @param [in,out] len Pointer to data length + * + * @return true if the request was handled successfully + */ +static int usbd_vendor_request_handler(uint8_t busid, struct usb_setup_packet *setup, uint8_t **data, uint32_t *len) +{ + uint32_t desclen; + + if (g_usbd_core[busid].descriptors->msosv1_descriptor) { + if (setup->bRequest == g_usbd_core[busid].descriptors->msosv1_descriptor->vendor_code) { + switch (setup->wIndex) { + case 0x04: + desclen = g_usbd_core[busid].descriptors->msosv1_descriptor->compat_id[0] + + (g_usbd_core[busid].descriptors->msosv1_descriptor->compat_id[1] << 8) + + (g_usbd_core[busid].descriptors->msosv1_descriptor->compat_id[2] << 16) + + (g_usbd_core[busid].descriptors->msosv1_descriptor->compat_id[3] << 24); + + *data = (uint8_t *)g_usbd_core[busid].descriptors->msosv1_descriptor->compat_id; + //memcpy(*data, g_usbd_core[busid].descriptors->msosv1_descriptor->compat_id, desclen); + *len = desclen; + return 0; + case 0x05: + desclen = g_usbd_core[busid].descriptors->msosv1_descriptor->comp_id_property[setup->wValue][0] + + (g_usbd_core[busid].descriptors->msosv1_descriptor->comp_id_property[setup->wValue][1] << 8) + + (g_usbd_core[busid].descriptors->msosv1_descriptor->comp_id_property[setup->wValue][2] << 16) + + (g_usbd_core[busid].descriptors->msosv1_descriptor->comp_id_property[setup->wValue][3] << 24); + + *data = (uint8_t *)g_usbd_core[busid].descriptors->msosv1_descriptor->comp_id_property[setup->wValue]; + //memcpy(*data, g_usbd_core[busid].descriptors->msosv1_descriptor->comp_id_property[setup->wValue], desclen); + *len = desclen; + return 0; + default: + return -1; + } + } + } else if (g_usbd_core[busid].descriptors->msosv2_descriptor) { + if (setup->bRequest == g_usbd_core[busid].descriptors->msosv2_descriptor->vendor_code) { + switch (setup->wIndex) { + case WINUSB_REQUEST_GET_DESCRIPTOR_SET: + desclen = g_usbd_core[busid].descriptors->msosv2_descriptor->compat_id_len; + *data = (uint8_t *)g_usbd_core[busid].descriptors->msosv2_descriptor->compat_id; + //memcpy(*data, g_usbd_core[busid].descriptors->msosv2_descriptor->compat_id, desclen); + *len = g_usbd_core[busid].descriptors->msosv2_descriptor->compat_id_len; + return 0; + default: + return -1; + } + } + } + + if (g_usbd_core[busid].descriptors->webusb_url_descriptor) { + if (setup->bRequest == g_usbd_core[busid].descriptors->webusb_url_descriptor->vendor_code) { + switch (setup->wIndex) { + case WEBUSB_REQUEST_GET_URL: + desclen = g_usbd_core[busid].descriptors->webusb_url_descriptor->string_len; + *data = (uint8_t *)g_usbd_core[busid].descriptors->webusb_url_descriptor->string; + //memcpy(*data, g_usbd_core[busid].descriptors->webusb_url_descriptor->string, desclen); + *len = desclen; + return 0; + default: + return -1; + } + } + } + + for (uint8_t i = 0; i < g_usbd_core[busid].intf_offset; i++) { + struct usbd_interface *intf = g_usbd_core[busid].intf[i]; + + if (intf && intf->vendor_handler && (intf->vendor_handler(busid, setup, data, len) == 0)) { + return 0; + } + } + + return -1; +} + +/** + * @brief handle setup request( standard/class/vendor/other) + * + * @param [in] busid busid + * @param [in] setup The setup packet + * @param [in,out] data Data buffer + * @param [in,out] len Pointer to data length + * + * @return true if the request was handles successfully + */ +static bool usbd_setup_request_handler(uint8_t busid, struct usb_setup_packet *setup, uint8_t **data, uint32_t *len) +{ + switch (setup->bmRequestType & USB_REQUEST_TYPE_MASK) { + case USB_REQUEST_STANDARD: + if (usbd_standard_request_handler(busid, setup, data, len) < 0) { + /* Ignore error log for getting Device Qualifier Descriptor request */ + if ((setup->bRequest == 0x06) && (setup->wValue == 0x0600)) { + //USB_LOG_DBG("Ignore DQD in fs\r\n"); + return false; + } + USB_LOG_ERR("standard request error\r\n"); + usbd_print_setup(setup); + return false; + } + break; + case USB_REQUEST_CLASS: + if (usbd_class_request_handler(busid, setup, data, len) < 0) { + USB_LOG_ERR("class request error\r\n"); + usbd_print_setup(setup); + return false; + } + break; + case USB_REQUEST_VENDOR: + if (usbd_vendor_request_handler(busid, setup, data, len) < 0) { + USB_LOG_ERR("vendor request error\r\n"); + usbd_print_setup(setup); + return false; + } + break; + + default: + return false; + } + + return true; +} + +static void usbd_class_event_notify_handler(uint8_t busid, uint8_t event, void *arg) +{ + for (uint8_t i = 0; i < g_usbd_core[busid].intf_offset; i++) { + struct usbd_interface *intf = g_usbd_core[busid].intf[i]; + + if (arg) { + struct usb_interface_descriptor *desc = (struct usb_interface_descriptor *)arg; + if (intf && intf->notify_handler && (desc->bInterfaceNumber == (intf->intf_num))) { + intf->notify_handler(busid, event, arg); + } + } else { + if (intf && intf->notify_handler) { + intf->notify_handler(busid, event, arg); + } + } + } +} + +void usbd_event_sof_handler(uint8_t busid) +{ + g_usbd_core[busid].event_handler(busid, USBD_EVENT_SOF); +} + +void usbd_event_connect_handler(uint8_t busid) +{ + g_usbd_core[busid].event_handler(busid, USBD_EVENT_CONNECTED); +} + +void usbd_event_disconnect_handler(uint8_t busid) +{ + g_usbd_core[busid].configuration = 0; + g_usbd_core[busid].event_handler(busid, USBD_EVENT_DISCONNECTED); +} + +void usbd_event_resume_handler(uint8_t busid) +{ + g_usbd_core[busid].is_suspend = false; + g_usbd_core[busid].event_handler(busid, USBD_EVENT_RESUME); +} + +void usbd_event_suspend_handler(uint8_t busid) +{ + if (g_usbd_core[busid].device_address > 0) { + g_usbd_core[busid].is_suspend = true; + g_usbd_core[busid].event_handler(busid, USBD_EVENT_SUSPEND); + } +} + +void usbd_event_reset_handler(uint8_t busid) +{ + struct usb_endpoint_descriptor ep0; + + usbd_set_address(busid, 0); + g_usbd_core[busid].device_address = 0; + g_usbd_core[busid].configuration = 0; + g_usbd_core[busid].ep0_next_state = USBD_EP0_STATE_SETUP; + g_usbd_core[busid].speed = USB_SPEED_UNKNOWN; + + USB_ASSERT_MSG(g_usbd_core[busid].descriptors->device_descriptor_callback != NULL, + "device_descriptor_callback is NULL\r\n"); + + struct usb_device_descriptor *device_desc = (struct usb_device_descriptor *)g_usbd_core[busid].descriptors->device_descriptor_callback(g_usbd_core[busid].speed); + ep0.wMaxPacketSize = device_desc->bMaxPacketSize0; + + ep0.bLength = 7; + ep0.bDescriptorType = USB_DESCRIPTOR_TYPE_ENDPOINT; + ep0.bmAttributes = USB_ENDPOINT_TYPE_CONTROL; + ep0.bEndpointAddress = USB_CONTROL_IN_EP0; + ep0.bInterval = 0; + usbd_ep_open(busid, &ep0); + + ep0.bEndpointAddress = USB_CONTROL_OUT_EP0; + usbd_ep_open(busid, &ep0); + + usbd_class_event_notify_handler(busid, USBD_EVENT_RESET, NULL); + g_usbd_core[busid].event_handler(busid, USBD_EVENT_RESET); +} + +static void __usbd_event_ep0_setup_complete_handler(uint8_t busid, struct usb_setup_packet *setup) +{ + uint8_t *buf; + + USB_LOG_DBG("[%s] 0x%02x 0x%02x 0x%04x 0x%04x 0x%04x\r\n", + usb_ep0_state_string[usbd_get_ep0_next_state(busid)], + setup->bmRequestType, + setup->bRequest, + setup->wValue, + setup->wIndex, + setup->wLength); + + if (setup->wLength > CONFIG_USBDEV_REQUEST_BUFFER_LEN) { + if ((setup->bmRequestType & USB_REQUEST_DIR_MASK) == USB_REQUEST_DIR_OUT) { + USB_LOG_ERR("Request buffer too small\r\n"); + usbd_ep_set_stall(busid, USB_CONTROL_IN_EP0); + return; + } + } + + g_usbd_core[busid].ep0_data_buf = g_usbd_core[busid].req_data; + g_usbd_core[busid].ep0_data_buf_residue = setup->wLength; + g_usbd_core[busid].ep0_data_buf_len = setup->wLength; + g_usbd_core[busid].zlp_flag = false; + buf = g_usbd_core[busid].ep0_data_buf; + + /* handle class request when all the data is received */ + if (setup->wLength && ((setup->bmRequestType & USB_REQUEST_DIR_MASK) == USB_REQUEST_DIR_OUT)) { + USB_LOG_DBG("Start reading %d bytes from ep0\r\n", setup->wLength); + g_usbd_core[busid].ep0_next_state = USBD_EP0_STATE_OUT_DATA; + usbd_ep_start_read(busid, USB_CONTROL_OUT_EP0, g_usbd_core[busid].ep0_data_buf, setup->wLength); + return; + } + + /* Ask installed handler to process request */ + if (!usbd_setup_request_handler(busid, setup, &buf, &g_usbd_core[busid].ep0_data_buf_len)) { + g_usbd_core[busid].ep0_next_state = USBD_EP0_STATE_SETUP; + usbd_ep_set_stall(busid, USB_CONTROL_IN_EP0); + return; + } + + /* Send smallest of requested and offered length */ + g_usbd_core[busid].ep0_data_buf_residue = MIN(g_usbd_core[busid].ep0_data_buf_len, setup->wLength); + if (g_usbd_core[busid].ep0_data_buf_residue > CONFIG_USBDEV_REQUEST_BUFFER_LEN) { + USB_LOG_ERR("Request buffer too small\r\n"); + g_usbd_core[busid].ep0_next_state = USBD_EP0_STATE_SETUP; + usbd_ep_set_stall(busid, USB_CONTROL_IN_EP0); + return; + } + + /* use *data = xxx; g_usbd_core[busid].ep0_data_buf records real data address, we should copy data into ep0 buffer. + * Why we should copy once? because some chips are not access to flash with dma if real data address is in flash address(such as ch32). + */ + if (buf != g_usbd_core[busid].ep0_data_buf) { +#ifdef CONFIG_USBDEV_EP0_INDATA_NO_COPY + g_usbd_core[busid].ep0_data_buf = buf; +#else + usb_memcpy(g_usbd_core[busid].ep0_data_buf, buf, g_usbd_core[busid].ep0_data_buf_residue); +#endif + } else { + /* use memcpy(*data, xxx, len); has copied into ep0 buffer, we do nothing */ + } + + if (g_usbd_core[busid].ep0_data_buf_residue > 0) { + g_usbd_core[busid].ep0_next_state = USBD_EP0_STATE_IN_DATA; + } else { + g_usbd_core[busid].ep0_next_state = USBD_EP0_STATE_IN_STATUS; + } + + /* Send data or status to host */ + usbd_ep_start_write(busid, USB_CONTROL_IN_EP0, g_usbd_core[busid].ep0_data_buf, g_usbd_core[busid].ep0_data_buf_residue); + /* + * Set ZLP flag when host asks for a bigger length and the data size is + * multiplier of USB_CTRL_EP_MPS, to indicate the transfer done after zlp + * sent. + */ + if ((setup->wLength > g_usbd_core[busid].ep0_data_buf_len) && (!(g_usbd_core[busid].ep0_data_buf_len % USB_CTRL_EP_MPS))) { + g_usbd_core[busid].zlp_flag = true; + } +} + +void usbd_event_ep0_setup_complete_handler(uint8_t busid, uint8_t *psetup) +{ + struct usb_setup_packet *setup = &g_usbd_core[busid].setup; + + memcpy(setup, psetup, 8); + +#ifdef CONFIG_USBDEV_EP0_THREAD + usb_osal_mq_send(g_usbd_core[busid].usbd_ep0_mq, USB_EP0_STATE_SETUP); +#else + __usbd_event_ep0_setup_complete_handler(busid, setup); +#endif +} + +static void usbd_event_ep0_in_complete_handler(uint8_t busid, uint8_t ep, uint32_t nbytes) +{ + struct usb_setup_packet *setup = &g_usbd_core[busid].setup; + + (void)ep; + + g_usbd_core[busid].ep0_data_buf += nbytes; + g_usbd_core[busid].ep0_data_buf_residue -= nbytes; + + USB_LOG_DBG("[%s] in %d bytes, %d remained\r\n", + usb_ep0_state_string[usbd_get_ep0_next_state(busid)], + (unsigned int)nbytes, + (unsigned int)g_usbd_core[busid].ep0_data_buf_residue); + + if (g_usbd_core[busid].ep0_data_buf_residue != 0) { + /* Start sending the remain data */ + usbd_ep_start_write(busid, USB_CONTROL_IN_EP0, g_usbd_core[busid].ep0_data_buf, g_usbd_core[busid].ep0_data_buf_residue); + } else { + if (g_usbd_core[busid].zlp_flag == true) { + g_usbd_core[busid].zlp_flag = false; + /* Send zlp to host */ + USB_LOG_DBG("EP0 Send zlp\r\n"); + usbd_ep_start_write(busid, USB_CONTROL_IN_EP0, NULL, 0); + } else { + /* Satisfying three conditions will jump here. + * 1. send status completely + * 2. send zlp completely + * 3. send last data completely. + */ + if (setup->wLength && ((setup->bmRequestType & USB_REQUEST_DIR_MASK) == USB_REQUEST_DIR_IN)) { + /* if all data has sent completely, start reading out status */ + g_usbd_core[busid].ep0_next_state = USBD_EP0_STATE_OUT_STATUS; + usbd_ep_start_read(busid, USB_CONTROL_OUT_EP0, NULL, 0); + return; + } + + if (g_usbd_core[busid].ep0_next_state == USBD_EP0_STATE_IN_STATUS) { + g_usbd_core[busid].ep0_next_state = USBD_EP0_STATE_SETUP; + } + +#ifdef CONFIG_USBDEV_TEST_MODE + if (g_usbd_core[busid].test_req) { + usbd_execute_test_mode(busid, HI_BYTE(setup->wIndex)); + g_usbd_core[busid].test_req = false; + } +#endif + } + } +} + +static void usbd_event_ep0_out_complete_handler(uint8_t busid, uint8_t ep, uint32_t nbytes) +{ + struct usb_setup_packet *setup = &g_usbd_core[busid].setup; + + (void)ep; + (void)setup; + + USB_LOG_DBG("[%s] out %d bytes, %d remained\r\n", + usb_ep0_state_string[usbd_get_ep0_next_state(busid)], + (unsigned int)nbytes, + (unsigned int)g_usbd_core[busid].ep0_data_buf_residue); + + if (nbytes > 0) { + g_usbd_core[busid].ep0_data_buf += nbytes; + g_usbd_core[busid].ep0_data_buf_residue -= nbytes; + + if (g_usbd_core[busid].ep0_data_buf_residue == 0) { +#ifdef CONFIG_USBDEV_EP0_THREAD + usb_osal_mq_send(g_usbd_core[busid].usbd_ep0_mq, USB_EP0_STATE_OUT); +#else + /* Received all, send data to handler */ + g_usbd_core[busid].ep0_data_buf = g_usbd_core[busid].req_data; + if (!usbd_setup_request_handler(busid, setup, &g_usbd_core[busid].ep0_data_buf, &g_usbd_core[busid].ep0_data_buf_len)) { + g_usbd_core[busid].ep0_next_state = USBD_EP0_STATE_SETUP; + usbd_ep_set_stall(busid, USB_CONTROL_IN_EP0); + return; + } + + g_usbd_core[busid].ep0_next_state = USBD_EP0_STATE_IN_STATUS; + /*Send status to host*/ + usbd_ep_start_write(busid, USB_CONTROL_IN_EP0, NULL, 0); +#endif + } else { + /* Start reading the remain data */ + usbd_ep_start_read(busid, USB_CONTROL_OUT_EP0, g_usbd_core[busid].ep0_data_buf, g_usbd_core[busid].ep0_data_buf_residue); + } + } else { + /* Read out status completely, do nothing */ + g_usbd_core[busid].ep0_next_state = USBD_EP0_STATE_SETUP; + } +} + +void usbd_event_ep_in_complete_handler(uint8_t busid, uint8_t ep, uint32_t nbytes) +{ + if (g_usbd_core[busid].tx_msg[ep & 0x7f].cb) { + g_usbd_core[busid].tx_msg[ep & 0x7f].cb(busid, ep, nbytes); + } +} + +void usbd_event_ep_out_complete_handler(uint8_t busid, uint8_t ep, uint32_t nbytes) +{ + if (g_usbd_core[busid].rx_msg[ep & 0x7f].cb) { + g_usbd_core[busid].rx_msg[ep & 0x7f].cb(busid, ep, nbytes); + } +} + +void usbd_desc_register(uint8_t busid, const struct usb_descriptor *desc) +{ + memset(&g_usbd_core[busid], 0, sizeof(struct usbd_core_priv)); + + g_usbd_core[busid].descriptors = desc; + g_usbd_core[busid].intf_offset = 0; + + g_usbd_core[busid].tx_msg[0].ep = 0x80; + g_usbd_core[busid].tx_msg[0].cb = usbd_event_ep0_in_complete_handler; + g_usbd_core[busid].rx_msg[0].ep = 0x00; + g_usbd_core[busid].rx_msg[0].cb = usbd_event_ep0_out_complete_handler; +} + +void usbd_add_interface(uint8_t busid, struct usbd_interface *intf) +{ + intf->intf_num = g_usbd_core[busid].intf_offset; + g_usbd_core[busid].intf[g_usbd_core[busid].intf_offset] = intf; + g_usbd_core[busid].intf_offset++; +} + +void usbd_add_endpoint(uint8_t busid, struct usbd_endpoint *ep) +{ + if (ep->ep_addr & 0x80) { + g_usbd_core[busid].tx_msg[ep->ep_addr & 0x7f].ep = ep->ep_addr; + g_usbd_core[busid].tx_msg[ep->ep_addr & 0x7f].cb = ep->ep_cb; + } else { + g_usbd_core[busid].rx_msg[ep->ep_addr & 0x7f].ep = ep->ep_addr; + g_usbd_core[busid].rx_msg[ep->ep_addr & 0x7f].cb = ep->ep_cb; + } +} + +uint16_t usbd_get_ep_mps(uint8_t busid, uint8_t ep) +{ + if (ep & 0x80) { + return g_usbd_core[busid].tx_msg[ep & 0x7f].ep_mps; + } else { + return g_usbd_core[busid].rx_msg[ep & 0x7f].ep_mps; + } +} + +uint8_t usbd_get_ep_mult(uint8_t busid, uint8_t ep) +{ + if (ep & 0x80) { + return g_usbd_core[busid].tx_msg[ep & 0x7f].ep_mult; + } else { + return g_usbd_core[busid].rx_msg[ep & 0x7f].ep_mult; + } +} + +bool usb_device_is_configured(uint8_t busid) +{ + return g_usbd_core[busid].configuration; +} + +bool usb_device_is_suspend(uint8_t busid) +{ + return g_usbd_core[busid].is_suspend; +} + +int usbd_send_remote_wakeup(uint8_t busid) +{ + if (g_usbd_core[busid].remote_wakeup_support && g_usbd_core[busid].remote_wakeup_enabled && g_usbd_core[busid].is_suspend) { + return usbd_set_remote_wakeup(busid); + } else { + if (!g_usbd_core[busid].remote_wakeup_support) { + USB_LOG_ERR("device does not support remote wakeup\r\n"); + } + if (!g_usbd_core[busid].remote_wakeup_enabled) { + USB_LOG_ERR("device remote wakeup is not enabled\r\n"); + } + if (!g_usbd_core[busid].is_suspend) { + USB_LOG_ERR("device is not in suspend state\r\n"); + } + return -1; + } +} + +uint8_t usbd_get_ep0_next_state(uint8_t busid) +{ + return g_usbd_core[busid].ep0_next_state; +} + +#ifdef CONFIG_USBDEV_EP0_THREAD +static void usbdev_ep0_thread(CONFIG_USB_OSAL_THREAD_SET_ARGV) +{ + uintptr_t event; + int ret; + uint8_t busid = (uint8_t)CONFIG_USB_OSAL_THREAD_GET_ARGV; + struct usb_setup_packet *setup = &g_usbd_core[busid].setup; + + while (1) { + ret = usb_osal_mq_recv(g_usbd_core[busid].usbd_ep0_mq, (uintptr_t *)&event, USB_OSAL_WAITING_FOREVER); + if (ret < 0) { + continue; + } + USB_LOG_DBG("event:%d\r\n", (unsigned int)event); + + switch (event) { + case USB_EP0_STATE_SETUP: + __usbd_event_ep0_setup_complete_handler(busid, setup); + break; + case USB_EP0_STATE_IN: + // do nothing + break; + case USB_EP0_STATE_OUT: + /* Received all, send data to handler */ + g_usbd_core[busid].ep0_data_buf = g_usbd_core[busid].req_data; + if (!usbd_setup_request_handler(busid, setup, &g_usbd_core[busid].ep0_data_buf, &g_usbd_core[busid].ep0_data_buf_len)) { + g_usbd_core[busid].ep0_next_state = USBD_EP0_STATE_SETUP; + usbd_ep_set_stall(busid, USB_CONTROL_IN_EP0); + continue; + } + + g_usbd_core[busid].ep0_next_state = USBD_EP0_STATE_IN_STATUS; + /*Send status to host*/ + usbd_ep_start_write(busid, USB_CONTROL_IN_EP0, NULL, 0); + break; + + default: + break; + } + } +} +#endif + +int usbd_initialize(uint8_t busid, uintptr_t reg_base, void (*event_handler)(uint8_t busid, uint8_t event)) +{ + int ret; + struct usbd_bus *bus; + + USB_ASSERT_MSG(busid < CONFIG_USBDEV_MAX_BUS, "bus overflow\r\n"); + + bus = &g_usbdev_bus[busid]; + bus->reg_base = reg_base; + +#ifdef CONFIG_USBDEV_EP0_THREAD + g_usbd_core[busid].usbd_ep0_mq = usb_osal_mq_create(1); + if (g_usbd_core[busid].usbd_ep0_mq == NULL) { + USB_LOG_ERR("No memory to alloc for g_usbd_core[busid].usbd_ep0_mq\r\n"); + while (1) { + } + } + g_usbd_core[busid].usbd_ep0_thread = usb_osal_thread_create("usbd_ep0", CONFIG_USBDEV_EP0_STACKSIZE, CONFIG_USBDEV_EP0_PRIO, usbdev_ep0_thread, (void *)(uint32_t)busid); + if (g_usbd_core[busid].usbd_ep0_thread == NULL) { + USB_LOG_ERR("No memory to alloc for g_usbd_core[busid].usbd_ep0_thread\r\n"); + while (1) { + } + } +#endif + + g_usbd_core[busid].event_handler = event_handler; + usbd_class_event_notify_handler(busid, USBD_EVENT_INIT, NULL); + g_usbd_core[busid].event_handler(busid, USBD_EVENT_INIT); + ret = usb_dc_init(busid); + return ret; +} + +int usbd_deinitialize(uint8_t busid) +{ + USB_ASSERT_MSG(busid < CONFIG_USBDEV_MAX_BUS, "bus overflow\r\n"); + + usb_dc_deinit(busid); +#ifdef CONFIG_USBDEV_EP0_THREAD + if (g_usbd_core[busid].usbd_ep0_thread) { + usb_osal_thread_delete(g_usbd_core[busid].usbd_ep0_thread); + } + if (g_usbd_core[busid].usbd_ep0_mq) { + usb_osal_mq_delete(g_usbd_core[busid].usbd_ep0_mq); + } +#endif + g_usbd_core[busid].event_handler(busid, USBD_EVENT_DEINIT); + usbd_class_event_notify_handler(busid, USBD_EVENT_DEINIT, NULL); + return 0; +} diff --git a/kernel/cherryusb/core/usbd_core.h b/kernel/cherryusb/core/usbd_core.h new file mode 100644 index 0000000..ac9c58f --- /dev/null +++ b/kernel/cherryusb/core/usbd_core.h @@ -0,0 +1,120 @@ +/* + * Copyright (c) 2022, sakumisu + * + * SPDX-License-Identifier: Apache-2.0 + */ +#ifndef USBD_CORE_H +#define USBD_CORE_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include +#include +#include + +#include "usb_config.h" +#include "usb_util.h" +#include "usb_errno.h" +#include "usb_def.h" +#include "usb_list.h" +#include "usb_log.h" +#include "usb_dc.h" +#include "usb_osal.h" +#include "usb_memcpy.h" +#include "usb_ringbuffer.h" +#include "usb_mempool.h" +#include "usb_dcache.h" +#include "usb_version.h" + +enum usbd_event_type { + /* USB DCD IRQ */ + USBD_EVENT_ERROR, /** USB error reported by the controller */ + USBD_EVENT_RESET, /** USB reset */ + USBD_EVENT_SOF, /** Start of Frame received */ + USBD_EVENT_CONNECTED, /** USB connected*/ + USBD_EVENT_DISCONNECTED, /** USB disconnected */ + USBD_EVENT_SUSPEND, /** USB connection suspended by the HOST */ + USBD_EVENT_RESUME, /** USB connection resumed by the HOST */ + + /* USB DEVICE STATUS */ + USBD_EVENT_CONFIGURED, /** USB configuration done */ + USBD_EVENT_SET_INTERFACE, /** USB interface selected */ + USBD_EVENT_SET_REMOTE_WAKEUP, /** USB set remote wakeup */ + USBD_EVENT_CLR_REMOTE_WAKEUP, /** USB clear remote wakeup */ + USBD_EVENT_INIT, /** USB init done when call usbd_initialize */ + USBD_EVENT_DEINIT, /** USB deinit done when call usbd_deinitialize */ + USBD_EVENT_UNKNOWN +}; + +#define USBD_EP0_STATE_SETUP 0 +#define USBD_EP0_STATE_IN_DATA 1 +#define USBD_EP0_STATE_OUT_DATA 2 +#define USBD_EP0_STATE_IN_STATUS 3 +#define USBD_EP0_STATE_OUT_STATUS 4 + +typedef int (*usbd_request_handler)(uint8_t busid, struct usb_setup_packet *setup, uint8_t **data, uint32_t *len); +typedef void (*usbd_endpoint_callback)(uint8_t busid, uint8_t ep, uint32_t nbytes); +typedef void (*usbd_notify_handler)(uint8_t busid, uint8_t event, void *arg); +typedef void (*usbd_event_handler_t)(uint8_t busid, uint8_t event); + +struct usbd_endpoint { + uint8_t ep_addr; + usbd_endpoint_callback ep_cb; +}; + +struct usbd_interface { + usbd_request_handler class_interface_handler; + usbd_request_handler class_endpoint_handler; + usbd_request_handler vendor_handler; + usbd_notify_handler notify_handler; + const uint8_t *hid_report_descriptor; + uint32_t hid_report_descriptor_len; + uint8_t intf_num; +}; + +struct usb_descriptor { + const uint8_t *(*device_descriptor_callback)(uint8_t speed); + const uint8_t *(*config_descriptor_callback)(uint8_t speed); + const uint8_t *(*device_quality_descriptor_callback)(uint8_t speed); + const uint8_t *(*other_speed_descriptor_callback)(uint8_t speed); + const char *(*string_descriptor_callback)(uint8_t speed, uint8_t index); + const struct usb_msosv1_descriptor *msosv1_descriptor; + const struct usb_msosv2_descriptor *msosv2_descriptor; + const struct usb_webusb_descriptor *webusb_url_descriptor; + const struct usb_bos_descriptor *bos_descriptor; +}; + +struct usbd_bus { + uint8_t busid; + uintptr_t reg_base; +}; + +extern struct usbd_bus g_usbdev_bus[]; + +#ifdef USBD_IRQHandler +#error USBD_IRQHandler is obsolete, please call USBD_IRQHandler(xxx) in your irq +#endif + +void usbd_desc_register(uint8_t busid, const struct usb_descriptor *desc); + +void usbd_add_interface(uint8_t busid, struct usbd_interface *intf); +void usbd_add_endpoint(uint8_t busid, struct usbd_endpoint *ep); + +uint16_t usbd_get_ep_mps(uint8_t busid, uint8_t ep); +uint8_t usbd_get_ep_mult(uint8_t busid, uint8_t ep); +bool usb_device_is_configured(uint8_t busid); +bool usb_device_is_suspend(uint8_t busid); +int usbd_send_remote_wakeup(uint8_t busid); +uint8_t usbd_get_ep0_next_state(uint8_t busid); + +int usbd_initialize(uint8_t busid, uintptr_t reg_base, usbd_event_handler_t event_handler); +int usbd_deinitialize(uint8_t busid); + +#ifdef __cplusplus +} +#endif + +#endif /* USBD_CORE_H */ diff --git a/kernel/cherryusb/core/usbh_core.c b/kernel/cherryusb/core/usbh_core.c new file mode 100644 index 0000000..cce9a46 --- /dev/null +++ b/kernel/cherryusb/core/usbh_core.c @@ -0,0 +1,1218 @@ +/* + * Copyright (c) 2022, sakumisu + * + * SPDX-License-Identifier: Apache-2.0 + */ +#include "usbh_core.h" + +#undef USB_DBG_TAG +#define USB_DBG_TAG "usbh_core" +#include "usb_log.h" + +struct usbh_class_info *usbh_class_info_table_begin = NULL; +struct usbh_class_info *usbh_class_info_table_end = NULL; + +usb_slist_t g_bus_head = USB_SLIST_OBJECT_INIT(g_bus_head); + +struct setup_align_buffer { + uint8_t buffer[USB_ALIGN_UP(8, CONFIG_USB_ALIGN_SIZE)]; +}; + +USB_NOCACHE_RAM_SECTION USB_MEM_ALIGNX uint8_t ep0_request_buffer[CONFIG_USBHOST_MAX_BUS][USB_ALIGN_UP(CONFIG_USBHOST_REQUEST_BUFFER_LEN, CONFIG_USB_ALIGN_SIZE)]; +USB_NOCACHE_RAM_SECTION USB_MEM_ALIGNX struct setup_align_buffer g_setup_buffer[CONFIG_USBHOST_MAX_BUS][CONFIG_USBHOST_MAX_EXTHUBS + 1][CONFIG_USBHOST_MAX_EHPORTS]; + +struct usbh_bus g_usbhost_bus[CONFIG_USBHOST_MAX_BUS]; + +/* general descriptor field offsets */ +#define DESC_bLength 0 /** Length offset */ +#define DESC_bDescriptorType 1 /** Descriptor type offset */ + +#define USB_DEV_ADDR_MAX 0x7f +#define USB_DEV_ADDR_MARK_OFFSET 5 +#define USB_DEV_ADDR_MARK_MASK 0x1f + +static void dummy_event_handler(uint8_t busid, uint8_t hub_index, uint8_t hub_port, uint8_t intf, uint8_t event) +{ + (void)busid; + (void)hub_index; + (void)hub_port; + (void)intf; + (void)event; +} + +static int usbh_allocate_devaddr(struct usbh_devaddr_map *devgen) +{ + uint8_t lastaddr = devgen->last; + uint8_t devaddr = lastaddr; + int index; + int bitno; + + for (;;) { + devaddr++; + if (devaddr > 0x7f) { + devaddr = 2; + } + if (devaddr == lastaddr) { + return -USB_ERR_NOMEM; + } + + index = devaddr >> 5; + bitno = devaddr & 0x1f; + if ((devgen->alloctab[index] & (1ul << bitno)) == 0) { + devgen->alloctab[index] |= (1ul << bitno); + devgen->last = devaddr; + return (int)devaddr; + } + } +} + +static int __usbh_free_devaddr(struct usbh_devaddr_map *devgen, uint8_t devaddr) +{ + int index; + int bitno; + + if ((devaddr > 0) && (devaddr < USB_DEV_ADDR_MAX)) { + index = devaddr >> USB_DEV_ADDR_MARK_OFFSET; + bitno = devaddr & USB_DEV_ADDR_MARK_MASK; + + /* Free the address */ + if ((devgen->alloctab[index] & (1ul << bitno)) != 0) { + devgen->alloctab[index] &= ~(1ul << bitno); + } else { + return -1; + } + } + + return 0; +} + +static int usbh_free_devaddr(struct usbh_hubport *hport) +{ + if (hport->dev_addr > 0) { + __usbh_free_devaddr(&hport->bus->devgen, hport->dev_addr); + } + return 0; +} + +static const struct usbh_class_driver *usbh_find_class_driver(uint8_t class, uint8_t subclass, uint8_t protocol, uint8_t intf, + uint16_t vid, uint16_t pid) +{ + struct usbh_class_info *index = NULL; + + for (index = usbh_class_info_table_begin; index < usbh_class_info_table_end; index++) { + if ((index->match_flags & USB_CLASS_MATCH_INTF_CLASS) && !(index->bInterfaceClass == class)) { + continue; + } + if ((index->match_flags & USB_CLASS_MATCH_INTF_SUBCLASS) && !(index->bInterfaceSubClass == subclass)) { + continue; + } + if ((index->match_flags & USB_CLASS_MATCH_INTF_PROTOCOL) && !(index->bInterfaceProtocol == protocol)) { + continue; + } + if ((index->match_flags & USB_CLASS_MATCH_INTF_NUM) && !(index->bInterfaceNumber == intf)) { + continue; + } + if (index->match_flags & USB_CLASS_MATCH_VID_PID && index->id_table) { + /* scan id table */ + uint32_t i; + for (i = 0; index->id_table[i][0]; i++) { + if (index->id_table[i][0] == vid && index->id_table[i][1] == pid) { + break; + } + } + /* do not match, continue next */ + if (!index->id_table[i][0]) { + continue; + } + } + return index->class_driver; + } + return NULL; +} + +static int parse_device_descriptor(struct usbh_hubport *hport, struct usb_device_descriptor *desc, uint16_t length) +{ + if (desc->bLength != USB_SIZEOF_DEVICE_DESC) { + USB_LOG_ERR("invalid device bLength 0x%02x\r\n", desc->bLength); + return -USB_ERR_INVAL; + } else if (desc->bDescriptorType != USB_DESCRIPTOR_TYPE_DEVICE) { + USB_LOG_ERR("unexpected device descriptor 0x%02x\r\n", desc->bDescriptorType); + return -USB_ERR_INVAL; + } else { + if (length <= 8) { + return 0; + } +#if 0 + USB_LOG_DBG("Device Descriptor:\r\n"); + USB_LOG_DBG("bLength: 0x%02x \r\n", desc->bLength); + USB_LOG_DBG("bDescriptorType: 0x%02x \r\n", desc->bDescriptorType); + USB_LOG_DBG("bcdUSB: 0x%04x \r\n", desc->bcdUSB); + USB_LOG_DBG("bDeviceClass: 0x%02x \r\n", desc->bDeviceClass); + USB_LOG_DBG("bDeviceSubClass: 0x%02x \r\n", desc->bDeviceSubClass); + USB_LOG_DBG("bDeviceProtocol: 0x%02x \r\n", desc->bDeviceProtocol); + USB_LOG_DBG("bMaxPacketSize0: 0x%02x \r\n", desc->bMaxPacketSize0); + USB_LOG_DBG("idVendor: 0x%04x \r\n", desc->idVendor); + USB_LOG_DBG("idProduct: 0x%04x \r\n", desc->idProduct); + USB_LOG_DBG("bcdDevice: 0x%04x \r\n", desc->bcdDevice); + USB_LOG_DBG("iManufacturer: 0x%02x \r\n", desc->iManufacturer); + USB_LOG_DBG("iProduct: 0x%02x \r\n", desc->iProduct); + USB_LOG_DBG("iSerialNumber: 0x%02x \r\n", desc->iSerialNumber); + USB_LOG_DBG("bNumConfigurations: 0x%02x\r\n", desc->bNumConfigurations); +#endif + hport->device_desc.bLength = desc->bLength; + hport->device_desc.bDescriptorType = desc->bDescriptorType; + hport->device_desc.bcdUSB = desc->bcdUSB; + hport->device_desc.bDeviceClass = desc->bDeviceClass; + hport->device_desc.bDeviceSubClass = desc->bDeviceSubClass; + hport->device_desc.bDeviceProtocol = desc->bDeviceProtocol; + hport->device_desc.bMaxPacketSize0 = desc->bMaxPacketSize0; + hport->device_desc.idVendor = desc->idVendor; + hport->device_desc.idProduct = desc->idProduct; + hport->device_desc.bcdDevice = desc->bcdDevice; + hport->device_desc.iManufacturer = desc->iManufacturer; + hport->device_desc.iProduct = desc->iProduct; + hport->device_desc.iSerialNumber = desc->iSerialNumber; + hport->device_desc.bNumConfigurations = desc->bNumConfigurations; + } + return 0; +} + +static int parse_config_descriptor(struct usbh_hubport *hport, struct usb_configuration_descriptor *desc, uint16_t length) +{ + struct usb_interface_descriptor *intf_desc; + struct usb_endpoint_descriptor *ep_desc; + uint8_t cur_alt_setting = 0xff; + uint8_t cur_iface = 0xff; + uint8_t cur_ep = 0xff; + uint8_t cur_ep_num = 0xff; + uint32_t desc_len = 0; + uint8_t *p; + + if (desc->bLength != USB_SIZEOF_CONFIG_DESC) { + USB_LOG_ERR("invalid config bLength 0x%02x\r\n", desc->bLength); + return -USB_ERR_INVAL; + } else if (desc->bDescriptorType != USB_DESCRIPTOR_TYPE_CONFIGURATION) { + USB_LOG_ERR("unexpected config descriptor 0x%02x\r\n", desc->bDescriptorType); + return -USB_ERR_INVAL; + } else { + if (length <= USB_SIZEOF_CONFIG_DESC) { + return 0; + } +#if 0 + USB_LOG_DBG("Config Descriptor:\r\n"); + USB_LOG_DBG("bLength: 0x%02x \r\n", desc->bLength); + USB_LOG_DBG("bDescriptorType: 0x%02x \r\n", desc->bDescriptorType); + USB_LOG_DBG("wTotalLength: 0x%04x \r\n", desc->wTotalLength); + USB_LOG_DBG("bNumInterfaces: 0x%02x \r\n", desc->bNumInterfaces); + USB_LOG_DBG("bConfigurationValue: 0x%02x \r\n", desc->bConfigurationValue); + USB_LOG_DBG("iConfiguration: 0x%02x \r\n", desc->iConfiguration); + USB_LOG_DBG("bmAttributes: 0x%02x \r\n", desc->bmAttributes); + USB_LOG_DBG("bMaxPower: 0x%02x \r\n", desc->bMaxPower); +#endif + hport->config.config_desc.bLength = desc->bLength; + hport->config.config_desc.bDescriptorType = desc->bDescriptorType; + hport->config.config_desc.wTotalLength = desc->wTotalLength; + hport->config.config_desc.bNumInterfaces = desc->bNumInterfaces; + hport->config.config_desc.bConfigurationValue = desc->bConfigurationValue; + hport->config.config_desc.iConfiguration = desc->iConfiguration; + hport->config.config_desc.iConfiguration = desc->iConfiguration; + hport->config.config_desc.bmAttributes = desc->bmAttributes; + hport->config.config_desc.bMaxPower = desc->bMaxPower; + + p = (uint8_t *)desc; + p += USB_SIZEOF_CONFIG_DESC; + desc_len = USB_SIZEOF_CONFIG_DESC; + + memset(hport->config.intf, 0, sizeof(struct usbh_interface) * CONFIG_USBHOST_MAX_INTERFACES); + + while (p[DESC_bLength] && (desc_len <= length)) { + switch (p[DESC_bDescriptorType]) { + case USB_DESCRIPTOR_TYPE_INTERFACE: + intf_desc = (struct usb_interface_descriptor *)p; + cur_iface = intf_desc->bInterfaceNumber; + cur_alt_setting = intf_desc->bAlternateSetting; + cur_ep_num = intf_desc->bNumEndpoints; + cur_ep = 0; + + if (cur_iface >= CONFIG_USBHOST_MAX_INTERFACES) { + USB_LOG_ERR("Interface num %d overflow\r\n", cur_iface); + return -USB_ERR_NOMEM; + } + + if (cur_ep_num >= CONFIG_USBHOST_MAX_ENDPOINTS) { + USB_LOG_ERR("Endpoint num %d overflow\r\n", cur_ep_num); + return -USB_ERR_NOMEM; + } + + if (cur_alt_setting >= CONFIG_USBHOST_MAX_INTF_ALTSETTINGS) { + USB_LOG_ERR("Interface altsetting num %d overflow\r\n", cur_alt_setting); + return -USB_ERR_NOMEM; + } + +#if 0 + USB_LOG_DBG("Interface Descriptor:\r\n"); + USB_LOG_DBG("bLength: 0x%02x \r\n", intf_desc->bLength); + USB_LOG_DBG("bDescriptorType: 0x%02x \r\n", intf_desc->bDescriptorType); + USB_LOG_DBG("bInterfaceNumber: 0x%02x \r\n", intf_desc->bInterfaceNumber); + USB_LOG_DBG("bAlternateSetting: 0x%02x \r\n", intf_desc->bAlternateSetting); + USB_LOG_DBG("bNumEndpoints: 0x%02x \r\n", intf_desc->bNumEndpoints); + USB_LOG_DBG("bInterfaceClass: 0x%02x \r\n", intf_desc->bInterfaceClass); + USB_LOG_DBG("bInterfaceSubClass: 0x%02x \r\n", intf_desc->bInterfaceSubClass); + USB_LOG_DBG("bInterfaceProtocol: 0x%02x \r\n", intf_desc->bInterfaceProtocol); + USB_LOG_DBG("iInterface: 0x%02x \r\n", intf_desc->iInterface); +#endif + memcpy(&hport->config.intf[cur_iface].altsetting[cur_alt_setting].intf_desc, intf_desc, 9); + hport->config.intf[cur_iface].altsetting_num = cur_alt_setting + 1; + break; + case USB_DESCRIPTOR_TYPE_ENDPOINT: + ep_desc = (struct usb_endpoint_descriptor *)p; + memcpy(&hport->config.intf[cur_iface].altsetting[cur_alt_setting].ep[cur_ep].ep_desc, ep_desc, 7); + cur_ep++; + break; + + default: + break; + } + /* skip to next descriptor */ + desc_len += p[DESC_bLength]; + p += p[DESC_bLength]; + } + } + return 0; +} + +static void usbh_print_setup(struct usb_setup_packet *setup) +{ + (void)setup; + + USB_LOG_DBG("Setup: " + "bmRequestType 0x%02x, bRequest 0x%02x, wValue 0x%04x, wIndex 0x%04x, wLength 0x%04x\r\n", + setup->bmRequestType, + setup->bRequest, + setup->wValue, + setup->wIndex, + setup->wLength); +} + +static int usbh_get_default_mps(int speed) +{ + switch (speed) { + case USB_SPEED_LOW: /* For low speed, we use 8 bytes */ + return 8; + case USB_SPEED_FULL: /* For full or high speed, we use 64 bytes */ + case USB_SPEED_HIGH: + return 64; + case USB_SPEED_SUPER: /* For super speed , we must use 512 bytes */ + case USB_SPEED_SUPER_PLUS: + return 512; + default: + return 64; + } +} + +int usbh_enumerate(struct usbh_hubport *hport) +{ + struct usb_interface_descriptor *intf_desc; + struct usb_setup_packet *setup; + struct usb_device_descriptor *dev_desc; + struct usb_endpoint_descriptor *ep; + int dev_addr; + uint16_t ep_mps; + uint8_t config_value; + uint8_t config_index; + int ret; + + hport->setup = (struct usb_setup_packet *)&g_setup_buffer[hport->bus->busid][hport->parent->index - 1][hport->port - 1]; + setup = hport->setup; + ep = &hport->ep0; + + /* Config EP0 mps from speed */ + ep->bEndpointAddress = 0x00; + ep->bDescriptorType = USB_DESCRIPTOR_TYPE_ENDPOINT; + ep->bmAttributes = USB_ENDPOINT_TYPE_CONTROL; + ep->wMaxPacketSize = usbh_get_default_mps(hport->speed); + ep->bInterval = 0; + ep->bLength = 7; + + /* Configure EP0 with zero address */ + hport->dev_addr = 0; + + /* Read the first 8 bytes of the device descriptor */ + setup->bmRequestType = USB_REQUEST_DIR_IN | USB_REQUEST_STANDARD | USB_REQUEST_RECIPIENT_DEVICE; + setup->bRequest = USB_REQUEST_GET_DESCRIPTOR; + setup->wValue = (uint16_t)((USB_DESCRIPTOR_TYPE_DEVICE << 8) | 0); + setup->wIndex = 0; + setup->wLength = 8; + + ret = usbh_control_transfer(hport, setup, ep0_request_buffer[hport->bus->busid]); + if (ret < 0) { + USB_LOG_ERR("Failed to get device descriptor,errorcode:%d\r\n", ret); + goto errout; + } + + ret = parse_device_descriptor(hport, (struct usb_device_descriptor *)ep0_request_buffer[hport->bus->busid], 8); + if (ret < 0) { + USB_LOG_ERR("Parse device descriptor fail\r\n"); + goto errout; + } + + /* Extract the correct max packetsize from the device descriptor */ + dev_desc = (struct usb_device_descriptor *)ep0_request_buffer[hport->bus->busid]; + if (dev_desc->bcdUSB >= USB_3_0) { + ep_mps = 1 << dev_desc->bMaxPacketSize0; + } else { + ep_mps = dev_desc->bMaxPacketSize0; + } + + USB_LOG_DBG("Device rev=%04x cls=%02x sub=%02x proto=%02x size=%d\r\n", + dev_desc->bcdUSB, dev_desc->bDeviceClass, dev_desc->bDeviceSubClass, + dev_desc->bDeviceProtocol, ep_mps); + + /* Reconfigure EP0 with the correct maximum packet size */ + ep->wMaxPacketSize = ep_mps; + + /* Assign a function address to the device connected to this port */ + dev_addr = usbh_allocate_devaddr(&hport->bus->devgen); + if (dev_addr < 0) { + USB_LOG_ERR("Failed to allocate devaddr,errorcode:%d\r\n", ret); + goto errout; + } + + /* Set the USB device address */ + setup->bmRequestType = USB_REQUEST_DIR_OUT | USB_REQUEST_STANDARD | USB_REQUEST_RECIPIENT_DEVICE; + setup->bRequest = USB_REQUEST_SET_ADDRESS; + setup->wValue = dev_addr; + setup->wIndex = 0; + setup->wLength = 0; + + ret = usbh_control_transfer(hport, setup, NULL); + if (ret < 0) { + USB_LOG_ERR("Failed to set devaddr,errorcode:%d\r\n", ret); + goto errout; + } + + /* Wait device set address completely */ + usb_osal_msleep(10); + + /*Reconfigure EP0 with the correct address */ + hport->dev_addr = dev_addr; + + /* Read the full device descriptor */ + setup->bmRequestType = USB_REQUEST_DIR_IN | USB_REQUEST_STANDARD | USB_REQUEST_RECIPIENT_DEVICE; + setup->bRequest = USB_REQUEST_GET_DESCRIPTOR; + setup->wValue = (uint16_t)((USB_DESCRIPTOR_TYPE_DEVICE << 8) | 0); + setup->wIndex = 0; + setup->wLength = USB_SIZEOF_DEVICE_DESC; + + ret = usbh_control_transfer(hport, setup, ep0_request_buffer[hport->bus->busid]); + if (ret < 0) { + USB_LOG_ERR("Failed to get full device descriptor,errorcode:%d\r\n", ret); + goto errout; + } + + parse_device_descriptor(hport, (struct usb_device_descriptor *)ep0_request_buffer[hport->bus->busid], USB_SIZEOF_DEVICE_DESC); + USB_LOG_INFO("New device found,idVendor:%04x,idProduct:%04x,bcdDevice:%04x\r\n", + ((struct usb_device_descriptor *)ep0_request_buffer[hport->bus->busid])->idVendor, + ((struct usb_device_descriptor *)ep0_request_buffer[hport->bus->busid])->idProduct, + ((struct usb_device_descriptor *)ep0_request_buffer[hport->bus->busid])->bcdDevice); + + USB_LOG_INFO("The device has %d bNumConfigurations\r\n", ((struct usb_device_descriptor *)ep0_request_buffer[hport->bus->busid])->bNumConfigurations); + + config_index = usbh_get_hport_active_config_index(hport); + USB_LOG_DBG("The device selects config %d\r\n", config_index); + + /* Read the first 9 bytes of the config descriptor */ + setup->bmRequestType = USB_REQUEST_DIR_IN | USB_REQUEST_STANDARD | USB_REQUEST_RECIPIENT_DEVICE; + setup->bRequest = USB_REQUEST_GET_DESCRIPTOR; + setup->wValue = (uint16_t)((USB_DESCRIPTOR_TYPE_CONFIGURATION << 8) | config_index); + setup->wIndex = 0; + setup->wLength = USB_SIZEOF_CONFIG_DESC; + + ret = usbh_control_transfer(hport, setup, ep0_request_buffer[hport->bus->busid]); + if (ret < 0) { + USB_LOG_ERR("Failed to get config descriptor,errorcode:%d\r\n", ret); + goto errout; + } + + ret = parse_config_descriptor(hport, (struct usb_configuration_descriptor *)ep0_request_buffer[hport->bus->busid], USB_SIZEOF_CONFIG_DESC); + if (ret < 0) { + USB_LOG_ERR("Parse config descriptor fail\r\n"); + goto errout; + } + + /* Read the full size of the configuration data */ + uint16_t wTotalLength = ((struct usb_configuration_descriptor *)ep0_request_buffer[hport->bus->busid])->wTotalLength; + + if (wTotalLength > CONFIG_USBHOST_REQUEST_BUFFER_LEN) { + ret = -USB_ERR_NOMEM; + USB_LOG_ERR("wTotalLength %d is overflow, default is %d\r\n", wTotalLength, (unsigned int)CONFIG_USBHOST_REQUEST_BUFFER_LEN); + goto errout; + } + + setup->bmRequestType = USB_REQUEST_DIR_IN | USB_REQUEST_STANDARD | USB_REQUEST_RECIPIENT_DEVICE; + setup->bRequest = USB_REQUEST_GET_DESCRIPTOR; + setup->wValue = (uint16_t)((USB_DESCRIPTOR_TYPE_CONFIGURATION << 8) | config_index); + setup->wIndex = 0; + setup->wLength = wTotalLength; + + ret = usbh_control_transfer(hport, setup, ep0_request_buffer[hport->bus->busid]); + if (ret < 0) { + USB_LOG_ERR("Failed to get full config descriptor,errorcode:%d\r\n", ret); + goto errout; + } + + ret = parse_config_descriptor(hport, (struct usb_configuration_descriptor *)ep0_request_buffer[hport->bus->busid], wTotalLength); + if (ret < 0) { + USB_LOG_ERR("Parse config descriptor fail\r\n"); + goto errout; + } + + USB_LOG_INFO("The device has %d interfaces\r\n", ((struct usb_configuration_descriptor *)ep0_request_buffer[hport->bus->busid])->bNumInterfaces); + hport->raw_config_desc = usb_osal_malloc(wTotalLength + 1); + if (hport->raw_config_desc == NULL) { + ret = -USB_ERR_NOMEM; + USB_LOG_ERR("No memory to alloc for raw_config_desc\r\n"); + goto errout; + } + + config_value = ((struct usb_configuration_descriptor *)ep0_request_buffer[hport->bus->busid])->bConfigurationValue; + memcpy(hport->raw_config_desc, ep0_request_buffer[hport->bus->busid], wTotalLength); + hport->raw_config_desc[wTotalLength] = '\0'; + +#ifdef CONFIG_USBHOST_GET_STRING_DESC + uint8_t string_buffer[128]; + + if (hport->device_desc.iManufacturer > 0) { + /* Get Manufacturer string */ + memset(string_buffer, 0, 128); + ret = usbh_get_string_desc(hport, USB_STRING_MFC_INDEX, string_buffer, 128); + if (ret < 0) { + USB_LOG_ERR("Failed to get Manufacturer string,errorcode:%d\r\n", ret); + goto errout; + } + + USB_LOG_INFO("Manufacturer: %s\r\n", string_buffer); + } else { + USB_LOG_WRN("Do not support Manufacturer string\r\n"); + } + + if (hport->device_desc.iProduct > 0) { + /* Get Product string */ + memset(string_buffer, 0, 128); + ret = usbh_get_string_desc(hport, USB_STRING_PRODUCT_INDEX, string_buffer, 128); + if (ret < 0) { + USB_LOG_ERR("Failed to get Product string,errorcode:%d\r\n", ret); + goto errout; + } + + USB_LOG_INFO("Product: %s\r\n", string_buffer); + } else { + USB_LOG_WRN("Do not support Product string\r\n"); + } + + if (hport->device_desc.iSerialNumber > 0) { + /* Get SerialNumber string */ + memset(string_buffer, 0, 128); + ret = usbh_get_string_desc(hport, USB_STRING_SERIAL_INDEX, string_buffer, 128); + if (ret < 0) { + USB_LOG_ERR("Failed to get SerialNumber string,errorcode:%d\r\n", ret); + goto errout; + } + + USB_LOG_INFO("SerialNumber: %s\r\n", string_buffer); + } else { + USB_LOG_WRN("Do not support SerialNumber string\r\n"); + } +#endif + /* Select device configuration 1 */ + setup->bmRequestType = USB_REQUEST_DIR_OUT | USB_REQUEST_STANDARD | USB_REQUEST_RECIPIENT_DEVICE; + setup->bRequest = USB_REQUEST_SET_CONFIGURATION; + setup->wValue = config_value; + setup->wIndex = 0; + setup->wLength = 0; + + ret = usbh_control_transfer(hport, setup, NULL); + if (ret < 0) { + USB_LOG_ERR("Failed to set configuration,errorcode:%d\r\n", ret); + goto errout; + } + +#ifdef CONFIG_USBHOST_MSOS_ENABLE + setup->bmRequestType = USB_REQUEST_DIR_IN | USB_REQUEST_VENDOR | USB_REQUEST_RECIPIENT_DEVICE; + setup->bRequest = CONFIG_USBHOST_MSOS_VENDOR_CODE; + setup->wValue = 0; + setup->wIndex = 0x0004; + setup->wLength = 16; + + ret = usbh_control_transfer(hport, setup, ep0_request_buffer[hport->bus->busid]); + if (ret < 0 && (ret != -USB_ERR_STALL)) { + USB_LOG_ERR("Failed to get msosv1 compat id,errorcode:%d\r\n", ret); + goto errout; + } +#endif + USB_LOG_INFO("Enumeration success, start loading class driver\r\n"); + hport->bus->event_handler(hport->bus->busid, hport->parent->index, hport->port, USB_INTERFACE_ANY, USBH_EVENT_DEVICE_CONFIGURED); + /*search supported class driver*/ + for (uint8_t i = 0; i < hport->config.config_desc.bNumInterfaces; i++) { + intf_desc = &hport->config.intf[i].altsetting[0].intf_desc; + + USB_ASSERT_MSG(intf_desc->bInterfaceNumber == i, "Interface number mismatch, do not support non-standard device\r\n"); + + struct usbh_class_driver *class_driver = (struct usbh_class_driver *)usbh_find_class_driver(intf_desc->bInterfaceClass, + intf_desc->bInterfaceSubClass, + intf_desc->bInterfaceProtocol, + intf_desc->bInterfaceNumber, + hport->device_desc.idVendor, + hport->device_desc.idProduct); + + if (class_driver == NULL) { + USB_LOG_ERR("Do not support Class:0x%02x, Subclass:0x%02x, Protocl:0x%02x on interface %u\r\n", + intf_desc->bInterfaceClass, + intf_desc->bInterfaceSubClass, + intf_desc->bInterfaceProtocol, + i); + hport->bus->event_handler(hport->bus->busid, hport->parent->index, hport->port, i, USBH_EVENT_INTERFACE_UNSUPPORTED); + continue; + } + hport->config.intf[i].class_driver = class_driver; + USB_LOG_INFO("Loading %s class driver on interface %u\r\n", class_driver->driver_name, i); + ret = CLASS_CONNECT(hport, i); + if (ret >= 0) { + hport->bus->event_handler(hport->bus->busid, hport->parent->index, hport->port, i, USBH_EVENT_INTERFACE_START); + } + } + +errout: + if (hport->raw_config_desc) { + usb_osal_free(hport->raw_config_desc); + hport->raw_config_desc = NULL; + } + return ret; +} + +void usbh_hubport_release(struct usbh_hubport *hport) +{ + if (hport->connected) { + hport->connected = false; + usbh_kill_urb(&hport->ep0_urb); + usbh_free_devaddr(hport); + for (uint8_t i = 0; i < hport->config.config_desc.bNumInterfaces; i++) { + if (hport->config.intf[i].class_driver && hport->config.intf[i].class_driver->disconnect) { + CLASS_DISCONNECT(hport, i); + } + hport->bus->event_handler(hport->bus->busid, hport->parent->index, hport->port, i, USBH_EVENT_INTERFACE_STOP); + } + hport->config.config_desc.bNumInterfaces = 0; + usb_osal_mutex_take(hport->mutex); + usb_osal_mutex_delete(hport->mutex); + USB_LOG_INFO("Device on Bus %u, Hub %u, Port %u disconnected\r\n", hport->bus->busid, hport->parent->index, hport->port); + hport->bus->event_handler(hport->bus->busid, hport->parent->index, hport->port, USB_INTERFACE_ANY, USBH_EVENT_DEVICE_DISCONNECTED); + } +} + +static void usbh_bus_init(struct usbh_bus *bus, uint8_t busid, uintptr_t reg_base) +{ + memset(bus, 0, sizeof(struct usbh_bus)); + bus->busid = busid; + bus->hcd.hcd_id = busid; + bus->hcd.reg_base = reg_base; + + /* devaddr 1 is for roothub */ + bus->devgen.last = 0x7f; + + usb_slist_add_tail(&g_bus_head, &bus->list); +} + +int usbh_initialize(uint8_t busid, uintptr_t reg_base, usbh_event_handler_t event_handler) +{ + struct usbh_bus *bus; + + USB_ASSERT_MSG(busid < CONFIG_USBHOST_MAX_BUS, "bus overflow\r\n"); + + bus = &g_usbhost_bus[busid]; + + usbh_bus_init(bus, busid, reg_base); + + if (event_handler) { + bus->event_handler = event_handler; + } else { + bus->event_handler = dummy_event_handler; + } + +#ifdef __ARMCC_VERSION /* ARM C Compiler */ + extern const int usbh_class_info$$Base; + extern const int usbh_class_info$$Limit; + usbh_class_info_table_begin = (struct usbh_class_info *)&usbh_class_info$$Base; + usbh_class_info_table_end = (struct usbh_class_info *)&usbh_class_info$$Limit; +#elif defined(__GNUC__) + extern uint32_t __usbh_class_info_start__; + extern uint32_t __usbh_class_info_end__; + usbh_class_info_table_begin = (struct usbh_class_info *)&__usbh_class_info_start__; + usbh_class_info_table_end = (struct usbh_class_info *)&__usbh_class_info_end__; +#elif defined(__ICCARM__) || defined(__ICCRX__) || defined(__ICCRISCV__) + usbh_class_info_table_begin = (struct usbh_class_info *)__section_begin(".usbh_class_info"); + usbh_class_info_table_end = (struct usbh_class_info *)__section_end(".usbh_class_info"); +#endif + usbh_hub_initialize(bus); + return 0; +} + +int usbh_deinitialize(uint8_t busid) +{ + struct usbh_bus *bus; + + USB_ASSERT_MSG(busid < CONFIG_USBHOST_MAX_BUS, "bus overflow\r\n"); + + bus = &g_usbhost_bus[busid]; + + usbh_hub_deinitialize(bus); + + usb_slist_remove(&g_bus_head, &bus->list); + + return 0; +} + +int usbh_control_transfer(struct usbh_hubport *hport, struct usb_setup_packet *setup, uint8_t *buffer) +{ + struct usbh_urb *urb; + volatile uint8_t retry = 3; + int ret; + + if (!hport || !setup) { + return -USB_ERR_INVAL; + } + + if (!hport->connected) { + return -USB_ERR_NODEV; + } + + urb = &hport->ep0_urb; + + usb_osal_mutex_take(hport->mutex); + + usbh_print_setup(setup); + +resubmit: + usbh_control_urb_fill(urb, hport, setup, buffer, setup->wLength, CONFIG_USBHOST_CONTROL_TRANSFER_TIMEOUT, NULL, NULL); + ret = usbh_submit_urb(urb); + if (ret == 0) { + ret = urb->actual_length; + } + + if (ret < 0 && (ret != -USB_ERR_TIMEOUT)) { + retry--; + if (retry > 0) { + USB_LOG_WRN("Control transfer failed, errorcode %d, retrying...\r\n", ret); + goto resubmit; + } + } + + usb_osal_mutex_give(hport->mutex); + return ret; +} + +int usbh_get_string_desc(struct usbh_hubport *hport, uint8_t index, uint8_t *output, uint16_t output_len) +{ + struct usb_setup_packet *setup = hport->setup; + int ret; + uint8_t *src; + uint8_t *dst; + uint16_t len; + uint16_t i = 2; + uint16_t j = 0; + + /* Get Manufacturer string */ + setup->bmRequestType = USB_REQUEST_DIR_IN | USB_REQUEST_STANDARD | USB_REQUEST_RECIPIENT_DEVICE; + setup->bRequest = USB_REQUEST_GET_DESCRIPTOR; + setup->wValue = (uint16_t)((USB_DESCRIPTOR_TYPE_STRING << 8) | index); + setup->wIndex = 0x0409; + setup->wLength = 255; + + ret = usbh_control_transfer(hport, setup, ep0_request_buffer[hport->bus->busid]); + if (ret < 0) { + return ret; + } + + src = ep0_request_buffer[hport->bus->busid]; + dst = output; + len = src[0]; + + if (((len - 2) / 2) > output_len) { + return -USB_ERR_NOMEM; + } + + while (i < len) { + dst[j] = src[i]; + i += 2; + j++; + } + + return 0; +} + +int usbh_set_interface(struct usbh_hubport *hport, uint8_t intf, uint8_t altsetting) +{ + struct usb_setup_packet *setup = hport->setup; + + setup->bmRequestType = USB_REQUEST_DIR_OUT | USB_REQUEST_STANDARD | USB_REQUEST_RECIPIENT_INTERFACE; + setup->bRequest = USB_REQUEST_SET_INTERFACE; + setup->wValue = altsetting; + setup->wIndex = intf; + setup->wLength = 0; + + return usbh_control_transfer(hport, setup, NULL); +} + +static void *usbh_list_all_interface_name(struct usbh_hub *hub, const char *devname) +{ + struct usbh_hubport *hport; + struct usbh_hub *hub_next; + void *priv; + + for (uint8_t port = 0; port < hub->nports; port++) { + hport = &hub->child[port]; + if (hport->connected) { + for (uint8_t itf = 0; itf < hport->config.config_desc.bNumInterfaces; itf++) { + if (hport->config.intf[itf].class_driver && hport->config.intf[itf].class_driver->driver_name) { + if ((strncmp(hport->config.intf[itf].devname, devname, CONFIG_USBHOST_DEV_NAMELEN) == 0) && hport->config.intf[itf].priv) + return hport->config.intf[itf].priv; + + if (strcmp(hport->config.intf[itf].class_driver->driver_name, "hub") == 0) { + hub_next = hport->config.intf[itf].priv; + + if (hub_next && hub_next->connected) { + priv = usbh_list_all_interface_name(hub_next, devname); + if (priv) { + return priv; + } + } + } + } + } + } + } + return NULL; +} + +static struct usbh_hubport *usbh_list_all_hubport(struct usbh_hub *hub, uint8_t hub_index, uint8_t hub_port) +{ + struct usbh_hubport *hport; + struct usbh_hub *hub_next; + + if (hub->index == hub_index) { + hport = &hub->child[hub_port - 1]; + if (hport->connected) { + return hport; + } else { + return NULL; + } + } else { + for (uint8_t port = 0; port < hub->nports; port++) { + hport = &hub->child[port]; + if (hport->connected) { + for (uint8_t itf = 0; itf < hport->config.config_desc.bNumInterfaces; itf++) { + if (hport->config.intf[itf].class_driver && hport->config.intf[itf].class_driver->driver_name) { + if (strcmp(hport->config.intf[itf].class_driver->driver_name, "hub") == 0) { + hub_next = hport->config.intf[itf].priv; + + if (hub_next && hub_next->connected) { + hport = usbh_list_all_hubport(hub_next, hub_index, hub_port); + if (hport) { + return hport; + } + } + } + } + } + } + } + } + return NULL; +} + +void *usbh_find_class_instance(const char *devname) +{ + usb_slist_t *bus_list; + struct usbh_hub *hub; + struct usbh_bus *bus; + void *priv; + size_t flags; + + flags = usb_osal_enter_critical_section(); + usb_slist_for_each(bus_list, &g_bus_head) + { + bus = usb_slist_entry(bus_list, struct usbh_bus, list); + hub = &bus->hcd.roothub; + + priv = usbh_list_all_interface_name(hub, devname); + if (priv) { + usb_osal_leave_critical_section(flags); + return priv; + } + } + usb_osal_leave_critical_section(flags); + return NULL; +} + +struct usbh_hubport *usbh_find_hubport(uint8_t busid, uint8_t hub_index, uint8_t hub_port) +{ + struct usbh_hub *hub; + struct usbh_bus *bus; + struct usbh_hubport *hport; + size_t flags; + + flags = usb_osal_enter_critical_section(); + + bus = &g_usbhost_bus[busid]; + hub = &bus->hcd.roothub; + + hport = usbh_list_all_hubport(hub, hub_index, hub_port); + usb_osal_leave_critical_section(flags); + return hport; +} + +static void usbh_print_hubport_info(struct usbh_hubport *hport) +{ + USB_LOG_RAW("Device Descriptor:\r\n"); + USB_LOG_RAW(" bLength: 0x%02x \r\n", hport->device_desc.bLength); + USB_LOG_RAW(" bDescriptorType: 0x%02x \r\n", hport->device_desc.bDescriptorType); + USB_LOG_RAW(" bcdUSB: 0x%04x \r\n", hport->device_desc.bcdUSB); + USB_LOG_RAW(" bDeviceClass: 0x%02x \r\n", hport->device_desc.bDeviceClass); + USB_LOG_RAW(" bDeviceSubClass: 0x%02x \r\n", hport->device_desc.bDeviceSubClass); + USB_LOG_RAW(" bDeviceProtocol: 0x%02x \r\n", hport->device_desc.bDeviceProtocol); + USB_LOG_RAW(" bMaxPacketSize0: 0x%02x \r\n", hport->device_desc.bMaxPacketSize0); + USB_LOG_RAW(" idVendor: 0x%04x \r\n", hport->device_desc.idVendor); + USB_LOG_RAW(" idProduct: 0x%04x \r\n", hport->device_desc.idProduct); + USB_LOG_RAW(" bcdDevice: 0x%04x \r\n", hport->device_desc.bcdDevice); + USB_LOG_RAW(" iManufacturer: 0x%02x \r\n", hport->device_desc.iManufacturer); + USB_LOG_RAW(" iProduct: 0x%02x \r\n", hport->device_desc.iProduct); + USB_LOG_RAW(" iSerialNumber: 0x%02x \r\n", hport->device_desc.iSerialNumber); + USB_LOG_RAW(" bNumConfigurations: 0x%02x\r\n", hport->device_desc.bNumConfigurations); + + USB_LOG_RAW(" Config Descriptor:\r\n"); + USB_LOG_RAW(" bLength: 0x%02x \r\n", hport->config.config_desc.bLength); + USB_LOG_RAW(" bDescriptorType: 0x%02x \r\n", hport->config.config_desc.bDescriptorType); + USB_LOG_RAW(" wTotalLength: 0x%04x \r\n", hport->config.config_desc.wTotalLength); + USB_LOG_RAW(" bNumInterfaces: 0x%02x \r\n", hport->config.config_desc.bNumInterfaces); + USB_LOG_RAW(" bConfigurationValue: 0x%02x \r\n", hport->config.config_desc.bConfigurationValue); + USB_LOG_RAW(" iConfiguration: 0x%02x \r\n", hport->config.config_desc.iConfiguration); + USB_LOG_RAW(" bmAttributes: 0x%02x \r\n", hport->config.config_desc.bmAttributes); + USB_LOG_RAW(" bMaxPower: 0x%02x \r\n", hport->config.config_desc.bMaxPower); + + for (uint8_t i = 0; i < hport->config.config_desc.bNumInterfaces; i++) { + for (uint8_t j = 0; j < hport->config.intf[i].altsetting_num; j++) { + USB_LOG_RAW(" Interface Descriptor:\r\n"); + USB_LOG_RAW(" bLength: 0x%02x \r\n", hport->config.intf[i].altsetting[j].intf_desc.bLength); + USB_LOG_RAW(" bDescriptorType: 0x%02x \r\n", hport->config.intf[i].altsetting[j].intf_desc.bDescriptorType); + USB_LOG_RAW(" bInterfaceNumber: 0x%02x \r\n", hport->config.intf[i].altsetting[j].intf_desc.bInterfaceNumber); + USB_LOG_RAW(" bAlternateSetting: 0x%02x \r\n", hport->config.intf[i].altsetting[j].intf_desc.bAlternateSetting); + USB_LOG_RAW(" bNumEndpoints: 0x%02x \r\n", hport->config.intf[i].altsetting[j].intf_desc.bNumEndpoints); + USB_LOG_RAW(" bInterfaceClass: 0x%02x \r\n", hport->config.intf[i].altsetting[j].intf_desc.bInterfaceClass); + USB_LOG_RAW(" bInterfaceSubClass: 0x%02x \r\n", hport->config.intf[i].altsetting[j].intf_desc.bInterfaceSubClass); + USB_LOG_RAW(" bInterfaceProtocol: 0x%02x \r\n", hport->config.intf[i].altsetting[j].intf_desc.bInterfaceProtocol); + USB_LOG_RAW(" iInterface: 0x%02x \r\n", hport->config.intf[i].altsetting[j].intf_desc.iInterface); + + for (uint8_t k = 0; k < hport->config.intf[i].altsetting[j].intf_desc.bNumEndpoints; k++) { + USB_LOG_RAW(" Endpoint Descriptor:\r\n"); + USB_LOG_RAW(" bLength: 0x%02x \r\n", hport->config.intf[i].altsetting[j].ep[k].ep_desc.bLength); + USB_LOG_RAW(" bDescriptorType: 0x%02x \r\n", hport->config.intf[i].altsetting[j].ep[k].ep_desc.bDescriptorType); + USB_LOG_RAW(" bEndpointAddress: 0x%02x \r\n", hport->config.intf[i].altsetting[j].ep[k].ep_desc.bEndpointAddress); + USB_LOG_RAW(" bmAttributes: 0x%02x \r\n", hport->config.intf[i].altsetting[j].ep[k].ep_desc.bmAttributes); + USB_LOG_RAW(" wMaxPacketSize: 0x%04x \r\n", hport->config.intf[i].altsetting[j].ep[k].ep_desc.wMaxPacketSize); + USB_LOG_RAW(" bInterval: 0x%02x \r\n", hport->config.intf[i].altsetting[j].ep[k].ep_desc.bInterval); + } + } + } +} + +static void usbh_list_device(struct usbh_hub *hub, bool astree, bool verbose, int dev_addr, int vid, int pid) +{ + static const char *speed_table[] = { + "UNKNOWN", + "low-speed", + "full-speed", + "high-speed", + "wireless", + "super-speed", + "super-speed-plus", + }; + + static const char *root_speed_table[] = { + "UNKNOWN", + "1.1", + "1.1", + "2.0", + "2.5", + "3.0", + "3.0", + }; + + static const uint16_t speed_baud[] = { + 0, + 12, + 12, + 480, + 480, + 5000, + 10000, + }; + + struct usbh_bus *bus; + struct usbh_hubport *hport; + struct usbh_hub *hub_next; + + uint8_t imbuf[64]; + uint8_t ipbuf[64]; + + const char *pimstr; + const char *pipstr; + + bool imvalid = false; + bool ipvalid = false; + + int ret; + + bus = hub->bus; + + (void)speed_table; + + if (hub->is_roothub) { + if (astree) { + USB_LOG_RAW("/: Bus %02u.Port 1: Dev %u, Class=root_hub, Driver=hcd, %uM\r\n", + bus->busid, hub->hub_addr, speed_baud[hub->speed]); + + } else { + if ((dev_addr < 0) || (hub->hub_addr == dev_addr)) { + if (((vid < 0) || (vid == 0xffff)) && ((pid < 0) || (pid == 0xffff))) { + USB_LOG_RAW("Bus %03u Device %03u: ID %04x:%04x %s %s root hub\r\n", + bus->busid, hub->hub_addr, 0xffff, 0xffff, + "Cherry-Embedded", root_speed_table[hub->speed]); + } + } + } + } + + for (uint8_t port = 0; port < hub->nports; port++) { + hport = &hub->child[port]; + if (hport->connected) { + ret = 0; + if (hport->device_desc.iManufacturer) { + memset(imbuf, 0, sizeof(imbuf)); + ret = usbh_get_string_desc(hport, hport->device_desc.iManufacturer, imbuf, sizeof(imbuf)); + if (ret == 0) { + imvalid = true; + } + } + + if (hport->device_desc.iProduct) { + memset(ipbuf, 0, sizeof(ipbuf)); + ret = usbh_get_string_desc(hport, hport->device_desc.iProduct, ipbuf, sizeof(ipbuf)); + if (ret == 0) { + ipvalid = true; + } + } + + if (imvalid) { + pimstr = (const char *)imbuf; + } else { + pimstr = "Not specified Manufacturer"; + } + + if (ipvalid) { + pipstr = (const char *)ipbuf; + } else { + pipstr = "Not specified Product"; + } + + if (!astree) { + if ((dev_addr < 0) || (hport->dev_addr == dev_addr)) { + if (((vid < 0) || (vid == hport->device_desc.idVendor)) && ((pid < 0) || (pid == hport->device_desc.idProduct))) { + USB_LOG_RAW("Bus %03u Device %03u: ID %04x:%04x %s %s\r\n", + bus->busid, hport->dev_addr, hport->device_desc.idVendor, hport->device_desc.idProduct, + pimstr, pipstr); + + if (verbose) { + usbh_print_hubport_info(hport); + } + } + } + } + + for (uint8_t intf = 0; intf < hport->config.config_desc.bNumInterfaces; intf++) { + if (hport->config.intf[intf].class_driver && hport->config.intf[intf].class_driver->driver_name) { + if (astree) { + for (uint8_t j = 0; j < hub->index; j++) { + USB_LOG_RAW(" "); + } + + USB_LOG_RAW("|__ Port %u: Dev %u, If %u, ClassDriver=%s, %uM\r\n", + hport->port, hport->dev_addr, intf, hport->config.intf[intf].class_driver->driver_name, speed_baud[hport->speed]); + } + + if (!strcmp(hport->config.intf[intf].class_driver->driver_name, "hub")) { + hub_next = hport->config.intf[intf].priv; + + if (hub_next && hub_next->connected) { + usbh_list_device(hub_next, astree, verbose, dev_addr, vid, pid); + } + } + } else if (astree) { + for (uint8_t j = 0; j < hub->index; j++) { + USB_LOG_RAW(" "); + } + + USB_LOG_RAW("|__ Port %u: Dev %u, If 0 ClassDriver=none, %uM\r\n", + hport->port, hport->dev_addr, speed_baud[hport->speed]); + } + } + } + } +} + +void lsusb_help(void) +{ + USB_LOG_RAW("List USB Devices\r\n" + "Usage: lsusb [options]...\r\n" + "\r\n" + "-v, --verbose\r\n" + " - increase verbosity (show descriptors)\r\n" + "-s [[bus]:][dev_addr]\r\n" + " - show only devices with specified device and/or\r\n" + " bus numbers (in decimal)\r\n" + "-d vendor:[product]\r\n" + " - show only devices with the specified vendor and\r\n" + " product ID numbers (in hexadecimal)\r\n" + "-t, --tree\r\n" + " - dump the physical USB device hierarchy as a tree\r\n" + "-V, --version\r\n" + " - show version of the cherryusb\r\n" + "-h, --help\r\n" + " - show usage and help information\r\n"); +} + +int lsusb(int argc, char **argv) +{ + usb_slist_t *bus_list; + struct usbh_bus *bus; + + int busid = -1; + int dev_addr = -1; + int vid = -1; + int pid = -1; + bool astree = false; + bool verbose = false; + + if (argc < 2) { + lsusb_help(); + return 0; + } + + while (argc > 1) { + argc--; + argv++; + + if (!strcmp(*argv, "-V") || !strcmp(*argv, "--version")) { + USB_LOG_RAW("CherryUSB version %s\r\n", CHERRYUSB_VERSION_STR); + return 0; + } else if (!strcmp(*argv, "-h") || !strcmp(*argv, "--help")) { + lsusb_help(); + return 0; + } else if (!strcmp(*argv, "-v") || !strcmp(*argv, "--verbose")) { + verbose = true; + } else if (!strcmp(*argv, "-t") || !strcmp(*argv, "--tree")) { + astree = true; + } else if (!strcmp(*argv, "-s")) { + if (argc > 1) { + argc--; + argv++; + + if (*argv[0] == '-') { + continue; + } + + char *endptr; + const char *colon = strchr(*argv, ':'); + (void)endptr; + + if (colon != NULL) { + const char *str; + if (colon > *argv) { + busid = strtol(*argv, &endptr, 10); + } + str = colon + 1; + if (*str != '\0') { + dev_addr = strtol(str, &endptr, 10); + if (dev_addr <= 0 || dev_addr >= 128) { + dev_addr = -1; + } + } + } else { + dev_addr = strtol(*argv, &endptr, 10); + if (dev_addr <= 0 || dev_addr >= 128) { + dev_addr = -1; + } + } + } + } else if (!strcmp(*argv, "-d")) { + if (argc > 1) { + argc--; + argv++; + + if (*argv[0] == '-') { + continue; + } + + char *endptr; + const char *colon = strchr(*argv, ':'); + (void)endptr; + + if (colon == NULL) { + continue; + } + const char *str; + + vid = strtol(*argv, &endptr, 16); + if (vid < 0 || vid > 0xffff) { + vid = -1; + continue; + } + str = colon + 1; + if (*str != '\0') { + pid = strtol(str, &endptr, 16); + if (pid < 0 || pid > 0xffff) { + pid = -1; + } + } + } + } + } + + if (astree) { + busid = -1; + dev_addr = -1; + vid = -1; + pid = -1; + verbose = false; + } + + usb_slist_for_each(bus_list, &g_bus_head) + { + bus = usb_slist_entry(bus_list, struct usbh_bus, list); + if (busid >= 0) { + if (bus->busid != busid) { + continue; + } + } + + usbh_list_device(&bus->hcd.roothub, astree, verbose, dev_addr, vid, pid); + } + + return 0; +} + +__WEAK uint8_t usbh_get_hport_active_config_index(struct usbh_hubport *hport) +{ + ARG_UNUSED(hport); + + return 0; // Default to configuration index 0 +} diff --git a/kernel/cherryusb/core/usbh_core.h b/kernel/cherryusb/core/usbh_core.h new file mode 100644 index 0000000..abd193d --- /dev/null +++ b/kernel/cherryusb/core/usbh_core.h @@ -0,0 +1,326 @@ +/* + * Copyright (c) 2022, sakumisu + * + * SPDX-License-Identifier: Apache-2.0 + */ +#ifndef USBH_CORE_H +#define USBH_CORE_H + +#include +#include +#include +#include + +#include "usb_config.h" +#include "usb_util.h" +#include "usb_errno.h" +#include "usb_def.h" +#include "usb_list.h" +#include "usb_log.h" +#include "usb_hc.h" +#include "usb_osal.h" +#include "usbh_hub.h" +#include "usb_memcpy.h" +#include "usb_ringbuffer.h" +#include "usb_mempool.h" +#include "usb_dcache.h" +#include "usb_version.h" + +#ifdef __cplusplus +extern "C" { +#endif + +enum usbh_event_type { + /* USB HCD IRQ */ + USBH_EVENT_ERROR, + USBH_EVENT_SOF, + + /* USB DEVICE STATUS */ + USBH_EVENT_DEVICE_RESET, + USBH_EVENT_DEVICE_CONNECTED, + USBH_EVENT_DEVICE_DISCONNECTED, + USBH_EVENT_DEVICE_CONFIGURED, + USBH_EVENT_DEVICE_WAKEUP, + USBH_EVENT_DEVICE_SUSPEND, + USBH_EVENT_DEVICE_RESUME, + + /* USB DEVICE INTERFACE STATUS */ + USBH_EVENT_INTERFACE_UNSUPPORTED, + USBH_EVENT_INTERFACE_START, + USBH_EVENT_INTERFACE_STOP, + + /* USB FRAMEWORK STATUS */ + USBH_EVENT_INIT, + USBH_EVENT_DEINIT, + USBH_EVENT_UNKNOWN, +}; + +#define USB_HUB_PORT_ANY 0 +#define USB_HUB_INDEX_ANY 0 +#define USB_INTERFACE_ANY 0xff + +#define USB_CLASS_MATCH_VENDOR 0x0001 +#define USB_CLASS_MATCH_PRODUCT 0x0002 +#define USB_CLASS_MATCH_INTF_CLASS 0x0004 +#define USB_CLASS_MATCH_INTF_SUBCLASS 0x0008 +#define USB_CLASS_MATCH_INTF_PROTOCOL 0x0010 +#define USB_CLASS_MATCH_INTF_NUM 0x0020 +#define USB_CLASS_MATCH_VID_PID (USB_CLASS_MATCH_VENDOR | USB_CLASS_MATCH_PRODUCT) + +#define CLASS_CONNECT(hport, i) ((hport)->config.intf[i].class_driver->connect(hport, i)) +#define CLASS_DISCONNECT(hport, i) ((hport)->config.intf[i].class_driver->disconnect(hport, i)) + +#ifdef __ARMCC_VERSION /* ARM C Compiler */ +#define CLASS_INFO_DEFINE __attribute__((section("usbh_class_info"))) __USED __ALIGNED(1) +#elif defined(__GNUC__) +#define CLASS_INFO_DEFINE __attribute__((section(".usbh_class_info"))) __USED __ALIGNED(1) +#elif defined(__ICCARM__) || defined(__ICCRX__) || defined(__ICCRISCV__) +#pragma section = ".usbh_class_info" +#define CLASS_INFO_DEFINE __attribute__((section(".usbh_class_info"))) __USED __ALIGNED(1) +#endif + +#define USBH_GET_URB_INTERVAL(interval, speed) (speed < USB_SPEED_HIGH ? (interval * 1000) : ((1 << (interval - 1)) * 125)) + +#define USBH_EP_INIT(ep, ep_desc) \ + do { \ + ep = ep_desc; \ + USB_LOG_INFO("Ep=%02x Attr=%02u Mps=%d Interval=%02u Mult=%02u\r\n", \ + ep_desc->bEndpointAddress, \ + ep_desc->bmAttributes, \ + USB_GET_MAXPACKETSIZE(ep_desc->wMaxPacketSize), \ + ep_desc->bInterval, \ + USB_GET_MULT(ep_desc->wMaxPacketSize)); \ + } while (0) + +typedef void (*usbh_event_handler_t)(uint8_t busid, uint8_t hub_index, uint8_t hub_port, uint8_t intf, uint8_t event); + +struct usbh_class_info { + uint8_t match_flags; /* Used for product specific matches; range is inclusive */ + uint8_t bInterfaceClass; /* Base device class code */ + uint8_t bInterfaceSubClass; /* Sub-class, depends on base class. Eg. */ + uint8_t bInterfaceProtocol; /* Protocol, depends on base class. Eg. */ + uint8_t bInterfaceNumber; /* Interface number */ + const uint16_t (*id_table)[2]; /* List of Vendor/Product ID pairs */ + const struct usbh_class_driver *class_driver; +}; + +struct usbh_hubport; +struct usbh_class_driver { + const char *driver_name; + int (*connect)(struct usbh_hubport *hport, uint8_t intf); + int (*disconnect)(struct usbh_hubport *hport, uint8_t intf); +}; + +struct usbh_endpoint { + struct usb_endpoint_descriptor ep_desc; +}; + +struct usbh_interface_altsetting { + struct usb_interface_descriptor intf_desc; + struct usbh_endpoint ep[CONFIG_USBHOST_MAX_ENDPOINTS]; +}; + +struct usbh_interface { + char devname[CONFIG_USBHOST_DEV_NAMELEN]; + struct usbh_class_driver *class_driver; + void *priv; + struct usbh_interface_altsetting altsetting[CONFIG_USBHOST_MAX_INTF_ALTSETTINGS]; + uint8_t altsetting_num; +}; + +struct usbh_configuration { + struct usb_configuration_descriptor config_desc; + struct usbh_interface intf[CONFIG_USBHOST_MAX_INTERFACES]; +}; + +struct usbh_hubport { + bool connected; /* True: device connected; false: disconnected */ + uint8_t port; /* Hub port index */ + uint8_t dev_addr; /* device address */ + uint8_t speed; /* device speed */ + uint8_t depth; /* distance from root hub */ + uint8_t route; /* route string */ + uint8_t slot_id; /* slot id */ + struct usb_device_descriptor device_desc; + struct usbh_configuration config; + const char *iManufacturer; + const char *iProduct; + const char *iSerialNumber; + uint8_t *raw_config_desc; + struct usb_setup_packet *setup; + struct usbh_hub *parent; + struct usbh_hub *self; /* if this hubport is a hub */ + struct usbh_bus *bus; + struct usb_endpoint_descriptor ep0; + struct usbh_urb ep0_urb; + usb_osal_mutex_t mutex; +}; + +struct usbh_hub { + bool connected; + bool is_roothub; + uint8_t index; + uint8_t hub_addr; + uint8_t speed; + uint8_t nports; + uint8_t powerdelay; + uint8_t tt_think; + bool ismtt; + struct usb_hub_descriptor hub_desc; /* USB 2.0 only */ + struct usb_hub_ss_descriptor hub_ss_desc; /* USB 3.0 only */ + struct usbh_hubport child[CONFIG_USBHOST_MAX_EHPORTS]; + struct usbh_hubport *parent; + struct usbh_bus *bus; + struct usb_endpoint_descriptor *intin; + struct usbh_urb intin_urb; + uint8_t *int_buffer; + struct usb_osal_timer *int_timer; +}; + +struct usbh_devaddr_map { + /** + * alloctab[0]:addr from 0~31 + * alloctab[1]:addr from 32~63 + * alloctab[2]:addr from 64~95 + * alloctab[3]:addr from 96~127 + * + */ + uint8_t last; /* Last device address */ + uint32_t alloctab[4]; /* Bit allocation table */ +}; + +struct usbh_hcd { + uintptr_t reg_base; + uint8_t hcd_id; + uint8_t roothub_intbuf[2]; /* at most 15 roothub ports */ + struct usbh_hub roothub; +}; + +struct usbh_bus { + usb_slist_t list; + uint8_t busid; + struct usbh_hcd hcd; + struct usbh_devaddr_map devgen; + usb_osal_thread_t hub_thread; + usb_osal_mq_t hub_mq; + usb_osal_sem_t hub_sem; + usbh_event_handler_t event_handler; +}; + +static inline void usbh_control_urb_fill(struct usbh_urb *urb, + struct usbh_hubport *hport, + struct usb_setup_packet *setup, + uint8_t *transfer_buffer, + uint32_t transfer_buffer_length, + uint32_t timeout, + usbh_complete_callback_t complete, + void *arg) +{ + urb->hport = hport; + urb->ep = &hport->ep0; + urb->setup = setup; + urb->transfer_buffer = transfer_buffer; + urb->transfer_buffer_length = transfer_buffer_length; + urb->timeout = timeout; + urb->complete = complete; + urb->arg = arg; +} + +static inline void usbh_bulk_urb_fill(struct usbh_urb *urb, + struct usbh_hubport *hport, + struct usb_endpoint_descriptor *ep, + uint8_t *transfer_buffer, + uint32_t transfer_buffer_length, + uint32_t timeout, + usbh_complete_callback_t complete, + void *arg) +{ + urb->hport = hport; + urb->ep = ep; + urb->setup = NULL; + urb->transfer_buffer = transfer_buffer; + urb->transfer_buffer_length = transfer_buffer_length; + urb->timeout = timeout; + urb->complete = complete; + urb->arg = arg; +} + +static inline void usbh_int_urb_fill(struct usbh_urb *urb, + struct usbh_hubport *hport, + struct usb_endpoint_descriptor *ep, + uint8_t *transfer_buffer, + uint32_t transfer_buffer_length, + uint32_t timeout, + usbh_complete_callback_t complete, + void *arg) +{ + urb->hport = hport; + urb->ep = ep; + urb->setup = NULL; + urb->transfer_buffer = transfer_buffer; + urb->transfer_buffer_length = transfer_buffer_length; + urb->timeout = timeout; + urb->complete = complete; + urb->arg = arg; + urb->interval = USBH_GET_URB_INTERVAL(ep->bInterval, hport->speed); +} + +extern struct usbh_bus g_usbhost_bus[]; +#ifdef USBH_IRQHandler +#error USBH_IRQHandler is obsolete, please call USBH_IRQHandler(xxx) in your irq +#endif + +/** + * @brief Submit an control transfer to an endpoint. + * This is a blocking method; this method will not return until the transfer has completed. + * Default timeout is 500ms. + * + * @param pipe The control endpoint to send/receive the control request. + * @param setup Setup packet to be sent. + * @param buffer buffer used for sending the request and for returning any responses. + * @return On success will return 0, and others indicate fail. + */ +int usbh_control_transfer(struct usbh_hubport *hport, struct usb_setup_packet *setup, uint8_t *buffer); + +/** + * @brief Retrieves a USB string descriptor from a specific hub port. + * + * This function is responsible for retrieving the USB string descriptor + * with the specified index from the USB device connected to the given hub port. + * The retrieved descriptor is stored in the output buffer provided. + * + * @param hport Pointer to the USB hub port structure. + * @param index Index of the string descriptor to retrieve. + * @param output Pointer to the buffer where the retrieved descriptor will be stored. + * @param output_len Length of the output buffer. + * @return On success will return 0, and others indicate fail. + */ +int usbh_get_string_desc(struct usbh_hubport *hport, uint8_t index, uint8_t *output, uint16_t output_len); + +/** + * @brief Sets the alternate setting for a USB interface on a specific hub port. + * + * This function is responsible for setting the alternate setting of the + * specified USB interface on the USB device connected to the given hub port. + * The interface and alternate setting are identified by the respective parameters. + * + * @param hport Pointer to the USB hub port structure. + * @param intf Interface number to set the alternate setting for. + * @param altsetting Alternate setting value to set for the interface. + * @return On success will return 0, and others indicate fail. + */ +int usbh_set_interface(struct usbh_hubport *hport, uint8_t intf, uint8_t altsetting); + +int usbh_initialize(uint8_t busid, uintptr_t reg_base, usbh_event_handler_t event_handler); +int usbh_deinitialize(uint8_t busid); +void *usbh_find_class_instance(const char *devname); +struct usbh_hubport *usbh_find_hubport(uint8_t busid, uint8_t hub_index, uint8_t hub_port); +uint8_t usbh_get_hport_active_config_index(struct usbh_hubport *hport); + +int lsusb(int argc, char **argv); + +#ifdef __cplusplus +} +#endif + +#endif /* USBH_CORE_H */ diff --git a/kernel/cherryusb/core/usbotg_core.c b/kernel/cherryusb/core/usbotg_core.c new file mode 100644 index 0000000..54237e6 --- /dev/null +++ b/kernel/cherryusb/core/usbotg_core.c @@ -0,0 +1,155 @@ +/* + * Copyright (c) 2025, sakumisu + * + * SPDX-License-Identifier: Apache-2.0 + */ +#include "usbotg_core.h" + +#ifdef CONFIG_USB_OTG_ENABLE +#undef USB_DBG_TAG +#define USB_DBG_TAG "usbotg_core" +#include "usb_log.h" + +#define CONFIG_USB_OTG_MAX_BUS CONFIG_USBHOST_MAX_BUS + +struct usbotg_core_priv { + uint8_t busid; + uint32_t reg_base; + bool usbh_initialized; + bool usbd_initialized; + usbd_event_handler_t device_event_callback; + usbh_event_handler_t host_event_callback; + uint8_t request_mode; + usb_osal_sem_t change_sem; + usb_osal_thread_t change_thread; +} g_usbotg_core[CONFIG_USB_OTG_MAX_BUS]; + +static void usbotg_host_initialize(uint8_t busid) +{ + if (g_usbotg_core[busid].usbh_initialized) { + return; + } + + if (g_usbotg_core[busid].usbd_initialized) { + usbd_deinitialize(busid); + g_usbotg_core[busid].usbd_initialized = false; + } + + USB_LOG_INFO("Switch to HOST mode\r\n"); + + g_usbotg_core[busid].usbh_initialized = true; + usbh_initialize(busid, g_usbotg_core[busid].reg_base, NULL); +} + +static void usbotg_device_initialize(uint8_t busid) +{ + if (g_usbotg_core[busid].usbd_initialized) { + return; + } + + if (g_usbotg_core[busid].usbh_initialized) { + usbh_deinitialize(busid); + g_usbotg_core[busid].usbh_initialized = false; + } + + USB_LOG_INFO("Switch to DEVICE mode\r\n"); + + g_usbotg_core[busid].usbd_initialized = true; + usbd_initialize(g_usbotg_core[busid].busid, g_usbotg_core[busid].reg_base, g_usbotg_core[busid].device_event_callback); +} + +static void usbotg_rolechange_thread(void *argument) +{ + uint8_t busid = (uint8_t)(uintptr_t)argument; + + usb_otg_init(busid); + + while (1) { + if (usb_osal_sem_take(g_usbotg_core[busid].change_sem, USB_OSAL_WAITING_FOREVER) == 0) { + if (g_usbotg_core[busid].request_mode == USBOTG_MODE_HOST) { + usbotg_host_initialize(busid); + } else if (g_usbotg_core[busid].request_mode == USBOTG_MODE_DEVICE) { + usbotg_device_initialize(busid); + } + } + } +} + +int usbotg_initialize(uint8_t busid, uint32_t reg_base, usbd_event_handler_t device_event_callback, usbh_event_handler_t host_event_callback, uint8_t default_role) +{ + char thread_name[32] = { 0 }; + + USB_ASSERT_MSG(busid < CONFIG_USB_OTG_MAX_BUS, "bus overflow\r\n"); + + g_usbotg_core[busid].busid = busid; + g_usbotg_core[busid].reg_base = reg_base; + g_usbotg_core[busid].device_event_callback = device_event_callback; + g_usbotg_core[busid].host_event_callback = host_event_callback; + + g_usbotg_core[busid].change_sem = usb_osal_sem_create(0); + if (g_usbotg_core[busid].change_sem == NULL) { + USB_LOG_ERR("Failed to create change_sem\r\n"); + while (1) { + } + } + + snprintf(thread_name, 32, "usbotg%u", busid); + g_usbotg_core[busid].change_thread = usb_osal_thread_create(thread_name, 2048, 10, usbotg_rolechange_thread, (void *)(uintptr_t)busid); + if (g_usbotg_core[busid].change_thread == NULL) { + USB_LOG_ERR("Failed to create usbotg thread\r\n"); + while (1) { + } + } + + usbotg_trigger_role_change(busid, default_role); + return 0; +} + +int usbotg_deinitialize(uint8_t busid) +{ + USB_ASSERT_MSG(busid < CONFIG_USB_OTG_MAX_BUS, "bus overflow\r\n"); + + if (g_usbotg_core[busid].usbd_initialized) { + usbd_deinitialize(busid); + g_usbotg_core[busid].usbd_initialized = false; + } + + if (g_usbotg_core[busid].usbh_initialized) { + usbh_deinitialize(busid); + g_usbotg_core[busid].usbh_initialized = false; + } + + if (g_usbotg_core[busid].change_thread) { + usb_osal_thread_delete(g_usbotg_core[busid].change_thread); + } + + if (g_usbotg_core[busid].change_sem) { + usb_otg_deinit(busid); + usb_osal_sem_delete(g_usbotg_core[busid].change_sem); + } + + return 0; +} + +void usbotg_trigger_role_change(uint8_t busid, uint8_t mode) +{ + USB_ASSERT_MSG(busid < CONFIG_USB_OTG_MAX_BUS, "bus overflow\r\n"); + + g_usbotg_core[busid].request_mode = mode; + + if (g_usbotg_core[busid].change_sem) { + usb_osal_sem_give(g_usbotg_core[busid].change_sem); + } +} + +void USBOTG_IRQHandler(uint8_t busid) +{ + USB_ASSERT_MSG(busid < CONFIG_USB_OTG_MAX_BUS, "bus overflow\r\n"); + + if (g_usbotg_core[busid].usbh_initialized) { + USBH_IRQHandler(busid); + } else if (g_usbotg_core[busid].usbd_initialized) { + USBD_IRQHandler(busid); + } +} +#endif /* CONFIG_USB_OTG_ENABLE */ \ No newline at end of file diff --git a/kernel/cherryusb/core/usbotg_core.h b/kernel/cherryusb/core/usbotg_core.h new file mode 100644 index 0000000..7eadb87 --- /dev/null +++ b/kernel/cherryusb/core/usbotg_core.h @@ -0,0 +1,27 @@ +/* + * Copyright (c) 2025, sakumisu + * + * SPDX-License-Identifier: Apache-2.0 + */ +#ifndef USBOTG_CORE_H +#define USBOTG_CORE_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include "usbd_core.h" +#include "usbh_core.h" +#include "usb_otg.h" + +int usbotg_initialize(uint8_t busid, uint32_t reg_base, usbd_event_handler_t device_event_callback, usbh_event_handler_t host_event_callback, uint8_t default_role); +int usbotg_deinitialize(uint8_t busid); + +/* called by user */ +void usbotg_trigger_role_change(uint8_t busid, uint8_t mode); + +#ifdef __cplusplus +} +#endif + +#endif /* USBOTG_CORE_H */ \ No newline at end of file diff --git a/kernel/cherryusb/osal/idf/linker.lf b/kernel/cherryusb/osal/idf/linker.lf new file mode 100644 index 0000000..24c8b27 --- /dev/null +++ b/kernel/cherryusb/osal/idf/linker.lf @@ -0,0 +1,13 @@ +[sections:usbh_class_info] +entries: + .usbh_class_info+ + +[scheme:usbh_class_info_array] +entries: + usbh_class_info -> flash_rodata + +[mapping:usbh_class_info_table] +archive: * +entries: + * (usbh_class_info_array); + usbh_class_info -> flash_rodata KEEP() SURROUND(usbh_class_info) \ No newline at end of file diff --git a/kernel/cherryusb/osal/idf/usb_config.h b/kernel/cherryusb/osal/idf/usb_config.h new file mode 100644 index 0000000..c443c12 --- /dev/null +++ b/kernel/cherryusb/osal/idf/usb_config.h @@ -0,0 +1,279 @@ +/* + * SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +#include "sdkconfig.h" +#include "esp_rom_sys.h" +#include "esp_attr.h" + +/* ================ USB common Configuration ================ */ + +#define CONFIG_USB_PRINTF(...) esp_rom_printf(__VA_ARGS__) + +#ifndef CONFIG_USB_DBG_LEVEL +#define CONFIG_USB_DBG_LEVEL USB_DBG_INFO +#endif + +/* Enable print with color */ +#define CONFIG_USB_PRINTF_COLOR_ENABLE + +/* data align size when use dma or use dcache */ +#ifndef CONFIG_USB_ALIGN_SIZE +#define CONFIG_USB_ALIGN_SIZE 4 +#endif + +// #define CONFIG_USB_DCACHE_ENABLE + +/* attribute data into no cache ram +* DRAM_DMA_ALIGNED_ATTR was introduced in IDF 5.3. If not defined, it falls back to DMA_ATTR +*/ +#ifndef DRAM_DMA_ALIGNED_ATTR +#define DRAM_DMA_ALIGNED_ATTR DMA_ATTR +#endif +#define USB_NOCACHE_RAM_SECTION DRAM_DMA_ALIGNED_ATTR + +/* use usb_memcpy default for high performance but cost more flash memory. + * And, arm libc has a bug that memcpy() may cause data misalignment when the size is not a multiple of 4. +*/ +// #define CONFIG_USB_MEMCPY_DISABLE + +/* ================= USB Device Stack Configuration ================ */ + +/* Ep0 in and out transfer buffer */ +#ifndef CONFIG_USBDEV_REQUEST_BUFFER_LEN +#define CONFIG_USBDEV_REQUEST_BUFFER_LEN 512 +#endif + +/* Setup packet log for debug */ +// #define CONFIG_USBDEV_SETUP_LOG_PRINT + +/* Send ep0 in data from user buffer instead of copying into ep0 reqdata + * Please note that user buffer must be aligned with CONFIG_USB_ALIGN_SIZE +*/ +// #define CONFIG_USBDEV_EP0_INDATA_NO_COPY + +/* Check if the input descriptor is correct */ +// #define CONFIG_USBDEV_DESC_CHECK + +/* Enable test mode */ +// #define CONFIG_USBDEV_TEST_MODE + +/* enable advance desc register api */ +#define CONFIG_USBDEV_ADVANCE_DESC + +/* move ep0 setup handler from isr to thread */ +// #define CONFIG_USBDEV_EP0_THREAD + +#ifndef CONFIG_USBDEV_EP0_PRIO +#define CONFIG_USBDEV_EP0_PRIO 4 +#endif + +#ifndef CONFIG_USBDEV_EP0_STACKSIZE +#define CONFIG_USBDEV_EP0_STACKSIZE 2048 +#endif + +#ifndef CONFIG_USBDEV_MSC_MAX_LUN +#define CONFIG_USBDEV_MSC_MAX_LUN 1 +#endif + +#ifndef CONFIG_USBDEV_MSC_MAX_BUFSIZE +#define CONFIG_USBDEV_MSC_MAX_BUFSIZE 512 +#endif + +#ifndef CONFIG_USBDEV_MSC_MANUFACTURER_STRING +#define CONFIG_USBDEV_MSC_MANUFACTURER_STRING "" +#endif + +#ifndef CONFIG_USBDEV_MSC_PRODUCT_STRING +#define CONFIG_USBDEV_MSC_PRODUCT_STRING "" +#endif + +#ifndef CONFIG_USBDEV_MSC_VERSION_STRING +#define CONFIG_USBDEV_MSC_VERSION_STRING "0.01" +#endif + +/* move msc read & write from isr to while(1), you should call usbd_msc_polling in while(1) */ +// #define CONFIG_USBDEV_MSC_POLLING + +/* move msc read & write from isr to thread */ +#define CONFIG_USBDEV_MSC_THREAD + +#ifndef CONFIG_USBDEV_MSC_PRIO +#define CONFIG_USBDEV_MSC_PRIO 4 +#endif + +#ifndef CONFIG_USBDEV_MSC_STACKSIZE +#define CONFIG_USBDEV_MSC_STACKSIZE 2048 +#endif + +#ifndef CONFIG_USBDEV_MTP_MAX_BUFSIZE +#define CONFIG_USBDEV_MTP_MAX_BUFSIZE 2048 +#endif + +#ifndef CONFIG_USBDEV_MTP_MAX_OBJECTS +#define CONFIG_USBDEV_MTP_MAX_OBJECTS 256 +#endif + +#ifndef CONFIG_USBDEV_MTP_MAX_PATHNAME +#define CONFIG_USBDEV_MTP_MAX_PATHNAME 256 +#endif + +#define CONFIG_USBDEV_MTP_THREAD + +#ifndef CONFIG_USBDEV_MTP_PRIO +#define CONFIG_USBDEV_MTP_PRIO 4 +#endif + +#ifndef CONFIG_USBDEV_MTP_STACKSIZE +#define CONFIG_USBDEV_MTP_STACKSIZE 4096 +#endif + +#ifndef CONFIG_USBDEV_RNDIS_RESP_BUFFER_SIZE +#define CONFIG_USBDEV_RNDIS_RESP_BUFFER_SIZE 156 +#endif + +/* rndis transfer buffer size, must be a multiple of (1536 + 44)*/ +#ifndef CONFIG_USBDEV_RNDIS_ETH_MAX_FRAME_SIZE +#define CONFIG_USBDEV_RNDIS_ETH_MAX_FRAME_SIZE 1580 +#endif + +#ifndef CONFIG_USBDEV_RNDIS_VENDOR_ID +#define CONFIG_USBDEV_RNDIS_VENDOR_ID 0x0000ffff +#endif + +#ifndef CONFIG_USBDEV_RNDIS_VENDOR_DESC +#define CONFIG_USBDEV_RNDIS_VENDOR_DESC "CherryUSB" +#endif + +/* ================ USB HOST Stack Configuration ================== */ + +#define CONFIG_USBHOST_MAX_RHPORTS 1 +#define CONFIG_USBHOST_MAX_EXTHUBS 1 +#define CONFIG_USBHOST_MAX_EHPORTS 4 +#define CONFIG_USBHOST_MAX_INTERFACES 8 +#define CONFIG_USBHOST_MAX_INTF_ALTSETTINGS 2 +#define CONFIG_USBHOST_MAX_ENDPOINTS 4 + +#define CONFIG_USBHOST_MAX_SERIAL_CLASS 4 +#define CONFIG_USBHOST_MAX_HID_CLASS 4 +#define CONFIG_USBHOST_MAX_MSC_CLASS 2 +#define CONFIG_USBHOST_MAX_AUDIO_CLASS 1 +#define CONFIG_USBHOST_MAX_VIDEO_CLASS 1 + +#define CONFIG_USBHOST_DEV_NAMELEN 16 + +#ifndef CONFIG_USBHOST_PSC_PRIO +#define CONFIG_USBHOST_PSC_PRIO 0 +#endif +#ifndef CONFIG_USBHOST_PSC_STACKSIZE +#define CONFIG_USBHOST_PSC_STACKSIZE 4096 +#endif + +//#define CONFIG_USBHOST_GET_STRING_DESC + +// #define CONFIG_USBHOST_MSOS_ENABLE +#ifndef CONFIG_USBHOST_MSOS_VENDOR_CODE +#define CONFIG_USBHOST_MSOS_VENDOR_CODE 0x00 +#endif + +/* Ep0 max transfer buffer */ +#ifndef CONFIG_USBHOST_REQUEST_BUFFER_LEN +#define CONFIG_USBHOST_REQUEST_BUFFER_LEN 2048 +#endif + +#ifndef CONFIG_USBHOST_CONTROL_TRANSFER_TIMEOUT +#define CONFIG_USBHOST_CONTROL_TRANSFER_TIMEOUT 500 +#endif + +#ifndef CONFIG_USBHOST_MSC_TIMEOUT +#define CONFIG_USBHOST_MSC_TIMEOUT 5000 +#endif + +#ifndef CONFIG_USBHOST_SERIAL_RX_SIZE +#define CONFIG_USBHOST_SERIAL_RX_SIZE 2048 +#endif + +/* This parameter affects usb performance, and depends on (TCP_WND)tcp eceive windows size, + * you can change to 2K ~ 16K and must be larger than TCP RX windows size in order to avoid being overflow. + */ +#ifndef CONFIG_USBHOST_RNDIS_ETH_MAX_RX_SIZE +#define CONFIG_USBHOST_RNDIS_ETH_MAX_RX_SIZE (2048) +#endif + +/* Because lwip do not support multi pbuf at a time, so increasing this variable has no performance improvement */ +#ifndef CONFIG_USBHOST_RNDIS_ETH_MAX_TX_SIZE +#define CONFIG_USBHOST_RNDIS_ETH_MAX_TX_SIZE (2048) +#endif + +/* This parameter affects usb performance, and depends on (TCP_WND)tcp eceive windows size, + * you can change to 2K ~ 16K and must be larger than TCP RX windows size in order to avoid being overflow. + */ +#ifndef CONFIG_USBHOST_CDC_NCM_ETH_MAX_RX_SIZE +#define CONFIG_USBHOST_CDC_NCM_ETH_MAX_RX_SIZE (2048) +#endif +/* Because lwip do not support multi pbuf at a time, so increasing this variable has no performance improvement */ +#ifndef CONFIG_USBHOST_CDC_NCM_ETH_MAX_TX_SIZE +#define CONFIG_USBHOST_CDC_NCM_ETH_MAX_TX_SIZE (2048) +#endif + +/* This parameter affects usb performance, and depends on (TCP_WND)tcp eceive windows size, + * you can change to 2K ~ 16K and must be larger than TCP RX windows size in order to avoid being overflow. + */ +#ifndef CONFIG_USBHOST_ASIX_ETH_MAX_RX_SIZE +#define CONFIG_USBHOST_ASIX_ETH_MAX_RX_SIZE (2048) +#endif +/* Because lwip do not support multi pbuf at a time, so increasing this variable has no performance improvement */ +#ifndef CONFIG_USBHOST_ASIX_ETH_MAX_TX_SIZE +#define CONFIG_USBHOST_ASIX_ETH_MAX_TX_SIZE (2048) +#endif + +/* This parameter affects usb performance, and depends on (TCP_WND)tcp eceive windows size, + * you can change to 2K ~ 16K and must be larger than TCP RX windows size in order to avoid being overflow. + */ +#ifndef CONFIG_USBHOST_RTL8152_ETH_MAX_RX_SIZE +#define CONFIG_USBHOST_RTL8152_ETH_MAX_RX_SIZE (2048) +#endif +/* Because lwip do not support multi pbuf at a time, so increasing this variable has no performance improvement */ +#ifndef CONFIG_USBHOST_RTL8152_ETH_MAX_TX_SIZE +#define CONFIG_USBHOST_RTL8152_ETH_MAX_TX_SIZE (2048) +#endif + +#define CONFIG_USBHOST_BLUETOOTH_HCI_H4 +// #define CONFIG_USBHOST_BLUETOOTH_HCI_LOG + +#ifndef CONFIG_USBHOST_BLUETOOTH_TX_SIZE +#define CONFIG_USBHOST_BLUETOOTH_TX_SIZE 2048 +#endif +#ifndef CONFIG_USBHOST_BLUETOOTH_RX_SIZE +#define CONFIG_USBHOST_BLUETOOTH_RX_SIZE 2048 +#endif + +#if CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3 +#define ESP_USB_FS0_BASE 0x60080000 +#define ESP_USBD_BASE ESP_USB_FS0_BASE +#define ESP_USBH_BASE ESP_USB_FS0_BASE +#define CONFIG_USBDEV_MAX_BUS 1 +#define CONFIG_USBHOST_MAX_BUS 1 +#elif CONFIG_IDF_TARGET_ESP32P4 +#define ESP_USB_HS0_BASE 0x50000000 +#define ESP_USB_FS0_BASE 0x50040000 +#define ESP_USBD_BASE ESP_USB_HS0_BASE +#define ESP_USBH_BASE ESP_USB_HS0_BASE +#define CONFIG_USBDEV_MAX_BUS 2 +#define CONFIG_USBHOST_MAX_BUS 2 +#define CONFIG_USB_HS +#else +#error "Unsupported SoC" +#endif + +#if CONFIG_IDF_TARGET_ESP32P4 +#define CONFIG_USB_DCACHE_ENABLE + +#undef CONFIG_USB_ALIGN_SIZE +#define CONFIG_USB_ALIGN_SIZE CONFIG_CACHE_L1_CACHE_LINE_SIZE + +#endif \ No newline at end of file diff --git a/kernel/cherryusb/osal/idf/usb_osal_idf.c b/kernel/cherryusb/osal/idf/usb_osal_idf.c new file mode 100644 index 0000000..69f734e --- /dev/null +++ b/kernel/cherryusb/osal/idf/usb_osal_idf.c @@ -0,0 +1,240 @@ +/* + * Copyright (c) 2022, sakumisu + * + * SPDX-License-Identifier: Apache-2.0 + */ +#include "usb_osal.h" +#include "usb_errno.h" +#include "freertos/FreeRTOS.h" +#include "freertos/semphr.h" +#include "freertos/timers.h" +#include "freertos/event_groups.h" +#include "esp_timer.h" + +static portMUX_TYPE spinlock = portMUX_INITIALIZER_UNLOCKED; + +usb_osal_thread_t usb_osal_thread_create(const char *name, uint32_t stack_size, uint32_t prio, usb_thread_entry_t entry, void *args) +{ + TaskHandle_t htask = NULL; + stack_size /= sizeof(StackType_t); + xTaskCreatePinnedToCore(entry, name, stack_size, args, configMAX_PRIORITIES - 1 - prio, &htask, CONFIG_ESP_TIMER_TASK_AFFINITY); + return (usb_osal_thread_t)htask; +} + +void usb_osal_thread_delete(usb_osal_thread_t thread) +{ + vTaskDelete(thread); +} + +void usb_osal_thread_schedule_other(void) +{ + TaskHandle_t xCurrentTask = xTaskGetCurrentTaskHandle(); + const UBaseType_t old_priority = uxTaskPriorityGet(xCurrentTask); + + vTaskPrioritySet(xCurrentTask, tskIDLE_PRIORITY); + + taskYIELD(); + + vTaskPrioritySet(xCurrentTask, old_priority); +} + +usb_osal_sem_t usb_osal_sem_create(uint32_t initial_count) +{ + return (usb_osal_sem_t)xSemaphoreCreateCounting(1, initial_count); +} + +usb_osal_sem_t usb_osal_sem_create_counting(uint32_t max_count) +{ + return (usb_osal_sem_t)xSemaphoreCreateCounting(0, max_count); +} + +void usb_osal_sem_delete(usb_osal_sem_t sem) +{ + vSemaphoreDelete((SemaphoreHandle_t)sem); +} + +int usb_osal_sem_take(usb_osal_sem_t sem, uint32_t timeout) +{ + if (timeout == USB_OSAL_WAITING_FOREVER) { + return (xSemaphoreTake((SemaphoreHandle_t)sem, portMAX_DELAY) == pdPASS) ? 0 : -USB_ERR_TIMEOUT; + } else { + return (xSemaphoreTake((SemaphoreHandle_t)sem, pdMS_TO_TICKS(timeout)) == pdPASS) ? 0 : -USB_ERR_TIMEOUT; + } +} + +int usb_osal_sem_give(usb_osal_sem_t sem) +{ + BaseType_t xHigherPriorityTaskWoken = pdFALSE; + int ret; + + if (xPortInIsrContext()) { + ret = xSemaphoreGiveFromISR((SemaphoreHandle_t)sem, &xHigherPriorityTaskWoken); + if (ret == pdPASS) { + portYIELD_FROM_ISR(xHigherPriorityTaskWoken); + } + } else { + ret = xSemaphoreGive((SemaphoreHandle_t)sem); + } + + return (ret == pdPASS) ? 0 : -USB_ERR_TIMEOUT; +} + +void usb_osal_sem_reset(usb_osal_sem_t sem) +{ + xQueueReset((QueueHandle_t)sem); +} + +usb_osal_mutex_t usb_osal_mutex_create(void) +{ + return (usb_osal_mutex_t)xSemaphoreCreateMutex(); +} + +void usb_osal_mutex_delete(usb_osal_mutex_t mutex) +{ + vSemaphoreDelete((SemaphoreHandle_t)mutex); +} + +int usb_osal_mutex_take(usb_osal_mutex_t mutex) +{ + return (xSemaphoreTake((SemaphoreHandle_t)mutex, portMAX_DELAY) == pdPASS) ? 0 : -USB_ERR_TIMEOUT; +} + +int usb_osal_mutex_give(usb_osal_mutex_t mutex) +{ + return (xSemaphoreGive((SemaphoreHandle_t)mutex) == pdPASS) ? 0 : -USB_ERR_TIMEOUT; +} + +usb_osal_mq_t usb_osal_mq_create(uint32_t max_msgs) +{ + return (usb_osal_mq_t)xQueueCreate(max_msgs, sizeof(uintptr_t)); +} + +void usb_osal_mq_delete(usb_osal_mq_t mq) +{ + vQueueDelete((QueueHandle_t)mq); +} + +int usb_osal_mq_send(usb_osal_mq_t mq, uintptr_t addr) +{ + BaseType_t xHigherPriorityTaskWoken = pdFALSE; + int ret; + + if (xPortInIsrContext()) { + ret = xQueueSendFromISR((usb_osal_mq_t)mq, &addr, &xHigherPriorityTaskWoken); + if (ret == pdPASS) { + portYIELD_FROM_ISR(xHigherPriorityTaskWoken); + } + } else { + ret = xQueueSend((usb_osal_mq_t)mq, &addr, 0xffffffff); + } + + return (ret == pdPASS) ? 0 : -USB_ERR_TIMEOUT; +} + +int usb_osal_mq_recv(usb_osal_mq_t mq, uintptr_t *addr, uint32_t timeout) +{ + BaseType_t xHigherPriorityTaskWoken = pdFALSE; + int ret; + + if (xPortInIsrContext()) { + ret = xQueueReceiveFromISR((usb_osal_mq_t)mq, addr, &xHigherPriorityTaskWoken); + if (ret == pdPASS) { + portYIELD_FROM_ISR(xHigherPriorityTaskWoken); + } + return (ret == pdPASS) ? 0 : -USB_ERR_TIMEOUT; + } else { + if (timeout == USB_OSAL_WAITING_FOREVER) { + return (xQueueReceive((usb_osal_mq_t)mq, addr, portMAX_DELAY) == pdPASS) ? 0 : -USB_ERR_TIMEOUT; + } else { + return (xQueueReceive((usb_osal_mq_t)mq, addr, pdMS_TO_TICKS(timeout)) == pdPASS) ? 0 : -USB_ERR_TIMEOUT; + } + } +} + +static void usb_timeout(void *arg) +{ + struct usb_osal_timer *timer = (struct usb_osal_timer *)arg; + + timer->handler(timer->argument); +} + +struct usb_osal_timer *usb_osal_timer_create(const char *name, uint32_t timeout_ms, usb_timer_handler_t handler, void *argument, bool is_period) +{ + struct usb_osal_timer *timer; + + timer = pvPortMalloc(sizeof(struct usb_osal_timer)); + + if (timer == NULL) { + return NULL; + } + + esp_timer_create_args_t timer_args = { + .callback = usb_timeout, + // argument specified here will be passed to timer callback function + .arg = (void *)timer, + .dispatch_method = ESP_TIMER_TASK, + .name = name, + .skip_unhandled_events = true + }; + + timer->handler = handler; + timer->argument = argument; + timer->is_period = is_period; + timer->timeout_ms = timeout_ms; + + if (esp_timer_create(&timer_args, (esp_timer_handle_t *)&timer->timer) != ESP_OK) { + vPortFree(timer); + return NULL; + } + + return timer; +} + +void usb_osal_timer_delete(struct usb_osal_timer *timer) +{ + esp_timer_stop((esp_timer_handle_t)timer->timer); + esp_timer_delete((esp_timer_handle_t)timer->timer); + vPortFree(timer); +} + +void usb_osal_timer_start(struct usb_osal_timer *timer) +{ + esp_timer_stop((esp_timer_handle_t)timer->timer); + + if (timer->is_period) { + esp_timer_start_periodic((esp_timer_handle_t)timer->timer, ((uint64_t)timer->timeout_ms) * 1000); + } else { + esp_timer_start_once((esp_timer_handle_t)timer->timer, ((uint64_t)timer->timeout_ms) * 1000); + } +} + +void usb_osal_timer_stop(struct usb_osal_timer *timer) +{ + esp_timer_stop((esp_timer_handle_t)timer->timer); +} + +size_t usb_osal_enter_critical_section(void) +{ + portENTER_CRITICAL_SAFE(&spinlock); + return 0; +} + +void usb_osal_leave_critical_section(size_t flag) +{ + portEXIT_CRITICAL_SAFE(&spinlock); +} + +void usb_osal_msleep(uint32_t delay) +{ + vTaskDelay(pdMS_TO_TICKS(delay)); +} + +void *usb_osal_malloc(size_t size) +{ + return malloc(size); +} + +void usb_osal_free(void *ptr) +{ + free(ptr); +} \ No newline at end of file diff --git a/kernel/cherryusb/osal/idf/usbh_class_info.ld b/kernel/cherryusb/osal/idf/usbh_class_info.ld new file mode 100644 index 0000000..117bfd8 --- /dev/null +++ b/kernel/cherryusb/osal/idf/usbh_class_info.ld @@ -0,0 +1,2 @@ +__usbh_class_info_start__ = _usbh_class_info_start; +__usbh_class_info_end__ = _usbh_class_info_end; \ No newline at end of file diff --git a/kernel/cherryusb/osal/usb_osal_freertos.c b/kernel/cherryusb/osal/usb_osal_freertos.c new file mode 100644 index 0000000..b30433c --- /dev/null +++ b/kernel/cherryusb/osal/usb_osal_freertos.c @@ -0,0 +1,272 @@ +/* + * Copyright (c) 2022, sakumisu + * + * SPDX-License-Identifier: Apache-2.0 + */ +#include "usb_osal.h" +#include "usb_errno.h" +#include "usb_config.h" +#include "usb_log.h" +#include +#include "semphr.h" +#include "timers.h" +#include "event_groups.h" + +usb_osal_thread_t usb_osal_thread_create(const char *name, uint32_t stack_size, uint32_t prio, usb_thread_entry_t entry, void *args) +{ + TaskHandle_t htask = NULL; + stack_size /= sizeof(StackType_t); + xTaskCreate(entry, name, stack_size, args, configMAX_PRIORITIES - 1 - prio, &htask); + if (htask == NULL) { + USB_LOG_ERR("Create thread %s failed\r\n", name); + while (1) { + } + } + return (usb_osal_thread_t)htask; +} + +void usb_osal_thread_delete(usb_osal_thread_t thread) +{ + vTaskDelete(thread); +} + +void usb_osal_thread_schedule_other(void) +{ + TaskHandle_t xCurrentTask = xTaskGetCurrentTaskHandle(); + const UBaseType_t old_priority = uxTaskPriorityGet(xCurrentTask); + + vTaskPrioritySet(xCurrentTask, tskIDLE_PRIORITY); + + taskYIELD(); + + vTaskPrioritySet(xCurrentTask, old_priority); +} + +usb_osal_sem_t usb_osal_sem_create(uint32_t initial_count) +{ + usb_osal_sem_t sem = (usb_osal_sem_t)xSemaphoreCreateCounting(1, initial_count); + if (sem == NULL) { + USB_LOG_ERR("Create semaphore failed\r\n"); + while (1) { + } + } + return sem; +} + +usb_osal_sem_t usb_osal_sem_create_counting(uint32_t max_count) +{ + usb_osal_sem_t sem = (usb_osal_sem_t)xSemaphoreCreateCounting(max_count, 0); + if (sem == NULL) { + USB_LOG_ERR("Create semaphore failed\r\n"); + while (1) { + } + } + return sem; +} + +void usb_osal_sem_delete(usb_osal_sem_t sem) +{ + vSemaphoreDelete((SemaphoreHandle_t)sem); +} + +int usb_osal_sem_take(usb_osal_sem_t sem, uint32_t timeout) +{ + if (timeout == USB_OSAL_WAITING_FOREVER) { + return (xSemaphoreTake((SemaphoreHandle_t)sem, portMAX_DELAY) == pdPASS) ? 0 : -USB_ERR_TIMEOUT; + } else { + return (xSemaphoreTake((SemaphoreHandle_t)sem, pdMS_TO_TICKS(timeout)) == pdPASS) ? 0 : -USB_ERR_TIMEOUT; + } +} + +int usb_osal_sem_give(usb_osal_sem_t sem) +{ + BaseType_t xHigherPriorityTaskWoken = pdFALSE; + int ret; + + if (xPortIsInsideInterrupt()) { + ret = xSemaphoreGiveFromISR((SemaphoreHandle_t)sem, &xHigherPriorityTaskWoken); + if (ret == pdPASS) { + portYIELD_FROM_ISR(xHigherPriorityTaskWoken); + } + } else { + ret = xSemaphoreGive((SemaphoreHandle_t)sem); + } + + return (ret == pdPASS) ? 0 : -USB_ERR_TIMEOUT; +} + +void usb_osal_sem_reset(usb_osal_sem_t sem) +{ + xQueueReset((QueueHandle_t)sem); +} + +usb_osal_mutex_t usb_osal_mutex_create(void) +{ + usb_osal_mutex_t mutex = (usb_osal_mutex_t)xSemaphoreCreateMutex(); + if (mutex == NULL) { + USB_LOG_ERR("Create mutex failed\r\n"); + while (1) { + } + } + return mutex; +} + +void usb_osal_mutex_delete(usb_osal_mutex_t mutex) +{ + vSemaphoreDelete((SemaphoreHandle_t)mutex); +} + +int usb_osal_mutex_take(usb_osal_mutex_t mutex) +{ + return (xSemaphoreTake((SemaphoreHandle_t)mutex, portMAX_DELAY) == pdPASS) ? 0 : -USB_ERR_TIMEOUT; +} + +int usb_osal_mutex_give(usb_osal_mutex_t mutex) +{ + return (xSemaphoreGive((SemaphoreHandle_t)mutex) == pdPASS) ? 0 : -USB_ERR_TIMEOUT; +} + +usb_osal_mq_t usb_osal_mq_create(uint32_t max_msgs) +{ + return (usb_osal_mq_t)xQueueCreate(max_msgs, sizeof(uintptr_t)); +} + +void usb_osal_mq_delete(usb_osal_mq_t mq) +{ + vQueueDelete((QueueHandle_t)mq); +} + +int usb_osal_mq_send(usb_osal_mq_t mq, uintptr_t addr) +{ + BaseType_t xHigherPriorityTaskWoken = pdFALSE; + int ret; + + if (xPortIsInsideInterrupt()) { + ret = xQueueSendFromISR((usb_osal_mq_t)mq, &addr, &xHigherPriorityTaskWoken); + if (ret == pdPASS) { + portYIELD_FROM_ISR(xHigherPriorityTaskWoken); + } + } else { + ret = xQueueSend((usb_osal_mq_t)mq, &addr, 0xffffffff); + } + + return (ret == pdPASS) ? 0 : -USB_ERR_TIMEOUT; +} + +int usb_osal_mq_recv(usb_osal_mq_t mq, uintptr_t *addr, uint32_t timeout) +{ + BaseType_t xHigherPriorityTaskWoken = pdFALSE; + int ret; + + if (xPortIsInsideInterrupt()) { + ret = xQueueReceiveFromISR((usb_osal_mq_t)mq, addr, &xHigherPriorityTaskWoken); + if (ret == pdPASS) { + portYIELD_FROM_ISR(xHigherPriorityTaskWoken); + } + return (ret == pdPASS) ? 0 : -USB_ERR_TIMEOUT; + } else { + if (timeout == USB_OSAL_WAITING_FOREVER) { + return (xQueueReceive((usb_osal_mq_t)mq, addr, portMAX_DELAY) == pdPASS) ? 0 : -USB_ERR_TIMEOUT; + } else { + return (xQueueReceive((usb_osal_mq_t)mq, addr, pdMS_TO_TICKS(timeout)) == pdPASS) ? 0 : -USB_ERR_TIMEOUT; + } + } +} + +static void __usb_timeout(TimerHandle_t *handle) +{ + struct usb_osal_timer *timer = (struct usb_osal_timer *)pvTimerGetTimerID((TimerHandle_t)handle); + + timer->handler(timer->argument); +} + +struct usb_osal_timer *usb_osal_timer_create(const char *name, uint32_t timeout_ms, usb_timer_handler_t handler, void *argument, bool is_period) +{ + struct usb_osal_timer *timer; + (void)name; + + timer = pvPortMalloc(sizeof(struct usb_osal_timer)); + + if (timer == NULL) { + USB_LOG_ERR("Create usb_osal_timer failed\r\n"); + while (1) { + } + } + memset(timer, 0, sizeof(struct usb_osal_timer)); + + timer->handler = handler; + timer->argument = argument; + + timer->timer = (void *)xTimerCreate("usb_tim", pdMS_TO_TICKS(timeout_ms), is_period, timer, (TimerCallbackFunction_t)__usb_timeout); + if (timer->timer == NULL) { + USB_LOG_ERR("Create timer failed\r\n"); + while (1) { + } + } + return timer; +} + +void usb_osal_timer_delete(struct usb_osal_timer *timer) +{ + xTimerStop(timer->timer, 0); + xTimerDelete(timer->timer, 0); + vPortFree(timer); +} + +void usb_osal_timer_start(struct usb_osal_timer *timer) +{ + BaseType_t xHigherPriorityTaskWoken = pdFALSE; + int ret; + + if (xPortIsInsideInterrupt()) { + ret = xTimerStartFromISR(timer->timer, &xHigherPriorityTaskWoken); + if (ret == pdPASS) { + portYIELD_FROM_ISR(xHigherPriorityTaskWoken); + } + } else { + xTimerStart(timer->timer, 0); + } +} + +void usb_osal_timer_stop(struct usb_osal_timer *timer) +{ + xTimerStop(timer->timer, 0); +} + +size_t usb_osal_enter_critical_section(void) +{ + size_t ret; + + if (xPortIsInsideInterrupt()) { + ret = taskENTER_CRITICAL_FROM_ISR(); + } else { + taskENTER_CRITICAL(); + ret = 1; + } + + return ret; +} + +void usb_osal_leave_critical_section(size_t flag) +{ + if (xPortIsInsideInterrupt()) { + taskEXIT_CRITICAL_FROM_ISR(flag); + } else { + taskEXIT_CRITICAL(); + } +} + +void usb_osal_msleep(uint32_t delay) +{ + vTaskDelay(pdMS_TO_TICKS(delay)); +} + +void *usb_osal_malloc(size_t size) +{ + return pvPortMalloc(size); +} + +void usb_osal_free(void *ptr) +{ + vPortFree(ptr); +} \ No newline at end of file diff --git a/kernel/cherryusb/osal/usb_osal_liteos_m.c b/kernel/cherryusb/osal/usb_osal_liteos_m.c new file mode 100644 index 0000000..6eaf76d --- /dev/null +++ b/kernel/cherryusb/osal/usb_osal_liteos_m.c @@ -0,0 +1,343 @@ +/* + * Copyright (c) 2025, HPMicro + * SPDX-License-Identifier: Apache-2.0 + */ +#include "usb_osal.h" +#include "usb_errno.h" +#include "usb_config.h" +#include "usb_log.h" + +#include "los_interrupt.h" +#include "los_task.h" +#include "los_queue.h" +#include "los_sem.h" +#include "los_mux.h" +#include "los_memory.h" +#include "los_swtmr.h" + +usb_osal_thread_t usb_osal_thread_create(const char *name, uint32_t stack_size, uint32_t prio, usb_thread_entry_t entry, void *args) +{ + UINT32 task_id; + UINT32 ret; + + TSK_INIT_PARAM_S task_init_param = { + .usTaskPrio = prio, + .pfnTaskEntry = (TSK_ENTRY_FUNC)entry, + .uwStackSize = stack_size, + .uwArg = (UINT32)args, + .pcName = name + }; + + ret = LOS_TaskCreate(&task_id, &task_init_param); + if (ret != LOS_OK) { + USB_LOG_ERR("Create task[%s] failed code[%u]\r\n", name, ret); + while (1) { + } + } + + return (usb_osal_thread_t)task_id; +} + +void usb_osal_thread_delete(usb_osal_thread_t thread) +{ + UINT32 task_id = (UINT32)thread; + UINT32 ret; + + if (thread == NULL) { + task_id = LOS_CurTaskIDGet(); + } + + ret = LOS_TaskDelete(task_id); + if (ret != LOS_OK) { + USB_LOG_ERR("Delete task id[%u] failed code[%u]\r\n", task_id, ret); + while (1) { + } + } +} + +void usb_osal_thread_schedule_other(void) +{ + UINT32 task_id = LOS_CurTaskIDGet(); + const UINT16 old_priority = LOS_TaskPriGet(task_id); + + LOS_TaskPriSet(task_id, OS_TASK_PRIORITY_LOWEST); + + LOS_TaskYield(); + + LOS_TaskPriSet(task_id, old_priority); +} + +usb_osal_sem_t usb_osal_sem_create(uint32_t initial_count) +{ + UINT32 sem_handle; + UINT32 ret; + + ret = LOS_SemCreate(initial_count, &sem_handle); + if (ret != LOS_OK) { + USB_LOG_ERR("Create Sem failed code[%u]\r\n", ret); + while (1) { + } + } + return (usb_osal_sem_t)sem_handle; +} + +usb_osal_sem_t usb_osal_sem_create_counting(uint32_t max_count) +{ + return usb_osal_sem_create(0); +} + +void usb_osal_sem_delete(usb_osal_sem_t sem) +{ + UINT32 sem_handle = (UINT32)sem; + UINT32 ret; + + ret = LOS_SemDelete(sem_handle); + if (ret != LOS_OK) { + USB_LOG_ERR("Delete sem handle[%u] failed code[%u]\r\n", + sem_handle, ret); + while (1) { + } + } +} + +int usb_osal_sem_take(usb_osal_sem_t sem, uint32_t timeout) +{ + UINT32 sem_handle = (UINT32)sem; + UINT32 ret; + + ret = LOS_SemPend(sem_handle, + timeout == USB_OSAL_WAITING_FOREVER ? + LOS_WAIT_FOREVER : + timeout); + + return ret == LOS_OK ? 0 : -USB_ERR_TIMEOUT; +} + +int usb_osal_sem_give(usb_osal_sem_t sem) +{ + UINT32 sem_handle = (UINT32)sem; + UINT32 ret; + + ret = LOS_SemPost(sem_handle); + + return ret == LOS_OK ? 0 : -USB_ERR_TIMEOUT; +} + +void usb_osal_sem_reset(usb_osal_sem_t sem) +{ +} + +usb_osal_mutex_t usb_osal_mutex_create(void) +{ + UINT32 mux_handle; + UINT32 ret; + + ret = LOS_MuxCreate(&mux_handle); + if (ret != LOS_OK) { + USB_LOG_ERR("Create mux failed code[%u]\r\n", ret); + while (1) { + } + } + return (usb_osal_mutex_t)mux_handle; +} + +void usb_osal_mutex_delete(usb_osal_mutex_t mutex) +{ + UINT32 mux_handle = (UINT32)mutex; + UINT32 ret; + + ret = LOS_MuxDelete(mux_handle); + if (ret != LOS_OK) { + USB_LOG_ERR("Delete mux handle[%u] failed code[%u]\r\n", + mux_handle, ret); + while (1) { + } + } +} + +int usb_osal_mutex_take(usb_osal_mutex_t mutex) +{ + UINT32 mux_handle = (UINT32)mutex; + UINT32 ret; + + ret = LOS_MuxPend(mux_handle, LOS_WAIT_FOREVER); + + return ret == LOS_OK ? 0 : -USB_ERR_TIMEOUT; +} + +int usb_osal_mutex_give(usb_osal_mutex_t mutex) +{ + UINT32 mux_handle = (UINT32)mutex; + UINT32 ret; + + ret = LOS_MuxPost(mux_handle); + + return ret == LOS_OK ? 0 : -USB_ERR_TIMEOUT; +} + +usb_osal_mq_t usb_osal_mq_create(uint32_t max_msgs) +{ + UINT32 queue_id; + UINT32 ret; + + ret = LOS_QueueCreate(NULL, max_msgs, &queue_id, 0, sizeof(uintptr_t)); + if (ret != LOS_OK) { + USB_LOG_ERR("Create queue failed code[%u]\r\n", ret); + while (1) { + } + } + return (usb_osal_mq_t)queue_id; +} + +void usb_osal_mq_delete(usb_osal_mq_t mq) +{ + UINT32 queue_id = (UINT32)mq; + UINT32 ret; + + ret = LOS_QueueDelete(queue_id); + if (ret != LOS_OK) { + USB_LOG_ERR("Delete queue id[%u] failed code[%u]\r\n", + queue_id, ret); + while (1) { + } + } +} + +int usb_osal_mq_send(usb_osal_mq_t mq, uintptr_t addr) +{ + UINT32 queue_id = (UINT32)mq; + UINT32 ret; + UINT32 timeout; + + if (OS_INT_ACTIVE) + timeout = LOS_NO_WAIT; + else + timeout = LOS_WAIT_FOREVER; + + ret = LOS_QueueWrite(queue_id, addr, sizeof(uintptr_t), timeout); + + return ret == LOS_OK ? 0 : -USB_ERR_TIMEOUT; +} + +int usb_osal_mq_recv(usb_osal_mq_t mq, uintptr_t *addr, uint32_t timeout) +{ + UINT32 queue_id = (UINT32)mq; + UINT32 ret; + UINT32 _timeout; + + if (OS_INT_ACTIVE) + _timeout = LOS_NO_WAIT; + else + _timeout = timeout == USB_OSAL_WAITING_FOREVER ? LOS_WAIT_FOREVER : timeout; + + ret = LOS_QueueRead(queue_id, addr, sizeof(uintptr_t), _timeout); + return ret == LOS_OK ? 0 : -USB_ERR_TIMEOUT; +} + +struct usb_osal_timer *usb_osal_timer_create(const char *name, uint32_t timeout_ms, usb_timer_handler_t handler, void *argument, bool is_period) +{ + UINT32 timer_id; + UINT32 ret; + struct usb_osal_timer *timer_handle; + + timer_handle = usb_osal_malloc(sizeof(struct usb_osal_timer)); + if (timer_handle == NULL) { + USB_LOG_ERR("Malloc usb_osal_timer failed\r\n"); + while (1) { + } + } + memset(timer_handle, 0x00, sizeof(struct usb_osal_timer)); + + ret = LOS_SwtmrCreate(timeout_ms, + is_period ? LOS_SWTMR_MODE_PERIOD : LOS_SWTMR_MODE_NO_SELFDELETE, + (SWTMR_PROC_FUNC)handler, &timer_id, (UINT32)argument +#if (LOSCFG_BASE_CORE_SWTMR_ALIGN == 1) + , + OS_SWTMR_ROUSES_IGNORE, OS_SWTMR_ALIGN_INSENSITIVE +#endif + ); + + if (ret != LOS_OK) { + USB_LOG_ERR("Create software timer failed code[%u]\r\n", ret); + while (1) { + } + } + + timer_handle->handler = handler; + timer_handle->argument = argument; + timer_handle->is_period = is_period; + timer_handle->timeout_ms = timeout_ms; + timer_handle->timer = (void *)timer_id; + + return timer_handle; +} + +void usb_osal_timer_delete(struct usb_osal_timer *timer) +{ + UINT32 timer_id = (UINT32)timer->timer; + UINT32 ret; + + ret = LOS_SwtmrDelete(timer_id); + if (ret != LOS_OK) { + USB_LOG_ERR("Delete software timer id[%u] failed code[%u]\r\n", + timer_id, ret); + while (1) { + } + } + usb_osal_free(timer); +} + +void usb_osal_timer_start(struct usb_osal_timer *timer) +{ + UINT32 timer_id = (UINT32)timer->timer; + UINT32 ret; + + ret = LOS_SwtmrStart(timer_id); + if (ret != LOS_OK) { + USB_LOG_ERR("Start software timer id[%u] failed code[%u]\r\n", + timer_id, ret); + while (1) { + } + } +} + +void usb_osal_timer_stop(struct usb_osal_timer *timer) +{ + UINT32 timer_id = (UINT32)timer->timer; + UINT32 ret; + + ret = LOS_SwtmrStop(timer_id); + if (ret != LOS_OK) { + USB_LOG_ERR("Stop software timer id[%u] failed code[%u]\r\n", + timer_id, ret); + while (1) { + } + } +} + +size_t usb_osal_enter_critical_section(void) +{ + return LOS_IntLock(); +} + +void usb_osal_leave_critical_section(size_t flag) +{ + LOS_IntRestore(flag); +} + +void usb_osal_msleep(uint32_t delay) +{ + LOS_Msleep(delay); +} + +void *usb_osal_malloc(size_t size) +{ + return LOS_MemAlloc((VOID *)OS_SYS_MEM_ADDR, size); +} + +void usb_osal_free(void *ptr) +{ + if (ptr != NULL) { + LOS_MemFree((VOID *)OS_SYS_MEM_ADDR, ptr); + } +} \ No newline at end of file diff --git a/kernel/cherryusb/osal/usb_osal_nuttx.c b/kernel/cherryusb/osal/usb_osal_nuttx.c new file mode 100644 index 0000000..36b53fa --- /dev/null +++ b/kernel/cherryusb/osal/usb_osal_nuttx.c @@ -0,0 +1,398 @@ +/* + * Copyright (c) 2024, sakumisu + * + * SPDX-License-Identifier: Apache-2.0 + */ +#include "usb_osal.h" +#include "usb_errno.h" + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +struct mq_adpt { + struct file mq; /* Message queue handle */ + uint32_t msgsize; /* Message size */ + char name[16]; /* Message queue name */ +}; + +usb_osal_thread_t usb_osal_thread_create(const char *name, uint32_t stack_size, uint32_t prio, usb_thread_entry_t entry, void *args) +{ + int pid; + char *argv[2]; + char arg1[32]; + + snprintf(arg1, 16, "%p", args); + argv[0] = arg1; + argv[1] = NULL; + + pid = kthread_create(name, CONFIG_SCHED_HPWORKPRIORITY - prio, stack_size, (void *)entry, + argv); + if (pid > 0) { + return (usb_osal_thread_t)pid; + } else { + return NULL; + } +} + +void usb_osal_thread_delete(usb_osal_thread_t thread) +{ + pid_t pid = (pid_t)((uintptr_t)thread); + + kthread_delete(pid); +} + +void usb_osal_thread_schedule_other(void) +{ + struct sched_param param; + int old_priority; + + /* Get current priority (pid=0 means current task) */ + assert(sched_getparam(0, ¶m) == 0); + old_priority = param.sched_priority; + + /* Set to minimum priority to yield CPU to other tasks */ + param.sched_priority = SCHED_PRIORITY_MIN; + assert(sched_setparam(0, ¶m) == 0); + + /* Yield CPU to other tasks */ + sched_yield(); + + /* Restore original priority */ + param.sched_priority = old_priority; + assert(sched_setparam(0, ¶m) == 0); +} + +usb_osal_sem_t usb_osal_sem_create(uint32_t initial_count) +{ + int ret; + sem_t *sem; + int tmp; + + tmp = sizeof(sem_t); + sem = kmm_malloc(tmp); + if (!sem) { + //printf("ERROR: Failed to alloc %d memory\n", tmp); + return NULL; + } + + ret = nxsem_init(sem, 0, initial_count); + if (ret) { + //printf("ERROR: Failed to initialize sem error=%d\n", ret); + kmm_free(sem); + return NULL; + } + return (usb_osal_sem_t)sem; +} + +usb_osal_sem_t usb_osal_sem_create_counting(uint32_t max_count) +{ + return usb_osal_sem_create(0); +} + +void usb_osal_sem_delete(usb_osal_sem_t sem) +{ + sem_t *__sem = (sem_t *)sem; + + nxsem_destroy(__sem); + kmm_free(__sem); +} + +int usb_osal_sem_take(usb_osal_sem_t sem, uint32_t timeout) +{ + int ret; + sem_t *__sem = (sem_t *)sem; + + if (timeout == 0xffffffff) { + ret = nxsem_wait(__sem); + } else { + ret = nxsem_tickwait(__sem, MSEC2TICK(timeout)); + } + + if (ret) { + return -USB_ERR_TIMEOUT; + } else { + return 0; + } +} + +int usb_osal_sem_give(usb_osal_sem_t sem) +{ + int ret; + sem_t *__sem = (sem_t *)sem; + + ret = nxsem_post(__sem); + if (ret) { + return -USB_ERR_INVAL; + } else { + return 0; + } +} + +void usb_osal_sem_reset(usb_osal_sem_t sem) +{ + nxsem_reset((sem_t *)sem, 0); +} + +usb_osal_mutex_t usb_osal_mutex_create(void) +{ + int ret; + mutex_t *mutex; + int tmp; + + tmp = sizeof(mutex_t); + mutex = kmm_malloc(tmp); + if (!mutex) { + //printf("ERROR: Failed to alloc %d memory\n", tmp); + return NULL; + } + + ret = nxmutex_init(mutex); + if (ret) { + //printf("ERROR: Failed to initialize mutex error=%d\n", ret); + kmm_free(mutex); + return NULL; + } + + return (usb_osal_mutex_t)mutex; +} + +void usb_osal_mutex_delete(usb_osal_mutex_t mutex) +{ + mutex_t *__mutex = (mutex_t *)mutex; + + nxmutex_destroy(__mutex); + kmm_free(__mutex); +} + +int usb_osal_mutex_take(usb_osal_mutex_t mutex) +{ + int ret; + mutex_t *__mutex = (mutex_t *)mutex; + + ret = nxmutex_lock(__mutex); + if (ret) { + return -USB_ERR_INVAL; + } else { + return 0; + } +} + +int usb_osal_mutex_give(usb_osal_mutex_t mutex) +{ + int ret; + mutex_t *__mutex = (mutex_t *)mutex; + + ret = nxmutex_unlock(__mutex); + if (ret) { + return -USB_ERR_INVAL; + } else { + return 0; + } +} + +usb_osal_mq_t usb_osal_mq_create(uint32_t max_msgs) +{ + struct mq_attr attr; + struct mq_adpt *mq_adpt; + int ret; + + mq_adpt = (struct mq_adpt *)kmm_malloc(sizeof(struct mq_adpt)); + + if (!mq_adpt) { + //printf("ERROR: Failed to kmm_malloc\n"); + return NULL; + } + + snprintf(mq_adpt->name, sizeof(mq_adpt->name), + "/tmp/%p", mq_adpt); + + attr.mq_maxmsg = max_msgs; + attr.mq_msgsize = sizeof(uintptr_t); + attr.mq_curmsgs = 0; + attr.mq_flags = 0; + + ret = file_mq_open(&mq_adpt->mq, mq_adpt->name, + O_RDWR | O_CREAT, 0644, &attr); + + if (ret < 0) { + //printf("ERROR: Failed to create mqueue\n"); + kmm_free(mq_adpt); + return NULL; + } + + mq_adpt->msgsize = sizeof(uintptr_t); + return (usb_osal_mq_t)mq_adpt; +} + +void usb_osal_mq_delete(usb_osal_mq_t mq) +{ + struct mq_adpt *mq_adpt = (struct mq_adpt *)mq; + + file_mq_close(&mq_adpt->mq); + file_mq_unlink(mq_adpt->name); + kmm_free(mq_adpt); +} + +int usb_osal_mq_send(usb_osal_mq_t mq, uintptr_t addr) +{ + struct mq_adpt *mq_adpt = (struct mq_adpt *)mq; + int ret; + + /* send mq from isr, do not use timeout*/ + ret = file_mq_send(&mq_adpt->mq, (const char *)&addr, mq_adpt->msgsize, 0); + if (ret < 0) { + return -USB_ERR_INVAL; + } else { + return 0; + } +} + +static void msec2spec(struct timespec *timespec, uint32_t ticks) +{ + uint32_t tmp; + + tmp = TICK2SEC(ticks); + timespec->tv_sec += tmp; + + ticks -= SEC2TICK(tmp); + tmp = TICK2NSEC(ticks); + + timespec->tv_nsec += tmp; +} + +int usb_osal_mq_recv(usb_osal_mq_t mq, uintptr_t *addr, uint32_t timeout) +{ + struct mq_adpt *mq_adpt = (struct mq_adpt *)mq; + struct timespec __timeout; + int ret; + + if (timeout == 0xffffffff) + return file_mq_receive(&mq_adpt->mq, (char *)addr, mq_adpt->msgsize, 0); + else { + ret = clock_gettime(CLOCK_REALTIME, &__timeout); + + if (ret < 0) { + //printf("ERROR: Failed to get time\n"); + return -USB_ERR_INVAL; + } + + if (timeout) { + msec2spec(&__timeout, timeout); + } + + return file_mq_timedreceive(&mq_adpt->mq, + (char *)addr, + mq_adpt->msgsize, + 0, + &__timeout); + } +} + +static void os_timer_callback(wdparm_t arg) +{ + struct usb_osal_timer *timer; + + timer = (struct usb_osal_timer *)arg; + + if (timer->handler) { + timer->handler(timer->argument); + } + + if (timer->is_period) { + wd_start(timer->timer, timer->timeout_ms, os_timer_callback, arg); + } +} + +struct usb_osal_timer *usb_osal_timer_create(const char *name, uint32_t timeout_ms, usb_timer_handler_t handler, void *argument, bool is_period) +{ + struct usb_osal_timer *timer = kmm_malloc(sizeof(struct usb_osal_timer)); + struct wdog_s *wdog = kmm_malloc(sizeof(struct wdog_s)); + + (void)name; + + if (!timer || !wdog) { + return NULL; + } + + memset((void *)timer, 0, sizeof(struct usb_osal_timer)); + memset((void *)wdog, 0, sizeof(struct wdog_s)); + + timer->handler = handler; + timer->argument = argument; + timer->timeout_ms = MSEC2TICK(timeout_ms); + timer->is_period = is_period; + timer->timer = (void *)wdog; + + return (struct usb_osal_timer *)timer; +} + +void usb_osal_timer_delete(struct usb_osal_timer *timer) +{ + wd_cancel(timer->timer); + + kmm_free(timer->timer); + kmm_free(timer); +} + +void usb_osal_timer_start(struct usb_osal_timer *timer) +{ + wd_start(timer->timer, timer->timeout_ms, os_timer_callback, (wdparm_t)timer); +} + +void usb_osal_timer_stop(struct usb_osal_timer *timer) +{ + wd_cancel(timer->timer); +} + +size_t usb_osal_enter_critical_section(void) +{ + irqstate_t flags; + + flags = enter_critical_section(); + + return (size_t)flags; +} + +void usb_osal_leave_critical_section(size_t flag) +{ + leave_critical_section(flag); +} + +void usb_osal_msleep(uint32_t delay) +{ + useconds_t usec = delay * 1000; + + nxsig_usleep(usec); +} + +void *usb_osal_malloc(size_t size) +{ + return kmm_malloc(size); +} + +void usb_osal_free(void *ptr) +{ + kmm_free(ptr); +} \ No newline at end of file diff --git a/kernel/cherryusb/osal/usb_osal_rtthread.c b/kernel/cherryusb/osal/usb_osal_rtthread.c new file mode 100644 index 0000000..cf0e683 --- /dev/null +++ b/kernel/cherryusb/osal/usb_osal_rtthread.c @@ -0,0 +1,229 @@ +/* + * Copyright (c) 2022, sakumisu + * + * SPDX-License-Identifier: Apache-2.0 + */ +#include "usb_osal.h" +#include "usb_errno.h" +#include "usb_config.h" +#include "usb_log.h" +#include +#include + +usb_osal_thread_t usb_osal_thread_create(const char *name, uint32_t stack_size, uint32_t prio, usb_thread_entry_t entry, void *args) +{ + rt_thread_t htask; + htask = rt_thread_create(name, entry, args, stack_size, prio, 10); + if (htask == NULL) { + USB_LOG_ERR("Create thread %s failed\r\n", name); + while (1) { + } + } + rt_thread_startup(htask); + return (usb_osal_thread_t)htask; +} + +void usb_osal_thread_delete(usb_osal_thread_t thread) +{ + if (thread == NULL) { + rt_thread_t self = rt_thread_self(); + rt_thread_control(self, RT_THREAD_CTRL_CLOSE, RT_NULL); + return; + } + + rt_thread_delete(thread); +} + +void usb_osal_thread_schedule_other(void) +{ + rt_thread_t self = rt_thread_self(); + rt_uint8_t priority; +#if (RTTHREAD_VERSION >= RT_VERSION_CHECK(5, 2, 0)) + const rt_uint8_t old_priority = RT_SCHED_PRIV(self).current_priority; +#else + const rt_uint8_t old_priority = self->current_priority; +#endif + priority = RT_THREAD_PRIORITY_MAX - 1; + rt_thread_control(self, RT_THREAD_CTRL_CHANGE_PRIORITY, (void *)&priority); + + rt_thread_yield(); + + rt_thread_control(self, RT_THREAD_CTRL_CHANGE_PRIORITY, (void *)&old_priority); +} + +usb_osal_sem_t usb_osal_sem_create(uint32_t initial_count) +{ + usb_osal_sem_t sem = (usb_osal_sem_t)rt_sem_create("usbh_sem", initial_count, RT_IPC_FLAG_FIFO); + if (sem == NULL) { + USB_LOG_ERR("Create semaphore failed\r\n"); + while (1) { + } + } + return sem; +} + +usb_osal_sem_t usb_osal_sem_create_counting(uint32_t max_count) +{ + return usb_osal_sem_create(0); +} + +void usb_osal_sem_delete(usb_osal_sem_t sem) +{ + rt_sem_delete((rt_sem_t)sem); +} + +int usb_osal_sem_take(usb_osal_sem_t sem, uint32_t timeout) +{ + int ret = 0; + rt_err_t result = RT_EOK; + + if (timeout == USB_OSAL_WAITING_FOREVER) { + result = rt_sem_take((rt_sem_t)sem, RT_WAITING_FOREVER); + } else { + result = rt_sem_take((rt_sem_t)sem, rt_tick_from_millisecond(timeout)); + } + if (result == -RT_ETIMEOUT) { + ret = -USB_ERR_TIMEOUT; + } else if (result == -RT_ERROR) { + ret = -USB_ERR_INVAL; + } else { + ret = 0; + } + + return (int)ret; +} + +int usb_osal_sem_give(usb_osal_sem_t sem) +{ + return (int)rt_sem_release((rt_sem_t)sem); +} + +void usb_osal_sem_reset(usb_osal_sem_t sem) +{ + rt_sem_control((rt_sem_t)sem, RT_IPC_CMD_RESET, (void *)0); +} + +usb_osal_mutex_t usb_osal_mutex_create(void) +{ + usb_osal_mutex_t mutex = (usb_osal_mutex_t)rt_mutex_create("usbh_mutex", RT_IPC_FLAG_FIFO); + if (mutex == NULL) { + USB_LOG_ERR("Create mutex failed\r\n"); + while (1) { + } + } + return mutex; +} + +void usb_osal_mutex_delete(usb_osal_mutex_t mutex) +{ + rt_mutex_delete((rt_mutex_t)mutex); +} + +int usb_osal_mutex_take(usb_osal_mutex_t mutex) +{ + return (int)rt_mutex_take((rt_mutex_t)mutex, RT_WAITING_FOREVER); +} + +int usb_osal_mutex_give(usb_osal_mutex_t mutex) +{ + return (int)rt_mutex_release((rt_mutex_t)mutex); +} + +usb_osal_mq_t usb_osal_mq_create(uint32_t max_msgs) +{ + return (usb_osal_mq_t)rt_mq_create("usbh_mq", sizeof(uintptr_t), max_msgs, RT_IPC_FLAG_FIFO); +} + +void usb_osal_mq_delete(usb_osal_mq_t mq) +{ + rt_mq_delete((rt_mq_t)mq); +} + +int usb_osal_mq_send(usb_osal_mq_t mq, uintptr_t addr) +{ + return rt_mq_send((rt_mq_t)mq, &addr, sizeof(uintptr_t)); +} + +int usb_osal_mq_recv(usb_osal_mq_t mq, uintptr_t *addr, uint32_t timeout) +{ + int ret = 0; + rt_err_t result = RT_EOK; + + if (timeout == USB_OSAL_WAITING_FOREVER) { + result = rt_mq_recv((rt_mq_t)mq, addr, sizeof(uintptr_t), RT_WAITING_FOREVER); + } else { + result = rt_mq_recv((rt_mq_t)mq, addr, sizeof(uintptr_t), rt_tick_from_millisecond(timeout)); + } + if (result == -RT_ETIMEOUT) { + ret = -USB_ERR_TIMEOUT; + } else if (result == -RT_ERROR) { + ret = -USB_ERR_INVAL; + } else { + ret = 0; + } + + return (int)ret; +} + +struct usb_osal_timer *usb_osal_timer_create(const char *name, uint32_t timeout_ms, usb_timer_handler_t handler, void *argument, bool is_period) +{ + struct usb_osal_timer *timer; + + timer = rt_malloc(sizeof(struct usb_osal_timer)); + if (timer == NULL) { + USB_LOG_ERR("Create usb_osal_timer failed\r\n"); + while (1) { + } + } + memset(timer, 0, sizeof(struct usb_osal_timer)); + + timer->timer = (void *)rt_timer_create(name, handler, argument, timeout_ms, is_period ? (RT_TIMER_FLAG_PERIODIC | RT_TIMER_FLAG_SOFT_TIMER) : (RT_TIMER_FLAG_ONE_SHOT | RT_TIMER_FLAG_SOFT_TIMER)); + if (timer->timer == NULL) { + USB_LOG_ERR("Create timer failed\r\n"); + while (1) { + } + } + return timer; +} + +void usb_osal_timer_delete(struct usb_osal_timer *timer) +{ + rt_timer_stop(timer->timer); + rt_timer_delete(timer->timer); + rt_free(timer); +} + +void usb_osal_timer_start(struct usb_osal_timer *timer) +{ + rt_timer_start(timer->timer); +} + +void usb_osal_timer_stop(struct usb_osal_timer *timer) +{ + rt_timer_stop(timer->timer); +} + +size_t usb_osal_enter_critical_section(void) +{ + return rt_hw_interrupt_disable(); +} + +void usb_osal_leave_critical_section(size_t flag) +{ + rt_hw_interrupt_enable(flag); +} + +void usb_osal_msleep(uint32_t delay) +{ + rt_thread_mdelay(delay); +} + +void *usb_osal_malloc(size_t size) +{ + return rt_malloc(size); +} + +void usb_osal_free(void *ptr) +{ + rt_free(ptr); +} \ No newline at end of file diff --git a/kernel/cherryusb/osal/usb_osal_threadx.c b/kernel/cherryusb/osal/usb_osal_threadx.c new file mode 100644 index 0000000..2a6d005 --- /dev/null +++ b/kernel/cherryusb/osal/usb_osal_threadx.c @@ -0,0 +1,329 @@ +/* + * Copyright (c) 2024, sakumisu + * + * SPDX-License-Identifier: Apache-2.0 + */ +#include "usb_osal.h" +#include "usb_errno.h" +#include "usb_config.h" +#include "usb_log.h" +#include "tx_api.h" + +extern TX_BYTE_POOL usb_byte_pool; // define usb_byte_pool and call usb_osal_init first + +usb_osal_mq_t usb_osal_mq; + +usb_osal_thread_t usb_osal_thread_create(const char *name, uint32_t stack_size, uint32_t prio, usb_thread_entry_t entry, void *args) +{ + TX_THREAD *thread_ptr = TX_NULL; + + tx_byte_allocate(&usb_byte_pool, (VOID **)&thread_ptr, USB_ALIGN_UP(sizeof(TX_THREAD), 4) + stack_size, TX_NO_WAIT); + if (thread_ptr == TX_NULL) { + USB_LOG_ERR("Create thread %s failed\r\n", name); + while (1) { + } + } + + tx_thread_create(thread_ptr, (CHAR *)name, (VOID(*)(ULONG))entry, (uintptr_t)args, + ((CHAR *)thread_ptr + USB_ALIGN_UP(sizeof(TX_THREAD), 4)), stack_size, + prio, prio, TX_NO_TIME_SLICE, TX_AUTO_START); + + return (usb_osal_thread_t)thread_ptr; +} + +void usb_osal_thread_delete(usb_osal_thread_t thread) +{ + if (thread == NULL) { + thread = tx_thread_identify(); + + usb_osal_mq_send(usb_osal_mq, (uintptr_t)thread); + + tx_thread_terminate(thread); + return; + } + + tx_thread_terminate(thread); + tx_thread_delete(thread); + tx_byte_release(thread); +} + +void usb_osal_thread_schedule_other(void) +{ + TX_THREAD *current_thread = tx_thread_identify(); + const UINT old_priority = current_thread->tx_thread_priority; + + tx_thread_priority_change(current_thread, TX_MAX_PRIORITIES - 1, &old_priority); + + tx_thread_relinquish(); + + tx_thread_priority_change(current_thread, old_priority, &old_priority); +} + +usb_osal_sem_t usb_osal_sem_create(uint32_t initial_count) +{ + TX_SEMAPHORE *sem_ptr = TX_NULL; + + tx_byte_allocate(&usb_byte_pool, (VOID **)&sem_ptr, sizeof(TX_SEMAPHORE), TX_NO_WAIT); + if (sem_ptr == TX_NULL) { + USB_LOG_ERR("Create semaphore failed\r\n"); + while (1) { + } + } + + tx_semaphore_create(sem_ptr, "usbh_sem", initial_count); + return (usb_osal_sem_t)sem_ptr; +} + +usb_osal_sem_t usb_osal_sem_create_counting(uint32_t max_count) +{ + return usb_osal_sem_create(0); +} + +void usb_osal_sem_delete(usb_osal_sem_t sem) +{ + tx_semaphore_delete((TX_SEMAPHORE *)sem); + tx_byte_release(sem); +} + +int usb_osal_sem_take(usb_osal_sem_t sem, uint32_t timeout) +{ + int ret = 0; + + ret = tx_semaphore_get((TX_SEMAPHORE *)sem, timeout); + if (ret == TX_SUCCESS) { + ret = 0; + } else if ((ret == TX_WAIT_ABORTED) || (ret == TX_NO_INSTANCE)) { + ret = -USB_ERR_TIMEOUT; + } else { + ret = -USB_ERR_INVAL; + } + + return (int)ret; +} + +int usb_osal_sem_give(usb_osal_sem_t sem) +{ + return (tx_semaphore_put((TX_SEMAPHORE *)sem) == TX_SUCCESS) ? 0 : -USB_ERR_INVAL; +} + +void usb_osal_sem_reset(usb_osal_sem_t sem) +{ + tx_semaphore_get((TX_SEMAPHORE *)sem, 0); +} + +usb_osal_mutex_t usb_osal_mutex_create(void) +{ + TX_MUTEX *mutex_ptr = TX_NULL; + + tx_byte_allocate(&usb_byte_pool, (VOID **)&mutex_ptr, sizeof(TX_MUTEX), TX_NO_WAIT); + if (mutex_ptr == TX_NULL) { + USB_LOG_ERR("Create mutex failed\r\n"); + while (1) { + } + } + + tx_mutex_create(mutex_ptr, "usbh_mutex", TX_INHERIT); + return (usb_osal_mutex_t)mutex_ptr; +} + +void usb_osal_mutex_delete(usb_osal_mutex_t mutex) +{ + tx_mutex_delete((TX_MUTEX *)mutex); + tx_byte_release(mutex); +} + +int usb_osal_mutex_take(usb_osal_mutex_t mutex) +{ + int ret = 0; + + ret = tx_mutex_get((TX_MUTEX *)mutex, TX_WAIT_FOREVER); + if (ret == TX_SUCCESS) { + ret = 0; + } else if ((ret == TX_WAIT_ABORTED) || (ret == TX_NO_INSTANCE)) { + ret = -USB_ERR_TIMEOUT; + } else { + ret = -USB_ERR_INVAL; + } + + return (int)ret; +} + +int usb_osal_mutex_give(usb_osal_mutex_t mutex) +{ + return (tx_mutex_put((TX_MUTEX *)mutex) == TX_SUCCESS) ? 0 : -USB_ERR_INVAL; +} + +usb_osal_mq_t usb_osal_mq_create(uint32_t max_msgs) +{ + TX_QUEUE *queue_ptr = TX_NULL; + + tx_byte_allocate(&usb_byte_pool, (VOID **)&queue_ptr, USB_ALIGN_UP(sizeof(TX_QUEUE), 4) + sizeof(uintptr_t) * max_msgs, TX_NO_WAIT); + if (queue_ptr == TX_NULL) { + USB_LOG_ERR("Create TX_QUEUE failed\r\n"); + while (1) { + } + } + + tx_queue_create(queue_ptr, "usbh_mq", sizeof(uintptr_t) / 4, (CHAR *)queue_ptr + USB_ALIGN_UP(sizeof(TX_QUEUE), 4), sizeof(uintptr_t) * max_msgs); + return (usb_osal_mq_t)queue_ptr; +} + +void usb_osal_mq_delete(usb_osal_mq_t mq) +{ + tx_queue_delete((TX_QUEUE *)mq); + tx_byte_release(mq); +} + +int usb_osal_mq_send(usb_osal_mq_t mq, uintptr_t addr) +{ + return (tx_queue_send((TX_QUEUE *)mq, &addr, TX_NO_WAIT) == TX_SUCCESS) ? 0 : -USB_ERR_INVAL; +} + +int usb_osal_mq_recv(usb_osal_mq_t mq, uintptr_t *addr, uint32_t timeout) +{ + int ret = 0; + + ret = tx_queue_receive((TX_QUEUE *)mq, addr, timeout); + if (ret == TX_SUCCESS) { + ret = 0; + } else if (ret == TX_QUEUE_EMPTY) { + ret = -USB_ERR_TIMEOUT; + } else { + ret = -USB_ERR_INVAL; + } + + return (int)ret; +} + +struct usb_osal_timer *usb_osal_timer_create(const char *name, uint32_t timeout_ms, usb_timer_handler_t handler, void *argument, bool is_period) +{ + TX_TIMER *timer_ptr = TX_NULL; + struct usb_osal_timer *timer; + + tx_byte_allocate(&usb_byte_pool, (VOID **)&timer, sizeof(struct usb_osal_timer), TX_NO_WAIT); + if (timer == TX_NULL) { + USB_LOG_ERR("Create usb_osal_timer failed\r\n"); + while (1) { + } + } + memset(timer, 0, sizeof(struct usb_osal_timer)); + + tx_byte_allocate(&usb_byte_pool, (VOID **)&timer_ptr, sizeof(TX_TIMER), TX_NO_WAIT); + if (timer_ptr == TX_NULL) { + USB_LOG_ERR("Create TX_TIMER failed\r\n"); + while (1) { + } + } + + timer->timer = timer_ptr; + timer->timeout_ms = timeout_ms; + timer->is_period = is_period; + if (tx_timer_create(timer_ptr, (CHAR *)name, (void (*)(ULONG))handler, (uintptr_t)argument, 1, is_period ? 1 : 0, + TX_NO_ACTIVATE) != TX_SUCCESS) { + return NULL; + } + return timer; +} + +void usb_osal_timer_delete(struct usb_osal_timer *timer) +{ + tx_timer_deactivate((TX_TIMER *)timer->timer); + tx_timer_delete((TX_TIMER *)timer->timer); + tx_byte_release(timer->timer); + tx_byte_release(timer); +} + +void usb_osal_timer_start(struct usb_osal_timer *timer) +{ + if (tx_timer_change((TX_TIMER *)timer->timer, timer->timeout_ms, timer->is_period ? timer->timeout_ms : 0) == TX_SUCCESS) { + /* Call the tx_timer_activate to activates the specified application + timer. The expiration routines of timers that expire at the same + time are executed in the order they were activated. */ + if (tx_timer_activate((TX_TIMER *)timer->timer) == TX_SUCCESS) { + /* Return osOK for success */ + } else { + /* Return osErrorResource in case of error */ + } + } else { + } +} + +void usb_osal_timer_stop(struct usb_osal_timer *timer) +{ + tx_timer_deactivate((TX_TIMER *)timer->timer); +} + +size_t usb_osal_enter_critical_section(void) +{ + TX_INTERRUPT_SAVE_AREA + + TX_DISABLE + + return interrupt_save; +} + +void usb_osal_leave_critical_section(size_t flag) +{ + TX_INTERRUPT_SAVE_AREA + + interrupt_save = flag; + TX_RESTORE +} + +void usb_osal_msleep(uint32_t delay) +{ +#if TX_TIMER_TICKS_PER_SECOND != 1000 +#error "TX_TIMER_TICKS_PER_SECOND must be 1000" +#endif + tx_thread_sleep(delay); +} + +void *usb_osal_malloc(size_t size) +{ + CHAR *pointer = TX_NULL; + + tx_byte_allocate(&usb_byte_pool, (VOID **)&pointer, size, TX_WAIT_FOREVER); + + return pointer; +} + +void usb_osal_free(void *ptr) +{ + tx_byte_release(ptr); +} + +static void usb_osal_thread(CONFIG_USB_OSAL_THREAD_SET_ARGV) +{ + int ret; + usb_osal_thread_t thread; + + while (1) { + ret = usb_osal_mq_recv(usb_osal_mq, (uintptr_t *)&thread, TX_WAIT_FOREVER); + if (ret < 0) { + continue; + } + tx_thread_delete(thread); + tx_byte_release(thread); + } +} + +void usb_osal_init(uint8_t *mem, uint32_t mem_size) +{ + usb_osal_thread_t thread; + + tx_byte_pool_create(&usb_byte_pool, "usb byte pool", mem, mem_size); + + thread = usb_osal_thread_create("usb_osal", 2048, 10, usb_osal_thread, NULL); + if (thread == NULL) { + USB_LOG_ERR("Create usb_osal_thread failed\r\n"); + while (1) { + } + } + + usb_osal_mq = usb_osal_mq_create(32); + if (usb_osal_mq == NULL) { + USB_LOG_ERR("Create usb_osal_mq failed\r\n"); + while (1) { + } + } +} diff --git a/kernel/cherryusb/osal/usb_osal_zephyr.c b/kernel/cherryusb/osal/usb_osal_zephyr.c new file mode 100644 index 0000000..b65d752 --- /dev/null +++ b/kernel/cherryusb/osal/usb_osal_zephyr.c @@ -0,0 +1,317 @@ +/* + * Copyright (c) 2025, sakumisu + * + * SPDX-License-Identifier: Apache-2.0 + */ +#include "usb_osal.h" +#include "usb_errno.h" +#include "usb_config.h" +#include "usb_log.h" + +#include +#if (KERNELVERSION >= 0x3020000) +#include +#else +#include +#endif + +struct release_thread_work { + struct k_work work; + usb_osal_thread_t thread; +}; + +usb_osal_thread_t usb_osal_thread_create(const char *name, uint32_t stack_size, uint32_t prio, usb_thread_entry_t entry, void *args) +{ + k_tid_t tid = NULL; + struct k_thread *thread = (struct k_thread *)k_aligned_alloc(8, sizeof(struct k_thread) + stack_size); + k_thread_stack_t *stack = (k_thread_stack_t *)thread; + + if (thread == NULL) { + USB_LOG_ERR("Create thread faild\r\n"); + return NULL; + } + + tid = k_thread_create(thread, (k_thread_stack_t *)&stack[sizeof(struct k_thread)], + stack_size, + (k_thread_entry_t)entry, + args, NULL, NULL, + prio, + 0, + K_NO_WAIT); + +#if defined(CONFIG_THREAD_NAME) + k_thread_name_set(tid, name); +#endif + + return (usb_osal_thread_t)tid; +} + +static void release_thread_handler(struct k_work *work) +{ + struct release_thread_work *release_work = (struct release_thread_work *)work; + k_free(release_work->thread); + k_work_cancel(work); + k_free(release_work); +} + +void usb_osal_thread_delete(usb_osal_thread_t thread) +{ + struct release_thread_work *release_work; + if (thread == NULL) { +#if (KERNELVERSION >= 0x3070000) + thread = k_sched_current_thread_query(); +#else + thread = z_current_get(); +#endif + release_work = k_malloc(sizeof(struct release_thread_work)); + release_work->thread = thread; + k_work_init(&release_work->work, release_thread_handler); + k_work_submit(&release_work->work); + k_thread_abort(thread); + return; + } + k_thread_abort(thread); + k_free(thread); +} + +void usb_osal_thread_schedule_other(void) +{ +#if (KERNELVERSION >= 0x3070000) + struct k_thread *current_thread = k_sched_current_thread_query(); +#else + struct k_thread *current_thread = z_current_get(); +#endif + const int old_priority = k_thread_priority_get(current_thread); + + k_thread_priority_set(current_thread, K_LOWEST_APPLICATION_THREAD_PRIO); + + k_yield(); + + k_thread_priority_set(current_thread, old_priority); +} + +usb_osal_sem_t usb_osal_sem_create(uint32_t initial_count) +{ + struct k_sem *sem; + + sem = k_malloc(sizeof(struct k_sem)); + if (sem == NULL) { + USB_LOG_ERR("Create semaphore faild\r\n"); + return NULL; + } + k_sem_init(sem, initial_count, 1); + + return (usb_osal_sem_t)sem; +} + +usb_osal_sem_t usb_osal_sem_create_counting(uint32_t max_count) +{ + struct k_sem *sem; + + sem = k_malloc(sizeof(struct k_sem)); + if (sem == NULL) { + USB_LOG_ERR("Create semaphore faild\r\n"); + return NULL; + } + k_sem_init(sem, 0, max_count); + + return (usb_osal_sem_t)sem; +} + +void usb_osal_sem_delete(usb_osal_sem_t sem) +{ + while (k_sem_take((struct k_sem *)sem, K_NO_WAIT) != 0) { + break; + } + k_free((struct k_sem *)sem); +} + +int usb_osal_sem_take(usb_osal_sem_t sem, uint32_t timeout) +{ + if (timeout == USB_OSAL_WAITING_FOREVER) { + return (k_sem_take((struct k_sem *)sem, K_FOREVER) == 0) ? 0 : -USB_ERR_TIMEOUT; + } else { + return (k_sem_take((struct k_sem *)sem, K_MSEC(timeout)) == 0) ? 0 : -USB_ERR_TIMEOUT; + } +} + +int usb_osal_sem_give(usb_osal_sem_t sem) +{ + k_sem_give((struct k_sem *)sem); + + return 0; +} + +void usb_osal_sem_reset(usb_osal_sem_t sem) +{ + k_sem_reset((struct k_sem *)sem); +} + +usb_osal_mutex_t usb_osal_mutex_create(void) +{ + struct k_mutex *mutex; + + mutex = k_malloc(sizeof(struct k_mutex)); + if (mutex == NULL) { + USB_LOG_ERR("Create mutex faild\r\n"); + return NULL; + } + k_mutex_init(mutex); + + return (usb_osal_mutex_t)mutex; +} + +void usb_osal_mutex_delete(usb_osal_mutex_t mutex) +{ + k_free((struct k_mutex *)mutex); +} + +int usb_osal_mutex_take(usb_osal_mutex_t mutex) +{ + return (k_mutex_lock((struct k_mutex *)mutex, K_FOREVER) == 0) ? 0 : -USB_ERR_TIMEOUT; +} + +int usb_osal_mutex_give(usb_osal_mutex_t mutex) +{ + return (k_mutex_unlock((struct k_mutex *)mutex) == 0) ? 0 : -USB_ERR_INVAL; +} + +usb_osal_mq_t usb_osal_mq_create(uint32_t max_msgs) +{ + struct k_msgq *msgq; + + msgq = k_malloc(sizeof(struct k_msgq)); + if (msgq == NULL) { + USB_LOG_ERR("Create message queue faild\r\n"); + return NULL; + } + if (k_msgq_alloc_init(msgq, sizeof(uintptr_t), max_msgs) != 0) { + return NULL; + } + + return (usb_osal_mq_t)msgq; +} + +void usb_osal_mq_delete(usb_osal_mq_t mq) +{ + struct k_msgq *msgq; + + msgq = (struct k_msgq *)mq; + + k_msgq_purge(msgq); + k_free(msgq->buffer_start); + k_free(msgq); +} + +int usb_osal_mq_send(usb_osal_mq_t mq, uintptr_t addr) +{ + struct k_msgq *msgq; + + msgq = (struct k_msgq *)mq; + + if (k_is_in_isr()) { + return (k_msgq_put(msgq, &addr, K_NO_WAIT) == 0) ? 0 : -USB_ERR_TIMEOUT; + } else { + return (k_msgq_put(msgq, &addr, K_FOREVER) == 0) ? 0 : -USB_ERR_TIMEOUT; + } +} + +int usb_osal_mq_recv(usb_osal_mq_t mq, uintptr_t *addr, uint32_t timeout) +{ + struct k_msgq *msgq; + + msgq = (struct k_msgq *)mq; + + if (k_is_in_isr()) { + return (k_msgq_get(msgq, addr, K_NO_WAIT) == 0) ? 0 : -USB_ERR_TIMEOUT; + } else { + if (timeout == USB_OSAL_WAITING_FOREVER) { + return (k_msgq_get(msgq, addr, K_FOREVER) == 0) ? 0 : -USB_ERR_TIMEOUT; + } else { + return (k_msgq_get(msgq, addr, K_MSEC(timeout)) == 0) ? 0 : -USB_ERR_TIMEOUT; + } + } +} + +static void zephyr_timer_wrapper(struct k_timer *ktimer) +{ + struct usb_osal_timer *timer = (struct usb_osal_timer *)ktimer->user_data; + + timer->handler(timer->argument); +} + +struct usb_osal_timer *usb_osal_timer_create(const char *name, uint32_t timeout_ms, usb_timer_handler_t handler, void *argument, bool is_period) +{ + struct usb_osal_timer *timer; + + (void)name; + + timer = k_malloc(sizeof(struct usb_osal_timer)); + if (timer == NULL) { + USB_LOG_ERR("Create timer faild\r\n"); + return NULL; + } + memset(timer, 0, sizeof(struct usb_osal_timer)); + + timer->timer = k_malloc(sizeof(struct k_timer)); + if (timer->timer == NULL) { + USB_LOG_ERR("Create timer faild\r\n"); + return NULL; + } + + timer->handler = handler; + timer->argument = argument; + timer->is_period = is_period; + timer->timeout_ms = timeout_ms; + + k_timer_init(timer->timer, zephyr_timer_wrapper, NULL); + k_timer_user_data_set(timer->timer, timer); + + return timer; +} + +void usb_osal_timer_delete(struct usb_osal_timer *timer) +{ + k_timer_stop(timer->timer); + k_free(timer->timer); + k_free(timer); +} + +void usb_osal_timer_start(struct usb_osal_timer *timer) +{ + if (timer->is_period) { + k_timer_start(timer->timer, K_MSEC(timer->timeout_ms), K_MSEC(timer->timeout_ms)); + } else { + k_timer_start(timer->timer, K_MSEC(timer->timeout_ms), K_NO_WAIT); + } +} + +void usb_osal_timer_stop(struct usb_osal_timer *timer) +{ + k_timer_stop(timer->timer); +} + +size_t usb_osal_enter_critical_section(void) +{ + return irq_lock(); +} + +void usb_osal_leave_critical_section(size_t flag) +{ + irq_unlock(flag); +} + +void usb_osal_msleep(uint32_t delay) +{ + k_sleep(K_MSEC(delay)); +} + +void *usb_osal_malloc(size_t size) +{ + return k_malloc(size); +} + +void usb_osal_free(void *ptr) +{ + k_free(ptr); +} \ No newline at end of file diff --git a/kernel/cherryusb/port/aic/usb_dc_aic.c b/kernel/cherryusb/port/aic/usb_dc_aic.c new file mode 100644 index 0000000..fafa611 --- /dev/null +++ b/kernel/cherryusb/port/aic/usb_dc_aic.c @@ -0,0 +1,1661 @@ +/* + * Copyright (c) 2023-2024, ArtInChip Technology Co., Ltd + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include "usbd_core.h" +#include "usb_dc_aic_reg.h" + +// clang-format off +#ifndef __UNALIGNED_UINT32_WRITE + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT32_READ + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) +#endif +// clang-format on + +#define FS_PORT 0 +#define HS_PORT 1 + +#ifndef CONFIG_USB_AIC_DC_PORT +#error "please select CONFIG_USB_AIC_DC_PORT with FS_PORT or HS_PORT" +#endif + +#ifndef USB_BASE +#define USB_BASE CONFIG_USB_AIC_DC_BASE +#endif + +#ifdef LPKG_CHERRYUSB_DEVICE_HID_IO_TEMPLATE +#define USB_RAM_SIZE 1024 /* define with maximum value*/ +#else +#define USB_RAM_SIZE 512 /* define with maximum value*/ +#endif + +#ifndef USB_NUM_BIDIR_ENDPOINTS +#define USB_NUM_BIDIR_ENDPOINTS 5 /* define with minimum value*/ +#endif + +/* USB_P_TXFIFO_NUM: + * There are only 2 Periodic_TXFIFO, and each Interrupt/Isochronous In ep + * needs to request one P_TXFIFO. So, only two Interrupt/Isochronous In ep + * can be requested for at most. + */ +#define USB_P_TXFIFO_NUM 2 + +#define AIC_UDC_REG ((AIC_UDC_RegDef *)(USB_BASE)) +#define AIC_EP_FIFO(i) *(__IO uint32_t *)(USB_BASE + AIC_EP_FIFO_BASE + ((i)*AIC_EP_FIFO_SIZE)) + +/* Endpoint state */ +struct aic_ep_state { + uint16_t ep_mps; /* Endpoint max packet size */ + uint8_t ep_type; /* Endpoint type */ + uint8_t ep_stalled; /* Endpoint stall flag */ + uint8_t *xfer_buf; +#ifdef CONFIG_USB_AIC_DMA_ENABLE + uint8_t *xfer_align_buf; + uint32_t xfer_align_len; +#endif + uint32_t xfer_len; + uint32_t actual_xfer_len; +}; + +extern uint32_t usbd_clk; + +/* Driver state */ +/*USB_NOCACHE_RAM_SECTION*/ struct aic_udc { + USB_MEM_ALIGNX struct usb_setup_packet setup; + USB_MEM_ALIGNX struct aic_ep_state in_ep[USB_NUM_BIDIR_ENDPOINTS]; /*!< IN endpoint parameters*/ + struct aic_ep_state out_ep[USB_NUM_BIDIR_ENDPOINTS]; /*!< OUT endpoint parameters */ + struct usb_endpoint_descriptor in_ep_desc[USB_NUM_BIDIR_ENDPOINTS]; + uint32_t p_txfifo_map; /* map which periodic_txfifo is used */ + uint32_t np_txfifo_map; /* map no-periodic_txfifo is used */ +} g_aic_udc; + +#define AIC_EP0_SETUP 1 +#define AIC_EP0_DATA_IN 2 +#define AIC_EP0_STATUS_OUT 3 +#define AIC_EP0_DATA_OUT 12 +#define AIC_EP0_STATUS_IN 13 + +uint8_t ep0_ctrl_stage = 0; /* 1 = setup stage, 2 = data stage, 3 = status stage */ + +#ifdef CONFIG_USB_AIC_DMA_ENABLE +static uint8_t g_aic_udc_ibuf[USB_RAM_SIZE] __ALIGNED(CACHE_LINE_SIZE); +static uint8_t g_aic_udc_obuf[USB_RAM_SIZE] __ALIGNED(CACHE_LINE_SIZE); + +void aic_udc_dcache_clean(uintptr_t addr, uint32_t len) +{ + aicos_dcache_clean_range((size_t *)addr, len); +} + +void aic_udc_dcache_invalidate(uintptr_t addr, uint32_t len) +{ + aicos_dcache_invalid_range((size_t *)addr, len); +} + +void aic_udc_dcache_clean_invalidate(uintptr_t addr, uint32_t len) +{ + aicos_dcache_clean_invalid_range((size_t *)addr, len); +} + +static int aic_udc_ep_buf_alloc(struct aic_ep_state *ep, uint32_t len, + uint8_t *sbuf) +{ + ep->xfer_len = len; + if (len % CACHE_LINE_SIZE) + ep->xfer_align_len = ALIGN_UP(len, CACHE_LINE_SIZE); + else + ep->xfer_align_len = len; + + if (ep->xfer_align_len > USB_RAM_SIZE) { + ep->xfer_align_buf = aicos_malloc_align(0, ep->xfer_align_len, + CACHE_LINE_SIZE); + USB_LOG_DBG("aicos_malloc_align %d bytes.", ep->xfer_align_len); + if (!ep->xfer_align_buf) { + USB_LOG_ERR("alloc error.\r\n"); + return -5; + } + } else { + ep->xfer_align_buf = sbuf; + } + + return 0; +} + +static void aic_udc_ep_buf_free(struct aic_ep_state *ep, uint8_t *sbuf) +{ + if (!ep->xfer_align_buf) + return; + + /* Whether the buf is allocated dynamically */ + if (ep->xfer_align_buf != sbuf) { + USB_LOG_DBG("aicos_free_align %d bytes.", ep->xfer_align_len); + aicos_free_align(0, ep->xfer_align_buf); + } + + ep->xfer_align_buf = NULL; + ep->xfer_align_len = 0; +} + +static int aic_udc_ibuf_alloc(struct aic_ep_state *ep, uint32_t len) +{ + return aic_udc_ep_buf_alloc(ep, len, g_aic_udc_ibuf); +} + +static int aic_udc_obuf_alloc(struct aic_ep_state *ep, uint32_t len) +{ + return aic_udc_ep_buf_alloc(ep, len, g_aic_udc_obuf); +} + +static void aic_udc_ibuf_free(struct aic_ep_state *ep) +{ + aic_udc_ep_buf_free(ep, g_aic_udc_ibuf); +} + +static void aic_udc_obuf_free(struct aic_ep_state *ep) +{ + aic_udc_ep_buf_free(ep, g_aic_udc_obuf); +} +#else +#define aic_udc_dcache_clean(addr, len) +#define aic_udc_dcache_invalidate(addr, len) +#define aic_udc_dcache_clean_invalidate(addr, len) +#endif + +static void aic_set_dma_nextep(void) +{ + uint32_t i; + uint32_t inepcfg = 0; + + /* dma to set the next-endpoint pointer. */ + for (i = 0; i < USB_NUM_BIDIR_ENDPOINTS; i++) { + uint32_t next = ((i + 1) % USB_NUM_BIDIR_ENDPOINTS) << DEPCTL_NEXT_EP_BIT; + + inepcfg = readl(&AIC_UDC_REG->inepcfg[i]); + inepcfg &= ~DEPCTL_NEXT_EP_MASK; + inepcfg |= next; + writel(inepcfg, &AIC_UDC_REG->inepcfg[i]); + } +} + +static inline int aic_reset(void) +{ + uint32_t count = 0U; + uint32_t tmpreg = 0; + + /* Wait for AHB master IDLE state. */ + do { + if (++count > 200000U) { + return -1; + } + tmpreg = readl(&AIC_UDC_REG->ahbbasic); + } while ((tmpreg & AHBBASIC_AHBIDLE) == 0U); + + /* Core Soft Reset */ + count = 0U; + tmpreg = readl(&AIC_UDC_REG->usbdevinit); + tmpreg |= USBDEVINIT_CSFTRST; + writel(tmpreg, &AIC_UDC_REG->usbdevinit); + + do { + if (++count > 200000U) { + return -1; + } + tmpreg = readl(&AIC_UDC_REG->usbdevinit); + } while ((tmpreg & USBDEVINIT_CSFTRST) == USBDEVINIT_CSFTRST); + + return 0; +} + +static inline int aic_core_init(void) +{ + int ret; + uint32_t usb_gusbcfg = + 0 << 19 /* ULPI Clock SuspendM */ + | 0 << 18 /* ULPI Phy Auto Resume */ + | 0 << 15 /* PHY Low Power Clock sel */ + | 0x5 << 10 /* USB Turnaround time (0x5 for HS phy) */ + | 0 << 7 /* ULPI DDR sel 0:single 8bit, 1:double 4bit */ + /*| 0 << 6 0: high speed utmi+, 1: full speed serial*/ +#ifdef FPGA_BOARD_ARTINCHIP + | 1 << 4 /* 0: utmi+, 1:ulpi*/ +#else + | 0 << 4 /* 0: utmi+, 1:ulpi*/ +#endif + | 0 << 3 /* UTMI+ PHY 0:8bit, 1:16bit (ULPI PHY set 8bit) */ + | 0x7 << 0; /* HS/FS timeout calibration**/ + + /* Activate the USB Transceiver */ + writel(usb_gusbcfg, &AIC_UDC_REG->usbphyif); + + /* Reset after a PHY select */ + ret = aic_reset(); + + aic_set_dma_nextep(); + + return ret; +} + +static inline int aic_flush_rxfifo(void) +{ + uint32_t count = 0; + uint32_t tmpreg = 0; + + tmpreg = readl(&AIC_UDC_REG->usbdevinit); + tmpreg |= USBDEVINIT_RXFFLSH; + writel(tmpreg, &AIC_UDC_REG->usbdevinit); + + do { + if (++count > 200000U) { + return -1; + } + tmpreg = readl(&AIC_UDC_REG->usbdevinit); + } while ((tmpreg & USBDEVINIT_RXFFLSH) == USBDEVINIT_RXFFLSH); + + return 0; +} + +static inline int aic_flush_txfifo(uint32_t num) +{ + uint32_t count = 0U; + uint32_t tmpreg = 0; + + tmpreg = readl(&AIC_UDC_REG->usbdevinit); + tmpreg &= ~ USBDEVINIT_TXFNUM(USBDEVINIT_TXFNUM_LIMIT); + tmpreg |= USBDEVINIT_TXFNUM(num & USBDEVINIT_TXFNUM_LIMIT) + | USBDEVINIT_TXFFLSH; + writel(tmpreg, &AIC_UDC_REG->usbdevinit); + + do { + if (++count > 200000U) { + return -1; + } + tmpreg = readl(&AIC_UDC_REG->usbdevinit); + } while ((tmpreg & USBDEVINIT_TXFFLSH) == USBDEVINIT_TXFFLSH); + + return 0; +} + +static void aic_set_turnaroundtime(uint32_t hclk, uint8_t speed) +{ + uint32_t UsbTrd; + uint32_t tmpreg = 0; + + /* The USBTRD is configured according to the tables below, depending on AHB frequency + used by application. In the low AHB frequency range it is used to stretch enough the USB response + time to IN tokens, the USB turnaround time, so to compensate for the longer AHB read access + latency to the Data FIFO */ + if (speed == USB_ENUM_SPEED_FULL) { + if ((hclk >= 14200000U) && (hclk < 15000000U)) { + /* hclk Clock Range between 14.2-15 MHz */ + UsbTrd = 0xFU; + } else if ((hclk >= 15000000U) && (hclk < 16000000U)) { + /* hclk Clock Range between 15-16 MHz */ + UsbTrd = 0xEU; + } else if ((hclk >= 16000000U) && (hclk < 17200000U)) { + /* hclk Clock Range between 16-17.2 MHz */ + UsbTrd = 0xDU; + } else if ((hclk >= 17200000U) && (hclk < 18500000U)) { + /* hclk Clock Range between 17.2-18.5 MHz */ + UsbTrd = 0xCU; + } else if ((hclk >= 18500000U) && (hclk < 20000000U)) { + /* hclk Clock Range between 18.5-20 MHz */ + UsbTrd = 0xBU; + } else if ((hclk >= 20000000U) && (hclk < 21800000U)) { + /* hclk Clock Range between 20-21.8 MHz */ + UsbTrd = 0xAU; + } else if ((hclk >= 21800000U) && (hclk < 24000000U)) { + /* hclk Clock Range between 21.8-24 MHz */ + UsbTrd = 0x9U; + } else if ((hclk >= 24000000U) && (hclk < 27700000U)) { + /* hclk Clock Range between 24-27.7 MHz */ + UsbTrd = 0x8U; + } else if ((hclk >= 27700000U) && (hclk < 32000000U)) { + /* hclk Clock Range between 27.7-32 MHz */ + UsbTrd = 0x7U; + } else {/* if(hclk >= 32000000) */ + /* hclk Clock Range between 32-200 MHz */ + UsbTrd = 0x6U; + } + } else if (speed == USB_ENUM_SPEED_HIGH) { + UsbTrd = USBPHYIF_HS_TRDT_VALUE; + } else { + UsbTrd = USBPHYIF_DEFAULT_TRDT_VALUE; + } + + tmpreg = readl(&AIC_UDC_REG->usbphyif); + tmpreg |= USBPHYIF_TOUTCAL_LIMIT; + tmpreg &= ~USBPHYIF_USBTRDTIM_MASK; + tmpreg |= (uint32_t)((UsbTrd << USBPHYIF_USBTRDTIM_SHIFT) + & USBPHYIF_USBTRDTIM_MASK); + writel(tmpreg, &AIC_UDC_REG->usbphyif); +} + +#if 0 +static void aic_set_txfifo(uint8_t fifo, uint16_t size) +{ + uint8_t i; + uint32_t Tx_Offset; + + /* TXn min size = 16 words. (n : Transmit FIFO index) + When a TxFIFO is not used, the Configuration should be as follows: + case 1 : n > m and Txn is not used (n,m : Transmit FIFO indexes) + --> Txm can use the space allocated for Txn. + case2 : n < m and Txn is not used (n,m : Transmit FIFO indexes) + --> Txn should be configured with the minimum space of 16 words + The FIFO is used optimally when used TxFIFOs are allocated in the top + of the FIFO.Ex: use EP1 and EP2 as IN instead of EP1 and EP3 as IN ones. + When DMA is used 3n * FIFO locations should be reserved for internal DMA registers */ + + Tx_Offset = AIC_UDC_REG->rxfifosiz; + + if (fifo == 0U) { + AIC_UDC_REG->nptxfifosiz = ((uint32_t)size << 16) | Tx_Offset; + } else { + Tx_Offset += (AIC_UDC_REG->nptxfifosiz) >> 16; + for (i = 0U; i < (fifo - 1U); i++) { + Tx_Offset += (AIC_UDC_REG->txfifosiz[i] >> 16); + } + + /* Multiply Tx_Size by 2 to get higher performance */ + AIC_UDC_REG->txfifosiz[fifo - 1U] = ((uint32_t)size << 16) | Tx_Offset; + } +} +#endif + +static uint8_t aic_get_devspeed(void) +{ + uint8_t speed; + uint32_t DevEnumSpeed = readl(&AIC_UDC_REG->usblinests); + + DevEnumSpeed &= USB_ENUM_SPEED_MASK; + if (DevEnumSpeed == USB_HIGH_30_60MHZ) { + speed = USB_ENUM_SPEED_HIGH; + } else if (DevEnumSpeed == USB_FULL_30_60MHZ) { + speed = USB_ENUM_SPEED_FULL; + } else { + speed = 0xFU; + } + + return speed; +} + +static void aic_ep0_start_read_setup(uint8_t *psetup) +{ + uint32_t outepcfg = 0; + + g_aic_udc.out_ep[0].xfer_buf = psetup; + g_aic_udc.out_ep[0].xfer_len = 8; + ep0_ctrl_stage = AIC_EP0_SETUP; + + USB_LOG_DBG("\r\n"); + USB_LOG_DBG("[1]: Control transfer start read setup."); + + aic_udc_dcache_invalidate((uintptr_t)psetup, CACHE_LINE_SIZE); + + writel((1<<29) | (DXEPTSIZ_PKT_CNT_MASK & (1U << 19)) | (8U), &AIC_UDC_REG->outeptsfsiz[0]); + +#ifdef CONFIG_USB_AIC_DMA_ENABLE + writel((uint32_t)(uintptr_t)psetup, &AIC_UDC_REG->outepdmaaddr[0]); +#endif + writel(0xFFFFFFFFU, &AIC_UDC_REG->outepint[0]); + + /* EP enable */ + outepcfg = readl(&AIC_UDC_REG->outepcfg[0]); + outepcfg |= DEPCTL_CNAK | DEPCTL_EPENA | DEPCTL_USBACTEP; + writel(outepcfg, &AIC_UDC_REG->outepcfg[0]); +} + +void aic_ep_write(uint8_t ep_idx, uint8_t *src, uint16_t len) +{ + uint32_t *pSrc = (uint32_t *)src; + uint32_t count32b, i; + + count32b = ((uint32_t)len + 3U) / 4U; + for (i = 0U; i < count32b; i++) { + AIC_EP_FIFO(ep_idx) = __UNALIGNED_UINT32_READ(pSrc); + pSrc++; + } +} + +void aic_ep_read(uint8_t *dest, uint16_t len) +{ + uint32_t *pDest = (uint32_t *)dest; + uint32_t i; + uint32_t count32b = ((uint32_t)len + 3U) / 4U; + + for (i = 0U; i < count32b; i++) { + __UNALIGNED_UINT32_WRITE(pDest, AIC_EP_FIFO(0U)); + pDest++; + } +} + +#ifndef CONFIG_USB_AIC_DMA_ENABLE +static void aic_tx_fifo_empty_procecss(uint8_t ep_idx) +{ + uint32_t len; + //uint32_t len32b; + + len = g_aic_udc.in_ep[ep_idx].xfer_len - g_aic_udc.in_ep[ep_idx].actual_xfer_len; + if (len > g_aic_udc.in_ep[ep_idx].ep_mps) { + len = g_aic_udc.in_ep[ep_idx].ep_mps; + } + + //len32b = (len + 3U) / 4U; + + while (/*((AIC_UDC_REG->ineptxsts[ep_idx] & INEPTXSTS_IN_EP_TXFIFO_STS) >= len32b) &&*/ + (g_aic_udc.in_ep[ep_idx].actual_xfer_len < g_aic_udc.in_ep[ep_idx].xfer_len) && (g_aic_udc.in_ep[ep_idx].xfer_len != 0U)) { + /* Write the FIFO */ + len = g_aic_udc.in_ep[ep_idx].xfer_len - g_aic_udc.in_ep[ep_idx].actual_xfer_len; + if (len > g_aic_udc.in_ep[ep_idx].ep_mps) { + len = g_aic_udc.in_ep[ep_idx].ep_mps; + } + + aic_ep_write(ep_idx, g_aic_udc.in_ep[ep_idx].xfer_buf, len); + g_aic_udc.in_ep[ep_idx].xfer_buf += len; + g_aic_udc.in_ep[ep_idx].actual_xfer_len += len; + } +} +#endif + +/** + * @brief aic_get_glb_intstatus: return the global USB interrupt status + * @retval status + */ +static inline uint32_t aic_get_glb_intstatus(void) +{ + uint32_t tmpreg; + uint32_t mask; + + tmpreg = readl(&AIC_UDC_REG->usbintsts); + mask = readl(&AIC_UDC_REG->usbintmsk); + + return tmpreg & mask; +} + +/** + * @brief aic_get_outeps_intstatus: return the USB device OUT endpoints interrupt status + * @retval status + */ +static inline uint32_t aic_get_outeps_intstatus(void) +{ + uint32_t tmpreg; + uint32_t mask; + + tmpreg = readl(&AIC_UDC_REG->usbepint); + mask = readl(&AIC_UDC_REG->usbepintmsk); + + return (((tmpreg & mask) & 0xffff0000U) >> 16); +} + +/** + * @brief aic_get_ineps_intstatus: return the USB device IN endpoints interrupt status + * @retval status + */ +static inline uint32_t aic_get_ineps_intstatus(void) +{ + uint32_t tmpreg; + uint32_t mask; + + tmpreg = readl(&AIC_UDC_REG->usbepint); + mask = readl(&AIC_UDC_REG->usbepintmsk); + + return ((tmpreg & mask) & 0xFFFFU); +} + +/** + * @brief Returns Device OUT EP Interrupt register + * @param epnum endpoint number + * This parameter can be a value from 0 to 15 + * @retval Device OUT EP Interrupt register + */ +static inline uint32_t aic_get_outep_intstatus(uint8_t epnum) +{ + uint32_t tmpreg; + uint32_t mask; + + tmpreg = readl(&AIC_UDC_REG->outepint[epnum]); + USB_LOG_DBG("[int]: Out ep%d outepint = 0x%x [%d].", epnum, tmpreg, ep0_ctrl_stage); + mask = readl(&AIC_UDC_REG->outepintmsk); + + return tmpreg & mask; +} + +/** + * @brief Returns Device IN EP Interrupt register + * @param epnum endpoint number + * This parameter can be a value from 0 to 15 + * @retval Device IN EP Interrupt register + */ +static inline uint32_t aic_get_inep_intstatus(uint8_t epnum) +{ + uint32_t tmpreg; + uint32_t mask; + + tmpreg = readl(&AIC_UDC_REG->inepint[epnum]); + USB_LOG_DBG("[int]: In ep%d inepint = 0x%x [%d].", epnum, tmpreg, ep0_ctrl_stage); + mask = readl(&AIC_UDC_REG->inepintmsk); + + return tmpreg & mask; +} + +__WEAK void usb_dc_low_level_init(void) +{ +} + +__WEAK void usb_dc_low_level_deinit(void) +{ +} + +int usb_dc_rst(void) +{ + uint32_t outepintmsk = 0; + uint32_t inepintmsk = 0; + + USB_LOG_DBG("usb_dc_rst.\n"); + + usbd_set_address(0); + + aic_flush_txfifo(0x10U); + aic_flush_rxfifo(); + + for (uint8_t i = 0U; i < USB_NUM_BIDIR_ENDPOINTS; i++) { + if (i == 0U) { + writel(DEPCTL_SNAK, &AIC_UDC_REG->inepcfg[i]); + writel(DEPCTL_SNAK, &AIC_UDC_REG->outepcfg[i]); + } else { + usbd_ep_close(i); + usbd_ep_close(i | 0x80); + } + + writel(0U, &AIC_UDC_REG->ineptsfsiz[i]); + writel(0xFFFFFFFFU, &AIC_UDC_REG->inepint[i]); + writel(0U, &AIC_UDC_REG->outeptsfsiz[i]); + writel(0xFFFFFFFFU, &AIC_UDC_REG->outepint[i]); + } + + writel(0, &AIC_UDC_REG->usbepintmsk); + outepintmsk = TRANSFER_DONE | CTRL_OUT_EP_SETUP_PHASE_DONE | CTRL_OUT_EP_STATUS_PHASE_RCVD; + inepintmsk = TRANSFER_DONE | NON_ISO_IN_EP_TIMEOUT | INTKNEPMIS; +#ifndef CONFIG_USB_AIC_DMA_ENABLE + outepintmsk |= CTRL_OUT_EP_SETUP_PHASE_DONE; + inepintmsk |= INTKN_TXFEMP; +#endif + writel(outepintmsk, &AIC_UDC_REG->outepintmsk); + writel(inepintmsk, &AIC_UDC_REG->inepintmsk); + + aic_set_dma_nextep(); + +#ifdef CONFIG_USB_AIC_DMA_ENABLE + for (uint8_t i = 0U; i < USB_NUM_BIDIR_ENDPOINTS; i++) { + aic_udc_obuf_free(&g_aic_udc.out_ep[i]); + aic_udc_ibuf_free(&g_aic_udc.in_ep[i]); + } +#endif + + memset(&g_aic_udc, 0, sizeof(struct aic_udc)); + usbd_event_reset_handler(0); + /* Start reading setup */ + aic_ep0_start_read_setup((uint8_t *)&g_aic_udc.setup); + + return 0; +} + +int usb_dc_init(uint8_t busid) +{ + int ret; + uint32_t base = 0; + uint32_t tmpreg = 0; + + memset(&g_aic_udc, 0, sizeof(struct aic_udc)); + + usb_dc_low_level_init(); + + /* Disconnect */ + tmpreg = readl(&AIC_UDC_REG->usbdevfunc); + tmpreg |= USBDEVFUNC_SFTDISCON; + writel(tmpreg, &AIC_UDC_REG->usbdevfunc); + /* Disable Interrupt */ + tmpreg = readl(&AIC_UDC_REG->usbdevinit); + tmpreg &= ~USBDEVINIT_GLBL_INTR_EN; + writel(tmpreg, &AIC_UDC_REG->usbdevinit); + + ret = aic_core_init(); + + for (uint8_t i = 0U; i < 2U; i++) { + writel(0, &AIC_UDC_REG->txfifosiz[i]); + } + + /* Device mode configuration */ + tmpreg = readl(&AIC_UDC_REG->usbdevconf); + tmpreg |= PERIOD_FRAME_INTERVAL_80; + +#if defined(CONFIG_USB_HS) + /* Set Core speed to High speed mode */ + tmpreg |= DEV_SPEED_HIGH_SPEED_20; +#else + tmpreg |= DEV_SPEED_FULL_SPEED_20; +#endif + writel(tmpreg, &AIC_UDC_REG->usbdevconf); + + ret = aic_flush_txfifo(0x10U); + ret = aic_flush_rxfifo(); + + /* Clear all pending Device Interrupts */ + writel(0, &AIC_UDC_REG->inepintmsk); + writel(0, &AIC_UDC_REG->outepintmsk); + writel(0, &AIC_UDC_REG->usbepintmsk); + + /* Disable all interrupts. */ + writel(0, &AIC_UDC_REG->usbintmsk); + /* Clear any pending interrupts */ + writel(0xBFFFFFFFU, &AIC_UDC_REG->usbintsts); + + /* Enable interrupts matching to the Device mode ONLY */ + tmpreg = INT_RESET | INT_ENUMDONE | + INT_OUT_EP | INT_IN_EP | + INT_INCOMP_ISO_IN_INT | INT_INCOMP_ISO_OUT_INT | INT_SUSPEND; + writel(tmpreg, &AIC_UDC_REG->usbintmsk); + +#ifdef CONFIG_USB_AIC_DMA_ENABLE + tmpreg = readl(&AIC_UDC_REG->usbdevinit); + tmpreg |= (USBDEVINIT_HBSTLEN_INCR4 << USBDEVINIT_HBSTLEN_SHIFT); + tmpreg |= USBDEVINIT_DMA_EN; + writel(tmpreg, &AIC_UDC_REG->usbdevinit); +#else + tmpreg = readl(&AIC_UDC_REG->usbintmsk); + tmpreg |= INT_RX_FIFO_NOT_EMPTY; + writel(tmpreg, &AIC_UDC_REG->usbintmsk); +#endif + + /* Assign FIFO */ + base = 0; + writel(AIC_RX_FIFO_SIZE, &AIC_UDC_REG->rxfifosiz); + base += AIC_RX_FIFO_SIZE; + writel((AIC_NP_TX_FIFO_SIZE << 16) | base, &AIC_UDC_REG->nptxfifosiz); + base += AIC_NP_TX_FIFO_SIZE; + writel((AIC_PERIOD_TX_FIFO1_SIZE << 16) | base, &AIC_UDC_REG->txfifosiz[0]); + base += AIC_PERIOD_TX_FIFO1_SIZE; + writel((AIC_PERIOD_TX_FIFO2_SIZE << 16) | base, &AIC_UDC_REG->txfifosiz[1]); + + usb_dc_rst(); + + /* Enable Interrupt */ + tmpreg = readl(&AIC_UDC_REG->usbdevinit); + tmpreg |= USBDEVINIT_GLBL_INTR_EN; + writel(tmpreg, &AIC_UDC_REG->usbdevinit); + /* Connect */ + tmpreg = readl(&AIC_UDC_REG->usbdevfunc); + tmpreg &= ~USBDEVFUNC_SFTDISCON; + writel(tmpreg, &AIC_UDC_REG->usbdevfunc); + + return ret; +} + +int usb_dc_deinit(uint8_t busid) +{ + uint32_t tmpreg = 0; + + usbd_event_suspend_handler(); + + /* Clear Pending interrupt */ + for (uint8_t i = 0U; i < USB_NUM_BIDIR_ENDPOINTS; i++) { + writel(0xFB7FU, &AIC_UDC_REG->outepint[i]); + writel(0xFB7FU, &AIC_UDC_REG->inepint[i]); + } + + /* Clear interrupt masks */ + writel(0, &AIC_UDC_REG->inepintmsk); + writel(0, &AIC_UDC_REG->outepintmsk); + writel(0, &AIC_UDC_REG->usbepintmsk); + + /* Flush the FIFO */ + aic_flush_txfifo(0x10U); + aic_flush_rxfifo(); + + tmpreg = readl(&AIC_UDC_REG->usbdevfunc); + tmpreg |= USBDEVFUNC_SFTDISCON; + writel(tmpreg, &AIC_UDC_REG->usbdevfunc); + + usb_dc_low_level_deinit(); + return 0; +} + +int usbd_set_address(uint8_t busid, const uint8_t addr) +{ + uint32_t tmpreg = 0; + + tmpreg = readl(&AIC_UDC_REG->usbdevconf); + tmpreg &= ~(DEVICE_ADDRESS_MASK); + tmpreg |= ((uint32_t)addr << 4) & DEVICE_ADDRESS_MASK; + writel(tmpreg, &AIC_UDC_REG->usbdevconf); + + return 0; +} + +uint8_t usbd_get_port_speed(uint8_t busid, const uint8_t port) +{ + uint8_t speed; + uint32_t DevEnumSpeed = readl(&AIC_UDC_REG->usblinests); + + DevEnumSpeed &= USB_ENUM_SPEED_MASK; + + if (DevEnumSpeed == USB_HIGH_30_60MHZ) { + speed = USB_SPEED_HIGH; + } else if (DevEnumSpeed == USB_FULL_30_60MHZ) { + speed = USB_SPEED_FULL; + } else { + speed = USB_SPEED_FULL; + } + + return speed; +} + +int usbd_ep_open(uint8_t busid, const struct usb_endpoint_descriptor *ep) +{ + uint8_t ep_idx = USB_EP_GET_IDX(ep->bEndpointAddress); + uint16_t ep_mps; + uint8_t tx_fifo_num = 0; + uint32_t i; + uint32_t usbepintmsk = 0; + uint32_t epcfg = 0; + + if (ep_idx > (USB_NUM_BIDIR_ENDPOINTS - 1)) { + USB_LOG_ERR("Ep addr %d overflow\r\n", ep->bEndpointAddress); + return -1; + } + + ep_mps = USB_GET_MAXPACKETSIZE(ep->wMaxPacketSize); + if (ep_idx == 0) { + switch (ep_mps) { + case 8: + ep_mps = DEPCTL0_MPS_8; + break; + case 16: + ep_mps = DEPCTL0_MPS_16; + break; + case 32: + ep_mps = DEPCTL0_MPS_32; + break; + case 64: + ep_mps = DEPCTL0_MPS_64; + break; + } + } + + usbepintmsk = readl(&AIC_UDC_REG->usbepintmsk); + if (USB_EP_DIR_IS_OUT(ep->bEndpointAddress)) { + g_aic_udc.out_ep[ep_idx].ep_mps = USB_GET_MAXPACKETSIZE(ep->wMaxPacketSize); + g_aic_udc.out_ep[ep_idx].ep_type = USB_GET_ENDPOINT_TYPE(ep->bmAttributes); + + usbepintmsk |= DAINT_OUT_MASK & (uint32_t)(1UL << (16 + ep_idx)); + writel(usbepintmsk, &AIC_UDC_REG->usbepintmsk); + epcfg = readl(&AIC_UDC_REG->outepcfg[ep_idx]); + epcfg |= (ep_mps & DEPCTL_MPS_MASK) | + ((uint32_t)USB_GET_ENDPOINT_TYPE(ep->bmAttributes) << 18) | + DEPCTL_SETD0PID | + DEPCTL_USBACTEP; + writel(epcfg, &AIC_UDC_REG->outepcfg[ep_idx]); + } else { + g_aic_udc.in_ep_desc[ep_idx] = *ep; + g_aic_udc.in_ep[ep_idx].ep_mps = USB_GET_MAXPACKETSIZE(ep->wMaxPacketSize); + g_aic_udc.in_ep[ep_idx].ep_type = USB_GET_ENDPOINT_TYPE(ep->bmAttributes); + + usbepintmsk |= DAINT_IN_MASK & (uint32_t)(1UL << ep_idx); + writel(usbepintmsk, &AIC_UDC_REG->usbepintmsk); + + /* Period IN EP alloc fifo num */ + if ((USB_GET_ENDPOINT_TYPE(ep->bmAttributes) == USB_ENDPOINT_TYPE_INTERRUPT) || + (USB_GET_ENDPOINT_TYPE(ep->bmAttributes) == USB_ENDPOINT_TYPE_ISOCHRONOUS)) { + for (i = 1; i <= USB_P_TXFIFO_NUM; i++) { + if (g_aic_udc.p_txfifo_map & (1 << i)) + continue; + g_aic_udc.p_txfifo_map |= (1 << i); + tx_fifo_num = i; + break; + } + + if (tx_fifo_num == 0) + return -1; + + aic_flush_txfifo(tx_fifo_num); + } else { + g_aic_udc.np_txfifo_map |= (1 << ep_idx); + } + + epcfg = readl(&AIC_UDC_REG->inepcfg[ep_idx]); + epcfg |= (ep_mps & DEPCTL_MPS_MASK) | + ((uint32_t)USB_GET_ENDPOINT_TYPE(ep->bmAttributes) << 18) | + (tx_fifo_num << 22) | + DEPCTL_SETD0PID | + DEPCTL_USBACTEP; + writel(epcfg, &AIC_UDC_REG->inepcfg[ep_idx]); + } + return 0; +} + +int usbd_ep_close(uint8_t busid, const uint8_t ep) +{ + uint8_t ep_idx = USB_EP_GET_IDX(ep); + uint8_t tx_fifo_num = 0; + int i = 0; + uint32_t outepcfg = 0; + uint32_t outepint = 0; + uint32_t inepcfg = 0; + uint32_t inepint = 0; + uint32_t usbintsts = 0; + uint32_t usbdevfunc = 0; + uint32_t usbepintmsk = 0; + + #define DIS_EP_TIMOUT 100 + + if (USB_EP_DIR_IS_OUT(ep)) { + outepcfg = readl(&AIC_UDC_REG->outepcfg[ep_idx]); + if (outepcfg & DEPCTL_EPENA) { + /* (1) Wait for global nak to take effect */ + usbintsts = readl(&AIC_UDC_REG->usbintsts); + if (!(usbintsts & INT_GOUTNAKEFF)) { + usbdevfunc = readl(&AIC_UDC_REG->usbdevfunc); + usbdevfunc |= USBDEVFUNC_SGOUTNAK; + writel(usbdevfunc, &AIC_UDC_REG->usbdevfunc); + } + + for (i = 0; i < DIS_EP_TIMOUT; i++) { + usbintsts = readl(&AIC_UDC_REG->usbintsts); + if (usbintsts & INT_GOUTNAKEFF) + break; + aic_udelay(1); + } + + if (i == DIS_EP_TIMOUT) + USB_LOG_ERR("%s: timeout USBINTSTS.GOUTNAKEFF\n", __func__); + + /* (2) Disable ep */ + outepcfg = readl(&AIC_UDC_REG->outepcfg[ep_idx]); + outepcfg |= DEPCTL_SNAK; + outepcfg |= DEPCTL_EPDIS; + writel(outepcfg, &AIC_UDC_REG->outepcfg[ep_idx]); + + for (i = 0; i < DIS_EP_TIMOUT*10; i++) { + outepint = readl(&AIC_UDC_REG->outepint[ep_idx]); + if (outepint & EPDISBLD) + break; + aic_udelay(1); + } + + if (i == DIS_EP_TIMOUT) + USB_LOG_ERR("%s: timeout OUTEPCFG.EPDisable\n", __func__); + + /* Clear EPDISBLD interrupt */ + outepint = readl(&AIC_UDC_REG->outepint[ep_idx]); + outepint |= EPDISBLD; + writel(outepint, &AIC_UDC_REG->outepint[ep_idx]); + + /* (3) Remove global NAKs */ + usbdevfunc = readl(&AIC_UDC_REG->usbdevfunc); + usbdevfunc |= USBDEVFUNC_CGOUTNAK; + writel(usbdevfunc, &AIC_UDC_REG->usbdevfunc); + } + + usbepintmsk = readl(&AIC_UDC_REG->usbepintmsk); + usbepintmsk &= ~(DAINT_OUT_MASK & (uint32_t)(1UL << (16 + ep_idx))); + writel(usbepintmsk, &AIC_UDC_REG->usbepintmsk); + writel(0, &AIC_UDC_REG->outepcfg[ep_idx]); + } else { + inepcfg = readl(&AIC_UDC_REG->inepcfg[ep_idx]); + tx_fifo_num = (inepcfg & DEPCTL_TXFIFONUM_MASK) >> DEPCTL_TXFIFONUM_SHIFT; + + inepcfg = readl(&AIC_UDC_REG->inepcfg[ep_idx]); + if (inepcfg & DEPCTL_EPENA) { + if (tx_fifo_num) { + /* (1) Wait for Nak effect */ + inepcfg |= DEPCTL_SNAK; + writel(inepcfg, &AIC_UDC_REG->inepcfg[ep_idx]); + + for (i = 0; i < DIS_EP_TIMOUT; i++) { + inepint = readl(&AIC_UDC_REG->inepint[ep_idx]); + if (inepint & INEP_NAKEFF) + break; + aic_udelay(1); + } + + if (i == DIS_EP_TIMOUT) + USB_LOG_ERR("%s: timeout INEPINT.NAKEFF\n", __func__); + } else { + /* (1) Wait for Nak effect */ + usbdevfunc = readl(&AIC_UDC_REG->usbdevfunc); + usbdevfunc |= USBDEVFUNC_SGNPINNAK; + writel(usbdevfunc, &AIC_UDC_REG->usbdevfunc); + + for (i = 0; i < DIS_EP_TIMOUT; i++) { + usbintsts = readl(&AIC_UDC_REG->usbintsts); + if (usbintsts & INT_GINNAKEFF) + break; + aic_udelay(1); + } + + if (i == DIS_EP_TIMOUT) + USB_LOG_ERR("%s: timeout USBINTSTS.GOUTNAKEFF\n", __func__); + } + + /* (2) Disable ep */ + inepcfg = readl(&AIC_UDC_REG->inepcfg[ep_idx]); + inepcfg |= DEPCTL_SNAK; + inepcfg |= DEPCTL_EPDIS; + writel(inepcfg, &AIC_UDC_REG->inepcfg[ep_idx]); + + for (i = 0; i < DIS_EP_TIMOUT; i++) { + inepint = readl(&AIC_UDC_REG->inepint[ep_idx]); + if (inepint & EPDISBLD) + break; + aic_udelay(1); + } + + if (i == DIS_EP_TIMOUT) + USB_LOG_ERR("%s: timeout OUTEPCFG.EPDisable\n", __func__); + + /* Clear EPDISBLD interrupt */ + inepint = readl(&AIC_UDC_REG->inepint[ep_idx]); + inepint |= EPDISBLD; + writel(inepint, &AIC_UDC_REG->inepint[ep_idx]); + + /* (3) Flush TX FIFO */ + aic_flush_txfifo(tx_fifo_num); + + /* Period IN EP free fifo num */ + if (tx_fifo_num > 0) + g_aic_udc.p_txfifo_map &= ~(1 << tx_fifo_num); + else + g_aic_udc.np_txfifo_map &= ~(1 << ep_idx); + + /* (4) Clear Global In NP NAK in Shared FIFO for non periodic ep */ + if (!tx_fifo_num) { + usbdevfunc = readl(&AIC_UDC_REG->usbdevfunc); + usbdevfunc |= USBDEVFUNC_CGNPINNAK; + writel(usbdevfunc, &AIC_UDC_REG->usbdevfunc); + } + } + + usbepintmsk = readl(&AIC_UDC_REG->usbepintmsk); + usbepintmsk &= ~(DAINT_OUT_MASK & (uint32_t)(1UL << ep_idx)); + writel(usbepintmsk, &AIC_UDC_REG->usbepintmsk); + writel(0, &AIC_UDC_REG->inepcfg[ep_idx]); + } + +#ifdef CONFIG_USB_AIC_DMA_ENABLE + if (USB_EP_DIR_IS_OUT(ep)) { + aic_udc_obuf_free(&g_aic_udc.out_ep[ep_idx]); + } else { + aic_udc_ibuf_free(&g_aic_udc.in_ep[ep_idx]); + } +#endif + + return 0; +} + +int usbd_npinep_rewrite(const uint8_t ep) +{ + int i = 0; + int j = 0; + int fail = 0; + unsigned int pending_map = 0; + //int data_len = 0; + uint32_t tmpreg = 0; + + for (i = 0U, j = 0; i < USB_NUM_BIDIR_ENDPOINTS; i++) { + tmpreg = readl(&AIC_UDC_REG->inepcfg[i]); + if (!((g_aic_udc.np_txfifo_map & (1 << i)) && + (tmpreg & DEPCTL_EPENA))) + continue; + + j++; + + pending_map |= (1 << i); + } + if (j <= 1) + return 0; + + /* (1) close all no-periodic ep */ + /* (1.1) Set Global In NP NAK in Shared FIFO for non periodic ep */ + tmpreg = readl(&AIC_UDC_REG->usbdevfunc); + tmpreg |= USBDEVFUNC_SGNPINNAK; + writel(tmpreg, &AIC_UDC_REG->usbdevfunc); + + for (i = 0; i < DIS_EP_TIMOUT; i++) { + tmpreg = readl(&AIC_UDC_REG->usbintsts); + if (tmpreg & INT_GINNAKEFF) + break; + aic_udelay(1); + } + + if (i == DIS_EP_TIMOUT) + USB_LOG_ERR("%s: timeout USBINTSTS.GOUTNAKEFF\n", __func__); + + /* (1.2) Disable ep */ + for (i = 0U; i < USB_NUM_BIDIR_ENDPOINTS; i++) { + tmpreg = readl(&AIC_UDC_REG->inepcfg[i]); + if (!((g_aic_udc.np_txfifo_map & (1 << i)) && + (tmpreg & DEPCTL_EPENA))) + continue; + + tmpreg |= DEPCTL_SNAK; + tmpreg |= DEPCTL_EPDIS; + writel(tmpreg, &AIC_UDC_REG->inepcfg[i]); + + /* remain data */ + #if 0 + tmpreg = readl(&AIC_UDC_REG->ineptsfsiz[i]); + data_len = tmpreg & DXEPTSIZ_XFER_SIZE_MASK; + g_aic_udc.in_ep[ep].xfer_buf += g_aic_udc.in_ep[ep].xfer_len - data_len; + g_aic_udc.in_ep[ep].xfer_len = data_len; + #endif + + //pending_map |= (1 << i); + } + + for (j = 0; j < DIS_EP_TIMOUT; j++) { + fail = 0; + for (i = 0U; i < USB_NUM_BIDIR_ENDPOINTS; i++) { + if (!(pending_map & (1 << i))) + continue; + tmpreg = readl(&AIC_UDC_REG->inepint[i]); + if (!(tmpreg & EPDISBLD)) { + fail = i+1; + break; + } + } + if (!fail) + break; + aic_udelay(1); + } + + if (j == DIS_EP_TIMOUT) + USB_LOG_ERR("%s: ep%d timeout OUTEPCFG.EPDisable\n", __func__, fail-1); + + /* Clear EPDISBLD interrupt */ + for (i = 0U; i < USB_NUM_BIDIR_ENDPOINTS; i++) { + if (!(pending_map & (1 << i))) + continue; + tmpreg = readl(&AIC_UDC_REG->inepint[i]); + tmpreg |= EPDISBLD; + writel(tmpreg, &AIC_UDC_REG->inepint[i]); + } + + /* (1.3) Flush TX FIFO0 */ + aic_flush_txfifo(0); + + /* (1.4) Clear Global In NP NAK in Shared FIFO for non periodic ep */ + tmpreg = readl(&AIC_UDC_REG->usbdevfunc); + tmpreg |= USBDEVFUNC_CGNPINNAK; + writel(tmpreg, &AIC_UDC_REG->usbdevfunc); + + /* (2) reopen current ep */ + usbd_ep_open(&g_aic_udc.in_ep_desc[ep]); + + /* (3) rewrite current ep */ + if (pending_map & (1 << ep)) { + usbd_ep_start_write(ep, g_aic_udc.in_ep[ep].xfer_buf, + g_aic_udc.in_ep[ep].xfer_len); + } + + /* (4) reopen & rewrite other ep, let's receive ep mismtach interrupt */ + for (i = 0U; i < USB_NUM_BIDIR_ENDPOINTS; i++) { + if (!(pending_map & (1 << i)) || + (i == ep)) + continue; + usbd_ep_open(&g_aic_udc.in_ep_desc[i]); + usbd_ep_start_write(i, g_aic_udc.in_ep[i].xfer_buf, + g_aic_udc.in_ep[i].xfer_len); + } + + return 0; +} + +int usbd_ep_set_stall(uint8_t busid, const uint8_t ep) +{ + uint8_t ep_idx = USB_EP_GET_IDX(ep); + uint32_t tmpreg = 0; + + if (USB_EP_DIR_IS_OUT(ep)) { + tmpreg = readl(&AIC_UDC_REG->outepcfg[ep_idx]); + if (((tmpreg & DEPCTL_EPENA) == 0U) && (ep_idx != 0U)) { + tmpreg &= ~(DEPCTL_EPDIS); + } + tmpreg |= DEPCTL_STALL; + writel(tmpreg, &AIC_UDC_REG->outepcfg[ep_idx]); + } else { + tmpreg = readl(&AIC_UDC_REG->inepcfg[ep_idx]); + if (((tmpreg & DEPCTL_EPENA) == 0U) && (ep_idx != 0U)) { + tmpreg &= ~(DEPCTL_EPDIS); + } + tmpreg |= DEPCTL_STALL; + writel(tmpreg, &AIC_UDC_REG->inepcfg[ep_idx]); + } + +#ifdef CONFIG_USB_AIC_DMA_ENABLE + if (ep_idx == 0) { + aic_ep0_start_read_setup((uint8_t *)&g_aic_udc.setup); + } +#endif + return 0; +} + +int usbd_ep_clear_stall(uint8_t busid, const uint8_t ep) +{ + uint8_t ep_idx = USB_EP_GET_IDX(ep); + uint32_t tmpreg = 0; + + if (USB_EP_DIR_IS_OUT(ep)) { + tmpreg = readl(&AIC_UDC_REG->outepcfg[ep_idx]); + tmpreg &= ~DEPCTL_STALL; + if ((g_aic_udc.out_ep[ep_idx].ep_type == USB_ENDPOINT_TYPE_INTERRUPT) || + (g_aic_udc.out_ep[ep_idx].ep_type == USB_ENDPOINT_TYPE_BULK)) { + tmpreg |= DEPCTL_SETD0PID; /* DATA0 */ + } + writel(tmpreg, &AIC_UDC_REG->outepcfg[ep_idx]); + } else { + tmpreg = readl(&AIC_UDC_REG->inepcfg[ep_idx]); + tmpreg &= ~DEPCTL_STALL; + if ((g_aic_udc.in_ep[ep_idx].ep_type == USB_ENDPOINT_TYPE_INTERRUPT) || + (g_aic_udc.in_ep[ep_idx].ep_type == USB_ENDPOINT_TYPE_BULK)) { + tmpreg |= DEPCTL_SETD0PID; /* DATA0 */ + } + writel(tmpreg, &AIC_UDC_REG->inepcfg[ep_idx]); + } + + return 0; +} + +int usbd_ep_is_stalled(uint8_t busid, const uint8_t ep, uint8_t *stalled) +{ + if (USB_EP_DIR_IS_OUT(ep)) { + } else { + } + return 0; +} + +int usbd_ep_start_write_raw(const uint8_t ep, const uint8_t *data, uint32_t data_len, uint8_t cache_align) +{ + uint8_t ep_idx = USB_EP_GET_IDX(ep); + uint32_t pktcnt = 0; + uint32_t inepcfg = 0; + uint32_t ineptsfsiz = 0; + uint32_t usblinests = 0; + + if (!data && data_len) { + return -1; + } + inepcfg = readl(&AIC_UDC_REG->inepcfg[ep_idx]); + if (inepcfg & DEPCTL_EPENA) { + return -2; + } + if (ep_idx && !(inepcfg & DEPCTL_MPS_MASK)) { + return -3; + } + if ((uint32_t)(uintptr_t)data & 0x03) { + return -4; + } + + g_aic_udc.in_ep[ep_idx].xfer_buf = (uint8_t *)data; + g_aic_udc.in_ep[ep_idx].xfer_len = data_len; + g_aic_udc.in_ep[ep_idx].actual_xfer_len = 0; + +#ifdef CONFIG_USB_AIC_DMA_ENABLE + if (cache_align && (ep_idx != 0) && (data_len > 0) && + ((((uint32_t)(uintptr_t)data % CACHE_LINE_SIZE) != 0) || + (((uint32_t)(uintptr_t)(data + data_len) % CACHE_LINE_SIZE) != 0))) { + + if (g_aic_udc.in_ep[ep_idx].xfer_align_len != data_len) { + int ret = 0; + + aic_udc_ibuf_free(&g_aic_udc.in_ep[ep_idx]); + ret = aic_udc_ibuf_alloc(&g_aic_udc.in_ep[ep_idx], data_len); + if (ret) + return ret; + } + memcpy(g_aic_udc.in_ep[ep_idx].xfer_align_buf, data, data_len); + data = g_aic_udc.in_ep[ep_idx].xfer_align_buf; + } else { + aic_udc_ibuf_free(&g_aic_udc.in_ep[ep_idx]); + } + + if (data_len>0) + aic_udc_dcache_clean((uintptr_t)data, ALIGN_UP(data_len, CACHE_LINE_SIZE)); +#endif + + ineptsfsiz = readl(&AIC_UDC_REG->ineptsfsiz[ep_idx]); + ineptsfsiz &= ~(DXEPTSIZ_PKT_CNT_MASK); + ineptsfsiz &= ~(DXEPTSIZ_XFER_SIZE_MASK); + + if (data_len == 0) { + ineptsfsiz |= (DXEPTSIZ_PKT_CNT_MASK & (1U << 19)); + writel(ineptsfsiz, &AIC_UDC_REG->ineptsfsiz[ep_idx]); + inepcfg |= (DEPCTL_CNAK | DEPCTL_EPENA); + writel(inepcfg, &AIC_UDC_REG->inepcfg[ep_idx]); + return 0; + } + + if (ep_idx == 0) { + if (data_len > g_aic_udc.in_ep[ep_idx].ep_mps) { + data_len = g_aic_udc.in_ep[ep_idx].ep_mps; + } + g_aic_udc.in_ep[ep_idx].xfer_len = data_len; + ineptsfsiz |= (DXEPTSIZ_PKT_CNT_MASK & (1U << 19)); + ineptsfsiz |= (DXEPTSIZ_XFER_SIZE_MASK & data_len); + } else { + pktcnt = (uint16_t)((data_len + g_aic_udc.in_ep[ep_idx].ep_mps - 1U) / g_aic_udc.in_ep[ep_idx].ep_mps); + + ineptsfsiz |= (DXEPTSIZ_PKT_CNT_MASK & (pktcnt << 19)); + ineptsfsiz |= (DXEPTSIZ_XFER_SIZE_MASK & data_len); + } + + if (g_aic_udc.in_ep[ep_idx].ep_type == USB_ENDPOINT_TYPE_ISOCHRONOUS) { + usblinests = readl(&AIC_UDC_REG->usblinests); + if ((usblinests & (1U << 8)) == 0U) { + inepcfg &= ~DEPCTL_SETD0PID; + inepcfg |= DEPCTL_SETD1PID; + } else { + inepcfg &= ~DEPCTL_SETD1PID; + inepcfg |= DEPCTL_SETD0PID; + } + ineptsfsiz &= ~(DXEPTSIZ_MULCNT_MASK); + ineptsfsiz |= ((pktcnt << DXEPTSIZ_MULCNT_SHIFT) & DXEPTSIZ_MULCNT_MASK); + } else if (g_aic_udc.in_ep[ep_idx].ep_type == USB_ENDPOINT_TYPE_INTERRUPT) { + ineptsfsiz &= ~(DXEPTSIZ_MULCNT_MASK); + ineptsfsiz |= (1U << DXEPTSIZ_MULCNT_SHIFT); + } + writel(ineptsfsiz, &AIC_UDC_REG->ineptsfsiz[ep_idx]); + +#ifdef CONFIG_USB_AIC_DMA_ENABLE + writel((uint32_t)(uintptr_t)data, &AIC_UDC_REG->inepdmaaddr[ep_idx]); +#endif + + writel(0xFFFFFFFFU, &AIC_UDC_REG->inepint[ep_idx]); + + inepcfg |= (DEPCTL_CNAK | DEPCTL_EPENA); + writel(inepcfg, &AIC_UDC_REG->inepcfg[ep_idx]); + + return 0; +} + + +int usbd_ep_start_write(uint8_t busid, const uint8_t ep, const uint8_t *data, uint32_t data_len) +{ + return usbd_ep_start_write_raw(ep, data, data_len, 1); +} + +int usbd_ep_start_read_raw(const uint8_t ep, uint8_t *data, uint32_t data_len, uint8_t cache_align) +{ + uint8_t ep_idx = USB_EP_GET_IDX(ep); + uint32_t pktcnt = 0; + uint32_t i = 0; + uint32_t outepcfg = 0; + uint32_t outeptsfsiz = 0; + uint32_t usblinests = 0; + + if (!data && data_len) { + return -1; + } + outepcfg = readl(&AIC_UDC_REG->outepcfg[ep_idx]); + if (outepcfg & DEPCTL_EPENA) { + for (i = 0; i < 100000; i++) { + outepcfg = readl(&AIC_UDC_REG->outepcfg[ep_idx]); + if (!(outepcfg & DEPCTL_EPENA)) + break; + } + if (i == 1000000) { + g_aic_udc.out_ep[ep_idx].xfer_len = data_len; + USB_LOG_ERR("ep%d AIC_UDC_REG->outepcfg[ep_idx] = 0x%x.\n", + (unsigned int)ep_idx, (unsigned int)outepcfg); + return -2; + } + } + if (ep_idx && !(outepcfg & DEPCTL_MPS_MASK)) { + return -3; + } + if (((uint32_t)(uintptr_t)data) & 0x03) { + return -4; + } + + g_aic_udc.out_ep[ep_idx].xfer_buf = (uint8_t *)data; + g_aic_udc.out_ep[ep_idx].xfer_len = data_len; + g_aic_udc.out_ep[ep_idx].actual_xfer_len = 0; + +#ifdef CONFIG_USB_AIC_DMA_ENABLE + if (cache_align && (ep_idx != 0) && (data_len > 0) && + ((((uint32_t)(uintptr_t)data % CACHE_LINE_SIZE) != 0) || + (((uint32_t)(uintptr_t)(data + data_len) % CACHE_LINE_SIZE) != 0))) { + + if (g_aic_udc.out_ep[ep_idx].xfer_align_len != data_len) { + int ret = 0; + + aic_udc_obuf_free(&g_aic_udc.out_ep[ep_idx]); + ret = aic_udc_obuf_alloc(&g_aic_udc.out_ep[ep_idx], data_len); + if (ret) + return ret; + } + data = g_aic_udc.out_ep[ep_idx].xfer_align_buf; + } else { + aic_udc_obuf_free(&g_aic_udc.out_ep[ep_idx]); + } + + if (data_len > 0) + aic_udc_dcache_invalidate((uintptr_t)data, ALIGN_UP(data_len, CACHE_LINE_SIZE)); +#endif + + outeptsfsiz = readl(&AIC_UDC_REG->outeptsfsiz[ep_idx]); + outeptsfsiz &= ~(DXEPTSIZ_PKT_CNT_MASK); + outeptsfsiz &= ~(DXEPTSIZ_XFER_SIZE_MASK); + outeptsfsiz &= ~(DXEPTSIZ_MULCNT_MASK); + + if (data_len == 0) { + outeptsfsiz |= (DXEPTSIZ_PKT_CNT_MASK & (1 << 19)); + outeptsfsiz |= (DXEPTSIZ_XFER_SIZE_MASK & g_aic_udc.out_ep[ep_idx].ep_mps); + writel(outeptsfsiz, &AIC_UDC_REG->outeptsfsiz[ep_idx]); + outepcfg |= (DEPCTL_CNAK | DEPCTL_EPENA); + writel(outepcfg, &AIC_UDC_REG->outepcfg[ep_idx]); + return 0; + } + + if (ep_idx == 0) { + if (data_len > g_aic_udc.out_ep[ep_idx].ep_mps) { + data_len = g_aic_udc.out_ep[ep_idx].ep_mps; + } + g_aic_udc.out_ep[ep_idx].xfer_len = data_len; + outeptsfsiz |= (DXEPTSIZ_PKT_CNT_MASK & (1U << 19)); + outeptsfsiz |= (DXEPTSIZ_XFER_SIZE_MASK & data_len); + writel(outeptsfsiz, &AIC_UDC_REG->outeptsfsiz[ep_idx]); + } else { + pktcnt = (uint16_t)((data_len + g_aic_udc.out_ep[ep_idx].ep_mps - 1U) / g_aic_udc.out_ep[ep_idx].ep_mps); + + outeptsfsiz |= (DXEPTSIZ_PKT_CNT_MASK & (pktcnt << 19)); + outeptsfsiz |= (DXEPTSIZ_XFER_SIZE_MASK & data_len); + writel(outeptsfsiz, &AIC_UDC_REG->outeptsfsiz[ep_idx]); + } + +#ifdef CONFIG_USB_AIC_DMA_ENABLE + writel((uint32_t)(uintptr_t)data, &AIC_UDC_REG->outepdmaaddr[ep_idx]); +#endif + if (g_aic_udc.out_ep[ep_idx].ep_type == USB_ENDPOINT_TYPE_ISOCHRONOUS) { + usblinests = readl(&AIC_UDC_REG->usblinests); + if ((usblinests & (1U << 8)) == 0U) { + outepcfg &= ~DEPCTL_SETD0PID; + outepcfg |= DEPCTL_SETD1PID; + } else { + outepcfg &= ~DEPCTL_SETD1PID; + outepcfg |= DEPCTL_SETD0PID; + } + } + writel(0xFFFFFFFFU, &AIC_UDC_REG->outepint[ep_idx]); + outepcfg |= (DEPCTL_CNAK | DEPCTL_EPENA); + writel(outepcfg, &AIC_UDC_REG->outepcfg[ep_idx]); + + return 0; +} + + +int usbd_ep_start_read(uint8_t busid, const uint8_t ep, uint8_t *data, uint32_t data_len) +{ + return usbd_ep_start_read_raw(ep, data, data_len, 1); +} + +void USBD_IRQHandler(void) +{ + uint32_t gint_status, ep_idx, ep_intr, epint, daintmask, tmpreg, tmpreg01; + gint_status = aic_get_glb_intstatus(); + + /* Avoid spurious interrupt */ + if (gint_status == 0) { + return; + } + +#ifndef CONFIG_USB_AIC_DMA_ENABLE + uint32_t temp; + uint32_t read_count; + + /* Handle RxQLevel Interrupt */ + if (gint_status & INT_RX_FIFO_NOT_EMPTY) { + tmpreg = readl(&AIC_UDC_REG->usbintmsk); + tmpreg &= ~(INT_RX_FIFO_NOT_EMPTY); + writel(tmpreg, &AIC_UDC_REG->usbintmsk); + + temp = readl(&AIC_UDC_REG->rxfifosts_pop); + ep_idx = temp & RXFIFOSTS_EPNUM_MASK; + + if ((temp & RXFIFOSTS_PKTSTS_MASK) == PKTSTS_OUT_DATA_PKT_REC) { + read_count = (temp & RXFIFOSTS_BCNT_MASK) >> 4; + if (read_count != 0) { + aic_ep_read(g_aic_udc.out_ep[ep_idx].xfer_buf, read_count); + g_aic_udc.out_ep[ep_idx].xfer_buf += read_count; + } + } else if ((temp & RXFIFOSTS_PKTSTS_MASK) == PKTSTS_SETUP_DATA_PKT_REC) { + read_count = (temp & RXFIFOSTS_BCNT_MASK) >> 4; + aic_ep_read((uint8_t *)&g_aic_udc.setup, read_count); + } else { + /* ... */ + } + tmpreg = readl(&AIC_UDC_REG->usbintmsk); + tmpreg |= INT_RX_FIFO_NOT_EMPTY; + writel(tmpreg, &AIC_UDC_REG->usbintmsk); + } +#endif + if (gint_status & INT_OUT_EP) { + ep_idx = 0; + ep_intr = aic_get_outeps_intstatus(); + while (ep_intr != 0U) { + if ((ep_intr & 0x1U) != 0U) { + epint = aic_get_outep_intstatus(ep_idx); + writel(epint, &AIC_UDC_REG->outepint[ep_idx]); + + struct aic_ep_state *ep = &g_aic_udc.out_ep[ep_idx]; + + if ((ep_idx == 0)) { + #ifdef CONFIG_USB_AIC_DMA_ENABLE + extern void usb_dc_sync_dma(void); + usb_dc_sync_dma(); + if (ep->xfer_align_buf) + memcpy(ep->xfer_buf, ep->xfer_align_buf, ep->xfer_len); + #endif + + if (ep0_ctrl_stage == AIC_EP0_SETUP) { + /* Setup data-out will send STATUS_PHASE_RCVD interrupt when next setup. + Attemp to re-read setup data. */ + if (epint & CTRL_OUT_EP_STATUS_PHASE_RCVD) { + aic_ep0_start_read_setup((uint8_t *)&g_aic_udc.setup); + } + + /* Normal setup handle */ + if (epint & CTRL_OUT_EP_SETUP_PHASE_DONE) { + if (g_aic_udc.setup.wLength) + if ((g_aic_udc.setup.bmRequestType & USB_REQUEST_DIR_MASK) == USB_REQUEST_DIR_OUT) + ep0_ctrl_stage = AIC_EP0_DATA_OUT; + else + ep0_ctrl_stage = AIC_EP0_DATA_IN; + else + ep0_ctrl_stage = AIC_EP0_STATUS_IN; + usbd_event_ep0_setup_complete_handler(0, (uint8_t *)&g_aic_udc.setup); + } + } else { + if ((epint & TRANSFER_DONE) == TRANSFER_DONE) { + if (ep->xfer_len == 0) { + /* Out status, start reading setup */ + aic_ep0_start_read_setup((uint8_t *)&g_aic_udc.setup); + } else { + //ep->actual_xfer_len = ep->xfer_len - ((AIC_UDC_REG->outeptsfsiz[ep_idx]) & DXEPTSIZ_XFER_SIZE_MASK); + ep->actual_xfer_len = ep->xfer_len; + ep->xfer_len = 0; + usbd_event_ep_out_complete_handler(0, 0x00, ep->actual_xfer_len); + } + } + } + } else { + #ifdef CONFIG_USB_AIC_DMA_ENABLE + extern void usb_dc_sync_dma(void); + usb_dc_sync_dma(); + if (ep->xfer_align_buf) + memcpy(ep->xfer_buf, ep->xfer_align_buf, ep->xfer_len); + #endif + tmpreg = readl(&AIC_UDC_REG->outeptsfsiz[ep_idx]); + ep->actual_xfer_len = ep->xfer_len - (tmpreg & DXEPTSIZ_XFER_SIZE_MASK); + ep->xfer_len = 0; + usbd_event_ep_out_complete_handler(0, ep_idx, ep->actual_xfer_len); + } + +#ifndef CONFIG_USB_AIC_DMA_ENABLE + if ((epint & CTRL_OUT_EP_SETUP_PHASE_DONE) == CTRL_OUT_EP_SETUP_PHASE_DONE) { + if (ep0_ctrl_stage == 1) { + ep0_ctrl_stage = 2; + usbd_event_ep0_setup_complete_handler(0, (uint8_t *)&g_aic_udc.setup); + } + } +#endif + } + ep_intr >>= 1U; + ep_idx++; + } + } + +#ifndef CONFIG_USB_AIC_DMA_ENABLE + if (gint_status & INT_NP_TX_FIFO_EMPTY) { + tmpreg = readl(&AIC_UDC_REG->usbintmsk); + tmpreg &= ~(INT_NP_TX_FIFO_EMPTY); + writel(tmpreg, &AIC_UDC_REG->usbintmsk); + aic_tx_fifo_empty_procecss(0); + } +#endif + + if (gint_status & INT_IN_EP) { + ep_idx = 0U; + ep_intr = aic_get_ineps_intstatus(); + while (ep_intr != 0U) { + if ((ep_intr & 0x1U) != 0U) { + epint = aic_get_inep_intstatus(ep_idx); + writel(epint, &AIC_UDC_REG->inepint[ep_idx]); + + if (epint & INTKNEPMIS) { + aic_udelay(100); + usbd_npinep_rewrite(ep_idx); + } + + if ((epint & TRANSFER_DONE) == TRANSFER_DONE) { + if (ep_idx == 0) { + if (g_aic_udc.setup.wLength && ((g_aic_udc.setup.bmRequestType & USB_REQUEST_DIR_MASK) == USB_REQUEST_DIR_OUT)) { + /* In status, start reading setup */ + aic_ep0_start_read_setup((uint8_t *)&g_aic_udc.setup); + } else if (g_aic_udc.setup.wLength == 0) { + /* In status, start reading setup */ + aic_ep0_start_read_setup((uint8_t *)&g_aic_udc.setup); + } else { + g_aic_udc.in_ep[ep_idx].actual_xfer_len = g_aic_udc.in_ep[ep_idx].xfer_len - ((AIC_UDC_REG->ineptsfsiz[ep_idx]) & DXEPTSIZ_XFER_SIZE_MASK); + g_aic_udc.in_ep[ep_idx].xfer_len = 0; + usbd_event_ep_in_complete_handler(0, 0x80, g_aic_udc.in_ep[ep_idx].actual_xfer_len); + } + } else { + tmpreg = readl(&AIC_UDC_REG->ineptsfsiz[ep_idx]); + g_aic_udc.in_ep[ep_idx].actual_xfer_len = g_aic_udc.in_ep[ep_idx].xfer_len - (tmpreg & DXEPTSIZ_XFER_SIZE_MASK); + g_aic_udc.in_ep[ep_idx].xfer_len = 0; + usbd_event_ep_in_complete_handler(0, ep_idx | 0x80, g_aic_udc.in_ep[ep_idx].actual_xfer_len); + } + } + + #ifndef CONFIG_USB_AIC_DMA_ENABLE + if ((epint & INTKN_TXFEMP) == INTKN_TXFEMP) { + aic_tx_fifo_empty_procecss(ep_idx); + } + #endif + } + ep_intr >>= 1U; + ep_idx++; + } + } + if (gint_status & INT_RESET) { + writel(INT_RESET, &AIC_UDC_REG->usbintsts); + tmpreg = readl(&AIC_UDC_REG->usbdevfunc); + tmpreg &= ~USBDEVFUNC_RMTWKUPSIG; + writel(tmpreg, &AIC_UDC_REG->usbdevfunc); + + usb_dc_rst(); + } + + if (gint_status & INT_ENUMDONE) { + writel(INT_ENUMDONE, &AIC_UDC_REG->usbintsts); + aic_set_turnaroundtime(usbd_clk, aic_get_devspeed()); + + tmpreg = readl(&AIC_UDC_REG->usbdevfunc); + tmpreg |= USBDEVFUNC_CGNPINNAK; + writel(tmpreg, &AIC_UDC_REG->usbdevfunc); + } + if (gint_status & INT_INCOMP_ISO_OUT_INT) { + daintmask = readl(&AIC_UDC_REG->usbepintmsk); + daintmask >>= 16; + + for (ep_idx = 1; ep_idx < USB_NUM_BIDIR_ENDPOINTS; ep_idx++) { + if ((BIT(ep_idx) & ~daintmask) || (g_aic_udc.out_ep[ep_idx].ep_type != USB_ENDPOINT_TYPE_ISOCHRONOUS)) + continue; + + tmpreg = readl(&AIC_UDC_REG->outepcfg[ep_idx]); + if (!(tmpreg & DEPCTL_USBACTEP)) + continue; + tmpreg01 = readl(&AIC_UDC_REG->usblinests); + if ((tmpreg01 & (1U << 8)) != 0U) { + tmpreg |= DEPCTL_SETD0PID; + tmpreg &= ~DEPCTL_SETD1PID; + } else { + tmpreg &= ~DEPCTL_SETD0PID; + tmpreg |= DEPCTL_SETD1PID; + } + writel(tmpreg, &AIC_UDC_REG->outepcfg[ep_idx]); + } + + writel(INT_INCOMP_ISO_OUT_INT, &AIC_UDC_REG->usbintsts); + } + + if (gint_status & INT_INCOMP_ISO_IN_INT) { + daintmask = readl(&AIC_UDC_REG->usbepintmsk); + daintmask &= 0xFFFF; + + for (ep_idx = 1; ep_idx < USB_NUM_BIDIR_ENDPOINTS; ep_idx++) { + if (((BIT(ep_idx) & ~daintmask)) || (g_aic_udc.in_ep[ep_idx].ep_type != USB_ENDPOINT_TYPE_ISOCHRONOUS)) + continue; + + tmpreg = readl(&AIC_UDC_REG->inepcfg[ep_idx]); + if (!(tmpreg & DEPCTL_USBACTEP)) + continue; + tmpreg01 = readl(&AIC_UDC_REG->usblinests); + if ((tmpreg01 & (1U << 8)) != 0U) { + tmpreg |= DEPCTL_SETD0PID; + tmpreg &= ~DEPCTL_SETD1PID; + } else { + tmpreg &= ~DEPCTL_SETD0PID; + tmpreg |= DEPCTL_SETD1PID; + } + writel(tmpreg, &AIC_UDC_REG->inepcfg[ep_idx]); + } + + writel(INT_INCOMP_ISO_IN_INT, &AIC_UDC_REG->usbintsts); + } + + if (gint_status & INT_SOF) { + writel(INT_SOF, &AIC_UDC_REG->usbintsts); + } + if (gint_status & INT_SUSPEND) { + writel(INT_SUSPEND, &AIC_UDC_REG->usbintsts); + usbd_event_suspend_handler(0); + } + if (gint_status & INT_RESUME) { + writel(INT_RESUME, &AIC_UDC_REG->usbintsts); + } +} diff --git a/kernel/cherryusb/port/aic/usb_dc_aic_ll.c b/kernel/cherryusb/port/aic/usb_dc_aic_ll.c new file mode 100644 index 0000000..b7e7bc9 --- /dev/null +++ b/kernel/cherryusb/port/aic/usb_dc_aic_ll.c @@ -0,0 +1,59 @@ +/* + * Copyright (c) 2022-2024, ArtInChip Technology Co., Ltd + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include +#include "usbd_core.h" +#include "usb_dc_aic_reg.h" + +extern irqreturn_t USBD_IRQHandler(int irq, void * data); + +uint32_t usbd_clk; +static unsigned char dma_sync_buffer[CACHE_LINE_SIZE] __attribute__((aligned(CACHE_LINE_SIZE))); + +void usb_dc_sync_dma(void) +{ + asm volatile("sw t0, (%0)" : : "r"(dma_sync_buffer)); + csi_dcache_clean_range((phy_addr_t)(ptr_t)dma_sync_buffer, CACHE_LINE_SIZE); +} + +void usb_dc_low_level_init(void) +{ + /* set usb0 phy switch: Host/Device */ +#if defined(AIC_USING_USB0_DEVICE) || defined(AIC_USING_USB0_OTG) + hal_syscfg_usb_phy0_sw_host(0); +#endif + /* set pin-mux */ + + /* enable clock */ + hal_clk_enable(CONFIG_USB_AIC_DC_PHY_CLK); + hal_clk_enable(CONFIG_USB_AIC_DC_CLK); + aicos_udelay(300); + hal_reset_assert(CONFIG_USB_AIC_DC_PHY_RESET); + hal_reset_assert(CONFIG_USB_AIC_DC_RESET); + aicos_udelay(300); + hal_reset_deassert(CONFIG_USB_AIC_DC_PHY_RESET); + hal_reset_deassert(CONFIG_USB_AIC_DC_RESET); + aicos_udelay(300); + + usbd_clk = hal_clk_get_freq(CONFIG_USB_AIC_DC_CLK); + + /* register interrupt callback */ + aicos_request_irq(CONFIG_USB_AIC_DC_IRQ_NUM, USBD_IRQHandler, + 0, "usb_device", NULL); + aicos_irq_enable(CONFIG_USB_AIC_DC_IRQ_NUM); +} + +void usb_dc_low_level_deinit(void) +{ + aicos_irq_disable(CONFIG_USB_AIC_DC_IRQ_NUM); + + hal_reset_assert(CONFIG_USB_AIC_DC_PHY_RESET); + hal_reset_assert(CONFIG_USB_AIC_DC_RESET); + hal_clk_disable(CONFIG_USB_AIC_DC_PHY_CLK); + hal_clk_disable(CONFIG_USB_AIC_DC_CLK); +} diff --git a/kernel/cherryusb/port/aic/usb_dc_aic_reg.h b/kernel/cherryusb/port/aic/usb_dc_aic_reg.h new file mode 100644 index 0000000..b35b8d4 --- /dev/null +++ b/kernel/cherryusb/port/aic/usb_dc_aic_reg.h @@ -0,0 +1,312 @@ +/* + * Copyright (c) 2022-2024, Artinchip Technology Co., Ltd + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef __USB_DC_AIC_REG_H__ +#define __USB_DC_AIC_REG_H__ + +#define __IO volatile /*!< Defines 'read / write' permissions */ + +typedef struct { + __IO uint32_t ahbbasic; /* 0x0000: AHBBASIC */ + __IO uint32_t usbdevinit; /* 0x0004: USBDEVINIT */ + __IO uint32_t usbphyif; /* 0x0008: USBPHYIF */ + __IO uint32_t usbulpiphy; /* 0x000C: USBULPIPHY */ + __IO uint32_t usbintsts; /* 0x0010: USBINTSTS */ + __IO uint32_t usbintmsk; /* 0x0014: USBINTMSK */ + __IO uint32_t rxfifosiz; /* 0x0018: RXFIFOSIZ */ + __IO uint32_t rxfifosts_pop; /* 0x001C: RXFIFOSTS pop */ + __IO uint32_t nptxfifosiz; /* 0x0020: NPTXFIFOSIZ */ + __IO uint32_t nptxfifosts; /* 0x0024: NPTXFIFOSTS */ + __IO uint32_t txfifosiz[2]; /* 0x0028 - 0x002C: TXFIFOSIZ() */ + __IO uint32_t rxfifosts_dbg; /* 0x0030: RXFIFOSTS_DBG */ + uint8_t res0[0x1cc]; + __IO uint32_t usbdevconf; /* 0x0200: USBDEVCONF */ + __IO uint32_t usbdevfunc; /* 0x0204: USBDEVFUNC */ + __IO uint32_t usblinests; /* 0x0208: USBLINESTS */ + __IO uint32_t inepintmsk; /* 0x020C: INEPINTMSK */ + __IO uint32_t outepintmsk; /* 0x0210: OUTEPINTMSK */ + __IO uint32_t usbepint; /* 0x0214: USBEPINT */ + __IO uint32_t usbepintmsk; /* 0x0218: USBEPINTMSK */ + uint8_t res1[4]; + __IO uint32_t inepcfg[5]; /* 0x0220 - 0x0230: INEPCFG() */ + uint8_t res2[0xc]; + __IO uint32_t outepcfg[5]; /* 0x0240 - 0x0250: OUTEPCFG() */ + uint8_t res3[0xc]; + __IO uint32_t inepint[5]; /* 0x0260 - 0x0270: INEPINT() */ + uint8_t res4[0xc]; + __IO uint32_t outepint[5]; /* 0x0280 - 0x0290: OUTEPINT() */ + uint8_t res5[0xc]; + __IO uint32_t ineptsfsiz[5]; /* 0x02A0 - 0x02B0: INEPTSFSIZ() */ + uint8_t res6[0xc]; + __IO uint32_t outeptsfsiz[5]; /* 0x02C0 - 0x02D0: OUTEPTSFSIZ() */ + uint8_t res7[0x2c]; + __IO uint32_t inepdmaaddr[5]; /* 0x0300 - 0x0310: INEPDMAADDR() */ + uint8_t res8[0xc]; + __IO uint32_t outepdmaaddr[5]; /* 0x0320 - 0x0330: OUTEPDMAADDR() */ + uint8_t res9[0xc]; + __IO uint32_t ineptxsts[5]; /* 0x0340 - 0x0350: INEPTXSTS() */ + uint8_t res10[0xc]; + __IO uint32_t dtknqr1; /* 0x0360: DTKNQR1 */ + __IO uint32_t dtknqr2; /* 0x0364: DTKNQR2 */ + __IO uint32_t dtknqr3; /* 0x0368: DTKNQR3 */ + __IO uint32_t dtknqr4; /* 0x036C: DTKNQR4 */ +}AIC_UDC_RegDef; + +/*===================================================================== */ +/*definitions related to CSR setting */ + +/* AHBBASIC */ +#define AHBBASIC_NOTI_ALL_DMA_WRIT (1 << 8) +#define AHBBASIC_REM_MEM_SUPP (1 << 7) +#define AHBBASIC_INV_DESC_ENDIANNESS (1 << 6) +#define AHBBASIC_AHB_SINGLE (1 << 5) +#define AHBBASIC_TXENDDELAY (1 << 3) +#define AHBBASIC_AHBIDLE (1 << 2) +#define AHBBASIC_DMAREQ (1 << 1) + +/* USBDEVINIT */ +#define USBDEVINIT_HBSTLEN_MASK (0xf << 12) +#define USBDEVINIT_HBSTLEN_SHIFT 12 +#define USBDEVINIT_HBSTLEN_SINGLE 0 +#define USBDEVINIT_HBSTLEN_INCR 1 +#define USBDEVINIT_HBSTLEN_INCR4 3 +#define USBDEVINIT_HBSTLEN_INCR8 5 +#define USBDEVINIT_HBSTLEN_INCR16 7 +#define USBDEVINIT_DMA_EN (1 << 11) +#define USBDEVINIT_NP_TXF_EMP_LVL (1 << 10) +#define USBDEVINIT_GLBL_INTR_EN (1 << 9) +#define USBDEVINIT_CTRL_MASK (USBDEVINIT_NP_TXF_EMP_LVL | \ + USBDEVINIT_DMA_EN | \ + USBDEVINIT_GLBL_INTR_EN) +#define USBDEVINIT_IN_TKNQ_FLSH (1 << 8) +#define USBDEVINIT_TXFNUM_MASK (0x1f << 3) +#define USBDEVINIT_TXFNUM_SHIFT 3 +#define USBDEVINIT_TXFNUM_LIMIT 0x1f +#define USBDEVINIT_TXFNUM(_x) ((_x) << 3) +#define USBDEVINIT_TXFFLSH (1 << 2) +#define USBDEVINIT_RXFFLSH (1 << 1) +#define USBDEVINIT_CSFTRST (1 << 0) + +/* USBPHYIF */ +#define USBPHYIF_ULPI_CLK_SUSP_M (1 << 19) +#define USBPHYIF_ULPI_AUTO_RES (1 << 18) +#define USBPHYIF_PHY_LP_CLK_SEL (1 << 15) +#define USBPHYIF_USBTRDTIM_MASK (0xf << 10) +#define USBPHYIF_USBTRDTIM_SHIFT 10 +#ifndef USBPHYIF_HS_TRDT_VALUE +#define USBPHYIF_HS_TRDT_VALUE 9U +#endif /* USBD_HS_TRDT_VALUE */ +#ifndef USBPHYIF_FS_TRDT_VALUE +#define USBPHYIF_FS_TRDT_VALUE 5U +#define USBPHYIF_DEFAULT_TRDT_VALUE 9U +#endif /* USBD_HS_TRDT_VALUE */ +#define USBPHYIF_DDRSEL (1 << 7) +#define USBPHYIF_ULPI_UTMI_SEL (1 << 4) +#define USBPHYIF_PHYIF16 (1 << 3) +#define USBPHYIF_PHYIF8 (0 << 3) +#define USBPHYIF_TOUTCAL_MASK (0x7 << 0) +#define USBPHYIF_TOUTCAL_SHIFT 0 +#define USBPHYIF_TOUTCAL_LIMIT 0x7 +#define USBPHYIF_TOUTCAL(_x) ((_x) << 0) + +/* USBINTSTS/USBINTMSK interrupt register */ +#define INT_RESUME (1u << 31) +#define INT_INCOMP_ISO_OUT_INT (0x1 << 21) +#define INT_INCOMP_ISO_IN_INT (0x1 << 20) +#define INT_OUT_EP (0x1 << 19) +#define INT_IN_EP (0x1 << 18) +#define INT_ENUMDONE (0x1 << 13) +#define INT_RESET (0x1 << 12) +#define INT_SUSPEND (0x1 << 11) +#define INT_EARLY_SUSPEND (0x1 << 10) +#define INT_GOUTNAKEFF (0x1 << 7) +#define INT_GINNAKEFF (0x1 << 6) +#define INT_NP_TX_FIFO_EMPTY (0x1 << 5) +#define INT_RX_FIFO_NOT_EMPTY (0x1 << 4) +#define INT_SOF (0x1 << 3) + +#define FULL_SPEED_CONTROL_PKT_SIZE 8 +#define FULL_SPEED_BULK_PKT_SIZE 64 + +#define HIGH_SPEED_CONTROL_PKT_SIZE 64 +#define HIGH_SPEED_BULK_PKT_SIZE 512 + +#define RX_FIFO_SIZE (1024) +#define NPTX_FIFO_SIZE (1024) +#define PTX_FIFO_SIZE (384) + +/* fifo size configure */ +#define EPS_NUM 5 +#define PERIOD_IN_EP_NUM 2 +#define TOTAL_FIFO_SIZE 0x3f6 +#ifdef LPKG_CHERRYUSB_DEVICE_VIDEO_DVP_TEMPLATE +/* video_dvp_template must use 2K Bytes period_tx_fifo */ +#define AIC_RX_FIFO_SIZE 0x99 +#define AIC_NP_TX_FIFO_SIZE 0x100 +#define AIC_PERIOD_TX_FIFO1_SIZE 0x200 +#define AIC_PERIOD_TX_FIFO2_SIZE 0x0 +#else +/* default configuration */ +#define AIC_RX_FIFO_SIZE 0x119 +#define AIC_NP_TX_FIFO_SIZE 0x100 +#define AIC_PERIOD_TX_FIFO1_SIZE 0x100 +#define AIC_PERIOD_TX_FIFO2_SIZE 0xDD +#endif + +#define DEPCTL_TXFNUM_0 (0x0 << 22) +#define DEPCTL_TXFNUM_1 (0x1 << 22) +#define DEPCTL_TXFNUM_2 (0x2 << 22) +#define DEPCTL_TXFNUM_3 (0x3 << 22) +#define DEPCTL_TXFNUM_4 (0x4 << 22) + +/* RXFIFOSTS */ +#define RXFIFOSTS_EPNUM_MASK (0xFU << 0) +#define RXFIFOSTS_BCNT_MASK (0x7FFU << 4) +#define RXFIFOSTS_DPID_MASK (0x3U << 15) +#define RXFIFOSTS_PKTSTS_SHIFT (17) +#define RXFIFOSTS_PKTSTS_MASK (0xFU << RXFIFOSTS_PKTSTS_SHIFT) +#define PKTSTS_GLOBAL_OUT_NAK (0x1 << RXFIFOSTS_PKTSTS_SHIFT) +#define PKTSTS_OUT_DATA_PKT_REC (0x2 << RXFIFOSTS_PKTSTS_SHIFT) +#define PKTSTS_OUT_TRANSFER_COMP (0x3 << RXFIFOSTS_PKTSTS_SHIFT) +#define PKTSTS_SETUP_TRANSACTION_COMP (0x4 << RXFIFOSTS_PKTSTS_SHIFT) +#define PKTSTS_SETUP_DATA_PKT_REC (0x6 << RXFIFOSTS_PKTSTS_SHIFT) +#define RXFIFOSTS_FN_MASK (0xFU << 21) + +/* USBDEVCONF */ +#define DEV_SPEED_HIGH_SPEED_20 (0x0 << 0) +#define DEV_SPEED_FULL_SPEED_20 (0x1 << 0) +#define DEV_SPEED_LOW_SPEED_11 (0x2 << 0) +#define DEV_SPEED_FULL_SPEED_11 (0x3 << 0) +#define EP_MISS_CNT(x) (x << 18) +#define DEVICE_ADDRESS_MASK (0x7F << 4) +#define DEVICE_ADDRESS(x) (x << 4) +#define PERIOD_FRAME_INTERVAL_80 (0 << 11) +#define PERIOD_FRAME_INTERVAL_85 (1 << 11) +#define PERIOD_FRAME_INTERVAL_90 (2 << 11) +#define PERIOD_FRAME_INTERVAL_95 (3 << 11) + +/* USBDEVFUNC */ +#define NORMAL_OPERATION (0x1 << 0) +#define SOFT_DISCONNECT (0x1 << 1) +#define USBDEVFUNC_SERVICE_INTERVAL_SUPPORTED (1 << 19) +#define USBDEVFUNC_PWRONPRGDONE (1 << 11) +#define USBDEVFUNC_CGOUTNAK (1 << 10) +#define USBDEVFUNC_SGOUTNAK (1 << 9) +#define USBDEVFUNC_CGNPINNAK (1 << 8) +#define USBDEVFUNC_SGNPINNAK (1 << 7) +#define USBDEVFUNC_TSTCTL_MASK (0x7 << 4) +#define USBDEVFUNC_TSTCTL_SHIFT (4) +#define USBDEVFUNC_GOUTNAKSTS (1 << 3) +#define USBDEVFUNC_GNPINNAKSTS (1 << 2) +#define USBDEVFUNC_SFTDISCON (1 << 1) +#define USBDEVFUNC_RMTWKUPSIG (1 << 0) + +/* USBLINESTS: Enumeration speed */ +#define USB_ENUM_SPEED_SHIFT 1 +#define USB_ENUM_SPEED_MASK (0x3 << USB_ENUM_SPEED_SHIFT) +#define USB_ENUM_SPEED_HIGH 0 +#define USB_ENUM_SPEED_FULL 1 +#define USB_HIGH_30_60MHZ (0x0 << USB_ENUM_SPEED_SHIFT) +#define USB_FULL_30_60MHZ (0x1 << USB_ENUM_SPEED_SHIFT) +#define USB_LOW_6MHZ (0x2 << USB_ENUM_SPEED_SHIFT) +#define USB_FULL_48MHZ (0x3 << USB_ENUM_SPEED_SHIFT) + +/* USBEPINT endpoint interrupt register */ +#define DAINT_OUT_BIT (16) +#define DAINT_IN_MASK (0xFFFF) +#define DAINT_OUT_MASK (0xFFFFU << DAINT_OUT_BIT) + +/* INEPCFG()/OUTEPCFG() + * devicecontrol IN/OUT endpoint 0 control register + */ +#define DEPCTL_EPENA (1u << 31) +#define DEPCTL_EPDIS (0x1 << 30) +#define DEPCTL_SETD1PID (0x1 << 29) +#define DEPCTL_SETD0PID (0x1 << 28) +#define DEPCTL_SNAK (0x1 << 27) +#define DEPCTL_CNAK (0x1 << 26) +#define DEPCTL_TXFIFONUM_SHIFT 22 +#define DEPCTL_TXFIFONUM_MASK (0xF << 22) +#define DEPCTL_STALL (0x1 << 21) +#define DEPCTL_TYPE_BIT (18) +#define DEPCTL_TYPE_MASK (0x3 << 18) +#define DEPCTL_CTRL_TYPE (0x0 << 18) +#define DEPCTL_ISO_TYPE (0x1 << 18) +#define DEPCTL_BULK_TYPE (0x2 << 18) +#define DEPCTL_INTR_TYPE (0x3 << 18) +#define DEPCTL_USBACTEP (0x1 << 15) +#define DEPCTL_NEXT_EP_BIT (11) +#define DEPCTL_NEXT_EP_MASK (0xFU << DEPCTL_NEXT_EP_BIT) +#define DEPCTL_MPS_BIT (0) +#define DEPCTL_MPS_MASK (0x7FF) + +#define DEPCTL0_MPS_64 (0x0 << 0) +#define DEPCTL0_MPS_32 (0x1 << 0) +#define DEPCTL0_MPS_16 (0x2 << 0) +#define DEPCTL0_MPS_8 (0x3 << 0) +#define DEPCTL_MPS_BULK_512 (512 << 0) +#define DEPCTL_MPS_INT_MPS_16 (16 << 0) + +#define DIEPCTL0_NEXT_EP_BIT (11) + +/* INEPINT/OUTEPINT device IN/OUT endpoint interrupt register */ +#define CTRL_OUT_EP_SETUP_RCVD (0x1 << 15) +#define TXFIFO_EMP_INT (0x1 << 7) +#define INEP_NAKEFF (0x1 << 6) +#define BACK2BACK_SETUP_RECEIVED (0x1 << 6) +#define CTRL_OUT_EP_STATUS_PHASE_RCVD (0x1 << 5) +#define INTKNEPMIS (0x1 << 5) +#define INTKN_TXFEMP (0x1 << 4) +#define NON_ISO_IN_EP_TIMEOUT (0x1 << 3) +#define CTRL_OUT_EP_SETUP_PHASE_DONE (0x1 << 3) +#define AHB_ERROR (0x1 << 2) +#define EPDISBLD (0x1 << 1) +#define TRANSFER_DONE (0x1 << 0) + +/* Masks definitions */ +#define GINTMSK_INIT (INT_OUT_EP | INT_IN_EP | INT_RESUME | INT_ENUMDONE\ + | INT_RESET | INT_SUSPEND) +#define DOEPMSK_INIT (CTRL_OUT_EP_SETUP_PHASE_DONE |\ + AHB_ERROR | TRANSFER_DONE) +#define DIEPMSK_INIT (NON_ISO_IN_EP_TIMEOUT | AHB_ERROR | TRANSFER_DONE) +#define GAHBCFG_INIT (USBDEVINIT_DMA_EN | USBDEVINIT_GLBL_INTR_EN\ + | (USBDEVINIT_HBSTLEN_INCR4 <<\ + USBDEVINIT_HBSTLEN_SHIFT)) + +/* INEPTSFSIZ/OUTEPTSFSIZ */ +#define DXEPTSIZ_MULCNT_SHIFT 29 +#define DXEPTSIZ_MULCNT_MASK (0x3U << DXEPTSIZ_MULCNT_SHIFT) +#define DXEPTSIZ_PKT_CNT_SHIFT 19 +#define DXEPTSIZ_PKT_CNT_MASK (0x3FFU << DXEPTSIZ_PKT_CNT_SHIFT) +#define DXEPTSIZ_XFER_SIZE_SHIFT 0 +#define DXEPTSIZ_XFER_SIZE_MASK (0x7FFFFU << DXEPTSIZ_XFER_SIZE_SHIFT) + +/* Device Endpoint X Transfer Size Register INEPTSFSIZ() */ +#define DIEPT_SIZ_PKT_CNT(x) (x << 19) +#define DIEPT_SIZ_XFER_SIZE(x) (x << 0) + +/* Device OUT Endpoint X Transfer Size Register OUTEPTSFSIZ() */ +#define DOEPT_SIZ_PKT_CNT(x) (x << 19) +#define DOEPT_SIZ_XFER_SIZE(x) (x << 0) +#define DOEPT_SIZ_XFER_SIZE_MAX_EP0 (0x7F << 0) +#define DOEPT_SIZ_XFER_SIZE_MAX_EP (0x7FFF << 0) + +/* Device Endpoint-N Control Register INEPCFG()/OUTEPCFG() */ +#define DIEPCTL_TX_FIFO_NUM(x) (x << 22) +#define DIEPCTL_TX_FIFO_NUM_MASK (~DIEPCTL_TX_FIFO_NUM(0xF)) + +/* Device ALL Endpoints Interrupt Register (USBEPINT) */ +#define DAINT_IN_EP_INT(x) (x << 0) +#define DAINT_OUT_EP_INT(x) (x << 16) + +#define AIC_EP_FIFO_BASE 0x1000UL +#define AIC_EP_FIFO_SIZE 0x1000UL + +/* In EPn Txfifo Status (INEPTXSTS) */ +#define INEPTXSTS_IN_EP_TXFIFO_STS (0xFFFFU << 0) + + +#endif diff --git a/kernel/cherryusb/port/bouffalolab/README.md b/kernel/cherryusb/port/bouffalolab/README.md new file mode 100644 index 0000000..7779b2b --- /dev/null +++ b/kernel/cherryusb/port/bouffalolab/README.md @@ -0,0 +1,5 @@ +# Note + +## Support Chip List + +- BL616/BL808 diff --git a/kernel/cherryusb/port/bouffalolab/usb_dc_bl.c b/kernel/cherryusb/port/bouffalolab/usb_dc_bl.c new file mode 100644 index 0000000..18cba93 --- /dev/null +++ b/kernel/cherryusb/port/bouffalolab/usb_dc_bl.c @@ -0,0 +1,1157 @@ +/* + * Copyright (c) 2024, sakumisu + * + * SPDX-License-Identifier: Apache-2.0 + */ +#include "bflb_core.h" +#include "usbd_core.h" +#include "hardware/usb_v2_reg.h" + +/* select only one mode */ +// #define CONFIG_USB_PINGPONG_ENABLE +// #define CONFIG_USB_TRIPLE_ENABLE + +#define BFLB_USB_BASE ((uint32_t)0x20072000) +#define BFLB_PDS_BASE ((uint32_t)0x2000e000) + +#define PDS_USB_CTL_OFFSET (0x500) /* usb_ctl */ +#define PDS_USB_PHY_CTRL_OFFSET (0x504) /* usb_phy_ctrl */ + +/* 0x500 : usb_ctl */ +#define PDS_REG_USB_SW_RST_N (1 << 0U) +#define PDS_REG_USB_EXT_SUSP_N (1 << 1U) +#define PDS_REG_USB_WAKEUP (1 << 2U) +#define PDS_REG_USB_L1_WAKEUP (1 << 3U) +#define PDS_REG_USB_DRVBUS_POL (1 << 4U) +#define PDS_REG_USB_IDDIG (1 << 5U) + +/* 0x504 : usb_phy_ctrl */ +#define PDS_REG_USB_PHY_PONRST (1 << 0U) +#define PDS_REG_USB_PHY_OSCOUTEN (1 << 1U) +#define PDS_REG_USB_PHY_XTLSEL_SHIFT (2U) +#define PDS_REG_USB_PHY_XTLSEL_MASK (0x3 << PDS_REG_USB_PHY_XTLSEL_SHIFT) +#define PDS_REG_USB_PHY_OUTCLKSEL (1 << 4U) +#define PDS_REG_USB_PHY_PLLALIV (1 << 5U) +#define PDS_REG_PU_USB20_PSW (1 << 6U) + +#define USB_SOF_TIMER_MASK_AFTER_RESET_HS (0x44C) +#define USB_SOF_TIMER_MASK_AFTER_RESET_FS (0x2710) + +extern void USBD_IRQHandler(uint8_t busid); + +void USBD_IRQ(int irq, void *arg) +{ + USBD_IRQHandler(0); +} + +static void bflb_usb_phy_init(void) +{ + uint32_t regval; + + /* USB_PHY_CTRL[3:2] reg_usb_phy_xtlsel=0 */ + /* 2000e504 = 0x40; #100; USB_PHY_CTRL[6] reg_pu_usb20_psw=1 (VCC33A) */ + /* 2000e504 = 0x41; #500; USB_PHY_CTRL[0] reg_usb_phy_ponrst=1 */ + /* 2000e500 = 0x20; #100; USB_CTL[0] reg_usb_sw_rst_n=0 */ + /* 2000e500 = 0x22; #500; USB_CTL[1] reg_usb_ext_susp_n=1 */ + /* 2000e500 = 0x23; #100; USB_CTL[0] reg_usb_sw_rst_n=1 */ + /* #1.2ms; wait UCLK */ + /* wait(soc616_b0.usb_uclk); */ + + regval = getreg32(BFLB_PDS_BASE + PDS_USB_PHY_CTRL_OFFSET); + regval &= ~PDS_REG_USB_PHY_XTLSEL_MASK; + putreg32(regval, BFLB_PDS_BASE + PDS_USB_PHY_CTRL_OFFSET); + + regval = getreg32(BFLB_PDS_BASE + PDS_USB_PHY_CTRL_OFFSET); + regval |= PDS_REG_PU_USB20_PSW; + putreg32(regval, BFLB_PDS_BASE + PDS_USB_PHY_CTRL_OFFSET); + + regval = getreg32(BFLB_PDS_BASE + PDS_USB_PHY_CTRL_OFFSET); + regval |= PDS_REG_USB_PHY_PONRST; + putreg32(regval, BFLB_PDS_BASE + PDS_USB_PHY_CTRL_OFFSET); + + /* greater than 5T */ + bflb_mtimer_delay_us(1); + + regval = getreg32(BFLB_PDS_BASE + PDS_USB_CTL_OFFSET); + regval &= ~PDS_REG_USB_SW_RST_N; + putreg32(regval, BFLB_PDS_BASE + PDS_USB_CTL_OFFSET); + + /* greater than 5T */ + bflb_mtimer_delay_us(1); + + regval = getreg32(BFLB_PDS_BASE + PDS_USB_CTL_OFFSET); + regval |= PDS_REG_USB_EXT_SUSP_N; + putreg32(regval, BFLB_PDS_BASE + PDS_USB_CTL_OFFSET); + + /* wait UCLK 1.2ms */ + bflb_mtimer_delay_ms(3); + + regval = getreg32(BFLB_PDS_BASE + PDS_USB_CTL_OFFSET); + regval |= PDS_REG_USB_SW_RST_N; + putreg32(regval, BFLB_PDS_BASE + PDS_USB_CTL_OFFSET); + + bflb_mtimer_delay_ms(2); +} + +#define USB_FIFO_F0 0 +#define USB_FIFO_F1 1 +#define USB_FIFO_F2 2 +#define USB_FIFO_F3 3 +#define USB_FIFO_CXF 0xff + +#define USB_FIFO_DIR_OUT 0 +#define USB_FIFO_DIR_IN 1 +#define USB_FIFO_DIR_BID 2 + +#define USB_VDMA_DIR_FIFO2MEM 0 +#define USB_VDMA_DIR_MEM2FIFO 1 + +#define USB_NUM_BIDIR_ENDPOINTS 5 + +/* Endpoint state */ +struct bl_ep_state { + uint16_t ep_mps; /* Endpoint max packet size */ + uint8_t ep_type; /* Endpoint type */ + uint8_t ep_stalled; /* Endpoint stall flag */ + uint8_t ep_enable; /* Endpoint enable */ + bool ep_active; + uint8_t *xfer_buf; + uint32_t xfer_len; + uint32_t actual_xfer_len; +}; + +struct bl_udc { + struct bl_ep_state in_ep[USB_NUM_BIDIR_ENDPOINTS]; /*!< IN endpoint parameters */ + struct bl_ep_state out_ep[USB_NUM_BIDIR_ENDPOINTS]; /*!< OUT endpoint parameters */ +} g_bl_udc; + +static USB_NOCACHE_RAM_SECTION USB_MEM_ALIGNX uint8_t g_setup_buffer[8]; + +static void bflb_usb_reset_fifo(uint8_t fifo) +{ + uint32_t regval; + + if (fifo == USB_FIFO_CXF) { + regval = getreg32(BFLB_USB_BASE + USB_DEV_CXCFE_OFFSET); + regval |= USB_CX_CLR; + putreg32(regval, BFLB_USB_BASE + USB_DEV_CXCFE_OFFSET); + } else { + regval = getreg32(BFLB_USB_BASE + USB_DEV_FIBC0_OFFSET + 4 * fifo); + regval |= USB_FFRST0_HOV; + putreg32(regval, BFLB_USB_BASE + USB_DEV_FIBC0_OFFSET + 4 * fifo); + } +} + +void bflb_usb_get_setup_packet(uint32_t setup[2]) +{ + uint32_t regval; + + regval = getreg32(BFLB_USB_BASE + USB_DMA_TFN_OFFSET); + regval |= USB_ACC_CXF_HOV; + putreg32(regval, BFLB_USB_BASE + USB_DMA_TFN_OFFSET); + + setup[0] = getreg32(BFLB_USB_BASE + USB_DMA_CPS3_OFFSET); + setup[1] = getreg32(BFLB_USB_BASE + USB_DMA_CPS3_OFFSET); + + regval = getreg32(BFLB_USB_BASE + USB_DMA_TFN_OFFSET); + regval &= ~USB_ACC_CXF_HOV; + putreg32(regval, BFLB_USB_BASE + USB_DMA_TFN_OFFSET); +} + +static void bflb_usb_set_ep_fifomap(uint8_t ep_idx, uint8_t fifo) +{ + uint32_t regval; + + if (ep_idx < 5) { + regval = getreg32(BFLB_USB_BASE + USB_DEV_EPMAP0_OFFSET); + regval &= ~(0xff << ((ep_idx - 1) * 8)); + regval |= (fifo << ((ep_idx - 1) * 8)); + regval |= (fifo << ((ep_idx - 1) * 8 + 4)); + putreg32(regval, BFLB_USB_BASE + USB_DEV_EPMAP0_OFFSET); + } else { + regval = getreg32(BFLB_USB_BASE + USB_DEV_EPMAP1_OFFSET); + regval &= ~(0xff << ((ep_idx - 4 - 1) * 8)); + regval |= (fifo << ((ep_idx - 4 - 1) * 8)); + regval |= (fifo << ((ep_idx - 4 - 1) * 8 + 4)); + putreg32(regval, BFLB_USB_BASE + USB_DEV_EPMAP1_OFFSET); + } +} + +static void bflb_usb_set_fifo_epmap(uint8_t fifo, uint8_t ep_idx, uint8_t dir) +{ + uint32_t regval; + + regval = getreg32(BFLB_USB_BASE + USB_DEV_FMAP_OFFSET); + regval &= ~(0x3f << (fifo * 8)); + regval |= (ep_idx << (fifo * 8)); + regval |= (dir << (fifo * 8 + 4)); + putreg32(regval, BFLB_USB_BASE + USB_DEV_FMAP_OFFSET); +} + +static void bflb_usb_set_outep_mps(uint8_t ep_idx, uint16_t ep_mps) +{ + uint32_t regval; + + regval = getreg32(BFLB_USB_BASE + USB_DEV_OUTMPS1_OFFSET + (ep_idx - 1) * 4); + regval &= ~USB_MAXPS_OEP1_MASK; + regval |= ep_mps; + putreg32(regval, BFLB_USB_BASE + USB_DEV_OUTMPS1_OFFSET + (ep_idx - 1) * 4); +} + +static void bflb_usb_set_inep_mps(uint8_t ep_idx, uint16_t ep_mps) +{ + uint32_t regval; + + regval = getreg32(BFLB_USB_BASE + USB_DEV_INMPS1_OFFSET + (ep_idx - 1) * 4); + regval &= ~USB_MAXPS_IEP1_MASK; + regval |= ep_mps; + putreg32(regval, BFLB_USB_BASE + USB_DEV_INMPS1_OFFSET + (ep_idx - 1) * 4); +} + +static uint8_t bflb_usb_get_fifo_ep(uint8_t fifo) +{ + uint32_t regval; + + regval = (getreg32(BFLB_USB_BASE + USB_DEV_FMAP_OFFSET) & (0xf << (fifo * 8))); + regval >>= (fifo * 8); + return regval; +} + +static void bflb_usb_fifo_config(uint8_t fifo, uint8_t ep_type, uint16_t block_size, uint8_t block_num, bool fifo_en) +{ + uint32_t regval; + + if (fifo < 4) { + regval = getreg32(BFLB_USB_BASE + USB_DEV_FCFG_OFFSET); + regval &= ~(0x3f << (fifo * 8)); + regval |= (ep_type << (fifo * 8 + 0)); + regval |= ((block_num - 1) << (fifo * 8 + 2)); + if (block_size == 1024) { + regval |= (1 << (fifo * 8 + 4)); + } + + if (fifo_en) { + regval |= (1 << (fifo * 8 + 5)); + } + putreg32(regval, BFLB_USB_BASE + USB_DEV_FCFG_OFFSET); + } +} + +static void bflb_usb_vdma_start_write(uint8_t fifo, const uint8_t *data, uint32_t len) +{ + uint32_t regval; + + if (fifo == USB_FIFO_CXF) { + regval = getreg32(BFLB_USB_BASE + USB_VDMA_CXFPS1_OFFSET); + regval &= ~USB_VDMA_LEN_CXF_MASK; + regval &= ~USB_VDMA_IO_CXF; + regval |= USB_VDMA_TYPE_CXF; + regval |= (len << USB_VDMA_LEN_CXF_SHIFT); + putreg32(regval, BFLB_USB_BASE + USB_VDMA_CXFPS1_OFFSET); + + putreg32((uint32_t)data, BFLB_USB_BASE + USB_VDMA_CXFPS2_OFFSET); + + regval = getreg32(BFLB_USB_BASE + USB_VDMA_CXFPS1_OFFSET); + regval |= USB_VDMA_START_CXF; + putreg32(regval, BFLB_USB_BASE + USB_VDMA_CXFPS1_OFFSET); + } else { + regval = getreg32(BFLB_USB_BASE + USB_VDMA_F0PS1_OFFSET + fifo * 8); + regval &= ~USB_VDMA_LEN_CXF_MASK; + regval &= ~USB_VDMA_IO_CXF; + regval |= USB_VDMA_TYPE_CXF; + regval |= (len << USB_VDMA_LEN_CXF_SHIFT); + putreg32(regval, BFLB_USB_BASE + USB_VDMA_F0PS1_OFFSET + fifo * 8); + + putreg32((uint32_t)data, BFLB_USB_BASE + USB_VDMA_F0PS2_OFFSET + fifo * 8); + + regval = getreg32(BFLB_USB_BASE + USB_VDMA_F0PS1_OFFSET + fifo * 8); + regval |= USB_VDMA_START_CXF; + putreg32(regval, BFLB_USB_BASE + USB_VDMA_F0PS1_OFFSET + fifo * 8); + } +} + +static void bflb_usb_vdma_start_read(uint8_t fifo, uint8_t *data, uint32_t len) +{ + uint32_t regval; + + if (fifo == USB_FIFO_CXF) { + regval = getreg32(BFLB_USB_BASE + USB_VDMA_CXFPS1_OFFSET); + regval &= ~USB_VDMA_LEN_CXF_MASK; + regval &= ~USB_VDMA_IO_CXF; + regval &= ~USB_VDMA_TYPE_CXF; + regval |= (len << USB_VDMA_LEN_CXF_SHIFT); + putreg32(regval, BFLB_USB_BASE + USB_VDMA_CXFPS1_OFFSET); + + putreg32((uint32_t)data, BFLB_USB_BASE + USB_VDMA_CXFPS2_OFFSET); + + regval = getreg32(BFLB_USB_BASE + USB_VDMA_CXFPS1_OFFSET); + regval |= USB_VDMA_START_CXF; + putreg32(regval, BFLB_USB_BASE + USB_VDMA_CXFPS1_OFFSET); + } else { + regval = getreg32(BFLB_USB_BASE + USB_VDMA_F0PS1_OFFSET + fifo * 8); + regval &= ~USB_VDMA_LEN_CXF_MASK; + regval &= ~USB_VDMA_IO_CXF; + regval &= ~USB_VDMA_TYPE_CXF; + regval |= (len << USB_VDMA_LEN_CXF_SHIFT); + putreg32(regval, BFLB_USB_BASE + USB_VDMA_F0PS1_OFFSET + fifo * 8); + + putreg32((uint32_t)data, BFLB_USB_BASE + USB_VDMA_F0PS2_OFFSET + fifo * 8); + + regval = getreg32(BFLB_USB_BASE + USB_VDMA_F0PS1_OFFSET + fifo * 8); + regval |= USB_VDMA_START_CXF; + putreg32(regval, BFLB_USB_BASE + USB_VDMA_F0PS1_OFFSET + fifo * 8); + } +} + +static uint32_t bflb_usb_vdma_get_remain_size(uint8_t fifo) +{ + uint32_t regval; + + if (fifo == USB_FIFO_CXF) { + regval = (getreg32(BFLB_USB_BASE + USB_VDMA_CXFPS1_OFFSET) & USB_VDMA_LEN_CXF_MASK); + regval >>= USB_VDMA_LEN_CXF_SHIFT; + + } else { + regval = (getreg32(BFLB_USB_BASE + USB_VDMA_F0PS1_OFFSET + fifo * 8) & USB_VDMA_LEN_CXF_MASK); + regval >>= USB_VDMA_LEN_CXF_SHIFT; + } + + return regval; +} + +static inline void bflb_usb_control_transfer_done(void) +{ + uint32_t regval; + + regval = getreg32(BFLB_USB_BASE + USB_DEV_CXCFE_OFFSET); + regval |= USB_CX_DONE; + putreg32(regval, BFLB_USB_BASE + USB_DEV_CXCFE_OFFSET); +} + +static inline void bflb_usb_set_mult(uint8_t ep_idx, uint8_t mult) +{ + uint32_t regval; + + regval = getreg32(BFLB_USB_BASE + USB_DEV_INMPS1_OFFSET + (ep_idx - 1) * 4); + regval &= ~USB_TX_NUM_HBW_IEP1_MASK; + regval |= (mult << USB_TX_NUM_HBW_IEP1_SHIFT); + putreg32(regval, BFLB_USB_BASE + USB_DEV_INMPS1_OFFSET + (ep_idx - 1) * 4); +} + +static inline void bflb_usb_send_zlp(uint8_t ep_idx) +{ + uint32_t regval; + + regval = getreg32(BFLB_USB_BASE + USB_DEV_INMPS1_OFFSET + (ep_idx - 1) * 4); + regval |= USB_TX0BYTE_IEP1; + putreg32(regval, BFLB_USB_BASE + USB_DEV_INMPS1_OFFSET + (ep_idx - 1) * 4); +} + +static inline uint32_t bflb_usb_get_tx_zlp_intstatus(void) +{ + return getreg32(BFLB_USB_BASE + USB_DEV_TXZ_OFFSET); +} + +static inline uint32_t bflb_usb_get_rx_zlp_intstatus(void) +{ + return getreg32(BFLB_USB_BASE + USB_DEV_RXZ_OFFSET); +} + +static inline void bflb_usb_clear_tx_zlp_intstatus(uint8_t ep_idx) +{ + putreg32((1 << (ep_idx - 1)), BFLB_USB_BASE + USB_DEV_TXZ_OFFSET); +} + +static inline void bflb_usb_clear_rx_zlp_intstatus(uint8_t ep_idx) +{ + putreg32((1 << (ep_idx - 1)), BFLB_USB_BASE + USB_DEV_RXZ_OFFSET); +} + +static uint32_t bflb_usb_get_source_group_intstatus(uint8_t group) +{ + switch (group) { + case 0: + return (getreg32(BFLB_USB_BASE + USB_DEV_ISG0_OFFSET) & ~getreg32(BFLB_USB_BASE + USB_DEV_MISG0_OFFSET)); + case 1: + return (getreg32(BFLB_USB_BASE + USB_DEV_ISG1_OFFSET) & ~getreg32(BFLB_USB_BASE + USB_DEV_MISG1_OFFSET)); + case 2: + return (getreg32(BFLB_USB_BASE + USB_DEV_ISG2_OFFSET) & ~getreg32(BFLB_USB_BASE + USB_DEV_MISG2_OFFSET)); + case 3: + return (getreg32(BFLB_USB_BASE + USB_DEV_ISG3_OFFSET) & ~getreg32(BFLB_USB_BASE + USB_DEV_MISG3_OFFSET)); + case 4: + return (getreg32(BFLB_USB_BASE + USB_DEV_ISG4_OFFSET) & ~getreg32(BFLB_USB_BASE + USB_DEV_MISG4_OFFSET)); + default: + break; + } + return 0; +} + +static void bflb_usb_source_group_int_clear(uint8_t group, uint32_t int_clear) +{ + switch (group) { + case 0: + putreg32(int_clear, BFLB_USB_BASE + USB_DEV_ISG0_OFFSET); + break; + case 1: + putreg32(int_clear, BFLB_USB_BASE + USB_DEV_ISG1_OFFSET); + break; + case 2: + putreg32(int_clear, BFLB_USB_BASE + USB_DEV_ISG2_OFFSET); + break; + case 3: + putreg32(int_clear, BFLB_USB_BASE + USB_DEV_ISG3_OFFSET); + break; + case 4: + putreg32(int_clear, BFLB_USB_BASE + USB_DEV_ISG4_OFFSET); + break; + + default: + break; + } +} + +static uint8_t usb_get_transfer_fifo(uint8_t ep_idx) +{ + uint8_t target_fifo_id; + + if ((g_bl_udc.out_ep[ep_idx].ep_mps > 512) || (g_bl_udc.in_ep[ep_idx].ep_mps > 512)) { +#if defined(CONFIG_USB_PINGPONG_ENABLE) + target_fifo_id = USB_FIFO_F0; +#elif defined(CONFIG_USB_TRIPLE_ENABLE) + while (1) { + } +#else + if (ep_idx == 1) { + target_fifo_id = USB_FIFO_F0; + } else { + target_fifo_id = USB_FIFO_F2; + } +#endif + } else { +#if defined(CONFIG_USB_PINGPONG_ENABLE) + if (ep_idx == 1) { + target_fifo_id = USB_FIFO_F0; + } else { + target_fifo_id = USB_FIFO_F2; + } +#elif defined(CONFIG_USB_TRIPLE_ENABLE) + if (ep_idx == 1) { + target_fifo_id = USB_FIFO_F0; + } else { + target_fifo_id = USB_FIFO_F3; + } +#else + target_fifo_id = (ep_idx - 1); +#endif + } + + return target_fifo_id; +} + +int usb_dc_init(uint8_t busid) +{ + uint32_t regval; + + bflb_usb_phy_init(); + + bflb_irq_attach(37, USBD_IRQ, NULL); + bflb_irq_enable(37); + + /* disable device-A for device */ + regval = getreg32(BFLB_PDS_BASE + PDS_USB_CTL_OFFSET); + regval |= PDS_REG_USB_IDDIG; + putreg32(regval, BFLB_PDS_BASE + PDS_USB_CTL_OFFSET); + + /* disable global irq */ + regval = getreg32(BFLB_USB_BASE + USB_DEV_CTL_OFFSET); + regval &= ~USB_GLINT_EN_HOV; + putreg32(regval, BFLB_USB_BASE + USB_DEV_CTL_OFFSET); + + regval = getreg32(BFLB_USB_BASE + USB_PHY_TST_OFFSET); + regval |= USB_UNPLUG; + putreg32(regval, BFLB_USB_BASE + USB_PHY_TST_OFFSET); + + regval = getreg32(BFLB_USB_BASE + USB_DEV_CTL_OFFSET); + regval &= ~USB_CAP_RMWAKUP; + regval |= USB_CHIP_EN_HOV; + putreg32(regval, BFLB_USB_BASE + USB_DEV_CTL_OFFSET); + + regval = getreg32(BFLB_USB_BASE + USB_DEV_CTL_OFFSET); + regval |= USB_SFRST_HOV; +#ifdef CONFIG_USB_HS + regval &= ~USB_FORCE_FS; +#else + regval |= USB_FORCE_FS; +#endif + putreg32(regval, BFLB_USB_BASE + USB_DEV_CTL_OFFSET); + + while (getreg32(BFLB_USB_BASE + USB_DEV_CTL_OFFSET) & USB_SFRST_HOV) { + } + + regval = getreg32(BFLB_USB_BASE + USB_DEV_ADR_OFFSET); + regval &= ~USB_AFT_CONF; + putreg32(regval, BFLB_USB_BASE + USB_DEV_ADR_OFFSET); + + regval = getreg32(BFLB_USB_BASE + USB_DEV_SMT_OFFSET); + regval &= ~USB_SOFMT_MASK; +#ifdef CONFIG_USB_HS + regval |= USB_SOF_TIMER_MASK_AFTER_RESET_HS; +#else + regval |= USB_SOF_TIMER_MASK_AFTER_RESET_FS; +#endif + putreg32(regval, BFLB_USB_BASE + USB_DEV_SMT_OFFSET); + + /* enable setup irq in source group0 */ + regval = getreg32(BFLB_USB_BASE + USB_DEV_MISG0_OFFSET); + regval &= ~USB_MCX_SETUP_INT; + regval |= USB_MCX_IN_INT; + regval |= (1 << 3); + regval |= USB_MCX_OUT_INT; + regval |= USB_MCX_IN_INT; + regval |= USB_MCX_COMFAIL_INT; + regval |= USB_MCX_COMABORT_INT; + putreg32(regval, BFLB_USB_BASE + USB_DEV_MISG0_OFFSET); + + /* disable all fifo irq in source group1 */ + putreg32(0xffffffff, BFLB_USB_BASE + USB_DEV_MISG1_OFFSET); + + /* enable rst/tx0/rx0 irq in source group2 */ + regval = 0xffffffff; + regval &= ~USB_MUSBRST_INT; + regval &= ~USB_MSUSP_INT; + regval &= ~USB_MRESM_INT; + regval &= ~USB_MTX0BYTE_INT; + regval &= ~USB_MRX0BYTE_INT; + putreg32(regval, BFLB_USB_BASE + USB_DEV_MISG2_OFFSET); + + /* enable vdma cmplt and error irq in source group3 */ + regval = 0xffffffff; + regval &= ~(USB_MVDMA_CMPLT_CXF | + USB_MVDMA_CMPLT_F0 | + USB_MVDMA_CMPLT_F1 | + USB_MVDMA_CMPLT_F2 | + USB_MVDMA_CMPLT_F3); + // regval &= ~(USB_MVDMA_ERROR_CXF | + // USB_MVDMA_ERROR_F0 | + // USB_MVDMA_ERROR_F1 | + // USB_MVDMA_ERROR_F2 | + // USB_MVDMA_ERROR_F3); + putreg32(regval, BFLB_USB_BASE + USB_DEV_MISG3_OFFSET); + + /* enable group irq */ + regval = getreg32(BFLB_USB_BASE + USB_DEV_MIGR_OFFSET); + regval &= ~USB_MINT_G0; + regval &= ~USB_MINT_G1; + regval &= ~USB_MINT_G2; + regval &= ~USB_MINT_G3; + regval &= ~USB_MINT_G4; + putreg32(regval, BFLB_USB_BASE + USB_DEV_MIGR_OFFSET); + + /* enable device irq */ + regval = getreg32(BFLB_USB_BASE + USB_GLB_INT_OFFSET); + regval |= USB_MHC_INT; + regval |= USB_MOTG_INT; + regval &= ~USB_MDEV_INT; + putreg32(regval, BFLB_USB_BASE + USB_GLB_INT_OFFSET); + + bflb_usb_source_group_int_clear(2, 0x3ff); + bflb_usb_source_group_int_clear(3, 0xffffffff); + + for (uint8_t i = 1; i < 9; i++) { + bflb_usb_set_ep_fifomap(i, 15); + bflb_usb_set_fifo_epmap(i, 15, 0); + } + + /* enable vdma */ + regval = getreg32(BFLB_USB_BASE + USB_VDMA_CTRL_OFFSET); + regval |= USB_VDMA_EN; + putreg32(regval, BFLB_USB_BASE + USB_VDMA_CTRL_OFFSET); + + regval = getreg32(BFLB_USB_BASE + USB_PHY_TST_OFFSET); + regval &= ~USB_UNPLUG; + putreg32(regval, BFLB_USB_BASE + USB_PHY_TST_OFFSET); + + /* enable global irq */ + regval = getreg32(BFLB_USB_BASE + USB_DEV_CTL_OFFSET); + regval |= USB_GLINT_EN_HOV; + putreg32(regval, BFLB_USB_BASE + USB_DEV_CTL_OFFSET); + + return 0; +} + +int usb_dc_deinit(uint8_t busid) +{ + uint32_t regval; + + /* disable global irq */ + regval = getreg32(BFLB_USB_BASE + USB_DEV_CTL_OFFSET); + regval &= ~USB_GLINT_EN_HOV; + putreg32(regval, BFLB_USB_BASE + USB_DEV_CTL_OFFSET); + + regval = getreg32(BFLB_USB_BASE + USB_PHY_TST_OFFSET); + regval |= USB_UNPLUG; + putreg32(regval, BFLB_USB_BASE + USB_PHY_TST_OFFSET); + + regval = getreg32(BFLB_PDS_BASE + PDS_USB_PHY_CTRL_OFFSET); + regval &= ~PDS_REG_USB_PHY_XTLSEL_MASK; + putreg32(regval, BFLB_PDS_BASE + PDS_USB_PHY_CTRL_OFFSET); + + regval = getreg32(BFLB_PDS_BASE + PDS_USB_PHY_CTRL_OFFSET); + regval &= ~PDS_REG_PU_USB20_PSW; + putreg32(regval, BFLB_PDS_BASE + PDS_USB_PHY_CTRL_OFFSET); + + regval = getreg32(BFLB_PDS_BASE + PDS_USB_PHY_CTRL_OFFSET); + regval &= ~PDS_REG_USB_PHY_PONRST; + putreg32(regval, BFLB_PDS_BASE + PDS_USB_PHY_CTRL_OFFSET); + + regval = getreg32(BFLB_PDS_BASE + PDS_USB_CTL_OFFSET); + regval &= ~PDS_REG_USB_EXT_SUSP_N; + putreg32(regval, BFLB_PDS_BASE + PDS_USB_CTL_OFFSET); + + return 0; +} + +int usbd_set_address(uint8_t busid, const uint8_t addr) +{ + uint32_t regval; + + regval = getreg32(BFLB_USB_BASE + USB_DEV_ADR_OFFSET); + regval &= ~USB_DEVADR_MASK; + regval |= addr; + putreg32(regval, BFLB_USB_BASE + USB_DEV_ADR_OFFSET); + + return 0; +} + +int usbd_set_remote_wakeup(uint8_t busid) +{ + uint32_t regval; + + regval = getreg32(BFLB_USB_BASE + USB_DEV_CTL_OFFSET); + regval |= USB_CAP_RMWAKUP; + putreg32(regval, BFLB_USB_BASE + USB_DEV_CTL_OFFSET); + + bflb_mtimer_delay_ms(10); + + regval = getreg32(BFLB_USB_BASE + USB_DEV_CTL_OFFSET); + regval &= ~USB_CAP_RMWAKUP; + putreg32(regval, BFLB_USB_BASE + USB_DEV_CTL_OFFSET); + + return 0; +} + +uint8_t usbd_get_port_speed(uint8_t busid) +{ + uint8_t speed = 3; + + speed = (getreg32(BFLB_USB_BASE + USB_OTG_CSR_OFFSET) & USB_SPD_TYP_HOV_POV_MASK) >> USB_SPD_TYP_HOV_POV_SHIFT; + + if (speed == 0) { + return USB_SPEED_FULL; + } else if (speed == 1) { + return USB_SPEED_LOW; + } else if (speed == 2) { + return USB_SPEED_HIGH; + } + return USB_SPEED_HIGH; +} + +int usbd_ep_open(uint8_t busid, const struct usb_endpoint_descriptor *ep) +{ + uint8_t ep_addr; + uint32_t regval; + + ep_addr = ep->bEndpointAddress; + + uint8_t ep_idx = USB_EP_GET_IDX(ep_addr); + + if (ep_idx > 4) { + return 0; + } + + if (USB_EP_DIR_IS_OUT(ep_addr)) { + g_bl_udc.out_ep[ep_idx].ep_mps = USB_GET_MAXPACKETSIZE(ep->wMaxPacketSize); + g_bl_udc.out_ep[ep_idx].ep_type = USB_GET_ENDPOINT_TYPE(ep->bmAttributes); + g_bl_udc.out_ep[ep_idx].ep_enable = 1U; + bflb_usb_set_outep_mps(ep_idx, USB_GET_MAXPACKETSIZE(ep->wMaxPacketSize)); + } else { + g_bl_udc.in_ep[ep_idx].ep_mps = USB_GET_MAXPACKETSIZE(ep->wMaxPacketSize); + g_bl_udc.in_ep[ep_idx].ep_type = USB_GET_ENDPOINT_TYPE(ep->bmAttributes); + g_bl_udc.in_ep[ep_idx].ep_enable = 1U; + bflb_usb_set_inep_mps(ep_idx, USB_GET_MAXPACKETSIZE(ep->wMaxPacketSize)); + bflb_usb_set_mult(ep_idx, 0); + } + + if (ep_idx != 0) { +#if !defined(CONFIG_USB_PINGPONG_ENABLE) && !defined(CONFIG_USB_TRIPLE_ENABLE) + if (USB_GET_MAXPACKETSIZE(ep->wMaxPacketSize) > 512) { + bflb_usb_set_ep_fifomap(1, USB_FIFO_F0); + bflb_usb_set_ep_fifomap(2, USB_FIFO_F2); + + bflb_usb_set_fifo_epmap(USB_FIFO_F0, 1, USB_FIFO_DIR_BID); + bflb_usb_set_fifo_epmap(USB_FIFO_F1, 1, USB_FIFO_DIR_BID); + bflb_usb_set_fifo_epmap(USB_FIFO_F2, 2, USB_FIFO_DIR_BID); + bflb_usb_set_fifo_epmap(USB_FIFO_F3, 2, USB_FIFO_DIR_BID); + + if (ep_idx == 1) { + bflb_usb_fifo_config(USB_FIFO_F0, USB_GET_ENDPOINT_TYPE(ep->bmAttributes), 1024, 1, true); + bflb_usb_fifo_config(USB_FIFO_F1, USB_GET_ENDPOINT_TYPE(ep->bmAttributes), 1024, 1, false); + } else if (ep_idx == 2) { + bflb_usb_fifo_config(USB_FIFO_F2, USB_GET_ENDPOINT_TYPE(ep->bmAttributes), 1024, 1, true); + bflb_usb_fifo_config(USB_FIFO_F3, USB_GET_ENDPOINT_TYPE(ep->bmAttributes), 1024, 1, false); + } else { + return -1; + } + } else { + bflb_usb_set_ep_fifomap(1, USB_FIFO_F0); + bflb_usb_set_ep_fifomap(2, USB_FIFO_F1); + bflb_usb_set_ep_fifomap(3, USB_FIFO_F2); + bflb_usb_set_ep_fifomap(4, USB_FIFO_F3); + + bflb_usb_set_fifo_epmap(USB_FIFO_F0, 1, USB_FIFO_DIR_BID); + bflb_usb_set_fifo_epmap(USB_FIFO_F1, 2, USB_FIFO_DIR_BID); + bflb_usb_set_fifo_epmap(USB_FIFO_F2, 3, USB_FIFO_DIR_BID); + bflb_usb_set_fifo_epmap(USB_FIFO_F3, 4, USB_FIFO_DIR_BID); + + if (ep_idx == 1) { + bflb_usb_fifo_config(USB_FIFO_F0, USB_GET_ENDPOINT_TYPE(ep->bmAttributes), 512, 1, true); + } else if (ep_idx == 2) { + bflb_usb_fifo_config(USB_FIFO_F1, USB_GET_ENDPOINT_TYPE(ep->bmAttributes), 512, 1, true); + } else if (ep_idx == 3) { + bflb_usb_fifo_config(USB_FIFO_F2, USB_GET_ENDPOINT_TYPE(ep->bmAttributes), 512, 1, true); + } else if (ep_idx == 4) { + bflb_usb_fifo_config(USB_FIFO_F3, USB_GET_ENDPOINT_TYPE(ep->bmAttributes), 512, 1, true); + } else { + return -1; + } + } +#elif defined(CONFIG_USB_PINGPONG_ENABLE) + if (USB_GET_MAXPACKETSIZE(ep->wMaxPacketSize) > 512) { + bflb_usb_set_ep_fifomap(1, USB_FIFO_F0); + + bflb_usb_set_fifo_epmap(USB_FIFO_F0, 1, USB_FIFO_DIR_BID); + bflb_usb_set_fifo_epmap(USB_FIFO_F1, 1, USB_FIFO_DIR_BID); + bflb_usb_set_fifo_epmap(USB_FIFO_F2, 1, USB_FIFO_DIR_BID); + bflb_usb_set_fifo_epmap(USB_FIFO_F3, 1, USB_FIFO_DIR_BID); + + if (ep_idx == 1) { + bflb_usb_fifo_config(USB_FIFO_F0, USB_GET_ENDPOINT_TYPE(ep->bmAttributes), 1024, 2, true); + bflb_usb_fifo_config(USB_FIFO_F1, USB_GET_ENDPOINT_TYPE(ep->bmAttributes), 1024, 2, false); + bflb_usb_fifo_config(USB_FIFO_F2, USB_GET_ENDPOINT_TYPE(ep->bmAttributes), 1024, 2, false); + bflb_usb_fifo_config(USB_FIFO_F3, USB_GET_ENDPOINT_TYPE(ep->bmAttributes), 1024, 2, false); + } else { + return -1; + } + } else { + bflb_usb_set_ep_fifomap(1, USB_FIFO_F0); + bflb_usb_set_ep_fifomap(2, USB_FIFO_F2); + + bflb_usb_set_fifo_epmap(USB_FIFO_F0, 1, USB_FIFO_DIR_BID); + bflb_usb_set_fifo_epmap(USB_FIFO_F1, 1, USB_FIFO_DIR_BID); + bflb_usb_set_fifo_epmap(USB_FIFO_F2, 2, USB_FIFO_DIR_BID); + bflb_usb_set_fifo_epmap(USB_FIFO_F3, 2, USB_FIFO_DIR_BID); + + if (ep_idx == 1) { + bflb_usb_fifo_config(USB_FIFO_F0, USB_GET_ENDPOINT_TYPE(ep->bmAttributes), 512, 2, true); + bflb_usb_fifo_config(USB_FIFO_F1, USB_GET_ENDPOINT_TYPE(ep->bmAttributes), 512, 2, false); + } else if (ep_idx == 2) { + bflb_usb_fifo_config(USB_FIFO_F2, USB_GET_ENDPOINT_TYPE(ep->bmAttributes), 512, 2, true); + bflb_usb_fifo_config(USB_FIFO_F3, USB_GET_ENDPOINT_TYPE(ep->bmAttributes), 512, 2, false); + } else { + return -1; + } + } +#elif defined(CONFIG_USB_TRIPLE_ENABLE) + if (USB_GET_MAXPACKETSIZE(ep->wMaxPacketSize) > 512) { + return -1; + } else { + bflb_usb_set_ep_fifomap(1, USB_FIFO_F0); + bflb_usb_set_ep_fifomap(2, USB_FIFO_F3); + + bflb_usb_set_fifo_epmap(USB_FIFO_F0, 1, USB_FIFO_DIR_BID); + bflb_usb_set_fifo_epmap(USB_FIFO_F1, 1, USB_FIFO_DIR_BID); + bflb_usb_set_fifo_epmap(USB_FIFO_F2, 1, USB_FIFO_DIR_BID); + bflb_usb_set_fifo_epmap(USB_FIFO_F3, 2, USB_FIFO_DIR_BID); + + if (ep_idx == 1) { + bflb_usb_fifo_config(USB_FIFO_F0, USB_GET_ENDPOINT_TYPE(ep->bmAttributes), 512, 3, true); + bflb_usb_fifo_config(USB_FIFO_F1, USB_GET_ENDPOINT_TYPE(ep->bmAttributes), 512, 3, false); + bflb_usb_fifo_config(USB_FIFO_F2, USB_GET_ENDPOINT_TYPE(ep->bmAttributes), 512, 3, false); + } else if (ep_idx == 2) { + bflb_usb_fifo_config(USB_FIFO_F3, USB_GET_ENDPOINT_TYPE(ep->bmAttributes), 512, 1, true); + } else { + return -1; + } + } +#endif + regval = getreg32(BFLB_USB_BASE + USB_DEV_ADR_OFFSET); + regval |= USB_AFT_CONF; + putreg32(regval, BFLB_USB_BASE + USB_DEV_ADR_OFFSET); + } + return 0; +} + +int usbd_ep_close(uint8_t busid, const uint8_t ep) +{ + return 0; +} + +int usbd_ep_set_stall(uint8_t busid, const uint8_t ep) +{ + uint32_t regval; + + uint8_t ep_idx = USB_EP_GET_IDX(ep); + + if (ep_idx == 0) { + regval = getreg32(BFLB_USB_BASE + USB_DEV_CXCFE_OFFSET); + regval |= USB_CX_STL; + putreg32(regval, BFLB_USB_BASE + USB_DEV_CXCFE_OFFSET); + } else { + if (USB_EP_DIR_IS_OUT(ep)) { + regval = getreg32(BFLB_USB_BASE + USB_DEV_OUTMPS1_OFFSET + (ep_idx - 1) * 4); + regval |= USB_STL_OEP1; + //regval |= USB_RSTG_OEP1; + putreg32(regval, BFLB_USB_BASE + USB_DEV_OUTMPS1_OFFSET + (ep_idx - 1) * 4); + } else { + regval = getreg32(BFLB_USB_BASE + USB_DEV_INMPS1_OFFSET + (ep_idx - 1) * 4); + regval |= USB_STL_IEP1; + //regval |= USB_RSTG_IEP1; + putreg32(regval, BFLB_USB_BASE + USB_DEV_INMPS1_OFFSET + (ep_idx - 1) * 4); + } + } + + return 0; +} + +int usbd_ep_clear_stall(uint8_t busid, const uint8_t ep) +{ + uint32_t regval; + + uint8_t ep_idx = USB_EP_GET_IDX(ep); + + if (ep_idx == 0) { + } else { + if (USB_EP_DIR_IS_OUT(ep)) { + regval = getreg32(BFLB_USB_BASE + USB_DEV_OUTMPS1_OFFSET + (ep_idx - 1) * 4); + //regval &= ~USB_RSTG_OEP1; + regval &= ~USB_STL_OEP1; + putreg32(regval, BFLB_USB_BASE + USB_DEV_OUTMPS1_OFFSET + (ep_idx - 1) * 4); + } else { + regval = getreg32(BFLB_USB_BASE + USB_DEV_INMPS1_OFFSET + (ep_idx - 1) * 4); + //regval &= ~USB_RSTG_IEP1; + regval &= ~USB_STL_IEP1; + putreg32(regval, BFLB_USB_BASE + USB_DEV_INMPS1_OFFSET + (ep_idx - 1) * 4); + } + } + + return 0; +} + +int usbd_ep_is_stalled(uint8_t busid, const uint8_t ep, uint8_t *stalled) +{ + uint32_t regval; + + uint8_t ep_idx = USB_EP_GET_IDX(ep); + + if (ep_idx == 0) { + } else { + if (USB_EP_DIR_IS_OUT(ep)) { + regval = getreg32(BFLB_USB_BASE + USB_DEV_OUTMPS1_OFFSET + (ep_idx - 1) * 4); + if (regval & USB_STL_OEP1) { + *stalled = 1; + } else { + *stalled = 0; + } + } else { + regval = getreg32(BFLB_USB_BASE + USB_DEV_INMPS1_OFFSET + (ep_idx - 1) * 4); + if (regval & USB_STL_IEP1) { + *stalled = 1; + } else { + *stalled = 0; + } + } + } + + return 0; +} + +int usbd_ep_start_write(uint8_t busid, const uint8_t ep, const uint8_t *data, uint32_t data_len) +{ + uint8_t ep_idx = USB_EP_GET_IDX(ep); + + if (!data && data_len) { + return -1; + } + + if (!g_bl_udc.in_ep[ep_idx].ep_enable) { + return -2; + } + + g_bl_udc.in_ep[ep_idx].xfer_buf = (uint8_t *)data; + g_bl_udc.in_ep[ep_idx].xfer_len = data_len; + g_bl_udc.in_ep[ep_idx].actual_xfer_len = 0; + g_bl_udc.in_ep[ep_idx].ep_active = true; + + if (ep_idx == 0) { + if (data_len == 0) { + g_bl_udc.in_ep[ep_idx].ep_active = false; + bflb_usb_control_transfer_done(); + } else { + data_len = MIN(data_len, g_bl_udc.in_ep[ep_idx].ep_mps); + g_bl_udc.in_ep[ep_idx].xfer_len = data_len; + bflb_usb_vdma_start_write(USB_FIFO_CXF, data, data_len); + } + } else { + if (data_len == 0) { + bflb_usb_send_zlp(ep_idx); + } else { + bflb_usb_vdma_start_write(usb_get_transfer_fifo(ep_idx), data, data_len); + } + } + + return 0; +} + +int usbd_ep_start_read(uint8_t busid, const uint8_t ep, uint8_t *data, uint32_t data_len) +{ + uint8_t ep_idx = USB_EP_GET_IDX(ep); + + if (!data && data_len) { + return -1; + } + + if (!g_bl_udc.out_ep[ep_idx].ep_enable) { + return -2; + } + + if (data_len == 0) { + return 0; + } + + g_bl_udc.out_ep[ep_idx].xfer_buf = (uint8_t *)data; + g_bl_udc.out_ep[ep_idx].xfer_len = data_len; + g_bl_udc.out_ep[ep_idx].actual_xfer_len = 0; + g_bl_udc.out_ep[ep_idx].ep_active = true; + + if (ep_idx == 0) { + data_len = MIN(data_len, g_bl_udc.out_ep[ep_idx].ep_mps); + g_bl_udc.out_ep[ep_idx].xfer_len = data_len; + bflb_usb_vdma_start_read(USB_FIFO_CXF, data, data_len); + } else { + bflb_usb_vdma_start_read(usb_get_transfer_fifo(ep_idx), data, data_len); + } + return 0; +} + +void USBD_IRQHandler(uint8_t busid) +{ + uint32_t glb_intstatus; + uint32_t dev_intstatus; + uint32_t subgroup_intstatus; + uint32_t regval; + uint8_t ep_idx; + + glb_intstatus = getreg32(BFLB_USB_BASE + USB_GLB_ISR_OFFSET); + + if (glb_intstatus & USB_DEV_INT) { + dev_intstatus = getreg32(BFLB_USB_BASE + USB_DEV_IGR_OFFSET); + if (dev_intstatus & USB_INT_G0) { + subgroup_intstatus = bflb_usb_get_source_group_intstatus(0); + + if (subgroup_intstatus & USB_CX_SETUP_INT) { + bflb_usb_vdma_start_read(USB_FIFO_CXF, g_setup_buffer, 8); + while (getreg32(BFLB_USB_BASE + USB_VDMA_CXFPS1_OFFSET) & USB_VDMA_START_CXF) { + } + + bflb_usb_source_group_int_clear(3, USB_VDMA_CMPLT_CXF); + + usbd_event_ep0_setup_complete_handler(0, g_setup_buffer); + } + } + if (dev_intstatus & USB_INT_G1) { + } + if (dev_intstatus & USB_INT_G2) { + subgroup_intstatus = bflb_usb_get_source_group_intstatus(2); + + if (subgroup_intstatus & USB_SUSP_INT) { + bflb_usb_source_group_int_clear(2, USB_SUSP_INT); + + bflb_usb_reset_fifo(USB_FIFO_F0); + bflb_usb_reset_fifo(USB_FIFO_F1); + bflb_usb_reset_fifo(USB_FIFO_F2); + bflb_usb_reset_fifo(USB_FIFO_F3); + bflb_usb_reset_fifo(USB_FIFO_CXF); + + usbd_event_suspend_handler(0); + } + if (subgroup_intstatus & USB_RESM_INT) { + bflb_usb_source_group_int_clear(2, USB_RESM_INT); + usbd_event_resume_handler(0); + } + if (subgroup_intstatus & USB_TX0BYTE_INT) { + for (uint8_t i = 1; i < 5; i++) { + if (bflb_usb_get_tx_zlp_intstatus() & (1 << (i - 1))) { + bflb_usb_clear_tx_zlp_intstatus(i); + usbd_event_ep_in_complete_handler(0, i | 0x80, 0); + } + } + bflb_usb_source_group_int_clear(2, USB_TX0BYTE_INT); + } + if (subgroup_intstatus & USB_RX0BYTE_INT) { + for (uint8_t i = 1; i < 5; i++) { + if (bflb_usb_get_rx_zlp_intstatus() & (1 << (i - 1))) { + bflb_usb_clear_rx_zlp_intstatus(i); + usbd_event_ep_out_complete_handler(0, i, 0); + } + } + + bflb_usb_source_group_int_clear(2, USB_RX0BYTE_INT); + } + if (subgroup_intstatus & USBRST_INT) { + bflb_usb_source_group_int_clear(2, USBRST_INT); + + bflb_usb_reset_fifo(USB_FIFO_F0); + bflb_usb_reset_fifo(USB_FIFO_F1); + bflb_usb_reset_fifo(USB_FIFO_F2); + bflb_usb_reset_fifo(USB_FIFO_F3); + bflb_usb_reset_fifo(USB_FIFO_CXF); + + regval = getreg32(BFLB_USB_BASE + USB_DEV_SMT_OFFSET); + regval &= ~USB_SOFMT_MASK; +#ifdef CONFIG_USB_HS + regval |= USB_SOF_TIMER_MASK_AFTER_RESET_HS; +#else + regval |= USB_SOF_TIMER_MASK_AFTER_RESET_FS; +#endif + putreg32(regval, BFLB_USB_BASE + USB_DEV_SMT_OFFSET); + + memset(&g_bl_udc, 0, sizeof(g_bl_udc)); + + usbd_event_reset_handler(0); + } + } + if (dev_intstatus & USB_INT_G3) { + subgroup_intstatus = bflb_usb_get_source_group_intstatus(3); + bflb_usb_source_group_int_clear(3, subgroup_intstatus); + if (subgroup_intstatus & USB_VDMA_CMPLT_CXF) { + if (g_bl_udc.in_ep[0].ep_active) { + g_bl_udc.in_ep[0].ep_active = false; + g_bl_udc.in_ep[0].actual_xfer_len = g_bl_udc.in_ep[0].xfer_len - bflb_usb_vdma_get_remain_size(USB_FIFO_CXF); + if (g_bl_udc.in_ep[0].actual_xfer_len < g_bl_udc.in_ep[0].ep_mps) { + bflb_usb_control_transfer_done(); + } + usbd_event_ep_in_complete_handler(0, 0x80, g_bl_udc.in_ep[0].actual_xfer_len); + } else { + g_bl_udc.out_ep[0].ep_active = false; + g_bl_udc.out_ep[0].actual_xfer_len = g_bl_udc.out_ep[0].xfer_len - bflb_usb_vdma_get_remain_size(USB_FIFO_CXF); + usbd_event_ep_out_complete_handler(0, 0x00, g_bl_udc.out_ep[0].actual_xfer_len); + } + } + + for (uint8_t i = 0; i < 4; i++) { + if (subgroup_intstatus & (1 << (i + 1))) { + ep_idx = bflb_usb_get_fifo_ep(i); + if (g_bl_udc.in_ep[ep_idx].ep_active) { + g_bl_udc.in_ep[ep_idx].ep_active = 0; + g_bl_udc.in_ep[ep_idx].actual_xfer_len = g_bl_udc.in_ep[ep_idx].xfer_len - bflb_usb_vdma_get_remain_size(i); + usbd_event_ep_in_complete_handler(0, ep_idx | 0x80, g_bl_udc.in_ep[ep_idx].actual_xfer_len); + } else if (g_bl_udc.out_ep[ep_idx].ep_active) { + g_bl_udc.out_ep[ep_idx].ep_active = 0; + g_bl_udc.out_ep[ep_idx].actual_xfer_len = g_bl_udc.out_ep[ep_idx].xfer_len - bflb_usb_vdma_get_remain_size(i); + usbd_event_ep_out_complete_handler(0, ep_idx & 0x7f, g_bl_udc.out_ep[ep_idx].actual_xfer_len); + } + } + } + } + if (dev_intstatus & USB_INT_G4) { + } + } +} + +#ifdef CONFIG_USBDEV_TEST_MODE +void usbd_execute_test_mode(uint8_t busid, uint8_t test_mode) +{ + uint32_t regval; + + switch (test_mode) { + case 1: // Test_J + { + regval = getreg32(BFLB_USB_BASE + USB_PHY_TST_OFFSET); + regval |= USB_TST_JSTA; + putreg32(regval, BFLB_USB_BASE + USB_PHY_TST_OFFSET); + bflb_usb_control_transfer_done(); + } break; + case 2: // Test_K + { + regval = getreg32(BFLB_USB_BASE + USB_PHY_TST_OFFSET); + regval |= USB_TST_KSTA; + putreg32(regval, BFLB_USB_BASE + USB_PHY_TST_OFFSET); + + bflb_usb_control_transfer_done(); + } break; + case 3: // TEST_SE0_NAK + { + regval = getreg32(BFLB_USB_BASE + USB_PHY_TST_OFFSET); + regval |= USB_TST_SE0NAK; + putreg32(regval, BFLB_USB_BASE + USB_PHY_TST_OFFSET); + + bflb_usb_control_transfer_done(); + } break; + case 4: // Test_Packet + { + bflb_usb_control_transfer_done(); + regval = getreg32(BFLB_USB_BASE + USB_PHY_TST_OFFSET); + regval |= USB_TST_PKT; + putreg32(regval, BFLB_USB_BASE + USB_PHY_TST_OFFSET); + + __attribute__((aligned(32))) uint8_t temp[53]; + uint8_t *pp; + uint8_t i; + pp = temp; + + for (i = 0; i < 9; i++) /*JKJKJKJK x 9*/ + *pp++ = 0x00; + + for (i = 0; i < 8; i++) /* 8*AA */ + *pp++ = 0xAA; + + for (i = 0; i < 8; i++) /* 8*EE */ + *pp++ = 0xEE; + + *pp++ = 0xFE; + + for (i = 0; i < 11; i++) /* 11*FF */ + *pp++ = 0xFF; + + *pp++ = 0x7F; + *pp++ = 0xBF; + *pp++ = 0xDF; + *pp++ = 0xEF; + *pp++ = 0xF7; + *pp++ = 0xFB; + *pp++ = 0xFD; + *pp++ = 0xFC; + *pp++ = 0x7E; + *pp++ = 0xBF; + *pp++ = 0xDF; + *pp++ = 0xEF; + *pp++ = 0xF7; + *pp++ = 0xFB; + *pp++ = 0xFD; + *pp++ = 0x7E; + + bflb_usb_vdma_start_write(USB_FIFO_CXF, temp, 53); + + regval = getreg32(BFLB_USB_BASE + USB_DEV_CXCFE_OFFSET); + regval |= USB_TST_PKDONE; + putreg32(regval, BFLB_USB_BASE + USB_DEV_CXCFE_OFFSET); + + } break; + case 5: // Test_Force_Enable + break; + + default: + break; + } +} +#endif \ No newline at end of file diff --git a/kernel/cherryusb/port/ch32/README.md b/kernel/cherryusb/port/ch32/README.md new file mode 100644 index 0000000..68a1ab7 --- /dev/null +++ b/kernel/cherryusb/port/ch32/README.md @@ -0,0 +1,16 @@ +# Note + +## Support Chip List + +## CH32FS + +- CH32V30X/CH32V20X/CH32V10X/CH32X035 + +## CH32HS + +- CH32V30X + +## CH58X + +- CH57X/CH58X(usbfs) +- CH585(usbhs) diff --git a/kernel/cherryusb/port/ch32/ch32fs/usb_ch32_usbfs_reg.h b/kernel/cherryusb/port/ch32/ch32fs/usb_ch32_usbfs_reg.h new file mode 100644 index 0000000..34a9607 --- /dev/null +++ b/kernel/cherryusb/port/ch32/ch32fs/usb_ch32_usbfs_reg.h @@ -0,0 +1,409 @@ +/* + * Copyright (c) 2022, sakumisu + * + * SPDX-License-Identifier: Apache-2.0 + */ +#ifndef _USB_CH32_USBFS_REG_H +#define _USB_CH32_USBFS_REG_H + +#define __IO volatile /* defines 'read / write' permissions */ + +/* USBOTG_FS Registers */ +typedef struct +{ + __IO uint8_t BASE_CTRL; + __IO uint8_t UDEV_CTRL; + __IO uint8_t INT_EN; + __IO uint8_t DEV_ADDR; + __IO uint8_t Reserve0; + __IO uint8_t MIS_ST; + __IO uint8_t INT_FG; + __IO uint8_t INT_ST; + __IO uint16_t RX_LEN; + __IO uint16_t Reserve1; + __IO uint8_t UEP4_1_MOD; + __IO uint8_t UEP2_3_MOD; + __IO uint8_t UEP5_6_MOD; + __IO uint8_t UEP7_MOD; + __IO uint32_t UEP0_DMA; + __IO uint32_t UEP1_DMA; + __IO uint32_t UEP2_DMA; + __IO uint32_t UEP3_DMA; + __IO uint32_t UEP4_DMA; + __IO uint32_t UEP5_DMA; + __IO uint32_t UEP6_DMA; + __IO uint32_t UEP7_DMA; + __IO uint16_t UEP0_TX_LEN; + __IO uint8_t UEP0_TX_CTRL; + __IO uint8_t UEP0_RX_CTRL; + __IO uint16_t UEP1_TX_LEN; + __IO uint8_t UEP1_TX_CTRL; + __IO uint8_t UEP1_RX_CTRL; + __IO uint16_t UEP2_TX_LEN; + __IO uint8_t UEP2_TX_CTRL; + __IO uint8_t UEP2_RX_CTRL; + __IO uint16_t UEP3_TX_LEN; + __IO uint8_t UEP3_TX_CTRL; + __IO uint8_t UEP3_RX_CTRL; + __IO uint16_t UEP4_TX_LEN; + __IO uint8_t UEP4_TX_CTRL; + __IO uint8_t UEP4_RX_CTRL; + __IO uint16_t UEP5_TX_LEN; + __IO uint8_t UEP5_TX_CTRL; + __IO uint8_t UEP5_RX_CTRL; + __IO uint16_t UEP6_TX_LEN; + __IO uint8_t UEP6_TX_CTRL; + __IO uint8_t UEP6_RX_CTRL; + __IO uint16_t UEP7_TX_LEN; + __IO uint8_t UEP7_TX_CTRL; + __IO uint8_t UEP7_RX_CTRL; + __IO uint32_t Reserve2; + __IO uint32_t OTG_CR; + __IO uint32_t OTG_SR; +} USBOTG_FS_TypeDef; + +typedef struct __attribute__((packed)) { + __IO uint8_t BASE_CTRL; + __IO uint8_t HOST_CTRL; + __IO uint8_t INT_EN; + __IO uint8_t DEV_ADDR; + __IO uint8_t Reserve0; + __IO uint8_t MIS_ST; + __IO uint8_t INT_FG; + __IO uint8_t INT_ST; + __IO uint16_t RX_LEN; + __IO uint16_t Reserve1; + __IO uint8_t Reserve2; + __IO uint8_t HOST_EP_MOD; + __IO uint16_t Reserve3; + __IO uint32_t Reserve4; + __IO uint32_t Reserve5; + __IO uint32_t HOST_RX_DMA; + __IO uint32_t HOST_TX_DMA; + __IO uint32_t Reserve6; + __IO uint32_t Reserve7; + __IO uint32_t Reserve8; + __IO uint32_t Reserve9; + __IO uint32_t Reserve10; + __IO uint16_t Reserve11; + __IO uint16_t HOST_SETUP; + __IO uint8_t HOST_EP_PID; + __IO uint8_t Reserve12; + __IO uint8_t Reserve13; + __IO uint8_t HOST_RX_CTRL; + __IO uint16_t HOST_TX_LEN; + __IO uint8_t HOST_TX_CTRL; + __IO uint8_t Reserve14; + __IO uint32_t Reserve15; + __IO uint32_t Reserve16; + __IO uint32_t Reserve17; + __IO uint32_t Reserve18; + __IO uint32_t Reserve19; + __IO uint32_t OTG_CR; + __IO uint32_t OTG_SR; +} USBOTGH_FS_TypeDef; + +typedef struct +{ + __IO uint8_t BASE_CTRL; /*!< 0x40008000 */ + __IO uint8_t HOST_CTRL; /*!< 0x40008001 */ + __IO uint8_t INT_EN; /*!< 0x40008002 */ + __IO uint8_t DEV_ADDR; /*!< 0x40008003 */ + __IO uint8_t USB_STATUS0; /*!< 0x40008004 */ + __IO uint8_t MIS_ST; /*!< 0x40008005 */ + __IO uint8_t INT_FG; /*!< 0x40008006 */ + __IO uint8_t INT_ST; /*!< 0x40008007 */ + __IO uint8_t RX_LEN; /*!< 0x40008008 */ + __IO uint8_t Reserve1; /*!< 0x40008009 */ + __IO uint8_t Reserve2; /*!< 0x4000800a */ + __IO uint8_t Reserve3; /*!< 0x4000800b */ + __IO uint8_t UEP4_1_MOD; /*!< 0x4000800c */ + __IO uint8_t HOST_EP_MOD; /*!< 0x4000800d */ + __IO uint8_t UEP567_MOD; /*!< 0x4000800e */ + __IO uint8_t Reserve4; /*!< 0x4000800f */ + __IO uint16_t UEP0_DMA; /*!< 0x40008010 */ + __IO uint16_t Reserve5; /*!< 0x40008012 */ + __IO uint16_t UEP1_DMA; /*!< 0x40008014 */ + __IO uint16_t Reserve6; /*!< 0x40008016 */ + __IO uint16_t HOST_RX_DMA; /*!< 0x40008018 */ + __IO uint16_t Reserve7; /*!< 0x4000801a */ + __IO uint16_t HOST_TX_DMA; /*!< 0x4000801c */ + __IO uint16_t Reserve8; /*!< 0x4000801e */ + __IO uint8_t UEP0_T_LEN; /*!< 0x40008020 */ + __IO uint8_t Reserve9; /*!< 0x40008021 */ + __IO uint8_t UEP0_CTRL; /*!< 0x40008022 */ + __IO uint8_t Reserve10; /*!< 0x40008023 */ + __IO uint8_t UEP1_T_LEN; /*!< 0x40008024 */ + __IO uint8_t Reserve11; /*!< 0x40008025 */ + __IO uint8_t HOST_SETUP; /*!< 0x40008026 */ + __IO uint8_t Reserve12; /*!< 0x40008027 */ + __IO uint8_t HOST_EP_PID; /*!< 0x40008028 */ + __IO uint8_t Reserve13; /*!< 0x40008029 */ + __IO uint8_t HOST_RX_CTRL; /*!< 0x4000802a */ + __IO uint8_t Reserve14; /*!< 0x4000802b */ + __IO uint8_t HOST_TX_LEN; /*!< 0x4000802c */ + __IO uint8_t Reserve15; /*!< 0x4000802d */ + __IO uint8_t HOST_TX_CTRL; /*!< 0x4000802e */ + __IO uint8_t Reserve16; /*!< 0x4000802f */ + __IO uint8_t UEP4_T_LEN; /*!< 0x40008030 */ + __IO uint8_t Reserve17; /*!< 0x40008031 */ + __IO uint8_t UEP4_CTRL; /*!< 0x40008032 */ + __IO uint8_t Reserve18[33]; /*!< 0x40008033 */ + __IO uint16_t UEP5_DMA; /*!< 0x40008054 */ + __IO uint16_t Reserve19; /*!< 0x40008056 */ + __IO uint16_t UEP6_DMA; /*!< 0x40008058 */ + __IO uint16_t Reserve20; /*!< 0x4000805a */ + __IO uint16_t UEP7_DMA; /*!< 0x4000805c */ + __IO uint8_t Reserve21[6]; /*!< 0x4000805e */ + __IO uint8_t UEP5_T_LEN; /*!< 0x40008064 */ + __IO uint8_t Reserve22; /*!< 0x40008065 */ + __IO uint8_t UEP5_CTRL; /*!< 0x40008066 */ + __IO uint8_t Reserve23; /*!< 0x40008067 */ + __IO uint8_t UEP6_T_LEN; /*!< 0x40008068 */ + __IO uint8_t Reserve24; /*!< 0x40008069 */ + __IO uint8_t UEP6_CTRL; /*!< 0x4000806a */ + __IO uint8_t Reserve25; /*!< 0x4000806b */ + __IO uint8_t UEP7_T_LEN; /*!< 0x4000806c */ + __IO uint8_t Reserve26; /*!< 0x4000806d */ + __IO uint8_t UEP7_CTRL; /*!< 0x4000806e */ +} USB_FS_TypeDef; + +#define USBFS_BASE ((uint32_t)0x50000000) + +#define USBFS_DEVICE ((USBOTG_FS_TypeDef *)USBFS_BASE) +#define USBFS_HOST ((USBOTGH_FS_TypeDef *)USBFS_BASE) + +/******************* GLOBAL ******************/ + +/* BASE USB_CTRL */ +#define USBFS_BASE_CTRL_OFFSET 0x00 // USB base control +#define USBFS_UC_HOST_MODE 0x80 // enable USB host mode: 0=device mode, 1=host mode +#define USBFS_UC_LOW_SPEED 0x40 // enable USB low speed: 0=12Mbps, 1=1.5Mbps +#define USBFS_UC_DEV_PU_EN 0x20 // USB device enable and internal pullup resistance enable +#define USBFS_UC_SYS_CTRL1 0x20 // USB system control high bit +#define USBFS_UC_SYS_CTRL0 0x10 // USB system control low bit +#define USBFS_UC_SYS_CTRL_MASK 0x30 // bit mask of USB system control +// UC_HOST_MODE & UC_SYS_CTRL1 & UC_SYS_CTRL0: USB system control +// 0 00: disable USB device and disable internal pullup resistance +// 0 01: enable USB device and disable internal pullup resistance, need external pullup resistance +// 0 1x: enable USB device and enable internal pullup resistance +// 1 00: enable USB host and normal status +// 1 01: enable USB host and force UDP/UDM output SE0 state +// 1 10: enable USB host and force UDP/UDM output J state +// 1 11: enable USB host and force UDP/UDM output resume or K state +#define USBFS_UC_INT_BUSY 0x08 // enable automatic responding busy for device mode or automatic pause for host mode during interrupt flag UIF_TRANSFER valid +#define USBFS_UC_RESET_SIE 0x04 // force reset USB SIE, need software clear +#define USBFS_UC_CLR_ALL 0x02 // force clear FIFO and count of USB +#define USBFS_UC_DMA_EN 0x01 // DMA enable and DMA interrupt enable for USB + +/* USB INT EN */ +#define USBFS_INT_EN_OFFSET 0x02 +#define USBFS_UIE_DEV_SOF 0x80 // enable interrupt for SOF received for USB device mode +#define USBFS_UIE_DEV_NAK 0x40 // enable interrupt for NAK responded for USB device mode +#define USBFS_UIE_FIFO_OV 0x10 // enable interrupt for FIFO overflow +#define USBFS_UIE_HST_SOF 0x08 // enable interrupt for host SOF timer action for USB host mode +#define USBFS_UIE_SUSPEND 0x04 // enable interrupt for USB suspend or resume event +#define USBFS_UIE_TRANSFER 0x02 // enable interrupt for USB transfer completion +#define USBFS_UIE_DETECT 0x01 // enable interrupt for USB device detected event for USB host mode +#define USBFS_UIE_BUS_RST 0x01 // enable interrupt for USB bus reset event for USB device mode +/* USB_DEV_ADDR */ +#define USBFS_DEV_ADDR_OFFSET 0x03 +#define USBFS_UDA_GP_BIT 0x80 // general purpose bit +#define USBFS_USB_ADDR_MASK 0x7F // bit mask for USB device address + +/* USB_STATUS */ +#define USBFS_USB_STATUS_OFFSET 0x04 + +/* USB_MIS_ST */ +#define USBFS_MIS_ST_OFFSET 0x05 +#define USBFS_UMS_SOF_PRES 0x80 // RO, indicate host SOF timer presage status +#define USBFS_UMS_SOF_ACT 0x40 // RO, indicate host SOF timer action status for USB host +#define USBFS_UMS_SIE_FREE 0x20 // RO, indicate USB SIE free status +#define USBFS_UMS_R_FIFO_RDY 0x10 // RO, indicate USB receiving FIFO ready status (not empty) +#define USBFS_UMS_BUS_RESET 0x08 // RO, indicate USB bus reset status +#define USBFS_UMS_SUSPEND 0x04 // RO, indicate USB suspend status +#define USBFS_UMS_DM_LEVEL 0x02 // RO, indicate UDM level saved at device attached to USB host +#define USBFS_UMS_DEV_ATTACH 0x01 // RO, indicate device attached status on USB host + +/* USB_INT_FG */ +#define USBFS_INT_FG_OFFSET 0x06 +#define USBFS_U_IS_NAK 0x80 // RO, indicate current USB transfer is NAK received +#define USBFS_U_TOG_OK 0x40 // RO, indicate current USB transfer toggle is OK +#define USBFS_U_SIE_FREE 0x20 // RO, indicate USB SIE free status +#define USBFS_UIF_FIFO_OV 0x10 // FIFO overflow interrupt flag for USB, direct bit address clear or write 1 to clear +#define USBFS_UIF_HST_SOF 0x08 // host SOF timer interrupt flag for USB host, direct bit address clear or write 1 to clear +#define USBFS_UIF_SUSPEND 0x04 // USB suspend or resume event interrupt flag, direct bit address clear or write 1 to clear +#define USBFS_UIF_TRANSFER 0x02 // USB transfer completion interrupt flag, direct bit address clear or write 1 to clear +#define USBFS_UIF_DETECT 0x01 // device detected event interrupt flag for USB host mode, direct bit address clear or write 1 to clear +#define USBFS_UIF_BUS_RST 0x01 // bus reset event interrupt flag for USB device mode, direct bit address clear or write 1 to clear + +/* USB_INT_ST */ +#define USBFS_INT_ST_OFFSET 0x07 +#define USBFS_UIS_IS_SETUP 0x80 // RO, indicate current USB transfer is setup received for USB device mode +#define USBFS_UIS_IS_NAK 0x80 // RO, indicate current USB transfer is NAK received for USB device mode +#define USBFS_UIS_TOG_OK 0x40 // RO, indicate current USB transfer toggle is OK +#define USBFS_UIS_TOKEN1 0x20 // RO, current token PID code bit 1 received for USB device mode +#define USBFS_UIS_TOKEN0 0x10 // RO, current token PID code bit 0 received for USB device mode +#define USBFS_UIS_TOKEN_MASK 0x30 // RO, bit mask of current token PID code received for USB device mode +#define USBFS_UIS_TOKEN_OUT 0x00 +#define USBFS_UIS_TOKEN_SOF 0x10 +#define USBFS_UIS_TOKEN_IN 0x20 +#define USBFS_UIS_TOKEN_SETUP 0x30 +// UIS_TOKEN1 & UIS_TOKEN0: current token PID code received for USB device mode +// 00: OUT token PID received +// 01: SOF token PID received +// 10: IN token PID received +// 11: SETUP token PID received +#define USBFS_UIS_ENDP_MASK 0x0F // RO, bit mask of current transfer endpoint number for USB device mode +/* USB_RX_LEN */ +#define USBFS_RX_LEN_OFFSET 0x08 + +/******************* DEVICE ******************/ + +/* UDEV_CTRL */ +#define USBFS_UDEV_CTRL_OFFSET 0x01 +#define USBFS_UD_PD_DIS 0x80 // disable USB UDP/UDM pulldown resistance: 0=enable pulldown, 1=disable +#define USBFS_UD_DP_PIN 0x20 // ReadOnly: indicate current UDP pin level +#define USBFS_UD_DM_PIN 0x10 // ReadOnly: indicate current UDM pin level +#define USBFS_UD_LOW_SPEED 0x04 // enable USB physical port low speed: 0=full speed, 1=low speed +#define USBFS_UD_GP_BIT 0x02 // general purpose bit +#define USBFS_UD_PORT_EN 0x01 // enable USB physical port I/O: 0=disable, 1=enable + +/* UEP4_1_MOD */ +#define USBFS_UEP4_1_MOD_OFFSET 0x0C +#define USBFS_UEP1_RX_EN 0x80 // enable USB endpoint 1 receiving (OUT) +#define USBFS_UEP1_TX_EN 0x40 // enable USB endpoint 1 transmittal (IN) +#define USBFS_UEP1_BUF_MOD 0x10 // buffer mode of USB endpoint 1 +// UEPn_RX_EN & UEPn_TX_EN & UEPn_BUF_MOD: USB endpoint 1/2/3 buffer mode, buffer start address is UEPn_DMA +// 0 0 x: disable endpoint and disable buffer +// 1 0 0: 64 bytes buffer for receiving (OUT endpoint) +// 1 0 1: dual 64 bytes buffer by toggle bit bUEP_R_TOG selection for receiving (OUT endpoint), total=128bytes +// 0 1 0: 64 bytes buffer for transmittal (IN endpoint) +// 0 1 1: dual 64 bytes buffer by toggle bit bUEP_T_TOG selection for transmittal (IN endpoint), total=128bytes +// 1 1 0: 64 bytes buffer for receiving (OUT endpoint) + 64 bytes buffer for transmittal (IN endpoint), total=128bytes +// 1 1 1: dual 64 bytes buffer by bUEP_R_TOG selection for receiving (OUT endpoint) + dual 64 bytes buffer by bUEP_T_TOG selection for transmittal (IN endpoint), total=256bytes +#define USBFS_UEP4_RX_EN 0x08 // enable USB endpoint 4 receiving (OUT) +#define USBFS_UEP4_TX_EN 0x04 // enable USB endpoint 4 transmittal (IN) +// UEP4_RX_EN & UEP4_TX_EN: USB endpoint 4 buffer mode, buffer start address is UEP0_DMA +// 0 0: single 64 bytes buffer for endpoint 0 receiving & transmittal (OUT & IN endpoint) +// 1 0: single 64 bytes buffer for endpoint 0 receiving & transmittal (OUT & IN endpoint) + 64 bytes buffer for endpoint 4 receiving (OUT endpoint), total=128bytes +// 0 1: single 64 bytes buffer for endpoint 0 receiving & transmittal (OUT & IN endpoint) + 64 bytes buffer for endpoint 4 transmittal (IN endpoint), total=128bytes +// 1 1: single 64 bytes buffer for endpoint 0 receiving & transmittal (OUT & IN endpoint) +// + 64 bytes buffer for endpoint 4 receiving (OUT endpoint) + 64 bytes buffer for endpoint 4 transmittal (IN endpoint), total=192bytes + +/* UEP2_3_MOD */ +#define USBFS_UEP2_3_MOD_OFFSET 0x0D +#define USBFS_UEP3_RX_EN 0x80 // enable USB endpoint 3 receiving (OUT) +#define USBFS_UEP3_TX_EN 0x40 // enable USB endpoint 3 transmittal (IN) +#define USBFS_UEP3_BUF_MOD 0x10 // buffer mode of USB endpoint 3 +#define USBFS_UEP2_RX_EN 0x08 // enable USB endpoint 2 receiving (OUT) +#define USBFS_UEP2_TX_EN 0x04 // enable USB endpoint 2 transmittal (IN) +#define USBFS_UEP2_BUF_MOD 0x01 // buffer mode of USB endpoint 2 + +/* UEP5_6_MOD */ +#define USBFS_UEP5_6_MOD_OFFSET 0x0E +#define USBFS_UEP6_RX_EN 0x80 // enable USB endpoint 6 receiving (OUT) +#define USBFS_UEP6_TX_EN 0x40 // enable USB endpoint 6 transmittal (IN) +#define USBFS_UEP6_BUF_MOD 0x10 // buffer mode of USB endpoint 6 +#define USBFS_UEP5_RX_EN 0x08 // enable USB endpoint 5 receiving (OUT) +#define USBFS_UEP5_TX_EN 0x04 // enable USB endpoint 5 transmittal (IN) +#define USBFS_UEP5_BUF_MOD 0x01 // buffer mode of USB endpoint 5 + +/* UEP7_MOD */ +#define USBFS_UEP7_MOD_OFFSET 0x0F +#define USBFS_UEP7_RX_EN 0x08 // enable USB endpoint 7 receiving (OUT) +#define USBFS_UEP7_TX_EN 0x04 // enable USB endpoint 7 transmittal (IN) +#define USBFS_UEP7_BUF_MOD 0x01 // buffer mode of USB endpoint 7 + +/* USB_DMA */ +#define USBFS_UEPx_DMA_OFFSET(n) (0x10 + 4 * (n)) // endpoint x DMA buffer address +#define USBFS_UEP0_DMA_OFFSET 0x10 // endpoint 0 DMA buffer address +#define USBFS_UEP1_DMA_OFFSET 0x14 // endpoint 1 DMA buffer address +#define USBFS_UEP2_DMA_OFFSET 0x18 // endpoint 2 DMA buffer address +#define USBFS_UEP3_DMA_OFFSET 0x1c // endpoint 3 DMA buffer address +#define USBFS_UEP4_DMA_OFFSET 0x20 // endpoint 4 DMA buffer address +#define USBFS_UEP5_DMA_OFFSET 0x24 // endpoint 5 DMA buffer address +#define USBFS_UEP6_DMA_OFFSET 0x28 // endpoint 6 DMA buffer address +#define USBFS_UEP7_DMA_OFFSET 0x2c // endpoint 7 DMA buffer address +/* USB_EP_CTRL */ +#define USBFS_UEPx_T_LEN_OFFSET(n) (0x30 + 4 * (n)) // endpoint x DMA buffer address +#define USBFS_UEPx_TX_CTRL_OFFSET(n) (0x30 + 4 * (n) + 2) // endpoint x DMA buffer address +#define USBFS_UEPx_RX_CTRL_OFFSET(n) (0x30 + 4 * (n) + 3) // endpoint x DMA buffer address + +#define USBFS_UEP_AUTO_TOG 0x08 // enable automatic toggle after successful transfer completion on endpoint 1/2/3: 0=manual toggle, 1=automatic toggle +#define USBFS_UEP_R_TOG 0x04 // expected data toggle flag of USB endpoint X receiving (OUT): 0=DATA0, 1=DATA1 +#define USBFS_UEP_T_TOG 0x04 // prepared data toggle flag of USB endpoint X transmittal (IN): 0=DATA0, 1=DATA1 + +#define USBFS_UEP_R_RES1 0x02 // handshake response type high bit for USB endpoint X receiving (OUT) +#define USBFS_UEP_R_RES0 0x01 // handshake response type low bit for USB endpoint X receiving (OUT) +#define USBFS_UEP_R_RES_MASK 0x03 // bit mask of handshake response type for USB endpoint X receiving (OUT) +#define USBFS_UEP_R_RES_ACK 0x00 +#define USBFS_UEP_R_RES_TOUT 0x01 +#define USBFS_UEP_R_RES_NAK 0x02 +#define USBFS_UEP_R_RES_STALL 0x03 +// RB_UEP_R_RES1 & RB_UEP_R_RES0: handshake response type for USB endpoint X receiving (OUT) +// 00: ACK (ready) +// 01: no response, time out to host, for non-zero endpoint isochronous transactions +// 10: NAK (busy) +// 11: STALL (error) +#define USBFS_UEP_T_RES1 0x02 // handshake response type high bit for USB endpoint X transmittal (IN) +#define USBFS_UEP_T_RES0 0x01 // handshake response type low bit for USB endpoint X transmittal (IN) +#define USBFS_UEP_T_RES_MASK 0x03 // bit mask of handshake response type for USB endpoint X transmittal (IN) +#define USBFS_UEP_T_RES_ACK 0x00 +#define USBFS_UEP_T_RES_TOUT 0x01 +#define USBFS_UEP_T_RES_NAK 0x02 +#define USBFS_UEP_T_RES_STALL 0x03 +// bUEP_T_RES1 & bUEP_T_RES0: handshake response type for USB endpoint X transmittal (IN) +// 00: DATA0 or DATA1 then expecting ACK (ready) +// 01: DATA0 or DATA1 then expecting no response, time out from host, for non-zero endpoint isochronous transactions +// 10: NAK (busy) +// 11: TALL (error) + +/******************* HOST ******************/ + +#define USBFS_UHOST_CTRL_OFFSET 0x01 // USB host physical prot control +#define USBFS_UH_PD_DIS 0x80 // disable USB UDP/UDM pulldown resistance: 0=enable pulldown, 1=disable +#define USBFS_UH_DP_PIN 0x20 // ReadOnly: indicate current UDP pin level +#define USBFS_UH_DM_PIN 0x10 // ReadOnly: indicate current UDM pin level +#define USBFS_UH_LOW_SPEED 0x04 // enable USB port low speed: 0=full speed, 1=low speed +#define USBFS_UH_BUS_RESET 0x02 // control USB bus reset: 0=normal, 1=force bus reset +#define USBFS_UH_PORT_EN 0x01 // enable USB port: 0=disable, 1=enable port, automatic disabled if USB device detached + +#define USBFS_UH_EP_MOD_OFFSET USBFS_UEP2_3_MOD_OFFSET +#define USBFS_UH_EP_TX_EN 0x40 // enable USB host OUT endpoint transmittal +#define USBFS_UH_EP_TBUF_MOD 0x10 // buffer mode of USB host OUT endpoint +// bUH_EP_TX_EN & bUH_EP_TBUF_MOD: USB host OUT endpoint buffer mode, buffer start address is UH_TX_DMA +// 0 x: disable endpoint and disable buffer +// 1 0: 64 bytes buffer for transmittal (OUT endpoint) +// 1 1: dual 64 bytes buffer by toggle bit bUH_T_TOG selection for transmittal (OUT endpoint), total=128bytes +#define USBFS_UH_EP_RX_EN 0x08 // enable USB host IN endpoint receiving +#define USBFS_UH_EP_RBUF_MOD 0x01 // buffer mode of USB host IN endpoint +// bUH_EP_RX_EN & bUH_EP_RBUF_MOD: USB host IN endpoint buffer mode, buffer start address is UH_RX_DMA +// 0 x: disable endpoint and disable buffer +// 1 0: 64 bytes buffer for receiving (IN endpoint) +// 1 1: dual 64 bytes buffer by toggle bit bUH_R_TOG selection for receiving (IN endpoint), total=128bytes + +#define USBFS_UH_RX_DMA_OFFSET USBFS_UEPx_DMA_OFFSET(2) // host rx endpoint buffer high address +#define USBFS_UH_TX_DMA_OFFSET USBFS_UEPx_DMA_OFFSET(3) // host tx endpoint buffer high address + +#define USBFS_UH_SETUP_OFFSET USBFS_UEPx_TX_CTRL_OFFSET(1) +#define USBFS_UH_PRE_PID_EN 0x0400 // USB host PRE PID enable for low speed device via hub +#define USBFS_UH_SOF_EN 0x04 // USB host automatic SOF enable + +#define USBFS_UH_EP_PID_OFFSET USBFS_UEPx_T_LEN_OFFSET(2) +#define USBFS_UH_TOKEN_MASK 0xF0 // bit mask of token PID for USB host transfer +#define USBFS_UH_ENDP_MASK 0x0F // bit mask of endpoint number for USB host transfer + +#define USBFS_UH_RX_CTRL_OFFSET USBFS_UEPx_RX_CTRL_OFFSET(2) // host receiver endpoint control +#define USBFS_UH_R_AUTO_TOG 0x08 // enable automatic toggle after successful transfer completion: 0=manual toggle, 1=automatic toggle +#define USBFS_UH_R_TOG 0x04 // expected data toggle flag of host receiving (IN): 0=DATA0, 1=DATA1 +#define USBFS_UH_R_RES 0x01 // prepared handshake response type for host receiving (IN): 0=ACK (ready), 1=no response, time out to device, for isochronous transactions + +#define USBFS_UH_TX_LEN_OFFSET USBFS_UEPx_T_LEN_OFFSET(3) + +#define USBFS_UH_TX_CTRL_OFFSET USBFS_UEPx_TX_CTRL_OFFSET(3) // host transmittal endpoint control +#define USBFS_UH_T_AUTO_TOG 0x08 // enable automatic toggle after successful transfer completion: 0=manual toggle, 1=automatic toggle +#define USBFS_UH_T_TOG 0x04 // prepared data toggle flag of host transmittal (SETUP/OUT): 0=DATA0, 1=DATA1 +#define USBFS_UH_T_RES 0x01 // expected handshake response type for host transmittal (SETUP/OUT): 0=ACK (ready), 1=no response, time out from device, for isochronous transactions + +#endif diff --git a/kernel/cherryusb/port/ch32/ch32fs/usb_dc_usbfs.c b/kernel/cherryusb/port/ch32/ch32fs/usb_dc_usbfs.c new file mode 100644 index 0000000..8047d42 --- /dev/null +++ b/kernel/cherryusb/port/ch32/ch32fs/usb_dc_usbfs.c @@ -0,0 +1,412 @@ +/* + * Copyright (c) 2022, sakumisu + * + * SPDX-License-Identifier: Apache-2.0 + */ +#include "usbd_core.h" +#include "usb_ch32_usbfs_reg.h" + +#ifdef CONFIG_USB_HS +#error "usb fs do not support hs" +#endif + +#ifndef USB_NUM_BIDIR_ENDPOINTS +#define USB_NUM_BIDIR_ENDPOINTS 8 +#endif + +#define USB_SET_DMA(ep_idx, addr) (*(volatile uint32_t *)((uint32_t)(&USBFS_DEVICE->UEP0_DMA) + 4 * ep_idx) = addr) +#define USB_SET_TX_LEN(ep_idx, len) (*(volatile uint16_t *)((uint32_t)(&USBFS_DEVICE->UEP0_TX_LEN) + 4 * ep_idx) = len) +#define USB_GET_TX_LEN(ep_idx) (*(volatile uint16_t *)((uint32_t)(&USBFS_DEVICE->UEP0_TX_LEN) + 4 * ep_idx)) +#define USB_SET_TX_CTRL(ep_idx, val) (*(volatile uint8_t *)((uint32_t)(&USBFS_DEVICE->UEP0_TX_CTRL) + 4 * ep_idx) = val) +#define USB_GET_TX_CTRL(ep_idx) (*(volatile uint8_t *)((uint32_t)(&USBFS_DEVICE->UEP0_TX_CTRL) + 4 * ep_idx)) +#define USB_SET_RX_CTRL(ep_idx, val) (*(volatile uint8_t *)((uint32_t)(&USBFS_DEVICE->UEP0_RX_CTRL) + 4 * ep_idx) = val) +#define USB_GET_RX_CTRL(ep_idx) (*(volatile uint8_t *)((uint32_t)(&USBFS_DEVICE->UEP0_RX_CTRL) + 4 * ep_idx)) + +/* Endpoint state */ +struct ch32_usbfs_ep_state { + uint16_t ep_mps; /* Endpoint max packet size */ + uint8_t ep_type; /* Endpoint type */ + uint8_t ep_stalled; /* Endpoint stall flag */ + uint8_t ep_enable; /* Endpoint enable */ + uint8_t *xfer_buf; + uint32_t xfer_len; + uint32_t actual_xfer_len; +}; + +/* Driver state */ +struct ch32_usbfs_udc { + __attribute__((aligned(4))) struct usb_setup_packet setup; + volatile uint8_t dev_addr; + struct ch32_usbfs_ep_state in_ep[USB_NUM_BIDIR_ENDPOINTS]; /*!< IN endpoint parameters*/ + struct ch32_usbfs_ep_state out_ep[USB_NUM_BIDIR_ENDPOINTS]; /*!< OUT endpoint parameters */ + __attribute__((aligned(4))) uint8_t ep_databuf[USB_NUM_BIDIR_ENDPOINTS - 1][64 + 64]; //epx_out(64)+epx_in(64) +} g_ch32_usbfs_udc; + +volatile bool ep0_rx_data_toggle; +volatile bool ep0_tx_data_toggle; + +__WEAK void usb_dc_low_level_init(void) +{ +} + +__WEAK void usb_dc_low_level_deinit(void) +{ +} + +int usb_dc_init(uint8_t busid) +{ + usb_dc_low_level_init(); + + USBFS_DEVICE->BASE_CTRL = 0x00; + + USBFS_DEVICE->UEP4_1_MOD = USBFS_UEP4_RX_EN | USBFS_UEP4_TX_EN | USBFS_UEP1_RX_EN | USBFS_UEP1_TX_EN; + USBFS_DEVICE->UEP2_3_MOD = USBFS_UEP2_RX_EN | USBFS_UEP2_TX_EN | USBFS_UEP3_RX_EN | USBFS_UEP3_TX_EN; + USBFS_DEVICE->UEP5_6_MOD = USBFS_UEP5_RX_EN | USBFS_UEP5_TX_EN | USBFS_UEP6_RX_EN | USBFS_UEP6_TX_EN; + USBFS_DEVICE->UEP7_MOD = USBFS_UEP7_RX_EN | USBFS_UEP7_TX_EN; + + USBFS_DEVICE->UEP1_DMA = (uint32_t)g_ch32_usbfs_udc.ep_databuf[0]; + USBFS_DEVICE->UEP2_DMA = (uint32_t)g_ch32_usbfs_udc.ep_databuf[1]; + USBFS_DEVICE->UEP3_DMA = (uint32_t)g_ch32_usbfs_udc.ep_databuf[2]; + USBFS_DEVICE->UEP4_DMA = (uint32_t)g_ch32_usbfs_udc.ep_databuf[3]; + USBFS_DEVICE->UEP5_DMA = (uint32_t)g_ch32_usbfs_udc.ep_databuf[4]; + USBFS_DEVICE->UEP6_DMA = (uint32_t)g_ch32_usbfs_udc.ep_databuf[5]; + USBFS_DEVICE->UEP7_DMA = (uint32_t)g_ch32_usbfs_udc.ep_databuf[6]; + + USBFS_DEVICE->INT_FG = 0xFF; + USBFS_DEVICE->INT_EN = USBFS_UIE_SUSPEND | USBFS_UIE_BUS_RST | USBFS_UIE_TRANSFER; + USBFS_DEVICE->DEV_ADDR = 0x00; + + USBFS_DEVICE->BASE_CTRL = USBFS_UC_DEV_PU_EN | USBFS_UC_INT_BUSY | USBFS_UC_DMA_EN; + USBFS_DEVICE->UDEV_CTRL = USBFS_UD_PD_DIS | USBFS_UD_PORT_EN; + return 0; +} + +int usb_dc_deinit(uint8_t busid) +{ + return 0; +} + +int usbd_set_address(uint8_t busid, const uint8_t addr) +{ + if (addr == 0) { + USBFS_DEVICE->DEV_ADDR = (USBFS_DEVICE->DEV_ADDR & USBFS_UDA_GP_BIT) | 0; + } + g_ch32_usbfs_udc.dev_addr = addr; + return 0; +} + +int usbd_set_remote_wakeup(uint8_t busid) +{ + return -1; +} + +uint8_t usbd_get_port_speed(uint8_t busid) +{ + return USB_SPEED_FULL; +} + +int usbd_ep_open(uint8_t busid, const struct usb_endpoint_descriptor *ep) +{ + uint8_t ep_idx = USB_EP_GET_IDX(ep->bEndpointAddress); + + if (USB_EP_DIR_IS_OUT(ep->bEndpointAddress)) { + g_ch32_usbfs_udc.out_ep[ep_idx].ep_mps = USB_GET_MAXPACKETSIZE(ep->wMaxPacketSize); + g_ch32_usbfs_udc.out_ep[ep_idx].ep_type = USB_GET_ENDPOINT_TYPE(ep->bmAttributes); + g_ch32_usbfs_udc.out_ep[ep_idx].ep_enable = true; + USB_SET_RX_CTRL(ep_idx, USBFS_UEP_R_RES_NAK | USBFS_UEP_AUTO_TOG); + } else { + g_ch32_usbfs_udc.in_ep[ep_idx].ep_mps = USB_GET_MAXPACKETSIZE(ep->wMaxPacketSize); + g_ch32_usbfs_udc.in_ep[ep_idx].ep_type = USB_GET_ENDPOINT_TYPE(ep->bmAttributes); + g_ch32_usbfs_udc.in_ep[ep_idx].ep_enable = true; + USB_SET_TX_CTRL(ep_idx, USBFS_UEP_T_RES_NAK | USBFS_UEP_AUTO_TOG); + } + return 0; +} +int usbd_ep_close(uint8_t busid, const uint8_t ep) +{ + return 0; +} +int usbd_ep_set_stall(uint8_t busid, const uint8_t ep) +{ + uint8_t ep_idx = USB_EP_GET_IDX(ep); + + if (USB_EP_DIR_IS_OUT(ep)) { + if (ep_idx == 0) { + USBFS_DEVICE->UEP0_RX_CTRL = USBFS_UEP_R_TOG | USBFS_UEP_R_RES_STALL; + } else { + USB_SET_RX_CTRL(ep_idx, (USB_GET_RX_CTRL(ep_idx) & ~USBFS_UEP_R_RES_MASK) | USBFS_UEP_R_RES_STALL); + } + } else { + if (ep_idx == 0) { + USBFS_DEVICE->UEP0_TX_CTRL = USBFS_UEP_T_TOG | USBFS_UEP_T_RES_STALL; + } else { + USB_SET_TX_CTRL(ep_idx, (USB_GET_TX_CTRL(ep_idx) & ~USBFS_UEP_T_RES_MASK) | USBFS_UEP_T_RES_STALL); + } + } + + if (ep_idx == 0) { + USB_SET_DMA(ep_idx, (uint32_t)&g_ch32_usbfs_udc.setup); + USB_SET_RX_CTRL(ep_idx, USBFS_UEP_R_RES_ACK); + } + return 0; +} + +int usbd_ep_clear_stall(uint8_t busid, const uint8_t ep) +{ + uint8_t ep_idx = USB_EP_GET_IDX(ep); + + if (ep_idx == 0) { + return 0; + } + + if (USB_EP_DIR_IS_OUT(ep)) { + USB_SET_RX_CTRL(ep_idx, (USB_GET_RX_CTRL(ep_idx) & ~(USBFS_UEP_R_TOG | USBFS_UEP_R_RES_MASK)) | USBFS_UEP_R_RES_ACK); + } else { + USB_SET_TX_CTRL(ep_idx, (USB_GET_TX_CTRL(ep_idx) & ~(USBFS_UEP_T_TOG | USBFS_UEP_T_RES_MASK)) | USBFS_UEP_T_RES_NAK); + } + return 0; +} + +int usbd_ep_is_stalled(uint8_t busid, const uint8_t ep, uint8_t *stalled) +{ + return 0; +} + +int usbd_ep_start_write(uint8_t busid, const uint8_t ep, const uint8_t *data, uint32_t data_len) +{ + uint8_t ep_idx = USB_EP_GET_IDX(ep); + + if (!data && data_len) { + return -1; + } + if (!g_ch32_usbfs_udc.in_ep[ep_idx].ep_enable) { + return -2; + } + + if ((uint32_t)data & 0x03) { + printf("data do not align4\r\n"); + return -3; + } + + g_ch32_usbfs_udc.in_ep[ep_idx].xfer_buf = (uint8_t *)data; + g_ch32_usbfs_udc.in_ep[ep_idx].xfer_len = data_len; + g_ch32_usbfs_udc.in_ep[ep_idx].actual_xfer_len = 0; + + if (ep_idx == 0) { + if (data_len == 0) { + USB_SET_TX_LEN(ep_idx, 0); + } else { + data_len = MIN(data_len, g_ch32_usbfs_udc.in_ep[ep_idx].ep_mps); + USB_SET_TX_LEN(ep_idx, data_len); + USB_SET_DMA(ep_idx, (uint32_t)data); + } + if (ep0_tx_data_toggle) { + USB_SET_TX_CTRL(ep_idx, USBFS_UEP_T_TOG | USBFS_UEP_T_RES_ACK); + } else { + USB_SET_TX_CTRL(ep_idx, USBFS_UEP_T_RES_ACK); + } + + } else { + if (data_len == 0) { + USB_SET_TX_LEN(ep_idx, 0); + } else { + data_len = MIN(data_len, g_ch32_usbfs_udc.in_ep[ep_idx].ep_mps); + USB_SET_TX_LEN(ep_idx, data_len); + memcpy(&g_ch32_usbfs_udc.ep_databuf[ep_idx - 1][64], data, data_len); + } + USB_SET_TX_CTRL(ep_idx, (USB_GET_TX_CTRL(ep_idx) & ~USBFS_UEP_T_RES_MASK) | USBFS_UEP_T_RES_ACK); + } + return 0; +} + +int usbd_ep_start_read(uint8_t busid, const uint8_t ep, uint8_t *data, uint32_t data_len) +{ + uint8_t ep_idx = USB_EP_GET_IDX(ep); + + if (!data && data_len) { + return -1; + } + if (!g_ch32_usbfs_udc.out_ep[ep_idx].ep_enable) { + return -2; + } + if ((uint32_t)data & 0x03) { + printf("data do not align4\r\n"); + return -3; + } + + g_ch32_usbfs_udc.out_ep[ep_idx].xfer_buf = (uint8_t *)data; + g_ch32_usbfs_udc.out_ep[ep_idx].xfer_len = data_len; + g_ch32_usbfs_udc.out_ep[ep_idx].actual_xfer_len = 0; + + if (ep_idx == 0) { + if (data_len == 0) { + } else { + USB_SET_DMA(ep_idx, (uint32_t)data); + } + if (ep0_rx_data_toggle) { + USB_SET_RX_CTRL(ep_idx, USBFS_UEP_R_TOG | USBFS_UEP_R_RES_ACK); + } else { + USB_SET_RX_CTRL(ep_idx, USBFS_UEP_R_RES_ACK); + } + return 0; + } else { + USB_SET_RX_CTRL(ep_idx, (USB_GET_RX_CTRL(ep_idx) & ~USBFS_UEP_R_RES_MASK) | USBFS_UEP_R_RES_ACK); + } + + return 0; +} + +void USBD_IRQHandler(uint8_t busid) +{ + uint32_t ep_idx = 0, token, write_count, read_count; + uint8_t intflag = 0; + + intflag = USBFS_DEVICE->INT_FG; + + if (intflag & USBFS_UIF_TRANSFER) { + token = USBFS_DEVICE->INT_ST & USBFS_UIS_TOKEN_MASK; + ep_idx = USBFS_DEVICE->INT_ST & USBFS_UIS_ENDP_MASK; + + USBFS_DEVICE->INT_FG = USBFS_UIF_TRANSFER; + + switch (token) { + case USBFS_UIS_TOKEN_SETUP: + USB_SET_RX_CTRL(ep_idx, USBFS_UEP_R_RES_NAK); + usbd_event_ep0_setup_complete_handler(0, (uint8_t *)&g_ch32_usbfs_udc.setup); + break; + + case USBFS_UIS_TOKEN_IN: + if (ep_idx == 0x00) { + if (g_ch32_usbfs_udc.in_ep[ep_idx].xfer_len >= g_ch32_usbfs_udc.in_ep[ep_idx].ep_mps) { + g_ch32_usbfs_udc.in_ep[ep_idx].xfer_len -= g_ch32_usbfs_udc.in_ep[ep_idx].ep_mps; + g_ch32_usbfs_udc.in_ep[ep_idx].actual_xfer_len += g_ch32_usbfs_udc.in_ep[ep_idx].ep_mps; + ep0_tx_data_toggle ^= 1; + } else { + g_ch32_usbfs_udc.in_ep[ep_idx].actual_xfer_len += g_ch32_usbfs_udc.in_ep[ep_idx].xfer_len; + g_ch32_usbfs_udc.in_ep[ep_idx].xfer_len = 0; + ep0_tx_data_toggle = true; + } + + usbd_event_ep_in_complete_handler(0, ep_idx | 0x80, g_ch32_usbfs_udc.in_ep[ep_idx].actual_xfer_len); + + if (g_ch32_usbfs_udc.dev_addr > 0) { + USBFS_DEVICE->DEV_ADDR = (USBFS_DEVICE->DEV_ADDR & USBFS_UDA_GP_BIT) | g_ch32_usbfs_udc.dev_addr; + g_ch32_usbfs_udc.dev_addr = 0; + } + + if (g_ch32_usbfs_udc.setup.wLength && ((g_ch32_usbfs_udc.setup.bmRequestType & USB_REQUEST_DIR_MASK) == USB_REQUEST_DIR_OUT)) { + /* In status, start reading setup */ + USB_SET_DMA(ep_idx, (uint32_t)&g_ch32_usbfs_udc.setup); + USB_SET_RX_CTRL(ep_idx, USBFS_UEP_R_RES_ACK); + ep0_tx_data_toggle = true; + + } else if (g_ch32_usbfs_udc.setup.wLength == 0) { + /* In status, start reading setup */ + USB_SET_DMA(ep_idx, (uint32_t)&g_ch32_usbfs_udc.setup); + USB_SET_RX_CTRL(ep_idx, USBFS_UEP_R_RES_ACK); + ep0_tx_data_toggle = true; + } + } else { + USB_SET_TX_CTRL(ep_idx, (USB_GET_TX_CTRL(ep_idx) & ~USBFS_UEP_T_RES_MASK) | USBFS_UEP_T_RES_NAK); + + if (g_ch32_usbfs_udc.in_ep[ep_idx].xfer_len > g_ch32_usbfs_udc.in_ep[ep_idx].ep_mps) { + g_ch32_usbfs_udc.in_ep[ep_idx].xfer_buf += g_ch32_usbfs_udc.in_ep[ep_idx].ep_mps; + g_ch32_usbfs_udc.in_ep[ep_idx].xfer_len -= g_ch32_usbfs_udc.in_ep[ep_idx].ep_mps; + g_ch32_usbfs_udc.in_ep[ep_idx].actual_xfer_len += g_ch32_usbfs_udc.in_ep[ep_idx].ep_mps; + + write_count = MIN(g_ch32_usbfs_udc.in_ep[ep_idx].xfer_len, g_ch32_usbfs_udc.in_ep[ep_idx].ep_mps); + USB_SET_TX_LEN(ep_idx, write_count); + memcpy(&g_ch32_usbfs_udc.ep_databuf[ep_idx - 1][64], g_ch32_usbfs_udc.in_ep[ep_idx].xfer_buf, write_count); + + USB_SET_TX_CTRL(ep_idx, (USB_GET_TX_CTRL(ep_idx) & ~USBFS_UEP_T_RES_MASK) | USBFS_UEP_T_RES_ACK); + } else { + g_ch32_usbfs_udc.in_ep[ep_idx].actual_xfer_len += g_ch32_usbfs_udc.in_ep[ep_idx].xfer_len; + g_ch32_usbfs_udc.in_ep[ep_idx].xfer_len = 0; + usbd_event_ep_in_complete_handler(0, ep_idx | 0x80, g_ch32_usbfs_udc.in_ep[ep_idx].actual_xfer_len); + } + } + break; + case USBFS_UIS_TOKEN_OUT: + if (ep_idx == 0x00) { + USB_SET_RX_CTRL(ep_idx, USBFS_UEP_R_RES_NAK); + + read_count = USBFS_DEVICE->RX_LEN; + + g_ch32_usbfs_udc.out_ep[ep_idx].actual_xfer_len += read_count; + g_ch32_usbfs_udc.out_ep[ep_idx].xfer_len -= read_count; + + usbd_event_ep_out_complete_handler(0, 0x00, g_ch32_usbfs_udc.out_ep[ep_idx].actual_xfer_len); + + if (read_count == 0) { + /* Out status, start reading setup */ + USB_SET_DMA(ep_idx, (uint32_t)&g_ch32_usbfs_udc.setup); + USB_SET_RX_CTRL(ep_idx, USBFS_UEP_R_RES_ACK); + ep0_rx_data_toggle = true; + ep0_tx_data_toggle = true; + } else { + ep0_rx_data_toggle ^= 1; + } + } else { + if (USBFS_DEVICE->INT_ST & USBFS_UIS_TOG_OK) { + USB_SET_RX_CTRL(ep_idx, (USB_GET_RX_CTRL(ep_idx) & ~USBFS_UEP_R_RES_MASK) | USBFS_UEP_R_RES_NAK); + read_count = USBFS_DEVICE->RX_LEN; + + memcpy(g_ch32_usbfs_udc.out_ep[ep_idx].xfer_buf, &g_ch32_usbfs_udc.ep_databuf[ep_idx - 1][0], read_count); + + g_ch32_usbfs_udc.out_ep[ep_idx].xfer_buf += read_count; + g_ch32_usbfs_udc.out_ep[ep_idx].actual_xfer_len += read_count; + g_ch32_usbfs_udc.out_ep[ep_idx].xfer_len -= read_count; + + if ((read_count < g_ch32_usbfs_udc.out_ep[ep_idx].ep_mps) || (g_ch32_usbfs_udc.out_ep[ep_idx].xfer_len == 0)) { + usbd_event_ep_out_complete_handler(0, ep_idx, g_ch32_usbfs_udc.out_ep[ep_idx].actual_xfer_len); + } else { + USB_SET_RX_CTRL(ep_idx, (USB_GET_RX_CTRL(ep_idx) & ~USBFS_UEP_R_RES_MASK) | USBFS_UEP_R_RES_ACK); + } + } + } + break; + + case USBFS_UIS_TOKEN_SOF: + + break; + + default: + break; + } + + } else if (intflag & USBFS_UIF_BUS_RST) { + USBFS_DEVICE->INT_FG = USBFS_UIF_BUS_RST; + + USBFS_DEVICE->UEP0_TX_LEN = 0; + USBFS_DEVICE->UEP0_TX_CTRL = USBFS_UEP_T_RES_NAK; + USBFS_DEVICE->UEP0_RX_CTRL = USBFS_UEP_R_RES_NAK; + + for (uint8_t ep_idx = 1; ep_idx < USB_NUM_BIDIR_ENDPOINTS; ep_idx++) { + USB_SET_TX_LEN(ep_idx, 0); + USB_SET_TX_CTRL(ep_idx, USBFS_UEP_T_RES_NAK | USBFS_UEP_AUTO_TOG); + USB_SET_RX_CTRL(ep_idx, USBFS_UEP_R_RES_NAK | USBFS_UEP_AUTO_TOG); + } + + ep0_tx_data_toggle = true; + ep0_rx_data_toggle = true; + + memset(&g_ch32_usbfs_udc, 0, sizeof(struct ch32_usbfs_udc)); + usbd_event_reset_handler(0); + USB_SET_DMA(ep_idx, (uint32_t)&g_ch32_usbfs_udc.setup); + USB_SET_RX_CTRL(ep_idx, USBFS_UEP_R_RES_ACK); + } else if (intflag & USBFS_UIF_SUSPEND) { + if (USBFS_DEVICE->MIS_ST & USBFS_UMS_SUSPEND) { + } else { + } + USBFS_DEVICE->INT_FG = USBFS_UIF_SUSPEND; + } else { + USBFS_DEVICE->INT_FG = intflag; + } +} + +void USBFS_IRQHandler(void) __attribute__((interrupt("WCH-Interrupt-fast"))); +void USBFS_IRQHandler(void) +{ + extern void USBD_IRQHandler(uint8_t busid); + USBD_IRQHandler(0); +} \ No newline at end of file diff --git a/kernel/cherryusb/port/ch32/ch32hs/usb_ch32_usbhs_reg.h b/kernel/cherryusb/port/ch32/ch32hs/usb_ch32_usbhs_reg.h new file mode 100644 index 0000000..1dca5d1 --- /dev/null +++ b/kernel/cherryusb/port/ch32/ch32hs/usb_ch32_usbhs_reg.h @@ -0,0 +1,564 @@ +/* + * Copyright (c) 2022, sakumisu + * + * SPDX-License-Identifier: Apache-2.0 + */ +#ifndef _USB_CH32_USBHS_REG_H +#define _USB_CH32_USBHS_REG_H + +#define __IO volatile /* defines 'read / write' permissions */ + +/* USBHS Registers */ +typedef struct +{ + __IO uint8_t CONTROL; + __IO uint8_t HOST_CTRL; + __IO uint8_t INT_EN; + __IO uint8_t DEV_AD; + __IO uint16_t FRAME_NO; + __IO uint8_t SUSPEND; + __IO uint8_t RESERVED0; + __IO uint8_t SPEED_TYPE; + __IO uint8_t MIS_ST; + __IO uint8_t INT_FG; + __IO uint8_t INT_ST; + __IO uint16_t RX_LEN; + __IO uint16_t RESERVED1; + __IO uint32_t ENDP_CONFIG; + __IO uint32_t ENDP_TYPE; + __IO uint32_t BUF_MODE; + __IO uint32_t UEP0_DMA; + __IO uint32_t UEP1_RX_DMA; + __IO uint32_t UEP2_RX_DMA; + __IO uint32_t UEP3_RX_DMA; + __IO uint32_t UEP4_RX_DMA; + __IO uint32_t UEP5_RX_DMA; + __IO uint32_t UEP6_RX_DMA; + __IO uint32_t UEP7_RX_DMA; + __IO uint32_t UEP8_RX_DMA; + __IO uint32_t UEP9_RX_DMA; + __IO uint32_t UEP10_RX_DMA; + __IO uint32_t UEP11_RX_DMA; + __IO uint32_t UEP12_RX_DMA; + __IO uint32_t UEP13_RX_DMA; + __IO uint32_t UEP14_RX_DMA; + __IO uint32_t UEP15_RX_DMA; + __IO uint32_t UEP1_TX_DMA; + __IO uint32_t UEP2_TX_DMA; + __IO uint32_t UEP3_TX_DMA; + __IO uint32_t UEP4_TX_DMA; + __IO uint32_t UEP5_TX_DMA; + __IO uint32_t UEP6_TX_DMA; + __IO uint32_t UEP7_TX_DMA; + __IO uint32_t UEP8_TX_DMA; + __IO uint32_t UEP9_TX_DMA; + __IO uint32_t UEP10_TX_DMA; + __IO uint32_t UEP11_TX_DMA; + __IO uint32_t UEP12_TX_DMA; + __IO uint32_t UEP13_TX_DMA; + __IO uint32_t UEP14_TX_DMA; + __IO uint32_t UEP15_TX_DMA; + __IO uint16_t UEP0_MAX_LEN; + __IO uint16_t RESERVED2; + __IO uint16_t UEP1_MAX_LEN; + __IO uint16_t RESERVED3; + __IO uint16_t UEP2_MAX_LEN; + __IO uint16_t RESERVED4; + __IO uint16_t UEP3_MAX_LEN; + __IO uint16_t RESERVED5; + __IO uint16_t UEP4_MAX_LEN; + __IO uint16_t RESERVED6; + __IO uint16_t UEP5_MAX_LEN; + __IO uint16_t RESERVED7; + __IO uint16_t UEP6_MAX_LEN; + __IO uint16_t RESERVED8; + __IO uint16_t UEP7_MAX_LEN; + __IO uint16_t RESERVED9; + __IO uint16_t UEP8_MAX_LEN; + __IO uint16_t RESERVED10; + __IO uint16_t UEP9_MAX_LEN; + __IO uint16_t RESERVED11; + __IO uint16_t UEP10_MAX_LEN; + __IO uint16_t RESERVED12; + __IO uint16_t UEP11_MAX_LEN; + __IO uint16_t RESERVED13; + __IO uint16_t UEP12_MAX_LEN; + __IO uint16_t RESERVED14; + __IO uint16_t UEP13_MAX_LEN; + __IO uint16_t RESERVED15; + __IO uint16_t UEP14_MAX_LEN; + __IO uint16_t RESERVED16; + __IO uint16_t UEP15_MAX_LEN; + __IO uint16_t RESERVED17; + __IO uint16_t UEP0_TX_LEN; + __IO uint8_t UEP0_TX_CTRL; + __IO uint8_t UEP0_RX_CTRL; + __IO uint16_t UEP1_TX_LEN; + __IO uint8_t UEP1_TX_CTRL; + __IO uint8_t UEP1_RX_CTRL; + __IO uint16_t UEP2_TX_LEN; + __IO uint8_t UEP2_TX_CTRL; + __IO uint8_t UEP2_RX_CTRL; + __IO uint16_t UEP3_TX_LEN; + __IO uint8_t UEP3_TX_CTRL; + __IO uint8_t UEP3_RX_CTRL; + __IO uint16_t UEP4_TX_LEN; + __IO uint8_t UEP4_TX_CTRL; + __IO uint8_t UEP4_RX_CTRL; + __IO uint16_t UEP5_TX_LEN; + __IO uint8_t UEP5_TX_CTRL; + __IO uint8_t UEP5_RX_CTRL; + __IO uint16_t UEP6_TX_LEN; + __IO uint8_t UEP6_TX_CTRL; + __IO uint8_t UEP6_RX_CTRL; + __IO uint16_t UEP7_TX_LEN; + __IO uint8_t UEP7_TX_CTRL; + __IO uint8_t UEP7_RX_CTRL; + __IO uint16_t UEP8_TX_LEN; + __IO uint8_t UEP8_TX_CTRL; + __IO uint8_t UEP8_RX_CTRL; + __IO uint16_t UEP9_TX_LEN; + __IO uint8_t UEP9_TX_CTRL; + __IO uint8_t UEP9_RX_CTRL; + __IO uint16_t UEP10_TX_LEN; + __IO uint8_t UEP10_TX_CTRL; + __IO uint8_t UEP10_RX_CTRL; + __IO uint16_t UEP11_TX_LEN; + __IO uint8_t UEP11_TX_CTRL; + __IO uint8_t UEP11_RX_CTRL; + __IO uint16_t UEP12_TX_LEN; + __IO uint8_t UEP12_TX_CTRL; + __IO uint8_t UEP12_RX_CTRL; + __IO uint16_t UEP13_TX_LEN; + __IO uint8_t UEP13_TX_CTRL; + __IO uint8_t UEP13_RX_CTRL; + __IO uint16_t UEP14_TX_LEN; + __IO uint8_t UEP14_TX_CTRL; + __IO uint8_t UEP14_RX_CTRL; + __IO uint16_t UEP15_TX_LEN; + __IO uint8_t UEP15_TX_CTRL; + __IO uint8_t UEP15_RX_CTRL; +} USBHSD_TypeDef; + +typedef struct __attribute__((packed)) { + __IO uint8_t CONTROL; + __IO uint8_t HOST_CTRL; + __IO uint8_t INT_EN; + __IO uint8_t DEV_AD; + __IO uint16_t FRAME_NO; + __IO uint8_t SUSPEND; + __IO uint8_t RESERVED0; + __IO uint8_t SPEED_TYPE; + __IO uint8_t MIS_ST; + __IO uint8_t INT_FG; + __IO uint8_t INT_ST; + __IO uint16_t RX_LEN; + __IO uint16_t RESERVED1; + __IO uint32_t HOST_EP_CONFIG; + __IO uint32_t HOST_EP_TYPE; + __IO uint32_t RESERVED2; + __IO uint32_t RESERVED3; + __IO uint32_t RESERVED4; + __IO uint32_t HOST_RX_DMA; + __IO uint32_t RESERVED5; + __IO uint32_t RESERVED6; + __IO uint32_t RESERVED7; + __IO uint32_t RESERVED8; + __IO uint32_t RESERVED9; + __IO uint32_t RESERVED10; + __IO uint32_t RESERVED11; + __IO uint32_t RESERVED12; + __IO uint32_t RESERVED13; + __IO uint32_t RESERVED14; + __IO uint32_t RESERVED15; + __IO uint32_t RESERVED16; + __IO uint32_t RESERVED17; + __IO uint32_t RESERVED18; + __IO uint32_t RESERVED19; + __IO uint32_t HOST_TX_DMA; + __IO uint32_t RESERVED20; + __IO uint32_t RESERVED21; + __IO uint32_t RESERVED22; + __IO uint32_t RESERVED23; + __IO uint32_t RESERVED24; + __IO uint32_t RESERVED25; + __IO uint32_t RESERVED26; + __IO uint32_t RESERVED27; + __IO uint32_t RESERVED28; + __IO uint32_t RESERVED29; + __IO uint32_t RESERVED30; + __IO uint32_t RESERVED31; + __IO uint32_t RESERVED32; + __IO uint32_t RESERVED33; + __IO uint16_t HOST_RX_MAX_LEN; + __IO uint16_t RESERVED34; + __IO uint32_t RESERVED35; + __IO uint32_t RESERVED36; + __IO uint32_t RESERVED37; + __IO uint32_t RESERVED38; + __IO uint32_t RESERVED39; + __IO uint32_t RESERVED40; + __IO uint32_t RESERVED41; + __IO uint32_t RESERVED42; + __IO uint32_t RESERVED43; + __IO uint32_t RESERVED44; + __IO uint32_t RESERVED45; + __IO uint32_t RESERVED46; + __IO uint32_t RESERVED47; + __IO uint32_t RESERVED48; + __IO uint32_t RESERVED49; + __IO uint8_t HOST_EP_PID; + __IO uint8_t RESERVED50; + __IO uint8_t RESERVED51; + __IO uint8_t HOST_RX_CTRL; + __IO uint16_t HOST_TX_LEN; + __IO uint8_t HOST_TX_CTRL; + __IO uint8_t RESERVED52; + __IO uint16_t HOST_SPLIT_DATA; +} USBHSH_TypeDef; + +#define USBHS_BASE ((uint32_t)(0x40000000 + 0x23400)) + +#define USBHS_DEVICE ((USBHSD_TypeDef *)USBHS_BASE) +#define USBHS_HOST ((USBHSH_TypeDef *)USBHS_BASE) + +/******************* GLOBAL ******************/ + +// USB CONTROL +#define USBHS_CONTROL_OFFSET 0x00 +#define USBHS_DMA_EN (1 << 0) +#define USBHS_ALL_CLR (1 << 1) +#define USBHS_FORCE_RST (1 << 2) +#define USBHS_INT_BUSY_EN (1 << 3) +#define USBHS_DEV_PU_EN (1 << 4) +#define USBHS_SPEED_MASK (3 << 5) +#define USBHS_FULL_SPEED (0 << 5) +#define USBHS_HIGH_SPEED (1 << 5) +#define USBHS_LOW_SPEED (2 << 5) +#define USBHS_HOST_MODE (1 << 7) + +// USB_INT_EN +#define USBHS_INT_EN_OFFSET 0x02 +#define USBHS_BUS_RST_EN (1 << 0) +#define USBHS_DETECT_EN (1 << 0) +#define USBHS_TRANSFER_EN (1 << 1) +#define USBHS_SUSPEND_EN (1 << 2) +#define USBHS_SOF_ACT_EN (1 << 3) +#define USBHS_FIFO_OV_EN (1 << 4) +#define USBHS_SETUP_ACT_EN (1 << 5) +#define USBHS_ISO_ACT_EN (1 << 6) +#define USBHS_DEV_NAK_EN (1 << 7) + +// USB DEV AD +#define USBHS_DEV_AD_OFFSET 0x03 +// USB FRAME_NO +#define USBHS_FRAME_NO_OFFSET 0x04 +// USB SUSPEND +#define USBHS_SUSPEND_OFFSET 0x06 +#define USBHS_DEV_REMOTE_WAKEUP (1 << 2) +#define USBHS_LINESTATE_MASK (2 << 4) /* Read Only */ + +// RESERVED0 + +// USB SPEED TYPE +#define USBHS_SPEED_TYPE_OFFSET 0x08 +#define USBSPEED_MASK (0x03) + +// USB_MIS_ST +#define USBHS_MIS_ST_OFFSET 0x09 +#define USBHS_SPLIT_CAN (1 << 0) +#define USBHS_ATTACH (1 << 1) +#define USBHS_SUSPEND (1 << 2) +#define USBHS_BUS_RESET (1 << 3) +#define USBHS_R_FIFO_RDY (1 << 4) +#define USBHS_SIE_FREE (1 << 5) +#define USBHS_SOF_ACT (1 << 6) +#define USBHS_SOF_PRES (1 << 7) + +// INT_FLAG +#define USBHS_INT_FLAG_OFFSET 0x0A +#define USBHS_BUS_RST_FLAG (1 << 0) +#define USBHS_DETECT_FLAG (1 << 0) +#define USBHS_TRANSFER_FLAG (1 << 1) +#define USBHS_SUSPEND_FLAG (1 << 2) +#define USBHS_HST_SOF_FLAG (1 << 3) +#define USBHS_FIFO_OV_FLAG (1 << 4) +#define USBHS_SETUP_FLAG (1 << 5) +#define USBHS_ISO_ACT_FLAG (1 << 6) + +// INT_ST +#define USBHS_INT_ST_OFFSET 0x0B +#define USBHS_DEV_UIS_IS_NAK (1 << 7) +#define USBHS_DEV_UIS_TOG_OK (1 << 6) +#define MASK_UIS_TOKEN (3 << 4) +#define MASK_UIS_ENDP (0x0F) +#define MASK_UIS_H_RES (0x0F) + +#define USBHS_TOGGLE_OK (0x40) +#define USBHS_HOST_RES (0x0f) + +//USB_RX_LEN +#define USBHS_RX_LEN_OFFSET 0x0C +/******************* DEVICE ******************/ + +//UEP_CONFIG +#define USBHS_UEP_CONFIG_OFFSET 0x10 +#define USBHS_EP0_T_EN (1 << 0) +#define USBHS_EP0_R_EN (1 << 16) + +#define USBHS_EP1_T_EN (1 << 1) +#define USBHS_EP1_R_EN (1 << 17) + +#define USBHS_EP2_T_EN (1 << 2) +#define USBHS_EP2_R_EN (1 << 18) + +#define USBHS_EP3_T_EN (1 << 3) +#define USBHS_EP3_R_EN (1 << 19) + +#define USBHS_EP4_T_EN (1 << 4) +#define USBHS_EP4_R_EN (1 << 20) + +#define USBHS_EP5_T_EN (1 << 5) +#define USBHS_EP5_R_EN (1 << 21) + +#define USBHS_EP6_T_EN (1 << 6) +#define USBHS_EP6_R_EN (1 << 22) + +#define USBHS_EP7_T_EN (1 << 7) +#define USBHS_EP7_R_EN (1 << 23) + +#define USBHS_EP8_T_EN (1 << 8) +#define USBHS_EP8_R_EN (1 << 24) + +#define USBHS_EP9_T_EN (1 << 9) +#define USBHS_EP9_R_EN (1 << 25) + +#define USBHS_EP10_T_EN (1 << 10) +#define USBHS_EP10_R_EN (1 << 26) + +#define USBHS_EP11_T_EN (1 << 11) +#define USBHS_EP11_R_EN (1 << 27) + +#define USBHS_EP12_T_EN (1 << 12) +#define USBHS_EP12_R_EN (1 << 28) + +#define USBHS_EP13_T_EN (1 << 13) +#define USBHS_EP13_R_EN (1 << 29) + +#define USBHS_EP14_T_EN (1 << 14) +#define USBHS_EP14_R_EN (1 << 30) + +#define USBHS_EP15_T_EN (1 << 15) +#define USBHS_EP15_R_EN (1 << 31) + +//UEP_TYPE +#define USBHS_UEP_TYPE_OFFSET 0x14 +#define USBHS_EP0_T_TYP (1 << 0) +#define USBHS_EP0_R_TYP (1 << 16) + +#define USBHS_EP1_T_TYP (1 << 1) +#define USBHS_EP1_R_TYP (1 << 17) + +#define USBHS_EP2_T_TYP (1 << 2) +#define USBHS_EP2_R_TYP (1 << 18) + +#define USBHS_EP3_T_TYP (1 << 3) +#define USBHS_EP3_R_TYP (1 << 19) + +#define USBHS_EP4_T_TYP (1 << 4) +#define USBHS_EP4_R_TYP (1 << 20) + +#define USBHS_EP5_T_TYP (1 << 5) +#define USBHS_EP5_R_TYP (1 << 21) + +#define USBHS_EP6_T_TYP (1 << 6) +#define USBHS_EP6_R_TYP (1 << 22) + +#define USBHS_EP7_T_TYP (1 << 7) +#define USBHS_EP7_R_TYP (1 << 23) + +#define USBHS_EP8_T_TYP (1 << 8) +#define USBHS_EP8_R_TYP (1 << 24) + +#define USBHS_EP9_T_TYP (1 << 8) +#define USBHS_EP9_R_TYP (1 << 25) + +#define USBHS_EP10_T_TYP (1 << 10) +#define USBHS_EP10_R_TYP (1 << 26) + +#define USBHS_EP11_T_TYP (1 << 11) +#define USBHS_EP11_R_TYP (1 << 27) + +#define USBHS_EP12_T_TYP (1 << 12) +#define USBHS_EP12_R_TYP (1 << 28) + +#define USBHS_EP13_T_TYP (1 << 13) +#define USBHS_EP13_R_TYP (1 << 29) + +#define USBHS_EP14_T_TYP (1 << 14) +#define USBHS_EP14_R_TYP (1 << 30) + +#define USBHS_EP15_T_TYP (1 << 15) +#define USBHS_EP15_R_TYP (1 << 31) + +/* BUF_MOD UEP1~15 */ +#define USBHS_BUF_MOD_OFFSET 0x18 +#define USBHS_EP0_BUF_MOD (1 << 0) +#define USBHS_EP0_ISO_BUF_MOD (1 << 16) + +#define USBHS_EP1_BUF_MOD (1 << 1) +#define USBHS_EP1_ISO_BUF_MOD (1 << 17) + +#define USBHS_EP2_BUF_MOD (1 << 2) +#define USBHS_EP2_ISO_BUF_MOD (1 << 18) + +#define USBHS_EP3_BUF_MOD (1 << 3) +#define USBHS_EP3_ISO_BUF_MOD (1 << 19) + +#define USBHS_EP4_BUF_MOD (1 << 4) +#define USBHS_EP4_ISO_BUF_MOD (1 << 20) + +#define USBHS_EP5_BUF_MOD (1 << 5) +#define USBHS_EP5_ISO_BUF_MOD (1 << 21) + +#define USBHS_EP6_BUF_MOD (1 << 6) +#define USBHS_EP6_ISO_BUF_MOD (1 << 22) + +#define USBHS_EP7_BUF_MOD (1 << 7) +#define USBHS_EP7_ISO_BUF_MOD (1 << 23) + +#define USBHS_EP8_BUF_MOD (1 << 8) +#define USBHS_EP8_ISO_BUF_MOD (1 << 24) + +#define USBHS_EP9_BUF_MOD (1 << 9) +#define USBHS_EP9_ISO_BUF_MOD (1 << 25) + +#define USBHS_EP10_BUF_MOD (1 << 10) +#define USBHS_EP10_ISO_BUF_MOD (1 << 26) + +#define USBHS_EP11_BUF_MOD (1 << 11) +#define USBHS_EP11_ISO_BUF_MOD (1 << 27) + +#define USBHS_EP12_BUF_MOD (1 << 12) +#define USBHS_EP12_ISO_BUF_MOD (1 << 28) + +#define USBHS_EP13_BUF_MOD (1 << 13) +#define USBHS_EP13_ISO_BUF_MOD (1 << 29) + +#define USBHS_EP14_BUF_MOD (1 << 14) +#define USBHS_EP14_ISO_BUF_MOD (1 << 30) + +#define USBHS_EP15_BUF_MOD (1 << 15) +#define USBHS_EP15_ISO_BUF_MOD (1 << 31) +//USBHS_EPn_T_EN USBHS_EPn_R_EN USBHS_EPn_BUF_MOD 锟斤拷锟斤拷锟斤拷锟斤拷UEPn_DMA为锟斤拷始锟斤拷址锟缴碉拷锟斤拷锟斤拷锟斤拷锟� +// 0 0 x 锟剿点被锟斤拷锟矫ｏ拷未锟矫碉拷UEPn_*_DMA锟斤拷锟斤拷锟斤拷锟斤拷 +// 1 0 0 锟斤拷锟秸ｏ拷OUT锟斤拷锟斤拷锟斤拷锟斤拷锟阶碉拷址为UEPn_RX_DMA +// 1 0 1 bUEPn_RX_TOG[0]=0,使锟矫伙拷锟斤拷锟斤拷UEPn_RX_DMA锟斤拷bUEPn_RX_TOG[0]=1,使锟矫伙拷锟斤拷锟斤拷UEPn_TX_DMA +// 0 1 0 锟斤拷锟斤拷(IN)锟斤拷锟斤拷锟斤拷锟阶碉拷址为UEPn_TX_DMA锟斤拷 +// 0 1 1 bUEPn_TX_TOG[0]=0,使锟矫伙拷锟斤拷锟斤拷UEPn_TX_DMA锟斤拷bUEPn_TX_TOG[0]=1,使锟矫伙拷锟斤拷锟斤拷UEPn_RX_DMA + +/* USB0_DMA */ +#define USBHS_UEP0_DMA_OFFSET(n) (0x1C) // endpoint 0 DMA buffer address + +/* USBX_RX_DMA */ +#define USBHS_UEPx_RX_DMA_OFFSET(n) (0x1C + 4 * (n)) // endpoint x DMA buffer address + +#define USBHS_UEPx_TX_DMA_OFFSET(n) (0x58 + 4 * (n)) // endpoint x DMA buffer address + +#define USBHS_UEPx_MAX_LEN_OFFSET(n) (0x98 + 4 * (n)) // endpoint x DMA buffer address + +#define USBHS_UEPx_T_LEN_OFFSET(n) (0xD8 + 4 * (n)) // endpoint x DMA buffer address +#define USBHS_UEPx_TX_CTRL_OFFSET(n) (0xD8 + 4 * (n) + 2) // endpoint x DMA buffer address +#define USBHS_UEPx_RX_CTRL_OFFSET(n) (0xD8 + 4 * (n) + 3) // endpoint x DMA buffer address + +// UEPn_T_LEN +#define USBHS_EP_T_LEN_MASK (0x7FF) + +//UEPn_TX_CTRL +#define USBHS_EP_T_RES_MASK (3 << 0) +#define USBHS_EP_T_RES_ACK (0 << 0) +#define USBHS_EP_T_RES_NYET (1 << 0) +#define USBHS_EP_T_RES_NAK (2 << 0) +#define USBHS_EP_T_RES_STALL (3 << 0) + +#define USBHS_EP_T_TOG_MASK (3 << 3) +#define USBHS_EP_T_TOG_0 (0 << 3) +#define USBHS_EP_T_TOG_1 (1 << 3) +#define USBHS_EP_T_TOG_2 (2 << 3) +#define USBHS_EP_T_TOG_M (3 << 3) + +#define USBHS_EP_T_AUTOTOG (1 << 5) + +//UEPn_RX_CTRL +#define USBHS_EP_R_RES_MASK (3 << 0) +#define USBHS_EP_R_RES_ACK (0 << 0) +#define USBHS_EP_R_RES_NYET (1 << 0) +#define USBHS_EP_R_RES_NAK (2 << 0) +#define USBHS_EP_R_RES_STALL (3 << 0) + +#define USBHS_EP_R_TOG_MASK (3 << 3) +#define USBHS_EP_R_TOG_0 (0 << 3) +#define USBHS_EP_R_TOG_1 (1 << 3) +#define USBHS_EP_R_TOG_2 (2 << 3) +#define USBHS_EP_R_TOG_M (3 << 3) + +#define USBHS_EP_R_AUTOTOG (1 << 5) + +#define USBHS_TOG_MATCH (1 << 6) + +/******************* HOST ******************/ +// USB HOST_CTRL +#define USBHS_SEND_BUS_RESET (1 << 0) +#define USBHS_SEND_BUS_SUSPEND (1 << 1) +#define USBHS_SEND_BUS_RESUME (1 << 2) +#define USBHS_REMOTE_WAKE (1 << 3) +#define USBHS_PHY_SUSPENDM (1 << 4) +#define USBHS_UH_SOFT_FREE (1 << 6) +#define USBHS_SEND_SOF_EN (1 << 7) + +//UH_CONFIG +#define USBHS_HOST_TX_EN (1 << 3) +#define USBHS_HOST_RX_EN (1 << 18) + +// HOST_EP_TYPE +#define USBHS_ENDP_TX_ISO (1 << 3) +#define USBHS_ENDP_RX_ISO (1 << (16 + 2)) + +// R32_UH_EP_PID +#define USBHS_HOST_MASK_TOKEN (0x0f) +#define USBHS_HOST_MASK_ENDP (0x0f << 4) + +//R8_UH_RX_CTRL +#define USBHS_EP_R_RES_MASK (3 << 0) +#define USBHS_EP_R_RES_ACK (0 << 0) +#define USBHS_EP_R_RES_NYET (1 << 0) +#define USBHS_EP_R_RES_NAK (2 << 0) +#define USBHS_EP_R_RES_STALL (3 << 0) + +#define USBHS_UH_R_RES_NO (1 << 2) +#define USBHS_UH_R_TOG_1 (1 << 3) +#define USBHS_UH_R_TOG_2 (2 << 3) +#define USBHS_UH_R_TOG_3 (3 << 3) +#define USBHS_UH_R_TOG_AUTO (1 << 5) +#define USBHS_UH_R_DATA_NO (1 << 6) +//R8_UH_TX_CTRL +#define USBHS_UH_T_RES_MASK (3 << 0) +#define USBHS_UH_T_RES_ACK (0 << 0) +#define USBHS_UH_T_RES_NYET (1 << 0) +#define USBHS_UH_T_RES_NAK (2 << 0) +#define USBHS_UH_T_RES_STALL (3 << 0) + +#define USBHS_UH_T_RES_NO (1 << 2) +#define USBHS_UH_T_TOG_1 (1 << 3) +#define USBHS_UH_T_TOG_2 (2 << 3) +#define USBHS_UH_T_TOG_3 (3 << 3) +#define USBHS_UH_T_TOG_AUTO (1 << 5) +#define USBHS_UH_T_DATA_NO (1 << 6) + +// 00: OUT, 01:SOF, 10:IN, 11:SETUP +#define PID_OUT 0 +#define PID_SOF 1 +#define PID_IN 2 +#define PID_SETUP 3 + +#endif diff --git a/kernel/cherryusb/port/ch32/ch32hs/usb_dc_usbhs.c b/kernel/cherryusb/port/ch32/ch32hs/usb_dc_usbhs.c new file mode 100644 index 0000000..b882baf --- /dev/null +++ b/kernel/cherryusb/port/ch32/ch32hs/usb_dc_usbhs.c @@ -0,0 +1,428 @@ +/* + * Copyright (c) 2022, sakumisu + * + * SPDX-License-Identifier: Apache-2.0 + */ +#include "usbd_core.h" +#include "usb_ch32_usbhs_reg.h" + +#ifndef USB_NUM_BIDIR_ENDPOINTS +#define USB_NUM_BIDIR_ENDPOINTS 16 +#endif + +#define USB_SET_RX_DMA(ep_idx, addr) (*(volatile uint32_t *)((uint32_t)(&USBHS_DEVICE->UEP1_RX_DMA) + 4 * (ep_idx - 1)) = addr) +#define USB_SET_TX_DMA(ep_idx, addr) (*(volatile uint32_t *)((uint32_t)(&USBHS_DEVICE->UEP1_TX_DMA) + 4 * (ep_idx - 1)) = addr) +#define USB_SET_MAX_LEN(ep_idx, len) (*(volatile uint16_t *)((uint32_t)(&USBHS_DEVICE->UEP0_MAX_LEN) + 4 * ep_idx) = len) +#define USB_SET_TX_LEN(ep_idx, len) (*(volatile uint16_t *)((uint32_t)(&USBHS_DEVICE->UEP0_TX_LEN) + 4 * ep_idx) = len) +#define USB_GET_TX_LEN(ep_idx) (*(volatile uint16_t *)((uint32_t)(&USBHS_DEVICE->UEP0_TX_LEN) + 4 * ep_idx)) +#define USB_SET_TX_CTRL(ep_idx, val) (*(volatile uint8_t *)((uint32_t)(&USBHS_DEVICE->UEP0_TX_CTRL) + 4 * ep_idx) = val) +#define USB_GET_TX_CTRL(ep_idx) (*(volatile uint8_t *)((uint32_t)(&USBHS_DEVICE->UEP0_TX_CTRL) + 4 * ep_idx)) +#define USB_SET_RX_CTRL(ep_idx, val) (*(volatile uint8_t *)((uint32_t)(&USBHS_DEVICE->UEP0_RX_CTRL) + 4 * ep_idx) = val) +#define USB_GET_RX_CTRL(ep_idx) (*(volatile uint8_t *)((uint32_t)(&USBHS_DEVICE->UEP0_RX_CTRL) + 4 * ep_idx)) + +/* Endpoint state */ +struct ch32_usbhs_ep_state { + uint16_t ep_mps; /* Endpoint max packet size */ + uint8_t ep_type; /* Endpoint type */ + uint8_t ep_stalled; /* Endpoint stall flag */ + uint8_t ep_enable; /* Endpoint enable */ + uint8_t *xfer_buf; + uint32_t xfer_len; + uint32_t actual_xfer_len; +}; + +/* Driver state */ +struct ch32_usbhs_udc { + __attribute__((aligned(4))) struct usb_setup_packet setup; + volatile uint8_t dev_addr; + struct ch32_usbhs_ep_state in_ep[USB_NUM_BIDIR_ENDPOINTS]; /*!< IN endpoint parameters*/ + struct ch32_usbhs_ep_state out_ep[USB_NUM_BIDIR_ENDPOINTS]; /*!< OUT endpoint parameters */ +} g_ch32_usbhs_udc; + +volatile uint8_t mps_over_flag = 0; +volatile bool ep0_rx_data_toggle; +volatile bool ep0_tx_data_toggle; +volatile bool epx_tx_data_toggle[USB_NUM_BIDIR_ENDPOINTS - 1]; + +__WEAK void usb_dc_low_level_init(void) +{ +} + +__WEAK void usb_dc_low_level_deinit(void) +{ +} + +int usb_dc_init(uint8_t busid) +{ + usb_dc_low_level_init(); + + USBHS_DEVICE->HOST_CTRL = 0x00; + USBHS_DEVICE->HOST_CTRL = USBHS_PHY_SUSPENDM; + + USBHS_DEVICE->CONTROL = 0; +#ifdef CONFIG_USB_HS + USBHS_DEVICE->CONTROL = USBHS_DMA_EN | USBHS_INT_BUSY_EN | USBHS_HIGH_SPEED; +#else + USBHS_DEVICE->CONTROL = USBHS_DMA_EN | USBHS_INT_BUSY_EN | USBHS_FULL_SPEED; +#endif + + USBHS_DEVICE->INT_FG = 0xff; + USBHS_DEVICE->INT_EN = 0; + USBHS_DEVICE->INT_EN = USBHS_SETUP_ACT_EN | USBHS_TRANSFER_EN | USBHS_DETECT_EN; + + USBHS_DEVICE->ENDP_TYPE = 0x00; + USBHS_DEVICE->BUF_MODE = 0x00; + + USBHS_DEVICE->CONTROL |= USBHS_DEV_PU_EN; + + return 0; +} + +int usb_dc_deinit(uint8_t busid) +{ + return 0; +} + +int usbd_set_address(uint8_t busid, const uint8_t addr) +{ + if (addr == 0) { + USBHS_DEVICE->DEV_AD = addr & 0xff; + } + g_ch32_usbhs_udc.dev_addr = addr; + return 0; +} + +int usbd_set_remote_wakeup(uint8_t busid) +{ + return -1; +} + +uint8_t usbd_get_port_speed(uint8_t busid) +{ + return USB_SPEED_HIGH; +} + +int usbd_ep_open(uint8_t busid, const struct usb_endpoint_descriptor *ep) +{ + uint8_t ep_idx = USB_EP_GET_IDX(ep->bEndpointAddress); + + if (USB_EP_DIR_IS_OUT(ep->bEndpointAddress)) { + g_ch32_usbhs_udc.out_ep[ep_idx].ep_mps = USB_GET_MAXPACKETSIZE(ep->wMaxPacketSize); + g_ch32_usbhs_udc.out_ep[ep_idx].ep_type = USB_GET_ENDPOINT_TYPE(ep->bmAttributes); + g_ch32_usbhs_udc.out_ep[ep_idx].ep_enable = true; + if (g_ch32_usbhs_udc.out_ep[ep_idx].ep_type == USB_ENDPOINT_TYPE_ISOCHRONOUS) { + USBHS_DEVICE->ENDP_TYPE |= (1 << (ep_idx + 16)); + } else { + USBHS_DEVICE->ENDP_TYPE &= ~(1 << (ep_idx + 16)); + } + USBHS_DEVICE->ENDP_CONFIG |= (1 << (ep_idx + 16)); + USB_SET_RX_CTRL(ep_idx, USBHS_EP_R_RES_NAK | USBHS_EP_R_TOG_0 | USBHS_EP_R_AUTOTOG); + } else { + g_ch32_usbhs_udc.in_ep[ep_idx].ep_mps = USB_GET_MAXPACKETSIZE(ep->wMaxPacketSize); + g_ch32_usbhs_udc.in_ep[ep_idx].ep_type = USB_GET_ENDPOINT_TYPE(ep->bmAttributes); + g_ch32_usbhs_udc.in_ep[ep_idx].ep_enable = true; + if (g_ch32_usbhs_udc.in_ep[ep_idx].ep_type == USB_ENDPOINT_TYPE_ISOCHRONOUS) { + USBHS_DEVICE->ENDP_TYPE |= (1 << (ep_idx)); + USB_SET_TX_CTRL(ep_idx, USBHS_EP_T_RES_NAK | USBHS_EP_T_TOG_0); + } else { + USBHS_DEVICE->ENDP_TYPE &= ~(1 << (ep_idx)); + USB_SET_TX_CTRL(ep_idx, USBHS_EP_T_RES_NAK | USBHS_EP_T_TOG_0 | USBHS_EP_T_AUTOTOG); + } + USBHS_DEVICE->ENDP_CONFIG |= (1 << (ep_idx)); + } + USB_SET_MAX_LEN(ep_idx, USB_GET_MAXPACKETSIZE(ep->wMaxPacketSize)); + return 0; +} + +int usbd_ep_close(uint8_t busid, const uint8_t ep) +{ + uint8_t ep_idx = USB_EP_GET_IDX(ep); + if (USB_EP_DIR_IS_OUT(ep)) { + USBHS_DEVICE->ENDP_CONFIG &= ~(1 << (ep_idx + 16)); + } else { + USBHS_DEVICE->ENDP_CONFIG &= ~(1 << (ep_idx)); + } + return 0; +} + +int usbd_ep_set_stall(uint8_t busid, const uint8_t ep) +{ + uint8_t ep_idx = USB_EP_GET_IDX(ep); + + if (USB_EP_DIR_IS_OUT(ep)) { + if (ep_idx == 0) { + USBHS_DEVICE->UEP0_RX_CTRL = USBHS_EP_R_RES_STALL; + } else { + USB_SET_RX_CTRL(ep_idx, (USB_GET_RX_CTRL(ep_idx) & ~USBHS_EP_R_RES_MASK) | USBHS_EP_R_RES_STALL); + } + } else { + if (ep_idx == 0) { + USBHS_DEVICE->UEP0_TX_CTRL = USBHS_EP_T_RES_STALL; + } else { + USB_SET_TX_CTRL(ep_idx, (USB_GET_TX_CTRL(ep_idx) & ~USBHS_EP_T_RES_MASK) | USBHS_EP_T_RES_STALL); + } + } + + return 0; +} + +int usbd_ep_clear_stall(uint8_t busid, const uint8_t ep) +{ + uint8_t ep_idx = USB_EP_GET_IDX(ep); + + if (USB_EP_DIR_IS_OUT(ep)) { + USB_SET_RX_CTRL(ep_idx, USBHS_EP_R_RES_ACK | USBHS_EP_R_TOG_0); + } else { + USB_SET_TX_CTRL(ep_idx, USBHS_EP_T_RES_NAK | USBHS_EP_T_TOG_0); + } + return 0; +} + +int usbd_ep_is_stalled(uint8_t busid, const uint8_t ep, uint8_t *stalled) +{ + uint8_t ep_idx = USB_EP_GET_IDX(ep); + + if (USB_EP_DIR_IS_OUT(ep)) { + *stalled = USB_GET_RX_CTRL(ep_idx) & USBHS_EP_R_RES_STALL ? 1 : 0; + } else { + *stalled = USB_GET_TX_CTRL(ep_idx) & USBHS_EP_T_RES_STALL ? 1 : 0; + } + return 0; +} + +int usbd_ep_start_write(uint8_t busid, const uint8_t ep, const uint8_t *data, uint32_t data_len) +{ + uint8_t ep_idx = USB_EP_GET_IDX(ep); + uint32_t tmp; + + if (!data && data_len) { + return -1; + } + if (!g_ch32_usbhs_udc.in_ep[ep_idx].ep_enable) { + return -2; + } + if ((uint32_t)data & 0x03) { + return -3; + } + + g_ch32_usbhs_udc.in_ep[ep_idx].xfer_buf = (uint8_t *)data; + g_ch32_usbhs_udc.in_ep[ep_idx].xfer_len = data_len; + g_ch32_usbhs_udc.in_ep[ep_idx].actual_xfer_len = 0; + + if (ep_idx == 0) { + if (data_len == 0) { + USB_SET_TX_LEN(ep_idx, 0); + } else { + data_len = MIN(data_len, g_ch32_usbhs_udc.in_ep[ep_idx].ep_mps); + USB_SET_TX_LEN(ep_idx, data_len); + USBHS_DEVICE->UEP0_DMA = (uint32_t)data; + } + tmp = ep0_tx_data_toggle ? USBHS_EP_T_TOG_1 : USBHS_EP_T_TOG_0; + USBHS_DEVICE->UEP0_TX_CTRL = USBHS_EP_T_RES_ACK | tmp; + } else { + if (data_len == 0) { + USB_SET_TX_LEN(ep_idx, 0); + } else { + data_len = MIN(data_len, g_ch32_usbhs_udc.in_ep[ep_idx].ep_mps); + USB_SET_TX_LEN(ep_idx, data_len); + USB_SET_TX_DMA(ep_idx, (uint32_t)data); + } + tmp = USB_GET_TX_CTRL(ep_idx); + tmp &= ~(USBHS_EP_T_RES_MASK | USBHS_EP_T_TOG_MASK); + tmp |= USBHS_EP_T_RES_ACK; + if (g_ch32_usbhs_udc.in_ep[ep_idx].ep_type == USB_ENDPOINT_TYPE_ISOCHRONOUS) { + tmp |= USBHS_EP_T_TOG_0; + } else { + tmp |= (epx_tx_data_toggle[ep_idx - 1] ? USBHS_EP_T_TOG_1 : USBHS_EP_T_TOG_0); + } + USB_SET_TX_CTRL(ep_idx, tmp); + } + return 0; +} + +int usbd_ep_start_read(uint8_t busid, const uint8_t ep, uint8_t *data, uint32_t data_len) +{ + uint8_t ep_idx = USB_EP_GET_IDX(ep); + + if (!data && data_len) { + return -1; + } + if (!g_ch32_usbhs_udc.out_ep[ep_idx].ep_enable) { + return -2; + } + if ((uint32_t)data & 0x03) { + return -3; + } + + g_ch32_usbhs_udc.out_ep[ep_idx].xfer_buf = (uint8_t *)data; + g_ch32_usbhs_udc.out_ep[ep_idx].xfer_len = data_len; + g_ch32_usbhs_udc.out_ep[ep_idx].actual_xfer_len = 0; + + if (ep_idx == 0) { + if (data_len == 0) { + USBHS_DEVICE->UEP0_RX_CTRL = USBHS_EP_R_RES_ACK | USBHS_EP_R_TOG_1; + } else { + USBHS_DEVICE->UEP0_DMA = (uint32_t)data; + USBHS_DEVICE->UEP0_RX_CTRL = USBHS_EP_R_RES_ACK | (ep0_rx_data_toggle ? USBHS_EP_R_TOG_1 : USBHS_EP_R_TOG_0); + } + return 0; + } else { + USB_SET_RX_DMA(ep_idx, (uint32_t)data); + if (g_ch32_usbhs_udc.out_ep[ep_idx].ep_type == USB_ENDPOINT_TYPE_ISOCHRONOUS) { + USB_SET_RX_CTRL(ep_idx, (USB_GET_RX_CTRL(ep_idx) & ~(USBHS_EP_R_RES_MASK | USBHS_EP_R_TOG_MASK)) | USBHS_EP_R_RES_ACK | USBHS_EP_R_TOG_0); + } else { + USB_SET_RX_CTRL(ep_idx, (USB_GET_RX_CTRL(ep_idx) & ~USBHS_EP_R_RES_MASK) | USBHS_EP_R_RES_ACK); + } + } + + return 0; +} + +void USBD_IRQHandler(uint8_t busid) +{ + uint32_t ep_idx, token, write_count, read_count; + uint8_t intflag = 0; + + intflag = USBHS_DEVICE->INT_FG; + + if (intflag & USBHS_TRANSFER_FLAG) { + ep_idx = (USBHS_DEVICE->INT_ST) & MASK_UIS_ENDP; + token = (((USBHS_DEVICE->INT_ST) & MASK_UIS_TOKEN) >> 4) & 0x03; + + USBHS_DEVICE->INT_FG = USBHS_TRANSFER_FLAG; + + if (token == PID_IN) { + USB_SET_TX_CTRL(ep_idx, (USB_GET_TX_CTRL(ep_idx) & ~(USBHS_EP_T_RES_MASK | USBHS_EP_T_TOG_MASK)) | USBHS_EP_T_RES_NAK | USBHS_EP_T_TOG_0); + if (ep_idx == 0x00) { + if (g_ch32_usbhs_udc.in_ep[ep_idx].xfer_len >= g_ch32_usbhs_udc.in_ep[ep_idx].ep_mps) { + g_ch32_usbhs_udc.in_ep[ep_idx].xfer_len -= g_ch32_usbhs_udc.in_ep[ep_idx].ep_mps; + g_ch32_usbhs_udc.in_ep[ep_idx].actual_xfer_len += g_ch32_usbhs_udc.in_ep[ep_idx].ep_mps; + ep0_tx_data_toggle ^= 1; + } else { + g_ch32_usbhs_udc.in_ep[ep_idx].actual_xfer_len += g_ch32_usbhs_udc.in_ep[ep_idx].xfer_len; + g_ch32_usbhs_udc.in_ep[ep_idx].xfer_len = 0; + ep0_tx_data_toggle = true; + } + + usbd_event_ep_in_complete_handler(0, ep_idx | 0x80, g_ch32_usbhs_udc.in_ep[ep_idx].actual_xfer_len); + + if (g_ch32_usbhs_udc.dev_addr > 0) { + USBHS_DEVICE->DEV_AD = g_ch32_usbhs_udc.dev_addr & 0xff; + g_ch32_usbhs_udc.dev_addr = 0; + } + + if (g_ch32_usbhs_udc.setup.wLength && ((g_ch32_usbhs_udc.setup.bmRequestType & USB_REQUEST_DIR_MASK) == USB_REQUEST_DIR_OUT)) { + /* In status, start reading setup */ + USBHS_DEVICE->UEP0_DMA = (uint32_t)&g_ch32_usbhs_udc.setup; + USBHS_DEVICE->UEP0_RX_CTRL = USBHS_EP_R_RES_ACK; + ep0_tx_data_toggle = true; + + } else if (g_ch32_usbhs_udc.setup.wLength == 0) { + /* In status, start reading setup */ + USBHS_DEVICE->UEP0_DMA = (uint32_t)&g_ch32_usbhs_udc.setup; + USBHS_DEVICE->UEP0_RX_CTRL = USBHS_EP_R_RES_ACK; + ep0_tx_data_toggle = true; + } + } else { + if (g_ch32_usbhs_udc.in_ep[ep_idx].xfer_len > g_ch32_usbhs_udc.in_ep[ep_idx].ep_mps) { + g_ch32_usbhs_udc.in_ep[ep_idx].xfer_buf += g_ch32_usbhs_udc.in_ep[ep_idx].ep_mps; + g_ch32_usbhs_udc.in_ep[ep_idx].xfer_len -= g_ch32_usbhs_udc.in_ep[ep_idx].ep_mps; + g_ch32_usbhs_udc.in_ep[ep_idx].actual_xfer_len += g_ch32_usbhs_udc.in_ep[ep_idx].ep_mps; + epx_tx_data_toggle[ep_idx - 1] ^= 1; + + write_count = MIN(g_ch32_usbhs_udc.in_ep[ep_idx].xfer_len, g_ch32_usbhs_udc.in_ep[ep_idx].ep_mps); + USB_SET_TX_LEN(ep_idx, write_count); + USB_SET_TX_DMA(ep_idx, (uint32_t)g_ch32_usbhs_udc.in_ep[ep_idx].xfer_buf); + + uint32_t tmp = USB_GET_TX_CTRL(ep_idx); + tmp &= ~(USBHS_EP_T_RES_MASK | USBHS_EP_T_TOG_MASK); + tmp |= USBHS_EP_T_RES_ACK; + + if (g_ch32_usbhs_udc.in_ep[ep_idx].ep_type == USB_ENDPOINT_TYPE_ISOCHRONOUS) { + tmp |= USBHS_EP_T_TOG_0; + } else { + tmp |= (epx_tx_data_toggle[ep_idx - 1] ? USBHS_EP_T_TOG_1 : USBHS_EP_T_TOG_0); + } + + USB_SET_TX_CTRL(ep_idx, tmp); + } else { + g_ch32_usbhs_udc.in_ep[ep_idx].actual_xfer_len += g_ch32_usbhs_udc.in_ep[ep_idx].xfer_len; + g_ch32_usbhs_udc.in_ep[ep_idx].xfer_len = 0; + epx_tx_data_toggle[ep_idx - 1] ^= 1; + usbd_event_ep_in_complete_handler(0, ep_idx | 0x80, g_ch32_usbhs_udc.in_ep[ep_idx].actual_xfer_len); + } + } + } else if (token == PID_OUT) { + USB_SET_RX_CTRL(ep_idx, (USB_GET_RX_CTRL(ep_idx) & ~USBHS_EP_R_RES_MASK) | USBHS_EP_R_RES_NAK); + if (ep_idx == 0x00) { + read_count = USBHS_DEVICE->RX_LEN; + + g_ch32_usbhs_udc.out_ep[ep_idx].actual_xfer_len += read_count; + g_ch32_usbhs_udc.out_ep[ep_idx].xfer_len -= read_count; + + usbd_event_ep_out_complete_handler(0, 0x00, g_ch32_usbhs_udc.out_ep[ep_idx].actual_xfer_len); + + if (read_count == 0) { + /* Out status, start reading setup */ + USBHS_DEVICE->UEP0_DMA = (uint32_t)&g_ch32_usbhs_udc.setup; + USBHS_DEVICE->UEP0_RX_CTRL = USBHS_EP_R_RES_ACK; + ep0_rx_data_toggle = true; + ep0_tx_data_toggle = true; + } else { + ep0_rx_data_toggle ^= 1; + } + } else { + if (USBHS_DEVICE->INT_ST & USBHS_DEV_UIS_TOG_OK) { + read_count = USBHS_DEVICE->RX_LEN; + + g_ch32_usbhs_udc.out_ep[ep_idx].xfer_buf += read_count; + g_ch32_usbhs_udc.out_ep[ep_idx].actual_xfer_len += read_count; + g_ch32_usbhs_udc.out_ep[ep_idx].xfer_len -= read_count; + + if ((read_count < g_ch32_usbhs_udc.out_ep[ep_idx].ep_mps) || (g_ch32_usbhs_udc.out_ep[ep_idx].xfer_len == 0)) { + usbd_event_ep_out_complete_handler(0, ep_idx, g_ch32_usbhs_udc.out_ep[ep_idx].actual_xfer_len); + } else { + USB_SET_RX_DMA(ep_idx, (uint32_t)g_ch32_usbhs_udc.out_ep[ep_idx].xfer_buf); + USB_SET_RX_CTRL(ep_idx, (USB_GET_RX_CTRL(ep_idx) & ~USBHS_EP_R_RES_MASK) | USBHS_EP_R_RES_ACK); + } + } + } + } + } + + if (intflag & USBHS_SETUP_FLAG) { + USBHS_DEVICE->INT_FG = USBHS_SETUP_FLAG; + usbd_event_ep0_setup_complete_handler(0, (uint8_t *)&g_ch32_usbhs_udc.setup); + } + + if (intflag & USBHS_DETECT_FLAG) { + USBHS_DEVICE->INT_FG = USBHS_DETECT_FLAG; + + USBHS_DEVICE->ENDP_CONFIG = USBHS_EP0_T_EN | USBHS_EP0_R_EN; + + USBHS_DEVICE->UEP0_TX_LEN = 0; + USBHS_DEVICE->UEP0_TX_CTRL = USBHS_EP_T_RES_NAK; + + ep0_tx_data_toggle = true; + ep0_rx_data_toggle = true; + + for (uint8_t ep_idx = 1; ep_idx < USB_NUM_BIDIR_ENDPOINTS; ep_idx++) { + USB_SET_TX_LEN(ep_idx, 0); + USB_SET_TX_CTRL(ep_idx, USBHS_EP_T_AUTOTOG | USBHS_EP_T_RES_NAK); // autotog does not work + USB_SET_RX_CTRL(ep_idx, USBHS_EP_R_AUTOTOG | USBHS_EP_R_RES_NAK); + epx_tx_data_toggle[ep_idx - 1] = false; + } + + memset(&g_ch32_usbhs_udc, 0, sizeof(struct ch32_usbhs_udc)); + usbd_event_reset_handler(0); + USBHS_DEVICE->UEP0_DMA = (uint32_t)&g_ch32_usbhs_udc.setup; + USBHS_DEVICE->UEP0_RX_CTRL = USBHS_EP_R_RES_ACK; + } +} + +void USBHS_IRQHandler(void) __attribute__((interrupt("WCH-Interrupt-fast"))); +void USBHS_IRQHandler(void) +{ + extern void USBD_IRQHandler(uint8_t busid); + USBD_IRQHandler(0); +} diff --git a/kernel/cherryusb/port/ch32/ch58x/usb_ch585_usbhs_dc.c b/kernel/cherryusb/port/ch32/ch58x/usb_ch585_usbhs_dc.c new file mode 100644 index 0000000..2e6724c --- /dev/null +++ b/kernel/cherryusb/port/ch32/ch58x/usb_ch585_usbhs_dc.c @@ -0,0 +1,526 @@ +#include "usbd_core.h" +#include "usb_ch585_usbhs_reg.h" + +/** + * @brief Related register macro + */ +#define USB_BASE 0x40009000u +#define CH585_USBHS_DEV ((USBHSD_TypeDef *)USB_BASE) + +#define R16_PIN_CONFIG (*((PUINT16V)0x4000101A)) +#define R32_PIN_CONFIG (*((PUINT32V)0x40001018)) // RW, I/O pin configuration +#define RB_PIN_USB2_EN 0x20 + +#define USB_SET_RX_DMA(ep_idx, addr) (*(volatile uint32_t *)((uint32_t)(&CH585_USBHS_DEV->UEP1_RX_DMA) + 4 * (ep_idx - 1)) = addr) +#define USB_SET_TX_DMA(ep_idx, addr) (*(volatile uint32_t *)((uint32_t)(&CH585_USBHS_DEV->UEP1_TX_DMA) + 4 * (ep_idx - 1)) = addr) + +#define USB_SET_MAX_LEN(ep_idx, len) (*(volatile uint16_t *)((uint32_t)(&CH585_USBHS_DEV->UEP0_MAX_LEN) + 4 * ep_idx) = len) +#define USB_SET_TX_LEN(ep_idx, len) (*(volatile uint16_t *)((uint32_t)(&CH585_USBHS_DEV->UEP0_TX_LEN) + 4 * ep_idx) = len) +#define USB_GET_TX_LEN(ep_idx) (*(volatile uint16_t *)((uint32_t)(&CH585_USBHS_DEV->UEP0_TX_LEN) + 4 * ep_idx)) +#define USB_SET_TX_CTRL(ep_idx, val) (*(volatile uint8_t *)((uint32_t)(&CH585_USBHS_DEV->UEP0_TX_CTRL) + 4 * ep_idx) = val) +#define USB_GET_TX_CTRL(ep_idx) (*(volatile uint8_t *)((uint32_t)(&CH585_USBHS_DEV->UEP0_TX_CTRL) + 4 * ep_idx)) +#define USB_SET_RX_CTRL(ep_idx, val) (*(volatile uint8_t *)((uint32_t)(&CH585_USBHS_DEV->UEP0_RX_CTRL) + 4 * ep_idx) = val) +#define USB_GET_RX_CTRL(ep_idx) (*(volatile uint8_t *)((uint32_t)(&CH585_USBHS_DEV->UEP0_RX_CTRL) + 4 * ep_idx)) +#define EPn_SET_TX_NAK(ep_idx) USB_SET_TX_CTRL(ep_idx, (USB_GET_TX_CTRL(ep_idx) & ~USBHS_UEP_T_RES_MASK) | USBHS_UEP_T_RES_NAK) +#define EPn_SET_TX_VALID(ep_idx) USB_SET_TX_CTRL(ep_idx, (USB_GET_TX_CTRL(ep_idx) & ~USBHS_UEP_T_RES_MASK) | USBHS_UEP_T_RES_ACK) +#define EPn_SET_RX_NAK(ep_idx) USB_SET_RX_CTRL(ep_idx, (USB_GET_RX_CTRL(ep_idx) & ~USBHS_UEP_R_RES_MASK) | USBHS_UEP_R_RES_NAK) +#define EPn_SET_RX_VALID(ep_idx) USB_SET_RX_CTRL(ep_idx, (USB_GET_RX_CTRL(ep_idx) & ~USBHS_UEP_R_RES_MASK) | USBHS_UEP_R_RES_ACK) +#define EPn_GET_RX_LEN(ep_idx) (*(volatile uint16_t *)((uint32_t)(&CH585_USBHS_DEV->USB_EP0_RX_LEN) + 4 * ep_idx)) +#define EPn_SET_TX_LEN(ep_idx, len) (*(volatile uint16_t *)((uint32_t)(&CH585_USBHS_DEV->UEP0_TX_LEN) + 4 * ep_idx) = len) +#define EPn_CLEAR_TX_DONE(ep_idx) USB_SET_TX_CTRL(ep_idx, USB_GET_TX_CTRL(ep_idx) & ~USBHS_UEP_T_DONE) +#define EPn_CLEAR_RX_DONE(ep_idx) USB_SET_RX_CTRL(ep_idx, USB_GET_RX_CTRL(ep_idx) & ~USBHS_UEP_R_DONE) +#define EPn_SET_TX_ISO_VALID(ep_idx) +#define EPn_SET_RX_ISO_VALID(ep_idx) + +/* ep nums */ +#ifndef CONFIG_USBDEV_EP_NUM +#define CONFIG_USBDEV_EP_NUM 8 +#endif + +/** + * @brief Endpoint information structure + */ +typedef struct _usbd_ep_info { + uint8_t mps; /* Maximum packet length of endpoint */ + uint8_t eptype; /* Endpoint Type */ + uint8_t ep_enable; /* Endpoint enable */ + uint8_t *xfer_buf; + uint32_t xfer_len; + uint32_t actual_xfer_len; +} usbd_ep_info; + +/* ch58x usb */ +static struct _ch58x_core_prvi { + uint8_t address; /* Address */ + usbd_ep_info ep_in[CONFIG_USBDEV_EP_NUM]; + usbd_ep_info ep_out[CONFIG_USBDEV_EP_NUM]; + struct usb_setup_packet setup; +} usb_dc_cfg; + +__WEAK void usb_dc_low_level_init(void) +{ +} + +__WEAK void usb_dc_low_level_deinit(void) +{ +} + +/** + * @brief USB initialization + * @pre None + * @param[in] None + * @retval >=0 success otherwise failure + */ +int usb_dc_init(uint8_t busid) +{ + R8_USBHS_PLL_CTRL = USBHS_PLL_EN; + R16_PIN_CONFIG |= RB_PIN_USB2_EN; + CH585_USBHS_DEV->CONTROL = USBHS_UD_RST_LINK | USBHS_UD_PHY_SUSPENDM; + CH585_USBHS_DEV->INT_EN = USBHS_UDIE_BUS_RST | USBHS_UDIE_SUSPEND | USBHS_UDIE_BUS_SLEEP | USBHS_UDIE_LPM_ACT | USBHS_UDIE_TRANSFER | USBHS_UDIE_LINK_RDY; + /* Enable all end points */ + CH585_USBHS_DEV->UEP_TX_EN = 0xffff; + CH585_USBHS_DEV->UEP_RX_EN = 0xffff; + + CH585_USBHS_DEV->BASE_MODE = USBHS_UD_SPEED_HIGH; + CH585_USBHS_DEV->CONTROL = USBHS_UD_DEV_EN | USBHS_UD_DMA_EN | USBHS_UD_LPM_EN | USBHS_UD_PHY_SUSPENDM; + + CH585_USBHS_DEV->UEP_T_TOG_AUTO = 0xfe; + CH585_USBHS_DEV->UEP_R_TOG_AUTO = 0xfe; + usb_dc_low_level_init(); + return 0; +} + +int usb_dc_deinit(uint8_t busid) +{ + R8_USBHS_PLL_CTRL &= ~USBHS_PLL_EN; + R32_PIN_CONFIG &= ~RB_PIN_USB2_EN; + + CH585_USBHS_DEV->CONTROL |= USBHS_UD_RST_SIE; + CH585_USBHS_DEV->CONTROL &= ~USBHS_UD_RST_SIE; + usb_dc_low_level_deinit(); + return 0; +} + +/** + * @brief Set address + * @pre None + * @param[in] address ：8-bit valid address + * @retval >=0 success otherwise failure + */ +int usbd_set_address(uint8_t busid, const uint8_t address) +{ + if (address == 0) { + CH585_USBHS_DEV->DEV_AD = (CH585_USBHS_DEV->DEV_AD & 0x80) | address; + } + usb_dc_cfg.address = address; + return 0; +} + +int usbd_set_remote_wakeup(uint8_t busid) +{ + return -1; +} + +uint8_t usbd_get_port_speed(uint8_t busid) +{ + return USB_SPEED_HIGH; +} + +/** + * @brief Open endpoint + * @pre None + * @param[in] ep_cfg : Endpoint configuration structure pointer + * @retval >=0 success otherwise failure + */ +int usbd_ep_open(uint8_t busid, const struct usb_endpoint_descriptor *ep) +{ + uint8_t epid = USB_EP_GET_IDX(ep->bEndpointAddress); + if (epid > (CONFIG_USBDEV_EP_NUM - 1)) { + /** + * If you use ch58x, you can change the CONFIG_USBDEV_EP_NUM set to 8 + */ + USB_LOG_ERR("Ep addr %02x overflow\r\n", ep->bEndpointAddress); + return -1; + } + + uint8_t mps = USB_GET_MAXPACKETSIZE(ep->wMaxPacketSize); + USB_SET_MAX_LEN(epid, mps); + + if (USB_EP_DIR_IS_IN(ep->bEndpointAddress)) { + usb_dc_cfg.ep_in[epid].ep_enable = true; + usb_dc_cfg.ep_in[epid].mps = mps; + usb_dc_cfg.ep_in[epid].eptype = USB_GET_ENDPOINT_TYPE(ep->bmAttributes); + USB_SET_TX_CTRL(epid, USBHS_UEP_T_RES_NAK); + EPn_CLEAR_TX_DONE(epid); + } else if (USB_EP_DIR_IS_OUT(ep->bEndpointAddress)) { + usb_dc_cfg.ep_out[epid].ep_enable = true; + usb_dc_cfg.ep_out[epid].mps = mps; + usb_dc_cfg.ep_out[epid].eptype = USB_GET_ENDPOINT_TYPE(ep->bmAttributes); + USB_SET_RX_CTRL(epid, USBHS_UEP_R_RES_NAK); + } + + return 0; +} + +/** + * @brief Close endpoint + * @pre None + * @param[in] ep ： Endpoint address + * @retval >=0 success otherwise failure + */ +int usbd_ep_close(uint8_t busid, const uint8_t ep) +{ + uint8_t epid = USB_EP_GET_IDX(ep); + if (USB_EP_DIR_IS_IN(ep)) { + usb_dc_cfg.ep_in[epid].ep_enable = false; + } else if (USB_EP_DIR_IS_OUT(ep)) { + usb_dc_cfg.ep_out[epid].ep_enable = false; + } + return 0; +} + +/** + * @brief Endpoint setting stall + * @pre None + * @param[in] ep ： Endpoint address + * @retval >=0 success otherwise failure + */ +int usbd_ep_set_stall(uint8_t busid, const uint8_t ep) +{ + uint8_t ep_idx = USB_EP_GET_IDX(ep); + if (USB_EP_DIR_IS_OUT(ep)) { + if (ep_idx == 0) { + CH585_USBHS_DEV->UEP0_RX_CTRL = USBHS_UEP_R_RES_STALL; + } else { + USB_SET_RX_CTRL(ep_idx, (USB_GET_RX_CTRL(ep_idx) & ~USBHS_UEP_R_RES_MASK) | USBHS_UEP_R_RES_STALL); + } + } else { + if (ep_idx == 0) { + CH585_USBHS_DEV->UEP0_TX_CTRL = USBHS_UEP_T_RES_STALL; + } else { + USB_SET_TX_CTRL(ep_idx, (USB_GET_TX_CTRL(ep_idx) & ~USBHS_UEP_T_RES_MASK) | USBHS_UEP_T_RES_STALL); + } + } + return 0; +} + +/** + * @brief Endpoint clear stall + * @pre None + * @param[in] ep ： Endpoint address + * @retval >=0 success otherwise failure + */ +int usbd_ep_clear_stall(uint8_t busid, const uint8_t ep) +{ + uint8_t ep_idx = USB_EP_GET_IDX(ep); + + if (USB_EP_DIR_IS_OUT(ep)) { + USB_SET_RX_CTRL(ep_idx, USBHS_UEP_R_RES_ACK | USBHS_UEP_R_TOG_DATA0); + } else { + USB_SET_TX_CTRL(ep_idx, USBHS_UEP_T_RES_NAK | USBHS_UEP_T_TOG_DATA0); + } + return 0; +} + +/** + * @brief Check endpoint status + * @pre None + * @param[in] ep ： Endpoint address + * @param[out] stalled ： Outgoing endpoint status + * @retval >=0 success otherwise failure + */ +int usbd_ep_is_stalled(uint8_t busid, const uint8_t ep, uint8_t *stalled) +{ + if (USB_EP_DIR_IS_OUT(ep)) { + } else { + } + return 0; +} + +/** + * @brief Setup in ep transfer setting and start transfer. + * + * This function is asynchronous. + * This function is similar to uart with tx dma. + * + * This function is called to write data to the specified endpoint. The + * supplied usbd_endpoint_callback function will be called when data is transmitted + * out. + * + * @param[in] ep Endpoint address corresponding to the one + * listed in the device configuration table + * @param[in] data Pointer to data to write + * @param[in] data_len Length of the data requested to write. This may + * be zero for a zero length status packet. + * @return 0 on success, negative errno code on fail. + */ +int usbd_ep_start_write(uint8_t busid, const uint8_t ep, const uint8_t *data, uint32_t data_len) +{ + uint8_t ep_idx = USB_EP_GET_IDX(ep); + + if (!data && data_len) { + return -1; + } + if (!usb_dc_cfg.ep_in[ep_idx].ep_enable) { + return -2; + } + if ((uint32_t)data & 0x03) { + return -3; + } + + usb_dc_cfg.ep_in[ep_idx].xfer_buf = (uint8_t *)data; + usb_dc_cfg.ep_in[ep_idx].xfer_len = data_len; + usb_dc_cfg.ep_in[ep_idx].actual_xfer_len = 0; + + if (ep_idx == 0) { + if (data_len == 0) { + USB_SET_TX_LEN(ep_idx, 0); + } else { + data_len = MIN(data_len, usb_dc_cfg.ep_in[ep_idx].mps); + USB_SET_TX_LEN(ep_idx, data_len); + CH585_USBHS_DEV->UEP0_DMA = (uint32_t)data; + } + } else { + if (data_len == 0) { + USB_SET_TX_LEN(ep_idx, 0); + } else { + data_len = MIN(data_len, usb_dc_cfg.ep_in[ep_idx].mps); + USB_SET_TX_LEN(ep_idx, data_len); + USB_SET_TX_DMA(ep_idx, (uint32_t)data); + } + } + + EPn_SET_TX_VALID(ep_idx); + return 0; +} + +/** + * @brief Setup out ep transfer setting and start transfer. + * + * This function is asynchronous. + * This function is similar to uart with rx dma. + * + * This function is called to read data to the specified endpoint. The + * supplied usbd_endpoint_callback function will be called when data is received + * in. + * + * @param[in] ep Endpoint address corresponding to the one + * listed in the device configuration table + * @param[in] data Pointer to data to read + * @param[in] data_len Max length of the data requested to read. + * + * @return 0 on success, negative errno code on fail. + */ +int usbd_ep_start_read(uint8_t busid, const uint8_t ep, uint8_t *data, uint32_t data_len) +{ + uint8_t ep_idx = USB_EP_GET_IDX(ep); + + if (!data && data_len) { + return -1; + } + if (!usb_dc_cfg.ep_out[ep_idx].ep_enable) { + return -2; + } + if ((uint32_t)data & 0x03) { + return -3; + } + + usb_dc_cfg.ep_out[ep_idx].xfer_buf = (uint8_t *)data; + usb_dc_cfg.ep_out[ep_idx].xfer_len = data_len; + usb_dc_cfg.ep_out[ep_idx].actual_xfer_len = 0; + + if (ep_idx == 0) { + if (data_len == 0) { + } else { + CH585_USBHS_DEV->UEP0_DMA = (uint32_t)data; + } + } else { + USB_SET_RX_DMA(ep_idx, (uint32_t)data); + } + + EPn_SET_RX_VALID(ep_idx); + return 0; +} + +static inline void handle_ep0_in(void) +{ + switch (usb_dc_cfg.setup.bmRequestType >> USB_REQUEST_DIR_SHIFT) { + case 1: + CH585_USBHS_DEV->UEP0_TX_CTRL ^= USBHS_UEP_T_TOG_DATA1; + EPn_SET_TX_NAK(0); + if (usb_dc_cfg.ep_in[0].xfer_len > usb_dc_cfg.ep_in[0].mps) { + usb_dc_cfg.ep_in[0].xfer_len -= usb_dc_cfg.ep_in[0].mps; + usb_dc_cfg.ep_in[0].actual_xfer_len += usb_dc_cfg.ep_in[0].mps; + usbd_event_ep_in_complete_handler(0, 0 | 0x80, usb_dc_cfg.ep_in[0].actual_xfer_len); + } else { + usb_dc_cfg.ep_in[0].actual_xfer_len += usb_dc_cfg.ep_in[0].xfer_len; + usb_dc_cfg.ep_in[0].xfer_len = 0; + usbd_event_ep_in_complete_handler(0, 0 | 0x80, usb_dc_cfg.ep_in[0].actual_xfer_len); + } + break; + case 0: + /* Set */ + switch (usb_dc_cfg.setup.bRequest) { + case USB_REQUEST_SET_ADDRESS: + /* Fill in the equipment address */ + CH585_USBHS_DEV->DEV_AD = usb_dc_cfg.address; + CH585_USBHS_DEV->UEP0_DMA = (uint32_t)&usb_dc_cfg.setup; + EPn_SET_TX_NAK(0); + EPn_SET_RX_VALID(0); + break; + default: + /* Normal out state phase */ + CH585_USBHS_DEV->UEP0_DMA = (uint32_t)&usb_dc_cfg.setup; + EPn_SET_TX_NAK(0); + EPn_SET_RX_VALID(0); + break; + } + break; + } +} + +static inline void handle_non_ep0_in(uint8_t epid) +{ + EPn_SET_TX_NAK(epid); + if (usb_dc_cfg.ep_in[epid].xfer_len > usb_dc_cfg.ep_in[epid].mps) { + /* Need start in again */ + usb_dc_cfg.ep_in[epid].xfer_buf += usb_dc_cfg.ep_in[epid].mps; + usb_dc_cfg.ep_in[epid].xfer_len -= usb_dc_cfg.ep_in[epid].mps; + usb_dc_cfg.ep_in[epid].actual_xfer_len += usb_dc_cfg.ep_in[epid].mps; + + uint32_t write_count = MIN(usb_dc_cfg.ep_in[epid].xfer_len, usb_dc_cfg.ep_in[epid].mps); + USB_SET_TX_LEN(epid, write_count); + USB_SET_TX_DMA(epid, (uint32_t)usb_dc_cfg.ep_in[epid].xfer_buf); + + if (usb_dc_cfg.ep_in[epid].eptype != USB_ENDPOINT_TYPE_ISOCHRONOUS) { + EPn_SET_TX_VALID(epid); + } else { + EPn_SET_TX_ISO_VALID(epid); + } + } else { + usb_dc_cfg.ep_in[epid].actual_xfer_len += usb_dc_cfg.ep_in[epid].xfer_len; + usb_dc_cfg.ep_in[epid].xfer_len = 0; + usbd_event_ep_in_complete_handler(0, epid | 0x80, usb_dc_cfg.ep_in[epid].actual_xfer_len); + } +} + +static inline void usb_process_ep_in(uint8_t epid) +{ + if (epid == 0) { + handle_ep0_in(); + } else { + handle_non_ep0_in(epid); + } + + EPn_CLEAR_TX_DONE(epid); +} + +static inline void usb_process_ep_out(uint8_t epid) +{ + EPn_SET_RX_NAK(epid); + if (epid == 0) { + if (CH585_USBHS_DEV->UEP0_RX_CTRL & USBHS_UEP_R_SETUP_IS) { + CH585_USBHS_DEV->UEP0_RX_CTRL |= USBHS_UEP_R_TOG_DATA1; + CH585_USBHS_DEV->UEP0_TX_CTRL |= USBHS_UEP_T_TOG_DATA1; + if (usb_dc_cfg.setup.bmRequestType >> USB_REQUEST_DIR_SHIFT == 0) { + /** + * Ep0 The next in must be the status stage. + * The device must reply to the host data 0 length packet. + * Here, set the transmission length to 0 and the transmission status to ACK, + * and wait for the host to send the in token to retrieve + */ + EPn_SET_TX_LEN(0, 0); + EPn_SET_TX_VALID(0); + } + usbd_event_ep0_setup_complete_handler(0, (uint8_t *)&usb_dc_cfg.setup); + } else { + CH585_USBHS_DEV->UEP0_RX_CTRL ^= USBHS_UEP_R_TOG_DATA1; + uint32_t read_count = EPn_GET_RX_LEN(0); + usb_dc_cfg.ep_out[0].actual_xfer_len += read_count; + usb_dc_cfg.ep_out[0].xfer_len -= read_count; + usbd_event_ep_out_complete_handler(0, 0x00, usb_dc_cfg.ep_out[0].actual_xfer_len); + if (read_count == 0) { + /* Out status, start reading setup */ + CH585_USBHS_DEV->UEP0_DMA = (uint32_t)&usb_dc_cfg.setup; + EPn_SET_RX_VALID(0); + } + } + } else { + if (USB_GET_RX_CTRL(epid) & USBHS_UEP_R_TOG_MATCH) { + uint32_t read_count = EPn_GET_RX_LEN(epid); + usb_dc_cfg.ep_out[epid].xfer_buf += read_count; + usb_dc_cfg.ep_out[epid].actual_xfer_len += read_count; + usb_dc_cfg.ep_out[epid].xfer_len -= read_count; + + if ((read_count < usb_dc_cfg.ep_out[epid].mps) || (usb_dc_cfg.ep_out[epid].xfer_len == 0)) { + usbd_event_ep_out_complete_handler(0, ((epid) & 0x7f), usb_dc_cfg.ep_out[epid].actual_xfer_len); + } else { + USB_SET_RX_DMA(epid, (uint32_t)usb_dc_cfg.ep_out[epid].xfer_buf); + if (usb_dc_cfg.ep_out[epid].eptype != USB_ENDPOINT_TYPE_ISOCHRONOUS) { + EPn_SET_RX_VALID(epid); + } else { + EPn_SET_RX_ISO_VALID(epid); + } + } + } + } + + EPn_CLEAR_RX_DONE(epid); +} + +static inline void usb_trans_end_process(void) +{ + uint8_t epid = (CH585_USBHS_DEV->INT_ST & USBHS_UDIS_EP_ID_MASK); + switch (CH585_USBHS_DEV->INT_ST & USBHS_UDIS_EP_DIR) { + case USBHS_UDIS_EP_DIR: /* in */ + usb_process_ep_in(epid); + break; + case 0: /* setup or out */ + usb_process_ep_out(epid); + break; + default: + break; + } +} + +/** + * @brief USB interrupt processing function + * @pre None + * @param[in] None + * @retval None + */ +void USBD_IRQHandler(uint8_t busid) +{ + volatile uint8_t intflag = 0; + intflag = CH585_USBHS_DEV->INT_FG; + + if (intflag & USBHS_UDIF_TRANSFER) { + usb_trans_end_process(); + } else if (intflag & USBHS_UDIF_BUS_RST) { + /* Reset */ + CH585_USBHS_DEV->DEV_AD = 0; + usbd_event_reset_handler(0); + /* Set ep0 rx vaild to start receive setup packet */ + CH585_USBHS_DEV->UEP0_DMA = (uint32_t)&usb_dc_cfg.setup; + // EPn_SET_RX_VALID(0); + R8_U2EP0_TX_CTRL = USBHS_UEP_T_RES_NAK; + R8_U2EP0_RX_CTRL = USBHS_UEP_R_RES_ACK; + CH585_USBHS_DEV->INT_FG = USBHS_UDIF_BUS_RST; + } else if (intflag & USBHS_UDIF_SUSPEND) { + if (CH585_USBHS_DEV->MIS_ST & USBHS_UDMS_SUSPEND) { + /* Suspend */ + } else { + /* Wake up */ + } + CH585_USBHS_DEV->INT_FG = USBHS_UDIF_SUSPEND; + } else { + CH585_USBHS_DEV->INT_FG = intflag; + } +} + +void USB2_DEVICE_IRQHandler(void) __attribute__((interrupt("WCH-Interrupt-fast"))) __attribute__((section(".highcode"))); +void USB2_DEVICE_IRQHandler(void) +{ + extern void USBD_IRQHandler(uint8_t busid); + USBD_IRQHandler(0); +} \ No newline at end of file diff --git a/kernel/cherryusb/port/ch32/ch58x/usb_ch585_usbhs_reg.h b/kernel/cherryusb/port/ch32/ch58x/usb_ch585_usbhs_reg.h new file mode 100644 index 0000000..cfec7f7 --- /dev/null +++ b/kernel/cherryusb/port/ch32/ch58x/usb_ch585_usbhs_reg.h @@ -0,0 +1,455 @@ +/* + * Copyright (c) 2024, sakumisu + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +/**********************************/ +/*********USB high speed**********/ +/**********************************/ +typedef volatile unsigned short *PUINT16V; +typedef volatile unsigned long *PUINT32V; +typedef volatile unsigned char *PUINT8V; + +/* USB high speed device register */ +#define R8_USB2_CTRL (*((PUINT8V)0x40009000)) // RW, USB_high_speed control register +#define USBHS_UD_LPM_EN 0x80 // RW, enable LPM +#define USBHS_UD_DEV_EN 0x20 // RW, enable USB equipment +#define USBHS_UD_DMA_EN 0x10 // RW, enable DMA transmit +#define USBHS_UD_PHY_SUSPENDM 0x08 // RW, suspeng USB PHY +#define USBHS_UD_CLR_ALL 0x04 // RW, clear all interupt flag +#define USBHS_UD_RST_SIE 0x02 // RW, reset USB protocol processor,including end point register +#define USBHS_UD_RST_LINK 0x01 // RW, enable LNK layer reset +#define R8_USB2_BASE_MODE (*((PUINT8V)0x40009001)) // RW, USB_high_speed mode control register +#define USBHS_UD_SPEED_FULL 0x00 +#define USBHS_UD_SPEED_HIGH 0x01 +#define USBHS_UD_SPEED_LOW 0x02 +#define USBHS_UD_SPEED_TYPE 0x03 // RW, speed mode excpeted by the equipment,00:full speed, 01:high speed, 10:low speed +#define R8_USB2_INT_EN (*((PUINT8V)0x40009002)) // RW, USB_high_speed intreurpt enable register +#define USBHS_UDIE_FIFO_OVER 0x80 // RW, enable fifo overflow interupt +#define USBHS_UDIE_LINK_RDY 0x40 // RW, enable USB conect interupt +#define USBHS_UDIE_SOF_ACT 0x20 // RW, enable SOF package received interupt +#define USBHS_UDIE_TRANSFER 0x10 // RW, enable USB transmit end interupt +#define USBHS_UDIE_LPM_ACT 0x08 // RW, enable lpm transmit end interupt +#define USBHS_UDIE_BUS_SLEEP 0x04 // RW, enable usb bus sleep interupt +#define USBHS_UDIE_SUSPEND 0x02 // RW, enable usb bus suspend interupt +#define USBHS_UDIE_BUS_RST 0x01 // RW, enable usb bus reset interupt +#define R8_USB2_DEV_AD (*((PUINT8V)0x40009003)) // RW, USB_high_speed device adress register +#define USBHS_UD_DEV_ADDR 0x7F // RW, adress of usb equipment +#define R8_USB2_WAKE_CTRL (*((PUINT8V)0x40009004)) // RW, USB_high_speed wake up remotely register +#define USBHS_UD_UD_REMOTE_WKUP 0x01 // RW1, wake up remotely and auto reset hardware +#define R8_USB2_TEST_MODE (*((PUINT8V)0x40009005)) // RW, USB_high_speed test mode register +#define USBHS_UD_TEST_EN 0x80 // RW, enable test mode +#define USBHS_UD_TEST_SE0NAK 0x08 // RW, output SE0 when in test mode +#define USBHS_UD_TEST_PKT 0x04 // RW, output one package(including DATA0,data and length of end pont4) when in test mode,not work on virtual equipment +#define USBHS_UD_TEST_K 0x02 // RW, output K when in test mode +#define USBHS_UD_TEST_J 0x01 // RW, output J when in test mode +#define R16_USB2_LPM_DATA (*((PUINT16V)0x40009006)) // RW, USB_high_speed power control register +#define USBHS_UD_LPM_BUSY 0x8000 // RW, power control busy +#define USBHS_UD_LPM_DATA 0x07FF // RO, power control data +#define R8_USB2_INT_FG (*((PUINT8V)0x40009008)) // RW, USB_high_speed interupt flag register +#define USBHS_UDIF_FIFO_OV 0x80 // RW1, clear fifo overflow interupt flag +#define USBHS_UDIF_LINK_RDY 0x40 // RW1, clear USB conect interupt flag +#define USBHS_UDIF_RX_SOF 0x20 // RW1, clear SOF package received interupt flag +#define USBHS_UDIF_TRANSFER 0x10 // RO, USB transmit end interupt flag,cleared by USBHS_UDMS_HS_MOD +#define USBHS_UDIF_LPM_ACT 0x08 // RW1, clear lpm transmit end interupt flag +#define USBHS_UDIF_BUS_SLEEP 0x04 // RW1, clear usb bus sleep interupt flag +#define USBHS_UDIF_SUSPEND 0x02 // RW1, clear usb bus suspend interupt flag +#define USBHS_UDIF_BUS_RST 0x01 // RW1, clear usb bus reset interupt flag +#define R8_USB2_INT_ST (*((PUINT8V)0x40009009)) // RW, USB_high_speed interupt status register +#define USBHS_UDIS_EP_DIR 0x10 // RO, end point tranfer diector of data +#define USBHS_UDIS_EP_ID_MASK 0x07 // RO, number of end point which data transmission occured +#define R8_USB2_MIS_ST (*((PUINT8V)0x4000900A)) // RW, USB_high_speed miscellaneous register +#define USBHS_UDMS_HS_MOD 0x80 // RO, host with high speed +#define USBHS_UDMS_SUSP_REQ 0x10 // RO, requirment of suspending USB +#define USBHS_UDMS_SIE_FREE 0x08 // RO, USB free state +#define USBHS_UDMS_SLEEP 0x04 // RO, USB sleep state +#define USBHS_UDMS_SUSPEND 0x02 // RO, USB in suspend state +#define USBHS_UDMS_READY 0x01 // RO, USB in connected state +#define R16_USB2_FRAME_NO (*((PUINT16V)0x4000900C)) // RW, USB_high_speed frame number register +#define USBHS_UD_MFRAME_NO 0xE000 +#define USBHS_UD_FRAME_NO 0x07FF +#define R16_USB2_BUS (*((PUINT16V)0x4000900E)) // RW, USB_high_speed bus status register +#define USBHS_USB_DM_ST 0x08 +#define USBHS_USB_DP_ST 0x04 +#define USB_WAKEUP 0x01 +#define R16_U2EP_TX_EN (*((PUINT16V)0x40009010)) // RW, USB_high_speed end point transmit enable register +/* Bit definition for R16_U2EP_TX_EN & R16_U2EP_RX_EN register */ +#define RB_EP0_EN 0x0001 +#define RB_EP1_EN 0x0002 +#define RB_EP2_EN 0x0004 +#define RB_EP3_EN 0x0008 +#define RB_EP4_EN 0x0010 +#define RB_EP5_EN 0x0020 +#define RB_EP6_EN 0x0040 +#define RB_EP7_EN 0x0080 +#define RB_EP8_EN 0x0100 +#define RB_EP9_EN 0x0200 +#define RB_EP10_EN 0x0400 +#define RB_EP11_EN 0x0800 +#define RB_EP12_EN 0x1000 +#define RB_EP13_EN 0x2000 +#define RB_EP14_EN 0x4000 +#define RB_EP15_EN 0x8000 + +#define R16_U2EP_RX_EN (*((PUINT16V)0x40009012)) // RW, USB_high_speed end point receive enableregister +#define USBHS_UEP_RX_EN 0xFFFF +#define R16_U2EP_T_TOG_AUTO (*((PUINT16V)0x40009014)) // RW, USB_high_speed end point transmit auto toggle enable register +#define USBHS_UEP_T_TOG_AUTO 0xFF +#define R16_U2EP_R_TOG_AUTO (*((PUINT16V)0x40009016)) // RW, USB_high_speed end point receive auto toggle enable register +#define USBHS_UEP_R_TOG_AUTO 0xFF +#define R8_U2EP_T_BURST (*((PUINT8V)0x40009018)) // RW, USB_high_speed end point transmit burst register +#define USBHS_UEP_T_BURST_EN 0xFF +#define R8_U2EP_T_BURST_MODE (*((PUINT8V)0x40009019)) // RW, USB_high_speed end point transmit burst mode register +#define USBHS_UEP_T_BURST_MODE 0xFF +#define R8_U2EP_R_BURST (*((PUINT8V)0x4000901A)) // RW, USB_high_speed end point receive burst register +#define USBHS_UEP_R_BURST_EN 0xFF +#define R8_U2EP_R_RES_MODE (*((PUINT8V)0x4000901B)) // RW, USB_high_speed end point transmit reply mode register +#define USBHS_UEP_R_RES_MODE 0xFF +#define R32_U2EP_AF_MODE (*((PUINT32V)0x4000901C)) // RW, USB_high_speed end point multiplexing register +#define USBHS_UEP_T_AF 0xFE +#define R32_U2EP0_DMA (*((PUINT32V)0x40009020)) // RW, USB_high_speed end point0 begin adress of DMA buffer register +#define UEPn_DMA 0x01FFFF +#define R32_U2EP1_RX_DMA (*((PUINT32V)0x40009024)) // RW, USB_high_speed end point1 begin adress of DMA receive buffer register +#define R32_U2EP2_RX_DMA (*((PUINT32V)0x40009028)) // RW, USB_high_speed end point2 begin adress of DMA receive buffer register +#define R32_U2EP3_RX_DMA (*((PUINT32V)0x4000902C)) // RW, USB_high_speed end point3 begin adress of DMA receive buffer register +#define R32_U2EP4_RX_DMA (*((PUINT32V)0x40009030)) // RW, USB_high_speed end point4 begin adress of DMA receive buffer register +#define R32_U2EP5_RX_DMA (*((PUINT32V)0x40009034)) // RW, USB_high_speed end point5 begin adress of DMA receive buffer register +#define R32_U2EP6_RX_DMA (*((PUINT32V)0x40009038)) // RW, USB_high_speed end point6 begin adress of DMA receive buffer register +#define R32_U2EP7_RX_DMA (*((PUINT32V)0x4000903C)) // RW, USB_high_speed end point7 begin adress of DMA receive buffer register +#define UEPn_RX_DMA 0x01FFFF +#define R32_U2EP1_TX_DMA (*((PUINT32V)0x40009040)) // RW, USB_high_speed end point1 begin adress of DMA transmit buffer register +#define R32_U2EP2_TX_DMA (*((PUINT32V)0x40009044)) // RW, USB_high_speed end point2 begin adress of DMA transmit buffer register +#define R32_U2EP3_TX_DMA (*((PUINT32V)0x40009048)) // RW, USB_high_speed end point3 begin adress of DMA transmit buffer register +#define R32_U2EP4_TX_DMA (*((PUINT32V)0x4000904C)) // RW, USB_high_speed end point4 begin adress of DMA transmit buffer register +#define R32_U2EP5_TX_DMA (*((PUINT32V)0x40009050)) // RW, USB_high_speed end point5 begin adress of DMA transmit buffer register +#define R32_U2EP6_TX_DMA (*((PUINT32V)0x40009054)) // RW, USB_high_speed end point6 begin adress of DMA transmit buffer register +#define R32_U2EP7_TX_DMA (*((PUINT32V)0x40009058)) // RW, USB_high_speed end point7 begin adress of DMA transmit buffer register +#define UEPn_TX_DMA 0x01FFFF +#define R32_U2EP0_MAX_LEN (*((PUINT32V)0x4000905C)) // RW, USB_high_speed end point0 max length package register +#define R32_U2EP1_MAX_LEN (*((PUINT32V)0x40009060)) // RW, USB_high_speed end point1 max length package register +#define R32_U2EP2_MAX_LEN (*((PUINT32V)0x40009064)) // RW, USB_high_speed end point2 max length package register +#define R32_U2EP3_MAX_LEN (*((PUINT32V)0x40009068)) // RW, USB_high_speed end point3 max length package register +#define R32_U2EP4_MAX_LEN (*((PUINT32V)0x4000906C)) // RW, USB_high_speed end point4 max length package register +#define R32_U2EP5_MAX_LEN (*((PUINT32V)0x40009070)) // RW, USB_high_speed end point5 max length package register +#define R32_U2EP6_MAX_LEN (*((PUINT32V)0x40009074)) // RW, USB_high_speed end point6 max length package register +#define R32_U2EP7_MAX_LEN (*((PUINT32V)0x40009078)) // RW, USB_high_speed end point7 max length package register +#define UEPn_MAX_LEN 0x007F +#define R16_U2EP0_RX_LEN (*((PUINT16V)0x4000907C)) // RW, USB_high_speed end point0 length of receive register +#define UEP0_RX_LEN 0x007F +#define R16_U2EP1_RX_LEN (*((PUINT16V)0x40009080)) // RW, USB_high_speed end point1 single received length register +#define R16_U2EP1_R_SIZE (*((PUINT16V)0x40009082)) // RW, USB_high_speed end point1 total received length register +#define R16_U2EP2_RX_LEN (*((PUINT16V)0x40009084)) // RW, USB_high_speed end point2 single received length register +#define R16_U2EP2_R_SIZE (*((PUINT16V)0x40009086)) // RW, USB_high_speed end point2 total received length register +#define R16_U2EP3_RX_LEN (*((PUINT16V)0x40009088)) // RW, USB_high_speed end point3 single received length register +#define R16_U2EP3_R_SIZE (*((PUINT16V)0x4000908A)) // RW, USB_high_speed end point3 total received length register +#define R16_U2EP4_RX_LEN (*((PUINT16V)0x4000908C)) // RW, USB_high_speed end point4 single received length register +#define R16_U2EP4_R_SIZE (*((PUINT16V)0x4000908E)) // RW, USB_high_speed end point4 total received length register +#define R16_U2EP5_RX_LEN (*((PUINT16V)0x40009090)) // RW, USB_high_speed end point5 single received length register +#define R16_U2EP5_R_SIZE (*((PUINT16V)0x40009092)) // RW, USB_high_speed end point5 total received length register +#define R16_U2EP6_RX_LEN (*((PUINT16V)0x40009094)) // RW, USB_high_speed end point6 single received length register +#define R16_U2EP6_R_SIZE (*((PUINT16V)0x40009096)) // RW, USB_high_speed end point6 total received length register +#define R16_U2EP7_RX_LEN (*((PUINT16V)0x40009098)) // RW, USB_high_speed end point7 single received length register +#define R16_U2EP7_R_SIZE (*((PUINT16V)0x4000909A)) // RW, USB_high_speed end point7 total received length register +#define UEPn_RX_LEN 0xFFFF +#define UEPn_R_SIZE 0xFFFF +#define R16_U2EP0_T_LEN (*((PUINT16V)0x4000909C)) // RW, USB_high_speed end point0 length of transmission register +#define UEP0_T_LEN 0x7F +#define R8_U2EP0_TX_CTRL (*((PUINT8V)0x4000909E)) // RW, USB_high_speed end point0 transmit control register +#define R8_U2EP0_RX_CTRL (*((PUINT8V)0x4000909F)) // RW, USB_high_speed end point0 receive control register +#define R16_U2EP1_T_LEN (*((PUINT16V)0x400090A0)) // RW, USB_high_speed end point1 length of transmission register +#define R8_U2EP1_TX_CTRL (*((PUINT8V)0x400090A2)) // RW, USB_high_speed end point1 transmit control register +#define R8_U2EP1_RX_CTRL (*((PUINT8V)0x400090A3)) // RW, USB_high_speed end point1 receive control register +#define R16_U2EP2_T_LEN (*((PUINT16V)0x400090A4)) // RW, USB_high_speed end point2 length of transmission register +#define R8_U2EP2_TX_CTRL (*((PUINT8V)0x400090A6)) // RW, USB_high_speed end point2 transmit control register +#define R8_U2EP2_RX_CTRL (*((PUINT8V)0x400090A7)) // RW, USB_high_speed end point2 receive control register +#define R16_U2EP3_T_LEN (*((PUINT16V)0x400090A8)) // RW, USB_high_speed end point3 length of transmission register +#define R8_U2EP3_TX_CTRL (*((PUINT8V)0x400090AA)) // RW, USB_high_speed end point3 transmit control register +#define R8_U2EP3_RX_CTRL (*((PUINT8V)0x400090AB)) // RW, USB_high_speed end point3 receive control register +#define R16_U2EP4_T_LEN (*((PUINT16V)0x400090AC)) // RW, USB_high_speed end point4 length of transmission register +#define R8_U2EP4_TX_CTRL (*((PUINT8V)0x400090AE)) // RW, USB_high_speed end point4 transmit control register +#define R8_U2EP4_RX_CTRL (*((PUINT8V)0x400090AF)) // RW, USB_high_speed end point4 receive control register +#define R16_U2EP5_T_LEN (*((PUINT16V)0x400090B0)) // RW, USB_high_speed end point5 length of transmission register +#define R8_U2EP5_TX_CTRL (*((PUINT8V)0x400090B2)) // RW, USB_high_speed end point5 transmit control register +#define R8_U2EP5_RX_CTRL (*((PUINT8V)0x400090B3)) // RW, USB_high_speed end point5 receive control register +#define R16_U2EP6_T_LEN (*((PUINT16V)0x400090B4)) // RW, USB_high_speed end point6 length of transmission register +#define R8_U2EP6_TX_CTRL (*((PUINT8V)0x400090B6)) // RW, USB_high_speed end point6 transmit control register +#define R8_U2EP6_RX_CTRL (*((PUINT8V)0x400090B7)) // RW, USB_high_speed end point6 receive control register +#define R16_U2EP7_T_LEN (*((PUINT16V)0x400090B8)) // RW, USB_high_speed end point7 length of transmission register +#define R8_U2EP7_TX_CTRL (*((PUINT8V)0x400090BA)) // RW, USB_high_speed end point7 transmit control register +#define R8_U2EP7_RX_CTRL (*((PUINT8V)0x400090BB)) // RW, USB_high_speed end point7 receive control register +/**R16_UEPn_T_LEN**/ +#define UEPn_T_LEN 0xFFFF +/**R8_UEPn_TX_CTRL**/ +#define USBHS_UEP_T_DONE 0x80 +#define USBHS_UEP_T_NAK_ACT 0x40 +#define USBHS_UEP_T_TOG_MASK 0x0C +#define USBHS_UEP_T_TOG_MDATA 0x0C +#define USBHS_UEP_T_TOG_DATA2 0x08 +#define USBHS_UEP_T_TOG_DATA1 0x04 +#define USBHS_UEP_T_TOG_DATA0 0x00 +#define USBHS_UEP_T_RES_MASK 0x03 +#define USBHS_UEP_T_RES_ACK 0x02 +#define USBHS_UEP_T_RES_STALL 0x01 +#define USBHS_UEP_T_RES_NAK 0x00 + +/**R8_UEPn_RX_CTRL**/ +#define USBHS_UEP_R_DONE 0x80 +#define USBHS_UEP_R_NAK_ACT 0x40 +#define USBHS_UEP_R_NAK_TOG 0x20 +#define USBHS_UEP_R_TOG_MATCH 0x10 +#define USBHS_UEP_R_SETUP_IS 0x08 +#define USBHS_UEP_R_TOG_MASK 0x0C +#define USBHS_UEP_R_TOG_MDATA 0x0C +#define USBHS_UEP_R_TOG_DATA2 0x08 +#define USBHS_UEP_R_TOG_DATA1 0x04 +#define USBHS_UEP_R_TOG_DATA0 0x00 +#define USBHS_UEP_R_RES_MASK 0x03 +#define USBHS_UEP_R_RES_ACK 0x02 +#define USBHS_UEP_R_RES_STALL 0x01 +#define USBHS_UEP_R_RES_NAK 0x00 + +#define R16_U2EP_T_ISO (*((PUINT16V)0x400090BC)) // RW, USB_high_speed end point transmit sync mode register +#define USBHS_UEP1_T_ISO_EN 0x02 +#define USBHS_UEP2_T_ISO_EN 0x04 +#define USBHS_UEP3_T_ISO_EN 0x08 +#define USBHS_UEP4_T_ISO_EN 0x10 +#define USBHS_UEP5_T_ISO_EN 0x20 +#define USBHS_UEP6_T_ISO_EN 0x40 +#define USBHS_UEP7_T_ISO_EN 0x80 +#define R16_U2EP_R_ISO (*((PUINT16V)0x400090BE)) // RW, USB_high_speed end point receive sync mode register +#define USBHS_UEP1_R_ISO_EN 0x02 +#define USBHS_UEP2_R_ISO_EN 0x04 +#define USBHS_UEP3_R_ISO_EN 0x08 +#define USBHS_UEP4_R_ISO_EN 0x10 +#define USBHS_UEP5_R_ISO_EN 0x20 +#define USBHS_UEP6_R_ISO_EN 0x40 +#define USBHS_UEP7_R_ISO_EN 0x80 + +/* USB high speed host register */ +#define R8_U2H_CFG (*((PUINT8V)0x40009100)) // RW, USB_high_speed register +#define USBHS_UH_LPM_EN 0x80 +#define USBHS_UH_FORCE_FS 0x40 +#define USBHS_UH_SOF_EN 0x20 +#define USBHS_UH_DMA_EN 0x10 +#define USBHS_UH_PHY_SUSPENDM 0x08 +#define USBHS_UH_CLR_ALL 0x04 +#define USBHS_RST_SIE 0x02 +#define USBHS_RST_LINK 0x01 +#define R8_U2H_INT_EN (*((PUINT8V)0x40009102)) // RW, USB_high_speed register +#define USBHS_UHIE_FIFO_OVER 0x80 +#define USBHS_UHIE_TX_HALT 0x40 +#define USBHS_UHIE_SOF_ACT 0x20 +#define USBHS_UHIE_TRANSFER 0x10 +#define USBHS_UHIE_RESUME_ACT 0x08 +#define USBHS_UHIE_WKUP_ACT 0x04 +#define R8_U2H_DEV_AD (*((PUINT8V)0x40009103)) // RW, USB_high_speed register +#define USBHS_UH_DEV_ADDR 0xFF +#define R32_U2H_CONTROL (*((PUINT32V)0x40009104)) // RW, USB_high_speed register +#define USBHS_UH_RX_NO_RES 0x800000 +#define USBHS_UH_TX_NO_RES 0x400000 +#define USBHS_UH_RX_NO_DATA 0x200000 +#define USBHS_UH_TX_NO_DATA 0x100000 +#define USBHS_UH_PRE_PID_EN 0x080000 +#define USBHS_UH_SPLIT_VALID 0x040000 +#define USBHS_UH_LPM_VALID 0x020000 +#define USBHS_UH_HOST_ACTION 0x010000 +#define USBHS_UH_BUF_MODE 0x0400 +#define USBHS_UH_T_TOG_MASK 0x0300 +#define USBHS_UH_T_TOG_MDATA 0x0300 +#define USBHS_UH_T_TOG_DATA2 0x0200 +#define USBHS_UH_T_TOG_DATA1 0x0100 +#define USBHS_UH_T_TOG_DATA0 0x0000 +#define USBHS_UH_T_ENDP_MASK 0xF0 +#define USBHS_UH_T_TOKEN_MASK 0x0F + +#define R8_U2H_INT_FLAG (*((PUINT8V)0x40009108)) // RW, USB_high_speed register +#define USBHS_UHIF_FIFO_OVER 0x80 +#define USBHS_UHIF_TX_HALT 0x40 +#define USBHS_UHIF_SOF_ACT 0x20 +#define USBHS_UHIF_TRANSFER 0x10 +#define USBHS_UHIF_RESUME_ACT 0x08 +#define USBHS_UHIF_WKUP_ACT 0x04 +#define R8_U2H_INT_ST (*((PUINT8V)0x40009109)) // RW, USB_high_speed register +#define USBHS_UHIF_PORT_RX_RESUME 0x10 +#define USBHS_UH_R_TOKEN_MASK 0x0F +#define R8_U2H_MIS_ST (*((PUINT8V)0x4000910A)) // RW, USB_high_speed register +#define USBHS_UHMS_BUS_SE0 0x80 +#define USBHS_UHMS_BUS_J 0x40 +#define USBHS_UHMS_LINESTATE 0x30 +#define USBHS_UHMS_USB_WAKEUP 0x08 +#define USBHS_UHMS_SOF_ACT 0x04 +#define USBHS_UHMS_SOF_PRE 0x02 +#define USBHS_UHMS_SOF_FREE 0x01 +#define R32_U2H_LPM_DATA (*((PUINT32V)0x4000910C)) // RW, USB_high_speed register +#define USBHS_UH_LPM_DATA 0x07FF +#define R32_U2H_SPLIT_DATA (*((PUINT32V)0x40009110)) // RW, USB_high_speed register +#define USBHS_UH_SPLIT_DATA 0x07FFFF +#define R32_U2H_FRAME (*((PUINT32V)0x40009114)) // RW, USB_high_speed register +#define USBHS_UH_SOF_CNT_CLR 0x02000000 +#define USBHS_UH_SOF_CNT_EN 0x01000000 +#define USBHS_UH_MFRAME_NO 0x070000 +#define USBHS_UH_FRAME_NO 0x07FF +#define R32_U2H_TX_LEN (*((PUINT32V)0x40009118)) // RW, USB_high_speed register +#define USBHS_UH_TX_LEN 0x07FF +#define R32_U2H_RX_LEN (*((PUINT32V)0x4000911C)) // RW, USB_high_speed register +#define USBHS_UH_RX_LEN 0x07FF +#define R32_U2H_RX_MAX_LEN (*((PUINT32V)0x40009120)) // RW, USB_high_speed register +#define USBHS_UH_RX_MAX_LEN 0x07FF +#define R32_U2H_RX_DMA (*((PUINT32V)0x40009124)) // RW, USB_high_speed register +#define USBHS_R32_UH_RX_DMA 0x01FFFF +#define R32_U2H_TX_DMA (*((PUINT32V)0x40009128)) // RW, USB_high_speed register +#define USBHS_R32_UH_TX_DMA 0x01FFFF +#define R32_U2H_PORT_CTRL (*((PUINT32V)0x4000912C)) // RW, USB_high_speed register +#define USBHS_UH_BUS_RST_LONG 0x010000 +#define USBHS_UH_PORT_SLEEP_BESL 0xF000 +#define USBHS_UH_CLR_PORT_SLEEP 0x0100 +#define USBHS_UH_CLR_PORT_CONNECT 0x20 +#define USBHS_UH_CLR_PORT_EN 0x10 +#define USBHS_UH_SET_PORT_SLEEP 0x08 +#define USBHS_UH_CLR_PORT_SUSP 0x04 +#define USBHS_UH_SET_PORT_SUSP 0x02 +#define USBHS_UH_SET_PORT_RESET 0x01 +#define R8_U2H_PORT_CFG (*((PUINT8V)0x40009130)) // RW, USB_high_speed register +#define USBHS_UH_PD_EN 0x80 +#define USBHS_UH_HOST_EN 0x01 +#define R8_U2H_PORT_INT_EN (*((PUINT8V)0x40009132)) // RW, USB_high_speed register +#define USBHS_UHIE_PORT_SLP 0x20 +#define USBHS_UHIE_PORT_RESET 0x10 +#define USBHS_UHIE_PORT_SUSP 0x04 +#define USBHS_UHIE_PORT_EN 0x02 +#define USBHS_UHIE_PORT_CONNECT 0x01 +#define R8_U2H_PORT_TEST_CT (*((PUINT8V)0x40009133)) // RW, USB_high_speed register +#define USBHS_UH_TEST_FORCE_EN 0x04 +#define USBHS_UH_TEST_K 0x02 +#define USBHS_UH_TEST_J 0x01 +#define R16_U2H_PORT_ST (*((PUINT16V)0x40009134)) // RW, USB_high_speed register +#define USBHS_UHIS_PORT_TEST 0x0800 +#define USBHS_UHIS_PORT_SPEED_MASK 0x0600 +#define USBHS_UHIS_PORT_HS 0x0400 +#define USBHS_UHIS_PORT_LS 0x0200 +#define USBHS_UHIS_PORT_FS 0x0000 +#define USBHS_UHIS_PORT_SLP 0x20 +#define USBHS_UHIS_PORT_RST 0x10 +#define USBHS_UHIS_PORT_SUSP 0x04 +#define USBHS_UHIS_PORT_EN 0x02 +#define USBHS_UHIS_PORT_CONNECT 0x01 +#define R8_U2H_PORT_CHG (*((PUINT8V)0x40009136)) +#define USBHS_UHIF_PORT_SLP 0x20 +#define USBHS_UHIF_PORT_RESET 0x10 +#define USBHS_UHIF_PORT_SUSP 0x04 +#define USBHS_UHIF_PORT_EN 0x02 +#define USBHS_UHIF_PORT_CONNECT 0x01 +#define R32_U2H_BC_CTRL (*((PUINT32V)0x4000913C)) +#define UDM_VSRC_ACT 0x0400 +#define UDM_BC_VSRC 0x0200 +#define UDP_BC_VSRC 0x0100 +#define BC_AUTO_MODE 0x40 +#define UDM_BC_CMPE 0x20 +#define UDP_BC_CMPE 0x10 +#define UDM_BC_CMPO 0x02 +#define UDP_BC_CMPO 0x01 +#define R8_USBHS_PLL_CTRL (*((PUINT8V)0x40009200)) +#define USBHS_PLL_EN 0x04 +#define USBHS_PLL_LOWPOW 0x02 +#define USBHS_PLL_CKSEL 0x01 + +#define __IO volatile /* defines 'read / write' permissions */ + +typedef struct +{ + __IO uint8_t CONTROL; /* 0x40009000 */ + __IO uint8_t BASE_MODE; /* 0x40009001 */ + __IO uint8_t INT_EN; /* 0x40009002 */ + __IO uint8_t DEV_AD; /* 0x40009003 */ + __IO uint8_t WAKE_CTRL; /* 0x40009004 远程唤醒寄存器 */ + __IO uint8_t TEST_MODE; /* 0x40009005 测试模式寄存器 */ + __IO uint16_t LPM_DATA; /* 0x40009006 */ + __IO uint8_t INT_FG; /* 0x40009008 */ + __IO uint8_t INT_ST; /* 0x40009009 */ + __IO uint8_t MIS_ST; /* 0x4000900a */ + __IO uint8_t RESERVE0; /* 0x4000900b */ + __IO uint16_t FRAME_NO; /* 0x4000900c */ + __IO uint16_t USB_BUS; /* 0x4000900e */ + __IO uint16_t UEP_TX_EN; /* 0x40009010 */ + __IO uint16_t UEP_RX_EN; /* 0x40009012 */ + + __IO uint16_t UEP_T_TOG_AUTO; /* 0x40009014 */ + __IO uint16_t UEP_R_TOG_AUTO; /* 0x40009016 */ + __IO uint8_t UEP_T_BURST; /* 0x40009018 */ + __IO uint8_t UEP_T_BURST_MODE; /* 0x40009019 */ + __IO uint8_t UEP_R_BURST; /* 0x4000901a */ + __IO uint8_t UEP_R_RES_MODE; /* 0x4000901b */ + __IO uint32_t UEP_AF_MODE; /* 0x4000901c */ + + __IO uint32_t UEP0_DMA; /* 0x40009020 */ + __IO uint32_t UEP1_RX_DMA; /* 0x40009024 */ + __IO uint32_t UEP2_RX_DMA; /* 0x40009028 */ + __IO uint32_t UEP3_RX_DMA; /* 0x4000902c */ + __IO uint32_t UEP4_RX_DMA; /* 0x40009030 */ + __IO uint32_t UEP5_RX_DMA; /* 0x40009034 */ + __IO uint32_t UEP6_RX_DMA; /* 0x40009038 */ + __IO uint32_t UEP7_RX_DMA; /* 0x4000903c */ + + __IO uint32_t UEP1_TX_DMA; /* 0x40009040 */ + __IO uint32_t UEP2_TX_DMA; /* 0x40009044 */ + __IO uint32_t UEP3_TX_DMA; /* 0x40009048 */ + __IO uint32_t UEP4_TX_DMA; /* 0x4000904c */ + __IO uint32_t UEP5_TX_DMA; /* 0x40009050 */ + __IO uint32_t UEP6_TX_DMA; /* 0x40009054 */ + __IO uint32_t UEP7_TX_DMA; /* 0x40009058 */ + + __IO uint32_t UEP0_MAX_LEN; /* 0x4000905c */ + __IO uint32_t UEP1_MAX_LEN; /* 0x40009060 */ + __IO uint32_t UEP2_MAX_LEN; /* 0x40009064 */ + __IO uint32_t UEP3_MAX_LEN; /* 0x40009068 */ + __IO uint32_t UEP4_MAX_LEN; /* 0x4000906c */ + __IO uint32_t UEP5_MAX_LEN; /* 0x40009070 */ + __IO uint32_t UEP6_MAX_LEN; /* 0x40009074 */ + __IO uint32_t UEP7_MAX_LEN; /* 0x40009078 */ + + __IO uint16_t USB_EP0_RX_LEN; /* 0x4000907c */ + __IO uint16_t RESERVE1; /* 0x4000907e */ + __IO uint16_t UEP1_RX_LEN; /* 0x40009080 */ + __IO uint16_t UEP1_R_SIZE; /* 0x40009082 */ + __IO uint16_t UEP2_RX_LEN; /* 0x40009084 */ + __IO uint16_t UEP2_R_SIZE; /* 0x40009086 */ + __IO uint16_t UEP3_RX_LEN; /* 0x40009088 */ + __IO uint16_t UEP3_R_SIZE; /* 0x4000908a */ + __IO uint16_t UEP4_RX_LEN; /* 0x4000908c */ + __IO uint16_t UEP4_R_SIZE; /* 0x4000908e */ + __IO uint16_t UEP5_RX_LEN; /* 0x40009090 */ + __IO uint16_t UEP5_R_SIZE; /* 0x40009092 */ + __IO uint16_t UEP6_RX_LEN; /* 0x40009094 */ + __IO uint16_t UEP6_R_SIZE; /* 0x40009096 */ + __IO uint16_t UEP7_RX_LEN; /* 0x40009098 */ + __IO uint16_t UEP7_R_SIZE; /* 0x4000909a */ + + __IO uint16_t UEP0_TX_LEN; /* 0x4000909c */ + __IO uint8_t UEP0_TX_CTRL; /* 0x4000909e */ + __IO uint8_t UEP0_RX_CTRL; /* 0x4000909f */ + __IO uint16_t UEP1_TX_LEN; /* 0x400090a0 */ + __IO uint8_t UEP1_TX_CTRL; /* 0x400090a2 */ + __IO uint8_t UEP1_RX_CTRL; /* 0x400090a3 */ + __IO uint16_t UEP2_TX_LEN; /* 0x400090a4 */ + __IO uint8_t UEP2_TX_CTRL; /* 0x400090a6 */ + __IO uint8_t UEP2_RX_CTRL; /* 0x400090a7 */ + __IO uint16_t UEP3_TX_LEN; /* 0x400090a8 */ + __IO uint8_t UEP3_TX_CTRL; /* 0x400090aa */ + __IO uint8_t UEP3_RX_CTRL; /* 0x400090ab */ + __IO uint16_t UEP4_TX_LEN; /* 0x400090ac */ + __IO uint8_t UEP4_TX_CTRL; /* 0x400090ae */ + __IO uint8_t UEP4_RX_CTRL; /* 0x400090af */ + __IO uint16_t UEP5_TX_LEN; /* 0x400090b0 */ + __IO uint8_t UEP5_TX_CTRL; /* 0x400090b2 */ + __IO uint8_t UEP5_RX_CTRL; /* 0x400090b3 */ + __IO uint16_t UEP6_TX_LEN; /* 0x400090b4 */ + __IO uint8_t UEP6_TX_CTRL; /* 0x400090b6 */ + __IO uint8_t UEP6_RX_CTRL; /* 0x400090b7 */ + __IO uint16_t UEP7_TX_LEN; /* 0x400090b8 */ + __IO uint8_t UEP7_TX_CTRL; /* 0x400090ba */ + __IO uint8_t UEP7_RX_CTRL; /* 0x400090bb */ + __IO uint16_t UEP_TX_ISO; /* 0x400090bc */ + __IO uint16_t UEP_RX_ISO; /* 0x400090be */ +} USBHSD_TypeDef; \ No newline at end of file diff --git a/kernel/cherryusb/port/ch32/ch58x/usb_ch58x_dc_usbfs.c b/kernel/cherryusb/port/ch32/ch58x/usb_ch58x_dc_usbfs.c new file mode 100644 index 0000000..e86f418 --- /dev/null +++ b/kernel/cherryusb/port/ch32/ch58x/usb_ch58x_dc_usbfs.c @@ -0,0 +1,640 @@ +/* + * Copyright (c) 2022, sakumisu + * + * SPDX-License-Identifier: Apache-2.0 + */ +#include "usbd_core.h" +#include "usb_ch58x_usbfs_reg.h" + +/** + * @brief Related register macro + */ +#define USB0_BASE 0x40008000u +#define USB1_BASE 0x40008400u + +#ifndef USBD +#define USBD USB0_BASE +#endif +#define CH58x_USBFS_DEV ((USB_FS_TypeDef *)USBD) + +/*!< 8-bit value of endpoint control register */ +#define EPn_CTRL(epid) \ + *(volatile uint8_t *)(&(CH58x_USBFS_DEV->UEP0_CTRL) + epid * 4 + (epid / 5) * 48) + +/*!< The length register value of the endpoint send buffer */ +#define EPn_TX_LEN(epid) \ + *(volatile uint8_t *)(&(CH58x_USBFS_DEV->UEP0_T_LEN) + epid * 4 + (epid / 5) * 48) + +/*!< Read setup packet to use in ep0 in */ +#define GET_SETUP_PACKET(data_add) \ + *(struct usb_setup_packet *)data_add + +/*!< Set epid ep tx valid // Not an isochronous endpoint */ +#define EPn_SET_TX_VALID(epid) \ + EPn_CTRL(epid) = (EPn_CTRL(epid) & ~MASK_UEP_T_RES) | UEP_T_RES_ACK; +/*!< Set epid ep rx valid // Not an isochronous endpoint */ +#define EPn_SET_RX_VALID(epid) \ + EPn_CTRL(epid) = (EPn_CTRL(epid) & ~MASK_UEP_R_RES) | UEP_R_RES_ACK; +/*!< Set epid ep tx valid // Isochronous endpoint */ +#define EPn_SET_TX_ISO_VALID(epid) \ + EPn_CTRL(epid) = (EPn_CTRL(epid) & ~MASK_UEP_T_RES) | UEP_T_RES_TOUT; +/*!< Set epid ep rx valid // Isochronous endpoint */ +#define EPn_SET_RX_ISO_VALID(epid) \ + EPn_CTRL(epid) = (EPn_CTRL(epid) & ~MASK_UEP_R_RES) | UEP_R_RES_TOUT; +/*!< Set epid ep tx nak */ +#define EPn_SET_TX_NAK(epid) \ + EPn_CTRL(epid) = (EPn_CTRL(epid) & ~MASK_UEP_T_RES) | UEP_T_RES_NAK; +/*!< Set epid ep rx nak */ +#define EPn_SET_RX_NAK(epid) \ + EPn_CTRL(epid) = (EPn_CTRL(epid) & ~MASK_UEP_R_RES) | UEP_R_RES_NAK; +/*!< Set epid ep tx stall */ +#define EPn_SET_TX_STALL(epid) \ + EPn_CTRL(epid) = (EPn_CTRL(epid) & ~MASK_UEP_T_RES) | UEP_T_RES_STALL +/*!< Set epid ep rx stall */ +#define EPn_SET_RX_STALL(epid) \ + EPn_CTRL(epid) = (EPn_CTRL(epid) & ~MASK_UEP_R_RES) | UEP_R_RES_STALL +/*!< Clear epid ep tx stall */ +#define EPn_CLR_TX_STALL(epid) \ + EPn_CTRL(epid) = (EPn_CTRL(epid) & ~(RB_UEP_T_TOG | MASK_UEP_T_RES)) | UEP_T_RES_NAK +/*!< Clear epid ep rx stall */ +#define EPn_CLR_RX_STALL(epid) \ + EPn_CTRL(epid) = (EPn_CTRL(epid) & ~(RB_UEP_R_TOG | MASK_UEP_R_RES)) | UEP_R_RES_ACK +/*!< Set epid ep tx len */ +#define EPn_SET_TX_LEN(epid, len) \ + EPn_TX_LEN(epid) = len +/*!< Get epid ep rx len */ +#define EPn_GET_RX_LEN(epid) \ + CH58x_USBFS_DEV->USB_RX_LEN + +/*!< ep nums */ +#ifndef CONFIG_USBDEV_EP_NUM +#define CONFIG_USBDEV_EP_NUM 5 +#endif +/*!< ep mps */ +#define EP_MPS 64 +/*!< set ep4 in mps 64 */ +#define EP4_IN_MPS EP_MPS +/*!< set ep4 out mps 64 */ +#define EP4_OUT_MPS EP_MPS + +/*!< User defined assignment endpoint RAM */ +__attribute__((aligned(4))) uint8_t ep0_data_buff[64 + EP4_OUT_MPS + EP4_IN_MPS]; /*!< ep0(64)+ep4_out(64)+ep4_in(64) */ +__attribute__((aligned(4))) uint8_t ep1_data_buff[64 + 64]; /*!< ep1_out(64)+ep1_in(64) */ +__attribute__((aligned(4))) uint8_t ep2_data_buff[64 + 64]; /*!< ep2_out(64)+ep2_in(64) */ +__attribute__((aligned(4))) uint8_t ep3_data_buff[64 + 64]; /*!< ep3_out(64)+ep3_in(64) */ +#if (CONFIG_USBDEV_EP_NUM == 8) +/** + * This dcd porting can be used on ch581, ch582, ch583, + * and also on ch571, ch572, and ch573. Note that only five endpoints are available for ch571, ch572, and ch573. + */ +__attribute__((aligned(4))) uint8_t ep5_data_buff[64 + 64]; /*!< ep5_out(64)+ep5_in(64) */ +__attribute__((aligned(4))) uint8_t ep6_data_buff[64 + 64]; /*!< ep6_out(64)+ep6_in(64) */ +__attribute__((aligned(4))) uint8_t ep7_data_buff[64 + 64]; /*!< ep7_out(64)+ep7_in(64) */ +#endif +/** + * @brief Endpoint information structure + */ +typedef struct _usbd_ep_info { + uint8_t mps; /*!< Maximum packet length of endpoint */ + uint8_t eptype; /*!< Endpoint Type */ + uint8_t *ep_ram_addr; /*!< Endpoint buffer address */ + + uint8_t ep_enable; /* Endpoint enable */ + uint8_t *xfer_buf; + uint32_t xfer_len; + uint32_t actual_xfer_len; +} usbd_ep_info; + +/*!< ch58x usb */ +static struct _ch58x_core_prvi { + uint8_t address; /*!< Address */ + usbd_ep_info ep_in[CONFIG_USBDEV_EP_NUM]; + usbd_ep_info ep_out[CONFIG_USBDEV_EP_NUM]; + struct usb_setup_packet setup; +} usb_dc_cfg; + +__WEAK void usb_dc_low_level_init(void) +{ +} + +__WEAK void usb_dc_low_level_deinit(void) +{ +} + +/** + * @brief USB initialization + * @pre None + * @param[in] None + * @retval >=0 success otherwise failure + */ +int usb_dc_init(uint8_t busid) +{ + usb_dc_cfg.ep_in[0].ep_ram_addr = ep0_data_buff; + usb_dc_cfg.ep_out[0].ep_ram_addr = ep0_data_buff; + + usb_dc_cfg.ep_in[1].ep_ram_addr = ep1_data_buff + 64; + usb_dc_cfg.ep_out[1].ep_ram_addr = ep1_data_buff; + + usb_dc_cfg.ep_in[2].ep_ram_addr = ep2_data_buff + 64; + usb_dc_cfg.ep_out[2].ep_ram_addr = ep2_data_buff; + + usb_dc_cfg.ep_in[3].ep_ram_addr = ep3_data_buff + 64; + usb_dc_cfg.ep_out[3].ep_ram_addr = ep3_data_buff; + + usb_dc_cfg.ep_in[4].ep_ram_addr = ep0_data_buff + 64 + EP4_OUT_MPS; + usb_dc_cfg.ep_out[4].ep_ram_addr = ep0_data_buff + 64; +#if (CONFIG_USBDEV_EP_NUM == 8) + usb_dc_cfg.ep_in[5].ep_ram_addr = ep5_data_buff + 64; + usb_dc_cfg.ep_out[5].ep_ram_addr = ep5_data_buff; + + usb_dc_cfg.ep_in[6].ep_ram_addr = ep6_data_buff + 64; + usb_dc_cfg.ep_out[6].ep_ram_addr = ep6_data_buff; + + usb_dc_cfg.ep_in[7].ep_ram_addr = ep7_data_buff + 64; + usb_dc_cfg.ep_out[7].ep_ram_addr = ep7_data_buff; +#endif + /*!< Set the mode first and cancel RB_UC_CLR_ALL */ + CH58x_USBFS_DEV->USB_CTRL = 0x00; + CH58x_USBFS_DEV->UEP4_1_MOD = RB_UEP4_RX_EN | RB_UEP4_TX_EN | RB_UEP1_RX_EN | RB_UEP1_TX_EN; /*!< EP4 OUT+IN EP1 OUT+IN */ + CH58x_USBFS_DEV->UEP2_3_MOD = RB_UEP2_RX_EN | RB_UEP2_TX_EN | RB_UEP3_RX_EN | RB_UEP3_TX_EN; /*!< EP2 OUT+IN EP3 OUT+IN */ +#if (CONFIG_USBDEV_EP_NUM == 8) + CH58x_USBFS_DEV->UEP567_MOD = RB_UEP5_RX_EN | RB_UEP5_TX_EN | RB_UEP6_RX_EN | RB_UEP6_TX_EN | RB_UEP7_RX_EN | RB_UEP7_TX_EN; /*!< EP5 EP6 EP7 OUT+IN */ +#endif + CH58x_USBFS_DEV->UEP0_DMA = (uint16_t)(uint32_t)ep0_data_buff; + CH58x_USBFS_DEV->UEP1_DMA = (uint16_t)(uint32_t)ep1_data_buff; + CH58x_USBFS_DEV->UEP2_DMA = (uint16_t)(uint32_t)ep2_data_buff; + CH58x_USBFS_DEV->UEP3_DMA = (uint16_t)(uint32_t)ep3_data_buff; +#if (CONFIG_USBDEV_EP_NUM == 8) + CH58x_USBFS_DEV->UEP5_DMA = (uint16_t)(uint32_t)ep5_data_buff; + CH58x_USBFS_DEV->UEP6_DMA = (uint16_t)(uint32_t)ep6_data_buff; + CH58x_USBFS_DEV->UEP7_DMA = (uint16_t)(uint32_t)ep7_data_buff; +#endif + CH58x_USBFS_DEV->UEP0_CTRL = UEP_R_RES_NAK | UEP_T_RES_NAK; + CH58x_USBFS_DEV->UEP1_CTRL = UEP_R_RES_NAK | UEP_T_RES_NAK | RB_UEP_AUTO_TOG; + CH58x_USBFS_DEV->UEP2_CTRL = UEP_R_RES_NAK | UEP_T_RES_NAK | RB_UEP_AUTO_TOG; + CH58x_USBFS_DEV->UEP3_CTRL = UEP_R_RES_NAK | UEP_T_RES_NAK | RB_UEP_AUTO_TOG; + CH58x_USBFS_DEV->UEP4_CTRL = UEP_R_RES_NAK | UEP_T_RES_NAK; +#if (CONFIG_USBDEV_EP_NUM == 8) + CH58x_USBFS_DEV->UEP5_CTRL = UEP_R_RES_NAK | UEP_T_RES_NAK | RB_UEP_AUTO_TOG; + CH58x_USBFS_DEV->UEP6_CTRL = UEP_R_RES_NAK | UEP_T_RES_NAK | RB_UEP_AUTO_TOG; + CH58x_USBFS_DEV->UEP7_CTRL = UEP_R_RES_NAK | UEP_T_RES_NAK | RB_UEP_AUTO_TOG; +#endif + CH58x_USBFS_DEV->USB_DEV_AD = 0x00; + + /*!< Start the USB device and DMA, and automatically return to NAK before the interrupt flag is cleared during the interrupt */ + CH58x_USBFS_DEV->USB_CTRL = RB_UC_DEV_PU_EN | RB_UC_INT_BUSY | RB_UC_DMA_EN; + if ((uint32_t) & (CH58x_USBFS_DEV->USB_CTRL) == (uint32_t)USB0_BASE) { + /*!< USB0 */ + R16_PIN_ANALOG_IE |= RB_PIN_USB_IE | RB_PIN_USB_DP_PU; + } else if ((uint32_t) & (CH58x_USBFS_DEV->USB_CTRL) == (uint32_t)USB1_BASE) { + /*!< USB1 */ + R16_PIN_ANALOG_IE |= RB_PIN_USB2_IE | RB_PIN_USB2_DP_PU; + } + + CH58x_USBFS_DEV->USB_INT_FG = 0xff; /*!< Clear interrupt flag */ + CH58x_USBFS_DEV->UDEV_CTRL = RB_UD_PD_DIS | RB_UD_PORT_EN; /*!< Allow USB port */ + CH58x_USBFS_DEV->USB_INT_EN = RB_UIE_SUSPEND | RB_UIE_BUS_RST | RB_UIE_TRANSFER; + + usb_dc_low_level_init(); + return 0; +} + +int usb_dc_deinit(uint8_t busid) +{ + return 0; +} + +/** + * @brief Set address + * @pre None + * @param[in] address ：8-bit valid address + * @retval >=0 success otherwise failure + */ +int usbd_set_address(uint8_t busid, const uint8_t address) +{ + if (address == 0) { + CH58x_USBFS_DEV->USB_DEV_AD = (CH58x_USBFS_DEV->USB_DEV_AD & 0x80) | address; + } + usb_dc_cfg.address = address; + return 0; +} + +int usbd_set_remote_wakeup(uint8_t busid) +{ + return -1; +} + +uint8_t usbd_get_port_speed(uint8_t busid) +{ + return USB_SPEED_FULL; +} + +/** + * @brief Open endpoint + * @pre None + * @param[in] ep_cfg : Endpoint configuration structure pointer + * @retval >=0 success otherwise failure + */ +int usbd_ep_open(uint8_t busid, const struct usb_endpoint_descriptor *ep) +{ + /*!< ep id */ + uint8_t epid = USB_EP_GET_IDX(ep->bEndpointAddress); + if (epid > (CONFIG_USBDEV_EP_NUM - 1)) { + /** + * If you use ch58x, you can change the CONFIG_USBDEV_EP_NUM set to 8 + */ + USB_LOG_ERR("Ep addr %02x overflow\r\n", ep->bEndpointAddress); + return -1; + } + + /*!< ep max packet length */ + uint8_t mps = USB_GET_MAXPACKETSIZE(ep->wMaxPacketSize); + /*!< update ep max packet length */ + if (USB_EP_DIR_IS_IN(ep->bEndpointAddress)) { + /*!< in */ + usb_dc_cfg.ep_in[epid].ep_enable = true; + usb_dc_cfg.ep_in[epid].mps = mps; + usb_dc_cfg.ep_in[epid].eptype = USB_GET_ENDPOINT_TYPE(ep->bmAttributes); + } else if (USB_EP_DIR_IS_OUT(ep->bEndpointAddress)) { + /*!< out */ + usb_dc_cfg.ep_out[epid].ep_enable = true; + usb_dc_cfg.ep_out[epid].mps = mps; + usb_dc_cfg.ep_out[epid].eptype = USB_GET_ENDPOINT_TYPE(ep->bmAttributes); + } + return 0; +} + +/** + * @brief Close endpoint + * @pre None + * @param[in] ep ： Endpoint address + * @retval >=0 success otherwise failure + */ +int usbd_ep_close(uint8_t busid, const uint8_t ep) +{ + /*!< ep id */ + uint8_t epid = USB_EP_GET_IDX(ep); + if (USB_EP_DIR_IS_IN(ep)) { + /*!< in */ + usb_dc_cfg.ep_in[epid].ep_enable = false; + } else if (USB_EP_DIR_IS_OUT(ep)) { + /*!< out */ + usb_dc_cfg.ep_out[epid].ep_enable = false; + } + return 0; +} + + +/** + * @brief Endpoint setting stall + * @pre None + * @param[in] ep ： Endpoint address + * @retval >=0 success otherwise failure + */ +int usbd_ep_set_stall(uint8_t busid, const uint8_t ep) +{ + /*!< ep id */ + uint8_t epid = USB_EP_GET_IDX(ep); + if (USB_EP_DIR_IS_OUT(ep)) { + EPn_SET_RX_STALL(epid); + } else { + EPn_SET_TX_STALL(epid); + } + return 0; +} + +/** + * @brief Endpoint clear stall + * @pre None + * @param[in] ep ： Endpoint address + * @retval >=0 success otherwise failure + */ +int usbd_ep_clear_stall(uint8_t busid, const uint8_t ep) +{ + uint8_t epid = USB_EP_GET_IDX(ep); + if (USB_EP_DIR_IS_OUT(ep)) { + EPn_CLR_RX_STALL(epid); + } else { + EPn_CLR_TX_STALL(epid); + } + return 0; +} + +/** + * @brief Check endpoint status + * @pre None + * @param[in] ep ： Endpoint address + * @param[out] stalled ： Outgoing endpoint status + * @retval >=0 success otherwise failure + */ +int usbd_ep_is_stalled(uint8_t busid, const uint8_t ep, uint8_t *stalled) +{ + if (USB_EP_DIR_IS_OUT(ep)) { + } else { + } + return 0; +} + +/** + * @brief Setup in ep transfer setting and start transfer. + * + * This function is asynchronous. + * This function is similar to uart with tx dma. + * + * This function is called to write data to the specified endpoint. The + * supplied usbd_endpoint_callback function will be called when data is transmitted + * out. + * + * @param[in] ep Endpoint address corresponding to the one + * listed in the device configuration table + * @param[in] data Pointer to data to write + * @param[in] data_len Length of the data requested to write. This may + * be zero for a zero length status packet. + * @return 0 on success, negative errno code on fail. + */ +int usbd_ep_start_write(uint8_t busid, const uint8_t ep, const uint8_t *data, uint32_t data_len) +{ + uint8_t ep_idx = USB_EP_GET_IDX(ep); + + if (!data && data_len) { + return -1; + } + if (!usb_dc_cfg.ep_in[ep_idx].ep_enable) { + return -2; + } + if ((uint32_t)data & 0x03) { + return -3; + } + + usb_dc_cfg.ep_in[ep_idx].xfer_buf = (uint8_t *)data; + usb_dc_cfg.ep_in[ep_idx].xfer_len = data_len; + usb_dc_cfg.ep_in[ep_idx].actual_xfer_len = 0; + + if (data_len == 0) { + /*!< write 0 len data */ + EPn_SET_TX_LEN(ep_idx, 0); + /*!< enable tx */ + if (usb_dc_cfg.ep_in[ep_idx].eptype != USB_ENDPOINT_TYPE_ISOCHRONOUS) { + EPn_SET_TX_VALID(ep_idx); + } else { + EPn_SET_TX_ISO_VALID(ep_idx); + } + /*!< return */ + return 0; + } else { + /*!< Not zlp */ + data_len = MIN(data_len, usb_dc_cfg.ep_in[ep_idx].mps); + /*!< write buff */ + memcpy(usb_dc_cfg.ep_in[ep_idx].ep_ram_addr, data, data_len); + /*!< write real_wt_nums len data */ + EPn_SET_TX_LEN(ep_idx, data_len); + /*!< enable tx */ + if (usb_dc_cfg.ep_in[ep_idx].eptype != USB_ENDPOINT_TYPE_ISOCHRONOUS) { + EPn_SET_TX_VALID(ep_idx); + } else { + EPn_SET_TX_ISO_VALID(ep_idx); + } + } + return 0; +} + +/** + * @brief Setup out ep transfer setting and start transfer. + * + * This function is asynchronous. + * This function is similar to uart with rx dma. + * + * This function is called to read data to the specified endpoint. The + * supplied usbd_endpoint_callback function will be called when data is received + * in. + * + * @param[in] ep Endpoint address corresponding to the one + * listed in the device configuration table + * @param[in] data Pointer to data to read + * @param[in] data_len Max length of the data requested to read. + * + * @return 0 on success, negative errno code on fail. + */ +int usbd_ep_start_read(uint8_t busid, const uint8_t ep, uint8_t *data, uint32_t data_len) +{ + uint8_t ep_idx = USB_EP_GET_IDX(ep); + + if (!data && data_len) { + return -1; + } + if (!usb_dc_cfg.ep_out[ep_idx].ep_enable) { + return -2; + } + if ((uint32_t)data & 0x03) { + return -3; + } + + usb_dc_cfg.ep_out[ep_idx].xfer_buf = (uint8_t *)data; + usb_dc_cfg.ep_out[ep_idx].xfer_len = data_len; + usb_dc_cfg.ep_out[ep_idx].actual_xfer_len = 0; + + if (data_len == 0) { + } else { + data_len = MIN(data_len, usb_dc_cfg.ep_out[ep_idx].mps); + } + + if (usb_dc_cfg.ep_out[ep_idx].eptype != USB_ENDPOINT_TYPE_ISOCHRONOUS) { + EPn_SET_RX_VALID(ep_idx); + } else { + EPn_SET_RX_ISO_VALID(ep_idx); + } + return 0; +} + +/** + * @brief USB interrupt processing function + * @pre None + * @param[in] None + * @retval None + */ +void USBD_IRQHandler(uint8_t busid) +{ + volatile uint8_t intflag = 0; + intflag = CH58x_USBFS_DEV->USB_INT_FG; + + if (intflag & RB_UIF_TRANSFER) { + if ((CH58x_USBFS_DEV->USB_INT_ST & MASK_UIS_TOKEN) != MASK_UIS_TOKEN) { + uint8_t epid = ((CH58x_USBFS_DEV->USB_INT_ST & (MASK_UIS_TOKEN | MASK_UIS_ENDP)) & 0x0f); + switch ((CH58x_USBFS_DEV->USB_INT_ST & (MASK_UIS_TOKEN | MASK_UIS_ENDP)) & 0xf0) { + case UIS_TOKEN_IN: + if (epid == 0) { + /** + * IN The host takes away the data that has been stored in FIFO + */ + switch (usb_dc_cfg.setup.bmRequestType >> USB_REQUEST_DIR_SHIFT) { + case 1: + /*!< Get */ + CH58x_USBFS_DEV->UEP0_CTRL ^= RB_UEP_T_TOG; + /** + * Here is to take away the last data, and the IN interrupt will be triggered only after it is successfully taken away. + * Therefore, the status of the in endpoint is set to NAK here. If there is data transmission, + * the endpoint status will be set to ack again in the in handler of EP0. + */ + EPn_SET_TX_NAK(0); + + /*!< IN */ + if (usb_dc_cfg.ep_in[0].xfer_len > usb_dc_cfg.ep_in[0].mps) { + usb_dc_cfg.ep_in[0].xfer_len -= usb_dc_cfg.ep_in[0].mps; + usb_dc_cfg.ep_in[0].actual_xfer_len += usb_dc_cfg.ep_in[0].mps; + usbd_event_ep_in_complete_handler(0, 0 | 0x80, usb_dc_cfg.ep_in[0].actual_xfer_len); + } else { + usb_dc_cfg.ep_in[0].actual_xfer_len += usb_dc_cfg.ep_in[0].xfer_len; + usb_dc_cfg.ep_in[0].xfer_len = 0; + usbd_event_ep_in_complete_handler(0, 0 | 0x80, usb_dc_cfg.ep_in[0].actual_xfer_len); + } + break; + case 0: + /*!< Set */ + switch (usb_dc_cfg.setup.bRequest) { + case USB_REQUEST_SET_ADDRESS: + /*!< Fill in the equipment address */ + CH58x_USBFS_DEV->USB_DEV_AD = (CH58x_USBFS_DEV->USB_DEV_AD & RB_UDA_GP_BIT) | usb_dc_cfg.address; + /** + * In the state phase after setting the address, the host has sent an in token packet of data1 to take the packet of 0 length, + * Ch58x USB IP needs to manually set the status of the in endpoint to NAK + */ + EPn_SET_TX_NAK(0); + EPn_SET_RX_VALID(0); + break; + default: + /*!< Normal out state phase */ + /** + * The host has sent an in token packet of data1 and taken the packet of 0 length. + * Here, you only need to set the status of the in endpoint to NAK and out endpoint ACK + */ + EPn_SET_TX_NAK(0); + EPn_SET_RX_VALID(0); + break; + } + break; + } + } else { + if (epid == 4) { + CH58x_USBFS_DEV->UEP4_CTRL ^= RB_UEP_T_TOG; + } + EPn_SET_TX_NAK(epid); + if (usb_dc_cfg.ep_in[epid].xfer_len > usb_dc_cfg.ep_in[epid].mps) { + /*!< Need start in again */ + usb_dc_cfg.ep_in[epid].xfer_buf += usb_dc_cfg.ep_in[epid].mps; + usb_dc_cfg.ep_in[epid].xfer_len -= usb_dc_cfg.ep_in[epid].mps; + usb_dc_cfg.ep_in[epid].actual_xfer_len += usb_dc_cfg.ep_in[epid].mps; + if (usb_dc_cfg.ep_in[epid].xfer_len > usb_dc_cfg.ep_in[epid].mps) { + memcpy(usb_dc_cfg.ep_in[epid].ep_ram_addr, usb_dc_cfg.ep_in[epid].xfer_buf, usb_dc_cfg.ep_in[epid].mps); + EPn_SET_TX_LEN(epid, usb_dc_cfg.ep_in[epid].mps); + } else { + memcpy(usb_dc_cfg.ep_in[epid].ep_ram_addr, usb_dc_cfg.ep_in[epid].xfer_buf, usb_dc_cfg.ep_in[epid].xfer_len); + EPn_SET_TX_LEN(epid, usb_dc_cfg.ep_in[epid].xfer_len); + } + if (usb_dc_cfg.ep_in[epid].eptype != USB_ENDPOINT_TYPE_ISOCHRONOUS) { + EPn_SET_TX_VALID(epid); + } else { + EPn_SET_TX_ISO_VALID(epid); + } + } else { + usb_dc_cfg.ep_in[epid].actual_xfer_len += usb_dc_cfg.ep_in[epid].xfer_len; + usb_dc_cfg.ep_in[epid].xfer_len = 0; + usbd_event_ep_in_complete_handler(0, epid | 0x80, usb_dc_cfg.ep_in[epid].actual_xfer_len); + } + } + break; + case UIS_TOKEN_OUT: + if (epid == 0) { + /*!< ep0 out */ + CH58x_USBFS_DEV->UEP0_CTRL ^= RB_UEP_R_TOG; + EPn_SET_RX_NAK(epid); + uint32_t read_count = EPn_GET_RX_LEN(0); + memcpy(usb_dc_cfg.ep_out[epid].xfer_buf, usb_dc_cfg.ep_out[epid].ep_ram_addr, read_count); + + usb_dc_cfg.ep_out[0].actual_xfer_len += read_count; + usb_dc_cfg.ep_out[0].xfer_len -= read_count; + usbd_event_ep_out_complete_handler(0, 0x00, usb_dc_cfg.ep_out[0].actual_xfer_len); + if (read_count == 0) { + /*!< Out status, start reading setup */ + EPn_SET_RX_VALID(0); + } + } else { + if ((CH58x_USBFS_DEV->USB_INT_ST) & RB_UIS_TOG_OK) { + if (epid == 4) { + CH58x_USBFS_DEV->UEP4_CTRL ^= RB_UEP_R_TOG; + } + EPn_SET_RX_NAK(epid); + uint32_t read_count = EPn_GET_RX_LEN(epid); + memcpy(usb_dc_cfg.ep_out[epid].xfer_buf, usb_dc_cfg.ep_out[epid].ep_ram_addr, read_count); + usb_dc_cfg.ep_out[epid].xfer_buf += read_count; + usb_dc_cfg.ep_out[epid].actual_xfer_len += read_count; + usb_dc_cfg.ep_out[epid].xfer_len -= read_count; + + if ((read_count < usb_dc_cfg.ep_out[epid].mps) || (usb_dc_cfg.ep_out[epid].xfer_len == 0)) { + usbd_event_ep_out_complete_handler(0, ((epid)&0x7f), usb_dc_cfg.ep_out[epid].actual_xfer_len); + } else { + if (usb_dc_cfg.ep_out[epid].eptype != USB_ENDPOINT_TYPE_ISOCHRONOUS) { + EPn_SET_RX_VALID(epid); + } else { + EPn_SET_RX_ISO_VALID(epid); + } + } + } + } + break; + default: + break; + } + CH58x_USBFS_DEV->USB_INT_FG = RB_UIF_TRANSFER; + } + + if (CH58x_USBFS_DEV->USB_INT_ST & RB_UIS_SETUP_ACT) { + /*!< Setup */ + /** + * Setup the device must respond with ACK, and the next data phase is DATA1 + * If it is sent, the data1 packet will be sent. + * If it is received, the data1 packet is expected to be received. + * If it is in, the host will send the data1 out packet to complete the status phase after the in completes. + * If it is out, the host will send the data1 in packet to complete the status phase after the out completes. + */ + CH58x_USBFS_DEV->UEP0_CTRL = RB_UEP_R_TOG | RB_UEP_T_TOG | UEP_T_RES_NAK; + /*!< get setup packet */ + usb_dc_cfg.setup = GET_SETUP_PACKET(usb_dc_cfg.ep_out[0].ep_ram_addr); + if (usb_dc_cfg.setup.bmRequestType >> USB_REQUEST_DIR_SHIFT == 0) { + /** + * Ep0 The next in must be the status stage. + * The device must reply to the host data 0 length packet. + * Here, set the transmission length to 0 and the transmission status to ACK, + * and wait for the host to send the in token to retrieve + */ + EPn_SET_TX_LEN(0, 0); + EPn_SET_TX_VALID(0); + } + EPn_SET_RX_NAK(0); + usbd_event_ep0_setup_complete_handler(0, (uint8_t *)&(usb_dc_cfg.setup)); + CH58x_USBFS_DEV->USB_INT_FG = RB_UIF_TRANSFER; + } + } else if (intflag & RB_UIF_BUS_RST) { + /*!< Reset */ + CH58x_USBFS_DEV->USB_DEV_AD = 0; + usbd_event_reset_handler(0); + /*!< Set ep0 rx vaild to start receive setup packet */ + EPn_SET_RX_VALID(0); + CH58x_USBFS_DEV->USB_INT_FG = RB_UIF_BUS_RST; + } else if (intflag & RB_UIF_SUSPEND) { + if (CH58x_USBFS_DEV->USB_MIS_ST & RB_UMS_SUSPEND) { + /*!< Suspend */ + } else { + /*!< Wake up */ + } + CH58x_USBFS_DEV->USB_INT_FG = RB_UIF_SUSPEND; + } else { + CH58x_USBFS_DEV->USB_INT_FG = intflag; + } +} + +void USB_IRQHandler(void) __attribute__((interrupt("WCH-Interrupt-fast"))) __attribute__((section(".highcode"))); +void USB_IRQHandler(void) +{ + extern void USBD_IRQHandler(uint8_t busid); + USBD_IRQHandler(0); +} diff --git a/kernel/cherryusb/port/ch32/ch58x/usb_ch58x_usbfs_reg.h b/kernel/cherryusb/port/ch32/ch58x/usb_ch58x_usbfs_reg.h new file mode 100644 index 0000000..f7fda8c --- /dev/null +++ b/kernel/cherryusb/port/ch32/ch58x/usb_ch58x_usbfs_reg.h @@ -0,0 +1,249 @@ +/* + * Copyright (c) 2022, sakumisu + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#define __IO volatile +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#define RB_UC_HOST_MODE 0x80 // enable USB host mode: 0=device mode, 1=host mode +#define RB_UC_LOW_SPEED 0x40 // enable USB low speed: 0=12Mbps, 1=1.5Mbps +#define RB_UC_DEV_PU_EN 0x20 // USB device enable and internal pullup resistance enable +#define RB_UC_SYS_CTRL1 0x20 // USB system control high bit +#define RB_UC_SYS_CTRL0 0x10 // USB system control low bit +#define MASK_UC_SYS_CTRL 0x30 // bit mask of USB system control +#define RB_UC_INT_BUSY 0x08 // enable automatic responding busy for device mode or automatic pause for host mode during interrupt flag UIF_TRANSFER valid +#define RB_UC_RESET_SIE 0x04 // force reset USB SIE, need software clear +#define RB_UC_CLR_ALL 0x02 // force clear FIFO and count of USB +#define RB_UC_DMA_EN 0x01 // DMA enable and DMA interrupt enable for USB + +#define RB_UD_PD_DIS 0x80 // disable USB UDP/UDM pulldown resistance: 0=enable pulldown, 1=disable +#define RB_UD_DP_PIN 0x20 // ReadOnly: indicate current UDP pin level +#define RB_UD_DM_PIN 0x10 // ReadOnly: indicate current UDM pin level +#define RB_UD_LOW_SPEED 0x04 // enable USB physical port low speed: 0=full speed, 1=low speed +#define RB_UD_GP_BIT 0x02 // general purpose bit +#define RB_UD_PORT_EN 0x01 // enable USB physical port I/O: 0=disable, 1=enable + +#define RB_UH_PD_DIS 0x80 // disable USB UDP/UDM pulldown resistance: 0=enable pulldown, 1=disable +#define RB_UH_DP_PIN 0x20 // ReadOnly: indicate current UDP pin level +#define RB_UH_DM_PIN 0x10 // ReadOnly: indicate current UDM pin level +#define RB_UH_LOW_SPEED 0x04 // enable USB port low speed: 0=full speed, 1=low speed +#define RB_UH_BUS_RESET 0x02 // control USB bus reset: 0=normal, 1=force bus reset +#define RB_UH_PORT_EN 0x01 // enable USB port: 0=disable, 1=enable port, automatic disabled if USB device detached + +#define RB_UIE_DEV_SOF 0x80 // enable interrupt for SOF received for USB device mode +#define RB_UIE_DEV_NAK 0x40 // enable interrupt for NAK responded for USB device mode +#define RB_UIE_FIFO_OV 0x10 // enable interrupt for FIFO overflow +#define RB_UIE_HST_SOF 0x08 // enable interrupt for host SOF timer action for USB host mode +#define RB_UIE_SUSPEND 0x04 // enable interrupt for USB suspend or resume event +#define RB_UIE_TRANSFER 0x02 // enable interrupt for USB transfer completion +#define RB_UIE_DETECT 0x01 // enable interrupt for USB device detected event for USB host mode +#define RB_UIE_BUS_RST 0x01 // enable interrupt for USB bus reset event for USB device mode + +#define RB_UDA_GP_BIT 0x80 // general purpose bit +#define MASK_USB_ADDR 0x7F // bit mask for USB device address + +#define RB_UMS_SOF_PRES 0x80 // RO, indicate host SOF timer presage status +#define RB_UMS_SOF_ACT 0x40 // RO, indicate host SOF timer action status for USB host +#define RB_UMS_SIE_FREE 0x20 // RO, indicate USB SIE free status +#define RB_UMS_R_FIFO_RDY 0x10 // RO, indicate USB receiving FIFO ready status (not empty) +#define RB_UMS_BUS_RESET 0x08 // RO, indicate USB bus reset status +#define RB_UMS_SUSPEND 0x04 // RO, indicate USB suspend status +#define RB_UMS_DM_LEVEL 0x02 // RO, indicate UDM level saved at device attached to USB host +#define RB_UMS_DEV_ATTACH 0x01 // RO, indicate device attached status on USB host + +#define RB_U_IS_NAK 0x80 // RO, indicate current USB transfer is NAK received +#define RB_U_TOG_OK 0x40 // RO, indicate current USB transfer toggle is OK +#define RB_U_SIE_FREE 0x20 // RO, indicate USB SIE free status +#define RB_UIF_FIFO_OV 0x10 // FIFO overflow interrupt flag for USB, direct bit address clear or write 1 to clear +#define RB_UIF_HST_SOF 0x08 // host SOF timer interrupt flag for USB host, direct bit address clear or write 1 to clear +#define RB_UIF_SUSPEND 0x04 // USB suspend or resume event interrupt flag, direct bit address clear or write 1 to clear +#define RB_UIF_TRANSFER 0x02 // USB transfer completion interrupt flag, direct bit address clear or write 1 to clear +#define RB_UIF_DETECT 0x01 // device detected event interrupt flag for USB host mode, direct bit address clear or write 1 to clear +#define RB_UIF_BUS_RST 0x01 // bus reset event interrupt flag for USB device mode, direct bit address clear or write 1 to clear + +#define RB_UIS_SETUP_ACT 0x80 // RO, indicate SETUP token & 8 bytes setup request received for USB device mode +#define RB_UIS_TOG_OK 0x40 // RO, indicate current USB transfer toggle is OK +#define RB_UIS_TOKEN1 0x20 // RO, current token PID code bit 1 received for USB device mode +#define RB_UIS_TOKEN0 0x10 // RO, current token PID code bit 0 received for USB device mode +#define MASK_UIS_TOKEN 0x30 // RO, bit mask of current token PID code received for USB device mode +#define UIS_TOKEN_OUT 0x00 +#define UIS_TOKEN_SOF 0x10 +#define UIS_TOKEN_IN 0x20 +#define UIS_TOKEN_SETUP 0x30 + +#define MASK_UIS_ENDP 0x0F // RO, bit mask of current transfer endpoint number for USB device mode +#define MASK_UIS_H_RES 0x0F // RO, bit mask of current transfer handshake response for USB host mode: 0000=no response, time out from device, others=handshake response PID received + +#define R8_USB_RX_LEN (*((uint8_t *)0x40008008)) // USB receiving length +#define RB_UEP1_RX_EN 0x80 // enable USB endpoint 1 receiving (OUT) +#define RB_UEP1_TX_EN 0x40 // enable USB endpoint 1 transmittal (IN) +#define RB_UEP1_BUF_MOD 0x10 // buffer mode of USB endpoint 1 + +#define RB_UEP4_RX_EN 0x08 // enable USB endpoint 4 receiving (OUT) +#define RB_UEP4_TX_EN 0x04 // enable USB endpoint 4 transmittal (IN) + +#define RB_UEP3_RX_EN 0x80 // enable USB endpoint 3 receiving (OUT) +#define RB_UEP3_TX_EN 0x40 // enable USB endpoint 3 transmittal (IN) +#define RB_UEP3_BUF_MOD 0x10 // buffer mode of USB endpoint 3 +#define RB_UEP2_RX_EN 0x08 // enable USB endpoint 2 receiving (OUT) +#define RB_UEP2_TX_EN 0x04 // enable USB endpoint 2 transmittal (IN) +#define RB_UEP2_BUF_MOD 0x01 // buffer mode of USB endpoint 2 + +#define RB_UEP7_RX_EN 0x20 // enable USB endpoint 7 receiving (OUT) +#define RB_UEP7_TX_EN 0x10 // enable USB endpoint 7 transmittal (IN) +#define RB_UEP6_RX_EN 0x08 // enable USB endpoint 6 receiving (OUT) +#define RB_UEP6_TX_EN 0x04 // enable USB endpoint 6 transmittal (IN) +#define RB_UEP5_RX_EN 0x02 // enable USB endpoint 5 receiving (OUT) +#define RB_UEP5_TX_EN 0x01 // enable USB endpoint 5 transmittal (IN) + +#define RB_UH_EP_TX_EN 0x40 // enable USB host OUT endpoint transmittal +#define RB_UH_EP_TBUF_MOD 0x10 // buffer mode of USB host OUT endpoint + +#define RB_UH_EP_RX_EN 0x08 // enable USB host IN endpoint receiving +#define RB_UH_EP_RBUF_MOD 0x01 // buffer mode of USB host IN endpoint + +#define RB_UEP_R_TOG 0x80 // expected data toggle flag of USB endpoint X receiving (OUT): 0=DATA0, 1=DATA1 +#define RB_UEP_T_TOG 0x40 // prepared data toggle flag of USB endpoint X transmittal (IN): 0=DATA0, 1=DATA1 +#define RB_UEP_AUTO_TOG 0x10 // enable automatic toggle after successful transfer completion on endpoint 1/2/3: 0=manual toggle, 1=automatic toggle +#define RB_UEP_R_RES1 0x08 // handshake response type high bit for USB endpoint X receiving (OUT) +#define RB_UEP_R_RES0 0x04 // handshake response type low bit for USB endpoint X receiving (OUT) +#define MASK_UEP_R_RES 0x0C // bit mask of handshake response type for USB endpoint X receiving (OUT) +#define UEP_R_RES_ACK 0x00 +#define UEP_R_RES_TOUT 0x04 +#define UEP_R_RES_NAK 0x08 +#define UEP_R_RES_STALL 0x0C + +#define RB_UEP_T_RES1 0x02 // handshake response type high bit for USB endpoint X transmittal (IN) +#define RB_UEP_T_RES0 0x01 // handshake response type low bit for USB endpoint X transmittal (IN) +#define MASK_UEP_T_RES 0x03 // bit mask of handshake response type for USB endpoint X transmittal (IN) +#define UEP_T_RES_ACK 0x00 +#define UEP_T_RES_TOUT 0x01 +#define UEP_T_RES_NAK 0x02 +#define UEP_T_RES_STALL 0x03 + +#define RB_UH_PRE_PID_EN 0x80 // USB host PRE PID enable for low speed device via hub +#define RB_UH_SOF_EN 0x40 // USB host automatic SOF enable + +#define R8_UH_EP_PID R8_UEP2_T_LEN // host endpoint and PID +#define MASK_UH_TOKEN 0xF0 // bit mask of token PID for USB host transfer +#define MASK_UH_ENDP 0x0F // bit mask of endpoint number for USB host transfer + +#define R8_UH_RX_CTRL R8_UEP2_CTRL // host receiver endpoint control +#define RB_UH_R_TOG 0x80 // expected data toggle flag of host receiving (IN): 0=DATA0, 1=DATA1 +#define RB_UH_R_AUTO_TOG 0x10 // enable automatic toggle after successful transfer completion: 0=manual toggle, 1=automatic toggle +#define RB_UH_R_RES 0x04 // prepared handshake response type for host receiving (IN): 0=ACK (ready), 1=no response, time out to device, for isochronous transactions + +#define R8_UH_TX_LEN R8_UEP3_T_LEN // host transmittal endpoint transmittal length + +#define RB_UH_T_TOG 0x40 // prepared data toggle flag of host transmittal (SETUP/OUT): 0=DATA0, 1=DATA1 +#define RB_UH_T_AUTO_TOG 0x10 // enable automatic toggle after successful transfer completion: 0=manual toggle, 1=automatic toggle +#define RB_UH_T_RES 0x01 // expected handshake response type for host transmittal (SETUP/OUT): 0=ACK (ready), 1=no response, time out from device, for isochronous transactions + +#define R16_PIN_ANALOG_IE (*((uint16_t *)0x4000101A)) // RW, analog pin enable and digital input disable +#define RB_PIN_USB_IE 0x80 // RW, USB analog I/O enable: 0=analog I/O disable, 1=analog I/O enable +#define RB_PIN_USB_DP_PU 0x40 // RW, USB UDP internal pullup resistance enable: 0=enable/disable by RB_UC_DEV_PU_EN, 1=enable pullup, replace RB_UC_DEV_PU_EN under sleep mode +#define RB_PIN_USB2_IE 0x20 // RW, USB2 analog I/O enable: 0=analog I/O disable, 1=analog I/O enable +#define RB_PIN_USB2_DP_PU 0x10 // RW, USB2 UDP internal pullup resistance enable: 0=enable/disable by RB_UC_DEV_PU_EN, 1=enable pullup, replace RB_UC_DEV_PU_EN under sleep mode +/*!< USB Regs */ +typedef struct +{ + __IO uint8_t USB_CTRL; /*!< 0x40008000 */ + union { + __IO uint8_t UDEV_CTRL; /*!< 0x40008001 */ + __IO uint8_t UHOST_CTRL; /*!< 0x40008001 */ + }; + __IO uint8_t USB_INT_EN; /*!< 0x40008002 */ + __IO uint8_t USB_DEV_AD; /*!< 0x40008003 */ + __IO uint8_t USB_STATUS0; /*!< 0x40008004 */ + __IO uint8_t USB_MIS_ST; /*!< 0x40008005 */ + __IO uint8_t USB_INT_FG; /*!< 0x40008006 */ + __IO uint8_t USB_INT_ST; /*!< 0x40008007 */ + __IO uint8_t USB_RX_LEN; /*!< 0x40008008 */ + __IO uint8_t Reserve1; /*!< 0x40008009 */ + __IO uint8_t Reserve2; /*!< 0x4000800a */ + __IO uint8_t Reserve3; /*!< 0x4000800b */ + __IO uint8_t UEP4_1_MOD; /*!< 0x4000800c */ + union { + __IO uint8_t UEP2_3_MOD; /*!< 0x4000800d */ + __IO uint8_t UH_EP_MOD; /*!< 0x4000800d */ + }; + __IO uint8_t UEP567_MOD; /*!< 0x4000800e */ + __IO uint8_t Reserve4; /*!< 0x4000800f */ + __IO uint16_t UEP0_DMA; /*!< 0x40008010 */ + __IO uint16_t Reserve5; /*!< 0x40008012 */ + __IO uint16_t UEP1_DMA; /*!< 0x40008014 */ + __IO uint16_t Reserve6; /*!< 0x40008016 */ + union { + __IO uint16_t UEP2_DMA; /*!< 0x40008018 */ + __IO uint16_t UH_RX_DMA; /*!< 0x40008018 */ + }; + __IO uint16_t Reserve7; /*!< 0x4000801a */ + union { + __IO uint16_t UEP3_DMA; /*!< 0x4000801c */ + __IO uint16_t UH_TX_DMA; /*!< 0x4000801c */ + }; + __IO uint16_t Reserve8; /*!< 0x4000801e */ + __IO uint8_t UEP0_T_LEN; /*!< 0x40008020 */ + __IO uint8_t Reserve9; /*!< 0x40008021 */ + __IO uint8_t UEP0_CTRL; /*!< 0x40008022 */ + __IO uint8_t Reserve10; /*!< 0x40008023 */ + __IO uint8_t UEP1_T_LEN; /*!< 0x40008024 */ + __IO uint8_t Reserve11; /*!< 0x40008025 */ + union { + __IO uint8_t UEP1_CTRL; /*!< 0x40008026 */ + __IO uint8_t UH_SETUP; /*!< 0x40008026 */ + }; + __IO uint8_t Reserve12; /*!< 0x40008027 */ + union { + __IO uint8_t UEP2_T_LEN; /*!< 0x40008028 */ + __IO uint8_t UH_EP_PID; /*!< 0x40008028 */ + }; + __IO uint8_t Reserve13; /*!< 0x40008029 */ + union { + __IO uint8_t UEP2_CTRL; /*!< 0x4000802a */ + __IO uint8_t UH_RX_CTRL; /*!< 0x4000802a */ + }; + __IO uint8_t Reserve14; /*!< 0x4000802b */ + union { + __IO uint8_t UEP3_T_LEN; /*!< 0x4000802c */ + __IO uint8_t UH_TX_LEN; /*!< 0x4000802c */ + }; + __IO uint8_t Reserve15; /*!< 0x4000802d */ + union { + __IO uint8_t UEP3_CTRL; /*!< 0x4000802e */ + __IO uint8_t UH_TX_CTRL; /*!< 0x4000802e */ + }; + __IO uint8_t Reserve16; /*!< 0x4000802f */ + __IO uint8_t UEP4_T_LEN; /*!< 0x40008030 */ + __IO uint8_t Reserve17; /*!< 0x40008031 */ + __IO uint8_t UEP4_CTRL; /*!< 0x40008032 */ + __IO uint8_t Reserve18[33]; /*!< 0x40008033 */ + __IO uint16_t UEP5_DMA; /*!< 0x40008054 */ + __IO uint16_t Reserve19; /*!< 0x40008056 */ + __IO uint16_t UEP6_DMA; /*!< 0x40008058 */ + __IO uint16_t Reserve20; /*!< 0x4000805a */ + __IO uint16_t UEP7_DMA; /*!< 0x4000805c */ + __IO uint8_t Reserve21[6]; /*!< 0x4000805e */ + __IO uint8_t UEP5_T_LEN; /*!< 0x40008064 */ + __IO uint8_t Reserve22; /*!< 0x40008065 */ + __IO uint8_t UEP5_CTRL; /*!< 0x40008066 */ + __IO uint8_t Reserve23; /*!< 0x40008067 */ + __IO uint8_t UEP6_T_LEN; /*!< 0x40008068 */ + __IO uint8_t Reserve24; /*!< 0x40008069 */ + __IO uint8_t UEP6_CTRL; /*!< 0x4000806a */ + __IO uint8_t Reserve25; /*!< 0x4000806b */ + __IO uint8_t UEP7_T_LEN; /*!< 0x4000806c */ + __IO uint8_t Reserve26; /*!< 0x4000806d */ + __IO uint8_t UEP7_CTRL; /*!< 0x4000806e */ +} USB_FS_TypeDef; + +#ifdef __cplusplus +} +#endif diff --git a/kernel/cherryusb/port/chipidea/README.md b/kernel/cherryusb/port/chipidea/README.md new file mode 100644 index 0000000..c2c2160 --- /dev/null +++ b/kernel/cherryusb/port/chipidea/README.md @@ -0,0 +1,14 @@ +# Note + +## Support Chip List + +### NXP + +Modify USB_NOCACHE_RAM_SECTION + +``` +#define USB_NOCACHE_RAM_SECTION __attribute__((section(".NonCacheable"))) +``` + +- IMRT10XX/IMRT11XX (chipidea + EHCI) +- MCXN9XX/MCXN236 (chipidea + EHCI) diff --git a/kernel/cherryusb/port/chipidea/usb_chipidea_reg.h b/kernel/cherryusb/port/chipidea/usb_chipidea_reg.h new file mode 100644 index 0000000..4867ef5 --- /dev/null +++ b/kernel/cherryusb/port/chipidea/usb_chipidea_reg.h @@ -0,0 +1,2249 @@ +/* + * Copyright (c) 2021-2024 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + + +#ifndef HPM_USB_H +#define HPM_USB_H + +#define __R volatile const /* Define "read-only" permission */ +#define __RW volatile /* Define "read-write" permission */ +#define __W volatile /* Define "write-only" permission */ + +typedef struct { + __R uint8_t RESERVED0[128]; /* 0x0 - 0x7F: Reserved */ + __RW uint32_t GPTIMER0LD; /* 0x80: General Purpose Timer #0 Load Register */ + __RW uint32_t GPTIMER0CTRL; /* 0x84: General Purpose Timer #0 Controller Register */ + __RW uint32_t GPTIMER1LD; /* 0x88: General Purpose Timer #1 Load Register */ + __RW uint32_t GPTIMER1CTRL; /* 0x8C: General Purpose Timer #1 Controller Register */ + __RW uint32_t SBUSCFG; /* 0x90: System Bus Config Register */ + __R uint8_t RESERVED1[172]; /* 0x94 - 0x13F: Reserved */ + __RW uint32_t USBCMD; /* 0x140: USB Command Register */ + __RW uint32_t USBSTS; /* 0x144: USB Status Register */ + __RW uint32_t USBINTR; /* 0x148: Interrupt Enable Register */ + __RW uint32_t FRINDEX; /* 0x14C: USB Frame Index Register */ + __R uint8_t RESERVED2[4]; /* 0x150 - 0x153: Reserved */ + union { + __RW uint32_t DEVICEADDR; /* 0x154: Device Address Register */ + __RW uint32_t PERIODICLISTBASE; /* 0x154: Frame List Base Address Register */ + }; + union { + __RW uint32_t ASYNCLISTADDR; /* 0x158: Next Asynch. Address Register */ + __RW uint32_t ENDPTLISTADDR; /* 0x158: Endpoint List Address Register */ + }; + __R uint8_t RESERVED3[4]; /* 0x15C - 0x15F: Reserved */ + __RW uint32_t BURSTSIZE; /* 0x160: Programmable Burst Size Register */ + __RW uint32_t TXFILLTUNING; /* 0x164: TX FIFO Fill Tuning Register */ + __R uint8_t RESERVED4[16]; /* 0x168 - 0x177: Reserved */ + __RW uint32_t ENDPTNAK; /* 0x178: Endpoint NAK Register */ + __RW uint32_t ENDPTNAKEN; /* 0x17C: Endpoint NAK Enable Register */ + __R uint8_t RESERVED5[4]; /* 0x180 - 0x183: Reserved */ + __RW uint32_t PORTSC1; /* 0x184: Port Status & Control */ + __R uint8_t RESERVED6[28]; /* 0x188 - 0x1A3: Reserved */ + __RW uint32_t OTGSC; /* 0x1A4: On-The-Go Status & control Register */ + __RW uint32_t USBMODE; /* 0x1A8: USB Device Mode Register */ + __RW uint32_t ENDPTSETUPSTAT; /* 0x1AC: Endpoint Setup Status Register */ + __RW uint32_t ENDPTPRIME; /* 0x1B0: Endpoint Prime Register */ + __RW uint32_t ENDPTFLUSH; /* 0x1B4: Endpoint Flush Register */ + __R uint32_t ENDPTSTAT; /* 0x1B8: Endpoint Status Register */ + __RW uint32_t ENDPTCOMPLETE; /* 0x1BC: Endpoint Complete Register */ + __RW uint32_t ENDPTCTRL[8]; /* 0x1C0 - 0x1DC: Endpoint Control0 Register... Endpoint Control7 Register */ +} CHIPIDEA_TypeDef; + + +/* Bitfield definition for register: GPTIMER0LD */ +/* + * GPTLD (RW) + * + * GPTLD + * General Purpose Timer Load Value + * These bit fields are loaded to GPTCNT bits when GPTRST bit is set '1b'. + * This value represents the time in microseconds minus 1 for the timer duration. + * Example: for a one millisecond timer, load 1000-1=999 or 0x0003E7. + * NOTE: Max value is 0xFFFFFF or 16.777215 seconds. + */ +#define USB_GPTIMER0LD_GPTLD_MASK (0xFFFFFFUL) +#define USB_GPTIMER0LD_GPTLD_SHIFT (0U) +#define USB_GPTIMER0LD_GPTLD_SET(x) (((uint32_t)(x) << USB_GPTIMER0LD_GPTLD_SHIFT) & USB_GPTIMER0LD_GPTLD_MASK) +#define USB_GPTIMER0LD_GPTLD_GET(x) (((uint32_t)(x) & USB_GPTIMER0LD_GPTLD_MASK) >> USB_GPTIMER0LD_GPTLD_SHIFT) + +/* Bitfield definition for register: GPTIMER0CTRL */ +/* + * GPTRUN (RW) + * + * GPTRUN + * General Purpose Timer Run + * GPTCNT bits are not effected when setting or clearing this bit. + * 0 - Stop counting + * 1 - Run + */ +#define USB_GPTIMER0CTRL_GPTRUN_MASK (0x80000000UL) +#define USB_GPTIMER0CTRL_GPTRUN_SHIFT (31U) +#define USB_GPTIMER0CTRL_GPTRUN_SET(x) (((uint32_t)(x) << USB_GPTIMER0CTRL_GPTRUN_SHIFT) & USB_GPTIMER0CTRL_GPTRUN_MASK) +#define USB_GPTIMER0CTRL_GPTRUN_GET(x) (((uint32_t)(x) & USB_GPTIMER0CTRL_GPTRUN_MASK) >> USB_GPTIMER0CTRL_GPTRUN_SHIFT) + +/* + * GPTRST (WO) + * + * GPTRST + * General Purpose Timer Reset + * 0 - No action + * 1 - Load counter value from GPTLD bits in n_GPTIMER0LD + */ +#define USB_GPTIMER0CTRL_GPTRST_MASK (0x40000000UL) +#define USB_GPTIMER0CTRL_GPTRST_SHIFT (30U) +#define USB_GPTIMER0CTRL_GPTRST_SET(x) (((uint32_t)(x) << USB_GPTIMER0CTRL_GPTRST_SHIFT) & USB_GPTIMER0CTRL_GPTRST_MASK) +#define USB_GPTIMER0CTRL_GPTRST_GET(x) (((uint32_t)(x) & USB_GPTIMER0CTRL_GPTRST_MASK) >> USB_GPTIMER0CTRL_GPTRST_SHIFT) + +/* + * GPTMODE (RW) + * + * GPTMODE + * General Purpose Timer Mode + * In one shot mode, the timer will count down to zero, generate an interrupt, and stop until the counter is + * reset by software; + * In repeat mode, the timer will count down to zero, generate an interrupt and automatically reload the + * counter value from GPTLD bits to start again. + * 0 - One Shot Mode + * 1 - Repeat Mode + */ +#define USB_GPTIMER0CTRL_GPTMODE_MASK (0x1000000UL) +#define USB_GPTIMER0CTRL_GPTMODE_SHIFT (24U) +#define USB_GPTIMER0CTRL_GPTMODE_SET(x) (((uint32_t)(x) << USB_GPTIMER0CTRL_GPTMODE_SHIFT) & USB_GPTIMER0CTRL_GPTMODE_MASK) +#define USB_GPTIMER0CTRL_GPTMODE_GET(x) (((uint32_t)(x) & USB_GPTIMER0CTRL_GPTMODE_MASK) >> USB_GPTIMER0CTRL_GPTMODE_SHIFT) + +/* + * GPTCNT (RO) + * + * GPTCNT + * General Purpose Timer Counter. + * This field is the count value of the countdown timer. + */ +#define USB_GPTIMER0CTRL_GPTCNT_MASK (0xFFFFFFUL) +#define USB_GPTIMER0CTRL_GPTCNT_SHIFT (0U) +#define USB_GPTIMER0CTRL_GPTCNT_GET(x) (((uint32_t)(x) & USB_GPTIMER0CTRL_GPTCNT_MASK) >> USB_GPTIMER0CTRL_GPTCNT_SHIFT) + +/* Bitfield definition for register: GPTIMER1LD */ +/* + * GPTLD (RW) + * + * GPTLD + * General Purpose Timer Load Value + * These bit fields are loaded to GPTCNT bits when GPTRST bit is set '1b'. + * This value represents the time in microseconds minus 1 for the timer duration. + * Example: for a one millisecond timer, load 1000-1=999 or 0x0003E7. + * NOTE: Max value is 0xFFFFFF or 16.777215 seconds. + */ +#define USB_GPTIMER1LD_GPTLD_MASK (0xFFFFFFUL) +#define USB_GPTIMER1LD_GPTLD_SHIFT (0U) +#define USB_GPTIMER1LD_GPTLD_SET(x) (((uint32_t)(x) << USB_GPTIMER1LD_GPTLD_SHIFT) & USB_GPTIMER1LD_GPTLD_MASK) +#define USB_GPTIMER1LD_GPTLD_GET(x) (((uint32_t)(x) & USB_GPTIMER1LD_GPTLD_MASK) >> USB_GPTIMER1LD_GPTLD_SHIFT) + +/* Bitfield definition for register: GPTIMER1CTRL */ +/* + * GPTRUN (RW) + * + * GPTRUN + * General Purpose Timer Run + * GPTCNT bits are not effected when setting or clearing this bit. + * 0 - Stop counting + * 1 - Run + */ +#define USB_GPTIMER1CTRL_GPTRUN_MASK (0x80000000UL) +#define USB_GPTIMER1CTRL_GPTRUN_SHIFT (31U) +#define USB_GPTIMER1CTRL_GPTRUN_SET(x) (((uint32_t)(x) << USB_GPTIMER1CTRL_GPTRUN_SHIFT) & USB_GPTIMER1CTRL_GPTRUN_MASK) +#define USB_GPTIMER1CTRL_GPTRUN_GET(x) (((uint32_t)(x) & USB_GPTIMER1CTRL_GPTRUN_MASK) >> USB_GPTIMER1CTRL_GPTRUN_SHIFT) + +/* + * GPTRST (WO) + * + * GPTRST + * General Purpose Timer Reset + * 0 - No action + * 1 - Load counter value from GPTLD bits in USB_n_GPTIMER1LD + */ +#define USB_GPTIMER1CTRL_GPTRST_MASK (0x40000000UL) +#define USB_GPTIMER1CTRL_GPTRST_SHIFT (30U) +#define USB_GPTIMER1CTRL_GPTRST_SET(x) (((uint32_t)(x) << USB_GPTIMER1CTRL_GPTRST_SHIFT) & USB_GPTIMER1CTRL_GPTRST_MASK) +#define USB_GPTIMER1CTRL_GPTRST_GET(x) (((uint32_t)(x) & USB_GPTIMER1CTRL_GPTRST_MASK) >> USB_GPTIMER1CTRL_GPTRST_SHIFT) + +/* + * GPTMODE (RW) + * + * GPTMODE + * General Purpose Timer Mode + * In one shot mode, the timer will count down to zero, generate an interrupt, and stop until the counter is + * reset by software. In repeat mode, the timer will count down to zero, generate an interrupt and + * automatically reload the counter value from GPTLD bits to start again. + * 0 - One Shot Mode + * 1 - Repeat Mode + */ +#define USB_GPTIMER1CTRL_GPTMODE_MASK (0x1000000UL) +#define USB_GPTIMER1CTRL_GPTMODE_SHIFT (24U) +#define USB_GPTIMER1CTRL_GPTMODE_SET(x) (((uint32_t)(x) << USB_GPTIMER1CTRL_GPTMODE_SHIFT) & USB_GPTIMER1CTRL_GPTMODE_MASK) +#define USB_GPTIMER1CTRL_GPTMODE_GET(x) (((uint32_t)(x) & USB_GPTIMER1CTRL_GPTMODE_MASK) >> USB_GPTIMER1CTRL_GPTMODE_SHIFT) + +/* + * GPTCNT (RO) + * + * GPTCNT + * General Purpose Timer Counter. + * This field is the count value of the countdown timer. + */ +#define USB_GPTIMER1CTRL_GPTCNT_MASK (0xFFFFFFUL) +#define USB_GPTIMER1CTRL_GPTCNT_SHIFT (0U) +#define USB_GPTIMER1CTRL_GPTCNT_GET(x) (((uint32_t)(x) & USB_GPTIMER1CTRL_GPTCNT_MASK) >> USB_GPTIMER1CTRL_GPTCNT_SHIFT) + +/* Bitfield definition for register: SBUSCFG */ +/* + * AHBBRST (RW) + * + * AHBBRST + * AHB master interface Burst configuration + * These bits control AHB master transfer type sequence (or priority). + * NOTE: This register overrides n_BURSTSIZE register when its value is not zero. + * 000 - Incremental burst of unspecified length only + * 001 - INCR4 burst, then single transfer + * 010 - INCR8 burst, INCR4 burst, then single transfer + * 011 - INCR16 burst, INCR8 burst, INCR4 burst, then single transfer + * 100 - Reserved, don't use + * 101 - INCR4 burst, then incremental burst of unspecified length + * 110 - INCR8 burst, INCR4 burst, then incremental burst of unspecified length + * 111 - INCR16 burst, INCR8 burst, INCR4 burst, then incremental burst of unspecified length + */ +#define USB_SBUSCFG_AHBBRST_MASK (0x7U) +#define USB_SBUSCFG_AHBBRST_SHIFT (0U) +#define USB_SBUSCFG_AHBBRST_SET(x) (((uint32_t)(x) << USB_SBUSCFG_AHBBRST_SHIFT) & USB_SBUSCFG_AHBBRST_MASK) +#define USB_SBUSCFG_AHBBRST_GET(x) (((uint32_t)(x) & USB_SBUSCFG_AHBBRST_MASK) >> USB_SBUSCFG_AHBBRST_SHIFT) + +/* Bitfield definition for register: USBCMD */ +/* + * ITC (RW) + * + * ITC + * Interrupt Threshold Control -Read/Write. + * The system software uses this field to set the maximum rate at which the host/device controller will issue interrupts. + * ITC contains the maximum interrupt interval measured in micro-frames. Valid values are + * shown below. + * Value Maximum Interrupt Interval + * 00000000 - Immediate (no threshold) + * 00000001 - 1 micro-frame + * 00000010 - 2 micro-frames + * 00000100 - 4 micro-frames + * 00001000 - 8 micro-frames + * 00010000 - 16 micro-frames + * 00100000 - 32 micro-frames + * 01000000 - 64 micro-frames + */ +#define USB_USBCMD_ITC_MASK (0xFF0000UL) +#define USB_USBCMD_ITC_SHIFT (16U) +#define USB_USBCMD_ITC_SET(x) (((uint32_t)(x) << USB_USBCMD_ITC_SHIFT) & USB_USBCMD_ITC_MASK) +#define USB_USBCMD_ITC_GET(x) (((uint32_t)(x) & USB_USBCMD_ITC_MASK) >> USB_USBCMD_ITC_SHIFT) + +/* + * FS_2 (RW) + * + * FS_2 + * Frame List Size - (Read/Write or Read Only). [host mode only] + * This field is Read/Write only if Programmable Frame List Flag in the HCCPARAMS registers is set to one. + * This field specifies the size of the frame list that controls which bits in the Frame Index Register should be used for the Frame List Current index. + * NOTE: This field is made up from USBCMD bits 15, 3 and 2. + * Value Meaning + * 0b000 - 1024 elements (4096 bytes) Default value + * 0b001 - 512 elements (2048 bytes) + * 0b010 - 256 elements (1024 bytes) + * 0b011 - 128 elements (512 bytes) + * 0b100 - 64 elements (256 bytes) + * 0b101 - 32 elements (128 bytes) + * 0b110 - 16 elements (64 bytes) + * 0b111 - 8 elements (32 bytes) + */ +#define USB_USBCMD_FS_2_MASK (0x8000U) +#define USB_USBCMD_FS_2_SHIFT (15U) +#define USB_USBCMD_FS_2_SET(x) (((uint32_t)(x) << USB_USBCMD_FS_2_SHIFT) & USB_USBCMD_FS_2_MASK) +#define USB_USBCMD_FS_2_GET(x) (((uint32_t)(x) & USB_USBCMD_FS_2_MASK) >> USB_USBCMD_FS_2_SHIFT) + +/* + * ATDTW (RW) + * + * ATDTW + * Add dTD TripWire - Read/Write. [device mode only] + * This bit is used as a semaphore to ensure proper addition of a new dTD to an active (primed) endpoint's + * linked list. This bit is set and cleared by software. + * This bit would also be cleared by hardware when state machine is hazard region for which adding a dTD + * to a primed endpoint may go unrecognized. + */ +#define USB_USBCMD_ATDTW_MASK (0x4000U) +#define USB_USBCMD_ATDTW_SHIFT (14U) +#define USB_USBCMD_ATDTW_SET(x) (((uint32_t)(x) << USB_USBCMD_ATDTW_SHIFT) & USB_USBCMD_ATDTW_MASK) +#define USB_USBCMD_ATDTW_GET(x) (((uint32_t)(x) & USB_USBCMD_ATDTW_MASK) >> USB_USBCMD_ATDTW_SHIFT) + +/* + * SUTW (RW) + * + * SUTW + * Setup TripWire - Read/Write. [device mode only] + * This bit is used as a semaphore to ensure that the setup data payload of 8 bytes is extracted from a QH by the DCD without being corrupted. + * If the setup lockout mode is off (SLOM bit in USB core register n_USBMODE, see USBMODE ) then + * there is a hazard when new setup data arrives while the DCD is copying the setup data payload + * from the QH for a previous setup packet. This bit is set and cleared by software. + * This bit would also be cleared by hardware when a hazard detected. + */ +#define USB_USBCMD_SUTW_MASK (0x2000U) +#define USB_USBCMD_SUTW_SHIFT (13U) +#define USB_USBCMD_SUTW_SET(x) (((uint32_t)(x) << USB_USBCMD_SUTW_SHIFT) & USB_USBCMD_SUTW_MASK) +#define USB_USBCMD_SUTW_GET(x) (((uint32_t)(x) & USB_USBCMD_SUTW_MASK) >> USB_USBCMD_SUTW_SHIFT) + +/* + * ASPE (RW) + * + * ASPE + * Asynchronous Schedule Park Mode Enable - Read/Write. + * If the Asynchronous Park Capability bit in the HCCPARAMS register is a one, then this bit defaults to a 1h and is R/W. + * Otherwise the bit must be a zero and is RO. Software uses this bit to enable or disable Park mode. + * When this bit is one, Park mode is enabled. When this bit is a zero, Park mode is disabled. + * NOTE: ASPE bit reset value: '0b' for OTG controller . + */ +#define USB_USBCMD_ASPE_MASK (0x800U) +#define USB_USBCMD_ASPE_SHIFT (11U) +#define USB_USBCMD_ASPE_SET(x) (((uint32_t)(x) << USB_USBCMD_ASPE_SHIFT) & USB_USBCMD_ASPE_MASK) +#define USB_USBCMD_ASPE_GET(x) (((uint32_t)(x) & USB_USBCMD_ASPE_MASK) >> USB_USBCMD_ASPE_SHIFT) + +/* + * ASP (RW) + * + * ASP + * Asynchronous Schedule Park Mode Count - Read/Write. + * If the Asynchronous Park Capability bit in the HCCPARAMS register is a one, then this field defaults to 3h and is R/W. Otherwise it defaults to zero and is Read-Only. + * It contains a count of the number of successive transactions the host controller is allowed to + * execute from a high-speed queue head on the Asynchronous schedule before continuing traversal of the Asynchronous schedule. + * Valid values are 1h to 3h. Software must not write a zero to this bit when Park Mode Enable is a one as this will result in undefined behavior. + * This field is set to 3h in all controller core. + */ +#define USB_USBCMD_ASP_MASK (0x300U) +#define USB_USBCMD_ASP_SHIFT (8U) +#define USB_USBCMD_ASP_SET(x) (((uint32_t)(x) << USB_USBCMD_ASP_SHIFT) & USB_USBCMD_ASP_MASK) +#define USB_USBCMD_ASP_GET(x) (((uint32_t)(x) & USB_USBCMD_ASP_MASK) >> USB_USBCMD_ASP_SHIFT) + +/* + * IAA (RW) + * + * IAA + * Interrupt on Async Advance Doorbell - Read/Write. + * This bit is used as a doorbell by software to tell the host controller to issue an interrupt the next time it advances asynchronous schedule. Software must write a 1 to this bit to ring the doorbell. + * When the host controller has evicted all appropriate cached schedule states, + * it sets the Interrupt on Async Advance status bit in the USBSTS register. + * If the Interrupt on Sync Advance Enable bit in the USBINTR register is one, then the host controller will assert an interrupt at the next interrupt threshold. + * The host controller sets this bit to zero after it has set the Interrupt on Sync Advance status bit in the USBSTS register to one. + * Software should not write a one to this bit when the asynchronous schedule is inactive. Doing so will yield undefined results. + * This bit is only used in host mode. Writing a one to this bit when device mode is selected will have undefined results. + */ +#define USB_USBCMD_IAA_MASK (0x40U) +#define USB_USBCMD_IAA_SHIFT (6U) +#define USB_USBCMD_IAA_SET(x) (((uint32_t)(x) << USB_USBCMD_IAA_SHIFT) & USB_USBCMD_IAA_MASK) +#define USB_USBCMD_IAA_GET(x) (((uint32_t)(x) & USB_USBCMD_IAA_MASK) >> USB_USBCMD_IAA_SHIFT) + +/* + * ASE (RW) + * + * ASE + * Asynchronous Schedule Enable - Read/Write. Default 0b. + * This bit controls whether the host controller skips processing the Asynchronous Schedule. + * Only the host controller uses this bit. + * Values Meaning + * 0 - Do not process the Asynchronous Schedule. + * 1 - Use the ASYNCLISTADDR register to access the Asynchronous Schedule. + */ +#define USB_USBCMD_ASE_MASK (0x20U) +#define USB_USBCMD_ASE_SHIFT (5U) +#define USB_USBCMD_ASE_SET(x) (((uint32_t)(x) << USB_USBCMD_ASE_SHIFT) & USB_USBCMD_ASE_MASK) +#define USB_USBCMD_ASE_GET(x) (((uint32_t)(x) & USB_USBCMD_ASE_MASK) >> USB_USBCMD_ASE_SHIFT) + +/* + * PSE (RW) + * + * PSE + * Periodic Schedule Enable- Read/Write. Default 0b. + * This bit controls whether the host controller skips processing the Periodic Schedule. + * Only the host controller uses this bit. + * Values Meaning + * 0 - Do not process the Periodic Schedule + * 1 - Use the PERIODICLISTBASE register to access the Periodic Schedule. + */ +#define USB_USBCMD_PSE_MASK (0x10U) +#define USB_USBCMD_PSE_SHIFT (4U) +#define USB_USBCMD_PSE_SET(x) (((uint32_t)(x) << USB_USBCMD_PSE_SHIFT) & USB_USBCMD_PSE_MASK) +#define USB_USBCMD_PSE_GET(x) (((uint32_t)(x) & USB_USBCMD_PSE_MASK) >> USB_USBCMD_PSE_SHIFT) + +/* + * FS_1 (RW) + * + * FS_1 + * See description at bit 15 + */ +#define USB_USBCMD_FS_1_MASK (0xCU) +#define USB_USBCMD_FS_1_SHIFT (2U) +#define USB_USBCMD_FS_1_SET(x) (((uint32_t)(x) << USB_USBCMD_FS_1_SHIFT) & USB_USBCMD_FS_1_MASK) +#define USB_USBCMD_FS_1_GET(x) (((uint32_t)(x) & USB_USBCMD_FS_1_MASK) >> USB_USBCMD_FS_1_SHIFT) + +/* + * RST (RW) + * + * RST + * Controller Reset (RESET) - Read/Write. Software uses this bit to reset the controller. + * This bit is set to zero by the Host/Device Controller when the reset process is complete. Software cannot terminate the reset process early by writing a zero to this register. + * Host operation mode: + * When software writes a one to this bit, the Controller resets its internal pipelines, timers, counters, state machines etc. to their initial value. + * Any transaction currently in progress on USB is immediately terminated. A USB reset is not driven on downstream ports. + * Software should not set this bit to a one when the HCHalted bit in the USBSTS register is a zero. + * Attempting to reset an actively running host controller will result in undefined behavior. + * Device operation mode: + * When software writes a one to this bit, the Controller resets its internal pipelines, timers, counters, state machines etc. to their initial value. + * Writing a one to this bit when the device is in the attached state is not recommended, because the effect on an attached host is undefined. + * In order to ensure that the device is not in an attached state before initiating a device controller reset, all primed endpoints should be flushed and the USBCMD Run/Stop bit should be set to 0. + */ +#define USB_USBCMD_RST_MASK (0x2U) +#define USB_USBCMD_RST_SHIFT (1U) +#define USB_USBCMD_RST_SET(x) (((uint32_t)(x) << USB_USBCMD_RST_SHIFT) & USB_USBCMD_RST_MASK) +#define USB_USBCMD_RST_GET(x) (((uint32_t)(x) & USB_USBCMD_RST_MASK) >> USB_USBCMD_RST_SHIFT) + +/* + * RS (RW) + * + * RS + * Run/Stop (RS) - Read/Write. Default 0b. 1=Run. 0=Stop. + * Host operation mode: + * When set to '1b', the Controller proceeds with the execution of the schedule. The Controller continues execution as long as this bit is set to a one. + * When this bit is set to 0, the Host Controller completes the current transaction on the USB and then halts. + * The HC Halted bit in the status register indicates when the Controller has finished the transaction and has entered the stopped state. + * Software should not write a one to this field unless the controller is in the Halted state (that is, HCHalted in the USBSTS register is a one). + * Device operation mode: + * Writing a one to this bit will cause the controller to enable a pull-up on D+ and initiate an attach event. + * This control bit is not directly connected to the pull-up enable, as the pull-up will become disabled upon transitioning into high-speed mode. + * Software should use this bit to prevent an attach event before the controller has been properly initialized. Writing a 0 to this will cause a detach event. + */ +#define USB_USBCMD_RS_MASK (0x1U) +#define USB_USBCMD_RS_SHIFT (0U) +#define USB_USBCMD_RS_SET(x) (((uint32_t)(x) << USB_USBCMD_RS_SHIFT) & USB_USBCMD_RS_MASK) +#define USB_USBCMD_RS_GET(x) (((uint32_t)(x) & USB_USBCMD_RS_MASK) >> USB_USBCMD_RS_SHIFT) + +/* Bitfield definition for register: USBSTS */ +/* + * TI1 (RWC) + * + * TI1 + * General Purpose Timer Interrupt 1(GPTINT1)--R/WC. + * This bit is set when the counter in the GPTIMER1CTRL register transitions to zero, writing a one to this + * bit will clear it. + */ +#define USB_USBSTS_TI1_MASK (0x2000000UL) +#define USB_USBSTS_TI1_SHIFT (25U) +#define USB_USBSTS_TI1_SET(x) (((uint32_t)(x) << USB_USBSTS_TI1_SHIFT) & USB_USBSTS_TI1_MASK) +#define USB_USBSTS_TI1_GET(x) (((uint32_t)(x) & USB_USBSTS_TI1_MASK) >> USB_USBSTS_TI1_SHIFT) + +/* + * TI0 (RWC) + * + * TI0 + * General Purpose Timer Interrupt 0(GPTINT0)--R/WC. + * This bit is set when the counter in the GPTIMER0CTRL register transitions to zero, writing a one to this + * bit clears it. + */ +#define USB_USBSTS_TI0_MASK (0x1000000UL) +#define USB_USBSTS_TI0_SHIFT (24U) +#define USB_USBSTS_TI0_SET(x) (((uint32_t)(x) << USB_USBSTS_TI0_SHIFT) & USB_USBSTS_TI0_MASK) +#define USB_USBSTS_TI0_GET(x) (((uint32_t)(x) & USB_USBSTS_TI0_MASK) >> USB_USBSTS_TI0_SHIFT) + +/* + * UPI (RWC) + * + * USB Host Periodic Interrupt – RWC. Default = 0b. + * This bit is set by the Host Controller when the cause of an interrupt is a completion of a USB transaction + * where the Transfer Descriptor (TD) has an interrupt on complete (IOC) bit set and the TD was from the periodic schedule. + * This bit is also set by the Host Controller when a short packet is detected and the packet is on the periodic schedule. + * A short packet is when the actual number of bytes received was less than expected. + * This bit is not used by the device controller and will always be zero. + */ +#define USB_USBSTS_UPI_MASK (0x80000UL) +#define USB_USBSTS_UPI_SHIFT (19U) +#define USB_USBSTS_UPI_SET(x) (((uint32_t)(x) << USB_USBSTS_UPI_SHIFT) & USB_USBSTS_UPI_MASK) +#define USB_USBSTS_UPI_GET(x) (((uint32_t)(x) & USB_USBSTS_UPI_MASK) >> USB_USBSTS_UPI_SHIFT) + +/* + * UAI (RWC) + * + * USB Host Asynchronous Interrupt – RWC. Default = 0b. + * This bit is set by the Host Controller when the cause of an interrupt is a completion of a USB transaction + * where the Transfer Descriptor (TD) has an interrupt on complete (IOC) bit set AND the TD was from the asynchronous schedule. + * This bit is also set by the Host when a short packet is detected and the packet is on the asynchronous schedule. + * A short packet is when the actual number of bytes received was less than expected. + * This bit is not used by the device controller and will always be zero + */ +#define USB_USBSTS_UAI_MASK (0x40000UL) +#define USB_USBSTS_UAI_SHIFT (18U) +#define USB_USBSTS_UAI_SET(x) (((uint32_t)(x) << USB_USBSTS_UAI_SHIFT) & USB_USBSTS_UAI_MASK) +#define USB_USBSTS_UAI_GET(x) (((uint32_t)(x) & USB_USBSTS_UAI_MASK) >> USB_USBSTS_UAI_SHIFT) + +/* + * NAKI (RO) + * + * NAKI + * NAK Interrupt Bit--RO. + * This bit is set by hardware when for a particular endpoint both the TX/RX Endpoint NAK bit and + * corresponding TX/RX Endpoint NAK Enable bit are set. This bit is automatically cleared by hardware + * when all Enabled TX/RX Endpoint NAK bits are cleared. + */ +#define USB_USBSTS_NAKI_MASK (0x10000UL) +#define USB_USBSTS_NAKI_SHIFT (16U) +#define USB_USBSTS_NAKI_GET(x) (((uint32_t)(x) & USB_USBSTS_NAKI_MASK) >> USB_USBSTS_NAKI_SHIFT) + +/* + * AS (RO) + * + * AS + * Asynchronous Schedule Status - Read Only. + * This bit reports the current real status of the Asynchronous Schedule. When set to zero the asynchronous schedule status is disabled and if set to one the status is enabled. + * The Host Controller is not required to immediately disable or enable the Asynchronous Schedule when software transitions the Asynchronous Schedule Enable bit in the USBCMD register. + * When this bit and the Asynchronous Schedule Enable bit are the same value, the Asynchronous Schedule is either enabled (1) or disabled (0). + * Only used in the host operation mode. + */ +#define USB_USBSTS_AS_MASK (0x8000U) +#define USB_USBSTS_AS_SHIFT (15U) +#define USB_USBSTS_AS_GET(x) (((uint32_t)(x) & USB_USBSTS_AS_MASK) >> USB_USBSTS_AS_SHIFT) + +/* + * PS (RO) + * + * PS + * Periodic Schedule Status - Read Only. + * This bit reports the current real status of the Periodic Schedule. When set to zero the periodic schedule is disabled, and if set to one the status is enabled. + * The Host Controller is not required to immediately disable or enable the Periodic Schedule when software transitions the Periodic Schedule Enable bit in the USBCMD register. + * When this bit and the Periodic Schedule Enable bit are the same value, the Periodic Schedule is either enabled (1) or disabled (0). + * Only used in the host operation mode. + */ +#define USB_USBSTS_PS_MASK (0x4000U) +#define USB_USBSTS_PS_SHIFT (14U) +#define USB_USBSTS_PS_GET(x) (((uint32_t)(x) & USB_USBSTS_PS_MASK) >> USB_USBSTS_PS_SHIFT) + +/* + * RCL (RO) + * + * RCL + * Reclamation - Read Only. + * This is a read-only status bit used to detect an empty asynchronous schedule. + * Only used in the host operation mode. + */ +#define USB_USBSTS_RCL_MASK (0x2000U) +#define USB_USBSTS_RCL_SHIFT (13U) +#define USB_USBSTS_RCL_GET(x) (((uint32_t)(x) & USB_USBSTS_RCL_MASK) >> USB_USBSTS_RCL_SHIFT) + +/* + * HCH (RO) + * + * HCH + * HCHaIted - Read Only. + * This bit is a zero whenever the Run/Stop bit is a one. + * The Controller sets this bit to one after it has stopped executing because of the Run/Stop bit being set to 0, + * either by software or by the Controller hardware (for example, an internal error). + * Only used in the host operation mode. + * Default value is '0b' for OTG core . + * This is because OTG core is not operating as host in default. Please see CM bit in USB_n_USBMODE + * register. + * NOTE: HCH bit reset value: '0b' for OTG controller core . + */ +#define USB_USBSTS_HCH_MASK (0x1000U) +#define USB_USBSTS_HCH_SHIFT (12U) +#define USB_USBSTS_HCH_GET(x) (((uint32_t)(x) & USB_USBSTS_HCH_MASK) >> USB_USBSTS_HCH_SHIFT) + +/* + * SLI (RWC) + * + * SLI + * DCSuspend - R/WC. + * When a controller enters a suspend state from an active state, this bit will be set to a one. The device controller clears the bit upon exiting from a suspend state. + * Only used in device operation mode. + */ +#define USB_USBSTS_SLI_MASK (0x100U) +#define USB_USBSTS_SLI_SHIFT (8U) +#define USB_USBSTS_SLI_SET(x) (((uint32_t)(x) << USB_USBSTS_SLI_SHIFT) & USB_USBSTS_SLI_MASK) +#define USB_USBSTS_SLI_GET(x) (((uint32_t)(x) & USB_USBSTS_SLI_MASK) >> USB_USBSTS_SLI_SHIFT) + +/* + * SRI (RWC) + * + * SRI + * SOF Received - R/WC. + * When the device controller detects a Start Of (micro) Frame, this bit will be set to a one. + * When a SOF is extremely late, the device controller will automatically set this bit to indicate that an SOF was expected. + * Therefore, this bit will be set roughly every 1ms in device FS mode and every 125ms in HS mode and will be synchronized to the actual SOF that is received. + * Because the device controller is initialized to FS before connect, this bit will be set at an interval of 1ms during the prelude to connect and chirp. + * In host mode, this bit will be set every 125us and can be used by host controller driver as a time base. + * Software writes a 1 to this bit to clear it. + */ +#define USB_USBSTS_SRI_MASK (0x80U) +#define USB_USBSTS_SRI_SHIFT (7U) +#define USB_USBSTS_SRI_SET(x) (((uint32_t)(x) << USB_USBSTS_SRI_SHIFT) & USB_USBSTS_SRI_MASK) +#define USB_USBSTS_SRI_GET(x) (((uint32_t)(x) & USB_USBSTS_SRI_MASK) >> USB_USBSTS_SRI_SHIFT) + +/* + * URI (RWC) + * + * URI + * USB Reset Received - R/WC. + * When the device controller detects a USB Reset and enters the default state, this bit will be set to a one. + * Software can write a 1 to this bit to clear the USB Reset Received status bit. + * Only used in device operation mode. + */ +#define USB_USBSTS_URI_MASK (0x40U) +#define USB_USBSTS_URI_SHIFT (6U) +#define USB_USBSTS_URI_SET(x) (((uint32_t)(x) << USB_USBSTS_URI_SHIFT) & USB_USBSTS_URI_MASK) +#define USB_USBSTS_URI_GET(x) (((uint32_t)(x) & USB_USBSTS_URI_MASK) >> USB_USBSTS_URI_SHIFT) + +/* + * AAI (RWC) + * + * AAI + * Interrupt on Async Advance - R/WC. + * System software can force the host controller to issue an interrupt the next time the host controller advances the asynchronous schedule + * by writing a one to the Interrupt on Async Advance Doorbell bit in the n_USBCMD register. This status bit indicates the assertion of that interrupt source. + * Only used in host operation mode. + */ +#define USB_USBSTS_AAI_MASK (0x20U) +#define USB_USBSTS_AAI_SHIFT (5U) +#define USB_USBSTS_AAI_SET(x) (((uint32_t)(x) << USB_USBSTS_AAI_SHIFT) & USB_USBSTS_AAI_MASK) +#define USB_USBSTS_AAI_GET(x) (((uint32_t)(x) & USB_USBSTS_AAI_MASK) >> USB_USBSTS_AAI_SHIFT) + +/* + * SEI (RWC) + * + * System Error – RWC. Default = 0b. + * In the BVCI implementation of the USBHS core, this bit is not used, and will always be cleared to '0b'. + * In the AMBA implementation, this bit will be set to '1b' when an Error response is seen by the master interface (HRESP[1:0]=ERROR) + */ +#define USB_USBSTS_SEI_MASK (0x10U) +#define USB_USBSTS_SEI_SHIFT (4U) +#define USB_USBSTS_SEI_SET(x) (((uint32_t)(x) << USB_USBSTS_SEI_SHIFT) & USB_USBSTS_SEI_MASK) +#define USB_USBSTS_SEI_GET(x) (((uint32_t)(x) & USB_USBSTS_SEI_MASK) >> USB_USBSTS_SEI_SHIFT) + +/* + * FRI (RWC) + * + * FRI + * Frame List Rollover - R/WC. + * The Host Controller sets this bit to a one when the Frame List Index rolls over from its maximum value to + * zero. The exact value at which the rollover occurs depends on the frame list size. For example. If the + * frame list size (as programmed in the Frame List Size field of the USB_n_USBCMD register) is 1024, the + * Frame Index Register rolls over every time FRINDEX [13] toggles. Similarly, if the size is 512, the Host + * Controller sets this bit to a one every time FHINDEX [12] toggles. + * Only used in host operation mode. + */ +#define USB_USBSTS_FRI_MASK (0x8U) +#define USB_USBSTS_FRI_SHIFT (3U) +#define USB_USBSTS_FRI_SET(x) (((uint32_t)(x) << USB_USBSTS_FRI_SHIFT) & USB_USBSTS_FRI_MASK) +#define USB_USBSTS_FRI_GET(x) (((uint32_t)(x) & USB_USBSTS_FRI_MASK) >> USB_USBSTS_FRI_SHIFT) + +/* + * PCI (RWC) + * + * PCI + * Port Change Detect - R/WC. + * The Host Controller sets this bit to a one when on any port a Connect Status occurs, a Port Enable/Disable Change occurs, + * or the Force Port Resume bit is set as the result of a J-K transition on the suspended port. + * The Device Controller sets this bit to a one when the port controller enters the full or high-speed operational state. + * When the port controller exits the full or high-speed operation states due to Reset or Suspend events, + * the notification mechanisms are the USB Reset Received bit and the DCSuspend bits Respectively. + */ +#define USB_USBSTS_PCI_MASK (0x4U) +#define USB_USBSTS_PCI_SHIFT (2U) +#define USB_USBSTS_PCI_SET(x) (((uint32_t)(x) << USB_USBSTS_PCI_SHIFT) & USB_USBSTS_PCI_MASK) +#define USB_USBSTS_PCI_GET(x) (((uint32_t)(x) & USB_USBSTS_PCI_MASK) >> USB_USBSTS_PCI_SHIFT) + +/* + * UEI (RWC) + * + * UEI + * USB Error Interrupt (USBERRINT) - R/WC. + * When completion of a USB transaction results in an error condition, this bit is set by the Host/Device Controller. + * This bit is set along with the USBINT bit, if the TD on which the error interrupt occurred also had its interrupt on complete (IOC) bit set. + */ +#define USB_USBSTS_UEI_MASK (0x2U) +#define USB_USBSTS_UEI_SHIFT (1U) +#define USB_USBSTS_UEI_SET(x) (((uint32_t)(x) << USB_USBSTS_UEI_SHIFT) & USB_USBSTS_UEI_MASK) +#define USB_USBSTS_UEI_GET(x) (((uint32_t)(x) & USB_USBSTS_UEI_MASK) >> USB_USBSTS_UEI_SHIFT) + +/* + * UI (RWC) + * + * UI + * USB Interrupt (USBINT) - R/WC. + * This bit is set by the Host/Device Controller when the cause of an interrupt is a completion of a USB + * transaction where the Transfer Descriptor (TD) has an interrupt on complete (IOC) bit set. + * This bit is also set by the Host/Device Controller when a short packet is detected. A short packet is when + * the actual number of bytes received was less than the expected number of bytes. + */ +#define USB_USBSTS_UI_MASK (0x1U) +#define USB_USBSTS_UI_SHIFT (0U) +#define USB_USBSTS_UI_SET(x) (((uint32_t)(x) << USB_USBSTS_UI_SHIFT) & USB_USBSTS_UI_MASK) +#define USB_USBSTS_UI_GET(x) (((uint32_t)(x) & USB_USBSTS_UI_MASK) >> USB_USBSTS_UI_SHIFT) + +/* Bitfield definition for register: USBINTR */ +/* + * TIE1 (RW) + * + * TIE1 + * General Purpose Timer #1 Interrupt Enable + * When this bit is one and the TI1 bit in n_USBSTS register is a one the controller will issue an interrupt. + */ +#define USB_USBINTR_TIE1_MASK (0x2000000UL) +#define USB_USBINTR_TIE1_SHIFT (25U) +#define USB_USBINTR_TIE1_SET(x) (((uint32_t)(x) << USB_USBINTR_TIE1_SHIFT) & USB_USBINTR_TIE1_MASK) +#define USB_USBINTR_TIE1_GET(x) (((uint32_t)(x) & USB_USBINTR_TIE1_MASK) >> USB_USBINTR_TIE1_SHIFT) + +/* + * TIE0 (RW) + * + * TIE0 + * General Purpose Timer #0 Interrupt Enable + * When this bit is one and the TI0 bit in n_USBSTS register is a one the controller will issue an interrupt. + */ +#define USB_USBINTR_TIE0_MASK (0x1000000UL) +#define USB_USBINTR_TIE0_SHIFT (24U) +#define USB_USBINTR_TIE0_SET(x) (((uint32_t)(x) << USB_USBINTR_TIE0_SHIFT) & USB_USBINTR_TIE0_MASK) +#define USB_USBINTR_TIE0_GET(x) (((uint32_t)(x) & USB_USBINTR_TIE0_MASK) >> USB_USBINTR_TIE0_SHIFT) + +/* + * UPIE (RW) + * + * UPIE + * USB Host Periodic Interrupt Enable + * When this bit is one, and the UPI bit in the n_USBSTS register is one, host controller will issue an + * interrupt at the next interrupt threshold. + */ +#define USB_USBINTR_UPIE_MASK (0x80000UL) +#define USB_USBINTR_UPIE_SHIFT (19U) +#define USB_USBINTR_UPIE_SET(x) (((uint32_t)(x) << USB_USBINTR_UPIE_SHIFT) & USB_USBINTR_UPIE_MASK) +#define USB_USBINTR_UPIE_GET(x) (((uint32_t)(x) & USB_USBINTR_UPIE_MASK) >> USB_USBINTR_UPIE_SHIFT) + +/* + * UAIE (RW) + * + * UAIE + * USB Host Asynchronous Interrupt Enable + * When this bit is one, and the UAI bit in the n_USBSTS register is one, host controller will issue an + * interrupt at the next interrupt threshold. + */ +#define USB_USBINTR_UAIE_MASK (0x40000UL) +#define USB_USBINTR_UAIE_SHIFT (18U) +#define USB_USBINTR_UAIE_SET(x) (((uint32_t)(x) << USB_USBINTR_UAIE_SHIFT) & USB_USBINTR_UAIE_MASK) +#define USB_USBINTR_UAIE_GET(x) (((uint32_t)(x) & USB_USBINTR_UAIE_MASK) >> USB_USBINTR_UAIE_SHIFT) + +/* + * NAKE (RO) + * + * NAKE + * NAK Interrupt Enable + * When this bit is one and the NAKI bit in n_USBSTS register is a one the controller will issue an interrupt. + */ +#define USB_USBINTR_NAKE_MASK (0x10000UL) +#define USB_USBINTR_NAKE_SHIFT (16U) +#define USB_USBINTR_NAKE_GET(x) (((uint32_t)(x) & USB_USBINTR_NAKE_MASK) >> USB_USBINTR_NAKE_SHIFT) + +/* + * SLE (RW) + * + * SLE + * Sleep Interrupt Enable + * When this bit is one and the SLI bit in n_n_USBSTS register is a one the controller will issue an interrupt. + * Only used in device operation mode. + */ +#define USB_USBINTR_SLE_MASK (0x100U) +#define USB_USBINTR_SLE_SHIFT (8U) +#define USB_USBINTR_SLE_SET(x) (((uint32_t)(x) << USB_USBINTR_SLE_SHIFT) & USB_USBINTR_SLE_MASK) +#define USB_USBINTR_SLE_GET(x) (((uint32_t)(x) & USB_USBINTR_SLE_MASK) >> USB_USBINTR_SLE_SHIFT) + +/* + * SRE (RW) + * + * SRE + * SOF Received Interrupt Enable + * When this bit is one and the SRI bit in n_USBSTS register is a one the controller will issue an interrupt. + */ +#define USB_USBINTR_SRE_MASK (0x80U) +#define USB_USBINTR_SRE_SHIFT (7U) +#define USB_USBINTR_SRE_SET(x) (((uint32_t)(x) << USB_USBINTR_SRE_SHIFT) & USB_USBINTR_SRE_MASK) +#define USB_USBINTR_SRE_GET(x) (((uint32_t)(x) & USB_USBINTR_SRE_MASK) >> USB_USBINTR_SRE_SHIFT) + +/* + * URE (RW) + * + * URE + * USB Reset Interrupt Enable + * When this bit is one and the URI bit in n_USBSTS register is a one the controller will issue an interrupt. + * Only used in device operation mode. + */ +#define USB_USBINTR_URE_MASK (0x40U) +#define USB_USBINTR_URE_SHIFT (6U) +#define USB_USBINTR_URE_SET(x) (((uint32_t)(x) << USB_USBINTR_URE_SHIFT) & USB_USBINTR_URE_MASK) +#define USB_USBINTR_URE_GET(x) (((uint32_t)(x) & USB_USBINTR_URE_MASK) >> USB_USBINTR_URE_SHIFT) + +/* + * AAE (RW) + * + * AAE + * Async Advance Interrupt Enable + * When this bit is one and the AAI bit in n_USBSTS register is a one the controller will issue an interrupt. + * Only used in host operation mode. + */ +#define USB_USBINTR_AAE_MASK (0x20U) +#define USB_USBINTR_AAE_SHIFT (5U) +#define USB_USBINTR_AAE_SET(x) (((uint32_t)(x) << USB_USBINTR_AAE_SHIFT) & USB_USBINTR_AAE_MASK) +#define USB_USBINTR_AAE_GET(x) (((uint32_t)(x) & USB_USBINTR_AAE_MASK) >> USB_USBINTR_AAE_SHIFT) + +/* + * SEE (RW) + * + * SEE + * System Error Interrupt Enable + * When this bit is one and the SEI bit in n_USBSTS register is a one the controller will issue an interrupt. + * Only used in host operation mode. + */ +#define USB_USBINTR_SEE_MASK (0x10U) +#define USB_USBINTR_SEE_SHIFT (4U) +#define USB_USBINTR_SEE_SET(x) (((uint32_t)(x) << USB_USBINTR_SEE_SHIFT) & USB_USBINTR_SEE_MASK) +#define USB_USBINTR_SEE_GET(x) (((uint32_t)(x) & USB_USBINTR_SEE_MASK) >> USB_USBINTR_SEE_SHIFT) + +/* + * FRE (RW) + * + * FRE + * Frame List Rollover Interrupt Enable + * When this bit is one and the FRI bit in n_USBSTS register is a one the controller will issue an interrupt. + * Only used in host operation mode. + */ +#define USB_USBINTR_FRE_MASK (0x8U) +#define USB_USBINTR_FRE_SHIFT (3U) +#define USB_USBINTR_FRE_SET(x) (((uint32_t)(x) << USB_USBINTR_FRE_SHIFT) & USB_USBINTR_FRE_MASK) +#define USB_USBINTR_FRE_GET(x) (((uint32_t)(x) & USB_USBINTR_FRE_MASK) >> USB_USBINTR_FRE_SHIFT) + +/* + * PCE (RW) + * + * PCE + * Port Change Detect Interrupt Enable + * When this bit is one and the PCI bit in n_USBSTS register is a one the controller will issue an interrupt. + */ +#define USB_USBINTR_PCE_MASK (0x4U) +#define USB_USBINTR_PCE_SHIFT (2U) +#define USB_USBINTR_PCE_SET(x) (((uint32_t)(x) << USB_USBINTR_PCE_SHIFT) & USB_USBINTR_PCE_MASK) +#define USB_USBINTR_PCE_GET(x) (((uint32_t)(x) & USB_USBINTR_PCE_MASK) >> USB_USBINTR_PCE_SHIFT) + +/* + * UEE (RWC) + * + * UEE + * USB Error Interrupt Enable + * When this bit is one and the UEI bit in n_USBSTS register is a one the controller will issue an interrupt. + */ +#define USB_USBINTR_UEE_MASK (0x2U) +#define USB_USBINTR_UEE_SHIFT (1U) +#define USB_USBINTR_UEE_SET(x) (((uint32_t)(x) << USB_USBINTR_UEE_SHIFT) & USB_USBINTR_UEE_MASK) +#define USB_USBINTR_UEE_GET(x) (((uint32_t)(x) & USB_USBINTR_UEE_MASK) >> USB_USBINTR_UEE_SHIFT) + +/* + * UE (RW) + * + * UE + * USB Interrupt Enable + * When this bit is one and the UI bit in n_USBSTS register is a one the controller will issue an interrupt. + */ +#define USB_USBINTR_UE_MASK (0x1U) +#define USB_USBINTR_UE_SHIFT (0U) +#define USB_USBINTR_UE_SET(x) (((uint32_t)(x) << USB_USBINTR_UE_SHIFT) & USB_USBINTR_UE_MASK) +#define USB_USBINTR_UE_GET(x) (((uint32_t)(x) & USB_USBINTR_UE_MASK) >> USB_USBINTR_UE_SHIFT) + +/* Bitfield definition for register: FRINDEX */ +/* + * FRINDEX (RW) + * + * FRINDEX + * Frame Index. + * The value, in this register, increments at the end of each time frame (micro-frame). Bits [N: 3] are used for the Frame List current index. + * This means that each location of the frame list is accessed 8 times (frames or micro-frames) before moving to the next index. + * The following illustrates values of N based on the value of the Frame List Size field in the USBCMD register, when used in host mode. + * USBCMD [Frame List Size] Number Elements N + * In device mode the value is the current frame number of the last frame transmitted. It is not used as an index. + * In either mode bits 2:0 indicate the current microframe. + * The bit field values description below is represented as (Frame List Size) Number Elements N. + * 00000000000000 - (1024) 12 + * 00000000000001 - (512) 11 + * 00000000000010 - (256) 10 + * 00000000000011 - (128) 9 + * 00000000000100 - (64) 8 + * 00000000000101 - (32) 7 + * 00000000000110 - (16) 6 + * 00000000000111 - (8) 5 + */ +#define USB_FRINDEX_FRINDEX_MASK (0x3FFFU) +#define USB_FRINDEX_FRINDEX_SHIFT (0U) +#define USB_FRINDEX_FRINDEX_SET(x) (((uint32_t)(x) << USB_FRINDEX_FRINDEX_SHIFT) & USB_FRINDEX_FRINDEX_MASK) +#define USB_FRINDEX_FRINDEX_GET(x) (((uint32_t)(x) & USB_FRINDEX_FRINDEX_MASK) >> USB_FRINDEX_FRINDEX_SHIFT) + +/* Bitfield definition for register: DEVICEADDR */ +/* + * USBADR (RW) + * + * USBADR + * Device Address. + * These bits correspond to the USB device address + */ +#define USB_DEVICEADDR_USBADR_MASK (0xFE000000UL) +#define USB_DEVICEADDR_USBADR_SHIFT (25U) +#define USB_DEVICEADDR_USBADR_SET(x) (((uint32_t)(x) << USB_DEVICEADDR_USBADR_SHIFT) & USB_DEVICEADDR_USBADR_MASK) +#define USB_DEVICEADDR_USBADR_GET(x) (((uint32_t)(x) & USB_DEVICEADDR_USBADR_MASK) >> USB_DEVICEADDR_USBADR_SHIFT) + +/* + * USBADRA (RW) + * + * USBADRA + * Device Address Advance. Default=0. + * When this bit is '0', any writes to USBADR are instantaneous. + * When this bit is written to a '1' at the same time or before USBADR is written, the write to the USBADR field is staged and held in a hidden register. + * After an IN occurs on endpoint 0 and is ACKed, USBADR will be loaded from the holding register. + * Hardware will automatically clear this bit on the following conditions: + * 1) IN is ACKed to endpoint 0. (USBADR is updated from staging register). + * 2) OUT/SETUP occur to endpoint 0. (USBADR is not updated). + * 3) Device Reset occurs (USBADR is reset to 0). + * NOTE: After the status phase of the SET_ADDRESS descriptor, the DCD has 2 ms to program the USBADR field. + * This mechanism will ensure this specification is met when the DCD can not write of the device address within 2ms from the SET_ADDRESS status phase. + * If the DCD writes the USBADR with USBADRA=1 after the SET_ADDRESS data phase (before the prime of the status phase), + * the USBADR will be programmed instantly at the correct time and meet the 2ms USB requirement. + */ +#define USB_DEVICEADDR_USBADRA_MASK (0x1000000UL) +#define USB_DEVICEADDR_USBADRA_SHIFT (24U) +#define USB_DEVICEADDR_USBADRA_SET(x) (((uint32_t)(x) << USB_DEVICEADDR_USBADRA_SHIFT) & USB_DEVICEADDR_USBADRA_MASK) +#define USB_DEVICEADDR_USBADRA_GET(x) (((uint32_t)(x) & USB_DEVICEADDR_USBADRA_MASK) >> USB_DEVICEADDR_USBADRA_SHIFT) + +/* Bitfield definition for register: PERIODICLISTBASE */ +/* + * BASEADR (RW) + * + * BASEADR + * Base Address (Low). + * These bits correspond to memory address signals [31:12], respectively. + * Only used by the host controller. + */ +#define USB_PERIODICLISTBASE_BASEADR_MASK (0xFFFFF000UL) +#define USB_PERIODICLISTBASE_BASEADR_SHIFT (12U) +#define USB_PERIODICLISTBASE_BASEADR_SET(x) (((uint32_t)(x) << USB_PERIODICLISTBASE_BASEADR_SHIFT) & USB_PERIODICLISTBASE_BASEADR_MASK) +#define USB_PERIODICLISTBASE_BASEADR_GET(x) (((uint32_t)(x) & USB_PERIODICLISTBASE_BASEADR_MASK) >> USB_PERIODICLISTBASE_BASEADR_SHIFT) + +/* Bitfield definition for register: ASYNCLISTADDR */ +/* + * ASYBASE (RW) + * + * ASYBASE + * Link Pointer Low (LPL). + * These bits correspond to memory address signals [31:5], respectively. This field may only reference a + * Queue Head (QH). + * Only used by the host controller. + */ +#define USB_ASYNCLISTADDR_ASYBASE_MASK (0xFFFFFFE0UL) +#define USB_ASYNCLISTADDR_ASYBASE_SHIFT (5U) +#define USB_ASYNCLISTADDR_ASYBASE_SET(x) (((uint32_t)(x) << USB_ASYNCLISTADDR_ASYBASE_SHIFT) & USB_ASYNCLISTADDR_ASYBASE_MASK) +#define USB_ASYNCLISTADDR_ASYBASE_GET(x) (((uint32_t)(x) & USB_ASYNCLISTADDR_ASYBASE_MASK) >> USB_ASYNCLISTADDR_ASYBASE_SHIFT) + +/* Bitfield definition for register: ENDPTLISTADDR */ +/* + * EPBASE (RW) + * + * EPBASE + * Endpoint List Pointer(Low). These bits correspond to memory address signals [31:11], respectively. + * This field will reference a list of up to 32 Queue Head (QH) (that is, one queue head per endpoint & direction). + */ +#define USB_ENDPTLISTADDR_EPBASE_MASK (0xFFFFF800UL) +#define USB_ENDPTLISTADDR_EPBASE_SHIFT (11U) +#define USB_ENDPTLISTADDR_EPBASE_SET(x) (((uint32_t)(x) << USB_ENDPTLISTADDR_EPBASE_SHIFT) & USB_ENDPTLISTADDR_EPBASE_MASK) +#define USB_ENDPTLISTADDR_EPBASE_GET(x) (((uint32_t)(x) & USB_ENDPTLISTADDR_EPBASE_MASK) >> USB_ENDPTLISTADDR_EPBASE_SHIFT) + +/* Bitfield definition for register: BURSTSIZE */ +/* + * TXPBURST (RW) + * + * TXPBURST + * Programmable TX Burst Size. + * Default value is determined by TXBURST bits in n_HWTXBUF. + * This register represents the maximum length of a the burst in 32-bit words while moving data from system + * memory to the USB bus. + */ +#define USB_BURSTSIZE_TXPBURST_MASK (0xFF00U) +#define USB_BURSTSIZE_TXPBURST_SHIFT (8U) +#define USB_BURSTSIZE_TXPBURST_SET(x) (((uint32_t)(x) << USB_BURSTSIZE_TXPBURST_SHIFT) & USB_BURSTSIZE_TXPBURST_MASK) +#define USB_BURSTSIZE_TXPBURST_GET(x) (((uint32_t)(x) & USB_BURSTSIZE_TXPBURST_MASK) >> USB_BURSTSIZE_TXPBURST_SHIFT) + +/* + * RXPBURST (RW) + * + * RXPBURST + * Programmable RX Burst Size. + * Default value is determined by TXBURST bits in n_HWRXBUF. + * This register represents the maximum length of a the burst in 32-bit words while moving data from the + * USB bus to system memory. + */ +#define USB_BURSTSIZE_RXPBURST_MASK (0xFFU) +#define USB_BURSTSIZE_RXPBURST_SHIFT (0U) +#define USB_BURSTSIZE_RXPBURST_SET(x) (((uint32_t)(x) << USB_BURSTSIZE_RXPBURST_SHIFT) & USB_BURSTSIZE_RXPBURST_MASK) +#define USB_BURSTSIZE_RXPBURST_GET(x) (((uint32_t)(x) & USB_BURSTSIZE_RXPBURST_MASK) >> USB_BURSTSIZE_RXPBURST_SHIFT) + +/* Bitfield definition for register: TXFILLTUNING */ +/* + * TXFIFOTHRES (RW) + * + * TXFIFOTHRES + * FIFO Burst Threshold. (Read/Write) + * This register controls the number of data bursts that are posted to the TX latency FIFO in host mode before the packet begins on to the bus. + * The minimum value is 2 and this value should be a low as possible to maximize USB performance. + * A higher value can be used in systems with unpredictable latency and/or insufficient bandwidth + * where the FIFO may underrun because the data transferred from the latency FIFO to USB occurs before it can be replenished from system memory. + * This value is ignored if the Stream Disable bit in USB_n_USBMODE register is set. + */ +#define USB_TXFILLTUNING_TXFIFOTHRES_MASK (0x3F0000UL) +#define USB_TXFILLTUNING_TXFIFOTHRES_SHIFT (16U) +#define USB_TXFILLTUNING_TXFIFOTHRES_SET(x) (((uint32_t)(x) << USB_TXFILLTUNING_TXFIFOTHRES_SHIFT) & USB_TXFILLTUNING_TXFIFOTHRES_MASK) +#define USB_TXFILLTUNING_TXFIFOTHRES_GET(x) (((uint32_t)(x) & USB_TXFILLTUNING_TXFIFOTHRES_MASK) >> USB_TXFILLTUNING_TXFIFOTHRES_SHIFT) + +/* + * TXSCHHEALTH (RWC) + * + * TXSCHHEALTH + * Scheduler Health Counter. (Read/Write To Clear) + * Table continues on the next page + * This register increments when the host controller fails to fill the TX latency FIFO to the level programmed by TXFIFOTHRES + * before running out of time to send the packet before the next Start-Of-Frame. + * This health counter measures the number of times this occurs to provide feedback to selecting a proper TXSCHOH. + * Writing to this register will clear the counter and this counter will max. at 31. + */ +#define USB_TXFILLTUNING_TXSCHHEALTH_MASK (0x1F00U) +#define USB_TXFILLTUNING_TXSCHHEALTH_SHIFT (8U) +#define USB_TXFILLTUNING_TXSCHHEALTH_SET(x) (((uint32_t)(x) << USB_TXFILLTUNING_TXSCHHEALTH_SHIFT) & USB_TXFILLTUNING_TXSCHHEALTH_MASK) +#define USB_TXFILLTUNING_TXSCHHEALTH_GET(x) (((uint32_t)(x) & USB_TXFILLTUNING_TXSCHHEALTH_MASK) >> USB_TXFILLTUNING_TXSCHHEALTH_SHIFT) + +/* + * TXSCHOH (RW) + * + * TXSCHOH + * Scheduler Overhead. (Read/Write) [Default = 0] + * This register adds an additional fixed offset to the schedule time estimator described above as Tff. + * As an approximation, the value chosen for this register should limit the number of back-off events captured + * in the TXSCHHEALTH to less than 10 per second in a highly utilized bus. + * Choosing a value that is too high for this register is not desired as it can needlessly reduce USB utilization. + * The time unit represented in this register is 1.267us when a device is connected in High-Speed Mode. + * The time unit represented in this register is 6.333us when a device is connected in Low/Full Speed Mode. + * Default value is '08h' for OTG controller core . + */ +#define USB_TXFILLTUNING_TXSCHOH_MASK (0x7FU) +#define USB_TXFILLTUNING_TXSCHOH_SHIFT (0U) +#define USB_TXFILLTUNING_TXSCHOH_SET(x) (((uint32_t)(x) << USB_TXFILLTUNING_TXSCHOH_SHIFT) & USB_TXFILLTUNING_TXSCHOH_MASK) +#define USB_TXFILLTUNING_TXSCHOH_GET(x) (((uint32_t)(x) & USB_TXFILLTUNING_TXSCHOH_MASK) >> USB_TXFILLTUNING_TXSCHOH_SHIFT) + +/* Bitfield definition for register: ENDPTNAK */ +/* + * EPTN (RWC) + * + * EPTN + * TX Endpoint NAK - R/WC. + * Each TX endpoint has 1 bit in this field. The bit is set when the + * device sends a NAK handshake on a received IN token for the corresponding endpoint. + * Bit [N] - Endpoint #[N], N is 0-7 + */ +#define USB_ENDPTNAK_EPTN_MASK (0xFFFF0000UL) +#define USB_ENDPTNAK_EPTN_SHIFT (16U) +#define USB_ENDPTNAK_EPTN_SET(x) (((uint32_t)(x) << USB_ENDPTNAK_EPTN_SHIFT) & USB_ENDPTNAK_EPTN_MASK) +#define USB_ENDPTNAK_EPTN_GET(x) (((uint32_t)(x) & USB_ENDPTNAK_EPTN_MASK) >> USB_ENDPTNAK_EPTN_SHIFT) + +/* + * EPRN (RWC) + * + * EPRN + * RX Endpoint NAK - R/WC. + * Each RX endpoint has 1 bit in this field. The bit is set when the + * device sends a NAK handshake on a received OUT or PING token for the corresponding endpoint. + * Bit [N] - Endpoint #[N], N is 0-7 + */ +#define USB_ENDPTNAK_EPRN_MASK (0xFFFFU) +#define USB_ENDPTNAK_EPRN_SHIFT (0U) +#define USB_ENDPTNAK_EPRN_SET(x) (((uint32_t)(x) << USB_ENDPTNAK_EPRN_SHIFT) & USB_ENDPTNAK_EPRN_MASK) +#define USB_ENDPTNAK_EPRN_GET(x) (((uint32_t)(x) & USB_ENDPTNAK_EPRN_MASK) >> USB_ENDPTNAK_EPRN_SHIFT) + +/* Bitfield definition for register: ENDPTNAKEN */ +/* + * EPTNE (RW) + * + * EPTNE + * TX Endpoint NAK Enable - R/W. + * Each bit is an enable bit for the corresponding TX Endpoint NAK bit. If this bit is set and the + * corresponding TX Endpoint NAK bit is set, the NAK Interrupt bit is set. + * Bit [N] - Endpoint #[N], N is 0-7 + */ +#define USB_ENDPTNAKEN_EPTNE_MASK (0xFFFF0000UL) +#define USB_ENDPTNAKEN_EPTNE_SHIFT (16U) +#define USB_ENDPTNAKEN_EPTNE_SET(x) (((uint32_t)(x) << USB_ENDPTNAKEN_EPTNE_SHIFT) & USB_ENDPTNAKEN_EPTNE_MASK) +#define USB_ENDPTNAKEN_EPTNE_GET(x) (((uint32_t)(x) & USB_ENDPTNAKEN_EPTNE_MASK) >> USB_ENDPTNAKEN_EPTNE_SHIFT) + +/* + * EPRNE (RW) + * + * EPRNE + * RX Endpoint NAK Enable - R/W. + * Each bit is an enable bit for the corresponding RX Endpoint NAK bit. If this bit is set and the + * corresponding RX Endpoint NAK bit is set, the NAK Interrupt bit is set. + * Bit [N] - Endpoint #[N], N is 0-7 + */ +#define USB_ENDPTNAKEN_EPRNE_MASK (0xFFFFU) +#define USB_ENDPTNAKEN_EPRNE_SHIFT (0U) +#define USB_ENDPTNAKEN_EPRNE_SET(x) (((uint32_t)(x) << USB_ENDPTNAKEN_EPRNE_SHIFT) & USB_ENDPTNAKEN_EPRNE_MASK) +#define USB_ENDPTNAKEN_EPRNE_GET(x) (((uint32_t)(x) & USB_ENDPTNAKEN_EPRNE_MASK) >> USB_ENDPTNAKEN_EPRNE_SHIFT) + +/* Bitfield definition for register: PORTSC1 */ +/* + * STS (RW) + * + * STS + * Serial Transceiver Select + * 1 Serial Interface Engine is selected + * 0 Parallel Interface signals is selected + * Serial Interface Engine can be used in combination with UTMI+/ULPI physical interface to provide FS/LS signaling instead of the parallel interface signals. + * When this bit is set '1b', serial interface engine will be used instead of parallel interface signals. + */ +#define USB_PORTSC1_STS_MASK (0x20000000UL) +#define USB_PORTSC1_STS_SHIFT (29U) +#define USB_PORTSC1_STS_SET(x) (((uint32_t)(x) << USB_PORTSC1_STS_SHIFT) & USB_PORTSC1_STS_MASK) +#define USB_PORTSC1_STS_GET(x) (((uint32_t)(x) & USB_PORTSC1_STS_MASK) >> USB_PORTSC1_STS_SHIFT) + +/* + * PTW (RW) + * + * PTW + * Parallel Transceiver Width + * This bit has no effect if serial interface engine is used. + * 0 - Select the 8-bit UTMI interface [60MHz] + * 1 - Select the 16-bit UTMI interface [30MHz] + */ +#define USB_PORTSC1_PTW_MASK (0x10000000UL) +#define USB_PORTSC1_PTW_SHIFT (28U) +#define USB_PORTSC1_PTW_SET(x) (((uint32_t)(x) << USB_PORTSC1_PTW_SHIFT) & USB_PORTSC1_PTW_MASK) +#define USB_PORTSC1_PTW_GET(x) (((uint32_t)(x) & USB_PORTSC1_PTW_MASK) >> USB_PORTSC1_PTW_SHIFT) + +/* + * PSPD (RO) + * + * PSPD + * Port Speed - Read Only. + * This register field indicates the speed at which the port is operating. + * 00 - Full Speed + * 01 - Low Speed + * 10 - High Speed + * 11 - Undefined + */ +#define USB_PORTSC1_PSPD_MASK (0xC000000UL) +#define USB_PORTSC1_PSPD_SHIFT (26U) +#define USB_PORTSC1_PSPD_GET(x) (((uint32_t)(x) & USB_PORTSC1_PSPD_MASK) >> USB_PORTSC1_PSPD_SHIFT) + +/* + * PFSC (RW) + * + * PFSC + * Port Force Full Speed Connect - Read/Write. Default = 0b. + * When this bit is set to '1b', the port will be forced to only connect at Full Speed, It disables the chirp + * sequence that allows the port to identify itself as High Speed. + * 0 - Normal operation + * 1 - Forced to full speed + */ +#define USB_PORTSC1_PFSC_MASK (0x1000000UL) +#define USB_PORTSC1_PFSC_SHIFT (24U) +#define USB_PORTSC1_PFSC_SET(x) (((uint32_t)(x) << USB_PORTSC1_PFSC_SHIFT) & USB_PORTSC1_PFSC_MASK) +#define USB_PORTSC1_PFSC_GET(x) (((uint32_t)(x) & USB_PORTSC1_PFSC_MASK) >> USB_PORTSC1_PFSC_SHIFT) + +/* + * PHCD (RW) + * + * PHCD + * PHY Low Power Suspend - Clock Disable (PLPSCD) - Read/Write. Default = 0b. + * When this bit is set to '1b', the PHY clock is disabled. Reading this bit will indicate the status of the PHY + * clock. + * NOTE: The PHY clock cannot be disabled if it is being used as the system clock. + * In device mode, The PHY can be put into Low Power Suspend when the device is not running (USBCMD + * Run/Stop=0b) or the host has signalled suspend (PORTSC1 SUSPEND=1b). PHY Low power suspend + * will be cleared automatically when the host initials resume. Before forcing a resume from the device, the + * device controller driver must clear this bit. + * In host mode, the PHY can be put into Low Power Suspend when the downstream device has been put + * into suspend mode or when no downstream device is connected. Low power suspend is completely + * under the control of software. + * 0 - Enable PHY clock + * 1 - Disable PHY clock + */ +#define USB_PORTSC1_PHCD_MASK (0x800000UL) +#define USB_PORTSC1_PHCD_SHIFT (23U) +#define USB_PORTSC1_PHCD_SET(x) (((uint32_t)(x) << USB_PORTSC1_PHCD_SHIFT) & USB_PORTSC1_PHCD_MASK) +#define USB_PORTSC1_PHCD_GET(x) (((uint32_t)(x) & USB_PORTSC1_PHCD_MASK) >> USB_PORTSC1_PHCD_SHIFT) + +/* + * WKOC (RW) + * + * WKOC + * Wake on Over-current Enable (WKOC_E) - Read/Write. Default = 0b. + * Writing this bit to a one enables the port to be sensitive to over-current conditions as wake-up events. + * This field is zero if Port Power(PORTSC1) is zero. + */ +#define USB_PORTSC1_WKOC_MASK (0x400000UL) +#define USB_PORTSC1_WKOC_SHIFT (22U) +#define USB_PORTSC1_WKOC_SET(x) (((uint32_t)(x) << USB_PORTSC1_WKOC_SHIFT) & USB_PORTSC1_WKOC_MASK) +#define USB_PORTSC1_WKOC_GET(x) (((uint32_t)(x) & USB_PORTSC1_WKOC_MASK) >> USB_PORTSC1_WKOC_SHIFT) + +/* + * WKDC (RW) + * + * WKDC + * Wake on Disconnect Enable (WKDSCNNT_E) - Read/Write. Default=0b. Writing this bit to a one enables + * the port to be sensitive to device disconnects as wake-up events. + * This field is zero if Port Power(PORTSC1) is zero or in device mode. + */ +#define USB_PORTSC1_WKDC_MASK (0x200000UL) +#define USB_PORTSC1_WKDC_SHIFT (21U) +#define USB_PORTSC1_WKDC_SET(x) (((uint32_t)(x) << USB_PORTSC1_WKDC_SHIFT) & USB_PORTSC1_WKDC_MASK) +#define USB_PORTSC1_WKDC_GET(x) (((uint32_t)(x) & USB_PORTSC1_WKDC_MASK) >> USB_PORTSC1_WKDC_SHIFT) + +/* + * WKCN (RW) + * + * WKCN + * Wake on Connect Enable (WKCNNT_E) - Read/Write. Default=0b. + * Writing this bit to a one enables the port to be sensitive to device connects as wake-up events. + * This field is zero if Port Power(PORTSC1) is zero or in device mode. + */ +#define USB_PORTSC1_WKCN_MASK (0x100000UL) +#define USB_PORTSC1_WKCN_SHIFT (20U) +#define USB_PORTSC1_WKCN_SET(x) (((uint32_t)(x) << USB_PORTSC1_WKCN_SHIFT) & USB_PORTSC1_WKCN_MASK) +#define USB_PORTSC1_WKCN_GET(x) (((uint32_t)(x) & USB_PORTSC1_WKCN_MASK) >> USB_PORTSC1_WKCN_SHIFT) + +/* + * PTC (RW) + * + * PTC + * Port Test Control - Read/Write. Default = 0000b. + * Refer to Port Test Mode for the operational model for using these test modes and the USB Specification Revision 2.0, Chapter 7 for details on each test mode. + * The FORCE_ENABLE_FS and FORCE ENABLE_LS are extensions to the test mode support specified in the EHCI specification. + * Writing the PTC field to any of the FORCE_ENABLE_{HS/FS/LS} values will force the port into the connected and enabled state at the selected speed. + * Writing the PTC field back to TEST_MODE_DISABLE will allow the port state machines to progress normally from that point. + * NOTE: Low speed operations are not supported as a peripheral device. + * Any other value than zero indicates that the port is operating in test mode. + * Value Specific Test + * 0000 - TEST_MODE_DISABLE + * 0001 - J_STATE + * 0010 - K_STATE + * 0011 - SE0 (host) / NAK (device) + * 0100 - Packet + * 0101 - FORCE_ENABLE_HS + * 0110 - FORCE_ENABLE_FS + * 0111 - FORCE_ENABLE_LS + * 1000-1111 - Reserved + */ +#define USB_PORTSC1_PTC_MASK (0xF0000UL) +#define USB_PORTSC1_PTC_SHIFT (16U) +#define USB_PORTSC1_PTC_SET(x) (((uint32_t)(x) << USB_PORTSC1_PTC_SHIFT) & USB_PORTSC1_PTC_MASK) +#define USB_PORTSC1_PTC_GET(x) (((uint32_t)(x) & USB_PORTSC1_PTC_MASK) >> USB_PORTSC1_PTC_SHIFT) + +/* + * PP (RW) + * + * PP + * Port Power (PP)-Read/Write or Read Only. + * The function of this bit depends on the value of the Port Power Switching (PPC) field in the HCSPARAMS register. The behavior is as follows: + * PPC + * PP Operation + * 0 + * 1b Read Only - Host controller does not have port power control switches. Each port is hard-wired to power. + * 1 + * 1b/0b - Read/Write. OTG controller requires port power control switches. This bit represents the current setting of the switch (0=off, 1=on). + * When power is not available on a port (that is, PP equals a 0), the port is non-functional and will not report attaches, detaches, etc. + * When an over-current condition is detected on a powered port and PPC is a one, + * the PP bit in each affected port may be transitional by the host controller driver from a one to a zero (removing power from the port). + * This feature is implemented in all controller cores (PPC = 1). + */ +#define USB_PORTSC1_PP_MASK (0x1000U) +#define USB_PORTSC1_PP_SHIFT (12U) +#define USB_PORTSC1_PP_SET(x) (((uint32_t)(x) << USB_PORTSC1_PP_SHIFT) & USB_PORTSC1_PP_MASK) +#define USB_PORTSC1_PP_GET(x) (((uint32_t)(x) & USB_PORTSC1_PP_MASK) >> USB_PORTSC1_PP_SHIFT) + +/* + * LS (RO) + * + * LS + * Line Status-Read Only. These bits reflect the current logical levels of the D+ (bit 11) and D- (bit 10) signal + * lines. + * In host mode, the use of linestate by the host controller driver is not necessary (unlike EHCI), because + * the port controller state machine and the port routing manage the connection of LS and FS. + * In device mode, the use of linestate by the device controller driver is not necessary. + * The encoding of the bits are: + * Bits [11:10] Meaning + * 00 - SE0 + * 01 - K-state + * 10 - J-state + * 11 - Undefined + */ +#define USB_PORTSC1_LS_MASK (0xC00U) +#define USB_PORTSC1_LS_SHIFT (10U) +#define USB_PORTSC1_LS_GET(x) (((uint32_t)(x) & USB_PORTSC1_LS_MASK) >> USB_PORTSC1_LS_SHIFT) + +/* + * HSP (RO) + * + * HSP + * High-Speed Port - Read Only. Default = 0b. + * When the bit is one, the host/device connected to the port is in high-speed mode and if set to zero, the + * host/device connected to the port is not in a high-speed mode. + * NOTE: HSP is redundant with PSPD(bit 27, 26) but remained for compatibility. + */ +#define USB_PORTSC1_HSP_MASK (0x200U) +#define USB_PORTSC1_HSP_SHIFT (9U) +#define USB_PORTSC1_HSP_GET(x) (((uint32_t)(x) & USB_PORTSC1_HSP_MASK) >> USB_PORTSC1_HSP_SHIFT) + +/* + * PR (RW) + * + * PR + * Port Reset - Read/Write or Read Only. Default = 0b. + * In Host Mode: Read/Write. 1=Port is in Reset. 0=Port is not in Reset. Default 0. + * When software writes a one to this bit the bus-reset sequence as defined in the USB Specification Revision 2.0 is started. + * This bit will automatically change to zero after the reset sequence is complete. + * This behavior is different from EHCI where the host controller driver is required to set this bit to a zero after the reset duration is timed in the driver. + * In Device Mode: This bit is a read only status bit. Device reset from the USB bus is also indicated in the USBSTS register. + */ +#define USB_PORTSC1_PR_MASK (0x100U) +#define USB_PORTSC1_PR_SHIFT (8U) +#define USB_PORTSC1_PR_SET(x) (((uint32_t)(x) << USB_PORTSC1_PR_SHIFT) & USB_PORTSC1_PR_MASK) +#define USB_PORTSC1_PR_GET(x) (((uint32_t)(x) & USB_PORTSC1_PR_MASK) >> USB_PORTSC1_PR_SHIFT) + +/* + * SUSP (RW) + * + * SUSP + * Suspend - Read/Write or Read Only. Default = 0b. + * 1=Port in suspend state. 0=Port not in suspend state. + * In Host Mode: Read/Write. + * Port Enabled Bit and Suspend bit of this register define the port states as follows: + * Bits [Port Enabled, Suspend] Port State + * 0x Disable + * 10 Enable + * 11 Suspend + * When in suspend state, downstream propagation of data is blocked on this port, except for port reset. + * The blocking occurs at the end of the current transaction if a transaction was in progress when this bit was written to 1. + * In the suspend state, the port is sensitive to resume detection. + * Note that the bit status does not change until the port is suspended and that there may be a delay in suspending a port if there is a transaction currently in progress on the USB. + * The host controller will unconditionally set this bit to zero when software sets the Force Port Resume bit to zero. The host controller ignores a write of zero to this bit. + * If host software sets this bit to a one when the port is not enabled (that is, Port enabled bit is a zero) the results are undefined. + * This field is zero if Port Power(PORTSC1) is zero in host mode. + * In Device Mode: Read Only. + * In device mode this bit is a read only status bit. + */ +#define USB_PORTSC1_SUSP_MASK (0x80U) +#define USB_PORTSC1_SUSP_SHIFT (7U) +#define USB_PORTSC1_SUSP_SET(x) (((uint32_t)(x) << USB_PORTSC1_SUSP_SHIFT) & USB_PORTSC1_SUSP_MASK) +#define USB_PORTSC1_SUSP_GET(x) (((uint32_t)(x) & USB_PORTSC1_SUSP_MASK) >> USB_PORTSC1_SUSP_SHIFT) + +/* + * FPR (RW) + * + * FPR + * Force Port Resume -Read/Write. 1= Resume detected/driven on port. 0=No resume (K-state) detected driven on port. Default = 0. + * In Host Mode: + * Software sets this bit to one to drive resume signaling. The Host Controller sets this bit to one if a J-to-K transition is detected while the port is in the Suspend state. + * When this bit transitions to a one because a J-to-K transition is detected, the Port Change Detect bit in the USBSTS register is also set to one. + * This bit will automatically change to zero after the resume sequence is complete. + * This behavior is different from EHCI where the host controller driver is required to set this bit to a zero after the resume duration is timed in the driver. + * Note that when the Host controller owns the port, the resume sequence follows the defined sequence documented in the USB Specification Revision 2.0. + * The resume signaling (Full-speed 'K') is driven on the port as long as this bit remains a one. This bit will remain a one until the port has switched to the high-speed idle. + * Writing a zero has no effect because the port controller will time the resume operation, clear the bit the port control state switches to HS or FS idle. + * This field is zero if Port Power(PORTSC1) is zero in host mode. + * This bit is not-EHCI compatible. + * In Device mode: + * After the device has been in Suspend State for 5ms or more, software must set this bit to one to drive resume signaling before clearing. + * The Device Controller will set this bit to one if a J-to-K transition is detected while the port is in the Suspend state. + * The bit will be cleared when the device returns to normal operation. + * Also, when this bit wil be cleared because a K-to-J transition detected, the Port Change Detect bit in the USBSTS register is also set to one. + */ +#define USB_PORTSC1_FPR_MASK (0x40U) +#define USB_PORTSC1_FPR_SHIFT (6U) +#define USB_PORTSC1_FPR_SET(x) (((uint32_t)(x) << USB_PORTSC1_FPR_SHIFT) & USB_PORTSC1_FPR_MASK) +#define USB_PORTSC1_FPR_GET(x) (((uint32_t)(x) & USB_PORTSC1_FPR_MASK) >> USB_PORTSC1_FPR_SHIFT) + +/* + * OCC (RW) + * + * OCC + * Over-current Change-R/WC. Default=0. + * This bit is set '1b' by hardware when there is a change to Over-current Active. Software can clear this bit by writing a one to this bit position. + */ +#define USB_PORTSC1_OCC_MASK (0x20U) +#define USB_PORTSC1_OCC_SHIFT (5U) +#define USB_PORTSC1_OCC_SET(x) (((uint32_t)(x) << USB_PORTSC1_OCC_SHIFT) & USB_PORTSC1_OCC_MASK) +#define USB_PORTSC1_OCC_GET(x) (((uint32_t)(x) & USB_PORTSC1_OCC_MASK) >> USB_PORTSC1_OCC_SHIFT) + +/* + * OCA (RO) + * + * OCA + * Over-current Active-Read Only. Default 0. + * This bit will automatically transition from one to zero when the over current condition is removed. + * 0 - This port does not have an over-current condition. + * 1 - This port currently has an over-current condition + */ +#define USB_PORTSC1_OCA_MASK (0x10U) +#define USB_PORTSC1_OCA_SHIFT (4U) +#define USB_PORTSC1_OCA_GET(x) (((uint32_t)(x) & USB_PORTSC1_OCA_MASK) >> USB_PORTSC1_OCA_SHIFT) + +/* + * PEC (RWC) + * + * PEC + * Port Enable/Disable Change-R/WC. 1=Port enabled/disabled status has changed. 0=No change. Default = 0. + * In Host Mode: + * For the root hub, this bit is set to a one only when a port is disabled due to disconnect on the port or + * due to the appropriate conditions existing at the EOF2 point (See Chapter 11 of the USB Specification). + * Software clears this by writing a one to it. + * This field is zero if Port Power(PORTSC1) is zero. + * In Device mode: + * The device port is always enabled, so this bit is always '0b'. + */ +#define USB_PORTSC1_PEC_MASK (0x8U) +#define USB_PORTSC1_PEC_SHIFT (3U) +#define USB_PORTSC1_PEC_SET(x) (((uint32_t)(x) << USB_PORTSC1_PEC_SHIFT) & USB_PORTSC1_PEC_MASK) +#define USB_PORTSC1_PEC_GET(x) (((uint32_t)(x) & USB_PORTSC1_PEC_MASK) >> USB_PORTSC1_PEC_SHIFT) + +/* + * PE (RWC) + * + * PE + * Port Enabled/Disabled-Read/Write. 1=Enable. 0=Disable. Default 0. + * In Host Mode: + * Ports can only be enabled by the host controller as a part of the reset and enable. Software cannot enable a port by writing a one to this field. + * Ports can be disabled by either a fault condition (disconnect event or other fault condition) or by the host software. + * Note that the bit status does not change until the port state actually changes. There may be a delay in disabling or enabling a port due to other host controller and bus events. + * When the port is disabled, (0b) downstream propagation of data is blocked except for reset. + * This field is zero if Port Power(PORTSC1) is zero in host mode. + * In Device Mode: + * The device port is always enabled, so this bit is always '1b'. + */ +#define USB_PORTSC1_PE_MASK (0x4U) +#define USB_PORTSC1_PE_SHIFT (2U) +#define USB_PORTSC1_PE_SET(x) (((uint32_t)(x) << USB_PORTSC1_PE_SHIFT) & USB_PORTSC1_PE_MASK) +#define USB_PORTSC1_PE_GET(x) (((uint32_t)(x) & USB_PORTSC1_PE_MASK) >> USB_PORTSC1_PE_SHIFT) + +/* + * CSC (RWC) + * + * CSC + * Connect Status Change-R/WC. 1 =Change in Current Connect Status. 0=No change. Default 0. + * In Host Mode: + * Indicates a change has occurred in the port's Current Connect Status. + * The host/device controller sets this bit for all changes to the port device connect status, even if system software has not cleared an existing connect status change. + * For example, the insertion status changes twice before system software has cleared the changed condition, + * hub hardware will be 'setting' an already-set bit (that is, the bit will remain set). Software clears this bit by writing a one to it. + * This field is zero if Port Power(PORTSC1) is zero in host mode. + * In Device Mode: + * This bit is undefined in device controller mode. + */ +#define USB_PORTSC1_CSC_MASK (0x2U) +#define USB_PORTSC1_CSC_SHIFT (1U) +#define USB_PORTSC1_CSC_SET(x) (((uint32_t)(x) << USB_PORTSC1_CSC_SHIFT) & USB_PORTSC1_CSC_MASK) +#define USB_PORTSC1_CSC_GET(x) (((uint32_t)(x) & USB_PORTSC1_CSC_MASK) >> USB_PORTSC1_CSC_SHIFT) + +/* + * CCS (RWC) + * + * CCS + * Current Connect Status-Read Only. + * In Host Mode: + * 1=Device is present on port. 0=No device is present. Default = 0. + * This value reflects the current state of the port, and may not correspond directly to the event that caused the Connect Status Change bit (Bit 1) to be set. + * This field is zero if Port Power(PORTSC1) is zero in host mode. + * In Device Mode: + * 1=Attached. 0=Not Attached. Default=0. + * A one indicates that the device successfully attached and is operating in either high speed or full speed as indicated by the High Speed Port bit in this register. + * A zero indicates that the device did not attach successfully or was forcibly disconnected by the software writing a zero to the Run bit in the USBCMD register. + * It does not state the device being disconnected or Suspended. + */ +#define USB_PORTSC1_CCS_MASK (0x1U) +#define USB_PORTSC1_CCS_SHIFT (0U) +#define USB_PORTSC1_CCS_SET(x) (((uint32_t)(x) << USB_PORTSC1_CCS_SHIFT) & USB_PORTSC1_CCS_MASK) +#define USB_PORTSC1_CCS_GET(x) (((uint32_t)(x) & USB_PORTSC1_CCS_MASK) >> USB_PORTSC1_CCS_SHIFT) + +/* Bitfield definition for register: OTGSC */ +/* + * ASVIE (RW) + * + * ASVIE + * A Session Valid Interrupt Enable - Read/Write. + */ +#define USB_OTGSC_ASVIE_MASK (0x4000000UL) +#define USB_OTGSC_ASVIE_SHIFT (26U) +#define USB_OTGSC_ASVIE_SET(x) (((uint32_t)(x) << USB_OTGSC_ASVIE_SHIFT) & USB_OTGSC_ASVIE_MASK) +#define USB_OTGSC_ASVIE_GET(x) (((uint32_t)(x) & USB_OTGSC_ASVIE_MASK) >> USB_OTGSC_ASVIE_SHIFT) + +/* + * AVVIE (RW) + * + * AVVIE + * A VBus Valid Interrupt Enable - Read/Write. + * Setting this bit enables the A VBus valid interrupt. + */ +#define USB_OTGSC_AVVIE_MASK (0x2000000UL) +#define USB_OTGSC_AVVIE_SHIFT (25U) +#define USB_OTGSC_AVVIE_SET(x) (((uint32_t)(x) << USB_OTGSC_AVVIE_SHIFT) & USB_OTGSC_AVVIE_MASK) +#define USB_OTGSC_AVVIE_GET(x) (((uint32_t)(x) & USB_OTGSC_AVVIE_MASK) >> USB_OTGSC_AVVIE_SHIFT) + +/* + * IDIE (RW) + * + * IDIE + * USB ID Interrupt Enable - Read/Write. + * Setting this bit enables the USB ID interrupt. + */ +#define USB_OTGSC_IDIE_MASK (0x1000000UL) +#define USB_OTGSC_IDIE_SHIFT (24U) +#define USB_OTGSC_IDIE_SET(x) (((uint32_t)(x) << USB_OTGSC_IDIE_SHIFT) & USB_OTGSC_IDIE_MASK) +#define USB_OTGSC_IDIE_GET(x) (((uint32_t)(x) & USB_OTGSC_IDIE_MASK) >> USB_OTGSC_IDIE_SHIFT) + +/* + * ASVIS (RWC) + * + * ASVIS + * A Session Valid Interrupt Status - Read/Write to Clear. + * This bit is set when VBus has either risen above or fallen below the A session valid threshold. + * Software must write a one to clear this bit. + */ +#define USB_OTGSC_ASVIS_MASK (0x40000UL) +#define USB_OTGSC_ASVIS_SHIFT (18U) +#define USB_OTGSC_ASVIS_SET(x) (((uint32_t)(x) << USB_OTGSC_ASVIS_SHIFT) & USB_OTGSC_ASVIS_MASK) +#define USB_OTGSC_ASVIS_GET(x) (((uint32_t)(x) & USB_OTGSC_ASVIS_MASK) >> USB_OTGSC_ASVIS_SHIFT) + +/* + * AVVIS (RWC) + * + * AVVIS + * A VBus Valid Interrupt Status - Read/Write to Clear. + * This bit is set when VBus has either risen above or fallen below the VBus valid threshold on an A device. + * Software must write a one to clear this bit. + */ +#define USB_OTGSC_AVVIS_MASK (0x20000UL) +#define USB_OTGSC_AVVIS_SHIFT (17U) +#define USB_OTGSC_AVVIS_SET(x) (((uint32_t)(x) << USB_OTGSC_AVVIS_SHIFT) & USB_OTGSC_AVVIS_MASK) +#define USB_OTGSC_AVVIS_GET(x) (((uint32_t)(x) & USB_OTGSC_AVVIS_MASK) >> USB_OTGSC_AVVIS_SHIFT) + +/* + * IDIS (RWC) + * + * IDIS + * USB ID Interrupt Status - Read/Write. + * This bit is set when a change on the ID input has been detected. + * Software must write a one to clear this bit. + */ +#define USB_OTGSC_IDIS_MASK (0x10000UL) +#define USB_OTGSC_IDIS_SHIFT (16U) +#define USB_OTGSC_IDIS_SET(x) (((uint32_t)(x) << USB_OTGSC_IDIS_SHIFT) & USB_OTGSC_IDIS_MASK) +#define USB_OTGSC_IDIS_GET(x) (((uint32_t)(x) & USB_OTGSC_IDIS_MASK) >> USB_OTGSC_IDIS_SHIFT) + +/* + * ASV (RO) + * + * ASV + * A Session Valid - Read Only. + * Indicates VBus is above the A session valid threshold. + */ +#define USB_OTGSC_ASV_MASK (0x400U) +#define USB_OTGSC_ASV_SHIFT (10U) +#define USB_OTGSC_ASV_GET(x) (((uint32_t)(x) & USB_OTGSC_ASV_MASK) >> USB_OTGSC_ASV_SHIFT) + +/* + * AVV (RO) + * + * AVV + * A VBus Valid - Read Only. + * Indicates VBus is above the A VBus valid threshold. + */ +#define USB_OTGSC_AVV_MASK (0x200U) +#define USB_OTGSC_AVV_SHIFT (9U) +#define USB_OTGSC_AVV_GET(x) (((uint32_t)(x) & USB_OTGSC_AVV_MASK) >> USB_OTGSC_AVV_SHIFT) + +/* + * ID (RO) + * + * ID + * USB ID - Read Only. + * 0 = A device, 1 = B device + */ +#define USB_OTGSC_ID_MASK (0x100U) +#define USB_OTGSC_ID_SHIFT (8U) +#define USB_OTGSC_ID_GET(x) (((uint32_t)(x) & USB_OTGSC_ID_MASK) >> USB_OTGSC_ID_SHIFT) + +/* + * IDPU (RW) + * + * IDPU + * ID Pullup - Read/Write + * This bit provide control over the ID pull-up resistor; 0 = off, 1 = on [default]. When this bit is 0, the ID input + * will not be sampled. + */ +#define USB_OTGSC_IDPU_MASK (0x20U) +#define USB_OTGSC_IDPU_SHIFT (5U) +#define USB_OTGSC_IDPU_SET(x) (((uint32_t)(x) << USB_OTGSC_IDPU_SHIFT) & USB_OTGSC_IDPU_MASK) +#define USB_OTGSC_IDPU_GET(x) (((uint32_t)(x) & USB_OTGSC_IDPU_MASK) >> USB_OTGSC_IDPU_SHIFT) + +/* + * VC (RW) + * + * VC + * VBUS Charge - Read/Write. + * Setting this bit causes the VBus line to be charged. This is used for VBus pulsing during SRP. + */ +#define USB_OTGSC_VC_MASK (0x2U) +#define USB_OTGSC_VC_SHIFT (1U) +#define USB_OTGSC_VC_SET(x) (((uint32_t)(x) << USB_OTGSC_VC_SHIFT) & USB_OTGSC_VC_MASK) +#define USB_OTGSC_VC_GET(x) (((uint32_t)(x) & USB_OTGSC_VC_MASK) >> USB_OTGSC_VC_SHIFT) + +/* + * VD (RW) + * + * VD + * VBUS_Discharge - Read/Write. + * Setting this bit causes VBus to discharge through a resistor. + */ +#define USB_OTGSC_VD_MASK (0x1U) +#define USB_OTGSC_VD_SHIFT (0U) +#define USB_OTGSC_VD_SET(x) (((uint32_t)(x) << USB_OTGSC_VD_SHIFT) & USB_OTGSC_VD_MASK) +#define USB_OTGSC_VD_GET(x) (((uint32_t)(x) & USB_OTGSC_VD_MASK) >> USB_OTGSC_VD_SHIFT) + +/* Bitfield definition for register: USBMODE */ +/* + * SDIS (RW) + * + * SDIS + * Stream Disable Mode. (0 - Inactive [default]; 1 - Active) + * Device Mode: Setting to a '1' disables double priming on both RX and TX for low bandwidth systems. + * This mode ensures that when the RX and TX buffers are sufficient to contain an entire packet that the standard double buffering scheme is disabled to prevent overruns/underruns in bandwidth limited systems. + * Note: In High Speed Mode, all packets received are responded to with a NYET handshake when stream disable is active. + * Host Mode: Setting to a '1' ensures that overruns/underruns of the latency FIFO are eliminated for low bandwidth systems + * where the RX and TX buffers are sufficient to contain the entire packet. Enabling stream disable also has the effect of ensuring the TX latency is filled to capacity before the packet is launched onto the USB. + * NOTE: Time duration to pre-fill the FIFO becomes significant when stream disable is active. See TXFILLTUNING and TXTTFILLTUNING [MPH Only] to characterize the adjustments needed for + * the scheduler when using this feature. + * NOTE: The use of this feature substantially limits of the overall USB performance that can be achieved. + */ +#define USB_USBMODE_SDIS_MASK (0x10U) +#define USB_USBMODE_SDIS_SHIFT (4U) +#define USB_USBMODE_SDIS_SET(x) (((uint32_t)(x) << USB_USBMODE_SDIS_SHIFT) & USB_USBMODE_SDIS_MASK) +#define USB_USBMODE_SDIS_GET(x) (((uint32_t)(x) & USB_USBMODE_SDIS_MASK) >> USB_USBMODE_SDIS_SHIFT) + +/* + * SLOM (RW) + * + * SLOM + * Setup Lockout Mode. In device mode, this bit controls behavior of the setup lock mechanism. See Control Endpoint Operation Model . + * 0 - Setup Lockouts On (default); + * 1 - Setup Lockouts Off. DCD requires use of Setup Data Buffer Tripwire in USBCMD. + */ +#define USB_USBMODE_SLOM_MASK (0x8U) +#define USB_USBMODE_SLOM_SHIFT (3U) +#define USB_USBMODE_SLOM_SET(x) (((uint32_t)(x) << USB_USBMODE_SLOM_SHIFT) & USB_USBMODE_SLOM_MASK) +#define USB_USBMODE_SLOM_GET(x) (((uint32_t)(x) & USB_USBMODE_SLOM_MASK) >> USB_USBMODE_SLOM_SHIFT) + +/* + * ES (RW) + * + * ES + * Endian Select - Read/Write. This bit can change the byte alignment of the transfer buffers to match the + * host microprocessor. The bit fields in the microprocessor interface and the data structures are unaffected + * by the value of this bit because they are based upon the 32-bit word. + * Bit Meaning + * 0 - Little Endian [Default] + * 1 - Big Endian + */ +#define USB_USBMODE_ES_MASK (0x4U) +#define USB_USBMODE_ES_SHIFT (2U) +#define USB_USBMODE_ES_SET(x) (((uint32_t)(x) << USB_USBMODE_ES_SHIFT) & USB_USBMODE_ES_MASK) +#define USB_USBMODE_ES_GET(x) (((uint32_t)(x) & USB_USBMODE_ES_MASK) >> USB_USBMODE_ES_SHIFT) + +/* + * CM (RW) + * + * CM + * Controller Mode - R/WO. Controller mode is defaulted to the proper mode for host only and device only + * implementations. For those designs that contain both host & device capability, the controller defaults to + * an idle state and needs to be initialized to the desired operating mode after reset. For combination host/ + * device controllers, this register can only be written once after reset. If it is necessary to switch modes, + * software must reset the controller by writing to the RESET bit in the USBCMD register before + * reprogramming this register. + * For OTG controller core, reset value is '00b'. + * 00 - Idle [Default for combination host/device] + * 01 - Reserved + * 10 - Device Controller [Default for device only controller] + * 11 - Host Controller [Default for host only controller] + */ +#define USB_USBMODE_CM_MASK (0x3U) +#define USB_USBMODE_CM_SHIFT (0U) +#define USB_USBMODE_CM_SET(x) (((uint32_t)(x) << USB_USBMODE_CM_SHIFT) & USB_USBMODE_CM_MASK) +#define USB_USBMODE_CM_GET(x) (((uint32_t)(x) & USB_USBMODE_CM_MASK) >> USB_USBMODE_CM_SHIFT) + +/* Bitfield definition for register: ENDPTSETUPSTAT */ +/* + * ENDPTSETUPSTAT (RWC) + * + * ENDPTSETUPSTAT + * Setup Endpoint Status. For every setup transaction that is received, a corresponding bit in this register is set to one. + * Software must clear or acknowledge the setup transfer by writing a one to a respective bit after it has read the setup data from Queue head. + * The response to a setup packet as in the order of operations and total response time is crucial to limit bus time outs while the setup lock out mechanism is engaged. + * This register is only used in device mode. + */ +#define USB_ENDPTSETUPSTAT_ENDPTSETUPSTAT_MASK (0xFFFFU) +#define USB_ENDPTSETUPSTAT_ENDPTSETUPSTAT_SHIFT (0U) +#define USB_ENDPTSETUPSTAT_ENDPTSETUPSTAT_SET(x) (((uint32_t)(x) << USB_ENDPTSETUPSTAT_ENDPTSETUPSTAT_SHIFT) & USB_ENDPTSETUPSTAT_ENDPTSETUPSTAT_MASK) +#define USB_ENDPTSETUPSTAT_ENDPTSETUPSTAT_GET(x) (((uint32_t)(x) & USB_ENDPTSETUPSTAT_ENDPTSETUPSTAT_MASK) >> USB_ENDPTSETUPSTAT_ENDPTSETUPSTAT_SHIFT) + +/* Bitfield definition for register: ENDPTPRIME */ +/* + * PETB (RWS) + * + * PETB + * Prime Endpoint Transmit Buffer - R/WS. For each endpoint a corresponding bit is used to request that a + * buffer is prepared for a transmit operation in order to respond to a USB IN/INTERRUPT transaction. + * Software should write a one to the corresponding bit when posting a new transfer descriptor to an + * endpoint queue head. Hardware automatically uses this bit to begin parsing for a new transfer descriptor + * from the queue head and prepare a transmit buffer. Hardware clears this bit when the associated + * endpoint(s) is (are) successfully primed. + * NOTE: These bits are momentarily set by hardware during hardware re-priming operations when a dTD + * is retired, and the dQH is updated. + * PETB[N] - Endpoint #N, N is in 0..7 + */ +#define USB_ENDPTPRIME_PETB_MASK (0xFFFF0000UL) +#define USB_ENDPTPRIME_PETB_SHIFT (16U) +#define USB_ENDPTPRIME_PETB_SET(x) (((uint32_t)(x) << USB_ENDPTPRIME_PETB_SHIFT) & USB_ENDPTPRIME_PETB_MASK) +#define USB_ENDPTPRIME_PETB_GET(x) (((uint32_t)(x) & USB_ENDPTPRIME_PETB_MASK) >> USB_ENDPTPRIME_PETB_SHIFT) + +/* + * PERB (RWS) + * + * PERB + * Prime Endpoint Receive Buffer - R/WS. For each endpoint, a corresponding bit is used to request a buffer prepare for a receive operation for when a USB host initiates a USB OUT transaction. + * Software should write a one to the corresponding bit whenever posting a new transfer descriptor to an endpoint queue head. + * Hardware automatically uses this bit to begin parsing for a new transfer descriptor from the queue head and prepare a receive buffer. + * Hardware clears this bit when the associated endpoint(s) is (are) successfully primed. + * NOTE: These bits are momentarily set by hardware during hardware re-priming operations when a dTD + * is retired, and the dQH is updated. + * PERB[N] - Endpoint #N, N is in 0..7 + */ +#define USB_ENDPTPRIME_PERB_MASK (0xFFFFU) +#define USB_ENDPTPRIME_PERB_SHIFT (0U) +#define USB_ENDPTPRIME_PERB_SET(x) (((uint32_t)(x) << USB_ENDPTPRIME_PERB_SHIFT) & USB_ENDPTPRIME_PERB_MASK) +#define USB_ENDPTPRIME_PERB_GET(x) (((uint32_t)(x) & USB_ENDPTPRIME_PERB_MASK) >> USB_ENDPTPRIME_PERB_SHIFT) + +/* Bitfield definition for register: ENDPTFLUSH */ +/* + * FETB (RWS) + * + * FETB + * Flush Endpoint Transmit Buffer - R/WS. Writing one to a bit(s) in this register causes the associated endpoint(s) to clear any primed buffers. + * If a packet is in progress for one of the associated endpoints, then that transfer continues until completion. + * Hardware clears this register after the endpoint flush operation is successful. + * FETB[N] - Endpoint #N, N is in 0..7 + */ +#define USB_ENDPTFLUSH_FETB_MASK (0xFFFF0000UL) +#define USB_ENDPTFLUSH_FETB_SHIFT (16U) +#define USB_ENDPTFLUSH_FETB_SET(x) (((uint32_t)(x) << USB_ENDPTFLUSH_FETB_SHIFT) & USB_ENDPTFLUSH_FETB_MASK) +#define USB_ENDPTFLUSH_FETB_GET(x) (((uint32_t)(x) & USB_ENDPTFLUSH_FETB_MASK) >> USB_ENDPTFLUSH_FETB_SHIFT) + +/* + * FERB (RWS) + * + * FERB + * Flush Endpoint Receive Buffer - R/WS. Writing one to a bit(s) causes the associated endpoint(s) to clear any primed buffers. + * If a packet is in progress for one of the associated endpoints, then that transfer continues until completion. + * Hardware clears this register after the endpoint flush operation is successful. + * FERB[N] - Endpoint #N, N is in 0..7 + */ +#define USB_ENDPTFLUSH_FERB_MASK (0xFFFFU) +#define USB_ENDPTFLUSH_FERB_SHIFT (0U) +#define USB_ENDPTFLUSH_FERB_SET(x) (((uint32_t)(x) << USB_ENDPTFLUSH_FERB_SHIFT) & USB_ENDPTFLUSH_FERB_MASK) +#define USB_ENDPTFLUSH_FERB_GET(x) (((uint32_t)(x) & USB_ENDPTFLUSH_FERB_MASK) >> USB_ENDPTFLUSH_FERB_SHIFT) + +/* Bitfield definition for register: ENDPTSTAT */ +/* + * ETBR (RO) + * + * ETBR + * Endpoint Transmit Buffer Ready -- Read Only. One bit for each endpoint indicates status of the respective endpoint buffer. + * This bit is set to one by the hardware as a response to receiving a command from a corresponding bit in the ENDPTPRIME register. + * There is always a delay between setting a bit in the ENDPTPRIME register and endpoint indicating ready. + * This delay time varies based upon the current USB traffic and the number of bits set in the ENDPRIME register. + * Buffer ready is cleared by USB reset, by the USB DMA system, or through the ENDPTFLUSH register. + * NOTE: These bits are momentarily cleared by hardware during hardware endpoint re-priming operations when a dTD is retired, and the dQH is updated. + * ETBR[N] - Endpoint #N, N is in 0..7 + */ +#define USB_ENDPTSTAT_ETBR_MASK (0xFFFF0000UL) +#define USB_ENDPTSTAT_ETBR_SHIFT (16U) +#define USB_ENDPTSTAT_ETBR_GET(x) (((uint32_t)(x) & USB_ENDPTSTAT_ETBR_MASK) >> USB_ENDPTSTAT_ETBR_SHIFT) + +/* + * ERBR (RO) + * + * ERBR + * Endpoint Receive Buffer Ready -- Read Only. One bit for each endpoint indicates status of the respective + * endpoint buffer. This bit is set to a one by the hardware as a response to receiving a command from a + * corresponding bit in the ENDPRIME register. There is always a delay between setting a bit in the + * ENDPRIME register and endpoint indicating ready. This delay time varies based upon the current USB + * traffic and the number of bits set in the ENDPRIME register. Buffer ready is cleared by USB reset, by the + * USB DMA system, or through the ENDPTFLUSH register. + * NOTE: These bits are momentarily cleared by hardware during hardware endpoint re-priming operations + * when a dTD is retired, and the dQH is updated. + * ERBR[N] - Endpoint #N, N is in 0..7 + */ +#define USB_ENDPTSTAT_ERBR_MASK (0xFFFFU) +#define USB_ENDPTSTAT_ERBR_SHIFT (0U) +#define USB_ENDPTSTAT_ERBR_GET(x) (((uint32_t)(x) & USB_ENDPTSTAT_ERBR_MASK) >> USB_ENDPTSTAT_ERBR_SHIFT) + +/* Bitfield definition for register: ENDPTCOMPLETE */ +/* + * ETCE (RWC) + * + * ETCE + * Endpoint Transmit Complete Event - R/WC. Each bit indicates a transmit event (IN/INTERRUPT) occurred and software should read the corresponding endpoint queue to determine the endpoint status. + * If the corresponding IOC bit is set in the Transfer Descriptor, then this bit is set simultaneously with the USBINT . Writing one clears the corresponding bit in this register. + * ETCE[N] - Endpoint #N, N is in 0..7 + */ +#define USB_ENDPTCOMPLETE_ETCE_MASK (0xFFFF0000UL) +#define USB_ENDPTCOMPLETE_ETCE_SHIFT (16U) +#define USB_ENDPTCOMPLETE_ETCE_SET(x) (((uint32_t)(x) << USB_ENDPTCOMPLETE_ETCE_SHIFT) & USB_ENDPTCOMPLETE_ETCE_MASK) +#define USB_ENDPTCOMPLETE_ETCE_GET(x) (((uint32_t)(x) & USB_ENDPTCOMPLETE_ETCE_MASK) >> USB_ENDPTCOMPLETE_ETCE_SHIFT) + +/* + * ERCE (RWC) + * + * ERCE + * Endpoint Receive Complete Event - RW/C. Each bit indicates a received event (OUT/SETUP) occurred + * and software should read the corresponding endpoint queue to determine the transfer status. If the + * corresponding IOC bit is set in the Transfer Descriptor, then this bit is set simultaneously with the + * USBINT . Writing one clears the corresponding bit in this register. + * ERCE[N] - Endpoint #N, N is in 0..7 + */ +#define USB_ENDPTCOMPLETE_ERCE_MASK (0xFFFFU) +#define USB_ENDPTCOMPLETE_ERCE_SHIFT (0U) +#define USB_ENDPTCOMPLETE_ERCE_SET(x) (((uint32_t)(x) << USB_ENDPTCOMPLETE_ERCE_SHIFT) & USB_ENDPTCOMPLETE_ERCE_MASK) +#define USB_ENDPTCOMPLETE_ERCE_GET(x) (((uint32_t)(x) & USB_ENDPTCOMPLETE_ERCE_MASK) >> USB_ENDPTCOMPLETE_ERCE_SHIFT) + +/* Bitfield definition for register array: ENDPTCTRL */ +/* + * TXE (RW) + * + * TXE + * TX Endpoint Enable + * 0 Disabled [Default] + * 1 Enabled + * An Endpoint should be enabled only after it has been configured. + */ +#define USB_ENDPTCTRL_TXE_MASK (0x800000UL) +#define USB_ENDPTCTRL_TXE_SHIFT (23U) +#define USB_ENDPTCTRL_TXE_SET(x) (((uint32_t)(x) << USB_ENDPTCTRL_TXE_SHIFT) & USB_ENDPTCTRL_TXE_MASK) +#define USB_ENDPTCTRL_TXE_GET(x) (((uint32_t)(x) & USB_ENDPTCTRL_TXE_MASK) >> USB_ENDPTCTRL_TXE_SHIFT) + +/* + * TXR (WS) + * + * TXR + * TX Data Toggle Reset (WS) + * Write 1 - Reset PID Sequence + * Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order + * to synchronize the data PID's between the Host and device. + */ +#define USB_ENDPTCTRL_TXR_MASK (0x400000UL) +#define USB_ENDPTCTRL_TXR_SHIFT (22U) +#define USB_ENDPTCTRL_TXR_SET(x) (((uint32_t)(x) << USB_ENDPTCTRL_TXR_SHIFT) & USB_ENDPTCTRL_TXR_MASK) +#define USB_ENDPTCTRL_TXR_GET(x) (((uint32_t)(x) & USB_ENDPTCTRL_TXR_MASK) >> USB_ENDPTCTRL_TXR_SHIFT) + +/* + * TXT (RW) + * + * TXT + * TX Endpoint Type - Read/Write + * 00 Control + * 01 Isochronous + * 10 Bulk + * 11 Interrupt + */ +#define USB_ENDPTCTRL_TXT_MASK (0xC0000UL) +#define USB_ENDPTCTRL_TXT_SHIFT (18U) +#define USB_ENDPTCTRL_TXT_SET(x) (((uint32_t)(x) << USB_ENDPTCTRL_TXT_SHIFT) & USB_ENDPTCTRL_TXT_MASK) +#define USB_ENDPTCTRL_TXT_GET(x) (((uint32_t)(x) & USB_ENDPTCTRL_TXT_MASK) >> USB_ENDPTCTRL_TXT_SHIFT) + +/* + * TXS (RW) + * + * TXS + * TX Endpoint Stall - Read/Write + * 0 End Point OK + * 1 End Point Stalled + * This bit will be cleared automatically upon receipt of a SETUP request if this Endpoint is configured + * as a Control Endpoint and this bit will continue to be cleared by hardware until the associated ENDPTSETUPSTAT bit is cleared. + * Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. + * This control will continue to STALL until this bit is either cleared by software or automatically cleared as above for control endpoints. + * NOTE: [CONTROL ENDPOINT TYPES ONLY]: there is a slight delay (50 clocks max) between the ENDPTSETUPSTAT begin cleared and hardware continuing to clear this bit. + * In most systems, it is unlikely the DCD software will observe this delay. However, should the DCD observe that the stall bit is not set after writing a one to it then follow this procedure: + * continually write this stall bit until it is set or until a new setup has been received by checking the associated endptsetupstat Bit. + */ +#define USB_ENDPTCTRL_TXS_MASK (0x10000UL) +#define USB_ENDPTCTRL_TXS_SHIFT (16U) +#define USB_ENDPTCTRL_TXS_SET(x) (((uint32_t)(x) << USB_ENDPTCTRL_TXS_SHIFT) & USB_ENDPTCTRL_TXS_MASK) +#define USB_ENDPTCTRL_TXS_GET(x) (((uint32_t)(x) & USB_ENDPTCTRL_TXS_MASK) >> USB_ENDPTCTRL_TXS_SHIFT) + +/* + * RXE (RW) + * + * RXE + * RX Endpoint Enable + * 0 Disabled [Default] + * 1 Enabled + * An Endpoint should be enabled only after it has been configured. + */ +#define USB_ENDPTCTRL_RXE_MASK (0x80U) +#define USB_ENDPTCTRL_RXE_SHIFT (7U) +#define USB_ENDPTCTRL_RXE_SET(x) (((uint32_t)(x) << USB_ENDPTCTRL_RXE_SHIFT) & USB_ENDPTCTRL_RXE_MASK) +#define USB_ENDPTCTRL_RXE_GET(x) (((uint32_t)(x) & USB_ENDPTCTRL_RXE_MASK) >> USB_ENDPTCTRL_RXE_SHIFT) + +/* + * RXR (WS) + * + * RXR + * RX Data Toggle Reset (WS) + * Write 1 - Reset PID Sequence + * Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order + * to synchronize the data PID's between the host and device. + */ +#define USB_ENDPTCTRL_RXR_MASK (0x40U) +#define USB_ENDPTCTRL_RXR_SHIFT (6U) +#define USB_ENDPTCTRL_RXR_SET(x) (((uint32_t)(x) << USB_ENDPTCTRL_RXR_SHIFT) & USB_ENDPTCTRL_RXR_MASK) +#define USB_ENDPTCTRL_RXR_GET(x) (((uint32_t)(x) & USB_ENDPTCTRL_RXR_MASK) >> USB_ENDPTCTRL_RXR_SHIFT) + +/* + * RXT (RW) + * + * RXT + * RX Endpoint Type - Read/Write + * 00 Control + * 01 Isochronous + * 10 Bulk + * 11 Interrupt + */ +#define USB_ENDPTCTRL_RXT_MASK (0xCU) +#define USB_ENDPTCTRL_RXT_SHIFT (2U) +#define USB_ENDPTCTRL_RXT_SET(x) (((uint32_t)(x) << USB_ENDPTCTRL_RXT_SHIFT) & USB_ENDPTCTRL_RXT_MASK) +#define USB_ENDPTCTRL_RXT_GET(x) (((uint32_t)(x) & USB_ENDPTCTRL_RXT_MASK) >> USB_ENDPTCTRL_RXT_SHIFT) + +/* + * RXS (RW) + * + * RXS + * RX Endpoint Stall - Read/Write + * 0 End Point OK. [Default] + * 1 End Point Stalled + * This bit is set automatically upon receipt of a SETUP request if this Endpoint is configured as a Control + * Endpointand this bit will continue to be cleared by hardware until the associated ENDPTSETUPSTAT bit + * is cleared. + * Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. This + * control will continue to STALL until this bit is either cleared by software or automatically cleared as above + * for control endpoints. + * NOTE: [CONTROL ENDPOINT TYPES ONLY]: there is a slight delay (50 clocks max) between the + * ENDPTSETUPSTAT begin cleared and hardware continuing to clear this bit. In most systems, it + * is unlikely the DCD software will observe this delay. However, should the DCD observe that the + * stall bit is not set after writing a one to it then follow this procedure: continually write this stall bit + * until it is set or until a new setup has been received by checking the associated endptsetupstat + * Bit. + */ +#define USB_ENDPTCTRL_RXS_MASK (0x1U) +#define USB_ENDPTCTRL_RXS_SHIFT (0U) +#define USB_ENDPTCTRL_RXS_SET(x) (((uint32_t)(x) << USB_ENDPTCTRL_RXS_SHIFT) & USB_ENDPTCTRL_RXS_MASK) +#define USB_ENDPTCTRL_RXS_GET(x) (((uint32_t)(x) & USB_ENDPTCTRL_RXS_MASK) >> USB_ENDPTCTRL_RXS_SHIFT) + +/* Bitfield definition for register: OTG_CTRL0 */ +/* + * OTG_WKDPDMCHG_EN (RW) + * + */ +#define USB_OTG_CTRL0_OTG_WKDPDMCHG_EN_MASK (0x2000000UL) +#define USB_OTG_CTRL0_OTG_WKDPDMCHG_EN_SHIFT (25U) +#define USB_OTG_CTRL0_OTG_WKDPDMCHG_EN_SET(x) (((uint32_t)(x) << USB_OTG_CTRL0_OTG_WKDPDMCHG_EN_SHIFT) & USB_OTG_CTRL0_OTG_WKDPDMCHG_EN_MASK) +#define USB_OTG_CTRL0_OTG_WKDPDMCHG_EN_GET(x) (((uint32_t)(x) & USB_OTG_CTRL0_OTG_WKDPDMCHG_EN_MASK) >> USB_OTG_CTRL0_OTG_WKDPDMCHG_EN_SHIFT) + +/* + * AUTORESUME_EN (RW) + * + */ +#define USB_OTG_CTRL0_AUTORESUME_EN_MASK (0x80000UL) +#define USB_OTG_CTRL0_AUTORESUME_EN_SHIFT (19U) +#define USB_OTG_CTRL0_AUTORESUME_EN_SET(x) (((uint32_t)(x) << USB_OTG_CTRL0_AUTORESUME_EN_SHIFT) & USB_OTG_CTRL0_AUTORESUME_EN_MASK) +#define USB_OTG_CTRL0_AUTORESUME_EN_GET(x) (((uint32_t)(x) & USB_OTG_CTRL0_AUTORESUME_EN_MASK) >> USB_OTG_CTRL0_AUTORESUME_EN_SHIFT) + +/* + * OTG_VBUS_WAKEUP_EN (RW) + * + */ +#define USB_OTG_CTRL0_OTG_VBUS_WAKEUP_EN_MASK (0x20000UL) +#define USB_OTG_CTRL0_OTG_VBUS_WAKEUP_EN_SHIFT (17U) +#define USB_OTG_CTRL0_OTG_VBUS_WAKEUP_EN_SET(x) (((uint32_t)(x) << USB_OTG_CTRL0_OTG_VBUS_WAKEUP_EN_SHIFT) & USB_OTG_CTRL0_OTG_VBUS_WAKEUP_EN_MASK) +#define USB_OTG_CTRL0_OTG_VBUS_WAKEUP_EN_GET(x) (((uint32_t)(x) & USB_OTG_CTRL0_OTG_VBUS_WAKEUP_EN_MASK) >> USB_OTG_CTRL0_OTG_VBUS_WAKEUP_EN_SHIFT) + +/* + * OTG_ID_WAKEUP_EN (RW) + * + */ +#define USB_OTG_CTRL0_OTG_ID_WAKEUP_EN_MASK (0x10000UL) +#define USB_OTG_CTRL0_OTG_ID_WAKEUP_EN_SHIFT (16U) +#define USB_OTG_CTRL0_OTG_ID_WAKEUP_EN_SET(x) (((uint32_t)(x) << USB_OTG_CTRL0_OTG_ID_WAKEUP_EN_SHIFT) & USB_OTG_CTRL0_OTG_ID_WAKEUP_EN_MASK) +#define USB_OTG_CTRL0_OTG_ID_WAKEUP_EN_GET(x) (((uint32_t)(x) & USB_OTG_CTRL0_OTG_ID_WAKEUP_EN_MASK) >> USB_OTG_CTRL0_OTG_ID_WAKEUP_EN_SHIFT) + +/* + * OTG_VBUS_SOURCE_SEL (RW) + * + */ +#define USB_OTG_CTRL0_OTG_VBUS_SOURCE_SEL_MASK (0x2000U) +#define USB_OTG_CTRL0_OTG_VBUS_SOURCE_SEL_SHIFT (13U) +#define USB_OTG_CTRL0_OTG_VBUS_SOURCE_SEL_SET(x) (((uint32_t)(x) << USB_OTG_CTRL0_OTG_VBUS_SOURCE_SEL_SHIFT) & USB_OTG_CTRL0_OTG_VBUS_SOURCE_SEL_MASK) +#define USB_OTG_CTRL0_OTG_VBUS_SOURCE_SEL_GET(x) (((uint32_t)(x) & USB_OTG_CTRL0_OTG_VBUS_SOURCE_SEL_MASK) >> USB_OTG_CTRL0_OTG_VBUS_SOURCE_SEL_SHIFT) + +/* + * OTG_UTMI_SUSPENDM_SW (RW) + * + * default 0 for naneng usbphy + */ +#define USB_OTG_CTRL0_OTG_UTMI_SUSPENDM_SW_MASK (0x1000U) +#define USB_OTG_CTRL0_OTG_UTMI_SUSPENDM_SW_SHIFT (12U) +#define USB_OTG_CTRL0_OTG_UTMI_SUSPENDM_SW_SET(x) (((uint32_t)(x) << USB_OTG_CTRL0_OTG_UTMI_SUSPENDM_SW_SHIFT) & USB_OTG_CTRL0_OTG_UTMI_SUSPENDM_SW_MASK) +#define USB_OTG_CTRL0_OTG_UTMI_SUSPENDM_SW_GET(x) (((uint32_t)(x) & USB_OTG_CTRL0_OTG_UTMI_SUSPENDM_SW_MASK) >> USB_OTG_CTRL0_OTG_UTMI_SUSPENDM_SW_SHIFT) + +/* + * OTG_UTMI_RESET_SW (RW) + * + * default 1 for naneng usbphy + */ +#define USB_OTG_CTRL0_OTG_UTMI_RESET_SW_MASK (0x800U) +#define USB_OTG_CTRL0_OTG_UTMI_RESET_SW_SHIFT (11U) +#define USB_OTG_CTRL0_OTG_UTMI_RESET_SW_SET(x) (((uint32_t)(x) << USB_OTG_CTRL0_OTG_UTMI_RESET_SW_SHIFT) & USB_OTG_CTRL0_OTG_UTMI_RESET_SW_MASK) +#define USB_OTG_CTRL0_OTG_UTMI_RESET_SW_GET(x) (((uint32_t)(x) & USB_OTG_CTRL0_OTG_UTMI_RESET_SW_MASK) >> USB_OTG_CTRL0_OTG_UTMI_RESET_SW_SHIFT) + +/* + * OTG_WAKEUP_INT_ENABLE (RW) + * + */ +#define USB_OTG_CTRL0_OTG_WAKEUP_INT_ENABLE_MASK (0x400U) +#define USB_OTG_CTRL0_OTG_WAKEUP_INT_ENABLE_SHIFT (10U) +#define USB_OTG_CTRL0_OTG_WAKEUP_INT_ENABLE_SET(x) (((uint32_t)(x) << USB_OTG_CTRL0_OTG_WAKEUP_INT_ENABLE_SHIFT) & USB_OTG_CTRL0_OTG_WAKEUP_INT_ENABLE_MASK) +#define USB_OTG_CTRL0_OTG_WAKEUP_INT_ENABLE_GET(x) (((uint32_t)(x) & USB_OTG_CTRL0_OTG_WAKEUP_INT_ENABLE_MASK) >> USB_OTG_CTRL0_OTG_WAKEUP_INT_ENABLE_SHIFT) + +/* + * OTG_POWER_MASK (RW) + * + */ +#define USB_OTG_CTRL0_OTG_POWER_MASK_MASK (0x200U) +#define USB_OTG_CTRL0_OTG_POWER_MASK_SHIFT (9U) +#define USB_OTG_CTRL0_OTG_POWER_MASK_SET(x) (((uint32_t)(x) << USB_OTG_CTRL0_OTG_POWER_MASK_SHIFT) & USB_OTG_CTRL0_OTG_POWER_MASK_MASK) +#define USB_OTG_CTRL0_OTG_POWER_MASK_GET(x) (((uint32_t)(x) & USB_OTG_CTRL0_OTG_POWER_MASK_MASK) >> USB_OTG_CTRL0_OTG_POWER_MASK_SHIFT) + +/* + * OTG_OVER_CUR_POL (RW) + * + */ +#define USB_OTG_CTRL0_OTG_OVER_CUR_POL_MASK (0x100U) +#define USB_OTG_CTRL0_OTG_OVER_CUR_POL_SHIFT (8U) +#define USB_OTG_CTRL0_OTG_OVER_CUR_POL_SET(x) (((uint32_t)(x) << USB_OTG_CTRL0_OTG_OVER_CUR_POL_SHIFT) & USB_OTG_CTRL0_OTG_OVER_CUR_POL_MASK) +#define USB_OTG_CTRL0_OTG_OVER_CUR_POL_GET(x) (((uint32_t)(x) & USB_OTG_CTRL0_OTG_OVER_CUR_POL_MASK) >> USB_OTG_CTRL0_OTG_OVER_CUR_POL_SHIFT) + +/* + * OTG_OVER_CUR_DIS (RW) + * + */ +#define USB_OTG_CTRL0_OTG_OVER_CUR_DIS_MASK (0x80U) +#define USB_OTG_CTRL0_OTG_OVER_CUR_DIS_SHIFT (7U) +#define USB_OTG_CTRL0_OTG_OVER_CUR_DIS_SET(x) (((uint32_t)(x) << USB_OTG_CTRL0_OTG_OVER_CUR_DIS_SHIFT) & USB_OTG_CTRL0_OTG_OVER_CUR_DIS_MASK) +#define USB_OTG_CTRL0_OTG_OVER_CUR_DIS_GET(x) (((uint32_t)(x) & USB_OTG_CTRL0_OTG_OVER_CUR_DIS_MASK) >> USB_OTG_CTRL0_OTG_OVER_CUR_DIS_SHIFT) + +/* + * SER_MODE_SUSPEND_EN (RW) + * + * for naneng usbphy, only switch to serial mode when suspend + */ +#define USB_OTG_CTRL0_SER_MODE_SUSPEND_EN_MASK (0x10U) +#define USB_OTG_CTRL0_SER_MODE_SUSPEND_EN_SHIFT (4U) +#define USB_OTG_CTRL0_SER_MODE_SUSPEND_EN_SET(x) (((uint32_t)(x) << USB_OTG_CTRL0_SER_MODE_SUSPEND_EN_SHIFT) & USB_OTG_CTRL0_SER_MODE_SUSPEND_EN_MASK) +#define USB_OTG_CTRL0_SER_MODE_SUSPEND_EN_GET(x) (((uint32_t)(x) & USB_OTG_CTRL0_SER_MODE_SUSPEND_EN_MASK) >> USB_OTG_CTRL0_SER_MODE_SUSPEND_EN_SHIFT) + +/* Bitfield definition for register: PHY_CTRL0 */ +/* + * GPIO_ID_SEL_N (RW) + * + */ +#define USB_PHY_CTRL0_GPIO_ID_SEL_N_MASK (0x2000000UL) +#define USB_PHY_CTRL0_GPIO_ID_SEL_N_SHIFT (25U) +#define USB_PHY_CTRL0_GPIO_ID_SEL_N_SET(x) (((uint32_t)(x) << USB_PHY_CTRL0_GPIO_ID_SEL_N_SHIFT) & USB_PHY_CTRL0_GPIO_ID_SEL_N_MASK) +#define USB_PHY_CTRL0_GPIO_ID_SEL_N_GET(x) (((uint32_t)(x) & USB_PHY_CTRL0_GPIO_ID_SEL_N_MASK) >> USB_PHY_CTRL0_GPIO_ID_SEL_N_SHIFT) + +/* + * ID_DIG_OVERRIDE (RW) + * + */ +#define USB_PHY_CTRL0_ID_DIG_OVERRIDE_MASK (0x4000U) +#define USB_PHY_CTRL0_ID_DIG_OVERRIDE_SHIFT (14U) +#define USB_PHY_CTRL0_ID_DIG_OVERRIDE_SET(x) (((uint32_t)(x) << USB_PHY_CTRL0_ID_DIG_OVERRIDE_SHIFT) & USB_PHY_CTRL0_ID_DIG_OVERRIDE_MASK) +#define USB_PHY_CTRL0_ID_DIG_OVERRIDE_GET(x) (((uint32_t)(x) & USB_PHY_CTRL0_ID_DIG_OVERRIDE_MASK) >> USB_PHY_CTRL0_ID_DIG_OVERRIDE_SHIFT) + +/* + * SESS_VALID_OVERRIDE (RW) + * + */ +#define USB_PHY_CTRL0_SESS_VALID_OVERRIDE_MASK (0x2000U) +#define USB_PHY_CTRL0_SESS_VALID_OVERRIDE_SHIFT (13U) +#define USB_PHY_CTRL0_SESS_VALID_OVERRIDE_SET(x) (((uint32_t)(x) << USB_PHY_CTRL0_SESS_VALID_OVERRIDE_SHIFT) & USB_PHY_CTRL0_SESS_VALID_OVERRIDE_MASK) +#define USB_PHY_CTRL0_SESS_VALID_OVERRIDE_GET(x) (((uint32_t)(x) & USB_PHY_CTRL0_SESS_VALID_OVERRIDE_MASK) >> USB_PHY_CTRL0_SESS_VALID_OVERRIDE_SHIFT) + +/* + * VBUS_VALID_OVERRIDE (RW) + * + */ +#define USB_PHY_CTRL0_VBUS_VALID_OVERRIDE_MASK (0x1000U) +#define USB_PHY_CTRL0_VBUS_VALID_OVERRIDE_SHIFT (12U) +#define USB_PHY_CTRL0_VBUS_VALID_OVERRIDE_SET(x) (((uint32_t)(x) << USB_PHY_CTRL0_VBUS_VALID_OVERRIDE_SHIFT) & USB_PHY_CTRL0_VBUS_VALID_OVERRIDE_MASK) +#define USB_PHY_CTRL0_VBUS_VALID_OVERRIDE_GET(x) (((uint32_t)(x) & USB_PHY_CTRL0_VBUS_VALID_OVERRIDE_MASK) >> USB_PHY_CTRL0_VBUS_VALID_OVERRIDE_SHIFT) + +/* + * ID_DIG_OVERRIDE_EN (RW) + * + */ +#define USB_PHY_CTRL0_ID_DIG_OVERRIDE_EN_MASK (0x4U) +#define USB_PHY_CTRL0_ID_DIG_OVERRIDE_EN_SHIFT (2U) +#define USB_PHY_CTRL0_ID_DIG_OVERRIDE_EN_SET(x) (((uint32_t)(x) << USB_PHY_CTRL0_ID_DIG_OVERRIDE_EN_SHIFT) & USB_PHY_CTRL0_ID_DIG_OVERRIDE_EN_MASK) +#define USB_PHY_CTRL0_ID_DIG_OVERRIDE_EN_GET(x) (((uint32_t)(x) & USB_PHY_CTRL0_ID_DIG_OVERRIDE_EN_MASK) >> USB_PHY_CTRL0_ID_DIG_OVERRIDE_EN_SHIFT) + +/* + * SESS_VALID_OVERRIDE_EN (RW) + * + */ +#define USB_PHY_CTRL0_SESS_VALID_OVERRIDE_EN_MASK (0x2U) +#define USB_PHY_CTRL0_SESS_VALID_OVERRIDE_EN_SHIFT (1U) +#define USB_PHY_CTRL0_SESS_VALID_OVERRIDE_EN_SET(x) (((uint32_t)(x) << USB_PHY_CTRL0_SESS_VALID_OVERRIDE_EN_SHIFT) & USB_PHY_CTRL0_SESS_VALID_OVERRIDE_EN_MASK) +#define USB_PHY_CTRL0_SESS_VALID_OVERRIDE_EN_GET(x) (((uint32_t)(x) & USB_PHY_CTRL0_SESS_VALID_OVERRIDE_EN_MASK) >> USB_PHY_CTRL0_SESS_VALID_OVERRIDE_EN_SHIFT) + +/* + * VBUS_VALID_OVERRIDE_EN (RW) + * + */ +#define USB_PHY_CTRL0_VBUS_VALID_OVERRIDE_EN_MASK (0x1U) +#define USB_PHY_CTRL0_VBUS_VALID_OVERRIDE_EN_SHIFT (0U) +#define USB_PHY_CTRL0_VBUS_VALID_OVERRIDE_EN_SET(x) (((uint32_t)(x) << USB_PHY_CTRL0_VBUS_VALID_OVERRIDE_EN_SHIFT) & USB_PHY_CTRL0_VBUS_VALID_OVERRIDE_EN_MASK) +#define USB_PHY_CTRL0_VBUS_VALID_OVERRIDE_EN_GET(x) (((uint32_t)(x) & USB_PHY_CTRL0_VBUS_VALID_OVERRIDE_EN_MASK) >> USB_PHY_CTRL0_VBUS_VALID_OVERRIDE_EN_SHIFT) + +/* Bitfield definition for register: PHY_CTRL1 */ +/* + * UTMI_CFG_RST_N (RW) + * + */ +#define USB_PHY_CTRL1_UTMI_CFG_RST_N_MASK (0x100000UL) +#define USB_PHY_CTRL1_UTMI_CFG_RST_N_SHIFT (20U) +#define USB_PHY_CTRL1_UTMI_CFG_RST_N_SET(x) (((uint32_t)(x) << USB_PHY_CTRL1_UTMI_CFG_RST_N_SHIFT) & USB_PHY_CTRL1_UTMI_CFG_RST_N_MASK) +#define USB_PHY_CTRL1_UTMI_CFG_RST_N_GET(x) (((uint32_t)(x) & USB_PHY_CTRL1_UTMI_CFG_RST_N_MASK) >> USB_PHY_CTRL1_UTMI_CFG_RST_N_SHIFT) + +/* + * UTMI_OTG_SUSPENDM (RW) + * + * OTG suspend, not utmi_suspendm + */ +#define USB_PHY_CTRL1_UTMI_OTG_SUSPENDM_MASK (0x2U) +#define USB_PHY_CTRL1_UTMI_OTG_SUSPENDM_SHIFT (1U) +#define USB_PHY_CTRL1_UTMI_OTG_SUSPENDM_SET(x) (((uint32_t)(x) << USB_PHY_CTRL1_UTMI_OTG_SUSPENDM_SHIFT) & USB_PHY_CTRL1_UTMI_OTG_SUSPENDM_MASK) +#define USB_PHY_CTRL1_UTMI_OTG_SUSPENDM_GET(x) (((uint32_t)(x) & USB_PHY_CTRL1_UTMI_OTG_SUSPENDM_MASK) >> USB_PHY_CTRL1_UTMI_OTG_SUSPENDM_SHIFT) + +/* Bitfield definition for register: TOP_STATUS */ +/* + * WAKEUP_INT_STATUS (RW) + * + */ +#define USB_TOP_STATUS_WAKEUP_INT_STATUS_MASK (0x80000000UL) +#define USB_TOP_STATUS_WAKEUP_INT_STATUS_SHIFT (31U) +#define USB_TOP_STATUS_WAKEUP_INT_STATUS_SET(x) (((uint32_t)(x) << USB_TOP_STATUS_WAKEUP_INT_STATUS_SHIFT) & USB_TOP_STATUS_WAKEUP_INT_STATUS_MASK) +#define USB_TOP_STATUS_WAKEUP_INT_STATUS_GET(x) (((uint32_t)(x) & USB_TOP_STATUS_WAKEUP_INT_STATUS_MASK) >> USB_TOP_STATUS_WAKEUP_INT_STATUS_SHIFT) + +/* Bitfield definition for register: PHY_STATUS */ +/* + * UTMI_CLK_VALID (RW) + * + */ +#define USB_PHY_STATUS_UTMI_CLK_VALID_MASK (0x80000000UL) +#define USB_PHY_STATUS_UTMI_CLK_VALID_SHIFT (31U) +#define USB_PHY_STATUS_UTMI_CLK_VALID_SET(x) (((uint32_t)(x) << USB_PHY_STATUS_UTMI_CLK_VALID_SHIFT) & USB_PHY_STATUS_UTMI_CLK_VALID_MASK) +#define USB_PHY_STATUS_UTMI_CLK_VALID_GET(x) (((uint32_t)(x) & USB_PHY_STATUS_UTMI_CLK_VALID_MASK) >> USB_PHY_STATUS_UTMI_CLK_VALID_SHIFT) + +/* + * LINE_STATE (RW) + * + */ +#define USB_PHY_STATUS_LINE_STATE_MASK (0xC0U) +#define USB_PHY_STATUS_LINE_STATE_SHIFT (6U) +#define USB_PHY_STATUS_LINE_STATE_SET(x) (((uint32_t)(x) << USB_PHY_STATUS_LINE_STATE_SHIFT) & USB_PHY_STATUS_LINE_STATE_MASK) +#define USB_PHY_STATUS_LINE_STATE_GET(x) (((uint32_t)(x) & USB_PHY_STATUS_LINE_STATE_MASK) >> USB_PHY_STATUS_LINE_STATE_SHIFT) + +/* + * HOST_DISCONNECT (RW) + * + */ +#define USB_PHY_STATUS_HOST_DISCONNECT_MASK (0x20U) +#define USB_PHY_STATUS_HOST_DISCONNECT_SHIFT (5U) +#define USB_PHY_STATUS_HOST_DISCONNECT_SET(x) (((uint32_t)(x) << USB_PHY_STATUS_HOST_DISCONNECT_SHIFT) & USB_PHY_STATUS_HOST_DISCONNECT_MASK) +#define USB_PHY_STATUS_HOST_DISCONNECT_GET(x) (((uint32_t)(x) & USB_PHY_STATUS_HOST_DISCONNECT_MASK) >> USB_PHY_STATUS_HOST_DISCONNECT_SHIFT) + +/* + * ID_DIG (RW) + * + */ +#define USB_PHY_STATUS_ID_DIG_MASK (0x10U) +#define USB_PHY_STATUS_ID_DIG_SHIFT (4U) +#define USB_PHY_STATUS_ID_DIG_SET(x) (((uint32_t)(x) << USB_PHY_STATUS_ID_DIG_SHIFT) & USB_PHY_STATUS_ID_DIG_MASK) +#define USB_PHY_STATUS_ID_DIG_GET(x) (((uint32_t)(x) & USB_PHY_STATUS_ID_DIG_MASK) >> USB_PHY_STATUS_ID_DIG_SHIFT) + +/* + * UTMI_SESS_VALID (RW) + * + */ +#define USB_PHY_STATUS_UTMI_SESS_VALID_MASK (0x4U) +#define USB_PHY_STATUS_UTMI_SESS_VALID_SHIFT (2U) +#define USB_PHY_STATUS_UTMI_SESS_VALID_SET(x) (((uint32_t)(x) << USB_PHY_STATUS_UTMI_SESS_VALID_SHIFT) & USB_PHY_STATUS_UTMI_SESS_VALID_MASK) +#define USB_PHY_STATUS_UTMI_SESS_VALID_GET(x) (((uint32_t)(x) & USB_PHY_STATUS_UTMI_SESS_VALID_MASK) >> USB_PHY_STATUS_UTMI_SESS_VALID_SHIFT) + +/* + * VBUS_VALID (RW) + * + */ +#define USB_PHY_STATUS_VBUS_VALID_MASK (0x1U) +#define USB_PHY_STATUS_VBUS_VALID_SHIFT (0U) +#define USB_PHY_STATUS_VBUS_VALID_SET(x) (((uint32_t)(x) << USB_PHY_STATUS_VBUS_VALID_SHIFT) & USB_PHY_STATUS_VBUS_VALID_MASK) +#define USB_PHY_STATUS_VBUS_VALID_GET(x) (((uint32_t)(x) & USB_PHY_STATUS_VBUS_VALID_MASK) >> USB_PHY_STATUS_VBUS_VALID_SHIFT) + + + +/* ENDPTCTRL register group index macro definition */ +#define USB_ENDPTCTRL_ENDPTCTRL0 (0UL) +#define USB_ENDPTCTRL_ENDPTCTRL1 (1UL) +#define USB_ENDPTCTRL_ENDPTCTRL2 (2UL) +#define USB_ENDPTCTRL_ENDPTCTRL3 (3UL) +#define USB_ENDPTCTRL_ENDPTCTRL4 (4UL) +#define USB_ENDPTCTRL_ENDPTCTRL5 (5UL) +#define USB_ENDPTCTRL_ENDPTCTRL6 (6UL) +#define USB_ENDPTCTRL_ENDPTCTRL7 (7UL) + + +#endif /* HPM_USB_H */ diff --git a/kernel/cherryusb/port/chipidea/usb_dc_chipidea.c b/kernel/cherryusb/port/chipidea/usb_dc_chipidea.c new file mode 100644 index 0000000..d8122ec --- /dev/null +++ b/kernel/cherryusb/port/chipidea/usb_dc_chipidea.c @@ -0,0 +1,740 @@ +/* + * Copyright (c) 2021-2024 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ +/* + * Copyright (c) 2024, sakumisu + * + * SPDX-License-Identifier: Apache-2.0 + */ +#include "usbd_core.h" +#include "usb_chipidea_reg.h" + +#define USB_OTG_DEV ((CHIPIDEA_TypeDef *)g_usbdev_bus[busid].reg_base) + +#define CHIPIDEA_BITSMASK(val, offset) ((uint32_t)(val) << (offset)) +#define QTD_COUNT_EACH_ENDPOINT (8U) + +#ifndef CONFIG_USBDEV_EP_NUM +#define CONFIG_USBDEV_EP_NUM 8 +#endif + +/* ENDPTCTRL */ +enum { + ENDPTCTRL_STALL = CHIPIDEA_BITSMASK(1, 0), + ENDPTCTRL_TYPE = CHIPIDEA_BITSMASK(3, 2), + ENDPTCTRL_TOGGLE_INHIBIT = CHIPIDEA_BITSMASK(1, 5), + ENDPTCTRL_TOGGLE_RESET = CHIPIDEA_BITSMASK(1, 6), + ENDPTCTRL_ENABLE = CHIPIDEA_BITSMASK(1, 7), +}; + +/* USBSTS, USBINTR */ +enum { + intr_usb = CHIPIDEA_BITSMASK(1, 0), + intr_error = CHIPIDEA_BITSMASK(1, 1), + intr_port_change = CHIPIDEA_BITSMASK(1, 2), + intr_reset = CHIPIDEA_BITSMASK(1, 6), + intr_sof = CHIPIDEA_BITSMASK(1, 7), + intr_suspend = CHIPIDEA_BITSMASK(1, 8), + intr_nak = CHIPIDEA_BITSMASK(1, 16) +}; + +/* Queue Transfer Descriptor */ +typedef struct { + /* Word 0: Next QTD Pointer */ + volatile uint32_t next; /* Next link pointer This field contains the physical memory address of the next dTD to be processed */ + + /* Word 1: qTQ Token */ + volatile uint32_t : 3; + volatile uint32_t xact_err : 1; + volatile uint32_t : 1; + volatile uint32_t buffer_err : 1; + volatile uint32_t halted : 1; + volatile uint32_t active : 1; + volatile uint32_t : 2; + volatile uint32_t iso_mult_override : 2; /* This field can be used for transmit ISOs to override the MULT field in the dQH. This field must be zero for all packet types that are not transmit-ISO. */ + volatile uint32_t : 3; + volatile uint32_t int_on_complete : 1; + volatile uint32_t total_bytes : 15; + volatile uint32_t : 0; + + /* Word 2-6: Buffer Page Pointer List, Each element in the list is a 4K page aligned, physical memory address. The lower 12 bits in each pointer are reserved (except for the first one) as each memory pointer must reference the start of a 4K page */ + volatile uint32_t buffer[5]; + + /*------------- DCD Area -------------*/ + volatile uint16_t expected_bytes; + volatile uint8_t reserved[2]; +} dcd_qtd_t; + +/* Queue Head */ +typedef struct { + /* Word 0: Capabilities and Characteristics */ + + volatile uint32_t : 15; /* Number of packets executed per transaction descriptor 00 - Execute N transactions as demonstrated by the USB variable length protocol where N is computed using Max_packet_length and the Total_bytes field in the dTD. 01 - Execute one transaction 10 - Execute two transactions 11 - Execute three transactions Remark: Non-isochronous endpoints must set MULT = 00. Remark: Isochronous endpoints must set MULT = 01, 10, or 11 as needed. */ + volatile uint32_t int_on_setup : 1; /* Interrupt on setup This bit is used on control type endpoints to indicate if USBINT is set in response to a setup being received. */ + volatile uint32_t max_packet_size : 11; /* This directly corresponds to the maximum packet size of the associated endpoint (wMaxPacketSize) */ + volatile uint32_t : 2; + volatile uint32_t zero_length_termination : 1; /* This bit is used for non-isochronous endpoints to indicate when a zero-length packet is received to terminate transfers in case the total transfer length is “multiple”. 0 - Enable zero-length packet to terminate transfers equal to a multiple of Max_packet_length (default). 1 - Disable zero-length packet on transfers that are equal in length to a multiple Max_packet_length. */ + volatile uint32_t iso_mult : 2; + volatile uint32_t : 0; + + /* Word 1: Current qTD Pointer */ + volatile uint32_t qtd_addr; + + /* Word 2-9: Transfer Overlay */ + volatile dcd_qtd_t qtd_overlay; + + /* Word 10-11: Setup request (control OUT only) */ + volatile struct usb_setup_packet setup_request; + + /*-------------------------------------------------------------------- + * Due to the fact QHD is 64 bytes aligned but occupies only 48 bytes + * thus there are 16 bytes padding free that we can make use of. + *-------------------------------------------------------------------- + */ + volatile uint8_t reserved[16]; +} dcd_qhd_t; + +typedef struct { + dcd_qhd_t qhd[CONFIG_USBDEV_EP_NUM * 2]; + dcd_qtd_t qtd[CONFIG_USBDEV_EP_NUM * 2 * QTD_COUNT_EACH_ENDPOINT]; +} dcd_data_t; + +/* Endpoint state */ +struct chipidea_ep_state { + uint16_t ep_mps; /* Endpoint max packet size */ + uint8_t ep_type; /* Endpoint type */ + uint8_t ep_stalled; /* Endpoint stall flag */ + uint8_t ep_enable; /* Endpoint enable */ + uint8_t *xfer_buf; + uint32_t xfer_len; + uint32_t actual_xfer_len; +}; + +/* Driver state */ +struct chipidea_udc { + dcd_data_t *dcd_data; + bool is_suspend; + struct chipidea_ep_state in_ep[CONFIG_USBDEV_EP_NUM]; /*!< IN endpoint parameters*/ + struct chipidea_ep_state out_ep[CONFIG_USBDEV_EP_NUM]; /*!< OUT endpoint parameters */ +} g_chipidea_udc[CONFIG_USBDEV_MAX_BUS]; + +static USB_NOCACHE_RAM_SECTION __attribute__((aligned(2048))) dcd_data_t _dcd_data0; +#if CONFIG_USBDEV_MAX_BUS == 2 +static USB_NOCACHE_RAM_SECTION __attribute__((aligned(2048))) dcd_data_t _dcd_data1; +#endif + +static dcd_data_t *g_dcd_data[CONFIG_USBDEV_MAX_BUS] = { + &_dcd_data0, +#if CONFIG_USBDEV_MAX_BUS == 2 + &_dcd_data1 +#endif +}; + +/* Index to bit position in register */ +static inline uint8_t ep_idx2bit(uint8_t ep_idx) +{ + return ep_idx / 2 + ((ep_idx % 2) ? 16 : 0); +} + +static void __chipidea_bus_reset(CHIPIDEA_TypeDef *ptr) +{ + /* The reset value for all endpoint types is the control endpoint. If one endpoint + * direction is enabled and the paired endpoint of opposite direction is disabled, then the + * endpoint type of the unused direction must be changed from the control type to any other + * type (e.g. bulk). Leaving an un-configured endpoint control will cause undefined behavior + * for the data PID tracking on the active endpoint. + */ + + for (uint32_t i = 1; i < CONFIG_USBDEV_EP_NUM; i++) { + ptr->ENDPTCTRL[i] = USB_ENDPTCTRL_TXT_SET(USB_ENDPOINT_TYPE_BULK) | USB_ENDPTCTRL_RXT_SET(USB_ENDPOINT_TYPE_BULK); + } + + /* Clear All Registers */ + ptr->ENDPTNAK = ptr->ENDPTNAK; + ptr->ENDPTNAKEN = 0; + ptr->USBSTS = ptr->USBSTS; + ptr->ENDPTSETUPSTAT = ptr->ENDPTSETUPSTAT; + ptr->ENDPTCOMPLETE = ptr->ENDPTCOMPLETE; + + while (ptr->ENDPTPRIME) { + } + ptr->ENDPTFLUSH = 0xFFFFFFFF; + while (ptr->ENDPTFLUSH) { + } +} + +static void chipidea_init(CHIPIDEA_TypeDef *ptr) +{ + /* Reset controller */ + ptr->USBCMD |= USB_USBCMD_RST_MASK; + while (USB_USBCMD_RST_GET(ptr->USBCMD)) { + } + + /* Set mode to device, must be set immediately after reset */ + ptr->USBMODE &= ~USB_USBMODE_CM_MASK; + ptr->USBMODE |= USB_USBMODE_CM_SET(2); + + /* Disable setup lockout, please refer to "Control Endpoint Operation" section in RM. */ + ptr->USBMODE &= ~USB_USBMODE_SLOM_MASK; + + /* Set the endian */ + ptr->USBMODE &= ~USB_USBMODE_ES_MASK; + + /* Set parallel interface signal */ + ptr->PORTSC1 &= ~USB_PORTSC1_STS_MASK; + + /* Set parallel transceiver width */ + ptr->PORTSC1 &= ~USB_PORTSC1_PTW_MASK; + + /* Set usb forced to full speed mode */ + //ptr->PORTSC1 |= USB_PORTSC1_PFSC_MASK; + + /* Not use interrupt threshold. */ + ptr->USBCMD &= ~USB_USBCMD_ITC_MASK; + + /* Enable VBUS discharge */ + ptr->OTGSC |= USB_OTGSC_VD_MASK; +} + +static void chipidea_deinit(CHIPIDEA_TypeDef *ptr) +{ + /* Stop */ + ptr->USBCMD &= ~USB_USBCMD_RS_MASK; + + /* Reset controller */ + ptr->USBCMD |= USB_USBCMD_RST_MASK; + while (USB_USBCMD_RST_GET(ptr->USBCMD)) { + } + + /* Reset endpoint list address register */ + ptr->ENDPTLISTADDR = 0; + + /* Reset status register */ + ptr->USBSTS = ptr->USBSTS; + + /* Reset interrupt enable register */ + ptr->USBINTR = 0; +} + +/*--------------------------------------------------------------------- + * Endpoint API + *--------------------------------------------------------------------- + */ +static void __chipidea_edpt_open(CHIPIDEA_TypeDef *ptr, uint8_t ep_addr, uint8_t ep_type) +{ + uint8_t const epnum = ep_addr & 0x0f; + uint8_t const dir = (ep_addr & 0x80) >> 7; + + /* Enable EP Control */ + uint32_t temp = ptr->ENDPTCTRL[epnum]; + temp &= ~((0x03 << 2) << (dir ? 16 : 0)); + temp |= ((ep_type << 2) | ENDPTCTRL_ENABLE | ENDPTCTRL_TOGGLE_RESET) << (dir ? 16 : 0); + ptr->ENDPTCTRL[epnum] = temp; +} + +static void chipidea_edpt_xfer(CHIPIDEA_TypeDef *ptr, uint8_t ep_idx) +{ + uint32_t offset = ep_idx / 2 + ((ep_idx % 2) ? 16 : 0); + + /* Start transfer */ + ptr->ENDPTPRIME = 1 << offset; +} + +static void chipidea_edpt_stall(CHIPIDEA_TypeDef *ptr, uint8_t ep_addr) +{ + uint8_t const epnum = ep_addr & 0x0f; + uint8_t const dir = (ep_addr & 0x80) >> 7; + + ptr->ENDPTCTRL[epnum] |= ENDPTCTRL_STALL << (dir ? 16 : 0); +} + +static void chipidea_edpt_clear_stall(CHIPIDEA_TypeDef *ptr, uint8_t ep_addr) +{ + uint8_t const epnum = ep_addr & 0x0f; + uint8_t const dir = (ep_addr & 0x80) >> 7; + + /* data toggle also need to be reset */ + ptr->ENDPTCTRL[epnum] |= ENDPTCTRL_TOGGLE_RESET << (dir ? 16 : 0); + ptr->ENDPTCTRL[epnum] &= ~(ENDPTCTRL_STALL << (dir ? 16 : 0)); +} + +static bool chipidea_edpt_check_stall(CHIPIDEA_TypeDef *ptr, uint8_t ep_addr) +{ + uint8_t const epnum = ep_addr & 0x0f; + uint8_t const dir = (ep_addr & 0x80) >> 7; + + return (ptr->ENDPTCTRL[epnum] & (ENDPTCTRL_STALL << (dir ? 16 : 0))) ? true : false; +} + +static void chipidea_edpt_close(CHIPIDEA_TypeDef *ptr, uint8_t ep_addr) +{ + uint8_t const epnum = ep_addr & 0x0f; + uint8_t const dir = (ep_addr & 0x80) >> 7; + + uint32_t primebit = CHIPIDEA_BITSMASK(1, epnum) << (dir ? 16 : 0); + + /* Flush the endpoint to stop a transfer. */ + do { + /* Set the corresponding bit(s) in the ENDPTFLUSH register */ + ptr->ENDPTFLUSH |= primebit; + + /* Wait until all bits in the ENDPTFLUSH register are cleared. */ + while (0U != (ptr->ENDPTFLUSH & primebit)) { + } + /* + * Read the ENDPTSTAT register to ensure that for all endpoints + * commanded to be flushed, that the corresponding bits + * are now cleared. + */ + } while (0U != (ptr->ENDPTSTAT & primebit)); + + /* Disable the endpoint */ + ptr->ENDPTCTRL[epnum] &= ~((ENDPTCTRL_TYPE | ENDPTCTRL_ENABLE | ENDPTCTRL_STALL) << (dir ? 16 : 0)); + ptr->ENDPTCTRL[epnum] |= (USB_ENDPOINT_TYPE_BULK << 2) << (dir ? 16 : 0); +} + +/* Initialize qtd */ +static void usb_qtd_init(dcd_qtd_t *p_qtd, void *data_ptr, uint16_t total_bytes) +{ + memset(p_qtd, 0, sizeof(dcd_qtd_t)); + + p_qtd->next = 1; + p_qtd->active = 1; + p_qtd->total_bytes = p_qtd->expected_bytes = total_bytes; + + if (data_ptr != NULL) { + p_qtd->buffer[0] = (uint32_t)data_ptr; + for (uint8_t i = 1; i < 5; i++) { + p_qtd->buffer[i] = ((p_qtd->buffer[i - 1]) & 0xFFFFF000UL) + 4096U; + } + } +} + +static dcd_qhd_t *chipidea_qhd_get(uint8_t busid, uint8_t ep_idx) +{ + dcd_data_t *dcd_data; + + dcd_data = g_chipidea_udc[busid].dcd_data; + return &dcd_data->qhd[ep_idx]; +} + +static dcd_qtd_t *chipidea_qtd_get(uint8_t busid, uint8_t ep_idx) +{ + dcd_data_t *dcd_data; + + dcd_data = g_chipidea_udc[busid].dcd_data; + return &dcd_data->qtd[ep_idx * QTD_COUNT_EACH_ENDPOINT]; +} + +static void chipidea_bus_reset(uint8_t busid, uint16_t ep0_max_packet_size) +{ + dcd_data_t *dcd_data; + + dcd_data = g_chipidea_udc[busid].dcd_data; + __chipidea_bus_reset(USB_OTG_DEV); + + /* Queue Head & Queue TD */ + memset(dcd_data, 0, sizeof(dcd_data_t)); + + /* Set up Control Endpoints (0 OUT, 1 IN) */ + dcd_data->qhd[0].zero_length_termination = dcd_data->qhd[1].zero_length_termination = 1; + dcd_data->qhd[0].max_packet_size = dcd_data->qhd[1].max_packet_size = ep0_max_packet_size; + dcd_data->qhd[0].qtd_overlay.next = dcd_data->qhd[1].qtd_overlay.next = 1; + + /* OUT only */ + dcd_data->qhd[0].int_on_setup = 1; +} + +static void chipidea_edpt_open(uint8_t busid, uint8_t ep_addr, uint8_t ep_type, uint16_t ep_mps) +{ + uint8_t const epnum = ep_addr & 0x0f; + uint8_t const dir = (ep_addr & 0x80) >> 7; + uint8_t const ep_idx = 2 * epnum + dir; + dcd_data_t *dcd_data; + dcd_qhd_t *p_qhd; + + /* Prepare Queue Head */ + dcd_data = g_chipidea_udc[busid].dcd_data; + p_qhd = &dcd_data->qhd[ep_idx]; + memset(p_qhd, 0, sizeof(dcd_qhd_t)); + + p_qhd->zero_length_termination = 1; + p_qhd->max_packet_size = ep_mps & 0x7FFu; + p_qhd->qtd_overlay.next = 1; + if (ep_type == USB_ENDPOINT_TYPE_ISOCHRONOUS) { + p_qhd->iso_mult = ((ep_mps >> 11u) & 0x3u) + 1u; + } + + __chipidea_edpt_open(USB_OTG_DEV, ep_addr, ep_type); +} + +static bool chipidea_start_xfer(uint8_t busid, uint8_t ep_addr, uint8_t *buffer, uint32_t total_bytes) +{ + uint8_t const epnum = ep_addr & 0x0f; + uint8_t const dir = (ep_addr & 0x80) >> 7; + uint8_t const ep_idx = 2 * epnum + dir; + uint8_t qtd_num; + uint8_t i; + uint32_t xfer_len; + dcd_qhd_t *p_qhd; + dcd_qtd_t *p_qtd; + dcd_qtd_t *first_p_qtd = NULL; + dcd_qtd_t *prev_p_qtd = NULL; + dcd_data_t *dcd_data; + + dcd_data = g_chipidea_udc[busid].dcd_data; + + if (epnum == 0) { + /* follows UM Setup packet handling using setup lockout mechanism + * wait until ENDPTSETUPSTAT before priming data/status in response TODO add time out + */ + while (USB_OTG_DEV->ENDPTSETUPSTAT & CHIPIDEA_BITSMASK(1, 0)) { + } + } + + qtd_num = (total_bytes + 0x3fff) / 0x4000; + if (qtd_num > QTD_COUNT_EACH_ENDPOINT) { + return false; + } + + if (buffer != NULL) { + buffer = (uint8_t *)buffer; + } + p_qhd = &dcd_data->qhd[ep_idx]; + i = 0; + do { + p_qtd = &dcd_data->qtd[ep_idx * QTD_COUNT_EACH_ENDPOINT + i]; + i++; + + if (total_bytes > 0x4000) { + xfer_len = 0x4000; + total_bytes -= 0x4000; + } else { + xfer_len = total_bytes; + total_bytes = 0; + } + + usb_qtd_init(p_qtd, (void *)buffer, xfer_len); + if (total_bytes == 0) { + p_qtd->int_on_complete = true; + } + buffer += xfer_len; + + if (prev_p_qtd) { + prev_p_qtd->next = (uint32_t)p_qtd; + } else { + first_p_qtd = p_qtd; + } + prev_p_qtd = p_qtd; + } while (total_bytes > 0); + + p_qhd->qtd_overlay.next = (uint32_t)first_p_qtd; /* link qtd to qhd */ + + chipidea_edpt_xfer(USB_OTG_DEV, ep_idx); + + return true; +} + +__WEAK void usb_dc_low_level_init(uint8_t busid) +{ +} + +__WEAK void usb_dc_low_level_deinit(uint8_t busid) +{ +} + +int usb_dc_init(uint8_t busid) +{ + uint32_t int_mask; + int_mask = (USB_USBINTR_UE_MASK | USB_USBINTR_UEE_MASK | USB_USBINTR_SLE_MASK | + USB_USBINTR_PCE_MASK | USB_USBINTR_URE_MASK); + + usb_dc_low_level_init(busid); + + memset(&g_chipidea_udc[busid], 0, sizeof(struct chipidea_udc)); + g_chipidea_udc[busid].dcd_data = g_dcd_data[busid]; + memset(g_chipidea_udc[busid].dcd_data, 0, sizeof(dcd_data_t)); + + chipidea_init(USB_OTG_DEV); + + /* Set endpoint list address */ + USB_OTG_DEV->ENDPTLISTADDR = ((uint32_t)g_chipidea_udc[busid].dcd_data->qhd) & USB_ENDPTLISTADDR_EPBASE_MASK; + + /* Clear status */ + USB_OTG_DEV->USBSTS = USB_OTG_DEV->USBSTS; + +#ifdef CONFIG_USBDEV_SOF_ENABLE + int_mask |= USB_USBINTR_SRE_MASK; +#endif + + /* Enable interrupt mask */ + USB_OTG_DEV->USBINTR |= int_mask; + + /* Connect by enabling internal pull-up resistor on D+/D- */ + USB_OTG_DEV->USBCMD |= USB_USBCMD_RS_MASK; + return 0; +} + +int usb_dc_deinit(uint8_t busid) +{ + chipidea_deinit(USB_OTG_DEV); + + for (uint32_t i = 0; i < CONFIG_USBDEV_EP_NUM; i++) { + chipidea_edpt_close(USB_OTG_DEV, (i | 0x80)); + chipidea_edpt_close(USB_OTG_DEV, (i | 0x00)); + } + + usb_dc_low_level_deinit(busid); + return 0; +} + +int usbd_set_address(uint8_t busid, const uint8_t addr) +{ + USB_OTG_DEV->DEVICEADDR = USB_DEVICEADDR_USBADR_SET(addr) | USB_DEVICEADDR_USBADRA_MASK; + return 0; +} + +int usbd_set_remote_wakeup(uint8_t busid) +{ + if (!USB_PORTSC1_SUSP_GET(USB_OTG_DEV->PORTSC1)) { + return -1; + } + + USB_OTG_DEV->PORTSC1 |= USB_PORTSC1_FPR_MASK; + while (USB_OTG_DEV->PORTSC1 & USB_PORTSC1_FPR_MASK) { + } + + return 0; +} + +uint8_t usbd_get_port_speed(uint8_t busid) +{ + uint8_t speed; + + speed = USB_PORTSC1_PSPD_GET(USB_OTG_DEV->PORTSC1); + + if (speed == 0x00) { + return USB_SPEED_FULL; + } + if (speed == 0x01) { + return USB_SPEED_LOW; + } + if (speed == 0x02) { + return USB_SPEED_HIGH; + } + + return 0; +} + +int usbd_ep_open(uint8_t busid, const struct usb_endpoint_descriptor *ep) +{ + uint8_t ep_idx = USB_EP_GET_IDX(ep->bEndpointAddress); + + USB_ASSERT_MSG(ep_idx < CONFIG_USBDEV_EP_NUM, "Ep addr %02x overflow", ep->bEndpointAddress); + + chipidea_edpt_open(busid, ep->bEndpointAddress, USB_GET_ENDPOINT_TYPE(ep->bmAttributes), ep->wMaxPacketSize); + + if (USB_EP_DIR_IS_OUT(ep->bEndpointAddress)) { + g_chipidea_udc[busid].out_ep[ep_idx].ep_mps = USB_GET_MAXPACKETSIZE(ep->wMaxPacketSize); + g_chipidea_udc[busid].out_ep[ep_idx].ep_type = USB_GET_ENDPOINT_TYPE(ep->bmAttributes); + g_chipidea_udc[busid].out_ep[ep_idx].ep_enable = true; + } else { + g_chipidea_udc[busid].in_ep[ep_idx].ep_mps = USB_GET_MAXPACKETSIZE(ep->wMaxPacketSize); + g_chipidea_udc[busid].in_ep[ep_idx].ep_type = USB_GET_ENDPOINT_TYPE(ep->bmAttributes); + g_chipidea_udc[busid].in_ep[ep_idx].ep_enable = true; + } + + return 0; +} + +int usbd_ep_close(uint8_t busid, const uint8_t ep) +{ + uint8_t ep_idx = USB_EP_GET_IDX(ep); + + if (USB_EP_DIR_IS_OUT(ep)) { + g_chipidea_udc[busid].out_ep[ep_idx].ep_enable = false; + } else { + g_chipidea_udc[busid].in_ep[ep_idx].ep_enable = false; + } + + chipidea_edpt_close(USB_OTG_DEV, ep); + + return 0; +} + +int usbd_ep_set_stall(uint8_t busid, const uint8_t ep) +{ + chipidea_edpt_stall(USB_OTG_DEV, ep); + return 0; +} + +int usbd_ep_clear_stall(uint8_t busid, const uint8_t ep) +{ + chipidea_edpt_clear_stall(USB_OTG_DEV, ep); + return 0; +} + +int usbd_ep_is_stalled(uint8_t busid, const uint8_t ep, uint8_t *stalled) +{ + *stalled = chipidea_edpt_check_stall(USB_OTG_DEV, ep); + return 0; +} + +int usbd_ep_start_write(uint8_t busid, const uint8_t ep, const uint8_t *data, uint32_t data_len) +{ + uint8_t ep_idx = USB_EP_GET_IDX(ep); + + if (!data && data_len) { + return -1; + } + if (!g_chipidea_udc[busid].in_ep[ep_idx].ep_enable) { + return -2; + } + +#ifdef CONFIG_USB_DCACHE_ENABLE + USB_ASSERT_MSG(!((uintptr_t)data % CONFIG_USB_ALIGN_SIZE), "data is not aligned %d", CONFIG_USB_ALIGN_SIZE); +#endif + + g_chipidea_udc[busid].in_ep[ep_idx].xfer_buf = (uint8_t *)data; + g_chipidea_udc[busid].in_ep[ep_idx].xfer_len = data_len; + g_chipidea_udc[busid].in_ep[ep_idx].actual_xfer_len = 0; + + usb_dcache_clean((uintptr_t)data, USB_ALIGN_UP(data_len, CONFIG_USB_ALIGN_SIZE)); + chipidea_start_xfer(busid, ep, (uint8_t *)data, data_len); + + return 0; +} + +int usbd_ep_start_read(uint8_t busid, const uint8_t ep, uint8_t *data, uint32_t data_len) +{ + uint8_t ep_idx = USB_EP_GET_IDX(ep); + + if (!data && data_len) { + return -1; + } + if (!g_chipidea_udc[busid].out_ep[ep_idx].ep_enable) { + return -2; + } + +#ifdef CONFIG_USB_DCACHE_ENABLE + USB_ASSERT_MSG(!((uintptr_t)data % CONFIG_USB_ALIGN_SIZE), "data is not aligned %d", CONFIG_USB_ALIGN_SIZE); +#endif + + g_chipidea_udc[busid].out_ep[ep_idx].xfer_buf = (uint8_t *)data; + g_chipidea_udc[busid].out_ep[ep_idx].xfer_len = data_len; + g_chipidea_udc[busid].out_ep[ep_idx].actual_xfer_len = 0; + + usb_dcache_invalidate((uintptr_t)data, USB_ALIGN_UP(data_len, CONFIG_USB_ALIGN_SIZE)); + chipidea_start_xfer(busid, ep, data, data_len); + + return 0; +} + +void USBD_IRQHandler(uint8_t busid) +{ + uint32_t int_status; + uint32_t transfer_len; + bool ep_cb_req; + + /* Acknowledge handled interrupt */ + int_status = USB_OTG_DEV->USBSTS; + int_status &= USB_OTG_DEV->USBINTR; + USB_OTG_DEV->USBSTS = int_status; + + if (int_status & intr_error) { + USB_LOG_ERR("usbd intr error!\r\n"); + } + +#ifdef CONFIG_USBDEV_SOF_ENABLE + if (int_status & intr_sof) { + usbd_event_sof_handler(busid); + } +#endif + + if (int_status & intr_reset) { + g_chipidea_udc[busid].is_suspend = false; + memset(g_chipidea_udc[busid].in_ep, 0, sizeof(struct chipidea_ep_state) * CONFIG_USBDEV_EP_NUM); + memset(g_chipidea_udc[busid].out_ep, 0, sizeof(struct chipidea_ep_state) * CONFIG_USBDEV_EP_NUM); + usbd_event_reset_handler(busid); + chipidea_bus_reset(busid, g_chipidea_udc[busid].in_ep[0].ep_mps); + } + + if (int_status & intr_suspend) { + if (USB_PORTSC1_SUSP_GET(USB_OTG_DEV->PORTSC1)) { + /* Note: Host may delay more than 3 ms before and/or after bus reset before doing enumeration. */ + if (USB_DEVICEADDR_USBADR_GET(USB_OTG_DEV->DEVICEADDR)) { + g_chipidea_udc[busid].is_suspend = true; + usbd_event_suspend_handler(busid); + } + } else { + } + } + + if (int_status & intr_port_change) { + if (!USB_PORTSC1_CCS_GET(USB_OTG_DEV->PORTSC1)) { + usbd_event_disconnect_handler(busid); + } else { + if (g_chipidea_udc[busid].is_suspend) { + g_chipidea_udc[busid].is_suspend = false; + usbd_event_resume_handler(busid); + } + usbd_event_connect_handler(busid); + } + } + + if (int_status & intr_usb) { + uint32_t const edpt_complete = USB_OTG_DEV->ENDPTCOMPLETE; + uint32_t edpt_setup_status = USB_OTG_DEV->ENDPTSETUPSTAT; + + if (edpt_complete) { + USB_OTG_DEV->ENDPTCOMPLETE = edpt_complete; + for (uint8_t ep_idx = 0; ep_idx < (CONFIG_USBDEV_EP_NUM * 2); ep_idx++) { + if (edpt_complete & (1 << ep_idx2bit(ep_idx))) { + transfer_len = 0; + ep_cb_req = true; + + /* Failed QTD also get ENDPTCOMPLETE set */ + dcd_qtd_t *p_qtd = chipidea_qtd_get(busid, ep_idx); + while (1) { + if (p_qtd->halted || p_qtd->xact_err || p_qtd->buffer_err) { + USB_LOG_ERR("usbd transfer error!\r\n"); + ep_cb_req = false; + break; + } else if (p_qtd->active) { + ep_cb_req = false; + break; + } else { + transfer_len += p_qtd->expected_bytes - p_qtd->total_bytes; + } + + if (p_qtd->next == 1) { + break; + } else { + p_qtd = (dcd_qtd_t *)p_qtd->next; + } + } + + if (ep_cb_req) { + uint8_t const ep_addr = (ep_idx / 2) | ((ep_idx & 0x01) ? 0x80 : 0); + if (ep_addr & 0x80) { + usbd_event_ep_in_complete_handler(busid, ep_addr, transfer_len); + } else { + usb_dcache_invalidate((uintptr_t)g_chipidea_udc[busid].out_ep[ep_idx / 2].xfer_buf, USB_ALIGN_UP(transfer_len, CONFIG_USB_ALIGN_SIZE)); + usbd_event_ep_out_complete_handler(busid, ep_addr, transfer_len); + } + } + } + } + } + + if (edpt_setup_status) { + /*------------- Set up Received -------------*/ + USB_OTG_DEV->ENDPTSETUPSTAT = edpt_setup_status; + dcd_qhd_t *qhd0 = chipidea_qhd_get(busid, 0); + usbd_event_ep0_setup_complete_handler(busid, (uint8_t *)&qhd0->setup_request); + } + } +} \ No newline at end of file diff --git a/kernel/cherryusb/port/dwc2/README.md b/kernel/cherryusb/port/dwc2/README.md new file mode 100644 index 0000000..db82c6c --- /dev/null +++ b/kernel/cherryusb/port/dwc2/README.md @@ -0,0 +1,55 @@ +# Note + +Please note that host must support dma mode. + +## Support Chip List + +### STM32 + +**有且仅有 PB14/PB15 引脚支持 host 模式, 部分 F7/H7 可能 PA11/PA12 也支持**。 + +- STM32F105xc、STM32F107xc +- STM32F205xx、STM32F207xx、STM32F215xx、STM32F217xx +- STM32F401xc、STM32F401xe、STM32F405xx、STM32F407xx、STM32F411xe、STM32F412cx、STM32F412rx、STM32F412vx、STM32F412zx、STM32F413xx、STM32F415xx、STM32F417xx、STM32F423xx、STM32F423xx、STM32F429xx、STM32F437xx、STM32F439xx、STM32F446xx、STM32F469xx、STM32F479xx +- STM32F7xx +- STM32H7xx +- STM32L4xx +- STM32U5xx + +### AT32 + +**有且仅有 AT32F405xx PB14/PB15引脚支持 host 模式**。 + +- AT32F402xx、AT32F405xx、AT32F415xx、AT32F423xx、AT32F425xx、AT32F435xx、AT32F437xx + +### GD32 + +**由于无法读取 DWC2 配置信息，并且有部分寄存器是非标准的，因此暂时无法支持 GD 系列**。 + +- GD32F30X_CL +- GD32F405、GD32F407 +- GD32F350、GD32F450 + +### HC32 + +- HC32F4A0 + +### Espressif + +- ESP32S2、ESP32S3、ESP32P4 + +### Sophgo + +- CV18xx + +### Kendryte + +- K230 + +### Nationstech + +- N32H4X + +### Infineon + +- PSOC Edge E8X \ No newline at end of file diff --git a/kernel/cherryusb/port/dwc2/usb_dc_dwc2.c b/kernel/cherryusb/port/dwc2/usb_dc_dwc2.c new file mode 100644 index 0000000..92479c8 --- /dev/null +++ b/kernel/cherryusb/port/dwc2/usb_dc_dwc2.c @@ -0,0 +1,1221 @@ +/* + * Copyright (c) 2022, sakumisu + * + * SPDX-License-Identifier: Apache-2.0 + */ +#include "usbd_core.h" +#include "usb_dwc2_reg.h" +#include "usb_dwc2_param.h" + +#define USBD_BASE (g_usbdev_bus[busid].reg_base) + +#define USB_OTG_GLB ((DWC2_GlobalTypeDef *)(USBD_BASE)) +#define USB_OTG_DEV ((DWC2_DeviceTypeDef *)(USBD_BASE + USB_OTG_DEVICE_BASE)) +#define USB_OTG_PCGCCTL *(__IO uint32_t *)((uint32_t)USBD_BASE + USB_OTG_PCGCCTL_BASE) +#define USB_OTG_INEP(i) ((DWC2_INEndpointTypeDef *)(USBD_BASE + USB_OTG_IN_ENDPOINT_BASE + ((i)*USB_OTG_EP_REG_SIZE))) +#define USB_OTG_OUTEP(i) ((DWC2_OUTEndpointTypeDef *)(USBD_BASE + USB_OTG_OUT_ENDPOINT_BASE + ((i)*USB_OTG_EP_REG_SIZE))) +#define USB_OTG_FIFO(i) *(__IO uint32_t *)(USBD_BASE + USB_OTG_FIFO_BASE + ((i)*USB_OTG_FIFO_SIZE)) + +/* Endpoint state */ +struct dwc2_ep_state { + uint16_t ep_mps; /* Endpoint max packet size */ + uint8_t ep_type; /* Endpoint type */ + uint8_t ep_stalled; /* Endpoint stall flag */ + uint8_t *xfer_buf; + uint32_t xfer_len; + uint32_t actual_xfer_len; +}; + +/* Driver state */ +USB_NOCACHE_RAM_SECTION struct dwc2_udc { + USB_MEM_ALIGNX struct usb_setup_packet setup; + USB_MEM_ALIGNX uint8_t pad; /* Pad to CONFIG_USB_ALIGN_SIZE bytes */ + struct dwc2_hw_params hw_params; + struct dwc2_user_params user_params; + struct dwc2_ep_state in_ep[16]; /*!< IN endpoint parameters*/ + struct dwc2_ep_state out_ep[16]; /*!< OUT endpoint parameters */ +} g_dwc2_udc[CONFIG_USBDEV_MAX_BUS]; + +static inline int dwc2_reset(uint8_t busid) +{ + volatile uint32_t count = 0U; + + /* Wait for AHB master IDLE state. */ + do { + if (++count > 200000U) { + return -1; + } + } while ((USB_OTG_GLB->GRSTCTL & USB_OTG_GRSTCTL_AHBIDL) == 0U); + + /* Core Soft Reset */ + count = 0U; + USB_OTG_GLB->GRSTCTL |= USB_OTG_GRSTCTL_CSRST; + + if (g_dwc2_udc[busid].hw_params.snpsid < 0x4F54420AU) { + do { + if (++count > 200000U) { + USB_LOG_ERR("DWC2 reset timeout\r\n"); + return -1; + } + } while ((USB_OTG_GLB->GRSTCTL & USB_OTG_GRSTCTL_CSRST) == USB_OTG_GRSTCTL_CSRST); + } else { + do { + if (++count > 200000U) { + USB_LOG_ERR("DWC2 reset timeout\r\n"); + return -1; + } + } while ((USB_OTG_GLB->GRSTCTL & USB_OTG_GRSTCTL_CSRSTDONE) != USB_OTG_GRSTCTL_CSRSTDONE); + + USB_OTG_GLB->GRSTCTL &= ~USB_OTG_GRSTCTL_CSRST; + USB_OTG_GLB->GRSTCTL |= USB_OTG_GRSTCTL_CSRSTDONE; + } + + return 0; +} + +static inline int dwc2_core_init(uint8_t busid) +{ + int ret; + uint32_t regval; + + if (g_dwc2_udc[busid].user_params.phy_type == DWC2_PHY_TYPE_PARAM_FS) { + /* Select FS Embedded PHY */ + USB_OTG_GLB->GUSBCFG |= USB_OTG_GUSBCFG_PHYSEL; + } else { + regval = USB_OTG_GLB->GUSBCFG; + regval &= ~USB_OTG_GUSBCFG_PHYSEL; + /* disable external vbus source */ + regval &= ~(USB_OTG_GUSBCFG_ULPIEVBUSD | USB_OTG_GUSBCFG_ULPIEVBUSI); + /* disable ULPI FS/LS */ + regval &= ~(USB_OTG_GUSBCFG_ULPIFSLS | USB_OTG_GUSBCFG_ULPICSM); + + switch (g_dwc2_udc[busid].user_params.phy_type) { + case DWC2_PHY_TYPE_PARAM_ULPI: + regval |= USB_OTG_GUSBCFG_ULPI_UTMI_SEL; + regval &= ~USB_OTG_GUSBCFG_PHYIF16; + regval &= ~USB_OTG_GUSBCFG_DDR_SEL; + + break; + case DWC2_PHY_TYPE_PARAM_UTMI: + regval &= ~USB_OTG_GUSBCFG_ULPI_UTMI_SEL; + regval &= ~USB_OTG_GUSBCFG_PHYIF16; + + if (g_dwc2_udc[busid].user_params.phy_utmi_width == 16) { + regval |= USB_OTG_GUSBCFG_PHYIF16; + } + break; + + default: + break; + } + USB_OTG_GLB->GUSBCFG = regval; + } + + /* Reset after a PHY select */ + ret = dwc2_reset(busid); + return ret; +} + +static inline void dwc2_set_mode(uint8_t busid, uint8_t mode) +{ + USB_OTG_GLB->GUSBCFG &= ~(USB_OTG_GUSBCFG_FHMOD | USB_OTG_GUSBCFG_FDMOD); + + if (mode == USB_OTG_MODE_HOST) { + USB_OTG_GLB->GUSBCFG |= USB_OTG_GUSBCFG_FHMOD; + } else if (mode == USB_OTG_MODE_DEVICE) { + USB_OTG_GLB->GUSBCFG |= USB_OTG_GUSBCFG_FDMOD; + } + + while (1) { + if ((USB_OTG_GLB->GINTSTS & 0x1U) == USB_OTG_MODE_DEVICE) { + break; + } + usbd_dwc2_delay_ms(10); + } +} + +static inline int dwc2_flush_rxfifo(uint8_t busid) +{ + volatile uint32_t count = 0U; + + /* Wait for AHB master IDLE state. */ + do { + if (++count > 200000U) { + return -1; + } + } while ((USB_OTG_GLB->GRSTCTL & USB_OTG_GRSTCTL_AHBIDL) == 0U); + + count = 0; + USB_OTG_GLB->GRSTCTL = USB_OTG_GRSTCTL_RXFFLSH; + + do { + if (++count > 200000U) { + return -1; + } + } while ((USB_OTG_GLB->GRSTCTL & USB_OTG_GRSTCTL_RXFFLSH) == USB_OTG_GRSTCTL_RXFFLSH); + + return 0; +} + +static inline int dwc2_flush_txfifo(uint8_t busid, uint32_t num) +{ + volatile uint32_t count = 0U; + + /* Wait for AHB master IDLE state. */ + do { + if (++count > 200000U) { + return -1; + } + } while ((USB_OTG_GLB->GRSTCTL & USB_OTG_GRSTCTL_AHBIDL) == 0U); + + count = 0; + USB_OTG_GLB->GRSTCTL = (USB_OTG_GRSTCTL_TXFFLSH | (num << 6)); + + do { + if (++count > 200000U) { + return -1; + } + } while ((USB_OTG_GLB->GRSTCTL & USB_OTG_GRSTCTL_TXFFLSH) == USB_OTG_GRSTCTL_TXFFLSH); + + return 0; +} + +static void dwc2_set_turnaroundtime(uint8_t busid, uint32_t hclk, uint8_t speed) +{ + uint32_t UsbTrd; + + /* The USBTRD is configured according to the tables below, depending on AHB frequency + used by application. In the low AHB frequency range it is used to stretch enough the USB response + time to IN tokens, the USB turnaround time, so to compensate for the longer AHB read access + latency to the Data FIFO */ + if (speed == USB_OTG_SPEED_FULL) { + if ((hclk >= 14200000U) && (hclk < 15000000U)) { + /* hclk Clock Range between 14.2-15 MHz */ + UsbTrd = 0xFU; + } else if ((hclk >= 15000000U) && (hclk < 16000000U)) { + /* hclk Clock Range between 15-16 MHz */ + UsbTrd = 0xEU; + } else if ((hclk >= 16000000U) && (hclk < 17200000U)) { + /* hclk Clock Range between 16-17.2 MHz */ + UsbTrd = 0xDU; + } else if ((hclk >= 17200000U) && (hclk < 18500000U)) { + /* hclk Clock Range between 17.2-18.5 MHz */ + UsbTrd = 0xCU; + } else if ((hclk >= 18500000U) && (hclk < 20000000U)) { + /* hclk Clock Range between 18.5-20 MHz */ + UsbTrd = 0xBU; + } else if ((hclk >= 20000000U) && (hclk < 21800000U)) { + /* hclk Clock Range between 20-21.8 MHz */ + UsbTrd = 0xAU; + } else if ((hclk >= 21800000U) && (hclk < 24000000U)) { + /* hclk Clock Range between 21.8-24 MHz */ + UsbTrd = 0x9U; + } else if ((hclk >= 24000000U) && (hclk < 27700000U)) { + /* hclk Clock Range between 24-27.7 MHz */ + UsbTrd = 0x8U; + } else if ((hclk >= 27700000U) && (hclk < 32000000U)) { + /* hclk Clock Range between 27.7-32 MHz */ + UsbTrd = 0x7U; + } else /* if(hclk >= 32000000) */ + { + /* hclk Clock Range between 32-200 MHz */ + UsbTrd = 0x6U; + } + } else if (speed == USB_OTG_SPEED_HIGH) { + UsbTrd = USBD_HS_TRDT_VALUE; + } else { + UsbTrd = USBD_DEFAULT_TRDT_VALUE; + } + + USB_OTG_GLB->GUSBCFG &= ~USB_OTG_GUSBCFG_TRDT; + USB_OTG_GLB->GUSBCFG |= (uint32_t)((UsbTrd << USB_OTG_GUSBCFG_TRDT_Pos) & USB_OTG_GUSBCFG_TRDT); +} + +static void dwc2_set_txfifo(uint8_t busid, uint8_t fifo, uint16_t size) +{ + uint8_t i; + uint32_t tx_offset; + + /* TXn min size = 16 words. (n : Transmit FIFO index) + When a TxFIFO is not used, the Configuration should be as follows: + case 1 : n > m and Txn is not used (n,m : Transmit FIFO indexes) + --> Txm can use the space allocated for Txn. + case2 : n < m and Txn is not used (n,m : Transmit FIFO indexes) + --> Txn should be configured with the minimum space of 16 words + The FIFO is used optimally when used TxFIFOs are allocated in the top + of the FIFO.Ex: use EP1 and EP2 as IN instead of EP1 and EP3 as IN ones. + When DMA is used 3n * FIFO locations should be reserved for internal DMA registers */ + + tx_offset = USB_OTG_GLB->GRXFSIZ; + + if (fifo == 0U) { + USB_OTG_GLB->DIEPTXF0_HNPTXFSIZ = ((uint32_t)size << 16) | tx_offset; + } else { + tx_offset += (USB_OTG_GLB->DIEPTXF0_HNPTXFSIZ) >> 16; + for (i = 0U; i < (fifo - 1U); i++) { + tx_offset += (USB_OTG_GLB->DIEPTXF[i] >> 16); + } + + /* Multiply Tx_Size by 2 to get higher performance */ + USB_OTG_GLB->DIEPTXF[fifo - 1U] = ((uint32_t)size << 16) | tx_offset; + } + + USB_LOG_INFO("fifo%d size:%04x, offset:%04x\r\n", fifo, size, tx_offset); +} + +static uint8_t dwc2_get_devspeed(uint8_t busid) +{ + uint8_t speed; + uint32_t DevEnumSpeed = USB_OTG_DEV->DSTS & USB_OTG_DSTS_ENUMSPD; + + if (DevEnumSpeed == DSTS_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ) { + speed = USB_OTG_SPEED_HIGH; + } else if ((DevEnumSpeed == DSTS_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ) || + (DevEnumSpeed == DSTS_ENUMSPD_FS_PHY_48MHZ)) { + speed = USB_OTG_SPEED_FULL; + } else { + speed = 0xFU; + } + + return speed; +} + +static void dwc2_ep0_start_read_setup(uint8_t busid, uint8_t *psetup) +{ + USB_OTG_OUTEP(0U)->DOEPTSIZ = (1U * 8U) | (1U << 19) | (1U << 29); + + if (g_dwc2_udc[busid].user_params.device_dma_enable) { + usb_dcache_invalidate((uintptr_t)&g_dwc2_udc[busid].setup, USB_ALIGN_UP(8, CONFIG_USB_ALIGN_SIZE)); + + USB_OTG_OUTEP(0U)->DOEPDMA = (uint32_t)psetup; + /* EP enable */ + USB_OTG_OUTEP(0U)->DOEPCTL |= USB_OTG_DOEPCTL_EPENA | USB_OTG_DOEPCTL_USBAEP; + } +} + +void dwc2_ep_write(uint8_t busid, uint8_t ep_idx, uint8_t *src, uint16_t len) +{ + uint32_t *p32; + uint8_t *p8; + uint32_t val; + uint8_t remain; + + p32 = (uint32_t *)src; + for (uint32_t i = 0U; i < (len / 4); i++) { + USB_OTG_FIFO((uint32_t)ep_idx) = *p32++; + } + + remain = len % 4; + + if (remain) { + p8 = (uint8_t *)p32; + val = (uint32_t)(*p8++); + + if (remain > 1) { + val |= (uint32_t)((*p8++) << 8); + } + + if (remain > 2) { + val |= (uint32_t)((*p8++) << 16); + } + + USB_OTG_FIFO((uint32_t)ep_idx) = val; + } +} + +void dwc2_ep_read(uint8_t busid, uint8_t *dest, uint16_t len) +{ + uint32_t *p32; + uint8_t *p8; + uint32_t val; + uint8_t remain; + + p32 = (uint32_t *)dest; + for (uint32_t i = 0U; i < (len / 4); i++) { + *p32++ = USB_OTG_FIFO(0U); + } + + remain = len % 4; + + if (remain) { + p8 = (uint8_t *)p32; + val = USB_OTG_FIFO(0U); + + *p8++ = (uint8_t)(val & 0xFFU); + + if (remain > 1) { + *p8++ = (uint8_t)((val >> 8) & 0xFFU); + } + + if (remain > 2) { + *p8++ = (uint8_t)((val >> 16) & 0xFFU); + } + } +} + +static void dwc2_tx_fifo_empty_procecss(uint8_t busid, uint8_t ep_idx) +{ + uint32_t len; + uint32_t len32b; + uint32_t fifoemptymsk; + + len = g_dwc2_udc[busid].in_ep[ep_idx].xfer_len - g_dwc2_udc[busid].in_ep[ep_idx].actual_xfer_len; + if (len > g_dwc2_udc[busid].in_ep[ep_idx].ep_mps) { + len = g_dwc2_udc[busid].in_ep[ep_idx].ep_mps; + } + + len32b = (len + 3U) / 4U; + + while (((USB_OTG_INEP(ep_idx)->DTXFSTS & USB_OTG_DTXFSTS_INEPTFSAV) >= len32b) && + (g_dwc2_udc[busid].in_ep[ep_idx].actual_xfer_len < g_dwc2_udc[busid].in_ep[ep_idx].xfer_len) && (g_dwc2_udc[busid].in_ep[ep_idx].xfer_len != 0U)) { + /* Write the FIFO */ + len = g_dwc2_udc[busid].in_ep[ep_idx].xfer_len - g_dwc2_udc[busid].in_ep[ep_idx].actual_xfer_len; + if (len > g_dwc2_udc[busid].in_ep[ep_idx].ep_mps) { + len = g_dwc2_udc[busid].in_ep[ep_idx].ep_mps; + } + if (g_dwc2_udc[busid].in_ep[ep_idx].ep_type == USB_ENDPOINT_TYPE_ISOCHRONOUS) { + if ((USB_OTG_DEV->DSTS & (1U << 8)) == 0U) { + USB_OTG_INEP(ep_idx)->DIEPCTL &= ~USB_OTG_DIEPCTL_SD0PID_SEVNFRM; + USB_OTG_INEP(ep_idx)->DIEPCTL |= USB_OTG_DIEPCTL_SODDFRM; + } else { + USB_OTG_INEP(ep_idx)->DIEPCTL &= ~USB_OTG_DIEPCTL_SODDFRM; + USB_OTG_INEP(ep_idx)->DIEPCTL |= USB_OTG_DIEPCTL_SD0PID_SEVNFRM; + } + USB_OTG_INEP(ep_idx)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_MULCNT); + USB_OTG_INEP(ep_idx)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_MULCNT & (1U << 29)); + } + + dwc2_ep_write(busid, ep_idx, g_dwc2_udc[busid].in_ep[ep_idx].xfer_buf, len); + g_dwc2_udc[busid].in_ep[ep_idx].xfer_buf += len; + g_dwc2_udc[busid].in_ep[ep_idx].actual_xfer_len += len; + } + + if (g_dwc2_udc[busid].in_ep[ep_idx].xfer_len <= g_dwc2_udc[busid].in_ep[ep_idx].actual_xfer_len) { + fifoemptymsk = (uint32_t)(0x1UL << (ep_idx & 0x0f)); + USB_OTG_DEV->DIEPEMPMSK &= ~fifoemptymsk; + } +} + +/** + * @brief dwc2_get_glb_intstatus: return the global USB interrupt status + * @retval status + */ +static inline uint32_t dwc2_get_glb_intstatus(uint8_t busid) +{ + uint32_t tmpreg; + + tmpreg = USB_OTG_GLB->GINTSTS; + tmpreg &= USB_OTG_GLB->GINTMSK; + + return tmpreg; +} + +/** + * @brief dwc2_get_outeps_intstatus: return the USB device OUT endpoints interrupt status + * @retval status + */ +static inline uint32_t dwc2_get_outeps_intstatus(uint8_t busid) +{ + uint32_t tmpreg; + + tmpreg = USB_OTG_DEV->DAINT; + tmpreg &= USB_OTG_DEV->DAINTMSK; + + return ((tmpreg & 0xffff0000U) >> 16); +} + +/** + * @brief dwc2_get_ineps_intstatus: return the USB device IN endpoints interrupt status + * @retval status + */ +static inline uint32_t dwc2_get_ineps_intstatus(uint8_t busid) +{ + uint32_t tmpreg; + + tmpreg = USB_OTG_DEV->DAINT; + tmpreg &= USB_OTG_DEV->DAINTMSK; + + return ((tmpreg & 0xFFFFU)); +} + +/** + * @brief Returns Device OUT EP Interrupt register + * @param epnum endpoint number + * This parameter can be a value from 0 to 15 + * @retval Device OUT EP Interrupt register + */ +static inline uint32_t dwc2_get_outep_intstatus(uint8_t busid, uint8_t epnum) +{ + uint32_t tmpreg; + + tmpreg = USB_OTG_OUTEP((uint32_t)epnum)->DOEPINT; + USB_OTG_OUTEP((uint32_t)epnum)->DOEPINT = tmpreg; + tmpreg = tmpreg & USB_OTG_DEV->DOEPMSK; + + return tmpreg; +} + +/** + * @brief Returns Device IN EP Interrupt register + * @param epnum endpoint number + * This parameter can be a value from 0 to 15 + * @retval Device IN EP Interrupt register + */ +static inline uint32_t dwc2_get_inep_intstatus(uint8_t busid, uint8_t epnum) +{ + uint32_t tmpreg, msk, emp; + + msk = USB_OTG_DEV->DIEPMSK; + emp = USB_OTG_DEV->DIEPEMPMSK; + msk |= ((emp >> (epnum & 0x0F)) & 0x1U) << 7; + + tmpreg = USB_OTG_INEP((uint32_t)epnum)->DIEPINT; + USB_OTG_INEP((uint32_t)epnum)->DIEPINT = tmpreg; + tmpreg = tmpreg & msk; + + return tmpreg; +} + +int usb_dc_init(uint8_t busid) +{ + int ret; + uint32_t fifo_num; + + memset(&g_dwc2_udc[busid], 0, sizeof(struct dwc2_udc)); + + usb_dc_low_level_init(busid); + + USB_LOG_INFO("========== dwc2 dcd params ==========\r\n"); + USB_LOG_INFO("CID:%08x\r\n", (unsigned int)USB_OTG_GLB->CID); + USB_LOG_INFO("GSNPSID:%08x\r\n", (unsigned int)USB_OTG_GLB->GSNPSID); + USB_LOG_INFO("GHWCFG1:%08x\r\n", (unsigned int)USB_OTG_GLB->GHWCFG1); + USB_LOG_INFO("GHWCFG2:%08x\r\n", (unsigned int)USB_OTG_GLB->GHWCFG2); + USB_LOG_INFO("GHWCFG3:%08x\r\n", (unsigned int)USB_OTG_GLB->GHWCFG3); + USB_LOG_INFO("GHWCFG4:%08x\r\n", (unsigned int)USB_OTG_GLB->GHWCFG4); + + dwc2_get_hwparams(USBD_BASE, &g_dwc2_udc[busid].hw_params); + dwc2_get_user_params(USBD_BASE, &g_dwc2_udc[busid].user_params); + + if (g_dwc2_udc[busid].user_params.phy_utmi_width == 0) { + g_dwc2_udc[busid].user_params.phy_utmi_width = 8; + } + if (g_dwc2_udc[busid].user_params.total_fifo_size == 0) { + g_dwc2_udc[busid].user_params.total_fifo_size = g_dwc2_udc[busid].hw_params.total_fifo_size; + } + + USB_LOG_INFO("dwc2 has %d endpoints and dfifo depth(32-bit words) is %d\r\n", + g_dwc2_udc[busid].hw_params.num_dev_ep + 1, + g_dwc2_udc[busid].user_params.total_fifo_size); + + USB_OTG_GLB->GAHBCFG &= ~USB_OTG_GAHBCFG_GINT; + + USB_OTG_DEV->DCTL |= USB_OTG_DCTL_SDIS; + + /* This is vendor register */ + USB_OTG_GLB->GCCFG = g_dwc2_udc[busid].user_params.device_gccfg; + + ret = dwc2_core_init(busid); + + /* Force Device Mode*/ + dwc2_set_mode(busid, USB_OTG_MODE_DEVICE); + + USB_ASSERT_MSG((USB_OTG_GLB->GRXFSIZ & 0xffff) >= g_dwc2_udc[busid].user_params.device_rx_fifo_size, + "device_rx_fifo_size cannot be larger than power_on_value %u", (unsigned int)(USB_OTG_GLB->GRXFSIZ & 0xffff)); + for (uint8_t i = 0; i < (g_dwc2_udc[busid].hw_params.num_dev_ep + 1); i++) { + uint16_t reset_txfifo_size; + if (i == 0) { + reset_txfifo_size = USB_OTG_GLB->DIEPTXF0_HNPTXFSIZ >> 16 & 0xffff; + } else { + reset_txfifo_size = USB_OTG_GLB->DIEPTXF[i - 1] >> 16 & 0xffff; + } + USB_ASSERT_MSG(reset_txfifo_size >= g_dwc2_udc[busid].user_params.device_tx_fifo_size[i], + "device_tx_fifo_size[%u] cannot be larger than power_on_value %u", i, reset_txfifo_size); + } + + if (g_dwc2_udc[busid].user_params.b_session_valid_override) { + /* B-peripheral session valid override enable */ + USB_OTG_GLB->GOTGCTL |= USB_OTG_GOTGCTL_BVALOEN; + USB_OTG_GLB->GOTGCTL |= USB_OTG_GOTGCTL_BVALOVAL; + } + + USB_OTG_GLB->GUSBCFG |= USB_OTG_GUSBCFG_TOCAL; + + for (uint8_t i = 0U; i < 15U; i++) { + USB_OTG_GLB->DIEPTXF[i] = 0U; + } + + /* Restart the Phy Clock */ + USB_OTG_PCGCCTL = 0U; + + /* Device speed configuration */ + USB_OTG_DEV->DCFG &= ~USB_OTG_DCFG_DSPD; + + if (g_dwc2_udc[busid].user_params.phy_type != DWC2_PHY_TYPE_PARAM_FS) { + USB_ASSERT_MSG(g_dwc2_udc[busid].hw_params.hs_phy_type != 0, "This dwc2 version does not support hs, so stop working"); + USB_OTG_DEV->DCFG |= USB_OTG_SPEED_HIGH; + } else { + if (g_dwc2_udc[busid].hw_params.hs_phy_type == 0) { + USB_OTG_DEV->DCFG |= USB_OTG_SPEED_FULL; + } else { + USB_OTG_DEV->DCFG |= USB_OTG_SPEED_HIGH_IN_FULL; + } + } + + /* Clear all pending Device Interrupts */ + USB_OTG_DEV->DIEPMSK = 0U; + USB_OTG_DEV->DOEPMSK = 0U; + USB_OTG_DEV->DAINTMSK = 0U; + + /* Disable all interrupts. */ + USB_OTG_GLB->GINTMSK = 0U; + /* Clear any pending interrupts */ + USB_OTG_GLB->GINTSTS = 0xBFFFFFFFU; + + /* Enable interrupts matching to the Device mode ONLY */ + USB_OTG_GLB->GINTMSK = USB_OTG_GINTMSK_USBRST | USB_OTG_GINTMSK_ENUMDNEM | + USB_OTG_GINTMSK_OEPINT | USB_OTG_GINTMSK_IEPINT | + USB_OTG_GINTMSK_USBSUSPM | USB_OTG_GINTMSK_WUIM; + + if (g_dwc2_udc[busid].user_params.device_dma_enable) { + USB_ASSERT_MSG(g_dwc2_udc[busid].hw_params.arch == GHWCFG2_INT_DMA_ARCH, "This dwc2 version does not support dma mode, so stop working"); + + USB_OTG_DEV->DCFG &= ~USB_OTG_DCFG_DESCDMA; + USB_OTG_GLB->GAHBCFG &= ~USB_OTG_GAHBCFG_HBSTLEN; + USB_OTG_GLB->GAHBCFG |= (USB_OTG_GAHBCFG_DMAEN | USB_OTG_GAHBCFG_HBSTLEN_4); + } else { + USB_OTG_GLB->GINTMSK |= USB_OTG_GINTMSK_RXFLVLM; + } + +#ifdef CONFIG_USBDEV_SOF_ENABLE + USB_OTG_GLB->GINTMSK |= USB_OTG_GINTMSK_SOFM; +#endif + + USB_OTG_GLB->GRXFSIZ = g_dwc2_udc[busid].user_params.device_rx_fifo_size; + + fifo_num = g_dwc2_udc[busid].user_params.device_rx_fifo_size; + for (uint8_t i = 0; i < (g_dwc2_udc[busid].hw_params.num_dev_ep + 1); i++) { + dwc2_set_txfifo(busid, i, g_dwc2_udc[busid].user_params.device_tx_fifo_size[i]); + fifo_num += g_dwc2_udc[busid].user_params.device_tx_fifo_size[i]; + + USB_ASSERT_MSG(fifo_num <= g_dwc2_udc[busid].user_params.total_fifo_size, "Your fifo config is overflow, please check"); + } + + if (g_dwc2_udc[busid].user_params.phy_type != DWC2_PHY_TYPE_PARAM_FS) { + USB_ASSERT_MSG(g_dwc2_udc[busid].user_params.device_rx_fifo_size >= (5 + 8 + 512 / 4 + 1 + 2 * 8 + 1), "Your rx fifo size config is invalid, please check"); + } else { + USB_ASSERT_MSG(g_dwc2_udc[busid].user_params.device_rx_fifo_size >= (5 + 8 + 64 / 4 + 1 + 2 * 8 + 1), "Your rx fifo size config is invalid, please check"); + } + + ret = dwc2_flush_txfifo(busid, 0x10U); + ret = dwc2_flush_rxfifo(busid); + + USB_OTG_GLB->GAHBCFG |= USB_OTG_GAHBCFG_GINT; + USB_OTG_DEV->DCTL &= ~USB_OTG_DCTL_SDIS; + + return ret; +} + +int usb_dc_deinit(uint8_t busid) +{ + USB_OTG_GLB->GAHBCFG &= ~USB_OTG_GAHBCFG_GINT; + USB_OTG_DEV->DCTL |= USB_OTG_DCTL_SDIS; + + /* Clear Pending interrupt */ + for (uint8_t i = 0U; i < 15U; i++) { + USB_OTG_INEP(i)->DIEPINT = 0xFB7FU; + USB_OTG_OUTEP(i)->DOEPINT = 0xFB7FU; + } + + /* Clear interrupt masks */ + USB_OTG_DEV->DIEPMSK = 0U; + USB_OTG_DEV->DOEPMSK = 0U; + USB_OTG_DEV->DAINTMSK = 0U; + + /* Disable all interrupts. */ + USB_OTG_GLB->GINTMSK = 0U; + /* Clear any pending interrupts */ + USB_OTG_GLB->GINTSTS = 0xBFFFFFFFU; + + /* Flush the FIFO */ + dwc2_flush_txfifo(busid, 0x10U); + dwc2_flush_rxfifo(busid); + + usb_dc_low_level_deinit(busid); + return 0; +} + +int usbd_set_address(uint8_t busid, const uint8_t addr) +{ + USB_OTG_DEV->DCFG &= ~(USB_OTG_DCFG_DAD); + USB_OTG_DEV->DCFG |= ((uint32_t)addr << 4) & USB_OTG_DCFG_DAD; + return 0; +} + +int usbd_set_remote_wakeup(uint8_t busid) +{ + if (!(USB_OTG_DEV->DSTS & USB_OTG_DSTS_SUSPSTS)) { + return -1; + } + USB_OTG_DEV->DCTL |= USB_OTG_DCTL_RWUSIG; + usbd_dwc2_delay_ms(10); + USB_OTG_DEV->DCTL &= ~USB_OTG_DCTL_RWUSIG; + return 0; +} + +uint8_t usbd_get_port_speed(uint8_t busid) +{ + uint8_t speed; + uint32_t DevEnumSpeed = USB_OTG_DEV->DSTS & USB_OTG_DSTS_ENUMSPD; + + if (DevEnumSpeed == DSTS_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ) { + speed = USB_SPEED_HIGH; + } else if ((DevEnumSpeed == DSTS_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ) || + (DevEnumSpeed == DSTS_ENUMSPD_FS_PHY_48MHZ)) { + speed = USB_SPEED_FULL; + } else { + speed = USB_SPEED_FULL; + } + + return speed; +} + +int usbd_ep_open(uint8_t busid, const struct usb_endpoint_descriptor *ep) +{ + uint8_t ep_idx = USB_EP_GET_IDX(ep->bEndpointAddress); + uint16_t ep_mps; + + USB_ASSERT_MSG(ep_idx < (g_dwc2_udc[busid].hw_params.num_dev_ep + 1), "Ep addr %02x overflow", ep->bEndpointAddress); + + if (USB_EP_DIR_IS_OUT(ep->bEndpointAddress)) { + g_dwc2_udc[busid].out_ep[ep_idx].ep_mps = USB_GET_MAXPACKETSIZE(ep->wMaxPacketSize); + g_dwc2_udc[busid].out_ep[ep_idx].ep_type = USB_GET_ENDPOINT_TYPE(ep->bmAttributes); + + ep_mps = USB_GET_MAXPACKETSIZE(ep->wMaxPacketSize); + if (ep_idx == 0) { + switch (ep_mps) { + case 64: + ep_mps = EP_MPS_64; + break; + case 32: + ep_mps = EP_MPS_32; + break; + case 16: + ep_mps = EP_MPS_16; + break; + case 8: + ep_mps = EP_MPS_8; + break; + + default: + ep_mps = EP_MPS_64; + break; + } + } + + USB_OTG_DEV->DAINTMSK |= USB_OTG_DAINTMSK_OEPM & (uint32_t)(1UL << (16 + ep_idx)); + + USB_OTG_OUTEP(ep_idx)->DOEPCTL |= (ep_mps & USB_OTG_DOEPCTL_MPSIZ) | + ((uint32_t)USB_GET_ENDPOINT_TYPE(ep->bmAttributes) << 18) | + USB_OTG_DIEPCTL_SD0PID_SEVNFRM | + USB_OTG_DOEPCTL_USBAEP; + } else { + uint16_t fifo_size; + if (ep_idx == 0) { + fifo_size = (USB_OTG_GLB->DIEPTXF0_HNPTXFSIZ >> 16); + } else { + fifo_size = (USB_OTG_GLB->DIEPTXF[ep_idx - 1U] >> 16); + } + + USB_ASSERT_MSG((fifo_size * 4) >= USB_GET_MAXPACKETSIZE(ep->wMaxPacketSize), "Ep addr %02x fifo overflow", ep->bEndpointAddress); + + g_dwc2_udc[busid].in_ep[ep_idx].ep_mps = USB_GET_MAXPACKETSIZE(ep->wMaxPacketSize); + g_dwc2_udc[busid].in_ep[ep_idx].ep_type = USB_GET_ENDPOINT_TYPE(ep->bmAttributes); + + ep_mps = USB_GET_MAXPACKETSIZE(ep->wMaxPacketSize); + if (ep_idx == 0) { + switch (ep_mps) { + case 64: + ep_mps = EP_MPS_64; + break; + case 32: + ep_mps = EP_MPS_32; + break; + case 16: + ep_mps = EP_MPS_16; + break; + case 8: + ep_mps = EP_MPS_8; + break; + + default: + ep_mps = EP_MPS_64; + break; + } + } + + USB_OTG_DEV->DAINTMSK |= USB_OTG_DAINTMSK_IEPM & (uint32_t)(1UL << ep_idx); + + USB_OTG_INEP(ep_idx)->DIEPCTL |= (ep_mps & USB_OTG_DIEPCTL_MPSIZ) | + ((uint32_t)USB_GET_ENDPOINT_TYPE(ep->bmAttributes) << 18) | (ep_idx << 22) | + USB_OTG_DIEPCTL_SD0PID_SEVNFRM | + USB_OTG_DIEPCTL_USBAEP; + dwc2_flush_txfifo(busid, ep_idx); + } + return 0; +} + +int usbd_ep_close(uint8_t busid, const uint8_t ep) +{ + uint8_t ep_idx = USB_EP_GET_IDX(ep); + volatile uint32_t count = 0U; + + if (USB_EP_DIR_IS_OUT(ep)) { + if (USB_OTG_OUTEP(ep_idx)->DOEPCTL & USB_OTG_DOEPCTL_EPENA) { + USB_OTG_OUTEP(ep_idx)->DOEPCTL |= USB_OTG_DOEPCTL_SNAK; + USB_OTG_OUTEP(ep_idx)->DOEPCTL |= USB_OTG_DOEPCTL_EPDIS; + + /* Wait for endpoint disabled interrupt */ + count = 0; + do { + if (++count > 50000) { + break; + } + } while ((USB_OTG_OUTEP(ep_idx)->DOEPINT & USB_OTG_DOEPINT_EPDISD) != USB_OTG_DOEPINT_EPDISD); + + /* Clear and unmask endpoint disabled interrupt */ + USB_OTG_OUTEP(ep_idx)->DOEPINT = USB_OTG_DOEPINT_EPDISD; + } + + USB_OTG_DEV->DEACHMSK &= ~(USB_OTG_DAINTMSK_OEPM & ((uint32_t)(1UL << (ep_idx & 0x07)) << 16)); + USB_OTG_DEV->DAINTMSK &= ~(USB_OTG_DAINTMSK_OEPM & ((uint32_t)(1UL << (ep_idx & 0x07)) << 16)); + USB_OTG_OUTEP(ep_idx)->DOEPCTL = 0; + } else { + if (USB_OTG_INEP(ep_idx)->DIEPCTL & USB_OTG_DIEPCTL_EPENA) { + USB_OTG_INEP(ep_idx)->DIEPCTL |= USB_OTG_DIEPCTL_SNAK; + USB_OTG_INEP(ep_idx)->DIEPCTL |= USB_OTG_DIEPCTL_EPDIS; + + /* Wait for endpoint disabled interrupt */ + count = 0; + do { + if (++count > 50000) { + break; + } + } while ((USB_OTG_INEP(ep_idx)->DIEPINT & USB_OTG_DIEPINT_EPDISD) != USB_OTG_DIEPINT_EPDISD); + + /* Clear and unmask endpoint disabled interrupt */ + USB_OTG_INEP(ep_idx)->DIEPINT = USB_OTG_DIEPINT_EPDISD; + } + + USB_OTG_DEV->DEACHMSK &= ~(USB_OTG_DAINTMSK_IEPM & (uint32_t)(1UL << (ep_idx & 0x07))); + USB_OTG_DEV->DAINTMSK &= ~(USB_OTG_DAINTMSK_IEPM & (uint32_t)(1UL << (ep_idx & 0x07))); + USB_OTG_INEP(ep_idx)->DIEPCTL = 0; + } + return 0; +} + +int usbd_ep_set_stall(uint8_t busid, const uint8_t ep) +{ + uint8_t ep_idx = USB_EP_GET_IDX(ep); + + if (USB_EP_DIR_IS_OUT(ep)) { + if (((USB_OTG_OUTEP(ep_idx)->DOEPCTL & USB_OTG_DOEPCTL_EPENA) == 0U) && (ep_idx != 0U)) { + USB_OTG_OUTEP(ep_idx)->DOEPCTL &= ~(USB_OTG_DOEPCTL_EPDIS); + } + USB_OTG_OUTEP(ep_idx)->DOEPCTL |= USB_OTG_DOEPCTL_STALL; + } else { + if (((USB_OTG_INEP(ep_idx)->DIEPCTL & USB_OTG_DIEPCTL_EPENA) == 0U) && (ep_idx != 0U)) { + USB_OTG_INEP(ep_idx)->DIEPCTL &= ~(USB_OTG_DIEPCTL_EPDIS); + } + USB_OTG_INEP(ep_idx)->DIEPCTL |= USB_OTG_DIEPCTL_STALL; + } + + if ((ep_idx == 0) && g_dwc2_udc[busid].user_params.device_dma_enable) { + dwc2_ep0_start_read_setup(busid, (uint8_t *)&g_dwc2_udc[busid].setup); + } + + return 0; +} + +int usbd_ep_clear_stall(uint8_t busid, const uint8_t ep) +{ + uint8_t ep_idx = USB_EP_GET_IDX(ep); + + if (USB_EP_DIR_IS_OUT(ep)) { + USB_OTG_OUTEP(ep_idx)->DOEPCTL &= ~USB_OTG_DOEPCTL_STALL; + if ((g_dwc2_udc[busid].out_ep[ep_idx].ep_type == USB_ENDPOINT_TYPE_INTERRUPT) || + (g_dwc2_udc[busid].out_ep[ep_idx].ep_type == USB_ENDPOINT_TYPE_BULK)) { + USB_OTG_OUTEP(ep_idx)->DOEPCTL |= USB_OTG_DOEPCTL_SD0PID_SEVNFRM; /* DATA0 */ + } + } else { + USB_OTG_INEP(ep_idx)->DIEPCTL &= ~USB_OTG_DIEPCTL_STALL; + if ((g_dwc2_udc[busid].in_ep[ep_idx].ep_type == USB_ENDPOINT_TYPE_INTERRUPT) || + (g_dwc2_udc[busid].in_ep[ep_idx].ep_type == USB_ENDPOINT_TYPE_BULK)) { + USB_OTG_INEP(ep_idx)->DIEPCTL |= USB_OTG_DIEPCTL_SD0PID_SEVNFRM; /* DATA0 */ + } + } + return 0; +} + +int usbd_ep_is_stalled(uint8_t busid, const uint8_t ep, uint8_t *stalled) +{ + uint8_t ep_idx = USB_EP_GET_IDX(ep); + + if (USB_EP_DIR_IS_OUT(ep)) { + if (USB_OTG_OUTEP(ep_idx)->DOEPCTL & USB_OTG_DOEPCTL_STALL) { + *stalled = 1; + } else { + *stalled = 0; + } + } else { + if (USB_OTG_INEP(ep_idx)->DIEPCTL & USB_OTG_DIEPCTL_STALL) { + *stalled = 1; + } else { + *stalled = 0; + } + } + return 0; +} + +int usbd_ep_start_write(uint8_t busid, const uint8_t ep, const uint8_t *data, uint32_t data_len) +{ + uint8_t ep_idx = USB_EP_GET_IDX(ep); + uint32_t pktcnt = 0; + + USB_ASSERT_MSG(!((uint32_t)data % 0x04), "dwc2 data must be 4-byte aligned"); + + if (g_dwc2_udc[busid].user_params.device_dma_enable) { + USB_ASSERT_MSG(!((uint32_t)data % CONFIG_USB_ALIGN_SIZE), "dwc2 data must be %d-byte aligned", CONFIG_USB_ALIGN_SIZE); + } + + if (!data && data_len) { + return -1; + } + + if (ep_idx && !(USB_OTG_INEP(ep_idx)->DIEPCTL & USB_OTG_DIEPCTL_MPSIZ)) { + return -2; + } + + g_dwc2_udc[busid].in_ep[ep_idx].xfer_buf = (uint8_t *)data; + g_dwc2_udc[busid].in_ep[ep_idx].xfer_len = data_len; + g_dwc2_udc[busid].in_ep[ep_idx].actual_xfer_len = 0; + + USB_OTG_INEP(ep_idx)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_PKTCNT); + USB_OTG_INEP(ep_idx)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_XFRSIZ); + + if (data_len == 0) { + USB_OTG_INEP(ep_idx)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_PKTCNT & (1U << 19)); + USB_OTG_INEP(ep_idx)->DIEPCTL |= (USB_OTG_DIEPCTL_CNAK | USB_OTG_DIEPCTL_EPENA); + return 0; + } + + if (ep_idx == 0) { + if (data_len > g_dwc2_udc[busid].in_ep[ep_idx].ep_mps) { + data_len = g_dwc2_udc[busid].in_ep[ep_idx].ep_mps; + } + g_dwc2_udc[busid].in_ep[ep_idx].xfer_len = data_len; + USB_OTG_INEP(ep_idx)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_PKTCNT & (1U << 19)); + USB_OTG_INEP(ep_idx)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_XFRSIZ & data_len); + } else { + pktcnt = (uint16_t)((data_len + g_dwc2_udc[busid].in_ep[ep_idx].ep_mps - 1U) / g_dwc2_udc[busid].in_ep[ep_idx].ep_mps); + + USB_OTG_INEP(ep_idx)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_PKTCNT & (pktcnt << 19)); + USB_OTG_INEP(ep_idx)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_XFRSIZ & data_len); + } + + if (g_dwc2_udc[busid].in_ep[ep_idx].ep_type == USB_ENDPOINT_TYPE_ISOCHRONOUS) { + if ((USB_OTG_DEV->DSTS & (1U << 8)) == 0U) { + USB_OTG_INEP(ep_idx)->DIEPCTL &= ~USB_OTG_DIEPCTL_SD0PID_SEVNFRM; + USB_OTG_INEP(ep_idx)->DIEPCTL |= USB_OTG_DIEPCTL_SODDFRM; + } else { + USB_OTG_INEP(ep_idx)->DIEPCTL &= ~USB_OTG_DIEPCTL_SODDFRM; + USB_OTG_INEP(ep_idx)->DIEPCTL |= USB_OTG_DIEPCTL_SD0PID_SEVNFRM; + } + } + + if (g_dwc2_udc[busid].in_ep[ep_idx].ep_type == USB_ENDPOINT_TYPE_ISOCHRONOUS || + g_dwc2_udc[busid].in_ep[ep_idx].ep_type == USB_ENDPOINT_TYPE_INTERRUPT) { + USB_OTG_INEP(ep_idx)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_MULCNT); + USB_OTG_INEP(ep_idx)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_MULCNT & ((usbd_get_ep_mult(busid, ep) + 1) << 29)); + } + + if (g_dwc2_udc[busid].user_params.device_dma_enable) { + usb_dcache_clean((uintptr_t)data, USB_ALIGN_UP(data_len, CONFIG_USB_ALIGN_SIZE)); + USB_OTG_INEP(ep_idx)->DIEPDMA = (uint32_t)data; + + USB_OTG_INEP(ep_idx)->DIEPCTL |= (USB_OTG_DIEPCTL_CNAK | USB_OTG_DIEPCTL_EPENA); + } else { + USB_OTG_INEP(ep_idx)->DIEPCTL |= (USB_OTG_DIEPCTL_CNAK | USB_OTG_DIEPCTL_EPENA); + /* Enable the Tx FIFO Empty Interrupt for this EP */ + if (data_len > 0U) { + USB_OTG_DEV->DIEPEMPMSK |= 1UL << (ep_idx & 0x0f); + } + } + return 0; +} + +int usbd_ep_start_read(uint8_t busid, const uint8_t ep, uint8_t *data, uint32_t data_len) +{ + uint8_t ep_idx = USB_EP_GET_IDX(ep); + uint32_t pktcnt = 0; + + USB_ASSERT_MSG(!((uint32_t)data % 0x04), "dwc2 data must be 4-byte aligned"); + + if (g_dwc2_udc[busid].user_params.device_dma_enable) { + USB_ASSERT_MSG(!((uint32_t)data % CONFIG_USB_ALIGN_SIZE), "dwc2 data must be %d-byte aligned", CONFIG_USB_ALIGN_SIZE); + } + + if (!data && data_len) { + return -1; + } + + if (ep_idx && !(USB_OTG_OUTEP(ep_idx)->DOEPCTL & USB_OTG_DOEPCTL_MPSIZ)) { + return -2; + } + + g_dwc2_udc[busid].out_ep[ep_idx].xfer_buf = (uint8_t *)data; + g_dwc2_udc[busid].out_ep[ep_idx].xfer_len = data_len; + g_dwc2_udc[busid].out_ep[ep_idx].actual_xfer_len = 0; + + USB_OTG_OUTEP(ep_idx)->DOEPTSIZ &= ~(USB_OTG_DOEPTSIZ_PKTCNT); + USB_OTG_OUTEP(ep_idx)->DOEPTSIZ &= ~(USB_OTG_DOEPTSIZ_XFRSIZ); + if (data_len == 0) { + USB_OTG_OUTEP(ep_idx)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_PKTCNT & (1 << 19)); + USB_OTG_OUTEP(ep_idx)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_XFRSIZ & g_dwc2_udc[busid].out_ep[ep_idx].ep_mps); + USB_OTG_OUTEP(ep_idx)->DOEPCTL |= (USB_OTG_DOEPCTL_CNAK | USB_OTG_DOEPCTL_EPENA); + return 0; + } + + if (ep_idx == 0) { + if (data_len > g_dwc2_udc[busid].out_ep[ep_idx].ep_mps) { + data_len = g_dwc2_udc[busid].out_ep[ep_idx].ep_mps; + } + g_dwc2_udc[busid].out_ep[ep_idx].xfer_len = data_len; + USB_OTG_OUTEP(ep_idx)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_PKTCNT & (1U << 19)); + USB_OTG_OUTEP(ep_idx)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_XFRSIZ & data_len); + } else { + pktcnt = (uint16_t)((data_len + g_dwc2_udc[busid].out_ep[ep_idx].ep_mps - 1U) / g_dwc2_udc[busid].out_ep[ep_idx].ep_mps); + + USB_OTG_OUTEP(ep_idx)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_PKTCNT & (pktcnt << 19)); + USB_OTG_OUTEP(ep_idx)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_XFRSIZ & data_len); + } + + if (g_dwc2_udc[busid].user_params.device_dma_enable) { + usb_dcache_invalidate((uintptr_t)data, USB_ALIGN_UP(data_len, CONFIG_USB_ALIGN_SIZE)); + USB_OTG_OUTEP(ep_idx)->DOEPDMA = (uint32_t)data; + } + if (g_dwc2_udc[busid].out_ep[ep_idx].ep_type == USB_ENDPOINT_TYPE_ISOCHRONOUS) { + if ((USB_OTG_DEV->DSTS & (1U << 8)) == 0U) { + USB_OTG_OUTEP(ep_idx)->DOEPCTL &= ~USB_OTG_DOEPCTL_SD0PID_SEVNFRM; + USB_OTG_OUTEP(ep_idx)->DOEPCTL |= USB_OTG_DOEPCTL_SODDFRM; + } else { + USB_OTG_OUTEP(ep_idx)->DOEPCTL &= ~USB_OTG_DOEPCTL_SODDFRM; + USB_OTG_OUTEP(ep_idx)->DOEPCTL |= USB_OTG_DOEPCTL_SD0PID_SEVNFRM; + } + } + USB_OTG_OUTEP(ep_idx)->DOEPCTL |= (USB_OTG_DOEPCTL_CNAK | USB_OTG_DOEPCTL_EPENA); + return 0; +} + +void USBD_IRQHandler(uint8_t busid) +{ + uint32_t gint_status, temp, ep_idx, ep_intr, epint, read_count; + gint_status = dwc2_get_glb_intstatus(busid); + + (void)read_count; + + if ((USB_OTG_GLB->GINTSTS & 0x1U) == USB_OTG_MODE_DEVICE) { + /* Avoid spurious interrupt */ + if (gint_status == 0) { + return; + } + + if (!g_dwc2_udc[busid].user_params.device_dma_enable) { + /* Handle RxQLevel Interrupt */ + if (gint_status & USB_OTG_GINTSTS_RXFLVL) { + USB_MASK_INTERRUPT(USB_OTG_GLB, USB_OTG_GINTSTS_RXFLVL); + + temp = USB_OTG_GLB->GRXSTSP; + ep_idx = temp & USB_OTG_GRXSTSP_EPNUM; + + if (((temp & USB_OTG_GRXSTSP_PKTSTS) >> USB_OTG_GRXSTSP_PKTSTS_Pos) == STS_DATA_UPDT) { + read_count = (temp & USB_OTG_GRXSTSP_BCNT) >> 4; + if (read_count != 0) { + dwc2_ep_read(busid, g_dwc2_udc[busid].out_ep[ep_idx].xfer_buf, read_count); + g_dwc2_udc[busid].out_ep[ep_idx].xfer_buf += read_count; + } + } else if (((temp & USB_OTG_GRXSTSP_PKTSTS) >> USB_OTG_GRXSTSP_PKTSTS_Pos) == STS_SETUP_UPDT) { + read_count = (temp & USB_OTG_GRXSTSP_BCNT) >> 4; + dwc2_ep_read(busid, (uint8_t *)&g_dwc2_udc[busid].setup, read_count); + } else { + /* ... */ + } + USB_UNMASK_INTERRUPT(USB_OTG_GLB, USB_OTG_GINTSTS_RXFLVL); + } + } + + if (gint_status & USB_OTG_GINTSTS_OEPINT) { + ep_idx = 0; + ep_intr = dwc2_get_outeps_intstatus(busid); + while (ep_intr != 0U) { + if ((ep_intr & 0x1U) != 0U) { + epint = dwc2_get_outep_intstatus(busid, ep_idx); + + if ((epint & USB_OTG_DOEPINT_XFRC) == USB_OTG_DOEPINT_XFRC) { + if (ep_idx == 0) { + if (usbd_get_ep0_next_state(busid) == USBD_EP0_STATE_SETUP) { + goto process_setup; // goto ep0 setup, xfer_len is not used + } + + if (g_dwc2_udc[busid].out_ep[ep_idx].xfer_len == 0) { + /* If ep0 xfer_len is 0, it means that we are in outstatus phase */ + g_dwc2_udc[busid].out_ep[ep_idx].actual_xfer_len = 0; + } else { + /* If ep0 xfer_len is not 0, it means that we are in outdata phase */ + g_dwc2_udc[busid].out_ep[ep_idx].actual_xfer_len = g_dwc2_udc[busid].out_ep[ep_idx].xfer_len - ((USB_OTG_OUTEP(ep_idx)->DOEPTSIZ) & USB_OTG_DOEPTSIZ_XFRSIZ); + } + + g_dwc2_udc[busid].out_ep[ep_idx].xfer_len = 0; + if (g_dwc2_udc[busid].user_params.device_dma_enable) { + usb_dcache_invalidate((uintptr_t)g_dwc2_udc[busid].out_ep[ep_idx].xfer_buf, USB_ALIGN_UP(g_dwc2_udc[busid].out_ep[ep_idx].actual_xfer_len, CONFIG_USB_ALIGN_SIZE)); + } + usbd_event_ep_out_complete_handler(busid, 0x00, g_dwc2_udc[busid].out_ep[ep_idx].actual_xfer_len); + + if (usbd_get_ep0_next_state(busid) == USBD_EP0_STATE_SETUP) { + /* Out status, start reading setup */ + dwc2_ep0_start_read_setup(busid, (uint8_t *)&g_dwc2_udc[busid].setup); + } + } else { + g_dwc2_udc[busid].out_ep[ep_idx].actual_xfer_len = g_dwc2_udc[busid].out_ep[ep_idx].xfer_len - ((USB_OTG_OUTEP(ep_idx)->DOEPTSIZ) & USB_OTG_DOEPTSIZ_XFRSIZ); + g_dwc2_udc[busid].out_ep[ep_idx].xfer_len = 0; + if (g_dwc2_udc[busid].user_params.device_dma_enable) { + usb_dcache_invalidate((uintptr_t)g_dwc2_udc[busid].out_ep[ep_idx].xfer_buf, USB_ALIGN_UP(g_dwc2_udc[busid].out_ep[ep_idx].actual_xfer_len, CONFIG_USB_ALIGN_SIZE)); + } + usbd_event_ep_out_complete_handler(busid, ep_idx, g_dwc2_udc[busid].out_ep[ep_idx].actual_xfer_len); + } + } + // clang-format off +process_setup: + // clang-format on + if ((epint & USB_OTG_DOEPINT_STUP) == USB_OTG_DOEPINT_STUP) { + if (g_dwc2_udc[busid].user_params.device_dma_enable) { + usb_dcache_invalidate((uintptr_t)&g_dwc2_udc[busid].setup, USB_ALIGN_UP(8, CONFIG_USB_ALIGN_SIZE)); + } + usbd_event_ep0_setup_complete_handler(busid, (uint8_t *)&g_dwc2_udc[busid].setup); + } + } + ep_intr >>= 1U; + ep_idx++; + } + } + if (gint_status & USB_OTG_GINTSTS_IEPINT) { + ep_idx = 0U; + ep_intr = dwc2_get_ineps_intstatus(busid); + while (ep_intr != 0U) { + if ((ep_intr & 0x1U) != 0U) { + epint = dwc2_get_inep_intstatus(busid, ep_idx); + + if ((epint & USB_OTG_DIEPINT_XFRC) == USB_OTG_DIEPINT_XFRC) { + if (ep_idx == 0) { + g_dwc2_udc[busid].in_ep[ep_idx].actual_xfer_len = g_dwc2_udc[busid].in_ep[ep_idx].xfer_len - ((USB_OTG_INEP(ep_idx)->DIEPTSIZ) & USB_OTG_DIEPTSIZ_XFRSIZ); + g_dwc2_udc[busid].in_ep[ep_idx].xfer_len = 0; + usbd_event_ep_in_complete_handler(busid, 0x80, g_dwc2_udc[busid].in_ep[ep_idx].actual_xfer_len); + + if (usbd_get_ep0_next_state(busid) == USBD_EP0_STATE_SETUP) { + /* In status, start reading setup */ + dwc2_ep0_start_read_setup(busid, (uint8_t *)&g_dwc2_udc[busid].setup); + } + } else { + g_dwc2_udc[busid].in_ep[ep_idx].actual_xfer_len = g_dwc2_udc[busid].in_ep[ep_idx].xfer_len - ((USB_OTG_INEP(ep_idx)->DIEPTSIZ) & USB_OTG_DIEPTSIZ_XFRSIZ); + g_dwc2_udc[busid].in_ep[ep_idx].xfer_len = 0; + usbd_event_ep_in_complete_handler(busid, ep_idx | 0x80, g_dwc2_udc[busid].in_ep[ep_idx].actual_xfer_len); + } + } + if (!g_dwc2_udc[busid].user_params.device_dma_enable) { + if ((epint & USB_OTG_DIEPINT_TXFE) == USB_OTG_DIEPINT_TXFE) { + dwc2_tx_fifo_empty_procecss(busid, ep_idx); + } + } + } + ep_intr >>= 1U; + ep_idx++; + } + } + if (gint_status & USB_OTG_GINTSTS_USBRST) { + USB_OTG_GLB->GINTSTS = USB_OTG_GINTSTS_USBRST; + USB_OTG_DEV->DCTL &= ~USB_OTG_DCTL_RWUSIG; + + dwc2_flush_txfifo(busid, 0x10U); + dwc2_flush_rxfifo(busid); + + for (uint8_t i = 0U; i < (g_dwc2_udc[busid].hw_params.num_dev_ep + 1); i++) { + if (i == 0U) { + USB_OTG_INEP(i)->DIEPCTL = USB_OTG_DIEPCTL_SNAK; + USB_OTG_OUTEP(i)->DOEPCTL = USB_OTG_DOEPCTL_SNAK; + } else { + if (USB_OTG_INEP(i)->DIEPCTL & USB_OTG_DIEPCTL_EPENA) { + USB_OTG_INEP(i)->DIEPCTL = (USB_OTG_DIEPCTL_EPDIS | USB_OTG_DIEPCTL_SNAK); + } else { + USB_OTG_INEP(i)->DIEPCTL = 0; + } + if (USB_OTG_OUTEP(i)->DOEPCTL & USB_OTG_DOEPCTL_EPENA) { + USB_OTG_OUTEP(i)->DOEPCTL = (USB_OTG_DOEPCTL_EPDIS | USB_OTG_DOEPCTL_SNAK); + } else { + USB_OTG_OUTEP(i)->DOEPCTL = 0; + } + } + USB_OTG_INEP(i)->DIEPTSIZ = 0U; + USB_OTG_INEP(i)->DIEPINT = 0xFBFFU; + USB_OTG_OUTEP(i)->DOEPTSIZ = 0U; + USB_OTG_OUTEP(i)->DOEPINT = 0xFBFFU; + } + + USB_OTG_DEV->DAINTMSK |= 0x10001U; + + USB_OTG_DEV->DOEPMSK = USB_OTG_DOEPMSK_STUPM | + USB_OTG_DOEPMSK_XFRCM; + + USB_OTG_DEV->DIEPMSK = USB_OTG_DIEPMSK_XFRCM; + + memset(g_dwc2_udc[busid].in_ep, 0, sizeof(struct dwc2_ep_state) * 16); + memset(g_dwc2_udc[busid].out_ep, 0, sizeof(struct dwc2_ep_state) * 16); + usbd_event_reset_handler(busid); + } + if (gint_status & USB_OTG_GINTSTS_ENUMDNE) { + USB_OTG_GLB->GINTSTS = USB_OTG_GINTSTS_ENUMDNE; + dwc2_set_turnaroundtime(busid, usbd_dwc2_get_system_clock(), dwc2_get_devspeed(busid)); + + USB_OTG_DEV->DCTL |= USB_OTG_DCTL_CGINAK; + + /* Start reading setup */ + dwc2_ep0_start_read_setup(busid, (uint8_t *)&g_dwc2_udc[busid].setup); + } + if (gint_status & USB_OTG_GINTSTS_PXFR_INCOMPISOOUT) { + USB_OTG_GLB->GINTSTS = USB_OTG_GINTSTS_PXFR_INCOMPISOOUT; + } + + if (gint_status & USB_OTG_GINTSTS_IISOIXFR) { + USB_OTG_GLB->GINTSTS = USB_OTG_GINTSTS_IISOIXFR; + } +#ifdef CONFIG_USBDEV_SOF_ENABLE + if (gint_status & USB_OTG_GINTSTS_SOF) { + USB_OTG_GLB->GINTSTS = USB_OTG_GINTSTS_SOF; + usbd_event_sof_handler(busid); + } +#endif + if (gint_status & USB_OTG_GINTSTS_USBSUSP) { + USB_OTG_GLB->GINTSTS = USB_OTG_GINTSTS_USBSUSP; + usbd_event_suspend_handler(busid); + } + if (gint_status & USB_OTG_GINTSTS_WKUINT) { + USB_OTG_GLB->GINTSTS = USB_OTG_GINTSTS_WKUINT; + usbd_event_resume_handler(busid); + } + if (gint_status & USB_OTG_GINTSTS_OTGINT) { + temp = USB_OTG_GLB->GOTGINT; + if ((temp & USB_OTG_GOTGINT_SEDET) == USB_OTG_GOTGINT_SEDET) { + } else { + } + USB_OTG_GLB->GOTGINT |= temp; + } + } +} diff --git a/kernel/cherryusb/port/dwc2/usb_dwc2_param.h b/kernel/cherryusb/port/dwc2/usb_dwc2_param.h new file mode 100644 index 0000000..74e436c --- /dev/null +++ b/kernel/cherryusb/port/dwc2/usb_dwc2_param.h @@ -0,0 +1,367 @@ +/* + * Copyright (c) 2025, sakumisu + * + * SPDX-License-Identifier: Apache-2.0 + */ +#ifndef __USB_DWC2_PARAM_H__ +#define __USB_DWC2_PARAM_H__ + +/* Maximum number of Endpoints/HostChannels */ +#define MAX_EPS_CHANNELS 16 + +#define HSOTG_REG(x) (x) + +#define dwc2_readl(addr) \ + (*(volatile uint32_t *)(addr)) + +#define GUID_OFFSET HSOTG_REG(0x003C) + +#define GSNPSID_OFFSET HSOTG_REG(0x0040) +#define GSNPSID_ID_MASK (0xFFFF0000UL) + +#define GHWCFG1_OFFSET HSOTG_REG(0x0044) + +#define GHWCFG2_OFFSET HSOTG_REG(0x0048) +#define GHWCFG2_OTG_ENABLE_IC_USB (0x01UL << 31U) +#define GHWCFG2_DEV_TOKEN_Q_DEPTH_MASK (0x1FUL << 26U) +#define GHWCFG2_DEV_TOKEN_Q_DEPTH_SHIFT (26U) +#define GHWCFG2_HOST_PERIO_TX_Q_DEPTH_MASK (0x03UL << 24U) +#define GHWCFG2_HOST_PERIO_TX_Q_DEPTH_SHIFT (24U) +#define GHWCFG2_NONPERIO_TX_Q_DEPTH_MASK (0x03UL << 22U) +#define GHWCFG2_NONPERIO_TX_Q_DEPTH_SHIFT (22U) +#define GHWCFG2_MULTI_PROC_INT (0x01UL << 20U) +#define GHWCFG2_DYNAMIC_FIFO (0x01UL << 19U) +#define GHWCFG2_PERIO_EP_SUPPORTED (0x01UL << 18U) +#define GHWCFG2_NUM_HOST_CHAN_MASK (0x0FUL << 14U) +#define GHWCFG2_NUM_HOST_CHAN_SHIFT (14U) +#define GHWCFG2_NUM_DEV_EP_MASK (0x0FUL << 10U) +#define GHWCFG2_NUM_DEV_EP_SHIFT (10U) +#define GHWCFG2_FS_PHY_TYPE_MASK (0x03UL << 8U) +#define GHWCFG2_FS_PHY_TYPE_SHIFT (8U) +#define GHWCFG2_FS_PHY_TYPE_NOT_SUPPORTED (0x00UL) +#define GHWCFG2_FS_PHY_TYPE_DEDICATED (0x01UL) +#define GHWCFG2_FS_PHY_TYPE_SHARED_UTMI (0x02UL) +#define GHWCFG2_FS_PHY_TYPE_SHARED_ULPI (0x03UL) +#define GHWCFG2_HS_PHY_TYPE_MASK (0x03UL << 6U) +#define GHWCFG2_HS_PHY_TYPE_SHIFT (6U) +#define GHWCFG2_HS_PHY_TYPE_NOT_SUPPORTED (0x00UL) +#define GHWCFG2_HS_PHY_TYPE_UTMI (0x01UL) +#define GHWCFG2_HS_PHY_TYPE_ULPI (0x02UL) +#define GHWCFG2_HS_PHY_TYPE_UTMI_ULPI (0x03UL) +#define GHWCFG2_POINT2POINT (0x01UL << 5U) +#define GHWCFG2_ARCHITECTURE_MASK (0x03UL << 3U) +#define GHWCFG2_ARCHITECTURE_SHIFT (3U) +#define GHWCFG2_SLAVE_ONLY_ARCH (0x00UL) +#define GHWCFG2_EXT_DMA_ARCH (0x01UL) +#define GHWCFG2_INT_DMA_ARCH (0x02UL) +#define GHWCFG2_OP_MODE_MASK (0x07UL << 0U) +#define GHWCFG2_OP_MODE_SHIFT (0U) +#define GHWCFG2_OP_MODE_HNP_SRP_CAPABLE (0x00UL) +#define GHWCFG2_OP_MODE_SRP_ONLY_CAPABLE (0x01UL) +#define GHWCFG2_OP_MODE_NO_HNP_SRP_CAPABLE (0x02UL) +#define GHWCFG2_OP_MODE_SRP_CAPABLE_DEVICE (0x03UL) +#define GHWCFG2_OP_MODE_NO_SRP_CAPABLE_DEVICE (0x04UL) +#define GHWCFG2_OP_MODE_SRP_CAPABLE_HOST (0x05UL) +#define GHWCFG2_OP_MODE_NO_SRP_CAPABLE_HOST (0x06UL) +#define GHWCFG2_OP_MODE_UNDEFINED (0x07UL) + +#define GHWCFG3_OFFSET HSOTG_REG(0x004C) +#define GHWCFG3_DFIFO_DEPTH_MASK (0xFFFFUL << 16U) +#define GHWCFG3_DFIFO_DEPTH_SHIFT (16U) +#define GHWCFG3_OTG_LPM_EN (0x0001UL << 15U) +#define GHWCFG3_BC_SUPPORT (0x0001UL << 14U) +#define GHWCFG3_OTG_ENABLE_HSIC (0x0001UL << 13U) +#define GHWCFG3_ADP_SUPP (0x0001UL << 12U) +#define GHWCFG3_SYNCH_RESET_TYPE (0x0001UL << 11U) +#define GHWCFG3_OPTIONAL_FEATURES (0x0001UL << 10U) +#define GHWCFG3_VENDOR_CTRL_IF (0x0001UL << 9U) +#define GHWCFG3_I2C (0x0001UL << 8U) +#define GHWCFG3_OTG_FUNC (0x0001UL << 7U) +#define GHWCFG3_PACKET_SIZE_CNTR_WIDTH_MASK (0x0007UL << 4U) +#define GHWCFG3_PACKET_SIZE_CNTR_WIDTH_SHIFT (4U) +#define GHWCFG3_XFER_SIZE_CNTR_WIDTH_MASK (0x000FUL << 0U) +#define GHWCFG3_XFER_SIZE_CNTR_WIDTH_SHIFT (0U) + +#define GHWCFG4_OFFSET HSOTG_REG(0x0050) +#define GHWCFG4_DESC_DMA_DYN (0x1UL << 31U) +#define GHWCFG4_DESC_DMA (0x1UL << 30U) +#define GHWCFG4_NUM_IN_EPS_MASK (0xFUL << 26U) +#define GHWCFG4_NUM_IN_EPS_SHIFT (26U) +#define GHWCFG4_DED_FIFO_EN (0x1UL << 25U) +#define GHWCFG4_DED_FIFO_SHIFT (25U) +#define GHWCFG4_SESSION_END_FILT_EN (0x1UL << 24U) +#define GHWCFG4_B_VALID_FILT_EN (0x1UL << 23U) +#define GHWCFG4_A_VALID_FILT_EN (0x1UL << 22U) +#define GHWCFG4_VBUS_VALID_FILT_EN (0x1UL << 21U) +#define GHWCFG4_IDDIG_FILT_EN (0x1UL << 20U) +#define GHWCFG4_NUM_DEV_MODE_CTRL_EP_MASK (0xFUL << 16U) +#define GHWCFG4_NUM_DEV_MODE_CTRL_EP_SHIFT (16U) +#define GHWCFG4_UTMI_PHY_DATA_WIDTH_MASK (0x3UL << 14U) +#define GHWCFG4_UTMI_PHY_DATA_WIDTH_SHIFT (14U) +#define GHWCFG4_UTMI_PHY_DATA_WIDTH_8 (0x0UL) +#define GHWCFG4_UTMI_PHY_DATA_WIDTH_16 (0x1UL) +#define GHWCFG4_UTMI_PHY_DATA_WIDTH_8_OR_16 (0x2UL) +#define GHWCFG4_ACG_SUPPORTED (0x1UL << 12U) +#define GHWCFG4_IPG_ISOC_SUPPORTED (0x1UL << 11U) +#define GHWCFG4_SERVICE_INTERVAL_SUPPORTED (0x1UL << 10U) +#define GHWCFG4_XHIBER (0x1UL << 7U) +#define GHWCFG4_HIBER (0x1UL << 6U) +#define GHWCFG4_MIN_AHB_FREQ (0x1UL << 5U) +#define GHWCFG4_POWER_OPTIMIZ (0x1UL << 4U) +#define GHWCFG4_NUM_DEV_PERIO_IN_EP_MASK (0xFUL << 0U) +#define GHWCFG4_NUM_DEV_PERIO_IN_EP_SHIFT (0U) + +/** + * struct dwc2_hw_params - Autodetected parameters. + * + * These parameters are the various parameters read from hardware + * registers during initialization. They typically contain the best + * supported or maximum value that can be configured in the + * corresponding dwc2_core_params value. + * + * The values that are not in dwc2_core_params are documented below. + * + * @snpsid: Value from SNPSID register + * @dev_ep_dirs: Direction of device endpoints (GHWCFG1) + * + * @op_mode: Mode of Operation + * 0 - HNP- and SRP-Capable OTG (Host & Device) + * 1 - SRP-Capable OTG (Host & Device) + * 2 - Non-HNP and Non-SRP Capable OTG (Host & Device) + * 3 - SRP-Capable Device + * 4 - Non-OTG Device + * 5 - SRP-Capable Host + * 6 - Non-OTG Host + * @arch: Architecture + * 0 - Slave only + * 1 - External DMA + * 2 - Internal DMA + * @enable_dynamic_fifo: 0 - Use coreConsultant-specified FIFO size parameters + * 1 - Allow dynamic FIFO sizing (default, if available) + * @host_channels: The number of host channel registers to use + * 1 to 16 + * @hs_phy_type: High-speed PHY interface type + * 0 - High-speed interface not supported + * 1 - UTMI+ + * 2 - ULPI + * 3 - UTMI+ and ULPI + * @fs_phy_type: Full-speed PHY interface type + * 0 - Full speed interface not supported + * 1 - Dedicated full speed interface + * 2 - FS pins shared with UTMI+ pins + * 3 - FS pins shared with ULPI pins + * @num_dev_ep: Number of device endpoints available + * @nperio_tx_q_depth: + * Non-Periodic Request Queue Depth + * 2, 4 or 8 + * @dev_token_q_depth: Device Mode IN Token Sequence Learning Queue + * Depth + * 0 to 30 + * @host_perio_tx_q_depth: + * Host Mode Periodic Request Queue Depth + * 2, 4 or 8 + * + * @max_transfer_size: The maximum transfer size supported, in bytes + * 2047 to 65,535 + * Actual maximum value is autodetected and also + * the default. + * @max_packet_count: The maximum number of packets in a transfer + * 15 to 511 + * Actual maximum value is autodetected and also + * the default. + * @i2c_enable: Specifies whether to use the I2Cinterface for a full + * speed PHY. This parameter is only applicable if phy_type + * is FS. + * 0 - No (default) + * 1 - Yes + * @total_fifo_size: Total internal RAM for FIFOs (bytes) + * @lpm_mode: For enabling Link Power Management in the controller + * 0 - Disable + * 1 - Enable + * + * @en_multiple_tx_fifo: Specifies whether dedicated per-endpoint transmit FIFOs + * are enabled for non-periodic IN endpoints in device + * mode. + * @num_dev_in_eps: Number of device IN endpoints available + * @num_dev_perio_in_ep: Number of device periodic IN endpoints + * available + * @dma_desc_enable: When DMA mode is enabled, specifies whether to use + * address DMA mode or descriptor DMA mode for accessing + * the data FIFOs. The driver will automatically detect the + * value for this if none is specified. + * 0 - Address DMA + * 1 - Descriptor DMA (default, if available) + + * @power_optimized: Are power optimizations enabled? + * @hibernation: Is hibernation enabled? + * @utmi_phy_data_width: UTMI+ PHY data width + * 0 - 8 bits + * 1 - 16 bits + * 2 - 8 or 16 bits + + * @acg_enable: For enabling Active Clock Gating in the controller + * 0 - Disable + * 1 - Enable + * @ipg_isoc_en: This feature indicates that the controller supports + * the worst-case scenario of Rx followed by Rx + * Interpacket Gap (IPG) (32 bitTimes) as per the utmi + * specification for any token following ISOC OUT token. + * 0 - Don't support + * 1 - Support + * @service_interval_mode: For enabling service interval based scheduling in the + * controller. + * 0 - Disable + * 1 - Enable + */ +struct dwc2_hw_params { + uint32_t snpsid; + uint32_t dev_ep_dirs; + + unsigned op_mode : 3; + unsigned arch : 2; + unsigned enable_dynamic_fifo : 1; + unsigned host_channels : 5; + unsigned hs_phy_type : 2; + unsigned fs_phy_type : 2; + unsigned num_dev_ep : 4; + unsigned nperio_tx_q_depth : 3; + unsigned host_perio_tx_q_depth : 3; + unsigned dev_token_q_depth : 5; + + unsigned max_transfer_size : 26; + unsigned max_packet_count : 11; + unsigned i2c_enable : 1; + unsigned total_fifo_size : 16; + unsigned lpm_mode : 1; + + unsigned en_multiple_tx_fifo : 1; + unsigned num_dev_in_eps : 4; + unsigned num_dev_perio_in_ep : 4; + unsigned dma_desc_enable : 1; + unsigned power_optimized : 1; + unsigned hibernation : 1; + unsigned utmi_phy_data_width : 2; + unsigned acg_enable : 1; + unsigned ipg_isoc_en : 1; + unsigned service_interval_mode : 1; +}; + +#define DWC2_PHY_TYPE_PARAM_FS 0 +#define DWC2_PHY_TYPE_PARAM_UTMI 1 +#define DWC2_PHY_TYPE_PARAM_ULPI 2 + +struct dwc2_user_params { + uint8_t phy_type; + uint8_t phy_utmi_width; + + bool device_dma_enable; + bool device_dma_desc_enable; + /* (5 * number of control endpoints + 8) + ((largest USB packet used / 4) + 1 for + * status information) + (2 * number of OUT endpoints) + 1 for Global NAK + */ + uint16_t device_rx_fifo_size; + /* IN Endpoints Max packet Size / 4 */ + uint16_t device_tx_fifo_size[MAX_EPS_CHANNELS]; + + bool host_dma_desc_enable; + /* + * (largest USB packet used / 4) + 1 for status information + 1 transfer complete + + * 1 location each for Bulk/Control endpoint for handling NAK/NYET scenario + */ + uint16_t host_rx_fifo_size; + /* largest non-periodic USB packet used / 4 */ + uint16_t host_nperio_tx_fifo_size; + /* largest periodic USB packet used / 4 */ + uint16_t host_perio_tx_fifo_size; + + uint32_t device_gccfg; + uint32_t host_gccfg; + + bool b_session_valid_override; + uint32_t total_fifo_size; +}; + +struct usb_dwc2_user_fifo_config { + /* (5 * number of control endpoints + 8) + ((largest USB packet used / 4) + 1 for + * status information) + (2 * number of OUT endpoints) + 1 for Global NAK + */ + uint16_t device_rx_fifo_size; + /* IN Endpoints Max packet Size / 4 */ + uint16_t device_tx_fifo_size[MAX_EPS_CHANNELS]; +}; + +static inline void dwc2_get_hwparams(uint32_t reg_base, struct dwc2_hw_params *hw) +{ + unsigned int width; + uint32_t snpsid, hwcfg1, hwcfg2, hwcfg3, hwcfg4; + + snpsid = dwc2_readl(reg_base + GSNPSID_OFFSET); + + hwcfg1 = dwc2_readl(reg_base + GHWCFG1_OFFSET); + hwcfg2 = dwc2_readl(reg_base + GHWCFG2_OFFSET); + hwcfg3 = dwc2_readl(reg_base + GHWCFG3_OFFSET); + hwcfg4 = dwc2_readl(reg_base + GHWCFG4_OFFSET); + + /* snpsid */ + hw->snpsid = snpsid; + + /* hwcfg1 */ + hw->dev_ep_dirs = hwcfg1; + + /* hwcfg2 */ + hw->op_mode = (hwcfg2 & GHWCFG2_OP_MODE_MASK) >> + GHWCFG2_OP_MODE_SHIFT; + hw->arch = (hwcfg2 & GHWCFG2_ARCHITECTURE_MASK) >> + GHWCFG2_ARCHITECTURE_SHIFT; + hw->enable_dynamic_fifo = !!(hwcfg2 & GHWCFG2_DYNAMIC_FIFO); + hw->host_channels = 1 + ((hwcfg2 & GHWCFG2_NUM_HOST_CHAN_MASK) >> + GHWCFG2_NUM_HOST_CHAN_SHIFT); + hw->hs_phy_type = (hwcfg2 & GHWCFG2_HS_PHY_TYPE_MASK) >> + GHWCFG2_HS_PHY_TYPE_SHIFT; + hw->fs_phy_type = (hwcfg2 & GHWCFG2_FS_PHY_TYPE_MASK) >> + GHWCFG2_FS_PHY_TYPE_SHIFT; + hw->num_dev_ep = (hwcfg2 & GHWCFG2_NUM_DEV_EP_MASK) >> + GHWCFG2_NUM_DEV_EP_SHIFT; + hw->nperio_tx_q_depth = + (hwcfg2 & GHWCFG2_NONPERIO_TX_Q_DEPTH_MASK) >> + GHWCFG2_NONPERIO_TX_Q_DEPTH_SHIFT << 1; + hw->host_perio_tx_q_depth = + (hwcfg2 & GHWCFG2_HOST_PERIO_TX_Q_DEPTH_MASK) >> + GHWCFG2_HOST_PERIO_TX_Q_DEPTH_SHIFT << 1; + hw->dev_token_q_depth = + (hwcfg2 & GHWCFG2_DEV_TOKEN_Q_DEPTH_MASK) >> + GHWCFG2_DEV_TOKEN_Q_DEPTH_SHIFT; + + /* hwcfg3 */ + width = (hwcfg3 & GHWCFG3_XFER_SIZE_CNTR_WIDTH_MASK) >> + GHWCFG3_XFER_SIZE_CNTR_WIDTH_SHIFT; + hw->max_transfer_size = (1 << (width + 11)) - 1; + width = (hwcfg3 & GHWCFG3_PACKET_SIZE_CNTR_WIDTH_MASK) >> + GHWCFG3_PACKET_SIZE_CNTR_WIDTH_SHIFT; + hw->max_packet_count = (1 << (width + 4)) - 1; + hw->i2c_enable = !!(hwcfg3 & GHWCFG3_I2C); + hw->total_fifo_size = (hwcfg3 & GHWCFG3_DFIFO_DEPTH_MASK) >> + GHWCFG3_DFIFO_DEPTH_SHIFT; + hw->lpm_mode = !!(hwcfg3 & GHWCFG3_OTG_LPM_EN); + + /* hwcfg4 */ + hw->en_multiple_tx_fifo = !!(hwcfg4 & GHWCFG4_DED_FIFO_EN); + hw->num_dev_perio_in_ep = (hwcfg4 & GHWCFG4_NUM_DEV_PERIO_IN_EP_MASK) >> + GHWCFG4_NUM_DEV_PERIO_IN_EP_SHIFT; + hw->num_dev_in_eps = (hwcfg4 & GHWCFG4_NUM_IN_EPS_MASK) >> + GHWCFG4_NUM_IN_EPS_SHIFT; + hw->dma_desc_enable = !!(hwcfg4 & GHWCFG4_DESC_DMA); + hw->power_optimized = !!(hwcfg4 & GHWCFG4_POWER_OPTIMIZ); + hw->hibernation = !!(hwcfg4 & GHWCFG4_HIBER); + hw->utmi_phy_data_width = (hwcfg4 & GHWCFG4_UTMI_PHY_DATA_WIDTH_MASK) >> + GHWCFG4_UTMI_PHY_DATA_WIDTH_SHIFT; + hw->acg_enable = !!(hwcfg4 & GHWCFG4_ACG_SUPPORTED); + hw->ipg_isoc_en = !!(hwcfg4 & GHWCFG4_IPG_ISOC_SUPPORTED); + hw->service_interval_mode = !!(hwcfg4 & + GHWCFG4_SERVICE_INTERVAL_SUPPORTED); +} + +void dwc2_get_user_params(uint32_t reg_base, struct dwc2_user_params *params); +void dwc2_get_user_fifo_config(uint32_t reg_base, struct usb_dwc2_user_fifo_config *config); + +#endif \ No newline at end of file diff --git a/kernel/cherryusb/port/dwc2/usb_dwc2_reg.h b/kernel/cherryusb/port/dwc2/usb_dwc2_reg.h new file mode 100644 index 0000000..69b0960 --- /dev/null +++ b/kernel/cherryusb/port/dwc2/usb_dwc2_reg.h @@ -0,0 +1,1738 @@ +/* + * Copyright (c) 2022, sakumisu + * + * SPDX-License-Identifier: Apache-2.0 + */ +#ifndef __USB_DWC2_REG_H__ +#define __USB_DWC2_REG_H__ + +#define __IO volatile /*!< Defines 'read / write' permissions */ +/** + * @brief USB_OTG_Core_Registers + */ +typedef struct +{ + __IO uint32_t GOTGCTL; /*!< USB_OTG Control and Status Register 000h */ + __IO uint32_t GOTGINT; /*!< USB_OTG Interrupt Register 004h */ + __IO uint32_t GAHBCFG; /*!< Core AHB Configuration Register 008h */ + __IO uint32_t GUSBCFG; /*!< Core USB Configuration Register 00Ch */ + __IO uint32_t GRSTCTL; /*!< Core Reset Register 010h */ + __IO uint32_t GINTSTS; /*!< Core Interrupt Register 014h */ + __IO uint32_t GINTMSK; /*!< Core Interrupt Mask Register 018h */ + __IO uint32_t GRXSTSR; /*!< Receive Sts Q Read Register 01Ch */ + __IO uint32_t GRXSTSP; /*!< Receive Sts Q Read & POP Register 020h */ + __IO uint32_t GRXFSIZ; /*!< Receive FIFO Size Register 024h */ + __IO uint32_t DIEPTXF0_HNPTXFSIZ; /*!< EP0 / Non Periodic Tx FIFO Size Register 028h */ + __IO uint32_t HNPTXSTS; /*!< Non Periodic Tx FIFO/Queue Sts reg 02Ch */ + uint32_t Reserved30[2]; /*!< Reserved 030h */ + __IO uint32_t GCCFG; /*!< General Purpose IO Register 038h */ + __IO uint32_t CID; /*!< User ID Register 03Ch */ + __IO uint32_t GSNPSID; /*!< USB_OTG core ID 040h */ + __IO uint32_t GHWCFG1; /*!< User HW config1 044h */ + __IO uint32_t GHWCFG2; /*!< User HW config2 048h */ + __IO uint32_t GHWCFG3; /*!< User HW config3 04Ch */ + __IO uint32_t GHWCFG4; /*!< User HW config4 050h */ + __IO uint32_t GLPMCFG; /*!< LPM Register 054h */ + __IO uint32_t GPWRDN; /*!< Power Down Register 058h */ + __IO uint32_t GDFIFOCFG; /*!< DFIFO Software Config Register 05Ch */ + __IO uint32_t GADPCTL; /*!< ADP Timer, Control and Status Register 60Ch */ + uint32_t Reserved43[39]; /*!< Reserved 058h-0FFh */ + __IO uint32_t HPTXFSIZ; /*!< Host Periodic Tx FIFO Size Reg 100h */ + __IO uint32_t DIEPTXF[0x0F]; /*!< dev Periodic Transmit FIFO */ +} DWC2_GlobalTypeDef; + +/** + * @brief USB_OTG_device_Registers + */ +typedef struct +{ + __IO uint32_t DCFG; /*!< dev Configuration Register 800h */ + __IO uint32_t DCTL; /*!< dev Control Register 804h */ + __IO uint32_t DSTS; /*!< dev Status Register (RO) 808h */ + uint32_t Reserved0C; /*!< Reserved 80Ch */ + __IO uint32_t DIEPMSK; /*!< dev IN Endpoint Mask 810h */ + __IO uint32_t DOEPMSK; /*!< dev OUT Endpoint Mask 814h */ + __IO uint32_t DAINT; /*!< dev All Endpoints Itr Reg 818h */ + __IO uint32_t DAINTMSK; /*!< dev All Endpoints Itr Mask 81Ch */ + uint32_t Reserved20; /*!< Reserved 820h */ + uint32_t Reserved9; /*!< Reserved 824h */ + __IO uint32_t DVBUSDIS; /*!< dev VBUS discharge Register 828h */ + __IO uint32_t DVBUSPULSE; /*!< dev VBUS Pulse Register 82Ch */ + __IO uint32_t DTHRCTL; /*!< dev threshold 830h */ + __IO uint32_t DIEPEMPMSK; /*!< dev empty msk 834h */ + __IO uint32_t DEACHINT; /*!< dedicated EP interrupt 838h */ + __IO uint32_t DEACHMSK; /*!< dedicated EP msk 83Ch */ + uint32_t Reserved40; /*!< dedicated EP mask 840h */ + __IO uint32_t DINEP1MSK; /*!< dedicated EP mask 844h */ + uint32_t Reserved44[15]; /*!< Reserved 844-87Ch */ + __IO uint32_t DOUTEP1MSK; /*!< dedicated EP msk 884h */ +} DWC2_DeviceTypeDef; + +/** + * @brief USB_OTG_IN_Endpoint-Specific_Register + */ +typedef struct +{ + __IO uint32_t DIEPCTL; /*!< dev IN Endpoint Control Reg 900h + (ep_num * 20h) + 00h */ + uint32_t Reserved04; /*!< Reserved 900h + (ep_num * 20h) + 04h */ + __IO uint32_t DIEPINT; /*!< dev IN Endpoint Itr Reg 900h + (ep_num * 20h) + 08h */ + uint32_t Reserved0C; /*!< Reserved 900h + (ep_num * 20h) + 0Ch */ + __IO uint32_t DIEPTSIZ; /*!< IN Endpoint Txfer Size 900h + (ep_num * 20h) + 10h */ + __IO uint32_t DIEPDMA; /*!< IN Endpoint DMA Address Reg 900h + (ep_num * 20h) + 14h */ + __IO uint32_t DTXFSTS; /*!< IN Endpoint Tx FIFO Status Reg 900h + (ep_num * 20h) + 18h */ + uint32_t Reserved18; /*!< Reserved 900h+(ep_num*20h)+1Ch-900h+ (ep_num * 20h) + 1Ch */ +} DWC2_INEndpointTypeDef; + +/** + * @brief USB_OTG_OUT_Endpoint-Specific_Registers + */ +typedef struct +{ + __IO uint32_t DOEPCTL; /*!< dev OUT Endpoint Control Reg B00h + (ep_num * 20h) + 00h */ + uint32_t Reserved04; /*!< Reserved B00h + (ep_num * 20h) + 04h */ + __IO uint32_t DOEPINT; /*!< dev OUT Endpoint Itr Reg B00h + (ep_num * 20h) + 08h */ + uint32_t Reserved0C; /*!< Reserved B00h + (ep_num * 20h) + 0Ch */ + __IO uint32_t DOEPTSIZ; /*!< dev OUT Endpoint Txfer Size B00h + (ep_num * 20h) + 10h */ + __IO uint32_t DOEPDMA; /*!< dev OUT Endpoint DMA Address B00h + (ep_num * 20h) + 14h */ + uint32_t Reserved18[2]; /*!< Reserved B00h + (ep_num * 20h) + 18h - B00h + (ep_num * 20h) + 1Ch */ +} DWC2_OUTEndpointTypeDef; + +/** + * @brief USB_OTG_Host_Mode_Register_Structures + */ +typedef struct +{ + __IO uint32_t HCFG; /*!< Host Configuration Register 400h */ + __IO uint32_t HFIR; /*!< Host Frame Interval Register 404h */ + __IO uint32_t HFNUM; /*!< Host Frame Nbr/Frame Remaining 408h */ + uint32_t Reserved40C; /*!< Reserved 40Ch */ + __IO uint32_t HPTXSTS; /*!< Host Periodic Tx FIFO/ Queue Status 410h */ + __IO uint32_t HAINT; /*!< Host All Channels Interrupt Register 414h */ + __IO uint32_t HAINTMSK; /*!< Host All Channels Interrupt Mask 418h */ + __IO uint32_t HFLBADDR; /*!< Host frame list base address register 41Ch */ + uint32_t Reserved420[8]; /*!< Reserved 420h */ + __IO uint32_t HPRT; /*!< Host port control and status register 440h */ +} DWC2_HostTypeDef; + +/** + * @brief USB_OTG_Host_Channel_Specific_Registers + */ +typedef struct +{ + __IO uint32_t HCCHAR; /*!< Host Channel Characteristics Register 500h */ + __IO uint32_t HCSPLT; /*!< Host Channel Split Control Register 504h */ + __IO uint32_t HCINT; /*!< Host Channel Interrupt Register 508h */ + __IO uint32_t HCINTMSK; /*!< Host Channel Interrupt Mask Register 50Ch */ + __IO uint32_t HCTSIZ; /*!< Host Channel Transfer Size Register 510h */ + __IO uint32_t HCDMA; /*!< Host Channel DMA Address Register 514h */ + uint32_t Reserved0; /*!< Reserved 518h */ + __IO uint32_t HCDMAB; /*!< Host Channel DMA Address Buffer Register 51Ch */ + uint32_t Reserved[2]; /*!< Reserved */ +} DWC2_HostChannelTypeDef; + +#define USB_OTG_GLOBAL_BASE 0x000UL +#define USB_OTG_DEVICE_BASE 0x800UL +#define USB_OTG_IN_ENDPOINT_BASE 0x900UL +#define USB_OTG_OUT_ENDPOINT_BASE 0xB00UL +#define USB_OTG_EP_REG_SIZE 0x20UL +#define USB_OTG_HOST_BASE 0x400UL +#define USB_OTG_HOST_PORT_BASE 0x440UL +#define USB_OTG_HOST_CHANNEL_BASE 0x500UL +#define USB_OTG_HOST_CHANNEL_SIZE 0x20UL +#define USB_OTG_PCGCCTL_BASE 0xE00UL +#define USB_OTG_FIFO_BASE 0x1000UL +#define USB_OTG_FIFO_SIZE 0x1000UL + +/******************************************************************************/ +/* */ +/* USB_OTG */ +/* */ +/******************************************************************************/ +/******************** Bit definition for USB_OTG_GOTGCTL register ***********/ +#define USB_OTG_GOTGCTL_SRQSCS_Pos (0U) +#define USB_OTG_GOTGCTL_SRQSCS_Msk (0x1UL << USB_OTG_GOTGCTL_SRQSCS_Pos) /*!< 0x00000001 */ +#define USB_OTG_GOTGCTL_SRQSCS USB_OTG_GOTGCTL_SRQSCS_Msk /*!< Session request success */ +#define USB_OTG_GOTGCTL_SRQ_Pos (1U) +#define USB_OTG_GOTGCTL_SRQ_Msk (0x1UL << USB_OTG_GOTGCTL_SRQ_Pos) /*!< 0x00000002 */ +#define USB_OTG_GOTGCTL_SRQ USB_OTG_GOTGCTL_SRQ_Msk /*!< Session request */ +#define USB_OTG_GOTGCTL_VBVALOEN_Pos (2U) +#define USB_OTG_GOTGCTL_VBVALOEN_Msk (0x1UL << USB_OTG_GOTGCTL_VBVALOEN_Pos) /*!< 0x00000004 */ +#define USB_OTG_GOTGCTL_VBVALOEN USB_OTG_GOTGCTL_VBVALOEN_Msk /*!< VBUS valid override enable */ +#define USB_OTG_GOTGCTL_VBVALOVAL_Pos (3U) +#define USB_OTG_GOTGCTL_VBVALOVAL_Msk (0x1UL << USB_OTG_GOTGCTL_VBVALOVAL_Pos) /*!< 0x00000008 */ +#define USB_OTG_GOTGCTL_VBVALOVAL USB_OTG_GOTGCTL_VBVALOVAL_Msk /*!< VBUS valid override value */ +#define USB_OTG_GOTGCTL_AVALOEN_Pos (4U) +#define USB_OTG_GOTGCTL_AVALOEN_Msk (0x1UL << USB_OTG_GOTGCTL_AVALOEN_Pos) /*!< 0x00000010 */ +#define USB_OTG_GOTGCTL_AVALOEN USB_OTG_GOTGCTL_AVALOEN_Msk /*!< A-peripheral session valid override enable */ +#define USB_OTG_GOTGCTL_AVALOVAL_Pos (5U) +#define USB_OTG_GOTGCTL_AVALOVAL_Msk (0x1UL << USB_OTG_GOTGCTL_AVALOVAL_Pos) /*!< 0x00000020 */ +#define USB_OTG_GOTGCTL_AVALOVAL USB_OTG_GOTGCTL_AVALOVAL_Msk /*!< A-peripheral session valid override value */ +#define USB_OTG_GOTGCTL_BVALOEN_Pos (6U) +#define USB_OTG_GOTGCTL_BVALOEN_Msk (0x1UL << USB_OTG_GOTGCTL_BVALOEN_Pos) /*!< 0x00000040 */ +#define USB_OTG_GOTGCTL_BVALOEN USB_OTG_GOTGCTL_BVALOEN_Msk /*!< B-peripheral session valid override enable */ +#define USB_OTG_GOTGCTL_BVALOVAL_Pos (7U) +#define USB_OTG_GOTGCTL_BVALOVAL_Msk (0x1UL << USB_OTG_GOTGCTL_BVALOVAL_Pos) /*!< 0x00000080 */ +#define USB_OTG_GOTGCTL_BVALOVAL USB_OTG_GOTGCTL_BVALOVAL_Msk /*!< B-peripheral session valid override value */ +#define USB_OTG_GOTGCTL_HNGSCS_Pos (8U) +#define USB_OTG_GOTGCTL_HNGSCS_Msk (0x1UL << USB_OTG_GOTGCTL_HNGSCS_Pos) /*!< 0x00000100 */ +#define USB_OTG_GOTGCTL_HNGSCS USB_OTG_GOTGCTL_HNGSCS_Msk /*!< Host set HNP enable */ +#define USB_OTG_GOTGCTL_HNPRQ_Pos (9U) +#define USB_OTG_GOTGCTL_HNPRQ_Msk (0x1UL << USB_OTG_GOTGCTL_HNPRQ_Pos) /*!< 0x00000200 */ +#define USB_OTG_GOTGCTL_HNPRQ USB_OTG_GOTGCTL_HNPRQ_Msk /*!< HNP request */ +#define USB_OTG_GOTGCTL_HSHNPEN_Pos (10U) +#define USB_OTG_GOTGCTL_HSHNPEN_Msk (0x1UL << USB_OTG_GOTGCTL_HSHNPEN_Pos) /*!< 0x00000400 */ +#define USB_OTG_GOTGCTL_HSHNPEN USB_OTG_GOTGCTL_HSHNPEN_Msk /*!< Host set HNP enable */ +#define USB_OTG_GOTGCTL_DHNPEN_Pos (11U) +#define USB_OTG_GOTGCTL_DHNPEN_Msk (0x1UL << USB_OTG_GOTGCTL_DHNPEN_Pos) /*!< 0x00000800 */ +#define USB_OTG_GOTGCTL_DHNPEN USB_OTG_GOTGCTL_DHNPEN_Msk /*!< Device HNP enabled */ +#define USB_OTG_GOTGCTL_EHEN_Pos (12U) +#define USB_OTG_GOTGCTL_EHEN_Msk (0x1UL << USB_OTG_GOTGCTL_EHEN_Pos) /*!< 0x00001000 */ +#define USB_OTG_GOTGCTL_EHEN USB_OTG_GOTGCTL_EHEN_Msk /*!< Embedded host enable */ +#define USB_OTG_GOTGCTL_CIDSTS_Pos (16U) +#define USB_OTG_GOTGCTL_CIDSTS_Msk (0x1UL << USB_OTG_GOTGCTL_CIDSTS_Pos) /*!< 0x00010000 */ +#define USB_OTG_GOTGCTL_CIDSTS USB_OTG_GOTGCTL_CIDSTS_Msk /*!< Connector ID status */ +#define USB_OTG_GOTGCTL_DBCT_Pos (17U) +#define USB_OTG_GOTGCTL_DBCT_Msk (0x1UL << USB_OTG_GOTGCTL_DBCT_Pos) /*!< 0x00020000 */ +#define USB_OTG_GOTGCTL_DBCT USB_OTG_GOTGCTL_DBCT_Msk /*!< Long/short debounce time */ +#define USB_OTG_GOTGCTL_ASVLD_Pos (18U) +#define USB_OTG_GOTGCTL_ASVLD_Msk (0x1UL << USB_OTG_GOTGCTL_ASVLD_Pos) /*!< 0x00040000 */ +#define USB_OTG_GOTGCTL_ASVLD USB_OTG_GOTGCTL_ASVLD_Msk /*!< A-session valid */ +#define USB_OTG_GOTGCTL_BSESVLD_Pos (19U) +#define USB_OTG_GOTGCTL_BSESVLD_Msk (0x1UL << USB_OTG_GOTGCTL_BSESVLD_Pos) /*!< 0x00080000 */ +#define USB_OTG_GOTGCTL_BSESVLD USB_OTG_GOTGCTL_BSESVLD_Msk /*!< B-session valid */ +#define USB_OTG_GOTGCTL_OTGVER_Pos (20U) +#define USB_OTG_GOTGCTL_OTGVER_Msk (0x1UL << USB_OTG_GOTGCTL_OTGVER_Pos) /*!< 0x00100000 */ +#define USB_OTG_GOTGCTL_OTGVER USB_OTG_GOTGCTL_OTGVER_Msk /*!< OTG version */ + +/******************** Bit definition forUSB_OTG_HCFG register ********************/ + +#define USB_OTG_HCFG_FSLSPCS_Pos (0U) +#define USB_OTG_HCFG_FSLSPCS_Msk (0x3UL << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000003 */ +#define USB_OTG_HCFG_FSLSPCS USB_OTG_HCFG_FSLSPCS_Msk /*!< FS/LS PHY clock select */ +#define USB_OTG_HCFG_FSLSPCLKSEL_30_60_MHZ (0x0UL << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000000 */ +#define USB_OTG_HCFG_FSLSPCLKSEL_48_MHZ (0x1UL << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000001 */ +#define USB_OTG_HCFG_FSLSPCLKSEL_6_MHZ (0x2UL << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000002 */ +#define USB_OTG_HCFG_FSLSS_Pos (2U) +#define USB_OTG_HCFG_FSLSS_Msk (0x1UL << USB_OTG_HCFG_FSLSS_Pos) /*!< 0x00000004 */ +#define USB_OTG_HCFG_FSLSS USB_OTG_HCFG_FSLSS_Msk /*!< FS- and LS-only support */ + +/******************** Bit definition for USB_OTG_DCFG register ********************/ + +#define USB_OTG_DCFG_DSPD_Pos (0U) +#define USB_OTG_DCFG_DSPD_Msk (0x3UL << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000003 */ +#define USB_OTG_DCFG_DSPD USB_OTG_DCFG_DSPD_Msk /*!< Device speed */ +#define USB_OTG_DCFG_DSPD_0 (0x1UL << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000001 */ +#define USB_OTG_DCFG_DSPD_1 (0x2UL << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000002 */ +#define USB_OTG_DCFG_NZLSOHSK_Pos (2U) +#define USB_OTG_DCFG_NZLSOHSK_Msk (0x1UL << USB_OTG_DCFG_NZLSOHSK_Pos) /*!< 0x00000004 */ +#define USB_OTG_DCFG_NZLSOHSK USB_OTG_DCFG_NZLSOHSK_Msk /*!< Nonzero-length status OUT handshake */ + +#define USB_OTG_DCFG_DAD_Pos (4U) +#define USB_OTG_DCFG_DAD_Msk (0x7FUL << USB_OTG_DCFG_DAD_Pos) /*!< 0x000007F0 */ +#define USB_OTG_DCFG_DAD USB_OTG_DCFG_DAD_Msk /*!< Device address */ +#define USB_OTG_DCFG_DAD_0 (0x01UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000010 */ +#define USB_OTG_DCFG_DAD_1 (0x02UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000020 */ +#define USB_OTG_DCFG_DAD_2 (0x04UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000040 */ +#define USB_OTG_DCFG_DAD_3 (0x08UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000080 */ +#define USB_OTG_DCFG_DAD_4 (0x10UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000100 */ +#define USB_OTG_DCFG_DAD_5 (0x20UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000200 */ +#define USB_OTG_DCFG_DAD_6 (0x40UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000400 */ + +#define USB_OTG_DCFG_PFIVL_Pos (11U) +#define USB_OTG_DCFG_PFIVL_Msk (0x3UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001800 */ +#define USB_OTG_DCFG_PFIVL USB_OTG_DCFG_PFIVL_Msk /*!< Periodic (micro)frame interval */ +#define USB_OTG_DCFG_PFIVL_0 (0x1UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00000800 */ +#define USB_OTG_DCFG_PFIVL_1 (0x2UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001000 */ + +#define USB_OTG_DCFG_XCVRDLY_Pos (14U) +#define USB_OTG_DCFG_XCVRDLY_Msk (0x1UL << USB_OTG_DCFG_XCVRDLY_Pos) /*!< 0x00004000 */ +#define USB_OTG_DCFG_XCVRDLY USB_OTG_DCFG_XCVRDLY_Msk /*!< Transceiver delay */ + +#define USB_OTG_DCFG_ERRATIM_Pos (15U) +#define USB_OTG_DCFG_ERRATIM_Msk (0x1UL << USB_OTG_DCFG_ERRATIM_Pos) /*!< 0x00008000 */ +#define USB_OTG_DCFG_ERRATIM USB_OTG_DCFG_ERRATIM_Msk /*!< Erratic error interrupt mask */ + +#define USB_OTG_DCFG_DESCDMA_Pos (23U) +#define USB_OTG_DCFG_DESCDMA_Msk (0x1UL << USB_OTG_DCFG_DESCDMA_Pos) +#define USB_OTG_DCFG_DESCDMA USB_OTG_DCFG_DESCDMA_Msk + +#define USB_OTG_DCFG_PERSCHIVL_Pos (24U) +#define USB_OTG_DCFG_PERSCHIVL_Msk (0x3UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x03000000 */ +#define USB_OTG_DCFG_PERSCHIVL USB_OTG_DCFG_PERSCHIVL_Msk /*!< Periodic scheduling interval */ +#define USB_OTG_DCFG_PERSCHIVL_0 (0x1UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x01000000 */ +#define USB_OTG_DCFG_PERSCHIVL_1 (0x2UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x02000000 */ + +/******************** Bit definition for USB_OTG_PCGCR register ********************/ +#define USB_OTG_PCGCR_STPPCLK_Pos (0U) +#define USB_OTG_PCGCR_STPPCLK_Msk (0x1UL << USB_OTG_PCGCR_STPPCLK_Pos) /*!< 0x00000001 */ +#define USB_OTG_PCGCR_STPPCLK USB_OTG_PCGCR_STPPCLK_Msk /*!< Stop PHY clock */ +#define USB_OTG_PCGCR_GATEHCLK_Pos (1U) +#define USB_OTG_PCGCR_GATEHCLK_Msk (0x1UL << USB_OTG_PCGCR_GATEHCLK_Pos) /*!< 0x00000002 */ +#define USB_OTG_PCGCR_GATEHCLK USB_OTG_PCGCR_GATEHCLK_Msk /*!< Gate HCLK */ +#define USB_OTG_PCGCR_PHYSUSP_Pos (4U) +#define USB_OTG_PCGCR_PHYSUSP_Msk (0x1UL << USB_OTG_PCGCR_PHYSUSP_Pos) /*!< 0x00000010 */ +#define USB_OTG_PCGCR_PHYSUSP USB_OTG_PCGCR_PHYSUSP_Msk /*!< PHY suspended */ + +/******************** Bit definition for USB_OTG_GOTGINT register ********************/ +#define USB_OTG_GOTGINT_SEDET_Pos (2U) +#define USB_OTG_GOTGINT_SEDET_Msk (0x1UL << USB_OTG_GOTGINT_SEDET_Pos) /*!< 0x00000004 */ +#define USB_OTG_GOTGINT_SEDET USB_OTG_GOTGINT_SEDET_Msk /*!< Session end detected */ +#define USB_OTG_GOTGINT_SRSSCHG_Pos (8U) +#define USB_OTG_GOTGINT_SRSSCHG_Msk (0x1UL << USB_OTG_GOTGINT_SRSSCHG_Pos) /*!< 0x00000100 */ +#define USB_OTG_GOTGINT_SRSSCHG USB_OTG_GOTGINT_SRSSCHG_Msk /*!< Session request success status change */ +#define USB_OTG_GOTGINT_HNSSCHG_Pos (9U) +#define USB_OTG_GOTGINT_HNSSCHG_Msk (0x1UL << USB_OTG_GOTGINT_HNSSCHG_Pos) /*!< 0x00000200 */ +#define USB_OTG_GOTGINT_HNSSCHG USB_OTG_GOTGINT_HNSSCHG_Msk /*!< Host negotiation success status change */ +#define USB_OTG_GOTGINT_HNGDET_Pos (17U) +#define USB_OTG_GOTGINT_HNGDET_Msk (0x1UL << USB_OTG_GOTGINT_HNGDET_Pos) /*!< 0x00020000 */ +#define USB_OTG_GOTGINT_HNGDET USB_OTG_GOTGINT_HNGDET_Msk /*!< Host negotiation detected */ +#define USB_OTG_GOTGINT_ADTOCHG_Pos (18U) +#define USB_OTG_GOTGINT_ADTOCHG_Msk (0x1UL << USB_OTG_GOTGINT_ADTOCHG_Pos) /*!< 0x00040000 */ +#define USB_OTG_GOTGINT_ADTOCHG USB_OTG_GOTGINT_ADTOCHG_Msk /*!< A-device timeout change */ +#define USB_OTG_GOTGINT_DBCDNE_Pos (19U) +#define USB_OTG_GOTGINT_DBCDNE_Msk (0x1UL << USB_OTG_GOTGINT_DBCDNE_Pos) /*!< 0x00080000 */ +#define USB_OTG_GOTGINT_DBCDNE USB_OTG_GOTGINT_DBCDNE_Msk /*!< Debounce done */ + +/******************** Bit definition for USB_OTG_DCTL register ********************/ +#define USB_OTG_DCTL_RWUSIG_Pos (0U) +#define USB_OTG_DCTL_RWUSIG_Msk (0x1UL << USB_OTG_DCTL_RWUSIG_Pos) /*!< 0x00000001 */ +#define USB_OTG_DCTL_RWUSIG USB_OTG_DCTL_RWUSIG_Msk /*!< Remote wakeup signaling */ +#define USB_OTG_DCTL_SDIS_Pos (1U) +#define USB_OTG_DCTL_SDIS_Msk (0x1UL << USB_OTG_DCTL_SDIS_Pos) /*!< 0x00000002 */ +#define USB_OTG_DCTL_SDIS USB_OTG_DCTL_SDIS_Msk /*!< Soft disconnect */ +#define USB_OTG_DCTL_GINSTS_Pos (2U) +#define USB_OTG_DCTL_GINSTS_Msk (0x1UL << USB_OTG_DCTL_GINSTS_Pos) /*!< 0x00000004 */ +#define USB_OTG_DCTL_GINSTS USB_OTG_DCTL_GINSTS_Msk /*!< Global IN NAK status */ +#define USB_OTG_DCTL_GONSTS_Pos (3U) +#define USB_OTG_DCTL_GONSTS_Msk (0x1UL << USB_OTG_DCTL_GONSTS_Pos) /*!< 0x00000008 */ +#define USB_OTG_DCTL_GONSTS USB_OTG_DCTL_GONSTS_Msk /*!< Global OUT NAK status */ + +#define USB_OTG_DCTL_TCTL_Pos (4U) +#define USB_OTG_DCTL_TCTL_Msk (0x7UL << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000070 */ +#define USB_OTG_DCTL_TCTL USB_OTG_DCTL_TCTL_Msk /*!< Test control */ +#define USB_OTG_DCTL_TCTL_0 (0x1UL << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000010 */ +#define USB_OTG_DCTL_TCTL_1 (0x2UL << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000020 */ +#define USB_OTG_DCTL_TCTL_2 (0x4UL << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000040 */ +#define USB_OTG_DCTL_SGINAK_Pos (7U) +#define USB_OTG_DCTL_SGINAK_Msk (0x1UL << USB_OTG_DCTL_SGINAK_Pos) /*!< 0x00000080 */ +#define USB_OTG_DCTL_SGINAK USB_OTG_DCTL_SGINAK_Msk /*!< Set global IN NAK */ +#define USB_OTG_DCTL_CGINAK_Pos (8U) +#define USB_OTG_DCTL_CGINAK_Msk (0x1UL << USB_OTG_DCTL_CGINAK_Pos) /*!< 0x00000100 */ +#define USB_OTG_DCTL_CGINAK USB_OTG_DCTL_CGINAK_Msk /*!< Clear global IN NAK */ +#define USB_OTG_DCTL_SGONAK_Pos (9U) +#define USB_OTG_DCTL_SGONAK_Msk (0x1UL << USB_OTG_DCTL_SGONAK_Pos) /*!< 0x00000200 */ +#define USB_OTG_DCTL_SGONAK USB_OTG_DCTL_SGONAK_Msk /*!< Set global OUT NAK */ +#define USB_OTG_DCTL_CGONAK_Pos (10U) +#define USB_OTG_DCTL_CGONAK_Msk (0x1UL << USB_OTG_DCTL_CGONAK_Pos) /*!< 0x00000400 */ +#define USB_OTG_DCTL_CGONAK USB_OTG_DCTL_CGONAK_Msk /*!< Clear global OUT NAK */ +#define USB_OTG_DCTL_POPRGDNE_Pos (11U) +#define USB_OTG_DCTL_POPRGDNE_Msk (0x1UL << USB_OTG_DCTL_POPRGDNE_Pos) /*!< 0x00000800 */ +#define USB_OTG_DCTL_POPRGDNE USB_OTG_DCTL_POPRGDNE_Msk /*!< Power-on programming done */ + +/******************** Bit definition for USB_OTG_HFIR register ********************/ +#define USB_OTG_HFIR_FRIVL_Pos (0U) +#define USB_OTG_HFIR_FRIVL_Msk (0xFFFFUL << USB_OTG_HFIR_FRIVL_Pos) /*!< 0x0000FFFF */ +#define USB_OTG_HFIR_FRIVL USB_OTG_HFIR_FRIVL_Msk /*!< Frame interval */ +#define USB_OTG_HFIR_RELOAD_CTRL_Pos (16U) +#define USB_OTG_HFIR_RELOAD_CTRL_Msk (0x1UL << USB_OTG_HFIR_RELOAD_CTRL_Pos) +#define USB_OTG_HFIR_RELOAD_CTRL USB_OTG_HFIR_RELOAD_CTRL_Msk + +/******************** Bit definition for USB_OTG_HFNUM register ********************/ +#define USB_OTG_HFNUM_FRNUM_Pos (0U) +#define USB_OTG_HFNUM_FRNUM_Msk (0xFFFFUL << USB_OTG_HFNUM_FRNUM_Pos) /*!< 0x0000FFFF */ +#define USB_OTG_HFNUM_FRNUM USB_OTG_HFNUM_FRNUM_Msk /*!< Frame number */ +#define USB_OTG_HFNUM_FTREM_Pos (16U) +#define USB_OTG_HFNUM_FTREM_Msk (0xFFFFUL << USB_OTG_HFNUM_FTREM_Pos) /*!< 0xFFFF0000 */ +#define USB_OTG_HFNUM_FTREM USB_OTG_HFNUM_FTREM_Msk /*!< Frame time remaining */ + +/******************** Bit definition for USB_OTG_DSTS register ********************/ +#define USB_OTG_DSTS_SUSPSTS_Pos (0U) +#define USB_OTG_DSTS_SUSPSTS_Msk (0x1UL << USB_OTG_DSTS_SUSPSTS_Pos) /*!< 0x00000001 */ +#define USB_OTG_DSTS_SUSPSTS USB_OTG_DSTS_SUSPSTS_Msk /*!< Suspend status */ + +#define USB_OTG_DSTS_ENUMSPD_Pos (1U) +#define USB_OTG_DSTS_ENUMSPD_Msk (0x3UL << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000006 */ +#define USB_OTG_DSTS_ENUMSPD USB_OTG_DSTS_ENUMSPD_Msk /*!< Enumerated speed */ +#define USB_OTG_DSTS_ENUMSPD_0 (0x1UL << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000002 */ +#define USB_OTG_DSTS_ENUMSPD_1 (0x2UL << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000004 */ +#define USB_OTG_DSTS_EERR_Pos (3U) +#define USB_OTG_DSTS_EERR_Msk (0x1UL << USB_OTG_DSTS_EERR_Pos) /*!< 0x00000008 */ +#define USB_OTG_DSTS_EERR USB_OTG_DSTS_EERR_Msk /*!< Erratic error */ +#define USB_OTG_DSTS_FNSOF_Pos (8U) +#define USB_OTG_DSTS_FNSOF_Msk (0x3FFFUL << USB_OTG_DSTS_FNSOF_Pos) /*!< 0x003FFF00 */ +#define USB_OTG_DSTS_FNSOF USB_OTG_DSTS_FNSOF_Msk /*!< Frame number of the received SOF */ + +/******************** Bit definition for USB_OTG_GAHBCFG register ********************/ +#define USB_OTG_GAHBCFG_GINT_Pos (0U) +#define USB_OTG_GAHBCFG_GINT_Msk (0x1UL << USB_OTG_GAHBCFG_GINT_Pos) /*!< 0x00000001 */ +#define USB_OTG_GAHBCFG_GINT USB_OTG_GAHBCFG_GINT_Msk /*!< Global interrupt mask */ +#define USB_OTG_GAHBCFG_HBSTLEN_Pos (1U) +#define USB_OTG_GAHBCFG_HBSTLEN_Msk (0xFUL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< 0x0000001E */ +#define USB_OTG_GAHBCFG_HBSTLEN USB_OTG_GAHBCFG_HBSTLEN_Msk /*!< Burst length/type */ +#define USB_OTG_GAHBCFG_HBSTLEN_0 (0x0UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< Single */ +#define USB_OTG_GAHBCFG_HBSTLEN_1 (0x1UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR */ +#define USB_OTG_GAHBCFG_HBSTLEN_2 (0x3UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR4 */ +#define USB_OTG_GAHBCFG_HBSTLEN_3 (0x5UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR8 */ +#define USB_OTG_GAHBCFG_HBSTLEN_4 (0x7UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR16 */ +#define USB_OTG_GAHBCFG_DMAEN_Pos (5U) +#define USB_OTG_GAHBCFG_DMAEN_Msk (0x1UL << USB_OTG_GAHBCFG_DMAEN_Pos) /*!< 0x00000020 */ +#define USB_OTG_GAHBCFG_DMAEN USB_OTG_GAHBCFG_DMAEN_Msk /*!< DMA enable */ +#define USB_OTG_GAHBCFG_TXFELVL_Pos (7U) +#define USB_OTG_GAHBCFG_TXFELVL_Msk (0x1UL << USB_OTG_GAHBCFG_TXFELVL_Pos) /*!< 0x00000080 */ +#define USB_OTG_GAHBCFG_TXFELVL USB_OTG_GAHBCFG_TXFELVL_Msk /*!< TxFIFO empty level */ +#define USB_OTG_GAHBCFG_PTXFELVL_Pos (8U) +#define USB_OTG_GAHBCFG_PTXFELVL_Msk (0x1UL << USB_OTG_GAHBCFG_PTXFELVL_Pos) /*!< 0x00000100 */ +#define USB_OTG_GAHBCFG_PTXFELVL USB_OTG_GAHBCFG_PTXFELVL_Msk /*!< Periodic TxFIFO empty level */ + +/******************** Bit definition for USB_OTG_GUSBCFG register ********************/ + +#define USB_OTG_GUSBCFG_TOCAL_Pos (0U) +#define USB_OTG_GUSBCFG_TOCAL_Msk (0x7UL << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000007 */ +#define USB_OTG_GUSBCFG_TOCAL USB_OTG_GUSBCFG_TOCAL_Msk /*!< FS timeout calibration */ +#define USB_OTG_GUSBCFG_PHYIF_Pos (3U) +#define USB_OTG_GUSBCFG_PHYIF_Msk (0x1UL << USB_OTG_GUSBCFG_PHYIF_Pos) +#define USB_OTG_GUSBCFG_PHYIF USB_OTG_GUSBCFG_PHYIF_Msk +#define USB_OTG_GUSBCFG_PHYIF8 (0x0UL << USB_OTG_GUSBCFG_PHYIF_Pos) +#define USB_OTG_GUSBCFG_PHYIF16 (0x1UL << USB_OTG_GUSBCFG_PHYIF_Pos) +#define USB_OTG_GUSBCFG_ULPI_UTMI_SEL_Pos (4U) +#define USB_OTG_GUSBCFG_ULPI_UTMI_SEL_Msk (0x1UL << USB_OTG_GUSBCFG_ULPI_UTMI_SEL_Pos) +#define USB_OTG_GUSBCFG_ULPI_UTMI_SEL USB_OTG_GUSBCFG_ULPI_UTMI_SEL_Msk +#define USB_OTG_GUSBCFG_PHYSEL_Pos (6U) +#define USB_OTG_GUSBCFG_PHYSEL_Msk (0x1UL << USB_OTG_GUSBCFG_PHYSEL_Pos) /*!< 0x00000040 */ +#define USB_OTG_GUSBCFG_PHYSEL USB_OTG_GUSBCFG_PHYSEL_Msk /*!< USB 2.0 high-speed ULPI PHY or USB 1.1 full-speed serial transceiver select */ +#define USB_OTG_GUSBCFG_DDR_SEL_Pos (7U) +#define USB_OTG_GUSBCFG_DDR_SEL_Msk (0x1UL << USB_OTG_GUSBCFG_DDR_SEL_Pos) +#define USB_OTG_GUSBCFG_DDR_SEL USB_OTG_GUSBCFG_DDR_SEL_Msk +#define USB_OTG_GUSBCFG_SRPCAP_Pos (8U) +#define USB_OTG_GUSBCFG_SRPCAP_Msk (0x1UL << USB_OTG_GUSBCFG_SRPCAP_Pos) /*!< 0x00000100 */ +#define USB_OTG_GUSBCFG_SRPCAP USB_OTG_GUSBCFG_SRPCAP_Msk /*!< SRP-capable */ +#define USB_OTG_GUSBCFG_HNPCAP_Pos (9U) +#define USB_OTG_GUSBCFG_HNPCAP_Msk (0x1UL << USB_OTG_GUSBCFG_HNPCAP_Pos) /*!< 0x00000200 */ +#define USB_OTG_GUSBCFG_HNPCAP USB_OTG_GUSBCFG_HNPCAP_Msk /*!< HNP-capable */ +#define USB_OTG_GUSBCFG_TRDT_Pos (10U) +#define USB_OTG_GUSBCFG_TRDT_Msk (0xFUL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00003C00 */ +#define USB_OTG_GUSBCFG_TRDT USB_OTG_GUSBCFG_TRDT_Msk /*!< USB turnaround time */ +#define USB_OTG_GUSBCFG_TRDT_0 (0x1UL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00000400 */ +#define USB_OTG_GUSBCFG_TRDT_1 (0x2UL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00000800 */ +#define USB_OTG_GUSBCFG_TRDT_2 (0x4UL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00001000 */ +#define USB_OTG_GUSBCFG_TRDT_3 (0x8UL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00002000 */ +#define USB_OTG_GUSBCFG_PHYLPCS_Pos (15U) +#define USB_OTG_GUSBCFG_PHYLPCS_Msk (0x1UL << USB_OTG_GUSBCFG_PHYLPCS_Pos) /*!< 0x00008000 */ +#define USB_OTG_GUSBCFG_PHYLPCS USB_OTG_GUSBCFG_PHYLPCS_Msk /*!< PHY Low-power clock select */ +#define USB_OTG_GUSBCFG_ULPIFSLS_Pos (17U) +#define USB_OTG_GUSBCFG_ULPIFSLS_Msk (0x1UL << USB_OTG_GUSBCFG_ULPIFSLS_Pos) /*!< 0x00020000 */ +#define USB_OTG_GUSBCFG_ULPIFSLS USB_OTG_GUSBCFG_ULPIFSLS_Msk /*!< ULPI FS/LS select */ +#define USB_OTG_GUSBCFG_ULPIAR_Pos (18U) +#define USB_OTG_GUSBCFG_ULPIAR_Msk (0x1UL << USB_OTG_GUSBCFG_ULPIAR_Pos) /*!< 0x00040000 */ +#define USB_OTG_GUSBCFG_ULPIAR USB_OTG_GUSBCFG_ULPIAR_Msk /*!< ULPI Auto-resume */ +#define USB_OTG_GUSBCFG_ULPICSM_Pos (19U) +#define USB_OTG_GUSBCFG_ULPICSM_Msk (0x1UL << USB_OTG_GUSBCFG_ULPICSM_Pos) /*!< 0x00080000 */ +#define USB_OTG_GUSBCFG_ULPICSM USB_OTG_GUSBCFG_ULPICSM_Msk /*!< ULPI Clock SuspendM */ +#define USB_OTG_GUSBCFG_ULPIEVBUSD_Pos (20U) +#define USB_OTG_GUSBCFG_ULPIEVBUSD_Msk (0x1UL << USB_OTG_GUSBCFG_ULPIEVBUSD_Pos) /*!< 0x00100000 */ +#define USB_OTG_GUSBCFG_ULPIEVBUSD USB_OTG_GUSBCFG_ULPIEVBUSD_Msk /*!< ULPI External VBUS Drive */ +#define USB_OTG_GUSBCFG_ULPIEVBUSI_Pos (21U) +#define USB_OTG_GUSBCFG_ULPIEVBUSI_Msk (0x1UL << USB_OTG_GUSBCFG_ULPIEVBUSI_Pos) /*!< 0x00200000 */ +#define USB_OTG_GUSBCFG_ULPIEVBUSI USB_OTG_GUSBCFG_ULPIEVBUSI_Msk /*!< ULPI external VBUS indicator */ +#define USB_OTG_GUSBCFG_TSDPS_Pos (22U) +#define USB_OTG_GUSBCFG_TSDPS_Msk (0x1UL << USB_OTG_GUSBCFG_TSDPS_Pos) /*!< 0x00400000 */ +#define USB_OTG_GUSBCFG_TSDPS USB_OTG_GUSBCFG_TSDPS_Msk /*!< TermSel DLine pulsing selection */ +#define USB_OTG_GUSBCFG_PCCI_Pos (23U) +#define USB_OTG_GUSBCFG_PCCI_Msk (0x1UL << USB_OTG_GUSBCFG_PCCI_Pos) /*!< 0x00800000 */ +#define USB_OTG_GUSBCFG_PCCI USB_OTG_GUSBCFG_PCCI_Msk /*!< Indicator complement */ +#define USB_OTG_GUSBCFG_PTCI_Pos (24U) +#define USB_OTG_GUSBCFG_PTCI_Msk (0x1UL << USB_OTG_GUSBCFG_PTCI_Pos) /*!< 0x01000000 */ +#define USB_OTG_GUSBCFG_PTCI USB_OTG_GUSBCFG_PTCI_Msk /*!< Indicator pass through */ +#define USB_OTG_GUSBCFG_ULPIIPD_Pos (25U) +#define USB_OTG_GUSBCFG_ULPIIPD_Msk (0x1UL << USB_OTG_GUSBCFG_ULPIIPD_Pos) /*!< 0x02000000 */ +#define USB_OTG_GUSBCFG_ULPIIPD USB_OTG_GUSBCFG_ULPIIPD_Msk /*!< ULPI interface protect disable */ +#define USB_OTG_GUSBCFG_FHMOD_Pos (29U) +#define USB_OTG_GUSBCFG_FHMOD_Msk (0x1UL << USB_OTG_GUSBCFG_FHMOD_Pos) /*!< 0x20000000 */ +#define USB_OTG_GUSBCFG_FHMOD USB_OTG_GUSBCFG_FHMOD_Msk /*!< Forced host mode */ +#define USB_OTG_GUSBCFG_FDMOD_Pos (30U) +#define USB_OTG_GUSBCFG_FDMOD_Msk (0x1UL << USB_OTG_GUSBCFG_FDMOD_Pos) /*!< 0x40000000 */ +#define USB_OTG_GUSBCFG_FDMOD USB_OTG_GUSBCFG_FDMOD_Msk /*!< Forced peripheral mode */ +#define USB_OTG_GUSBCFG_CTXPKT_Pos (31U) +#define USB_OTG_GUSBCFG_CTXPKT_Msk (0x1UL << USB_OTG_GUSBCFG_CTXPKT_Pos) /*!< 0x80000000 */ +#define USB_OTG_GUSBCFG_CTXPKT USB_OTG_GUSBCFG_CTXPKT_Msk /*!< Corrupt Tx packet */ + +/******************** Bit definition for USB_OTG_GRSTCTL register ********************/ +#define USB_OTG_GRSTCTL_CSRST_Pos (0U) +#define USB_OTG_GRSTCTL_CSRST_Msk (0x1UL << USB_OTG_GRSTCTL_CSRST_Pos) /*!< 0x00000001 */ +#define USB_OTG_GRSTCTL_CSRST USB_OTG_GRSTCTL_CSRST_Msk /*!< Core soft reset */ +#define USB_OTG_GRSTCTL_HSRST_Pos (1U) +#define USB_OTG_GRSTCTL_HSRST_Msk (0x1UL << USB_OTG_GRSTCTL_HSRST_Pos) /*!< 0x00000002 */ +#define USB_OTG_GRSTCTL_HSRST USB_OTG_GRSTCTL_HSRST_Msk /*!< HCLK soft reset */ +#define USB_OTG_GRSTCTL_FCRST_Pos (2U) +#define USB_OTG_GRSTCTL_FCRST_Msk (0x1UL << USB_OTG_GRSTCTL_FCRST_Pos) /*!< 0x00000004 */ +#define USB_OTG_GRSTCTL_FCRST USB_OTG_GRSTCTL_FCRST_Msk /*!< Host frame counter reset */ +#define USB_OTG_GRSTCTL_RXFFLSH_Pos (4U) +#define USB_OTG_GRSTCTL_RXFFLSH_Msk (0x1UL << USB_OTG_GRSTCTL_RXFFLSH_Pos) /*!< 0x00000010 */ +#define USB_OTG_GRSTCTL_RXFFLSH USB_OTG_GRSTCTL_RXFFLSH_Msk /*!< RxFIFO flush */ +#define USB_OTG_GRSTCTL_TXFFLSH_Pos (5U) +#define USB_OTG_GRSTCTL_TXFFLSH_Msk (0x1UL << USB_OTG_GRSTCTL_TXFFLSH_Pos) /*!< 0x00000020 */ +#define USB_OTG_GRSTCTL_TXFFLSH USB_OTG_GRSTCTL_TXFFLSH_Msk /*!< TxFIFO flush */ +#define USB_OTG_GRSTCTL_CSRSTDONE_Pos (29U) +#define USB_OTG_GRSTCTL_CSRSTDONE_Msk (0x1UL << USB_OTG_GRSTCTL_CSRSTDONE_Pos) /*!< 0x20000000 */ +#define USB_OTG_GRSTCTL_CSRSTDONE USB_OTG_GRSTCTL_CSRSTDONE_Msk /*!< Core soft reset done */ + +#define USB_OTG_GRSTCTL_TXFNUM_Pos (6U) +#define USB_OTG_GRSTCTL_TXFNUM_Msk (0x1FUL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x000007C0 */ +#define USB_OTG_GRSTCTL_TXFNUM USB_OTG_GRSTCTL_TXFNUM_Msk /*!< TxFIFO number */ +#define USB_OTG_GRSTCTL_TXFNUM_0 (0x01UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000040 */ +#define USB_OTG_GRSTCTL_TXFNUM_1 (0x02UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000080 */ +#define USB_OTG_GRSTCTL_TXFNUM_2 (0x04UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000100 */ +#define USB_OTG_GRSTCTL_TXFNUM_3 (0x08UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000200 */ +#define USB_OTG_GRSTCTL_TXFNUM_4 (0x10UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000400 */ +#define USB_OTG_GRSTCTL_DMAREQ_Pos (30U) +#define USB_OTG_GRSTCTL_DMAREQ_Msk (0x1UL << USB_OTG_GRSTCTL_DMAREQ_Pos) /*!< 0x40000000 */ +#define USB_OTG_GRSTCTL_DMAREQ USB_OTG_GRSTCTL_DMAREQ_Msk /*!< DMA request signal */ +#define USB_OTG_GRSTCTL_AHBIDL_Pos (31U) +#define USB_OTG_GRSTCTL_AHBIDL_Msk (0x1UL << USB_OTG_GRSTCTL_AHBIDL_Pos) /*!< 0x80000000 */ +#define USB_OTG_GRSTCTL_AHBIDL USB_OTG_GRSTCTL_AHBIDL_Msk /*!< AHB master idle */ + +/******************** Bit definition for USB_OTG_DIEPMSK register ********************/ +#define USB_OTG_DIEPMSK_XFRCM_Pos (0U) +#define USB_OTG_DIEPMSK_XFRCM_Msk (0x1UL << USB_OTG_DIEPMSK_XFRCM_Pos) /*!< 0x00000001 */ +#define USB_OTG_DIEPMSK_XFRCM USB_OTG_DIEPMSK_XFRCM_Msk /*!< Transfer completed interrupt mask */ +#define USB_OTG_DIEPMSK_EPDM_Pos (1U) +#define USB_OTG_DIEPMSK_EPDM_Msk (0x1UL << USB_OTG_DIEPMSK_EPDM_Pos) /*!< 0x00000002 */ +#define USB_OTG_DIEPMSK_EPDM USB_OTG_DIEPMSK_EPDM_Msk /*!< Endpoint disabled interrupt mask */ +#define USB_OTG_DIEPMSK_TOM_Pos (3U) +#define USB_OTG_DIEPMSK_TOM_Msk (0x1UL << USB_OTG_DIEPMSK_TOM_Pos) /*!< 0x00000008 */ +#define USB_OTG_DIEPMSK_TOM USB_OTG_DIEPMSK_TOM_Msk /*!< Timeout condition mask (nonisochronous endpoints) */ +#define USB_OTG_DIEPMSK_ITTXFEMSK_Pos (4U) +#define USB_OTG_DIEPMSK_ITTXFEMSK_Msk (0x1UL << USB_OTG_DIEPMSK_ITTXFEMSK_Pos) /*!< 0x00000010 */ +#define USB_OTG_DIEPMSK_ITTXFEMSK USB_OTG_DIEPMSK_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask */ +#define USB_OTG_DIEPMSK_INEPNMM_Pos (5U) +#define USB_OTG_DIEPMSK_INEPNMM_Msk (0x1UL << USB_OTG_DIEPMSK_INEPNMM_Pos) /*!< 0x00000020 */ +#define USB_OTG_DIEPMSK_INEPNMM USB_OTG_DIEPMSK_INEPNMM_Msk /*!< IN token received with EP mismatch mask */ +#define USB_OTG_DIEPMSK_INEPNEM_Pos (6U) +#define USB_OTG_DIEPMSK_INEPNEM_Msk (0x1UL << USB_OTG_DIEPMSK_INEPNEM_Pos) /*!< 0x00000040 */ +#define USB_OTG_DIEPMSK_INEPNEM USB_OTG_DIEPMSK_INEPNEM_Msk /*!< IN endpoint NAK effective mask */ +#define USB_OTG_DIEPMSK_TXFURM_Pos (8U) +#define USB_OTG_DIEPMSK_TXFURM_Msk (0x1UL << USB_OTG_DIEPMSK_TXFURM_Pos) /*!< 0x00000100 */ +#define USB_OTG_DIEPMSK_TXFURM USB_OTG_DIEPMSK_TXFURM_Msk /*!< FIFO underrun mask */ +#define USB_OTG_DIEPMSK_BIM_Pos (9U) +#define USB_OTG_DIEPMSK_BIM_Msk (0x1UL << USB_OTG_DIEPMSK_BIM_Pos) /*!< 0x00000200 */ +#define USB_OTG_DIEPMSK_BIM USB_OTG_DIEPMSK_BIM_Msk /*!< BNA interrupt mask */ + +/******************** Bit definition for USB_OTG_HPTXSTS register ********************/ +#define USB_OTG_HPTXSTS_PTXFSAVL_Pos (0U) +#define USB_OTG_HPTXSTS_PTXFSAVL_Msk (0xFFFFUL << USB_OTG_HPTXSTS_PTXFSAVL_Pos) /*!< 0x0000FFFF */ +#define USB_OTG_HPTXSTS_PTXFSAVL USB_OTG_HPTXSTS_PTXFSAVL_Msk /*!< Periodic transmit data FIFO space available */ +#define USB_OTG_HPTXSTS_PTXQSAV_Pos (16U) +#define USB_OTG_HPTXSTS_PTXQSAV_Msk (0xFFUL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00FF0000 */ +#define USB_OTG_HPTXSTS_PTXQSAV USB_OTG_HPTXSTS_PTXQSAV_Msk /*!< Periodic transmit request queue space available */ +#define USB_OTG_HPTXSTS_PTXQSAV_0 (0x01UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00010000 */ +#define USB_OTG_HPTXSTS_PTXQSAV_1 (0x02UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00020000 */ +#define USB_OTG_HPTXSTS_PTXQSAV_2 (0x04UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00040000 */ +#define USB_OTG_HPTXSTS_PTXQSAV_3 (0x08UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00080000 */ +#define USB_OTG_HPTXSTS_PTXQSAV_4 (0x10UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00100000 */ +#define USB_OTG_HPTXSTS_PTXQSAV_5 (0x20UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00200000 */ +#define USB_OTG_HPTXSTS_PTXQSAV_6 (0x40UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00400000 */ +#define USB_OTG_HPTXSTS_PTXQSAV_7 (0x80UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00800000 */ + +#define USB_OTG_HPTXSTS_PTXQTOP_Pos (24U) +#define USB_OTG_HPTXSTS_PTXQTOP_Msk (0xFFUL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0xFF000000 */ +#define USB_OTG_HPTXSTS_PTXQTOP USB_OTG_HPTXSTS_PTXQTOP_Msk /*!< Top of the periodic transmit request queue */ +#define USB_OTG_HPTXSTS_PTXQTOP_0 (0x01UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x01000000 */ +#define USB_OTG_HPTXSTS_PTXQTOP_1 (0x02UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x02000000 */ +#define USB_OTG_HPTXSTS_PTXQTOP_2 (0x04UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x04000000 */ +#define USB_OTG_HPTXSTS_PTXQTOP_3 (0x08UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x08000000 */ +#define USB_OTG_HPTXSTS_PTXQTOP_4 (0x10UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x10000000 */ +#define USB_OTG_HPTXSTS_PTXQTOP_5 (0x20UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x20000000 */ +#define USB_OTG_HPTXSTS_PTXQTOP_6 (0x40UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x40000000 */ +#define USB_OTG_HPTXSTS_PTXQTOP_7 (0x80UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x80000000 */ + +/******************** Bit definition for USB_OTG_HAINT register ********************/ +#define USB_OTG_HAINT_HAINT_Pos (0U) +#define USB_OTG_HAINT_HAINT_Msk (0xFFFFUL << USB_OTG_HAINT_HAINT_Pos) /*!< 0x0000FFFF */ +#define USB_OTG_HAINT_HAINT USB_OTG_HAINT_HAINT_Msk /*!< Channel interrupts */ + +/******************** Bit definition for USB_OTG_DOEPMSK register ********************/ +#define USB_OTG_DOEPMSK_XFRCM_Pos (0U) +#define USB_OTG_DOEPMSK_XFRCM_Msk (0x1UL << USB_OTG_DOEPMSK_XFRCM_Pos) /*!< 0x00000001 */ +#define USB_OTG_DOEPMSK_XFRCM USB_OTG_DOEPMSK_XFRCM_Msk /*!< Transfer completed interrupt mask */ +#define USB_OTG_DOEPMSK_EPDM_Pos (1U) +#define USB_OTG_DOEPMSK_EPDM_Msk (0x1UL << USB_OTG_DOEPMSK_EPDM_Pos) /*!< 0x00000002 */ +#define USB_OTG_DOEPMSK_EPDM USB_OTG_DOEPMSK_EPDM_Msk /*!< Endpoint disabled interrupt mask */ +#define USB_OTG_DOEPMSK_AHBERRM_Pos (2U) +#define USB_OTG_DOEPMSK_AHBERRM_Msk (0x1UL << USB_OTG_DOEPMSK_AHBERRM_Pos) /*!< 0x00000004 */ +#define USB_OTG_DOEPMSK_AHBERRM USB_OTG_DOEPMSK_AHBERRM_Msk /*!< OUT transaction AHB Error interrupt mask */ +#define USB_OTG_DOEPMSK_STUPM_Pos (3U) +#define USB_OTG_DOEPMSK_STUPM_Msk (0x1UL << USB_OTG_DOEPMSK_STUPM_Pos) /*!< 0x00000008 */ +#define USB_OTG_DOEPMSK_STUPM USB_OTG_DOEPMSK_STUPM_Msk /*!< SETUP phase done mask */ +#define USB_OTG_DOEPMSK_OTEPDM_Pos (4U) +#define USB_OTG_DOEPMSK_OTEPDM_Msk (0x1UL << USB_OTG_DOEPMSK_OTEPDM_Pos) /*!< 0x00000010 */ +#define USB_OTG_DOEPMSK_OTEPDM USB_OTG_DOEPMSK_OTEPDM_Msk /*!< OUT token received when endpoint disabled mask */ +#define USB_OTG_DOEPMSK_OTEPSPRM_Pos (5U) +#define USB_OTG_DOEPMSK_OTEPSPRM_Msk (0x1UL << USB_OTG_DOEPMSK_OTEPSPRM_Pos) /*!< 0x00000020 */ +#define USB_OTG_DOEPMSK_OTEPSPRM USB_OTG_DOEPMSK_OTEPSPRM_Msk /*!< Status Phase Received mask */ +#define USB_OTG_DOEPMSK_B2BSTUP_Pos (6U) +#define USB_OTG_DOEPMSK_B2BSTUP_Msk (0x1UL << USB_OTG_DOEPMSK_B2BSTUP_Pos) /*!< 0x00000040 */ +#define USB_OTG_DOEPMSK_B2BSTUP USB_OTG_DOEPMSK_B2BSTUP_Msk /*!< Back-to-back SETUP packets received mask */ +#define USB_OTG_DOEPMSK_OPEM_Pos (8U) +#define USB_OTG_DOEPMSK_OPEM_Msk (0x1UL << USB_OTG_DOEPMSK_OPEM_Pos) /*!< 0x00000100 */ +#define USB_OTG_DOEPMSK_OPEM USB_OTG_DOEPMSK_OPEM_Msk /*!< OUT packet error mask */ +#define USB_OTG_DOEPMSK_BOIM_Pos (9U) +#define USB_OTG_DOEPMSK_BOIM_Msk (0x1UL << USB_OTG_DOEPMSK_BOIM_Pos) /*!< 0x00000200 */ +#define USB_OTG_DOEPMSK_BOIM USB_OTG_DOEPMSK_BOIM_Msk /*!< BNA interrupt mask */ +#define USB_OTG_DOEPMSK_BERRM_Pos (12U) +#define USB_OTG_DOEPMSK_BERRM_Msk (0x1UL << USB_OTG_DOEPMSK_BERRM_Pos) /*!< 0x00001000 */ +#define USB_OTG_DOEPMSK_BERRM USB_OTG_DOEPMSK_BERRM_Msk /*!< Babble error interrupt mask */ +#define USB_OTG_DOEPMSK_NAKM_Pos (13U) +#define USB_OTG_DOEPMSK_NAKM_Msk (0x1UL << USB_OTG_DOEPMSK_NAKM_Pos) /*!< 0x00002000 */ +#define USB_OTG_DOEPMSK_NAKM USB_OTG_DOEPMSK_NAKM_Msk /*!< OUT Packet NAK interrupt mask */ +#define USB_OTG_DOEPMSK_NYETM_Pos (14U) +#define USB_OTG_DOEPMSK_NYETM_Msk (0x1UL << USB_OTG_DOEPMSK_NYETM_Pos) /*!< 0x00004000 */ +#define USB_OTG_DOEPMSK_NYETM USB_OTG_DOEPMSK_NYETM_Msk /*!< NYET interrupt mask */ +/******************** Bit definition for USB_OTG_GINTSTS register ********************/ +#define USB_OTG_GINTSTS_CMOD_Pos (0U) +#define USB_OTG_GINTSTS_CMOD_Msk (0x1UL << USB_OTG_GINTSTS_CMOD_Pos) /*!< 0x00000001 */ +#define USB_OTG_GINTSTS_CMOD USB_OTG_GINTSTS_CMOD_Msk /*!< Current mode of operation */ +#define USB_OTG_GINTSTS_MMIS_Pos (1U) +#define USB_OTG_GINTSTS_MMIS_Msk (0x1UL << USB_OTG_GINTSTS_MMIS_Pos) /*!< 0x00000002 */ +#define USB_OTG_GINTSTS_MMIS USB_OTG_GINTSTS_MMIS_Msk /*!< Mode mismatch interrupt */ +#define USB_OTG_GINTSTS_OTGINT_Pos (2U) +#define USB_OTG_GINTSTS_OTGINT_Msk (0x1UL << USB_OTG_GINTSTS_OTGINT_Pos) /*!< 0x00000004 */ +#define USB_OTG_GINTSTS_OTGINT USB_OTG_GINTSTS_OTGINT_Msk /*!< OTG interrupt */ +#define USB_OTG_GINTSTS_SOF_Pos (3U) +#define USB_OTG_GINTSTS_SOF_Msk (0x1UL << USB_OTG_GINTSTS_SOF_Pos) /*!< 0x00000008 */ +#define USB_OTG_GINTSTS_SOF USB_OTG_GINTSTS_SOF_Msk /*!< Start of frame */ +#define USB_OTG_GINTSTS_RXFLVL_Pos (4U) +#define USB_OTG_GINTSTS_RXFLVL_Msk (0x1UL << USB_OTG_GINTSTS_RXFLVL_Pos) /*!< 0x00000010 */ +#define USB_OTG_GINTSTS_RXFLVL USB_OTG_GINTSTS_RXFLVL_Msk /*!< RxFIFO nonempty */ +#define USB_OTG_GINTSTS_NPTXFE_Pos (5U) +#define USB_OTG_GINTSTS_NPTXFE_Msk (0x1UL << USB_OTG_GINTSTS_NPTXFE_Pos) /*!< 0x00000020 */ +#define USB_OTG_GINTSTS_NPTXFE USB_OTG_GINTSTS_NPTXFE_Msk /*!< Nonperiodic TxFIFO empty */ +#define USB_OTG_GINTSTS_GINAKEFF_Pos (6U) +#define USB_OTG_GINTSTS_GINAKEFF_Msk (0x1UL << USB_OTG_GINTSTS_GINAKEFF_Pos) /*!< 0x00000040 */ +#define USB_OTG_GINTSTS_GINAKEFF USB_OTG_GINTSTS_GINAKEFF_Msk /*!< Global IN nonperiodic NAK effective */ +#define USB_OTG_GINTSTS_BOUTNAKEFF_Pos (7U) +#define USB_OTG_GINTSTS_BOUTNAKEFF_Msk (0x1UL << USB_OTG_GINTSTS_BOUTNAKEFF_Pos) /*!< 0x00000080 */ +#define USB_OTG_GINTSTS_BOUTNAKEFF USB_OTG_GINTSTS_BOUTNAKEFF_Msk /*!< Global OUT NAK effective */ +#define USB_OTG_GINTSTS_ESUSP_Pos (10U) +#define USB_OTG_GINTSTS_ESUSP_Msk (0x1UL << USB_OTG_GINTSTS_ESUSP_Pos) /*!< 0x00000400 */ +#define USB_OTG_GINTSTS_ESUSP USB_OTG_GINTSTS_ESUSP_Msk /*!< Early suspend */ +#define USB_OTG_GINTSTS_USBSUSP_Pos (11U) +#define USB_OTG_GINTSTS_USBSUSP_Msk (0x1UL << USB_OTG_GINTSTS_USBSUSP_Pos) /*!< 0x00000800 */ +#define USB_OTG_GINTSTS_USBSUSP USB_OTG_GINTSTS_USBSUSP_Msk /*!< USB suspend */ +#define USB_OTG_GINTSTS_USBRST_Pos (12U) +#define USB_OTG_GINTSTS_USBRST_Msk (0x1UL << USB_OTG_GINTSTS_USBRST_Pos) /*!< 0x00001000 */ +#define USB_OTG_GINTSTS_USBRST USB_OTG_GINTSTS_USBRST_Msk /*!< USB reset */ +#define USB_OTG_GINTSTS_ENUMDNE_Pos (13U) +#define USB_OTG_GINTSTS_ENUMDNE_Msk (0x1UL << USB_OTG_GINTSTS_ENUMDNE_Pos) /*!< 0x00002000 */ +#define USB_OTG_GINTSTS_ENUMDNE USB_OTG_GINTSTS_ENUMDNE_Msk /*!< Enumeration done */ +#define USB_OTG_GINTSTS_ISOODRP_Pos (14U) +#define USB_OTG_GINTSTS_ISOODRP_Msk (0x1UL << USB_OTG_GINTSTS_ISOODRP_Pos) /*!< 0x00004000 */ +#define USB_OTG_GINTSTS_ISOODRP USB_OTG_GINTSTS_ISOODRP_Msk /*!< Isochronous OUT packet dropped interrupt */ +#define USB_OTG_GINTSTS_EOPF_Pos (15U) +#define USB_OTG_GINTSTS_EOPF_Msk (0x1UL << USB_OTG_GINTSTS_EOPF_Pos) /*!< 0x00008000 */ +#define USB_OTG_GINTSTS_EOPF USB_OTG_GINTSTS_EOPF_Msk /*!< End of periodic frame interrupt */ +#define USB_OTG_GINTSTS_IEPINT_Pos (18U) +#define USB_OTG_GINTSTS_IEPINT_Msk (0x1UL << USB_OTG_GINTSTS_IEPINT_Pos) /*!< 0x00040000 */ +#define USB_OTG_GINTSTS_IEPINT USB_OTG_GINTSTS_IEPINT_Msk /*!< IN endpoint interrupt */ +#define USB_OTG_GINTSTS_OEPINT_Pos (19U) +#define USB_OTG_GINTSTS_OEPINT_Msk (0x1UL << USB_OTG_GINTSTS_OEPINT_Pos) /*!< 0x00080000 */ +#define USB_OTG_GINTSTS_OEPINT USB_OTG_GINTSTS_OEPINT_Msk /*!< OUT endpoint interrupt */ +#define USB_OTG_GINTSTS_IISOIXFR_Pos (20U) +#define USB_OTG_GINTSTS_IISOIXFR_Msk (0x1UL << USB_OTG_GINTSTS_IISOIXFR_Pos) /*!< 0x00100000 */ +#define USB_OTG_GINTSTS_IISOIXFR USB_OTG_GINTSTS_IISOIXFR_Msk /*!< Incomplete isochronous IN transfer */ +#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Pos (21U) +#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Msk (0x1UL << USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Pos) /*!< 0x00200000 */ +#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Msk /*!< Incomplete periodic transfer */ +#define USB_OTG_GINTSTS_DATAFSUSP_Pos (22U) +#define USB_OTG_GINTSTS_DATAFSUSP_Msk (0x1UL << USB_OTG_GINTSTS_DATAFSUSP_Pos) /*!< 0x00400000 */ +#define USB_OTG_GINTSTS_DATAFSUSP USB_OTG_GINTSTS_DATAFSUSP_Msk /*!< Data fetch suspended */ +#define USB_OTG_GINTSTS_RSTDET_Pos (23U) +#define USB_OTG_GINTSTS_RSTDET_Msk (0x1UL << USB_OTG_GINTSTS_RSTDET_Pos) /*!< 0x00800000 */ +#define USB_OTG_GINTSTS_RSTDET USB_OTG_GINTSTS_RSTDET_Msk /*!< Reset detected interrupt */ +#define USB_OTG_GINTSTS_HPRTINT_Pos (24U) +#define USB_OTG_GINTSTS_HPRTINT_Msk (0x1UL << USB_OTG_GINTSTS_HPRTINT_Pos) /*!< 0x01000000 */ +#define USB_OTG_GINTSTS_HPRTINT USB_OTG_GINTSTS_HPRTINT_Msk /*!< Host port interrupt */ +#define USB_OTG_GINTSTS_HCINT_Pos (25U) +#define USB_OTG_GINTSTS_HCINT_Msk (0x1UL << USB_OTG_GINTSTS_HCINT_Pos) /*!< 0x02000000 */ +#define USB_OTG_GINTSTS_HCINT USB_OTG_GINTSTS_HCINT_Msk /*!< Host channels interrupt */ +#define USB_OTG_GINTSTS_PTXFE_Pos (26U) +#define USB_OTG_GINTSTS_PTXFE_Msk (0x1UL << USB_OTG_GINTSTS_PTXFE_Pos) /*!< 0x04000000 */ +#define USB_OTG_GINTSTS_PTXFE USB_OTG_GINTSTS_PTXFE_Msk /*!< Periodic TxFIFO empty */ +#define USB_OTG_GINTSTS_LPMINT_Pos (27U) +#define USB_OTG_GINTSTS_LPMINT_Msk (0x1UL << USB_OTG_GINTSTS_LPMINT_Pos) /*!< 0x08000000 */ +#define USB_OTG_GINTSTS_LPMINT USB_OTG_GINTSTS_LPMINT_Msk /*!< LPM interrupt */ +#define USB_OTG_GINTSTS_CIDSCHG_Pos (28U) +#define USB_OTG_GINTSTS_CIDSCHG_Msk (0x1UL << USB_OTG_GINTSTS_CIDSCHG_Pos) /*!< 0x10000000 */ +#define USB_OTG_GINTSTS_CIDSCHG USB_OTG_GINTSTS_CIDSCHG_Msk /*!< Connector ID status change */ +#define USB_OTG_GINTSTS_DISCINT_Pos (29U) +#define USB_OTG_GINTSTS_DISCINT_Msk (0x1UL << USB_OTG_GINTSTS_DISCINT_Pos) /*!< 0x20000000 */ +#define USB_OTG_GINTSTS_DISCINT USB_OTG_GINTSTS_DISCINT_Msk /*!< Disconnect detected interrupt */ +#define USB_OTG_GINTSTS_SRQINT_Pos (30U) +#define USB_OTG_GINTSTS_SRQINT_Msk (0x1UL << USB_OTG_GINTSTS_SRQINT_Pos) /*!< 0x40000000 */ +#define USB_OTG_GINTSTS_SRQINT USB_OTG_GINTSTS_SRQINT_Msk /*!< Session request/new session detected interrupt */ +#define USB_OTG_GINTSTS_WKUINT_Pos (31U) +#define USB_OTG_GINTSTS_WKUINT_Msk (0x1UL << USB_OTG_GINTSTS_WKUINT_Pos) /*!< 0x80000000 */ +#define USB_OTG_GINTSTS_WKUINT USB_OTG_GINTSTS_WKUINT_Msk /*!< Resume/remote wakeup detected interrupt */ + +/******************** Bit definition for USB_OTG_GINTMSK register ********************/ +#define USB_OTG_GINTMSK_MMISM_Pos (1U) +#define USB_OTG_GINTMSK_MMISM_Msk (0x1UL << USB_OTG_GINTMSK_MMISM_Pos) /*!< 0x00000002 */ +#define USB_OTG_GINTMSK_MMISM USB_OTG_GINTMSK_MMISM_Msk /*!< Mode mismatch interrupt mask */ +#define USB_OTG_GINTMSK_OTGINT_Pos (2U) +#define USB_OTG_GINTMSK_OTGINT_Msk (0x1UL << USB_OTG_GINTMSK_OTGINT_Pos) /*!< 0x00000004 */ +#define USB_OTG_GINTMSK_OTGINT USB_OTG_GINTMSK_OTGINT_Msk /*!< OTG interrupt mask */ +#define USB_OTG_GINTMSK_SOFM_Pos (3U) +#define USB_OTG_GINTMSK_SOFM_Msk (0x1UL << USB_OTG_GINTMSK_SOFM_Pos) /*!< 0x00000008 */ +#define USB_OTG_GINTMSK_SOFM USB_OTG_GINTMSK_SOFM_Msk /*!< Start of frame mask */ +#define USB_OTG_GINTMSK_RXFLVLM_Pos (4U) +#define USB_OTG_GINTMSK_RXFLVLM_Msk (0x1UL << USB_OTG_GINTMSK_RXFLVLM_Pos) /*!< 0x00000010 */ +#define USB_OTG_GINTMSK_RXFLVLM USB_OTG_GINTMSK_RXFLVLM_Msk /*!< Receive FIFO nonempty mask */ +#define USB_OTG_GINTMSK_NPTXFEM_Pos (5U) +#define USB_OTG_GINTMSK_NPTXFEM_Msk (0x1UL << USB_OTG_GINTMSK_NPTXFEM_Pos) /*!< 0x00000020 */ +#define USB_OTG_GINTMSK_NPTXFEM USB_OTG_GINTMSK_NPTXFEM_Msk /*!< Nonperiodic TxFIFO empty mask */ +#define USB_OTG_GINTMSK_GINAKEFFM_Pos (6U) +#define USB_OTG_GINTMSK_GINAKEFFM_Msk (0x1UL << USB_OTG_GINTMSK_GINAKEFFM_Pos) /*!< 0x00000040 */ +#define USB_OTG_GINTMSK_GINAKEFFM USB_OTG_GINTMSK_GINAKEFFM_Msk /*!< Global nonperiodic IN NAK effective mask */ +#define USB_OTG_GINTMSK_GONAKEFFM_Pos (7U) +#define USB_OTG_GINTMSK_GONAKEFFM_Msk (0x1UL << USB_OTG_GINTMSK_GONAKEFFM_Pos) /*!< 0x00000080 */ +#define USB_OTG_GINTMSK_GONAKEFFM USB_OTG_GINTMSK_GONAKEFFM_Msk /*!< Global OUT NAK effective mask */ +#define USB_OTG_GINTMSK_ESUSPM_Pos (10U) +#define USB_OTG_GINTMSK_ESUSPM_Msk (0x1UL << USB_OTG_GINTMSK_ESUSPM_Pos) /*!< 0x00000400 */ +#define USB_OTG_GINTMSK_ESUSPM USB_OTG_GINTMSK_ESUSPM_Msk /*!< Early suspend mask */ +#define USB_OTG_GINTMSK_USBSUSPM_Pos (11U) +#define USB_OTG_GINTMSK_USBSUSPM_Msk (0x1UL << USB_OTG_GINTMSK_USBSUSPM_Pos) /*!< 0x00000800 */ +#define USB_OTG_GINTMSK_USBSUSPM USB_OTG_GINTMSK_USBSUSPM_Msk /*!< USB suspend mask */ +#define USB_OTG_GINTMSK_USBRST_Pos (12U) +#define USB_OTG_GINTMSK_USBRST_Msk (0x1UL << USB_OTG_GINTMSK_USBRST_Pos) /*!< 0x00001000 */ +#define USB_OTG_GINTMSK_USBRST USB_OTG_GINTMSK_USBRST_Msk /*!< USB reset mask */ +#define USB_OTG_GINTMSK_ENUMDNEM_Pos (13U) +#define USB_OTG_GINTMSK_ENUMDNEM_Msk (0x1UL << USB_OTG_GINTMSK_ENUMDNEM_Pos) /*!< 0x00002000 */ +#define USB_OTG_GINTMSK_ENUMDNEM USB_OTG_GINTMSK_ENUMDNEM_Msk /*!< Enumeration done mask */ +#define USB_OTG_GINTMSK_ISOODRPM_Pos (14U) +#define USB_OTG_GINTMSK_ISOODRPM_Msk (0x1UL << USB_OTG_GINTMSK_ISOODRPM_Pos) /*!< 0x00004000 */ +#define USB_OTG_GINTMSK_ISOODRPM USB_OTG_GINTMSK_ISOODRPM_Msk /*!< Isochronous OUT packet dropped interrupt mask */ +#define USB_OTG_GINTMSK_EOPFM_Pos (15U) +#define USB_OTG_GINTMSK_EOPFM_Msk (0x1UL << USB_OTG_GINTMSK_EOPFM_Pos) /*!< 0x00008000 */ +#define USB_OTG_GINTMSK_EOPFM USB_OTG_GINTMSK_EOPFM_Msk /*!< End of periodic frame interrupt mask */ +#define USB_OTG_GINTMSK_EPMISM_Pos (17U) +#define USB_OTG_GINTMSK_EPMISM_Msk (0x1UL << USB_OTG_GINTMSK_EPMISM_Pos) /*!< 0x00020000 */ +#define USB_OTG_GINTMSK_EPMISM USB_OTG_GINTMSK_EPMISM_Msk /*!< Endpoint mismatch interrupt mask */ +#define USB_OTG_GINTMSK_IEPINT_Pos (18U) +#define USB_OTG_GINTMSK_IEPINT_Msk (0x1UL << USB_OTG_GINTMSK_IEPINT_Pos) /*!< 0x00040000 */ +#define USB_OTG_GINTMSK_IEPINT USB_OTG_GINTMSK_IEPINT_Msk /*!< IN endpoints interrupt mask */ +#define USB_OTG_GINTMSK_OEPINT_Pos (19U) +#define USB_OTG_GINTMSK_OEPINT_Msk (0x1UL << USB_OTG_GINTMSK_OEPINT_Pos) /*!< 0x00080000 */ +#define USB_OTG_GINTMSK_OEPINT USB_OTG_GINTMSK_OEPINT_Msk /*!< OUT endpoints interrupt mask */ +#define USB_OTG_GINTMSK_IISOIXFRM_Pos (20U) +#define USB_OTG_GINTMSK_IISOIXFRM_Msk (0x1UL << USB_OTG_GINTMSK_IISOIXFRM_Pos) /*!< 0x00100000 */ +#define USB_OTG_GINTMSK_IISOIXFRM USB_OTG_GINTMSK_IISOIXFRM_Msk /*!< Incomplete isochronous IN transfer mask */ +#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos (21U) +#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk (0x1UL << USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos) /*!< 0x00200000 */ +#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk /*!< Incomplete periodic transfer mask */ +#define USB_OTG_GINTMSK_FSUSPM_Pos (22U) +#define USB_OTG_GINTMSK_FSUSPM_Msk (0x1UL << USB_OTG_GINTMSK_FSUSPM_Pos) /*!< 0x00400000 */ +#define USB_OTG_GINTMSK_FSUSPM USB_OTG_GINTMSK_FSUSPM_Msk /*!< Data fetch suspended mask */ +#define USB_OTG_GINTMSK_RSTDEM_Pos (23U) +#define USB_OTG_GINTMSK_RSTDEM_Msk (0x1UL << USB_OTG_GINTMSK_RSTDEM_Pos) /*!< 0x00800000 */ +#define USB_OTG_GINTMSK_RSTDEM USB_OTG_GINTMSK_RSTDEM_Msk /*!< Reset detected interrupt mask */ +#define USB_OTG_GINTMSK_PRTIM_Pos (24U) +#define USB_OTG_GINTMSK_PRTIM_Msk (0x1UL << USB_OTG_GINTMSK_PRTIM_Pos) /*!< 0x01000000 */ +#define USB_OTG_GINTMSK_PRTIM USB_OTG_GINTMSK_PRTIM_Msk /*!< Host port interrupt mask */ +#define USB_OTG_GINTMSK_HCIM_Pos (25U) +#define USB_OTG_GINTMSK_HCIM_Msk (0x1UL << USB_OTG_GINTMSK_HCIM_Pos) /*!< 0x02000000 */ +#define USB_OTG_GINTMSK_HCIM USB_OTG_GINTMSK_HCIM_Msk /*!< Host channels interrupt mask */ +#define USB_OTG_GINTMSK_PTXFEM_Pos (26U) +#define USB_OTG_GINTMSK_PTXFEM_Msk (0x1UL << USB_OTG_GINTMSK_PTXFEM_Pos) /*!< 0x04000000 */ +#define USB_OTG_GINTMSK_PTXFEM USB_OTG_GINTMSK_PTXFEM_Msk /*!< Periodic TxFIFO empty mask */ +#define USB_OTG_GINTMSK_LPMINTM_Pos (27U) +#define USB_OTG_GINTMSK_LPMINTM_Msk (0x1UL << USB_OTG_GINTMSK_LPMINTM_Pos) /*!< 0x08000000 */ +#define USB_OTG_GINTMSK_LPMINTM USB_OTG_GINTMSK_LPMINTM_Msk /*!< LPM interrupt Mask */ +#define USB_OTG_GINTMSK_CIDSCHGM_Pos (28U) +#define USB_OTG_GINTMSK_CIDSCHGM_Msk (0x1UL << USB_OTG_GINTMSK_CIDSCHGM_Pos) /*!< 0x10000000 */ +#define USB_OTG_GINTMSK_CIDSCHGM USB_OTG_GINTMSK_CIDSCHGM_Msk /*!< Connector ID status change mask */ +#define USB_OTG_GINTMSK_DISCINT_Pos (29U) +#define USB_OTG_GINTMSK_DISCINT_Msk (0x1UL << USB_OTG_GINTMSK_DISCINT_Pos) /*!< 0x20000000 */ +#define USB_OTG_GINTMSK_DISCINT USB_OTG_GINTMSK_DISCINT_Msk /*!< Disconnect detected interrupt mask */ +#define USB_OTG_GINTMSK_SRQIM_Pos (30U) +#define USB_OTG_GINTMSK_SRQIM_Msk (0x1UL << USB_OTG_GINTMSK_SRQIM_Pos) /*!< 0x40000000 */ +#define USB_OTG_GINTMSK_SRQIM USB_OTG_GINTMSK_SRQIM_Msk /*!< Session request/new session detected interrupt mask */ +#define USB_OTG_GINTMSK_WUIM_Pos (31U) +#define USB_OTG_GINTMSK_WUIM_Msk (0x1UL << USB_OTG_GINTMSK_WUIM_Pos) /*!< 0x80000000 */ +#define USB_OTG_GINTMSK_WUIM USB_OTG_GINTMSK_WUIM_Msk /*!< Resume/remote wakeup detected interrupt mask */ + +/******************** Bit definition for USB_OTG_DAINT register ********************/ +#define USB_OTG_DAINT_IEPINT_Pos (0U) +#define USB_OTG_DAINT_IEPINT_Msk (0xFFFFUL << USB_OTG_DAINT_IEPINT_Pos) /*!< 0x0000FFFF */ +#define USB_OTG_DAINT_IEPINT USB_OTG_DAINT_IEPINT_Msk /*!< IN endpoint interrupt bits */ +#define USB_OTG_DAINT_OEPINT_Pos (16U) +#define USB_OTG_DAINT_OEPINT_Msk (0xFFFFUL << USB_OTG_DAINT_OEPINT_Pos) /*!< 0xFFFF0000 */ +#define USB_OTG_DAINT_OEPINT USB_OTG_DAINT_OEPINT_Msk /*!< OUT endpoint interrupt bits */ + +/******************** Bit definition for OTG register ********************/ +#define USB_OTG_CHNUM_Pos (0U) +#define USB_OTG_CHNUM_Msk (0xFUL << USB_OTG_CHNUM_Pos) /*!< 0x0000000F */ +#define USB_OTG_CHNUM USB_OTG_CHNUM_Msk /*!< Channel number */ +#define USB_OTG_CHNUM_0 (0x1UL << USB_OTG_CHNUM_Pos) /*!< 0x00000001 */ +#define USB_OTG_CHNUM_1 (0x2UL << USB_OTG_CHNUM_Pos) /*!< 0x00000002 */ +#define USB_OTG_CHNUM_2 (0x4UL << USB_OTG_CHNUM_Pos) /*!< 0x00000004 */ +#define USB_OTG_CHNUM_3 (0x8UL << USB_OTG_CHNUM_Pos) /*!< 0x00000008 */ +#define USB_OTG_BCNT_Pos (4U) +#define USB_OTG_BCNT_Msk (0x7FFUL << USB_OTG_BCNT_Pos) /*!< 0x00007FF0 */ +#define USB_OTG_BCNT USB_OTG_BCNT_Msk /*!< Byte count */ + +#define USB_OTG_DPID_Pos (15U) +#define USB_OTG_DPID_Msk (0x3UL << USB_OTG_DPID_Pos) /*!< 0x00018000 */ +#define USB_OTG_DPID USB_OTG_DPID_Msk /*!< Data PID */ +#define USB_OTG_DPID_0 (0x1UL << USB_OTG_DPID_Pos) /*!< 0x00008000 */ +#define USB_OTG_DPID_1 (0x2UL << USB_OTG_DPID_Pos) /*!< 0x00010000 */ + +#define USB_OTG_PKTSTS_Pos (17U) +#define USB_OTG_PKTSTS_Msk (0xFUL << USB_OTG_PKTSTS_Pos) /*!< 0x001E0000 */ +#define USB_OTG_PKTSTS USB_OTG_PKTSTS_Msk /*!< Packet status */ +#define USB_OTG_PKTSTS_0 (0x1UL << USB_OTG_PKTSTS_Pos) /*!< 0x00020000 */ +#define USB_OTG_PKTSTS_1 (0x2UL << USB_OTG_PKTSTS_Pos) /*!< 0x00040000 */ +#define USB_OTG_PKTSTS_2 (0x4UL << USB_OTG_PKTSTS_Pos) /*!< 0x00080000 */ +#define USB_OTG_PKTSTS_3 (0x8UL << USB_OTG_PKTSTS_Pos) /*!< 0x00100000 */ + +#define USB_OTG_EPNUM_Pos (0U) +#define USB_OTG_EPNUM_Msk (0xFUL << USB_OTG_EPNUM_Pos) /*!< 0x0000000F */ +#define USB_OTG_EPNUM USB_OTG_EPNUM_Msk /*!< Endpoint number */ +#define USB_OTG_EPNUM_0 (0x1UL << USB_OTG_EPNUM_Pos) /*!< 0x00000001 */ +#define USB_OTG_EPNUM_1 (0x2UL << USB_OTG_EPNUM_Pos) /*!< 0x00000002 */ +#define USB_OTG_EPNUM_2 (0x4UL << USB_OTG_EPNUM_Pos) /*!< 0x00000004 */ +#define USB_OTG_EPNUM_3 (0x8UL << USB_OTG_EPNUM_Pos) /*!< 0x00000008 */ + +#define USB_OTG_FRMNUM_Pos (21U) +#define USB_OTG_FRMNUM_Msk (0xFUL << USB_OTG_FRMNUM_Pos) /*!< 0x01E00000 */ +#define USB_OTG_FRMNUM USB_OTG_FRMNUM_Msk /*!< Frame number */ +#define USB_OTG_FRMNUM_0 (0x1UL << USB_OTG_FRMNUM_Pos) /*!< 0x00200000 */ +#define USB_OTG_FRMNUM_1 (0x2UL << USB_OTG_FRMNUM_Pos) /*!< 0x00400000 */ +#define USB_OTG_FRMNUM_2 (0x4UL << USB_OTG_FRMNUM_Pos) /*!< 0x00800000 */ +#define USB_OTG_FRMNUM_3 (0x8UL << USB_OTG_FRMNUM_Pos) /*!< 0x01000000 */ + +/******************** Bit definition for USB_OTG_HAINTMSK register ********************/ +#define USB_OTG_HAINTMSK_HAINTM_Pos (0U) +#define USB_OTG_HAINTMSK_HAINTM_Msk (0xFFFFUL << USB_OTG_HAINTMSK_HAINTM_Pos) /*!< 0x0000FFFF */ +#define USB_OTG_HAINTMSK_HAINTM USB_OTG_HAINTMSK_HAINTM_Msk /*!< Channel interrupt mask */ + +/******************** Bit definition for USB_OTG_GRXSTSP register ********************/ +#define USB_OTG_GRXSTSP_EPNUM_Pos (0U) +#define USB_OTG_GRXSTSP_EPNUM_Msk (0xFUL << USB_OTG_GRXSTSP_EPNUM_Pos) /*!< 0x0000000F */ +#define USB_OTG_GRXSTSP_EPNUM USB_OTG_GRXSTSP_EPNUM_Msk /*!< IN EP interrupt mask bits */ +#define USB_OTG_GRXSTSP_BCNT_Pos (4U) +#define USB_OTG_GRXSTSP_BCNT_Msk (0x7FFUL << USB_OTG_GRXSTSP_BCNT_Pos) /*!< 0x00007FF0 */ +#define USB_OTG_GRXSTSP_BCNT USB_OTG_GRXSTSP_BCNT_Msk /*!< OUT EP interrupt mask bits */ +#define USB_OTG_GRXSTSP_DPID_Pos (15U) +#define USB_OTG_GRXSTSP_DPID_Msk (0x3UL << USB_OTG_GRXSTSP_DPID_Pos) /*!< 0x00018000 */ +#define USB_OTG_GRXSTSP_DPID USB_OTG_GRXSTSP_DPID_Msk /*!< OUT EP interrupt mask bits */ +#define USB_OTG_GRXSTSP_PKTSTS_Pos (17U) +#define USB_OTG_GRXSTSP_PKTSTS_Msk (0xFUL << USB_OTG_GRXSTSP_PKTSTS_Pos) /*!< 0x001E0000 */ +#define USB_OTG_GRXSTSP_PKTSTS USB_OTG_GRXSTSP_PKTSTS_Msk /*!< OUT EP interrupt mask bits */ + +/******************** Bit definition for USB_OTG_DAINTMSK register ********************/ +#define USB_OTG_DAINTMSK_IEPM_Pos (0U) +#define USB_OTG_DAINTMSK_IEPM_Msk (0xFFFFUL << USB_OTG_DAINTMSK_IEPM_Pos) /*!< 0x0000FFFF */ +#define USB_OTG_DAINTMSK_IEPM USB_OTG_DAINTMSK_IEPM_Msk /*!< IN EP interrupt mask bits */ +#define USB_OTG_DAINTMSK_OEPM_Pos (16U) +#define USB_OTG_DAINTMSK_OEPM_Msk (0xFFFFUL << USB_OTG_DAINTMSK_OEPM_Pos) /*!< 0xFFFF0000 */ +#define USB_OTG_DAINTMSK_OEPM USB_OTG_DAINTMSK_OEPM_Msk /*!< OUT EP interrupt mask bits */ + +/******************** Bit definition for USB_OTG_GRXFSIZ register ********************/ +#define USB_OTG_GRXFSIZ_RXFD_Pos (0U) +#define USB_OTG_GRXFSIZ_RXFD_Msk (0xFFFFUL << USB_OTG_GRXFSIZ_RXFD_Pos) /*!< 0x0000FFFF */ +#define USB_OTG_GRXFSIZ_RXFD USB_OTG_GRXFSIZ_RXFD_Msk /*!< RxFIFO depth */ + +/******************** Bit definition for USB_OTG_DVBUSDIS register ********************/ +#define USB_OTG_DVBUSDIS_VBUSDT_Pos (0U) +#define USB_OTG_DVBUSDIS_VBUSDT_Msk (0xFFFFUL << USB_OTG_DVBUSDIS_VBUSDT_Pos) /*!< 0x0000FFFF */ +#define USB_OTG_DVBUSDIS_VBUSDT USB_OTG_DVBUSDIS_VBUSDT_Msk /*!< Device VBUS discharge time */ + +/******************** Bit definition for OTG register ********************/ +#define USB_OTG_NPTXFSA_Pos (0U) +#define USB_OTG_NPTXFSA_Msk (0xFFFFUL << USB_OTG_NPTXFSA_Pos) /*!< 0x0000FFFF */ +#define USB_OTG_NPTXFSA USB_OTG_NPTXFSA_Msk /*!< Nonperiodic transmit RAM start address */ +#define USB_OTG_NPTXFD_Pos (16U) +#define USB_OTG_NPTXFD_Msk (0xFFFFUL << USB_OTG_NPTXFD_Pos) /*!< 0xFFFF0000 */ +#define USB_OTG_NPTXFD USB_OTG_NPTXFD_Msk /*!< Nonperiodic TxFIFO depth */ +#define USB_OTG_TX0FSA_Pos (0U) +#define USB_OTG_TX0FSA_Msk (0xFFFFUL << USB_OTG_TX0FSA_Pos) /*!< 0x0000FFFF */ +#define USB_OTG_TX0FSA USB_OTG_TX0FSA_Msk /*!< Endpoint 0 transmit RAM start address */ +#define USB_OTG_TX0FD_Pos (16U) +#define USB_OTG_TX0FD_Msk (0xFFFFUL << USB_OTG_TX0FD_Pos) /*!< 0xFFFF0000 */ +#define USB_OTG_TX0FD USB_OTG_TX0FD_Msk /*!< Endpoint 0 TxFIFO depth */ + +/******************** Bit definition forUSB_OTG_DVBUSPULSE register ********************/ +#define USB_OTG_DVBUSPULSE_DVBUSP_Pos (0U) +#define USB_OTG_DVBUSPULSE_DVBUSP_Msk (0xFFFUL << USB_OTG_DVBUSPULSE_DVBUSP_Pos) /*!< 0x00000FFF */ +#define USB_OTG_DVBUSPULSE_DVBUSP USB_OTG_DVBUSPULSE_DVBUSP_Msk /*!< Device VBUS pulsing time */ + +/******************** Bit definition for USB_OTG_GNPTXSTS register ********************/ +#define USB_OTG_GNPTXSTS_NPTXFSAV_Pos (0U) +#define USB_OTG_GNPTXSTS_NPTXFSAV_Msk (0xFFFFUL << USB_OTG_GNPTXSTS_NPTXFSAV_Pos) /*!< 0x0000FFFF */ +#define USB_OTG_GNPTXSTS_NPTXFSAV USB_OTG_GNPTXSTS_NPTXFSAV_Msk /*!< Nonperiodic TxFIFO space available */ + +#define USB_OTG_GNPTXSTS_NPTQXSAV_Pos (16U) +#define USB_OTG_GNPTXSTS_NPTQXSAV_Msk (0xFFUL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00FF0000 */ +#define USB_OTG_GNPTXSTS_NPTQXSAV USB_OTG_GNPTXSTS_NPTQXSAV_Msk /*!< Nonperiodic transmit request queue space available */ +#define USB_OTG_GNPTXSTS_NPTQXSAV_0 (0x01UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00010000 */ +#define USB_OTG_GNPTXSTS_NPTQXSAV_1 (0x02UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00020000 */ +#define USB_OTG_GNPTXSTS_NPTQXSAV_2 (0x04UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00040000 */ +#define USB_OTG_GNPTXSTS_NPTQXSAV_3 (0x08UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00080000 */ +#define USB_OTG_GNPTXSTS_NPTQXSAV_4 (0x10UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00100000 */ +#define USB_OTG_GNPTXSTS_NPTQXSAV_5 (0x20UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00200000 */ +#define USB_OTG_GNPTXSTS_NPTQXSAV_6 (0x40UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00400000 */ +#define USB_OTG_GNPTXSTS_NPTQXSAV_7 (0x80UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00800000 */ + +#define USB_OTG_GNPTXSTS_NPTXQTOP_Pos (24U) +#define USB_OTG_GNPTXSTS_NPTXQTOP_Msk (0x7FUL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x7F000000 */ +#define USB_OTG_GNPTXSTS_NPTXQTOP USB_OTG_GNPTXSTS_NPTXQTOP_Msk /*!< Top of the nonperiodic transmit request queue */ +#define USB_OTG_GNPTXSTS_NPTXQTOP_0 (0x01UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x01000000 */ +#define USB_OTG_GNPTXSTS_NPTXQTOP_1 (0x02UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x02000000 */ +#define USB_OTG_GNPTXSTS_NPTXQTOP_2 (0x04UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x04000000 */ +#define USB_OTG_GNPTXSTS_NPTXQTOP_3 (0x08UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x08000000 */ +#define USB_OTG_GNPTXSTS_NPTXQTOP_4 (0x10UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x10000000 */ +#define USB_OTG_GNPTXSTS_NPTXQTOP_5 (0x20UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x20000000 */ +#define USB_OTG_GNPTXSTS_NPTXQTOP_6 (0x40UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x40000000 */ + +/******************** Bit definition for USB_OTG_DTHRCTL register ********************/ +#define USB_OTG_DTHRCTL_NONISOTHREN_Pos (0U) +#define USB_OTG_DTHRCTL_NONISOTHREN_Msk (0x1UL << USB_OTG_DTHRCTL_NONISOTHREN_Pos) /*!< 0x00000001 */ +#define USB_OTG_DTHRCTL_NONISOTHREN USB_OTG_DTHRCTL_NONISOTHREN_Msk /*!< Nonisochronous IN endpoints threshold enable */ +#define USB_OTG_DTHRCTL_ISOTHREN_Pos (1U) +#define USB_OTG_DTHRCTL_ISOTHREN_Msk (0x1UL << USB_OTG_DTHRCTL_ISOTHREN_Pos) /*!< 0x00000002 */ +#define USB_OTG_DTHRCTL_ISOTHREN USB_OTG_DTHRCTL_ISOTHREN_Msk /*!< ISO IN endpoint threshold enable */ + +#define USB_OTG_DTHRCTL_TXTHRLEN_Pos (2U) +#define USB_OTG_DTHRCTL_TXTHRLEN_Msk (0x1FFUL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x000007FC */ +#define USB_OTG_DTHRCTL_TXTHRLEN USB_OTG_DTHRCTL_TXTHRLEN_Msk /*!< Transmit threshold length */ +#define USB_OTG_DTHRCTL_TXTHRLEN_0 (0x001UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000004 */ +#define USB_OTG_DTHRCTL_TXTHRLEN_1 (0x002UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000008 */ +#define USB_OTG_DTHRCTL_TXTHRLEN_2 (0x004UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000010 */ +#define USB_OTG_DTHRCTL_TXTHRLEN_3 (0x008UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000020 */ +#define USB_OTG_DTHRCTL_TXTHRLEN_4 (0x010UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000040 */ +#define USB_OTG_DTHRCTL_TXTHRLEN_5 (0x020UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000080 */ +#define USB_OTG_DTHRCTL_TXTHRLEN_6 (0x040UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000100 */ +#define USB_OTG_DTHRCTL_TXTHRLEN_7 (0x080UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000200 */ +#define USB_OTG_DTHRCTL_TXTHRLEN_8 (0x100UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000400 */ +#define USB_OTG_DTHRCTL_RXTHREN_Pos (16U) +#define USB_OTG_DTHRCTL_RXTHREN_Msk (0x1UL << USB_OTG_DTHRCTL_RXTHREN_Pos) /*!< 0x00010000 */ +#define USB_OTG_DTHRCTL_RXTHREN USB_OTG_DTHRCTL_RXTHREN_Msk /*!< Receive threshold enable */ + +#define USB_OTG_DTHRCTL_RXTHRLEN_Pos (17U) +#define USB_OTG_DTHRCTL_RXTHRLEN_Msk (0x1FFUL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x03FE0000 */ +#define USB_OTG_DTHRCTL_RXTHRLEN USB_OTG_DTHRCTL_RXTHRLEN_Msk /*!< Receive threshold length */ +#define USB_OTG_DTHRCTL_RXTHRLEN_0 (0x001UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00020000 */ +#define USB_OTG_DTHRCTL_RXTHRLEN_1 (0x002UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00040000 */ +#define USB_OTG_DTHRCTL_RXTHRLEN_2 (0x004UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00080000 */ +#define USB_OTG_DTHRCTL_RXTHRLEN_3 (0x008UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00100000 */ +#define USB_OTG_DTHRCTL_RXTHRLEN_4 (0x010UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00200000 */ +#define USB_OTG_DTHRCTL_RXTHRLEN_5 (0x020UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00400000 */ +#define USB_OTG_DTHRCTL_RXTHRLEN_6 (0x040UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00800000 */ +#define USB_OTG_DTHRCTL_RXTHRLEN_7 (0x080UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x01000000 */ +#define USB_OTG_DTHRCTL_RXTHRLEN_8 (0x100UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x02000000 */ +#define USB_OTG_DTHRCTL_ARPEN_Pos (27U) +#define USB_OTG_DTHRCTL_ARPEN_Msk (0x1UL << USB_OTG_DTHRCTL_ARPEN_Pos) /*!< 0x08000000 */ +#define USB_OTG_DTHRCTL_ARPEN USB_OTG_DTHRCTL_ARPEN_Msk /*!< Arbiter parking enable */ + +/******************** Bit definition for USB_OTG_DIEPEMPMSK register ********************/ +#define USB_OTG_DIEPEMPMSK_INEPTXFEM_Pos (0U) +#define USB_OTG_DIEPEMPMSK_INEPTXFEM_Msk (0xFFFFUL << USB_OTG_DIEPEMPMSK_INEPTXFEM_Pos) /*!< 0x0000FFFF */ +#define USB_OTG_DIEPEMPMSK_INEPTXFEM USB_OTG_DIEPEMPMSK_INEPTXFEM_Msk /*!< IN EP Tx FIFO empty interrupt mask bits */ + +/******************** Bit definition for USB_OTG_DEACHINT register ********************/ +#define USB_OTG_DEACHINT_IEP1INT_Pos (1U) +#define USB_OTG_DEACHINT_IEP1INT_Msk (0x1UL << USB_OTG_DEACHINT_IEP1INT_Pos) /*!< 0x00000002 */ +#define USB_OTG_DEACHINT_IEP1INT USB_OTG_DEACHINT_IEP1INT_Msk /*!< IN endpoint 1interrupt bit */ +#define USB_OTG_DEACHINT_OEP1INT_Pos (17U) +#define USB_OTG_DEACHINT_OEP1INT_Msk (0x1UL << USB_OTG_DEACHINT_OEP1INT_Pos) /*!< 0x00020000 */ +#define USB_OTG_DEACHINT_OEP1INT USB_OTG_DEACHINT_OEP1INT_Msk /*!< OUT endpoint 1 interrupt bit */ + +/******************** Bit definition for USB_OTG_GCCFG register ********************/ +#define USB_OTG_GCCFG_DCDET_Pos (0U) +#define USB_OTG_GCCFG_DCDET_Msk (0x1UL << USB_OTG_GCCFG_DCDET_Pos) /*!< 0x00000001 */ +#define USB_OTG_GCCFG_DCDET USB_OTG_GCCFG_DCDET_Msk /*!< Data contact detection (DCD) status */ +#define USB_OTG_GCCFG_PDET_Pos (1U) +#define USB_OTG_GCCFG_PDET_Msk (0x1UL << USB_OTG_GCCFG_PDET_Pos) /*!< 0x00000002 */ +#define USB_OTG_GCCFG_PDET USB_OTG_GCCFG_PDET_Msk /*!< Primary detection (PD) status */ +#define USB_OTG_GCCFG_SDET_Pos (2U) +#define USB_OTG_GCCFG_SDET_Msk (0x1UL << USB_OTG_GCCFG_SDET_Pos) /*!< 0x00000004 */ +#define USB_OTG_GCCFG_SDET USB_OTG_GCCFG_SDET_Msk /*!< Secondary detection (SD) status */ +#define USB_OTG_GCCFG_PS2DET_Pos (3U) +#define USB_OTG_GCCFG_PS2DET_Msk (0x1UL << USB_OTG_GCCFG_PS2DET_Pos) /*!< 0x00000008 */ +#define USB_OTG_GCCFG_PS2DET USB_OTG_GCCFG_PS2DET_Msk /*!< DM pull-up detection status */ +#define USB_OTG_GCCFG_PWRDWN_Pos (16U) +#define USB_OTG_GCCFG_PWRDWN_Msk (0x1UL << USB_OTG_GCCFG_PWRDWN_Pos) /*!< 0x00010000 */ +#define USB_OTG_GCCFG_PWRDWN USB_OTG_GCCFG_PWRDWN_Msk /*!< Power down */ +#define USB_OTG_GCCFG_BCDEN_Pos (17U) +#define USB_OTG_GCCFG_BCDEN_Msk (0x1UL << USB_OTG_GCCFG_BCDEN_Pos) /*!< 0x00020000 */ +#define USB_OTG_GCCFG_BCDEN USB_OTG_GCCFG_BCDEN_Msk /*!< Battery charging detector (BCD) enable */ +#define USB_OTG_GCCFG_DCDEN_Pos (18U) +#define USB_OTG_GCCFG_DCDEN_Msk (0x1UL << USB_OTG_GCCFG_DCDEN_Pos) /*!< 0x00040000 */ +#define USB_OTG_GCCFG_DCDEN USB_OTG_GCCFG_DCDEN_Msk /*!< Data contact detection (DCD) mode enable*/ +#define USB_OTG_GCCFG_PDEN_Pos (19U) +#define USB_OTG_GCCFG_PDEN_Msk (0x1UL << USB_OTG_GCCFG_PDEN_Pos) /*!< 0x00080000 */ +#define USB_OTG_GCCFG_PDEN USB_OTG_GCCFG_PDEN_Msk /*!< Primary detection (PD) mode enable*/ +#define USB_OTG_GCCFG_SDEN_Pos (20U) +#define USB_OTG_GCCFG_SDEN_Msk (0x1UL << USB_OTG_GCCFG_SDEN_Pos) /*!< 0x00100000 */ +#define USB_OTG_GCCFG_SDEN USB_OTG_GCCFG_SDEN_Msk /*!< Secondary detection (SD) mode enable */ +#define USB_OTG_GCCFG_VBDEN_Pos (21U) +#define USB_OTG_GCCFG_VBDEN_Msk (0x1UL << USB_OTG_GCCFG_VBDEN_Pos) /*!< 0x00200000 */ +#define USB_OTG_GCCFG_VBDEN USB_OTG_GCCFG_VBDEN_Msk /*!< Secondary detection (SD) mode enable */ + +#define USB_OTG_GCCFG_I2CPADEN_Pos (17U) +#define USB_OTG_GCCFG_I2CPADEN_Msk (0x1UL << USB_OTG_GCCFG_I2CPADEN_Pos) /*!< 0x00020000 */ +#define USB_OTG_GCCFG_I2CPADEN USB_OTG_GCCFG_I2CPADEN_Msk /*!< Enable I2C bus connection for the external I2C PHY interface*/ +#define USB_OTG_GCCFG_VBUSASEN_Pos (18U) +#define USB_OTG_GCCFG_VBUSASEN_Msk (0x1UL << USB_OTG_GCCFG_VBUSASEN_Pos) /*!< 0x00040000 */ +#define USB_OTG_GCCFG_VBUSASEN USB_OTG_GCCFG_VBUSASEN_Msk /*!< Enable the VBUS sensing device */ +#define USB_OTG_GCCFG_VBUSBSEN_Pos (19U) +#define USB_OTG_GCCFG_VBUSBSEN_Msk (0x1UL << USB_OTG_GCCFG_VBUSBSEN_Pos) /*!< 0x00080000 */ +#define USB_OTG_GCCFG_VBUSBSEN USB_OTG_GCCFG_VBUSBSEN_Msk /*!< Enable the VBUS sensing device */ +#define USB_OTG_GCCFG_SOFOUTEN_Pos (20U) +#define USB_OTG_GCCFG_SOFOUTEN_Msk (0x1UL << USB_OTG_GCCFG_SOFOUTEN_Pos) /*!< 0x00100000 */ +#define USB_OTG_GCCFG_SOFOUTEN USB_OTG_GCCFG_SOFOUTEN_Msk /*!< SOF output enable */ +#define USB_OTG_GCCFG_NOVBUSSENS_Pos (21U) +#define USB_OTG_GCCFG_NOVBUSSENS_Msk (0x1UL << USB_OTG_GCCFG_NOVBUSSENS_Pos) /*!< 0x00200000 */ +#define USB_OTG_GCCFG_NOVBUSSENS USB_OTG_GCCFG_NOVBUSSENS_Msk /*!< VBUS sensing disable option*/ + +/******************** Bit definition forUSB_OTG_GPWRDN) register ********************/ +#define USB_OTG_GPWRDN_ADPMEN_Pos (0U) +#define USB_OTG_GPWRDN_ADPMEN_Msk (0x1UL << USB_OTG_GPWRDN_ADPMEN_Pos) /*!< 0x00000001 */ +#define USB_OTG_GPWRDN_ADPMEN USB_OTG_GPWRDN_ADPMEN_Msk /*!< ADP module enable */ +#define USB_OTG_GPWRDN_ADPIF_Pos (23U) +#define USB_OTG_GPWRDN_ADPIF_Msk (0x1UL << USB_OTG_GPWRDN_ADPIF_Pos) /*!< 0x00800000 */ +#define USB_OTG_GPWRDN_ADPIF USB_OTG_GPWRDN_ADPIF_Msk /*!< ADP Interrupt flag */ + +/******************** Bit definition forUSB_OTG_DEACHINTMSK register ********************/ +#define USB_OTG_DEACHINTMSK_IEP1INTM_Pos (1U) +#define USB_OTG_DEACHINTMSK_IEP1INTM_Msk (0x1UL << USB_OTG_DEACHINTMSK_IEP1INTM_Pos) /*!< 0x00000002 */ +#define USB_OTG_DEACHINTMSK_IEP1INTM USB_OTG_DEACHINTMSK_IEP1INTM_Msk /*!< IN Endpoint 1 interrupt mask bit */ +#define USB_OTG_DEACHINTMSK_OEP1INTM_Pos (17U) +#define USB_OTG_DEACHINTMSK_OEP1INTM_Msk (0x1UL << USB_OTG_DEACHINTMSK_OEP1INTM_Pos) /*!< 0x00020000 */ +#define USB_OTG_DEACHINTMSK_OEP1INTM USB_OTG_DEACHINTMSK_OEP1INTM_Msk /*!< OUT Endpoint 1 interrupt mask bit */ + +/******************** Bit definition for USB_OTG_CID register ********************/ +#define USB_OTG_CID_PRODUCT_ID_Pos (0U) +#define USB_OTG_CID_PRODUCT_ID_Msk (0xFFFFFFFFUL << USB_OTG_CID_PRODUCT_ID_Pos) /*!< 0xFFFFFFFF */ +#define USB_OTG_CID_PRODUCT_ID USB_OTG_CID_PRODUCT_ID_Msk /*!< Product ID field */ + +/******************** Bit definition for USB_OTG_GLPMCFG register ********************/ +#define USB_OTG_GLPMCFG_LPMEN_Pos (0U) +#define USB_OTG_GLPMCFG_LPMEN_Msk (0x1UL << USB_OTG_GLPMCFG_LPMEN_Pos) /*!< 0x00000001 */ +#define USB_OTG_GLPMCFG_LPMEN USB_OTG_GLPMCFG_LPMEN_Msk /*!< LPM support enable */ +#define USB_OTG_GLPMCFG_LPMACK_Pos (1U) +#define USB_OTG_GLPMCFG_LPMACK_Msk (0x1UL << USB_OTG_GLPMCFG_LPMACK_Pos) /*!< 0x00000002 */ +#define USB_OTG_GLPMCFG_LPMACK USB_OTG_GLPMCFG_LPMACK_Msk /*!< LPM Token acknowledge enable */ +#define USB_OTG_GLPMCFG_BESL_Pos (2U) +#define USB_OTG_GLPMCFG_BESL_Msk (0xFUL << USB_OTG_GLPMCFG_BESL_Pos) /*!< 0x0000003C */ +#define USB_OTG_GLPMCFG_BESL USB_OTG_GLPMCFG_BESL_Msk /*!< BESL value received with last ACKed LPM Token */ +#define USB_OTG_GLPMCFG_REMWAKE_Pos (6U) +#define USB_OTG_GLPMCFG_REMWAKE_Msk (0x1UL << USB_OTG_GLPMCFG_REMWAKE_Pos) /*!< 0x00000040 */ +#define USB_OTG_GLPMCFG_REMWAKE USB_OTG_GLPMCFG_REMWAKE_Msk /*!< bRemoteWake value received with last ACKed LPM Token */ +#define USB_OTG_GLPMCFG_L1SSEN_Pos (7U) +#define USB_OTG_GLPMCFG_L1SSEN_Msk (0x1UL << USB_OTG_GLPMCFG_L1SSEN_Pos) /*!< 0x00000080 */ +#define USB_OTG_GLPMCFG_L1SSEN USB_OTG_GLPMCFG_L1SSEN_Msk /*!< L1 shallow sleep enable */ +#define USB_OTG_GLPMCFG_BESLTHRS_Pos (8U) +#define USB_OTG_GLPMCFG_BESLTHRS_Msk (0xFUL << USB_OTG_GLPMCFG_BESLTHRS_Pos) /*!< 0x00000F00 */ +#define USB_OTG_GLPMCFG_BESLTHRS USB_OTG_GLPMCFG_BESLTHRS_Msk /*!< BESL threshold */ +#define USB_OTG_GLPMCFG_L1DSEN_Pos (12U) +#define USB_OTG_GLPMCFG_L1DSEN_Msk (0x1UL << USB_OTG_GLPMCFG_L1DSEN_Pos) /*!< 0x00001000 */ +#define USB_OTG_GLPMCFG_L1DSEN USB_OTG_GLPMCFG_L1DSEN_Msk /*!< L1 deep sleep enable */ +#define USB_OTG_GLPMCFG_LPMRSP_Pos (13U) +#define USB_OTG_GLPMCFG_LPMRSP_Msk (0x3UL << USB_OTG_GLPMCFG_LPMRSP_Pos) /*!< 0x00006000 */ +#define USB_OTG_GLPMCFG_LPMRSP USB_OTG_GLPMCFG_LPMRSP_Msk /*!< LPM response */ +#define USB_OTG_GLPMCFG_SLPSTS_Pos (15U) +#define USB_OTG_GLPMCFG_SLPSTS_Msk (0x1UL << USB_OTG_GLPMCFG_SLPSTS_Pos) /*!< 0x00008000 */ +#define USB_OTG_GLPMCFG_SLPSTS USB_OTG_GLPMCFG_SLPSTS_Msk /*!< Port sleep status */ +#define USB_OTG_GLPMCFG_L1RSMOK_Pos (16U) +#define USB_OTG_GLPMCFG_L1RSMOK_Msk (0x1UL << USB_OTG_GLPMCFG_L1RSMOK_Pos) /*!< 0x00010000 */ +#define USB_OTG_GLPMCFG_L1RSMOK USB_OTG_GLPMCFG_L1RSMOK_Msk /*!< Sleep State Resume OK */ +#define USB_OTG_GLPMCFG_LPMCHIDX_Pos (17U) +#define USB_OTG_GLPMCFG_LPMCHIDX_Msk (0xFUL << USB_OTG_GLPMCFG_LPMCHIDX_Pos) /*!< 0x001E0000 */ +#define USB_OTG_GLPMCFG_LPMCHIDX USB_OTG_GLPMCFG_LPMCHIDX_Msk /*!< LPM Channel Index */ +#define USB_OTG_GLPMCFG_LPMRCNT_Pos (21U) +#define USB_OTG_GLPMCFG_LPMRCNT_Msk (0x7UL << USB_OTG_GLPMCFG_LPMRCNT_Pos) /*!< 0x00E00000 */ +#define USB_OTG_GLPMCFG_LPMRCNT USB_OTG_GLPMCFG_LPMRCNT_Msk /*!< LPM retry count */ +#define USB_OTG_GLPMCFG_SNDLPM_Pos (24U) +#define USB_OTG_GLPMCFG_SNDLPM_Msk (0x1UL << USB_OTG_GLPMCFG_SNDLPM_Pos) /*!< 0x01000000 */ +#define USB_OTG_GLPMCFG_SNDLPM USB_OTG_GLPMCFG_SNDLPM_Msk /*!< Send LPM transaction */ +#define USB_OTG_GLPMCFG_LPMRCNTSTS_Pos (25U) +#define USB_OTG_GLPMCFG_LPMRCNTSTS_Msk (0x7UL << USB_OTG_GLPMCFG_LPMRCNTSTS_Pos) /*!< 0x0E000000 */ +#define USB_OTG_GLPMCFG_LPMRCNTSTS USB_OTG_GLPMCFG_LPMRCNTSTS_Msk /*!< LPM retry count status */ +#define USB_OTG_GLPMCFG_ENBESL_Pos (28U) +#define USB_OTG_GLPMCFG_ENBESL_Msk (0x1UL << USB_OTG_GLPMCFG_ENBESL_Pos) /*!< 0x10000000 */ +#define USB_OTG_GLPMCFG_ENBESL USB_OTG_GLPMCFG_ENBESL_Msk /*!< Enable best effort service latency */ + +/******************** Bit definition for USB_OTG_DIEPEACHMSK1 register ********************/ +#define USB_OTG_DIEPEACHMSK1_XFRCM_Pos (0U) +#define USB_OTG_DIEPEACHMSK1_XFRCM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_XFRCM_Pos) /*!< 0x00000001 */ +#define USB_OTG_DIEPEACHMSK1_XFRCM USB_OTG_DIEPEACHMSK1_XFRCM_Msk /*!< Transfer completed interrupt mask */ +#define USB_OTG_DIEPEACHMSK1_EPDM_Pos (1U) +#define USB_OTG_DIEPEACHMSK1_EPDM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_EPDM_Pos) /*!< 0x00000002 */ +#define USB_OTG_DIEPEACHMSK1_EPDM USB_OTG_DIEPEACHMSK1_EPDM_Msk /*!< Endpoint disabled interrupt mask */ +#define USB_OTG_DIEPEACHMSK1_TOM_Pos (3U) +#define USB_OTG_DIEPEACHMSK1_TOM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_TOM_Pos) /*!< 0x00000008 */ +#define USB_OTG_DIEPEACHMSK1_TOM USB_OTG_DIEPEACHMSK1_TOM_Msk /*!< Timeout condition mask (nonisochronous endpoints) */ +#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Pos (4U) +#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Pos) /*!< 0x00000010 */ +#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask */ +#define USB_OTG_DIEPEACHMSK1_INEPNMM_Pos (5U) +#define USB_OTG_DIEPEACHMSK1_INEPNMM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_INEPNMM_Pos) /*!< 0x00000020 */ +#define USB_OTG_DIEPEACHMSK1_INEPNMM USB_OTG_DIEPEACHMSK1_INEPNMM_Msk /*!< IN token received with EP mismatch mask */ +#define USB_OTG_DIEPEACHMSK1_INEPNEM_Pos (6U) +#define USB_OTG_DIEPEACHMSK1_INEPNEM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_INEPNEM_Pos) /*!< 0x00000040 */ +#define USB_OTG_DIEPEACHMSK1_INEPNEM USB_OTG_DIEPEACHMSK1_INEPNEM_Msk /*!< IN endpoint NAK effective mask */ +#define USB_OTG_DIEPEACHMSK1_TXFURM_Pos (8U) +#define USB_OTG_DIEPEACHMSK1_TXFURM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_TXFURM_Pos) /*!< 0x00000100 */ +#define USB_OTG_DIEPEACHMSK1_TXFURM USB_OTG_DIEPEACHMSK1_TXFURM_Msk /*!< FIFO underrun mask */ +#define USB_OTG_DIEPEACHMSK1_BIM_Pos (9U) +#define USB_OTG_DIEPEACHMSK1_BIM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_BIM_Pos) /*!< 0x00000200 */ +#define USB_OTG_DIEPEACHMSK1_BIM USB_OTG_DIEPEACHMSK1_BIM_Msk /*!< BNA interrupt mask */ +#define USB_OTG_DIEPEACHMSK1_NAKM_Pos (13U) +#define USB_OTG_DIEPEACHMSK1_NAKM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_NAKM_Pos) /*!< 0x00002000 */ +#define USB_OTG_DIEPEACHMSK1_NAKM USB_OTG_DIEPEACHMSK1_NAKM_Msk /*!< NAK interrupt mask */ + +/******************** Bit definition for USB_OTG_HPRT register ********************/ +#define USB_OTG_HPRT_PCSTS_Pos (0U) +#define USB_OTG_HPRT_PCSTS_Msk (0x1UL << USB_OTG_HPRT_PCSTS_Pos) /*!< 0x00000001 */ +#define USB_OTG_HPRT_PCSTS USB_OTG_HPRT_PCSTS_Msk /*!< Port connect status */ +#define USB_OTG_HPRT_PCDET_Pos (1U) +#define USB_OTG_HPRT_PCDET_Msk (0x1UL << USB_OTG_HPRT_PCDET_Pos) /*!< 0x00000002 */ +#define USB_OTG_HPRT_PCDET USB_OTG_HPRT_PCDET_Msk /*!< Port connect detected */ +#define USB_OTG_HPRT_PENA_Pos (2U) +#define USB_OTG_HPRT_PENA_Msk (0x1UL << USB_OTG_HPRT_PENA_Pos) /*!< 0x00000004 */ +#define USB_OTG_HPRT_PENA USB_OTG_HPRT_PENA_Msk /*!< Port enable */ +#define USB_OTG_HPRT_PENCHNG_Pos (3U) +#define USB_OTG_HPRT_PENCHNG_Msk (0x1UL << USB_OTG_HPRT_PENCHNG_Pos) /*!< 0x00000008 */ +#define USB_OTG_HPRT_PENCHNG USB_OTG_HPRT_PENCHNG_Msk /*!< Port enable/disable change */ +#define USB_OTG_HPRT_POCA_Pos (4U) +#define USB_OTG_HPRT_POCA_Msk (0x1UL << USB_OTG_HPRT_POCA_Pos) /*!< 0x00000010 */ +#define USB_OTG_HPRT_POCA USB_OTG_HPRT_POCA_Msk /*!< Port overcurrent active */ +#define USB_OTG_HPRT_POCCHNG_Pos (5U) +#define USB_OTG_HPRT_POCCHNG_Msk (0x1UL << USB_OTG_HPRT_POCCHNG_Pos) /*!< 0x00000020 */ +#define USB_OTG_HPRT_POCCHNG USB_OTG_HPRT_POCCHNG_Msk /*!< Port overcurrent change */ +#define USB_OTG_HPRT_PRES_Pos (6U) +#define USB_OTG_HPRT_PRES_Msk (0x1UL << USB_OTG_HPRT_PRES_Pos) /*!< 0x00000040 */ +#define USB_OTG_HPRT_PRES USB_OTG_HPRT_PRES_Msk /*!< Port resume */ +#define USB_OTG_HPRT_PSUSP_Pos (7U) +#define USB_OTG_HPRT_PSUSP_Msk (0x1UL << USB_OTG_HPRT_PSUSP_Pos) /*!< 0x00000080 */ +#define USB_OTG_HPRT_PSUSP USB_OTG_HPRT_PSUSP_Msk /*!< Port suspend */ +#define USB_OTG_HPRT_PRST_Pos (8U) +#define USB_OTG_HPRT_PRST_Msk (0x1UL << USB_OTG_HPRT_PRST_Pos) /*!< 0x00000100 */ +#define USB_OTG_HPRT_PRST USB_OTG_HPRT_PRST_Msk /*!< Port reset */ + +#define USB_OTG_HPRT_PLSTS_Pos (10U) +#define USB_OTG_HPRT_PLSTS_Msk (0x3UL << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000C00 */ +#define USB_OTG_HPRT_PLSTS USB_OTG_HPRT_PLSTS_Msk /*!< Port line status */ +#define USB_OTG_HPRT_PLSTS_0 (0x1UL << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000400 */ +#define USB_OTG_HPRT_PLSTS_1 (0x2UL << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000800 */ +#define USB_OTG_HPRT_PPWR_Pos (12U) +#define USB_OTG_HPRT_PPWR_Msk (0x1UL << USB_OTG_HPRT_PPWR_Pos) /*!< 0x00001000 */ +#define USB_OTG_HPRT_PPWR USB_OTG_HPRT_PPWR_Msk /*!< Port power */ + +#define USB_OTG_HPRT_PTCTL_Pos (13U) +#define USB_OTG_HPRT_PTCTL_Msk (0xFUL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x0001E000 */ +#define USB_OTG_HPRT_PTCTL USB_OTG_HPRT_PTCTL_Msk /*!< Port test control */ +#define USB_OTG_HPRT_PTCTL_0 (0x1UL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00002000 */ +#define USB_OTG_HPRT_PTCTL_1 (0x2UL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00004000 */ +#define USB_OTG_HPRT_PTCTL_2 (0x4UL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00008000 */ +#define USB_OTG_HPRT_PTCTL_3 (0x8UL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00010000 */ + +#define USB_OTG_HPRT_PSPD_Pos (17U) +#define USB_OTG_HPRT_PSPD_Msk (0x3UL << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00060000 */ +#define USB_OTG_HPRT_PSPD USB_OTG_HPRT_PSPD_Msk /*!< Port speed */ +#define USB_OTG_HPRT_PSPD_0 (0x1UL << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00020000 */ +#define USB_OTG_HPRT_PSPD_1 (0x2UL << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00040000 */ + +/******************** Bit definition for USB_OTG_DOEPEACHMSK1 register ********************/ +#define USB_OTG_DOEPEACHMSK1_XFRCM_Pos (0U) +#define USB_OTG_DOEPEACHMSK1_XFRCM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_XFRCM_Pos) /*!< 0x00000001 */ +#define USB_OTG_DOEPEACHMSK1_XFRCM USB_OTG_DOEPEACHMSK1_XFRCM_Msk /*!< Transfer completed interrupt mask */ +#define USB_OTG_DOEPEACHMSK1_EPDM_Pos (1U) +#define USB_OTG_DOEPEACHMSK1_EPDM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_EPDM_Pos) /*!< 0x00000002 */ +#define USB_OTG_DOEPEACHMSK1_EPDM USB_OTG_DOEPEACHMSK1_EPDM_Msk /*!< Endpoint disabled interrupt mask */ +#define USB_OTG_DOEPEACHMSK1_TOM_Pos (3U) +#define USB_OTG_DOEPEACHMSK1_TOM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_TOM_Pos) /*!< 0x00000008 */ +#define USB_OTG_DOEPEACHMSK1_TOM USB_OTG_DOEPEACHMSK1_TOM_Msk /*!< Timeout condition mask */ +#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Pos (4U) +#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Pos) /*!< 0x00000010 */ +#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask */ +#define USB_OTG_DOEPEACHMSK1_INEPNMM_Pos (5U) +#define USB_OTG_DOEPEACHMSK1_INEPNMM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_INEPNMM_Pos) /*!< 0x00000020 */ +#define USB_OTG_DOEPEACHMSK1_INEPNMM USB_OTG_DOEPEACHMSK1_INEPNMM_Msk /*!< IN token received with EP mismatch mask */ +#define USB_OTG_DOEPEACHMSK1_INEPNEM_Pos (6U) +#define USB_OTG_DOEPEACHMSK1_INEPNEM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_INEPNEM_Pos) /*!< 0x00000040 */ +#define USB_OTG_DOEPEACHMSK1_INEPNEM USB_OTG_DOEPEACHMSK1_INEPNEM_Msk /*!< IN endpoint NAK effective mask */ +#define USB_OTG_DOEPEACHMSK1_TXFURM_Pos (8U) +#define USB_OTG_DOEPEACHMSK1_TXFURM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_TXFURM_Pos) /*!< 0x00000100 */ +#define USB_OTG_DOEPEACHMSK1_TXFURM USB_OTG_DOEPEACHMSK1_TXFURM_Msk /*!< OUT packet error mask */ +#define USB_OTG_DOEPEACHMSK1_BIM_Pos (9U) +#define USB_OTG_DOEPEACHMSK1_BIM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_BIM_Pos) /*!< 0x00000200 */ +#define USB_OTG_DOEPEACHMSK1_BIM USB_OTG_DOEPEACHMSK1_BIM_Msk /*!< BNA interrupt mask */ +#define USB_OTG_DOEPEACHMSK1_BERRM_Pos (12U) +#define USB_OTG_DOEPEACHMSK1_BERRM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_BERRM_Pos) /*!< 0x00001000 */ +#define USB_OTG_DOEPEACHMSK1_BERRM USB_OTG_DOEPEACHMSK1_BERRM_Msk /*!< Bubble error interrupt mask */ +#define USB_OTG_DOEPEACHMSK1_NAKM_Pos (13U) +#define USB_OTG_DOEPEACHMSK1_NAKM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_NAKM_Pos) /*!< 0x00002000 */ +#define USB_OTG_DOEPEACHMSK1_NAKM USB_OTG_DOEPEACHMSK1_NAKM_Msk /*!< NAK interrupt mask */ +#define USB_OTG_DOEPEACHMSK1_NYETM_Pos (14U) +#define USB_OTG_DOEPEACHMSK1_NYETM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_NYETM_Pos) /*!< 0x00004000 */ +#define USB_OTG_DOEPEACHMSK1_NYETM USB_OTG_DOEPEACHMSK1_NYETM_Msk /*!< NYET interrupt mask */ + +/******************** Bit definition for USB_OTG_HPTXFSIZ register ********************/ +#define USB_OTG_HPTXFSIZ_PTXSA_Pos (0U) +#define USB_OTG_HPTXFSIZ_PTXSA_Msk (0xFFFFUL << USB_OTG_HPTXFSIZ_PTXSA_Pos) /*!< 0x0000FFFF */ +#define USB_OTG_HPTXFSIZ_PTXSA USB_OTG_HPTXFSIZ_PTXSA_Msk /*!< Host periodic TxFIFO start address */ +#define USB_OTG_HPTXFSIZ_PTXFD_Pos (16U) +#define USB_OTG_HPTXFSIZ_PTXFD_Msk (0xFFFFUL << USB_OTG_HPTXFSIZ_PTXFD_Pos) /*!< 0xFFFF0000 */ +#define USB_OTG_HPTXFSIZ_PTXFD USB_OTG_HPTXFSIZ_PTXFD_Msk /*!< Host periodic TxFIFO depth */ + +/******************** Bit definition for USB_OTG_DIEPCTL register ********************/ +#define USB_OTG_DIEPCTL_MPSIZ_Pos (0U) +#define USB_OTG_DIEPCTL_MPSIZ_Msk (0x7FFUL << USB_OTG_DIEPCTL_MPSIZ_Pos) /*!< 0x000007FF */ +#define USB_OTG_DIEPCTL_MPSIZ USB_OTG_DIEPCTL_MPSIZ_Msk /*!< Maximum packet size */ +#define USB_OTG_DIEPCTL_USBAEP_Pos (15U) +#define USB_OTG_DIEPCTL_USBAEP_Msk (0x1UL << USB_OTG_DIEPCTL_USBAEP_Pos) /*!< 0x00008000 */ +#define USB_OTG_DIEPCTL_USBAEP USB_OTG_DIEPCTL_USBAEP_Msk /*!< USB active endpoint */ +#define USB_OTG_DIEPCTL_EONUM_DPID_Pos (16U) +#define USB_OTG_DIEPCTL_EONUM_DPID_Msk (0x1UL << USB_OTG_DIEPCTL_EONUM_DPID_Pos) /*!< 0x00010000 */ +#define USB_OTG_DIEPCTL_EONUM_DPID USB_OTG_DIEPCTL_EONUM_DPID_Msk /*!< Even/odd frame */ +#define USB_OTG_DIEPCTL_NAKSTS_Pos (17U) +#define USB_OTG_DIEPCTL_NAKSTS_Msk (0x1UL << USB_OTG_DIEPCTL_NAKSTS_Pos) /*!< 0x00020000 */ +#define USB_OTG_DIEPCTL_NAKSTS USB_OTG_DIEPCTL_NAKSTS_Msk /*!< NAK status */ + +#define USB_OTG_DIEPCTL_EPTYP_Pos (18U) +#define USB_OTG_DIEPCTL_EPTYP_Msk (0x3UL << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x000C0000 */ +#define USB_OTG_DIEPCTL_EPTYP USB_OTG_DIEPCTL_EPTYP_Msk /*!< Endpoint type */ +#define USB_OTG_DIEPCTL_EPTYP_0 (0x1UL << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x00040000 */ +#define USB_OTG_DIEPCTL_EPTYP_1 (0x2UL << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x00080000 */ +#define USB_OTG_DIEPCTL_STALL_Pos (21U) +#define USB_OTG_DIEPCTL_STALL_Msk (0x1UL << USB_OTG_DIEPCTL_STALL_Pos) /*!< 0x00200000 */ +#define USB_OTG_DIEPCTL_STALL USB_OTG_DIEPCTL_STALL_Msk /*!< STALL handshake */ + +#define USB_OTG_DIEPCTL_TXFNUM_Pos (22U) +#define USB_OTG_DIEPCTL_TXFNUM_Msk (0xFUL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x03C00000 */ +#define USB_OTG_DIEPCTL_TXFNUM USB_OTG_DIEPCTL_TXFNUM_Msk /*!< TxFIFO number */ +#define USB_OTG_DIEPCTL_TXFNUM_0 (0x1UL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x00400000 */ +#define USB_OTG_DIEPCTL_TXFNUM_1 (0x2UL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x00800000 */ +#define USB_OTG_DIEPCTL_TXFNUM_2 (0x4UL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x01000000 */ +#define USB_OTG_DIEPCTL_TXFNUM_3 (0x8UL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x02000000 */ +#define USB_OTG_DIEPCTL_CNAK_Pos (26U) +#define USB_OTG_DIEPCTL_CNAK_Msk (0x1UL << USB_OTG_DIEPCTL_CNAK_Pos) /*!< 0x04000000 */ +#define USB_OTG_DIEPCTL_CNAK USB_OTG_DIEPCTL_CNAK_Msk /*!< Clear NAK */ +#define USB_OTG_DIEPCTL_SNAK_Pos (27U) +#define USB_OTG_DIEPCTL_SNAK_Msk (0x1UL << USB_OTG_DIEPCTL_SNAK_Pos) /*!< 0x08000000 */ +#define USB_OTG_DIEPCTL_SNAK USB_OTG_DIEPCTL_SNAK_Msk /*!< Set NAK */ +#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos (28U) +#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk (0x1UL << USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos) /*!< 0x10000000 */ +#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID */ +#define USB_OTG_DIEPCTL_SODDFRM_Pos (29U) +#define USB_OTG_DIEPCTL_SODDFRM_Msk (0x1UL << USB_OTG_DIEPCTL_SODDFRM_Pos) /*!< 0x20000000 */ +#define USB_OTG_DIEPCTL_SODDFRM USB_OTG_DIEPCTL_SODDFRM_Msk /*!< Set odd frame */ +#define USB_OTG_DIEPCTL_EPDIS_Pos (30U) +#define USB_OTG_DIEPCTL_EPDIS_Msk (0x1UL << USB_OTG_DIEPCTL_EPDIS_Pos) /*!< 0x40000000 */ +#define USB_OTG_DIEPCTL_EPDIS USB_OTG_DIEPCTL_EPDIS_Msk /*!< Endpoint disable */ +#define USB_OTG_DIEPCTL_EPENA_Pos (31U) +#define USB_OTG_DIEPCTL_EPENA_Msk (0x1UL << USB_OTG_DIEPCTL_EPENA_Pos) /*!< 0x80000000 */ +#define USB_OTG_DIEPCTL_EPENA USB_OTG_DIEPCTL_EPENA_Msk /*!< Endpoint enable */ + +/******************** Bit definition for USB_OTG_HCCHAR register ********************/ +#define USB_OTG_HCCHAR_MPSIZ_Pos (0U) +#define USB_OTG_HCCHAR_MPSIZ_Msk (0x7FFUL << USB_OTG_HCCHAR_MPSIZ_Pos) /*!< 0x000007FF */ +#define USB_OTG_HCCHAR_MPSIZ USB_OTG_HCCHAR_MPSIZ_Msk /*!< Maximum packet size */ + +#define USB_OTG_HCCHAR_EPNUM_Pos (11U) +#define USB_OTG_HCCHAR_EPNUM_Msk (0xFUL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00007800 */ +#define USB_OTG_HCCHAR_EPNUM USB_OTG_HCCHAR_EPNUM_Msk /*!< Endpoint number */ +#define USB_OTG_HCCHAR_EPNUM_0 (0x1UL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00000800 */ +#define USB_OTG_HCCHAR_EPNUM_1 (0x2UL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00001000 */ +#define USB_OTG_HCCHAR_EPNUM_2 (0x4UL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00002000 */ +#define USB_OTG_HCCHAR_EPNUM_3 (0x8UL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00004000 */ +#define USB_OTG_HCCHAR_EPDIR_Pos (15U) +#define USB_OTG_HCCHAR_EPDIR_Msk (0x1UL << USB_OTG_HCCHAR_EPDIR_Pos) /*!< 0x00008000 */ +#define USB_OTG_HCCHAR_EPDIR USB_OTG_HCCHAR_EPDIR_Msk /*!< Endpoint direction */ +#define USB_OTG_HCCHAR_LSDEV_Pos (17U) +#define USB_OTG_HCCHAR_LSDEV_Msk (0x1UL << USB_OTG_HCCHAR_LSDEV_Pos) /*!< 0x00020000 */ +#define USB_OTG_HCCHAR_LSDEV USB_OTG_HCCHAR_LSDEV_Msk /*!< Low-speed device */ + +#define USB_OTG_HCCHAR_EPTYP_Pos (18U) +#define USB_OTG_HCCHAR_EPTYP_Msk (0x3UL << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x000C0000 */ +#define USB_OTG_HCCHAR_EPTYP USB_OTG_HCCHAR_EPTYP_Msk /*!< Endpoint type */ +#define USB_OTG_HCCHAR_EPTYP_0 (0x1UL << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x00040000 */ +#define USB_OTG_HCCHAR_EPTYP_1 (0x2UL << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x00080000 */ + +#define USB_OTG_HCCHAR_MC_Pos (20U) +#define USB_OTG_HCCHAR_MC_Msk (0x3UL << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00300000 */ +#define USB_OTG_HCCHAR_MC USB_OTG_HCCHAR_MC_Msk /*!< Multi Count (MC) / Error Count (EC) */ +#define USB_OTG_HCCHAR_MC_0 (0x1UL << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00100000 */ +#define USB_OTG_HCCHAR_MC_1 (0x2UL << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00200000 */ + +#define USB_OTG_HCCHAR_DAD_Pos (22U) +#define USB_OTG_HCCHAR_DAD_Msk (0x7FUL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x1FC00000 */ +#define USB_OTG_HCCHAR_DAD USB_OTG_HCCHAR_DAD_Msk /*!< Device address */ +#define USB_OTG_HCCHAR_DAD_0 (0x01UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x00400000 */ +#define USB_OTG_HCCHAR_DAD_1 (0x02UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x00800000 */ +#define USB_OTG_HCCHAR_DAD_2 (0x04UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x01000000 */ +#define USB_OTG_HCCHAR_DAD_3 (0x08UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x02000000 */ +#define USB_OTG_HCCHAR_DAD_4 (0x10UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x04000000 */ +#define USB_OTG_HCCHAR_DAD_5 (0x20UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x08000000 */ +#define USB_OTG_HCCHAR_DAD_6 (0x40UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x10000000 */ +#define USB_OTG_HCCHAR_ODDFRM_Pos (29U) +#define USB_OTG_HCCHAR_ODDFRM_Msk (0x1UL << USB_OTG_HCCHAR_ODDFRM_Pos) /*!< 0x20000000 */ +#define USB_OTG_HCCHAR_ODDFRM USB_OTG_HCCHAR_ODDFRM_Msk /*!< Odd frame */ +#define USB_OTG_HCCHAR_CHDIS_Pos (30U) +#define USB_OTG_HCCHAR_CHDIS_Msk (0x1UL << USB_OTG_HCCHAR_CHDIS_Pos) /*!< 0x40000000 */ +#define USB_OTG_HCCHAR_CHDIS USB_OTG_HCCHAR_CHDIS_Msk /*!< Channel disable */ +#define USB_OTG_HCCHAR_CHENA_Pos (31U) +#define USB_OTG_HCCHAR_CHENA_Msk (0x1UL << USB_OTG_HCCHAR_CHENA_Pos) /*!< 0x80000000 */ +#define USB_OTG_HCCHAR_CHENA USB_OTG_HCCHAR_CHENA_Msk /*!< Channel enable */ + +/******************** Bit definition for USB_OTG_HCSPLT register ********************/ + +#define USB_OTG_HCSPLT_PRTADDR_Pos (0U) +#define USB_OTG_HCSPLT_PRTADDR_Msk (0x7FUL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x0000007F */ +#define USB_OTG_HCSPLT_PRTADDR USB_OTG_HCSPLT_PRTADDR_Msk /*!< Port address */ +#define USB_OTG_HCSPLT_PRTADDR_0 (0x01UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000001 */ +#define USB_OTG_HCSPLT_PRTADDR_1 (0x02UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000002 */ +#define USB_OTG_HCSPLT_PRTADDR_2 (0x04UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000004 */ +#define USB_OTG_HCSPLT_PRTADDR_3 (0x08UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000008 */ +#define USB_OTG_HCSPLT_PRTADDR_4 (0x10UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000010 */ +#define USB_OTG_HCSPLT_PRTADDR_5 (0x20UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000020 */ +#define USB_OTG_HCSPLT_PRTADDR_6 (0x40UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000040 */ + +#define USB_OTG_HCSPLT_HUBADDR_Pos (7U) +#define USB_OTG_HCSPLT_HUBADDR_Msk (0x7FUL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00003F80 */ +#define USB_OTG_HCSPLT_HUBADDR USB_OTG_HCSPLT_HUBADDR_Msk /*!< Hub address */ +#define USB_OTG_HCSPLT_HUBADDR_0 (0x01UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000080 */ +#define USB_OTG_HCSPLT_HUBADDR_1 (0x02UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000100 */ +#define USB_OTG_HCSPLT_HUBADDR_2 (0x04UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000200 */ +#define USB_OTG_HCSPLT_HUBADDR_3 (0x08UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000400 */ +#define USB_OTG_HCSPLT_HUBADDR_4 (0x10UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000800 */ +#define USB_OTG_HCSPLT_HUBADDR_5 (0x20UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00001000 */ +#define USB_OTG_HCSPLT_HUBADDR_6 (0x40UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00002000 */ + +#define USB_OTG_HCSPLT_XACTPOS_Pos (14U) +#define USB_OTG_HCSPLT_XACTPOS_Msk (0x3UL << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x0000C000 */ +#define USB_OTG_HCSPLT_XACTPOS USB_OTG_HCSPLT_XACTPOS_Msk /*!< XACTPOS */ +#define USB_OTG_HCSPLT_XACTPOS_0 (0x1UL << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x00004000 */ +#define USB_OTG_HCSPLT_XACTPOS_1 (0x2UL << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x00008000 */ +#define USB_OTG_HCSPLT_COMPLSPLT_Pos (16U) +#define USB_OTG_HCSPLT_COMPLSPLT_Msk (0x1UL << USB_OTG_HCSPLT_COMPLSPLT_Pos) /*!< 0x00010000 */ +#define USB_OTG_HCSPLT_COMPLSPLT USB_OTG_HCSPLT_COMPLSPLT_Msk /*!< Do complete split */ +#define USB_OTG_HCSPLT_SPLITEN_Pos (31U) +#define USB_OTG_HCSPLT_SPLITEN_Msk (0x1UL << USB_OTG_HCSPLT_SPLITEN_Pos) /*!< 0x80000000 */ +#define USB_OTG_HCSPLT_SPLITEN USB_OTG_HCSPLT_SPLITEN_Msk /*!< Split enable */ + +/******************** Bit definition for USB_OTG_HCINT register ********************/ +#define USB_OTG_HCINT_XFRC_Pos (0U) +#define USB_OTG_HCINT_XFRC_Msk (0x1UL << USB_OTG_HCINT_XFRC_Pos) /*!< 0x00000001 */ +#define USB_OTG_HCINT_XFRC USB_OTG_HCINT_XFRC_Msk /*!< Transfer completed */ +#define USB_OTG_HCINT_CHH_Pos (1U) +#define USB_OTG_HCINT_CHH_Msk (0x1UL << USB_OTG_HCINT_CHH_Pos) /*!< 0x00000002 */ +#define USB_OTG_HCINT_CHH USB_OTG_HCINT_CHH_Msk /*!< Channel halted */ +#define USB_OTG_HCINT_AHBERR_Pos (2U) +#define USB_OTG_HCINT_AHBERR_Msk (0x1UL << USB_OTG_HCINT_AHBERR_Pos) /*!< 0x00000004 */ +#define USB_OTG_HCINT_AHBERR USB_OTG_HCINT_AHBERR_Msk /*!< AHB error */ +#define USB_OTG_HCINT_STALL_Pos (3U) +#define USB_OTG_HCINT_STALL_Msk (0x1UL << USB_OTG_HCINT_STALL_Pos) /*!< 0x00000008 */ +#define USB_OTG_HCINT_STALL USB_OTG_HCINT_STALL_Msk /*!< STALL response received interrupt */ +#define USB_OTG_HCINT_NAK_Pos (4U) +#define USB_OTG_HCINT_NAK_Msk (0x1UL << USB_OTG_HCINT_NAK_Pos) /*!< 0x00000010 */ +#define USB_OTG_HCINT_NAK USB_OTG_HCINT_NAK_Msk /*!< NAK response received interrupt */ +#define USB_OTG_HCINT_ACK_Pos (5U) +#define USB_OTG_HCINT_ACK_Msk (0x1UL << USB_OTG_HCINT_ACK_Pos) /*!< 0x00000020 */ +#define USB_OTG_HCINT_ACK USB_OTG_HCINT_ACK_Msk /*!< ACK response received/transmitted interrupt */ +#define USB_OTG_HCINT_NYET_Pos (6U) +#define USB_OTG_HCINT_NYET_Msk (0x1UL << USB_OTG_HCINT_NYET_Pos) /*!< 0x00000040 */ +#define USB_OTG_HCINT_NYET USB_OTG_HCINT_NYET_Msk /*!< Response received interrupt */ +#define USB_OTG_HCINT_TXERR_Pos (7U) +#define USB_OTG_HCINT_TXERR_Msk (0x1UL << USB_OTG_HCINT_TXERR_Pos) /*!< 0x00000080 */ +#define USB_OTG_HCINT_TXERR USB_OTG_HCINT_TXERR_Msk /*!< Transaction error */ +#define USB_OTG_HCINT_BBERR_Pos (8U) +#define USB_OTG_HCINT_BBERR_Msk (0x1UL << USB_OTG_HCINT_BBERR_Pos) /*!< 0x00000100 */ +#define USB_OTG_HCINT_BBERR USB_OTG_HCINT_BBERR_Msk /*!< Babble error */ +#define USB_OTG_HCINT_FRMOR_Pos (9U) +#define USB_OTG_HCINT_FRMOR_Msk (0x1UL << USB_OTG_HCINT_FRMOR_Pos) /*!< 0x00000200 */ +#define USB_OTG_HCINT_FRMOR USB_OTG_HCINT_FRMOR_Msk /*!< Frame overrun */ +#define USB_OTG_HCINT_DTERR_Pos (10U) +#define USB_OTG_HCINT_DTERR_Msk (0x1UL << USB_OTG_HCINT_DTERR_Pos) /*!< 0x00000400 */ +#define USB_OTG_HCINT_DTERR USB_OTG_HCINT_DTERR_Msk /*!< Data toggle error */ + +/******************** Bit definition for USB_OTG_DIEPINT register ********************/ +#define USB_OTG_DIEPINT_XFRC_Pos (0U) +#define USB_OTG_DIEPINT_XFRC_Msk (0x1UL << USB_OTG_DIEPINT_XFRC_Pos) /*!< 0x00000001 */ +#define USB_OTG_DIEPINT_XFRC USB_OTG_DIEPINT_XFRC_Msk /*!< Transfer completed interrupt */ +#define USB_OTG_DIEPINT_EPDISD_Pos (1U) +#define USB_OTG_DIEPINT_EPDISD_Msk (0x1UL << USB_OTG_DIEPINT_EPDISD_Pos) /*!< 0x00000002 */ +#define USB_OTG_DIEPINT_EPDISD USB_OTG_DIEPINT_EPDISD_Msk /*!< Endpoint disabled interrupt */ +#define USB_OTG_DIEPINT_AHBERR_Pos (2U) +#define USB_OTG_DIEPINT_AHBERR_Msk (0x1UL << USB_OTG_DIEPINT_AHBERR_Pos) /*!< 0x00000004 */ +#define USB_OTG_DIEPINT_AHBERR USB_OTG_DIEPINT_AHBERR_Msk /*!< AHB Error (AHBErr) during an IN transaction */ +#define USB_OTG_DIEPINT_TOC_Pos (3U) +#define USB_OTG_DIEPINT_TOC_Msk (0x1UL << USB_OTG_DIEPINT_TOC_Pos) /*!< 0x00000008 */ +#define USB_OTG_DIEPINT_TOC USB_OTG_DIEPINT_TOC_Msk /*!< Timeout condition */ +#define USB_OTG_DIEPINT_ITTXFE_Pos (4U) +#define USB_OTG_DIEPINT_ITTXFE_Msk (0x1UL << USB_OTG_DIEPINT_ITTXFE_Pos) /*!< 0x00000010 */ +#define USB_OTG_DIEPINT_ITTXFE USB_OTG_DIEPINT_ITTXFE_Msk /*!< IN token received when TxFIFO is empty */ +#define USB_OTG_DIEPINT_INEPNM_Pos (5U) +#define USB_OTG_DIEPINT_INEPNM_Msk (0x1UL << USB_OTG_DIEPINT_INEPNM_Pos) /*!< 0x00000004 */ +#define USB_OTG_DIEPINT_INEPNM USB_OTG_DIEPINT_INEPNM_Msk /*!< IN token received with EP mismatch */ +#define USB_OTG_DIEPINT_INEPNE_Pos (6U) +#define USB_OTG_DIEPINT_INEPNE_Msk (0x1UL << USB_OTG_DIEPINT_INEPNE_Pos) /*!< 0x00000040 */ +#define USB_OTG_DIEPINT_INEPNE USB_OTG_DIEPINT_INEPNE_Msk /*!< IN endpoint NAK effective */ +#define USB_OTG_DIEPINT_TXFE_Pos (7U) +#define USB_OTG_DIEPINT_TXFE_Msk (0x1UL << USB_OTG_DIEPINT_TXFE_Pos) /*!< 0x00000080 */ +#define USB_OTG_DIEPINT_TXFE USB_OTG_DIEPINT_TXFE_Msk /*!< Transmit FIFO empty */ +#define USB_OTG_DIEPINT_TXFIFOUDRN_Pos (8U) +#define USB_OTG_DIEPINT_TXFIFOUDRN_Msk (0x1UL << USB_OTG_DIEPINT_TXFIFOUDRN_Pos) /*!< 0x00000100 */ +#define USB_OTG_DIEPINT_TXFIFOUDRN USB_OTG_DIEPINT_TXFIFOUDRN_Msk /*!< Transmit Fifo Underrun */ +#define USB_OTG_DIEPINT_BNA_Pos (9U) +#define USB_OTG_DIEPINT_BNA_Msk (0x1UL << USB_OTG_DIEPINT_BNA_Pos) /*!< 0x00000200 */ +#define USB_OTG_DIEPINT_BNA USB_OTG_DIEPINT_BNA_Msk /*!< Buffer not available interrupt */ +#define USB_OTG_DIEPINT_PKTDRPSTS_Pos (11U) +#define USB_OTG_DIEPINT_PKTDRPSTS_Msk (0x1UL << USB_OTG_DIEPINT_PKTDRPSTS_Pos) /*!< 0x00000800 */ +#define USB_OTG_DIEPINT_PKTDRPSTS USB_OTG_DIEPINT_PKTDRPSTS_Msk /*!< Packet dropped status */ +#define USB_OTG_DIEPINT_BERR_Pos (12U) +#define USB_OTG_DIEPINT_BERR_Msk (0x1UL << USB_OTG_DIEPINT_BERR_Pos) /*!< 0x00001000 */ +#define USB_OTG_DIEPINT_BERR USB_OTG_DIEPINT_BERR_Msk /*!< Babble error interrupt */ +#define USB_OTG_DIEPINT_NAK_Pos (13U) +#define USB_OTG_DIEPINT_NAK_Msk (0x1UL << USB_OTG_DIEPINT_NAK_Pos) /*!< 0x00002000 */ +#define USB_OTG_DIEPINT_NAK USB_OTG_DIEPINT_NAK_Msk /*!< NAK interrupt */ + +/******************** Bit definition forUSB_OTG_HCINTMSK register ********************/ +#define USB_OTG_HCINTMSK_XFRCM_Pos (0U) +#define USB_OTG_HCINTMSK_XFRCM_Msk (0x1UL << USB_OTG_HCINTMSK_XFRCM_Pos) /*!< 0x00000001 */ +#define USB_OTG_HCINTMSK_XFRCM USB_OTG_HCINTMSK_XFRCM_Msk /*!< Transfer completed mask */ +#define USB_OTG_HCINTMSK_CHHM_Pos (1U) +#define USB_OTG_HCINTMSK_CHHM_Msk (0x1UL << USB_OTG_HCINTMSK_CHHM_Pos) /*!< 0x00000002 */ +#define USB_OTG_HCINTMSK_CHHM USB_OTG_HCINTMSK_CHHM_Msk /*!< Channel halted mask */ +#define USB_OTG_HCINTMSK_AHBERR_Pos (2U) +#define USB_OTG_HCINTMSK_AHBERR_Msk (0x1UL << USB_OTG_HCINTMSK_AHBERR_Pos) /*!< 0x00000004 */ +#define USB_OTG_HCINTMSK_AHBERR USB_OTG_HCINTMSK_AHBERR_Msk /*!< AHB error */ +#define USB_OTG_HCINTMSK_STALLM_Pos (3U) +#define USB_OTG_HCINTMSK_STALLM_Msk (0x1UL << USB_OTG_HCINTMSK_STALLM_Pos) /*!< 0x00000008 */ +#define USB_OTG_HCINTMSK_STALLM USB_OTG_HCINTMSK_STALLM_Msk /*!< STALL response received interrupt mask */ +#define USB_OTG_HCINTMSK_NAKM_Pos (4U) +#define USB_OTG_HCINTMSK_NAKM_Msk (0x1UL << USB_OTG_HCINTMSK_NAKM_Pos) /*!< 0x00000010 */ +#define USB_OTG_HCINTMSK_NAKM USB_OTG_HCINTMSK_NAKM_Msk /*!< NAK response received interrupt mask */ +#define USB_OTG_HCINTMSK_ACKM_Pos (5U) +#define USB_OTG_HCINTMSK_ACKM_Msk (0x1UL << USB_OTG_HCINTMSK_ACKM_Pos) /*!< 0x00000020 */ +#define USB_OTG_HCINTMSK_ACKM USB_OTG_HCINTMSK_ACKM_Msk /*!< ACK response received/transmitted interrupt mask */ +#define USB_OTG_HCINTMSK_NYET_Pos (6U) +#define USB_OTG_HCINTMSK_NYET_Msk (0x1UL << USB_OTG_HCINTMSK_NYET_Pos) /*!< 0x00000040 */ +#define USB_OTG_HCINTMSK_NYET USB_OTG_HCINTMSK_NYET_Msk /*!< response received interrupt mask */ +#define USB_OTG_HCINTMSK_TXERRM_Pos (7U) +#define USB_OTG_HCINTMSK_TXERRM_Msk (0x1UL << USB_OTG_HCINTMSK_TXERRM_Pos) /*!< 0x00000080 */ +#define USB_OTG_HCINTMSK_TXERRM USB_OTG_HCINTMSK_TXERRM_Msk /*!< Transaction error mask */ +#define USB_OTG_HCINTMSK_BBERRM_Pos (8U) +#define USB_OTG_HCINTMSK_BBERRM_Msk (0x1UL << USB_OTG_HCINTMSK_BBERRM_Pos) /*!< 0x00000100 */ +#define USB_OTG_HCINTMSK_BBERRM USB_OTG_HCINTMSK_BBERRM_Msk /*!< Babble error mask */ +#define USB_OTG_HCINTMSK_FRMORM_Pos (9U) +#define USB_OTG_HCINTMSK_FRMORM_Msk (0x1UL << USB_OTG_HCINTMSK_FRMORM_Pos) /*!< 0x00000200 */ +#define USB_OTG_HCINTMSK_FRMORM USB_OTG_HCINTMSK_FRMORM_Msk /*!< Frame overrun mask */ +#define USB_OTG_HCINTMSK_DTERRM_Pos (10U) +#define USB_OTG_HCINTMSK_DTERRM_Msk (0x1UL << USB_OTG_HCINTMSK_DTERRM_Pos) /*!< 0x00000400 */ +#define USB_OTG_HCINTMSK_DTERRM USB_OTG_HCINTMSK_DTERRM_Msk /*!< Data toggle error mask */ + +/******************** Bit definition for USB_OTG_DIEPTSIZ register ********************/ + +#define USB_OTG_DIEPTSIZ_XFRSIZ_Pos (0U) +#define USB_OTG_DIEPTSIZ_XFRSIZ_Msk (0x7FFFFUL << USB_OTG_DIEPTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */ +#define USB_OTG_DIEPTSIZ_XFRSIZ USB_OTG_DIEPTSIZ_XFRSIZ_Msk /*!< Transfer size */ +#define USB_OTG_DIEPTSIZ_PKTCNT_Pos (19U) +#define USB_OTG_DIEPTSIZ_PKTCNT_Msk (0x3FFUL << USB_OTG_DIEPTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */ +#define USB_OTG_DIEPTSIZ_PKTCNT USB_OTG_DIEPTSIZ_PKTCNT_Msk /*!< Packet count */ +#define USB_OTG_DIEPTSIZ_MULCNT_Pos (29U) +#define USB_OTG_DIEPTSIZ_MULCNT_Msk (0x3UL << USB_OTG_DIEPTSIZ_MULCNT_Pos) /*!< 0x60000000 */ +#define USB_OTG_DIEPTSIZ_MULCNT USB_OTG_DIEPTSIZ_MULCNT_Msk /*!< Packet count */ +/******************** Bit definition for USB_OTG_HCTSIZ register ********************/ +#define USB_OTG_HCTSIZ_XFRSIZ_Pos (0U) +#define USB_OTG_HCTSIZ_XFRSIZ_Msk (0x7FFFFUL << USB_OTG_HCTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */ +#define USB_OTG_HCTSIZ_XFRSIZ USB_OTG_HCTSIZ_XFRSIZ_Msk /*!< Transfer size */ +#define USB_OTG_HCTSIZ_PKTCNT_Pos (19U) +#define USB_OTG_HCTSIZ_PKTCNT_Msk (0x3FFUL << USB_OTG_HCTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */ +#define USB_OTG_HCTSIZ_PKTCNT USB_OTG_HCTSIZ_PKTCNT_Msk /*!< Packet count */ +#define USB_OTG_HCTSIZ_DOPING_Pos (31U) +#define USB_OTG_HCTSIZ_DOPING_Msk (0x1UL << USB_OTG_HCTSIZ_DOPING_Pos) /*!< 0x80000000 */ +#define USB_OTG_HCTSIZ_DOPING USB_OTG_HCTSIZ_DOPING_Msk /*!< Do PING */ +#define USB_OTG_HCTSIZ_DPID_Pos (29U) +#define USB_OTG_HCTSIZ_DPID_Msk (0x3UL << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x60000000 */ +#define USB_OTG_HCTSIZ_DPID USB_OTG_HCTSIZ_DPID_Msk /*!< Data PID */ +#define USB_OTG_HCTSIZ_DPID_0 (0x1UL << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x20000000 */ +#define USB_OTG_HCTSIZ_DPID_1 (0x2UL << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x40000000 */ + +/******************** Bit definition for USB_OTG_DIEPDMA register ********************/ +#define USB_OTG_DIEPDMA_DMAADDR_Pos (0U) +#define USB_OTG_DIEPDMA_DMAADDR_Msk (0xFFFFFFFFUL << USB_OTG_DIEPDMA_DMAADDR_Pos) /*!< 0xFFFFFFFF */ +#define USB_OTG_DIEPDMA_DMAADDR USB_OTG_DIEPDMA_DMAADDR_Msk /*!< DMA address */ + +/******************** Bit definition for USB_OTG_HCDMA register ********************/ +#define USB_OTG_HCDMA_DMAADDR_Pos (0U) +#define USB_OTG_HCDMA_DMAADDR_Msk (0xFFFFFFFFUL << USB_OTG_HCDMA_DMAADDR_Pos) /*!< 0xFFFFFFFF */ +#define USB_OTG_HCDMA_DMAADDR USB_OTG_HCDMA_DMAADDR_Msk /*!< DMA address */ + +/******************** Bit definition for USB_OTG_DTXFSTS register ********************/ +#define USB_OTG_DTXFSTS_INEPTFSAV_Pos (0U) +#define USB_OTG_DTXFSTS_INEPTFSAV_Msk (0xFFFFUL << USB_OTG_DTXFSTS_INEPTFSAV_Pos) /*!< 0x0000FFFF */ +#define USB_OTG_DTXFSTS_INEPTFSAV USB_OTG_DTXFSTS_INEPTFSAV_Msk /*!< IN endpoint TxFIFO space available */ + +/******************** Bit definition for USB_OTG_DIEPTXF register ********************/ +#define USB_OTG_DIEPTXF_INEPTXSA_Pos (0U) +#define USB_OTG_DIEPTXF_INEPTXSA_Msk (0xFFFFUL << USB_OTG_DIEPTXF_INEPTXSA_Pos) /*!< 0x0000FFFF */ +#define USB_OTG_DIEPTXF_INEPTXSA USB_OTG_DIEPTXF_INEPTXSA_Msk /*!< IN endpoint FIFOx transmit RAM start address */ +#define USB_OTG_DIEPTXF_INEPTXFD_Pos (16U) +#define USB_OTG_DIEPTXF_INEPTXFD_Msk (0xFFFFUL << USB_OTG_DIEPTXF_INEPTXFD_Pos) /*!< 0xFFFF0000 */ +#define USB_OTG_DIEPTXF_INEPTXFD USB_OTG_DIEPTXF_INEPTXFD_Msk /*!< IN endpoint TxFIFO depth */ + +/******************** Bit definition for USB_OTG_DOEPCTL register ********************/ + +#define USB_OTG_DOEPCTL_MPSIZ_Pos (0U) +#define USB_OTG_DOEPCTL_MPSIZ_Msk (0x7FFUL << USB_OTG_DOEPCTL_MPSIZ_Pos) /*!< 0x000007FF */ +#define USB_OTG_DOEPCTL_MPSIZ USB_OTG_DOEPCTL_MPSIZ_Msk /*!< Maximum packet size */ /*!GINTMSK &= ~(__INTERRUPT__)) +#define USB_UNMASK_INTERRUPT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->GINTMSK |= (__INTERRUPT__)) +#define CLEAR_IN_EP_INTR(__EPNUM__, __INTERRUPT__) (USBx_INEP(__EPNUM__)->DIEPINT = (__INTERRUPT__)) +#define CLEAR_OUT_EP_INTR(__EPNUM__, __INTERRUPT__) (USBx_OUTEP(__EPNUM__)->DOEPINT = (__INTERRUPT__)) +#define USB_MASK_HALT_HC_INT(chnum) (USB_OTG_HC(chnum)->HCINTMSK &= ~USB_OTG_HCINTMSK_CHHM) +#define USB_UNMASK_HALT_HC_INT(chnum) (USB_OTG_HC(chnum)->HCINTMSK |= USB_OTG_HCINTMSK_CHHM) +#define CLEAR_HC_INT(chnum, __INTERRUPT__) (USB_OTG_HC(chnum)->HCINT = (__INTERRUPT__)) + +void usb_dc_low_level_init(uint8_t busid); +void usb_dc_low_level_deinit(uint8_t busid); +void usbd_dwc2_delay_ms(uint8_t ms); +uint32_t usbd_dwc2_get_system_clock(void); + +#endif diff --git a/kernel/cherryusb/port/dwc2/usb_glue_at.c b/kernel/cherryusb/port/dwc2/usb_glue_at.c new file mode 100644 index 0000000..5fcb815 --- /dev/null +++ b/kernel/cherryusb/port/dwc2/usb_glue_at.c @@ -0,0 +1,114 @@ +/* + * Copyright (c) 2024, sakumisu + * + * SPDX-License-Identifier: Apache-2.0 + */ +#include "usbd_core.h" +#include "usbh_core.h" +#include "usb_dwc2_param.h" + +extern unsigned int system_core_clock; + +const struct dwc2_user_params param_pa11_pa12 = { + .phy_type = DWC2_PHY_TYPE_PARAM_FS, + .device_dma_enable = false, + .device_dma_desc_enable = false, + .device_rx_fifo_size = (320 - 16 - 16 - 16 - 16), + .device_tx_fifo_size = { + [0] = 16, // 64 byte + [1] = 16, // 64 byte + [2] = 16, // 64 byte + [3] = 16, // 64 byte + [4] = 0, + [5] = 0, + [6] = 0, + [7] = 0, + [8] = 0, + [9] = 0, + [10] = 0, + [11] = 0, + [12] = 0, + [13] = 0, + [14] = 0, + [15] = 0 }, +#ifdef AT32F415xx + .device_gccfg = ((1 << 16) | (1 << 18) | (1 << 19) | (1 << 21)), +#else + .device_gccfg = ((1 << 16) | (1 << 21)), +#endif + .total_fifo_size = 320 // 1280 byte +}; + +#if __has_include("at32f402_405.h") +#include "at32f402_405.h" + +const struct dwc2_user_params param_pb14_pb15 = { + .phy_type = DWC2_PHY_TYPE_PARAM_UTMI, + .device_dma_enable = true, + .device_dma_desc_enable = false, + .device_rx_fifo_size = (1008 - 16 - 256 - 128 - 128 - 128 - 128), + .device_tx_fifo_size = { + [0] = 16, // 64 byte + [1] = 256, // 1024 byte + [2] = 128, // 512 byte + [3] = 128, // 512 byte + [4] = 128, // 512 byte + [5] = 128, // 512 byte + [6] = 0, + [7] = 0, + [8] = 0, + [9] = 0, + [10] = 0, + [11] = 0, + [12] = 0, + [13] = 0, + [14] = 0, + [15] = 0 }, + + .host_dma_desc_enable = false, + .host_rx_fifo_size = 624, + .host_nperio_tx_fifo_size = 128, // 512 byte + .host_perio_tx_fifo_size = 256, // 1024 byte + + .device_gccfg = ((1 << 16) | (1 << 21)), + .host_gccfg = ((1 << 16) | (1 << 21)) +}; +#endif + +#ifndef CONFIG_USB_DWC2_CUSTOM_PARAM +void dwc2_get_user_params(uint32_t reg_base, struct dwc2_user_params *params) +{ +#if __has_include("at32f402_405.h") + if (reg_base == OTGHS_BASE) { + memcpy(params, ¶m_pb14_pb15, sizeof(struct dwc2_user_params)); + } else { + memcpy(params, ¶m_pa11_pa12, sizeof(struct dwc2_user_params)); + } +#else + memcpy(params, ¶m_pa11_pa12, sizeof(struct dwc2_user_params)); +#endif +#ifdef CONFIG_USB_DWC2_CUSTOM_FIFO + struct usb_dwc2_user_fifo_config s_dwc2_fifo_config; + + dwc2_get_user_fifo_config(reg_base, &s_dwc2_fifo_config); + + params->device_rx_fifo_size = s_dwc2_fifo_config.device_rx_fifo_size; + for (uint8_t i = 0; i < MAX_EPS_CHANNELS; i++) { + params->device_tx_fifo_size[i] = s_dwc2_fifo_config.device_tx_fifo_size[i]; + } +#endif +} +#endif + +void usbd_dwc2_delay_ms(uint8_t ms) +{ + uint32_t count = system_core_clock / 1000 * ms; + while (count--) { + __asm volatile("nop"); + } +} + +uint32_t usbd_dwc2_get_system_clock(void) +{ + return system_core_clock; +} diff --git a/kernel/cherryusb/port/dwc2/usb_glue_esp.c b/kernel/cherryusb/port/dwc2/usb_glue_esp.c new file mode 100644 index 0000000..6023129 --- /dev/null +++ b/kernel/cherryusb/port/dwc2/usb_glue_esp.c @@ -0,0 +1,296 @@ +/* + * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#include "sdkconfig.h" +#include "esp_idf_version.h" +#include "esp_intr_alloc.h" +#include "esp_private/usb_phy.h" +#include "soc/periph_defs.h" +#include "freertos/FreeRTOS.h" +#include "freertos/task.h" +#include "usbd_core.h" +#include "usbh_core.h" +#include "usb_dwc2_param.h" + +#define GET_USB_INDEX(reg_base) 0 +#define GET_USB_INTR_SOURCE(reg_base) ETS_USB_INTR_SOURCE +#define GET_USB_PHY_TARGET(reg_base) USB_PHY_TARGET_INT +#define GET_USB_PHY_SPEED(reg_base) USB_PHY_SPEED_UNDEFINED +#ifdef CONFIG_IDF_TARGET_ESP32S2 +#define DEFAULT_CPU_FREQ_MHZ CONFIG_ESP32S2_DEFAULT_CPU_FREQ_MHZ +#define DEFAULT_USB_INTR_SOURCE ETS_USB_INTR_SOURCE +#elif CONFIG_IDF_TARGET_ESP32S3 +#define DEFAULT_CPU_FREQ_MHZ CONFIG_ESP32S3_DEFAULT_CPU_FREQ_MHZ +#define DEFAULT_USB_INTR_SOURCE ETS_USB_INTR_SOURCE +#elif CONFIG_IDF_TARGET_ESP32P4 +#undef GET_USB_INDEX +#define GET_USB_INDEX(reg_base) ((reg_base) == (void*)ESP_USB_HS0_BASE ? 0 : 1) +#define DEFAULT_CPU_FREQ_MHZ CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ +#define DEFAULT_USB_INTR_SOURCE ETS_USB_OTG_INTR_SOURCE +#define USB_FS_INTR_SOURCE ETS_USB_OTG11_CH0_INTR_SOURCE +#undef GET_USB_INTR_SOURCE +#define GET_USB_INTR_SOURCE(reg_base) ((reg_base) == (void*)ESP_USB_HS0_BASE ? DEFAULT_USB_INTR_SOURCE : USB_FS_INTR_SOURCE) +#undef GET_USB_PHY_TARGET +#define GET_USB_PHY_TARGET(reg_base) ((reg_base) == (void*)ESP_USB_HS0_BASE ? USB_PHY_TARGET_UTMI : USB_PHY_TARGET_INT) +#undef GET_USB_PHY_SPEED +#define GET_USB_PHY_SPEED(reg_base) ((reg_base) == (void*)ESP_USB_HS0_BASE ? USB_PHY_SPEED_HIGH : USB_PHY_SPEED_FULL) +#else +#define DEFAULT_CPU_FREQ_MHZ 160 +#endif + +uint32_t SystemCoreClock = (DEFAULT_CPU_FREQ_MHZ * 1000 * 1000); +static usb_phy_handle_t s_phy_handle[SOC_USB_OTG_PERIPH_NUM] = {NULL}; +static intr_handle_t s_interrupt_handle[SOC_USB_OTG_PERIPH_NUM] = {NULL}; + +#if CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3 +const struct dwc2_user_params param_fs = { + .phy_type = DWC2_PHY_TYPE_PARAM_FS, + .device_dma_enable = true, + .device_dma_desc_enable = false, + .device_rx_fifo_size = (200 - 16 * 7), + .device_tx_fifo_size = { + [0] = 16, // 64 byte + [1] = 16, // 64 byte + [2] = 16, // 64 byte + [3] = 16, // 64 byte + [4] = 16, // 64 byte + [5] = 16, // 64 byte + [6] = 16, // 64 byte + [7] = 0, + [8] = 0, + [9] = 0, + [10] = 0, + [11] = 0, + [12] = 0, + [13] = 0, + [14] = 0, + [15] = 0 }, + + .host_dma_desc_enable = false, + .host_rx_fifo_size = 80, + .host_nperio_tx_fifo_size = 60, // 240 byte + .host_perio_tx_fifo_size = 60, // 240 byte +}; +#elif CONFIG_IDF_TARGET_ESP32P4 +const struct dwc2_user_params param_fs = { + .phy_type = DWC2_PHY_TYPE_PARAM_FS, + .device_dma_enable = true, + .device_dma_desc_enable = false, + .device_rx_fifo_size = (200 - 16 * 7), + .device_tx_fifo_size = { + [0] = 16, // 64 byte + [1] = 16, // 64 byte + [2] = 16, // 64 byte + [3] = 16, // 64 byte + [4] = 16, // 64 byte + [5] = 16, // 64 byte + [6] = 16, // 64 byte + [7] = 0, + [8] = 0, + [9] = 0, + [10] = 0, + [11] = 0, + [12] = 0, + [13] = 0, + [14] = 0, + [15] = 0 }, + + .host_dma_desc_enable = false, + .host_rx_fifo_size = (200 - 60 - 60), + .host_nperio_tx_fifo_size = 60, // 240 byte + .host_perio_tx_fifo_size = 60, // 240 byte +}; + +const struct dwc2_user_params param_hs = { + .phy_type = DWC2_PHY_TYPE_PARAM_UTMI, + .device_dma_enable = true, + .device_dma_desc_enable = false, + .device_rx_fifo_size = (896 - 16 - 128 - 128 - 128 - 128 - 16 - 16), + .device_tx_fifo_size = { + [0] = 16, // 64 byte + [1] = 128, // 512 byte + [2] = 128, // 512 byte + [3] = 128, // 512 byte + [4] = 128, // 512 byte + [5] = 16, // 64 byte + [6] = 16, // 64 byte + [7] = 0, + [8] = 0, + [9] = 0, + [10] = 0, + [11] = 0, + [12] = 0, + [13] = 0, + [14] = 0, + [15] = 0 }, + + .host_dma_desc_enable = false, + .host_rx_fifo_size = (896 - 128 - 128), + .host_nperio_tx_fifo_size = 128, // 512 byte + .host_perio_tx_fifo_size = 128, // 512 byte +}; +#endif + +static void usb_dc_interrupt_cb(void *arg_pv) +{ + extern void USBD_IRQHandler(uint8_t busid); + uint8_t busid = (uintptr_t)arg_pv; + USBD_IRQHandler(busid); +} + +void usb_dc_low_level_init(uint8_t busid) +{ + esp_err_t ret; + void *reg_base = (void*)g_usbdev_bus[busid].reg_base; + (void)reg_base; + usb_phy_config_t phy_config = { + .controller = USB_PHY_CTRL_OTG, + .otg_mode = USB_OTG_MODE_DEVICE, + }; + phy_config.target = GET_USB_PHY_TARGET(reg_base); + phy_config.otg_speed = GET_USB_PHY_SPEED(reg_base); + + ret = usb_new_phy(&phy_config, &s_phy_handle[GET_USB_INDEX(reg_base)]); + if (ret != ESP_OK) { + USB_LOG_ERR("USB Phy Init Failed!\r\n"); + return; + } + + uintptr_t arg = busid; + // TODO: Check when to enable interrupt + ret = esp_intr_alloc(GET_USB_INTR_SOURCE(reg_base), ESP_INTR_FLAG_LOWMED, usb_dc_interrupt_cb, (void *)arg, &s_interrupt_handle[GET_USB_INDEX(reg_base)]); + if (ret != ESP_OK) { + USB_LOG_ERR("USB Interrupt Init Failed!\r\n"); + return; + } + USB_LOG_INFO("cherryusb, version: " CHERRYUSB_VERSION_STR "\r\n"); +} + +void usb_dc_low_level_deinit(uint8_t busid) +{ + void *reg_base = (void*)g_usbdev_bus[busid].reg_base; + (void)reg_base; + if (s_interrupt_handle[GET_USB_INDEX(reg_base)]) { + esp_intr_free(s_interrupt_handle[GET_USB_INDEX(reg_base)]); + s_interrupt_handle[GET_USB_INDEX(reg_base)] = NULL; + } + if (s_phy_handle[GET_USB_INDEX(reg_base)]) { + usb_del_phy(s_phy_handle[GET_USB_INDEX(reg_base)]); + s_phy_handle[GET_USB_INDEX(reg_base)] = NULL; + } +} + +static void usb_hc_interrupt_cb(void *arg_pv) +{ + extern void USBH_IRQHandler(uint8_t busid); + uint8_t busid = (uintptr_t)arg_pv; + USBH_IRQHandler(busid); +} + +void usb_hc_low_level_init(struct usbh_bus *bus) +{ + void *reg_base = (void*)bus->hcd.reg_base; + (void)reg_base; + // Host Library defaults to internal PHY + usb_phy_config_t phy_config = { + .controller = USB_PHY_CTRL_OTG, + .otg_mode = USB_OTG_MODE_HOST, + .otg_speed = USB_PHY_SPEED_UNDEFINED, // In Host mode, the speed is determined by the connected device + .ext_io_conf = NULL, + .otg_io_conf = NULL, + }; + phy_config.target = GET_USB_PHY_TARGET(reg_base); + + esp_err_t ret = usb_new_phy(&phy_config, &s_phy_handle[GET_USB_INDEX(reg_base)]); + if (ret != ESP_OK) { + USB_LOG_ERR("USB Phy Init Failed!\r\n"); + return; + } + + uintptr_t arg = bus->busid; + // TODO: Check when to enable interrupt + ret = esp_intr_alloc(GET_USB_INTR_SOURCE(reg_base), ESP_INTR_FLAG_LOWMED, usb_hc_interrupt_cb, (void*)(arg), &s_interrupt_handle[GET_USB_INDEX(reg_base)]); + if (ret != ESP_OK) { + USB_LOG_ERR("USB Interrupt Init Failed!\r\n"); + return; + } + USB_LOG_INFO("cherryusb, version: " CHERRYUSB_VERSION_STR "\r\n"); +} + +void usb_hc_low_level_deinit(struct usbh_bus *bus) +{ + void *reg_base = (void*)bus->hcd.reg_base; + (void)reg_base; + if (s_interrupt_handle[GET_USB_INDEX(reg_base)]) { + esp_intr_free(s_interrupt_handle[GET_USB_INDEX(reg_base)]); + s_interrupt_handle[GET_USB_INDEX(reg_base)] = NULL; + } + if (s_phy_handle[GET_USB_INDEX(reg_base)]) { + usb_del_phy(s_phy_handle[GET_USB_INDEX(reg_base)]); + s_phy_handle[GET_USB_INDEX(reg_base)] = NULL; + } +} + +void dwc2_get_user_params(uint32_t reg_base, struct dwc2_user_params *params) +{ +#if CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3 + memcpy(params, ¶m_fs, sizeof(struct dwc2_user_params)); +#elif CONFIG_IDF_TARGET_ESP32P4 + if (reg_base == ESP_USB_HS0_BASE) { + memcpy(params, ¶m_hs, sizeof(struct dwc2_user_params)); + } else { + memcpy(params, ¶m_fs, sizeof(struct dwc2_user_params)); + } +#endif +#ifdef CONFIG_USB_DWC2_CUSTOM_FIFO + struct usb_dwc2_user_fifo_config s_dwc2_fifo_config; + + dwc2_get_user_fifo_config(reg_base, &s_dwc2_fifo_config); + + params->device_rx_fifo_size = s_dwc2_fifo_config.device_rx_fifo_size; + for (uint8_t i = 0; i < MAX_EPS_CHANNELS; i++) + { + params->device_tx_fifo_size[i] = s_dwc2_fifo_config.device_tx_fifo_size[i]; + } +#endif +} + +void usbd_dwc2_delay_ms(uint8_t ms) +{ + vTaskDelay(pdMS_TO_TICKS(ms)); +} + +uint32_t usbd_dwc2_get_system_clock(void) +{ + return SystemCoreClock; +} + +#ifdef CONFIG_USB_DCACHE_ENABLE +#include "esp_cache.h" + +void usb_dcache_clean(uintptr_t addr, size_t size) +{ + if (size == 0) + return; + + esp_cache_msync((void *)addr, size, ESP_CACHE_MSYNC_FLAG_TYPE_DATA | ESP_CACHE_MSYNC_FLAG_DIR_C2M); +} + +void usb_dcache_invalidate(uintptr_t addr, size_t size) +{ + if (size == 0) + return; + + esp_cache_msync((void *)addr, size, ESP_CACHE_MSYNC_FLAG_TYPE_DATA | ESP_CACHE_MSYNC_FLAG_DIR_M2C); +} + +void usb_dcache_flush(uintptr_t addr, size_t size) +{ + if (size == 0) + return; + + esp_cache_msync((void *)addr, size, ESP_CACHE_MSYNC_FLAG_TYPE_DATA | ESP_CACHE_MSYNC_FLAG_DIR_C2M | ESP_CACHE_MSYNC_FLAG_DIR_M2C); +} +#endif \ No newline at end of file diff --git a/kernel/cherryusb/port/dwc2/usb_glue_gd.c b/kernel/cherryusb/port/dwc2/usb_glue_gd.c new file mode 100644 index 0000000..1a23686 --- /dev/null +++ b/kernel/cherryusb/port/dwc2/usb_glue_gd.c @@ -0,0 +1,50 @@ +/* + * Copyright (c) 2024, sakumisu + * + * SPDX-License-Identifier: Apache-2.0 + */ +#include "usb_config.h" +#include "stdint.h" +#include "usb_dwc2_reg.h" + +#if 1 +#error you need to modify some usb register values then use this chip +#endif + +#if CONFIG_USBDEV_EP_NUM != 4 && CONFIG_USBDEV_EP_NUM != 6 +#error "gd32 only has 4 endpoints for pa11/pa12 and 6 endpoints for pb14/pb15" +#endif + +/* you can find this config in function:usb_core_init, file:drv_usb_core.c, for example: + * + * usb_regs->gr->GCCFG |= GCCFG_PWRON | GCCFG_VBUSACEN | GCCFG_VBUSBCEN; + * +*/ + +uint32_t usbd_get_dwc2_gccfg_conf(uint32_t reg_base) +{ +#ifdef CONFIG_USB_HS + return 0; +#else + return ((1 << 16) | (1 << 18) | (1 << 19) | (1 << 21)); +#endif +} + +uint32_t usbh_get_dwc2_gccfg_conf(uint32_t reg_base) +{ +#ifdef CONFIG_USB_HS + return 0; +#else + return ((1 << 16) | (1 << 18) | (1 << 19) | (1 << 21)); +#endif +} + +extern uint32_t SystemCoreClock; + +void usbd_dwc2_delay_ms(uint8_t ms) +{ + uint32_t count = SystemCoreClock / 1000 * ms; + while (count--) { + __asm volatile("nop"); + } +} diff --git a/kernel/cherryusb/port/dwc2/usb_glue_hc.c b/kernel/cherryusb/port/dwc2/usb_glue_hc.c new file mode 100644 index 0000000..38e065a --- /dev/null +++ b/kernel/cherryusb/port/dwc2/usb_glue_hc.c @@ -0,0 +1,308 @@ +/* + * Copyright (c) 2022-2024, Xiaohua Semiconductor Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2025-08-08 CDT first version + */ + +#include "usbd_core.h" +#include "usbh_core.h" +#include "usb_dwc2_param.h" + +#include "board_config.h" + +#if defined(RT_CHERRYUSB_HOST) && defined(RT_CHERRYUSB_DEVICE) + #if defined(HC32F460) || defined(HC32F472) + #error "Only one USB role can be selected!" + #endif +#endif + +const struct dwc2_user_params param_fs_core = +{ + .phy_type = DWC2_PHY_TYPE_PARAM_FS, +#ifdef CONFIG_USB_DWC2_DMA_ENABLE + .device_dma_enable = true, +#else + .device_dma_enable = false, +#endif + .device_dma_desc_enable = false, + .device_rx_fifo_size = CONFIG_USB_FS_CORE_DEVICE_RX_FIFO_SIZE, + .device_tx_fifo_size = { + [0] = CONFIG_USB_FS_CORE_DEVICE_TX0_FIFO_SIZE, + [1] = CONFIG_USB_FS_CORE_DEVICE_TX1_FIFO_SIZE, + [2] = CONFIG_USB_FS_CORE_DEVICE_TX2_FIFO_SIZE, + [3] = CONFIG_USB_FS_CORE_DEVICE_TX3_FIFO_SIZE, + [4] = CONFIG_USB_FS_CORE_DEVICE_TX4_FIFO_SIZE, + [5] = CONFIG_USB_FS_CORE_DEVICE_TX5_FIFO_SIZE, +#if defined(HC32F4A0) || defined(HC32F4A8) + [6] = CONFIG_USB_FS_CORE_DEVICE_TX6_FIFO_SIZE, + [7] = CONFIG_USB_FS_CORE_DEVICE_TX7_FIFO_SIZE, + [8] = CONFIG_USB_FS_CORE_DEVICE_TX8_FIFO_SIZE, + [9] = CONFIG_USB_FS_CORE_DEVICE_TX9_FIFO_SIZE, + [10] = CONFIG_USB_FS_CORE_DEVICE_TX10_FIFO_SIZE, + [11] = CONFIG_USB_FS_CORE_DEVICE_TX11_FIFO_SIZE, + [12] = CONFIG_USB_FS_CORE_DEVICE_TX12_FIFO_SIZE, + [13] = CONFIG_USB_FS_CORE_DEVICE_TX13_FIFO_SIZE, + [14] = CONFIG_USB_FS_CORE_DEVICE_TX14_FIFO_SIZE, + [15] = CONFIG_USB_FS_CORE_DEVICE_TX15_FIFO_SIZE +#elif defined(HC32F460) || defined(HC32F472) + [6] = 0, + [7] = 0, + [8] = 0, + [9] = 0, + [10] = 0, + [11] = 0, + [12] = 0, + [13] = 0, + [14] = 0, + [15] = 0 +#endif + }, + .total_fifo_size = CONFIG_USB_FS_CORE_TOTAL_FIFO_SIZE, + + .host_dma_desc_enable = false, + .host_rx_fifo_size = CONFIG_USB_FS_CORE_HOST_RX_FIFO_SIZE, + .host_nperio_tx_fifo_size = CONFIG_USB_FS_CORE_HOST_NP_FIFO_SIZE, + .host_perio_tx_fifo_size = CONFIG_USB_FS_CORE_HOST_PE_FIFO_SIZE, + .device_gccfg = 0, + .host_gccfg = 0, +#if defined(HC32F4A0) || defined(HC32F4A8) || defined(HC32F460) + .b_session_valid_override = false, +#elif defined(HC32F472) + .b_session_valid_override = true, +#endif +}; + +#if defined(HC32F4A0) || defined(HC32F4A8) +const struct dwc2_user_params param_hs_core = +{ +#ifdef CONFIG_USB_HS + .phy_type = DWC2_PHY_TYPE_PARAM_UTMI, +#else + .phy_type = DWC2_PHY_TYPE_PARAM_FS, +#endif +#ifdef CONFIG_USB_DWC2_DMA_ENABLE + .device_dma_enable = true, +#else + .device_dma_enable = false, +#endif + .device_dma_desc_enable = false, + .device_rx_fifo_size = CONFIG_USB_HS_CORE_DEVICE_RX_FIFO_SIZE, + .device_tx_fifo_size = { + [0] = CONFIG_USB_HS_CORE_DEVICE_TX0_FIFO_SIZE, + [1] = CONFIG_USB_HS_CORE_DEVICE_TX1_FIFO_SIZE, + [2] = CONFIG_USB_HS_CORE_DEVICE_TX2_FIFO_SIZE, + [3] = CONFIG_USB_HS_CORE_DEVICE_TX3_FIFO_SIZE, + [4] = CONFIG_USB_HS_CORE_DEVICE_TX4_FIFO_SIZE, + [5] = CONFIG_USB_HS_CORE_DEVICE_TX5_FIFO_SIZE, + [6] = CONFIG_USB_HS_CORE_DEVICE_TX6_FIFO_SIZE, + [7] = CONFIG_USB_HS_CORE_DEVICE_TX7_FIFO_SIZE, + [8] = CONFIG_USB_HS_CORE_DEVICE_TX8_FIFO_SIZE, + [9] = CONFIG_USB_HS_CORE_DEVICE_TX9_FIFO_SIZE, + [10] = CONFIG_USB_HS_CORE_DEVICE_TX10_FIFO_SIZE, + [11] = CONFIG_USB_HS_CORE_DEVICE_TX11_FIFO_SIZE, + [12] = CONFIG_USB_HS_CORE_DEVICE_TX12_FIFO_SIZE, + [13] = CONFIG_USB_HS_CORE_DEVICE_TX13_FIFO_SIZE, + [14] = CONFIG_USB_HS_CORE_DEVICE_TX14_FIFO_SIZE, + [15] = CONFIG_USB_HS_CORE_DEVICE_TX15_FIFO_SIZE + }, + .total_fifo_size = CONFIG_USB_HS_CORE_TOTAL_FIFO_SIZE, + + .host_dma_desc_enable = false, + .host_rx_fifo_size = CONFIG_USB_HS_CORE_HOST_RX_FIFO_SIZE, + .host_nperio_tx_fifo_size = CONFIG_USB_HS_CORE_HOST_NP_FIFO_SIZE, + .host_perio_tx_fifo_size = CONFIG_USB_HS_CORE_HOST_PE_FIFO_SIZE, + .device_gccfg = 0, + .host_gccfg = 0, + .b_session_valid_override = false, +}; +#endif + +#ifndef CONFIG_USB_DWC2_CUSTOM_PARAM +void dwc2_get_user_params(uint32_t reg_base, struct dwc2_user_params *params) +{ +#if defined(HC32F4A0) || defined(HC32F4A8) + if (reg_base == CM_USBHS_BASE) + { + memcpy(params, ¶m_hs_core, sizeof(struct dwc2_user_params)); + } + else +#endif + { + memcpy(params, ¶m_fs_core, sizeof(struct dwc2_user_params)); + } +#ifdef CONFIG_USB_DWC2_CUSTOM_FIFO + struct usb_dwc2_user_fifo_config s_dwc2_fifo_config; + + dwc2_get_user_fifo_config(reg_base, &s_dwc2_fifo_config); + + params->device_rx_fifo_size = s_dwc2_fifo_config.device_rx_fifo_size; + for (uint8_t i = 0; i < MAX_EPS_CHANNELS; i++) + { + params->device_tx_fifo_size[i] = s_dwc2_fifo_config.device_tx_fifo_size[i]; + } +#endif +} +#endif + +#define BOARD_INIT_USB_HOST_MODE (0U) +#define BOARD_INIT_USB_DEVICE_MODE (1U) +extern rt_err_t rt_hw_usbfs_board_init(uint8_t devmode); +static uint8_t g_usb_fs_busid = 0U; +#if defined(HC32F4A0) || defined(HC32F4A8) + extern rt_err_t rt_hw_usbhs_board_init(uint8_t devmode); + static uint8_t g_usb_hs_busid = 0U; +#endif + +#if defined(RT_CHERRYUSB_HOST) +static void usbh_fs_irq_handler(void) +{ + USBH_IRQHandler(g_usb_fs_busid); +} + +#if defined(HC32F4A0) || defined(HC32F4A8) +static void usbh_hs_irq_handler(void) +{ + USBH_IRQHandler(g_usb_hs_busid); +} +#endif + +#if defined(HC32F472) +void USBFS_Handler(void) +{ + usbh_fs_irq_handler(); +} +#endif + +void usb_hc_low_level_init(struct usbh_bus *bus) +{ + struct hc32_irq_config irq_config; + +#if defined(HC32F4A0) || defined(HC32F4A8) + if (bus->hcd.reg_base == CM_USBHS_BASE) + { + g_usb_hs_busid = bus->hcd.hcd_id; + + rt_hw_usbhs_board_init(BOARD_INIT_USB_HOST_MODE); + FCG_Fcg1PeriphClockCmd(FCG1_PERIPH_USBHS, ENABLE); +#ifndef CONFIG_USB_HS + /* enable the embedded PHY in USBHS mode */ + CM_PERIC->USB_SYCTLREG |= PERIC_USB_SYCTLREG_USBHS_FSPHYE; +#endif + + irq_config.irq_num = BSP_USBHS_GLB_IRQ_NUM; + irq_config.int_src = INT_SRC_USBHS_GLB; + irq_config.irq_prio = BSP_USBHS_GLB_IRQ_PRIO; + /* register interrupt */ + hc32_install_irq_handler(&irq_config, + usbh_hs_irq_handler, + RT_TRUE); + } + else +#endif + { + g_usb_fs_busid = bus->hcd.hcd_id; + + rt_hw_usbfs_board_init(BOARD_INIT_USB_HOST_MODE); + FCG_Fcg1PeriphClockCmd(FCG1_PERIPH_USBFS, ENABLE); + + irq_config.irq_num = BSP_USBFS_GLB_IRQ_NUM; + irq_config.int_src = INT_SRC_USBFS_GLB; + irq_config.irq_prio = BSP_USBFS_GLB_IRQ_PRIO; + /* register interrupt */ + hc32_install_irq_handler(&irq_config, + usbh_fs_irq_handler, + RT_TRUE); + } + +} +#endif + +#if defined(RT_CHERRYUSB_DEVICE) +static void usbd_fs_irq_handler(void) +{ + USBD_IRQHandler(g_usb_fs_busid); +} + +#if defined(HC32F4A0) || defined(HC32F4A8) +static void usbd_hs_irq_handler(void) +{ + USBD_IRQHandler(g_usb_hs_busid); +} +#endif + +#if defined(HC32F472) +void USBFS_Handler(void) +{ + usbd_fs_irq_handler(); +} +#endif + +void usb_dc_low_level_init(uint8_t busid) +{ + struct hc32_irq_config irq_config; + +#if defined(HC32F4A0) || defined(HC32F4A8) + if (g_usbdev_bus[busid].reg_base == CM_USBHS_BASE) + { + g_usb_hs_busid = busid; + + rt_hw_usbhs_board_init(BOARD_INIT_USB_DEVICE_MODE); + FCG_Fcg1PeriphClockCmd(FCG1_PERIPH_USBHS, ENABLE); + +#ifndef CONFIG_USB_HS + /* enable the embedded PHY in USBHS mode */ + CM_PERIC->USB_SYCTLREG |= PERIC_USB_SYCTLREG_USBHS_FSPHYE; +#endif + + irq_config.irq_num = BSP_USBHS_GLB_IRQ_NUM; + irq_config.int_src = INT_SRC_USBHS_GLB; + irq_config.irq_prio = BSP_USBHS_GLB_IRQ_PRIO; + /* register interrupt */ + hc32_install_irq_handler(&irq_config, + usbd_hs_irq_handler, + RT_TRUE); + } + else +#endif + { + g_usb_fs_busid = busid; + + rt_hw_usbfs_board_init(BOARD_INIT_USB_DEVICE_MODE); + FCG_Fcg1PeriphClockCmd(FCG1_PERIPH_USBFS, ENABLE); + + irq_config.irq_num = BSP_USBFS_GLB_IRQ_NUM; + irq_config.int_src = INT_SRC_USBFS_GLB; + irq_config.irq_prio = BSP_USBFS_GLB_IRQ_PRIO; + /* register interrupt */ + hc32_install_irq_handler(&irq_config, + usbd_fs_irq_handler, + RT_TRUE); + } +} + +void usb_dc_low_level_deinit(uint8_t busid) +{ + (void)busid; + /* reserved */ +} + +#endif + +extern uint32_t SystemCoreClock; + +void usbd_dwc2_delay_ms(uint8_t ms) +{ + uint32_t count = SystemCoreClock / 1000 * ms; + while (count--) { + __asm volatile("nop"); + } +} + +uint32_t usbd_dwc2_get_system_clock(void) +{ + return SystemCoreClock; +} diff --git a/kernel/cherryusb/port/dwc2/usb_glue_infineon.c b/kernel/cherryusb/port/dwc2/usb_glue_infineon.c new file mode 100644 index 0000000..5e54f57 --- /dev/null +++ b/kernel/cherryusb/port/dwc2/usb_glue_infineon.c @@ -0,0 +1,159 @@ +/* + * Copyright (c) 2026, sakumisu + * + * SPDX-License-Identifier: Apache-2.0 + */ +#include "usbd_core.h" +#include "usbh_core.h" +#include "usb_dwc2_param.h" +#include "rtthread.h" +#include "cybsp.h" +#include "cy_device.h" + +#if defined (COMPONENT_CM55) + +#if !defined(CONFIG_USB_DCACHE_ENABLE) +#error "Please enable CONFIG_USB_DCACHE_ENABLE and put USB_NOCACHE_RAM_SECTION to section ".cy_socmem_data" for CM55" +#endif + +#else +#define CONFIG_USB_DWC2_DMA_ENABLE +#endif + +const struct dwc2_user_params param_common = { + .phy_type = DWC2_PHY_TYPE_PARAM_UTMI, +#ifdef CONFIG_USB_DWC2_DMA_ENABLE + .device_dma_enable = true, +#else + .device_dma_enable = false, +#endif + .device_dma_desc_enable = false, + .device_rx_fifo_size = 0x21F, + .device_tx_fifo_size = { + [0] = 16, // 64 byte + [1] = 0x300, // 1024 byte, tripple buffer + [2] = 0x300, // 1024 byte, tripple buffer + [3] = 0x300, // 1024 byte, tripple buffer + [4] = 0x300, // 1024 byte, tripple buffer + [5] = 0x300, // 1024 byte, tripple buffer + [6] = 0x300, // 1024 byte, tripple buffer + [7] = 0x300, // 1024 byte, tripple buffer + [8] = 0x300, // 1024 byte, tripple buffer + [9] = 0, + [10] = 0, + [11] = 0, + [12] = 0, + [13] = 0, + [14] = 0, + [15] = 0 }, + + .host_dma_desc_enable = false, + .host_rx_fifo_size = 0x21F, + .host_nperio_tx_fifo_size = 0x100, // 512 byte, double buffer + .host_perio_tx_fifo_size = 0x400, // 1024 byte, four buffer + + .device_gccfg = 0, + .host_gccfg = 0 +}; + +#ifndef CONFIG_USB_DWC2_CUSTOM_PARAM +void dwc2_get_user_params(uint32_t reg_base, struct dwc2_user_params *params) +{ + memcpy(params, ¶m_common, sizeof(struct dwc2_user_params)); +#ifdef CONFIG_USB_DWC2_CUSTOM_FIFO + struct usb_dwc2_user_fifo_config s_dwc2_fifo_config; + + dwc2_get_user_fifo_config(reg_base, &s_dwc2_fifo_config); + + params->device_rx_fifo_size = s_dwc2_fifo_config.device_rx_fifo_size; + for (uint8_t i = 0; i < MAX_EPS_CHANNELS; i++) { + params->device_tx_fifo_size[i] = s_dwc2_fifo_config.device_tx_fifo_size[i]; + } +#endif +} +#endif + +void USBHS_DEVICE_IRQHandler(void) +{ + USBD_IRQHandler(0); +} + +void usb_dc_low_level_init(uint8_t busid) +{ + USBHS_SS->SUBSYSTEM_CTL = (1 << USBHS_SS_SUBSYSTEM_CTL_AHB_MASTER_SYNC_Pos) | USBHS_SS_SUBSYSTEM_CTL_SS_ENABLE_Msk; + USBHS_SS->PHY_FUNC_CTL_1 |= (7 << USBHS_SS_PHY_FUNC_CTL_1_PLL_FSEL_Pos); + USBHS_SS->PHY_FUNC_CTL_2 |= (USBHS_SS_PHY_FUNC_CTL_2_RES_TUNING_SEL_Msk | USBHS_SS_PHY_FUNC_CTL_2_EFUSE_SEL_Msk); + + rt_thread_mdelay(200); // Wait for PHY stable + + cy_stc_sysint_t usb_int_cfg = { + .intrSrc = usbhs_interrupt_usbhsctrl_IRQn, + .intrPriority = 3 + }; + + /* Install the interrupt service routine */ + Cy_SysInt_Init(&usb_int_cfg, USBHS_DEVICE_IRQHandler); + + NVIC_EnableIRQ(usbhs_interrupt_usbhsctrl_IRQn); +} + +void usb_dc_low_level_deinit(uint8_t busid) +{ + NVIC_DisableIRQ(usbhs_interrupt_usbhsctrl_IRQn); +} + +void usbd_dwc2_delay_ms(uint8_t ms) +{ + rt_thread_mdelay(ms); +} + +uint32_t usbd_dwc2_get_system_clock(void) +{ + return SystemCoreClock; +} + +void USBHS_HOST_IRQHandler(void) +{ + USBH_IRQHandler(0); +} + +void usb_hc_low_level_init(struct usbh_bus *bus) +{ + USBHS_SS->SUBSYSTEM_CTL = (1 << USBHS_SS_SUBSYSTEM_CTL_AHB_MASTER_SYNC_Pos) | USBHS_SS_SUBSYSTEM_CTL_USB_MODE_Msk | USBHS_SS_SUBSYSTEM_CTL_SS_ENABLE_Msk; + USBHS_SS->PHY_FUNC_CTL_1 |= (7 << USBHS_SS_PHY_FUNC_CTL_1_PLL_FSEL_Pos); + USBHS_SS->PHY_FUNC_CTL_2 |= (USBHS_SS_PHY_FUNC_CTL_2_RES_TUNING_SEL_Msk | USBHS_SS_PHY_FUNC_CTL_2_EFUSE_SEL_Msk); + + rt_thread_mdelay(200); // Wait for PHY stable + + cy_stc_sysint_t usb_int_cfg = { + .intrSrc = usbhs_interrupt_usbhsctrl_IRQn, + .intrPriority = 3 + }; + + /* Install the interrupt service routine */ + Cy_SysInt_Init(&usb_int_cfg, USBHS_HOST_IRQHandler); + + NVIC_EnableIRQ(usbhs_interrupt_usbhsctrl_IRQn); +} + +void usb_hc_low_level_deinit(struct usbh_bus *bus) +{ + NVIC_DisableIRQ(usbhs_interrupt_usbhsctrl_IRQn); +} + +#ifdef CONFIG_USB_DCACHE_ENABLE +void usb_dcache_clean(uintptr_t addr, size_t size) +{ + SCB_CleanDCache_by_Addr((void *)addr, size); +} + +void usb_dcache_invalidate(uintptr_t addr, size_t size) +{ + SCB_InvalidateDCache_by_Addr((void *)addr, size); +} + +void usb_dcache_flush(uintptr_t addr, size_t size) +{ + SCB_CleanInvalidateDCache_by_Addr((void *)addr, size); +} +#endif diff --git a/kernel/cherryusb/port/dwc2/usb_glue_kendryte.c b/kernel/cherryusb/port/dwc2/usb_glue_kendryte.c new file mode 100644 index 0000000..4e111dd --- /dev/null +++ b/kernel/cherryusb/port/dwc2/usb_glue_kendryte.c @@ -0,0 +1,225 @@ +/* Copyright (c) 2023, Canaan Bright Sight Co., Ltd + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND + * CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include "usbd_core.h" +#include "usbh_core.h" +#include "usb_dwc2_param.h" + +#include +#include "sysctl_rst.h" +#include "ioremap.h" +#include "mmu.h" +#include "cache.h" + +extern rt_mmu_info mmu_info; + +#if defined(ENABLE_CHERRY_USB) || defined(PKG_USING_CHERRYUSB) || defined(RT_USING_CHERRYUSB) +#define DEFAULT_USB_HCLK_FREQ_MHZ 200 + +uint32_t SystemCoreClock = (DEFAULT_USB_HCLK_FREQ_MHZ * 1000 * 1000); + +const uintptr_t usb_dev_addr[2] = { 0x91500000UL, 0x91540000UL }; + +#define USB_IDPULLUP0 (1 << 4) +#define USB_DMPULLDOWN0 (1 << 8) +#define USB_DPPULLDOWN0 (1 << 9) + +const struct dwc2_user_params param_common = { + .phy_type = DWC2_PHY_TYPE_PARAM_UTMI, + .device_dma_enable = true, + .device_dma_desc_enable = false, + .device_rx_fifo_size = (3016 - 16 - 256 * 8), + .device_tx_fifo_size = { + [0] = 16, // 64 byte + [1] = 512, // 1024 byte, double buffer + [2] = 256, // 1024 byte + [3] = 512, // 1024 byte, double buffer + [4] = 256, // 1024 byte + [5] = 256, // 1024 byte + [6] = 256, // 1024 byte + [7] = 0, + [8] = 0, + [9] = 0, + [10] = 0, + [11] = 0, + [12] = 0, + [13] = 0, + [14] = 0, + [15] = 0 }, + + .host_dma_desc_enable = false, + .host_rx_fifo_size = 3016 - 128 * 2 - 256 * 2, + .host_nperio_tx_fifo_size = 128 * 2, // 512 byte, double buffer + .host_perio_tx_fifo_size = 256 * 2, // 1024 byte, double buffer + + .device_gccfg = 0, + .host_gccfg = 0 +}; + +#ifndef CONFIG_USB_DWC2_CUSTOM_PARAM +void dwc2_get_user_params(uint32_t reg_base, struct dwc2_user_params *params) +{ + memcpy(params, ¶m_common, sizeof(struct dwc2_user_params)); +#ifdef CONFIG_USB_DWC2_CUSTOM_FIFO + struct usb_dwc2_user_fifo_config s_dwc2_fifo_config; + + dwc2_get_user_fifo_config(reg_base, &s_dwc2_fifo_config); + + params->device_rx_fifo_size = s_dwc2_fifo_config.device_rx_fifo_size; + for (uint8_t i = 0; i < MAX_EPS_CHANNELS; i++) { + params->device_tx_fifo_size[i] = s_dwc2_fifo_config.device_tx_fifo_size[i]; + } +#endif +} +#endif + +// USB Host +#if defined(ENABLE_CHERRY_USB_HOST) || defined(PKG_CHERRYUSB_HOST) || defined(RT_CHERRYUSB_HOST) +static void usb_hc_interrupt_cb(int irq, void *arg_pv) +{ + USBH_IRQHandler((uint8_t)(uintptr_t)arg_pv); +} + +void usb_hc_low_level_init(struct usbh_bus *bus) +{ + uint32_t *hs_reg; + uint32_t usb_ctl3; + + if ((uintptr_t)rt_hw_mmu_v2p(&mmu_info, (void *)bus->hcd.reg_base) == usb_dev_addr[0]) { + if (!sysctl_reset(SYSCTL_RESET_USB0)) { + USB_LOG_ERR("reset usb0 fail\n"); + } + + hs_reg = (uint32_t *)rt_ioremap((void *)(0x91585000 + 0x7C), 0x1000); + usb_ctl3 = *hs_reg | USB_IDPULLUP0; + + *hs_reg = usb_ctl3 | (USB_DMPULLDOWN0 | USB_DPPULLDOWN0); + + rt_iounmap(hs_reg); + + rt_hw_interrupt_install(173, usb_hc_interrupt_cb, (void *)(uintptr_t)bus->hcd.hcd_id, "usbh0"); + rt_hw_interrupt_umask(173); + + } else { + if (!sysctl_reset(SYSCTL_RESET_USB1)) { + USB_LOG_ERR("reset usb1 fail\n"); + } + + hs_reg = (uint32_t *)rt_ioremap((void *)(0x91585000 + 0x9C), 0x1000); + usb_ctl3 = *hs_reg | USB_IDPULLUP0; + + *hs_reg = usb_ctl3 | (USB_DMPULLDOWN0 | USB_DPPULLDOWN0); + + rt_iounmap(hs_reg); + + rt_hw_interrupt_install(174, usb_hc_interrupt_cb, (void *)(uintptr_t)bus->hcd.hcd_id, "usbh1"); + rt_hw_interrupt_umask(174); + } +} + +void usb_hc_low_level_deinit(struct usbh_bus *bus) +{ + if ((uintptr_t)rt_hw_mmu_v2p(&mmu_info, (void *)bus->hcd.reg_base) == usb_dev_addr[0]) { + rt_hw_interrupt_mask(173); + } else { + rt_hw_interrupt_mask(174); + } +} +#endif // ENABLE_CHERRY_USB_HOST + +// USB Device +#if defined(ENABLE_CHERRY_USB_DEVICE) || defined(PKG_CHERRYUSB_DEVICE) || defined(RT_CHERRYUSB_DEVICE) +static void usb_dc_interrupt_cb(int irq, void *arg_pv) +{ + USBD_IRQHandler((uint8_t)(uintptr_t)arg_pv); +} + +void usb_dc_low_level_init(uint8_t busid) +{ + if ((uintptr_t)rt_hw_mmu_v2p(&mmu_info, (void *)g_usbdev_bus[busid].reg_base) == usb_dev_addr[0]) { + if (!sysctl_reset(SYSCTL_RESET_USB0)) { + USB_LOG_ERR("reset usb0 fail\n"); + } + + uint32_t *hs_reg = (uint32_t *)rt_ioremap((void *)(0x91585000 + 0x7C), 0x1000); + *hs_reg = 0x37; + rt_iounmap(hs_reg); + + rt_hw_interrupt_install(173, usb_dc_interrupt_cb, (void *)(uintptr_t)busid, "usbd0"); + rt_hw_interrupt_umask(173); + } else { + if (!sysctl_reset(SYSCTL_RESET_USB1)) { + USB_LOG_ERR("reset usb1 fail\n"); + } + + uint32_t *hs_reg = (uint32_t *)rt_ioremap((void *)(0x91585000 + 0x9C), 0x1000); + *hs_reg = 0x37; + rt_iounmap(hs_reg); + + rt_hw_interrupt_install(174, usb_dc_interrupt_cb, (void *)(uintptr_t)busid, "usbd1"); + rt_hw_interrupt_umask(174); + } +} + +void usb_dc_low_level_deinit(uint8_t busid) +{ + if ((uintptr_t)rt_hw_mmu_v2p(&mmu_info, (void *)g_usbdev_bus[busid].reg_base) == usb_dev_addr[0]) { + rt_hw_interrupt_mask(173); + } else { + rt_hw_interrupt_mask(174); + } +} +#endif // ENABLE_CHERRY_USB_DEVICE + +void usbd_dwc2_delay_ms(uint8_t ms) +{ + rt_thread_mdelay(ms); +} + +uint32_t usbd_dwc2_get_system_clock(void) +{ + return SystemCoreClock; +} + +#ifdef CONFIG_USB_DCACHE_ENABLE +void usb_dcache_clean(uintptr_t addr, size_t size) +{ + rt_hw_cpu_dcache_clean((void *)addr, size); +} + +void usb_dcache_invalidate(uintptr_t addr, size_t size) +{ + rt_hw_cpu_dcache_invalidate((void *)addr, size); +} + +void usb_dcache_flush(uintptr_t addr, size_t size) +{ + rt_hw_cpu_dcache_clean_flush((void *)addr, size); +} +#endif + +#endif // ENABLE_CHERRY_USB diff --git a/kernel/cherryusb/port/dwc2/usb_glue_nation.c b/kernel/cherryusb/port/dwc2/usb_glue_nation.c new file mode 100644 index 0000000..3e96b22 --- /dev/null +++ b/kernel/cherryusb/port/dwc2/usb_glue_nation.c @@ -0,0 +1,193 @@ +/* + * Copyright (c) 2025, sakumisu + * + * SPDX-License-Identifier: Apache-2.0 + */ +#include "usbd_core.h" +#include "usbh_core.h" + +__WEAK void USBD_IRQHandler(uint8_t busid) +{ +} + +__WEAK void USBH_IRQHandler(uint8_t busid) +{ +} + +#if defined(N32H473) || defined(N32H474) || defined(N32H475) || defined(N32H482) || defined(N32H487) +#include "n32h47x_48x_rcc.h" +#include "n32h47x_48x_gpio.h" +#include "n32h47x_48x_exti.h" +#include "misc.h" + +typedef void (*usb_dwc2_irq)(uint8_t busid); + +static usb_dwc2_irq g_usb_dwc2_irq; +static volatile uint8_t g_usb_dwc2_busid = 0; + +static void usbhs_common_init(void) +{ + RCC_EnableAHB1PeriphClk(RCC_AHB_PERIPHEN_GPIOA | RCC_AHB_PERIPHEN_GPIOB, ENABLE); + RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPH_AFIO, ENABLE); + /* PLL= 240MHz */ +#if (HSE_VALUE == 8000000) + /* Select PLL clock as USBHS clock source , clock 15 divisions = 16M */ + RCC_ConfigUSBPLLPresClk(RCC_USBPLLCLK_SRC_PLL, RCC_USBPLLCLK_DIV15); + + /* Select the corresponding bandwidth and frequency*/ + RCC_ConfigUSBHSBandwidth(RCC_USBHS_BW_16M); + + /* Select USBHS clock source frequency */ + RCC_ConfigUSBHSFrequency(RCC_USBHS_FREQ_16_OR_32M); + + /* Select PLL as USBHS clock */ + RCC_ConfigUSBHSClk(RCC_USBHS_CLKSRC_PLLPRES); +#else //HSE 16M + RCC_ConfigUSBHSBandwidth(RCC_USBHS_BW_16M); + RCC_ConfigUSBHSFrequency(RCC_USBHS_FREQ_16_OR_32M); + RCC_ConfigUSBHSClk(RCC_USBHS_CLKSRC_HSE); +#endif + /* Reset the USBHS phy clock*/ + RCC_EnableAHBPeriphReset(RCC_AHBPRST_USBHSPHYRST); + /* Enables the USBHS peripheral clock*/ + RCC_EnableAHBPeriphClk(RCC_AHB_PERIPHEN_USBHS, ENABLE); + + NVIC_InitType NVIC_InitStructure; + // EXTI_InitType EXTI_InitStructure; + + // NVIC_InitStructure.NVIC_IRQChannel = USB_HS_WKUP_IRQn; + // NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0; + // NVIC_InitStructure.NVIC_IRQChannelSubPriority = 1; + // NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE; + // NVIC_Init(&NVIC_InitStructure); + + NVIC_InitStructure.NVIC_IRQChannel = USB_HS_IRQn; + NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 1; + NVIC_InitStructure.NVIC_IRQChannelSubPriority = 3; + NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE; + NVIC_Init(&NVIC_InitStructure); + + /* Configure the EXTI line 23 connected internally to the USBHS IP */ + // EXTI_ClrITPendBit(EXTI_LINE23); + // EXTI_InitStructure.EXTI_Line = EXTI_LINE23; + // EXTI_InitStructure.EXTI_Mode = EXTI_Mode_Interrupt; + // EXTI_InitStructure.EXTI_Trigger = EXTI_Trigger_Rising; + // EXTI_InitStructure.EXTI_LineCmd = ENABLE; + // EXTI_InitPeripheral(&EXTI_InitStructure); +} + +static void usbhs_gpio_init(void) +{ + GPIO_InitType GPIO_InitStructure; + + RCC_EnableAHB1PeriphClk(RCC_AHB_PERIPHEN_GPIOA | RCC_AHB_PERIPHEN_GPIOB | RCC_AHB_PERIPHEN_GPIOE, ENABLE); + RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPH_AFIO, ENABLE); + GPIO_ConfigPinRemap(0, 0, GPIO_RMP_SWJ_SWD); + + GPIO_InitStruct(&GPIO_InitStructure); +#ifdef USBHS_HOST + GPIO_InitStructure.Pin = GPIO_PIN_1; + GPIO_InitStructure.GPIO_Mode = GPIO_MODE_OUTPUT_PP; + GPIO_InitPeripheral(GPIOE, &GPIO_InitStructure); + GPIO_ResetBits(GPIOE, GPIO_PIN_1); + + GPIO_InitStructure.Pin = GPIO_PIN_3; + GPIO_InitPeripheral(GPIOB, &GPIO_InitStructure); + GPIO_ResetBits(GPIOB, GPIO_PIN_3); +#endif + // VBUS + // GPIO_InitStructure.Pin = GPIO_PIN_13; + // GPIO_InitStructure.GPIO_Mode = GPIO_MODE_INPUT; + // GPIO_InitPeripheral(GPIOB, &GPIO_InitStructure); + + // // SOF + // GPIO_InitStructure.Pin = GPIO_PIN_4; + // GPIO_InitStructure.GPIO_Mode = GPIO_MODE_AF_PP; + // GPIO_InitStructure.GPIO_Alternate = 8; // SOF + // GPIO_InitPeripheral(GPIOA, &GPIO_InitStructure); + + // // ID + // GPIO_InitStructure.Pin = GPIO_PIN_12; + // GPIO_InitStructure.GPIO_Mode = GPIO_MODE_AF_PP; + // GPIO_InitStructure.GPIO_Alternate = 14; // ID + // GPIO_InitPeripheral(GPIOB, &GPIO_InitStructure); +} + +void usb_dc_low_level_init(uint8_t busid) +{ + g_usb_dwc2_irq = USBD_IRQHandler; + g_usb_dwc2_busid = busid; + + usbhs_common_init(); + + RCC->USBHSCTRL2 |= (uint32_t)0x01 << 19; + RCC->USBHSCTRL1 |= (uint32_t)0x01 << 31; +} + +void usb_dc_low_level_deinit(uint8_t busid) +{ + NVIC_InitType NVIC_InitStructure; + + NVIC_InitStructure.NVIC_IRQChannel = USB_HS_IRQn; + NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 1; + NVIC_InitStructure.NVIC_IRQChannelSubPriority = 3; + NVIC_InitStructure.NVIC_IRQChannelCmd = DISABLE; + NVIC_Init(&NVIC_InitStructure); + + RCC_EnableAHBPeriphReset(RCC_AHBPRST_USBHSPHYRST); + /* Enables the USBHS peripheral clock*/ + RCC_EnableAHBPeriphClk(RCC_AHB_PERIPHEN_USBHS, DISABLE); +} + +void usb_hc_low_level_init(struct usbh_bus *bus) +{ + g_usb_dwc2_irq = USBH_IRQHandler; + g_usb_dwc2_busid = 0; + + usbhs_common_init(); + + RCC->USBHSCTRL2 &= ~(uint32_t)0x01 << 19; + RCC->USBHSCTRL1 |= (uint32_t)0x01 << 31; +} + +void usb_hc_low_level_deinit(struct usbh_bus *bus) +{ + NVIC_InitType NVIC_InitStructure; + + NVIC_InitStructure.NVIC_IRQChannel = USB_HS_IRQn; + NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 1; + NVIC_InitStructure.NVIC_IRQChannelSubPriority = 3; + NVIC_InitStructure.NVIC_IRQChannelCmd = DISABLE; + NVIC_Init(&NVIC_InitStructure); + + RCC_EnableAHBPeriphReset(RCC_AHBPRST_USBHSPHYRST); + /* Enables the USBHS peripheral clock*/ + RCC_EnableAHBPeriphClk(RCC_AHB_PERIPHEN_USBHS, DISABLE); +} + +uint32_t usbd_get_dwc2_gccfg_conf(uint32_t reg_base) +{ + return 0; +} + +uint32_t usbh_get_dwc2_gccfg_conf(uint32_t reg_base) +{ + return 0; +} + +void USB_HS_IRQHandler(void) +{ + g_usb_dwc2_irq(g_usb_dwc2_busid); +} + +extern uint32_t SystemCoreClock; + +void usbd_dwc2_delay_ms(uint8_t ms) +{ + uint32_t count = SystemCoreClock / 1000 * ms; + while (count--) { + __asm volatile("nop"); + } +} + +#endif diff --git a/kernel/cherryusb/port/dwc2/usb_glue_st.c b/kernel/cherryusb/port/dwc2/usb_glue_st.c new file mode 100644 index 0000000..b766ca4 --- /dev/null +++ b/kernel/cherryusb/port/dwc2/usb_glue_st.c @@ -0,0 +1,755 @@ +/* + * Copyright (c) 2024, sakumisu + * + * SPDX-License-Identifier: Apache-2.0 + */ +#include "usbd_core.h" +#include "usbh_core.h" +#include "usb_dwc2_param.h" + +#ifndef CONFIG_USB_DWC2_CUSTOM_PARAM + +#if __has_include("stm32f1xx_hal.h") +#include "stm32f1xx_hal.h" + +const struct dwc2_user_params param_pa11_pa12 = { + .phy_type = DWC2_PHY_TYPE_PARAM_FS, + .device_dma_enable = false, + .device_dma_desc_enable = false, + .device_rx_fifo_size = (320 - 16 - 64 - 16 - 16), + .device_tx_fifo_size = { + [0] = 16, // 64 byte + [1] = 64, // 256 byte + [2] = 16, // 64 byte + [3] = 16, // 64 byte + [4] = 0, + [5] = 0, + [6] = 0, + [7] = 0, + [8] = 0, + [9] = 0, + [10] = 0, + [11] = 0, + [12] = 0, + [13] = 0, + [14] = 0, + [15] = 0 }, + + .device_gccfg = ((1 << 16) | (1 << 21)), // fs: USB_OTG_GCCFG_PWRDWN | USB_OTG_GCCFG_NOVBUSSENS + .total_fifo_size = 320 // 1280 byte +}; + +const struct dwc2_user_params param_pb14_pb15 = { 0 }; // do not support +#if defined(HAL_HCD_MODULE_ENABLED) +#error "HAL_HCD_MODULE_ENABLED is not supported for STM32F1xx, please use HAL_PCD_MODULE_ENABLED" +#endif +#elif __has_include("stm32f2xx_hal.h") +#include "stm32f2xx_hal.h" + +const struct dwc2_user_params param_pa11_pa12 = { + .phy_type = DWC2_PHY_TYPE_PARAM_FS, + .device_dma_enable = false, + .device_dma_desc_enable = false, + .device_rx_fifo_size = (320 - 16 - 64 - 16 - 16), + .device_tx_fifo_size = { + [0] = 16, // 64 byte + [1] = 64, // 256 byte + [2] = 16, // 64 byte + [3] = 16, // 64 byte + [4] = 0, + [5] = 0, + [6] = 0, + [7] = 0, + [8] = 0, + [9] = 0, + [10] = 0, + [11] = 0, + [12] = 0, + [13] = 0, + [14] = 0, + [15] = 0 }, + + .device_gccfg = ((1 << 16) | (1 << 21)), // fs: USB_OTG_GCCFG_PWRDWN | USB_OTG_GCCFG_NOVBUSSENS + .total_fifo_size = 320 // 1280 byte +}; + +const struct dwc2_user_params param_pb14_pb15 = { +#ifdef CONFIG_USB_HS + .phy_type = DWC2_PHY_TYPE_PARAM_UTMI, +#else + .phy_type = DWC2_PHY_TYPE_PARAM_FS, +#endif +#ifdef CONFIG_USB_DWC2_DMA_ENABLE + .device_dma_enable = true, +#else + .device_dma_enable = false, +#endif + .device_dma_desc_enable = false, + .device_rx_fifo_size = (1012 - 16 - 256 - 128 - 128 - 128 - 128), + .device_tx_fifo_size = { + [0] = 16, // 64 byte + [1] = 256, // 1024 byte + [2] = 128, // 512 byte + [3] = 128, // 512 byte + [4] = 128, // 512 byte + [5] = 128, // 512 byte + [6] = 0, + [7] = 0, + [8] = 0, + [9] = 0, + [10] = 0, + [11] = 0, + [12] = 0, + [13] = 0, + [14] = 0, + [15] = 0 }, + + .host_dma_desc_enable = false, + .host_rx_fifo_size = 628, + .host_nperio_tx_fifo_size = 128, // 512 byte + .host_perio_tx_fifo_size = 256, // 1024 byte + +#ifdef CONFIG_USB_HS + .device_gccfg = 0, + .host_gccfg = 0, +#else + .device_gccfg = ((1 << 16) | (1 << 21)), // fs: USB_OTG_GCCFG_PWRDWN | USB_OTG_GCCFG_NOVBUSSENS hs:0 + .host_gccfg = ((1 << 16) | (1 << 21)) // fs: USB_OTG_GCCFG_PWRDWN | USB_OTG_GCCFG_NOVBUSSENS hs:0 +#endif +}; +#elif __has_include("stm32f4xx_hal.h") +#include "stm32f4xx_hal.h" + +const struct dwc2_user_params param_pa11_pa12 = { + .phy_type = DWC2_PHY_TYPE_PARAM_FS, + .device_dma_enable = false, + .device_dma_desc_enable = false, + .device_rx_fifo_size = (320 - 16 - 64 - 16 - 16), + .device_tx_fifo_size = { + [0] = 16, // 64 byte + [1] = 64, // 256 byte + [2] = 16, // 64 byte + [3] = 16, // 64 byte + [4] = 0, + [5] = 0, + [6] = 0, + [7] = 0, + [8] = 0, + [9] = 0, + [10] = 0, + [11] = 0, + [12] = 0, + [13] = 0, + [14] = 0, + [15] = 0 }, + +#if defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || \ + defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || \ + defined(STM32F423xx) + .device_gccfg = (1 << 16), // fs: USB_OTG_GCCFG_PWRDWN + .b_session_valid_override = true, +#else + .device_gccfg = ((1 << 16) | (1 << 21)), // fs: USB_OTG_GCCFG_PWRDWN | USB_OTG_GCCFG_NOVBUSSENS +#endif + .total_fifo_size = 320 // 1280 byte +}; + +const struct dwc2_user_params param_pb14_pb15 = { +#ifdef CONFIG_USB_HS + .phy_type = DWC2_PHY_TYPE_PARAM_UTMI, +#else + .phy_type = DWC2_PHY_TYPE_PARAM_FS, +#endif +#ifdef CONFIG_USB_DWC2_DMA_ENABLE + .device_dma_enable = true, +#else + .device_dma_enable = false, +#endif + .device_dma_desc_enable = false, + .device_rx_fifo_size = (1006 - 16 - 256 - 128 - 128 - 128 - 128), // 1006/1012 + .device_tx_fifo_size = { + [0] = 16, // 64 byte + [1] = 256, // 1024 byte + [2] = 128, // 512 byte + [3] = 128, // 512 byte + [4] = 128, // 512 byte + [5] = 128, // 512 byte + [6] = 0, + [7] = 0, + [8] = 0, + [9] = 0, + [10] = 0, + [11] = 0, + [12] = 0, + [13] = 0, + [14] = 0, + [15] = 0 }, + + .host_dma_desc_enable = false, + .host_rx_fifo_size = 622, + .host_nperio_tx_fifo_size = 128, // 512 byte + .host_perio_tx_fifo_size = 256, // 1024 byte +#ifdef CONFIG_USB_HS + .device_gccfg = 0, + .host_gccfg = 0, +#else +#if defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || \ + defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || \ + defined(STM32F423xx) + .device_gccfg = (1 << 16), // fs: USB_OTG_GCCFG_PWRDWN + .host_gccfg = (1 << 16), // fs: USB_OTG_GCCFG_PWRDWN + .b_session_valid_override = true, +#else + .device_gccfg = ((1 << 16) | (1 << 21)), // fs: USB_OTG_GCCFG_PWRDWN | USB_OTG_GCCFG_NOVBUSSENS hs:0 + .host_gccfg = ((1 << 16) | (1 << 21)) // fs: USB_OTG_GCCFG_PWRDWN | USB_OTG_GCCFG_NOVBUSSENS hs:0 +#endif +#endif +}; +#elif __has_include("stm32f7xx_hal.h") +#include "stm32f7xx_hal.h" + +const struct dwc2_user_params param_pa11_pa12 = { + .phy_type = DWC2_PHY_TYPE_PARAM_FS, + .device_dma_enable = false, + .device_dma_desc_enable = false, + .device_rx_fifo_size = (320 - 16 - 64 - 16 - 16), + .device_tx_fifo_size = { + [0] = 16, // 64 byte + [1] = 64, // 256 byte + [2] = 16, // 64 byte + [3] = 16, // 64 byte + [4] = 0, + [5] = 0, + [6] = 0, + [7] = 0, + [8] = 0, + [9] = 0, + [10] = 0, + [11] = 0, + [12] = 0, + [13] = 0, + [14] = 0, + [15] = 0 }, + + .device_gccfg = (1 << 16), // fs: USB_OTG_GCCFG_PWRDWN + .host_gccfg = (1 << 16), // fs: USB_OTG_GCCFG_PWRDWN + + .b_session_valid_override = true, + .total_fifo_size = 320 // 1280 byte +}; + +const struct dwc2_user_params param_pb14_pb15 = { +#if defined(STM32F722xx) || defined(STM32F723xx) || defined(STM32F730xx) || defined(STM32F732xx) || defined(STM32F733xx) + .phy_type = DWC2_PHY_TYPE_PARAM_UTMI, +#else + .phy_type = DWC2_PHY_TYPE_PARAM_FS, +#endif +#ifdef CONFIG_USB_DWC2_DMA_ENABLE + .device_dma_enable = true, +#else + .device_dma_enable = false, +#endif + .device_dma_desc_enable = false, + .device_rx_fifo_size = (1006 - 16 - 256 - 128 - 128 - 128 - 128), + .device_tx_fifo_size = { + [0] = 16, // 64 byte + [1] = 256, // 1024 byte + [2] = 128, // 512 byte + [3] = 128, // 512 byte + [4] = 128, // 512 byte + [5] = 128, // 512 byte + [6] = 0, + [7] = 0, + [8] = 0, + [9] = 0, + [10] = 0, + [11] = 0, + [12] = 0, + [13] = 0, + [14] = 0, + [15] = 0 }, + + .host_dma_desc_enable = false, + .host_rx_fifo_size = 622, + .host_nperio_tx_fifo_size = 128, // 512 byte + .host_perio_tx_fifo_size = 256, // 1024 byte +#if defined(STM32F722xx) || defined(STM32F723xx) || defined(STM32F730xx) || defined(STM32F732xx) || defined(STM32F733xx) + .device_gccfg = (1 << 23), // USB_OTG_GCCFG_PHYHSEN + .host_gccfg = (1 << 23), // USB_OTG_GCCFG_PHYHSEN +#else +#ifdef CONFIG_USB_HS + .device_gccfg = 0, + .host_gccfg = 0, +#else + .device_gccfg = (1 << 16), // fs: USB_OTG_GCCFG_PWRDWN hs:0 + .host_gccfg = (1 << 16), // fs: USB_OTG_GCCFG_PWRDWN hs:0 +#endif +#endif + .b_session_valid_override = true +}; +#elif __has_include("stm32h7xx_hal.h") +#include "stm32h7xx_hal.h" + +const struct dwc2_user_params param_pa11_pa12 = { + .phy_type = DWC2_PHY_TYPE_PARAM_FS, // DWC2_PHY_TYPE_PARAM_UTMI +#ifdef CONFIG_USB_DWC2_DMA_ENABLE + .device_dma_enable = true, +#else + .device_dma_enable = false, +#endif + .device_dma_desc_enable = false, + .device_rx_fifo_size = (952 - 16 - 256 - 128 - 128 - 128 - 128), + .device_tx_fifo_size = { + [0] = 16, // 64 byte + [1] = 256, // 1024 byte + [2] = 128, // 512 byte + [3] = 128, // 512 byte + [4] = 128, // 512 byte + [5] = 128, // 512 byte + [6] = 0, + [7] = 0, + [8] = 0, + [9] = 0, + [10] = 0, + [11] = 0, + [12] = 0, + [13] = 0, + [14] = 0, + [15] = 0 }, + + .host_dma_desc_enable = false, + .host_rx_fifo_size = 568, + .host_nperio_tx_fifo_size = 128, // 512 byte + .host_perio_tx_fifo_size = 256, // 1024 byte + + .device_gccfg = (1 << 16), // fs: USB_OTG_GCCFG_PWRDWN hs:0 + .host_gccfg = (1 << 16), // fs: USB_OTG_GCCFG_PWRDWN hs:0 + + .b_session_valid_override = true +}; + +const struct dwc2_user_params param_pb14_pb15 = { +#ifdef CONFIG_USB_HS + .phy_type = DWC2_PHY_TYPE_PARAM_UTMI, +#else + .phy_type = DWC2_PHY_TYPE_PARAM_FS, +#endif +#ifdef CONFIG_USB_DWC2_DMA_ENABLE + .device_dma_enable = true, +#else + .device_dma_enable = false, +#endif + .device_dma_desc_enable = false, + .device_rx_fifo_size = (952 - 16 - 256 - 128 - 128 - 128 - 128), + .device_tx_fifo_size = { + [0] = 16, // 64 byte + [1] = 256, // 1024 byte + [2] = 128, // 512 byte + [3] = 128, // 512 byte + [4] = 128, // 512 byte + [5] = 128, // 512 byte + [6] = 0, + [7] = 0, + [8] = 0, + [9] = 0, + [10] = 0, + [11] = 0, + [12] = 0, + [13] = 0, + [14] = 0, + [15] = 0 }, + + .host_dma_desc_enable = false, + .host_rx_fifo_size = 568, + .host_nperio_tx_fifo_size = 128, // 512 byte + .host_perio_tx_fifo_size = 256, // 1024 byte + +#ifdef CONFIG_USB_HS + .device_gccfg = 0, + .host_gccfg = 0, +#else + .device_gccfg = (1 << 16), // fs: USB_OTG_GCCFG_PWRDWN hs:0 + .host_gccfg = (1 << 16), // fs: USB_OTG_GCCFG_PWRDWN hs:0 +#endif + .b_session_valid_override = true +}; +#elif __has_include("stm32h7rsxx_hal.h") +#include "stm32h7rsxx_hal.h" + +const struct dwc2_user_params param_pa11_pa12 = { + .phy_type = DWC2_PHY_TYPE_PARAM_FS, + .device_dma_enable = false, + .device_dma_desc_enable = false, + .device_rx_fifo_size = (320 - 16 - 64 - 16 - 16), + .device_tx_fifo_size = { + [0] = 16, // 64 byte + [1] = 64, // 256 byte + [2] = 16, // 64 byte + [3] = 16, // 64 byte + [4] = 0, + [5] = 0, + [6] = 0, + [7] = 0, + [8] = 0, + [9] = 0, + [10] = 0, + [11] = 0, + [12] = 0, + [13] = 0, + [14] = 0, + [15] = 0 }, + + .device_gccfg = (1 << 16), // fs: USB_OTG_GCCFG_PWRDWN + .b_session_valid_override = true, + .total_fifo_size = 320 // 1280 byte +}; + +const struct dwc2_user_params param_pb14_pb15 = { + .phy_type = DWC2_PHY_TYPE_PARAM_UTMI, +#ifdef CONFIG_USB_DWC2_DMA_ENABLE + .device_dma_enable = true, +#else + .device_dma_enable = false, +#endif + .device_dma_desc_enable = false, + .device_rx_fifo_size = (952 - 16 - 256 - 128 - 128 - 128 - 128), + .device_tx_fifo_size = { + [0] = 16, // 64 byte + [1] = 256, // 1024 byte + [2] = 128, // 512 byte + [3] = 128, // 512 byte + [4] = 128, // 512 byte + [5] = 128, // 512 byte + [6] = 0, + [7] = 0, + [8] = 0, + [9] = 0, + [10] = 0, + [11] = 0, + [12] = 0, + [13] = 0, + [14] = 0, + [15] = 0 }, + + .host_dma_desc_enable = false, + .host_rx_fifo_size = 568, + .host_nperio_tx_fifo_size = 128, // 512 byte + .host_perio_tx_fifo_size = 256, // 1024 byte + + .device_gccfg = ((1 << 23) | (1 << 24)), // hs: USB_OTG_GCCFG_VBVALEXTOEN | USB_OTG_GCCFG_VBVALOVAL + .host_gccfg = (1 << 25) // hs: USB_OTG_GCCFG_PULLDOWNEN +}; +#elif __has_include("stm32l4xx_hal.h") +#include "stm32l4xx_hal.h" + +const struct dwc2_user_params param_pa11_pa12 = { + .phy_type = DWC2_PHY_TYPE_PARAM_FS, + .device_dma_enable = false, + .device_dma_desc_enable = false, + .device_rx_fifo_size = (320 - 16 - 64 - 16 - 16), + .device_tx_fifo_size = { + [0] = 16, // 64 byte + [1] = 64, // 256 byte + [2] = 16, // 64 byte + [3] = 16, // 64 byte + [4] = 0, + [5] = 0, + [6] = 0, + [7] = 0, + [8] = 0, + [9] = 0, + [10] = 0, + [11] = 0, + [12] = 0, + [13] = 0, + [14] = 0, + [15] = 0 }, + + .device_gccfg = (1 << 16), + .b_session_valid_override = true, + .total_fifo_size = 320 // 1280 byte +}; + +const struct dwc2_user_params param_pb14_pb15 = { 0 }; // do not support +#if defined(HAL_HCD_MODULE_ENABLED) +#error "HAL_HCD_MODULE_ENABLED is not supported for STM32L4xx, please use HAL_PCD_MODULE_ENABLED" +#endif +#elif __has_include("stm32u5xx_hal.h") +#include "stm32u5xx_hal.h" + +const struct dwc2_user_params param_pa11_pa12 = { + .phy_type = DWC2_PHY_TYPE_PARAM_FS, + .device_dma_enable = false, + .device_dma_desc_enable = false, + .device_rx_fifo_size = (320 - 16 - 64 - 16 - 16), + .device_tx_fifo_size = { + [0] = 16, // 64 byte + [1] = 64, // 256 byte + [2] = 16, // 64 byte + [3] = 16, // 64 byte + [4] = 0, + [5] = 0, + [6] = 0, + [7] = 0, + [8] = 0, + [9] = 0, + [10] = 0, + [11] = 0, + [12] = 0, + [13] = 0, + [14] = 0, + [15] = 0 }, + + .device_gccfg = (1 << 16), + .b_session_valid_override = true, + .total_fifo_size = 320 // 1280 byte +}; + +#if defined(STM32U595xx) || defined(STM32U5A5xx) || defined(STM32U599xx) || defined(STM32U5A9xx) || \ + defined(STM32U5F7xx) || defined(STM32U5G7xx) || defined(STM32U5F9xx) || defined(STM32U5G9xx) +const struct dwc2_user_params param_pb14_pb15 = { + .phy_type = DWC2_PHY_TYPE_PARAM_UTMI, +#ifdef CONFIG_USB_DWC2_DMA_ENABLE + .device_dma_enable = true, +#else + .device_dma_enable = false, +#endif + .device_dma_desc_enable = false, + .device_rx_fifo_size = (952 - 16 - 256 - 128 - 128 - 128 - 128), + .device_tx_fifo_size = { + [0] = 16, // 64 byte + [1] = 256, // 1024 byte + [2] = 128, // 512 byte + [3] = 128, // 512 byte + [4] = 128, // 512 byte + [5] = 128, // 512 byte + [6] = 0, + [7] = 0, + [8] = 0, + [9] = 0, + [10] = 0, + [11] = 0, + [12] = 0, + [13] = 0, + [14] = 0, + [15] = 0 }, + + .host_dma_desc_enable = false, + .host_rx_fifo_size = 568, + .host_nperio_tx_fifo_size = 128, // 512 byte + .host_perio_tx_fifo_size = 256, // 1024 byte + + .device_gccfg = ((1 << 23) | (1 << 24)), // hs: USB_OTG_GCCFG_VBVALEXTOEN | USB_OTG_GCCFG_VBVALOVAL + .host_gccfg = (1 << 25) // hs: USB_OTG_GCCFG_PULLDOWNEN +}; +#else +const struct dwc2_user_params param_pb14_pb15 = { 0 }; // do not support +#endif +#endif + +#endif // CONFIG_USB_DWC2_CUSTOM_PARAM + +#if !defined(HAL_HCD_MODULE_ENABLED) && !defined(HAL_PCD_MODULE_ENABLED) +#error please define HAL_HCD_MODULE_ENABLED or HAL_PCD_MODULE_ENABLED in stm32xxx_hal_conf.h +#endif + +typedef void (*usb_dwc2_irq)(uint8_t busid); + +struct dwc2_instance { + USB_OTG_GlobalTypeDef *Instance; +}; + +static usb_dwc2_irq g_usb_dwc2_irq[2]; +static uint8_t g_usb_dwc2_busid[2] = { 0, 0 }; +static struct dwc2_instance g_dwc2_instance; + +#if defined(STM32F722xx) || defined(STM32F723xx) || defined(STM32F730xx) || defined(STM32F732xx) || defined(STM32F733xx) +/** + * @brief Enables control of a High Speed USB PHY + * Init the low level hardware : GPIO, CLOCK, NVIC... + * @param USBx Selected device + * @retval HAL status + */ +static int usb_hsphy_init(uint32_t hse_value) +{ + __IO uint32_t count = 0U; + + /* Enable LDO */ + USB_HS_PHYC->USB_HS_PHYC_LDO |= USB_HS_PHYC_LDO_ENABLE; + + /* wait for LDO Ready */ + while ((USB_HS_PHYC->USB_HS_PHYC_LDO & USB_HS_PHYC_LDO_STATUS) == 0U) { + count++; + + if (count > 200000U) { + return -1; + } + } + + /* Controls PHY frequency operation selection */ + if (hse_value == 12000000U) /* HSE = 12MHz */ + { + USB_HS_PHYC->USB_HS_PHYC_PLL = (0x0U << 1); + } else if (hse_value == 12500000U) /* HSE = 12.5MHz */ + { + USB_HS_PHYC->USB_HS_PHYC_PLL = (0x2U << 1); + } else if (hse_value == 16000000U) /* HSE = 16MHz */ + { + USB_HS_PHYC->USB_HS_PHYC_PLL = (0x3U << 1); + } else if (hse_value == 24000000U) /* HSE = 24MHz */ + { + USB_HS_PHYC->USB_HS_PHYC_PLL = (0x4U << 1); + } else if (hse_value == 25000000U) /* HSE = 25MHz */ + { + USB_HS_PHYC->USB_HS_PHYC_PLL = (0x5U << 1); + } else if (hse_value == 32000000U) /* HSE = 32MHz */ + { + USB_HS_PHYC->USB_HS_PHYC_PLL = (0x7U << 1); + } else { + /* ... */ + } + + /* Control the tuning interface of the High Speed PHY */ + USB_HS_PHYC->USB_HS_PHYC_TUNE |= USB_HS_PHYC_TUNE_VALUE; + + /* Enable PLL internal PHY */ + USB_HS_PHYC->USB_HS_PHYC_PLL |= USB_HS_PHYC_PLL_PLLEN; + + /* 2ms Delay required to get internal phy clock stable */ + HAL_Delay(2U); + + return 0; +} +#endif + +#ifdef HAL_PCD_MODULE_ENABLED +void usb_dc_low_level_init(uint8_t busid) +{ + if (g_usbdev_bus[busid].reg_base == 0x40040000UL) { // USB_OTG_HS_PERIPH_BASE + g_usb_dwc2_busid[1] = busid; + g_usb_dwc2_irq[1] = USBD_IRQHandler; + } else { + g_usb_dwc2_busid[0] = busid; + g_usb_dwc2_irq[0] = USBD_IRQHandler; + } + + g_dwc2_instance.Instance = (USB_OTG_GlobalTypeDef *)g_usbdev_bus[busid].reg_base; + HAL_PCD_MspInit((PCD_HandleTypeDef *)&g_dwc2_instance); + +#if defined(STM32F722xx) || defined(STM32F723xx) || defined(STM32F730xx) || defined(STM32F732xx) || defined(STM32F733xx) + usb_hsphy_init(25000000U); +#endif +} + +void usb_dc_low_level_deinit(uint8_t busid) +{ + if (g_usbdev_bus[busid].reg_base == 0x40040000UL) { // USB_OTG_HS_PERIPH_BASE + g_usb_dwc2_busid[1] = 0; + g_usb_dwc2_irq[1] = NULL; + } else { + g_usb_dwc2_busid[0] = 0; + g_usb_dwc2_irq[0] = NULL; + } + + g_dwc2_instance.Instance = (USB_OTG_GlobalTypeDef *)g_usbdev_bus[busid].reg_base; + HAL_PCD_MspDeInit((PCD_HandleTypeDef *)&g_dwc2_instance); +} +#endif + +#ifdef HAL_HCD_MODULE_ENABLED +void usb_hc_low_level_init(struct usbh_bus *bus) +{ + if (bus->hcd.reg_base == 0x40040000UL) { // USB_OTG_HS_PERIPH_BASE + g_usb_dwc2_busid[1] = bus->hcd.hcd_id; + g_usb_dwc2_irq[1] = USBH_IRQHandler; + } else { + g_usb_dwc2_busid[0] = bus->hcd.hcd_id; + g_usb_dwc2_irq[0] = USBH_IRQHandler; + } + + g_dwc2_instance.Instance = (USB_OTG_GlobalTypeDef *)bus->hcd.reg_base; + HAL_HCD_MspInit((HCD_HandleTypeDef *)&g_dwc2_instance); + +#if defined(STM32F722xx) || defined(STM32F723xx) || defined(STM32F730xx) || defined(STM32F732xx) || defined(STM32F733xx) + usb_hsphy_init(25000000U); +#endif +} + +void usb_hc_low_level_deinit(struct usbh_bus *bus) +{ + if (bus->hcd.reg_base == 0x40040000UL) { // USB_OTG_HS_PERIPH_BASE + g_usb_dwc2_busid[1] = 0; + g_usb_dwc2_irq[1] = NULL; + } else { + g_usb_dwc2_busid[0] = 0; + g_usb_dwc2_irq[0] = NULL; + } + + g_dwc2_instance.Instance = (USB_OTG_GlobalTypeDef *)bus->hcd.reg_base; + HAL_HCD_MspDeInit((HCD_HandleTypeDef *)&g_dwc2_instance); +} +#endif + +#ifndef CONFIG_USB_DWC2_CUSTOM_PARAM +void dwc2_get_user_params(uint32_t reg_base, struct dwc2_user_params *params) +{ + if (reg_base == 0x40040000UL) { // USB_OTG_HS_PERIPH_BASE + memcpy(params, ¶m_pb14_pb15, sizeof(struct dwc2_user_params)); + } else { + memcpy(params, ¶m_pa11_pa12, sizeof(struct dwc2_user_params)); + } +#ifdef CONFIG_USB_DWC2_CUSTOM_FIFO + struct usb_dwc2_user_fifo_config s_dwc2_fifo_config; + + dwc2_get_user_fifo_config(reg_base, &s_dwc2_fifo_config); + + params->device_rx_fifo_size = s_dwc2_fifo_config.device_rx_fifo_size; + for (uint8_t i = 0; i < MAX_EPS_CHANNELS; i++) + { + params->device_tx_fifo_size[i] = s_dwc2_fifo_config.device_tx_fifo_size[i]; + } +#endif +} +#endif + +extern uint32_t SystemCoreClock; + +void usbd_dwc2_delay_ms(uint8_t ms) +{ + uint32_t count = SystemCoreClock / 1000 * ms; + while (count--) { + __asm volatile("nop"); + } +} + +uint32_t usbd_dwc2_get_system_clock(void) +{ + return SystemCoreClock; +} + +void OTG_FS_IRQHandler(void) +{ + g_usb_dwc2_irq[0](g_usb_dwc2_busid[0]); +} + +void OTG_HS_IRQHandler(void) +{ + g_usb_dwc2_irq[1](g_usb_dwc2_busid[1]); +} + +#ifdef CONFIG_USB_DCACHE_ENABLE +void usb_dcache_clean(uintptr_t addr, size_t size) +{ + SCB_CleanDCache_by_Addr((void *)addr, size); +} + +void usb_dcache_invalidate(uintptr_t addr, size_t size) +{ + SCB_InvalidateDCache_by_Addr((void *)addr, size); +} + +void usb_dcache_flush(uintptr_t addr, size_t size) +{ + SCB_CleanInvalidateDCache_by_Addr((void *)addr, size); +} +#endif \ No newline at end of file diff --git a/kernel/cherryusb/port/dwc2/usb_hc_dwc2.c b/kernel/cherryusb/port/dwc2/usb_hc_dwc2.c new file mode 100644 index 0000000..946dfd4 --- /dev/null +++ b/kernel/cherryusb/port/dwc2/usb_hc_dwc2.c @@ -0,0 +1,1553 @@ +/* + * Copyright (c) 2022, sakumisu + * + * SPDX-License-Identifier: Apache-2.0 + */ +#include "usbh_core.h" +#include "usbh_hub.h" +#include "usb_dwc2_reg.h" +#include "usb_dwc2_param.h" + +#define USB_OTG_GLB ((DWC2_GlobalTypeDef *)(bus->hcd.reg_base)) +#define USB_OTG_PCGCCTL *(__IO uint32_t *)((uint32_t)bus->hcd.reg_base + USB_OTG_PCGCCTL_BASE) +#define USB_OTG_HPRT *(__IO uint32_t *)((uint32_t)bus->hcd.reg_base + USB_OTG_HOST_PORT_BASE) +#define USB_OTG_HOST ((DWC2_HostTypeDef *)(bus->hcd.reg_base + USB_OTG_HOST_BASE)) +#define USB_OTG_HC(i) ((DWC2_HostChannelTypeDef *)(bus->hcd.reg_base + USB_OTG_HOST_CHANNEL_BASE + ((i)*USB_OTG_HOST_CHANNEL_SIZE))) + +struct dwc2_chan { + uint8_t ep0_state; + uint16_t num_packets; + uint32_t xferlen; + uint8_t chidx; + bool inuse; + bool do_ssplit; + bool do_csplit; + uint8_t hub_addr; + uint8_t hub_port; + uint16_t ssplit_frame; + usb_osal_sem_t waitsem; + struct usbh_urb *urb; + uint32_t iso_frame_idx; +}; + +struct dwc2_hcd { + volatile bool port_csc; + volatile bool port_pec; + volatile bool port_occ; + struct dwc2_hw_params hw_params; + struct dwc2_user_params user_params; + struct dwc2_chan chan_pool[16]; +} g_dwc2_hcd[CONFIG_USBHOST_MAX_BUS]; + +#define DWC2_EP0_STATE_SETUP 0 +#define DWC2_EP0_STATE_INDATA 1 +#define DWC2_EP0_STATE_OUTDATA 2 +#define DWC2_EP0_STATE_INSTATUS 3 +#define DWC2_EP0_STATE_OUTSTATUS 4 + +static inline int dwc2_reset(struct usbh_bus *bus) +{ + volatile uint32_t count = 0U; + + /* Wait for AHB master IDLE state. */ + do { + if (++count > 200000U) { + return -1; + } + } while ((USB_OTG_GLB->GRSTCTL & USB_OTG_GRSTCTL_AHBIDL) == 0U); + + /* Core Soft Reset */ + count = 0U; + USB_OTG_GLB->GRSTCTL |= USB_OTG_GRSTCTL_CSRST; + + if (g_dwc2_hcd[bus->hcd.hcd_id].hw_params.snpsid < 0x4F54420AU) { + do { + if (++count > 200000U) { + USB_LOG_ERR("DWC2 reset timeout\r\n"); + return -1; + } + } while ((USB_OTG_GLB->GRSTCTL & USB_OTG_GRSTCTL_CSRST) == USB_OTG_GRSTCTL_CSRST); + } else { + do { + if (++count > 200000U) { + USB_LOG_ERR("DWC2 reset timeout\r\n"); + return -1; + } + } while ((USB_OTG_GLB->GRSTCTL & USB_OTG_GRSTCTL_CSRSTDONE) != USB_OTG_GRSTCTL_CSRSTDONE); + + USB_OTG_GLB->GRSTCTL &= ~USB_OTG_GRSTCTL_CSRST; + USB_OTG_GLB->GRSTCTL |= USB_OTG_GRSTCTL_CSRSTDONE; + } + + return 0; +} + +static inline int dwc2_core_init(struct usbh_bus *bus) +{ + int ret; + uint32_t regval; + + if (g_dwc2_hcd[bus->hcd.hcd_id].user_params.phy_type == DWC2_PHY_TYPE_PARAM_FS) { + /* Select FS Embedded PHY */ + USB_OTG_GLB->GUSBCFG |= USB_OTG_GUSBCFG_PHYSEL; + } else { + regval = USB_OTG_GLB->GUSBCFG; + regval &= ~USB_OTG_GUSBCFG_PHYSEL; + /* disable external vbus source */ + regval &= ~(USB_OTG_GUSBCFG_ULPIEVBUSD | USB_OTG_GUSBCFG_ULPIEVBUSI); + /* disable ULPI FS/LS */ + regval &= ~(USB_OTG_GUSBCFG_ULPIFSLS | USB_OTG_GUSBCFG_ULPICSM); + + switch (g_dwc2_hcd[bus->hcd.hcd_id].user_params.phy_type) { + case DWC2_PHY_TYPE_PARAM_ULPI: + regval |= USB_OTG_GUSBCFG_ULPI_UTMI_SEL; + regval &= ~USB_OTG_GUSBCFG_PHYIF16; + regval &= ~USB_OTG_GUSBCFG_DDR_SEL; + + break; + case DWC2_PHY_TYPE_PARAM_UTMI: + regval &= ~USB_OTG_GUSBCFG_ULPI_UTMI_SEL; + regval &= ~USB_OTG_GUSBCFG_PHYIF16; + + if (g_dwc2_hcd[bus->hcd.hcd_id].user_params.phy_utmi_width == 16) { + regval |= USB_OTG_GUSBCFG_PHYIF16; + } + break; + + default: + break; + } + USB_OTG_GLB->GUSBCFG = regval; + } + + /* Reset after a PHY select */ + ret = dwc2_reset(bus); + return ret; +} + +static inline void dwc2_set_mode(struct usbh_bus *bus, uint8_t mode) +{ + USB_OTG_GLB->GUSBCFG &= ~(USB_OTG_GUSBCFG_FHMOD | USB_OTG_GUSBCFG_FDMOD); + + if (mode == USB_OTG_MODE_HOST) { + USB_OTG_GLB->GUSBCFG |= USB_OTG_GUSBCFG_FHMOD; + } else if (mode == USB_OTG_MODE_DEVICE) { + USB_OTG_GLB->GUSBCFG |= USB_OTG_GUSBCFG_FDMOD; + } + + while (1) { + if ((USB_OTG_GLB->GINTSTS & 0x1U) == USB_OTG_MODE_HOST) { + break; + } + usb_osal_msleep(10); + } +} + +static inline int dwc2_flush_rxfifo(struct usbh_bus *bus) +{ + volatile uint32_t count = 0U; + + /* Wait for AHB master IDLE state. */ + do { + if (++count > 200000U) { + return -1; + } + } while ((USB_OTG_GLB->GRSTCTL & USB_OTG_GRSTCTL_AHBIDL) == 0U); + + count = 0; + USB_OTG_GLB->GRSTCTL = USB_OTG_GRSTCTL_RXFFLSH; + + do { + if (++count > 200000U) { + return -1; + } + } while ((USB_OTG_GLB->GRSTCTL & USB_OTG_GRSTCTL_RXFFLSH) == USB_OTG_GRSTCTL_RXFFLSH); + + return 0; +} + +static inline int dwc2_flush_txfifo(struct usbh_bus *bus, uint32_t num) +{ + volatile uint32_t count = 0U; + + /* Wait for AHB master IDLE state. */ + do { + if (++count > 200000U) { + return -1; + } + } while ((USB_OTG_GLB->GRSTCTL & USB_OTG_GRSTCTL_AHBIDL) == 0U); + + count = 0; + USB_OTG_GLB->GRSTCTL = (USB_OTG_GRSTCTL_TXFFLSH | (num << 6)); + + do { + if (++count > 200000U) { + return -1; + } + } while ((USB_OTG_GLB->GRSTCTL & USB_OTG_GRSTCTL_TXFFLSH) == USB_OTG_GRSTCTL_TXFFLSH); + + return 0; +} + +static inline void dwc2_drivebus(struct usbh_bus *bus, uint8_t state) +{ + __IO uint32_t hprt0 = 0U; + + hprt0 = USB_OTG_HPRT; + + hprt0 &= ~(USB_OTG_HPRT_PENA | USB_OTG_HPRT_PCDET | + USB_OTG_HPRT_PENCHNG | USB_OTG_HPRT_POCCHNG); + + if (((hprt0 & USB_OTG_HPRT_PPWR) == 0U) && (state == 1U)) { + USB_OTG_HPRT = (USB_OTG_HPRT_PPWR | hprt0); + } + if (((hprt0 & USB_OTG_HPRT_PPWR) == USB_OTG_HPRT_PPWR) && (state == 0U)) { + USB_OTG_HPRT = ((~USB_OTG_HPRT_PPWR) & hprt0); + } +} + +static inline uint8_t usbh_get_port_speed(struct usbh_bus *bus, const uint8_t port) +{ + __IO uint32_t hprt0 = 0U; + uint8_t speed; + + hprt0 = USB_OTG_HPRT; + + speed = (hprt0 & USB_OTG_HPRT_PSPD) >> 17; + + if (speed == HPRT0_PRTSPD_HIGH_SPEED) { + return USB_SPEED_HIGH; + } else if (speed == HPRT0_PRTSPD_FULL_SPEED) { + return USB_SPEED_FULL; + } else if (speed == HPRT0_PRTSPD_LOW_SPEED) { + return USB_SPEED_LOW; + } else { + return USB_SPEED_UNKNOWN; + } +} + +static inline void dwc2_chan_char_init(struct usbh_bus *bus, + uint8_t ch_num, + uint8_t dev_addr, + uint8_t ep_addr, + uint8_t ep_type, + uint16_t ep_mps, + uint8_t ep_mult, + uint8_t speed) +{ + uint32_t regval; + + /* Program the HCCHAR register */ + regval = (((uint32_t)ep_mps << USB_OTG_HCCHAR_MPSIZ_Pos) & USB_OTG_HCCHAR_MPSIZ) | + ((((uint32_t)ep_addr & 0x7FU) << USB_OTG_HCCHAR_EPNUM_Pos) & USB_OTG_HCCHAR_EPNUM) | + (((uint32_t)ep_type << USB_OTG_HCCHAR_EPTYP_Pos) & USB_OTG_HCCHAR_EPTYP) | + (((uint32_t)ep_mult << USB_OTG_HCCHAR_MC_Pos) & USB_OTG_HCCHAR_MC) | + (((uint32_t)dev_addr << USB_OTG_HCCHAR_DAD_Pos) & USB_OTG_HCCHAR_DAD); + + if ((ep_addr & 0x80U) == 0x80U) { + regval |= USB_OTG_HCCHAR_EPDIR; + } + + /* LS device plugged to HUB */ + if ((speed == USB_SPEED_LOW) && (usbh_get_port_speed(bus, 0) != USB_SPEED_LOW)) { + regval |= USB_OTG_HCCHAR_LSDEV; + } + + if (ep_type == USB_ENDPOINT_TYPE_INTERRUPT) { + regval |= USB_OTG_HCCHAR_ODDFRM; + } + + USB_OTG_HC((uint32_t)ch_num)->HCCHAR = regval; +} + +static inline void dwc2_chan_splt_init(struct usbh_bus *bus, uint8_t ch_num) +{ + struct dwc2_chan *chan; + uint32_t hcsplt; + + chan = &g_dwc2_hcd[bus->hcd.hcd_id].chan_pool[ch_num]; + + if (chan->do_ssplit) { + hcsplt = USB_OTG_HCSPLT_SPLITEN; + hcsplt |= (chan->hub_addr << USB_OTG_HCSPLT_HUBADDR_Pos); + hcsplt |= chan->hub_port; + + if (chan->do_csplit) { + hcsplt |= USB_OTG_HCSPLT_COMPLSPLT; + } else { + hcsplt &= ~USB_OTG_HCSPLT_COMPLSPLT; + } + + USB_OTG_HC((uint32_t)ch_num)->HCSPLT = hcsplt; + } else { + USB_OTG_HC((uint32_t)ch_num)->HCSPLT = 0U; + } +} + +static void dwc2_chan_init(struct usbh_bus *bus, + uint8_t ch_num, + uint8_t dev_addr, + uint8_t ep_addr, + uint8_t ep_type, + uint16_t ep_mps, + uint8_t ep_mult, + uint8_t speed) +{ + USB_OTG_HC((uint32_t)ch_num)->HCINTMSK = 0U; + + /* Clear old interrupt conditions for this host channel. */ + USB_OTG_HC((uint32_t)ch_num)->HCINT = 0xFFFFFFFFU; + + /* Enable the top level host channel interrupt. */ + USB_OTG_HOST->HAINTMSK |= 1UL << (ch_num & 0xFU); + + dwc2_chan_char_init(bus, ch_num, dev_addr, ep_addr, ep_type, ep_mps, ep_mult, speed); + dwc2_chan_splt_init(bus, ch_num); +} + +static inline void dwc2_chan_transfer(struct usbh_bus *bus, uint8_t ch_num, uint8_t ep_addr, uint8_t *buf, uint32_t size, uint16_t num_packets, uint8_t pid) +{ + __IO uint32_t tmpreg; + uint8_t is_oddframe; + size_t flags; + + /* Initialize the HCTSIZn register */ + USB_OTG_HC(ch_num)->HCTSIZ = (size & USB_OTG_HCTSIZ_XFRSIZ) | + (((uint32_t)num_packets << 19) & USB_OTG_HCTSIZ_PKTCNT) | + (((uint32_t)pid << 29) & USB_OTG_HCTSIZ_DPID); + + /* xfer_buff MUST be 32-bits aligned */ + USB_OTG_HC(ch_num)->HCDMA = (uint32_t)buf; + + flags = usb_osal_enter_critical_section(); + + /* Enable channel interrupts required for this transfer. */ + USB_OTG_HC((uint32_t)ch_num)->HCINTMSK = USB_OTG_HCINTMSK_CHHM; + + is_oddframe = (((uint32_t)USB_OTG_HOST->HFNUM & 0x01U) != 0U) ? 0U : 1U; + USB_OTG_HC(ch_num)->HCCHAR &= ~USB_OTG_HCCHAR_ODDFRM; + USB_OTG_HC(ch_num)->HCCHAR |= (uint32_t)is_oddframe << 29; + + /* Set host channel enable */ + tmpreg = USB_OTG_HC(ch_num)->HCCHAR; + tmpreg &= ~USB_OTG_HCCHAR_CHDIS; + tmpreg |= USB_OTG_HCCHAR_CHENA; + USB_OTG_HC(ch_num)->HCCHAR = tmpreg; + + usb_osal_leave_critical_section(flags); +} + +static inline void dwc2_chan_enable_csplit(struct usbh_bus *bus, uint8_t ch_num, bool enable) +{ + if (enable) { + USB_OTG_HC((uint32_t)ch_num)->HCSPLT |= USB_OTG_HCSPLT_COMPLSPLT; + } else { + USB_OTG_HC((uint32_t)ch_num)->HCSPLT &= ~USB_OTG_HCSPLT_COMPLSPLT; + } +} + +static void dwc2_halt(struct usbh_bus *bus, uint8_t ch_num) +{ + volatile uint32_t ChannelEna = (USB_OTG_HC(ch_num)->HCCHAR & USB_OTG_HCCHAR_CHENA) >> 31; + volatile uint32_t count = 0U; + volatile uint32_t value; + + if (((USB_OTG_GLB->GAHBCFG & USB_OTG_GAHBCFG_DMAEN) == USB_OTG_GAHBCFG_DMAEN) && + (ChannelEna == 0U)) { + return; + } + + USB_OTG_HC(ch_num)->HCINTMSK = 0; + + value = USB_OTG_HC(ch_num)->HCCHAR; + value |= USB_OTG_HCCHAR_CHDIS; + value |= USB_OTG_HCCHAR_CHENA; + USB_OTG_HC(ch_num)->HCCHAR = value; + do { + if (++count > 200000U) { + break; + } + } while (USB_OTG_HC(ch_num)->HCCHAR & USB_OTG_HCCHAR_CHENA); + + USB_OTG_HC(ch_num)->HCINT = USB_OTG_HC(ch_num)->HCINT; +} + +static int usbh_reset_port(struct usbh_bus *bus, const uint8_t port) +{ + __IO uint32_t hprt0 = 0U; + volatile uint32_t timeout = 0; + + hprt0 = USB_OTG_HPRT; + + hprt0 &= ~(USB_OTG_HPRT_PENA | USB_OTG_HPRT_PCDET | + USB_OTG_HPRT_PENCHNG | USB_OTG_HPRT_POCCHNG); + + USB_OTG_HPRT = (USB_OTG_HPRT_PRST | hprt0); + usb_osal_msleep(100U); + USB_OTG_HPRT = ((~USB_OTG_HPRT_PRST) & hprt0); + usb_osal_msleep(10U); + + while (!(USB_OTG_HPRT & USB_OTG_HPRT_PENA)) { + if (!(USB_OTG_HPRT & USB_OTG_HPRT_PCSTS)) { + return -USB_ERR_NOTCONN; /* Port not connected */ + } + timeout++; + if (timeout > 10) { + USB_LOG_ERR("Reset port timeout\r\n"); + return -USB_ERR_TIMEOUT; + } + usb_osal_msleep(10U); + } + return 0; +} + +/** + * @brief dwc2_get_glb_intstatus: return the global USB interrupt status + * @retval status + */ +static inline uint32_t dwc2_get_glb_intstatus(struct usbh_bus *bus) +{ + uint32_t tmpreg; + + tmpreg = USB_OTG_GLB->GINTSTS; + tmpreg &= USB_OTG_GLB->GINTMSK; + + return tmpreg; +} + +static inline uint16_t dwc2_get_full_frame_num(struct usbh_bus *bus) +{ + uint16_t frame = usbh_get_frame_number(bus); + + /* USB_OTG_HFNUM_FRNUM_Msk is 0xFFFF but max frame num is 0x3FFF */ + return ((frame & 0x3FFF) >> 3); +} + +/** + * dwc2_calc_frame_interval() - Calculates the correct frame Interval value for + * the HFIR register according to PHY type and speed + * + * NOTE: The caller can modify the value of the HFIR register only after the + * Port Enable bit of the Host Port Control and Status register (HPRT.EnaPort) + * has been set + */ +uint32_t dwc2_calc_frame_interval(struct usbh_bus *bus) +{ + uint32_t usbcfg; + uint32_t hprt0; + int clock = 60; /* default value */ + + usbcfg = USB_OTG_GLB->GUSBCFG; + hprt0 = USB_OTG_HPRT; + + if (!(usbcfg & USB_OTG_GUSBCFG_PHYSEL) && (usbcfg & USB_OTG_GUSBCFG_ULPI_UTMI_SEL) && + !(usbcfg & USB_OTG_GUSBCFG_PHYIF16)) + clock = 60; + if ((usbcfg & USB_OTG_GUSBCFG_PHYSEL) && g_dwc2_hcd[bus->hcd.hcd_id].hw_params.fs_phy_type == + GHWCFG2_FS_PHY_TYPE_SHARED_ULPI) + clock = 48; + if (!(usbcfg & USB_OTG_GUSBCFG_PHYLPCS) && !(usbcfg & USB_OTG_GUSBCFG_PHYSEL) && + !(usbcfg & USB_OTG_GUSBCFG_ULPI_UTMI_SEL) && (usbcfg & USB_OTG_GUSBCFG_PHYIF16)) + clock = 30; + if (!(usbcfg & USB_OTG_GUSBCFG_PHYLPCS) && !(usbcfg & USB_OTG_GUSBCFG_PHYSEL) && + !(usbcfg & USB_OTG_GUSBCFG_ULPI_UTMI_SEL) && !(usbcfg & USB_OTG_GUSBCFG_PHYIF16)) + clock = 60; + if ((usbcfg & USB_OTG_GUSBCFG_PHYLPCS) && !(usbcfg & USB_OTG_GUSBCFG_PHYSEL) && + !(usbcfg & USB_OTG_GUSBCFG_ULPI_UTMI_SEL) && (usbcfg & USB_OTG_GUSBCFG_PHYIF16)) + clock = 48; + if ((usbcfg & USB_OTG_GUSBCFG_PHYSEL) && !(usbcfg & USB_OTG_GUSBCFG_PHYIF16) && + g_dwc2_hcd[bus->hcd.hcd_id].hw_params.fs_phy_type == GHWCFG2_FS_PHY_TYPE_SHARED_UTMI) + clock = 48; + if ((usbcfg & USB_OTG_GUSBCFG_PHYSEL) && + g_dwc2_hcd[bus->hcd.hcd_id].hw_params.fs_phy_type == GHWCFG2_FS_PHY_TYPE_DEDICATED) + clock = 48; + + if ((hprt0 & USB_OTG_HPRT_PSPD) >> USB_OTG_HPRT_PSPD_Pos == HPRT0_PRTSPD_HIGH_SPEED) + /* High speed case */ + return 125 * clock - 1; + + /* FS/LS case */ + return 1000 * clock - 1; +} + +static int dwc2_chan_alloc(struct usbh_bus *bus) +{ + size_t flags; + int chidx; + + flags = usb_osal_enter_critical_section(); + for (chidx = 0; chidx < g_dwc2_hcd[bus->hcd.hcd_id].hw_params.host_channels; chidx++) { + if (!g_dwc2_hcd[bus->hcd.hcd_id].chan_pool[chidx].inuse) { + g_dwc2_hcd[bus->hcd.hcd_id].chan_pool[chidx].inuse = true; + usb_osal_leave_critical_section(flags); + + g_dwc2_hcd[bus->hcd.hcd_id].chan_pool[chidx].do_ssplit = 0; + g_dwc2_hcd[bus->hcd.hcd_id].chan_pool[chidx].do_csplit = 0; + return chidx; + } + } + usb_osal_leave_critical_section(flags); + return -1; +} + +static void dwc2_chan_free(struct dwc2_chan *chan) +{ + size_t flags; + + flags = usb_osal_enter_critical_section(); + if (chan->urb) { + chan->urb->hcpriv = NULL; + chan->urb = NULL; + } + chan->inuse = false; + usb_osal_leave_critical_section(flags); +} + +static uint16_t dwc2_calculate_packet_num(uint32_t input_size, uint8_t ep_addr, uint16_t ep_mps, uint32_t *output_size) +{ + uint16_t num_packets; + + num_packets = (uint16_t)((input_size + ep_mps - 1U) / ep_mps); + + if (num_packets > 0x3FF) { + num_packets = 0x3FF; // pktcnt 10bits + } + + if (input_size == 0) { + num_packets = 1; + } + + if (ep_addr & 0x80) { + input_size = num_packets * ep_mps; + } else { + } + + *output_size = input_size; + return num_packets; +} + +static void dwc2_control_urb_init(struct usbh_bus *bus, uint8_t chidx, struct usbh_urb *urb, struct usb_setup_packet *setup, uint8_t *buffer, uint32_t buflen) +{ + struct dwc2_chan *chan; + uint32_t datalen; + uint8_t data_pid; + + chan = &g_dwc2_hcd[bus->hcd.hcd_id].chan_pool[chidx]; + + /* split buflen with ep mps */ + if (chan->do_ssplit && (chan->ep0_state == DWC2_EP0_STATE_INDATA || chan->ep0_state == DWC2_EP0_STATE_OUTDATA)) { + if (buflen > USB_GET_MAXPACKETSIZE(urb->ep->wMaxPacketSize)) { + datalen = USB_GET_MAXPACKETSIZE(urb->ep->wMaxPacketSize); + } else { + datalen = buflen; + } + + if (urb->data_toggle == 0) { + data_pid = HC_PID_DATA0; + } else { + data_pid = HC_PID_DATA1; + } + } else { + datalen = buflen; // buflen = setup->wLength + data_pid = HC_PID_DATA1; + } + + if (chan->ep0_state == DWC2_EP0_STATE_SETUP) /* fill setup */ + { + chan->num_packets = dwc2_calculate_packet_num(8, 0x00, USB_GET_MAXPACKETSIZE(urb->ep->wMaxPacketSize), &chan->xferlen); + dwc2_chan_init(bus, + chidx, + urb->hport->dev_addr, + 0x00, + USB_ENDPOINT_TYPE_CONTROL, + USB_GET_MAXPACKETSIZE(urb->ep->wMaxPacketSize), + 1, + urb->hport->speed); + dwc2_chan_transfer(bus, chidx, 0x00, (uint8_t *)setup, chan->xferlen, chan->num_packets, HC_PID_SETUP); + } else if (chan->ep0_state == DWC2_EP0_STATE_INDATA) /* fill in data */ + { + chan->num_packets = dwc2_calculate_packet_num(datalen, 0x80, USB_GET_MAXPACKETSIZE(urb->ep->wMaxPacketSize), &chan->xferlen); + dwc2_chan_init(bus, + chidx, + urb->hport->dev_addr, + 0x80, + USB_ENDPOINT_TYPE_CONTROL, + USB_GET_MAXPACKETSIZE(urb->ep->wMaxPacketSize), + 1, + urb->hport->speed); + dwc2_chan_transfer(bus, chidx, 0x80, buffer, chan->xferlen, chan->num_packets, data_pid); + } else if (chan->ep0_state == DWC2_EP0_STATE_OUTDATA) /* fill out data */ + { + chan->num_packets = dwc2_calculate_packet_num(datalen, 0x00, USB_GET_MAXPACKETSIZE(urb->ep->wMaxPacketSize), &chan->xferlen); + dwc2_chan_init(bus, + chidx, + urb->hport->dev_addr, + 0x00, + USB_ENDPOINT_TYPE_CONTROL, + USB_GET_MAXPACKETSIZE(urb->ep->wMaxPacketSize), + 1, + urb->hport->speed); + dwc2_chan_transfer(bus, chidx, 0x00, buffer, chan->xferlen, chan->num_packets, data_pid); + } else if (chan->ep0_state == DWC2_EP0_STATE_INSTATUS) /* fill in status */ + { + chan->num_packets = dwc2_calculate_packet_num(0, 0x80, USB_GET_MAXPACKETSIZE(urb->ep->wMaxPacketSize), &chan->xferlen); + dwc2_chan_init(bus, + chidx, + urb->hport->dev_addr, + 0x80, + USB_ENDPOINT_TYPE_CONTROL, + USB_GET_MAXPACKETSIZE(urb->ep->wMaxPacketSize), + 1, + urb->hport->speed); + dwc2_chan_transfer(bus, chidx, 0x80, NULL, chan->xferlen, chan->num_packets, HC_PID_DATA1); + } else if (chan->ep0_state == DWC2_EP0_STATE_OUTSTATUS) /* fill out status */ + { + chan->num_packets = dwc2_calculate_packet_num(0, 0x00, USB_GET_MAXPACKETSIZE(urb->ep->wMaxPacketSize), &chan->xferlen); + dwc2_chan_init(bus, + chidx, + urb->hport->dev_addr, + 0x00, + USB_ENDPOINT_TYPE_CONTROL, + USB_GET_MAXPACKETSIZE(urb->ep->wMaxPacketSize), + 1, + urb->hport->speed); + dwc2_chan_transfer(bus, chidx, 0x00, NULL, chan->xferlen, chan->num_packets, HC_PID_DATA1); + } +} + +static void dwc2_bulk_intr_urb_init(struct usbh_bus *bus, uint8_t chidx, struct usbh_urb *urb, uint8_t *buffer, uint32_t buflen) +{ + struct dwc2_chan *chan; + uint32_t datalen; + + chan = &g_dwc2_hcd[bus->hcd.hcd_id].chan_pool[chidx]; + + if (chan->do_ssplit) { + if (buflen > USB_GET_MAXPACKETSIZE(urb->ep->wMaxPacketSize)) { + datalen = USB_GET_MAXPACKETSIZE(urb->ep->wMaxPacketSize); + } else { + datalen = buflen; + } + } else { + datalen = buflen; + } + + chan->num_packets = dwc2_calculate_packet_num(datalen, urb->ep->bEndpointAddress, USB_GET_MAXPACKETSIZE(urb->ep->wMaxPacketSize), &chan->xferlen); + dwc2_chan_init(bus, + chidx, + urb->hport->dev_addr, + urb->ep->bEndpointAddress, + USB_GET_ENDPOINT_TYPE(urb->ep->bmAttributes), + USB_GET_MAXPACKETSIZE(urb->ep->wMaxPacketSize), + USB_GET_MULT(urb->ep->wMaxPacketSize) + 1, + urb->hport->speed); + dwc2_chan_transfer(bus, chidx, urb->ep->bEndpointAddress, buffer, chan->xferlen, chan->num_packets, urb->data_toggle == 0 ? HC_PID_DATA0 : HC_PID_DATA1); +} + +#if 0 +static void dwc2_iso_urb_init(struct usbh_bus *bus, uint8_t chidx, struct usbh_urb *urb, struct usbh_iso_frame_packet *iso_packet) +{ + struct dwc2_chan *chan; + + chan = &g_dwc2_hcd[bus->hcd.hcd_id].chan_pool[chidx]; + + chan->num_packets = dwc2_calculate_packet_num(iso_packet->transfer_buffer_length, urb->ep->bEndpointAddress, USB_GET_MAXPACKETSIZE(urb->ep->wMaxPacketSize), &chan->xferlen); + dwc2_chan_init(bus, chidx, urb->hport->dev_addr, urb->ep->bEndpointAddress, USB_ENDPOINT_TYPE_ISOCHRONOUS, USB_GET_MAXPACKETSIZE(urb->ep->wMaxPacketSize), urb->hport->speed); + dwc2_chan_transfer(bus, chidx, urb->ep->bEndpointAddress, iso_packet->transfer_buffer, chan->xferlen, chan->num_packets, HC_PID_DATA0); +} +#endif + +__WEAK void usb_hc_low_level_init(struct usbh_bus *bus) +{ + (void)bus; +} + +__WEAK void usb_hc_low_level_deinit(struct usbh_bus *bus) +{ + (void)bus; +} + +int usb_hc_init(struct usbh_bus *bus) +{ + int ret; + + memset(&g_dwc2_hcd[bus->hcd.hcd_id], 0, sizeof(struct dwc2_hcd)); + + usb_hc_low_level_init(bus); + + USB_LOG_INFO("========== dwc2 hcd params ==========\r\n"); + USB_LOG_INFO("CID:%08x\r\n", (unsigned int)USB_OTG_GLB->CID); + USB_LOG_INFO("GSNPSID:%08x\r\n", (unsigned int)USB_OTG_GLB->GSNPSID); + USB_LOG_INFO("GHWCFG1:%08x\r\n", (unsigned int)USB_OTG_GLB->GHWCFG1); + USB_LOG_INFO("GHWCFG2:%08x\r\n", (unsigned int)USB_OTG_GLB->GHWCFG2); + USB_LOG_INFO("GHWCFG3:%08x\r\n", (unsigned int)USB_OTG_GLB->GHWCFG3); + USB_LOG_INFO("GHWCFG4:%08x\r\n", (unsigned int)USB_OTG_GLB->GHWCFG4); + + dwc2_get_hwparams(bus->hcd.reg_base, &g_dwc2_hcd[bus->hcd.hcd_id].hw_params); + dwc2_get_user_params(bus->hcd.reg_base, &g_dwc2_hcd[bus->hcd.hcd_id].user_params); + + if (g_dwc2_hcd[bus->hcd.hcd_id].user_params.phy_utmi_width == 0) { + g_dwc2_hcd[bus->hcd.hcd_id].user_params.phy_utmi_width = 8; + } + if (g_dwc2_hcd[bus->hcd.hcd_id].user_params.total_fifo_size == 0) { + g_dwc2_hcd[bus->hcd.hcd_id].user_params.total_fifo_size = g_dwc2_hcd[bus->hcd.hcd_id].hw_params.total_fifo_size; + } + + for (uint8_t chidx = 0; chidx < g_dwc2_hcd[bus->hcd.hcd_id].hw_params.host_channels; chidx++) { + g_dwc2_hcd[bus->hcd.hcd_id].chan_pool[chidx].waitsem = usb_osal_sem_create(0); + } + + USB_LOG_INFO("dwc2 has %d channels and dfifo depth(32-bit words) is %d\r\n", + g_dwc2_hcd[bus->hcd.hcd_id].hw_params.host_channels, + g_dwc2_hcd[bus->hcd.hcd_id].user_params.total_fifo_size); + + USB_ASSERT_MSG(g_dwc2_hcd[bus->hcd.hcd_id].hw_params.arch == GHWCFG2_INT_DMA_ARCH, "This dwc2 version does not support dma mode, so stop working"); + USB_ASSERT_MSG((g_dwc2_hcd[bus->hcd.hcd_id].user_params.host_rx_fifo_size + + g_dwc2_hcd[bus->hcd.hcd_id].user_params.host_nperio_tx_fifo_size + + g_dwc2_hcd[bus->hcd.hcd_id].user_params.host_perio_tx_fifo_size) <= + g_dwc2_hcd[bus->hcd.hcd_id].user_params.total_fifo_size, + "Your fifo config is overflow, please check"); + + USB_OTG_GLB->GAHBCFG &= ~USB_OTG_GAHBCFG_GINT; + + /* This is vendor register */ + USB_OTG_GLB->GCCFG = g_dwc2_hcd[bus->hcd.hcd_id].user_params.host_gccfg; + + if (g_dwc2_hcd[bus->hcd.hcd_id].user_params.phy_type != DWC2_PHY_TYPE_PARAM_FS) { + USB_ASSERT_MSG(g_dwc2_hcd[bus->hcd.hcd_id].hw_params.hs_phy_type != 0, "This dwc2 version does not support hs, so stop working"); + } + + ret = dwc2_core_init(bus); + + /* Force Host Mode*/ + dwc2_set_mode(bus, USB_OTG_MODE_HOST); + + USB_ASSERT_MSG((USB_OTG_GLB->GRXFSIZ & 0xffff) >= g_dwc2_hcd[bus->hcd.hcd_id].user_params.host_rx_fifo_size, + "host_rx_fifo_size cannot be larger than power_on_value %u", (unsigned int)(USB_OTG_GLB->GRXFSIZ & 0xffff)); + USB_ASSERT_MSG(((USB_OTG_GLB->DIEPTXF0_HNPTXFSIZ >> 16) & 0xffff) >= g_dwc2_hcd[bus->hcd.hcd_id].user_params.host_nperio_tx_fifo_size, + "host_nperio_tx_fifo_size cannot be larger than power_on_value %u", (unsigned int)((USB_OTG_GLB->DIEPTXF0_HNPTXFSIZ >> 16) & 0xffff)); + USB_ASSERT_MSG(((USB_OTG_GLB->HPTXFSIZ >> 16) & 0xffff) >= g_dwc2_hcd[bus->hcd.hcd_id].user_params.host_perio_tx_fifo_size, + "host_perio_tx_fifo_size cannot be larger than power_on_value %u", (unsigned int)((USB_OTG_GLB->HPTXFSIZ >> 16) & 0xffff)); + + /* B-peripheral session valid override enable */ + USB_OTG_GLB->GOTGCTL &= ~USB_OTG_GOTGCTL_BVALOEN; + USB_OTG_GLB->GOTGCTL &= ~USB_OTG_GOTGCTL_BVALOVAL; + + USB_OTG_GLB->GUSBCFG |= USB_OTG_GUSBCFG_TOCAL; + + /* Restart the Phy Clock */ + USB_OTG_PCGCCTL = 0U; + + /* Set default Max speed support */ + USB_OTG_HOST->HCFG &= ~USB_OTG_HCFG_FSLSS; + + USB_OTG_HOST->HCFG &= ~USB_OTG_HCFG_FSLSPCS; + if (g_dwc2_hcd[bus->hcd.hcd_id].user_params.phy_type == DWC2_PHY_TYPE_PARAM_FS) { + bus->hcd.roothub.speed = USB_SPEED_FULL; + USB_OTG_HOST->HCFG |= USB_OTG_HCFG_FSLSPCLKSEL_48_MHZ; + } else { + bus->hcd.roothub.speed = USB_SPEED_HIGH; + USB_OTG_HOST->HCFG |= USB_OTG_HCFG_FSLSPCLKSEL_30_60_MHZ; + } + + if (g_dwc2_hcd[bus->hcd.hcd_id].hw_params.snpsid > 0x4F54292AU) { + USB_OTG_HOST->HFIR |= USB_OTG_HFIR_RELOAD_CTRL; + } + + /* Clear all pending HC Interrupts */ + for (uint8_t i = 0U; i < g_dwc2_hcd[bus->hcd.hcd_id].hw_params.host_channels; i++) { + USB_OTG_HC(i)->HCINT = 0xFFFFFFFFU; + USB_OTG_HC(i)->HCINTMSK = 0U; + } + + /* Disable all interrupts. */ + USB_OTG_GLB->GINTMSK = 0U; + + /* Clear any pending interrupts */ + USB_OTG_GLB->GINTSTS = 0xFFFFFFFFU; + + /* set FIFO size */ + USB_OTG_GLB->GRXFSIZ = g_dwc2_hcd[bus->hcd.hcd_id].user_params.host_rx_fifo_size; + USB_OTG_GLB->DIEPTXF0_HNPTXFSIZ = (uint32_t)(((g_dwc2_hcd[bus->hcd.hcd_id].user_params.host_nperio_tx_fifo_size << 16) & USB_OTG_NPTXFD) | + g_dwc2_hcd[bus->hcd.hcd_id].user_params.host_rx_fifo_size); + USB_OTG_GLB->HPTXFSIZ = (uint32_t)(((g_dwc2_hcd[bus->hcd.hcd_id].user_params.host_perio_tx_fifo_size << 16) & USB_OTG_HPTXFSIZ_PTXFD) | + (g_dwc2_hcd[bus->hcd.hcd_id].user_params.host_rx_fifo_size + g_dwc2_hcd[bus->hcd.hcd_id].user_params.host_nperio_tx_fifo_size)); + + ret = dwc2_flush_txfifo(bus, 0x10U); + ret = dwc2_flush_rxfifo(bus); + + USB_OTG_GLB->GAHBCFG &= ~USB_OTG_GAHBCFG_HBSTLEN; + USB_OTG_GLB->GAHBCFG |= USB_OTG_GAHBCFG_HBSTLEN_4; + USB_OTG_GLB->GAHBCFG |= USB_OTG_GAHBCFG_DMAEN; + + /* Enable interrupts matching to the Host mode ONLY */ + USB_OTG_GLB->GINTMSK |= (USB_OTG_GINTMSK_PRTIM | USB_OTG_GINTMSK_HCIM | + USB_OTG_GINTSTS_DISCINT); + + dwc2_drivebus(bus, 1); + usb_osal_msleep(200); + + USB_OTG_GLB->GAHBCFG |= USB_OTG_GAHBCFG_GINT; + + return ret; +} + +int usb_hc_deinit(struct usbh_bus *bus) +{ + USB_OTG_GLB->GAHBCFG &= ~USB_OTG_GAHBCFG_GINT; + + dwc2_flush_txfifo(bus, 0x10U); + dwc2_flush_rxfifo(bus); + + /* Flush out any leftover queued requests. */ + for (uint8_t chidx = 0; chidx < g_dwc2_hcd[bus->hcd.hcd_id].hw_params.host_channels; chidx++) { + dwc2_halt(bus, chidx); + } + + /* Disable all interrupts. */ + USB_OTG_GLB->GINTMSK = 0U; + + /* Clear any pending Host interrupts */ + USB_OTG_HOST->HAINT = 0xFFFFFFFFU; + USB_OTG_GLB->GINTSTS = 0xFFFFFFFFU; + + dwc2_drivebus(bus, 0); + usb_osal_msleep(200); + + for (uint8_t chidx = 0; chidx < g_dwc2_hcd[bus->hcd.hcd_id].hw_params.host_channels; chidx++) { + usb_osal_sem_delete(g_dwc2_hcd[bus->hcd.hcd_id].chan_pool[chidx].waitsem); + } + + usb_hc_low_level_deinit(bus); + return 0; +} + +uint16_t usbh_get_frame_number(struct usbh_bus *bus) +{ + return (USB_OTG_HOST->HFNUM & USB_OTG_HFNUM_FRNUM); +} + +int usbh_roothub_control(struct usbh_bus *bus, struct usb_setup_packet *setup, uint8_t *buf) +{ + __IO uint32_t hprt0; + uint8_t nports; + uint8_t port; + uint32_t status; + + nports = CONFIG_USBHOST_MAX_RHPORTS; + port = setup->wIndex; + if (setup->bmRequestType & USB_REQUEST_RECIPIENT_DEVICE) { + switch (setup->bRequest) { + case HUB_REQUEST_CLEAR_FEATURE: + switch (setup->wValue) { + case HUB_FEATURE_HUB_C_LOCALPOWER: + break; + case HUB_FEATURE_HUB_C_OVERCURRENT: + break; + default: + return -USB_ERR_NOTSUPP; + } + break; + case HUB_REQUEST_SET_FEATURE: + switch (setup->wValue) { + case HUB_FEATURE_HUB_C_LOCALPOWER: + break; + case HUB_FEATURE_HUB_C_OVERCURRENT: + break; + default: + return -USB_ERR_NOTSUPP; + } + break; + case HUB_REQUEST_GET_DESCRIPTOR: + break; + case HUB_REQUEST_GET_STATUS: + memset(buf, 0, 4); + break; + default: + break; + } + } else if (setup->bmRequestType & USB_REQUEST_RECIPIENT_OTHER) { + switch (setup->bRequest) { + case HUB_REQUEST_CLEAR_FEATURE: + if (!port || port > nports) { + return -USB_ERR_INVAL; + } + + switch (setup->wValue) { + case HUB_PORT_FEATURE_ENABLE: + USB_OTG_HPRT &= ~USB_OTG_HPRT_PENA; + break; + case HUB_PORT_FEATURE_SUSPEND: + case HUB_PORT_FEATURE_C_SUSPEND: + break; + case HUB_PORT_FEATURE_POWER: + dwc2_drivebus(bus, 0); + break; + case HUB_PORT_FEATURE_C_CONNECTION: + g_dwc2_hcd[bus->hcd.hcd_id].port_csc = 0; + break; + case HUB_PORT_FEATURE_C_ENABLE: + g_dwc2_hcd[bus->hcd.hcd_id].port_pec = 0; + break; + case HUB_PORT_FEATURE_C_OVER_CURREN: + g_dwc2_hcd[bus->hcd.hcd_id].port_occ = 0; + break; + case HUB_PORT_FEATURE_C_RESET: + break; + default: + return -USB_ERR_NOTSUPP; + } + break; + case HUB_REQUEST_SET_FEATURE: + if (!port || port > nports) { + return -USB_ERR_INVAL; + } + + switch (setup->wValue) { + case HUB_PORT_FEATURE_SUSPEND: + break; + case HUB_PORT_FEATURE_POWER: + dwc2_drivebus(bus, 1); + break; + case HUB_PORT_FEATURE_RESET: + return usbh_reset_port(bus, port); + + default: + return -USB_ERR_NOTSUPP; + } + break; + case HUB_REQUEST_GET_STATUS: + if (!port || port > nports) { + return -USB_ERR_INVAL; + } + hprt0 = USB_OTG_HPRT; + + status = 0; + if (g_dwc2_hcd[bus->hcd.hcd_id].port_csc) { + status |= (1 << HUB_PORT_FEATURE_C_CONNECTION); + } + if (g_dwc2_hcd[bus->hcd.hcd_id].port_pec) { + status |= (1 << HUB_PORT_FEATURE_C_ENABLE); + } + if (g_dwc2_hcd[bus->hcd.hcd_id].port_occ) { + status |= (1 << HUB_PORT_FEATURE_C_OVER_CURREN); + } + + if (hprt0 & USB_OTG_HPRT_PCSTS) { + status |= (1 << HUB_PORT_FEATURE_CONNECTION); + } + if (hprt0 & USB_OTG_HPRT_PENA) { + status |= (1 << HUB_PORT_FEATURE_ENABLE); + if (usbh_get_port_speed(bus, port) == USB_SPEED_LOW) { + status |= (1 << HUB_PORT_FEATURE_LOWSPEED); + } else if (usbh_get_port_speed(bus, port) == USB_SPEED_HIGH) { + status |= (1 << HUB_PORT_FEATURE_HIGHSPEED); + } + } + if (hprt0 & USB_OTG_HPRT_POCA) { + status |= (1 << HUB_PORT_FEATURE_OVERCURRENT); + } + if (hprt0 & USB_OTG_HPRT_PRST) { + status |= (1 << HUB_PORT_FEATURE_RESET); + } + if (hprt0 & USB_OTG_HPRT_PPWR) { + status |= (1 << HUB_PORT_FEATURE_POWER); + } + + memcpy(buf, &status, 4); + break; + default: + break; + } + } + return 0; +} + +int usbh_submit_urb(struct usbh_urb *urb) +{ + struct dwc2_chan *chan; + struct usbh_bus *bus; + size_t flags; + int ret = 0; + int chidx; + + if (!urb || !urb->hport || !urb->ep || !urb->hport->bus) { + return -USB_ERR_INVAL; + } + + /* dma addr must be aligned 4 bytes */ + USB_ASSERT_MSG(!((uintptr_t)urb->setup % 4) && !((uintptr_t)urb->transfer_buffer % 4), + "urb->setup or urb->transfer_buffer is not aligned 4 bytes"); + +#ifdef CONFIG_USB_DCACHE_ENABLE + USB_ASSERT_MSG(!((uintptr_t)urb->setup % CONFIG_USB_ALIGN_SIZE) && + !((uintptr_t)urb->transfer_buffer % CONFIG_USB_ALIGN_SIZE), + "urb->setup or urb->transfer_buffer is not aligned %d", CONFIG_USB_ALIGN_SIZE); +#endif + bus = urb->hport->bus; + + if (!(USB_OTG_HPRT & USB_OTG_HPRT_PCSTS) || !urb->hport->connected) { + return -USB_ERR_NOTCONN; + } + + if (urb->errorcode == -USB_ERR_BUSY) { + return -USB_ERR_BUSY; + } + + if (urb->ep->bEndpointAddress & 0x80) { + /* Check if pipe rx fifo is overflow */ + if (USB_GET_MAXPACKETSIZE(urb->ep->wMaxPacketSize) > (g_dwc2_hcd[bus->hcd.hcd_id].user_params.host_rx_fifo_size * 4)) { + return -USB_ERR_RANGE; + } + } else { + /* Check if intr and iso pipe tx fifo is overflow */ + if (((USB_GET_ENDPOINT_TYPE(urb->ep->bmAttributes) == USB_ENDPOINT_TYPE_ISOCHRONOUS) || + (USB_GET_ENDPOINT_TYPE(urb->ep->bmAttributes) == USB_ENDPOINT_TYPE_INTERRUPT)) && + USB_GET_MAXPACKETSIZE(urb->ep->wMaxPacketSize) > (g_dwc2_hcd[bus->hcd.hcd_id].user_params.host_perio_tx_fifo_size * 4)) { + return -USB_ERR_RANGE; + } else { + /* Check if control and bulk pipe tx fifo is overflow */ + if (USB_GET_MAXPACKETSIZE(urb->ep->wMaxPacketSize) > (g_dwc2_hcd[bus->hcd.hcd_id].user_params.host_nperio_tx_fifo_size * 4)) { + return -USB_ERR_RANGE; + } + } + } + + chidx = dwc2_chan_alloc(bus); + if (chidx == -1) { + return -USB_ERR_NOMEM; + } + + flags = usb_osal_enter_critical_section(); + + chan = &g_dwc2_hcd[bus->hcd.hcd_id].chan_pool[chidx]; + chan->chidx = chidx; + chan->urb = urb; + chan->do_ssplit = 0; + + if (urb->hport->speed != USB_SPEED_HIGH && + usbh_get_port_speed(bus, 0) == USB_SPEED_HIGH) { + chan->do_ssplit = 1; + chan->do_csplit = 0; + chan->hub_port = urb->hport->port; + chan->hub_addr = urb->hport->parent->hub_addr; + } + + urb->hcpriv = chan; + urb->errorcode = -USB_ERR_BUSY; + urb->actual_length = 0; + + usb_osal_leave_critical_section(flags); + + if (urb->setup) { + usb_dcache_clean((uintptr_t)urb->setup, USB_ALIGN_UP(sizeof(struct usb_setup_packet), CONFIG_USB_ALIGN_SIZE)); + + if (urb->transfer_buffer) { + if (urb->setup->bmRequestType & 0x80) { + usb_dcache_invalidate((uintptr_t)urb->transfer_buffer, USB_ALIGN_UP(urb->transfer_buffer_length, CONFIG_USB_ALIGN_SIZE)); + } else { + usb_dcache_clean((uintptr_t)urb->transfer_buffer, USB_ALIGN_UP(urb->transfer_buffer_length, CONFIG_USB_ALIGN_SIZE)); + } + } + } else if (urb->transfer_buffer && (USB_GET_ENDPOINT_TYPE(urb->ep->bmAttributes) != USB_ENDPOINT_TYPE_ISOCHRONOUS)) { + if (urb->ep->bEndpointAddress & 0x80) { + usb_dcache_invalidate((uintptr_t)urb->transfer_buffer, USB_ALIGN_UP(urb->transfer_buffer_length, CONFIG_USB_ALIGN_SIZE)); + } else { + usb_dcache_clean((uintptr_t)urb->transfer_buffer, USB_ALIGN_UP(urb->transfer_buffer_length, CONFIG_USB_ALIGN_SIZE)); + } + } else { + } + + switch (USB_GET_ENDPOINT_TYPE(urb->ep->bmAttributes)) { + case USB_ENDPOINT_TYPE_CONTROL: + chan->ep0_state = DWC2_EP0_STATE_SETUP; + dwc2_control_urb_init(bus, chidx, urb, urb->setup, urb->transfer_buffer, urb->transfer_buffer_length); + break; + case USB_ENDPOINT_TYPE_BULK: + case USB_ENDPOINT_TYPE_INTERRUPT: + dwc2_bulk_intr_urb_init(bus, chidx, urb, urb->transfer_buffer, urb->transfer_buffer_length); + break; + case USB_ENDPOINT_TYPE_ISOCHRONOUS: + break; + default: + break; + } + + if (urb->timeout > 0) { + /* wait until timeout or sem give */ + ret = usb_osal_sem_take(chan->waitsem, urb->timeout); + if (ret < 0) { + goto errout_timeout; + } + urb->timeout = 0; + ret = urb->errorcode; + /* we can free chan when waitsem is done */ + dwc2_chan_free(chan); + } + return ret; +errout_timeout: + urb->timeout = 0; + usbh_kill_urb(urb); + return ret; +} + +int usbh_kill_urb(struct usbh_urb *urb) +{ + struct dwc2_chan *chan; + struct usbh_bus *bus; + size_t flags; + + if (!urb || !urb->hcpriv || !urb->hport->bus) { + return -USB_ERR_INVAL; + } + + bus = urb->hport->bus; + + flags = usb_osal_enter_critical_section(); + + chan = (struct dwc2_chan *)urb->hcpriv; + + dwc2_halt(bus, chan->chidx); + + urb->errorcode = -USB_ERR_SHUTDOWN; + + if (urb->timeout) { + usb_osal_sem_give(chan->waitsem); + } else { + dwc2_chan_free(chan); + } + + if (urb->complete) { + urb->complete(urb->arg, urb->errorcode); + } + + usb_osal_leave_critical_section(flags); + + return 0; +} + +static inline void dwc2_urb_waitup(struct usbh_urb *urb) +{ + struct dwc2_chan *chan; + + chan = (struct dwc2_chan *)urb->hcpriv; + + if (urb->timeout) { + usb_osal_sem_give(chan->waitsem); + } else { + dwc2_chan_free(chan); + } + + if (urb->complete) { + if (urb->errorcode < 0) { + urb->complete(urb->arg, urb->errorcode); + } else { + urb->complete(urb->arg, urb->actual_length); + } + } +} + +static void dwc2_inchan_irq_handler(struct usbh_bus *bus, uint8_t ch_num) +{ + uint32_t chan_intstatus; + struct dwc2_chan *chan; + struct usbh_urb *urb; + + chan_intstatus = USB_OTG_HC(ch_num)->HCINT; + + chan = &g_dwc2_hcd[bus->hcd.hcd_id].chan_pool[ch_num]; + urb = chan->urb; + //printf("s1:%08x\r\n", chan_intstatus); + + if (chan_intstatus & USB_OTG_HCINT_CHH) { + USB_OTG_HC(ch_num)->HCINT = chan_intstatus; + if (chan_intstatus & USB_OTG_HCINT_XFRC) { + uint32_t count = chan->xferlen - (USB_OTG_HC(ch_num)->HCTSIZ & USB_OTG_HCTSIZ_XFRSIZ); /* how many size has received */ + uint8_t data_toggle = ((USB_OTG_HC(ch_num)->HCTSIZ & USB_OTG_HCTSIZ_DPID) >> USB_OTG_HCTSIZ_DPID_Pos); + + urb->actual_length += count; + urb->transfer_buffer_length -= count; + + if (data_toggle == HC_PID_DATA0) { + urb->data_toggle = 0; + } else { + urb->data_toggle = 1; + } + + if (chan->do_csplit) { + chan->do_csplit = 0; + dwc2_chan_enable_csplit(bus, ch_num, false); + } + + if (USB_GET_ENDPOINT_TYPE(urb->ep->bmAttributes) == USB_ENDPOINT_TYPE_CONTROL) { + if (chan->ep0_state == DWC2_EP0_STATE_INDATA) { + if (chan->do_ssplit && urb->transfer_buffer_length > 0 && (count == USB_GET_MAXPACKETSIZE(urb->ep->wMaxPacketSize))) { + dwc2_control_urb_init(bus, ch_num, urb, urb->setup, urb->transfer_buffer + urb->actual_length - 8, urb->transfer_buffer_length); + } else { + chan->ep0_state = DWC2_EP0_STATE_OUTSTATUS; + dwc2_control_urb_init(bus, ch_num, urb, urb->setup, urb->transfer_buffer, urb->transfer_buffer_length); + } + } else if (chan->ep0_state == DWC2_EP0_STATE_INSTATUS) { + chan->ep0_state = DWC2_EP0_STATE_SETUP; + urb->errorcode = 0; + dwc2_urb_waitup(urb); + } + } else if (USB_GET_ENDPOINT_TYPE(urb->ep->bmAttributes) == USB_ENDPOINT_TYPE_ISOCHRONOUS) { + } else { + if (chan->do_ssplit && urb->transfer_buffer_length > 0 && (count == USB_GET_MAXPACKETSIZE(urb->ep->wMaxPacketSize))) { + dwc2_bulk_intr_urb_init(bus, ch_num, urb, urb->transfer_buffer + urb->actual_length, urb->transfer_buffer_length); + } else { + usb_dcache_invalidate((uintptr_t)urb->transfer_buffer, USB_ALIGN_UP(urb->actual_length, CONFIG_USB_ALIGN_SIZE)); + urb->errorcode = 0; + dwc2_urb_waitup(urb); + } + } + } else if (chan_intstatus & USB_OTG_HCINT_AHBERR) { + urb->errorcode = -USB_ERR_IO; + dwc2_urb_waitup(urb); + } else if (chan_intstatus & USB_OTG_HCINT_STALL) { + urb->errorcode = -USB_ERR_STALL; + dwc2_urb_waitup(urb); + } else if (chan_intstatus & USB_OTG_HCINT_NAK) { + if (chan->do_ssplit) { + /* restart ssplit transfer */ + switch (USB_GET_ENDPOINT_TYPE(urb->ep->bmAttributes)) { + case USB_ENDPOINT_TYPE_CONTROL: + chan->do_csplit = 0; + dwc2_control_urb_init(bus, ch_num, urb, urb->setup, urb->transfer_buffer + urb->actual_length - 8, urb->transfer_buffer_length); + break; + case USB_ENDPOINT_TYPE_BULK: + chan->do_csplit = 0; + dwc2_bulk_intr_urb_init(bus, ch_num, urb, urb->transfer_buffer + urb->actual_length, urb->transfer_buffer_length); + break; + case USB_ENDPOINT_TYPE_INTERRUPT: + chan->do_csplit = 0; + dwc2_chan_enable_csplit(bus, ch_num, false); + urb->errorcode = -USB_ERR_NAK; + dwc2_urb_waitup(urb); + break; + + default: + break; + } + } else { + urb->errorcode = -USB_ERR_NAK; + dwc2_urb_waitup(urb); + } + } else if (chan_intstatus & USB_OTG_HCINT_ACK) { + if (chan->do_ssplit) { + /* start csplit transfer */ + chan->do_csplit = 1; + chan->ssplit_frame = dwc2_get_full_frame_num(bus); + switch (USB_GET_ENDPOINT_TYPE(urb->ep->bmAttributes)) { + case USB_ENDPOINT_TYPE_CONTROL: + dwc2_control_urb_init(bus, ch_num, urb, urb->setup, urb->transfer_buffer + urb->actual_length - 8, urb->transfer_buffer_length); + break; + case USB_ENDPOINT_TYPE_BULK: + case USB_ENDPOINT_TYPE_INTERRUPT: + dwc2_bulk_intr_urb_init(bus, ch_num, urb, urb->transfer_buffer + urb->actual_length, urb->transfer_buffer_length); + break; + + default: + break; + } + } + } else if (chan_intstatus & USB_OTG_HCINT_NYET) { + if (chan->do_ssplit) { + /* restart csplit transfer */ + chan->do_csplit = 1; + chan->ssplit_frame = dwc2_get_full_frame_num(bus); + switch (USB_GET_ENDPOINT_TYPE(urb->ep->bmAttributes)) { + case USB_ENDPOINT_TYPE_CONTROL: + dwc2_control_urb_init(bus, ch_num, urb, urb->setup, urb->transfer_buffer + urb->actual_length - 8, urb->transfer_buffer_length); + break; + case USB_ENDPOINT_TYPE_BULK: + case USB_ENDPOINT_TYPE_INTERRUPT: + dwc2_bulk_intr_urb_init(bus, ch_num, urb, urb->transfer_buffer + urb->actual_length, urb->transfer_buffer_length); + break; + + default: + break; + } + } else { + urb->errorcode = -USB_ERR_NAK; + dwc2_urb_waitup(urb); + } + } else if (chan_intstatus & USB_OTG_HCINT_TXERR) { + urb->errorcode = -USB_ERR_IO; + dwc2_urb_waitup(urb); + } else if (chan_intstatus & USB_OTG_HCINT_BBERR) { + urb->errorcode = -USB_ERR_BABBLE; + dwc2_urb_waitup(urb); + } else if (chan_intstatus & USB_OTG_HCINT_DTERR) { + urb->errorcode = -USB_ERR_DT; + dwc2_urb_waitup(urb); + } else if (chan_intstatus & USB_OTG_HCINT_FRMOR) { + urb->errorcode = -USB_ERR_IO; + dwc2_urb_waitup(urb); + } + } +} + +static void dwc2_outchan_irq_handler(struct usbh_bus *bus, uint8_t ch_num) +{ + uint32_t chan_intstatus; + struct dwc2_chan *chan; + struct usbh_urb *urb; + + chan_intstatus = USB_OTG_HC(ch_num)->HCINT; + + chan = &g_dwc2_hcd[bus->hcd.hcd_id].chan_pool[ch_num]; + urb = chan->urb; + //printf("s2:%08x\r\n", chan_intstatus); + + if (chan_intstatus & USB_OTG_HCINT_CHH) { + USB_OTG_HC(ch_num)->HCINT = chan_intstatus; + if (chan_intstatus & USB_OTG_HCINT_XFRC) { + uint32_t count = USB_OTG_HC(ch_num)->HCTSIZ & USB_OTG_HCTSIZ_XFRSIZ; /* last packet size */ + uint32_t has_used_packets = chan->num_packets - ((USB_OTG_HC(ch_num)->HCTSIZ & USB_OTG_HCTSIZ_PKTCNT) >> 19); /* how many packets have used */ + uint32_t olen = (has_used_packets - 1) * USB_GET_MAXPACKETSIZE(urb->ep->wMaxPacketSize) + count; /* the same with urb->actual_length += chan->xferlen; */ + uint8_t data_toggle = ((USB_OTG_HC(ch_num)->HCTSIZ & USB_OTG_HCTSIZ_DPID) >> USB_OTG_HCTSIZ_DPID_Pos); + + urb->actual_length += olen; + + if (chan->ep0_state == DWC2_EP0_STATE_OUTDATA || urb->setup == NULL) { + if (urb->transfer_buffer_length > olen) { + urb->transfer_buffer_length -= olen; + } else { + urb->transfer_buffer_length = 0; + } + } + + if (data_toggle == HC_PID_DATA0) { + urb->data_toggle = 0; + } else { + urb->data_toggle = 1; + } + + if (chan->do_csplit) { + chan->do_csplit = 0; + dwc2_chan_enable_csplit(bus, ch_num, false); + } + + if (USB_GET_ENDPOINT_TYPE(urb->ep->bmAttributes) == USB_ENDPOINT_TYPE_CONTROL) { + if (chan->ep0_state == DWC2_EP0_STATE_SETUP) { + if (urb->setup->wLength) { + if (urb->setup->bmRequestType & 0x80) { + chan->ep0_state = DWC2_EP0_STATE_INDATA; + } else { + chan->ep0_state = DWC2_EP0_STATE_OUTDATA; + } + } else { + chan->ep0_state = DWC2_EP0_STATE_INSTATUS; + } + dwc2_control_urb_init(bus, ch_num, urb, urb->setup, urb->transfer_buffer, urb->transfer_buffer_length); + } else if (chan->ep0_state == DWC2_EP0_STATE_OUTDATA) { + if (chan->do_ssplit && urb->transfer_buffer_length > 0) { + dwc2_control_urb_init(bus, ch_num, urb, urb->setup, urb->transfer_buffer + urb->actual_length - 8, urb->transfer_buffer_length); + } else { + chan->ep0_state = DWC2_EP0_STATE_INSTATUS; + dwc2_control_urb_init(bus, ch_num, urb, urb->setup, urb->transfer_buffer, urb->transfer_buffer_length); + } + } else if (chan->ep0_state == DWC2_EP0_STATE_OUTSTATUS) { + usb_dcache_invalidate((uintptr_t)urb->transfer_buffer, USB_ALIGN_UP(urb->actual_length - 8, CONFIG_USB_ALIGN_SIZE)); + chan->ep0_state = DWC2_EP0_STATE_SETUP; + urb->errorcode = 0; + dwc2_urb_waitup(urb); + } + } else if (USB_GET_ENDPOINT_TYPE(urb->ep->bmAttributes) == USB_ENDPOINT_TYPE_ISOCHRONOUS) { + } else { + if (chan->do_ssplit && urb->transfer_buffer_length > 0) { + dwc2_bulk_intr_urb_init(bus, ch_num, urb, urb->transfer_buffer + urb->actual_length, urb->transfer_buffer_length); + } else { + urb->errorcode = 0; + dwc2_urb_waitup(urb); + } + } + } else if (chan_intstatus & USB_OTG_HCINT_AHBERR) { + urb->errorcode = -USB_ERR_IO; + dwc2_urb_waitup(urb); + } else if (chan_intstatus & USB_OTG_HCINT_STALL) { + urb->errorcode = -USB_ERR_STALL; + dwc2_urb_waitup(urb); + } else if (chan_intstatus & USB_OTG_HCINT_NAK) { + if (chan->do_ssplit) { + /* restart ssplit transfer */ + switch (USB_GET_ENDPOINT_TYPE(urb->ep->bmAttributes)) { + case USB_ENDPOINT_TYPE_CONTROL: + chan->do_csplit = 0; + dwc2_control_urb_init(bus, ch_num, urb, urb->setup, urb->transfer_buffer + urb->actual_length - 8, urb->transfer_buffer_length); + break; + case USB_ENDPOINT_TYPE_BULK: + chan->do_csplit = 0; + dwc2_bulk_intr_urb_init(bus, ch_num, urb, urb->transfer_buffer + urb->actual_length, urb->transfer_buffer_length); + break; + case USB_ENDPOINT_TYPE_INTERRUPT: + chan->do_csplit = 0; + dwc2_chan_enable_csplit(bus, ch_num, false); + urb->errorcode = -USB_ERR_NAK; + dwc2_urb_waitup(urb); + break; + + default: + break; + } + } else { + urb->errorcode = -USB_ERR_NAK; + dwc2_urb_waitup(urb); + } + } else if (chan_intstatus & USB_OTG_HCINT_ACK) { + if (chan->do_ssplit) { + /* start csplit transfer */ + chan->do_csplit = 1; + chan->ssplit_frame = dwc2_get_full_frame_num(bus); + switch (USB_GET_ENDPOINT_TYPE(urb->ep->bmAttributes)) { + case USB_ENDPOINT_TYPE_CONTROL: + dwc2_control_urb_init(bus, ch_num, urb, urb->setup, urb->transfer_buffer + urb->actual_length - 8, urb->transfer_buffer_length); + break; + case USB_ENDPOINT_TYPE_BULK: + case USB_ENDPOINT_TYPE_INTERRUPT: + dwc2_bulk_intr_urb_init(bus, ch_num, urb, urb->transfer_buffer + urb->actual_length, urb->transfer_buffer_length); + break; + + default: + break; + } + } + } else if (chan_intstatus & USB_OTG_HCINT_NYET) { + if (chan->do_ssplit) { + /* restart csplit transfer */ + chan->do_csplit = 1; + chan->ssplit_frame = dwc2_get_full_frame_num(bus); + switch (USB_GET_ENDPOINT_TYPE(urb->ep->bmAttributes)) { + case USB_ENDPOINT_TYPE_CONTROL: + dwc2_control_urb_init(bus, ch_num, urb, urb->setup, urb->transfer_buffer + urb->actual_length - 8, urb->transfer_buffer_length); + break; + case USB_ENDPOINT_TYPE_BULK: + case USB_ENDPOINT_TYPE_INTERRUPT: + dwc2_bulk_intr_urb_init(bus, ch_num, urb, urb->transfer_buffer + urb->actual_length, urb->transfer_buffer_length); + break; + + default: + break; + } + } else { + urb->errorcode = -USB_ERR_NAK; + dwc2_urb_waitup(urb); + } + } else if (chan_intstatus & USB_OTG_HCINT_TXERR) { + urb->errorcode = -USB_ERR_IO; + dwc2_urb_waitup(urb); + } else if (chan_intstatus & USB_OTG_HCINT_BBERR) { + urb->errorcode = -USB_ERR_BABBLE; + dwc2_urb_waitup(urb); + } else if (chan_intstatus & USB_OTG_HCINT_DTERR) { + urb->errorcode = -USB_ERR_DT; + dwc2_urb_waitup(urb); + } else if (chan_intstatus & USB_OTG_HCINT_FRMOR) { + urb->errorcode = -USB_ERR_IO; + dwc2_urb_waitup(urb); + } + } +} + +static void dwc2_port_irq_handler(struct usbh_bus *bus) +{ + __IO uint32_t hprt0, hprt0_dup, regval; + + /* Handle Host Port Interrupts */ + hprt0 = USB_OTG_HPRT; + hprt0_dup = USB_OTG_HPRT; + + hprt0_dup &= ~(USB_OTG_HPRT_PENA | USB_OTG_HPRT_PCDET | + USB_OTG_HPRT_PENCHNG | USB_OTG_HPRT_POCCHNG); + + /* Check whether Port Connect detected */ + if ((hprt0 & USB_OTG_HPRT_PCDET) == USB_OTG_HPRT_PCDET) { + if ((hprt0 & USB_OTG_HPRT_PCSTS) == USB_OTG_HPRT_PCSTS) { + bus->hcd.roothub.int_buffer[0] = (1 << 1); + usbh_hub_thread_wakeup(&bus->hcd.roothub); + } + hprt0_dup |= USB_OTG_HPRT_PCDET; + g_dwc2_hcd[bus->hcd.hcd_id].port_csc = 1; + } + + /* Check whether Port Enable Changed */ + if ((hprt0 & USB_OTG_HPRT_PENCHNG) == USB_OTG_HPRT_PENCHNG) { + hprt0_dup |= USB_OTG_HPRT_PENCHNG; + g_dwc2_hcd[bus->hcd.hcd_id].port_pec = 1; + + if ((hprt0 & USB_OTG_HPRT_PENA) == USB_OTG_HPRT_PENA) { + regval = USB_OTG_HOST->HFIR; + regval &= ~USB_OTG_HFIR_FRIVL; + regval |= dwc2_calc_frame_interval(bus) & USB_OTG_HFIR_FRIVL; + USB_OTG_HOST->HFIR = regval; + + if (g_dwc2_hcd[bus->hcd.hcd_id].user_params.phy_type == DWC2_PHY_TYPE_PARAM_FS) { + if ((hprt0 & USB_OTG_HPRT_PSPD) == (HPRT0_PRTSPD_LOW_SPEED << 17)) { + if ((USB_OTG_HOST->HCFG & USB_OTG_HCFG_FSLSPCS) != USB_OTG_HCFG_FSLSPCLKSEL_6_MHZ) { + regval = USB_OTG_HOST->HCFG; + regval &= ~USB_OTG_HCFG_FSLSPCS; + regval |= USB_OTG_HCFG_FSLSPCLKSEL_6_MHZ; + USB_OTG_HOST->HCFG = regval; + } + } else { + if ((USB_OTG_HOST->HCFG & USB_OTG_HCFG_FSLSPCS) != USB_OTG_HCFG_FSLSPCLKSEL_48_MHZ) { + regval = USB_OTG_HOST->HCFG; + regval &= ~USB_OTG_HCFG_FSLSPCS; + regval |= USB_OTG_HCFG_FSLSPCLKSEL_48_MHZ; + USB_OTG_HOST->HCFG = regval; + } + } + } + } else { + } + } + + /* Check for an overcurrent */ + if ((hprt0 & USB_OTG_HPRT_POCCHNG) == USB_OTG_HPRT_POCCHNG) { + hprt0_dup |= USB_OTG_HPRT_POCCHNG; + g_dwc2_hcd[bus->hcd.hcd_id].port_occ = 1; + } + /* Clear Port Interrupts */ + USB_OTG_HPRT = hprt0_dup; +} + +void USBH_IRQHandler(uint8_t busid) +{ + uint32_t gint_status, chan_int; + struct usbh_bus *bus; + + bus = &g_usbhost_bus[busid]; + gint_status = dwc2_get_glb_intstatus(bus); + if ((USB_OTG_GLB->GINTSTS & 0x1U) == USB_OTG_MODE_HOST) { + /* Avoid spurious interrupt */ + if (gint_status == 0) { + return; + } + + if (gint_status & USB_OTG_GINTSTS_HPRTINT) { + dwc2_port_irq_handler(bus); + } + if (gint_status & USB_OTG_GINTSTS_DISCINT) { + g_dwc2_hcd[bus->hcd.hcd_id].port_csc = 1; + bus->hcd.roothub.int_buffer[0] = (1 << 1); + usbh_hub_thread_wakeup(&bus->hcd.roothub); + + USB_OTG_GLB->GINTSTS = USB_OTG_GINTSTS_DISCINT; + } + if (gint_status & USB_OTG_GINTSTS_HCINT) { + chan_int = (USB_OTG_HOST->HAINT & USB_OTG_HOST->HAINTMSK) & 0xFFFFU; + for (uint8_t i = 0U; i < g_dwc2_hcd[bus->hcd.hcd_id].hw_params.host_channels; i++) { + if ((chan_int & (1UL << (i & 0xFU))) != 0U) { + if ((USB_OTG_HC(i)->HCCHAR & USB_OTG_HCCHAR_EPDIR) == USB_OTG_HCCHAR_EPDIR) { + dwc2_inchan_irq_handler(bus, i); + } else { + dwc2_outchan_irq_handler(bus, i); + } + } + } + USB_OTG_GLB->GINTSTS = USB_OTG_GINTSTS_HCINT; + } + } +} \ No newline at end of file diff --git a/kernel/cherryusb/port/ehci/README.md b/kernel/cherryusb/port/ehci/README.md new file mode 100644 index 0000000..753fc44 --- /dev/null +++ b/kernel/cherryusb/port/ehci/README.md @@ -0,0 +1,38 @@ +# Note + +## Support Chip List + +### BouffaloLab + +- BouffaloLab BL616/BL808 (bouffalolab + EHCI) + +### HPMicro + +- HPM all series (hpmicro + EHCI) + +### AllwinnerTech + +- F133/T113 + +### Nuvoton + +- Nuvoton all series + +### Artinchip + +- d13x, d21x + +### NXP + +Modify USB_NOCACHE_RAM_SECTION + +``` +#define USB_NOCACHE_RAM_SECTION __attribute__((section(".NonCacheable"))) +``` + +- IMRT10XX/IMRT11XX (chipidea + EHCI) +- MCXN9XX/MCXN236 (chipidea + EHCI) + +### Intel + +- Intel 6 Series Chipset and Intel C200 Series Chipset diff --git a/kernel/cherryusb/port/ehci/usb_ehci_reg.h b/kernel/cherryusb/port/ehci/usb_ehci_reg.h new file mode 100644 index 0000000..3c797a6 --- /dev/null +++ b/kernel/cherryusb/port/ehci/usb_ehci_reg.h @@ -0,0 +1,393 @@ +/**************************************************************************** + * include/nuttx/usb/ehci.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ +/* + * Copyright 2022 sakumisu + * + * SPDX-License-Identifier: Apache-2.0 + */ +#ifndef __INCLUDE_NUTTX_USB_EHCI_H +#define __INCLUDE_NUTTX_USB_EHCI_H + +#define EHCI_FULL_SPEED (0) /* Full-Speed (12Mbs) */ +#define EHCI_LOW_SPEED (1) /* Low-Speed (1.5Mbs) */ +#define EHCI_HIGH_SPEED (2) /* High-Speed (480 Mb/s) */ + +/* Host Controller Capability Register Bit Definitions **********************/ + +/* Structural Parameters. Paragraph 2.2.3 */ + +#define EHCI_HCSPARAMS_NPORTS_SHIFT (0) /* Bit 0-3: Number of physical downstream ports */ +#define EHCI_HCSPARAMS_NPORTS_MASK (15 << EHCI_HCSPARAMS_NPORTS_SHIFT) +#define EHCI_HCSPARAMS_PPC (1 << 4) /* Bit 4: Port Power Control */ +#define EHCI_HCSPARAMS_PRR (1 << 7) /* Bit 7: Port Routing Rules */ +#define EHCI_HCSPARAMS_NPCC_SHIFT (8) /* Bit 8-11: Number of Ports per Companion Controller */ +#define EHCI_HCSPARAMS_NPCC_MASK (15 << EHCI_HCSPARAMS_NPCC_SHIFT) +#define EHCI_HCSPARAMS_NCC_SHIFT (12) /* Bit 12-15: Number of Companion Controllers */ +#define EHCI_HCSPARAMS_NCC_MASK (15 << EHCI_HCSPARAMS_NCC_SHIFT) +#define EHCI_HCSPARAMS_PIND (1 << 16) /* Bit 16: Port Indicators */ +#define EHCI_HCSPARAMS_DBGPORT_SHIFT (20) /* Bit 20-23: Debug Port Number */ +#define EHCI_HCSPARAMS_DBGPORT_MASK (15 << EHCI_HCSPARAMS_DBGPORT_SHIFT) + +/* Capability Parameters. Paragraph 2.2.4 */ + +#define EHCI_HCCPARAMS_64BIT (1 << 0) /* Bit 0: 64-bit Addressing Capability */ +#define EHCI_HCCPARAMS_PFLF (1 << 1) /* Bit 1: Programmable Frame List Flag */ +#define EHCI_HCCPARAMS_ASPC (1 << 2) /* Bit 2: Asynchronous Schedule Park Capability */ +#define EHCI_HCCPARAMS_IST_SHIFT (4) /* Bits 4-7: Isochronous Scheduling Threshold */ +#define EHCI_HCCPARAMS_IST_MASK (15 << EHCI_HCCPARAMS_IST_SHIFT) +#define EHCI_HCCPARAMS_EECP_SHIFT (8) /* Bits 8-15: EHCI Extended Capabilities Pointer */ +#define EHCI_HCCPARAMS_EECP_MASK (0xff << EHCI_HCCPARAMS_EECP_SHIFT) + +/* Host Controller Operational Register Bit Definitions *********************/ + +/* USB Command. Paragraph 2.3.1 */ + +#define EHCI_USBCMD_RUN (1 << 0) /* Bit 0: Run/Stop */ +#define EHCI_USBCMD_HCRESET (1 << 1) /* Bit 1: Host Controller Reset */ +#define EHCI_USBCMD_FLSIZE_SHIFT (2) /* Bits 2-3: Frame List Size */ +#define EHCI_USBCMD_FLSIZE_MASK (3 << EHCI_USBCMD_FLSIZE_SHIFT) +#define EHCI_USBCMD_FLSIZE_1024 (0 << EHCI_USBCMD_FLSIZE_SHIFT) /* 1024 elements (4096 bytes) */ +#define EHCI_USBCMD_FLSIZE_512 (1 << EHCI_USBCMD_FLSIZE_SHIFT) /* 512 elements (2048 bytes) */ +#define EHCI_USBCMD_FLSIZE_256 (2 << EHCI_USBCMD_FLSIZE_SHIFT) /* 256 elements (1024 bytes) */ +#define EHCI_USBCMD_PSEN (1 << 4) /* Bit 4: Periodic Schedule Enable */ +#define EHCI_USBCMD_ASEN (1 << 5) /* Bit 5: Asynchronous Schedule Enable */ +#define EHCI_USBCMD_IAAD (1 << 6) /* Bit 6: Interrupt on Async Advance Doorbell */ +#define EHCI_USBCMD_LRESET (1 << 7) /* Bit 7: Light Host Controller Reset */ +#define EHCI_USBCMD_ASYNC_PARKCNT_SHIFT (8) /* Bits 8-9: Asynchronous Schedule Park Mode Count */ +#define EHCI_USBCMD_ASYNC_PARKCNT_MASK (3 << EHCI_USBCMD_ASYNC_PARKCNT_SHIFT) +#define EHCI_USBCMD_ASYNC_PARK (1 << 11) /* Bit 11: Asynchronous Schedule Park Mode Enable */ +#define EHCI_USBCMD_ITHRE_SHIFT (16) /* Bits 16-23: Interrupt Threshold Control */ +#define EHCI_USBCMD_ITHRE_MASK (0xff << EHCI_USBCMD_ITHRE_SHIFT) +#define EHCI_USBCMD_ITHRE_1MF (0x01 << EHCI_USBCMD_ITHRE_SHIFT) /* 1 micro-frame */ +#define EHCI_USBCMD_ITHRE_2MF (0x02 << EHCI_USBCMD_ITHRE_SHIFT) /* 2 micro-frames */ +#define EHCI_USBCMD_ITHRE_4MF (0x04 << EHCI_USBCMD_ITHRE_SHIFT) /* 4 micro-frames */ +#define EHCI_USBCMD_ITHRE_8MF (0x08 << EHCI_USBCMD_ITHRE_SHIFT) /* 8 micro-frames (default, 1 ms) */ +#define EHCI_USBCMD_ITHRE_16MF (0x10 << EHCI_USBCMD_ITHRE_SHIFT) /* 16 micro-frames (2 ms) */ +#define EHCI_USBCMD_ITHRE_32MF (0x20 << EHCI_USBCMD_ITHRE_SHIFT) /* 32 micro-frames (4 ms) */ +#define EHCI_USBCMD_ITHRE_64MF (0x40 << EHCI_USBCMD_ITHRE_SHIFT) /* 64 micro-frames (8 ms) */ + +/* USB Status. Paragraph 2.3.2 */ + +#define EHCI_USBSTS_INT (1 << 0) /* Bit 0: USB Interrupt */ +#define EHCI_USBSTS_ERR (1 << 1) /* Bit 1: USB Error Interrupt */ +#define EHCI_USBSTS_PCD (1 << 2) /* Bit 2: Port Change Detect */ +#define EHCI_USBSTS_FLR (1 << 3) /* Bit 3: Frame List Rollover */ +#define EHCI_USBSTS_FATAL (1 << 4) /* Bit 4: Host System Error */ +#define EHCI_USBSTS_IAA (1 << 5) /* Bit 5: Interrupt on Async Advance */ +#define EHCI_USBSTS_HALTED (1 << 12) /* Bit 12: HC Halted */ +#define EHCI_USBSTS_RECLAM (1 << 13) /* Bit 13: Reclamation */ +#define EHCI_USBSTS_PSS (1 << 14) /* Bit 14: Periodic Schedule Status */ +#define EHCI_USBSTS_ASS (1 << 15) /* Bit 15: Asynchronous Schedule Status */ + /* Bits 16-31: Reserved */ + +/* USB Interrupt Enable. Paragraph 2.3.3 */ + +#define EHCI_USBIE_INT (1 << 0) /* Bit 0: USB Interrupt */ +#define EHCI_USBIE_ERR (1 << 1) /* Bit 1: USB Error Interrupt */ +#define EHCI_USBIE_PCD (1 << 2) /* Bit 2: Port Change Detect */ +#define EHCI_USBIE_FLROLL (1 << 3) /* Bit 3: Frame List Rollover */ +#define EHCI_USBIE_FATAL (1 << 4) /* Bit 4: Host System Error */ +#define EHCI_USBIE_IAA (1 << 5) /* Bit 5: Interrupt on Async Advance */ +#define EHCI_USBIE_ALLINTS (0x3f) /* Bits 0-5: All interrupts */ + +/* USB Frame Index. Paragraph 2.3.4 */ + +#define EHCI_FRINDEX_MASK (0x3fff) /* Bits 0-13: Frame index */ + +/* 4G Segment Selector. + * Paragraph 2.3.5, Bits[64:32] of data structure addresses + */ + +/* Frame List Base Address. Paragraph 2.3.6 */ +#define EHCI_PERIODICLISTBASE_MASK (0xfffff000) /* Bits 12-31: Base Address (Low) */ + +/* Next Asynchronous List Address. Paragraph 2.3.7 */ + +#define EHCI_ASYNCLISTADDR_MASK (0xffffffe0) /* Bits 5-31: Link Pointer Low (LPL) */ + +/* Configured Flag Register. Paragraph 2.3.8 */ + +#define EHCI_CONFIGFLAG (1 << 0) /* Bit 0: Configure Flag */ + +/* Port Status/Control, Port 1-n. Paragraph 2.3.9 */ + +#define EHCI_PORTSC_CCS (1 << 0) /* Bit 0: Current Connect Status */ +#define EHCI_PORTSC_CSC (1 << 1) /* Bit 1: Connect Status Change */ +#define EHCI_PORTSC_PE (1 << 2) /* Bit 2: Port Enable */ +#define EHCI_PORTSC_PEC (1 << 3) /* Bit 3: Port Enable/Disable Change */ +#define EHCI_PORTSC_OCA (1 << 4) /* Bit 4: Over-current Active */ +#define EHCI_PORTSC_OCC (1 << 5) /* Bit 5: Over-current Change */ +#define EHCI_PORTSC_RESUME (1 << 6) /* Bit 6: Force Port Resume */ +#define EHCI_PORTSC_SUSPEND (1 << 7) /* Bit 7: Suspend */ +#define EHCI_PORTSC_RESET (1 << 8) /* Bit 8: Port Reset */ +#define EHCI_PORTSC_LSTATUS_SHIFT (10) /* Bits 10-11: Line Status */ +#define EHCI_PORTSC_LSTATUS_MASK (3 << EHCI_PORTSC_LSTATUS_SHIFT) +#define EHCI_PORTSC_LSTATUS_SE0 (0 << EHCI_PORTSC_LSTATUS_SHIFT) /* SE0 Not Low-speed device, perform EHCI reset */ +#define EHCI_PORTSC_LSTATUS_KSTATE (1 << EHCI_PORTSC_LSTATUS_SHIFT) /* K-state Low-speed device, release ownership of port */ +#define EHCI_PORTSC_LSTATUS_JSTATE (2 << EHCI_PORTSC_LSTATUS_SHIFT) /* J-state Not Low-speed device, perform EHCI reset */ +#define EHCI_PORTSC_PP (1 << 12) /* Bit 12: Port Power */ +#define EHCI_PORTSC_OWNER (1 << 13) /* Bit 13: Port Owner */ +#define EHCI_PORTSC_PIC_SHIFT (14) /* Bits 14-15: Port Indicator Control */ +#define EHCI_PORTSC_PIC_MASK (3 << EHCI_PORTSC_PIC_SHIFT) +#define EHCI_PORTSC_PIC_OFF (0 << EHCI_PORTSC_PIC_SHIFT) /* Port indicators are off */ +#define EHCI_PORTSC_PIC_AMBER (1 << EHCI_PORTSC_PIC_SHIFT) /* Amber */ +#define EHCI_PORTSC_PIC_GREEN (2 << EHCI_PORTSC_PIC_SHIFT) /* Green */ +#define EHCI_PORTSC_PTC_SHIFT (16) /* Bits 16-19: Port Test Control */ +#define EHCI_PORTSC_PTC_MASK (15 << EHCI_PORTSC_PTC_SHIFT) +#define EHCI_PORTSC_PTC_DISABLED (0 << EHCI_PORTSC_PTC_SHIFT) /* Test mode not enabled */ +#define EHCI_PORTSC_PTC_JSTATE (1 << EHCI_PORTSC_PTC_SHIFT) /* Test J_STATE */ +#define EHCI_PORTSC_PTC_KSTATE (2 << EHCI_PORTSC_PTC_SHIFT) /* Test K_STATE */ +#define EHCI_PORTSC_PTC_SE0NAK (3 << EHCI_PORTSC_PTC_SHIFT) /* Test SE0_NAK */ +#define EHCI_PORTSC_PTC_PACKET (4 << EHCI_PORTSC_PTC_SHIFT) /* Test Packet */ +#define EHCI_PORTSC_PTC_ENABLE (5 << EHCI_PORTSC_PTC_SHIFT) /* Test FORCE_ENABLE */ +#define EHCI_PORTSC_WKCCNTE (1 << 20) /* Bit 20: Wake on Connect Enable */ +#define EHCI_PORTSC_WKDSCNNTE (1 << 21) /* Bit 21: Wake on Disconnect Enable */ +#define EHCI_PORTSC_WKOCE (1 << 22) /* Bit 22: Wake on Over-current Enable */ + /* Bits 23-31: Reserved */ + +#define EHCI_PORTSC_ALLINTS (EHCI_PORTSC_CSC | EHCI_PORTSC_PEC | \ + EHCI_PORTSC_OCC | EHCI_PORTSC_RESUME) + +/* Queue Head. Paragraph 3.6 */ + +/* Queue Head Horizontal Link Pointer: Queue Head DWord 0. Table 3-19 */ + +#define QH_HLP_END 0x1 + +#define QH_HLP_ITD(x) (((uintptr_t)(x) & ~0x1F) | 0x0) /* Isochronous Transfer Descriptor */ +#define QH_HLP_QH(x) (((uintptr_t)(x) & ~0x1F) | 0x2) /* Queue Head */ +#define QH_HLP_SITD(x) (((uintptr_t)(x) & ~0x1F) | 0x4) /* Split Transaction Isochronous Transfer Descriptor */ +#define QH_HLP_FSTN(x) (((uintptr_t)(x) & ~0x1F) | 0x6) /* Frame Span Traversal Node */ + +/* Endpoint Characteristics: Queue Head DWord 1. Table 3-19 */ + +#define QH_EPCHAR_DEVADDR_SHIFT (0) /* Bitx 0-6: Device Address */ +#define QH_EPCHAR_DEVADDR_MASK (0x7f << QH_EPCHAR_DEVADDR_SHIFT) +#define QH_EPCHAR_I (1 << 7) /* Bit 7: Inactivate on Next Transaction */ +#define QH_EPCHAR_ENDPT_SHIFT (8) /* Bitx 8-11: Endpoint Number */ +#define QH_EPCHAR_ENDPT_MASK (15 << QH_EPCHAR_ENDPT_SHIFT) +#define QH_EPCHAR_EPS_SHIFT (12) /* Bitx 12-13: Endpoint Speed */ +#define QH_EPCHAR_EPS_MASK (3 << QH_EPCHAR_EPS_SHIFT) +#define QH_EPCHAR_EPS_FULL (0 << QH_EPCHAR_EPS_SHIFT) /* Full-Speed (12Mbs) */ +#define QH_EPCHAR_EPS_LOW (1 << QH_EPCHAR_EPS_SHIFT) /* Low-Speed (1.5Mbs) */ +#define QH_EPCHAR_EPS_HIGH (2 << QH_EPCHAR_EPS_SHIFT) /* High-Speed (480 Mb/s) */ +#define QH_EPCHAR_DTC (1 << 14) /* Bit 14: Data Toggle Control */ +#define QH_EPCHAR_H (1 << 15) /* Bit 15: Head of Reclamation List Flag */ +#define QH_EPCHAR_MAXPKT_SHIFT (16) /* Bitx 16-26: Maximum Packet Length */ +#define QH_EPCHAR_MAXPKT_MASK (0x7ff << QH_EPCHAR_MAXPKT_SHIFT) +#define QH_EPCHAR_C (1 << 27) /* Bit 27: Control Endpoint Flag */ +#define QH_EPCHAR_RL_SHIFT (28) /* Bitx 28-31: Nak Count Reload */ +#define QH_EPCHAR_RL_MASK (15 << QH_EPCHAR_RL_SHIFT) + +/* Endpoint Capabilities: Queue Head DWord 2. Table 3-20 */ + +#define QH_EPCAPS_SSMASK_SHIFT (0) /* Bitx 0-7: Interrupt Schedule Mask (Frame S-mask) */ +#define QH_EPCAPS_SSMASK_MASK (0xff << QH_EPCAPS_SSMASK_SHIFT) +#define QH_EPCAPS_SSMASK(n) ((n) << QH_EPCAPS_SSMASK_SHIFT) +#define QH_EPCAPS_SCMASK_SHIFT (8) /* Bitx 8-15: Split Completion Mask (Frame C-Mask) */ +#define QH_EPCAPS_SCMASK_MASK (0xff << QH_EPCAPS_SCMASK_SHIFT) +#define QH_EPCAPS_SCMASK(n) ((n) << QH_EPCAPS_SCMASK_SHIFT) +#define QH_EPCAPS_HUBADDR_SHIFT (16) /* Bitx 16-22: Hub Address */ +#define QH_EPCAPS_HUBADDR_MASK (0x7f << QH_EPCAPS_HUBADDR_SHIFT) +#define QH_EPCAPS_HUBADDR(n) ((n) << QH_EPCAPS_HUBADDR_SHIFT) +#define QH_EPCAPS_PORT_SHIFT (23) /* Bit 23-29: Port Number */ +#define QH_EPCAPS_PORT_MASK (0x7f << QH_EPCAPS_PORT_SHIFT) +#define QH_EPCAPS_PORT(n) ((n) << QH_EPCAPS_PORT_SHIFT) +#define QH_EPCAPS_MULT_SHIFT (30) /* Bit 30-31: High-Bandwidth Pipe Multiplier */ +#define QH_EPCAPS_MULT_MASK (3 << QH_EPCAPS_MULT_SHIFT) +#define QH_EPCAPS_MULT(n) ((n) << QH_EPCAPS_MULT_SHIFT) + +/* qTD Token. Paragraph 3.5.3 */ + +#define QTD_LIST_END 1 + +#define QTD_TOKEN_STATUS_SHIFT (0) /* Bits 0-7: Status */ +#define QTD_TOKEN_STATUS_MASK (0xff << QTD_TOKEN_STATUS_SHIFT) +#define QTD_TOKEN_STATUS_PINGSTATE (1 << 0) /* Bit 0 Ping State */ +#define QTD_TOKEN_STATUS_ERR (1 << 0) /* Bit 0 Error */ +#define QTD_TOKEN_STATUS_SPLITXSTATE (1 << 1) /* Bit 1 Split Transaction State */ +#define QTD_TOKEN_STATUS_MMF (1 << 2) /* Bit 2 Missed Micro-Frame */ +#define QTD_TOKEN_STATUS_XACTERR (1 << 3) /* Bit 3 Transaction Error */ +#define QTD_TOKEN_STATUS_BABBLE (1 << 4) /* Bit 4 Babble Detected */ +#define QTD_TOKEN_STATUS_DBERR (1 << 5) /* Bit 5 Data Buffer Error */ +#define QTD_TOKEN_STATUS_HALTED (1 << 6) /* Bit 6 Halted */ +#define QTD_TOKEN_STATUS_ACTIVE (1 << 7) /* Bit 7 Active */ +#define QTD_TOKEN_STATUS_ERRORS (0x78 << QTD_TOKEN_STATUS_SHIFT) +#define QTD_TOKEN_PID_SHIFT (8) /* Bits 8-9: PID Code */ +#define QTD_TOKEN_PID_MASK (3 << QTD_TOKEN_PID_SHIFT) +#define QTD_TOKEN_PID_OUT (0 << QTD_TOKEN_PID_SHIFT) /* OUT Token generates token (E1H) */ +#define QTD_TOKEN_PID_IN (1 << QTD_TOKEN_PID_SHIFT) /* IN Token generates token (69H) */ +#define QTD_TOKEN_PID_SETUP (2 << QTD_TOKEN_PID_SHIFT) /* SETUP Token generates token (2DH) */ +#define QTD_TOKEN_CERR_SHIFT (10) /* Bits 10-11: Error Counter */ +#define QTD_TOKEN_CERR_MASK (3 << QTD_TOKEN_CERR_SHIFT) +#define QTD_TOKEN_CPAGE_SHIFT (12) /* Bits 12-14: Current Page */ +#define QTD_TOKEN_CPAGE_MASK (7 << QTD_TOKEN_CPAGE_SHIFT) +#define QTD_TOKEN_IOC (1 << 15) /* Bit 15: Interrupt On Complete */ +#define QTD_TOKEN_NBYTES_SHIFT (16) /* Bits 16-30: Total Bytes to Transfer */ +#define QTD_TOKEN_NBYTES_MASK (0x7fff << QTD_TOKEN_NBYTES_SHIFT) +#define QTD_TOKEN_TOGGLE (1 << 31) /* Bit 31: Data Toggle */ + +/* Isochronous (High-Speed) Transfer Descriptor (iTD). Paragraph 3.3 */ + +/* iTD Next Link Pointer. Paragraph 3.3.1 */ + +#define ITD_NLP_ITD(x) (((uintptr_t)(x) & ~0x1F) | 0x0) +#define ITD_NLP_QH(x) (((uintptr_t)(x) & ~0x1F) | 0x2) +#define ITD_NLP_SITD(x) (((uintptr_t)(x) & ~0x1F) | 0x4) +#define ITD_NLP_FSTN(x) (((uintptr_t)(x) & ~0x1F) | 0x6) + +/* iTD Transaction Status and Control List. Paragraph 3.3.2 */ +#define ITD_TSCL_XOFFS_SHIFT (0) /* Bits 0-11: Transaction X offset */ +#define ITD_TSCL_XOFFS_MASK (0xfff << ITD_TSCL_XOFFS_SHIFT) +#define ITD_TSCL_PG_SHIFT (12) /* Bits 12-14: Page select */ +#define ITD_TSCL_PG_MASK (7 << ITD_TSCL_PG_SHIFT) +#define ITD_TSCL_IOC (1 << 15) /* Bit 15: Interrupt On Comp */ +#define ITD_TSCL_LENGTH_SHIFT (16) /* Bits 16-27: Transaction length */ +#define ITD_TSCL_LENGTH_MASK (0xfff << ITD_TSCL_LENGTH_SHIFT) +#define ITD_TSCL_STATUS_SHIFT (28) /* Bits 28-31: Transaction status */ +#define ITD_TSCL_STATUS_MASK (15 << ITD_TSCL_STATUS_SHIFT) +#define ITD_TSCL_STATUS_XACTERR (1 << 28) /* Bit 28: Transaction error */ +#define ITD_TSCL_STATUS_BABBLE (1 << 29) /* Bit 29: Babble Detected */ +#define ITD_TSCL_STATUS_DBERROR (1 << 30) /* Bit 30: Data Buffer Error */ +#define ITD_TSCL_STATUS_ACTIVE (1 << 31) /* Bit 31: Active error */ + +/* iTD Buffer Page Pointer List. Paragraph 3.3.4 */ + +/* iTD Buffer Pointer Page 0. Table 3-4 */ + +#define ITD_BUFPTR0_DEVADDR_SHIFT (0) /* Bits 0-6: Device Address */ +#define ITD_BUFPTR0_DEVADDR_MASK (0x7f << ITD_BUFPTR0_DEVADDR_SHIFT) +#define ITD_BUFPTR0_ENDPT_SHIFT (8) /* Bits 8-11: Endpoint Number */ +#define ITD_BUFPTR0_ENDPT_MASK (15 << ITD_BUFPTR0_ENDPT_SHIFT) + +/* iTD Buffer Pointer Page 1. Table 3-5 */ + +#define ITD_BUFPTR1_MAXPKT_SHIFT (0) /* Bits 0-10: Maximum Packet Size */ +#define ITD_BUFPTR1_MAXPKT_MASK (0x7ff << ITD_BUFPTR1_MAXPKT_SHIFT) +#define ITD_BUFPTR1_DIRIN (1 << 11) /* Bit 11: Direction 1=IN */ +#define ITD_BUFPTR1_DIROUT (0) /* Bit 11: Direction 0=OUT */ + +/* iTD Buffer Pointer Page 2. Table 3-6 */ + +#define ITD_BUFPTR2_MULTI_SHIFT (0) /* Bits 0-1: Multi */ +#define ITD_BUFPTR2_MULTI_MASK (3 << ITD_BUFPTR2_MULTI_SHIFT) +#define ITD_BUFPTR2_MULTI_1 (1 << ITD_BUFPTR2_MULTI_SHIFT) /* One transaction per micro-frame */ +#define ITD_BUFPTR2_MULTI_2 (2 << ITD_BUFPTR2_MULTI_SHIFT) /* Two transactions per micro-frame */ +#define ITD_BUFPTR2_MULTI_3 (3 << ITD_BUFPTR2_MULTI_SHIFT) /* Three transactions per micro-frame */ + +/* Registers ****************************************************************/ + +/* Host Controller Capability Registers. + * This register block must be positioned at a well known address. + */ + +struct ehci_hccr { + volatile uint8_t caplength; /* 0x00: Capability Register Length */ + volatile uint8_t reserved; /* 0x01: reserved */ + volatile uint16_t hciversion; /* 0x02: Interface Version Number */ + volatile uint32_t hcsparams; /* 0x04: Structural Parameters */ + volatile uint32_t hccparams; /* 0x08: Capability Parameters */ + volatile uint8_t hcspportroute[8]; /* 0x0c: Companion Port Route Description */ +}; + +/* Host Controller Operational Registers. + * This register block is positioned at an offset of 'caplength' from the + * beginning of the Host Controller Capability Registers. + */ + +struct ehci_hcor { + volatile uint32_t usbcmd; /* 0x00: USB Command */ + volatile uint32_t usbsts; /* 0x04: USB Status */ + volatile uint32_t usbintr; /* 0x08: USB Interrupt Enable */ + volatile uint32_t frindex; /* 0x0c: USB Frame Index */ + volatile uint32_t ctrldssegment; /* 0x10: 4G Segment Selector */ + volatile uint32_t periodiclistbase; /* 0x14: Frame List Base Address */ + volatile uint32_t asynclistaddr; /* 0x18: Next Asynchronous List Address */ +#ifndef CONFIG_USB_EHCI_HCOR_RESERVED_DISABLE + uint32_t reserved[9]; +#endif + volatile uint32_t configflag; /* 0x40: Configured Flag Register */ + volatile uint32_t portsc[15]; /* 0x44: Port Status/Control */ +}; + +/* USB2 Debug Port Register Interface. + * This register block is normally found via the PCI capabalities. + * In non-PCI implementions, you need apriori information about the + * location of these registers. + */ + +struct ehci_debug { + uint32_t psc; /* 0x00: Debug Port Control/Status Register */ + uint32_t pids; /* 0x04: Debug USB PIDs Register */ + uint32_t data[2]; /* 0x08: Debug Data buffer Registers */ + uint32_t addr; /* 0x10: Device Address Register */ +}; + +/* Data Structures **********************************************************/ + +/* Queue Element Transfer Descriptor (qTD). Paragraph 3.5 */ + +struct ehci_qtd { + uint32_t next_qtd; /* 0x00-0x03: Next qTD Pointer */ + uint32_t alt_next_qtd; /* 0x04-0x07: Alternate Next qTD Pointer */ + uint32_t token; /* 0x08-0x0b: qTD Token */ + uint32_t bpl[5]; /* 0x0c-0x1c: Buffer Page Pointer List */ +}; + +#define SIZEOF_EHCI_QTD (32) /* 8*sizeof(uint32_t) */ + +/* Queue Head. Paragraph 3.6 */ + +struct ehci_qh { + uint32_t hlp; /* 0x00-0x03: Queue Head Horizontal Link Pointer */ + uint32_t epchar; /* 0x04-0x07: Endpoint Characteristics */ + uint32_t epcap; /* 0x08-0x0b: Endpoint Capabilities */ + uint32_t curr_qtd; /* 0x0c-0x0f: Current qTD Pointer */ + struct ehci_qtd overlay; /* 0x10-0x2c: Transfer overlay */ +}; + +#define SIZEOF_EHCI_QH (48) /* 4*sizeof(uint32_t) + 32 */ + +/* Isochronous (High-Speed) Transfer Descriptor (iTD). + * Paragraph 3.3. Must be aligned to 32-byte boundaries. + */ + +struct ehci_itd { + uint32_t nlp; /* 0x00-0x03: Next link pointer */ + uint32_t tscl[8]; /* 0x04-0x23: Transaction Status and Control List */ + uint32_t bpl[7]; /* 0x24-0x3c: Buffer Page Pointer List */ +}; + +#define SIZEOF_EHCI_ITD (64) /* 16*sizeof(uint32_t) */ + +/* Split Transaction Isochronous Transfer Descriptor (siTD). Paragraph 3.4 */ + +struct ehci_sitd { + uint32_t nlp; /* 0x00-0x03: Next link pointer */ + uint32_t epchar; /* 0x04-0x07: Endpoint and Transaction Translator Characteristics */ + uint32_t mfsc; /* 0x08-0x0b: Micro-frame Schedule Control */ + uint32_t tsc; /* 0x0c-0x0f: Transfer Status and Control */ + uint32_t bpl[2]; /* 0x10-0x17: Buffer Pointer List */ + uint32_t blp; /* 0x18-0x1b: Back link pointer */ +}; + +#define SIZEOF_EHCI_SITD (28) /* 7*sizeof(uint32_t) */ + +#endif /* __INCLUDE_NUTTX_USB_EHCI_H */ diff --git a/kernel/cherryusb/port/ehci/usb_glue_aic.c b/kernel/cherryusb/port/ehci/usb_glue_aic.c new file mode 100644 index 0000000..30a6beb --- /dev/null +++ b/kernel/cherryusb/port/ehci/usb_glue_aic.c @@ -0,0 +1,173 @@ +/* + * Copyright (c) 2022, Artinchip Technology Co., Ltd + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include +#include "usbh_core.h" +#include "usb_hc_ehci.h" +#include "usb_hc_ohci.h" + +#if !defined(CONFIG_USB_EHCI_CONFIGFLAG) +#error "aic ehci must define CONFIG_USB_EHCI_CONFIGFLAG" +#endif + +#if !defined(CONFIG_USB_EHCI_WITH_OHCI) +#error "aic must define CONFIG_USB_EHCI_WITH_OHCI for ls/fs device" +#endif + +#if CONFIG_USB_OHCI_HCOR_OFFSET != 0x400 +#error "aic CONFIG_USB_OHCI_HCOR_OFFSET must be 0x400" +#endif + +extern void USBH_IRQHandler(uint8_t busid); + +static void aic_ehci_isr(int vector, void *arg) +{ + struct usbh_bus *bus = (struct usbh_bus *)arg; + extern void USBH_IRQHandler(uint8_t busid); + USBH_IRQHandler(bus->hcd.hcd_id); +} + +static void aic_ohci_isr(int vector, void *arg) +{ + struct usbh_bus *bus = (struct usbh_bus *)arg; + extern void OHCI_IRQHandler(uint8_t busid); + OHCI_IRQHandler(bus->hcd.hcd_id); +} + +typedef struct aic_ehci_config { + uint32_t base_addr; + uint32_t clk_id; + uint32_t rst_id; + uint32_t phy_clk_id; + uint32_t phy_rst_id; + uint32_t irq_num; +} aic_ehci_config_t; + +aic_ehci_config_t config[] = { +#ifdef AIC_USING_USB0_HOST + { USB_HOST0_BASE, + CLK_USBH0, + RESET_USBH0, + CLK_USB_PHY0, + RESET_USBPHY0, + USB_HOST0_EHCI_IRQn }, +#else + { 0xFFFFFFFF, + 0xFFFFFFFF, + 0xFFFFFFFF, + 0xFFFFFFFF, + 0xFFFFFFFF, + 0xFFFFFFFF }, +#endif +#ifdef AIC_USING_USB1_HOST + { USB_HOST1_BASE, + CLK_USBH1, + RESET_USBH1, + CLK_USB_PHY1, + RESET_USBPHY1, + USB_HOST1_EHCI_IRQn } +#endif +}; + +void usb_hc_low_level_init(struct usbh_bus *bus) +{ + uint32_t val; + int i = 0; + + for (i = 0; i < sizeof(config) / sizeof(aic_ehci_config_t); i++) { + if (bus->hcd.reg_base == config[i].base_addr) + break; + } + + if (i == sizeof(config) / sizeof(aic_ehci_config_t)) + return; + + /* set usb0 phy switch: Host/Device */ + if (i == 0) + syscfg_usb_phy0_sw_host(1); + + /* enable clock */ + hal_clk_enable(config[i].phy_clk_id); + hal_clk_enable(config[i].clk_id); + aicos_udelay(300); + hal_reset_assert(config[i].phy_rst_id); + hal_reset_assert(config[i].rst_id); + aicos_udelay(300); + hal_reset_deassert(config[i].phy_rst_id); + hal_reset_deassert(config[i].rst_id); + aicos_udelay(300); + + /* set phy type: UTMI/ULPI */ + val = readl((volatile void *)(unsigned long)(config[i].base_addr + 0x800)); +#ifdef FPGA_BOARD_ARTINCHIP + /* fpga phy type = ULPI */ + writel((val & ~0x1U), (volatile void *)(unsigned long)(config[i].base_addr + 0x800)); +#else + /* board phy type = UTMI */ + writel((val | 0x1), (volatile void *)(unsigned long)(config[i].base_addr + 0x800)); +#endif + + /* Set AHB2STBUS_INSREG01 + Set EHCI packet buffer IN/OUT threshold (in DWORDs) + Must increase the OUT threshold to avoid underrun. (FIFO size - 4) + */ + writel((32 | (127 << 16)), (volatile void *)(unsigned long)(config[i].base_addr + 0x94)); + + /* register interrupt callback */ + aicos_request_irq(config[i].irq_num, (irq_handler_t)aic_ehci_isr, + 0, "usb_host_ehci", bus); + aicos_request_irq(config[i].irq_num + 1, (irq_handler_t)aic_ohci_isr, + 0, "usb_host_ohci", bus); + aicos_irq_enable(config[i].irq_num); + aicos_irq_enable(config[i].irq_num + 1); +} + +uint8_t usbh_get_port_speed(struct usbh_bus *bus, const uint8_t port) +{ + return USB_SPEED_HIGH; +} + +void usb_ehci_dcache_clean(uintptr_t addr, uint32_t len) +{ + aicos_dcache_clean_range((size_t *)addr, len); +} + +void usb_ehci_dcache_invalidate(uintptr_t addr, uint32_t len) +{ + aicos_dcache_invalid_range((size_t *)addr, len); +} + +void usb_ehci_dcache_clean_invalidate(uintptr_t addr, uint32_t len) +{ + aicos_dcache_clean_invalid_range((size_t *)addr, len); +} + +int __usbh_init(void) +{ +#if defined(AIC_USING_USB0_HOST) || defined(AIC_USING_USB1_HOST) + int bus_id = 0; +#endif + +#ifdef AIC_USING_USB0_HOST + usbh_initialize(bus_id, USB_HOST0_BASE, NULL); + bus_id++; +#endif + +#ifdef AIC_USING_USB1_HOST + usbh_initialize(bus_id, USB_HOST1_BASE, NULL); + bus_id++; +#endif + return 0; +} + +#if defined(KERNEL_RTTHREAD) +#include +#include + +INIT_ENV_EXPORT(__usbh_init); +#endif diff --git a/kernel/cherryusb/port/ehci/usb_glue_bouffalo.c b/kernel/cherryusb/port/ehci/usb_glue_bouffalo.c new file mode 100644 index 0000000..03cd1f3 --- /dev/null +++ b/kernel/cherryusb/port/ehci/usb_glue_bouffalo.c @@ -0,0 +1,161 @@ +/* + * Copyright (c) 2024, sakumisu + * + * SPDX-License-Identifier: Apache-2.0 + */ +#include "bflb_core.h" +#include "bflb_l1c.h" +#include "usbh_core.h" +#include "hardware/usb_v2_reg.h" + +#ifndef CONFIG_USB_EHCI_HCOR_RESERVED_DISABLE +#error "usb host must enable CONFIG_USB_EHCI_HCOR_RESERVED_DISABLE" +#endif + +#define BLFB_USB_BASE ((uint32_t)0x20072000) +#define BFLB_PDS_BASE ((uint32_t)0x2000e000) + +#define PDS_USB_CTL_OFFSET (0x500) /* usb_ctl */ +#define PDS_USB_PHY_CTRL_OFFSET (0x504) /* usb_phy_ctrl */ + +/* 0x500 : usb_ctl */ +#define PDS_REG_USB_SW_RST_N (1 << 0U) +#define PDS_REG_USB_EXT_SUSP_N (1 << 1U) +#define PDS_REG_USB_WAKEUP (1 << 2U) +#define PDS_REG_USB_L1_WAKEUP (1 << 3U) +#define PDS_REG_USB_DRVBUS_POL (1 << 4U) +#define PDS_REG_USB_IDDIG (1 << 5U) + +/* 0x504 : usb_phy_ctrl */ +#define PDS_REG_USB_PHY_PONRST (1 << 0U) +#define PDS_REG_USB_PHY_OSCOUTEN (1 << 1U) +#define PDS_REG_USB_PHY_XTLSEL_SHIFT (2U) +#define PDS_REG_USB_PHY_XTLSEL_MASK (0x3 << PDS_REG_USB_PHY_XTLSEL_SHIFT) +#define PDS_REG_USB_PHY_OUTCLKSEL (1 << 4U) +#define PDS_REG_USB_PHY_PLLALIV (1 << 5U) +#define PDS_REG_PU_USB20_PSW (1 << 6U) + +#define USB_SOF_TIMER_MASK_AFTER_RESET_HS (0x44C) +#define USB_SOF_TIMER_MASK_AFTER_RESET_FS (0x2710) + +extern void USBH_IRQHandler(uint8_t busid); + +void USBH_IRQ(int irq, void *arg) { + USBH_IRQHandler(0); +} + +static void bflb_usb_phy_init(void) +{ + uint32_t regval; + + /* USB_PHY_CTRL[3:2] reg_usb_phy_xtlsel=0 */ + /* 2000e504 = 0x40; #100; USB_PHY_CTRL[6] reg_pu_usb20_psw=1 (VCC33A) */ + /* 2000e504 = 0x41; #500; USB_PHY_CTRL[0] reg_usb_phy_ponrst=1 */ + /* 2000e500 = 0x20; #100; USB_CTL[0] reg_usb_sw_rst_n=0 */ + /* 2000e500 = 0x22; #500; USB_CTL[1] reg_usb_ext_susp_n=1 */ + /* 2000e500 = 0x23; #100; USB_CTL[0] reg_usb_sw_rst_n=1 */ + /* #1.2ms; wait UCLK */ + /* wait(soc616_b0.usb_uclk); */ + + regval = getreg32(BFLB_PDS_BASE + PDS_USB_PHY_CTRL_OFFSET); + regval &= ~PDS_REG_USB_PHY_XTLSEL_MASK; + putreg32(regval, BFLB_PDS_BASE + PDS_USB_PHY_CTRL_OFFSET); + + regval = getreg32(BFLB_PDS_BASE + PDS_USB_PHY_CTRL_OFFSET); + regval |= PDS_REG_PU_USB20_PSW; + putreg32(regval, BFLB_PDS_BASE + PDS_USB_PHY_CTRL_OFFSET); + + regval = getreg32(BFLB_PDS_BASE + PDS_USB_PHY_CTRL_OFFSET); + regval |= PDS_REG_USB_PHY_PONRST; + putreg32(regval, BFLB_PDS_BASE + PDS_USB_PHY_CTRL_OFFSET); + + /* greater than 5T */ + bflb_mtimer_delay_us(1); + + regval = getreg32(BFLB_PDS_BASE + PDS_USB_CTL_OFFSET); + regval &= ~PDS_REG_USB_SW_RST_N; + putreg32(regval, BFLB_PDS_BASE + PDS_USB_CTL_OFFSET); + + /* greater than 5T */ + bflb_mtimer_delay_us(1); + + regval = getreg32(BFLB_PDS_BASE + PDS_USB_CTL_OFFSET); + regval |= PDS_REG_USB_EXT_SUSP_N; + putreg32(regval, BFLB_PDS_BASE + PDS_USB_CTL_OFFSET); + + /* wait UCLK 1.2ms */ + bflb_mtimer_delay_ms(3); + + regval = getreg32(BFLB_PDS_BASE + PDS_USB_CTL_OFFSET); + regval |= PDS_REG_USB_SW_RST_N; + putreg32(regval, BFLB_PDS_BASE + PDS_USB_CTL_OFFSET); + + bflb_mtimer_delay_ms(2); +} + +void usb_hc_low_level_init(struct usbh_bus *bus) +{ + uint32_t regval; + + bflb_usb_phy_init(); + + bflb_irq_attach(37, USBH_IRQ, NULL); + bflb_irq_enable(37); + + /* enable device-A for host */ + regval = getreg32(BFLB_PDS_BASE + PDS_USB_CTL_OFFSET); + regval &= ~PDS_REG_USB_IDDIG; + putreg32(regval, BFLB_PDS_BASE + PDS_USB_CTL_OFFSET); + + regval = getreg32(BLFB_USB_BASE + USB_OTG_CSR_OFFSET); + regval |= USB_A_BUS_DROP_HOV; + regval &= ~USB_A_BUS_REQ_HOV; + putreg32(regval, BLFB_USB_BASE + USB_OTG_CSR_OFFSET); + + bflb_mtimer_delay_ms(10); + + /* enable vbus and bus control */ + regval = getreg32(BLFB_USB_BASE + USB_OTG_CSR_OFFSET); + regval &= ~USB_A_BUS_DROP_HOV; + regval |= USB_A_BUS_REQ_HOV; + putreg32(regval, BLFB_USB_BASE + USB_OTG_CSR_OFFSET); + + regval = getreg32(BLFB_USB_BASE + USB_GLB_INT_OFFSET); + regval |= USB_MDEV_INT; + regval |= USB_MOTG_INT; + regval &= ~USB_MHC_INT; + putreg32(regval, BLFB_USB_BASE + USB_GLB_INT_OFFSET); +} + +uint8_t usbh_get_port_speed(struct usbh_bus *bus, const uint8_t port) +{ + uint8_t speed = 3; + + speed = (getreg32(BLFB_USB_BASE + USB_OTG_CSR_OFFSET) & USB_SPD_TYP_HOV_POV_MASK) >> USB_SPD_TYP_HOV_POV_SHIFT; + + if (speed == 0) { + return USB_SPEED_FULL; + } else if (speed == 1) { + return USB_SPEED_LOW; + } else if (speed == 2) { + return USB_SPEED_HIGH; + } + return USB_SPEED_HIGH; +} + +#ifdef CONFIG_USB_DCACHE_ENABLE +void usb_dcache_clean(uintptr_t addr, size_t size) +{ + bflb_l1c_dcache_clean_range((void *)addr, size); +} + +void usb_dcache_invalidate(uintptr_t addr, size_t size) +{ + bflb_l1c_dcache_invalidate_range((void *)addr, size); +} + +void usb_dcache_flush(uintptr_t addr, size_t size) +{ + bflb_l1c_dcache_clean_invalidate_range((void *)addr, size); +} +#endif \ No newline at end of file diff --git a/kernel/cherryusb/port/ehci/usb_glue_intel.c b/kernel/cherryusb/port/ehci/usb_glue_intel.c new file mode 100644 index 0000000..74ed378 --- /dev/null +++ b/kernel/cherryusb/port/ehci/usb_glue_intel.c @@ -0,0 +1,55 @@ +#ifdef __rtems__ + +#include +#include +#include +#include "usbh_core.h" + +uint32_t echi_base; +static int ehci_bus; +static int ehci_slot; +static int ehci_function; +static int ehci_vector; + +extern void USBH_IRQHandler(uint8_t busid); + +void ehci_pci_scan(int bus, int slot, int fun, int vector) +{ + ehci_bus = bus; + ehci_slot = slot; + ehci_function = fun; + ehci_vector = vector; + pci_read_config_dword(bus, slot, fun, PCI_BASE_ADDRESS_0, &echi_base); +} +void usb_hc_low_level_init(struct usbh_bus *bus) +{ + //set software own ehci + uint32_t legacy_val; + pci_write_config_dword(ehci_bus, ehci_slot, ehci_function, 0x68, 1 << 24); + pci_read_config_dword(ehci_bus, ehci_slot, ehci_function, 0x68, &legacy_val); + if ((legacy_val & 0x01010000) == 0x01000000) + printf("OS owned echi\n"); + else + printf("BIOS owned echi\n"); + + rtems_status_code sc; + sc = rtems_interrupt_handler_install( + ehci_vector, + "USBirq", + RTEMS_INTERRUPT_SHARED, + USBH_IRQHandler, + (void *)0); + + if (sc != RTEMS_SUCCESSFUL) { + printf("USB install isr falied,%s\n", rtems_status_text(sc)); + return; + } +} + +uint8_t usbh_get_port_speed(struct usbh_bus *bus, const uint8_t port) +{ + printf("USB_SPEED_HIGH present\n"); + return USB_SPEED_HIGH; +} + +#endif \ No newline at end of file diff --git a/kernel/cherryusb/port/ehci/usb_glue_ma35d0.c b/kernel/cherryusb/port/ehci/usb_glue_ma35d0.c new file mode 100644 index 0000000..3e03bbd --- /dev/null +++ b/kernel/cherryusb/port/ehci/usb_glue_ma35d0.c @@ -0,0 +1,117 @@ +/**************************************************************************/ /** +* +* @copyright (C) 2020 Nuvoton Technology Corp. All rights reserved. +* +* SPDX-License-Identifier: Apache-2.0 +* +* Change Logs: +* Date Author Notes +* 2023-8-8 Wayne First version +* +******************************************************************************/ +#include "rtthread.h" + +#include "NuMicro.h" +#include "rthw.h" +#include "drv_sys.h" + +#define LOG_TAG "drv.cherry" +#define DBG_ENABLE +#define DBG_SECTION_NAME LOG_TAG +#define DBG_LEVEL DBG_LOG +#define DBG_COLOR +#include + +#if defined(PKG_CHERRYUSB_HOST) + +#include "usbh_core.h" + +static void nu_echi_isr(int vector, void *param) +{ + uint8_t busid = (uint8_t)param; + extern void USBH_IRQHandler(uint8_t busid); + USBH_IRQHandler(busid); +} + +static void nu_ochi_isr(int vector, void *param) +{ +} + +void usb_hc_low_level_init(struct usbh_bus *bus) +{ + int timeout = 100; + + if (bus->hcd.reg_base == HSUSBH0_BASE) { + /* Enable USBH clock */ + CLK_EnableModuleClock(HUSBH0_MODULE); + SYS_ResetModule(HSUSBH0_RST); + + /* Clock engine clock Configuration */ + SYS->USBPMISCR &= ~(SYS_USBPMISCR_PHY0POR_Msk | SYS_USBPMISCR_PHY0COMN_Msk); + rt_thread_mdelay(20); + SYS->USBPMISCR |= SYS_USBPMISCR_PHY0SUSPEND_Msk | SYS_USBPMISCR_PHY0COMN_Msk; + + /* set UHOVRCURH(SYS_MISCFCR0[12]) 1 => USBH Host over-current detect is high-active */ + /* 0 => USBH Host over-current detect is low-active */ + //SYS->MISCFCR0 |= SYS_MISCFCR0_UHOVRCURH_Msk; + SYS->MISCFCR0 &= ~SYS_MISCFCR0_UHOVRCURH_Msk; + while (1) { + rt_thread_mdelay(1); + if (SYS->USBPMISCR & SYS_USBPMISCR_PHY0HSTCKSTB_Msk) + break; /* both USB PHY0 and PHY1 clock 60MHz UTMI clock stable */ + + timeout--; + if (timeout == 0) { + rt_kprintf("USB PHY reset failed. USBPMISCR = 0x%08x\n", SYS->USBPMISCR); + return; + } + } + + /* Register interrupt service routine. */ + rt_hw_interrupt_install(HSUSBH0_IRQn, nu_echi_isr, (void *)bus->hcd.hcd_id, "ehci0"); + + /* Enable interrupt */ + rt_hw_interrupt_umask(HSUSBH0_IRQn); + } else if (bus->hcd.reg_base == HSUSBH1_BASE) { + /* Enable USBH clock */ + CLK_EnableModuleClock(HUSBH1_MODULE); + SYS_ResetModule(HSUSBH1_RST); + + /* Clock engine clock Configuration */ + SYS->USBPMISCR &= ~(SYS_USBPMISCR_PHY1POR_Msk | SYS_USBPMISCR_PHY1COMN_Msk); + rt_thread_mdelay(20); + SYS->USBPMISCR |= SYS_USBPMISCR_PHY1SUSPEND_Msk | SYS_USBPMISCR_PHY1COMN_Msk; + + /* set UHOVRCURH(SYS_MISCFCR0[12]) 1 => USBH Host over-current detect is high-active */ + /* 0 => USBH Host over-current detect is low-active */ + //SYS->MISCFCR0 |= SYS_MISCFCR0_UHOVRCURH_Msk; + SYS->MISCFCR0 &= ~SYS_MISCFCR0_UHOVRCURH_Msk; + while (1) { + rt_thread_mdelay(1); + if (SYS->USBPMISCR & SYS_USBPMISCR_PHY1HSTCKSTB_Msk) + break; /* both USB PHY0 and PHY1 clock 60MHz UTMI clock stable */ + + timeout--; + if (timeout == 0) { + rt_kprintf("USB PHY reset failed. USBPMISCR = 0x%08x\n", SYS->USBPMISCR); + return; + } + } + /* Register interrupt service routine. */ + rt_hw_interrupt_install(HSUSBH1_IRQn, nu_echi_isr, (void *)bus->hcd.hcd_id, "ehci1"); + + /* Enable interrupt */ + rt_hw_interrupt_umask(HSUSBH1_IRQn); + } +} + +void usb_hc_low_level2_init(struct usbh_bus *bus) +{ +} + +uint8_t usbh_get_port_speed(struct usbh_bus *bus, const uint8_t port) +{ + return USB_SPEED_HIGH; +} + +#endif diff --git a/kernel/cherryusb/port/ehci/usb_glue_nuc980.c b/kernel/cherryusb/port/ehci/usb_glue_nuc980.c new file mode 100644 index 0000000..4b8a8b3 --- /dev/null +++ b/kernel/cherryusb/port/ehci/usb_glue_nuc980.c @@ -0,0 +1,62 @@ +/**************************************************************************/ /** +* +* @copyright (C) 2020 Nuvoton Technology Corp. All rights reserved. +* +* SPDX-License-Identifier: Apache-2.0 +* +* Change Logs: +* Date Author Notes +* 2023-8-8 Wayne First version +* +******************************************************************************/ +#include "rtthread.h" + +#include "NuMicro.h" +#include "rthw.h" +#include "drv_sys.h" + +#define LOG_TAG "drv.cherry" +#define DBG_ENABLE +#define DBG_SECTION_NAME LOG_TAG +#define DBG_LEVEL DBG_LOG +#define DBG_COLOR +#include + +#if defined(PKG_CHERRYUSB_HOST) +#include "usbh_core.h" + +static void nu_ehci_isr(int vector, void *param) +{ + extern void USBH_IRQHandler(uint8_t busid); + USBH_IRQHandler(0); +} + +void usb_hc_low_level_init(struct usbh_bus *bus) +{ + LOG_D("%s %d", __FUNCTION__, __LINE__); + + rt_hw_interrupt_mask(IRQ_EHCI); + + /* Enable USBH clock */ + nu_sys_ipclk_enable(USBHCKEN); + nu_sys_ip_reset(USBHRST); + + outpw(0xB0015000 + 0xC4, 0x160); //HSUSBH->USBPCR0 = 0x160; /* enable PHY 0 */ + outpw(0xB0015000 + 0xC8, 0x520); //HSUSBH->USBPCR1 = 0x520; /* enable PHY 1 */ + + //USBH->HcMiscControl |= USBH_HcMiscControl_OCAL_Msk; /* Over-current active low */ + //outpw(0xB0017000 + 0x204, inpw(0xB0017000 + 0x204) | (0x1ul << 3)); + + //USBH->HcMiscControl &= ~USBH_HcMiscControl_OCAL_Msk; /* Over-current active high */ + outpw(0xB0017000 + 0x204, inpw(0xB0017000 + 0x204) & (~(0x1ul << 3))); + + rt_hw_interrupt_install(IRQ_EHCI, nu_ehci_isr, NULL, "ehci-1"); + rt_hw_interrupt_set_priority(IRQ_EHCI, IRQ_LEVEL_1); + rt_hw_interrupt_umask(IRQ_EHCI); +} + +uint8_t usbh_get_port_speed(struct usbh_bus *bus, const uint8_t port) +{ + return USB_SPEED_HIGH; +} +#endif \ No newline at end of file diff --git a/kernel/cherryusb/port/ehci/usb_glue_t113.c b/kernel/cherryusb/port/ehci/usb_glue_t113.c new file mode 100644 index 0000000..ec46dea --- /dev/null +++ b/kernel/cherryusb/port/ehci/usb_glue_t113.c @@ -0,0 +1,235 @@ +/* + * Copyright (c) 2026, HakumenJean + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2026-01-06 HakumenJean first version + */ + +#include +#include +#include +#include + +#include "usbh_core.h" +#include "usb_hc_ehci.h" +#ifdef CONFIG_USB_EHCI_WITH_OHCI +#include "usb_hc_ohci.h" +#endif + +#include "hal_clk.h" +#include "hal_reset.h" +#include "interrupt.h" + +#if CONFIG_USBHOST_MAX_BUS != 2 +#error "t113 has 2 usb host controller" +#endif + +#if CONFIG_USB_OHCI_HCOR_OFFSET != 0x400 +#error "t113 CONFIG_USB_OHCI_HCOR_OFFSET must be 0x400" +#endif + +#if defined(CONFIG_USB_EHCI_HCOR_RESERVED_DISABLE) +#error "t113 usb ehci register need reserved" +#endif + +#if !defined(CONFIG_USB_EHCI_CONFIGFLAG) +#error "t113 usb ehci has configflag register" +#endif + +#if defined(CONFIG_USB_EHCI_ISO) +#error "t113 usb ehci no iso register" +#endif + +#define USB0_OTG_BASE_ADDR (0x04100000U) +#define USB0_PHY_BASE_ADDR (0x04100400U) +#define USB0_EHCI_BASE_ADDR (0x04101000U) + +#define USB1_EHCI_BASE_ADDR (0x04200000U) +#define USB1_PHY_BASE_ADDR (0x04200800U) + +void usb_select_phyTohci(void) +{ + *(volatile rt_uint32_t *)(USB0_OTG_BASE_ADDR + 0x420) &= ~(1 << 0); +} + +void usb_gate_open(rt_uint8_t busid) +{ + if (busid == 0) { + /* otg gate open*/ + hal_clock_enable(hal_clock_get(HAL_SUNXI_CCU, CLK_BUS_OTG)); + + /* otg bus reset */ + hal_reset_control_reset(hal_reset_control_get(HAL_SUNXI_RESET, RST_BUS_OTG)); + + /* ehci gate open */ + hal_clock_enable(hal_clock_get(HAL_SUNXI_CCU, CLK_BUS_EHCI0)); + + /* ehci bus reset */ + hal_reset_control_reset(hal_reset_control_get(HAL_SUNXI_RESET, RST_BUS_EHCI0)); + + /* ohci gate open */ + hal_clock_enable(hal_clock_get(HAL_SUNXI_CCU, CLK_BUS_OHCI0)); + + /* ohci bus reset */ + hal_reset_control_reset(hal_reset_control_get(HAL_SUNXI_RESET, RST_BUS_OHCI0)); + + /* clock enable */ + hal_clock_enable(hal_clock_get(HAL_SUNXI_CCU, CLK_USB_OHCI0)); + + /* reset phy */ + hal_reset_control_reset(hal_reset_control_get(HAL_SUNXI_RESET, RST_USB_PHY0)); + + /* otg phy select */ + usb_select_phyTohci(); + } else { + /* ehci gate open */ + hal_clock_enable(hal_clock_get(HAL_SUNXI_CCU, CLK_BUS_EHCI1)); + + /* ehci bus reset */ + hal_reset_control_reset(hal_reset_control_get(HAL_SUNXI_RESET, RST_BUS_EHCI1)); + + /* ohci gate open */ + hal_clock_enable(hal_clock_get(HAL_SUNXI_CCU, CLK_BUS_OHCI1)); + + /* ohci bus reset */ + hal_reset_control_reset(hal_reset_control_get(HAL_SUNXI_RESET, RST_BUS_OHCI1)); + + /* clock enable */ + hal_clock_enable(hal_clock_get(HAL_SUNXI_CCU, CLK_USB_OHCI1)); + + /* reset phy */ + hal_reset_control_reset(hal_reset_control_get(HAL_SUNXI_RESET, RST_USB_PHY1)); + } +} + +void usb_clean_siddp(struct usbh_bus *bus) +{ + *(volatile rt_uint32_t *)(bus->hcd.reg_base + 0x810) &= ~(1 << 3); +} + +void usb_hci_set_passby(struct usbh_bus *bus) +{ + /* AHB Master interface INCR16 enable */ + /* AHB Master interface INCR8 enable */ + /* AHB Master interface burst type INCR4 enable */ + /* AHB Master interface INCRX align enable */ + /* ULPI bypass enable */ + *(volatile rt_uint32_t *)(bus->hcd.reg_base + 0x800) |= (1 << 11) | (1 << 10) | (1 << 9) | (1 << 8) | (1 << 0); +} + +void t113_ehci_isr(int vector, void *arg) +{ + struct usbh_bus *bus = (struct usbh_bus *)arg; + + rt_interrupt_enter(); + + USB_LOG_DBG("t113_ehci_isr"); + + extern void USBH_IRQHandler(uint8_t busid); + USBH_IRQHandler(bus->hcd.hcd_id); + + rt_interrupt_leave(); +} + +#ifdef CONFIG_USB_EHCI_WITH_OHCI + +void t113_ohci_isr(int vector, void *arg) +{ + struct usbh_bus *bus = (struct usbh_bus *)arg; + + rt_interrupt_enter(); + + USB_LOG_DBG("t113_ohci_isr"); + + extern void OHCI_IRQHandler(uint8_t busid); + OHCI_IRQHandler(bus->hcd.hcd_id); + + rt_interrupt_leave(); +} + +#endif + +void usb_hc_low_level_init(struct usbh_bus *bus) +{ + int vector; + RT_ASSERT(bus->busid <= 1); + + usb_gate_open(bus->busid); + usb_clean_siddp(bus); + usb_hci_set_passby(bus); + + /* register EHCI interrupt callback */ + vector = SUNXI_IRQ_USB0_EHCI + (bus->busid > 0 ? 3 : 0); + rt_hw_interrupt_install(vector, t113_ehci_isr, bus, RT_NULL); + rt_hw_interrupt_set_priority(vector, 11 << 4); + rt_hw_interrupt_umask(vector); + + /* register OHCI interrupt callback */ +#ifdef CONFIG_USB_EHCI_WITH_OHCI + rt_hw_interrupt_install(vector + 1, t113_ohci_isr, bus, RT_NULL); + rt_hw_interrupt_set_priority(vector, 11 << 4); + rt_hw_interrupt_umask(vector + 1); +#endif + + USB_LOG_DBG("usb%d vector : %d, phy : %X\n", bus->busid, vector, *(volatile rt_uint32_t *)(bus->hcd.reg_base + 0x810)); + USB_LOG_DBG("usb%d hc low level init success\n", bus->busid); +} + +uint8_t usbh_get_port_speed(struct usbh_bus *bus, const uint8_t port) +{ + /* Defined by individual manufacturers */ + uint32_t regval; + + regval = EHCI_HCOR->portsc[port - 1]; + if ((regval & EHCI_PORTSC_LSTATUS_MASK) == EHCI_PORTSC_LSTATUS_KSTATE) + return USB_SPEED_LOW; + + if (regval & EHCI_PORTSC_PE) + return USB_SPEED_HIGH; + else + return USB_SPEED_FULL; +} + +int __usbh_init(void) +{ +#ifdef T113_USING_USB0_HOST + /* USB0 MSC test OK */ + usbh_initialize(0, USB0_EHCI_BASE_ADDR, NULL); +#endif + +#ifdef T113_USING_USB1_HOST + /* USB1 MSC test OK */ + usbh_initialize(1, USB1_EHCI_BASE_ADDR, NULL); +#endif + return 0; +} + +#ifdef PKG_CHERRYUSB_HOST + +#include +#include +#include + +INIT_ENV_EXPORT(__usbh_init); + +#ifdef CONFIG_USB_DCACHE_ENABLE +void usb_dcache_clean(uintptr_t addr, size_t size) +{ + rt_hw_cpu_dcache_ops(RT_HW_CACHE_FLUSH, (void *)addr, size); +} + +void usb_dcache_invalidate(uintptr_t addr, size_t size) +{ + rt_hw_cpu_dcache_ops(RT_HW_CACHE_INVALIDATE, (void *)addr, size); +} + +void usb_dcache_flush(uintptr_t addr, size_t size) +{ + rt_hw_cpu_dcache_ops(RT_HW_CACHE_FLUSH, (void *)addr, size); +} +#endif + +#endif diff --git a/kernel/cherryusb/port/ehci/usb_hc_ehci.c b/kernel/cherryusb/port/ehci/usb_hc_ehci.c new file mode 100644 index 0000000..91c3747 --- /dev/null +++ b/kernel/cherryusb/port/ehci/usb_hc_ehci.c @@ -0,0 +1,1457 @@ +/* + * Copyright (c) 2022, sakumisu + * + * SPDX-License-Identifier: Apache-2.0 + */ +#include "usb_hc_ehci.h" +#ifdef CONFIG_USB_EHCI_WITH_OHCI +#include "usb_hc_ohci.h" +#endif + +#define EHCI_TUNE_CERR 3 /* 0-3 qtd retries; 0 == don't stop */ +#define EHCI_TUNE_RL_HS 4 /* nak throttle; see 4.9 */ +#define EHCI_TUNE_RL_TT 0 +#define EHCI_TUNE_MULT_HS 1 /* 1-3 transactions/uframe; 4.10.3 */ +#define EHCI_TUNE_MULT_TT 1 + +struct ehci_hcd g_ehci_hcd[CONFIG_USBHOST_MAX_BUS]; + +USB_NOCACHE_RAM_SECTION struct ehci_qh_hw ehci_qh_pool[CONFIG_USBHOST_MAX_BUS][CONFIG_USB_EHCI_QH_NUM]; +USB_NOCACHE_RAM_SECTION struct ehci_qtd_hw ehci_qtd_pool[CONFIG_USBHOST_MAX_BUS][CONFIG_USB_EHCI_QTD_NUM]; + +/* The head of the asynchronous queue */ +USB_NOCACHE_RAM_SECTION struct ehci_qh_hw g_async_qh_head[CONFIG_USBHOST_MAX_BUS]; +/* The head of the periodic queue */ +USB_NOCACHE_RAM_SECTION struct ehci_qh_hw g_periodic_qh_head[CONFIG_USBHOST_MAX_BUS]; + +/* The frame list */ +USB_NOCACHE_RAM_SECTION uint32_t g_framelist[CONFIG_USBHOST_MAX_BUS][USB_ALIGN_UP(CONFIG_USB_EHCI_FRAME_LIST_SIZE, 1024)] __attribute__((aligned(4096))); + +static struct ehci_qtd_hw *ehci_qtd_alloc(struct usbh_bus *bus) +{ + struct ehci_qtd_hw *qtd; + size_t flags; + + flags = usb_osal_enter_critical_section(); + for (uint32_t i = 0; i < CONFIG_USB_EHCI_QTD_NUM; i++) { + qtd = &ehci_qtd_pool[bus->hcd.hcd_id][i]; + if (!qtd->inuse) { + qtd->inuse = true; + usb_osal_leave_critical_section(flags); + + memset(&qtd->hw, 0, sizeof(struct ehci_qtd)); + qtd->hw.next_qtd = QTD_LIST_END; + qtd->hw.alt_next_qtd = QTD_LIST_END; + qtd->hw.token = QTD_TOKEN_STATUS_HALTED; + qtd->urb = NULL; + qtd->bufaddr = 0; + qtd->length = 0; + + return qtd; + } + } + usb_osal_leave_critical_section(flags); + return NULL; +} + +static void ehci_qtd_free(struct usbh_bus *bus, struct ehci_qtd_hw *qtd) +{ + size_t flags; + + (void)bus; + + flags = usb_osal_enter_critical_section(); + qtd->inuse = false; + qtd->urb = NULL; + usb_osal_leave_critical_section(flags); +} + +static struct ehci_qh_hw *ehci_qh_alloc(struct usbh_bus *bus) +{ + struct ehci_qh_hw *qh; + size_t flags; + + flags = usb_osal_enter_critical_section(); + for (uint32_t i = 0; i < CONFIG_USB_EHCI_QH_NUM; i++) { + qh = &ehci_qh_pool[bus->hcd.hcd_id][i]; + if (!qh->inuse) { + qh->inuse = true; + usb_osal_leave_critical_section(flags); + + memset(&qh->hw, 0, sizeof(struct ehci_qh)); + qh->hw.hlp = QTD_LIST_END; + qh->hw.overlay.next_qtd = QTD_LIST_END; + qh->hw.overlay.alt_next_qtd = QTD_LIST_END; + qh->urb = NULL; + qh->first_qtd = QTD_LIST_END; + qh->remove_in_iaad = 0; + + return qh; + } + } + usb_osal_leave_critical_section(flags); + return NULL; +} + +static void ehci_qh_free(struct usbh_bus *bus, struct ehci_qh_hw *qh) +{ + struct ehci_qtd_hw *qtd; + size_t flags; + + flags = usb_osal_enter_critical_section(); + if (qh->urb) { + qh->urb->hcpriv = NULL; + qh->urb = NULL; + } + qtd = EHCI_ADDR2QTD(qh->first_qtd); + + while (qtd) { + ehci_qtd_free(bus, qtd); + qtd = EHCI_ADDR2QTD(qtd->hw.next_qtd); + } + + qh->inuse = false; + qh->first_qtd = QTD_LIST_END; + usb_osal_leave_critical_section(flags); +} + +#if defined(CONFIG_USB_EHCI_DESC_DCACHE_ENABLE) +static inline void usb_ehci_qh_qtd_flush(struct ehci_qh_hw *qh) +{ + struct ehci_qtd_hw *qtd; + + qtd = EHCI_ADDR2QTD(qh->first_qtd); + + while (qtd) { + usb_dcache_clean((uintptr_t)&qtd->hw, CONFIG_USB_EHCI_ALIGN_SIZE); + qtd = EHCI_ADDR2QTD(qtd->hw.next_qtd); + } + usb_dcache_clean((uintptr_t)&qh->hw, CONFIG_USB_EHCI_ALIGN_SIZE); +} +#else +#define usb_ehci_qh_qtd_flush(qh) +#endif + +static inline void ehci_qh_add_head(struct ehci_qh_hw *head, struct ehci_qh_hw *n) +{ + n->hw.hlp = head->hw.hlp; + usb_ehci_qh_qtd_flush(n); + + usb_dcache_flush((uintptr_t)n->urb->transfer_buffer, USB_ALIGN_UP(n->urb->transfer_buffer_length, CONFIG_USB_ALIGN_SIZE)); + + head->hw.hlp = QH_HLP_QH(n); +#if defined(CONFIG_USB_EHCI_DESC_DCACHE_ENABLE) + usb_dcache_clean((uintptr_t)&head->hw, CONFIG_USB_EHCI_ALIGN_SIZE); +#endif +} + +static inline void ehci_qh_remove(struct ehci_qh_hw *head, struct ehci_qh_hw *n) +{ + struct ehci_qh_hw *tmp = head; + + while (EHCI_ADDR2QH(tmp->hw.hlp) && EHCI_ADDR2QH(tmp->hw.hlp) != n) { + tmp = EHCI_ADDR2QH(tmp->hw.hlp); + } + + if (tmp) { + tmp->hw.hlp = n->hw.hlp; +#if defined(CONFIG_USB_EHCI_DESC_DCACHE_ENABLE) + usb_dcache_clean((uintptr_t)&tmp->hw, CONFIG_USB_EHCI_ALIGN_SIZE); +#endif + } +} + +static int ehci_caculate_smask(int binterval) +{ + int order, interval; + + interval = 1; + while (binterval > 1) { + interval *= 2; + binterval--; + } + + if (interval < 2) /* interval 1 */ + return 0xFF; + if (interval < 4) /* interval 2 */ + return 0x55; + if (interval < 8) /* interval 4 */ + return 0x22; + for (order = 0; (interval > 1); order++) { + interval >>= 1; + } + return (0x1 << (order % 8)); +} + +static void ehci_qh_fill(struct ehci_qh_hw *qh, + uint8_t dev_addr, + uint8_t ep_addr, + uint8_t ep_type, + uint16_t ep_mps, + uint8_t ep_mult, + uint8_t ep_interval, + uint8_t speed, + uint8_t hubaddr, + uint8_t hubport) +{ + uint32_t epchar = 0; + uint32_t epcap = 0; + + /* QH endpoint characteristics: + * + * FIELD DESCRIPTION + * -------- ------------------------------- + * DEVADDR Device address + * I Inactivate on Next Transaction + * ENDPT Endpoint number + * EPS Endpoint speed + * DTC Data toggle control + * MAXPKT Max packet size + * C Control endpoint + * RL NAK count reloaded + */ + + /* QH endpoint capabilities + * + * FIELD DESCRIPTION + * -------- ------------------------------- + * SSMASK Interrupt Schedule Mask + * SCMASK Split Completion Mask + * HUBADDR Hub Address + * PORT Port number + * MULT High band width multiplier + */ + + epchar |= ((ep_addr & 0xf) << QH_EPCHAR_ENDPT_SHIFT); + epchar |= (dev_addr << QH_EPCHAR_DEVADDR_SHIFT); + epchar |= (ep_mps << QH_EPCHAR_MAXPKT_SHIFT); + + if (ep_type == USB_ENDPOINT_TYPE_CONTROL) { + epchar |= QH_EPCHAR_DTC; /* toggle from qtd */ + } + + switch (speed) { + case USB_SPEED_LOW: + epchar |= QH_EPCHAR_EPS_LOW; + __attribute__((fallthrough)); + case USB_SPEED_FULL: + if (ep_type == USB_ENDPOINT_TYPE_CONTROL) { + epchar |= QH_EPCHAR_C; /* for TT */ + } + + if (ep_type != USB_ENDPOINT_TYPE_INTERRUPT) { + epchar |= (EHCI_TUNE_RL_TT << QH_EPCHAR_RL_SHIFT); + } + + epcap |= QH_EPCAPS_MULT(EHCI_TUNE_MULT_TT); + + epcap |= QH_EPCAPS_HUBADDR(hubaddr); + epcap |= QH_EPCAPS_PORT(hubport); + + if (ep_type == USB_ENDPOINT_TYPE_INTERRUPT) { + epcap |= QH_EPCAPS_SSMASK(2); + epcap |= QH_EPCAPS_SCMASK(0x78); + } + + break; + case USB_SPEED_HIGH: + epchar |= QH_EPCHAR_EPS_HIGH; + if (ep_type == USB_ENDPOINT_TYPE_CONTROL) { + epchar |= (EHCI_TUNE_RL_HS << QH_EPCHAR_RL_SHIFT); + + epcap |= QH_EPCAPS_MULT(EHCI_TUNE_MULT_HS); + } else if (ep_type == USB_ENDPOINT_TYPE_BULK) { + epcap |= QH_EPCAPS_MULT(EHCI_TUNE_MULT_HS); + } else { + /* only for interrupt ep */ + epcap |= QH_EPCAPS_MULT(ep_mult); + epcap |= ehci_caculate_smask(ep_interval); + } + break; + + default: + break; + } + + qh->hw.epchar = epchar; + qh->hw.epcap = epcap; +} + +static void ehci_qtd_bpl_fill(struct ehci_qtd_hw *qtd, uint32_t bufaddr, size_t buflen) +{ + uint32_t rest; + + qtd->hw.bpl[0] = bufaddr; + rest = 0x1000 - (bufaddr & 0xfff); + + if (buflen < rest) { + rest = buflen; + } else { + bufaddr += 0x1000; + bufaddr &= ~0x0fff; + + for (int i = 1; rest < buflen && i < 5; i++) { + qtd->hw.bpl[i] = bufaddr; + bufaddr += 0x1000; + + if ((rest + 0x1000) < buflen) { + rest += 0x1000; + } else { + rest = buflen; + } + } + } +} + +static void ehci_qtd_fill(struct ehci_qtd_hw *qtd, uint32_t bufaddr, size_t buflen, uint32_t token) +{ + /* qTD token + * + * FIELD DESCRIPTION + * -------- ------------------------------- + * STATUS Status + * PID PID Code + * CERR Error Counter + * CPAGE Current Page + * IOC Interrupt on complete + * NBYTES Total Bytes to Transfer + * TOGGLE Data Toggle + */ + + qtd->hw.token = token; + + ehci_qtd_bpl_fill(qtd, usb_phyaddr2ramaddr(bufaddr), buflen); + qtd->bufaddr = bufaddr; + qtd->length = buflen; +} + +static struct ehci_qh_hw *ehci_control_urb_init(struct usbh_bus *bus, struct usbh_urb *urb, struct usb_setup_packet *setup, uint8_t *buffer, uint32_t buflen) +{ + struct ehci_qh_hw *qh = NULL; + struct ehci_qtd_hw *qtd_setup = NULL; + struct ehci_qtd_hw *qtd_data = NULL; + struct ehci_qtd_hw *qtd_status = NULL; + uint32_t token; + size_t flags; + + qh = ehci_qh_alloc(bus); + if (qh == NULL) { + return NULL; + } + + qtd_setup = ehci_qtd_alloc(bus); + qtd_status = ehci_qtd_alloc(bus); + USB_ASSERT_MSG(qtd_setup && qtd_status, "ctrl qtd alloc failed"); + + ehci_qh_fill(qh, + urb->hport->dev_addr, + urb->ep->bEndpointAddress, + USB_GET_ENDPOINT_TYPE(urb->ep->bmAttributes), + USB_GET_MAXPACKETSIZE(urb->ep->wMaxPacketSize), + 0, + 0, + urb->hport->speed, + urb->hport->parent->hub_addr, + urb->hport->port); + + /* fill setup qtd */ + token = QTD_TOKEN_STATUS_ACTIVE | + QTD_TOKEN_PID_SETUP | + ((uint32_t)EHCI_TUNE_CERR << QTD_TOKEN_CERR_SHIFT) | + ((uint32_t)8 << QTD_TOKEN_NBYTES_SHIFT); + + ehci_qtd_fill(qtd_setup, (uintptr_t)setup, 8, token); + qtd_setup->urb = urb; + + /* fill data qtd */ + if (setup->wLength > 0) { + qtd_data = ehci_qtd_alloc(bus); + USB_ASSERT_MSG(qtd_data, "ctrl qtd alloc failed"); + + if ((setup->bmRequestType & 0x80) == 0x80) { + token = QTD_TOKEN_PID_IN; + } else { + token = QTD_TOKEN_PID_OUT; + } + token |= QTD_TOKEN_STATUS_ACTIVE | + QTD_TOKEN_PID_OUT | + QTD_TOKEN_TOGGLE | + ((uint32_t)EHCI_TUNE_CERR << QTD_TOKEN_CERR_SHIFT) | + ((uint32_t)buflen << QTD_TOKEN_NBYTES_SHIFT); + + ehci_qtd_fill(qtd_data, (uintptr_t)buffer, buflen, token); + qtd_data->urb = urb; + qtd_setup->hw.next_qtd = EHCI_PTR2ADDR(qtd_data); + qtd_data->hw.next_qtd = EHCI_PTR2ADDR(qtd_status); + } else { + qtd_setup->hw.next_qtd = EHCI_PTR2ADDR(qtd_status); + } + + /* fill status qtd */ + if ((setup->bmRequestType & 0x80) == 0x80) { + token = QTD_TOKEN_PID_OUT; + } else { + token = QTD_TOKEN_PID_IN; + } + token |= QTD_TOKEN_STATUS_ACTIVE | + QTD_TOKEN_TOGGLE | + QTD_TOKEN_IOC | + ((uint32_t)EHCI_TUNE_CERR << QTD_TOKEN_CERR_SHIFT) | + ((uint32_t)0 << QTD_TOKEN_NBYTES_SHIFT); + + ehci_qtd_fill(qtd_status, 0, 0, token); + qtd_status->urb = urb; + qtd_status->hw.next_qtd = QTD_LIST_END; + + /* update qh first qtd */ + qh->hw.curr_qtd = EHCI_PTR2ADDR(qtd_setup); + qh->hw.overlay.next_qtd = EHCI_PTR2ADDR(qtd_setup); + + /* record qh first qtd */ + qh->first_qtd = EHCI_PTR2ADDR(qtd_setup); + + flags = usb_osal_enter_critical_section(); + + qh->urb = urb; + urb->hcpriv = qh; + /* add qh into async list */ + ehci_qh_add_head(&g_async_qh_head[bus->hcd.hcd_id], qh); + + EHCI_HCOR->usbcmd |= EHCI_USBCMD_ASEN; + + usb_osal_leave_critical_section(flags); + return qh; +} + +static struct ehci_qh_hw *ehci_bulk_urb_init(struct usbh_bus *bus, struct usbh_urb *urb, uint8_t *buffer, uint32_t buflen) +{ + struct ehci_qh_hw *qh = NULL; + struct ehci_qtd_hw *qtd = NULL; + struct ehci_qtd_hw *first_qtd = NULL; + struct ehci_qtd_hw *prev_qtd = NULL; + uint32_t xfer_len = 0; + uint32_t token; + size_t flags; + + qh = ehci_qh_alloc(bus); + if (qh == NULL) { + return NULL; + } + + ehci_qh_fill(qh, + urb->hport->dev_addr, + urb->ep->bEndpointAddress, + USB_GET_ENDPOINT_TYPE(urb->ep->bmAttributes), + USB_GET_MAXPACKETSIZE(urb->ep->wMaxPacketSize), + 0, + 0, + urb->hport->speed, + urb->hport->parent->hub_addr, + urb->hport->port); + + while (1) { + qtd = ehci_qtd_alloc(bus); + USB_ASSERT_MSG(qtd, "bulk qtd alloc failed"); + + if (buflen > 0x4000) { + xfer_len = 0x4000; + buflen -= 0x4000; + } else { + xfer_len = buflen; + buflen = 0; + } + + if (urb->ep->bEndpointAddress & 0x80) { + token = QTD_TOKEN_PID_IN; + } else { + token = QTD_TOKEN_PID_OUT; + } + + token |= QTD_TOKEN_STATUS_ACTIVE | + ((uint32_t)EHCI_TUNE_CERR << QTD_TOKEN_CERR_SHIFT) | + ((uint32_t)xfer_len << QTD_TOKEN_NBYTES_SHIFT); + + if (buflen == 0) { + token |= QTD_TOKEN_IOC; + } + + ehci_qtd_fill(qtd, (uintptr_t)buffer, xfer_len, token); + qtd->urb = urb; + qtd->hw.next_qtd = QTD_LIST_END; + buffer += xfer_len; + + if (prev_qtd) { + prev_qtd->hw.next_qtd = EHCI_PTR2ADDR(qtd); + } else { + first_qtd = qtd; + } + prev_qtd = qtd; + + if (buflen == 0) { + break; + } + } + + /* update qh first qtd */ + qh->hw.curr_qtd = EHCI_PTR2ADDR(first_qtd); + qh->hw.overlay.next_qtd = EHCI_PTR2ADDR(first_qtd); + + /* update data toggle */ + if (urb->data_toggle) { + qh->hw.overlay.token = QTD_TOKEN_TOGGLE; + } else { + qh->hw.overlay.token = 0; + } + + /* record qh first qtd */ + qh->first_qtd = EHCI_PTR2ADDR(first_qtd); + + flags = usb_osal_enter_critical_section(); + + qh->urb = urb; + urb->hcpriv = qh; + /* add qh into async list */ + ehci_qh_add_head(&g_async_qh_head[bus->hcd.hcd_id], qh); + + EHCI_HCOR->usbcmd |= EHCI_USBCMD_ASEN; + + usb_osal_leave_critical_section(flags); + return qh; +} + +static struct ehci_qh_hw *ehci_intr_urb_init(struct usbh_bus *bus, struct usbh_urb *urb, uint8_t *buffer, uint32_t buflen) +{ + struct ehci_qh_hw *qh = NULL; + struct ehci_qtd_hw *qtd = NULL; + struct ehci_qtd_hw *first_qtd = NULL; + struct ehci_qtd_hw *prev_qtd = NULL; + uint32_t xfer_len = 0; + uint32_t token; + size_t flags; + + qh = ehci_qh_alloc(bus); + if (qh == NULL) { + return NULL; + } + + ehci_qh_fill(qh, + urb->hport->dev_addr, + urb->ep->bEndpointAddress, + USB_GET_ENDPOINT_TYPE(urb->ep->bmAttributes), + USB_GET_MAXPACKETSIZE(urb->ep->wMaxPacketSize), + USB_GET_MULT(urb->ep->wMaxPacketSize) + 1, + urb->ep->bInterval, + urb->hport->speed, + urb->hport->parent->hub_addr, + urb->hport->port); + + while (1) { + qtd = ehci_qtd_alloc(bus); + USB_ASSERT_MSG(qtd, "intr qtd alloc failed"); + + if (buflen > 0x4000) { + xfer_len = 0x4000; + buflen -= 0x4000; + } else { + xfer_len = buflen; + buflen = 0; + } + + if (urb->ep->bEndpointAddress & 0x80) { + token = QTD_TOKEN_PID_IN; + } else { + token = QTD_TOKEN_PID_OUT; + } + + token |= QTD_TOKEN_STATUS_ACTIVE | + ((uint32_t)EHCI_TUNE_CERR << QTD_TOKEN_CERR_SHIFT) | + ((uint32_t)xfer_len << QTD_TOKEN_NBYTES_SHIFT); + + if (buflen == 0) { + token |= QTD_TOKEN_IOC; + } + + ehci_qtd_fill(qtd, (uintptr_t)buffer, xfer_len, token); + qtd->urb = urb; + qtd->hw.next_qtd = QTD_LIST_END; + buffer += xfer_len; + + if (prev_qtd) { + prev_qtd->hw.next_qtd = EHCI_PTR2ADDR(qtd); + } else { + first_qtd = qtd; + } + prev_qtd = qtd; + + if (buflen == 0) { + break; + } + } + + /* update qh first qtd */ + qh->hw.curr_qtd = EHCI_PTR2ADDR(first_qtd); + qh->hw.overlay.next_qtd = EHCI_PTR2ADDR(first_qtd); + + /* update data toggle */ + if (urb->data_toggle) { + qh->hw.overlay.token = QTD_TOKEN_TOGGLE; + } else { + qh->hw.overlay.token = 0; + } + + /* record qh first qtd */ + qh->first_qtd = EHCI_PTR2ADDR(first_qtd); + + flags = usb_osal_enter_critical_section(); + + qh->urb = urb; + urb->hcpriv = qh; + /* add qh into periodic list */ + ehci_qh_add_head(&g_periodic_qh_head[bus->hcd.hcd_id], qh); + + EHCI_HCOR->usbcmd |= EHCI_USBCMD_PSEN; + + usb_osal_leave_critical_section(flags); + return qh; +} + +static void ehci_urb_waitup(struct usbh_bus *bus, struct usbh_urb *urb) +{ + struct ehci_qh_hw *qh; + + qh = (struct ehci_qh_hw *)urb->hcpriv; + + qh->remove_in_iaad = 0; + + if (urb->timeout) { + usb_osal_sem_give(qh->waitsem); + } else { + ehci_qh_free(bus, qh); + } + + if (urb->complete) { + if (urb->errorcode < 0) { + urb->complete(urb->arg, urb->errorcode); + } else { + urb->complete(urb->arg, urb->actual_length); + } + } +} + +static void ehci_qh_scan_qtds(struct usbh_bus *bus, struct ehci_qh_hw *qhead, struct ehci_qh_hw *qh) +{ + struct ehci_qtd_hw *qtd; + + (void)bus; + + ehci_qh_remove(qhead, qh); + + qtd = EHCI_ADDR2QTD(qh->first_qtd); + + while (qtd) { + qtd->urb->actual_length += (qtd->length - ((qtd->hw.token & QTD_TOKEN_NBYTES_MASK) >> QTD_TOKEN_NBYTES_SHIFT)); + + qtd = EHCI_ADDR2QTD(qtd->hw.next_qtd); + } +} + +static void ehci_check_qh(struct usbh_bus *bus, struct ehci_qh_hw *qhead, struct ehci_qh_hw *qh) +{ + struct usbh_urb *urb; + struct ehci_qtd_hw *qtd; + uint32_t token; + + qtd = EHCI_ADDR2QTD(qh->first_qtd); + + if (qtd == NULL) { + return; + } + + while (qtd) { +#if defined(CONFIG_USB_EHCI_DESC_DCACHE_ENABLE) + usb_dcache_invalidate((uintptr_t)&qtd->hw, CONFIG_USB_EHCI_ALIGN_SIZE); +#endif + token = qtd->hw.token; + + if (token & QTD_TOKEN_STATUS_ERRORS) { + break; + } else if (token & QTD_TOKEN_STATUS_ACTIVE) { + return; + } + + qtd = EHCI_ADDR2QTD(qtd->hw.next_qtd); + } + + urb = qh->urb; + + if ((token & QTD_TOKEN_STATUS_ERRORS) == 0) { + if (token & QTD_TOKEN_TOGGLE) { + urb->data_toggle = true; + } else { + urb->data_toggle = false; + } + urb->errorcode = 0; + } else { + if (token & QTD_TOKEN_STATUS_BABBLE) { + urb->errorcode = -USB_ERR_BABBLE; + urb->data_toggle = 0; + } else if (token & QTD_TOKEN_STATUS_HALTED) { + urb->errorcode = -USB_ERR_STALL; + urb->data_toggle = 0; + } else if (token & (QTD_TOKEN_STATUS_DBERR | QTD_TOKEN_STATUS_XACTERR)) { + urb->errorcode = -USB_ERR_IO; + } + } + + ehci_qh_scan_qtds(bus, qhead, qh); + + if (USB_GET_ENDPOINT_TYPE(urb->ep->bmAttributes) == USB_ENDPOINT_TYPE_INTERRUPT) { + ehci_urb_waitup(bus, urb); + } else { + qh->remove_in_iaad = 1; + + EHCI_HCOR->usbcmd |= EHCI_USBCMD_IAAD; + } +} + +static void ehci_kill_qh(struct usbh_bus *bus, struct ehci_qh_hw *qhead, struct ehci_qh_hw *qh) +{ + (void)bus; + + ehci_qh_remove(qhead, qh); +} + +static int usbh_reset_port(struct usbh_bus *bus, const uint8_t port) +{ + volatile uint32_t timeout = 0; + uint32_t regval; + +#if defined(CONFIG_USB_EHCI_HPMICRO) && CONFIG_USB_EHCI_HPMICRO + if ((*(volatile uint32_t *)(bus->hcd.reg_base + 0x224) & 0xc0) == (2 << 6)) { /* Hardcode for hpm */ + EHCI_HCOR->portsc[port - 1] |= (1 << 29); + } else { + EHCI_HCOR->portsc[port - 1] &= ~(1 << 29); + } +#endif + regval = EHCI_HCOR->portsc[port - 1]; + regval &= ~EHCI_PORTSC_PE; + regval |= EHCI_PORTSC_RESET; + EHCI_HCOR->portsc[port - 1] = regval; + usb_osal_msleep(55); + + EHCI_HCOR->portsc[port - 1] &= ~EHCI_PORTSC_RESET; + while ((EHCI_HCOR->portsc[port - 1] & EHCI_PORTSC_RESET) != 0) { + usb_osal_msleep(1); + timeout++; + if (timeout > 100) { + return -USB_ERR_TIMEOUT; + } + } + + return 0; +} + +__WEAK void usb_hc_low_level_init(struct usbh_bus *bus) +{ + (void)bus; +} + +__WEAK void usb_hc_low_level2_init(struct usbh_bus *bus) +{ + (void)bus; +} + +__WEAK void usb_hc_low_level_deinit(struct usbh_bus *bus) +{ + (void)bus; +} + +int usb_hc_init(struct usbh_bus *bus) +{ + struct ehci_qh_hw *qh; + struct ehci_qtd_hw *qtd; + + volatile uint32_t timeout = 0; + uint32_t regval; + + bus->hcd.roothub.speed = USB_SPEED_HIGH; + + memset(&g_ehci_hcd[bus->hcd.hcd_id], 0, sizeof(struct ehci_hcd)); + memset(ehci_qh_pool[bus->hcd.hcd_id], 0, sizeof(struct ehci_qh_hw) * CONFIG_USB_EHCI_QH_NUM); + memset(ehci_qtd_pool[bus->hcd.hcd_id], 0, sizeof(struct ehci_qtd_hw) * CONFIG_USB_EHCI_QTD_NUM); + + for (uint8_t index = 0; index < CONFIG_USB_EHCI_QH_NUM; index++) { + qh = &ehci_qh_pool[bus->hcd.hcd_id][index]; + if ((uintptr_t)&qh->hw % 32) { + USB_LOG_ERR("struct ehci_qh_hw is not align 32\r\n"); + return -USB_ERR_INVAL; + } + } + + for (uint8_t index = 0; index < CONFIG_USB_EHCI_QTD_NUM; index++) { + qtd = &ehci_qtd_pool[bus->hcd.hcd_id][index]; + if ((uintptr_t)&qtd->hw % 32) { + USB_LOG_ERR("struct ehci_qtd_hw is not align 32\r\n"); + return -USB_ERR_INVAL; + } + } + + for (uint8_t index = 0; index < CONFIG_USB_EHCI_QH_NUM; index++) { + qh = &ehci_qh_pool[bus->hcd.hcd_id][index]; + qh->waitsem = usb_osal_sem_create(0); + } + + memset(&g_async_qh_head[bus->hcd.hcd_id], 0, sizeof(struct ehci_qh_hw)); + g_async_qh_head[bus->hcd.hcd_id].hw.hlp = QH_HLP_QH(&g_async_qh_head[bus->hcd.hcd_id]); + g_async_qh_head[bus->hcd.hcd_id].hw.epchar = QH_EPCHAR_H; + g_async_qh_head[bus->hcd.hcd_id].hw.overlay.next_qtd = QTD_LIST_END; + g_async_qh_head[bus->hcd.hcd_id].hw.overlay.alt_next_qtd = QTD_LIST_END; + g_async_qh_head[bus->hcd.hcd_id].hw.overlay.token = QTD_TOKEN_STATUS_HALTED; + g_async_qh_head[bus->hcd.hcd_id].first_qtd = QTD_LIST_END; + + memset(g_framelist[bus->hcd.hcd_id], 0, sizeof(uint32_t) * CONFIG_USB_EHCI_FRAME_LIST_SIZE); + + memset(&g_periodic_qh_head[bus->hcd.hcd_id], 0, sizeof(struct ehci_qh_hw)); + g_periodic_qh_head[bus->hcd.hcd_id].hw.hlp = QH_HLP_END; + g_periodic_qh_head[bus->hcd.hcd_id].hw.epchar = QH_EPCAPS_SSMASK(1); + g_periodic_qh_head[bus->hcd.hcd_id].hw.overlay.next_qtd = QTD_LIST_END; + g_periodic_qh_head[bus->hcd.hcd_id].hw.overlay.alt_next_qtd = QTD_LIST_END; + g_periodic_qh_head[bus->hcd.hcd_id].hw.overlay.token = QTD_TOKEN_STATUS_HALTED; + g_periodic_qh_head[bus->hcd.hcd_id].first_qtd = QTD_LIST_END; + + for (uint32_t i = 0; i < CONFIG_USB_EHCI_FRAME_LIST_SIZE; i++) { + g_framelist[bus->hcd.hcd_id][i] = QH_HLP_QH(&g_periodic_qh_head[bus->hcd.hcd_id]); + } + +#if defined(CONFIG_USB_EHCI_DESC_DCACHE_ENABLE) + usb_dcache_clean((uintptr_t)&g_async_qh_head[bus->hcd.hcd_id].hw, CONFIG_USB_EHCI_ALIGN_SIZE); + usb_dcache_clean((uintptr_t)&g_periodic_qh_head[bus->hcd.hcd_id].hw, CONFIG_USB_EHCI_ALIGN_SIZE); + usb_dcache_clean((uintptr_t)g_framelist[bus->hcd.hcd_id], sizeof(uint32_t) * CONFIG_USB_EHCI_FRAME_LIST_SIZE); +#endif + + usb_hc_low_level_init(bus); + + USB_LOG_INFO("EHCI HCIVERSION:0x%04x\r\n", (unsigned int)EHCI_HCCR->hciversion); + USB_LOG_INFO("EHCI HCSPARAMS:0x%06x\r\n", (unsigned int)EHCI_HCCR->hcsparams); + USB_LOG_INFO("EHCI HCCPARAMS:0x%04x\r\n", (unsigned int)EHCI_HCCR->hccparams); + + g_ehci_hcd[bus->hcd.hcd_id].ppc = (EHCI_HCCR->hcsparams & EHCI_HCSPARAMS_PPC) ? true : false; + g_ehci_hcd[bus->hcd.hcd_id].n_ports = (EHCI_HCCR->hcsparams & EHCI_HCSPARAMS_NPORTS_MASK) >> EHCI_HCSPARAMS_NPORTS_SHIFT; + g_ehci_hcd[bus->hcd.hcd_id].n_cc = (EHCI_HCCR->hcsparams & EHCI_HCSPARAMS_NCC_MASK) >> EHCI_HCSPARAMS_NCC_SHIFT; + g_ehci_hcd[bus->hcd.hcd_id].n_pcc = (EHCI_HCCR->hcsparams & EHCI_HCSPARAMS_NPCC_MASK) >> EHCI_HCSPARAMS_NPCC_SHIFT; + g_ehci_hcd[bus->hcd.hcd_id].has_tt = g_ehci_hcd[bus->hcd.hcd_id].n_cc ? false : true; + g_ehci_hcd[bus->hcd.hcd_id].hcor_offset = EHCI_HCCR->caplength; + + USB_LOG_INFO("EHCI ppc:%u, n_ports:%u, n_cc:%u, n_pcc:%u\r\n", + g_ehci_hcd[bus->hcd.hcd_id].ppc, + g_ehci_hcd[bus->hcd.hcd_id].n_ports, + g_ehci_hcd[bus->hcd.hcd_id].n_cc, + g_ehci_hcd[bus->hcd.hcd_id].n_pcc); + + EHCI_HCOR->usbcmd &= ~EHCI_USBCMD_RUN; + usb_osal_msleep(2); + EHCI_HCOR->usbcmd |= EHCI_USBCMD_HCRESET; + while (EHCI_HCOR->usbcmd & EHCI_USBCMD_HCRESET) { + usb_osal_msleep(1); + timeout++; + if (timeout > 100) { + return -USB_ERR_TIMEOUT; + } + } + + EHCI_HCOR->usbintr = 0; + EHCI_HCOR->usbsts = EHCI_HCOR->usbsts; + + usb_hc_low_level2_init(bus); + + /* Set the Current Asynchronous List Address. */ + EHCI_HCOR->asynclistaddr = EHCI_PTR2ADDR(&g_async_qh_head[bus->hcd.hcd_id]); + /* Set the Periodic Frame List Base Address. */ + EHCI_HCOR->periodiclistbase = EHCI_PTR2ADDR(g_framelist[bus->hcd.hcd_id]); + + regval = EHCI_HCOR->usbcmd; + regval &= ~(EHCI_USBCMD_ITHRE_MASK | EHCI_USBCMD_FLSIZE_MASK); +#if CONFIG_USB_EHCI_FRAME_LIST_SIZE == 1024 + regval |= EHCI_USBCMD_FLSIZE_1024; +#elif CONFIG_USB_EHCI_FRAME_LIST_SIZE == 512 + regval |= EHCI_USBCMD_FLSIZE_512; +#elif CONFIG_USB_EHCI_FRAME_LIST_SIZE == 256 + regval |= EHCI_USBCMD_FLSIZE_256; +#else +#error Unsupported frame size list size +#endif + +#if !defined(CONFIG_USB_EHCI_HPMICRO) || !CONFIG_USB_EHCI_HPMICRO + regval |= EHCI_USBCMD_ITHRE_1MF; +#endif + regval |= EHCI_USBCMD_ASEN; + regval |= EHCI_USBCMD_PSEN; + regval |= EHCI_USBCMD_RUN; + EHCI_HCOR->usbcmd = regval; + +#ifdef CONFIG_USB_EHCI_CONFIGFLAG + EHCI_HCOR->configflag = EHCI_CONFIGFLAG; +#endif + /* Wait for the EHCI to run (no longer report halted) */ + timeout = 0; + while (EHCI_HCOR->usbsts & EHCI_USBSTS_HALTED) { + usb_osal_msleep(1); + timeout++; + if (timeout > 100) { + return -USB_ERR_TIMEOUT; + } + } + + if (g_ehci_hcd[bus->hcd.hcd_id].ppc) { + for (uint8_t port = 0; port < g_ehci_hcd[bus->hcd.hcd_id].n_ports; port++) { + regval = EHCI_HCOR->portsc[port]; + regval |= EHCI_PORTSC_PP; + regval &= ~(EHCI_PORTSC_CSC | EHCI_PORTSC_PEC | EHCI_PORTSC_OCC); + EHCI_HCOR->portsc[port] = regval; + } + } + + if (g_ehci_hcd[bus->hcd.hcd_id].has_tt) { +#ifdef CONFIG_USB_EHCI_WITH_OHCI + USB_LOG_INFO("EHCI uses tt for ls/fs device, so cannot enable this macro\r\n"); + return -USB_ERR_INVAL; +#endif + } + + if (g_ehci_hcd[bus->hcd.hcd_id].has_tt) { + USB_LOG_INFO("EHCI uses tt for ls/fs device\r\n"); + } else { +#ifdef CONFIG_USB_EHCI_WITH_OHCI + USB_LOG_INFO("EHCI uses companion controller for ls/fs device\r\n"); + ohci_init(bus); +#else + USB_LOG_WRN("Do not enable companion controller, you should use a hub to support ls/fs device\r\n"); +#endif + } + + /* Enable EHCI interrupts. */ + EHCI_HCOR->usbintr = EHCI_USBIE_INT | EHCI_USBIE_ERR | EHCI_USBIE_PCD | EHCI_USBIE_FATAL | EHCI_USBIE_IAA; + return 0; +} + +int usb_hc_deinit(struct usbh_bus *bus) +{ + struct ehci_qh_hw *qh; + + volatile uint32_t timeout = 0; + uint32_t regval; + + EHCI_HCOR->usbintr = 0; + + regval = EHCI_HCOR->usbcmd; + regval &= ~EHCI_USBCMD_ASEN; + regval &= ~EHCI_USBCMD_PSEN; + regval &= ~EHCI_USBCMD_RUN; + EHCI_HCOR->usbcmd = regval; + + while ((EHCI_HCOR->usbsts & (EHCI_USBSTS_PSS | EHCI_USBSTS_ASS)) || ((EHCI_HCOR->usbsts & EHCI_USBSTS_HALTED) == 0)) { + usb_osal_msleep(1); + timeout++; + if (timeout > 100) { + return -USB_ERR_TIMEOUT; + } + } + + if (g_ehci_hcd[bus->hcd.hcd_id].ppc) { + for (uint8_t port = 0; port < g_ehci_hcd[bus->hcd.hcd_id].n_ports; port++) { + regval = EHCI_HCOR->portsc[port]; + regval &= ~EHCI_PORTSC_PP; + EHCI_HCOR->portsc[port] = regval; + } + } + +#ifdef CONFIG_USB_EHCI_CONFIGFLAG + EHCI_HCOR->configflag = 0; +#endif + + EHCI_HCOR->usbsts = EHCI_HCOR->usbsts; + EHCI_HCOR->usbcmd |= EHCI_USBCMD_HCRESET; + + for (uint8_t index = 0; index < CONFIG_USB_EHCI_QH_NUM; index++) { + qh = &ehci_qh_pool[bus->hcd.hcd_id][index]; + usb_osal_sem_delete(qh->waitsem); + } + +#ifdef CONFIG_USB_EHCI_WITH_OHCI + ohci_deinit(bus); +#endif + + usb_hc_low_level_deinit(bus); + return 0; +} + +uint16_t usbh_get_frame_number(struct usbh_bus *bus) +{ +#ifdef CONFIG_USB_EHCI_WITH_OHCI + if (EHCI_HCOR->portsc[0] & EHCI_PORTSC_OWNER) { + return ohci_get_frame_number(bus); + } +#endif + + return (((EHCI_HCOR->frindex & EHCI_FRINDEX_MASK) >> 3) & 0x3ff); +} + +int usbh_roothub_control(struct usbh_bus *bus, struct usb_setup_packet *setup, uint8_t *buf) +{ + uint8_t nports; + uint8_t port; + uint32_t temp, status; + + nports = g_ehci_hcd[bus->hcd.hcd_id].n_ports; + + port = setup->wIndex; + + temp = EHCI_HCOR->portsc[port - 1]; + +#ifdef CONFIG_USB_EHCI_WITH_OHCI + if (temp & EHCI_PORTSC_OWNER) { + return ohci_roothub_control(bus, setup, buf); + } + + if ((temp & EHCI_PORTSC_LSTATUS_MASK) == EHCI_PORTSC_LSTATUS_KSTATE) { + EHCI_HCOR->portsc[port - 1] |= EHCI_PORTSC_OWNER; + + while (!(EHCI_HCOR->portsc[port - 1] & EHCI_PORTSC_OWNER)) { + } + USB_LOG_INFO("Switch port %u to OHCI\r\n", port); + return ohci_roothub_control(bus, setup, buf); + } +#endif + if (setup->bmRequestType & USB_REQUEST_RECIPIENT_DEVICE) { + switch (setup->bRequest) { + case HUB_REQUEST_CLEAR_FEATURE: + switch (setup->wValue) { + case HUB_FEATURE_HUB_C_LOCALPOWER: + break; + case HUB_FEATURE_HUB_C_OVERCURRENT: + break; + default: + return -USB_ERR_NOTSUPP; + } + break; + case HUB_REQUEST_SET_FEATURE: + switch (setup->wValue) { + case HUB_FEATURE_HUB_C_LOCALPOWER: + break; + case HUB_FEATURE_HUB_C_OVERCURRENT: + break; + default: + return -USB_ERR_NOTSUPP; + } + break; + case HUB_REQUEST_GET_DESCRIPTOR: + break; + case HUB_REQUEST_GET_STATUS: + memset(buf, 0, 4); + break; + default: + break; + } + } else if (setup->bmRequestType & USB_REQUEST_RECIPIENT_OTHER) { + switch (setup->bRequest) { + case HUB_REQUEST_CLEAR_FEATURE: + if (!port || port > nports) { + return -USB_ERR_INVAL; + } + + switch (setup->wValue) { + case HUB_PORT_FEATURE_ENABLE: + EHCI_HCOR->portsc[port - 1] &= ~EHCI_PORTSC_PE; + break; + case HUB_PORT_FEATURE_SUSPEND: + EHCI_HCOR->portsc[port - 1] |= EHCI_PORTSC_RESUME; + usb_osal_msleep(20); + EHCI_HCOR->portsc[port - 1] &= ~EHCI_PORTSC_RESUME; + while (EHCI_HCOR->portsc[port - 1] & EHCI_PORTSC_RESUME) { + } + + temp = EHCI_HCOR->usbcmd; + temp |= EHCI_USBCMD_ASEN; + temp |= EHCI_USBCMD_PSEN; + temp |= EHCI_USBCMD_RUN; + EHCI_HCOR->usbcmd = temp; + + while ((EHCI_HCOR->usbcmd & EHCI_USBCMD_RUN) == 0) { + } + + case HUB_PORT_FEATURE_C_SUSPEND: + break; + case HUB_PORT_FEATURE_POWER: + EHCI_HCOR->portsc[port - 1] &= ~EHCI_PORTSC_PP; + break; + case HUB_PORT_FEATURE_C_CONNECTION: + EHCI_HCOR->portsc[port - 1] |= EHCI_PORTSC_CSC; + break; + case HUB_PORT_FEATURE_C_ENABLE: + EHCI_HCOR->portsc[port - 1] |= EHCI_PORTSC_PEC; + break; + case HUB_PORT_FEATURE_C_OVER_CURREN: + EHCI_HCOR->portsc[port - 1] |= EHCI_PORTSC_OCC; + break; + case HUB_PORT_FEATURE_C_RESET: + break; + default: + return -USB_ERR_NOTSUPP; + } + break; + case HUB_REQUEST_SET_FEATURE: + if (!port || port > nports) { + return -USB_ERR_INVAL; + } + + switch (setup->wValue) { + case HUB_PORT_FEATURE_SUSPEND: + temp = EHCI_HCOR->usbcmd; + temp &= ~EHCI_USBCMD_ASEN; + temp &= ~EHCI_USBCMD_PSEN; + temp &= ~EHCI_USBCMD_RUN; + EHCI_HCOR->usbcmd = temp; + + while (EHCI_HCOR->usbcmd & EHCI_USBCMD_RUN) { + } + + EHCI_HCOR->portsc[port - 1] |= EHCI_PORTSC_SUSPEND; + while ((EHCI_HCOR->portsc[port - 1] & EHCI_PORTSC_SUSPEND) == 0) { + } + break; + case HUB_PORT_FEATURE_POWER: + EHCI_HCOR->portsc[port - 1] |= EHCI_PORTSC_PP; + break; + case HUB_PORT_FEATURE_RESET: + usbh_reset_port(bus, port); +#ifdef CONFIG_USB_EHCI_WITH_OHCI + if (!(EHCI_HCOR->portsc[port - 1] & EHCI_PORTSC_PE)) { + EHCI_HCOR->portsc[port - 1] |= EHCI_PORTSC_OWNER; + + while (!(EHCI_HCOR->portsc[port - 1] & EHCI_PORTSC_OWNER)) { + } + + USB_LOG_INFO("Switch port %u to OHCI\r\n", port); + return -USB_ERR_NOTSUPP; + } +#endif + break; + + default: + return -USB_ERR_NOTSUPP; + } + break; + case HUB_REQUEST_GET_STATUS: + if (!port || port > nports) { + return -USB_ERR_INVAL; + } + temp = EHCI_HCOR->portsc[port - 1]; + + status = 0; + if (temp & EHCI_PORTSC_CSC) { + status |= (1 << HUB_PORT_FEATURE_C_CONNECTION); + } + if (temp & EHCI_PORTSC_PEC) { + status |= (1 << HUB_PORT_FEATURE_C_ENABLE); + } + if (temp & EHCI_PORTSC_OCC) { + status |= (1 << HUB_PORT_FEATURE_C_OVER_CURREN); + } + + if (temp & EHCI_PORTSC_CCS) { + status |= (1 << HUB_PORT_FEATURE_CONNECTION); + } + if (temp & EHCI_PORTSC_PE) { + status |= (1 << HUB_PORT_FEATURE_ENABLE); + + if (usbh_get_port_speed(bus, port) == USB_SPEED_LOW) { + status |= (1 << HUB_PORT_FEATURE_LOWSPEED); + } else if (usbh_get_port_speed(bus, port) == USB_SPEED_HIGH) { + status |= (1 << HUB_PORT_FEATURE_HIGHSPEED); + } + } + if (temp & EHCI_PORTSC_SUSPEND) { + status |= (1 << HUB_PORT_FEATURE_SUSPEND); + } + if (temp & EHCI_PORTSC_OCA) { + status |= (1 << HUB_PORT_FEATURE_OVERCURRENT); + } + if (temp & EHCI_PORTSC_RESET) { + status |= (1 << HUB_PORT_FEATURE_RESET); + } + if (temp & EHCI_PORTSC_PP || !(EHCI_HCCR->hcsparams & EHCI_HCSPARAMS_PPC)) { + status |= (1 << HUB_PORT_FEATURE_POWER); + } + memcpy(buf, &status, 4); + break; + default: + break; + } + } + return 0; +} + +int usbh_submit_urb(struct usbh_urb *urb) +{ + struct ehci_qh_hw *qh = NULL; + size_t flags; + int ret = 0; + struct usbh_hub *hub; + struct usbh_hubport *hport; + struct usbh_bus *bus; + + if (!urb || !urb->hport || !urb->ep || !urb->hport->bus) { + return -USB_ERR_INVAL; + } + +#ifdef CONFIG_USB_DCACHE_ENABLE + USB_ASSERT_MSG(!((uintptr_t)urb->setup % CONFIG_USB_ALIGN_SIZE) && + !((uintptr_t)urb->transfer_buffer % CONFIG_USB_ALIGN_SIZE), + "urb->setup or urb->transfer_buffer is not aligned %d", CONFIG_USB_ALIGN_SIZE); +#endif + bus = urb->hport->bus; + + /* find active hubport in roothub */ + hport = urb->hport; + hub = urb->hport->parent; + while (!hub->is_roothub) { + hport = hub->parent; + hub = hub->parent->parent; + } + +#ifdef CONFIG_USB_EHCI_WITH_OHCI + if (EHCI_HCOR->portsc[hport->port - 1] & EHCI_PORTSC_OWNER) { + return ohci_submit_urb(urb); + } +#endif + + if (!urb->hport->connected || !(EHCI_HCOR->portsc[hport->port - 1] & EHCI_PORTSC_CCS)) { + return -USB_ERR_NOTCONN; + } + + if (urb->errorcode == -USB_ERR_BUSY) { + return -USB_ERR_BUSY; + } + + flags = usb_osal_enter_critical_section(); + + urb->hcpriv = NULL; + urb->errorcode = -USB_ERR_BUSY; + urb->actual_length = 0; + + usb_osal_leave_critical_section(flags); + + switch (USB_GET_ENDPOINT_TYPE(urb->ep->bmAttributes)) { + case USB_ENDPOINT_TYPE_CONTROL: + qh = ehci_control_urb_init(bus, urb, urb->setup, urb->transfer_buffer, urb->transfer_buffer_length); + if (qh == NULL) { + return -USB_ERR_NOMEM; + } + break; + case USB_ENDPOINT_TYPE_BULK: + qh = ehci_bulk_urb_init(bus, urb, urb->transfer_buffer, urb->transfer_buffer_length); + if (qh == NULL) { + return -USB_ERR_NOMEM; + } + break; + case USB_ENDPOINT_TYPE_INTERRUPT: + qh = ehci_intr_urb_init(bus, urb, urb->transfer_buffer, urb->transfer_buffer_length); + if (qh == NULL) { + return -USB_ERR_NOMEM; + } + break; + case USB_ENDPOINT_TYPE_ISOCHRONOUS: +#ifdef CONFIG_USB_EHCI_ISO + ret = ehci_iso_urb_init(bus, urb); +#endif + break; + default: + break; + } + + if (urb->timeout > 0) { + /* wait until timeout or sem give */ + ret = usb_osal_sem_take(qh->waitsem, urb->timeout); + if (ret < 0) { + goto errout_timeout; + } + urb->timeout = 0; + ret = urb->errorcode; + /* we can free qh when waitsem is done */ + ehci_qh_free(bus, qh); + } + return ret; +errout_timeout: + urb->timeout = 0; + usbh_kill_urb(urb); + return ret; +} + +int usbh_kill_urb(struct usbh_urb *urb) +{ + struct ehci_qh_hw *qh; + struct usbh_bus *bus; + size_t flags; + bool remove_in_iaad = false; + + if (!urb || !urb->hport || !urb->hcpriv || !urb->hport->bus) { + return -USB_ERR_INVAL; + } + + bus = urb->hport->bus; + +#ifdef CONFIG_USB_EHCI_WITH_OHCI + if (EHCI_HCOR->portsc[urb->hport->port - 1] & EHCI_PORTSC_OWNER) { + return ohci_kill_urb(urb); + } +#endif + + flags = usb_osal_enter_critical_section(); + + EHCI_HCOR->usbcmd &= ~(EHCI_USBCMD_PSEN | EHCI_USBCMD_ASEN); + + if ((USB_GET_ENDPOINT_TYPE(urb->ep->bmAttributes) == USB_ENDPOINT_TYPE_CONTROL) || (USB_GET_ENDPOINT_TYPE(urb->ep->bmAttributes) == USB_ENDPOINT_TYPE_BULK)) { + qh = EHCI_ADDR2QH(g_async_qh_head[bus->hcd.hcd_id].hw.hlp); + while ((qh != &g_async_qh_head[bus->hcd.hcd_id]) && qh) { + if (qh->urb == urb) { + remove_in_iaad = true; + ehci_kill_qh(bus, &g_async_qh_head[bus->hcd.hcd_id], qh); + } + qh = EHCI_ADDR2QH(qh->hw.hlp); + } + } else if (USB_GET_ENDPOINT_TYPE(urb->ep->bmAttributes) == USB_ENDPOINT_TYPE_INTERRUPT) { + qh = EHCI_ADDR2QH(g_periodic_qh_head[bus->hcd.hcd_id].hw.hlp); + while (qh) { + if (qh->urb == urb) { + ehci_kill_qh(bus, &g_periodic_qh_head[bus->hcd.hcd_id], qh); + } + qh = EHCI_ADDR2QH(qh->hw.hlp); + } + } else { +#ifdef CONFIG_USB_EHCI_ISO + ehci_kill_iso_urb(bus, urb); + EHCI_HCOR->usbcmd |= (EHCI_USBCMD_PSEN | EHCI_USBCMD_ASEN); + usb_osal_leave_critical_section(flags); + return 0; +#endif + } + + EHCI_HCOR->usbcmd |= (EHCI_USBCMD_PSEN | EHCI_USBCMD_ASEN); + + qh = (struct ehci_qh_hw *)urb->hcpriv; + qh->remove_in_iaad = 0; + urb->errorcode = -USB_ERR_SHUTDOWN; + + if (urb->timeout) { + usb_osal_sem_give(qh->waitsem); + } else { + ehci_qh_free(bus, qh); + } + + if (remove_in_iaad) { + volatile uint32_t timeout = 0; + EHCI_HCOR->usbsts = EHCI_USBSTS_IAA; + EHCI_HCOR->usbcmd |= EHCI_USBCMD_IAAD; + while (!(EHCI_HCOR->usbsts & EHCI_USBSTS_IAA)) { + timeout++; + if (timeout > 200000) { + USB_LOG_ERR("iaad timeout\r\n"); + usb_osal_leave_critical_section(flags); + return -USB_ERR_TIMEOUT; + } + } + EHCI_HCOR->usbsts = EHCI_USBSTS_IAA; + } + + if (urb->complete) { + urb->complete(urb->arg, urb->errorcode); + } + + usb_osal_leave_critical_section(flags); + + return 0; +} + +static void ehci_scan_async_list(struct usbh_bus *bus) +{ + struct ehci_qh_hw *qh; + + qh = EHCI_ADDR2QH(g_async_qh_head[bus->hcd.hcd_id].hw.hlp); + while ((qh != &g_async_qh_head[bus->hcd.hcd_id]) && qh) { + if (qh->urb) { + ehci_check_qh(bus, &g_async_qh_head[bus->hcd.hcd_id], qh); + } + qh = EHCI_ADDR2QH(qh->hw.hlp); + } +} + +static void ehci_scan_periodic_list(struct usbh_bus *bus) +{ + struct ehci_qh_hw *qh; + + qh = EHCI_ADDR2QH(g_periodic_qh_head[bus->hcd.hcd_id].hw.hlp); + while (qh) { + if (qh->urb) { + ehci_check_qh(bus, &g_periodic_qh_head[bus->hcd.hcd_id], qh); + } + qh = EHCI_ADDR2QH(qh->hw.hlp); + } +} + +void USBH_IRQHandler(uint8_t busid) +{ + uint32_t usbsts; + struct usbh_bus *bus; + + bus = &g_usbhost_bus[busid]; + + usbsts = EHCI_HCOR->usbsts & EHCI_HCOR->usbintr; + EHCI_HCOR->usbsts = usbsts; + + if (usbsts & EHCI_USBSTS_INT) { + ehci_scan_async_list(bus); + ehci_scan_periodic_list(bus); +#ifdef CONFIG_USB_EHCI_ISO + ehci_scan_isochronous_list(bus); +#endif + } + + if (usbsts & EHCI_USBSTS_ERR) { + ehci_scan_async_list(bus); + ehci_scan_periodic_list(bus); +#ifdef CONFIG_USB_EHCI_ISO + ehci_scan_isochronous_list(bus); +#endif + } + + if (usbsts & EHCI_USBSTS_PCD) { + for (int port = 0; port < g_ehci_hcd[bus->hcd.hcd_id].n_ports; port++) { + uint32_t portsc = EHCI_HCOR->portsc[port]; + + if (portsc & EHCI_PORTSC_CSC) { + if ((portsc & EHCI_PORTSC_CCS) == EHCI_PORTSC_CCS) { + } else { +#if defined(CONFIG_USB_EHCI_NXP) + /* kUSB_ControllerEhci0 and kUSB_ControllerEhci1*/ + extern void USB_EhcihostPhyDisconnectDetectCmd(uint8_t controllerId, uint8_t enable); + USB_EhcihostPhyDisconnectDetectCmd(2 + busid, 0); +#endif + } + bus->hcd.roothub.int_buffer[0] |= (1 << (port + 1)); + usbh_hub_thread_wakeup(&bus->hcd.roothub); + } + } + } + + if (usbsts & EHCI_USBSTS_IAA) { + for (uint8_t index = 0; index < CONFIG_USB_EHCI_QH_NUM; index++) { + struct ehci_qh_hw *qh = &ehci_qh_pool[bus->hcd.hcd_id][index]; + if (qh->remove_in_iaad) { + ehci_urb_waitup(bus, qh->urb); + } + } + } + + if (usbsts & EHCI_USBSTS_FATAL) { + } +} \ No newline at end of file diff --git a/kernel/cherryusb/port/ehci/usb_hc_ehci.h b/kernel/cherryusb/port/ehci/usb_hc_ehci.h new file mode 100644 index 0000000..b39b51a --- /dev/null +++ b/kernel/cherryusb/port/ehci/usb_hc_ehci.h @@ -0,0 +1,102 @@ +/* + * Copyright (c) 2022, sakumisu + * + * SPDX-License-Identifier: Apache-2.0 + */ +#ifndef _USB_EHCI_PRIV_H +#define _USB_EHCI_PRIV_H + +#include "usbh_core.h" +#include "usbh_hub.h" +#include "usb_ehci_reg.h" + +#define EHCI_HCCR ((struct ehci_hccr *)(uintptr_t)(bus->hcd.reg_base + CONFIG_USB_EHCI_HCCR_OFFSET)) +#define EHCI_HCOR ((struct ehci_hcor *)(uintptr_t)(bus->hcd.reg_base + CONFIG_USB_EHCI_HCCR_OFFSET + g_ehci_hcd[bus->hcd.hcd_id].hcor_offset)) + +#define EHCI_PTR2ADDR(x) ((uintptr_t)(x) & ~0x1F) +#define EHCI_ADDR2QH(x) ((struct ehci_qh_hw *)(uintptr_t)((uintptr_t)(x) & ~0x1F)) +#define EHCI_ADDR2QTD(x) ((struct ehci_qtd_hw *)(uintptr_t)((uintptr_t)(x) & ~0x1F)) +#define EHCI_ADDR2ITD(x) ((struct ehci_itd_hw *)(uintptr_t)((uintptr_t)(x) & ~0x1F)) + +#ifndef CONFIG_USB_EHCI_QH_NUM +#define CONFIG_USB_EHCI_QH_NUM 10 +#endif +#ifndef CONFIG_USB_EHCI_QTD_NUM +#define CONFIG_USB_EHCI_QTD_NUM (CONFIG_USB_EHCI_QH_NUM * 3) +#endif +#ifndef CONFIG_USB_EHCI_ITD_NUM +#define CONFIG_USB_EHCI_ITD_NUM 5 +#endif +#ifndef CONFIG_USB_EHCI_ISO_NUM +#define CONFIG_USB_EHCI_ISO_NUM 4 +#endif + +#if CONFIG_USB_ALIGN_SIZE <= 32 +#define CONFIG_USB_EHCI_ALIGN_SIZE 32 +#elif CONFIG_USB_ALIGN_SIZE <= 64 +#define CONFIG_USB_EHCI_ALIGN_SIZE 64 +#else +#error "CONFIG_USB_ALIGN_SIZE must be 32 or 64" +#endif + +#if CONFIG_USB_EHCI_QTD_NUM < 9 +#error CONFIG_USB_EHCI_QTD_NUM is too small, recommand CONFIG_USB_EHCI_QH_NUM * 3 +#endif + +struct ehci_qtd_hw { + struct ehci_qtd hw; +#if defined(CONFIG_USB_EHCI_DESC_DCACHE_ENABLE) && (CONFIG_USB_ALIGN_SIZE == 64) + uint8_t pad[32]; +#endif + bool inuse; + struct usbh_urb *urb; + uintptr_t bufaddr; + uint32_t length; +} __attribute__((aligned(CONFIG_USB_EHCI_ALIGN_SIZE))); + +struct ehci_qh_hw { + struct ehci_qh hw; +#if defined(CONFIG_USB_EHCI_DESC_DCACHE_ENABLE) + uint16_t pad[16]; +#endif + bool inuse; + uint32_t first_qtd; + struct usbh_urb *urb; + usb_osal_sem_t waitsem; + uint8_t remove_in_iaad; +} __attribute__((aligned(CONFIG_USB_EHCI_ALIGN_SIZE))); + +struct ehci_itd_hw { + struct ehci_itd hw; + struct usbh_urb *urb; + uint16_t start_frame; + uint8_t mf_unmask; + uint8_t mf_valid; + uint32_t pkt_idx[8]; + bool dir_in; +} __attribute__((aligned(CONFIG_USB_EHCI_ALIGN_SIZE))); + +struct ehci_iso_hw { + struct ehci_itd_hw itd_pool[CONFIG_USB_EHCI_ITD_NUM]; + uint32_t itd_num; +}; + +struct ehci_hcd { + bool ehci_iso_used[CONFIG_USB_EHCI_ISO_NUM]; + bool ppc; /* Port Power Control */ + bool has_tt; /* if use tt instead of Companion Controller */ + uint8_t n_cc; /* Number of Companion Controller */ + uint8_t n_pcc; /* Number of ports supported per companion host controller */ + uint8_t n_ports; + uint8_t hcor_offset; +}; + +extern struct ehci_hcd g_ehci_hcd[CONFIG_USBHOST_MAX_BUS]; +extern uint32_t g_framelist[CONFIG_USBHOST_MAX_BUS][USB_ALIGN_UP(CONFIG_USB_EHCI_FRAME_LIST_SIZE, 1024)]; +extern uint8_t usbh_get_port_speed(struct usbh_bus *bus, const uint8_t port); + +int ehci_iso_urb_init(struct usbh_bus *bus, struct usbh_urb *urb); +void ehci_kill_iso_urb(struct usbh_bus *bus, struct usbh_urb *urb); +void ehci_scan_isochronous_list(struct usbh_bus *bus); + +#endif diff --git a/kernel/cherryusb/port/fsdev/README.md b/kernel/cherryusb/port/fsdev/README.md new file mode 100644 index 0000000..95e9ac2 --- /dev/null +++ b/kernel/cherryusb/port/fsdev/README.md @@ -0,0 +1,30 @@ +# Note + +## Support Chip List + +## STM32 + +- STM32F042x6、STM32F048xx、STM32F070x6、STM32F070xb、STM32F072xb、STM32F078xx +- STM32F102x6、STM32F102xb、STM32F103x6、STM32F103xb、STM32F103xe、STM32F103xg +- STM32F302x8、STM32F302xc、STM32F302xe、STM32F373xc +- STM32g431xx、STM32g441xx、STM32g471xx、STM32g483xx、STM32g484xx、STM32gbk1cb +- STM32l052xx、STM32l053xx、STM32l062xx、STM32l063xx、STM32l072xx、STM32l073xx、STM32l082xx、STM32l083xx +- STM32l100xb、STM32l100xba、STM32l100xc、STM32l151xb、STM32l151xba、STM32l151xc、STM32l151xca、STM32l151xd、STM32l151xdx、STM32l151xe、STM32l152xb、STM32l152xba、STM32l152xc、STM32l152xa、STM32l152xd、STM32l152xdx、STM32l152xe、STM32l162xc、STM32l162xca、STM32l162xd、STM32l162xdx、STM32l162xe +- STM32l412xx、STM32l422xx、STM32l432xx、STM32l433xx、STM32l442xx、STM32l452xx、STM32l462xx +- STM32wb5mxx、STM32wb35xx、STM32wb55xx + +## AT32 + +- AT32F403xx、AT32F407xx、AT32F413xx + +## APM32 + +- APM32f10x + +## GD32 + +- GD32F10X + +## CH32 + +- CH32F10x、CH32V10x diff --git a/kernel/cherryusb/port/fsdev/usb_dc_fsdev.c b/kernel/cherryusb/port/fsdev/usb_dc_fsdev.c new file mode 100644 index 0000000..3e1fa22 --- /dev/null +++ b/kernel/cherryusb/port/fsdev/usb_dc_fsdev.c @@ -0,0 +1,562 @@ +/* + * Copyright (c) 2022, sakumisu + * + * SPDX-License-Identifier: Apache-2.0 + */ +#include "usbd_core.h" + +#if (CONFIG_USB_DBG_LEVEL >= USB_DBG_LOG) +#error "fsdev cannot enable USB_DBG_LOG" +#endif + +#ifndef CONFIG_USBDEV_FSDEV_PMA_ACCESS +#error "please define CONFIG_USBDEV_FSDEV_PMA_ACCESS in usb_config.h" +#endif + +#define PMA_ACCESS CONFIG_USBDEV_FSDEV_PMA_ACCESS +#include "usb_fsdev_reg.h" + +#ifndef CONFIG_USB_FSDEV_RAM_SIZE +#define CONFIG_USB_FSDEV_RAM_SIZE 512 +#endif + +#undef CONFIG_USBDEV_EP_NUM +#define CONFIG_USBDEV_EP_NUM 8 + +#define USB ((USB_TypeDef *)g_usbdev_bus[0].reg_base) + +#define USB_BTABLE_SIZE (8 * CONFIG_USBDEV_EP_NUM) + +static void fsdev_write_pma(USB_TypeDef *USBx, uint8_t *pbUsrBuf, uint16_t wPMABufAddr, uint16_t wNBytes); +static void fsdev_read_pma(USB_TypeDef *USBx, uint8_t *pbUsrBuf, uint16_t wPMABufAddr, uint16_t wNBytes); + +/* Endpoint state */ +struct fsdev_ep_state { + uint16_t ep_mps; /* Endpoint max packet size */ + uint8_t ep_type; /* Endpoint type */ + uint8_t ep_stalled; /* Endpoint stall flag */ + uint8_t ep_enable; /* Endpoint enable */ + uint16_t ep_pma_buf_len; /* Previously allocated buffer size */ + uint16_t ep_pma_addr; /* ep pmd allocated addr */ + uint8_t *xfer_buf; + uint32_t xfer_len; + uint32_t actual_xfer_len; +}; + +/* Driver state */ +struct fsdev_udc { + struct usb_setup_packet setup; + volatile uint8_t dev_addr; /*!< USB Address */ + volatile uint32_t pma_offset; /*!< pma offset */ + struct fsdev_ep_state in_ep[CONFIG_USBDEV_EP_NUM]; /*!< IN endpoint parameters*/ + struct fsdev_ep_state out_ep[CONFIG_USBDEV_EP_NUM]; /*!< OUT endpoint parameters */ +} g_fsdev_udc; + +__WEAK void usb_dc_low_level_init(void) +{ +} + +__WEAK void usb_dc_low_level_deinit(void) +{ +} + +int usb_dc_init(uint8_t busid) +{ + usb_dc_low_level_init(); + + /* Init Device */ + /* CNTR_FRES = 1 */ + USB->CNTR = (uint16_t)USB_CNTR_FRES; + + /* CNTR_FRES = 0 */ + USB->CNTR = 0U; + + /* Clear pending interrupts */ + USB->ISTR = 0U; + + /*Set Btable Address*/ + USB->BTABLE = BTABLE_ADDRESS; + + uint32_t winterruptmask; + + /* Set winterruptmask variable */ + winterruptmask = USB_CNTR_CTRM | USB_CNTR_WKUPM | + USB_CNTR_SUSPM | USB_CNTR_ERRM | + USB_CNTR_ESOFM | USB_CNTR_RESETM; + +#ifdef CONFIG_USBDEV_SOF_ENABLE + winterruptmask |= USB_CNTR_SOFM; +#endif + + /* Set interrupt mask */ + USB->CNTR = (uint16_t)winterruptmask; + + /* Enabling DP Pull-UP bit to Connect internal PU resistor on USB DP line */ + USB->BCDR |= (uint16_t)USB_BCDR_DPPU; + + return 0; +} + +int usb_dc_deinit(uint8_t busid) +{ + /* disable all interrupts and force USB reset */ + USB->CNTR = (uint16_t)USB_CNTR_FRES; + + /* clear interrupt status register */ + USB->ISTR = 0U; + + /* switch-off device */ + USB->CNTR = (uint16_t)(USB_CNTR_FRES | USB_CNTR_PDWN); + + usb_dc_low_level_deinit(); + return 0; +} + +int usbd_set_address(uint8_t busid, const uint8_t addr) +{ + if (addr == 0U) { + /* set device address and enable function */ + USB->DADDR = (uint16_t)USB_DADDR_EF; + } + + g_fsdev_udc.dev_addr = addr; + return 0; +} + +int usbd_set_remote_wakeup(uint8_t busid) +{ + return -1; +} + +uint8_t usbd_get_port_speed(uint8_t busid) +{ + return USB_SPEED_FULL; +} + +int usbd_ep_open(uint8_t busid, const struct usb_endpoint_descriptor *ep) +{ + uint8_t ep_idx = USB_EP_GET_IDX(ep->bEndpointAddress); + + USB_ASSERT_MSG(ep_idx < CONFIG_USBDEV_EP_NUM, "Ep addr %02x overflow", ep->bEndpointAddress); + USB_ASSERT_MSG(USB_GET_ENDPOINT_TYPE(ep->bmAttributes) != USB_ENDPOINT_TYPE_ISOCHRONOUS, "iso endpoint not support in fsdev"); + + uint16_t wEpRegVal; + + /* initialize Endpoint */ + switch (USB_GET_ENDPOINT_TYPE(ep->bmAttributes)) { + case USB_ENDPOINT_TYPE_CONTROL: + wEpRegVal = USB_EP_CONTROL; + break; + + case USB_ENDPOINT_TYPE_BULK: + wEpRegVal = USB_EP_BULK; + break; + + case USB_ENDPOINT_TYPE_INTERRUPT: + wEpRegVal = USB_EP_INTERRUPT; + break; + + case USB_ENDPOINT_TYPE_ISOCHRONOUS: + wEpRegVal = USB_EP_ISOCHRONOUS; + break; + + default: + return -1; + } + + PCD_SET_EPTYPE(USB, ep_idx, wEpRegVal); + + PCD_SET_EP_ADDRESS(USB, ep_idx, ep_idx); + if (USB_EP_DIR_IS_OUT(ep->bEndpointAddress)) { + g_fsdev_udc.out_ep[ep_idx].ep_mps = USB_GET_MAXPACKETSIZE(ep->wMaxPacketSize); + g_fsdev_udc.out_ep[ep_idx].ep_type = USB_GET_ENDPOINT_TYPE(ep->bmAttributes); + g_fsdev_udc.out_ep[ep_idx].ep_enable = true; + if (g_fsdev_udc.out_ep[ep_idx].ep_mps > g_fsdev_udc.out_ep[ep_idx].ep_pma_buf_len) { + USB_ASSERT_MSG((g_fsdev_udc.pma_offset + g_fsdev_udc.out_ep[ep_idx].ep_mps) <= CONFIG_USB_FSDEV_RAM_SIZE, + "Ep pma %02x overflow", ep->bEndpointAddress); + + g_fsdev_udc.out_ep[ep_idx].ep_pma_buf_len = USB_GET_MAXPACKETSIZE(ep->wMaxPacketSize); + g_fsdev_udc.out_ep[ep_idx].ep_pma_addr = g_fsdev_udc.pma_offset; + /*Set the endpoint Receive buffer address */ + PCD_SET_EP_RX_ADDRESS(USB, ep_idx, g_fsdev_udc.pma_offset); + g_fsdev_udc.pma_offset += USB_GET_MAXPACKETSIZE(ep->wMaxPacketSize); + } + /*Set the endpoint Receive buffer counter*/ + PCD_SET_EP_RX_CNT(USB, ep_idx, USB_GET_MAXPACKETSIZE(ep->wMaxPacketSize)); + PCD_CLEAR_RX_DTOG(USB, ep_idx); + } else { + g_fsdev_udc.in_ep[ep_idx].ep_mps = USB_GET_MAXPACKETSIZE(ep->wMaxPacketSize); + g_fsdev_udc.in_ep[ep_idx].ep_type = USB_GET_ENDPOINT_TYPE(ep->bmAttributes); + g_fsdev_udc.in_ep[ep_idx].ep_enable = true; + if (g_fsdev_udc.in_ep[ep_idx].ep_mps > g_fsdev_udc.in_ep[ep_idx].ep_pma_buf_len) { + USB_ASSERT_MSG((g_fsdev_udc.pma_offset + g_fsdev_udc.in_ep[ep_idx].ep_mps) <= CONFIG_USB_FSDEV_RAM_SIZE, + "Ep pma %02x overflow", ep->bEndpointAddress); + + g_fsdev_udc.in_ep[ep_idx].ep_pma_buf_len = USB_GET_MAXPACKETSIZE(ep->wMaxPacketSize); + g_fsdev_udc.in_ep[ep_idx].ep_pma_addr = g_fsdev_udc.pma_offset; + /*Set the endpoint Transmit buffer address */ + PCD_SET_EP_TX_ADDRESS(USB, ep_idx, g_fsdev_udc.pma_offset); + g_fsdev_udc.pma_offset += USB_GET_MAXPACKETSIZE(ep->wMaxPacketSize); + } + + PCD_CLEAR_TX_DTOG(USB, ep_idx); + if (USB_GET_ENDPOINT_TYPE(ep->bmAttributes) != USB_ENDPOINT_TYPE_ISOCHRONOUS) { + /* Configure NAK status for the Endpoint */ + PCD_SET_EP_TX_STATUS(USB, ep_idx, USB_EP_TX_NAK); + } else { + /* Configure TX Endpoint to disabled state */ + PCD_SET_EP_TX_STATUS(USB, ep_idx, USB_EP_TX_DIS); + } + } + return 0; +} + +int usbd_ep_close(uint8_t busid, const uint8_t ep) +{ + uint8_t ep_idx = USB_EP_GET_IDX(ep); + + if (USB_EP_DIR_IS_OUT(ep)) { + PCD_CLEAR_RX_DTOG(USB, ep_idx); + + /* Configure DISABLE status for the Endpoint*/ + PCD_SET_EP_RX_STATUS(USB, ep_idx, USB_EP_RX_DIS); + } else { + PCD_CLEAR_TX_DTOG(USB, ep_idx); + + /* Configure DISABLE status for the Endpoint*/ + PCD_SET_EP_TX_STATUS(USB, ep_idx, USB_EP_TX_DIS); + } + return 0; +} + +int usbd_ep_set_stall(uint8_t busid, const uint8_t ep) +{ + uint8_t ep_idx = USB_EP_GET_IDX(ep); + + if (USB_EP_DIR_IS_OUT(ep)) { + PCD_SET_EP_RX_STATUS(USB, ep_idx, USB_EP_RX_STALL); + } else { + PCD_SET_EP_TX_STATUS(USB, ep_idx, USB_EP_TX_STALL); + } + return 0; +} + +int usbd_ep_clear_stall(uint8_t busid, const uint8_t ep) +{ + uint8_t ep_idx = USB_EP_GET_IDX(ep); + + if (USB_EP_DIR_IS_OUT(ep)) { + PCD_CLEAR_RX_DTOG(USB, ep_idx); + /* Configure VALID status for the Endpoint */ + PCD_SET_EP_RX_STATUS(USB, ep_idx, USB_EP_RX_VALID); + } else { + PCD_CLEAR_TX_DTOG(USB, ep_idx); + + if (g_fsdev_udc.in_ep[ep_idx].ep_type != USB_ENDPOINT_TYPE_ISOCHRONOUS) { + /* Configure NAK status for the Endpoint */ + PCD_SET_EP_TX_STATUS(USB, ep_idx, USB_EP_TX_NAK); + } + } + return 0; +} + +int usbd_ep_is_stalled(uint8_t busid, const uint8_t ep, uint8_t *stalled) +{ + uint8_t ep_idx = USB_EP_GET_IDX(ep); + + if (USB_EP_DIR_IS_OUT(ep)) { + if (PCD_GET_EP_RX_STATUS(USB, ep_idx) & USB_EP_RX_STALL) { + *stalled = 1; + } else { + *stalled = 0; + } + } else { + if (PCD_GET_EP_TX_STATUS(USB, ep_idx) & USB_EP_TX_STALL) { + *stalled = 1; + } else { + *stalled = 0; + } + } + return 0; +} + +int usbd_ep_start_write(uint8_t busid, const uint8_t ep, const uint8_t *data, uint32_t data_len) +{ + uint8_t ep_idx = USB_EP_GET_IDX(ep); + + if (!data && data_len) { + return -1; + } + + if (!g_fsdev_udc.in_ep[ep_idx].ep_enable) { + return -2; + } + + g_fsdev_udc.in_ep[ep_idx].xfer_buf = (uint8_t *)data; + g_fsdev_udc.in_ep[ep_idx].xfer_len = data_len; + g_fsdev_udc.in_ep[ep_idx].actual_xfer_len = 0; + + data_len = MIN(data_len, g_fsdev_udc.in_ep[ep_idx].ep_mps); + + fsdev_write_pma(USB, (uint8_t *)data, g_fsdev_udc.in_ep[ep_idx].ep_pma_addr, (uint16_t)data_len); + PCD_SET_EP_TX_CNT(USB, ep_idx, (uint16_t)data_len); + PCD_SET_EP_TX_STATUS(USB, ep_idx, USB_EP_TX_VALID); + + return 0; +} + +int usbd_ep_start_read(uint8_t busid, const uint8_t ep, uint8_t *data, uint32_t data_len) +{ + uint8_t ep_idx = USB_EP_GET_IDX(ep); + + if (!data && data_len) { + return -1; + } + if (!g_fsdev_udc.out_ep[ep_idx].ep_enable) { + return -2; + } + + g_fsdev_udc.out_ep[ep_idx].xfer_buf = data; + g_fsdev_udc.out_ep[ep_idx].xfer_len = data_len; + g_fsdev_udc.out_ep[ep_idx].actual_xfer_len = 0; + + PCD_SET_EP_RX_STATUS(USB, ep_idx, USB_EP_RX_VALID); + + return 0; +} + +void USBD_IRQHandler(uint8_t busid) +{ + uint16_t wIstr, wEPVal; + uint8_t ep_idx; + uint8_t read_count; + uint16_t write_count; + uint16_t store_ep[8]; + + wIstr = USB->ISTR; + if (wIstr & USB_ISTR_CTR) { + while ((USB->ISTR & USB_ISTR_CTR) != 0U) { + wIstr = USB->ISTR; + + /* extract highest priority endpoint number */ + ep_idx = (uint8_t)(wIstr & USB_ISTR_EP_ID); + + if (ep_idx == 0U) { + if ((wIstr & USB_ISTR_DIR) == 0U) { + PCD_CLEAR_TX_EP_CTR(USB, ep_idx); + + write_count = PCD_GET_EP_TX_CNT(USB, ep_idx); + + g_fsdev_udc.in_ep[ep_idx].xfer_buf += write_count; + g_fsdev_udc.in_ep[ep_idx].xfer_len -= write_count; + g_fsdev_udc.in_ep[ep_idx].actual_xfer_len += write_count; + + usbd_event_ep_in_complete_handler(0, ep_idx | 0x80, g_fsdev_udc.in_ep[ep_idx].actual_xfer_len); + + if (g_fsdev_udc.setup.wLength == 0) { + /* In status, start reading setup */ + usbd_ep_start_read(0, 0x00, NULL, 0); + } else if (g_fsdev_udc.setup.wLength && ((g_fsdev_udc.setup.bmRequestType & USB_REQUEST_DIR_MASK) == USB_REQUEST_DIR_OUT)) { + /* In status, start reading setup */ + usbd_ep_start_read(0, 0x00, NULL, 0); + } + + if ((g_fsdev_udc.dev_addr > 0U) && (write_count == 0U)) { + USB->DADDR = ((uint16_t)g_fsdev_udc.dev_addr | USB_DADDR_EF); + g_fsdev_udc.dev_addr = 0U; + } + + } else { + wEPVal = PCD_GET_ENDPOINT(USB, ep_idx); + + if ((wEPVal & USB_EP_SETUP) != 0U) { + PCD_CLEAR_RX_EP_CTR(USB, ep_idx); + + read_count = PCD_GET_EP_RX_CNT(USB, ep_idx); + fsdev_read_pma(USB, (uint8_t *)&g_fsdev_udc.setup, g_fsdev_udc.out_ep[ep_idx].ep_pma_addr, (uint16_t)read_count); + + usbd_event_ep0_setup_complete_handler(0, (uint8_t *)&g_fsdev_udc.setup); + + } else if ((wEPVal & USB_EP_CTR_RX) != 0U) { + PCD_CLEAR_RX_EP_CTR(USB, ep_idx); + + read_count = PCD_GET_EP_RX_CNT(USB, ep_idx); + + fsdev_read_pma(USB, g_fsdev_udc.out_ep[ep_idx].xfer_buf, g_fsdev_udc.out_ep[ep_idx].ep_pma_addr, (uint16_t)read_count); + + g_fsdev_udc.out_ep[ep_idx].xfer_buf += read_count; + g_fsdev_udc.out_ep[ep_idx].xfer_len -= read_count; + g_fsdev_udc.out_ep[ep_idx].actual_xfer_len += read_count; + + usbd_event_ep_out_complete_handler(0, ep_idx, g_fsdev_udc.out_ep[ep_idx].actual_xfer_len); + + if (read_count == 0) { + /* Out status, start reading setup */ + usbd_ep_start_read(0, 0x00, NULL, 0); + } + } + } + } else { + wEPVal = PCD_GET_ENDPOINT(USB, ep_idx); + + if ((wEPVal & USB_EP_CTR_RX) != 0U) { + PCD_CLEAR_RX_EP_CTR(USB, ep_idx); + read_count = PCD_GET_EP_RX_CNT(USB, ep_idx); + fsdev_read_pma(USB, g_fsdev_udc.out_ep[ep_idx].xfer_buf, g_fsdev_udc.out_ep[ep_idx].ep_pma_addr, (uint16_t)read_count); + g_fsdev_udc.out_ep[ep_idx].xfer_buf += read_count; + g_fsdev_udc.out_ep[ep_idx].xfer_len -= read_count; + g_fsdev_udc.out_ep[ep_idx].actual_xfer_len += read_count; + + if ((read_count < g_fsdev_udc.out_ep[ep_idx].ep_mps) || + (g_fsdev_udc.out_ep[ep_idx].xfer_len == 0)) { + usbd_event_ep_out_complete_handler(0, ep_idx, g_fsdev_udc.out_ep[ep_idx].actual_xfer_len); + } else { + PCD_SET_EP_RX_STATUS(USB, ep_idx, USB_EP_RX_VALID); + } + } + + if ((wEPVal & USB_EP_CTR_TX) != 0U) { + PCD_CLEAR_TX_EP_CTR(USB, ep_idx); + write_count = PCD_GET_EP_TX_CNT(USB, ep_idx); + + g_fsdev_udc.in_ep[ep_idx].xfer_buf += write_count; + g_fsdev_udc.in_ep[ep_idx].xfer_len -= write_count; + g_fsdev_udc.in_ep[ep_idx].actual_xfer_len += write_count; + + if (g_fsdev_udc.in_ep[ep_idx].xfer_len == 0) { + usbd_event_ep_in_complete_handler(0, ep_idx | 0x80, g_fsdev_udc.in_ep[ep_idx].actual_xfer_len); + } else { + write_count = MIN(g_fsdev_udc.in_ep[ep_idx].xfer_len, g_fsdev_udc.in_ep[ep_idx].ep_mps); + fsdev_write_pma(USB, g_fsdev_udc.in_ep[ep_idx].xfer_buf, g_fsdev_udc.in_ep[ep_idx].ep_pma_addr, (uint16_t)write_count); + PCD_SET_EP_TX_CNT(USB, ep_idx, write_count); + PCD_SET_EP_TX_STATUS(USB, ep_idx, USB_EP_TX_VALID); + } + } + } + } + } + if (wIstr & USB_ISTR_RESET) { + memset(&g_fsdev_udc, 0, sizeof(struct fsdev_udc)); + g_fsdev_udc.pma_offset = USB_BTABLE_SIZE; + usbd_event_reset_handler(0); + /* start reading setup packet */ + PCD_SET_EP_RX_STATUS(USB, 0, USB_EP_RX_VALID); + USB->ISTR &= (uint16_t)(~USB_ISTR_RESET); + } + if (wIstr & USB_ISTR_PMAOVR) { + USB->ISTR &= (uint16_t)(~USB_ISTR_PMAOVR); + } + if (wIstr & USB_ISTR_ERR) { + USB->ISTR &= (uint16_t)(~USB_ISTR_ERR); + } + if (wIstr & USB_ISTR_WKUP) { + USB->CNTR &= (uint16_t) ~(USB_CNTR_LP_MODE); + USB->CNTR &= (uint16_t) ~(USB_CNTR_FSUSP); + + USB->ISTR &= (uint16_t)(~USB_ISTR_WKUP); + } + if (wIstr & USB_ISTR_SUSP) { + /* WA: To Clear Wakeup flag if raised with suspend signal */ + + /* Store Endpoint register */ + for (uint8_t i = 0U; i < 8U; i++) { + store_ep[i] = PCD_GET_ENDPOINT(USB, i); + } + + /* FORCE RESET */ + USB->CNTR |= (uint16_t)(USB_CNTR_FRES); + + /* CLEAR RESET */ + USB->CNTR &= (uint16_t)(~USB_CNTR_FRES); + + /* wait for reset flag in ISTR */ + while ((USB->ISTR & USB_ISTR_RESET) == 0U) { + } + + /* Clear Reset Flag */ + USB->ISTR &= (uint16_t)(~USB_ISTR_RESET); + /* Restore Registre */ + for (uint8_t i = 0U; i < 8U; i++) { + PCD_SET_ENDPOINT(USB, i, store_ep[i]); + } + + /* Force low-power mode in the macrocell */ + USB->CNTR |= (uint16_t)USB_CNTR_FSUSP; + + /* clear of the ISTR bit must be done after setting of CNTR_FSUSP */ + USB->ISTR &= (uint16_t)(~USB_ISTR_SUSP); + + USB->CNTR |= (uint16_t)USB_CNTR_LP_MODE; + } +#ifdef CONFIG_USBDEV_SOF_ENABLE + if (wIstr & USB_ISTR_SOF) { + USB->ISTR &= (uint16_t)(~USB_ISTR_SOF); + usbd_event_sof_handler(0); + } +#endif + if (wIstr & USB_ISTR_ESOF) { + USB->ISTR &= (uint16_t)(~USB_ISTR_ESOF); + } +} + +static void fsdev_write_pma(USB_TypeDef *USBx, uint8_t *pbUsrBuf, uint16_t wPMABufAddr, uint16_t wNBytes) +{ + uint32_t n = ((uint32_t)wNBytes + 1U) >> 1; + uint32_t BaseAddr = (uint32_t)USBx; + uint32_t i, temp1, temp2; + __IO uint16_t *pdwVal; + uint8_t *pBuf = pbUsrBuf; + + pdwVal = (__IO uint16_t *)(BaseAddr + 0x400U + ((uint32_t)wPMABufAddr * PMA_ACCESS)); + + for (i = n; i != 0U; i--) { + temp1 = *pBuf; + pBuf++; + temp2 = temp1 | ((uint16_t)((uint16_t)*pBuf << 8)); + *pdwVal = (uint16_t)temp2; + pdwVal++; + +#if PMA_ACCESS > 1U + pdwVal++; +#endif + + pBuf++; + } +} + +/** + * @brief Copy data from packet memory area (PMA) to user memory buffer + * @param USBx USB peripheral instance register address. + * @param pbUsrBuf pointer to user memory area. + * @param wPMABufAddr address into PMA. + * @param wNBytes no. of bytes to be copied. + * @retval None + */ +static void fsdev_read_pma(USB_TypeDef *USBx, uint8_t *pbUsrBuf, uint16_t wPMABufAddr, uint16_t wNBytes) +{ + uint32_t n = (uint32_t)wNBytes >> 1; + uint32_t BaseAddr = (uint32_t)USBx; + uint32_t i, temp; + __IO uint16_t *pdwVal; + uint8_t *pBuf = pbUsrBuf; + + pdwVal = (__IO uint16_t *)(BaseAddr + 0x400U + ((uint32_t)wPMABufAddr * PMA_ACCESS)); + + for (i = n; i != 0U; i--) { + temp = *(__IO uint16_t *)pdwVal; + pdwVal++; + *pBuf = (uint8_t)((temp >> 0) & 0xFFU); + pBuf++; + *pBuf = (uint8_t)((temp >> 8) & 0xFFU); + pBuf++; + +#if PMA_ACCESS > 1U + pdwVal++; +#endif + } + + if ((wNBytes % 2U) != 0U) { + temp = *pdwVal; + *pBuf = (uint8_t)((temp >> 0) & 0xFFU); + } +} diff --git a/kernel/cherryusb/port/fsdev/usb_fsdev_reg.h b/kernel/cherryusb/port/fsdev/usb_fsdev_reg.h new file mode 100644 index 0000000..c67cf57 --- /dev/null +++ b/kernel/cherryusb/port/fsdev/usb_fsdev_reg.h @@ -0,0 +1,1684 @@ +/* + * Copyright (c) 2022, sakumisu + * + * SPDX-License-Identifier: Apache-2.0 + */ +#ifndef __USB_FSDEV_REG_H__ +#define __USB_FSDEV_REG_H__ + +#define __IO volatile /*!< Defines 'read / write' permissions */ +/** + * @brief Universal Serial Bus Full Speed Device + */ + +typedef struct +{ + __IO uint16_t EP0R; /*!< USB Endpoint 0 register, Address offset: 0x00 */ + __IO uint16_t RESERVED0; /*!< Reserved */ + __IO uint16_t EP1R; /*!< USB Endpoint 1 register, Address offset: 0x04 */ + __IO uint16_t RESERVED1; /*!< Reserved */ + __IO uint16_t EP2R; /*!< USB Endpoint 2 register, Address offset: 0x08 */ + __IO uint16_t RESERVED2; /*!< Reserved */ + __IO uint16_t EP3R; /*!< USB Endpoint 3 register, Address offset: 0x0C */ + __IO uint16_t RESERVED3; /*!< Reserved */ + __IO uint16_t EP4R; /*!< USB Endpoint 4 register, Address offset: 0x10 */ + __IO uint16_t RESERVED4; /*!< Reserved */ + __IO uint16_t EP5R; /*!< USB Endpoint 5 register, Address offset: 0x14 */ + __IO uint16_t RESERVED5; /*!< Reserved */ + __IO uint16_t EP6R; /*!< USB Endpoint 6 register, Address offset: 0x18 */ + __IO uint16_t RESERVED6; /*!< Reserved */ + __IO uint16_t EP7R; /*!< USB Endpoint 7 register, Address offset: 0x1C */ + __IO uint16_t RESERVED7[17]; /*!< Reserved */ + __IO uint16_t CNTR; /*!< Control register, Address offset: 0x40 */ + __IO uint16_t RESERVED8; /*!< Reserved */ + __IO uint16_t ISTR; /*!< Interrupt status register, Address offset: 0x44 */ + __IO uint16_t RESERVED9; /*!< Reserved */ + __IO uint16_t FNR; /*!< Frame number register, Address offset: 0x48 */ + __IO uint16_t RESERVEDA; /*!< Reserved */ + __IO uint16_t DADDR; /*!< Device address register, Address offset: 0x4C */ + __IO uint16_t RESERVEDB; /*!< Reserved */ + __IO uint16_t BTABLE; /*!< Buffer Table address register, Address offset: 0x50 */ + __IO uint16_t RESERVEDC; /*!< Reserved */ + __IO uint16_t LPMCSR; /*!< LPM Control and Status register, Address offset: 0x54 */ + __IO uint16_t RESERVEDD; /*!< Reserved */ + __IO uint16_t BCDR; /*!< Battery Charging detector register, Address offset: 0x58 */ + __IO uint16_t RESERVEDE; /*!< Reserved */ +} USB_TypeDef; + +/******************************************************************************/ +/* */ +/* USB Device FS */ +/* */ +/******************************************************************************/ + +/*!< Endpoint-specific registers */ +#define USB_EP0R USB_BASE /*!< Endpoint 0 register address */ +#define USB_EP1R (USB_BASE + 0x00000004) /*!< Endpoint 1 register address */ +#define USB_EP2R (USB_BASE + 0x00000008) /*!< Endpoint 2 register address */ +#define USB_EP3R (USB_BASE + 0x0000000C) /*!< Endpoint 3 register address */ +#define USB_EP4R (USB_BASE + 0x00000010) /*!< Endpoint 4 register address */ +#define USB_EP5R (USB_BASE + 0x00000014) /*!< Endpoint 5 register address */ +#define USB_EP6R (USB_BASE + 0x00000018) /*!< Endpoint 6 register address */ +#define USB_EP7R (USB_BASE + 0x0000001C) /*!< Endpoint 7 register address */ + +/* bit positions */ +#define USB_EP_CTR_RX_Pos (15U) +#define USB_EP_CTR_RX_Msk (0x1UL << USB_EP_CTR_RX_Pos) /*!< 0x00008000 */ +#define USB_EP_CTR_RX USB_EP_CTR_RX_Msk /*!< EndPoint Correct TRansfer RX */ +#define USB_EP_DTOG_RX_Pos (14U) +#define USB_EP_DTOG_RX_Msk (0x1UL << USB_EP_DTOG_RX_Pos) /*!< 0x00004000 */ +#define USB_EP_DTOG_RX USB_EP_DTOG_RX_Msk /*!< EndPoint Data TOGGLE RX */ +#define USB_EPRX_STAT_Pos (12U) +#define USB_EPRX_STAT_Msk (0x3UL << USB_EPRX_STAT_Pos) /*!< 0x00003000 */ +#define USB_EPRX_STAT USB_EPRX_STAT_Msk /*!< EndPoint RX STATus bit field */ +#define USB_EP_SETUP_Pos (11U) +#define USB_EP_SETUP_Msk (0x1UL << USB_EP_SETUP_Pos) /*!< 0x00000800 */ +#define USB_EP_SETUP USB_EP_SETUP_Msk /*!< EndPoint SETUP */ +#define USB_EP_T_FIELD_Pos (9U) +#define USB_EP_T_FIELD_Msk (0x3UL << USB_EP_T_FIELD_Pos) /*!< 0x00000600 */ +#define USB_EP_T_FIELD USB_EP_T_FIELD_Msk /*!< EndPoint TYPE */ +#define USB_EP_KIND_Pos (8U) +#define USB_EP_KIND_Msk (0x1UL << USB_EP_KIND_Pos) /*!< 0x00000100 */ +#define USB_EP_KIND USB_EP_KIND_Msk /*!< EndPoint KIND */ +#define USB_EP_CTR_TX_Pos (7U) +#define USB_EP_CTR_TX_Msk (0x1UL << USB_EP_CTR_TX_Pos) /*!< 0x00000080 */ +#define USB_EP_CTR_TX USB_EP_CTR_TX_Msk /*!< EndPoint Correct TRansfer TX */ +#define USB_EP_DTOG_TX_Pos (6U) +#define USB_EP_DTOG_TX_Msk (0x1UL << USB_EP_DTOG_TX_Pos) /*!< 0x00000040 */ +#define USB_EP_DTOG_TX USB_EP_DTOG_TX_Msk /*!< EndPoint Data TOGGLE TX */ +#define USB_EPTX_STAT_Pos (4U) +#define USB_EPTX_STAT_Msk (0x3UL << USB_EPTX_STAT_Pos) /*!< 0x00000030 */ +#define USB_EPTX_STAT USB_EPTX_STAT_Msk /*!< EndPoint TX STATus bit field */ +#define USB_EPADDR_FIELD_Pos (0U) +#define USB_EPADDR_FIELD_Msk (0xFUL << USB_EPADDR_FIELD_Pos) /*!< 0x0000000F */ +#define USB_EPADDR_FIELD USB_EPADDR_FIELD_Msk /*!< EndPoint ADDRess FIELD */ + +/* EndPoint REGister MASK (no toggle fields) */ +#define USB_EPREG_MASK (USB_EP_CTR_RX|USB_EP_SETUP|USB_EP_T_FIELD|USB_EP_KIND|USB_EP_CTR_TX|USB_EPADDR_FIELD) + /*!< EP_TYPE[1:0] EndPoint TYPE */ +#define USB_EP_TYPE_MASK_Pos (9U) +#define USB_EP_TYPE_MASK_Msk (0x3UL << USB_EP_TYPE_MASK_Pos) /*!< 0x00000600 */ +#define USB_EP_TYPE_MASK USB_EP_TYPE_MASK_Msk /*!< EndPoint TYPE Mask */ +#define USB_EP_BULK 0x00000000U /*!< EndPoint BULK */ +#define USB_EP_CONTROL 0x00000200U /*!< EndPoint CONTROL */ +#define USB_EP_ISOCHRONOUS 0x00000400U /*!< EndPoint ISOCHRONOUS */ +#define USB_EP_INTERRUPT 0x00000600U /*!< EndPoint INTERRUPT */ +#define USB_EP_T_MASK (~USB_EP_T_FIELD & USB_EPREG_MASK) + +#define USB_EPKIND_MASK (~USB_EP_KIND & USB_EPREG_MASK) /*!< EP_KIND EndPoint KIND */ + /*!< STAT_TX[1:0] STATus for TX transfer */ +#define USB_EP_TX_DIS 0x00000000U /*!< EndPoint TX DISabled */ +#define USB_EP_TX_STALL 0x00000010U /*!< EndPoint TX STALLed */ +#define USB_EP_TX_NAK 0x00000020U /*!< EndPoint TX NAKed */ +#define USB_EP_TX_VALID 0x00000030U /*!< EndPoint TX VALID */ +#define USB_EPTX_DTOG1 0x00000010U /*!< EndPoint TX Data TOGgle bit1 */ +#define USB_EPTX_DTOG2 0x00000020U /*!< EndPoint TX Data TOGgle bit2 */ +#define USB_EPTX_DTOGMASK (USB_EPTX_STAT|USB_EPREG_MASK) + /*!< STAT_RX[1:0] STATus for RX transfer */ +#define USB_EP_RX_DIS 0x00000000U /*!< EndPoint RX DISabled */ +#define USB_EP_RX_STALL 0x00001000U /*!< EndPoint RX STALLed */ +#define USB_EP_RX_NAK 0x00002000U /*!< EndPoint RX NAKed */ +#define USB_EP_RX_VALID 0x00003000U /*!< EndPoint RX VALID */ +#define USB_EPRX_DTOG1 0x00001000U /*!< EndPoint RX Data TOGgle bit1 */ +#define USB_EPRX_DTOG2 0x00002000U /*!< EndPoint RX Data TOGgle bit1 */ +#define USB_EPRX_DTOGMASK (USB_EPRX_STAT|USB_EPREG_MASK) + +/******************* Bit definition for USB_EP0R register *******************/ +#define USB_EP0R_EA_Pos (0U) +#define USB_EP0R_EA_Msk (0xFUL << USB_EP0R_EA_Pos) /*!< 0x0000000F */ +#define USB_EP0R_EA USB_EP0R_EA_Msk /*!< Endpoint Address */ + +#define USB_EP0R_STAT_TX_Pos (4U) +#define USB_EP0R_STAT_TX_Msk (0x3UL << USB_EP0R_STAT_TX_Pos) /*!< 0x00000030 */ +#define USB_EP0R_STAT_TX USB_EP0R_STAT_TX_Msk /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */ +#define USB_EP0R_STAT_TX_0 (0x1UL << USB_EP0R_STAT_TX_Pos) /*!< 0x00000010 */ +#define USB_EP0R_STAT_TX_1 (0x2UL << USB_EP0R_STAT_TX_Pos) /*!< 0x00000020 */ + +#define USB_EP0R_DTOG_TX_Pos (6U) +#define USB_EP0R_DTOG_TX_Msk (0x1UL << USB_EP0R_DTOG_TX_Pos) /*!< 0x00000040 */ +#define USB_EP0R_DTOG_TX USB_EP0R_DTOG_TX_Msk /*!< Data Toggle, for transmission transfers */ +#define USB_EP0R_CTR_TX_Pos (7U) +#define USB_EP0R_CTR_TX_Msk (0x1UL << USB_EP0R_CTR_TX_Pos) /*!< 0x00000080 */ +#define USB_EP0R_CTR_TX USB_EP0R_CTR_TX_Msk /*!< Correct Transfer for transmission */ +#define USB_EP0R_EP_KIND_Pos (8U) +#define USB_EP0R_EP_KIND_Msk (0x1UL << USB_EP0R_EP_KIND_Pos) /*!< 0x00000100 */ +#define USB_EP0R_EP_KIND USB_EP0R_EP_KIND_Msk /*!< Endpoint Kind */ + +#define USB_EP0R_EP_TYPE_Pos (9U) +#define USB_EP0R_EP_TYPE_Msk (0x3UL << USB_EP0R_EP_TYPE_Pos) /*!< 0x00000600 */ +#define USB_EP0R_EP_TYPE USB_EP0R_EP_TYPE_Msk /*!< EP_TYPE[1:0] bits (Endpoint type) */ +#define USB_EP0R_EP_TYPE_0 (0x1UL << USB_EP0R_EP_TYPE_Pos) /*!< 0x00000200 */ +#define USB_EP0R_EP_TYPE_1 (0x2UL << USB_EP0R_EP_TYPE_Pos) /*!< 0x00000400 */ + +#define USB_EP0R_SETUP_Pos (11U) +#define USB_EP0R_SETUP_Msk (0x1UL << USB_EP0R_SETUP_Pos) /*!< 0x00000800 */ +#define USB_EP0R_SETUP USB_EP0R_SETUP_Msk /*!< Setup transaction completed */ + +#define USB_EP0R_STAT_RX_Pos (12U) +#define USB_EP0R_STAT_RX_Msk (0x3UL << USB_EP0R_STAT_RX_Pos) /*!< 0x00003000 */ +#define USB_EP0R_STAT_RX USB_EP0R_STAT_RX_Msk /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */ +#define USB_EP0R_STAT_RX_0 (0x1UL << USB_EP0R_STAT_RX_Pos) /*!< 0x00001000 */ +#define USB_EP0R_STAT_RX_1 (0x2UL << USB_EP0R_STAT_RX_Pos) /*!< 0x00002000 */ + +#define USB_EP0R_DTOG_RX_Pos (14U) +#define USB_EP0R_DTOG_RX_Msk (0x1UL << USB_EP0R_DTOG_RX_Pos) /*!< 0x00004000 */ +#define USB_EP0R_DTOG_RX USB_EP0R_DTOG_RX_Msk /*!< Data Toggle, for reception transfers */ +#define USB_EP0R_CTR_RX_Pos (15U) +#define USB_EP0R_CTR_RX_Msk (0x1UL << USB_EP0R_CTR_RX_Pos) /*!< 0x00008000 */ +#define USB_EP0R_CTR_RX USB_EP0R_CTR_RX_Msk /*!< Correct Transfer for reception */ + +/******************* Bit definition for USB_EP1R register *******************/ +#define USB_EP1R_EA_Pos (0U) +#define USB_EP1R_EA_Msk (0xFUL << USB_EP1R_EA_Pos) /*!< 0x0000000F */ +#define USB_EP1R_EA USB_EP1R_EA_Msk /*!< Endpoint Address */ + +#define USB_EP1R_STAT_TX_Pos (4U) +#define USB_EP1R_STAT_TX_Msk (0x3UL << USB_EP1R_STAT_TX_Pos) /*!< 0x00000030 */ +#define USB_EP1R_STAT_TX USB_EP1R_STAT_TX_Msk /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */ +#define USB_EP1R_STAT_TX_0 (0x1UL << USB_EP1R_STAT_TX_Pos) /*!< 0x00000010 */ +#define USB_EP1R_STAT_TX_1 (0x2UL << USB_EP1R_STAT_TX_Pos) /*!< 0x00000020 */ + +#define USB_EP1R_DTOG_TX_Pos (6U) +#define USB_EP1R_DTOG_TX_Msk (0x1UL << USB_EP1R_DTOG_TX_Pos) /*!< 0x00000040 */ +#define USB_EP1R_DTOG_TX USB_EP1R_DTOG_TX_Msk /*!< Data Toggle, for transmission transfers */ +#define USB_EP1R_CTR_TX_Pos (7U) +#define USB_EP1R_CTR_TX_Msk (0x1UL << USB_EP1R_CTR_TX_Pos) /*!< 0x00000080 */ +#define USB_EP1R_CTR_TX USB_EP1R_CTR_TX_Msk /*!< Correct Transfer for transmission */ +#define USB_EP1R_EP_KIND_Pos (8U) +#define USB_EP1R_EP_KIND_Msk (0x1UL << USB_EP1R_EP_KIND_Pos) /*!< 0x00000100 */ +#define USB_EP1R_EP_KIND USB_EP1R_EP_KIND_Msk /*!< Endpoint Kind */ + +#define USB_EP1R_EP_TYPE_Pos (9U) +#define USB_EP1R_EP_TYPE_Msk (0x3UL << USB_EP1R_EP_TYPE_Pos) /*!< 0x00000600 */ +#define USB_EP1R_EP_TYPE USB_EP1R_EP_TYPE_Msk /*!< EP_TYPE[1:0] bits (Endpoint type) */ +#define USB_EP1R_EP_TYPE_0 (0x1UL << USB_EP1R_EP_TYPE_Pos) /*!< 0x00000200 */ +#define USB_EP1R_EP_TYPE_1 (0x2UL << USB_EP1R_EP_TYPE_Pos) /*!< 0x00000400 */ + +#define USB_EP1R_SETUP_Pos (11U) +#define USB_EP1R_SETUP_Msk (0x1UL << USB_EP1R_SETUP_Pos) /*!< 0x00000800 */ +#define USB_EP1R_SETUP USB_EP1R_SETUP_Msk /*!< Setup transaction completed */ + +#define USB_EP1R_STAT_RX_Pos (12U) +#define USB_EP1R_STAT_RX_Msk (0x3UL << USB_EP1R_STAT_RX_Pos) /*!< 0x00003000 */ +#define USB_EP1R_STAT_RX USB_EP1R_STAT_RX_Msk /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */ +#define USB_EP1R_STAT_RX_0 (0x1UL << USB_EP1R_STAT_RX_Pos) /*!< 0x00001000 */ +#define USB_EP1R_STAT_RX_1 (0x2UL << USB_EP1R_STAT_RX_Pos) /*!< 0x00002000 */ + +#define USB_EP1R_DTOG_RX_Pos (14U) +#define USB_EP1R_DTOG_RX_Msk (0x1UL << USB_EP1R_DTOG_RX_Pos) /*!< 0x00004000 */ +#define USB_EP1R_DTOG_RX USB_EP1R_DTOG_RX_Msk /*!< Data Toggle, for reception transfers */ +#define USB_EP1R_CTR_RX_Pos (15U) +#define USB_EP1R_CTR_RX_Msk (0x1UL << USB_EP1R_CTR_RX_Pos) /*!< 0x00008000 */ +#define USB_EP1R_CTR_RX USB_EP1R_CTR_RX_Msk /*!< Correct Transfer for reception */ + +/******************* Bit definition for USB_EP2R register *******************/ +#define USB_EP2R_EA_Pos (0U) +#define USB_EP2R_EA_Msk (0xFUL << USB_EP2R_EA_Pos) /*!< 0x0000000F */ +#define USB_EP2R_EA USB_EP2R_EA_Msk /*!< Endpoint Address */ + +#define USB_EP2R_STAT_TX_Pos (4U) +#define USB_EP2R_STAT_TX_Msk (0x3UL << USB_EP2R_STAT_TX_Pos) /*!< 0x00000030 */ +#define USB_EP2R_STAT_TX USB_EP2R_STAT_TX_Msk /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */ +#define USB_EP2R_STAT_TX_0 (0x1UL << USB_EP2R_STAT_TX_Pos) /*!< 0x00000010 */ +#define USB_EP2R_STAT_TX_1 (0x2UL << USB_EP2R_STAT_TX_Pos) /*!< 0x00000020 */ + +#define USB_EP2R_DTOG_TX_Pos (6U) +#define USB_EP2R_DTOG_TX_Msk (0x1UL << USB_EP2R_DTOG_TX_Pos) /*!< 0x00000040 */ +#define USB_EP2R_DTOG_TX USB_EP2R_DTOG_TX_Msk /*!< Data Toggle, for transmission transfers */ +#define USB_EP2R_CTR_TX_Pos (7U) +#define USB_EP2R_CTR_TX_Msk (0x1UL << USB_EP2R_CTR_TX_Pos) /*!< 0x00000080 */ +#define USB_EP2R_CTR_TX USB_EP2R_CTR_TX_Msk /*!< Correct Transfer for transmission */ +#define USB_EP2R_EP_KIND_Pos (8U) +#define USB_EP2R_EP_KIND_Msk (0x1UL << USB_EP2R_EP_KIND_Pos) /*!< 0x00000100 */ +#define USB_EP2R_EP_KIND USB_EP2R_EP_KIND_Msk /*!< Endpoint Kind */ + +#define USB_EP2R_EP_TYPE_Pos (9U) +#define USB_EP2R_EP_TYPE_Msk (0x3UL << USB_EP2R_EP_TYPE_Pos) /*!< 0x00000600 */ +#define USB_EP2R_EP_TYPE USB_EP2R_EP_TYPE_Msk /*!< EP_TYPE[1:0] bits (Endpoint type) */ +#define USB_EP2R_EP_TYPE_0 (0x1UL << USB_EP2R_EP_TYPE_Pos) /*!< 0x00000200 */ +#define USB_EP2R_EP_TYPE_1 (0x2UL << USB_EP2R_EP_TYPE_Pos) /*!< 0x00000400 */ + +#define USB_EP2R_SETUP_Pos (11U) +#define USB_EP2R_SETUP_Msk (0x1UL << USB_EP2R_SETUP_Pos) /*!< 0x00000800 */ +#define USB_EP2R_SETUP USB_EP2R_SETUP_Msk /*!< Setup transaction completed */ + +#define USB_EP2R_STAT_RX_Pos (12U) +#define USB_EP2R_STAT_RX_Msk (0x3UL << USB_EP2R_STAT_RX_Pos) /*!< 0x00003000 */ +#define USB_EP2R_STAT_RX USB_EP2R_STAT_RX_Msk /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */ +#define USB_EP2R_STAT_RX_0 (0x1UL << USB_EP2R_STAT_RX_Pos) /*!< 0x00001000 */ +#define USB_EP2R_STAT_RX_1 (0x2UL << USB_EP2R_STAT_RX_Pos) /*!< 0x00002000 */ + +#define USB_EP2R_DTOG_RX_Pos (14U) +#define USB_EP2R_DTOG_RX_Msk (0x1UL << USB_EP2R_DTOG_RX_Pos) /*!< 0x00004000 */ +#define USB_EP2R_DTOG_RX USB_EP2R_DTOG_RX_Msk /*!< Data Toggle, for reception transfers */ +#define USB_EP2R_CTR_RX_Pos (15U) +#define USB_EP2R_CTR_RX_Msk (0x1UL << USB_EP2R_CTR_RX_Pos) /*!< 0x00008000 */ +#define USB_EP2R_CTR_RX USB_EP2R_CTR_RX_Msk /*!< Correct Transfer for reception */ + +/******************* Bit definition for USB_EP3R register *******************/ +#define USB_EP3R_EA_Pos (0U) +#define USB_EP3R_EA_Msk (0xFUL << USB_EP3R_EA_Pos) /*!< 0x0000000F */ +#define USB_EP3R_EA USB_EP3R_EA_Msk /*!< Endpoint Address */ + +#define USB_EP3R_STAT_TX_Pos (4U) +#define USB_EP3R_STAT_TX_Msk (0x3UL << USB_EP3R_STAT_TX_Pos) /*!< 0x00000030 */ +#define USB_EP3R_STAT_TX USB_EP3R_STAT_TX_Msk /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */ +#define USB_EP3R_STAT_TX_0 (0x1UL << USB_EP3R_STAT_TX_Pos) /*!< 0x00000010 */ +#define USB_EP3R_STAT_TX_1 (0x2UL << USB_EP3R_STAT_TX_Pos) /*!< 0x00000020 */ + +#define USB_EP3R_DTOG_TX_Pos (6U) +#define USB_EP3R_DTOG_TX_Msk (0x1UL << USB_EP3R_DTOG_TX_Pos) /*!< 0x00000040 */ +#define USB_EP3R_DTOG_TX USB_EP3R_DTOG_TX_Msk /*!< Data Toggle, for transmission transfers */ +#define USB_EP3R_CTR_TX_Pos (7U) +#define USB_EP3R_CTR_TX_Msk (0x1UL << USB_EP3R_CTR_TX_Pos) /*!< 0x00000080 */ +#define USB_EP3R_CTR_TX USB_EP3R_CTR_TX_Msk /*!< Correct Transfer for transmission */ +#define USB_EP3R_EP_KIND_Pos (8U) +#define USB_EP3R_EP_KIND_Msk (0x1UL << USB_EP3R_EP_KIND_Pos) /*!< 0x00000100 */ +#define USB_EP3R_EP_KIND USB_EP3R_EP_KIND_Msk /*!< Endpoint Kind */ + +#define USB_EP3R_EP_TYPE_Pos (9U) +#define USB_EP3R_EP_TYPE_Msk (0x3UL << USB_EP3R_EP_TYPE_Pos) /*!< 0x00000600 */ +#define USB_EP3R_EP_TYPE USB_EP3R_EP_TYPE_Msk /*!< EP_TYPE[1:0] bits (Endpoint type) */ +#define USB_EP3R_EP_TYPE_0 (0x1UL << USB_EP3R_EP_TYPE_Pos) /*!< 0x00000200 */ +#define USB_EP3R_EP_TYPE_1 (0x2UL << USB_EP3R_EP_TYPE_Pos) /*!< 0x00000400 */ + +#define USB_EP3R_SETUP_Pos (11U) +#define USB_EP3R_SETUP_Msk (0x1UL << USB_EP3R_SETUP_Pos) /*!< 0x00000800 */ +#define USB_EP3R_SETUP USB_EP3R_SETUP_Msk /*!< Setup transaction completed */ + +#define USB_EP3R_STAT_RX_Pos (12U) +#define USB_EP3R_STAT_RX_Msk (0x3UL << USB_EP3R_STAT_RX_Pos) /*!< 0x00003000 */ +#define USB_EP3R_STAT_RX USB_EP3R_STAT_RX_Msk /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */ +#define USB_EP3R_STAT_RX_0 (0x1UL << USB_EP3R_STAT_RX_Pos) /*!< 0x00001000 */ +#define USB_EP3R_STAT_RX_1 (0x2UL << USB_EP3R_STAT_RX_Pos) /*!< 0x00002000 */ + +#define USB_EP3R_DTOG_RX_Pos (14U) +#define USB_EP3R_DTOG_RX_Msk (0x1UL << USB_EP3R_DTOG_RX_Pos) /*!< 0x00004000 */ +#define USB_EP3R_DTOG_RX USB_EP3R_DTOG_RX_Msk /*!< Data Toggle, for reception transfers */ +#define USB_EP3R_CTR_RX_Pos (15U) +#define USB_EP3R_CTR_RX_Msk (0x1UL << USB_EP3R_CTR_RX_Pos) /*!< 0x00008000 */ +#define USB_EP3R_CTR_RX USB_EP3R_CTR_RX_Msk /*!< Correct Transfer for reception */ + +/******************* Bit definition for USB_EP4R register *******************/ +#define USB_EP4R_EA_Pos (0U) +#define USB_EP4R_EA_Msk (0xFUL << USB_EP4R_EA_Pos) /*!< 0x0000000F */ +#define USB_EP4R_EA USB_EP4R_EA_Msk /*!< Endpoint Address */ + +#define USB_EP4R_STAT_TX_Pos (4U) +#define USB_EP4R_STAT_TX_Msk (0x3UL << USB_EP4R_STAT_TX_Pos) /*!< 0x00000030 */ +#define USB_EP4R_STAT_TX USB_EP4R_STAT_TX_Msk /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */ +#define USB_EP4R_STAT_TX_0 (0x1UL << USB_EP4R_STAT_TX_Pos) /*!< 0x00000010 */ +#define USB_EP4R_STAT_TX_1 (0x2UL << USB_EP4R_STAT_TX_Pos) /*!< 0x00000020 */ + +#define USB_EP4R_DTOG_TX_Pos (6U) +#define USB_EP4R_DTOG_TX_Msk (0x1UL << USB_EP4R_DTOG_TX_Pos) /*!< 0x00000040 */ +#define USB_EP4R_DTOG_TX USB_EP4R_DTOG_TX_Msk /*!< Data Toggle, for transmission transfers */ +#define USB_EP4R_CTR_TX_Pos (7U) +#define USB_EP4R_CTR_TX_Msk (0x1UL << USB_EP4R_CTR_TX_Pos) /*!< 0x00000080 */ +#define USB_EP4R_CTR_TX USB_EP4R_CTR_TX_Msk /*!< Correct Transfer for transmission */ +#define USB_EP4R_EP_KIND_Pos (8U) +#define USB_EP4R_EP_KIND_Msk (0x1UL << USB_EP4R_EP_KIND_Pos) /*!< 0x00000100 */ +#define USB_EP4R_EP_KIND USB_EP4R_EP_KIND_Msk /*!< Endpoint Kind */ + +#define USB_EP4R_EP_TYPE_Pos (9U) +#define USB_EP4R_EP_TYPE_Msk (0x3UL << USB_EP4R_EP_TYPE_Pos) /*!< 0x00000600 */ +#define USB_EP4R_EP_TYPE USB_EP4R_EP_TYPE_Msk /*!< EP_TYPE[1:0] bits (Endpoint type) */ +#define USB_EP4R_EP_TYPE_0 (0x1UL << USB_EP4R_EP_TYPE_Pos) /*!< 0x00000200 */ +#define USB_EP4R_EP_TYPE_1 (0x2UL << USB_EP4R_EP_TYPE_Pos) /*!< 0x00000400 */ + +#define USB_EP4R_SETUP_Pos (11U) +#define USB_EP4R_SETUP_Msk (0x1UL << USB_EP4R_SETUP_Pos) /*!< 0x00000800 */ +#define USB_EP4R_SETUP USB_EP4R_SETUP_Msk /*!< Setup transaction completed */ + +#define USB_EP4R_STAT_RX_Pos (12U) +#define USB_EP4R_STAT_RX_Msk (0x3UL << USB_EP4R_STAT_RX_Pos) /*!< 0x00003000 */ +#define USB_EP4R_STAT_RX USB_EP4R_STAT_RX_Msk /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */ +#define USB_EP4R_STAT_RX_0 (0x1UL << USB_EP4R_STAT_RX_Pos) /*!< 0x00001000 */ +#define USB_EP4R_STAT_RX_1 (0x2UL << USB_EP4R_STAT_RX_Pos) /*!< 0x00002000 */ + +#define USB_EP4R_DTOG_RX_Pos (14U) +#define USB_EP4R_DTOG_RX_Msk (0x1UL << USB_EP4R_DTOG_RX_Pos) /*!< 0x00004000 */ +#define USB_EP4R_DTOG_RX USB_EP4R_DTOG_RX_Msk /*!< Data Toggle, for reception transfers */ +#define USB_EP4R_CTR_RX_Pos (15U) +#define USB_EP4R_CTR_RX_Msk (0x1UL << USB_EP4R_CTR_RX_Pos) /*!< 0x00008000 */ +#define USB_EP4R_CTR_RX USB_EP4R_CTR_RX_Msk /*!< Correct Transfer for reception */ + +/******************* Bit definition for USB_EP5R register *******************/ +#define USB_EP5R_EA_Pos (0U) +#define USB_EP5R_EA_Msk (0xFUL << USB_EP5R_EA_Pos) /*!< 0x0000000F */ +#define USB_EP5R_EA USB_EP5R_EA_Msk /*!< Endpoint Address */ + +#define USB_EP5R_STAT_TX_Pos (4U) +#define USB_EP5R_STAT_TX_Msk (0x3UL << USB_EP5R_STAT_TX_Pos) /*!< 0x00000030 */ +#define USB_EP5R_STAT_TX USB_EP5R_STAT_TX_Msk /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */ +#define USB_EP5R_STAT_TX_0 (0x1UL << USB_EP5R_STAT_TX_Pos) /*!< 0x00000010 */ +#define USB_EP5R_STAT_TX_1 (0x2UL << USB_EP5R_STAT_TX_Pos) /*!< 0x00000020 */ + +#define USB_EP5R_DTOG_TX_Pos (6U) +#define USB_EP5R_DTOG_TX_Msk (0x1UL << USB_EP5R_DTOG_TX_Pos) /*!< 0x00000040 */ +#define USB_EP5R_DTOG_TX USB_EP5R_DTOG_TX_Msk /*!< Data Toggle, for transmission transfers */ +#define USB_EP5R_CTR_TX_Pos (7U) +#define USB_EP5R_CTR_TX_Msk (0x1UL << USB_EP5R_CTR_TX_Pos) /*!< 0x00000080 */ +#define USB_EP5R_CTR_TX USB_EP5R_CTR_TX_Msk /*!< Correct Transfer for transmission */ +#define USB_EP5R_EP_KIND_Pos (8U) +#define USB_EP5R_EP_KIND_Msk (0x1UL << USB_EP5R_EP_KIND_Pos) /*!< 0x00000100 */ +#define USB_EP5R_EP_KIND USB_EP5R_EP_KIND_Msk /*!< Endpoint Kind */ + +#define USB_EP5R_EP_TYPE_Pos (9U) +#define USB_EP5R_EP_TYPE_Msk (0x3UL << USB_EP5R_EP_TYPE_Pos) /*!< 0x00000600 */ +#define USB_EP5R_EP_TYPE USB_EP5R_EP_TYPE_Msk /*!< EP_TYPE[1:0] bits (Endpoint type) */ +#define USB_EP5R_EP_TYPE_0 (0x1UL << USB_EP5R_EP_TYPE_Pos) /*!< 0x00000200 */ +#define USB_EP5R_EP_TYPE_1 (0x2UL << USB_EP5R_EP_TYPE_Pos) /*!< 0x00000400 */ + +#define USB_EP5R_SETUP_Pos (11U) +#define USB_EP5R_SETUP_Msk (0x1UL << USB_EP5R_SETUP_Pos) /*!< 0x00000800 */ +#define USB_EP5R_SETUP USB_EP5R_SETUP_Msk /*!< Setup transaction completed */ + +#define USB_EP5R_STAT_RX_Pos (12U) +#define USB_EP5R_STAT_RX_Msk (0x3UL << USB_EP5R_STAT_RX_Pos) /*!< 0x00003000 */ +#define USB_EP5R_STAT_RX USB_EP5R_STAT_RX_Msk /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */ +#define USB_EP5R_STAT_RX_0 (0x1UL << USB_EP5R_STAT_RX_Pos) /*!< 0x00001000 */ +#define USB_EP5R_STAT_RX_1 (0x2UL << USB_EP5R_STAT_RX_Pos) /*!< 0x00002000 */ + +#define USB_EP5R_DTOG_RX_Pos (14U) +#define USB_EP5R_DTOG_RX_Msk (0x1UL << USB_EP5R_DTOG_RX_Pos) /*!< 0x00004000 */ +#define USB_EP5R_DTOG_RX USB_EP5R_DTOG_RX_Msk /*!< Data Toggle, for reception transfers */ +#define USB_EP5R_CTR_RX_Pos (15U) +#define USB_EP5R_CTR_RX_Msk (0x1UL << USB_EP5R_CTR_RX_Pos) /*!< 0x00008000 */ +#define USB_EP5R_CTR_RX USB_EP5R_CTR_RX_Msk /*!< Correct Transfer for reception */ + +/******************* Bit definition for USB_EP6R register *******************/ +#define USB_EP6R_EA_Pos (0U) +#define USB_EP6R_EA_Msk (0xFUL << USB_EP6R_EA_Pos) /*!< 0x0000000F */ +#define USB_EP6R_EA USB_EP6R_EA_Msk /*!< Endpoint Address */ + +#define USB_EP6R_STAT_TX_Pos (4U) +#define USB_EP6R_STAT_TX_Msk (0x3UL << USB_EP6R_STAT_TX_Pos) /*!< 0x00000030 */ +#define USB_EP6R_STAT_TX USB_EP6R_STAT_TX_Msk /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */ +#define USB_EP6R_STAT_TX_0 (0x1UL << USB_EP6R_STAT_TX_Pos) /*!< 0x00000010 */ +#define USB_EP6R_STAT_TX_1 (0x2UL << USB_EP6R_STAT_TX_Pos) /*!< 0x00000020 */ + +#define USB_EP6R_DTOG_TX_Pos (6U) +#define USB_EP6R_DTOG_TX_Msk (0x1UL << USB_EP6R_DTOG_TX_Pos) /*!< 0x00000040 */ +#define USB_EP6R_DTOG_TX USB_EP6R_DTOG_TX_Msk /*!< Data Toggle, for transmission transfers */ +#define USB_EP6R_CTR_TX_Pos (7U) +#define USB_EP6R_CTR_TX_Msk (0x1UL << USB_EP6R_CTR_TX_Pos) /*!< 0x00000080 */ +#define USB_EP6R_CTR_TX USB_EP6R_CTR_TX_Msk /*!< Correct Transfer for transmission */ +#define USB_EP6R_EP_KIND_Pos (8U) +#define USB_EP6R_EP_KIND_Msk (0x1UL << USB_EP6R_EP_KIND_Pos) /*!< 0x00000100 */ +#define USB_EP6R_EP_KIND USB_EP6R_EP_KIND_Msk /*!< Endpoint Kind */ + +#define USB_EP6R_EP_TYPE_Pos (9U) +#define USB_EP6R_EP_TYPE_Msk (0x3UL << USB_EP6R_EP_TYPE_Pos) /*!< 0x00000600 */ +#define USB_EP6R_EP_TYPE USB_EP6R_EP_TYPE_Msk /*!< EP_TYPE[1:0] bits (Endpoint type) */ +#define USB_EP6R_EP_TYPE_0 (0x1UL << USB_EP6R_EP_TYPE_Pos) /*!< 0x00000200 */ +#define USB_EP6R_EP_TYPE_1 (0x2UL << USB_EP6R_EP_TYPE_Pos) /*!< 0x00000400 */ + +#define USB_EP6R_SETUP_Pos (11U) +#define USB_EP6R_SETUP_Msk (0x1UL << USB_EP6R_SETUP_Pos) /*!< 0x00000800 */ +#define USB_EP6R_SETUP USB_EP6R_SETUP_Msk /*!< Setup transaction completed */ + +#define USB_EP6R_STAT_RX_Pos (12U) +#define USB_EP6R_STAT_RX_Msk (0x3UL << USB_EP6R_STAT_RX_Pos) /*!< 0x00003000 */ +#define USB_EP6R_STAT_RX USB_EP6R_STAT_RX_Msk /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */ +#define USB_EP6R_STAT_RX_0 (0x1UL << USB_EP6R_STAT_RX_Pos) /*!< 0x00001000 */ +#define USB_EP6R_STAT_RX_1 (0x2UL << USB_EP6R_STAT_RX_Pos) /*!< 0x00002000 */ + +#define USB_EP6R_DTOG_RX_Pos (14U) +#define USB_EP6R_DTOG_RX_Msk (0x1UL << USB_EP6R_DTOG_RX_Pos) /*!< 0x00004000 */ +#define USB_EP6R_DTOG_RX USB_EP6R_DTOG_RX_Msk /*!< Data Toggle, for reception transfers */ +#define USB_EP6R_CTR_RX_Pos (15U) +#define USB_EP6R_CTR_RX_Msk (0x1UL << USB_EP6R_CTR_RX_Pos) /*!< 0x00008000 */ +#define USB_EP6R_CTR_RX USB_EP6R_CTR_RX_Msk /*!< Correct Transfer for reception */ + +/******************* Bit definition for USB_EP7R register *******************/ +#define USB_EP7R_EA_Pos (0U) +#define USB_EP7R_EA_Msk (0xFUL << USB_EP7R_EA_Pos) /*!< 0x0000000F */ +#define USB_EP7R_EA USB_EP7R_EA_Msk /*!< Endpoint Address */ + +#define USB_EP7R_STAT_TX_Pos (4U) +#define USB_EP7R_STAT_TX_Msk (0x3UL << USB_EP7R_STAT_TX_Pos) /*!< 0x00000030 */ +#define USB_EP7R_STAT_TX USB_EP7R_STAT_TX_Msk /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */ +#define USB_EP7R_STAT_TX_0 (0x1UL << USB_EP7R_STAT_TX_Pos) /*!< 0x00000010 */ +#define USB_EP7R_STAT_TX_1 (0x2UL << USB_EP7R_STAT_TX_Pos) /*!< 0x00000020 */ + +#define USB_EP7R_DTOG_TX_Pos (6U) +#define USB_EP7R_DTOG_TX_Msk (0x1UL << USB_EP7R_DTOG_TX_Pos) /*!< 0x00000040 */ +#define USB_EP7R_DTOG_TX USB_EP7R_DTOG_TX_Msk /*!< Data Toggle, for transmission transfers */ +#define USB_EP7R_CTR_TX_Pos (7U) +#define USB_EP7R_CTR_TX_Msk (0x1UL << USB_EP7R_CTR_TX_Pos) /*!< 0x00000080 */ +#define USB_EP7R_CTR_TX USB_EP7R_CTR_TX_Msk /*!< Correct Transfer for transmission */ +#define USB_EP7R_EP_KIND_Pos (8U) +#define USB_EP7R_EP_KIND_Msk (0x1UL << USB_EP7R_EP_KIND_Pos) /*!< 0x00000100 */ +#define USB_EP7R_EP_KIND USB_EP7R_EP_KIND_Msk /*!< Endpoint Kind */ + +#define USB_EP7R_EP_TYPE_Pos (9U) +#define USB_EP7R_EP_TYPE_Msk (0x3UL << USB_EP7R_EP_TYPE_Pos) /*!< 0x00000600 */ +#define USB_EP7R_EP_TYPE USB_EP7R_EP_TYPE_Msk /*!< EP_TYPE[1:0] bits (Endpoint type) */ +#define USB_EP7R_EP_TYPE_0 (0x1UL << USB_EP7R_EP_TYPE_Pos) /*!< 0x00000200 */ +#define USB_EP7R_EP_TYPE_1 (0x2UL << USB_EP7R_EP_TYPE_Pos) /*!< 0x00000400 */ + +#define USB_EP7R_SETUP_Pos (11U) +#define USB_EP7R_SETUP_Msk (0x1UL << USB_EP7R_SETUP_Pos) /*!< 0x00000800 */ +#define USB_EP7R_SETUP USB_EP7R_SETUP_Msk /*!< Setup transaction completed */ + +#define USB_EP7R_STAT_RX_Pos (12U) +#define USB_EP7R_STAT_RX_Msk (0x3UL << USB_EP7R_STAT_RX_Pos) /*!< 0x00003000 */ +#define USB_EP7R_STAT_RX USB_EP7R_STAT_RX_Msk /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */ +#define USB_EP7R_STAT_RX_0 (0x1UL << USB_EP7R_STAT_RX_Pos) /*!< 0x00001000 */ +#define USB_EP7R_STAT_RX_1 (0x2UL << USB_EP7R_STAT_RX_Pos) /*!< 0x00002000 */ + +#define USB_EP7R_DTOG_RX_Pos (14U) +#define USB_EP7R_DTOG_RX_Msk (0x1UL << USB_EP7R_DTOG_RX_Pos) /*!< 0x00004000 */ +#define USB_EP7R_DTOG_RX USB_EP7R_DTOG_RX_Msk /*!< Data Toggle, for reception transfers */ +#define USB_EP7R_CTR_RX_Pos (15U) +#define USB_EP7R_CTR_RX_Msk (0x1UL << USB_EP7R_CTR_RX_Pos) /*!< 0x00008000 */ +#define USB_EP7R_CTR_RX USB_EP7R_CTR_RX_Msk /*!< Correct Transfer for reception */ + +/*!< Common registers */ +/******************* Bit definition for USB_CNTR register *******************/ +#define USB_CNTR_FRES_Pos (0U) +#define USB_CNTR_FRES_Msk (0x1UL << USB_CNTR_FRES_Pos) /*!< 0x00000001 */ +#define USB_CNTR_FRES USB_CNTR_FRES_Msk /*!< Force USB Reset */ +#define USB_CNTR_PDWN_Pos (1U) +#define USB_CNTR_PDWN_Msk (0x1UL << USB_CNTR_PDWN_Pos) /*!< 0x00000002 */ +#define USB_CNTR_PDWN USB_CNTR_PDWN_Msk /*!< Power down */ +#define USB_CNTR_LP_MODE_Pos (2U) +#define USB_CNTR_LP_MODE_Msk (0x1UL << USB_CNTR_LP_MODE_Pos) /*!< 0x00000004 */ +#define USB_CNTR_LP_MODE USB_CNTR_LP_MODE_Msk /*!< Low-power mode */ +#define USB_CNTR_FSUSP_Pos (3U) +#define USB_CNTR_FSUSP_Msk (0x1UL << USB_CNTR_FSUSP_Pos) /*!< 0x00000008 */ +#define USB_CNTR_FSUSP USB_CNTR_FSUSP_Msk /*!< Force suspend */ +#define USB_CNTR_RESUME_Pos (4U) +#define USB_CNTR_RESUME_Msk (0x1UL << USB_CNTR_RESUME_Pos) /*!< 0x00000010 */ +#define USB_CNTR_RESUME USB_CNTR_RESUME_Msk /*!< Resume request */ +#define USB_CNTR_ESOFM_Pos (8U) +#define USB_CNTR_ESOFM_Msk (0x1UL << USB_CNTR_ESOFM_Pos) /*!< 0x00000100 */ +#define USB_CNTR_ESOFM USB_CNTR_ESOFM_Msk /*!< Expected Start Of Frame Interrupt Mask */ +#define USB_CNTR_SOFM_Pos (9U) +#define USB_CNTR_SOFM_Msk (0x1UL << USB_CNTR_SOFM_Pos) /*!< 0x00000200 */ +#define USB_CNTR_SOFM USB_CNTR_SOFM_Msk /*!< Start Of Frame Interrupt Mask */ +#define USB_CNTR_RESETM_Pos (10U) +#define USB_CNTR_RESETM_Msk (0x1UL << USB_CNTR_RESETM_Pos) /*!< 0x00000400 */ +#define USB_CNTR_RESETM USB_CNTR_RESETM_Msk /*!< RESET Interrupt Mask */ +#define USB_CNTR_SUSPM_Pos (11U) +#define USB_CNTR_SUSPM_Msk (0x1UL << USB_CNTR_SUSPM_Pos) /*!< 0x00000800 */ +#define USB_CNTR_SUSPM USB_CNTR_SUSPM_Msk /*!< Suspend mode Interrupt Mask */ +#define USB_CNTR_WKUPM_Pos (12U) +#define USB_CNTR_WKUPM_Msk (0x1UL << USB_CNTR_WKUPM_Pos) /*!< 0x00001000 */ +#define USB_CNTR_WKUPM USB_CNTR_WKUPM_Msk /*!< Wakeup Interrupt Mask */ +#define USB_CNTR_ERRM_Pos (13U) +#define USB_CNTR_ERRM_Msk (0x1UL << USB_CNTR_ERRM_Pos) /*!< 0x00002000 */ +#define USB_CNTR_ERRM USB_CNTR_ERRM_Msk /*!< Error Interrupt Mask */ +#define USB_CNTR_PMAOVRM_Pos (14U) +#define USB_CNTR_PMAOVRM_Msk (0x1UL << USB_CNTR_PMAOVRM_Pos) /*!< 0x00004000 */ +#define USB_CNTR_PMAOVRM USB_CNTR_PMAOVRM_Msk /*!< Packet Memory Area Over / Underrun Interrupt Mask */ +#define USB_CNTR_CTRM_Pos (15U) +#define USB_CNTR_CTRM_Msk (0x1UL << USB_CNTR_CTRM_Pos) /*!< 0x00008000 */ +#define USB_CNTR_CTRM USB_CNTR_CTRM_Msk /*!< Correct Transfer Interrupt Mask */ + +/******************* Bit definition for USB_ISTR register *******************/ +#define USB_ISTR_EP_ID_Pos (0U) +#define USB_ISTR_EP_ID_Msk (0xFUL << USB_ISTR_EP_ID_Pos) /*!< 0x0000000F */ +#define USB_ISTR_EP_ID USB_ISTR_EP_ID_Msk /*!< Endpoint Identifier */ +#define USB_ISTR_DIR_Pos (4U) +#define USB_ISTR_DIR_Msk (0x1UL << USB_ISTR_DIR_Pos) /*!< 0x00000010 */ +#define USB_ISTR_DIR USB_ISTR_DIR_Msk /*!< Direction of transaction */ +#define USB_ISTR_ESOF_Pos (8U) +#define USB_ISTR_ESOF_Msk (0x1UL << USB_ISTR_ESOF_Pos) /*!< 0x00000100 */ +#define USB_ISTR_ESOF USB_ISTR_ESOF_Msk /*!< Expected Start Of Frame */ +#define USB_ISTR_SOF_Pos (9U) +#define USB_ISTR_SOF_Msk (0x1UL << USB_ISTR_SOF_Pos) /*!< 0x00000200 */ +#define USB_ISTR_SOF USB_ISTR_SOF_Msk /*!< Start Of Frame */ +#define USB_ISTR_RESET_Pos (10U) +#define USB_ISTR_RESET_Msk (0x1UL << USB_ISTR_RESET_Pos) /*!< 0x00000400 */ +#define USB_ISTR_RESET USB_ISTR_RESET_Msk /*!< USB RESET request */ +#define USB_ISTR_SUSP_Pos (11U) +#define USB_ISTR_SUSP_Msk (0x1UL << USB_ISTR_SUSP_Pos) /*!< 0x00000800 */ +#define USB_ISTR_SUSP USB_ISTR_SUSP_Msk /*!< Suspend mode request */ +#define USB_ISTR_WKUP_Pos (12U) +#define USB_ISTR_WKUP_Msk (0x1UL << USB_ISTR_WKUP_Pos) /*!< 0x00001000 */ +#define USB_ISTR_WKUP USB_ISTR_WKUP_Msk /*!< Wake up */ +#define USB_ISTR_ERR_Pos (13U) +#define USB_ISTR_ERR_Msk (0x1UL << USB_ISTR_ERR_Pos) /*!< 0x00002000 */ +#define USB_ISTR_ERR USB_ISTR_ERR_Msk /*!< Error */ +#define USB_ISTR_PMAOVR_Pos (14U) +#define USB_ISTR_PMAOVR_Msk (0x1UL << USB_ISTR_PMAOVR_Pos) /*!< 0x00004000 */ +#define USB_ISTR_PMAOVR USB_ISTR_PMAOVR_Msk /*!< Packet Memory Area Over / Underrun */ +#define USB_ISTR_CTR_Pos (15U) +#define USB_ISTR_CTR_Msk (0x1UL << USB_ISTR_CTR_Pos) /*!< 0x00008000 */ +#define USB_ISTR_CTR USB_ISTR_CTR_Msk /*!< Correct Transfer */ + +/******************* Bit definition for USB_FNR register ********************/ +#define USB_FNR_FN_Pos (0U) +#define USB_FNR_FN_Msk (0x7FFUL << USB_FNR_FN_Pos) /*!< 0x000007FF */ +#define USB_FNR_FN USB_FNR_FN_Msk /*!< Frame Number */ +#define USB_FNR_LSOF_Pos (11U) +#define USB_FNR_LSOF_Msk (0x3UL << USB_FNR_LSOF_Pos) /*!< 0x00001800 */ +#define USB_FNR_LSOF USB_FNR_LSOF_Msk /*!< Lost SOF */ +#define USB_FNR_LCK_Pos (13U) +#define USB_FNR_LCK_Msk (0x1UL << USB_FNR_LCK_Pos) /*!< 0x00002000 */ +#define USB_FNR_LCK USB_FNR_LCK_Msk /*!< Locked */ +#define USB_FNR_RXDM_Pos (14U) +#define USB_FNR_RXDM_Msk (0x1UL << USB_FNR_RXDM_Pos) /*!< 0x00004000 */ +#define USB_FNR_RXDM USB_FNR_RXDM_Msk /*!< Receive Data - Line Status */ +#define USB_FNR_RXDP_Pos (15U) +#define USB_FNR_RXDP_Msk (0x1UL << USB_FNR_RXDP_Pos) /*!< 0x00008000 */ +#define USB_FNR_RXDP USB_FNR_RXDP_Msk /*!< Receive Data + Line Status */ + +/****************** Bit definition for USB_DADDR register *******************/ +#define USB_DADDR_ADD_Pos (0U) +#define USB_DADDR_ADD_Msk (0x7FUL << USB_DADDR_ADD_Pos) /*!< 0x0000007F */ +#define USB_DADDR_ADD USB_DADDR_ADD_Msk /*!< ADD[6:0] bits (Device Address) */ +#define USB_DADDR_ADD0_Pos (0U) +#define USB_DADDR_ADD0_Msk (0x1UL << USB_DADDR_ADD0_Pos) /*!< 0x00000001 */ +#define USB_DADDR_ADD0 USB_DADDR_ADD0_Msk /*!< Bit 0 */ +#define USB_DADDR_ADD1_Pos (1U) +#define USB_DADDR_ADD1_Msk (0x1UL << USB_DADDR_ADD1_Pos) /*!< 0x00000002 */ +#define USB_DADDR_ADD1 USB_DADDR_ADD1_Msk /*!< Bit 1 */ +#define USB_DADDR_ADD2_Pos (2U) +#define USB_DADDR_ADD2_Msk (0x1UL << USB_DADDR_ADD2_Pos) /*!< 0x00000004 */ +#define USB_DADDR_ADD2 USB_DADDR_ADD2_Msk /*!< Bit 2 */ +#define USB_DADDR_ADD3_Pos (3U) +#define USB_DADDR_ADD3_Msk (0x1UL << USB_DADDR_ADD3_Pos) /*!< 0x00000008 */ +#define USB_DADDR_ADD3 USB_DADDR_ADD3_Msk /*!< Bit 3 */ +#define USB_DADDR_ADD4_Pos (4U) +#define USB_DADDR_ADD4_Msk (0x1UL << USB_DADDR_ADD4_Pos) /*!< 0x00000010 */ +#define USB_DADDR_ADD4 USB_DADDR_ADD4_Msk /*!< Bit 4 */ +#define USB_DADDR_ADD5_Pos (5U) +#define USB_DADDR_ADD5_Msk (0x1UL << USB_DADDR_ADD5_Pos) /*!< 0x00000020 */ +#define USB_DADDR_ADD5 USB_DADDR_ADD5_Msk /*!< Bit 5 */ +#define USB_DADDR_ADD6_Pos (6U) +#define USB_DADDR_ADD6_Msk (0x1UL << USB_DADDR_ADD6_Pos) /*!< 0x00000040 */ +#define USB_DADDR_ADD6 USB_DADDR_ADD6_Msk /*!< Bit 6 */ + +#define USB_DADDR_EF_Pos (7U) +#define USB_DADDR_EF_Msk (0x1UL << USB_DADDR_EF_Pos) /*!< 0x00000080 */ +#define USB_DADDR_EF USB_DADDR_EF_Msk /*!< Enable Function */ + +/****************** Bit definition for USB_BTABLE register ******************/ +#define USB_BTABLE_BTABLE_Pos (3U) +#define USB_BTABLE_BTABLE_Msk (0x1FFFUL << USB_BTABLE_BTABLE_Pos) /*!< 0x0000FFF8 */ +#define USB_BTABLE_BTABLE USB_BTABLE_BTABLE_Msk /*!< Buffer Table */ + +/****************** Bits definition for USB_BCDR register *******************/ +#define USB_BCDR_BCDEN ((uint16_t)0x0001U) /*!< Battery charging detector (BCD) enable */ +#define USB_BCDR_DCDEN ((uint16_t)0x0002U) /*!< Data contact detection (DCD) mode enable */ +#define USB_BCDR_PDEN ((uint16_t)0x0004U) /*!< Primary detection (PD) mode enable */ +#define USB_BCDR_SDEN ((uint16_t)0x0008U) /*!< Secondary detection (SD) mode enable */ +#define USB_BCDR_DCDET ((uint16_t)0x0010U) /*!< Data contact detection (DCD) status */ +#define USB_BCDR_PDET ((uint16_t)0x0020U) /*!< Primary detection (PD) status */ +#define USB_BCDR_SDET ((uint16_t)0x0040U) /*!< Secondary detection (SD) status */ +#define USB_BCDR_PS2DET ((uint16_t)0x0080U) /*!< PS2 port or proprietary charger detected */ +#define USB_BCDR_DPPU ((uint16_t)0x8000U) /*!< DP Pull-up Enable */ + +/******************* Bit definition for LPMCSR register *********************/ +#define USB_LPMCSR_LMPEN ((uint16_t)0x0001U) /*!< LPM support enable */ +#define USB_LPMCSR_LPMACK ((uint16_t)0x0002U) /*!< LPM Token acknowledge enable*/ +#define USB_LPMCSR_REMWAKE ((uint16_t)0x0008U) /*!< bRemoteWake value received with last ACKed LPM Token */ +#define USB_LPMCSR_BESL ((uint16_t)0x00F0U) /*!< BESL value received with last ACKed LPM Token */ + +/*!< Buffer descriptor table */ +/***************** Bit definition for USB_ADDR0_TX register *****************/ +#define USB_ADDR0_TX_ADDR0_TX_Pos (1U) +#define USB_ADDR0_TX_ADDR0_TX_Msk (0x7FFFUL << USB_ADDR0_TX_ADDR0_TX_Pos) /*!< 0x0000FFFE */ +#define USB_ADDR0_TX_ADDR0_TX USB_ADDR0_TX_ADDR0_TX_Msk /*!< Transmission Buffer Address 0 */ + +/***************** Bit definition for USB_ADDR1_TX register *****************/ +#define USB_ADDR1_TX_ADDR1_TX_Pos (1U) +#define USB_ADDR1_TX_ADDR1_TX_Msk (0x7FFFUL << USB_ADDR1_TX_ADDR1_TX_Pos) /*!< 0x0000FFFE */ +#define USB_ADDR1_TX_ADDR1_TX USB_ADDR1_TX_ADDR1_TX_Msk /*!< Transmission Buffer Address 1 */ + +/***************** Bit definition for USB_ADDR2_TX register *****************/ +#define USB_ADDR2_TX_ADDR2_TX_Pos (1U) +#define USB_ADDR2_TX_ADDR2_TX_Msk (0x7FFFUL << USB_ADDR2_TX_ADDR2_TX_Pos) /*!< 0x0000FFFE */ +#define USB_ADDR2_TX_ADDR2_TX USB_ADDR2_TX_ADDR2_TX_Msk /*!< Transmission Buffer Address 2 */ + +/***************** Bit definition for USB_ADDR3_TX register *****************/ +#define USB_ADDR3_TX_ADDR3_TX_Pos (1U) +#define USB_ADDR3_TX_ADDR3_TX_Msk (0x7FFFUL << USB_ADDR3_TX_ADDR3_TX_Pos) /*!< 0x0000FFFE */ +#define USB_ADDR3_TX_ADDR3_TX USB_ADDR3_TX_ADDR3_TX_Msk /*!< Transmission Buffer Address 3 */ + +/***************** Bit definition for USB_ADDR4_TX register *****************/ +#define USB_ADDR4_TX_ADDR4_TX_Pos (1U) +#define USB_ADDR4_TX_ADDR4_TX_Msk (0x7FFFUL << USB_ADDR4_TX_ADDR4_TX_Pos) /*!< 0x0000FFFE */ +#define USB_ADDR4_TX_ADDR4_TX USB_ADDR4_TX_ADDR4_TX_Msk /*!< Transmission Buffer Address 4 */ + +/***************** Bit definition for USB_ADDR5_TX register *****************/ +#define USB_ADDR5_TX_ADDR5_TX_Pos (1U) +#define USB_ADDR5_TX_ADDR5_TX_Msk (0x7FFFUL << USB_ADDR5_TX_ADDR5_TX_Pos) /*!< 0x0000FFFE */ +#define USB_ADDR5_TX_ADDR5_TX USB_ADDR5_TX_ADDR5_TX_Msk /*!< Transmission Buffer Address 5 */ + +/***************** Bit definition for USB_ADDR6_TX register *****************/ +#define USB_ADDR6_TX_ADDR6_TX_Pos (1U) +#define USB_ADDR6_TX_ADDR6_TX_Msk (0x7FFFUL << USB_ADDR6_TX_ADDR6_TX_Pos) /*!< 0x0000FFFE */ +#define USB_ADDR6_TX_ADDR6_TX USB_ADDR6_TX_ADDR6_TX_Msk /*!< Transmission Buffer Address 6 */ + +/***************** Bit definition for USB_ADDR7_TX register *****************/ +#define USB_ADDR7_TX_ADDR7_TX_Pos (1U) +#define USB_ADDR7_TX_ADDR7_TX_Msk (0x7FFFUL << USB_ADDR7_TX_ADDR7_TX_Pos) /*!< 0x0000FFFE */ +#define USB_ADDR7_TX_ADDR7_TX USB_ADDR7_TX_ADDR7_TX_Msk /*!< Transmission Buffer Address 7 */ + +/*----------------------------------------------------------------------------*/ + +/***************** Bit definition for USB_COUNT0_TX register ****************/ +#define USB_COUNT0_TX_COUNT0_TX_Pos (0U) +#define USB_COUNT0_TX_COUNT0_TX_Msk (0x3FFUL << USB_COUNT0_TX_COUNT0_TX_Pos) /*!< 0x000003FF */ +#define USB_COUNT0_TX_COUNT0_TX USB_COUNT0_TX_COUNT0_TX_Msk /*!< Transmission Byte Count 0 */ + +/***************** Bit definition for USB_COUNT1_TX register ****************/ +#define USB_COUNT1_TX_COUNT1_TX_Pos (0U) +#define USB_COUNT1_TX_COUNT1_TX_Msk (0x3FFUL << USB_COUNT1_TX_COUNT1_TX_Pos) /*!< 0x000003FF */ +#define USB_COUNT1_TX_COUNT1_TX USB_COUNT1_TX_COUNT1_TX_Msk /*!< Transmission Byte Count 1 */ + +/***************** Bit definition for USB_COUNT2_TX register ****************/ +#define USB_COUNT2_TX_COUNT2_TX_Pos (0U) +#define USB_COUNT2_TX_COUNT2_TX_Msk (0x3FFUL << USB_COUNT2_TX_COUNT2_TX_Pos) /*!< 0x000003FF */ +#define USB_COUNT2_TX_COUNT2_TX USB_COUNT2_TX_COUNT2_TX_Msk /*!< Transmission Byte Count 2 */ + +/***************** Bit definition for USB_COUNT3_TX register ****************/ +#define USB_COUNT3_TX_COUNT3_TX_Pos (0U) +#define USB_COUNT3_TX_COUNT3_TX_Msk (0x3FFUL << USB_COUNT3_TX_COUNT3_TX_Pos) /*!< 0x000003FF */ +#define USB_COUNT3_TX_COUNT3_TX USB_COUNT3_TX_COUNT3_TX_Msk /*!< Transmission Byte Count 3 */ + +/***************** Bit definition for USB_COUNT4_TX register ****************/ +#define USB_COUNT4_TX_COUNT4_TX_Pos (0U) +#define USB_COUNT4_TX_COUNT4_TX_Msk (0x3FFUL << USB_COUNT4_TX_COUNT4_TX_Pos) /*!< 0x000003FF */ +#define USB_COUNT4_TX_COUNT4_TX USB_COUNT4_TX_COUNT4_TX_Msk /*!< Transmission Byte Count 4 */ + +/***************** Bit definition for USB_COUNT5_TX register ****************/ +#define USB_COUNT5_TX_COUNT5_TX_Pos (0U) +#define USB_COUNT5_TX_COUNT5_TX_Msk (0x3FFUL << USB_COUNT5_TX_COUNT5_TX_Pos) /*!< 0x000003FF */ +#define USB_COUNT5_TX_COUNT5_TX USB_COUNT5_TX_COUNT5_TX_Msk /*!< Transmission Byte Count 5 */ + +/***************** Bit definition for USB_COUNT6_TX register ****************/ +#define USB_COUNT6_TX_COUNT6_TX_Pos (0U) +#define USB_COUNT6_TX_COUNT6_TX_Msk (0x3FFUL << USB_COUNT6_TX_COUNT6_TX_Pos) /*!< 0x000003FF */ +#define USB_COUNT6_TX_COUNT6_TX USB_COUNT6_TX_COUNT6_TX_Msk /*!< Transmission Byte Count 6 */ + +/***************** Bit definition for USB_COUNT7_TX register ****************/ +#define USB_COUNT7_TX_COUNT7_TX_Pos (0U) +#define USB_COUNT7_TX_COUNT7_TX_Msk (0x3FFUL << USB_COUNT7_TX_COUNT7_TX_Pos) /*!< 0x000003FF */ +#define USB_COUNT7_TX_COUNT7_TX USB_COUNT7_TX_COUNT7_TX_Msk /*!< Transmission Byte Count 7 */ + +/*----------------------------------------------------------------------------*/ + +/**************** Bit definition for USB_COUNT0_TX_0 register ***************/ +#define USB_COUNT0_TX_0_COUNT0_TX_0 0x000003FFU /*!< Transmission Byte Count 0 (low) */ + +/**************** Bit definition for USB_COUNT0_TX_1 register ***************/ +#define USB_COUNT0_TX_1_COUNT0_TX_1 0x03FF0000U /*!< Transmission Byte Count 0 (high) */ + +/**************** Bit definition for USB_COUNT1_TX_0 register ***************/ +#define USB_COUNT1_TX_0_COUNT1_TX_0 0x000003FFU /*!< Transmission Byte Count 1 (low) */ + +/**************** Bit definition for USB_COUNT1_TX_1 register ***************/ +#define USB_COUNT1_TX_1_COUNT1_TX_1 0x03FF0000U /*!< Transmission Byte Count 1 (high) */ + +/**************** Bit definition for USB_COUNT2_TX_0 register ***************/ +#define USB_COUNT2_TX_0_COUNT2_TX_0 0x000003FFU /*!< Transmission Byte Count 2 (low) */ + +/**************** Bit definition for USB_COUNT2_TX_1 register ***************/ +#define USB_COUNT2_TX_1_COUNT2_TX_1 0x03FF0000U /*!< Transmission Byte Count 2 (high) */ + +/**************** Bit definition for USB_COUNT3_TX_0 register ***************/ +#define USB_COUNT3_TX_0_COUNT3_TX_0 0x000003FFU /*!< Transmission Byte Count 3 (low) */ + +/**************** Bit definition for USB_COUNT3_TX_1 register ***************/ +#define USB_COUNT3_TX_1_COUNT3_TX_1 0x03FF0000U /*!< Transmission Byte Count 3 (high) */ + +/**************** Bit definition for USB_COUNT4_TX_0 register ***************/ +#define USB_COUNT4_TX_0_COUNT4_TX_0 0x000003FFU /*!< Transmission Byte Count 4 (low) */ + +/**************** Bit definition for USB_COUNT4_TX_1 register ***************/ +#define USB_COUNT4_TX_1_COUNT4_TX_1 0x03FF0000U /*!< Transmission Byte Count 4 (high) */ + +/**************** Bit definition for USB_COUNT5_TX_0 register ***************/ +#define USB_COUNT5_TX_0_COUNT5_TX_0 0x000003FFU /*!< Transmission Byte Count 5 (low) */ + +/**************** Bit definition for USB_COUNT5_TX_1 register ***************/ +#define USB_COUNT5_TX_1_COUNT5_TX_1 0x03FF0000U /*!< Transmission Byte Count 5 (high) */ + +/**************** Bit definition for USB_COUNT6_TX_0 register ***************/ +#define USB_COUNT6_TX_0_COUNT6_TX_0 0x000003FFU /*!< Transmission Byte Count 6 (low) */ + +/**************** Bit definition for USB_COUNT6_TX_1 register ***************/ +#define USB_COUNT6_TX_1_COUNT6_TX_1 0x03FF0000U /*!< Transmission Byte Count 6 (high) */ + +/**************** Bit definition for USB_COUNT7_TX_0 register ***************/ +#define USB_COUNT7_TX_0_COUNT7_TX_0 0x000003FFU /*!< Transmission Byte Count 7 (low) */ + +/**************** Bit definition for USB_COUNT7_TX_1 register ***************/ +#define USB_COUNT7_TX_1_COUNT7_TX_1 0x03FF0000U /*!< Transmission Byte Count 7 (high) */ + +/*----------------------------------------------------------------------------*/ + +/***************** Bit definition for USB_ADDR0_RX register *****************/ +#define USB_ADDR0_RX_ADDR0_RX_Pos (1U) +#define USB_ADDR0_RX_ADDR0_RX_Msk (0x7FFFUL << USB_ADDR0_RX_ADDR0_RX_Pos) /*!< 0x0000FFFE */ +#define USB_ADDR0_RX_ADDR0_RX USB_ADDR0_RX_ADDR0_RX_Msk /*!< Reception Buffer Address 0 */ + +/***************** Bit definition for USB_ADDR1_RX register *****************/ +#define USB_ADDR1_RX_ADDR1_RX_Pos (1U) +#define USB_ADDR1_RX_ADDR1_RX_Msk (0x7FFFUL << USB_ADDR1_RX_ADDR1_RX_Pos) /*!< 0x0000FFFE */ +#define USB_ADDR1_RX_ADDR1_RX USB_ADDR1_RX_ADDR1_RX_Msk /*!< Reception Buffer Address 1 */ + +/***************** Bit definition for USB_ADDR2_RX register *****************/ +#define USB_ADDR2_RX_ADDR2_RX_Pos (1U) +#define USB_ADDR2_RX_ADDR2_RX_Msk (0x7FFFUL << USB_ADDR2_RX_ADDR2_RX_Pos) /*!< 0x0000FFFE */ +#define USB_ADDR2_RX_ADDR2_RX USB_ADDR2_RX_ADDR2_RX_Msk /*!< Reception Buffer Address 2 */ + +/***************** Bit definition for USB_ADDR3_RX register *****************/ +#define USB_ADDR3_RX_ADDR3_RX_Pos (1U) +#define USB_ADDR3_RX_ADDR3_RX_Msk (0x7FFFUL << USB_ADDR3_RX_ADDR3_RX_Pos) /*!< 0x0000FFFE */ +#define USB_ADDR3_RX_ADDR3_RX USB_ADDR3_RX_ADDR3_RX_Msk /*!< Reception Buffer Address 3 */ + +/***************** Bit definition for USB_ADDR4_RX register *****************/ +#define USB_ADDR4_RX_ADDR4_RX_Pos (1U) +#define USB_ADDR4_RX_ADDR4_RX_Msk (0x7FFFUL << USB_ADDR4_RX_ADDR4_RX_Pos) /*!< 0x0000FFFE */ +#define USB_ADDR4_RX_ADDR4_RX USB_ADDR4_RX_ADDR4_RX_Msk /*!< Reception Buffer Address 4 */ + +/***************** Bit definition for USB_ADDR5_RX register *****************/ +#define USB_ADDR5_RX_ADDR5_RX_Pos (1U) +#define USB_ADDR5_RX_ADDR5_RX_Msk (0x7FFFUL << USB_ADDR5_RX_ADDR5_RX_Pos) /*!< 0x0000FFFE */ +#define USB_ADDR5_RX_ADDR5_RX USB_ADDR5_RX_ADDR5_RX_Msk /*!< Reception Buffer Address 5 */ + +/***************** Bit definition for USB_ADDR6_RX register *****************/ +#define USB_ADDR6_RX_ADDR6_RX_Pos (1U) +#define USB_ADDR6_RX_ADDR6_RX_Msk (0x7FFFUL << USB_ADDR6_RX_ADDR6_RX_Pos) /*!< 0x0000FFFE */ +#define USB_ADDR6_RX_ADDR6_RX USB_ADDR6_RX_ADDR6_RX_Msk /*!< Reception Buffer Address 6 */ + +/***************** Bit definition for USB_ADDR7_RX register *****************/ +#define USB_ADDR7_RX_ADDR7_RX_Pos (1U) +#define USB_ADDR7_RX_ADDR7_RX_Msk (0x7FFFUL << USB_ADDR7_RX_ADDR7_RX_Pos) /*!< 0x0000FFFE */ +#define USB_ADDR7_RX_ADDR7_RX USB_ADDR7_RX_ADDR7_RX_Msk /*!< Reception Buffer Address 7 */ + +/*----------------------------------------------------------------------------*/ + +/***************** Bit definition for USB_COUNT0_RX register ****************/ +#define USB_COUNT0_RX_COUNT0_RX_Pos (0U) +#define USB_COUNT0_RX_COUNT0_RX_Msk (0x3FFUL << USB_COUNT0_RX_COUNT0_RX_Pos) /*!< 0x000003FF */ +#define USB_COUNT0_RX_COUNT0_RX USB_COUNT0_RX_COUNT0_RX_Msk /*!< Reception Byte Count */ + +#define USB_COUNT0_RX_NUM_BLOCK_Pos (10U) +#define USB_COUNT0_RX_NUM_BLOCK_Msk (0x1FUL << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */ +#define USB_COUNT0_RX_NUM_BLOCK USB_COUNT0_RX_NUM_BLOCK_Msk /*!< NUM_BLOCK[4:0] bits (Number of blocks) */ +#define USB_COUNT0_RX_NUM_BLOCK_0 (0x01UL << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */ +#define USB_COUNT0_RX_NUM_BLOCK_1 (0x02UL << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */ +#define USB_COUNT0_RX_NUM_BLOCK_2 (0x04UL << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */ +#define USB_COUNT0_RX_NUM_BLOCK_3 (0x08UL << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */ +#define USB_COUNT0_RX_NUM_BLOCK_4 (0x10UL << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */ + +#define USB_COUNT0_RX_BLSIZE_Pos (15U) +#define USB_COUNT0_RX_BLSIZE_Msk (0x1UL << USB_COUNT0_RX_BLSIZE_Pos) /*!< 0x00008000 */ +#define USB_COUNT0_RX_BLSIZE USB_COUNT0_RX_BLSIZE_Msk /*!< BLock SIZE */ + +/***************** Bit definition for USB_COUNT1_RX register ****************/ +#define USB_COUNT1_RX_COUNT1_RX_Pos (0U) +#define USB_COUNT1_RX_COUNT1_RX_Msk (0x3FFUL << USB_COUNT1_RX_COUNT1_RX_Pos) /*!< 0x000003FF */ +#define USB_COUNT1_RX_COUNT1_RX USB_COUNT1_RX_COUNT1_RX_Msk /*!< Reception Byte Count */ + +#define USB_COUNT1_RX_NUM_BLOCK_Pos (10U) +#define USB_COUNT1_RX_NUM_BLOCK_Msk (0x1FUL << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */ +#define USB_COUNT1_RX_NUM_BLOCK USB_COUNT1_RX_NUM_BLOCK_Msk /*!< NUM_BLOCK[4:0] bits (Number of blocks) */ +#define USB_COUNT1_RX_NUM_BLOCK_0 (0x01UL << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */ +#define USB_COUNT1_RX_NUM_BLOCK_1 (0x02UL << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */ +#define USB_COUNT1_RX_NUM_BLOCK_2 (0x04UL << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */ +#define USB_COUNT1_RX_NUM_BLOCK_3 (0x08UL << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */ +#define USB_COUNT1_RX_NUM_BLOCK_4 (0x10UL << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */ + +#define USB_COUNT1_RX_BLSIZE_Pos (15U) +#define USB_COUNT1_RX_BLSIZE_Msk (0x1UL << USB_COUNT1_RX_BLSIZE_Pos) /*!< 0x00008000 */ +#define USB_COUNT1_RX_BLSIZE USB_COUNT1_RX_BLSIZE_Msk /*!< BLock SIZE */ + +/***************** Bit definition for USB_COUNT2_RX register ****************/ +#define USB_COUNT2_RX_COUNT2_RX_Pos (0U) +#define USB_COUNT2_RX_COUNT2_RX_Msk (0x3FFUL << USB_COUNT2_RX_COUNT2_RX_Pos) /*!< 0x000003FF */ +#define USB_COUNT2_RX_COUNT2_RX USB_COUNT2_RX_COUNT2_RX_Msk /*!< Reception Byte Count */ + +#define USB_COUNT2_RX_NUM_BLOCK_Pos (10U) +#define USB_COUNT2_RX_NUM_BLOCK_Msk (0x1FUL << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */ +#define USB_COUNT2_RX_NUM_BLOCK USB_COUNT2_RX_NUM_BLOCK_Msk /*!< NUM_BLOCK[4:0] bits (Number of blocks) */ +#define USB_COUNT2_RX_NUM_BLOCK_0 (0x01UL << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */ +#define USB_COUNT2_RX_NUM_BLOCK_1 (0x02UL << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */ +#define USB_COUNT2_RX_NUM_BLOCK_2 (0x04UL << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */ +#define USB_COUNT2_RX_NUM_BLOCK_3 (0x08UL << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */ +#define USB_COUNT2_RX_NUM_BLOCK_4 (0x10UL << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */ + +#define USB_COUNT2_RX_BLSIZE_Pos (15U) +#define USB_COUNT2_RX_BLSIZE_Msk (0x1UL << USB_COUNT2_RX_BLSIZE_Pos) /*!< 0x00008000 */ +#define USB_COUNT2_RX_BLSIZE USB_COUNT2_RX_BLSIZE_Msk /*!< BLock SIZE */ + +/***************** Bit definition for USB_COUNT3_RX register ****************/ +#define USB_COUNT3_RX_COUNT3_RX_Pos (0U) +#define USB_COUNT3_RX_COUNT3_RX_Msk (0x3FFUL << USB_COUNT3_RX_COUNT3_RX_Pos) /*!< 0x000003FF */ +#define USB_COUNT3_RX_COUNT3_RX USB_COUNT3_RX_COUNT3_RX_Msk /*!< Reception Byte Count */ + +#define USB_COUNT3_RX_NUM_BLOCK_Pos (10U) +#define USB_COUNT3_RX_NUM_BLOCK_Msk (0x1FUL << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */ +#define USB_COUNT3_RX_NUM_BLOCK USB_COUNT3_RX_NUM_BLOCK_Msk /*!< NUM_BLOCK[4:0] bits (Number of blocks) */ +#define USB_COUNT3_RX_NUM_BLOCK_0 (0x01UL << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */ +#define USB_COUNT3_RX_NUM_BLOCK_1 (0x02UL << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */ +#define USB_COUNT3_RX_NUM_BLOCK_2 (0x04UL << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */ +#define USB_COUNT3_RX_NUM_BLOCK_3 (0x08UL << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */ +#define USB_COUNT3_RX_NUM_BLOCK_4 (0x10UL << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */ + +#define USB_COUNT3_RX_BLSIZE_Pos (15U) +#define USB_COUNT3_RX_BLSIZE_Msk (0x1UL << USB_COUNT3_RX_BLSIZE_Pos) /*!< 0x00008000 */ +#define USB_COUNT3_RX_BLSIZE USB_COUNT3_RX_BLSIZE_Msk /*!< BLock SIZE */ + +/***************** Bit definition for USB_COUNT4_RX register ****************/ +#define USB_COUNT4_RX_COUNT4_RX_Pos (0U) +#define USB_COUNT4_RX_COUNT4_RX_Msk (0x3FFUL << USB_COUNT4_RX_COUNT4_RX_Pos) /*!< 0x000003FF */ +#define USB_COUNT4_RX_COUNT4_RX USB_COUNT4_RX_COUNT4_RX_Msk /*!< Reception Byte Count */ + +#define USB_COUNT4_RX_NUM_BLOCK_Pos (10U) +#define USB_COUNT4_RX_NUM_BLOCK_Msk (0x1FUL << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */ +#define USB_COUNT4_RX_NUM_BLOCK USB_COUNT4_RX_NUM_BLOCK_Msk /*!< NUM_BLOCK[4:0] bits (Number of blocks) */ +#define USB_COUNT4_RX_NUM_BLOCK_0 (0x01UL << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */ +#define USB_COUNT4_RX_NUM_BLOCK_1 (0x02UL << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */ +#define USB_COUNT4_RX_NUM_BLOCK_2 (0x04UL << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */ +#define USB_COUNT4_RX_NUM_BLOCK_3 (0x08UL << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */ +#define USB_COUNT4_RX_NUM_BLOCK_4 (0x10UL << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */ + +#define USB_COUNT4_RX_BLSIZE_Pos (15U) +#define USB_COUNT4_RX_BLSIZE_Msk (0x1UL << USB_COUNT4_RX_BLSIZE_Pos) /*!< 0x00008000 */ +#define USB_COUNT4_RX_BLSIZE USB_COUNT4_RX_BLSIZE_Msk /*!< BLock SIZE */ + +/***************** Bit definition for USB_COUNT5_RX register ****************/ +#define USB_COUNT5_RX_COUNT5_RX_Pos (0U) +#define USB_COUNT5_RX_COUNT5_RX_Msk (0x3FFUL << USB_COUNT5_RX_COUNT5_RX_Pos) /*!< 0x000003FF */ +#define USB_COUNT5_RX_COUNT5_RX USB_COUNT5_RX_COUNT5_RX_Msk /*!< Reception Byte Count */ + +#define USB_COUNT5_RX_NUM_BLOCK_Pos (10U) +#define USB_COUNT5_RX_NUM_BLOCK_Msk (0x1FUL << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */ +#define USB_COUNT5_RX_NUM_BLOCK USB_COUNT5_RX_NUM_BLOCK_Msk /*!< NUM_BLOCK[4:0] bits (Number of blocks) */ +#define USB_COUNT5_RX_NUM_BLOCK_0 (0x01UL << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */ +#define USB_COUNT5_RX_NUM_BLOCK_1 (0x02UL << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */ +#define USB_COUNT5_RX_NUM_BLOCK_2 (0x04UL << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */ +#define USB_COUNT5_RX_NUM_BLOCK_3 (0x08UL << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */ +#define USB_COUNT5_RX_NUM_BLOCK_4 (0x10UL << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */ + +#define USB_COUNT5_RX_BLSIZE_Pos (15U) +#define USB_COUNT5_RX_BLSIZE_Msk (0x1UL << USB_COUNT5_RX_BLSIZE_Pos) /*!< 0x00008000 */ +#define USB_COUNT5_RX_BLSIZE USB_COUNT5_RX_BLSIZE_Msk /*!< BLock SIZE */ + +/***************** Bit definition for USB_COUNT6_RX register ****************/ +#define USB_COUNT6_RX_COUNT6_RX_Pos (0U) +#define USB_COUNT6_RX_COUNT6_RX_Msk (0x3FFUL << USB_COUNT6_RX_COUNT6_RX_Pos) /*!< 0x000003FF */ +#define USB_COUNT6_RX_COUNT6_RX USB_COUNT6_RX_COUNT6_RX_Msk /*!< Reception Byte Count */ + +#define USB_COUNT6_RX_NUM_BLOCK_Pos (10U) +#define USB_COUNT6_RX_NUM_BLOCK_Msk (0x1FUL << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */ +#define USB_COUNT6_RX_NUM_BLOCK USB_COUNT6_RX_NUM_BLOCK_Msk /*!< NUM_BLOCK[4:0] bits (Number of blocks) */ +#define USB_COUNT6_RX_NUM_BLOCK_0 (0x01UL << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */ +#define USB_COUNT6_RX_NUM_BLOCK_1 (0x02UL << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */ +#define USB_COUNT6_RX_NUM_BLOCK_2 (0x04UL << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */ +#define USB_COUNT6_RX_NUM_BLOCK_3 (0x08UL << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */ +#define USB_COUNT6_RX_NUM_BLOCK_4 (0x10UL << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */ + +#define USB_COUNT6_RX_BLSIZE_Pos (15U) +#define USB_COUNT6_RX_BLSIZE_Msk (0x1UL << USB_COUNT6_RX_BLSIZE_Pos) /*!< 0x00008000 */ +#define USB_COUNT6_RX_BLSIZE USB_COUNT6_RX_BLSIZE_Msk /*!< BLock SIZE */ + +/***************** Bit definition for USB_COUNT7_RX register ****************/ +#define USB_COUNT7_RX_COUNT7_RX_Pos (0U) +#define USB_COUNT7_RX_COUNT7_RX_Msk (0x3FFUL << USB_COUNT7_RX_COUNT7_RX_Pos) /*!< 0x000003FF */ +#define USB_COUNT7_RX_COUNT7_RX USB_COUNT7_RX_COUNT7_RX_Msk /*!< Reception Byte Count */ + +#define USB_COUNT7_RX_NUM_BLOCK_Pos (10U) +#define USB_COUNT7_RX_NUM_BLOCK_Msk (0x1FUL << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */ +#define USB_COUNT7_RX_NUM_BLOCK USB_COUNT7_RX_NUM_BLOCK_Msk /*!< NUM_BLOCK[4:0] bits (Number of blocks) */ +#define USB_COUNT7_RX_NUM_BLOCK_0 (0x01UL << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */ +#define USB_COUNT7_RX_NUM_BLOCK_1 (0x02UL << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */ +#define USB_COUNT7_RX_NUM_BLOCK_2 (0x04UL << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */ +#define USB_COUNT7_RX_NUM_BLOCK_3 (0x08UL << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */ +#define USB_COUNT7_RX_NUM_BLOCK_4 (0x10UL << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */ + +#define USB_COUNT7_RX_BLSIZE_Pos (15U) +#define USB_COUNT7_RX_BLSIZE_Msk (0x1UL << USB_COUNT7_RX_BLSIZE_Pos) /*!< 0x00008000 */ +#define USB_COUNT7_RX_BLSIZE USB_COUNT7_RX_BLSIZE_Msk /*!< BLock SIZE */ + +/*----------------------------------------------------------------------------*/ + +/**************** Bit definition for USB_COUNT0_RX_0 register ***************/ +#define USB_COUNT0_RX_0_COUNT0_RX_0 0x000003FFU /*!< Reception Byte Count (low) */ + +#define USB_COUNT0_RX_0_NUM_BLOCK_0 0x00007C00U /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */ +#define USB_COUNT0_RX_0_NUM_BLOCK_0_0 0x00000400U /*!< Bit 0 */ +#define USB_COUNT0_RX_0_NUM_BLOCK_0_1 0x00000800U /*!< Bit 1 */ +#define USB_COUNT0_RX_0_NUM_BLOCK_0_2 0x00001000U /*!< Bit 2 */ +#define USB_COUNT0_RX_0_NUM_BLOCK_0_3 0x00002000U /*!< Bit 3 */ +#define USB_COUNT0_RX_0_NUM_BLOCK_0_4 0x00004000U /*!< Bit 4 */ + +#define USB_COUNT0_RX_0_BLSIZE_0 0x00008000U /*!< BLock SIZE (low) */ + +/**************** Bit definition for USB_COUNT0_RX_1 register ***************/ +#define USB_COUNT0_RX_1_COUNT0_RX_1 0x03FF0000U /*!< Reception Byte Count (high) */ + +#define USB_COUNT0_RX_1_NUM_BLOCK_1 0x7C000000U /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */ +#define USB_COUNT0_RX_1_NUM_BLOCK_1_0 0x04000000U /*!< Bit 1 */ +#define USB_COUNT0_RX_1_NUM_BLOCK_1_1 0x08000000U /*!< Bit 1 */ +#define USB_COUNT0_RX_1_NUM_BLOCK_1_2 0x10000000U /*!< Bit 2 */ +#define USB_COUNT0_RX_1_NUM_BLOCK_1_3 0x20000000U /*!< Bit 3 */ +#define USB_COUNT0_RX_1_NUM_BLOCK_1_4 0x40000000U /*!< Bit 4 */ + +#define USB_COUNT0_RX_1_BLSIZE_1 0x80000000U /*!< BLock SIZE (high) */ + +/**************** Bit definition for USB_COUNT1_RX_0 register ***************/ +#define USB_COUNT1_RX_0_COUNT1_RX_0 0x000003FFU /*!< Reception Byte Count (low) */ + +#define USB_COUNT1_RX_0_NUM_BLOCK_0 0x00007C00U /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */ +#define USB_COUNT1_RX_0_NUM_BLOCK_0_0 0x00000400U /*!< Bit 0 */ +#define USB_COUNT1_RX_0_NUM_BLOCK_0_1 0x00000800U /*!< Bit 1 */ +#define USB_COUNT1_RX_0_NUM_BLOCK_0_2 0x00001000U /*!< Bit 2 */ +#define USB_COUNT1_RX_0_NUM_BLOCK_0_3 0x00002000U /*!< Bit 3 */ +#define USB_COUNT1_RX_0_NUM_BLOCK_0_4 0x00004000U /*!< Bit 4 */ + +#define USB_COUNT1_RX_0_BLSIZE_0 0x00008000U /*!< BLock SIZE (low) */ + +/**************** Bit definition for USB_COUNT1_RX_1 register ***************/ +#define USB_COUNT1_RX_1_COUNT1_RX_1 0x03FF0000U /*!< Reception Byte Count (high) */ + +#define USB_COUNT1_RX_1_NUM_BLOCK_1 0x7C000000U /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */ +#define USB_COUNT1_RX_1_NUM_BLOCK_1_0 0x04000000U /*!< Bit 0 */ +#define USB_COUNT1_RX_1_NUM_BLOCK_1_1 0x08000000U /*!< Bit 1 */ +#define USB_COUNT1_RX_1_NUM_BLOCK_1_2 0x10000000U /*!< Bit 2 */ +#define USB_COUNT1_RX_1_NUM_BLOCK_1_3 0x20000000U /*!< Bit 3 */ +#define USB_COUNT1_RX_1_NUM_BLOCK_1_4 0x40000000U /*!< Bit 4 */ + +#define USB_COUNT1_RX_1_BLSIZE_1 0x80000000U /*!< BLock SIZE (high) */ + +/**************** Bit definition for USB_COUNT2_RX_0 register ***************/ +#define USB_COUNT2_RX_0_COUNT2_RX_0 0x000003FFU /*!< Reception Byte Count (low) */ + +#define USB_COUNT2_RX_0_NUM_BLOCK_0 0x00007C00U /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */ +#define USB_COUNT2_RX_0_NUM_BLOCK_0_0 0x00000400U /*!< Bit 0 */ +#define USB_COUNT2_RX_0_NUM_BLOCK_0_1 0x00000800U /*!< Bit 1 */ +#define USB_COUNT2_RX_0_NUM_BLOCK_0_2 0x00001000U /*!< Bit 2 */ +#define USB_COUNT2_RX_0_NUM_BLOCK_0_3 0x00002000U /*!< Bit 3 */ +#define USB_COUNT2_RX_0_NUM_BLOCK_0_4 0x00004000U /*!< Bit 4 */ + +#define USB_COUNT2_RX_0_BLSIZE_0 0x00008000U /*!< BLock SIZE (low) */ + +/**************** Bit definition for USB_COUNT2_RX_1 register ***************/ +#define USB_COUNT2_RX_1_COUNT2_RX_1 0x03FF0000U /*!< Reception Byte Count (high) */ + +#define USB_COUNT2_RX_1_NUM_BLOCK_1 0x7C000000U /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */ +#define USB_COUNT2_RX_1_NUM_BLOCK_1_0 0x04000000U /*!< Bit 0 */ +#define USB_COUNT2_RX_1_NUM_BLOCK_1_1 0x08000000U /*!< Bit 1 */ +#define USB_COUNT2_RX_1_NUM_BLOCK_1_2 0x10000000U /*!< Bit 2 */ +#define USB_COUNT2_RX_1_NUM_BLOCK_1_3 0x20000000U /*!< Bit 3 */ +#define USB_COUNT2_RX_1_NUM_BLOCK_1_4 0x40000000U /*!< Bit 4 */ + +#define USB_COUNT2_RX_1_BLSIZE_1 0x80000000U /*!< BLock SIZE (high) */ + +/**************** Bit definition for USB_COUNT3_RX_0 register ***************/ +#define USB_COUNT3_RX_0_COUNT3_RX_0 0x000003FFU /*!< Reception Byte Count (low) */ + +#define USB_COUNT3_RX_0_NUM_BLOCK_0 0x00007C00U /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */ +#define USB_COUNT3_RX_0_NUM_BLOCK_0_0 0x00000400U /*!< Bit 0 */ +#define USB_COUNT3_RX_0_NUM_BLOCK_0_1 0x00000800U /*!< Bit 1 */ +#define USB_COUNT3_RX_0_NUM_BLOCK_0_2 0x00001000U /*!< Bit 2 */ +#define USB_COUNT3_RX_0_NUM_BLOCK_0_3 0x00002000U /*!< Bit 3 */ +#define USB_COUNT3_RX_0_NUM_BLOCK_0_4 0x00004000U /*!< Bit 4 */ + +#define USB_COUNT3_RX_0_BLSIZE_0 0x00008000U /*!< BLock SIZE (low) */ + +/**************** Bit definition for USB_COUNT3_RX_1 register ***************/ +#define USB_COUNT3_RX_1_COUNT3_RX_1 0x03FF0000U /*!< Reception Byte Count (high) */ + +#define USB_COUNT3_RX_1_NUM_BLOCK_1 0x7C000000U /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */ +#define USB_COUNT3_RX_1_NUM_BLOCK_1_0 0x04000000U /*!< Bit 0 */ +#define USB_COUNT3_RX_1_NUM_BLOCK_1_1 0x08000000U /*!< Bit 1 */ +#define USB_COUNT3_RX_1_NUM_BLOCK_1_2 0x10000000U /*!< Bit 2 */ +#define USB_COUNT3_RX_1_NUM_BLOCK_1_3 0x20000000U /*!< Bit 3 */ +#define USB_COUNT3_RX_1_NUM_BLOCK_1_4 0x40000000U /*!< Bit 4 */ + +#define USB_COUNT3_RX_1_BLSIZE_1 0x80000000U /*!< BLock SIZE (high) */ + +/**************** Bit definition for USB_COUNT4_RX_0 register ***************/ +#define USB_COUNT4_RX_0_COUNT4_RX_0 0x000003FFU /*!< Reception Byte Count (low) */ + +#define USB_COUNT4_RX_0_NUM_BLOCK_0 0x00007C00U /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */ +#define USB_COUNT4_RX_0_NUM_BLOCK_0_0 0x00000400U /*!< Bit 0 */ +#define USB_COUNT4_RX_0_NUM_BLOCK_0_1 0x00000800U /*!< Bit 1 */ +#define USB_COUNT4_RX_0_NUM_BLOCK_0_2 0x00001000U /*!< Bit 2 */ +#define USB_COUNT4_RX_0_NUM_BLOCK_0_3 0x00002000U /*!< Bit 3 */ +#define USB_COUNT4_RX_0_NUM_BLOCK_0_4 0x00004000U /*!< Bit 4 */ + +#define USB_COUNT4_RX_0_BLSIZE_0 0x00008000U /*!< BLock SIZE (low) */ + +/**************** Bit definition for USB_COUNT4_RX_1 register ***************/ +#define USB_COUNT4_RX_1_COUNT4_RX_1 0x03FF0000U /*!< Reception Byte Count (high) */ + +#define USB_COUNT4_RX_1_NUM_BLOCK_1 0x7C000000U /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */ +#define USB_COUNT4_RX_1_NUM_BLOCK_1_0 0x04000000U /*!< Bit 0 */ +#define USB_COUNT4_RX_1_NUM_BLOCK_1_1 0x08000000U /*!< Bit 1 */ +#define USB_COUNT4_RX_1_NUM_BLOCK_1_2 0x10000000U /*!< Bit 2 */ +#define USB_COUNT4_RX_1_NUM_BLOCK_1_3 0x20000000U /*!< Bit 3 */ +#define USB_COUNT4_RX_1_NUM_BLOCK_1_4 0x40000000U /*!< Bit 4 */ + +#define USB_COUNT4_RX_1_BLSIZE_1 0x80000000U /*!< BLock SIZE (high) */ + +/**************** Bit definition for USB_COUNT5_RX_0 register ***************/ +#define USB_COUNT5_RX_0_COUNT5_RX_0 0x000003FFU /*!< Reception Byte Count (low) */ + +#define USB_COUNT5_RX_0_NUM_BLOCK_0 0x00007C00U /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */ +#define USB_COUNT5_RX_0_NUM_BLOCK_0_0 0x00000400U /*!< Bit 0 */ +#define USB_COUNT5_RX_0_NUM_BLOCK_0_1 0x00000800U /*!< Bit 1 */ +#define USB_COUNT5_RX_0_NUM_BLOCK_0_2 0x00001000U /*!< Bit 2 */ +#define USB_COUNT5_RX_0_NUM_BLOCK_0_3 0x00002000U /*!< Bit 3 */ +#define USB_COUNT5_RX_0_NUM_BLOCK_0_4 0x00004000U /*!< Bit 4 */ + +#define USB_COUNT5_RX_0_BLSIZE_0 0x00008000U /*!< BLock SIZE (low) */ + +/**************** Bit definition for USB_COUNT5_RX_1 register ***************/ +#define USB_COUNT5_RX_1_COUNT5_RX_1 0x03FF0000U /*!< Reception Byte Count (high) */ + +#define USB_COUNT5_RX_1_NUM_BLOCK_1 0x7C000000U /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */ +#define USB_COUNT5_RX_1_NUM_BLOCK_1_0 0x04000000U /*!< Bit 0 */ +#define USB_COUNT5_RX_1_NUM_BLOCK_1_1 0x08000000U /*!< Bit 1 */ +#define USB_COUNT5_RX_1_NUM_BLOCK_1_2 0x10000000U /*!< Bit 2 */ +#define USB_COUNT5_RX_1_NUM_BLOCK_1_3 0x20000000U /*!< Bit 3 */ +#define USB_COUNT5_RX_1_NUM_BLOCK_1_4 0x40000000U /*!< Bit 4 */ + +#define USB_COUNT5_RX_1_BLSIZE_1 0x80000000U /*!< BLock SIZE (high) */ + +/*************** Bit definition for USB_COUNT6_RX_0 register ***************/ +#define USB_COUNT6_RX_0_COUNT6_RX_0 0x000003FFU /*!< Reception Byte Count (low) */ + +#define USB_COUNT6_RX_0_NUM_BLOCK_0 0x00007C00U /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */ +#define USB_COUNT6_RX_0_NUM_BLOCK_0_0 0x00000400U /*!< Bit 0 */ +#define USB_COUNT6_RX_0_NUM_BLOCK_0_1 0x00000800U /*!< Bit 1 */ +#define USB_COUNT6_RX_0_NUM_BLOCK_0_2 0x00001000U /*!< Bit 2 */ +#define USB_COUNT6_RX_0_NUM_BLOCK_0_3 0x00002000U /*!< Bit 3 */ +#define USB_COUNT6_RX_0_NUM_BLOCK_0_4 0x00004000U /*!< Bit 4 */ + +#define USB_COUNT6_RX_0_BLSIZE_0 0x00008000U /*!< BLock SIZE (low) */ + +/**************** Bit definition for USB_COUNT6_RX_1 register ***************/ +#define USB_COUNT6_RX_1_COUNT6_RX_1 0x03FF0000U /*!< Reception Byte Count (high) */ + +#define USB_COUNT6_RX_1_NUM_BLOCK_1 0x7C000000U /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */ +#define USB_COUNT6_RX_1_NUM_BLOCK_1_0 0x04000000U /*!< Bit 0 */ +#define USB_COUNT6_RX_1_NUM_BLOCK_1_1 0x08000000U /*!< Bit 1 */ +#define USB_COUNT6_RX_1_NUM_BLOCK_1_2 0x10000000U /*!< Bit 2 */ +#define USB_COUNT6_RX_1_NUM_BLOCK_1_3 0x20000000U /*!< Bit 3 */ +#define USB_COUNT6_RX_1_NUM_BLOCK_1_4 0x40000000U /*!< Bit 4 */ + +#define USB_COUNT6_RX_1_BLSIZE_1 0x80000000U /*!< BLock SIZE (high) */ + +/*************** Bit definition for USB_COUNT7_RX_0 register ****************/ +#define USB_COUNT7_RX_0_COUNT7_RX_0 0x000003FFU /*!< Reception Byte Count (low) */ + +#define USB_COUNT7_RX_0_NUM_BLOCK_0 0x00007C00U /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */ +#define USB_COUNT7_RX_0_NUM_BLOCK_0_0 0x00000400U /*!< Bit 0 */ +#define USB_COUNT7_RX_0_NUM_BLOCK_0_1 0x00000800U /*!< Bit 1 */ +#define USB_COUNT7_RX_0_NUM_BLOCK_0_2 0x00001000U /*!< Bit 2 */ +#define USB_COUNT7_RX_0_NUM_BLOCK_0_3 0x00002000U /*!< Bit 3 */ +#define USB_COUNT7_RX_0_NUM_BLOCK_0_4 0x00004000U /*!< Bit 4 */ + +#define USB_COUNT7_RX_0_BLSIZE_0 0x00008000U /*!< BLock SIZE (low) */ + +/*************** Bit definition for USB_COUNT7_RX_1 register ****************/ +#define USB_COUNT7_RX_1_COUNT7_RX_1 0x03FF0000U /*!< Reception Byte Count (high) */ + +#define USB_COUNT7_RX_1_NUM_BLOCK_1 0x7C000000U /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */ +#define USB_COUNT7_RX_1_NUM_BLOCK_1_0 0x04000000U /*!< Bit 0 */ +#define USB_COUNT7_RX_1_NUM_BLOCK_1_1 0x08000000U /*!< Bit 1 */ +#define USB_COUNT7_RX_1_NUM_BLOCK_1_2 0x10000000U /*!< Bit 2 */ +#define USB_COUNT7_RX_1_NUM_BLOCK_1_3 0x20000000U /*!< Bit 3 */ +#define USB_COUNT7_RX_1_NUM_BLOCK_1_4 0x40000000U /*!< Bit 4 */ + +#define USB_COUNT7_RX_1_BLSIZE_1 0x80000000U /*!< BLock SIZE (high) */ + +/** + * @} + */ + +#define BTABLE_ADDRESS 0x000U + +#ifndef PMA_ACCESS +#define PMA_ACCESS 2U +#endif +/******************** Bit definition for USB_COUNTn_RX register *************/ +#define USB_CNTRX_NBLK_MSK (0x1FU << 10) +#define USB_CNTRX_BLSIZE (0x1U << 15) + +/* SetENDPOINT */ +#define PCD_SET_ENDPOINT(USBx, bEpNum, wRegValue) (*(__IO uint16_t *)(&(USBx)->EP0R + ((bEpNum) * 2U)) = (uint16_t)(wRegValue)) + +/* GetENDPOINT */ +#define PCD_GET_ENDPOINT(USBx, bEpNum) (*(__IO uint16_t *)(&(USBx)->EP0R + ((bEpNum) * 2U))) + +/** + * @brief sets the type in the endpoint register(bits EP_TYPE[1:0]) + * @param USBx USB peripheral instance register address. + * @param bEpNum Endpoint Number. + * @param wType Endpoint Type. + * @retval None + */ +#define PCD_SET_EPTYPE(USBx, bEpNum, wType) (PCD_SET_ENDPOINT((USBx), (bEpNum), ((PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EP_T_MASK) | (wType) | USB_EP_CTR_TX | USB_EP_CTR_RX))) + +/** + * @brief gets the type in the endpoint register(bits EP_TYPE[1:0]) + * @param USBx USB peripheral instance register address. + * @param bEpNum Endpoint Number. + * @retval Endpoint Type + */ +#define PCD_GET_EPTYPE(USBx, bEpNum) (PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EP_T_FIELD) + +/** + * @brief free buffer used from the application realizing it to the line + * toggles bit SW_BUF in the double buffered endpoint register + * @param USBx USB device. + * @param bEpNum, bDir + * @retval None + */ +#define PCD_FreeUserBuffer(USBx, bEpNum, bDir) \ + do { \ + if ((bDir) == 0U) \ + { \ + /* OUT double buffered endpoint */ \ + PCD_TX_DTOG((USBx), (bEpNum)); \ + } \ + else if ((bDir) == 1U) \ + { \ + /* IN double buffered endpoint */ \ + PCD_RX_DTOG((USBx), (bEpNum)); \ + } \ + } while(0) + +/** + * @brief sets the status for tx transfer (bits STAT_TX[1:0]). + * @param USBx USB peripheral instance register address. + * @param bEpNum Endpoint Number. + * @param wState new state + * @retval None + */ +#define PCD_SET_EP_TX_STATUS(USBx, bEpNum, wState) \ + do { \ + uint16_t _wRegVal; \ + \ + _wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPTX_DTOGMASK; \ + /* toggle first bit ? */ \ + if ((USB_EPTX_DTOG1 & (wState))!= 0U) \ + { \ + _wRegVal ^= USB_EPTX_DTOG1; \ + } \ + /* toggle second bit ? */ \ + if ((USB_EPTX_DTOG2 & (wState))!= 0U) \ + { \ + _wRegVal ^= USB_EPTX_DTOG2; \ + } \ + PCD_SET_ENDPOINT((USBx), (bEpNum), (_wRegVal | USB_EP_CTR_RX | USB_EP_CTR_TX)); \ + } while(0) /* PCD_SET_EP_TX_STATUS */ + +/** + * @brief sets the status for rx transfer (bits STAT_TX[1:0]) + * @param USBx USB peripheral instance register address. + * @param bEpNum Endpoint Number. + * @param wState new state + * @retval None + */ +#define PCD_SET_EP_RX_STATUS(USBx, bEpNum,wState) \ + do { \ + uint16_t _wRegVal; \ + \ + _wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPRX_DTOGMASK; \ + /* toggle first bit ? */ \ + if ((USB_EPRX_DTOG1 & (wState))!= 0U) \ + { \ + _wRegVal ^= USB_EPRX_DTOG1; \ + } \ + /* toggle second bit ? */ \ + if ((USB_EPRX_DTOG2 & (wState))!= 0U) \ + { \ + _wRegVal ^= USB_EPRX_DTOG2; \ + } \ + PCD_SET_ENDPOINT((USBx), (bEpNum), (_wRegVal | USB_EP_CTR_RX | USB_EP_CTR_TX)); \ + } while(0) /* PCD_SET_EP_RX_STATUS */ + +/** + * @brief sets the status for rx & tx (bits STAT_TX[1:0] & STAT_RX[1:0]) + * @param USBx USB peripheral instance register address. + * @param bEpNum Endpoint Number. + * @param wStaterx new state. + * @param wStatetx new state. + * @retval None + */ +#define PCD_SET_EP_TXRX_STATUS(USBx, bEpNum, wStaterx, wStatetx) \ + do { \ + uint16_t _wRegVal; \ + \ + _wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & (USB_EPRX_DTOGMASK | USB_EPTX_STAT); \ + /* toggle first bit ? */ \ + if ((USB_EPRX_DTOG1 & (wStaterx))!= 0U) \ + { \ + _wRegVal ^= USB_EPRX_DTOG1; \ + } \ + /* toggle second bit ? */ \ + if ((USB_EPRX_DTOG2 & (wStaterx))!= 0U) \ + { \ + _wRegVal ^= USB_EPRX_DTOG2; \ + } \ + /* toggle first bit ? */ \ + if ((USB_EPTX_DTOG1 & (wStatetx))!= 0U) \ + { \ + _wRegVal ^= USB_EPTX_DTOG1; \ + } \ + /* toggle second bit ? */ \ + if ((USB_EPTX_DTOG2 & (wStatetx))!= 0U) \ + { \ + _wRegVal ^= USB_EPTX_DTOG2; \ + } \ + \ + PCD_SET_ENDPOINT((USBx), (bEpNum), (_wRegVal | USB_EP_CTR_RX | USB_EP_CTR_TX)); \ + } while(0) /* PCD_SET_EP_TXRX_STATUS */ + +/** + * @brief gets the status for tx/rx transfer (bits STAT_TX[1:0] + * /STAT_RX[1:0]) + * @param USBx USB peripheral instance register address. + * @param bEpNum Endpoint Number. + * @retval status + */ +#define PCD_GET_EP_TX_STATUS(USBx, bEpNum) ((uint16_t)PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPTX_STAT) +#define PCD_GET_EP_RX_STATUS(USBx, bEpNum) ((uint16_t)PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPRX_STAT) + +/** + * @brief sets directly the VALID tx/rx-status into the endpoint register + * @param USBx USB peripheral instance register address. + * @param bEpNum Endpoint Number. + * @retval None + */ +#define PCD_SET_EP_TX_VALID(USBx, bEpNum) (PCD_SET_EP_TX_STATUS((USBx), (bEpNum), USB_EP_TX_VALID)) +#define PCD_SET_EP_RX_VALID(USBx, bEpNum) (PCD_SET_EP_RX_STATUS((USBx), (bEpNum), USB_EP_RX_VALID)) + +/** + * @brief checks stall condition in an endpoint. + * @param USBx USB peripheral instance register address. + * @param bEpNum Endpoint Number. + * @retval TRUE = endpoint in stall condition. + */ +#define PCD_GET_EP_TX_STALL_STATUS(USBx, bEpNum) (PCD_GET_EP_TX_STATUS((USBx), (bEpNum)) == USB_EP_TX_STALL) +#define PCD_GET_EP_RX_STALL_STATUS(USBx, bEpNum) (PCD_GET_EP_RX_STATUS((USBx), (bEpNum)) == USB_EP_RX_STALL) + +/** + * @brief set & clear EP_KIND bit. + * @param USBx USB peripheral instance register address. + * @param bEpNum Endpoint Number. + * @retval None + */ +#define PCD_SET_EP_KIND(USBx, bEpNum) \ + do { \ + uint16_t _wRegVal; \ + \ + _wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPREG_MASK; \ + \ + PCD_SET_ENDPOINT((USBx), (bEpNum), (_wRegVal | USB_EP_CTR_RX | USB_EP_CTR_TX | USB_EP_KIND)); \ + } while(0) /* PCD_SET_EP_KIND */ + +#define PCD_CLEAR_EP_KIND(USBx, bEpNum) \ + do { \ + uint16_t _wRegVal; \ + \ + _wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPKIND_MASK; \ + \ + PCD_SET_ENDPOINT((USBx), (bEpNum), (_wRegVal | USB_EP_CTR_RX | USB_EP_CTR_TX)); \ + } while(0) /* PCD_CLEAR_EP_KIND */ + +/** + * @brief Sets/clears directly STATUS_OUT bit in the endpoint register. + * @param USBx USB peripheral instance register address. + * @param bEpNum Endpoint Number. + * @retval None + */ +#define PCD_SET_OUT_STATUS(USBx, bEpNum) PCD_SET_EP_KIND((USBx), (bEpNum)) +#define PCD_CLEAR_OUT_STATUS(USBx, bEpNum) PCD_CLEAR_EP_KIND((USBx), (bEpNum)) + +/** + * @brief Sets/clears directly EP_KIND bit in the endpoint register. + * @param USBx USB peripheral instance register address. + * @param bEpNum Endpoint Number. + * @retval None + */ +#define PCD_SET_EP_DBUF(USBx, bEpNum) PCD_SET_EP_KIND((USBx), (bEpNum)) +#define PCD_CLEAR_EP_DBUF(USBx, bEpNum) PCD_CLEAR_EP_KIND((USBx), (bEpNum)) + +/** + * @brief Clears bit CTR_RX / CTR_TX in the endpoint register. + * @param USBx USB peripheral instance register address. + * @param bEpNum Endpoint Number. + * @retval None + */ +#define PCD_CLEAR_RX_EP_CTR(USBx, bEpNum) \ + do { \ + uint16_t _wRegVal; \ + \ + _wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & (0x7FFFU & USB_EPREG_MASK); \ + \ + PCD_SET_ENDPOINT((USBx), (bEpNum), (_wRegVal | USB_EP_CTR_TX)); \ + } while(0) /* PCD_CLEAR_RX_EP_CTR */ + +#define PCD_CLEAR_TX_EP_CTR(USBx, bEpNum) \ + do { \ + uint16_t _wRegVal; \ + \ + _wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & (0xFF7FU & USB_EPREG_MASK); \ + \ + PCD_SET_ENDPOINT((USBx), (bEpNum), (_wRegVal | USB_EP_CTR_RX)); \ + } while(0) /* PCD_CLEAR_TX_EP_CTR */ + +/** + * @brief Toggles DTOG_RX / DTOG_TX bit in the endpoint register. + * @param USBx USB peripheral instance register address. + * @param bEpNum Endpoint Number. + * @retval None + */ +#define PCD_RX_DTOG(USBx, bEpNum) \ + do { \ + uint16_t _wEPVal; \ + \ + _wEPVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPREG_MASK; \ + \ + PCD_SET_ENDPOINT((USBx), (bEpNum), (_wEPVal | USB_EP_CTR_RX | USB_EP_CTR_TX | USB_EP_DTOG_RX)); \ + } while(0) /* PCD_RX_DTOG */ + +#define PCD_TX_DTOG(USBx, bEpNum) \ + do { \ + uint16_t _wEPVal; \ + \ + _wEPVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPREG_MASK; \ + \ + PCD_SET_ENDPOINT((USBx), (bEpNum), (_wEPVal | USB_EP_CTR_RX | USB_EP_CTR_TX | USB_EP_DTOG_TX)); \ + } while(0) /* PCD_TX_DTOG */ +/** + * @brief Clears DTOG_RX / DTOG_TX bit in the endpoint register. + * @param USBx USB peripheral instance register address. + * @param bEpNum Endpoint Number. + * @retval None + */ +#define PCD_CLEAR_RX_DTOG(USBx, bEpNum) \ + do { \ + uint16_t _wRegVal; \ + \ + _wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)); \ + \ + if ((_wRegVal & USB_EP_DTOG_RX) != 0U)\ + { \ + PCD_RX_DTOG((USBx), (bEpNum)); \ + } \ + } while(0) /* PCD_CLEAR_RX_DTOG */ + +#define PCD_CLEAR_TX_DTOG(USBx, bEpNum) \ + do { \ + uint16_t _wRegVal; \ + \ + _wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)); \ + \ + if ((_wRegVal & USB_EP_DTOG_TX) != 0U)\ + { \ + PCD_TX_DTOG((USBx), (bEpNum)); \ + } \ + } while(0) /* PCD_CLEAR_TX_DTOG */ + +/** + * @brief Sets address in an endpoint register. + * @param USBx USB peripheral instance register address. + * @param bEpNum Endpoint Number. + * @param bAddr Address. + * @retval None + */ +#define PCD_SET_EP_ADDRESS(USBx, bEpNum, bAddr) \ + do { \ + uint16_t _wRegVal; \ + \ + _wRegVal = (PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPREG_MASK) | (bAddr); \ + \ + PCD_SET_ENDPOINT((USBx), (bEpNum), (_wRegVal | USB_EP_CTR_RX | USB_EP_CTR_TX)); \ + } while(0) /* PCD_SET_EP_ADDRESS */ + +/** + * @brief Gets address in an endpoint register. + * @param USBx USB peripheral instance register address. + * @param bEpNum Endpoint Number. + * @retval None + */ +#define PCD_GET_EP_ADDRESS(USBx, bEpNum) ((uint8_t)(PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPADDR_FIELD)) + +#define PCD_EP_TX_CNT(USBx, bEpNum) ((uint16_t *)((((uint32_t)(USBx)->BTABLE + ((uint32_t)(bEpNum) * 8U) + 2U) * PMA_ACCESS) + ((uint32_t)(USBx) + 0x400U))) +#define PCD_EP_RX_CNT(USBx, bEpNum) ((uint16_t *)((((uint32_t)(USBx)->BTABLE + ((uint32_t)(bEpNum) * 8U) + 6U) * PMA_ACCESS) + ((uint32_t)(USBx) + 0x400U))) + +/** + * @brief sets address of the tx/rx buffer. + * @param USBx USB peripheral instance register address. + * @param bEpNum Endpoint Number. + * @param wAddr address to be set (must be word aligned). + * @retval None + */ +#define PCD_SET_EP_TX_ADDRESS(USBx, bEpNum, wAddr) \ + do { \ + __IO uint16_t *_wRegVal; \ + uint32_t _wRegBase = (uint32_t)USBx; \ + \ + _wRegBase += (uint32_t)(USBx)->BTABLE; \ + _wRegVal = (__IO uint16_t *)(_wRegBase + 0x400U + (((uint32_t)(bEpNum) * 8U) * PMA_ACCESS)); \ + *_wRegVal = ((wAddr) >> 1) << 1; \ + } while(0) /* PCD_SET_EP_TX_ADDRESS */ + +#define PCD_SET_EP_RX_ADDRESS(USBx, bEpNum, wAddr) \ + do { \ + __IO uint16_t *_wRegVal; \ + uint32_t _wRegBase = (uint32_t)USBx; \ + \ + _wRegBase += (uint32_t)(USBx)->BTABLE; \ + _wRegVal = (__IO uint16_t *)(_wRegBase + 0x400U + ((((uint32_t)(bEpNum) * 8U) + 4U) * PMA_ACCESS)); \ + *_wRegVal = ((wAddr) >> 1) << 1; \ + } while(0) /* PCD_SET_EP_RX_ADDRESS */ + +/** + * @brief Gets address of the tx/rx buffer. + * @param USBx USB peripheral instance register address. + * @param bEpNum Endpoint Number. + * @retval address of the buffer. + */ +#define PCD_GET_EP_TX_ADDRESS(USBx, bEpNum) ((uint16_t)*PCD_EP_TX_ADDRESS((USBx), (bEpNum))) +#define PCD_GET_EP_RX_ADDRESS(USBx, bEpNum) ((uint16_t)*PCD_EP_RX_ADDRESS((USBx), (bEpNum))) + +/** + * @brief Sets counter of rx buffer with no. of blocks. + * @param pdwReg Register pointer + * @param wCount Counter. + * @param wNBlocks no. of Blocks. + * @retval None + */ +#define PCD_CALC_BLK32(pdwReg, wCount, wNBlocks) \ + do { \ + (wNBlocks) = (wCount) >> 5; \ + if (((wCount) & 0x1fU) == 0U) \ + { \ + (wNBlocks)--; \ + } \ + *(pdwReg) = (uint16_t)(((wNBlocks) << 10) | USB_CNTRX_BLSIZE); \ + } while(0) /* PCD_CALC_BLK32 */ + +#define PCD_CALC_BLK2(pdwReg, wCount, wNBlocks) \ + do { \ + (wNBlocks) = (wCount) >> 1; \ + if (((wCount) & 0x1U) != 0U) \ + { \ + (wNBlocks)++; \ + } \ + *(pdwReg) = (uint16_t)((wNBlocks) << 10); \ + } while(0) /* PCD_CALC_BLK2 */ + +#define PCD_SET_EP_CNT_RX_REG(pdwReg, wCount) \ + do { \ + uint32_t wNBlocks; \ + if ((wCount) == 0U) \ + { \ + *(pdwReg) &= (uint16_t)~USB_CNTRX_NBLK_MSK; \ + *(pdwReg) |= USB_CNTRX_BLSIZE; \ + } \ + else if((wCount) <= 62U) \ + { \ + PCD_CALC_BLK2((pdwReg), (wCount), wNBlocks); \ + } \ + else \ + { \ + PCD_CALC_BLK32((pdwReg), (wCount), wNBlocks); \ + } \ + } while(0) /* PCD_SET_EP_CNT_RX_REG */ + +#define PCD_SET_EP_RX_DBUF0_CNT(USBx, bEpNum, wCount) \ + do { \ + uint32_t _wRegBase = (uint32_t)(USBx); \ + __IO uint16_t *pdwReg; \ + \ + _wRegBase += (uint32_t)(USBx)->BTABLE; \ + pdwReg = (__IO uint16_t *)(_wRegBase + 0x400U + ((((uint32_t)(bEpNum) * 8U) + 2U) * PMA_ACCESS)); \ + PCD_SET_EP_CNT_RX_REG(pdwReg, (wCount)); \ + } while(0) + +/** + * @brief sets counter for the tx/rx buffer. + * @param USBx USB peripheral instance register address. + * @param bEpNum Endpoint Number. + * @param wCount Counter value. + * @retval None + */ +#define PCD_SET_EP_TX_CNT(USBx, bEpNum, wCount) \ + do { \ + uint32_t _wRegBase = (uint32_t)(USBx); \ + __IO uint16_t *_wRegVal; \ + \ + _wRegBase += (uint32_t)(USBx)->BTABLE; \ + _wRegVal = (__IO uint16_t *)(_wRegBase + 0x400U + ((((uint32_t)(bEpNum) * 8U) + 2U) * PMA_ACCESS)); \ + *_wRegVal = (uint16_t)(wCount); \ + } while(0) + +#define PCD_SET_EP_RX_CNT(USBx, bEpNum, wCount) \ + do { \ + uint32_t _wRegBase = (uint32_t)(USBx); \ + __IO uint16_t *_wRegVal; \ + \ + _wRegBase += (uint32_t)(USBx)->BTABLE; \ + _wRegVal = (__IO uint16_t *)(_wRegBase + 0x400U + ((((uint32_t)(bEpNum) * 8U) + 6U) * PMA_ACCESS)); \ + PCD_SET_EP_CNT_RX_REG(_wRegVal, (wCount)); \ + } while(0) + +/** + * @brief gets counter of the tx buffer. + * @param USBx USB peripheral instance register address. + * @param bEpNum Endpoint Number. + * @retval Counter value + */ +#define PCD_GET_EP_TX_CNT(USBx, bEpNum) ((uint32_t)(*PCD_EP_TX_CNT((USBx), (bEpNum))) & 0x3ffU) +#define PCD_GET_EP_RX_CNT(USBx, bEpNum) ((uint32_t)(*PCD_EP_RX_CNT((USBx), (bEpNum))) & 0x3ffU) + +/** + * @brief Sets buffer 0/1 address in a double buffer endpoint. + * @param USBx USB peripheral instance register address. + * @param bEpNum Endpoint Number. + * @param wBuf0Addr buffer 0 address. + * @retval Counter value + */ +#define PCD_SET_EP_DBUF0_ADDR(USBx, bEpNum, wBuf0Addr) \ + do { \ + PCD_SET_EP_TX_ADDRESS((USBx), (bEpNum), (wBuf0Addr)); \ + } while(0) /* PCD_SET_EP_DBUF0_ADDR */ + +#define PCD_SET_EP_DBUF1_ADDR(USBx, bEpNum, wBuf1Addr) \ + do { \ + PCD_SET_EP_RX_ADDRESS((USBx), (bEpNum), (wBuf1Addr)); \ + } while(0) /* PCD_SET_EP_DBUF1_ADDR */ + +/** + * @brief Sets addresses in a double buffer endpoint. + * @param USBx USB peripheral instance register address. + * @param bEpNum Endpoint Number. + * @param wBuf0Addr: buffer 0 address. + * @param wBuf1Addr = buffer 1 address. + * @retval None + */ +#define PCD_SET_EP_DBUF_ADDR(USBx, bEpNum, wBuf0Addr, wBuf1Addr) \ + do { \ + PCD_SET_EP_DBUF0_ADDR((USBx), (bEpNum), (wBuf0Addr)); \ + PCD_SET_EP_DBUF1_ADDR((USBx), (bEpNum), (wBuf1Addr)); \ + } while(0) /* PCD_SET_EP_DBUF_ADDR */ + +/** + * @brief Gets buffer 0/1 address of a double buffer endpoint. + * @param USBx USB peripheral instance register address. + * @param bEpNum Endpoint Number. + * @retval None + */ +#define PCD_GET_EP_DBUF0_ADDR(USBx, bEpNum) (PCD_GET_EP_TX_ADDRESS((USBx), (bEpNum))) +#define PCD_GET_EP_DBUF1_ADDR(USBx, bEpNum) (PCD_GET_EP_RX_ADDRESS((USBx), (bEpNum))) + +/** + * @brief Gets buffer 0/1 address of a double buffer endpoint. + * @param USBx USB peripheral instance register address. + * @param bEpNum Endpoint Number. + * @param bDir endpoint dir EP_DBUF_OUT = OUT + * EP_DBUF_IN = IN + * @param wCount: Counter value + * @retval None + */ +#define PCD_SET_EP_DBUF0_CNT(USBx, bEpNum, bDir, wCount) \ + do { \ + if ((bDir) == 0U) \ + /* OUT endpoint */ \ + { \ + PCD_SET_EP_RX_DBUF0_CNT((USBx), (bEpNum), (wCount)); \ + } \ + else \ + { \ + if ((bDir) == 1U) \ + { \ + /* IN endpoint */ \ + PCD_SET_EP_TX_CNT((USBx), (bEpNum), (wCount)); \ + } \ + } \ + } while(0) /* SetEPDblBuf0Count*/ + +#define PCD_SET_EP_DBUF1_CNT(USBx, bEpNum, bDir, wCount) \ + do { \ + uint32_t _wBase = (uint32_t)(USBx); \ + __IO uint16_t *_wEPRegVal; \ + \ + if ((bDir) == 0U) \ + { \ + /* OUT endpoint */ \ + PCD_SET_EP_RX_CNT((USBx), (bEpNum), (wCount)); \ + } \ + else \ + { \ + if ((bDir) == 1U) \ + { \ + /* IN endpoint */ \ + _wBase += (uint32_t)(USBx)->BTABLE; \ + _wEPRegVal = (__IO uint16_t *)(_wBase + 0x400U + ((((uint32_t)(bEpNum) * 8U) + 6U) * PMA_ACCESS)); \ + *_wEPRegVal = (uint16_t)(wCount); \ + } \ + } \ + } while(0) /* SetEPDblBuf1Count */ + +#define PCD_SET_EP_DBUF_CNT(USBx, bEpNum, bDir, wCount) \ + do { \ + PCD_SET_EP_DBUF0_CNT((USBx), (bEpNum), (bDir), (wCount)); \ + PCD_SET_EP_DBUF1_CNT((USBx), (bEpNum), (bDir), (wCount)); \ + } while(0) /* PCD_SET_EP_DBUF_CNT */ + +/** + * @brief Gets buffer 0/1 rx/tx counter for double buffering. + * @param USBx USB peripheral instance register address. + * @param bEpNum Endpoint Number. + * @retval None + */ +#define PCD_GET_EP_DBUF0_CNT(USBx, bEpNum) (PCD_GET_EP_TX_CNT((USBx), (bEpNum))) +#define PCD_GET_EP_DBUF1_CNT(USBx, bEpNum) (PCD_GET_EP_RX_CNT((USBx), (bEpNum))) + +#endif \ No newline at end of file diff --git a/kernel/cherryusb/port/fsdev/usb_glue_st.c b/kernel/cherryusb/port/fsdev/usb_glue_st.c new file mode 100644 index 0000000..70a98ac --- /dev/null +++ b/kernel/cherryusb/port/fsdev/usb_glue_st.c @@ -0,0 +1,66 @@ +/* + * Copyright (c) 2025, sakumisu + * + * SPDX-License-Identifier: Apache-2.0 + */ +#include "usbd_core.h" + +#if __has_include("stm32f0xx_hal.h") +#include "stm32f0xx_hal.h" +#elif __has_include("stm32f1xx_hal.h") +#include "stm32f1xx_hal.h" +#elif __has_include("stm32f3xx_hal.h") +#include "stm32f3xx_hal.h" +#elif __has_include("stm32g0xx_hal.h") +#include "stm32g0xx_hal.h" +#elif __has_include("stm32g4xx_hal.h") +#include "stm32g4xx_hal.h" +#elif __has_include("stm32l0xx_hal.h") +#include "stm32l0xx_hal.h" +#elif __has_include("stm32l1xx_hal.h") +#include "stm32l1xx_hal.h" +#elif __has_include("stm32l4xx_hal.h") +#include "stm32l4xx_hal.h" +#elif __has_include("stm32l5xx_hal.h") +#include "stm32l5xx_hal.h" +#endif + +#if !defined(HAL_PCD_MODULE_ENABLED) +#error please define HAL_PCD_MODULE_ENABLED in stm32xxx_hal_conf.h +#endif + +#ifndef CONFIG_USBDEV_FSDEV_PMA_ACCESS +#error "please define CONFIG_USBDEV_FSDEV_PMA_ACCESS in usb_config.h" +#endif + +#if CONFIG_USBDEV_FSDEV_PMA_ACCESS != PMA_ACCESS +#error "CONFIG_USBDEV_FSDEV_PMA_ACCESS must be equal PMA_ACCESS" +#endif + +struct fsdev_instance { + USB_TypeDef *Instance; +}; + +static struct fsdev_instance g_fsdev_instance; + +void usb_dc_low_level_init(uint8_t busid) +{ + g_fsdev_instance.Instance = (USB_TypeDef *)g_usbdev_bus[busid].reg_base; + HAL_PCD_MspInit((PCD_HandleTypeDef *)&g_fsdev_instance); +} + +void usb_dc_low_level_deinit(uint8_t busid) +{ + g_fsdev_instance.Instance = (USB_TypeDef *)g_usbdev_bus[busid].reg_base; + HAL_PCD_MspDeInit((PCD_HandleTypeDef *)&g_fsdev_instance); +} + +void USB_IRQHandler(void) +{ + USBD_IRQHandler(0); +} + +void USB_LP_IRQHandler(void) +{ + USBD_IRQHandler(0); +} \ No newline at end of file diff --git a/kernel/cherryusb/port/hpmicro/README.md b/kernel/cherryusb/port/hpmicro/README.md new file mode 100644 index 0000000..558074d --- /dev/null +++ b/kernel/cherryusb/port/hpmicro/README.md @@ -0,0 +1,5 @@ +# Note + +## Support Chip List + +- HPM all series (HPMicro + EHCI) diff --git a/kernel/cherryusb/port/hpmicro/usb_dc_hpm.c b/kernel/cherryusb/port/hpmicro/usb_dc_hpm.c new file mode 100644 index 0000000..60af118 --- /dev/null +++ b/kernel/cherryusb/port/hpmicro/usb_dc_hpm.c @@ -0,0 +1,413 @@ +/* + * Copyright (c) 2022-2025 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ +#include "usbd_core.h" +#include "hpm_usb_device.h" +#include "usb_glue_hpm.h" +#include "hpm_sdk_version.h" + +#if SDK_VERSION_NUMBER < 0x10C00 +#error "Please use SDK version 1.12.0 or later because of USB api modification" +#endif + +#define USB_NUM_BIDIR_ENDPOINTS USB_SOC_DCD_MAX_ENDPOINT_COUNT + +/* USBSTS, USBINTR */ +enum { + intr_usb = USB_USBINTR_UE_MASK, + intr_error = USB_USBINTR_UEE_MASK, + intr_port_change = USB_USBINTR_PCE_MASK, + intr_reset = USB_USBINTR_URE_MASK, + intr_sof = USB_USBINTR_SRE_MASK, + intr_suspend = USB_USBINTR_SLE_MASK, + intr_nak = USB_USBINTR_NAKE_MASK, +}; + +/* Endpoint state */ +struct hpm_ep_state { + uint16_t ep_mps; /* Endpoint max packet size */ + uint8_t ep_type; /* Endpoint type */ + uint8_t ep_stalled; /* Endpoint stall flag */ + uint8_t ep_enable; /* Endpoint enable */ + uint8_t *xfer_buf; + uint32_t xfer_len; + uint32_t actual_xfer_len; +}; + +/*---------------------------------------------------------------------* + * Variable Definitions + *---------------------------------------------------------------------*/ +/* Driver state */ +struct hpm_udc { + usb_device_handle_t *handle; + bool is_suspend; + struct hpm_ep_state in_ep[USB_NUM_BIDIR_ENDPOINTS]; /*!< IN endpoint parameters*/ + struct hpm_ep_state out_ep[USB_NUM_BIDIR_ENDPOINTS]; /*!< OUT endpoint parameters */ +} g_hpm_udc[CONFIG_USBDEV_MAX_BUS]; + +static USB_NOCACHE_RAM_SECTION ATTR_ALIGN(USB_SOC_DCD_DATA_RAM_ADDRESS_ALIGNMENT) + uint8_t _dcd_data[CONFIG_USBDEV_MAX_BUS][HPM_ALIGN_UP(sizeof(dcd_data_t), USB_SOC_DCD_DATA_RAM_ADDRESS_ALIGNMENT)]; +static USB_NOCACHE_RAM_SECTION usb_device_handle_t usb_device_handle[CONFIG_USBDEV_MAX_BUS]; +static uint8_t _setup_data[8]; + +/* Index to bit position in register */ +static inline uint8_t ep_idx2bit(uint8_t ep_idx) +{ + return ep_idx / 2 + ((ep_idx % 2) ? 16 : 0); +} + +static void usb_dc_isr_connect(uint8_t busid) +{ + if (g_usbdev_bus[busid].reg_base == HPM_USB0_BASE) { + g_usb_hpm_busid[0] = busid; + g_usb_hpm_irq[0] = USBD_IRQHandler; + + hpm_usb_isr_enable(HPM_USB0_BASE); + } else { +#ifdef HPM_USB1_BASE + g_usb_hpm_busid[1] = busid; + g_usb_hpm_irq[1] = USBD_IRQHandler; + + hpm_usb_isr_enable(HPM_USB1_BASE); +#endif + } +} + +static void usb_dc_isr_disconnect(uint8_t busid) +{ + if (g_usbdev_bus[busid].reg_base == HPM_USB0_BASE) { + hpm_usb_isr_disable(HPM_USB0_BASE); + + g_usb_hpm_busid[0] = 0; + g_usb_hpm_irq[0] = NULL; + } else { +#ifdef HPM_USB1_BASE + hpm_usb_isr_disable(HPM_USB1_BASE); + + g_usb_hpm_busid[1] = 0; + g_usb_hpm_irq[1] = NULL; +#endif + } +} + +int usb_dc_init(uint8_t busid) +{ + memset(&g_hpm_udc[busid], 0, sizeof(struct hpm_udc)); + g_hpm_udc[busid].handle = &usb_device_handle[busid]; + g_hpm_udc[busid].handle->regs = (USB_Type *)g_usbdev_bus[busid].reg_base; + g_hpm_udc[busid].handle->dcd_data = (dcd_data_t *)&_dcd_data[busid][0]; + + uint32_t int_mask; + int_mask = (intr_usb | intr_error |intr_port_change | intr_reset | intr_suspend); + +#ifdef CONFIG_USBDEV_SOF_ENABLE + int_mask |= intr_sof; +#endif + + usb_device_init(g_hpm_udc[busid].handle, int_mask); +#ifdef CONFIG_USB_OTG_ENABLE + usb_otgsc_enable_id_chg_int(g_hpm_udc[busid].handle->regs); +#endif + usb_dc_isr_connect(busid); + + return 0; +} + +int usb_dc_deinit(uint8_t busid) +{ + usb_dc_isr_disconnect(busid); + + usb_device_deinit(g_hpm_udc[busid].handle); + + return 0; +} + +int usbd_set_address(uint8_t busid, const uint8_t addr) +{ + usb_device_handle_t *handle = g_hpm_udc[busid].handle; + usb_dcd_set_address(handle->regs, addr); + return 0; +} + +int usbd_set_remote_wakeup(uint8_t busid) +{ + USB_Type *ptr; + + ptr = g_hpm_udc[busid].handle->regs; + + if (!usb_get_suspend_status(ptr)) { + return -1; + } + + usb_force_port_resume(ptr); + + return 0; +} + +void usbd_execute_test_mode(uint8_t busid, uint8_t test_mode) +{ + usb_set_port_test_mode(g_hpm_udc[busid].handle->regs, test_mode); +} + +uint8_t usbd_get_port_speed(uint8_t busid) +{ + uint8_t speed; + + speed = usb_get_port_speed(g_hpm_udc[busid].handle->regs); + + if (speed == 0x00) { + return USB_SPEED_FULL; + } + if (speed == 0x01) { + return USB_SPEED_LOW; + } + if (speed == 0x02) { + return USB_SPEED_HIGH; + } + + return 0; +} + +int usbd_ep_open(uint8_t busid, const struct usb_endpoint_descriptor *ep) +{ + usb_endpoint_config_t tmp_ep_cfg; + usb_device_handle_t *handle = g_hpm_udc[busid].handle; + uint8_t ep_idx = USB_EP_GET_IDX(ep->bEndpointAddress); + + tmp_ep_cfg.xfer = USB_GET_ENDPOINT_TYPE(ep->bmAttributes); + tmp_ep_cfg.ep_addr = ep->bEndpointAddress; + tmp_ep_cfg.max_packet_size = ep->wMaxPacketSize; + + usb_device_edpt_open(handle, &tmp_ep_cfg); + + if (USB_EP_DIR_IS_OUT(ep->bEndpointAddress)) { + g_hpm_udc[busid].out_ep[ep_idx].ep_mps = USB_GET_MAXPACKETSIZE(ep->wMaxPacketSize); + g_hpm_udc[busid].out_ep[ep_idx].ep_type = USB_GET_ENDPOINT_TYPE(ep->bmAttributes); + g_hpm_udc[busid].out_ep[ep_idx].ep_enable = true; + } else { + g_hpm_udc[busid].in_ep[ep_idx].ep_mps = USB_GET_MAXPACKETSIZE(ep->wMaxPacketSize); + g_hpm_udc[busid].in_ep[ep_idx].ep_type = USB_GET_ENDPOINT_TYPE(ep->bmAttributes); + g_hpm_udc[busid].in_ep[ep_idx].ep_enable = true; + } + + return 0; +} + +int usbd_ep_close(uint8_t busid, const uint8_t ep) +{ + usb_device_handle_t *handle = g_hpm_udc[busid].handle; + uint8_t ep_idx = USB_EP_GET_IDX(ep); + + if (USB_EP_DIR_IS_OUT(ep)) { + g_hpm_udc[busid].out_ep[ep_idx].ep_enable = false; + } else { + g_hpm_udc[busid].in_ep[ep_idx].ep_enable = false; + } + + usb_device_edpt_close(handle, ep); + + return 0; +} + +int usbd_ep_set_stall(uint8_t busid, const uint8_t ep) +{ + usb_device_handle_t *handle = g_hpm_udc[busid].handle; + + usb_device_edpt_stall(handle, ep); + return 0; +} + +int usbd_ep_clear_stall(uint8_t busid, const uint8_t ep) +{ + usb_device_handle_t *handle = g_hpm_udc[busid].handle; + + usb_device_edpt_clear_stall(handle, ep); + return 0; +} + +int usbd_ep_is_stalled(uint8_t busid, const uint8_t ep, uint8_t *stalled) +{ + usb_device_handle_t *handle = g_hpm_udc[busid].handle; + + *stalled = usb_device_edpt_check_stall(handle, ep); + return 0; +} + +int usbd_ep_start_write(uint8_t busid, const uint8_t ep, const uint8_t *data, uint32_t data_len) +{ + uint8_t ep_idx = USB_EP_GET_IDX(ep); + usb_device_handle_t *handle = g_hpm_udc[busid].handle; + bool ret; + + if (!data && data_len) { + return -USB_ERR_NOMEM; + } + if (!g_hpm_udc[busid].in_ep[ep_idx].ep_enable) { + return -USB_ERR_NOTCONN; + } + +#ifdef CONFIG_USB_DCACHE_ENABLE + USB_ASSERT_MSG(!((uintptr_t)data % CONFIG_USB_ALIGN_SIZE), "data is not aligned %d", CONFIG_USB_ALIGN_SIZE); +#endif + + g_hpm_udc[busid].in_ep[ep_idx].xfer_buf = (uint8_t *)data; + g_hpm_udc[busid].in_ep[ep_idx].xfer_len = data_len; + g_hpm_udc[busid].in_ep[ep_idx].actual_xfer_len = 0; + + usb_dcache_clean((uintptr_t)data, USB_ALIGN_UP(data_len, CONFIG_USB_ALIGN_SIZE)); + ret = usb_device_edpt_xfer(handle, ep, (uint8_t *)data, data_len); + + return ret ? 0 : -USB_ERR_INVAL; +} + +int usbd_ep_start_read(uint8_t busid, const uint8_t ep, uint8_t *data, uint32_t data_len) +{ + uint8_t ep_idx = USB_EP_GET_IDX(ep); + usb_device_handle_t *handle = g_hpm_udc[busid].handle; + bool ret; + + if (!data && data_len) { + return -USB_ERR_NOMEM; + } + if (!g_hpm_udc[busid].out_ep[ep_idx].ep_enable) { + return -USB_ERR_NOTCONN; + } + +#ifdef CONFIG_USB_DCACHE_ENABLE + USB_ASSERT_MSG(!((uintptr_t)data % CONFIG_USB_ALIGN_SIZE), "data is not aligned %d", CONFIG_USB_ALIGN_SIZE); +#endif + + g_hpm_udc[busid].out_ep[ep_idx].xfer_buf = (uint8_t *)data; + g_hpm_udc[busid].out_ep[ep_idx].xfer_len = data_len; + g_hpm_udc[busid].out_ep[ep_idx].actual_xfer_len = 0; + + usb_dcache_invalidate((uintptr_t)data, USB_ALIGN_UP(data_len, CONFIG_USB_ALIGN_SIZE)); + ret = usb_device_edpt_xfer(handle, ep, data, data_len); + + return ret ? 0 : -USB_ERR_INVAL; +} + +void USBD_IRQHandler(uint8_t busid) +{ + uint32_t int_status; + usb_device_handle_t *handle = g_hpm_udc[busid].handle; + uint32_t transfer_len; + bool ep_cb_req; + + /* Acknowledge handled interrupt */ + int_status = usb_device_status_flags(handle); + int_status &= usb_device_interrupts(handle); + usb_device_clear_status_flags(handle, int_status); + + if (int_status & intr_error) { + USB_LOG_ERR("usbd intr error!\r\n"); + } + +#ifdef CONFIG_USBDEV_SOF_ENABLE + if (int_status & intr_sof) { + usbd_event_sof_handler(busid); + } +#endif + + if (int_status & intr_reset) { + g_hpm_udc[busid].is_suspend = false; + memset(g_hpm_udc[busid].in_ep, 0, sizeof(struct hpm_ep_state) * USB_NUM_BIDIR_ENDPOINTS); + memset(g_hpm_udc[busid].out_ep, 0, sizeof(struct hpm_ep_state) * USB_NUM_BIDIR_ENDPOINTS); + usbd_event_reset_handler(busid); + usb_device_bus_reset(handle, g_hpm_udc[busid].in_ep[0].ep_mps); + return; + } + + if (int_status & intr_suspend) { + if (usb_device_get_suspend_status(handle)) { + /* Note: Host may delay more than 3 ms before and/or after bus reset before doing enumeration. */ + if (usb_device_get_address(handle)) { + g_hpm_udc[busid].is_suspend = true; + usbd_event_suspend_handler(busid); + } + } else { + } + } + + if (int_status & intr_port_change) { + if (!usb_device_get_port_ccs(handle)) { + usbd_event_disconnect_handler(busid); + } else { + if (g_hpm_udc[busid].is_suspend) { + g_hpm_udc[busid].is_suspend = false; + usbd_event_resume_handler(busid); + } + usbd_event_connect_handler(busid); + } + } + + if (int_status & intr_usb) { + uint32_t const edpt_complete = usb_device_get_edpt_complete_status(handle); + uint32_t const edpt_setup_status = usb_device_get_setup_status(handle); + + if (edpt_complete) { + usb_device_clear_edpt_complete_status(handle, edpt_complete); + for (uint8_t ep_idx = 0; ep_idx < USB_SOS_DCD_MAX_QHD_COUNT; ep_idx++) { + if (edpt_complete & (1 << ep_idx2bit(ep_idx))) { + transfer_len = 0; + ep_cb_req = true; + + /* Failed QTD also get ENDPTCOMPLETE set */ + dcd_qhd_t *p_qhd = usb_device_qhd_get(handle, ep_idx); + dcd_qtd_t *p_qtd = p_qhd->attached_qtd; + while (1) { + if (p_qtd->halted || p_qtd->xact_err || p_qtd->buffer_err) { + USB_LOG_ERR("usbd transfer error!\r\n"); + ep_cb_req = false; + break; + } else if (p_qtd->active) { + ep_cb_req = false; + break; + } else { + transfer_len += p_qtd->expected_bytes - p_qtd->total_bytes; + if ((ep_idx & 0x01) != 0) { + g_hpm_udc[busid].in_ep[ep_idx / 2].actual_xfer_len = transfer_len; + } else { + g_hpm_udc[busid].out_ep[ep_idx / 2].actual_xfer_len = transfer_len; + } + p_qtd->in_use = false; + } + + if (p_qtd->next == USB_SOC_DCD_QTD_NEXT_INVALID) { + break; + } else { + p_qtd = (dcd_qtd_t *)p_qtd->next; + } + } + + if (ep_cb_req) { + uint8_t const ep_addr = (ep_idx / 2) | ((ep_idx & 0x01) ? 0x80 : 0); + if (ep_addr & 0x80) { + usbd_event_ep_in_complete_handler(busid, ep_addr, transfer_len); + } else { + usb_dcache_invalidate((uintptr_t)g_hpm_udc[busid].out_ep[ep_idx / 2].xfer_buf, USB_ALIGN_UP(transfer_len, CONFIG_USB_ALIGN_SIZE)); + usbd_event_ep_out_complete_handler(busid, ep_addr, transfer_len); + } + } + } + } + } + + if (edpt_setup_status) { + /*------------- Setup Received -------------*/ + dcd_qhd_t *qhd0 = usb_device_qhd_get(handle, 0); + + usb_device_clear_setup_status(handle, edpt_setup_status); + do { + usb_dcd_set_sutw(handle->regs, true); + memcpy(_setup_data, (uint8_t *)(&qhd0->setup_request), 8); + } while (!usb_dcd_get_sutw(handle->regs)); + usb_dcd_set_sutw(handle->regs, false); + + usbd_event_ep0_setup_complete_handler(busid, _setup_data); + } + } +} \ No newline at end of file diff --git a/kernel/cherryusb/port/hpmicro/usb_glue_hpm.c b/kernel/cherryusb/port/hpmicro/usb_glue_hpm.c new file mode 100644 index 0000000..aa5f9ce --- /dev/null +++ b/kernel/cherryusb/port/hpmicro/usb_glue_hpm.c @@ -0,0 +1,114 @@ +/* + * Copyright (c) 2022-2025 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ +#include "hpm_common.h" +#include "hpm_soc.h" +#include "hpm_l1c_drv.h" +#include "hpm_usb_drv.h" +#include "usb_config.h" + +void (*g_usb_hpm_irq[2])(uint8_t busid); +uint8_t g_usb_hpm_busid[2]; + +#ifndef CONFIG_CHERRYUSB_CUSTOM_IRQ_HANDLER +SDK_DECLARE_EXT_ISR_M(IRQn_USB0, hpm_isr_usb0) +#ifdef HPM_USB1_BASE +SDK_DECLARE_EXT_ISR_M(IRQn_USB1, hpm_isr_usb1) +#endif +#endif + +#ifdef CONFIG_USB_OTG_ENABLE +#include "usbotg_core.h" +int usb_otg_init(uint8_t busid) +{ + (void)busid; + + return 0; +} + +int usb_otg_deinit(uint8_t busid) +{ + (void)busid; + + return 0; +} + +void hpm_isr_usb0(void) +{ + if (usb_otgsc_get_id_chg_flag(HPM_USB0)) { + usb_otgsc_clear_id_chg_flag(HPM_USB0); + usbotg_trigger_role_change(g_usb_hpm_busid[0], usb_otgsc_get_id_status(HPM_USB0) ? USBOTG_MODE_DEVICE : USBOTG_MODE_HOST); + } + + USBOTG_IRQHandler(g_usb_hpm_busid[0]); +} + +#ifdef HPM_USB1_BASE +void hpm_isr_usb1(void) +{ + if (usb_otgsc_get_id_chg_flag(HPM_USB1)) { + usb_otgsc_clear_id_chg_flag(HPM_USB1); + usbotg_trigger_role_change(g_usb_hpm_busid[1], usb_otgsc_get_id_status(HPM_USB1) ? USBOTG_MODE_DEVICE : USBOTG_MODE_HOST); + } + + USBOTG_IRQHandler(g_usb_hpm_busid[1]); +} +#endif + +#else + +void hpm_isr_usb0(void) +{ + g_usb_hpm_irq[0](g_usb_hpm_busid[0]); +} + +#ifdef HPM_USB1_BASE +void hpm_isr_usb1(void) +{ + g_usb_hpm_irq[1](g_usb_hpm_busid[1]); +} +#endif + +#endif + +ATTR_WEAK void hpm_usb_isr_enable(uint32_t base) +{ + if (base == HPM_USB0_BASE) { + intc_m_enable_irq(IRQn_USB0); + } else { +#ifdef HPM_USB1_BASE + intc_m_enable_irq(IRQn_USB1); +#endif + } +} + +ATTR_WEAK void hpm_usb_isr_disable(uint32_t base) +{ + if (base == HPM_USB0_BASE) { + intc_m_disable_irq(IRQn_USB0); + } else { +#ifdef HPM_USB1_BASE + intc_m_disable_irq(IRQn_USB1); +#endif + } +} + +#ifdef CONFIG_USB_DCACHE_ENABLE +void usb_dcache_clean(uintptr_t addr, size_t size) +{ + l1c_dc_writeback(addr, size); +} + +void usb_dcache_invalidate(uintptr_t addr, size_t size) +{ + l1c_dc_invalidate(addr, size); +} + +void usb_dcache_flush(uintptr_t addr, size_t size) +{ + l1c_dc_flush(addr, size); +} +#endif diff --git a/kernel/cherryusb/port/hpmicro/usb_glue_hpm.h b/kernel/cherryusb/port/hpmicro/usb_glue_hpm.h new file mode 100644 index 0000000..dea2dd0 --- /dev/null +++ b/kernel/cherryusb/port/hpmicro/usb_glue_hpm.h @@ -0,0 +1,19 @@ +/* + * Copyright (c) 2022-2025 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef _HPM_USB_GLUE_HPM_H_ +#define _HPM_USB_GLUE_HPM_H_ + +extern void (*g_usb_hpm_irq[2])(uint8_t busid); +extern uint8_t g_usb_hpm_busid[2]; + +void hpm_usb_isr_enable(uint32_t base); +void hpm_usb_isr_disable(uint32_t base); +void hpm_isr_usb0(void); +void hpm_isr_usb1(void); + +#endif /* _HPM_USB_GLUE_HPM_H_ */ \ No newline at end of file diff --git a/kernel/cherryusb/port/hpmicro/usb_hc_hpm.c b/kernel/cherryusb/port/hpmicro/usb_hc_hpm.c new file mode 100644 index 0000000..2c34057 --- /dev/null +++ b/kernel/cherryusb/port/hpmicro/usb_hc_hpm.c @@ -0,0 +1,107 @@ +/* + * Copyright (c) 2022-2025 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ +#include "usbh_core.h" +#include "hpm_common.h" +#include "hpm_soc.h" +#include "hpm_usb_drv.h" +#include "usb_glue_hpm.h" + +#if !defined(CONFIG_USB_EHCI_HPMICRO) || !CONFIG_USB_EHCI_HPMICRO +#error "hpm ehci must set CONFIG_USB_EHCI_HPMICRO=1" +#endif + +#if !defined(CONFIG_USB_EHCI_HCCR_OFFSET) || CONFIG_USB_EHCI_HCCR_OFFSET != 0x100 +#error "hpm ehci must config CONFIG_USB_EHCI_HCCR_OFFSET to 0x100" +#endif + +extern void (*g_usb_hpm_irq[2])(uint8_t busid); +extern uint8_t g_usb_hpm_busid[2]; + +static void usb_host_mode_init(USB_Type *ptr) +{ + /* Set mode to host, must be set immediately after reset */ + ptr->USBMODE &= ~USB_USBMODE_CM_MASK; + ptr->USBMODE |= USB_USBMODE_CM_SET(3); + + /* Set the endian */ + ptr->USBMODE &= ~USB_USBMODE_ES_MASK; + + /* Set parallel interface signal */ + ptr->PORTSC1 &= ~USB_PORTSC1_STS_MASK; + + /* Set parallel transceiver width */ + ptr->PORTSC1 &= ~USB_PORTSC1_PTW_MASK; + +#ifdef CONFIG_USB_HOST_FORCE_FULL_SPEED + /* Set usb forced to full speed mode */ + ptr->PORTSC1 |= USB_PORTSC1_PFSC_MASK; +#endif + + /* Not use interrupt threshold. */ + ptr->USBCMD &= ~USB_USBCMD_ITC_MASK; +} + +void usb_hc_low_level_init(struct usbh_bus *bus) +{ + usb_phy_init((USB_Type *)(bus->hcd.reg_base), true); +} + +void usb_hc_low_level2_init(struct usbh_bus *bus) +{ + usb_host_mode_init((USB_Type *)(bus->hcd.reg_base)); + + if (bus->hcd.reg_base == HPM_USB0_BASE) { + g_usb_hpm_busid[0] = bus->hcd.hcd_id; + g_usb_hpm_irq[0] = USBH_IRQHandler; + } else { +#ifdef HPM_USB1_BASE + g_usb_hpm_busid[1] = bus->hcd.hcd_id; + g_usb_hpm_irq[1] = USBH_IRQHandler; +#endif + } + +#ifdef CONFIG_USB_OTG_ENABLE + usb_otgsc_enable_id_chg_int((USB_Type *)(bus->hcd.reg_base)); +#endif + hpm_usb_isr_enable(bus->hcd.reg_base); +} + +void usb_hc_low_level_deinit(struct usbh_bus *bus) +{ + usb_phy_deinit((USB_Type *)(bus->hcd.reg_base)); + hpm_usb_isr_disable(bus->hcd.reg_base); + + if (bus->hcd.reg_base == HPM_USB0_BASE) { + g_usb_hpm_busid[0] = 0; + g_usb_hpm_irq[0] = NULL; + } else { +#ifdef HPM_USB1_BASE + g_usb_hpm_busid[1] = 0; + g_usb_hpm_irq[1] = NULL; +#endif + } +} + +uint8_t usbh_get_port_speed(struct usbh_bus *bus, const uint8_t port) +{ + (void)port; + uint8_t speed; + + speed = usb_get_port_speed((USB_Type *)(bus->hcd.reg_base)); + + if (speed == 0x00) { + return USB_SPEED_FULL; + } + if (speed == 0x01) { + return USB_SPEED_LOW; + } + if (speed == 0x02) { + return USB_SPEED_HIGH; + } + + return 0; +} \ No newline at end of file diff --git a/kernel/cherryusb/port/kinetis/README.md b/kernel/cherryusb/port/kinetis/README.md new file mode 100644 index 0000000..b91b460 --- /dev/null +++ b/kernel/cherryusb/port/kinetis/README.md @@ -0,0 +1,18 @@ +# Note + +## Support Chip List + +### NXP + +Modify USB_NOCACHE_RAM_SECTION + +``` +#define USB_NOCACHE_RAM_SECTION __attribute__((section(".NonCacheable"))) +``` + +- MCXC444/MCXA153/MCXA156 (device only) +- MCXN947 + +### MM32 + +- MM32F3/MM32F5 diff --git a/kernel/cherryusb/port/kinetis/usb_dc_kinetis.c b/kernel/cherryusb/port/kinetis/usb_dc_kinetis.c new file mode 100644 index 0000000..6cbf535 --- /dev/null +++ b/kernel/cherryusb/port/kinetis/usb_dc_kinetis.c @@ -0,0 +1,463 @@ +/* + * Copyright (c) 2024, sakumisu + * + * SPDX-License-Identifier: Apache-2.0 + */ +#include "usbd_core.h" +#include "usb_kinetis_reg.h" + +#undef CONFIG_USBDEV_EP_NUM +#define CONFIG_USBDEV_EP_NUM 16 + +#define USB_OTG_DEV ((KINETIS_TypeDef *)g_usbdev_bus[busid].reg_base) + +/* Endpoint state */ +struct kinetis_ep_state { + uint16_t ep_mps; /* Endpoint max packet size */ + uint8_t ep_type; /* Endpoint type */ + uint8_t ep_stalled; /* Endpoint stall flag */ + uint8_t ep_enable; /* Endpoint enable */ + bool ep_odd; /* Endpoint odd */ + uint8_t *xfer_buf; + uint32_t xfer_len; + uint32_t actual_xfer_len; +}; + +/* Driver state */ +struct kinetis_udc { + uint8_t dev_addr; + struct kinetis_ep_state in_ep[CONFIG_USBDEV_EP_NUM]; /*!< IN endpoint parameters*/ + struct kinetis_ep_state out_ep[CONFIG_USBDEV_EP_NUM]; /*!< OUT endpoint parameters */ +} g_kinetis_udc[CONFIG_USBDEV_MAX_BUS]; + +USB_NOCACHE_RAM_SECTION __attribute__((aligned(512))) kinetis_bd_table_t g_kinetis_bdt[CONFIG_USBDEV_MAX_BUS]; +USB_NOCACHE_RAM_SECTION __attribute__((aligned(32))) uint8_t setup_packet[CONFIG_USBDEV_MAX_BUS][8]; + +static int kinetis_start_transfer(uint8_t busid, uint8_t ep, uint8_t *buffer, uint16_t buflen) +{ + uint8_t ep_idx = USB_EP_GET_IDX(ep); + uint8_t dir; + uint8_t odd; + uint16_t ep_mps; + kinetis_bd_t *bd; + kinetis_bd_t *next; + + if (USB_EP_DIR_IS_OUT(ep)) { + dir = 0; + odd = g_kinetis_udc[busid].out_ep[ep_idx].ep_odd; + ep_mps = g_kinetis_udc[busid].out_ep[ep_idx].ep_mps; + } else { + dir = 1; + odd = g_kinetis_udc[busid].in_ep[ep_idx].ep_odd; + ep_mps = g_kinetis_udc[busid].in_ep[ep_idx].ep_mps; + } + + bd = &g_kinetis_bdt[busid].table[ep_idx][dir][odd]; + + if (bd->own) { + USB_LOG_INFO("ep%02x is busy\r\n", ep); + return -1; + } + + bd->bc = buflen >= ep_mps ? ep_mps : buflen; + bd->addr = (uint32_t)buffer; + bd->own = 1; + return 0; +} + +static void kinetis_read_setup(uint8_t busid) +{ + uint8_t out_odd = g_kinetis_udc[busid].out_ep[0].ep_odd; + uint8_t in_odd = g_kinetis_udc[busid].in_ep[0].ep_odd; + + if (g_kinetis_bdt[busid].table[0][0][out_odd].own) { + USB_LOG_INFO("ep0 is busy\r\n"); + return; + } + + g_kinetis_bdt[busid].table[0][0][out_odd].data = 0; + g_kinetis_bdt[busid].table[0][0][out_odd ^ 1].data = 1; + g_kinetis_bdt[busid].table[0][1][in_odd].data = 1; + g_kinetis_bdt[busid].table[0][1][in_odd ^ 1].data = 0; + + kinetis_start_transfer(busid, USB_CONTROL_OUT_EP0, setup_packet[busid], 8); +} + +__WEAK void usb_dc_low_level_init(uint8_t busid) +{ +} + +__WEAK void usb_dc_low_level_deinit(uint8_t busid) +{ +} + +int usb_dc_init(uint8_t busid) +{ + usb_dc_low_level_init(busid); + + memset(&g_kinetis_udc[busid], 0, sizeof(g_kinetis_udc[busid])); + + USB_OTG_DEV->BDTPAGE1 = (uint8_t)((uintptr_t)&g_kinetis_bdt[busid] >> 8); + USB_OTG_DEV->BDTPAGE2 = (uint8_t)((uintptr_t)&g_kinetis_bdt[busid] >> 16); + USB_OTG_DEV->BDTPAGE3 = (uint8_t)((uintptr_t)&g_kinetis_bdt[busid] >> 24); + + USB_OTG_DEV->INTEN = USB_INTEN_USBRSTEN_MASK | USB_INTEN_TOKDNEEN_MASK | + USB_INTEN_SLEEPEN_MASK | USB_INTEN_RESUMEEN_MASK | + USB_INTEN_ERROREN_MASK; + +#ifdef CONFIG_USBDEV_SOF_ENABLE + USB_OTG_DEV->INTEN |= USB_INTEN_SOFTOKEN_MASK; +#endif + + USB_OTG_DEV->CTL |= USB_CTL_USBENSOFEN_MASK; + return 0; +} + +int usb_dc_deinit(uint8_t busid) +{ + USB_OTG_DEV->INTEN = 0; + USB_OTG_DEV->CTL &= ~USB_CTL_USBENSOFEN_MASK; + + memset(&g_kinetis_udc[busid], 0, sizeof(g_kinetis_udc[busid])); + + USB_OTG_DEV->BDTPAGE1 = (uint8_t)((uintptr_t)&g_kinetis_bdt[busid] >> 8); + USB_OTG_DEV->BDTPAGE2 = (uint8_t)((uintptr_t)&g_kinetis_bdt[busid] >> 16); + USB_OTG_DEV->BDTPAGE3 = (uint8_t)((uintptr_t)&g_kinetis_bdt[busid] >> 24); + + usb_dc_low_level_deinit(busid); + return 0; +} + +int usbd_set_address(uint8_t busid, const uint8_t addr) +{ + g_kinetis_udc[busid].dev_addr = addr; + + if (addr == 0) { + USB_OTG_DEV->ADDR = 0; + } + return 0; +} + +int usbd_set_remote_wakeup(uint8_t busid) +{ + USB_OTG_DEV->CTL |= USB_CTL_RESUME_MASK; + + usbd_kinetis_delay_ms(10); + + USB_OTG_DEV->CTL &= ~USB_CTL_RESUME_MASK; + + return 0; +} + +uint8_t usbd_get_port_speed(uint8_t busid) +{ + return USB_SPEED_FULL; +} + +int usbd_ep_open(uint8_t busid, const struct usb_endpoint_descriptor *ep) +{ + uint8_t ep_idx = USB_EP_GET_IDX(ep->bEndpointAddress); + uint8_t odd; + uint8_t dir; + kinetis_bd_t *bd; + uint8_t regval; + + /* Must not exceed max endpoint number */ + USB_ASSERT_MSG(ep_idx < CONFIG_USBDEV_EP_NUM, "Ep addr %02x overflow", ep->bEndpointAddress); + + if (USB_EP_DIR_IS_OUT(ep->bEndpointAddress)) { + g_kinetis_udc[busid].out_ep[ep_idx].ep_mps = USB_GET_MAXPACKETSIZE(ep->wMaxPacketSize); + g_kinetis_udc[busid].out_ep[ep_idx].ep_type = USB_GET_ENDPOINT_TYPE(ep->bmAttributes); + g_kinetis_udc[busid].out_ep[ep_idx].ep_enable = true; + + dir = 0; + odd = g_kinetis_udc[busid].out_ep[ep_idx].ep_odd; + } else { + g_kinetis_udc[busid].in_ep[ep_idx].ep_mps = USB_GET_MAXPACKETSIZE(ep->wMaxPacketSize); + g_kinetis_udc[busid].in_ep[ep_idx].ep_type = USB_GET_ENDPOINT_TYPE(ep->bmAttributes); + g_kinetis_udc[busid].in_ep[ep_idx].ep_enable = true; + + dir = 1; + odd = g_kinetis_udc[busid].in_ep[ep_idx].ep_odd; + } + + if (ep_idx != 0) { + regval = USB_ENDPT_EPCTLDIS_MASK; + regval |= (USB_GET_ENDPOINT_TYPE(ep->bmAttributes) != USB_ENDPOINT_TYPE_ISOCHRONOUS) ? USB_ENDPT_EPHSHK_MASK : 0; + regval |= dir ? USB_ENDPT_EPTXEN_MASK : USB_ENDPT_EPRXEN_MASK; + USB_OTG_DEV->ENDPOINT[ep_idx].ENDPT |= regval; + + if (USB_GET_ENDPOINT_TYPE(ep->bmAttributes) != USB_ENDPOINT_TYPE_ISOCHRONOUS) { + bd = &g_kinetis_bdt[busid].table[ep_idx][dir][odd]; + bd->dts = 1; + bd->data = 0; + + bd = &g_kinetis_bdt[busid].table[ep_idx][dir][odd ^ 1]; + bd->dts = 1; + bd->data = 1; + } + } + + return 0; +} + +int usbd_ep_close(uint8_t busid, const uint8_t ep) +{ + uint8_t ep_idx = USB_EP_GET_IDX(ep); + uint8_t dir; + kinetis_bd_t *bd; + + if (USB_EP_DIR_IS_OUT(ep)) { + g_kinetis_udc[busid].out_ep[ep_idx].ep_enable = false; + dir = 0; + } else { + g_kinetis_udc[busid].in_ep[ep_idx].ep_enable = false; + dir = 1; + } + + bd = &g_kinetis_bdt[busid].table[ep_idx][dir][0]; + bd->head = 0; + + bd = &g_kinetis_bdt[busid].table[ep_idx][dir][1]; + bd->head = 0; + + USB_OTG_DEV->ENDPOINT[ep_idx].ENDPT &= ~(dir ? USB_ENDPT_EPTXEN_MASK : USB_ENDPT_EPRXEN_MASK); + return 0; +} + +int usbd_ep_set_stall(uint8_t busid, const uint8_t ep) +{ + uint8_t ep_idx = USB_EP_GET_IDX(ep); + kinetis_bd_t *bd; + uint8_t odd; + uint8_t dir; + + if (0 == ep_idx) { + USB_OTG_DEV->ENDPOINT[ep_idx].ENDPT |= USB_ENDPT_EPSTALL_MASK; + + if (ep_idx == 0) { + kinetis_read_setup(busid); + } + } else { + if (USB_EP_DIR_IS_OUT(ep)) { + dir = 0; + odd = g_kinetis_udc[busid].out_ep[ep_idx].ep_odd; + } else { + dir = 1; + odd = g_kinetis_udc[busid].in_ep[ep_idx].ep_odd; + } + + bd = &g_kinetis_bdt[busid].table[ep_idx][dir][odd]; + + bd->bdt_stall = 1; + bd->own = 1; + } + return 0; +} + +int usbd_ep_clear_stall(uint8_t busid, const uint8_t ep) +{ + uint8_t ep_idx = USB_EP_GET_IDX(ep); + kinetis_bd_t *bd; + uint8_t odd; + uint8_t dir; + + if (USB_EP_DIR_IS_OUT(ep)) { + dir = 0; + odd = g_kinetis_udc[busid].out_ep[ep_idx].ep_odd; + } else { + dir = 1; + odd = g_kinetis_udc[busid].in_ep[ep_idx].ep_odd; + } + + bd = &g_kinetis_bdt[busid].table[ep_idx][dir][odd]; + + bd->own = 0; + bd->bdt_stall = 0; + bd->data = 0; + + bd = &g_kinetis_bdt[busid].table[ep_idx][dir][odd ^ 1]; + bd->data = 1; + + uint8_t regval = USB_OTG_DEV->ENDPOINT[ep_idx].ENDPT; + if (regval & USB_ENDPT_EPSTALL_MASK) { + USB_OTG_DEV->ENDPOINT[ep_idx].ENDPT = regval & ~USB_ENDPT_EPSTALL_MASK; + } + + return 0; +} + +int usbd_ep_is_stalled(uint8_t busid, const uint8_t ep, uint8_t *stalled) +{ + uint8_t ep_idx = USB_EP_GET_IDX(ep); + + uint8_t regval = USB_OTG_DEV->ENDPOINT[ep_idx].ENDPT; + if (regval & USB_ENDPT_EPSTALL_MASK) { + *stalled = 1; + } else { + *stalled = 0; + } + + return 0; +} + +int usbd_ep_start_write(uint8_t busid, const uint8_t ep, const uint8_t *data, + uint32_t data_len) +{ + uint8_t ep_idx = USB_EP_GET_IDX(ep); + + if (!data && data_len) { + return -1; + } + if (!g_kinetis_udc[busid].in_ep[ep_idx].ep_enable) { + return -2; + } + + g_kinetis_udc[busid].in_ep[ep_idx].xfer_buf = (uint8_t *)data; + g_kinetis_udc[busid].in_ep[ep_idx].xfer_len = data_len; + g_kinetis_udc[busid].in_ep[ep_idx].actual_xfer_len = 0; + + return kinetis_start_transfer(busid, ep, (uint8_t *)data, MIN(data_len, g_kinetis_udc[busid].in_ep[ep_idx].ep_mps)); +} + +int usbd_ep_start_read(uint8_t busid, const uint8_t ep, uint8_t *data, + uint32_t data_len) +{ + uint8_t ep_idx = USB_EP_GET_IDX(ep); + + if (!data && data_len) { + return -1; + } + if (!g_kinetis_udc[busid].out_ep[ep_idx].ep_enable) { + return -2; + } + + g_kinetis_udc[busid].out_ep[ep_idx].xfer_buf = (uint8_t *)data; + g_kinetis_udc[busid].out_ep[ep_idx].xfer_len = data_len; + g_kinetis_udc[busid].out_ep[ep_idx].actual_xfer_len = 0; + + return kinetis_start_transfer(busid, ep, (uint8_t *)data, MIN(data_len, g_kinetis_udc[busid].out_ep[ep_idx].ep_mps)); +} + +void USBD_IRQHandler(uint8_t busid) +{ + uint8_t s; + uint8_t pid; + uint8_t ep_idx; + uint8_t dir; + uint8_t odd; + uint16_t bc; + uint8_t is = USB_OTG_DEV->ISTAT; + uint8_t mask = USB_OTG_DEV->INTEN; + kinetis_bd_t *bd; + + USB_OTG_DEV->ISTAT = is & ~mask; + is &= mask; + + if (is & USB_ISTAT_ERROR_MASK) { + uint32_t es = USB_OTG_DEV->ERRSTAT; + USB_OTG_DEV->ERRSTAT = es; + USB_OTG_DEV->ISTAT = is; + } + + if (is & USB_ISTAT_USBRST_MASK) { + USB_OTG_DEV->ISTAT = is; + USB_OTG_DEV->CTL |= USB_CTL_ODDRST_MASK; + USB_OTG_DEV->ADDR = 0; + + USB_OTG_DEV->ENDPOINT[0].ENDPT = USB_ENDPT_EPHSHK_MASK | USB_ENDPT_EPRXEN_MASK | USB_ENDPT_EPTXEN_MASK; + for (uint8_t i = 1; i < 16; i++) { + USB_OTG_DEV->ENDPOINT[i].ENDPT = 0; + } + + memset(&g_kinetis_bdt[busid], 0, sizeof(g_kinetis_bdt[busid])); + memset(g_kinetis_udc[busid].in_ep, 0, sizeof(struct kinetis_ep_state) * CONFIG_USBDEV_EP_NUM); + memset(g_kinetis_udc[busid].out_ep, 0, sizeof(struct kinetis_ep_state) * CONFIG_USBDEV_EP_NUM); + usbd_event_reset_handler(busid); + + kinetis_read_setup(busid); + + USB_OTG_DEV->CTL &= ~USB_CTL_ODDRST_MASK; + } + + if (is & USB_ISTAT_SLEEP_MASK) { + USB_OTG_DEV->ISTAT = USB_ISTAT_SLEEP_MASK; + } + + if (is & USB_ISTAT_RESUME_MASK) { + USB_OTG_DEV->ISTAT = USB_ISTAT_RESUME_MASK; + } +#ifdef CONFIG_USBDEV_SOF_ENABLE + if (is & USB_ISTAT_SOFTOK_MASK) { + USB_OTG_DEV->ISTAT = USB_ISTAT_SOFTOK_MASK; + usbd_event_sof_handler(busid); + } +#endif + if (is & USB_ISTAT_STALL_MASK) { + USB_OTG_DEV->ISTAT = USB_ISTAT_STALL_MASK; + } + + if (is & USB_ISTAT_TOKDNE_MASK) { + s = USB_OTG_DEV->STAT; + USB_OTG_DEV->ISTAT = USB_ISTAT_TOKDNE_MASK; /* must be cleared after get STAT */ + + ep_idx = (s & USB_STAT_ENDP_MASK) >> USB_STAT_ENDP_SHIFT; + dir = (s & USB_STAT_TX_MASK) >> USB_STAT_TX_SHIFT; + odd = (s & USB_STAT_ODD_MASK) >> USB_STAT_ODD_SHIFT; + + bd = &g_kinetis_bdt[busid].table[ep_idx][dir][odd]; + + pid = bd->tok_pid; + bc = bd->bc; + + bd->bdt_stall = 0; + bd->dts = 1; + bd->ninc = 0; + bd->keep = 0; + + if (dir) { + g_kinetis_udc[busid].in_ep[ep_idx].ep_odd = odd ^ 1; + } else { + g_kinetis_udc[busid].out_ep[ep_idx].ep_odd = odd ^ 1; + } + + if (pid == USB_TOKEN_PID_SETUP) { + USB_OTG_DEV->CTL &= ~USB_CTL_TXSUSPENDTOKENBUSY_MASK; + usbd_event_ep0_setup_complete_handler(busid, (uint8_t *)bd->addr); + return; + } + + if (dir) { + g_kinetis_udc[busid].in_ep[ep_idx].xfer_buf += bc; + g_kinetis_udc[busid].in_ep[ep_idx].xfer_len -= bc; + g_kinetis_udc[busid].in_ep[ep_idx].actual_xfer_len += bc; + + if (g_kinetis_udc[busid].in_ep[ep_idx].xfer_len == 0) { + usbd_event_ep_in_complete_handler(busid, ep_idx | 0x80, g_kinetis_udc[busid].in_ep[ep_idx].actual_xfer_len); + } else { + kinetis_start_transfer(busid, ep_idx | 0x80, g_kinetis_udc[busid].in_ep[ep_idx].xfer_buf, + MIN(g_kinetis_udc[busid].in_ep[ep_idx].xfer_len, g_kinetis_udc[busid].in_ep[ep_idx].ep_mps)); + } + } else { + g_kinetis_udc[busid].out_ep[ep_idx].xfer_buf += bc; + g_kinetis_udc[busid].out_ep[ep_idx].xfer_len -= bc; + g_kinetis_udc[busid].out_ep[ep_idx].actual_xfer_len += bc; + + if ((bc < g_kinetis_udc[busid].out_ep[ep_idx].ep_mps) || (g_kinetis_udc[busid].out_ep[ep_idx].xfer_len == 0)) { + usbd_event_ep_out_complete_handler(busid, ep_idx, g_kinetis_udc[busid].out_ep[ep_idx].actual_xfer_len); + } else { + kinetis_start_transfer(busid, ep_idx, g_kinetis_udc[busid].out_ep[ep_idx].xfer_buf, + MIN(g_kinetis_udc[busid].out_ep[ep_idx].xfer_len, g_kinetis_udc[busid].out_ep[ep_idx].ep_mps)); + } + } + + if ((bc == 0) && (ep_idx == 0)) { + if ((g_kinetis_udc[busid].dev_addr > 0) && dir) { + USB_OTG_DEV->ADDR = g_kinetis_udc[busid].dev_addr; + g_kinetis_udc[busid].dev_addr = 0; + } + + kinetis_read_setup(busid); + } + } +} \ No newline at end of file diff --git a/kernel/cherryusb/port/kinetis/usb_glue_mcx.c b/kernel/cherryusb/port/kinetis/usb_glue_mcx.c new file mode 100644 index 0000000..b3d767a --- /dev/null +++ b/kernel/cherryusb/port/kinetis/usb_glue_mcx.c @@ -0,0 +1,93 @@ +/* + * Copyright (c) 2024, sakumisu + * + * SPDX-License-Identifier: Apache-2.0 + */ +#include "usbd_core.h" +#include "fsl_common.h" +#include "usb_kinetis_reg.h" + +#define USB_OTG_DEV ((KINETIS_MCX_TypeDef *)g_usbdev_bus[busid].reg_base) + +#if defined(MCXC444_H_) +#define USBD_IRQ USB0_IRQHandler +void USB_ClockInit(void) +{ + SystemCoreClockUpdate(); + CLOCK_EnableUsbfs0Clock(kCLOCK_UsbSrcIrc48M, 48000000U); +} +#elif defined(MCXA153_H_) +#define USBD_IRQ USB0_IRQHandler +void USB_ClockInit(void) +{ + RESET_PeripheralReset(kUSB0_RST_SHIFT_RSTn); + CLOCK_EnableUsbfsClock(); +} +#elif defined(MCXN947_CM33_CORE0_H_) +#define USBD_IRQ USB0_FS_IRQHandler +void USB_ClockInit(void) +{ + CLOCK_AttachClk(kCLK_48M_to_USB0); + CLOCK_EnableClock(kCLOCK_Usb0Ram); + CLOCK_EnableClock(kCLOCK_Usb0Fs); + CLOCK_EnableUsbfsClock(); +} +#elif defined(MCXA156_H_) +#define USBD_IRQ USB0_IRQHandler +void USB_ClockInit(void) +{ + RESET_PeripheralReset(kUSB0_RST_SHIFT_RSTn); + CLOCK_EnableUsbfsClock(); +} +#else +#error "Unsupported MCU with Kinetis IP" +#endif + +void USBD_IRQ(void) +{ + extern void USBD_IRQHandler(uint8_t busid); + USBD_IRQHandler(0); +} + +void usb_dc_low_level_init(uint8_t busid) +{ + USB_ClockInit(); + + uint8_t irqNumber; + + uint8_t usbDeviceKhciIrq[] = USB_IRQS; + irqNumber = usbDeviceKhciIrq[0]; + + /* Install isr, set priority, and enable IRQ. */ + NVIC_SetPriority((IRQn_Type)irqNumber, 3); + EnableIRQ((IRQn_Type)irqNumber); + + USB_OTG_DEV->USBTRC0 |= USB_USBTRC0_USBRESET_MASK; + while (USB_OTG_DEV->USBTRC0 & USB_USBTRC0_USBRESET_MASK); + + USB_OTG_DEV->USBTRC0 |= USB_USBTRC0_VREGIN_STS(1); /* software must set this bit to 1 */ + USB_OTG_DEV->USBCTRL = 0; + USB_OTG_DEV->CONTROL |= USB_CONTROL_DPPULLUPNONOTG_MASK; +} + +void usb_dc_low_level_deinit(uint8_t busid) +{ + USB_OTG_DEV->CONTROL &= ~USB_CONTROL_DPPULLUPNONOTG_MASK; + #if defined(MCXN947_CM33_CORE0_H_) + DisableIRQ((IRQn_Type)USB0_FS_IRQn); + #else + DisableIRQ((IRQn_Type)USB0_IRQn); + #endif +} + +void usbd_kinetis_delay_ms(uint8_t ms) +{ +#ifdef __RTTHREAD__ + rt_thread_mdelay(ms); +#else + for (uint32_t i = 0; i < ms; i++) + { + for (volatile uint32_t j = 0; j < 10000; j++); + } +#endif +} \ No newline at end of file diff --git a/kernel/cherryusb/port/kinetis/usb_glue_mm32.c b/kernel/cherryusb/port/kinetis/usb_glue_mm32.c new file mode 100644 index 0000000..75e722c --- /dev/null +++ b/kernel/cherryusb/port/kinetis/usb_glue_mm32.c @@ -0,0 +1,36 @@ +#include +#include + +#include "mm32_device.h" +#include "hal_rcc.h" +#include "usbd_core.h" + +void usb_dc_low_level_init(uint8_t busid) +{ + /* Select USBCLK source */ + // RCC_USBCLKConfig(RCC_USBCLKSource_PLLCLK_Div1); + RCC->CFGR &= ~(0x3 << 22); + RCC->CFGR |= (0x1 << 22); + + /* Enable USB clock */ + RCC->AHB2ENR |= 0x1 << 7; + +#define USB_DEVICE_INTERRUPT_PRIORITY (7U) + NVIC_SetPriority((IRQn_Type)USB_OTGFS_IRQn, USB_DEVICE_INTERRUPT_PRIORITY); + NVIC_EnableIRQ(USB_OTGFS_IRQn); +} + +void usb_dc_low_level_deinit(uint8_t busid) +{ + RCC->AHB2ENR &= ~(0x1 << 7); +} + +void USB_OTGFS_IRQHandler(void) +{ + USBD_IRQHandler(0); +} + +void usbd_kinetis_delay_ms(uint8_t ms) +{ + //delay_ms(ms); +} diff --git a/kernel/cherryusb/port/kinetis/usb_hc_kinetis.c b/kernel/cherryusb/port/kinetis/usb_hc_kinetis.c new file mode 100644 index 0000000..30404ce --- /dev/null +++ b/kernel/cherryusb/port/kinetis/usb_hc_kinetis.c @@ -0,0 +1 @@ +TODO \ No newline at end of file diff --git a/kernel/cherryusb/port/kinetis/usb_kinetis_reg.h b/kernel/cherryusb/port/kinetis/usb_kinetis_reg.h new file mode 100644 index 0000000..b2720a6 --- /dev/null +++ b/kernel/cherryusb/port/kinetis/usb_kinetis_reg.h @@ -0,0 +1,1487 @@ +/* + * Copyright (c) 2024, sakumisu + * + * SPDX-License-Identifier: Apache-2.0 + */ +#ifndef __USB_KINETIS_REG_H__ +#define __USB_KINETIS_REG_H__ + +#define __I volatile const /* Define "read-only" permission */ +#define __IO volatile /* Define "read-write" permission */ + +/* ---------------------------------------------------------------------------- + -- USB Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup USB_Peripheral_Access_Layer USB Peripheral Access Layer + * @{ + */ + +/** USB - Register Layout Typedef */ +typedef struct { + __I uint8_t PERID; /**< Peripheral ID, offset: 0x0 */ + uint8_t RESERVED_0[3]; + __I uint8_t IDCOMP; /**< Peripheral ID Complement, offset: 0x4 */ + uint8_t RESERVED_1[3]; + __I uint8_t REV; /**< Peripheral Revision, offset: 0x8 */ + uint8_t RESERVED_2[3]; + __I uint8_t ADDINFO; /**< Peripheral Additional Information, offset: 0xC */ + uint8_t RESERVED_3[3]; + __IO uint8_t OTGISTAT; /**< OTG Interrupt Status, offset: 0x10 */ + uint8_t RESERVED_4[3]; + __IO uint8_t OTGICR; /**< OTG Interrupt Control, offset: 0x14 */ + uint8_t RESERVED_5[3]; + __I uint8_t OTGSTAT; /**< OTG Status, offset: 0x18 */ + uint8_t RESERVED_6[3]; + __IO uint8_t OTGCTL; /**< OTG Control, offset: 0x1C */ + uint8_t RESERVED_7[99]; + __IO uint8_t ISTAT; /**< Interrupt Status, offset: 0x80 */ + uint8_t RESERVED_8[3]; + __IO uint8_t INTEN; /**< Interrupt Enable, offset: 0x84 */ + uint8_t RESERVED_9[3]; + __IO uint8_t ERRSTAT; /**< Error Interrupt Status, offset: 0x88 */ + uint8_t RESERVED_10[3]; + __IO uint8_t ERREN; /**< Error Interrupt Enable, offset: 0x8C */ + uint8_t RESERVED_11[3]; + __I uint8_t STAT; /**< Status, offset: 0x90 */ + uint8_t RESERVED_12[3]; + __IO uint8_t CTL; /**< Control, offset: 0x94 */ + uint8_t RESERVED_13[3]; + __IO uint8_t ADDR; /**< Address, offset: 0x98 */ + uint8_t RESERVED_14[3]; + __IO uint8_t BDTPAGE1; /**< BDT Page 1, offset: 0x9C */ + uint8_t RESERVED_15[3]; + __I uint8_t FRMNUML; /**< Frame Number Register Low, offset: 0xA0 */ + uint8_t RESERVED_16[3]; + __I uint8_t FRMNUMH; /**< Frame Number Register High, offset: 0xA4 */ + uint8_t RESERVED_17[3]; + __IO uint8_t TOKEN; /**< Token, offset: 0xA8 */ + uint8_t RESERVED_18[3]; + __IO uint8_t SOFTHLD; /**< SOF Threshold, offset: 0xAC */ + uint8_t RESERVED_19[3]; + __IO uint8_t BDTPAGE2; /**< BDT Page 2, offset: 0xB0 */ + uint8_t RESERVED_20[3]; + __IO uint8_t BDTPAGE3; /**< BDT Page 3, offset: 0xB4 */ + uint8_t RESERVED_21[11]; + struct { /* offset: 0xC0, array step: 0x4 */ + __IO uint8_t ENDPT; /**< Endpoint Control, array offset: 0xC0, array step: 0x4 */ + uint8_t RESERVED_0[3]; + } ENDPOINT[16]; +} KINETIS_TypeDef; + +/* ---------------------------------------------------------------------------- + -- USB Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup USB_Register_Masks USB Register Masks + * @{ + */ + +/*! @name PERID - Peripheral ID */ +/*! @{ */ + +#define USB_PERID_ID_MASK (0x3FU) +#define USB_PERID_ID_SHIFT (0U) +/*! ID - Peripheral Identification */ +#define USB_PERID_ID(x) (((uint8_t)(((uint8_t)(x)) << USB_PERID_ID_SHIFT)) & USB_PERID_ID_MASK) +/*! @} */ + +/*! @name IDCOMP - Peripheral ID Complement */ +/*! @{ */ + +#define USB_IDCOMP_NID_MASK (0x3FU) +#define USB_IDCOMP_NID_SHIFT (0U) +/*! NID - Negative Peripheral ID */ +#define USB_IDCOMP_NID(x) (((uint8_t)(((uint8_t)(x)) << USB_IDCOMP_NID_SHIFT)) & USB_IDCOMP_NID_MASK) +/*! @} */ + +/*! @name REV - Peripheral Revision */ +/*! @{ */ + +#define USB_REV_REV_MASK (0xFFU) +#define USB_REV_REV_SHIFT (0U) +/*! REV - Revision */ +#define USB_REV_REV(x) (((uint8_t)(((uint8_t)(x)) << USB_REV_REV_SHIFT)) & USB_REV_REV_MASK) +/*! @} */ + +/*! @name ADDINFO - Peripheral Additional Information */ +/*! @{ */ + +#define USB_ADDINFO_IEHOST_MASK (0x1U) +#define USB_ADDINFO_IEHOST_SHIFT (0U) +/*! IEHOST - Host Mode Enable + * 0b0..Disabled + * 0b1..Enabled + */ +#define USB_ADDINFO_IEHOST(x) (((uint8_t)(((uint8_t)(x)) << USB_ADDINFO_IEHOST_SHIFT)) & USB_ADDINFO_IEHOST_MASK) +/*! @} */ + +/*! @name OTGISTAT - OTG Interrupt Status */ +/*! @{ */ + +#define USB_OTGISTAT_LINE_STATE_CHG_MASK (0x20U) +#define USB_OTGISTAT_LINE_STATE_CHG_SHIFT (5U) +/*! LINE_STATE_CHG - Line State Change Interrupt Flag + * 0b0..Interrupt did not occur + * 0b1..Interrupt occurred + * 0b0..No effect + * 0b1..Clear the flag + */ +#define USB_OTGISTAT_LINE_STATE_CHG(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGISTAT_LINE_STATE_CHG_SHIFT)) & USB_OTGISTAT_LINE_STATE_CHG_MASK) + +#define USB_OTGISTAT_ONEMSEC_MASK (0x40U) +#define USB_OTGISTAT_ONEMSEC_SHIFT (6U) +/*! ONEMSEC - One Millisecond Timer Timeout Flag + * 0b0..Not timed out + * 0b1..Timed out + * 0b0..No effect + * 0b1..Clear the flag + */ +#define USB_OTGISTAT_ONEMSEC(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGISTAT_ONEMSEC_SHIFT)) & USB_OTGISTAT_ONEMSEC_MASK) +/*! @} */ + +/*! @name OTGICR - OTG Interrupt Control */ +/*! @{ */ + +#define USB_OTGICR_LINESTATEEN_MASK (0x20U) +#define USB_OTGICR_LINESTATEEN_SHIFT (5U) +/*! LINESTATEEN - Line State Change Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define USB_OTGICR_LINESTATEEN(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGICR_LINESTATEEN_SHIFT)) & USB_OTGICR_LINESTATEEN_MASK) + +#define USB_OTGICR_ONEMSECEN_MASK (0x40U) +#define USB_OTGICR_ONEMSECEN_SHIFT (6U) +/*! ONEMSECEN - 1-Millisecond Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define USB_OTGICR_ONEMSECEN(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGICR_ONEMSECEN_SHIFT)) & USB_OTGICR_ONEMSECEN_MASK) +/*! @} */ + +/*! @name OTGSTAT - OTG Status */ +/*! @{ */ + +#define USB_OTGSTAT_LINESTATESTABLE_MASK (0x20U) +#define USB_OTGSTAT_LINESTATESTABLE_SHIFT (5U) +/*! LINESTATESTABLE - Line State Stable + * 0b0..Unstable + * 0b1..Stable + */ +#define USB_OTGSTAT_LINESTATESTABLE(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGSTAT_LINESTATESTABLE_SHIFT)) & USB_OTGSTAT_LINESTATESTABLE_MASK) + +#define USB_OTGSTAT_ONEMSEC_MASK (0x40U) +#define USB_OTGSTAT_ONEMSEC_SHIFT (6U) +/*! ONEMSEC - Reserved for 1 ms count */ +#define USB_OTGSTAT_ONEMSEC(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGSTAT_ONEMSEC_SHIFT)) & USB_OTGSTAT_ONEMSEC_MASK) +/*! @} */ + +/*! @name OTGCTL - OTG Control */ +/*! @{ */ + +#define USB_OTGCTL_OTGEN_MASK (0x4U) +#define USB_OTGCTL_OTGEN_SHIFT (2U) +/*! OTGEN - On-The-Go Pullup and Pulldown Resistor Enable + * 0b0..If USBENSOFEN is 1 and HOSTMODEEN is 0 in the Control Register (CTL), then the D+ Data line pullup + * resistors are enabled. If HOSTMODEEN is 1, then the D+ and D- Data line pulldown resistors are engaged. + * 0b1..Uses the pullup and pulldown controls in this register. + */ +#define USB_OTGCTL_OTGEN(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGCTL_OTGEN_SHIFT)) & USB_OTGCTL_OTGEN_MASK) + +#define USB_OTGCTL_DMLOW_MASK (0x10U) +#define USB_OTGCTL_DMLOW_SHIFT (4U) +/*! DMLOW - D- Data Line Pulldown Resistor Enable + * 0b0..Disable + * 0b1..Enable + */ +#define USB_OTGCTL_DMLOW(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGCTL_DMLOW_SHIFT)) & USB_OTGCTL_DMLOW_MASK) + +#define USB_OTGCTL_DPLOW_MASK (0x20U) +#define USB_OTGCTL_DPLOW_SHIFT (5U) +/*! DPLOW - D+ Data Line pulldown Resistor Enable + * 0b0..Disable + * 0b1..Enable + */ +#define USB_OTGCTL_DPLOW(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGCTL_DPLOW_SHIFT)) & USB_OTGCTL_DPLOW_MASK) + +#define USB_OTGCTL_DPHIGH_MASK (0x80U) +#define USB_OTGCTL_DPHIGH_SHIFT (7U) +/*! DPHIGH - D+ Data Line Pullup Resistor Enable + * 0b0..Disable + * 0b1..Enable + */ +#define USB_OTGCTL_DPHIGH(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGCTL_DPHIGH_SHIFT)) & USB_OTGCTL_DPHIGH_MASK) +/*! @} */ + +/*! @name ISTAT - Interrupt Status */ +/*! @{ */ + +#define USB_ISTAT_USBRST_MASK (0x1U) +#define USB_ISTAT_USBRST_SHIFT (0U) +/*! USBRST - USB Reset Flag + * 0b0..Not detected + * 0b1..Detected + * 0b0..No effect + * 0b1..Clear the flag + */ +#define USB_ISTAT_USBRST(x) (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_USBRST_SHIFT)) & USB_ISTAT_USBRST_MASK) + +#define USB_ISTAT_ERROR_MASK (0x2U) +#define USB_ISTAT_ERROR_SHIFT (1U) +/*! ERROR - Error Flag + * 0b0..Error did not occur + * 0b1..Error occurred + * 0b0..No effect + * 0b1..Clear the flag + */ +#define USB_ISTAT_ERROR(x) (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_ERROR_SHIFT)) & USB_ISTAT_ERROR_MASK) + +#define USB_ISTAT_SOFTOK_MASK (0x4U) +#define USB_ISTAT_SOFTOK_SHIFT (2U) +/*! SOFTOK - Start Of Frame (SOF) Token Flag + * 0b0..Did not receive + * 0b1..Received + * 0b0..No effect + * 0b1..Clear the flag + */ +#define USB_ISTAT_SOFTOK(x) (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_SOFTOK_SHIFT)) & USB_ISTAT_SOFTOK_MASK) + +#define USB_ISTAT_TOKDNE_MASK (0x8U) +#define USB_ISTAT_TOKDNE_SHIFT (3U) +/*! TOKDNE - Current Token Processing Flag + * 0b0..Not processed + * 0b1..Processed + * 0b0..No effect + * 0b1..Clear the flag + */ +#define USB_ISTAT_TOKDNE(x) (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_TOKDNE_SHIFT)) & USB_ISTAT_TOKDNE_MASK) + +#define USB_ISTAT_SLEEP_MASK (0x10U) +#define USB_ISTAT_SLEEP_SHIFT (4U) +/*! SLEEP - Sleep Flag + * 0b0..Interrupt did not occur + * 0b1..Interrupt occurred + * 0b0..No effect + * 0b1..Clear the flag + */ +#define USB_ISTAT_SLEEP(x) (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_SLEEP_SHIFT)) & USB_ISTAT_SLEEP_MASK) + +#define USB_ISTAT_RESUME_MASK (0x20U) +#define USB_ISTAT_RESUME_SHIFT (5U) +/*! RESUME - Resume Flag + * 0b0..Interrupt did not occur + * 0b1..Interrupt occurred + * 0b0..No effect + * 0b1..Clear the flag + */ +#define USB_ISTAT_RESUME(x) (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_RESUME_SHIFT)) & USB_ISTAT_RESUME_MASK) + +#define USB_ISTAT_ATTACH_MASK (0x40U) +#define USB_ISTAT_ATTACH_SHIFT (6U) +/*! ATTACH - Attach Interrupt Flag + * 0b0..Not detected + * 0b1..Detected + * 0b0..No effect + * 0b1..Clear the flag + */ +#define USB_ISTAT_ATTACH(x) (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_ATTACH_SHIFT)) & USB_ISTAT_ATTACH_MASK) + +#define USB_ISTAT_STALL_MASK (0x80U) +#define USB_ISTAT_STALL_SHIFT (7U) +/*! STALL - Stall Interrupt Flag + * 0b0..Interrupt did not occur + * 0b1..Interrupt occurred + * 0b0..No effect + * 0b1..Clear the flag + */ +#define USB_ISTAT_STALL(x) (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_STALL_SHIFT)) & USB_ISTAT_STALL_MASK) +/*! @} */ + +/*! @name INTEN - Interrupt Enable */ +/*! @{ */ + +#define USB_INTEN_USBRSTEN_MASK (0x1U) +#define USB_INTEN_USBRSTEN_SHIFT (0U) +/*! USBRSTEN - USBRST Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define USB_INTEN_USBRSTEN(x) (((uint8_t)(((uint8_t)(x)) << USB_INTEN_USBRSTEN_SHIFT)) & USB_INTEN_USBRSTEN_MASK) + +#define USB_INTEN_ERROREN_MASK (0x2U) +#define USB_INTEN_ERROREN_SHIFT (1U) +/*! ERROREN - ERROR Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define USB_INTEN_ERROREN(x) (((uint8_t)(((uint8_t)(x)) << USB_INTEN_ERROREN_SHIFT)) & USB_INTEN_ERROREN_MASK) + +#define USB_INTEN_SOFTOKEN_MASK (0x4U) +#define USB_INTEN_SOFTOKEN_SHIFT (2U) +/*! SOFTOKEN - SOFTOK Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define USB_INTEN_SOFTOKEN(x) (((uint8_t)(((uint8_t)(x)) << USB_INTEN_SOFTOKEN_SHIFT)) & USB_INTEN_SOFTOKEN_MASK) + +#define USB_INTEN_TOKDNEEN_MASK (0x8U) +#define USB_INTEN_TOKDNEEN_SHIFT (3U) +/*! TOKDNEEN - TOKDNE Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define USB_INTEN_TOKDNEEN(x) (((uint8_t)(((uint8_t)(x)) << USB_INTEN_TOKDNEEN_SHIFT)) & USB_INTEN_TOKDNEEN_MASK) + +#define USB_INTEN_SLEEPEN_MASK (0x10U) +#define USB_INTEN_SLEEPEN_SHIFT (4U) +/*! SLEEPEN - SLEEP Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define USB_INTEN_SLEEPEN(x) (((uint8_t)(((uint8_t)(x)) << USB_INTEN_SLEEPEN_SHIFT)) & USB_INTEN_SLEEPEN_MASK) + +#define USB_INTEN_RESUMEEN_MASK (0x20U) +#define USB_INTEN_RESUMEEN_SHIFT (5U) +/*! RESUMEEN - RESUME Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define USB_INTEN_RESUMEEN(x) (((uint8_t)(((uint8_t)(x)) << USB_INTEN_RESUMEEN_SHIFT)) & USB_INTEN_RESUMEEN_MASK) + +#define USB_INTEN_ATTACHEN_MASK (0x40U) +#define USB_INTEN_ATTACHEN_SHIFT (6U) +/*! ATTACHEN - ATTACH Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define USB_INTEN_ATTACHEN(x) (((uint8_t)(((uint8_t)(x)) << USB_INTEN_ATTACHEN_SHIFT)) & USB_INTEN_ATTACHEN_MASK) + +#define USB_INTEN_STALLEN_MASK (0x80U) +#define USB_INTEN_STALLEN_SHIFT (7U) +/*! STALLEN - STALL Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define USB_INTEN_STALLEN(x) (((uint8_t)(((uint8_t)(x)) << USB_INTEN_STALLEN_SHIFT)) & USB_INTEN_STALLEN_MASK) +/*! @} */ + +/*! @name ERRSTAT - Error Interrupt Status */ +/*! @{ */ + +#define USB_ERRSTAT_PIDERR_MASK (0x1U) +#define USB_ERRSTAT_PIDERR_SHIFT (0U) +/*! PIDERR - PID Error Flag + * 0b0..Did not fail + * 0b1..Failed + * 0b0..No effect + * 0b1..Clear the flag + */ +#define USB_ERRSTAT_PIDERR(x) (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_PIDERR_SHIFT)) & USB_ERRSTAT_PIDERR_MASK) + +#define USB_ERRSTAT_CRC5EOF_MASK (0x2U) +#define USB_ERRSTAT_CRC5EOF_SHIFT (1U) +/*! CRC5EOF - CRC5 Error or End of Frame Error Flag + * 0b0..Interrupt did not occur + * 0b1..Interrupt occurred + * 0b0..No effect + * 0b1..Clear the flag + */ +#define USB_ERRSTAT_CRC5EOF(x) (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_CRC5EOF_SHIFT)) & USB_ERRSTAT_CRC5EOF_MASK) + +#define USB_ERRSTAT_CRC16_MASK (0x4U) +#define USB_ERRSTAT_CRC16_SHIFT (2U) +/*! CRC16 - CRC16 Error Flag + * 0b0..Not rejected + * 0b1..Rejected + * 0b0..No effect + * 0b1..Clear the flag + */ +#define USB_ERRSTAT_CRC16(x) (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_CRC16_SHIFT)) & USB_ERRSTAT_CRC16_MASK) + +#define USB_ERRSTAT_DFN8_MASK (0x8U) +#define USB_ERRSTAT_DFN8_SHIFT (3U) +/*! DFN8 - Data Field Not 8 Bits Flag + * 0b0..Integer number of bytes + * 0b1..Not an integer number of bytes + * 0b0..No effect + * 0b1..Clear the flag + */ +#define USB_ERRSTAT_DFN8(x) (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_DFN8_SHIFT)) & USB_ERRSTAT_DFN8_MASK) + +#define USB_ERRSTAT_BTOERR_MASK (0x10U) +#define USB_ERRSTAT_BTOERR_SHIFT (4U) +/*! BTOERR - Bus Turnaround Timeout Error Flag + * 0b0..Not timed out + * 0b1..Timed out + * 0b0..No effect + * 0b1..Clear the flag + */ +#define USB_ERRSTAT_BTOERR(x) (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_BTOERR_SHIFT)) & USB_ERRSTAT_BTOERR_MASK) + +#define USB_ERRSTAT_DMAERR_MASK (0x20U) +#define USB_ERRSTAT_DMAERR_SHIFT (5U) +/*! DMAERR - DMA Access Error Flag + * 0b0..Interrupt did not occur + * 0b1..Interrupt occurred + * 0b0..No effect + * 0b1..Clear the flag + */ +#define USB_ERRSTAT_DMAERR(x) (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_DMAERR_SHIFT)) & USB_ERRSTAT_DMAERR_MASK) + +#define USB_ERRSTAT_OWNERR_MASK (0x40U) +#define USB_ERRSTAT_OWNERR_SHIFT (6U) +/*! OWNERR - BD Unavailable Error Flag + * 0b0..Interrupt did not occur + * 0b1..Interrupt occurred + * 0b0..No effect + * 0b1..Clear the flag + */ +#define USB_ERRSTAT_OWNERR(x) (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_OWNERR_SHIFT)) & USB_ERRSTAT_OWNERR_MASK) + +#define USB_ERRSTAT_BTSERR_MASK (0x80U) +#define USB_ERRSTAT_BTSERR_SHIFT (7U) +/*! BTSERR - Bit Stuff Error Flag + * 0b0..Packet not rejected due to the error + * 0b1..Packet rejected due to the error + * 0b0..No effect + * 0b1..Clear the flag + */ +#define USB_ERRSTAT_BTSERR(x) (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_BTSERR_SHIFT)) & USB_ERRSTAT_BTSERR_MASK) +/*! @} */ + +/*! @name ERREN - Error Interrupt Enable */ +/*! @{ */ + +#define USB_ERREN_PIDERREN_MASK (0x1U) +#define USB_ERREN_PIDERREN_SHIFT (0U) +/*! PIDERREN - PIDERR Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define USB_ERREN_PIDERREN(x) (((uint8_t)(((uint8_t)(x)) << USB_ERREN_PIDERREN_SHIFT)) & USB_ERREN_PIDERREN_MASK) + +#define USB_ERREN_CRC5EOFEN_MASK (0x2U) +#define USB_ERREN_CRC5EOFEN_SHIFT (1U) +/*! CRC5EOFEN - CRC5/EOF Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define USB_ERREN_CRC5EOFEN(x) (((uint8_t)(((uint8_t)(x)) << USB_ERREN_CRC5EOFEN_SHIFT)) & USB_ERREN_CRC5EOFEN_MASK) + +#define USB_ERREN_CRC16EN_MASK (0x4U) +#define USB_ERREN_CRC16EN_SHIFT (2U) +/*! CRC16EN - CRC16 Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define USB_ERREN_CRC16EN(x) (((uint8_t)(((uint8_t)(x)) << USB_ERREN_CRC16EN_SHIFT)) & USB_ERREN_CRC16EN_MASK) + +#define USB_ERREN_DFN8EN_MASK (0x8U) +#define USB_ERREN_DFN8EN_SHIFT (3U) +/*! DFN8EN - DFN8 (Data Field Not Integer Number of Bytes) Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define USB_ERREN_DFN8EN(x) (((uint8_t)(((uint8_t)(x)) << USB_ERREN_DFN8EN_SHIFT)) & USB_ERREN_DFN8EN_MASK) + +#define USB_ERREN_BTOERREN_MASK (0x10U) +#define USB_ERREN_BTOERREN_SHIFT (4U) +/*! BTOERREN - BTOERR (Bus Timeout Error) Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define USB_ERREN_BTOERREN(x) (((uint8_t)(((uint8_t)(x)) << USB_ERREN_BTOERREN_SHIFT)) & USB_ERREN_BTOERREN_MASK) + +#define USB_ERREN_DMAERREN_MASK (0x20U) +#define USB_ERREN_DMAERREN_SHIFT (5U) +/*! DMAERREN - DMAERR Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define USB_ERREN_DMAERREN(x) (((uint8_t)(((uint8_t)(x)) << USB_ERREN_DMAERREN_SHIFT)) & USB_ERREN_DMAERREN_MASK) + +#define USB_ERREN_OWNERREN_MASK (0x40U) +#define USB_ERREN_OWNERREN_SHIFT (6U) +/*! OWNERREN - OWNERR Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define USB_ERREN_OWNERREN(x) (((uint8_t)(((uint8_t)(x)) << USB_ERREN_OWNERREN_SHIFT)) & USB_ERREN_OWNERREN_MASK) + +#define USB_ERREN_BTSERREN_MASK (0x80U) +#define USB_ERREN_BTSERREN_SHIFT (7U) +/*! BTSERREN - BTSERR (Bit Stuff Error) Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define USB_ERREN_BTSERREN(x) (((uint8_t)(((uint8_t)(x)) << USB_ERREN_BTSERREN_SHIFT)) & USB_ERREN_BTSERREN_MASK) +/*! @} */ + +/*! @name STAT - Status */ +/*! @{ */ + +#define USB_STAT_ODD_MASK (0x4U) +#define USB_STAT_ODD_SHIFT (2U) +/*! ODD - Odd Bank + * 0b0..Not in the odd bank + * 0b1..In the odd bank + */ +#define USB_STAT_ODD(x) (((uint8_t)(((uint8_t)(x)) << USB_STAT_ODD_SHIFT)) & USB_STAT_ODD_MASK) + +#define USB_STAT_TX_MASK (0x8U) +#define USB_STAT_TX_SHIFT (3U) +/*! TX - Transmit Indicator + * 0b0..Receive + * 0b1..Transmit + */ +#define USB_STAT_TX(x) (((uint8_t)(((uint8_t)(x)) << USB_STAT_TX_SHIFT)) & USB_STAT_TX_MASK) + +#define USB_STAT_ENDP_MASK (0xF0U) +#define USB_STAT_ENDP_SHIFT (4U) +/*! ENDP - Endpoint address */ +#define USB_STAT_ENDP(x) (((uint8_t)(((uint8_t)(x)) << USB_STAT_ENDP_SHIFT)) & USB_STAT_ENDP_MASK) +/*! @} */ + +/*! @name CTL - Control */ +/*! @{ */ + +#define USB_CTL_USBENSOFEN_MASK (0x1U) +#define USB_CTL_USBENSOFEN_SHIFT (0U) +/*! USBENSOFEN - USB Enable + * 0b0..Disable + * 0b1..Enable + */ +#define USB_CTL_USBENSOFEN(x) (((uint8_t)(((uint8_t)(x)) << USB_CTL_USBENSOFEN_SHIFT)) & USB_CTL_USBENSOFEN_MASK) + +#define USB_CTL_ODDRST_MASK (0x2U) +#define USB_CTL_ODDRST_SHIFT (1U) +/*! ODDRST - Odd Reset */ +#define USB_CTL_ODDRST(x) (((uint8_t)(((uint8_t)(x)) << USB_CTL_ODDRST_SHIFT)) & USB_CTL_ODDRST_MASK) + +#define USB_CTL_RESUME_MASK (0x4U) +#define USB_CTL_RESUME_SHIFT (2U) +/*! RESUME - Resume */ +#define USB_CTL_RESUME(x) (((uint8_t)(((uint8_t)(x)) << USB_CTL_RESUME_SHIFT)) & USB_CTL_RESUME_MASK) + +#define USB_CTL_HOSTMODEEN_MASK (0x8U) +#define USB_CTL_HOSTMODEEN_SHIFT (3U) +/*! HOSTMODEEN - Host Mode Enable + * 0b0..USBFS operates in Device mode. + * 0b1..USBFS operates in Host mode. In Host mode, USBFS performs USB transactions under the programmed control of the host processor. + */ +#define USB_CTL_HOSTMODEEN(x) (((uint8_t)(((uint8_t)(x)) << USB_CTL_HOSTMODEEN_SHIFT)) & USB_CTL_HOSTMODEEN_MASK) + +#define USB_CTL_RESET_MASK (0x10U) +#define USB_CTL_RESET_SHIFT (4U) +/*! RESET - Reset Signaling Enable + * 0b0..Disable + * 0b1..Enable + */ +#define USB_CTL_RESET(x) (((uint8_t)(((uint8_t)(x)) << USB_CTL_RESET_SHIFT)) & USB_CTL_RESET_MASK) + +#define USB_CTL_TXSUSPENDTOKENBUSY_MASK (0x20U) +#define USB_CTL_TXSUSPENDTOKENBUSY_SHIFT (5U) +/*! TXSUSPENDTOKENBUSY - TXD Suspend And Token Busy */ +#define USB_CTL_TXSUSPENDTOKENBUSY(x) (((uint8_t)(((uint8_t)(x)) << USB_CTL_TXSUSPENDTOKENBUSY_SHIFT)) & USB_CTL_TXSUSPENDTOKENBUSY_MASK) + +#define USB_CTL_SE0_MASK (0x40U) +#define USB_CTL_SE0_SHIFT (6U) +/*! SE0 - Live USB Single-Ended Zero signal */ +#define USB_CTL_SE0(x) (((uint8_t)(((uint8_t)(x)) << USB_CTL_SE0_SHIFT)) & USB_CTL_SE0_MASK) + +#define USB_CTL_JSTATE_MASK (0x80U) +#define USB_CTL_JSTATE_SHIFT (7U) +/*! JSTATE - Live USB Differential Receiver JSTATE Signal */ +#define USB_CTL_JSTATE(x) (((uint8_t)(((uint8_t)(x)) << USB_CTL_JSTATE_SHIFT)) & USB_CTL_JSTATE_MASK) +/*! @} */ + +/*! @name ADDR - Address */ +/*! @{ */ + +#define USB_ADDR_ADDR_MASK (0x7FU) +#define USB_ADDR_ADDR_SHIFT (0U) +/*! ADDR - USB Address */ +#define USB_ADDR_ADDR(x) (((uint8_t)(((uint8_t)(x)) << USB_ADDR_ADDR_SHIFT)) & USB_ADDR_ADDR_MASK) + +#define USB_ADDR_LSEN_MASK (0x80U) +#define USB_ADDR_LSEN_SHIFT (7U) +/*! LSEN - Low Speed Enable */ +#define USB_ADDR_LSEN(x) (((uint8_t)(((uint8_t)(x)) << USB_ADDR_LSEN_SHIFT)) & USB_ADDR_LSEN_MASK) +/*! @} */ + +/*! @name BDTPAGE1 - BDT Page 1 */ +/*! @{ */ + +#define USB_BDTPAGE1_BDTBA_MASK (0xFEU) +#define USB_BDTPAGE1_BDTBA_SHIFT (1U) +/*! BDTBA - BDT Base Address */ +#define USB_BDTPAGE1_BDTBA(x) (((uint8_t)(((uint8_t)(x)) << USB_BDTPAGE1_BDTBA_SHIFT)) & USB_BDTPAGE1_BDTBA_MASK) +/*! @} */ + +/*! @name FRMNUML - Frame Number Register Low */ +/*! @{ */ + +#define USB_FRMNUML_FRM_MASK (0xFFU) +#define USB_FRMNUML_FRM_SHIFT (0U) +/*! FRM - Frame Number, Bits 0-7 */ +#define USB_FRMNUML_FRM(x) (((uint8_t)(((uint8_t)(x)) << USB_FRMNUML_FRM_SHIFT)) & USB_FRMNUML_FRM_MASK) +/*! @} */ + +/*! @name FRMNUMH - Frame Number Register High */ +/*! @{ */ + +#define USB_FRMNUMH_FRM_MASK (0x7U) +#define USB_FRMNUMH_FRM_SHIFT (0U) +/*! FRM - Frame Number, Bits 8-10 */ +#define USB_FRMNUMH_FRM(x) (((uint8_t)(((uint8_t)(x)) << USB_FRMNUMH_FRM_SHIFT)) & USB_FRMNUMH_FRM_MASK) +/*! @} */ + +/*! @name TOKEN - Token */ +/*! @{ */ + +#define USB_TOKEN_TOKENENDPT_MASK (0xFU) +#define USB_TOKEN_TOKENENDPT_SHIFT (0U) +/*! TOKENENDPT - Token Endpoint Address */ +#define USB_TOKEN_TOKENENDPT(x) (((uint8_t)(((uint8_t)(x)) << USB_TOKEN_TOKENENDPT_SHIFT)) & USB_TOKEN_TOKENENDPT_MASK) + +#define USB_TOKEN_TOKENPID_MASK (0xF0U) +#define USB_TOKEN_TOKENPID_SHIFT (4U) +/*! TOKENPID - Token Type + * 0b0001..OUT token. USBFS performs an OUT (TX) transaction. + * 0b1001..IN token. USBFS performs an IN (RX) transaction. + * 0b1101..SETUP token. USBFS performs a SETUP (TX) transaction + */ +#define USB_TOKEN_TOKENPID(x) (((uint8_t)(((uint8_t)(x)) << USB_TOKEN_TOKENPID_SHIFT)) & USB_TOKEN_TOKENPID_MASK) +/*! @} */ + +/*! @name SOFTHLD - SOF Threshold */ +/*! @{ */ + +#define USB_SOFTHLD_CNT_MASK (0xFFU) +#define USB_SOFTHLD_CNT_SHIFT (0U) +/*! CNT - SOF Count Threshold */ +#define USB_SOFTHLD_CNT(x) (((uint8_t)(((uint8_t)(x)) << USB_SOFTHLD_CNT_SHIFT)) & USB_SOFTHLD_CNT_MASK) +/*! @} */ + +/*! @name BDTPAGE2 - BDT Page 2 */ +/*! @{ */ + +#define USB_BDTPAGE2_BDTBA_MASK (0xFFU) +#define USB_BDTPAGE2_BDTBA_SHIFT (0U) +/*! BDTBA - BDT Base Address */ +#define USB_BDTPAGE2_BDTBA(x) (((uint8_t)(((uint8_t)(x)) << USB_BDTPAGE2_BDTBA_SHIFT)) & USB_BDTPAGE2_BDTBA_MASK) +/*! @} */ + +/*! @name BDTPAGE3 - BDT Page 3 */ +/*! @{ */ + +#define USB_BDTPAGE3_BDTBA_MASK (0xFFU) +#define USB_BDTPAGE3_BDTBA_SHIFT (0U) +/*! BDTBA - BDT Base Address */ +#define USB_BDTPAGE3_BDTBA(x) (((uint8_t)(((uint8_t)(x)) << USB_BDTPAGE3_BDTBA_SHIFT)) & USB_BDTPAGE3_BDTBA_MASK) +/*! @} */ + +/*! @name ENDPT - Endpoint Control */ +/*! @{ */ + +#define USB_ENDPT_EPHSHK_MASK (0x1U) +#define USB_ENDPT_EPHSHK_SHIFT (0U) +/*! EPHSHK - Endpoint Handshaking Enable */ +#define USB_ENDPT_EPHSHK(x) (((uint8_t)(((uint8_t)(x)) << USB_ENDPT_EPHSHK_SHIFT)) & USB_ENDPT_EPHSHK_MASK) + +#define USB_ENDPT_EPSTALL_MASK (0x2U) +#define USB_ENDPT_EPSTALL_SHIFT (1U) +/*! EPSTALL - Endpoint Stalled */ +#define USB_ENDPT_EPSTALL(x) (((uint8_t)(((uint8_t)(x)) << USB_ENDPT_EPSTALL_SHIFT)) & USB_ENDPT_EPSTALL_MASK) + +#define USB_ENDPT_EPTXEN_MASK (0x4U) +#define USB_ENDPT_EPTXEN_SHIFT (2U) +/*! EPTXEN - Endpoint for TX transfers enable */ +#define USB_ENDPT_EPTXEN(x) (((uint8_t)(((uint8_t)(x)) << USB_ENDPT_EPTXEN_SHIFT)) & USB_ENDPT_EPTXEN_MASK) + +#define USB_ENDPT_EPRXEN_MASK (0x8U) +#define USB_ENDPT_EPRXEN_SHIFT (3U) +/*! EPRXEN - Endpoint for RX transfers enable */ +#define USB_ENDPT_EPRXEN(x) (((uint8_t)(((uint8_t)(x)) << USB_ENDPT_EPRXEN_SHIFT)) & USB_ENDPT_EPRXEN_MASK) + +#define USB_ENDPT_EPCTLDIS_MASK (0x10U) +#define USB_ENDPT_EPCTLDIS_SHIFT (4U) +/*! EPCTLDIS - Control Transfer Disable + * 0b0..Enable + * 0b1..Disable + */ +#define USB_ENDPT_EPCTLDIS(x) (((uint8_t)(((uint8_t)(x)) << USB_ENDPT_EPCTLDIS_SHIFT)) & USB_ENDPT_EPCTLDIS_MASK) + +#define USB_ENDPT_RETRYDIS_MASK (0x40U) +#define USB_ENDPT_RETRYDIS_SHIFT (6U) +/*! RETRYDIS - Retry Disable + * 0b0..Retried NAK'ed transactions in hardware. + * 0b1..Do not retry NAK'ed transactions. When a transaction is NAK'ed, the BDT PID field is updated with the NAK + * PID, and the TOKEN_DNE interrupt becomes 1. + */ +#define USB_ENDPT_RETRYDIS(x) (((uint8_t)(((uint8_t)(x)) << USB_ENDPT_RETRYDIS_SHIFT)) & USB_ENDPT_RETRYDIS_MASK) + +#define USB_ENDPT_HOSTWOHUB_MASK (0x80U) +#define USB_ENDPT_HOSTWOHUB_SHIFT (7U) +/*! HOSTWOHUB - Host Without A Hub + * 0b0..Connected using a hub (USBFS generates PRE_PID as required) + * 0b1..Connected directly to host without a hub, or was used to attach + */ +#define USB_ENDPT_HOSTWOHUB(x) (((uint8_t)(((uint8_t)(x)) << USB_ENDPT_HOSTWOHUB_SHIFT)) & USB_ENDPT_HOSTWOHUB_MASK) +/*! @} */ + +/* The count of USB_ENDPT */ +#define USB_ENDPT_COUNT (16U) + +/*! @name USBCTRL - USB Control */ +/*! @{ */ + +#define USB_USBCTRL_DPDM_LANE_REVERSE_MASK (0x4U) +#define USB_USBCTRL_DPDM_LANE_REVERSE_SHIFT (2U) +/*! DPDM_LANE_REVERSE - DP and DM Lane Reversal Control + * 0b0..Standard USB DP and DM package pin assignment + * 0b1..Reverse roles of USB DP and DM package pins + */ +#define USB_USBCTRL_DPDM_LANE_REVERSE(x) (((uint8_t)(((uint8_t)(x)) << USB_USBCTRL_DPDM_LANE_REVERSE_SHIFT)) & USB_USBCTRL_DPDM_LANE_REVERSE_MASK) + +#define USB_USBCTRL_HOST_LS_EOP_MASK (0x8U) +#define USB_USBCTRL_HOST_LS_EOP_SHIFT (3U) +/*! HOST_LS_EOP - Host-Mode-Only Low-Speed Device EOP Signaling + * 0b0..Full-speed device or a low-speed device through a hub + * 0b1..Directly-connected low-speed device + */ +#define USB_USBCTRL_HOST_LS_EOP(x) (((uint8_t)(((uint8_t)(x)) << USB_USBCTRL_HOST_LS_EOP_SHIFT)) & USB_USBCTRL_HOST_LS_EOP_MASK) + +#define USB_USBCTRL_UARTSEL_MASK (0x10U) +#define USB_USBCTRL_UARTSEL_SHIFT (4U) +/*! UARTSEL - UART Select + * 0b0..USB DP and DM external package pins are used for USB signaling. + * 0b1..USB DP and DM external package pins are used for UART signaling. + */ +#define USB_USBCTRL_UARTSEL(x) (((uint8_t)(((uint8_t)(x)) << USB_USBCTRL_UARTSEL_SHIFT)) & USB_USBCTRL_UARTSEL_MASK) + +#define USB_USBCTRL_UARTCHLS_MASK (0x20U) +#define USB_USBCTRL_UARTCHLS_SHIFT (5U) +/*! UARTCHLS - UART Signal Channel Select + * 0b0..USB DP and DM signals are used as UART TX/RX. + * 0b1..USB DP and DM signals are used as UART RX/TX. + */ +#define USB_USBCTRL_UARTCHLS(x) (((uint8_t)(((uint8_t)(x)) << USB_USBCTRL_UARTCHLS_SHIFT)) & USB_USBCTRL_UARTCHLS_MASK) + +#define USB_USBCTRL_PDE_MASK (0x40U) +#define USB_USBCTRL_PDE_SHIFT (6U) +/*! PDE - Pulldown Enable + * 0b0..Disable on D+ and D- + * 0b1..Enable on D+ and D- + */ +#define USB_USBCTRL_PDE(x) (((uint8_t)(((uint8_t)(x)) << USB_USBCTRL_PDE_SHIFT)) & USB_USBCTRL_PDE_MASK) + +#define USB_USBCTRL_SUSP_MASK (0x80U) +#define USB_USBCTRL_SUSP_SHIFT (7U) +/*! SUSP - Suspend + * 0b0..Not in Suspend state + * 0b1..In Suspend state + */ +#define USB_USBCTRL_SUSP(x) (((uint8_t)(((uint8_t)(x)) << USB_USBCTRL_SUSP_SHIFT)) & USB_USBCTRL_SUSP_MASK) +/*! @} */ + +/*! @name OBSERVE - USB OTG Observe */ +/*! @{ */ + +#define USB_OBSERVE_DMPD_MASK (0x10U) +#define USB_OBSERVE_DMPD_SHIFT (4U) +/*! DMPD - D- Pulldown + * 0b0..Disabled + * 0b1..Enabled + */ +#define USB_OBSERVE_DMPD(x) (((uint8_t)(((uint8_t)(x)) << USB_OBSERVE_DMPD_SHIFT)) & USB_OBSERVE_DMPD_MASK) + +#define USB_OBSERVE_DPPD_MASK (0x40U) +#define USB_OBSERVE_DPPD_SHIFT (6U) +/*! DPPD - D+ Pulldown + * 0b0..Disabled + * 0b1..Enabled + */ +#define USB_OBSERVE_DPPD(x) (((uint8_t)(((uint8_t)(x)) << USB_OBSERVE_DPPD_SHIFT)) & USB_OBSERVE_DPPD_MASK) + +#define USB_OBSERVE_DPPU_MASK (0x80U) +#define USB_OBSERVE_DPPU_SHIFT (7U) +/*! DPPU - D+ Pullup + * 0b0..Disabled + * 0b1..Enabled + */ +#define USB_OBSERVE_DPPU(x) (((uint8_t)(((uint8_t)(x)) << USB_OBSERVE_DPPU_SHIFT)) & USB_OBSERVE_DPPU_MASK) +/*! @} */ + +/*! @name CONTROL - USB OTG Control */ +/*! @{ */ + +#define USB_CONTROL_VBUS_SOURCE_SEL_MASK (0x1U) +#define USB_CONTROL_VBUS_SOURCE_SEL_SHIFT (0U) +/*! VBUS_SOURCE_SEL - VBUS Monitoring Source Select + * 0b0..Reserved + * 0b1..Resistive divider attached to a GPIO pin + */ +#define USB_CONTROL_VBUS_SOURCE_SEL(x) (((uint8_t)(((uint8_t)(x)) << USB_CONTROL_VBUS_SOURCE_SEL_SHIFT)) & USB_CONTROL_VBUS_SOURCE_SEL_MASK) + +#define USB_CONTROL_SESS_VLD_MASK (0x2U) +#define USB_CONTROL_SESS_VLD_SHIFT (1U) +/*! SESS_VLD - VBUS Session Valid status + * 0b1..Above + * 0b0..Below + */ +#define USB_CONTROL_SESS_VLD(x) (((uint8_t)(((uint8_t)(x)) << USB_CONTROL_SESS_VLD_SHIFT)) & USB_CONTROL_SESS_VLD_MASK) + +#define USB_CONTROL_DPPULLUPNONOTG_MASK (0x10U) +#define USB_CONTROL_DPPULLUPNONOTG_SHIFT (4U) +/*! DPPULLUPNONOTG - DP Pullup in Non-OTG Device Mode + * 0b0..Disable + * 0b1..Enabled + */ +#define USB_CONTROL_DPPULLUPNONOTG(x) (((uint8_t)(((uint8_t)(x)) << USB_CONTROL_DPPULLUPNONOTG_SHIFT)) & USB_CONTROL_DPPULLUPNONOTG_MASK) +/*! @} */ + +/*! @name USBTRC0 - USB Transceiver Control 0 */ +/*! @{ */ + +#define USB_USBTRC0_USB_RESUME_INT_MASK (0x1U) +#define USB_USBTRC0_USB_RESUME_INT_SHIFT (0U) +/*! USB_RESUME_INT - USB Asynchronous Interrupt + * 0b0..Not generated + * 0b1..Generated because of the USB asynchronous interrupt + */ +#define USB_USBTRC0_USB_RESUME_INT(x) (((uint8_t)(((uint8_t)(x)) << USB_USBTRC0_USB_RESUME_INT_SHIFT)) & USB_USBTRC0_USB_RESUME_INT_MASK) + +#define USB_USBTRC0_SYNC_DET_MASK (0x2U) +#define USB_USBTRC0_SYNC_DET_SHIFT (1U) +/*! SYNC_DET - Synchronous USB Interrupt Detect + * 0b0..Not detected + * 0b1..Detected + */ +#define USB_USBTRC0_SYNC_DET(x) (((uint8_t)(((uint8_t)(x)) << USB_USBTRC0_SYNC_DET_SHIFT)) & USB_USBTRC0_SYNC_DET_MASK) + +#define USB_USBTRC0_USB_CLK_RECOVERY_INT_MASK (0x4U) +#define USB_USBTRC0_USB_CLK_RECOVERY_INT_SHIFT (2U) +/*! USB_CLK_RECOVERY_INT - Combined USB Clock Recovery interrupt status */ +#define USB_USBTRC0_USB_CLK_RECOVERY_INT(x) (((uint8_t)(((uint8_t)(x)) << USB_USBTRC0_USB_CLK_RECOVERY_INT_SHIFT)) & USB_USBTRC0_USB_CLK_RECOVERY_INT_MASK) + +#define USB_USBTRC0_VREDG_DET_MASK (0x8U) +#define USB_USBTRC0_VREDG_DET_SHIFT (3U) +/*! VREDG_DET - VREGIN Rising Edge Interrupt Detect + * 0b0..Not detected + * 0b1..Detected + */ +#define USB_USBTRC0_VREDG_DET(x) (((uint8_t)(((uint8_t)(x)) << USB_USBTRC0_VREDG_DET_SHIFT)) & USB_USBTRC0_VREDG_DET_MASK) + +#define USB_USBTRC0_VFEDG_DET_MASK (0x10U) +#define USB_USBTRC0_VFEDG_DET_SHIFT (4U) +/*! VFEDG_DET - VREGIN Falling Edge Interrupt Detect + * 0b0..Not detected + * 0b1..Detected + */ +#define USB_USBTRC0_VFEDG_DET(x) (((uint8_t)(((uint8_t)(x)) << USB_USBTRC0_VFEDG_DET_SHIFT)) & USB_USBTRC0_VFEDG_DET_MASK) + +#define USB_USBTRC0_USBRESMEN_MASK (0x20U) +#define USB_USBTRC0_USBRESMEN_SHIFT (5U) +/*! USBRESMEN - Asynchronous Resume Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define USB_USBTRC0_USBRESMEN(x) (((uint8_t)(((uint8_t)(x)) << USB_USBTRC0_USBRESMEN_SHIFT)) & USB_USBTRC0_USBRESMEN_MASK) + +#define USB_USBTRC0_VREGIN_STS_MASK (0x40U) +#define USB_USBTRC0_VREGIN_STS_SHIFT (6U) +/*! VREGIN_STS - VREGIN Status */ +#define USB_USBTRC0_VREGIN_STS(x) (((uint8_t)(((uint8_t)(x)) << USB_USBTRC0_VREGIN_STS_SHIFT)) & USB_USBTRC0_VREGIN_STS_MASK) + +#define USB_USBTRC0_USBRESET_MASK (0x80U) +#define USB_USBTRC0_USBRESET_SHIFT (7U) +/*! USBRESET - USB Reset + * 0b0..Normal USBFS operation + * 0b1..Returns USBFS to its reset state + */ +#define USB_USBTRC0_USBRESET(x) (((uint8_t)(((uint8_t)(x)) << USB_USBTRC0_USBRESET_SHIFT)) & USB_USBTRC0_USBRESET_MASK) +/*! @} */ + +/*! @name USBFRMADJUST - Frame Adjust */ +/*! @{ */ + +#define USB_USBFRMADJUST_ADJ_MASK (0xFFU) +#define USB_USBFRMADJUST_ADJ_SHIFT (0U) +/*! ADJ - Frame Adjustment */ +#define USB_USBFRMADJUST_ADJ(x) (((uint8_t)(((uint8_t)(x)) << USB_USBFRMADJUST_ADJ_SHIFT)) & USB_USBFRMADJUST_ADJ_MASK) +/*! @} */ + +/*! @name KEEP_ALIVE_CTRL - Keep Alive Mode Control */ +/*! @{ */ + +#define USB_KEEP_ALIVE_CTRL_KEEP_ALIVE_EN_MASK (0x1U) +#define USB_KEEP_ALIVE_CTRL_KEEP_ALIVE_EN_SHIFT (0U) +/*! KEEP_ALIVE_EN - Keep Alive Mode Enable + * 0b0..Everything remains same as before. + * 0b1..USB shall enter USB_KEEP_ALIVE mode after asserting ipg_stop. + */ +#define USB_KEEP_ALIVE_CTRL_KEEP_ALIVE_EN(x) (((uint8_t)(((uint8_t)(x)) << USB_KEEP_ALIVE_CTRL_KEEP_ALIVE_EN_SHIFT)) & USB_KEEP_ALIVE_CTRL_KEEP_ALIVE_EN_MASK) + +#define USB_KEEP_ALIVE_CTRL_OWN_OVERRD_EN_MASK (0x2U) +#define USB_KEEP_ALIVE_CTRL_OWN_OVERRD_EN_SHIFT (1U) +/*! OWN_OVERRD_EN - OWN Bit Override Enable */ +#define USB_KEEP_ALIVE_CTRL_OWN_OVERRD_EN(x) (((uint8_t)(((uint8_t)(x)) << USB_KEEP_ALIVE_CTRL_OWN_OVERRD_EN_SHIFT)) & USB_KEEP_ALIVE_CTRL_OWN_OVERRD_EN_MASK) + +#define USB_KEEP_ALIVE_CTRL_STOP_ACK_DLY_EN_MASK (0x4U) +#define USB_KEEP_ALIVE_CTRL_STOP_ACK_DLY_EN_SHIFT (2U) +/*! STOP_ACK_DLY_EN - Stop Acknowledge Delay Enable + * 0b0..Enter KEEP_ALIVE mode immediately when there is no USB AHB transfer. + * 0b1..Enter KEEP_ALIVE mode until the USB core is idle and there is no USB AHB transfer. + */ +#define USB_KEEP_ALIVE_CTRL_STOP_ACK_DLY_EN(x) (((uint8_t)(((uint8_t)(x)) << USB_KEEP_ALIVE_CTRL_STOP_ACK_DLY_EN_SHIFT)) & USB_KEEP_ALIVE_CTRL_STOP_ACK_DLY_EN_MASK) + +#define USB_KEEP_ALIVE_CTRL_WAKE_REQ_EN_MASK (0x8U) +#define USB_KEEP_ALIVE_CTRL_WAKE_REQ_EN_SHIFT (3U) +/*! WAKE_REQ_EN - Wakeup Request Enable + * 0b0..Disable + * 0b1..Enable + */ +#define USB_KEEP_ALIVE_CTRL_WAKE_REQ_EN(x) (((uint8_t)(((uint8_t)(x)) << USB_KEEP_ALIVE_CTRL_WAKE_REQ_EN_SHIFT)) & USB_KEEP_ALIVE_CTRL_WAKE_REQ_EN_MASK) + +#define USB_KEEP_ALIVE_CTRL_WAKE_INT_EN_MASK (0x10U) +#define USB_KEEP_ALIVE_CTRL_WAKE_INT_EN_SHIFT (4U) +/*! WAKE_INT_EN - Wakeup Interrupt Enable */ +#define USB_KEEP_ALIVE_CTRL_WAKE_INT_EN(x) (((uint8_t)(((uint8_t)(x)) << USB_KEEP_ALIVE_CTRL_WAKE_INT_EN_SHIFT)) & USB_KEEP_ALIVE_CTRL_WAKE_INT_EN_MASK) + +#define USB_KEEP_ALIVE_CTRL_KEEP_ALIVE_STS_MASK (0x40U) +#define USB_KEEP_ALIVE_CTRL_KEEP_ALIVE_STS_SHIFT (6U) +/*! KEEP_ALIVE_STS - Keep Alive Status + * 0b0..Not in Keep Alive mode + * 0b1..In Keep Alive mode + */ +#define USB_KEEP_ALIVE_CTRL_KEEP_ALIVE_STS(x) (((uint8_t)(((uint8_t)(x)) << USB_KEEP_ALIVE_CTRL_KEEP_ALIVE_STS_SHIFT)) & USB_KEEP_ALIVE_CTRL_KEEP_ALIVE_STS_MASK) + +#define USB_KEEP_ALIVE_CTRL_WAKE_INT_STS_MASK (0x80U) +#define USB_KEEP_ALIVE_CTRL_WAKE_INT_STS_SHIFT (7U) +/*! WAKE_INT_STS - Wakeup Interrupt Status Flag + * 0b0..Interrupt did not occur + * 0b1..Interrupt occurred + * 0b0..No effect + * 0b1..Clear the flag + */ +#define USB_KEEP_ALIVE_CTRL_WAKE_INT_STS(x) (((uint8_t)(((uint8_t)(x)) << USB_KEEP_ALIVE_CTRL_WAKE_INT_STS_SHIFT)) & USB_KEEP_ALIVE_CTRL_WAKE_INT_STS_MASK) +/*! @} */ + +/*! @name KEEP_ALIVE_WKCTRL - Keep Alive Mode Wakeup Control */ +/*! @{ */ + +#define USB_KEEP_ALIVE_WKCTRL_WAKE_ON_THIS_MASK (0xFU) +#define USB_KEEP_ALIVE_WKCTRL_WAKE_ON_THIS_SHIFT (0U) +/*! WAKE_ON_THIS - Token PID for the wakeup request + * 0b0001..Wake up after receiving OUT or SETUP token packet. + * 0b1101..Wake up after receiving SETUP token packet. All other values are reserved. + */ +#define USB_KEEP_ALIVE_WKCTRL_WAKE_ON_THIS(x) (((uint8_t)(((uint8_t)(x)) << USB_KEEP_ALIVE_WKCTRL_WAKE_ON_THIS_SHIFT)) & USB_KEEP_ALIVE_WKCTRL_WAKE_ON_THIS_MASK) + +#define USB_KEEP_ALIVE_WKCTRL_WAKE_ENDPT_MASK (0xF0U) +#define USB_KEEP_ALIVE_WKCTRL_WAKE_ENDPT_SHIFT (4U) +/*! WAKE_ENDPT - Endpoint address for the wakeup request */ +#define USB_KEEP_ALIVE_WKCTRL_WAKE_ENDPT(x) (((uint8_t)(((uint8_t)(x)) << USB_KEEP_ALIVE_WKCTRL_WAKE_ENDPT_SHIFT)) & USB_KEEP_ALIVE_WKCTRL_WAKE_ENDPT_MASK) +/*! @} */ + +/*! @name MISCCTRL - Miscellaneous Control */ +/*! @{ */ + +#define USB_MISCCTRL_SOFDYNTHLD_MASK (0x1U) +#define USB_MISCCTRL_SOFDYNTHLD_SHIFT (0U) +/*! SOFDYNTHLD - Dynamic SOF Threshold Compare mode + * 0b0..When the byte-times SOF threshold is reached + * 0b1..When 8 byte-times SOF threshold is reached or overstepped + */ +#define USB_MISCCTRL_SOFDYNTHLD(x) (((uint8_t)(((uint8_t)(x)) << USB_MISCCTRL_SOFDYNTHLD_SHIFT)) & USB_MISCCTRL_SOFDYNTHLD_MASK) + +#define USB_MISCCTRL_SOFBUSSET_MASK (0x2U) +#define USB_MISCCTRL_SOFBUSSET_SHIFT (1U) +/*! SOFBUSSET - SOF_TOK Interrupt Generation Mode Select + * 0b0..According to the SOF threshold value + * 0b1..When the SOF counter reaches 0 + */ +#define USB_MISCCTRL_SOFBUSSET(x) (((uint8_t)(((uint8_t)(x)) << USB_MISCCTRL_SOFBUSSET_SHIFT)) & USB_MISCCTRL_SOFBUSSET_MASK) + +#define USB_MISCCTRL_OWNERRISODIS_MASK (0x4U) +#define USB_MISCCTRL_OWNERRISODIS_SHIFT (2U) +/*! OWNERRISODIS - OWN Error Detect for ISO IN and ISO OUT Disable + * 0b0..Enable + * 0b1..Disable + */ +#define USB_MISCCTRL_OWNERRISODIS(x) (((uint8_t)(((uint8_t)(x)) << USB_MISCCTRL_OWNERRISODIS_SHIFT)) & USB_MISCCTRL_OWNERRISODIS_MASK) + +#define USB_MISCCTRL_VREDG_EN_MASK (0x8U) +#define USB_MISCCTRL_VREDG_EN_SHIFT (3U) +/*! VREDG_EN - VREGIN Rising Edge Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define USB_MISCCTRL_VREDG_EN(x) (((uint8_t)(((uint8_t)(x)) << USB_MISCCTRL_VREDG_EN_SHIFT)) & USB_MISCCTRL_VREDG_EN_MASK) + +#define USB_MISCCTRL_VFEDG_EN_MASK (0x10U) +#define USB_MISCCTRL_VFEDG_EN_SHIFT (4U) +/*! VFEDG_EN - VREGIN Falling Edge Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define USB_MISCCTRL_VFEDG_EN(x) (((uint8_t)(((uint8_t)(x)) << USB_MISCCTRL_VFEDG_EN_SHIFT)) & USB_MISCCTRL_VFEDG_EN_MASK) + +#define USB_MISCCTRL_STL_ADJ_EN_MASK (0x80U) +#define USB_MISCCTRL_STL_ADJ_EN_SHIFT (7U) +/*! STL_ADJ_EN - USB Peripheral Mode Stall Adjust Enable + * 0b0..If ENDPTn[END_STALL] = 1, both IN and OUT directions for the associated endpoint stalls. + * 0b1..If ENDPTn[END_STALL] = 1, the STALL_xx_DIS registers control which directions for the associated endpoint stalls. + */ +#define USB_MISCCTRL_STL_ADJ_EN(x) (((uint8_t)(((uint8_t)(x)) << USB_MISCCTRL_STL_ADJ_EN_SHIFT)) & USB_MISCCTRL_STL_ADJ_EN_MASK) +/*! @} */ + +/*! @name STALL_IL_DIS - Peripheral Mode Stall Disable for Endpoints 7 to 0 in IN Direction */ +/*! @{ */ + +#define USB_STALL_IL_DIS_STALL_I_DIS0_MASK (0x1U) +#define USB_STALL_IL_DIS_STALL_I_DIS0_SHIFT (0U) +/*! STALL_I_DIS0 - Disable Endpoint 0 IN Direction + * 0b0..Enable + * 0b1..Disable + */ +#define USB_STALL_IL_DIS_STALL_I_DIS0(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_IL_DIS_STALL_I_DIS0_SHIFT)) & USB_STALL_IL_DIS_STALL_I_DIS0_MASK) + +#define USB_STALL_IL_DIS_STALL_I_DIS1_MASK (0x2U) +#define USB_STALL_IL_DIS_STALL_I_DIS1_SHIFT (1U) +/*! STALL_I_DIS1 - Disable Endpoint 1 IN Direction + * 0b0..Enable + * 0b1..Disable + */ +#define USB_STALL_IL_DIS_STALL_I_DIS1(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_IL_DIS_STALL_I_DIS1_SHIFT)) & USB_STALL_IL_DIS_STALL_I_DIS1_MASK) + +#define USB_STALL_IL_DIS_STALL_I_DIS2_MASK (0x4U) +#define USB_STALL_IL_DIS_STALL_I_DIS2_SHIFT (2U) +/*! STALL_I_DIS2 - Disable Endpoint 2 IN Direction + * 0b0..Enable + * 0b1..Disable + */ +#define USB_STALL_IL_DIS_STALL_I_DIS2(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_IL_DIS_STALL_I_DIS2_SHIFT)) & USB_STALL_IL_DIS_STALL_I_DIS2_MASK) + +#define USB_STALL_IL_DIS_STALL_I_DIS3_MASK (0x8U) +#define USB_STALL_IL_DIS_STALL_I_DIS3_SHIFT (3U) +/*! STALL_I_DIS3 - Disable Endpoint 3 IN Direction + * 0b0..Enable + * 0b1..Disable + */ +#define USB_STALL_IL_DIS_STALL_I_DIS3(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_IL_DIS_STALL_I_DIS3_SHIFT)) & USB_STALL_IL_DIS_STALL_I_DIS3_MASK) + +#define USB_STALL_IL_DIS_STALL_I_DIS4_MASK (0x10U) +#define USB_STALL_IL_DIS_STALL_I_DIS4_SHIFT (4U) +/*! STALL_I_DIS4 - Disable Endpoint 4 IN Direction + * 0b0..Enable + * 0b1..Disable + */ +#define USB_STALL_IL_DIS_STALL_I_DIS4(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_IL_DIS_STALL_I_DIS4_SHIFT)) & USB_STALL_IL_DIS_STALL_I_DIS4_MASK) + +#define USB_STALL_IL_DIS_STALL_I_DIS5_MASK (0x20U) +#define USB_STALL_IL_DIS_STALL_I_DIS5_SHIFT (5U) +/*! STALL_I_DIS5 - Disable Endpoint 5 IN Direction + * 0b0..Enable + * 0b1..Disable + */ +#define USB_STALL_IL_DIS_STALL_I_DIS5(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_IL_DIS_STALL_I_DIS5_SHIFT)) & USB_STALL_IL_DIS_STALL_I_DIS5_MASK) + +#define USB_STALL_IL_DIS_STALL_I_DIS6_MASK (0x40U) +#define USB_STALL_IL_DIS_STALL_I_DIS6_SHIFT (6U) +/*! STALL_I_DIS6 - Disable Endpoint 6 IN Direction + * 0b0..Enable + * 0b1..Disable + */ +#define USB_STALL_IL_DIS_STALL_I_DIS6(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_IL_DIS_STALL_I_DIS6_SHIFT)) & USB_STALL_IL_DIS_STALL_I_DIS6_MASK) + +#define USB_STALL_IL_DIS_STALL_I_DIS7_MASK (0x80U) +#define USB_STALL_IL_DIS_STALL_I_DIS7_SHIFT (7U) +/*! STALL_I_DIS7 - Disable Endpoint 7 IN Direction + * 0b0..Enable + * 0b1..Disable + */ +#define USB_STALL_IL_DIS_STALL_I_DIS7(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_IL_DIS_STALL_I_DIS7_SHIFT)) & USB_STALL_IL_DIS_STALL_I_DIS7_MASK) +/*! @} */ + +/*! @name STALL_IH_DIS - Peripheral Mode Stall Disable for Endpoints 15 to 8 in IN Direction */ +/*! @{ */ + +#define USB_STALL_IH_DIS_STALL_I_DIS8_MASK (0x1U) +#define USB_STALL_IH_DIS_STALL_I_DIS8_SHIFT (0U) +/*! STALL_I_DIS8 - Disable Endpoint 8 IN Direction + * 0b0..Enable + * 0b1..Disable + */ +#define USB_STALL_IH_DIS_STALL_I_DIS8(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_IH_DIS_STALL_I_DIS8_SHIFT)) & USB_STALL_IH_DIS_STALL_I_DIS8_MASK) + +#define USB_STALL_IH_DIS_STALL_I_DIS9_MASK (0x2U) +#define USB_STALL_IH_DIS_STALL_I_DIS9_SHIFT (1U) +/*! STALL_I_DIS9 - Disable Endpoint 9 IN Direction + * 0b0..Enable + * 0b1..Disable + */ +#define USB_STALL_IH_DIS_STALL_I_DIS9(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_IH_DIS_STALL_I_DIS9_SHIFT)) & USB_STALL_IH_DIS_STALL_I_DIS9_MASK) + +#define USB_STALL_IH_DIS_STALL_I_DIS10_MASK (0x4U) +#define USB_STALL_IH_DIS_STALL_I_DIS10_SHIFT (2U) +/*! STALL_I_DIS10 - Disable Endpoint 10 IN Direction + * 0b0..Enable + * 0b1..Disable + */ +#define USB_STALL_IH_DIS_STALL_I_DIS10(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_IH_DIS_STALL_I_DIS10_SHIFT)) & USB_STALL_IH_DIS_STALL_I_DIS10_MASK) + +#define USB_STALL_IH_DIS_STALL_I_DIS11_MASK (0x8U) +#define USB_STALL_IH_DIS_STALL_I_DIS11_SHIFT (3U) +/*! STALL_I_DIS11 - Disable Endpoint 11 IN Direction + * 0b0..Enable + * 0b1..Disable + */ +#define USB_STALL_IH_DIS_STALL_I_DIS11(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_IH_DIS_STALL_I_DIS11_SHIFT)) & USB_STALL_IH_DIS_STALL_I_DIS11_MASK) + +#define USB_STALL_IH_DIS_STALL_I_DIS12_MASK (0x10U) +#define USB_STALL_IH_DIS_STALL_I_DIS12_SHIFT (4U) +/*! STALL_I_DIS12 - Disable Endpoint 12 IN Direction + * 0b0..Enable + * 0b1..Disable + */ +#define USB_STALL_IH_DIS_STALL_I_DIS12(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_IH_DIS_STALL_I_DIS12_SHIFT)) & USB_STALL_IH_DIS_STALL_I_DIS12_MASK) + +#define USB_STALL_IH_DIS_STALL_I_DIS13_MASK (0x20U) +#define USB_STALL_IH_DIS_STALL_I_DIS13_SHIFT (5U) +/*! STALL_I_DIS13 - Disable Endpoint 13 IN Direction + * 0b0..Enable + * 0b1..Disable + */ +#define USB_STALL_IH_DIS_STALL_I_DIS13(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_IH_DIS_STALL_I_DIS13_SHIFT)) & USB_STALL_IH_DIS_STALL_I_DIS13_MASK) + +#define USB_STALL_IH_DIS_STALL_I_DIS14_MASK (0x40U) +#define USB_STALL_IH_DIS_STALL_I_DIS14_SHIFT (6U) +/*! STALL_I_DIS14 - Disable Endpoint 14 IN Direction + * 0b0..Enable + * 0b1..Disable + */ +#define USB_STALL_IH_DIS_STALL_I_DIS14(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_IH_DIS_STALL_I_DIS14_SHIFT)) & USB_STALL_IH_DIS_STALL_I_DIS14_MASK) + +#define USB_STALL_IH_DIS_STALL_I_DIS15_MASK (0x80U) +#define USB_STALL_IH_DIS_STALL_I_DIS15_SHIFT (7U) +/*! STALL_I_DIS15 - Disable Endpoint 15 IN Direction + * 0b0..Enable + * 0b1..Disable + */ +#define USB_STALL_IH_DIS_STALL_I_DIS15(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_IH_DIS_STALL_I_DIS15_SHIFT)) & USB_STALL_IH_DIS_STALL_I_DIS15_MASK) +/*! @} */ + +/*! @name STALL_OL_DIS - Peripheral Mode Stall Disable for Endpoints 7 to 0 in OUT Direction */ +/*! @{ */ + +#define USB_STALL_OL_DIS_STALL_O_DIS0_MASK (0x1U) +#define USB_STALL_OL_DIS_STALL_O_DIS0_SHIFT (0U) +/*! STALL_O_DIS0 - Disable Endpoint 0 OUT Direction + * 0b0..Enable + * 0b1..Disable + */ +#define USB_STALL_OL_DIS_STALL_O_DIS0(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_OL_DIS_STALL_O_DIS0_SHIFT)) & USB_STALL_OL_DIS_STALL_O_DIS0_MASK) + +#define USB_STALL_OL_DIS_STALL_O_DIS1_MASK (0x2U) +#define USB_STALL_OL_DIS_STALL_O_DIS1_SHIFT (1U) +/*! STALL_O_DIS1 - Disable Endpoint 1 OUT Direction + * 0b0..Enable + * 0b1..Disable + */ +#define USB_STALL_OL_DIS_STALL_O_DIS1(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_OL_DIS_STALL_O_DIS1_SHIFT)) & USB_STALL_OL_DIS_STALL_O_DIS1_MASK) + +#define USB_STALL_OL_DIS_STALL_O_DIS2_MASK (0x4U) +#define USB_STALL_OL_DIS_STALL_O_DIS2_SHIFT (2U) +/*! STALL_O_DIS2 - Disable Endpoint 2 OUT Direction + * 0b0..Enable + * 0b1..Disable + */ +#define USB_STALL_OL_DIS_STALL_O_DIS2(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_OL_DIS_STALL_O_DIS2_SHIFT)) & USB_STALL_OL_DIS_STALL_O_DIS2_MASK) + +#define USB_STALL_OL_DIS_STALL_O_DIS3_MASK (0x8U) +#define USB_STALL_OL_DIS_STALL_O_DIS3_SHIFT (3U) +/*! STALL_O_DIS3 - Disable Endpoint 3 OUT Direction + * 0b0..Enable + * 0b1..Disable + */ +#define USB_STALL_OL_DIS_STALL_O_DIS3(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_OL_DIS_STALL_O_DIS3_SHIFT)) & USB_STALL_OL_DIS_STALL_O_DIS3_MASK) + +#define USB_STALL_OL_DIS_STALL_O_DIS4_MASK (0x10U) +#define USB_STALL_OL_DIS_STALL_O_DIS4_SHIFT (4U) +/*! STALL_O_DIS4 - Disable Endpoint 4 OUT Direction + * 0b0..Enable + * 0b1..Disable + */ +#define USB_STALL_OL_DIS_STALL_O_DIS4(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_OL_DIS_STALL_O_DIS4_SHIFT)) & USB_STALL_OL_DIS_STALL_O_DIS4_MASK) + +#define USB_STALL_OL_DIS_STALL_O_DIS5_MASK (0x20U) +#define USB_STALL_OL_DIS_STALL_O_DIS5_SHIFT (5U) +/*! STALL_O_DIS5 - Disable Endpoint 5 OUT Direction + * 0b0..Enable + * 0b1..Disable + */ +#define USB_STALL_OL_DIS_STALL_O_DIS5(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_OL_DIS_STALL_O_DIS5_SHIFT)) & USB_STALL_OL_DIS_STALL_O_DIS5_MASK) + +#define USB_STALL_OL_DIS_STALL_O_DIS6_MASK (0x40U) +#define USB_STALL_OL_DIS_STALL_O_DIS6_SHIFT (6U) +/*! STALL_O_DIS6 - Disable Endpoint 6 OUT Direction + * 0b0..Enable + * 0b1..Disable + */ +#define USB_STALL_OL_DIS_STALL_O_DIS6(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_OL_DIS_STALL_O_DIS6_SHIFT)) & USB_STALL_OL_DIS_STALL_O_DIS6_MASK) + +#define USB_STALL_OL_DIS_STALL_O_DIS7_MASK (0x80U) +#define USB_STALL_OL_DIS_STALL_O_DIS7_SHIFT (7U) +/*! STALL_O_DIS7 - Disable Endpoint 7 OUT Direction + * 0b0..Enable + * 0b1..Disable + */ +#define USB_STALL_OL_DIS_STALL_O_DIS7(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_OL_DIS_STALL_O_DIS7_SHIFT)) & USB_STALL_OL_DIS_STALL_O_DIS7_MASK) +/*! @} */ + +/*! @name STALL_OH_DIS - Peripheral Mode Stall Disable for Endpoints 15 to 8 in OUT Direction */ +/*! @{ */ + +#define USB_STALL_OH_DIS_STALL_O_DIS8_MASK (0x1U) +#define USB_STALL_OH_DIS_STALL_O_DIS8_SHIFT (0U) +/*! STALL_O_DIS8 - Disable Endpoint 8 OUT Direction + * 0b0..Enable + * 0b1..Disable + */ +#define USB_STALL_OH_DIS_STALL_O_DIS8(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_OH_DIS_STALL_O_DIS8_SHIFT)) & USB_STALL_OH_DIS_STALL_O_DIS8_MASK) + +#define USB_STALL_OH_DIS_STALL_O_DIS9_MASK (0x2U) +#define USB_STALL_OH_DIS_STALL_O_DIS9_SHIFT (1U) +/*! STALL_O_DIS9 - Disable Endpoint 9 OUT Direction + * 0b0..Enable + * 0b1..Disable + */ +#define USB_STALL_OH_DIS_STALL_O_DIS9(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_OH_DIS_STALL_O_DIS9_SHIFT)) & USB_STALL_OH_DIS_STALL_O_DIS9_MASK) + +#define USB_STALL_OH_DIS_STALL_O_DIS10_MASK (0x4U) +#define USB_STALL_OH_DIS_STALL_O_DIS10_SHIFT (2U) +/*! STALL_O_DIS10 - Disable Endpoint 10 OUT Direction + * 0b0..Enable + * 0b1..Disable + */ +#define USB_STALL_OH_DIS_STALL_O_DIS10(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_OH_DIS_STALL_O_DIS10_SHIFT)) & USB_STALL_OH_DIS_STALL_O_DIS10_MASK) + +#define USB_STALL_OH_DIS_STALL_O_DIS11_MASK (0x8U) +#define USB_STALL_OH_DIS_STALL_O_DIS11_SHIFT (3U) +/*! STALL_O_DIS11 - Disable Endpoint 11 OUT Direction + * 0b0..Enable + * 0b1..Disable + */ +#define USB_STALL_OH_DIS_STALL_O_DIS11(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_OH_DIS_STALL_O_DIS11_SHIFT)) & USB_STALL_OH_DIS_STALL_O_DIS11_MASK) + +#define USB_STALL_OH_DIS_STALL_O_DIS12_MASK (0x10U) +#define USB_STALL_OH_DIS_STALL_O_DIS12_SHIFT (4U) +/*! STALL_O_DIS12 - Disable endpoint 12 OUT direction + * 0b0..Enable + * 0b1..Disable + */ +#define USB_STALL_OH_DIS_STALL_O_DIS12(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_OH_DIS_STALL_O_DIS12_SHIFT)) & USB_STALL_OH_DIS_STALL_O_DIS12_MASK) + +#define USB_STALL_OH_DIS_STALL_O_DIS13_MASK (0x20U) +#define USB_STALL_OH_DIS_STALL_O_DIS13_SHIFT (5U) +/*! STALL_O_DIS13 - Disable Endpoint 13 OUT Direction + * 0b0..Enable + * 0b1..Disable + */ +#define USB_STALL_OH_DIS_STALL_O_DIS13(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_OH_DIS_STALL_O_DIS13_SHIFT)) & USB_STALL_OH_DIS_STALL_O_DIS13_MASK) + +#define USB_STALL_OH_DIS_STALL_O_DIS14_MASK (0x40U) +#define USB_STALL_OH_DIS_STALL_O_DIS14_SHIFT (6U) +/*! STALL_O_DIS14 - Disable Endpoint 14 OUT Direction + * 0b0..Enable + * 0b1..Disable + */ +#define USB_STALL_OH_DIS_STALL_O_DIS14(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_OH_DIS_STALL_O_DIS14_SHIFT)) & USB_STALL_OH_DIS_STALL_O_DIS14_MASK) + +#define USB_STALL_OH_DIS_STALL_O_DIS15_MASK (0x80U) +#define USB_STALL_OH_DIS_STALL_O_DIS15_SHIFT (7U) +/*! STALL_O_DIS15 - Disable Endpoint 15 OUT Direction + * 0b0..Enable + * 0b1..Disable + */ +#define USB_STALL_OH_DIS_STALL_O_DIS15(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_OH_DIS_STALL_O_DIS15_SHIFT)) & USB_STALL_OH_DIS_STALL_O_DIS15_MASK) +/*! @} */ + +/*! @name CLK_RECOVER_CTRL - USB Clock Recovery Control */ +/*! @{ */ + +#define USB_CLK_RECOVER_CTRL_TRIM_INIT_VAL_SEL_MASK (0x8U) +#define USB_CLK_RECOVER_CTRL_TRIM_INIT_VAL_SEL_SHIFT (3U) +/*! TRIM_INIT_VAL_SEL - Selects the source for the initial FIRC trim fine value used after a reset. + * 0b0..Mid-scale + * 0b1..IFR + */ +#define USB_CLK_RECOVER_CTRL_TRIM_INIT_VAL_SEL(x) (((uint8_t)(((uint8_t)(x)) << USB_CLK_RECOVER_CTRL_TRIM_INIT_VAL_SEL_SHIFT)) & USB_CLK_RECOVER_CTRL_TRIM_INIT_VAL_SEL_MASK) + +#define USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN_MASK (0x20U) +#define USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN_SHIFT (5U) +/*! RESTART_IFRTRIM_EN - Restart from IFR Trim Value + * 0b0..Trim fine adjustment always works based on the previous updated trim fine value. + * 0b1..Trim fine restarts from the IFR trim value whenever you detect bus_reset or bus_resume or deassert module enable. + */ +#define USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN(x) (((uint8_t)(((uint8_t)(x)) << USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN_SHIFT)) & USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN_MASK) + +#define USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN_MASK (0x40U) +#define USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN_SHIFT (6U) +/*! RESET_RESUME_ROUGH_EN - Reset or Resume to Rough Phase Enable + * 0b0..Always works in tracking phase after the first time rough phase, to track transition. + * 0b1..Go back to rough stage whenever a bus reset or bus resume occurs. + */ +#define USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN(x) (((uint8_t)(((uint8_t)(x)) << USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN_SHIFT)) & USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN_MASK) + +#define USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN_MASK (0x80U) +#define USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN_SHIFT (7U) +/*! CLOCK_RECOVER_EN - Crystal-Less USB Enable + * 0b0..Disable + * 0b1..Enable + */ +#define USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN(x) (((uint8_t)(((uint8_t)(x)) << USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN_SHIFT)) & USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN_MASK) +/*! @} */ + +/*! @name CLK_RECOVER_IRC_EN - FIRC Oscillator Enable */ +/*! @{ */ + +#define USB_CLK_RECOVER_IRC_EN_IRC_EN_MASK (0x2U) +#define USB_CLK_RECOVER_IRC_EN_IRC_EN_SHIFT (1U) +/*! IRC_EN - Fast IRC enable + * 0b0..Disable + * 0b1..Enable + */ +#define USB_CLK_RECOVER_IRC_EN_IRC_EN(x) (((uint8_t)(((uint8_t)(x)) << USB_CLK_RECOVER_IRC_EN_IRC_EN_SHIFT)) & USB_CLK_RECOVER_IRC_EN_IRC_EN_MASK) +/*! @} */ + +/*! @name CLK_RECOVER_INT_EN - Clock Recovery Combined Interrupt Enable */ +/*! @{ */ + +#define USB_CLK_RECOVER_INT_EN_OVF_ERROR_EN_MASK (0x10U) +#define USB_CLK_RECOVER_INT_EN_OVF_ERROR_EN_SHIFT (4U) +/*! OVF_ERROR_EN - Overflow error interrupt enable + * 0b0..The interrupt is masked + * 0b1..The interrupt is enabled + */ +#define USB_CLK_RECOVER_INT_EN_OVF_ERROR_EN(x) (((uint8_t)(((uint8_t)(x)) << USB_CLK_RECOVER_INT_EN_OVF_ERROR_EN_SHIFT)) & USB_CLK_RECOVER_INT_EN_OVF_ERROR_EN_MASK) +/*! @} */ + +/*! @name CLK_RECOVER_INT_STATUS - Clock Recovery Separated Interrupt Status */ +/*! @{ */ + +#define USB_CLK_RECOVER_INT_STATUS_OVF_ERROR_MASK (0x10U) +#define USB_CLK_RECOVER_INT_STATUS_OVF_ERROR_SHIFT (4U) +/*! OVF_ERROR - Overflow Error Interrupt Status Flag + * 0b0..Interrupt did not occur + * 0b1..Unmasked interrupt occurred + * 0b0..No effect + * 0b1..Clear the flag + */ +#define USB_CLK_RECOVER_INT_STATUS_OVF_ERROR(x) (((uint8_t)(((uint8_t)(x)) << USB_CLK_RECOVER_INT_STATUS_OVF_ERROR_SHIFT)) & USB_CLK_RECOVER_INT_STATUS_OVF_ERROR_MASK) +/*! @} */ + +/*! + * @} + */ +/* end of group USB_Register_Masks */ + +/*! + * @brief This type of structure instance is used to implement the buffer descriptor for USB. + */ +typedef struct +{ + union { + uint32_t head; /*!< Head. */ + struct + { + uint32_t reserved0 : 2; /*!< RESEVED. */ + uint32_t bdt_stall : 1; /*!< Stall. */ + uint32_t dts : 1; /*!< Data shift sync. */ + uint32_t ninc : 1; /*!< DMA addr cannot increasing. */ + uint32_t keep : 1; /*!< Keep BD held by USB. */ + uint32_t data : 1; /*!< DATA0 or DATA1. */ + uint32_t own : 1; /*!< Owner, 0 is CPU, 1 is USB. */ + uint32_t reserved1 : 8; /*!< RESEVED. */ + uint32_t bc : 10; /*!< Packet size. */ + uint32_t reserved2 : 6; /*!< RESEVED. */ + }; + struct + { + uint32_t reserved3 : 2; /*!< RESEVED. */ + uint32_t tok_pid : 4; /*!< Token pid. */ + uint32_t reserved4 : 26; /*!< RESEVED. */ + }; + }; + uint32_t addr; /*!< Buffer addr. */ +} kinetis_bd_t; + +/*! + * @brief This type of structure instance is used to implement the buffer descriptor table for USB. + */ +typedef union { + kinetis_bd_t table[16][2][2]; /*!< [EndPoint] [Direction] [Odd_Even]. */ + uint8_t buffer[512]; /*!< buffer. */ +} kinetis_bd_table_t; + +/** + * @brief USBFS TokenPid type. + */ +typedef enum { + USB_TOKEN_PID_OUT = 0x1u, /*!< USB Token Pid: OUT. */ + USB_TOKEN_PID_IN = 0x9u, /*!< USB Token Pid: IN. */ + USB_TOKEN_PID_SETUP = 0xDu, /*!< USB Token Pid: SETUP. */ + USB_TOKEN_PID_DATA0 = 0x03, /*!< USB Token Pid: DATA0. */ + USB_TOKEN_PID_DATA1 = 0x0B, /*!< USB Token Pid: DATA1. */ + USB_TOKEN_PID_ACK = 0x02, /*!< USB Token Pid: ACK. */ + USB_TOKEN_PID_STALL = 0x0E, /*!< USB Token Pid: STALL. */ + USB_TOKEN_PID_NAK = 0x0A, /*!< USB Token Pid: NAK. */ + USB_TOKEN_PID_BUSTIMEOUT = 0x00, /*!< USB Token Pid: BUSTO. */ + USB_TOKEN_PID_ERR = 0x0f, /*!< USB Token Pid: ERR. */ +} USB_TOKEN_PID_Type; + +typedef struct { + KINETIS_TypeDef base; + __IO uint8_t USBCTRL; /**< USB Control, offset: 0x100 */ + uint8_t RESERVED_22[3]; + __I uint8_t OBSERVE; /**< USB OTG Observe, offset: 0x104 */ + uint8_t RESERVED_23[3]; + __IO uint8_t CONTROL; /**< USB OTG Control, offset: 0x108 */ + uint8_t RESERVED_24[3]; + __IO uint8_t USBTRC0; /**< USB Transceiver Control 0, offset: 0x10C */ + uint8_t RESERVED_25[7]; + __IO uint8_t USBFRMADJUST; /**< Frame Adjust, offset: 0x114 */ + uint8_t RESERVED_26[15]; + __IO uint8_t KEEP_ALIVE_CTRL; /**< Keep Alive Mode Control, offset: 0x124 */ + uint8_t RESERVED_27[3]; + __IO uint8_t KEEP_ALIVE_WKCTRL; /**< Keep Alive Mode Wakeup Control, offset: 0x128 */ + uint8_t RESERVED_28[3]; + __IO uint8_t MISCCTRL; /**< Miscellaneous Control, offset: 0x12C */ + uint8_t RESERVED_29[3]; + __IO uint8_t STALL_IL_DIS; /**< Peripheral Mode Stall Disable for Endpoints 7 to 0 in IN Direction, offset: 0x130 */ + uint8_t RESERVED_30[3]; + __IO uint8_t STALL_IH_DIS; /**< Peripheral Mode Stall Disable for Endpoints 15 to 8 in IN Direction, offset: 0x134 */ + uint8_t RESERVED_31[3]; + __IO uint8_t STALL_OL_DIS; /**< Peripheral Mode Stall Disable for Endpoints 7 to 0 in OUT Direction, offset: 0x138 */ + uint8_t RESERVED_32[3]; + __IO uint8_t STALL_OH_DIS; /**< Peripheral Mode Stall Disable for Endpoints 15 to 8 in OUT Direction, offset: 0x13C */ + uint8_t RESERVED_33[3]; + __IO uint8_t CLK_RECOVER_CTRL; /**< USB Clock Recovery Control, offset: 0x140 */ + uint8_t RESERVED_34[3]; + __IO uint8_t CLK_RECOVER_IRC_EN; /**< FIRC Oscillator Enable, offset: 0x144 */ + uint8_t RESERVED_35[15]; + __IO uint8_t CLK_RECOVER_INT_EN; /**< Clock Recovery Combined Interrupt Enable, offset: 0x154 */ + uint8_t RESERVED_36[7]; + __IO uint8_t CLK_RECOVER_INT_STATUS; /**< Clock Recovery Separated Interrupt Status, offset: 0x15C */ +} KINETIS_MCX_TypeDef; + +void usb_dc_low_level_init(uint8_t busid); +void usb_dc_low_level_deinit(uint8_t busid); + +void usbd_kinetis_delay_ms(uint8_t ms); +#endif \ No newline at end of file diff --git a/kernel/cherryusb/port/musb/README.md b/kernel/cherryusb/port/musb/README.md new file mode 100644 index 0000000..7c7b430 --- /dev/null +++ b/kernel/cherryusb/port/musb/README.md @@ -0,0 +1,24 @@ +# Note + +## Support Chip List + +### Eastsoft + +- ES32F3xx + +### TI + +- MSP432E4x +- TM4Cx + +### Bekencorp + +- BK7256/BK7258 + +### AllwinnerTech + +- F1Cxxx, F2Cxxx + +### SIFLI + +- SF325X diff --git a/kernel/cherryusb/port/musb/usb_dc_musb.c b/kernel/cherryusb/port/musb/usb_dc_musb.c new file mode 100644 index 0000000..de45b97 --- /dev/null +++ b/kernel/cherryusb/port/musb/usb_dc_musb.c @@ -0,0 +1,898 @@ +/* + * Copyright (c) 2022, sakumisu + * + * SPDX-License-Identifier: Apache-2.0 + */ +#include "usbd_core.h" +#include "usb_musb_reg.h" + +#define HWREG(x) \ + (*((volatile uint32_t *)(x))) +#define HWREGH(x) \ + (*((volatile uint16_t *)(x))) +#define HWREGB(x) \ + (*((volatile uint8_t *)(x))) + +#define USB_BASE (g_usbdev_bus[0].reg_base) + +#if defined(CONFIG_USB_MUSB_SUNXI) +#define MUSB_FADDR_OFFSET 0x98 +#define MUSB_POWER_OFFSET 0x40 +#define MUSB_TXIS_OFFSET 0x44 +#define MUSB_RXIS_OFFSET 0x46 +#define MUSB_TXIE_OFFSET 0x48 +#define MUSB_RXIE_OFFSET 0x4A +#define MUSB_IS_OFFSET 0x4C +#define MUSB_IE_OFFSET 0x50 +#define MUSB_EPIDX_OFFSET 0x42 + +#define MUSB_IND_TXMAP_OFFSET 0x80 +#define MUSB_IND_TXCSRL_OFFSET 0x82 +#define MUSB_IND_TXCSRH_OFFSET 0x83 +#define MUSB_IND_RXMAP_OFFSET 0x84 +#define MUSB_IND_RXCSRL_OFFSET 0x86 +#define MUSB_IND_RXCSRH_OFFSET 0x87 +#define MUSB_IND_RXCOUNT_OFFSET 0x88 +#define MUSB_IND_TXTYPE_OFFSET 0x8C +#define MUSB_IND_TXINTERVAL_OFFSET 0x8D +#define MUSB_IND_RXTYPE_OFFSET 0x8E +#define MUSB_IND_RXINTERVAL_OFFSET 0x8F + +#define MUSB_FIFO_OFFSET 0x00 + +#define MUSB_DEVCTL_OFFSET 0x41 + +#define MUSB_TXFIFOSZ_OFFSET 0x90 +#define MUSB_RXFIFOSZ_OFFSET 0x94 +#define MUSB_TXFIFOADD_OFFSET 0x92 +#define MUSB_RXFIFOADD_OFFSET 0x96 + +#define MUSB_TXFUNCADDR0_OFFSET 0x98 +#define MUSB_TXHUBADDR0_OFFSET 0x9A +#define MUSB_TXHUBPORT0_OFFSET 0x9B +#define MUSB_TXFUNCADDRx_OFFSET 0x98 +#define MUSB_TXHUBADDRx_OFFSET 0x9A +#define MUSB_TXHUBPORTx_OFFSET 0x9B +#define MUSB_RXFUNCADDRx_OFFSET 0x9C +#define MUSB_RXHUBADDRx_OFFSET 0x9E +#define MUSB_RXHUBPORTx_OFFSET 0x9F + +#define USB_TXMAP_BASE(ep_idx) (USB_BASE + MUSB_IND_TXMAP_OFFSET) +#define USB_TXCSRL_BASE(ep_idx) (USB_BASE + MUSB_IND_TXCSRL_OFFSET) +#define USB_TXCSRH_BASE(ep_idx) (USB_BASE + MUSB_IND_TXCSRH_OFFSET) +#define USB_RXMAP_BASE(ep_idx) (USB_BASE + MUSB_IND_RXMAP_OFFSET) +#define USB_RXCSRL_BASE(ep_idx) (USB_BASE + MUSB_IND_RXCSRL_OFFSET) +#define USB_RXCSRH_BASE(ep_idx) (USB_BASE + MUSB_IND_RXCSRH_OFFSET) +#define USB_RXCOUNT_BASE(ep_idx) (USB_BASE + MUSB_IND_RXCOUNT_OFFSET) +#define USB_TXTYPE_BASE(ep_idx) (USB_BASE + MUSB_IND_TXTYPE_OFFSET) +#define USB_TXINTERVAL_BASE(ep_idx) (USB_BASE + MUSB_IND_TXINTERVAL_OFFSET) +#define USB_RXTYPE_BASE(ep_idx) (USB_BASE + MUSB_IND_RXTYPE_OFFSET) +#define USB_RXINTERVAL_BASE(ep_idx) (USB_BASE + MUSB_IND_RXINTERVAL_OFFSET) + +#define USB_TXADDR_BASE(ep_idx) (USB_BASE + MUSB_TXFUNCADDRx_OFFSET) +#define USB_TXHUBADDR_BASE(ep_idx) (USB_BASE + MUSB_TXHUBADDRx_OFFSET) +#define USB_TXHUBPORT_BASE(ep_idx) (USB_BASE + MUSB_TXHUBPORTx_OFFSET) +#define USB_RXADDR_BASE(ep_idx) (USB_BASE + MUSB_RXFUNCADDRx_OFFSET) +#define USB_RXHUBADDR_BASE(ep_idx) (USB_BASE + MUSB_RXHUBADDRx_OFFSET) +#define USB_RXHUBPORT_BASE(ep_idx) (USB_BASE + MUSB_RXHUBPORTx_OFFSET) + +#elif defined(CONFIG_USB_MUSB_CUSTOM) +#include "musb_custom.h" +#else +#define MUSB_FADDR_OFFSET 0x00 +#define MUSB_POWER_OFFSET 0x01 +#define MUSB_TXIS_OFFSET 0x02 +#define MUSB_RXIS_OFFSET 0x04 +#define MUSB_TXIE_OFFSET 0x06 +#define MUSB_RXIE_OFFSET 0x08 +#define MUSB_IS_OFFSET 0x0A +#define MUSB_IE_OFFSET 0x0B + +#define MUSB_EPIDX_OFFSET 0x0E + +#define MUSB_IND_TXMAP_OFFSET 0x10 +#define MUSB_IND_TXCSRL_OFFSET 0x12 +#define MUSB_IND_TXCSRH_OFFSET 0x13 +#define MUSB_IND_RXMAP_OFFSET 0x14 +#define MUSB_IND_RXCSRL_OFFSET 0x16 +#define MUSB_IND_RXCSRH_OFFSET 0x17 +#define MUSB_IND_RXCOUNT_OFFSET 0x18 +#define MUSB_IND_TXTYPE_OFFSET 0x1A +#define MUSB_IND_TXINTERVAL_OFFSET 0x1B +#define MUSB_IND_RXTYPE_OFFSET 0x1C +#define MUSB_IND_RXINTERVAL_OFFSET 0x1D + +#define MUSB_FIFO_OFFSET 0x20 + +#define MUSB_DEVCTL_OFFSET 0x60 + +#define MUSB_TXFIFOSZ_OFFSET 0x62 +#define MUSB_RXFIFOSZ_OFFSET 0x63 +#define MUSB_TXFIFOADD_OFFSET 0x64 +#define MUSB_RXFIFOADD_OFFSET 0x66 + +#define MUSB_TXFUNCADDR0_OFFSET 0x80 +#define MUSB_TXHUBADDR0_OFFSET 0x82 +#define MUSB_TXHUBPORT0_OFFSET 0x83 +#define MUSB_TXFUNCADDRx_OFFSET 0x88 +#define MUSB_TXHUBADDRx_OFFSET 0x8A +#define MUSB_TXHUBPORTx_OFFSET 0x8B +#define MUSB_RXFUNCADDRx_OFFSET 0x8C +#define MUSB_RXHUBADDRx_OFFSET 0x8E +#define MUSB_RXHUBPORTx_OFFSET 0x8F + +#define MUSB_TXMAP0_OFFSET 0x100 + +// do not use EPIDX +#define USB_TXMAP_BASE(ep_idx) (USB_BASE + MUSB_TXMAP0_OFFSET + 0x10 * ep_idx) +#define USB_TXCSRL_BASE(ep_idx) (USB_BASE + MUSB_TXMAP0_OFFSET + 0x10 * ep_idx + 2) +#define USB_TXCSRH_BASE(ep_idx) (USB_BASE + MUSB_TXMAP0_OFFSET + 0x10 * ep_idx + 3) +#define USB_RXMAP_BASE(ep_idx) (USB_BASE + MUSB_TXMAP0_OFFSET + 0x10 * ep_idx + 4) +#define USB_RXCSRL_BASE(ep_idx) (USB_BASE + MUSB_TXMAP0_OFFSET + 0x10 * ep_idx + 6) +#define USB_RXCSRH_BASE(ep_idx) (USB_BASE + MUSB_TXMAP0_OFFSET + 0x10 * ep_idx + 7) +#define USB_RXCOUNT_BASE(ep_idx) (USB_BASE + MUSB_TXMAP0_OFFSET + 0x10 * ep_idx + 8) +#define USB_TXTYPE_BASE(ep_idx) (USB_BASE + MUSB_TXMAP0_OFFSET + 0x10 * ep_idx + 0x0A) +#define USB_TXINTERVAL_BASE(ep_idx) (USB_BASE + MUSB_TXMAP0_OFFSET + 0x10 * ep_idx + 0x0B) +#define USB_RXTYPE_BASE(ep_idx) (USB_BASE + MUSB_TXMAP0_OFFSET + 0x10 * ep_idx + 0x0C) +#define USB_RXINTERVAL_BASE(ep_idx) (USB_BASE + MUSB_TXMAP0_OFFSET + 0x10 * ep_idx + 0x0D) + +#define USB_TXADDR_BASE(ep_idx) (USB_BASE + MUSB_TXFUNCADDR0_OFFSET + 0x8 * ep_idx) +#define USB_TXHUBADDR_BASE(ep_idx) (USB_BASE + MUSB_TXFUNCADDR0_OFFSET + 0x8 * ep_idx + 2) +#define USB_TXHUBPORT_BASE(ep_idx) (USB_BASE + MUSB_TXFUNCADDR0_OFFSET + 0x8 * ep_idx + 3) +#define USB_RXADDR_BASE(ep_idx) (USB_BASE + MUSB_TXFUNCADDR0_OFFSET + 0x8 * ep_idx + 4) +#define USB_RXHUBADDR_BASE(ep_idx) (USB_BASE + MUSB_TXFUNCADDR0_OFFSET + 0x8 * ep_idx + 6) +#define USB_RXHUBPORT_BASE(ep_idx) (USB_BASE + MUSB_TXFUNCADDR0_OFFSET + 0x8 * ep_idx + 7) +#endif + +#define USB_FIFO_BASE(ep_idx) (USB_BASE + MUSB_FIFO_OFFSET + 0x4 * ep_idx) + +typedef enum { + USB_EP0_STATE_SETUP = 0x0, /**< SETUP DATA */ + USB_EP0_STATE_IN_DATA = 0x1, /**< IN DATA */ + USB_EP0_STATE_OUT_DATA = 0x3, /**< OUT DATA */ + USB_EP0_STATE_IN_STATUS = 0x4, /**< IN status */ + USB_EP0_STATE_OUT_STATUS = 0x5, /**< OUT status */ + USB_EP0_STATE_IN_ZLP = 0x6, /**< OUT status */ + USB_EP0_STATE_STALL = 0x7, /**< STALL status */ +} ep0_state_t; + +/* Endpoint state */ +struct musb_ep_state { + uint16_t ep_mps; /* Endpoint max packet size */ + uint8_t ep_type; /* Endpoint type */ + uint8_t ep_stalled; /* Endpoint stall flag */ + uint8_t ep_enable; /* Endpoint enable */ + uint8_t *xfer_buf; + uint32_t xfer_len; + uint32_t actual_xfer_len; +}; + +/* Driver state */ +struct musb_udc { + volatile uint8_t dev_addr; + __attribute__((aligned(32))) struct usb_setup_packet setup; + struct musb_ep_state in_ep[CONFIG_USB_MUSB_EP_NUM]; /*!< IN endpoint parameters*/ + struct musb_ep_state out_ep[CONFIG_USB_MUSB_EP_NUM]; /*!< OUT endpoint parameters */ +} g_musb_udc; + +static volatile uint8_t usb_ep0_state = USB_EP0_STATE_SETUP; + +/* get current active ep */ +static uint8_t musb_get_active_ep(void) +{ + return HWREGB(USB_BASE + MUSB_EPIDX_OFFSET); +} + +/* set the active ep */ +static void musb_set_active_ep(uint8_t ep_index) +{ + HWREGB(USB_BASE + MUSB_EPIDX_OFFSET) = ep_index; +} + +static void musb_write_packet(uint8_t ep_idx, uint8_t *buffer, uint16_t len) +{ + uint32_t *buf32; + uint8_t *buf8; + uint32_t count32; + uint32_t count8; + int i; + + if ((uint32_t)buffer & 0x03) { + buf8 = buffer; + for (i = 0; i < len; i++) { + HWREGB(USB_FIFO_BASE(ep_idx)) = *buf8++; + } + } else { + count32 = len >> 2; + count8 = len & 0x03; + + buf32 = (uint32_t *)buffer; + + while (count32--) { + HWREG(USB_FIFO_BASE(ep_idx)) = *buf32++; + } + + buf8 = (uint8_t *)buf32; + + while (count8--) { + HWREGB(USB_FIFO_BASE(ep_idx)) = *buf8++; + } + } +} + +static void musb_read_packet(uint8_t ep_idx, uint8_t *buffer, uint16_t len) +{ + uint32_t *buf32; + uint8_t *buf8; + uint32_t count32; + uint32_t count8; + int i; + + if ((uint32_t)buffer & 0x03) { + buf8 = buffer; + for (i = 0; i < len; i++) { + *buf8++ = HWREGB(USB_FIFO_BASE(ep_idx)); + } + } else { + count32 = len >> 2; + count8 = len & 0x03; + + buf32 = (uint32_t *)buffer; + + while (count32--) { + *buf32++ = HWREG(USB_FIFO_BASE(ep_idx)); + } + + buf8 = (uint8_t *)buf32; + + while (count8--) { + *buf8++ = HWREGB(USB_FIFO_BASE(ep_idx)); + } + } +} + +static uint32_t musb_get_fifo_size(uint16_t mps, uint16_t *used) +{ + uint32_t size; + + for (uint8_t i = USB_TXFIFOSZ_SIZE_8; i <= USB_TXFIFOSZ_SIZE_2048; i++) { + size = (8 << i); + if (mps <= size) { + *used = size; + return i; + } + } + + *used = 0; + return USB_TXFIFOSZ_SIZE_8; +} + +static uint32_t usbd_musb_fifo_config(struct musb_fifo_cfg *cfg, uint32_t offset) +{ + uint16_t fifo_used; + uint8_t c_size; + uint16_t c_off; + + c_off = offset >> 3; + c_size = musb_get_fifo_size(cfg->maxpacket, &fifo_used); + + musb_set_active_ep(cfg->ep_num); + + switch (cfg->style) { + case FIFO_TX: + HWREGB(USB_BASE + MUSB_TXFIFOSZ_OFFSET) = c_size & 0x0f; + HWREGH(USB_BASE + MUSB_TXFIFOADD_OFFSET) = c_off; + break; + case FIFO_RX: + HWREGB(USB_BASE + MUSB_RXFIFOSZ_OFFSET) = c_size & 0x0f; + HWREGH(USB_BASE + MUSB_RXFIFOADD_OFFSET) = c_off; + break; + case FIFO_TXRX: + HWREGB(USB_BASE + MUSB_TXFIFOSZ_OFFSET) = c_size & 0x0f; + HWREGH(USB_BASE + MUSB_TXFIFOADD_OFFSET) = c_off; + HWREGB(USB_BASE + MUSB_RXFIFOSZ_OFFSET) = c_size & 0x0f; + HWREGH(USB_BASE + MUSB_RXFIFOADD_OFFSET) = c_off; + break; + + default: + break; + } + + return (offset + fifo_used); +} + +__WEAK void usb_dc_low_level_init(void) +{ +} + +__WEAK void usb_dc_low_level_deinit(void) +{ +} + +int usb_dc_init(uint8_t busid) +{ + uint16_t offset = 0; + uint8_t cfg_num; + struct musb_fifo_cfg *cfg; + + usb_dc_low_level_init(); + +#ifdef CONFIG_USB_HS + HWREGB(USB_BASE + MUSB_POWER_OFFSET) |= USB_POWER_HSENAB; +#else + HWREGB(USB_BASE + MUSB_POWER_OFFSET) &= ~USB_POWER_HSENAB; +#endif + + musb_set_active_ep(0); + HWREGB(USB_BASE + MUSB_FADDR_OFFSET) = 0; + + HWREGB(USB_BASE + MUSB_DEVCTL_OFFSET) |= USB_DEVCTL_SESSION; + + cfg_num = usbd_get_musb_fifo_cfg(&cfg); + + for (uint8_t i = 0; i < cfg_num; i++) { + offset = usbd_musb_fifo_config(&cfg[i], offset); + } + + USB_ASSERT_MSG(offset <= usb_get_musb_ram_size(), "Your fifo config is overflow, please check"); + + /* Enable USB interrupts */ + HWREGB(USB_BASE + MUSB_IE_OFFSET) = USB_IE_RESET | USB_IE_SUSPND | USB_IE_RESUME; + HWREGH(USB_BASE + MUSB_TXIE_OFFSET) = USB_TXIE_EP0; + HWREGH(USB_BASE + MUSB_RXIE_OFFSET) = 0; + +#ifdef CONFIG_USBDEV_SOF_ENABLE + HWREGB(USB_BASE + MUSB_IE_OFFSET) |= USB_IE_SOF; +#endif + + HWREGB(USB_BASE + MUSB_POWER_OFFSET) |= USB_POWER_SOFTCONN; + return 0; +} + +int usb_dc_deinit(uint8_t busid) +{ + HWREGB(USB_BASE + MUSB_IE_OFFSET) = 0; + HWREGH(USB_BASE + MUSB_TXIE_OFFSET) = 0; + HWREGH(USB_BASE + MUSB_RXIE_OFFSET) = 0; + + HWREGB(USB_BASE + MUSB_POWER_OFFSET) &= ~USB_POWER_SOFTCONN; + + usb_dc_low_level_deinit(); + return 0; +} + +int usbd_set_address(uint8_t busid, const uint8_t addr) +{ + if (addr == 0) { + HWREGB(USB_BASE + MUSB_FADDR_OFFSET) = 0; + } + + g_musb_udc.dev_addr = addr; + return 0; +} + +int usbd_set_remote_wakeup(uint8_t busid) +{ + HWREGB(USB_BASE + MUSB_POWER_OFFSET) |= USB_POWER_RESUME; + usbd_musb_delay_ms(10); + HWREGB(USB_BASE + MUSB_POWER_OFFSET) &= ~USB_POWER_RESUME; + return 0; +} + +uint8_t usbd_get_port_speed(uint8_t busid) +{ + uint8_t speed = USB_SPEED_UNKNOWN; + + if (HWREGB(USB_BASE + MUSB_POWER_OFFSET) & USB_POWER_HSMODE) + speed = USB_SPEED_HIGH; + else if (HWREGB(USB_BASE + MUSB_DEVCTL_OFFSET) & USB_DEVCTL_FSDEV) + speed = USB_SPEED_FULL; + else if (HWREGB(USB_BASE + MUSB_DEVCTL_OFFSET) & USB_DEVCTL_LSDEV) + speed = USB_SPEED_LOW; + + return speed; +} + +int usbd_ep_open(uint8_t busid, const struct usb_endpoint_descriptor *ep) +{ + uint8_t ep_idx = USB_EP_GET_IDX(ep->bEndpointAddress); + uint8_t old_ep_idx; + uint32_t ui32Flags = 0; + uint16_t ui32Register = 0; + + if (ep_idx == 0) { + g_musb_udc.out_ep[0].ep_mps = USB_CTRL_EP_MPS; + g_musb_udc.out_ep[0].ep_type = 0x00; + g_musb_udc.out_ep[0].ep_enable = true; + g_musb_udc.in_ep[0].ep_mps = USB_CTRL_EP_MPS; + g_musb_udc.in_ep[0].ep_type = 0x00; + g_musb_udc.in_ep[0].ep_enable = true; + return 0; + } + + USB_ASSERT_MSG(ep_idx < CONFIG_USB_MUSB_EP_NUM, "Ep addr %02x overflow", ep->bEndpointAddress); + + old_ep_idx = musb_get_active_ep(); + musb_set_active_ep(ep_idx); + + if (USB_EP_DIR_IS_OUT(ep->bEndpointAddress)) { + g_musb_udc.out_ep[ep_idx].ep_mps = USB_GET_MAXPACKETSIZE(ep->wMaxPacketSize); + g_musb_udc.out_ep[ep_idx].ep_type = USB_GET_ENDPOINT_TYPE(ep->bmAttributes); + g_musb_udc.out_ep[ep_idx].ep_enable = true; + +#ifndef CONFIG_USB_MUSB_SIFLI + USB_ASSERT_MSG((8 << HWREGB(USB_BASE + MUSB_RXFIFOSZ_OFFSET)) >= g_musb_udc.out_ep[ep_idx].ep_mps, + "Ep %02x fifo is overflow", ep->bEndpointAddress); +#endif + + HWREGH(USB_RXMAP_BASE(ep_idx)) = USB_GET_MAXPACKETSIZE(ep->wMaxPacketSize); + + // + // Allow auto clearing of RxPktRdy when packet of size max packet + // has been unloaded from the FIFO. + // + if (ui32Flags & USB_EP_AUTO_CLEAR) { + ui32Register = USB_RXCSRH1_AUTOCL; + } + // + // Configure the DMA mode. + // + if (ui32Flags & USB_EP_DMA_MODE_1) { + ui32Register |= USB_RXCSRH1_DMAEN | USB_RXCSRH1_DMAMOD; + } else if (ui32Flags & USB_EP_DMA_MODE_0) { + ui32Register |= USB_RXCSRH1_DMAEN; + } + // + // If requested, disable NYET responses for high-speed bulk and + // interrupt endpoints. + // + if (ui32Flags & USB_EP_DIS_NYET) { + ui32Register |= USB_RXCSRH1_DISNYET; + } + + // + // Enable isochronous mode if requested. + // + if (USB_GET_ENDPOINT_TYPE(ep->bmAttributes) == 0x01) { + ui32Register |= USB_RXCSRH1_ISO; + } + + HWREGB(USB_RXCSRH_BASE(ep_idx)) = ui32Register; + + // Reset the Data toggle to zero. + if (HWREGB(USB_RXCSRL_BASE(ep_idx)) & USB_RXCSRL1_RXRDY) + HWREGB(USB_RXCSRL_BASE(ep_idx)) = (USB_RXCSRL1_CLRDT | USB_RXCSRL1_FLUSH); + else + HWREGB(USB_RXCSRL_BASE(ep_idx)) = USB_RXCSRL1_CLRDT; + + HWREGB(USB_TXCSRH_BASE(ep_idx)) &= ~USB_TXCSRH1_MODE; + } else { + g_musb_udc.in_ep[ep_idx].ep_mps = USB_GET_MAXPACKETSIZE(ep->wMaxPacketSize); + g_musb_udc.in_ep[ep_idx].ep_type = USB_GET_ENDPOINT_TYPE(ep->bmAttributes); + g_musb_udc.in_ep[ep_idx].ep_enable = true; + +#ifndef CONFIG_USB_MUSB_SIFLI + USB_ASSERT_MSG((8 << HWREGB(USB_BASE + MUSB_TXFIFOSZ_OFFSET)) >= g_musb_udc.in_ep[ep_idx].ep_mps, + "Ep %02x fifo is overflow", ep->bEndpointAddress); +#endif + + HWREGH(USB_TXMAP_BASE(ep_idx)) = USB_GET_MAXPACKETSIZE(ep->wMaxPacketSize); + + // + // Allow auto setting of TxPktRdy when max packet size has been loaded + // into the FIFO. + // + if (ui32Flags & USB_EP_AUTO_SET) { + ui32Register |= USB_TXCSRH1_AUTOSET; + } + + // + // Configure the DMA mode. + // + if (ui32Flags & USB_EP_DMA_MODE_1) { + ui32Register |= USB_TXCSRH1_DMAEN | USB_TXCSRH1_DMAMOD; + } else if (ui32Flags & USB_EP_DMA_MODE_0) { + ui32Register |= USB_TXCSRH1_DMAEN; + } + + // + // Enable isochronous mode if requested. + // + if (USB_GET_ENDPOINT_TYPE(ep->bmAttributes) == 0x01) { + ui32Register |= USB_TXCSRH1_ISO; + } + + HWREGB(USB_TXCSRH_BASE(ep_idx)) = ui32Register | USB_TXCSRH1_MODE; + + // Reset the Data toggle to zero. + if (HWREGB(USB_TXCSRL_BASE(ep_idx)) & USB_TXCSRL1_TXRDY) + HWREGB(USB_TXCSRL_BASE(ep_idx)) = (USB_TXCSRL1_CLRDT | USB_TXCSRL1_FLUSH); + else + HWREGB(USB_TXCSRL_BASE(ep_idx)) = USB_TXCSRL1_CLRDT; + } + + musb_set_active_ep(old_ep_idx); + + return 0; +} + +int usbd_ep_close(uint8_t busid, const uint8_t ep) +{ + return 0; +} + +int usbd_ep_set_stall(uint8_t busid, const uint8_t ep) +{ + uint8_t ep_idx = USB_EP_GET_IDX(ep); + uint8_t old_ep_idx; + + old_ep_idx = musb_get_active_ep(); + musb_set_active_ep(ep_idx); + + if (USB_EP_DIR_IS_OUT(ep)) { + if (ep_idx == 0x00) { + usb_ep0_state = USB_EP0_STATE_STALL; + HWREGB(USB_TXCSRL_BASE(ep_idx)) |= (USB_CSRL0_STALL | USB_CSRL0_RXRDYC); + } else { + HWREGB(USB_RXCSRL_BASE(ep_idx)) |= USB_RXCSRL1_STALL; + } + } else { + if (ep_idx == 0x00) { + usb_ep0_state = USB_EP0_STATE_STALL; + HWREGB(USB_TXCSRL_BASE(ep_idx)) |= (USB_CSRL0_STALL | USB_CSRL0_RXRDYC); + } else { + HWREGB(USB_TXCSRL_BASE(ep_idx)) |= USB_TXCSRL1_STALL; + } + } + + musb_set_active_ep(old_ep_idx); + return 0; +} + +int usbd_ep_clear_stall(uint8_t busid, const uint8_t ep) +{ + uint8_t ep_idx = USB_EP_GET_IDX(ep); + uint8_t old_ep_idx; + + old_ep_idx = musb_get_active_ep(); + musb_set_active_ep(ep_idx); + + if (USB_EP_DIR_IS_OUT(ep)) { + if (ep_idx == 0x00) { + HWREGB(USB_TXCSRL_BASE(ep_idx)) &= ~USB_CSRL0_STALLED; + } else { + // Clear the stall on an OUT endpoint. + HWREGB(USB_RXCSRL_BASE(ep_idx)) &= ~(USB_RXCSRL1_STALL | USB_RXCSRL1_STALLED); + // Reset the data toggle. + HWREGB(USB_RXCSRL_BASE(ep_idx)) |= USB_RXCSRL1_CLRDT; + } + } else { + if (ep_idx == 0x00) { + HWREGB(USB_TXCSRL_BASE(ep_idx)) &= ~USB_CSRL0_STALLED; + } else { + // Clear the stall on an IN endpoint. + HWREGB(USB_TXCSRL_BASE(ep_idx)) &= ~(USB_TXCSRL1_STALL | USB_TXCSRL1_STALLED); + // Reset the data toggle. + HWREGB(USB_TXCSRL_BASE(ep_idx)) |= USB_TXCSRL1_CLRDT; + } + } + + musb_set_active_ep(old_ep_idx); + return 0; +} + +int usbd_ep_is_stalled(uint8_t busid, const uint8_t ep, uint8_t *stalled) +{ + uint8_t ep_idx = USB_EP_GET_IDX(ep); + uint8_t old_ep_idx; + + old_ep_idx = musb_get_active_ep(); + musb_set_active_ep(ep_idx); + + if (USB_EP_DIR_IS_OUT(ep)) { + if (HWREGB(USB_RXCSRL_BASE(ep_idx)) & USB_RXCSRL1_STALL) { + *stalled = 1; + } else { + *stalled = 0; + } + } else { + if (HWREGB(USB_TXCSRL_BASE(ep_idx)) & USB_TXCSRL1_STALL) { + *stalled = 1; + } else { + *stalled = 0; + } + } + musb_set_active_ep(old_ep_idx); + return 0; +} + +int usbd_ep_start_write(uint8_t busid, const uint8_t ep, const uint8_t *data, uint32_t data_len) +{ + uint8_t ep_idx = USB_EP_GET_IDX(ep); + uint8_t old_ep_idx; + + if (!data && data_len) { + return -1; + } + if (!g_musb_udc.in_ep[ep_idx].ep_enable) { + return -2; + } + + old_ep_idx = musb_get_active_ep(); + musb_set_active_ep(ep_idx); + + if (HWREGB(USB_TXCSRL_BASE(ep_idx)) & USB_TXCSRL1_TXRDY) { + musb_set_active_ep(old_ep_idx); + return -3; + } + + g_musb_udc.in_ep[ep_idx].xfer_buf = (uint8_t *)data; + g_musb_udc.in_ep[ep_idx].xfer_len = data_len; + g_musb_udc.in_ep[ep_idx].actual_xfer_len = 0; + + if (data_len == 0) { + if (ep_idx == 0x00) { + if (g_musb_udc.setup.wLength == 0) { + usb_ep0_state = USB_EP0_STATE_IN_STATUS; + } else { + usb_ep0_state = USB_EP0_STATE_IN_ZLP; + } + HWREGB(USB_TXCSRL_BASE(ep_idx)) = (USB_CSRL0_TXRDY | USB_CSRL0_DATAEND); + } else { + HWREGB(USB_TXCSRL_BASE(ep_idx)) = USB_TXCSRL1_TXRDY; + HWREGH(USB_BASE + MUSB_TXIE_OFFSET) |= (1 << ep_idx); + } + musb_set_active_ep(old_ep_idx); + return 0; + } + data_len = MIN(data_len, g_musb_udc.in_ep[ep_idx].ep_mps); + + musb_write_packet(ep_idx, (uint8_t *)data, data_len); + HWREGH(USB_BASE + MUSB_TXIE_OFFSET) |= (1 << ep_idx); + + if (ep_idx == 0x00) { + usb_ep0_state = USB_EP0_STATE_IN_DATA; + if (data_len < g_musb_udc.in_ep[ep_idx].ep_mps) { + HWREGB(USB_TXCSRL_BASE(ep_idx)) = (USB_CSRL0_TXRDY | USB_CSRL0_DATAEND); + } else { + HWREGB(USB_TXCSRL_BASE(ep_idx)) = USB_CSRL0_TXRDY; + } + } else { + HWREGB(USB_TXCSRL_BASE(ep_idx)) = USB_TXCSRL1_TXRDY; + } + + musb_set_active_ep(old_ep_idx); + return 0; +} + +int usbd_ep_start_read(uint8_t busid, const uint8_t ep, uint8_t *data, uint32_t data_len) +{ + uint8_t ep_idx = USB_EP_GET_IDX(ep); + uint8_t old_ep_idx; + + if (!data && data_len) { + return -1; + } + if (!g_musb_udc.out_ep[ep_idx].ep_enable) { + return -2; + } + + old_ep_idx = musb_get_active_ep(); + musb_set_active_ep(ep_idx); + + g_musb_udc.out_ep[ep_idx].xfer_buf = data; + g_musb_udc.out_ep[ep_idx].xfer_len = data_len; + g_musb_udc.out_ep[ep_idx].actual_xfer_len = 0; + + if (data_len == 0) { + if (ep_idx == 0) { + usb_ep0_state = USB_EP0_STATE_SETUP; + } + musb_set_active_ep(old_ep_idx); + return 0; + } + if (ep_idx == 0) { + usb_ep0_state = USB_EP0_STATE_OUT_DATA; + } else { + HWREGH(USB_BASE + MUSB_RXIE_OFFSET) |= (1 << ep_idx); + } + musb_set_active_ep(old_ep_idx); + return 0; +} + +static void handle_ep0(void) +{ + uint8_t ep_idx = 0; // EP0 index is always 0 + uint8_t ep0_status = HWREGB(USB_TXCSRL_BASE(ep_idx)); + uint16_t read_count; + + if (ep0_status & USB_CSRL0_STALLED) { + HWREGB(USB_TXCSRL_BASE(ep_idx)) &= ~USB_CSRL0_STALLED; + usb_ep0_state = USB_EP0_STATE_SETUP; + return; + } + + if (ep0_status & USB_CSRL0_SETEND) { + HWREGB(USB_TXCSRL_BASE(ep_idx)) = USB_CSRL0_SETENDC; + } + + if (g_musb_udc.dev_addr > 0) { + HWREGB(USB_BASE + MUSB_FADDR_OFFSET) = g_musb_udc.dev_addr; + g_musb_udc.dev_addr = 0; + } + + switch (usb_ep0_state) { + case USB_EP0_STATE_SETUP: + if (ep0_status & USB_CSRL0_RXRDY) { + read_count = HWREGH(USB_RXCOUNT_BASE(ep_idx)); + + if (read_count != 8) { + return; + } + + musb_read_packet(0, (uint8_t *)&g_musb_udc.setup, 8); + if (g_musb_udc.setup.wLength) { + HWREGB(USB_TXCSRL_BASE(ep_idx)) = USB_CSRL0_RXRDYC; + } else { + HWREGB(USB_TXCSRL_BASE(ep_idx)) = (USB_CSRL0_RXRDYC | USB_CSRL0_DATAEND); + } + + usbd_event_ep0_setup_complete_handler(0, (uint8_t *)&g_musb_udc.setup); + } + break; + + case USB_EP0_STATE_IN_DATA: + if (g_musb_udc.in_ep[0].xfer_len > g_musb_udc.in_ep[0].ep_mps) { + g_musb_udc.in_ep[0].actual_xfer_len += g_musb_udc.in_ep[0].ep_mps; + g_musb_udc.in_ep[0].xfer_len -= g_musb_udc.in_ep[0].ep_mps; + } else { + g_musb_udc.in_ep[0].actual_xfer_len += g_musb_udc.in_ep[0].xfer_len; + g_musb_udc.in_ep[0].xfer_len = 0; + } + + usbd_event_ep_in_complete_handler(0, 0x80, g_musb_udc.in_ep[0].actual_xfer_len); + + break; + case USB_EP0_STATE_OUT_DATA: + if (ep0_status & USB_CSRL0_RXRDY) { + read_count = HWREGH(USB_RXCOUNT_BASE(ep_idx)); + + musb_read_packet(0, g_musb_udc.out_ep[0].xfer_buf, read_count); + g_musb_udc.out_ep[0].xfer_buf += read_count; + g_musb_udc.out_ep[0].actual_xfer_len += read_count; + + if (read_count < g_musb_udc.out_ep[0].ep_mps) { + usbd_event_ep_out_complete_handler(0, 0x00, g_musb_udc.out_ep[0].actual_xfer_len); + HWREGB(USB_TXCSRL_BASE(ep_idx)) = (USB_CSRL0_RXRDYC | USB_CSRL0_DATAEND); + usb_ep0_state = USB_EP0_STATE_IN_STATUS; + } else { + HWREGB(USB_TXCSRL_BASE(ep_idx)) = USB_CSRL0_RXRDYC; + } + } + break; + case USB_EP0_STATE_IN_STATUS: + case USB_EP0_STATE_IN_ZLP: + usb_ep0_state = USB_EP0_STATE_SETUP; + usbd_event_ep_in_complete_handler(0, 0x80, 0); + break; + } +} + +void USBD_IRQHandler(uint8_t busid) +{ + uint32_t is; + uint32_t txis; + uint32_t rxis; + uint8_t old_ep_idx; + uint8_t ep_idx; + uint16_t write_count, read_count; + + if (HWREGB(USB_BASE + MUSB_DEVCTL_OFFSET) & USB_DEVCTL_HOST) { + return; + } + + is = HWREGB(USB_BASE + MUSB_IS_OFFSET); + txis = HWREGH(USB_BASE + MUSB_TXIS_OFFSET); + rxis = HWREGH(USB_BASE + MUSB_RXIS_OFFSET); + + HWREGB(USB_BASE + MUSB_IS_OFFSET) = is; + + old_ep_idx = musb_get_active_ep(); + + /* Receive a reset signal from the USB bus */ + if (is & USB_IS_RESET) { + memset(&g_musb_udc, 0, sizeof(struct musb_udc)); + usbd_event_reset_handler(0); + HWREGH(USB_BASE + MUSB_TXIE_OFFSET) = USB_TXIE_EP0; + HWREGH(USB_BASE + MUSB_RXIE_OFFSET) = 0; + + usb_ep0_state = USB_EP0_STATE_SETUP; + } + +#ifdef CONFIG_USBDEV_SOF_ENABLE + if (is & USB_IS_SOF) { + usbd_event_sof_handler(0); + } +#endif + + if (is & USB_IS_RESUME) { + usbd_event_resume_handler(0); + } + + if (is & USB_IS_SUSPEND) { + usbd_event_suspend_handler(0); + } + + txis &= HWREGH(USB_BASE + MUSB_TXIE_OFFSET); + /* Handle EP0 interrupt */ + if (txis & USB_TXIE_EP0) { + HWREGH(USB_BASE + MUSB_TXIS_OFFSET) = USB_TXIE_EP0; + musb_set_active_ep(0); + handle_ep0(); + txis &= ~USB_TXIE_EP0; + } + + ep_idx = 1; + while (txis) { + if (txis & (1 << ep_idx)) { + musb_set_active_ep(ep_idx); + HWREGH(USB_BASE + MUSB_TXIS_OFFSET) = (1 << ep_idx); + if (HWREGB(USB_TXCSRL_BASE(ep_idx)) & USB_TXCSRL1_UNDRN) { + HWREGB(USB_TXCSRL_BASE(ep_idx)) &= ~USB_TXCSRL1_UNDRN; + } + + if (g_musb_udc.in_ep[ep_idx].xfer_len > g_musb_udc.in_ep[ep_idx].ep_mps) { + g_musb_udc.in_ep[ep_idx].xfer_buf += g_musb_udc.in_ep[ep_idx].ep_mps; + g_musb_udc.in_ep[ep_idx].actual_xfer_len += g_musb_udc.in_ep[ep_idx].ep_mps; + g_musb_udc.in_ep[ep_idx].xfer_len -= g_musb_udc.in_ep[ep_idx].ep_mps; + } else { + g_musb_udc.in_ep[ep_idx].xfer_buf += g_musb_udc.in_ep[ep_idx].xfer_len; + g_musb_udc.in_ep[ep_idx].actual_xfer_len += g_musb_udc.in_ep[ep_idx].xfer_len; + g_musb_udc.in_ep[ep_idx].xfer_len = 0; + } + + if (g_musb_udc.in_ep[ep_idx].xfer_len == 0) { + HWREGH(USB_BASE + MUSB_TXIE_OFFSET) &= ~(1 << ep_idx); + usbd_event_ep_in_complete_handler(0, ep_idx | 0x80, g_musb_udc.in_ep[ep_idx].actual_xfer_len); + } else { + write_count = MIN(g_musb_udc.in_ep[ep_idx].xfer_len, g_musb_udc.in_ep[ep_idx].ep_mps); + + musb_write_packet(ep_idx, g_musb_udc.in_ep[ep_idx].xfer_buf, write_count); + HWREGB(USB_TXCSRL_BASE(ep_idx)) = USB_TXCSRL1_TXRDY; + } + + txis &= ~(1 << ep_idx); + } + ep_idx++; + } + + rxis &= HWREGH(USB_BASE + MUSB_RXIE_OFFSET); + ep_idx = 1; + while (rxis) { + if (rxis & (1 << ep_idx)) { + musb_set_active_ep(ep_idx); + HWREGH(USB_BASE + MUSB_RXIS_OFFSET) = (1 << ep_idx); + if (HWREGB(USB_RXCSRL_BASE(ep_idx)) & USB_RXCSRL1_RXRDY) { + read_count = HWREGH(USB_RXCOUNT_BASE(ep_idx)); + + musb_read_packet(ep_idx, g_musb_udc.out_ep[ep_idx].xfer_buf, read_count); + HWREGB(USB_RXCSRL_BASE(ep_idx)) &= ~(USB_RXCSRL1_RXRDY); + + g_musb_udc.out_ep[ep_idx].xfer_buf += read_count; + g_musb_udc.out_ep[ep_idx].actual_xfer_len += read_count; + g_musb_udc.out_ep[ep_idx].xfer_len -= read_count; + + if ((read_count < g_musb_udc.out_ep[ep_idx].ep_mps) || (g_musb_udc.out_ep[ep_idx].xfer_len == 0)) { + HWREGH(USB_BASE + MUSB_RXIE_OFFSET) &= ~(1 << ep_idx); + usbd_event_ep_out_complete_handler(0, ep_idx, g_musb_udc.out_ep[ep_idx].actual_xfer_len); + } else { + } + } + + rxis &= ~(1 << ep_idx); + } + ep_idx++; + } + + musb_set_active_ep(old_ep_idx); +} diff --git a/kernel/cherryusb/port/musb/usb_glue_bk.c b/kernel/cherryusb/port/musb/usb_glue_bk.c new file mode 100644 index 0000000..67117e1 --- /dev/null +++ b/kernel/cherryusb/port/musb/usb_glue_bk.c @@ -0,0 +1,326 @@ +/* + * Copyright (c) 2024, sakumisu + * + * SPDX-License-Identifier: Apache-2.0 + */ +#include "sys_driver.h" +#include "gpio_driver.h" +#include +#include +#include +#include "bk_misc.h" +#include "usbd_core.h" +#include "usbh_core.h" +#include "usb_musb_reg.h" + +#define USB_BASE_ADDR SOC_USB_REG_BASE + +#if (CONFIG_SOC_BK7271) +#define REG_AHB2_USB_OTG_CFG (*((volatile unsigned char *)(USB_BASE_ADDR + 0x80))) +#define REG_AHB2_USB_DMA_ENDP (*((volatile unsigned char *)(USB_BASE_ADDR + 0x84))) +#define REG_AHB2_USB_VTH (*((volatile unsigned char *)(USB_BASE_ADDR + 0x88))) +#define REG_AHB2_USB_GEN (*((volatile unsigned char *)(USB_BASE_ADDR + 0x8C))) +#define REG_AHB2_USB_STAT (*((volatile unsigned char *)(USB_BASE_ADDR + 0x90))) +#define REG_AHB2_USB_INT (*((volatile unsigned char *)(USB_BASE_ADDR + 0x94))) +#define REG_AHB2_USB_RESET (*((volatile unsigned char *)(USB_BASE_ADDR + 0x98))) +#define REG_AHB2_USB_DEV_CFG (*((volatile unsigned char *)(USB_BASE_ADDR + 0x9C))) +#elif (CONFIG_SOC_BK7256XX) +#define REG_AHB2_USB_OTG_CFG (*((volatile unsigned char *)(USB_BASE_ADDR + 0x280))) +#define REG_AHB2_USB_DMA_ENDP (*((volatile unsigned char *)(USB_BASE_ADDR + 0x284))) +#define REG_AHB2_USB_VTH (*((volatile unsigned char *)(USB_BASE_ADDR + 0x288))) +#define REG_AHB2_USB_GEN (*((volatile unsigned char *)(USB_BASE_ADDR + 0x28C))) +#define REG_AHB2_USB_STAT (*((volatile unsigned char *)(USB_BASE_ADDR + 0x290))) +#define REG_AHB2_USB_INT (*((volatile unsigned char *)(USB_BASE_ADDR + 0x294))) +#define REG_AHB2_USB_RESET (*((volatile unsigned char *)(USB_BASE_ADDR + 0x298))) +#define REG_AHB2_USB_DEV_CFG (*((volatile unsigned char *)(USB_BASE_ADDR + 0x29C))) +#elif (CONFIG_SOC_BK7236XX) || (CONFIG_SOC_BK7239XX) || (CONFIG_SOC_BK7286XX) +#define REG_AHB2_USB_DEVICE_ID (*((volatile unsigned char *)(USB_BASE_ADDR + 0x280))) +#define REG_AHB2_USB_VERSION_ID (*((volatile unsigned char *)(USB_BASE_ADDR + 0x284))) +#define REG_AHB2_USB_GLOBAL_CTRL (*((volatile unsigned char *)(USB_BASE_ADDR + 0x288))) +#define REG_AHB2_USB_DEVICE_STATUS (*((volatile unsigned char *)(USB_BASE_ADDR + 0x28c))) +#define REG_AHB2_USB_OTG_CFG (*((volatile unsigned char *)(USB_BASE_ADDR + 0x290))) +#define REG_AHB2_USB_DMA_ENDP (*((volatile unsigned char *)(USB_BASE_ADDR + 0x294))) +#define REG_AHB2_USB_VTH (*((volatile unsigned char *)(USB_BASE_ADDR + 0x298))) +#define REG_AHB2_USB_GEN (*((volatile unsigned char *)(USB_BASE_ADDR + 0x29C))) +#define REG_AHB2_USB_STAT (*((volatile unsigned char *)(USB_BASE_ADDR + 0x2A0))) +#define REG_AHB2_USB_INT (*((volatile unsigned char *)(USB_BASE_ADDR + 0x2A4))) +#define REG_AHB2_USB_RESET (*((volatile unsigned char *)(USB_BASE_ADDR + 0x2A8))) +#define REG_AHB2_USB_DEV_CFG (*((volatile unsigned char *)(USB_BASE_ADDR + 0x2AC))) + +#define REG_USB_USR_700 (*((volatile unsigned long *)(USB_BASE_ADDR + 0x700))) +#define REG_USB_USR_704 (*((volatile unsigned long *)(USB_BASE_ADDR + 0x704))) +#define REG_USB_USR_708 (*((volatile unsigned long *)(USB_BASE_ADDR + 0x708))) +#define REG_USB_USR_70C (*((volatile unsigned long *)(USB_BASE_ADDR + 0x70C))) +#define REG_USB_USR_710 (*((volatile unsigned long *)(USB_BASE_ADDR + 0x710))) +#define REG_USB_USR_714 (*((volatile unsigned long *)(USB_BASE_ADDR + 0x714))) +#define REG_USB_PHY_00 (*((volatile unsigned long *)(USB_BASE_ADDR + 0x400))) +#define REG_USB_PHY_01 (*((volatile unsigned long *)(USB_BASE_ADDR + 0x404))) +#endif + +#define USB_DP_CAPABILITY_VALUE (0xF) +#define USB_DN_CAPABILITY_VALUE (0xF) + +#define NANENG_PHY_FC_REG01 (0x01 * 4) +#define NANENG_PHY_FC_REG02 (0x02 * 4) +#define NANENG_PHY_FC_REG03 (0x03 * 4) +#define NANENG_PHY_FC_REG04 (0x04 * 4) +#define NANENG_PHY_FC_REG05 (0x05 * 4) +#define NANENG_PHY_FC_REG06 (0x06 * 4) +#define NANENG_PHY_FC_REG07 (0x07 * 4) +#define NANENG_PHY_FC_REG08 (0x08 * 4) +#define NANENG_PHY_FC_REG09 (0x09 * 4) +#define NANENG_PHY_FC_REG0A (0x0A * 4) +#define NANENG_PHY_FC_REG0B (0x0B * 4) +#define NANENG_PHY_FC_REG0C (0x0C * 4) +#define NANENG_PHY_FC_REG0D (0x0D * 4) +#define NANENG_PHY_FC_REG0E (0x0E * 4) +#define NANENG_PHY_FC_REG0F (0x0F * 4) +#define NANENG_PHY_FC_REG0F_BYTE 0x0F + +#define NANENG_PHY_FC_REG10 (0x10 * 4) +#define NANENG_PHY_FC_REG11 (0x11 * 4) +#define NANENG_PHY_FC_REG12 (0x12 * 4) +#define NANENG_PHY_FC_REG13 (0x13 * 4) +#define NANENG_PHY_FC_REG14 (0x14 * 4) +#define NANENG_PHY_FC_REG15 (0x15 * 4) +#define NANENG_PHY_FC_REG16 (0x16 * 4) +#define NANENG_PHY_FC_REG17 (0x17 * 4) +#define NANENG_PHY_FC_REG18 (0x18 * 4) +#define NANENG_PHY_FC_REG19 (0x19 * 4) +#define NANENG_PHY_FC_REG1A (0x1A * 4) +#define NANENG_PHY_FC_REG1B (0x1B * 4) +#define NANENG_PHY_FC_REG1C (0x1C * 4) +#define NANENG_PHY_FC_REG1D (0x1D * 4) +#define NANENG_PHY_FC_REG1E (0x1E * 4) +#define NANENG_PHY_FC_REG1F (0x1F * 4) + +#if CONFIG_USB_MUSB_EP_NUM != 8 +#error beken chips only support 8 endpoints +#endif + +#if CONFIG_USB_MUSB_PIPE_NUM != 8 +#error beken chips only support 8 pipes +#endif + +// clang-format off +static struct musb_fifo_cfg musb_device_table[] = { +{ .ep_num = 0, .style = FIFO_TXRX, .maxpacket = 64, }, +{ .ep_num = 1, .style = FIFO_TX, .maxpacket = 1024, }, +{ .ep_num = 1, .style = FIFO_RX, .maxpacket = 1024, }, +{ .ep_num = 2, .style = FIFO_TX, .maxpacket = 512, }, +{ .ep_num = 2, .style = FIFO_RX, .maxpacket = 512, }, +{ .ep_num = 3, .style = FIFO_TX, .maxpacket = 512, }, +{ .ep_num = 3, .style = FIFO_RX, .maxpacket = 512, }, +{ .ep_num = 4, .style = FIFO_TX, .maxpacket = 512, }, +{ .ep_num = 4, .style = FIFO_RX, .maxpacket = 512, }, +{ .ep_num = 5, .style = FIFO_TX, .maxpacket = 512, }, +{ .ep_num = 5, .style = FIFO_RX, .maxpacket = 512, }, +{ .ep_num = 6, .style = FIFO_TXRX, .maxpacket = 512, }, +{ .ep_num = 7, .style = FIFO_TXRX, .maxpacket = 512, } +}; + +static struct musb_fifo_cfg musb_host_table[] = { +{ .ep_num = 0, .style = FIFO_TXRX, .maxpacket = 64, }, +{ .ep_num = 1, .style = FIFO_TX, .maxpacket = 1024, }, +{ .ep_num = 1, .style = FIFO_RX, .maxpacket = 1024, }, +{ .ep_num = 2, .style = FIFO_TX, .maxpacket = 512, }, +{ .ep_num = 2, .style = FIFO_RX, .maxpacket = 512, }, +{ .ep_num = 3, .style = FIFO_TX, .maxpacket = 512, }, +{ .ep_num = 3, .style = FIFO_RX, .maxpacket = 512, }, +{ .ep_num = 4, .style = FIFO_TX, .maxpacket = 512, }, +{ .ep_num = 4, .style = FIFO_RX, .maxpacket = 512, }, +{ .ep_num = 5, .style = FIFO_TX, .maxpacket = 512, }, +{ .ep_num = 5, .style = FIFO_RX, .maxpacket = 512, }, +{ .ep_num = 6, .style = FIFO_TXRX, .maxpacket = 512, }, +{ .ep_num = 7, .style = FIFO_TXRX, .maxpacket = 512, } +}; +// clang-format on + +uint8_t usbd_get_musb_fifo_cfg(struct musb_fifo_cfg **cfg) +{ + *cfg = musb_device_table; + return sizeof(musb_device_table) / sizeof(musb_device_table[0]); +} + +uint8_t usbh_get_musb_fifo_cfg(struct musb_fifo_cfg **cfg) +{ + *cfg = musb_host_table; + return sizeof(musb_host_table) / sizeof(musb_host_table[0]); +} + +uint32_t usb_get_musb_ram_size(void) +{ + return 8192; +} + +extern void USBD_IRQHandler(uint8_t busid); + +void USBD_IRQ(void) +{ + USBD_IRQHandler(0); +} + +static void bk_analog_layer_usb_sys_related_ops(uint32_t usb_mode, bool ops) +{ + extern void delay(INT32 num); + +#if 0 + sys_drv_usb_analog_phy_en(ops, NULL); + sys_drv_usb_analog_speed_en(ops, NULL); + sys_drv_usb_analog_ckmcu_en(ops, NULL); +#endif + if (ops) { + sys_drv_usb_clock_ctrl(true, NULL); + delay(100); +#if 0 + sys_drv_usb_analog_deepsleep_en(false); +#endif + sys_drv_usb_analog_dp_capability(USB_DP_CAPABILITY_VALUE); + sys_drv_usb_analog_dn_capability(USB_DN_CAPABILITY_VALUE); + if (!sys_hal_psram_ldo_status()) { + sys_drv_psram_ldo_enable(1); + } + sys_drv_usb_analog_phy_en(1, NULL); + + if (usb_mode == 0) { + REG_USB_USR_708 = 0x0; + REG_USB_USR_710 &= ~(0x1 << 7); + delay(100); + + REG_USB_USR_710 |= (0x1 << 15); + //REG_USB_USR_710 |= (0x1<<14); + REG_USB_USR_710 |= (0x1 << 16); + REG_USB_USR_710 |= (0x1 << 17); + REG_USB_USR_710 |= (0x1 << 18); + REG_USB_USR_710 |= (0x1 << 19); + REG_USB_USR_710 &= ~(0x1 << 20); + REG_USB_USR_710 |= (0x1 << 21); + REG_USB_USR_710 |= (0x0 << 0); + REG_USB_USR_710 |= (0x1 << 5); + REG_USB_USR_710 |= (0x1 << 6); + REG_USB_USR_710 |= (0x1 << 9); + REG_USB_USR_710 |= (0x1 << 10); + REG_USB_USR_710 |= (0x1 << 1); + + REG_USB_USR_710 |= (0x1 << 7); + REG_USB_USR_708 = 0x1; +#if 0 + REG_USB_PHY_00 = 0x08; + REG_USB_PHY_01 = 0x02; + REG_USB_USR_710 |= (0x1<< 8); + while(1){ + reg = REG_USB_USR_70C; + if(reg & 0x100){ + USB_DRIVER_LOGI("SelfTest Fin!\r\n"); + USB_DRIVER_LOGI("test end!\r\n"); + break; + } else { + USB_DRIVER_LOGI("70c_reg:0x%x\r\n", reg); + delay(10000); + } + } + REG_USB_PHY_00 &= ~0x08; + REG_USB_PHY_01 &= ~0x02; + REG_USB_USR_710 &= ~(0x1<< 8); +#endif + } else { + REG_USB_USR_710 |= (0x1 << 15); + REG_USB_USR_710 |= (0x1 << 14); + REG_USB_USR_710 |= (0x1 << 16); + REG_USB_USR_710 |= (0x1 << 17); + REG_USB_USR_710 |= (0x1 << 18); + REG_USB_USR_710 |= (0x1 << 19); + REG_USB_USR_710 &= ~(0x1 << 20); + REG_USB_USR_710 |= (0x1 << 21); + REG_USB_USR_710 |= (0x0 << 0); + REG_USB_USR_710 |= (0x1 << 5); + REG_USB_USR_710 |= (0x1 << 6); + REG_USB_USR_710 |= (0x1 << 9); + REG_USB_USR_710 |= (0x1 << 10); + REG_USB_USR_710 |= (0x1 << 7); + + REG_USB_USR_708 = 0x1; + } + } else { + sys_drv_usb_analog_phy_en(0, NULL); + sys_drv_usb_clock_ctrl(false, NULL); + } +} + +void usb_dc_low_level_init(void) +{ +#if CONFIG_SYS_CPU0 + bk_pm_module_vote_sleep_ctrl(PM_SLEEP_MODULE_NAME_USB_1, 0x0, 0x0); +#endif + bk_analog_layer_usb_sys_related_ops(1, true); + bk_gpio_set_output_high(CONFIG_USB_VBAT_CONTROL_GPIO_ID); + + bk_pm_module_vote_cpu_freq(PM_DEV_ID_USB_1, PM_CPU_FRQ_120M); + + sys_hal_usb_analog_phy_en(true); + + sys_drv_usb_clock_ctrl(true, NULL); + sys_drv_int_enable(USB_INTERRUPT_CTRL_BIT); + + bk_int_isr_register(INT_SRC_USB, USBD_IRQ, NULL); + bk_int_set_priority(INT_SRC_USB, 2); +} + +void usb_dc_low_level_deinit(void) +{ + bk_pm_module_vote_cpu_freq(PM_DEV_ID_USB_1, PM_CPU_FRQ_DEFAULT); + sys_hal_usb_analog_phy_en(false); + sys_drv_usb_clock_ctrl(false, NULL); + sys_drv_int_disable(USB_INTERRUPT_CTRL_BIT); + bk_int_isr_unregister(INT_SRC_USB); + bk_analog_layer_usb_sys_related_ops(1, false); + sys_drv_dev_clk_pwr_up(CLK_PWR_ID_USB_1, CLK_PWR_CTRL_PWR_DOWN); +} + +void usbd_musb_delay_ms(uint8_t ms) +{ + /* implement later */ +} + +extern void USBH_IRQHandler(uint8_t busid); + +void USBH_IRQ(void) +{ + USBH_IRQHandler(0); +} + +#define NANENG_PHY_CFG 1 +#define USB_PHY_BASE (SOC_USB_REG_BASE + 0x400) + +#define HWREG(x) \ + (*((volatile uint32_t *)(x))) +#define HWREGH(x) \ + (*((volatile uint16_t *)(x))) +#define HWREGB(x) \ + (*((volatile uint8_t *)(x))) + +void usb_hc_low_level_init(struct usbh_bus *bus) +{ +#if CONFIG_SYS_CPU0 + bk_pm_module_vote_sleep_ctrl(PM_SLEEP_MODULE_NAME_USB_1, 0x0, 0x0); +#endif + bk_analog_layer_usb_sys_related_ops(0, true); + bk_gpio_set_output_high(CONFIG_USB_VBAT_CONTROL_GPIO_ID); + +#if NANENG_PHY_CFG + //NANENG_PHY_CFG_HSRX_TEST + HWREGB(USB_PHY_BASE + NANENG_PHY_FC_REG0F) |= (0x1 << 4); + //disconnect value 640mv + HWREGB(USB_PHY_BASE + NANENG_PHY_FC_REG0B) = 0x7C; +#endif + bk_int_isr_register(INT_SRC_USB, USBH_IRQ, NULL); + sys_drv_int_enable(USB_INTERRUPT_CTRL_BIT); +} + +void usb_hc_low_level_deinit(struct usbh_bus *bus) +{ + sys_drv_int_disable(USB_INTERRUPT_CTRL_BIT); + bk_int_isr_unregister(INT_SRC_USB); + sys_drv_dev_clk_pwr_up(CLK_PWR_ID_USB_1, CLK_PWR_CTRL_PWR_DOWN); + bk_analog_layer_usb_sys_related_ops(0, false); +} \ No newline at end of file diff --git a/kernel/cherryusb/port/musb/usb_glue_es.c b/kernel/cherryusb/port/musb/usb_glue_es.c new file mode 100644 index 0000000..2d4e509 --- /dev/null +++ b/kernel/cherryusb/port/musb/usb_glue_es.c @@ -0,0 +1,58 @@ +/* + * Copyright (c) 2024, sakumisu + * + * SPDX-License-Identifier: Apache-2.0 + */ +#include "usb_config.h" +#include "stdint.h" +#include "usb_musb_reg.h" + +#if CONFIG_USB_MUSB_EP_NUM != 6 +#error es32 chips only support 6 endpoints +#endif + +#if CONFIG_USB_MUSB_PIPE_NUM != 6 +#error es32 chips only support 6 pipes +#endif + +// clang-format off +static struct musb_fifo_cfg musb_device_table[] = { +{ .ep_num = 0, .style = FIFO_TXRX, .maxpacket = 64, }, +{ .ep_num = 1, .style = FIFO_TXRX, .maxpacket = 1024, }, +{ .ep_num = 2, .style = FIFO_TXRX, .maxpacket = 512, }, +{ .ep_num = 3, .style = FIFO_TXRX, .maxpacket = 512, }, +{ .ep_num = 4, .style = FIFO_TXRX, .maxpacket = 512, }, +{ .ep_num = 5, .style = FIFO_TXRX, .maxpacket = 512, }, +}; + +static struct musb_fifo_cfg musb_host_table[] = { +{ .ep_num = 0, .style = FIFO_TXRX, .maxpacket = 64, }, +{ .ep_num = 1, .style = FIFO_TXRX, .maxpacket = 1024, }, +{ .ep_num = 2, .style = FIFO_TXRX, .maxpacket = 512, }, +{ .ep_num = 3, .style = FIFO_TXRX, .maxpacket = 512, }, +{ .ep_num = 4, .style = FIFO_TXRX, .maxpacket = 512, }, +{ .ep_num = 5, .style = FIFO_TXRX, .maxpacket = 512, }, +}; +// clang-format on + +uint8_t usbd_get_musb_fifo_cfg(struct musb_fifo_cfg **cfg) +{ + *cfg = musb_device_table; + return sizeof(musb_device_table) / sizeof(musb_device_table[0]); +} + +uint8_t usbh_get_musb_fifo_cfg(struct musb_fifo_cfg **cfg) +{ + *cfg = musb_host_table; + return sizeof(musb_host_table) / sizeof(musb_host_table[0]); +} + +uint32_t usb_get_musb_ram_size(void) +{ + return 4096; +} + +void usbd_musb_delay_ms(uint8_t ms) +{ + /* implement later */ +} diff --git a/kernel/cherryusb/port/musb/usb_glue_sifli.c b/kernel/cherryusb/port/musb/usb_glue_sifli.c new file mode 100644 index 0000000..0019482 --- /dev/null +++ b/kernel/cherryusb/port/musb/usb_glue_sifli.c @@ -0,0 +1,162 @@ +/* + * Copyright (c) 2025, sakumisu + * + * SPDX-License-Identifier: Apache-2.0 + */ +#include "usbd_core.h" +#include "usbh_core.h" +#include "usb_musb_reg.h" + +#undef USB_POWER_SOFTCONN +#undef USB_DEVCTL_FSDEV +#undef USB_DEVCTL_LSDEV +#undef USB_DEVCTL_SESSION +#undef USB_POWER_HSENAB +#undef USB_POWER_HSMODE +#undef USB_POWER_RESET +#undef USB_POWER_RESUME + +#ifndef CONFIG_USB_MUSB_SIFLI +#error must define CONFIG_USB_MUSB_SIFLI when use sifli chips +#endif + +#include "bf0_hal.h" + +uint8_t usbd_get_musb_fifo_cfg(struct musb_fifo_cfg **cfg) +{ + *cfg = NULL; // No FIFO configuration for this implementation, readonly + return 0; +} + +uint8_t usbh_get_musb_fifo_cfg(struct musb_fifo_cfg **cfg) +{ + *cfg = NULL; // No FIFO configuration for this implementation, readonly + return 0; +} + +uint32_t usb_get_musb_ram_size(void) +{ + return 0xFFFF; // No specific RAM size for this implementation +} + +void usbd_musb_delay_ms(uint8_t ms) +{ + /* implement later */ +} + +#ifdef PKG_CHERRYUSB_DEVICE +void usb_dc_low_level_init(uint8_t busid) +{ + HAL_RCC_EnableModule(RCC_MOD_USBC); + +#ifdef SOC_SF32LB58X + //hwp_usbc->utmicfg12 = hwp_usbc->utmicfg12 | 0x3; //set xo_clk_sel + hwp_usbc->ldo25 = hwp_usbc->ldo25 | 0xa; //set psw_en and ldo25_en + HAL_Delay(1); + hwp_usbc->swcntl3 = 0x1; //set utmi_en for USB2.0 + hwp_usbc->usbcfg = hwp_usbc->usbcfg | 0x40; //enable usb PLL. +#elif defined(SOC_SF32LB56X) || defined(SOC_SF32LB52X) + hwp_hpsys_cfg->USBCR |= HPSYS_CFG_USBCR_DM_PD | HPSYS_CFG_USBCR_DP_EN | HPSYS_CFG_USBCR_USB_EN; +#elif defined(SOC_SF32LB55X) + hwp_hpsys_cfg->USBCR |= HPSYS_CFG_USBCR_DM_PD | HPSYS_CFG_USBCR_USB_EN; +#endif +#ifndef SOC_SF32LB55X + hwp_usbc->usbcfg |= (USB_USBCFG_AVALID | USB_USBCFG_AVALID_DR); + hwp_usbc->dpbrxdisl = 0xFE; + hwp_usbc->dpbtxdisl = 0xFE; +#endif + NVIC_EnableIRQ(USBC_IRQn); + __HAL_SYSCFG_Enable_USB(); +} + +void usb_dc_low_level_deinit(uint8_t busid) +{ + NVIC_DisableIRQ(USBC_IRQn); +#ifdef SOC_SF32LB58X + hwp_usbc->usbcfg &= ~0x40; // Disable usb PLL. + hwp_usbc->swcntl3 = 0x0; + hwp_usbc->ldo25 &= ~0xa; // Disable psw_en and ldo25_en +#elif defined(SOC_SF32LB56X) || defined(SOC_SF32LB52X) + hwp_hpsys_cfg->USBCR &= ~(HPSYS_CFG_USBCR_DM_PD | HPSYS_CFG_USBCR_DP_EN | HPSYS_CFG_USBCR_USB_EN); +#elif defined(SOC_SF32LB55X) + hwp_hpsys_cfg->USBCR &= ~(HPSYS_CFG_USBCR_DM_PD | HPSYS_CFG_USBCR_USB_EN); +#endif + /* reset USB to make DP change to PULLDOWN state */ + hwp_hpsys_rcc->RSTR2 |= HPSYS_RCC_RSTR2_USBC; + HAL_Delay_us(100); + hwp_hpsys_rcc->RSTR2 &= ~HPSYS_RCC_RSTR2_USBC; + HAL_RCC_DisableModule(RCC_MOD_USBC); +} +#endif + +#ifdef PKG_CHERRYUSB_HOST +void usb_hc_low_level_init(struct usbh_bus *bus) +{ + HAL_RCC_EnableModule(RCC_MOD_USBC); + +#ifdef SOC_SF32LB58X + //hwp_usbc->utmicfg12 = hwp_usbc->utmicfg12 | 0x3; //set xo_clk_sel + hwp_usbc->ldo25 = hwp_usbc->ldo25 | 0xa; //set psw_en and ldo25_en + HAL_Delay(1); + hwp_usbc->swcntl3 = 0x1; //set utmi_en for USB2.0 + hwp_usbc->usbcfg = hwp_usbc->usbcfg | 0x40; //enable usb PLL. +#elif defined(SOC_SF32LB56X) || defined(SOC_SF32LB52X) + hwp_hpsys_cfg->USBCR |= HPSYS_CFG_USBCR_DM_PD | HPSYS_CFG_USBCR_DP_EN | HPSYS_CFG_USBCR_USB_EN; +#elif defined(SOC_SF32LB55X) + hwp_hpsys_cfg->USBCR |= HPSYS_CFG_USBCR_DM_PD | HPSYS_CFG_USBCR_USB_EN; +#endif +#ifndef SOC_SF32LB55X + hwp_usbc->usbcfg |= (USB_USBCFG_AVALID | USB_USBCFG_AVALID_DR); + hwp_usbc->dpbrxdisl = 0xFE; + hwp_usbc->dpbtxdisl = 0xFE; +#endif + __HAL_SYSCFG_Enable_USB(); + hwp_usbc->usbcfg &= 0xEF; + hwp_usbc->dbgl = 0x80; + + NVIC_EnableIRQ(USBC_IRQn); +} + +void usb_hc_low_level_deinit(struct usbh_bus *bus) +{ + NVIC_DisableIRQ(USBC_IRQn); +#ifdef SOC_SF32LB58X + hwp_usbc->usbcfg &= ~0x40; // Disable usb PLL. + hwp_usbc->swcntl3 = 0x0; + hwp_usbc->ldo25 &= ~0xa; // Disable psw_en and ldo25_en +#elif defined(SOC_SF32LB56X) || defined(SOC_SF32LB52X) + hwp_hpsys_cfg->USBCR &= ~(HPSYS_CFG_USBCR_DM_PD | HPSYS_CFG_USBCR_DP_EN | HPSYS_CFG_USBCR_USB_EN); +#elif defined(SOC_SF32LB55X) + hwp_hpsys_cfg->USBCR &= ~(HPSYS_CFG_USBCR_DM_PD | HPSYS_CFG_USBCR_USB_EN); +#endif + /* reset USB to make DP change to PULLDOWN state */ + hwp_hpsys_rcc->RSTR2 |= HPSYS_RCC_RSTR2_USBC; + HAL_Delay_us(100); + hwp_hpsys_rcc->RSTR2 &= ~HPSYS_RCC_RSTR2_USBC; + HAL_RCC_DisableModule(RCC_MOD_USBC); +} + +void musb_reset_prev(void) +{ +#if defined(SF32LB58X) + hwp_usbc->rsvd0 = 0xc; //58 +#endif +} + +void musb_reset_post(void) +{ +#if defined(SF32LB58X) + hwp_usbc->rsvd0 = 0x0; //58 +#endif +} +#endif + +void USBC_IRQHandler(void) +{ +#ifdef PKG_CHERRYUSB_DEVICE + USBD_IRQHandler(0); +#endif +#ifdef PKG_CHERRYUSB_HOST + USBH_IRQHandler(0); +#endif +} \ No newline at end of file diff --git a/kernel/cherryusb/port/musb/usb_glue_sunxi.c b/kernel/cherryusb/port/musb/usb_glue_sunxi.c new file mode 100644 index 0000000..6a12bab --- /dev/null +++ b/kernel/cherryusb/port/musb/usb_glue_sunxi.c @@ -0,0 +1,64 @@ +/* + * Copyright (c) 2024, sakumisu + * + * SPDX-License-Identifier: Apache-2.0 + */ +#include "usb_config.h" +#include "stdint.h" +#include "usb_musb_reg.h" + +#ifndef CONFIG_USB_MUSB_SUNXI +#error must define CONFIG_USB_MUSB_SUNXI when use sunxi chips +#endif + +#if CONFIG_USB_MUSB_EP_NUM != 4 +#error sunxi chips only support 4 endpoints +#endif + +#if CONFIG_USB_MUSB_PIPE_NUM != 4 +#error sunxi chips only support 4 pipes +#endif + +// clang-format off +static struct musb_fifo_cfg musb_device_table[] = { +{ .ep_num = 0, .style = FIFO_TXRX, .maxpacket = 64, }, +{ .ep_num = 1, .style = FIFO_TX, .maxpacket = 1024, }, +{ .ep_num = 1, .style = FIFO_RX, .maxpacket = 1024, }, +{ .ep_num = 2, .style = FIFO_TX, .maxpacket = 512, }, +{ .ep_num = 2, .style = FIFO_RX, .maxpacket = 512, }, +{ .ep_num = 3, .style = FIFO_TX, .maxpacket = 512, }, +{ .ep_num = 3, .style = FIFO_RX, .maxpacket = 512, }, +}; + +static struct musb_fifo_cfg musb_host_table[] = { +{ .ep_num = 0, .style = FIFO_TXRX, .maxpacket = 64, }, +{ .ep_num = 1, .style = FIFO_TX, .maxpacket = 1024, }, +{ .ep_num = 1, .style = FIFO_RX, .maxpacket = 1024, }, +{ .ep_num = 2, .style = FIFO_TX, .maxpacket = 512, }, +{ .ep_num = 2, .style = FIFO_RX, .maxpacket = 512, }, +{ .ep_num = 3, .style = FIFO_TX, .maxpacket = 512, }, +{ .ep_num = 3, .style = FIFO_RX, .maxpacket = 512, }, +}; +// clang-format on + +uint8_t usbd_get_musb_fifo_cfg(struct musb_fifo_cfg **cfg) +{ + *cfg = musb_device_table; + return sizeof(musb_device_table) / sizeof(musb_device_table[0]); +} + +uint8_t usbh_get_musb_fifo_cfg(struct musb_fifo_cfg **cfg) +{ + *cfg = musb_host_table; + return sizeof(musb_host_table) / sizeof(musb_host_table[0]); +} + +uint32_t usb_get_musb_ram_size(void) +{ + return 8192; +} + +void usbd_musb_delay_ms(uint8_t ms) +{ + /* implement later */ +} diff --git a/kernel/cherryusb/port/musb/usb_glue_ti.c b/kernel/cherryusb/port/musb/usb_glue_ti.c new file mode 100644 index 0000000..576a517 --- /dev/null +++ b/kernel/cherryusb/port/musb/usb_glue_ti.c @@ -0,0 +1,163 @@ +/* + * Copyright (c) 2026, sakumisu + * Copyright (c) 2026, MDLZCOOL + * + * SPDX-License-Identifier: Apache-2.0 + */ +#include "usbd_core.h" +#include "usbh_core.h" +#include "usb_musb_reg.h" + +#include "inc/hw_memmap.h" +#include "inc/hw_types.h" +#include "inc/hw_ints.h" +#include "inc/hw_gpio.h" +#include "inc/hw_sysctl.h" +#include "inc/hw_usb.h" +#include "driverlib/sysctl.h" +#include "driverlib/gpio.h" +#include "driverlib/interrupt.h" +#include "driverlib/pin_map.h" +#include "driverlib/rom.h" + +#define TM4C_MUSB_RAM_SIZE 4096 + +// clang-format off +static struct musb_fifo_cfg musb_device_table[] = { +{ .ep_num = 0, .style = FIFO_TXRX, .maxpacket = 64, }, +{ .ep_num = 1, .style = FIFO_TXRX, .maxpacket = 1024, }, +{ .ep_num = 2, .style = FIFO_TXRX, .maxpacket = 1024, }, +{ .ep_num = 3, .style = FIFO_TXRX, .maxpacket = 1024, }, +{ .ep_num = 4, .style = FIFO_TXRX, .maxpacket = 512, }, +{ .ep_num = 5, .style = FIFO_TXRX, .maxpacket = 256, }, +{ .ep_num = 6, .style = FIFO_TXRX, .maxpacket = 128, }, +{ .ep_num = 7, .style = FIFO_TXRX, .maxpacket = 64, }, +}; + +static struct musb_fifo_cfg musb_host_table[] = { +{ .ep_num = 0, .style = FIFO_TXRX, .maxpacket = 64, }, +{ .ep_num = 1, .style = FIFO_TXRX, .maxpacket = 1024, }, +{ .ep_num = 2, .style = FIFO_TXRX, .maxpacket = 1024, }, +{ .ep_num = 3, .style = FIFO_TXRX, .maxpacket = 1024, }, +{ .ep_num = 4, .style = FIFO_TXRX, .maxpacket = 512, }, +{ .ep_num = 5, .style = FIFO_TXRX, .maxpacket = 256, }, +{ .ep_num = 6, .style = FIFO_TXRX, .maxpacket = 128, }, +{ .ep_num = 7, .style = FIFO_TXRX, .maxpacket = 64, }, +}; +// clang-format on + +static void (*g_usb_irq_handler)(uint8_t busid) = NULL; + +extern void USBH_IRQHandler(uint8_t busid); +extern void USBD_IRQHandler(uint8_t busid); + +__WEAK void USBD_IRQHandler(uint8_t busid) +{ + (void)busid; +} + +__WEAK void USBH_IRQHandler(uint8_t busid) +{ + (void)busid; +} + +void USB0_Handler(void) +{ + if (g_usb_irq_handler) { + g_usb_irq_handler(0); + } +} + +uint8_t usbd_get_musb_fifo_cfg(struct musb_fifo_cfg **cfg) +{ + *cfg = musb_device_table; + return sizeof(musb_device_table) / sizeof(musb_device_table[0]); +} + +uint8_t usbh_get_musb_fifo_cfg(struct musb_fifo_cfg **cfg) +{ + *cfg = musb_host_table; + return sizeof(musb_host_table) / sizeof(musb_host_table[0]); +} + +uint32_t usb_get_musb_ram_size(void) +{ + return TM4C_MUSB_RAM_SIZE; +} + +void usbd_musb_delay_ms(uint8_t ms) +{ + /* implement later */ +} + +void usb_dc_low_level_init(void) +{ + SysCtlPeripheralEnable(SYSCTL_PERIPH_USB0); + SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOD); + SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOB); + + while (!SysCtlPeripheralReady(SYSCTL_PERIPH_USB0)) + ; + while (!SysCtlPeripheralReady(SYSCTL_PERIPH_GPIOD)) + ; + while (!SysCtlPeripheralReady(SYSCTL_PERIPH_GPIOB)) + ; + + SysCtlPeripheralReset(SYSCTL_PERIPH_USB0); + for (volatile int i = 0; i < 1000; i++) + ; + + GPIOPinTypeUSBAnalog(GPIO_PORTD_BASE, GPIO_PIN_4 | GPIO_PIN_5); + GPIOPinTypeUSBAnalog(GPIO_PORTB_BASE, GPIO_PIN_0 | GPIO_PIN_1); + + HWREGB(USB0_BASE + USB_O_GPCS) = USB_GPCS_DEVMOD; + SysCtlUSBPLLEnable(); + + g_usb_irq_handler = USBD_IRQHandler; + + IntPrioritySet(INT_USB0, (6 << 5)); + IntEnable(INT_USB0); +} + +void usb_dc_low_level_deinit(void) +{ + IntDisable(INT_USB0); + g_usb_irq_handler = NULL; + SysCtlPeripheralDisable(SYSCTL_PERIPH_USB0); +} + +void usb_hc_low_level_init(struct usbh_bus *bus) +{ + SysCtlPeripheralEnable(SYSCTL_PERIPH_USB0); + SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOD); + SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOB); + + while (!SysCtlPeripheralReady(SYSCTL_PERIPH_USB0)) + ; + while (!SysCtlPeripheralReady(SYSCTL_PERIPH_GPIOD)) + ; + while (!SysCtlPeripheralReady(SYSCTL_PERIPH_GPIOB)) + ; + + SysCtlPeripheralReset(SYSCTL_PERIPH_USB0); + for (volatile int i = 0; i < 1000; i++) + ; + + GPIOPinTypeUSBAnalog(GPIO_PORTD_BASE, GPIO_PIN_4 | GPIO_PIN_5); + GPIOPinTypeUSBAnalog(GPIO_PORTB_BASE, GPIO_PIN_0 | GPIO_PIN_1); + + HWREGB(USB0_BASE + USB_O_GPCS) &= ~(USB_GPCS_DEVMOD); + SysCtlUSBPLLEnable(); + + g_usb_irq_handler = USBH_IRQHandler; + + IntPrioritySet(INT_USB0, (6 << 5)); + IntEnable(INT_USB0); +} + +void usb_hc_low_level_deinit(struct usbh_bus *bus) +{ + IntDisable(INT_USB0); + g_usb_irq_handler = NULL; + SysCtlPeripheralDisable(SYSCTL_PERIPH_USB0); +} \ No newline at end of file diff --git a/kernel/cherryusb/port/musb/usb_hc_musb.c b/kernel/cherryusb/port/musb/usb_hc_musb.c new file mode 100644 index 0000000..b0c7500 --- /dev/null +++ b/kernel/cherryusb/port/musb/usb_hc_musb.c @@ -0,0 +1,1170 @@ +/* + * Copyright (c) 2022, sakumisu + * + * SPDX-License-Identifier: Apache-2.0 + */ +#include "usbh_core.h" +#include "usbh_hub.h" +#include "usb_musb_reg.h" + +#define HWREG(x) \ + (*((volatile uint32_t *)(x))) +#define HWREGH(x) \ + (*((volatile uint16_t *)(x))) +#define HWREGB(x) \ + (*((volatile uint8_t *)(x))) + +#define USB_BASE (bus->hcd.reg_base) + +#if defined(CONFIG_USB_MUSB_SUNXI) +#define MUSB_FADDR_OFFSET 0x98 +#define MUSB_POWER_OFFSET 0x40 +#define MUSB_TXIS_OFFSET 0x44 +#define MUSB_RXIS_OFFSET 0x46 +#define MUSB_TXIE_OFFSET 0x48 +#define MUSB_RXIE_OFFSET 0x4A +#define MUSB_IS_OFFSET 0x4C +#define MUSB_IE_OFFSET 0x50 +#define MUSB_EPIDX_OFFSET 0x42 + +#define MUSB_IND_TXMAP_OFFSET 0x80 +#define MUSB_IND_TXCSRL_OFFSET 0x82 +#define MUSB_IND_TXCSRH_OFFSET 0x83 +#define MUSB_IND_RXMAP_OFFSET 0x84 +#define MUSB_IND_RXCSRL_OFFSET 0x86 +#define MUSB_IND_RXCSRH_OFFSET 0x87 +#define MUSB_IND_RXCOUNT_OFFSET 0x88 +#define MUSB_IND_TXTYPE_OFFSET 0x8C +#define MUSB_IND_TXINTERVAL_OFFSET 0x8D +#define MUSB_IND_RXTYPE_OFFSET 0x8E +#define MUSB_IND_RXINTERVAL_OFFSET 0x8F + +#define MUSB_FIFO_OFFSET 0x00 + +#define MUSB_DEVCTL_OFFSET 0x41 + +#define MUSB_TXFIFOSZ_OFFSET 0x90 +#define MUSB_RXFIFOSZ_OFFSET 0x94 +#define MUSB_TXFIFOADD_OFFSET 0x92 +#define MUSB_RXFIFOADD_OFFSET 0x96 + +#define MUSB_TXFUNCADDR0_OFFSET 0x98 +#define MUSB_TXHUBADDR0_OFFSET 0x9A +#define MUSB_TXHUBPORT0_OFFSET 0x9B +#define MUSB_TXFUNCADDRx_OFFSET 0x98 +#define MUSB_TXHUBADDRx_OFFSET 0x9A +#define MUSB_TXHUBPORTx_OFFSET 0x9B +#define MUSB_RXFUNCADDRx_OFFSET 0x9C +#define MUSB_RXHUBADDRx_OFFSET 0x9E +#define MUSB_RXHUBPORTx_OFFSET 0x9F + +#define USB_TXMAP_BASE(ep_idx) (USB_BASE + MUSB_IND_TXMAP_OFFSET) +#define USB_TXCSRL_BASE(ep_idx) (USB_BASE + MUSB_IND_TXCSRL_OFFSET) +#define USB_TXCSRH_BASE(ep_idx) (USB_BASE + MUSB_IND_TXCSRH_OFFSET) +#define USB_RXMAP_BASE(ep_idx) (USB_BASE + MUSB_IND_RXMAP_OFFSET) +#define USB_RXCSRL_BASE(ep_idx) (USB_BASE + MUSB_IND_RXCSRL_OFFSET) +#define USB_RXCSRH_BASE(ep_idx) (USB_BASE + MUSB_IND_RXCSRH_OFFSET) +#define USB_RXCOUNT_BASE(ep_idx) (USB_BASE + MUSB_IND_RXCOUNT_OFFSET) +#define USB_TXTYPE_BASE(ep_idx) (USB_BASE + MUSB_IND_TXTYPE_OFFSET) +#define USB_TXINTERVAL_BASE(ep_idx) (USB_BASE + MUSB_IND_TXINTERVAL_OFFSET) +#define USB_RXTYPE_BASE(ep_idx) (USB_BASE + MUSB_IND_RXTYPE_OFFSET) +#define USB_RXINTERVAL_BASE(ep_idx) (USB_BASE + MUSB_IND_RXINTERVAL_OFFSET) + +#define USB_TXADDR_BASE(ep_idx) (USB_BASE + MUSB_TXFUNCADDRx_OFFSET) +#define USB_TXHUBADDR_BASE(ep_idx) (USB_BASE + MUSB_TXHUBADDRx_OFFSET) +#define USB_TXHUBPORT_BASE(ep_idx) (USB_BASE + MUSB_TXHUBPORTx_OFFSET) +#define USB_RXADDR_BASE(ep_idx) (USB_BASE + MUSB_RXFUNCADDRx_OFFSET) +#define USB_RXHUBADDR_BASE(ep_idx) (USB_BASE + MUSB_RXHUBADDRx_OFFSET) +#define USB_RXHUBPORT_BASE(ep_idx) (USB_BASE + MUSB_RXHUBPORTx_OFFSET) + +#elif defined(CONFIG_USB_MUSB_CUSTOM) +#include "musb_custom.h" +#else +#define MUSB_FADDR_OFFSET 0x00 +#define MUSB_POWER_OFFSET 0x01 +#define MUSB_TXIS_OFFSET 0x02 +#define MUSB_RXIS_OFFSET 0x04 +#define MUSB_TXIE_OFFSET 0x06 +#define MUSB_RXIE_OFFSET 0x08 +#define MUSB_IS_OFFSET 0x0A +#define MUSB_IE_OFFSET 0x0B + +#define MUSB_EPIDX_OFFSET 0x0E + +#define MUSB_IND_TXMAP_OFFSET 0x10 +#define MUSB_IND_TXCSRL_OFFSET 0x12 +#define MUSB_IND_TXCSRH_OFFSET 0x13 +#define MUSB_IND_RXMAP_OFFSET 0x14 +#define MUSB_IND_RXCSRL_OFFSET 0x16 +#define MUSB_IND_RXCSRH_OFFSET 0x17 +#define MUSB_IND_RXCOUNT_OFFSET 0x18 +#define MUSB_IND_TXTYPE_OFFSET 0x1A +#define MUSB_IND_TXINTERVAL_OFFSET 0x1B +#define MUSB_IND_RXTYPE_OFFSET 0x1C +#define MUSB_IND_RXINTERVAL_OFFSET 0x1D + +#define MUSB_FIFO_OFFSET 0x20 + +#define MUSB_DEVCTL_OFFSET 0x60 + +#define MUSB_TXFIFOSZ_OFFSET 0x62 +#define MUSB_RXFIFOSZ_OFFSET 0x63 +#define MUSB_TXFIFOADD_OFFSET 0x64 +#define MUSB_RXFIFOADD_OFFSET 0x66 + +#define MUSB_TXFUNCADDR0_OFFSET 0x80 +#define MUSB_TXHUBADDR0_OFFSET 0x82 +#define MUSB_TXHUBPORT0_OFFSET 0x83 +#define MUSB_TXFUNCADDRx_OFFSET 0x88 +#define MUSB_TXHUBADDRx_OFFSET 0x8A +#define MUSB_TXHUBPORTx_OFFSET 0x8B +#define MUSB_RXFUNCADDRx_OFFSET 0x8C +#define MUSB_RXHUBADDRx_OFFSET 0x8E +#define MUSB_RXHUBPORTx_OFFSET 0x8F + +#define MUSB_TXMAP0_OFFSET 0x100 + +// do not use EPIDX +#define USB_TXMAP_BASE(ep_idx) (USB_BASE + MUSB_TXMAP0_OFFSET + 0x10 * ep_idx) +#define USB_TXCSRL_BASE(ep_idx) (USB_BASE + MUSB_TXMAP0_OFFSET + 0x10 * ep_idx + 2) +#define USB_TXCSRH_BASE(ep_idx) (USB_BASE + MUSB_TXMAP0_OFFSET + 0x10 * ep_idx + 3) +#define USB_RXMAP_BASE(ep_idx) (USB_BASE + MUSB_TXMAP0_OFFSET + 0x10 * ep_idx + 4) +#define USB_RXCSRL_BASE(ep_idx) (USB_BASE + MUSB_TXMAP0_OFFSET + 0x10 * ep_idx + 6) +#define USB_RXCSRH_BASE(ep_idx) (USB_BASE + MUSB_TXMAP0_OFFSET + 0x10 * ep_idx + 7) +#define USB_RXCOUNT_BASE(ep_idx) (USB_BASE + MUSB_TXMAP0_OFFSET + 0x10 * ep_idx + 8) +#define USB_TXTYPE_BASE(ep_idx) (USB_BASE + MUSB_TXMAP0_OFFSET + 0x10 * ep_idx + 0x0A) +#define USB_TXINTERVAL_BASE(ep_idx) (USB_BASE + MUSB_TXMAP0_OFFSET + 0x10 * ep_idx + 0x0B) +#define USB_RXTYPE_BASE(ep_idx) (USB_BASE + MUSB_TXMAP0_OFFSET + 0x10 * ep_idx + 0x0C) +#define USB_RXINTERVAL_BASE(ep_idx) (USB_BASE + MUSB_TXMAP0_OFFSET + 0x10 * ep_idx + 0x0D) + +#define USB_TXADDR_BASE(ep_idx) (USB_BASE + MUSB_TXFUNCADDR0_OFFSET + 0x8 * ep_idx) +#define USB_TXHUBADDR_BASE(ep_idx) (USB_BASE + MUSB_TXFUNCADDR0_OFFSET + 0x8 * ep_idx + 2) +#define USB_TXHUBPORT_BASE(ep_idx) (USB_BASE + MUSB_TXFUNCADDR0_OFFSET + 0x8 * ep_idx + 3) +#define USB_RXADDR_BASE(ep_idx) (USB_BASE + MUSB_TXFUNCADDR0_OFFSET + 0x8 * ep_idx + 4) +#define USB_RXHUBADDR_BASE(ep_idx) (USB_BASE + MUSB_TXFUNCADDR0_OFFSET + 0x8 * ep_idx + 6) +#define USB_RXHUBPORT_BASE(ep_idx) (USB_BASE + MUSB_TXFUNCADDR0_OFFSET + 0x8 * ep_idx + 7) +#endif + +#define USB_FIFO_BASE(ep_idx) (USB_BASE + MUSB_FIFO_OFFSET + 0x4 * ep_idx) + +typedef enum { + USB_EP0_STATE_SETUP = 0x0, /**< SETUP DATA */ + USB_EP0_STATE_IN_DATA, /**< IN DATA */ + USB_EP0_STATE_IN_STATUS, /**< IN status*/ + USB_EP0_STATE_OUT_DATA, /**< OUT DATA */ + USB_EP0_STATE_OUT_STATUS, /**< OUT status */ +} ep0_state_t; + +struct musb_pipe { + uint8_t chidx; + bool inuse; + uint32_t xfrd; + volatile uint8_t ep0_state; + usb_osal_sem_t waitsem; + struct usbh_urb *urb; +}; + +struct musb_hcd { + volatile bool port_csc; + volatile bool port_pec; + volatile bool port_pe; + struct musb_pipe pipe_pool[CONFIG_USB_MUSB_PIPE_NUM]; +} g_musb_hcd[CONFIG_USBHOST_MAX_BUS]; + +/* get current active ep */ +static uint8_t musb_get_active_ep(struct usbh_bus *bus) +{ + return HWREGB(USB_BASE + MUSB_EPIDX_OFFSET); +} + +/* set the active ep */ +static void musb_set_active_ep(struct usbh_bus *bus, uint8_t ep_index) +{ + HWREGB(USB_BASE + MUSB_EPIDX_OFFSET) = ep_index; +} + +static void musb_fifo_flush(struct usbh_bus *bus, uint8_t ep) +{ + uint8_t ep_idx = ep & 0x7f; + if (ep_idx == 0) { + if ((HWREGB(USB_TXCSRL_BASE(ep_idx)) & (USB_CSRL0_RXRDY | USB_CSRL0_TXRDY)) != 0) + HWREGB(USB_RXCSRL_BASE(ep_idx)) |= USB_CSRH0_FLUSH; + } else { + if (ep & 0x80) { + if (HWREGB(USB_TXCSRL_BASE(ep_idx)) & USB_TXCSRL1_TXRDY) + HWREGB(USB_TXCSRL_BASE(ep_idx)) |= USB_TXCSRL1_FLUSH; + } else { + if (HWREGB(USB_RXCSRL_BASE(ep_idx)) & USB_RXCSRL1_RXRDY) + HWREGB(USB_RXCSRL_BASE(ep_idx)) |= USB_RXCSRL1_FLUSH; + } + } +} + +static void musb_write_packet(struct usbh_bus *bus, uint8_t ep_idx, uint8_t *buffer, uint16_t len) +{ + uint32_t *buf32; + uint8_t *buf8; + uint32_t count32; + uint32_t count8; + int i; + + if ((uint32_t)buffer & 0x03) { + buf8 = buffer; + for (i = 0; i < len; i++) { + HWREGB(USB_FIFO_BASE(ep_idx)) = *buf8++; + } + } else { + count32 = len >> 2; + count8 = len & 0x03; + + buf32 = (uint32_t *)buffer; + + while (count32--) { + HWREG(USB_FIFO_BASE(ep_idx)) = *buf32++; + } + + buf8 = (uint8_t *)buf32; + + while (count8--) { + HWREGB(USB_FIFO_BASE(ep_idx)) = *buf8++; + } + } +} + +static void musb_read_packet(struct usbh_bus *bus, uint8_t ep_idx, uint8_t *buffer, uint16_t len) +{ + uint32_t *buf32; + uint8_t *buf8; + uint32_t count32; + uint32_t count8; + int i; + + if ((uint32_t)buffer & 0x03) { + buf8 = buffer; + for (i = 0; i < len; i++) { + *buf8++ = HWREGB(USB_FIFO_BASE(ep_idx)); + } + } else { + count32 = len >> 2; + count8 = len & 0x03; + + buf32 = (uint32_t *)buffer; + + while (count32--) { + *buf32++ = HWREG(USB_FIFO_BASE(ep_idx)); + } + + buf8 = (uint8_t *)buf32; + + while (count8--) { + *buf8++ = HWREGB(USB_FIFO_BASE(ep_idx)); + } + } +} + +static uint32_t musb_get_fifo_size(uint16_t mps, uint16_t *used) +{ + uint32_t size; + + for (uint8_t i = USB_TXFIFOSZ_SIZE_8; i <= USB_TXFIFOSZ_SIZE_2048; i++) { + size = (8 << i); + if (mps <= size) { + *used = size; + return i; + } + } + + *used = 0; + return USB_TXFIFOSZ_SIZE_8; +} + +static uint32_t usbh_musb_fifo_config(struct usbh_bus *bus, struct musb_fifo_cfg *cfg, uint32_t offset) +{ + uint16_t fifo_used; + uint8_t c_size; + uint16_t c_off; + + c_off = offset >> 3; + c_size = musb_get_fifo_size(cfg->maxpacket, &fifo_used); + + musb_set_active_ep(bus, cfg->ep_num); + + switch (cfg->style) { + case FIFO_TX: + HWREGB(USB_BASE + MUSB_TXFIFOSZ_OFFSET) = c_size & 0x0f; + HWREGH(USB_BASE + MUSB_TXFIFOADD_OFFSET) = c_off; + break; + case FIFO_RX: + HWREGB(USB_BASE + MUSB_RXFIFOSZ_OFFSET) = c_size & 0x0f; + HWREGH(USB_BASE + MUSB_RXFIFOADD_OFFSET) = c_off; + break; + case FIFO_TXRX: + HWREGB(USB_BASE + MUSB_TXFIFOSZ_OFFSET) = c_size & 0x0f; + HWREGH(USB_BASE + MUSB_TXFIFOADD_OFFSET) = c_off; + HWREGB(USB_BASE + MUSB_RXFIFOSZ_OFFSET) = c_size & 0x0f; + HWREGH(USB_BASE + MUSB_RXFIFOADD_OFFSET) = c_off; + break; + + default: + break; + } + + return (offset + fifo_used); +} + +void musb_control_urb_init(struct usbh_bus *bus, uint8_t chidx, struct usbh_urb *urb, struct usb_setup_packet *setup, uint8_t *buffer, uint32_t buflen) +{ + uint8_t old_ep_index; + uint8_t speed = USB_TXTYPE1_SPEED_FULL; + + old_ep_index = musb_get_active_ep(bus); + musb_set_active_ep(bus, chidx); + + if (urb->hport->speed == USB_SPEED_HIGH) { + speed = USB_TYPE0_SPEED_HIGH; + } else if (urb->hport->speed == USB_SPEED_FULL) { + speed = USB_TYPE0_SPEED_FULL; + } else if (urb->hport->speed == USB_SPEED_LOW) { + speed = USB_TYPE0_SPEED_LOW; + } + +#ifdef CONFIG_USB_MUSB_WITHOUT_MULTIPOINT + /* Without multipoint, use FADDR for host target addressing and do not access Hub/FuncAddr regs */ + HWREGB(USB_BASE + MUSB_FADDR_OFFSET) = (urb->hport->dev_addr & 0x7F); + HWREGB(USB_TXTYPE_BASE(chidx)) = speed; +#else + HWREGB(USB_TXADDR_BASE(chidx)) = urb->hport->dev_addr; + HWREGB(USB_TXTYPE_BASE(chidx)) = speed; + HWREGB(USB_TXHUBADDR_BASE(chidx)) = 0; + HWREGB(USB_TXHUBPORT_BASE(chidx)) = 0; +#endif + + musb_write_packet(bus, chidx, (uint8_t *)setup, 8); + HWREGB(USB_TXCSRL_BASE(chidx)) = USB_CSRL0_TXRDY | USB_CSRL0_SETUP; + musb_set_active_ep(bus, old_ep_index); +} + +int musb_bulk_urb_init(struct usbh_bus *bus, uint8_t chidx, struct usbh_urb *urb, uint8_t *buffer, uint32_t buflen) +{ + uint8_t old_ep_index; + uint8_t speed = USB_TXTYPE1_SPEED_FULL; + + old_ep_index = musb_get_active_ep(bus); + musb_set_active_ep(bus, chidx); + + if (urb->hport->speed == USB_SPEED_HIGH) { + speed = USB_TXTYPE1_SPEED_HIGH; + } else if (urb->hport->speed == USB_SPEED_FULL) { + speed = USB_TXTYPE1_SPEED_FULL; + } else if (urb->hport->speed == USB_SPEED_LOW) { + speed = USB_TXTYPE1_SPEED_LOW; + } + + if (urb->ep->bEndpointAddress & 0x80) { + if ((8 << HWREGB(USB_BASE + MUSB_RXFIFOSZ_OFFSET)) < USB_GET_MAXPACKETSIZE(urb->ep->wMaxPacketSize)) { + USB_LOG_ERR("Ep %02x fifo is overflow\r\n", urb->ep->bEndpointAddress); + return -USB_ERR_RANGE; + } + +#ifdef CONFIG_USB_MUSB_WITHOUT_MULTIPOINT + HWREGB(USB_BASE + MUSB_FADDR_OFFSET) = (urb->hport->dev_addr & 0x7F); + HWREGB(USB_RXTYPE_BASE(chidx)) = (urb->ep->bEndpointAddress & 0x0f) | speed | USB_TXTYPE1_PROTO_BULK; + HWREGH(USB_RXMAP_BASE(chidx)) = USB_GET_MAXPACKETSIZE(urb->ep->wMaxPacketSize); + HWREGB(USB_RXINTERVAL_BASE(chidx)) = 0; +#else + HWREGB(USB_RXADDR_BASE(chidx)) = urb->hport->dev_addr; + HWREGB(USB_RXTYPE_BASE(chidx)) = (urb->ep->bEndpointAddress & 0x0f) | speed | USB_TXTYPE1_PROTO_BULK; + HWREGH(USB_RXMAP_BASE(chidx)) = USB_GET_MAXPACKETSIZE(urb->ep->wMaxPacketSize); + HWREGB(USB_RXINTERVAL_BASE(chidx)) = 0; + HWREGB(USB_RXHUBADDR_BASE(chidx)) = 0; + HWREGB(USB_RXHUBPORT_BASE(chidx)) = 0; +#endif + HWREGB(USB_TXCSRH_BASE(chidx)) &= ~USB_TXCSRH1_MODE; + HWREGB(USB_RXCSRL_BASE(chidx)) = USB_RXCSRL1_REQPKT; + + HWREGH(USB_BASE + MUSB_RXIE_OFFSET) |= (1 << chidx); + } else { + if ((8 << HWREGB(USB_BASE + MUSB_TXFIFOSZ_OFFSET)) < USB_GET_MAXPACKETSIZE(urb->ep->wMaxPacketSize)) { + USB_LOG_ERR("Ep %02x fifo is overflow\r\n", urb->ep->bEndpointAddress); + return -USB_ERR_RANGE; + } + +#ifdef CONFIG_USB_MUSB_WITHOUT_MULTIPOINT + HWREGB(USB_BASE + MUSB_FADDR_OFFSET) = (urb->hport->dev_addr & 0x7F); + HWREGB(USB_TXTYPE_BASE(chidx)) = (urb->ep->bEndpointAddress & 0x0f) | speed | USB_TXTYPE1_PROTO_BULK; + HWREGH(USB_TXMAP_BASE(chidx)) = USB_GET_MAXPACKETSIZE(urb->ep->wMaxPacketSize); + HWREGB(USB_TXINTERVAL_BASE(chidx)) = 0; +#else + HWREGB(USB_TXADDR_BASE(chidx)) = urb->hport->dev_addr; + HWREGB(USB_TXTYPE_BASE(chidx)) = (urb->ep->bEndpointAddress & 0x0f) | speed | USB_TXTYPE1_PROTO_BULK; + HWREGH(USB_TXMAP_BASE(chidx)) = USB_GET_MAXPACKETSIZE(urb->ep->wMaxPacketSize); + HWREGB(USB_TXINTERVAL_BASE(chidx)) = 0; + HWREGB(USB_TXHUBADDR_BASE(chidx)) = 0; + HWREGB(USB_TXHUBPORT_BASE(chidx)) = 0; +#endif + + if (buflen > USB_GET_MAXPACKETSIZE(urb->ep->wMaxPacketSize)) { + buflen = USB_GET_MAXPACKETSIZE(urb->ep->wMaxPacketSize); + } + + musb_write_packet(bus, chidx, buffer, buflen); + HWREGB(USB_TXCSRH_BASE(chidx)) |= USB_TXCSRH1_MODE; + HWREGB(USB_TXCSRL_BASE(chidx)) = USB_TXCSRL1_TXRDY; + + HWREGH(USB_BASE + MUSB_TXIE_OFFSET) |= (1 << chidx); + } + musb_set_active_ep(bus, old_ep_index); + return 0; +} + +int musb_intr_urb_init(struct usbh_bus *bus, uint8_t chidx, struct usbh_urb *urb, uint8_t *buffer, uint32_t buflen) +{ + uint8_t old_ep_index; + uint8_t speed = USB_TXTYPE1_SPEED_FULL; + + old_ep_index = musb_get_active_ep(bus); + musb_set_active_ep(bus, chidx); + + if (urb->hport->speed == USB_SPEED_HIGH) { + speed = USB_TXTYPE1_SPEED_HIGH; + } else if (urb->hport->speed == USB_SPEED_FULL) { + speed = USB_TXTYPE1_SPEED_FULL; + } else if (urb->hport->speed == USB_SPEED_LOW) { + speed = USB_TXTYPE1_SPEED_LOW; + } + + if (urb->ep->bEndpointAddress & 0x80) { + if ((8 << HWREGB(USB_BASE + MUSB_RXFIFOSZ_OFFSET)) < USB_GET_MAXPACKETSIZE(urb->ep->wMaxPacketSize)) { + USB_LOG_ERR("Ep %02x fifo is overflow\r\n", urb->ep->bEndpointAddress); + return -USB_ERR_RANGE; + } + +#ifdef CONFIG_USB_MUSB_WITHOUT_MULTIPOINT + HWREGB(USB_BASE + MUSB_FADDR_OFFSET) = (urb->hport->dev_addr & 0x7F); + HWREGB(USB_RXTYPE_BASE(chidx)) = (urb->ep->bEndpointAddress & 0x0f) | speed | USB_TXTYPE1_PROTO_INT; + HWREGH(USB_RXMAP_BASE(chidx)) = USB_GET_MAXPACKETSIZE(urb->ep->wMaxPacketSize); + HWREGB(USB_RXINTERVAL_BASE(chidx)) = urb->ep->bInterval; +#else + HWREGB(USB_RXADDR_BASE(chidx)) = urb->hport->dev_addr; + HWREGB(USB_RXTYPE_BASE(chidx)) = (urb->ep->bEndpointAddress & 0x0f) | speed | USB_TXTYPE1_PROTO_INT; + HWREGH(USB_RXMAP_BASE(chidx)) = USB_GET_MAXPACKETSIZE(urb->ep->wMaxPacketSize); + HWREGB(USB_RXINTERVAL_BASE(chidx)) = urb->ep->bInterval; + HWREGB(USB_RXHUBADDR_BASE(chidx)) = 0; + HWREGB(USB_RXHUBPORT_BASE(chidx)) = 0; +#endif + HWREGB(USB_TXCSRH_BASE(chidx)) &= ~USB_TXCSRH1_MODE; + HWREGB(USB_RXCSRL_BASE(chidx)) = USB_RXCSRL1_REQPKT; + + HWREGH(USB_BASE + MUSB_RXIE_OFFSET) |= (1 << chidx); + } else { + if ((8 << HWREGB(USB_BASE + MUSB_TXFIFOSZ_OFFSET)) < USB_GET_MAXPACKETSIZE(urb->ep->wMaxPacketSize)) { + USB_LOG_ERR("Ep %02x fifo is overflow\r\n", urb->ep->bEndpointAddress); + return -USB_ERR_RANGE; + } + +#ifdef CONFIG_USB_MUSB_WITHOUT_MULTIPOINT + HWREGB(USB_BASE + MUSB_FADDR_OFFSET) = (urb->hport->dev_addr & 0x7F); + HWREGB(USB_TXTYPE_BASE(chidx)) = (urb->ep->bEndpointAddress & 0x0f) | speed | USB_TXTYPE1_PROTO_INT; + HWREGH(USB_TXMAP_BASE(chidx)) = USB_GET_MAXPACKETSIZE(urb->ep->wMaxPacketSize); + HWREGB(USB_TXINTERVAL_BASE(chidx)) = urb->ep->bInterval; +#else + HWREGB(USB_TXADDR_BASE(chidx)) = urb->hport->dev_addr; + HWREGB(USB_TXTYPE_BASE(chidx)) = (urb->ep->bEndpointAddress & 0x0f) | speed | USB_TXTYPE1_PROTO_INT; + HWREGH(USB_TXMAP_BASE(chidx)) = USB_GET_MAXPACKETSIZE(urb->ep->wMaxPacketSize); + HWREGB(USB_TXINTERVAL_BASE(chidx)) = urb->ep->bInterval; + HWREGB(USB_TXHUBADDR_BASE(chidx)) = 0; + HWREGB(USB_TXHUBPORT_BASE(chidx)) = 0; +#endif + + if (buflen > USB_GET_MAXPACKETSIZE(urb->ep->wMaxPacketSize)) { + buflen = USB_GET_MAXPACKETSIZE(urb->ep->wMaxPacketSize); + } + + musb_write_packet(bus, chidx, buffer, buflen); + HWREGB(USB_TXCSRH_BASE(chidx)) |= USB_TXCSRH1_MODE; + HWREGB(USB_TXCSRL_BASE(chidx)) = USB_TXCSRL1_TXRDY; + + HWREGH(USB_BASE + MUSB_TXIE_OFFSET) |= (1 << chidx); + } + musb_set_active_ep(bus, old_ep_index); + return 0; +} + +static int usbh_reset_port(struct usbh_bus *bus, const uint8_t port) +{ + g_musb_hcd[bus->hcd.hcd_id].port_pe = 0; + HWREGB(USB_BASE + MUSB_POWER_OFFSET) |= USB_POWER_RESET; + +#ifdef CONFIG_USB_MUSB_SIFLI + extern void musb_reset_prev(void); + musb_reset_prev(); +#endif + usb_osal_msleep(20); + HWREGB(USB_BASE + MUSB_POWER_OFFSET) &= ~(USB_POWER_RESET); + usb_osal_msleep(20); +#ifdef CONFIG_USB_MUSB_SIFLI + extern void musb_reset_post(void); + musb_reset_post(); +#endif + g_musb_hcd[bus->hcd.hcd_id].port_pe = 1; + return 0; +} + +static uint8_t usbh_get_port_speed(struct usbh_bus *bus, const uint8_t port) +{ + uint8_t speed = USB_SPEED_UNKNOWN; + + if (HWREGB(USB_BASE + MUSB_POWER_OFFSET) & USB_POWER_HSMODE) + speed = USB_SPEED_HIGH; + else if (HWREGB(USB_BASE + MUSB_DEVCTL_OFFSET) & USB_DEVCTL_FSDEV) + speed = USB_SPEED_FULL; + else if (HWREGB(USB_BASE + MUSB_DEVCTL_OFFSET) & USB_DEVCTL_LSDEV) + speed = USB_SPEED_LOW; + + return speed; +} + +static int musb_pipe_alloc(struct usbh_bus *bus) +{ + int chidx; + uintptr_t flags; + + flags = usb_osal_enter_critical_section(); + for (chidx = 1; chidx < CONFIG_USB_MUSB_PIPE_NUM; chidx++) { + if (!g_musb_hcd[bus->hcd.hcd_id].pipe_pool[chidx].inuse) { + g_musb_hcd[bus->hcd.hcd_id].pipe_pool[chidx].inuse = true; + usb_osal_leave_critical_section(flags); + return chidx; + } + } + usb_osal_leave_critical_section(flags); + + return -1; +} + +static void musb_pipe_free(struct musb_pipe *pipe) +{ + uintptr_t flags; + + flags = usb_osal_enter_critical_section(); + if (pipe->urb) { + pipe->urb->hcpriv = NULL; + pipe->urb = NULL; + } + + pipe->inuse = false; + usb_osal_leave_critical_section(flags); +} + +__WEAK void usb_hc_low_level_init(struct usbh_bus *bus) +{ + (void)bus; +} + +__WEAK void usb_hc_low_level_deinit(struct usbh_bus *bus) +{ + (void)bus; +} + +int usb_hc_init(struct usbh_bus *bus) +{ + uint8_t regval; + uint16_t offset = 0; + uint8_t cfg_num; + struct musb_fifo_cfg *cfg; + + usb_hc_low_level_init(bus); + + memset(&g_musb_hcd[bus->hcd.hcd_id], 0, sizeof(struct musb_hcd)); + + for (uint8_t i = 0; i < CONFIG_USB_MUSB_PIPE_NUM; i++) { + g_musb_hcd[bus->hcd.hcd_id].pipe_pool[i].waitsem = usb_osal_sem_create(0); + } + + cfg_num = usbh_get_musb_fifo_cfg(&cfg); + + for (uint8_t i = 0; i < cfg_num; i++) { + offset = usbh_musb_fifo_config(bus, &cfg[i], offset); + } + + USB_ASSERT_MSG(offset <= usb_get_musb_ram_size(), "Your fifo config is overflow, please check"); + + /* Enable USB interrupts */ + regval = USB_IE_RESET | USB_IE_CONN | USB_IE_DISCON | + USB_IE_RESUME | USB_IE_SUSPND | + USB_IE_BABBLE | USB_IE_SESREQ | USB_IE_VBUSERR; + + HWREGB(USB_BASE + MUSB_IE_OFFSET) = regval; + HWREGH(USB_BASE + MUSB_TXIE_OFFSET) = USB_TXIE_EP0; + HWREGH(USB_BASE + MUSB_RXIE_OFFSET) = 0; + + HWREGB(USB_BASE + MUSB_POWER_OFFSET) |= USB_POWER_HSENAB; + + HWREGB(USB_BASE + MUSB_DEVCTL_OFFSET) |= USB_DEVCTL_SESSION; + +#ifdef CONFIG_USB_MUSB_SUNXI + musb_set_active_ep(bus, 0); + HWREGB(USB_TXCSRL_BASE(0)) = USB_CSRL0_TXRDY; +#endif + return 0; +} + +int usb_hc_deinit(struct usbh_bus *bus) +{ + HWREGB(USB_BASE + MUSB_IE_OFFSET) = 0; + HWREGH(USB_BASE + MUSB_TXIE_OFFSET) = 0; + HWREGH(USB_BASE + MUSB_RXIE_OFFSET) = 0; + + HWREGB(USB_BASE + MUSB_POWER_OFFSET) &= ~USB_POWER_HSENAB; + HWREGB(USB_BASE + MUSB_DEVCTL_OFFSET) &= ~USB_DEVCTL_SESSION; + + for (uint8_t i = 0; i < CONFIG_USB_MUSB_PIPE_NUM; i++) { + usb_osal_sem_delete(g_musb_hcd[bus->hcd.hcd_id].pipe_pool[i].waitsem); + } + + usb_hc_low_level_deinit(bus); + return 0; +} + +int usbh_roothub_control(struct usbh_bus *bus, struct usb_setup_packet *setup, uint8_t *buf) +{ + uint8_t nports; + uint8_t port; + uint32_t status; + + nports = CONFIG_USBHOST_MAX_RHPORTS; + port = setup->wIndex; + if (setup->bmRequestType & USB_REQUEST_RECIPIENT_DEVICE) { + switch (setup->bRequest) { + case HUB_REQUEST_CLEAR_FEATURE: + switch (setup->wValue) { + case HUB_FEATURE_HUB_C_LOCALPOWER: + break; + case HUB_FEATURE_HUB_C_OVERCURRENT: + break; + default: + return -USB_ERR_INVAL; + } + break; + case HUB_REQUEST_SET_FEATURE: + switch (setup->wValue) { + case HUB_FEATURE_HUB_C_LOCALPOWER: + break; + case HUB_FEATURE_HUB_C_OVERCURRENT: + break; + default: + return -USB_ERR_INVAL; + } + break; + case HUB_REQUEST_GET_DESCRIPTOR: + break; + case HUB_REQUEST_GET_STATUS: + memset(buf, 0, 4); + break; + default: + break; + } + } else if (setup->bmRequestType & USB_REQUEST_RECIPIENT_OTHER) { + switch (setup->bRequest) { + case HUB_REQUEST_CLEAR_FEATURE: + if (!port || port > nports) { + return -USB_ERR_INVAL; + } + + switch (setup->wValue) { + case HUB_PORT_FEATURE_ENABLE: + break; + case HUB_PORT_FEATURE_SUSPEND: + case HUB_PORT_FEATURE_C_SUSPEND: + break; + case HUB_PORT_FEATURE_POWER: + break; + case HUB_PORT_FEATURE_C_CONNECTION: + g_musb_hcd[bus->hcd.hcd_id].port_csc = 0; + break; + case HUB_PORT_FEATURE_C_ENABLE: + g_musb_hcd[bus->hcd.hcd_id].port_pec = 0; + break; + case HUB_PORT_FEATURE_C_OVER_CURREN: + break; + case HUB_PORT_FEATURE_C_RESET: + break; + default: + return -USB_ERR_INVAL; + } + break; + case HUB_REQUEST_SET_FEATURE: + if (!port || port > nports) { + return -USB_ERR_INVAL; + } + + switch (setup->wValue) { + case HUB_PORT_FEATURE_SUSPEND: + break; + case HUB_PORT_FEATURE_POWER: + break; + case HUB_PORT_FEATURE_RESET: + usbh_reset_port(bus, port); + break; + + default: + return -USB_ERR_INVAL; + } + break; + case HUB_REQUEST_GET_STATUS: + if (!port || port > nports) { + return -USB_ERR_INVAL; + } + + status = 0; + if (g_musb_hcd[bus->hcd.hcd_id].port_csc) { + status |= (1 << HUB_PORT_FEATURE_C_CONNECTION); + } + if (g_musb_hcd[bus->hcd.hcd_id].port_pec) { + status |= (1 << HUB_PORT_FEATURE_C_ENABLE); + } + + if (g_musb_hcd[bus->hcd.hcd_id].port_pe) { + status |= (1 << HUB_PORT_FEATURE_CONNECTION); + status |= (1 << HUB_PORT_FEATURE_ENABLE); + if (usbh_get_port_speed(bus, port) == USB_SPEED_LOW) { + status |= (1 << HUB_PORT_FEATURE_LOWSPEED); + } else if (usbh_get_port_speed(bus, port) == USB_SPEED_HIGH) { + status |= (1 << HUB_PORT_FEATURE_HIGHSPEED); + } + } + + status |= (1 << HUB_PORT_FEATURE_POWER); + memcpy(buf, &status, 4); + break; + default: + break; + } + } + return 0; +} + +int usbh_submit_urb(struct usbh_urb *urb) +{ + struct musb_pipe *pipe; + struct usbh_bus *bus; + int chidx; + size_t flags; + int ret = 0; + + if (!urb || !urb->hport || !urb->ep || !urb->hport->bus) { + return -USB_ERR_INVAL; + } + + if (!urb->hport->connected) { + return -USB_ERR_NOTCONN; + } + + if (urb->errorcode == -USB_ERR_BUSY) { + return -USB_ERR_BUSY; + } + + bus = urb->hport->bus; + + if (USB_GET_ENDPOINT_TYPE(urb->ep->bmAttributes) == USB_ENDPOINT_TYPE_CONTROL) { + chidx = 0; + } else { + chidx = musb_pipe_alloc(bus); + if (chidx == -1) { + return -USB_ERR_NOMEM; + } + } + + flags = usb_osal_enter_critical_section(); + + pipe = &g_musb_hcd[bus->hcd.hcd_id].pipe_pool[chidx]; + pipe->chidx = chidx; + pipe->urb = urb; + + urb->hcpriv = pipe; + urb->errorcode = -USB_ERR_BUSY; + urb->actual_length = 0; + + switch (USB_GET_ENDPOINT_TYPE(urb->ep->bmAttributes)) { + case USB_ENDPOINT_TYPE_CONTROL: + pipe->ep0_state = USB_EP0_STATE_SETUP; + musb_control_urb_init(bus, 0, urb, urb->setup, urb->transfer_buffer, urb->transfer_buffer_length); + break; + case USB_ENDPOINT_TYPE_BULK: + ret = musb_bulk_urb_init(bus, chidx, urb, urb->transfer_buffer, urb->transfer_buffer_length); + if (ret < 0) { + usb_osal_leave_critical_section(flags); + return ret; + } + break; + case USB_ENDPOINT_TYPE_INTERRUPT: + ret = musb_intr_urb_init(bus, chidx, urb, urb->transfer_buffer, urb->transfer_buffer_length); + if (ret < 0) { + usb_osal_leave_critical_section(flags); + return ret; + } + break; + case USB_ENDPOINT_TYPE_ISOCHRONOUS: + return -USB_ERR_NOTSUPP; + default: + break; + } + usb_osal_leave_critical_section(flags); + + if (urb->timeout > 0) { + /* wait until timeout or sem give */ + ret = usb_osal_sem_take(pipe->waitsem, urb->timeout); + if (ret < 0) { + goto errout_timeout; + } + urb->timeout = 0; + ret = urb->errorcode; + /* we can free pipe when waitsem is done */ + musb_pipe_free(pipe); + } + return ret; +errout_timeout: + urb->timeout = 0; + usbh_kill_urb(urb); + return ret; +} + +int usbh_kill_urb(struct usbh_urb *urb) +{ + struct musb_pipe *pipe; + struct usbh_bus *bus; + size_t flags; + + if (!urb || !urb->hcpriv || !urb->hport->bus) { + return -USB_ERR_INVAL; + } + + bus = urb->hport->bus; + + ARG_UNUSED(bus); + + flags = usb_osal_enter_critical_section(); + + pipe = (struct musb_pipe *)urb->hcpriv; + urb->errorcode = -USB_ERR_SHUTDOWN; + + if (urb->ep->bEndpointAddress & 0x80) { + HWREGH(USB_BASE + MUSB_RXIE_OFFSET) &= ~(1 << (urb->ep->bEndpointAddress & 0x0f)); + HWREGH(USB_BASE + MUSB_RXIS_OFFSET) = (1 << (urb->ep->bEndpointAddress & 0x0f)); + } else { + HWREGH(USB_BASE + MUSB_TXIE_OFFSET) &= ~(1 << (urb->ep->bEndpointAddress & 0x0f)); + HWREGH(USB_BASE + MUSB_TXIS_OFFSET) = (1 << (urb->ep->bEndpointAddress & 0x0f)); + } + + musb_fifo_flush(bus, urb->ep->bEndpointAddress); + + if (urb->timeout) { + usb_osal_sem_give(pipe->waitsem); + } else { + musb_pipe_free(pipe); + } + + if (urb->complete) { + urb->complete(urb->arg, urb->errorcode); + } + + usb_osal_leave_critical_section(flags); + return 0; +} + +static void musb_urb_waitup(struct usbh_urb *urb) +{ + struct musb_pipe *pipe; + + pipe = (struct musb_pipe *)urb->hcpriv; + + if (urb->timeout) { + usb_osal_sem_give(pipe->waitsem); + } else { + musb_pipe_free(pipe); + } + + if (urb->complete) { + if (urb->errorcode < 0) { + urb->complete(urb->arg, urb->errorcode); + } else { + urb->complete(urb->arg, urb->actual_length); + } + } +} + +void handle_ep0(struct usbh_bus *bus) +{ + uint8_t ep_idx = 0; + uint8_t ep0_status; + struct musb_pipe *pipe; + struct usbh_urb *urb; + uint32_t size; + + pipe = (struct musb_pipe *)&g_musb_hcd[bus->hcd.hcd_id].pipe_pool[0]; + urb = pipe->urb; + if (urb == NULL) { + return; + } + + musb_set_active_ep(bus, 0); + ep0_status = HWREGB(USB_TXCSRL_BASE(ep_idx)); + if (ep0_status & USB_CSRL0_STALLED) { + HWREGB(USB_TXCSRL_BASE(ep_idx)) &= ~USB_CSRL0_STALLED; + pipe->ep0_state = USB_EP0_STATE_SETUP; + urb->errorcode = -USB_ERR_STALL; + musb_urb_waitup(urb); + return; + } + if (ep0_status & USB_CSRL0_ERROR) { + HWREGB(USB_TXCSRL_BASE(ep_idx)) &= ~USB_CSRL0_ERROR; + musb_fifo_flush(bus, 0); + pipe->ep0_state = USB_EP0_STATE_SETUP; + urb->errorcode = -USB_ERR_IO; + musb_urb_waitup(urb); + return; + } + + switch (pipe->ep0_state) { + case USB_EP0_STATE_SETUP: + urb->actual_length += 8; + if (urb->transfer_buffer_length) { + if (urb->setup->bmRequestType & 0x80) { + pipe->ep0_state = USB_EP0_STATE_IN_DATA; + HWREGB(USB_TXCSRL_BASE(ep_idx)) = USB_CSRL0_REQPKT; + } else { + pipe->ep0_state = USB_EP0_STATE_OUT_DATA; + size = urb->transfer_buffer_length; + if (size > USB_GET_MAXPACKETSIZE(urb->ep->wMaxPacketSize)) { + size = USB_GET_MAXPACKETSIZE(urb->ep->wMaxPacketSize); + } + + musb_write_packet(bus, 0, urb->transfer_buffer, size); + HWREGB(USB_TXCSRL_BASE(ep_idx)) = USB_CSRL0_TXRDY; + + urb->transfer_buffer += size; + urb->transfer_buffer_length -= size; + urb->actual_length += size; + } + } else { + pipe->ep0_state = USB_EP0_STATE_IN_STATUS; + HWREGB(USB_TXCSRL_BASE(ep_idx)) = (USB_CSRL0_REQPKT | USB_CSRL0_STATUS); + } + break; + case USB_EP0_STATE_IN_DATA: + if (ep0_status & USB_CSRL0_RXRDY) { + size = HWREGH(USB_RXCOUNT_BASE(ep_idx)); + musb_read_packet(bus, 0, urb->transfer_buffer, size); + HWREGB(USB_TXCSRL_BASE(ep_idx)) &= ~USB_CSRL0_RXRDY; + urb->transfer_buffer += size; + urb->transfer_buffer_length -= size; + urb->actual_length += size; + + if ((size < USB_GET_MAXPACKETSIZE(urb->ep->wMaxPacketSize)) || (urb->transfer_buffer_length == 0)) { + pipe->ep0_state = USB_EP0_STATE_OUT_STATUS; + HWREGB(USB_TXCSRL_BASE(ep_idx)) = (USB_CSRL0_TXRDY | USB_CSRL0_STATUS); + } else { + HWREGB(USB_TXCSRL_BASE(ep_idx)) = USB_CSRL0_REQPKT; + } + } + break; + case USB_EP0_STATE_OUT_DATA: + if (urb->transfer_buffer_length > 0) { + size = urb->transfer_buffer_length; + if (size > USB_GET_MAXPACKETSIZE(urb->ep->wMaxPacketSize)) { + size = USB_GET_MAXPACKETSIZE(urb->ep->wMaxPacketSize); + } + + musb_write_packet(bus, 0, urb->transfer_buffer, size); + HWREGB(USB_TXCSRL_BASE(ep_idx)) = USB_CSRL0_TXRDY; + + urb->transfer_buffer += size; + urb->transfer_buffer_length -= size; + urb->actual_length += size; + } else { + pipe->ep0_state = USB_EP0_STATE_IN_STATUS; + HWREGB(USB_TXCSRL_BASE(ep_idx)) = (USB_CSRL0_REQPKT | USB_CSRL0_STATUS); + } + break; + case USB_EP0_STATE_OUT_STATUS: + urb->errorcode = 0; + musb_urb_waitup(urb); + break; + case USB_EP0_STATE_IN_STATUS: + if (ep0_status & (USB_CSRL0_RXRDY | USB_CSRL0_STATUS)) { + HWREGB(USB_TXCSRL_BASE(ep_idx)) &= ~(USB_CSRL0_RXRDY | USB_CSRL0_STATUS); + urb->errorcode = 0; + musb_urb_waitup(urb); + } + break; + } +} + +void USBH_IRQHandler(uint8_t busid) +{ + uint32_t is; + uint32_t txis; + uint32_t rxis; + uint8_t ep_csrl_status; + // uint8_t ep_csrh_status; + struct musb_pipe *pipe; + struct usbh_urb *urb; + uint8_t ep_idx; + uint8_t old_ep_idx; + struct usbh_bus *bus; + uint32_t size; + + bus = &g_usbhost_bus[busid]; + +#if 0 + if (!(HWREGB(USB_BASE + MUSB_DEVCTL_OFFSET) & USB_DEVCTL_HOST)) { + return; + } +#endif + + is = HWREGB(USB_BASE + MUSB_IS_OFFSET); + txis = HWREGH(USB_BASE + MUSB_TXIS_OFFSET); + rxis = HWREGH(USB_BASE + MUSB_RXIS_OFFSET); + + HWREGB(USB_BASE + MUSB_IS_OFFSET) = is; + + old_ep_idx = musb_get_active_ep(bus); + + if (is & USB_IS_CONN) { + g_musb_hcd[bus->hcd.hcd_id].port_csc = 1; + g_musb_hcd[bus->hcd.hcd_id].port_pec = 1; + g_musb_hcd[bus->hcd.hcd_id].port_pe = 1; + bus->hcd.roothub.int_buffer[0] = (1 << 1); + usbh_hub_thread_wakeup(&bus->hcd.roothub); + } + + if (is & USB_IS_DISCON) { + g_musb_hcd[bus->hcd.hcd_id].port_csc = 1; + g_musb_hcd[bus->hcd.hcd_id].port_pec = 1; + g_musb_hcd[bus->hcd.hcd_id].port_pe = 0; + bus->hcd.roothub.int_buffer[0] = (1 << 1); + usbh_hub_thread_wakeup(&bus->hcd.roothub); + } + + if (is & USB_IS_SOF) { + } + + if (is & USB_IS_RESUME) { + } + + if (is & USB_IS_SUSPEND) { + } + + if (is & USB_IS_VBUSERR) { + } + + if (is & USB_IS_SESREQ) { + } + + if (is & USB_IS_BABBLE) { + } + + txis &= HWREGH(USB_BASE + MUSB_TXIE_OFFSET); + /* Handle EP0 interrupt */ + if (txis & USB_TXIE_EP0) { + txis &= ~USB_TXIE_EP0; + HWREGH(USB_BASE + MUSB_TXIS_OFFSET) = USB_TXIE_EP0; + handle_ep0(bus); + } + + for (ep_idx = 1; ep_idx < CONFIG_USB_MUSB_PIPE_NUM; ep_idx++) { + if (txis & (1 << ep_idx)) { + HWREGH(USB_BASE + MUSB_TXIS_OFFSET) = (1 << ep_idx); + + pipe = &g_musb_hcd[bus->hcd.hcd_id].pipe_pool[ep_idx]; + urb = pipe->urb; + musb_set_active_ep(bus, ep_idx); + + ep_csrl_status = HWREGB(USB_TXCSRL_BASE(ep_idx)); + + if (ep_csrl_status & USB_TXCSRL1_ERROR) { + HWREGB(USB_TXCSRL_BASE(ep_idx)) &= ~USB_TXCSRL1_ERROR; + urb->errorcode = -USB_ERR_IO; + musb_urb_waitup(urb); + } else if (ep_csrl_status & USB_TXCSRL1_NAKTO) { + HWREGB(USB_TXCSRL_BASE(ep_idx)) &= ~USB_TXCSRL1_NAKTO; + urb->errorcode = -USB_ERR_NAK; + musb_urb_waitup(urb); + } else if (ep_csrl_status & USB_TXCSRL1_STALLED) { + HWREGB(USB_TXCSRL_BASE(ep_idx)) &= ~USB_TXCSRL1_STALLED; + urb->errorcode = -USB_ERR_STALL; + musb_urb_waitup(urb); + } else { + if (USB_GET_ENDPOINT_TYPE(urb->ep->bmAttributes) != USB_ENDPOINT_TYPE_ISOCHRONOUS) { + uint32_t size = urb->transfer_buffer_length; + + if (size > USB_GET_MAXPACKETSIZE(urb->ep->wMaxPacketSize)) { + size = USB_GET_MAXPACKETSIZE(urb->ep->wMaxPacketSize); + } + + urb->transfer_buffer += size; + urb->transfer_buffer_length -= size; + urb->actual_length += size; + + if (urb->transfer_buffer_length == 0) { + //HWREGH(USB_BASE + MUSB_TXIE_OFFSET) &= ~(1 << ep_idx); + urb->errorcode = 0; + musb_urb_waitup(urb); + } else { + musb_write_packet(bus, ep_idx, urb->transfer_buffer, MIN(urb->transfer_buffer_length, USB_GET_MAXPACKETSIZE(urb->ep->wMaxPacketSize))); + HWREGB(USB_TXCSRL_BASE(ep_idx)) = USB_TXCSRL1_TXRDY; + } + } + } + } + } + + rxis &= HWREGH(USB_BASE + MUSB_RXIE_OFFSET); + for (ep_idx = 1; ep_idx < CONFIG_USB_MUSB_PIPE_NUM; ep_idx++) { + if (rxis & (1 << ep_idx)) { + HWREGH(USB_BASE + MUSB_RXIS_OFFSET) = (1 << ep_idx); // clear isr flag + + pipe = &g_musb_hcd[bus->hcd.hcd_id].pipe_pool[ep_idx]; + urb = pipe->urb; + musb_set_active_ep(bus, ep_idx); + + ep_csrl_status = HWREGB(USB_RXCSRL_BASE(ep_idx)); + //ep_csrh_status = HWREGB(USB_BASE + USB_RXCSRH_BASE(ep_idx)); // todo:for iso transfer + + if (ep_csrl_status & USB_RXCSRL1_ERROR) { + HWREGB(USB_RXCSRL_BASE(ep_idx)) &= ~USB_RXCSRL1_ERROR; + urb->errorcode = -USB_ERR_IO; + musb_urb_waitup(urb); + } else if (ep_csrl_status & USB_RXCSRL1_NAKTO) { + HWREGB(USB_RXCSRL_BASE(ep_idx)) &= ~USB_RXCSRL1_NAKTO; + urb->errorcode = -USB_ERR_NAK; + musb_urb_waitup(urb); + } else if (ep_csrl_status & USB_RXCSRL1_STALLED) { + HWREGB(USB_RXCSRL_BASE(ep_idx)) &= ~USB_RXCSRL1_STALLED; + urb->errorcode = -USB_ERR_STALL; + musb_urb_waitup(urb); + } else if (ep_csrl_status & USB_RXCSRL1_RXRDY) { + if (USB_GET_ENDPOINT_TYPE(urb->ep->bmAttributes) != USB_ENDPOINT_TYPE_ISOCHRONOUS) { + size = HWREGH(USB_RXCOUNT_BASE(ep_idx)); + + musb_read_packet(bus, ep_idx, urb->transfer_buffer, size); + + HWREGB(USB_RXCSRL_BASE(ep_idx)) &= ~USB_RXCSRL1_RXRDY; + + urb->transfer_buffer += size; + urb->transfer_buffer_length -= size; + urb->actual_length += size; + + if ((size < USB_GET_MAXPACKETSIZE(urb->ep->wMaxPacketSize)) || (urb->transfer_buffer_length == 0)) { + //HWREGH(USB_BASE + MUSB_RXIE_OFFSET) &= ~(1 << ep_idx); + urb->errorcode = 0; + musb_urb_waitup(urb); + } else { + HWREGB(USB_RXCSRL_BASE(ep_idx)) = USB_RXCSRL1_REQPKT; + } + } + } + } + } + musb_set_active_ep(bus, old_ep_idx); +} diff --git a/kernel/cherryusb/port/musb/usb_musb_reg.h b/kernel/cherryusb/port/musb/usb_musb_reg.h new file mode 100644 index 0000000..1776537 --- /dev/null +++ b/kernel/cherryusb/port/musb/usb_musb_reg.h @@ -0,0 +1,3887 @@ +/* + * Copyright (c) 2022, sakumisu + * + * SPDX-License-Identifier: Apache-2.0 + */ +#ifndef __USB_MUSB_REG_H__ +#define __USB_MUSB_REG_H__ + +#define __I volatile const /* defines 'read only' permissions */ +#define __O volatile /* defines 'write only' permissions */ +#define __IO volatile /* defines 'read / write' permissions */ + +/** + * @brief Register map for USB0 peripheral (USB0) + */ +#ifdef CONFIG_USB_MUSB_SUNXI +#if 0 +typedef __PACKED_STRUCT { /*!< USB0 Structure */ + union { + __IO uint8_t FIFO0_BYTE; /*!< USB FIFO Endpoint 0 */ + __IO uint16_t FIFO0_HALF; /*!< USB FIFO Endpoint 0 */ + __IO uint32_t FIFO0_WORD; /*!< USB FIFO Endpoint 0 */ + } FIFO0; + union { + __IO uint8_t FIFO1_BYTE; /*!< USB FIFO Endpoint 1 */ + __IO uint16_t FIFO1_HALF; /*!< USB FIFO Endpoint 1 */ + __IO uint32_t FIFO1_WORD; /*!< USB FIFO Endpoint 1 */ + } FIFO1; + union { + __IO uint8_t FIFO2_BYTE; /*!< USB FIFO Endpoint 2 */ + __IO uint16_t FIFO2_HALF; /*!< USB FIFO Endpoint 2 */ + __IO uint32_t FIFO2_WORD; /*!< USB FIFO Endpoint 2 */ + } FIFO2; + union { + __IO uint8_t FIFO3_BYTE; /*!< USB FIFO Endpoint 3 */ + __IO uint16_t FIFO3_HALF; /*!< USB FIFO Endpoint 3 */ + __IO uint32_t FIFO3_WORD; /*!< USB FIFO Endpoint 3 */ + } FIFO3; + union { + __IO uint8_t FIFO4_BYTE; /*!< USB FIFO Endpoint 4 */ + __IO uint16_t FIFO4_HALF; /*!< USB FIFO Endpoint 4 */ + __IO uint32_t FIFO4_WORD; /*!< USB FIFO Endpoint 4 */ + } FIFO4; + union { + __IO uint8_t FIFO5_BYTE; /*!< USB FIFO Endpoint 5 */ + __IO uint16_t FIFO5_HALF; /*!< USB FIFO Endpoint 5 */ + __IO uint32_t FIFO5_WORD; /*!< USB FIFO Endpoint 5 */ + } FIFO5; + union { + __IO uint8_t FIFO6_BYTE; /*!< USB FIFO Endpoint 6 */ + __IO uint16_t FIFO6_HALF; /*!< USB FIFO Endpoint 6 */ + __IO uint32_t FIFO6_WORD; /*!< USB FIFO Endpoint 6 */ + } FIFO6; + union { + __IO uint8_t FIFO7_BYTE; /*!< USB FIFO Endpoint 7 */ + __IO uint16_t FIFO7_HALF; /*!< USB FIFO Endpoint 7 */ + __IO uint32_t FIFO7_WORD; /*!< USB FIFO Endpoint 7 */ + } FIFO7; + union { + __IO uint8_t FIFO_BYTE; /*!< USB FIFO Endpoint 7 */ + __IO uint16_t FIFO_HALF; /*!< USB FIFO Endpoint 7 */ + __IO uint32_t FIFO_WORD; /*!< USB FIFO Endpoint 7 */ + } FIFO_RESERVED[8]; + + // 0x40 + __IO uint8_t POWER; /*!< USB Power */ + __IO uint8_t DEVCTL; /*!< USB Device Control */ + __IO uint8_t EPIDX; /*!< USB Endpoint Index */ + __IO uint8_t VEND0; +// 0x44 + __IO uint16_t TXIS; /*!< USB Transmit Interrupt Status */ + __IO uint16_t RXIS; /*!< USB Receive Interrupt Status */ + // 0x48 + __IO uint16_t TXIE; /*!< USB Transmit Interrupt Enable */ + __IO uint16_t RXIE; /*!< USB Receive Interrupt Enable */ +// 0x4c + __IO uint8_t IS; /*!< USB General Interrupt Status */ + __I uint8_t IS_RESERVED[3]; + + __IO uint8_t IE; /*!< USB Interrupt Enable */ + __I uint8_t IE_RESERVED[3]; + + __IO uint16_t FRAME; /*!< USB Frame Value */ + __I uint8_t FRAME_RESERVED[34]; + + __IO uint8_t EPINFO; /*!< USB Endpoint Information */ + __IO uint8_t RAMINFO; /*!< USB RAM Information */ + __IO uint8_t LINKINFO; + __IO uint8_t VPLEN; /*!< USB OTG VBUS Pulse Timing */ +// 0x7c + __IO uint8_t HSEOF; /*!< USB High-Speed Last Transaction to End of Frame Timing */ + __IO uint8_t FSEOF; /*!< USB Full-Speed Last Transaction to End of Frame Timing */ + __IO uint8_t LSEOF; /*!< USB Low-Speed Last Transaction to End of Frame Timing */ + __I uint8_t RESERVED7F; + +// 0x80 + __IO uint16_t TXMAXP1; /*!< USB Maximum Transmit Data Endpoint 1 */ + __PACKED_UNION + { + __IO uint8_t CSRL0; + __IO uint8_t TXCSRL1; /*!< USB Transmit Control and Status Endpoint 1 Low */ + } ; + + __PACKED_UNION + { + __O uint8_t CSRH0; /*!< USB Control and Status Endpoint 0 High */ + __IO uint8_t TXCSRH1; /*!< USB Transmit Control and Status Endpoint 1 High */ + } ; +// 0x84 + __IO uint16_t RXMAXP1; /*!< USB Maximum Receive Data Endpoint 1 */ + __IO uint8_t RXCSRL1; /*!< USB Receive Control and Status Endpoint 1 Low */ + __IO uint8_t RXCSRH1; /*!< USB Receive Control and Status Endpoint 1 High */ + + __PACKED_UNION + { + __IO uint16_t COUNT0; + __IO uint16_t RXCOUNT1; /*!< USB Receive Byte Count Endpoint 1 */ + } ; + // 0x8A + __IO uint8_t TYPE0; /*!< USB Type Endpoint 0 */ + __IO uint8_t NAKLMT; /*!< USB NAK Limit */ + // 0x8C + __IO uint8_t TXTYPE1; /*!< USB Host Transmit Configure Type Endpoint 1 */ + __IO uint8_t TXINTERVAL1; /*!< USB Host Transmit Interval Endpoint 1 */ + __IO uint8_t RXTYPE1; /*!< USB Host Configure Receive Type Endpoint 1 */ + __IO uint8_t RXINTERVAL1; /*!< USB Host Receive Polling Interval Endpoint 1 */ +// 0x90 + __IO uint8_t TXFIFOSZ; /*!< USB Transmit Dynamic FIFO Sizing */ + __I uint8_t RESERVED91; + __IO uint16_t TXFIFOADD; /*!< USB Transmit FIFO Start Address */ +// 0x94 + __IO uint8_t RXFIFOSZ; /*!< USB Receive Dynamic FIFO Sizing */ + __I uint8_t RESERVED95; + __IO uint16_t RXFIFOADD; /*!< USB Receive FIFO Start Address */ + +/* "bus control"/target registers, for host side multipoint (external hubs) */ +// 0x98 + __PACKED_UNION + { + __IO uint8_t FADDR; + __IO uint8_t TXFUNCADDR0; + }; + + __I uint8_t RESERVERD99; +// 0x9A + __IO uint8_t TXHUBADDR0; + __IO uint8_t TXHUBPORT0; +// 0x9c + __IO uint8_t RXFUNCADDR0; + __I uint8_t RESERVED9d; + __IO uint8_t RXHUBADDR0; + __IO uint8_t RXHUBPORT0; +} USB0_Type; +#endif +#else +#if 0 +typedef struct { /*!< USB0 Structure */ + __IO uint8_t FADDR; /*!< USB Device Functional Address */ + __IO uint8_t POWER; /*!< USB Power */ + __IO uint16_t TXIS; /*!< USB Transmit Interrupt Status */ + __IO uint16_t RXIS; /*!< USB Receive Interrupt Status */ + __IO uint16_t TXIE; /*!< USB Transmit Interrupt Enable */ + __IO uint16_t RXIE; /*!< USB Receive Interrupt Enable */ + __IO uint8_t IS; /*!< USB General Interrupt Status */ + __IO uint8_t IE; /*!< USB Interrupt Enable */ + __IO uint16_t FRAME; /*!< USB Frame Value */ + __IO uint8_t EPIDX; /*!< USB Endpoint Index */ + __IO uint8_t TEST; /*!< USB Test Mode */ + __I uint32_t RESERVED0[4]; + union { + __IO uint8_t FIFO0_BYTE; /*!< USB FIFO Endpoint 0 */ + __IO uint16_t FIFO0_HALF; /*!< USB FIFO Endpoint 0 */ + __IO uint32_t FIFO0_WORD; /*!< USB FIFO Endpoint 0 */ + } FIFO0; + union { + __IO uint8_t FIFO1_BYTE; /*!< USB FIFO Endpoint 1 */ + __IO uint16_t FIFO1_HALF; /*!< USB FIFO Endpoint 1 */ + __IO uint32_t FIFO1_WORD; /*!< USB FIFO Endpoint 1 */ + } FIFO1; + union { + __IO uint8_t FIFO2_BYTE; /*!< USB FIFO Endpoint 2 */ + __IO uint16_t FIFO2_HALF; /*!< USB FIFO Endpoint 2 */ + __IO uint32_t FIFO2_WORD; /*!< USB FIFO Endpoint 2 */ + } FIFO2; + union { + __IO uint8_t FIFO3_BYTE; /*!< USB FIFO Endpoint 3 */ + __IO uint16_t FIFO3_HALF; /*!< USB FIFO Endpoint 3 */ + __IO uint32_t FIFO3_WORD; /*!< USB FIFO Endpoint 3 */ + } FIFO3; + union { + __IO uint8_t FIFO4_BYTE; /*!< USB FIFO Endpoint 4 */ + __IO uint16_t FIFO4_HALF; /*!< USB FIFO Endpoint 4 */ + __IO uint32_t FIFO4_WORD; /*!< USB FIFO Endpoint 4 */ + } FIFO4; + union { + __IO uint8_t FIFO5_BYTE; /*!< USB FIFO Endpoint 5 */ + __IO uint16_t FIFO5_HALF; /*!< USB FIFO Endpoint 5 */ + __IO uint32_t FIFO5_WORD; /*!< USB FIFO Endpoint 5 */ + } FIFO5; + union { + __IO uint8_t FIFO6_BYTE; /*!< USB FIFO Endpoint 6 */ + __IO uint16_t FIFO6_HALF; /*!< USB FIFO Endpoint 6 */ + __IO uint32_t FIFO6_WORD; /*!< USB FIFO Endpoint 6 */ + } FIFO6; + union { + __IO uint8_t FIFO7_BYTE; /*!< USB FIFO Endpoint 7 */ + __IO uint16_t FIFO7_HALF; /*!< USB FIFO Endpoint 7 */ + __IO uint32_t FIFO7_WORD; /*!< USB FIFO Endpoint 7 */ + } FIFO7; + __I uint32_t RESERVED1[8]; + __IO uint8_t DEVCTL; /*!< USB Device Control */ + __IO uint8_t CCONF; /*!< USB Common Configuration */ + __IO uint8_t TXFIFOSZ; /*!< USB Transmit Dynamic FIFO Sizing */ + __IO uint8_t RXFIFOSZ; /*!< USB Receive Dynamic FIFO Sizing */ + __IO uint16_t TXFIFOADD; /*!< USB Transmit FIFO Start Address */ + __IO uint16_t RXFIFOADD; /*!< USB Receive FIFO Start Address */ + __I uint32_t RESERVED2[2]; + __IO uint8_t ULPIVBUSCTL; /*!< USB ULPI VBUS Control */ + __I uint8_t RESERVED3[3]; + __IO uint8_t ULPIREGDATA; /*!< USB ULPI Register Data */ + __IO uint8_t ULPIREGADDR; /*!< USB ULPI Register Address */ + __IO uint8_t ULPIREGCTL; /*!< USB ULPI Register Control */ + __I uint8_t RESERVED4; + __IO uint8_t EPINFO; /*!< USB Endpoint Information */ + __IO uint8_t RAMINFO; /*!< USB RAM Information */ + __IO uint8_t CONTIM; /*!< USB Connect Timing */ + __IO uint8_t VPLEN; /*!< USB OTG VBUS Pulse Timing */ + __IO uint8_t HSEOF; /*!< USB High-Speed Last Transaction to End of Frame Timing */ + __IO uint8_t FSEOF; /*!< USB Full-Speed Last Transaction to End of Frame Timing */ + __IO uint8_t LSEOF; /*!< USB Low-Speed Last Transaction to End of Frame Timing */ + __I uint8_t RESERVED5; + __IO uint8_t TXFUNCADDR0; /*!< USB Transmit Functional Address Endpoint 0 */ + __I uint8_t RESERVED6; + __IO uint8_t TXHUBADDR0; /*!< USB Transmit Hub Address Endpoint 0 */ + __IO uint8_t TXHUBPORT0; /*!< USB Transmit Hub Port Endpoint 0 */ + __I uint32_t RESERVED7; + __IO uint8_t TXFUNCADDR1; /*!< USB Transmit Functional Address Endpoint 1 */ + __I uint8_t RESERVED8; + __IO uint8_t TXHUBADDR1; /*!< USB Transmit Hub Address Endpoint 1 */ + __IO uint8_t TXHUBPORT1; /*!< USB Transmit Hub Port Endpoint 1 */ + __IO uint8_t RXFUNCADDR1; /*!< USB Receive Functional Address Endpoint 1 */ + __I uint8_t RESERVED9; + __IO uint8_t RXHUBADDR1; /*!< USB Receive Hub Address Endpoint 1 */ + __IO uint8_t RXHUBPORT1; /*!< USB Receive Hub Port Endpoint 1 */ + __IO uint8_t TXFUNCADDR2; /*!< USB Transmit Functional Address Endpoint 2 */ + __I uint8_t RESERVED10; + __IO uint8_t TXHUBADDR2; /*!< USB Transmit Hub Address Endpoint 2 */ + __IO uint8_t TXHUBPORT2; /*!< USB Transmit Hub Port Endpoint 2 */ + __IO uint8_t RXFUNCADDR2; /*!< USB Receive Functional Address Endpoint 2 */ + __I uint8_t RESERVED11; + __IO uint8_t RXHUBADDR2; /*!< USB Receive Hub Address Endpoint 2 */ + __IO uint8_t RXHUBPORT2; /*!< USB Receive Hub Port Endpoint 2 */ + __IO uint8_t TXFUNCADDR3; /*!< USB Transmit Functional Address Endpoint 3 */ + __I uint8_t RESERVED12; + __IO uint8_t TXHUBADDR3; /*!< USB Transmit Hub Address Endpoint 3 */ + __IO uint8_t TXHUBPORT3; /*!< USB Transmit Hub Port Endpoint 3 */ + __IO uint8_t RXFUNCADDR3; /*!< USB Receive Functional Address Endpoint 3 */ + __I uint8_t RESERVED13; + __IO uint8_t RXHUBADDR3; /*!< USB Receive Hub Address Endpoint 3 */ + __IO uint8_t RXHUBPORT3; /*!< USB Receive Hub Port Endpoint 3 */ + __IO uint8_t TXFUNCADDR4; /*!< USB Transmit Functional Address Endpoint 4 */ + __I uint8_t RESERVED14; + __IO uint8_t TXHUBADDR4; /*!< USB Transmit Hub Address Endpoint 4 */ + __IO uint8_t TXHUBPORT4; /*!< USB Transmit Hub Port Endpoint 4 */ + __IO uint8_t RXFUNCADDR4; /*!< USB Receive Functional Address Endpoint 4 */ + __I uint8_t RESERVED15; + __IO uint8_t RXHUBADDR4; /*!< USB Receive Hub Address Endpoint 4 */ + __IO uint8_t RXHUBPORT4; /*!< USB Receive Hub Port Endpoint 4 */ + __IO uint8_t TXFUNCADDR5; /*!< USB Transmit Functional Address Endpoint 5 */ + __I uint8_t RESERVED16; + __IO uint8_t TXHUBADDR5; /*!< USB Transmit Hub Address Endpoint 5 */ + __IO uint8_t TXHUBPORT5; /*!< USB Transmit Hub Port Endpoint 5 */ + __IO uint8_t RXFUNCADDR5; /*!< USB Receive Functional Address Endpoint 5 */ + __I uint8_t RESERVED17; + __IO uint8_t RXHUBADDR5; /*!< USB Receive Hub Address Endpoint 5 */ + __IO uint8_t RXHUBPORT5; /*!< USB Receive Hub Port Endpoint 5 */ + __IO uint8_t TXFUNCADDR6; /*!< USB Transmit Functional Address Endpoint 6 */ + __I uint8_t RESERVED18; + __IO uint8_t TXHUBADDR6; /*!< USB Transmit Hub Address Endpoint 6 */ + __IO uint8_t TXHUBPORT6; /*!< USB Transmit Hub Port Endpoint 6 */ + __IO uint8_t RXFUNCADDR6; /*!< USB Receive Functional Address Endpoint 6 */ + __I uint8_t RESERVED19; + __IO uint8_t RXHUBADDR6; /*!< USB Receive Hub Address Endpoint 6 */ + __IO uint8_t RXHUBPORT6; /*!< USB Receive Hub Port Endpoint 6 */ + __IO uint8_t TXFUNCADDR7; /*!< USB Transmit Functional Address Endpoint 7 */ + __I uint8_t RESERVED20; + __IO uint8_t TXHUBADDR7; /*!< USB Transmit Hub Address Endpoint 7 */ + __IO uint8_t TXHUBPORT7; /*!< USB Transmit Hub Port Endpoint 7 */ + __IO uint8_t RXFUNCADDR7; /*!< USB Receive Functional Address Endpoint 7 */ + __I uint8_t RESERVED21; + __IO uint8_t RXHUBADDR7; /*!< USB Receive Hub Address Endpoint 7 */ + __IO uint8_t RXHUBPORT7; /*!< USB Receive Hub Port Endpoint 7 */ + __I uint32_t RESERVED22[16]; + __I uint16_t RESERVED23; + __O uint8_t CSRL0; /*!< USB Control and Status Endpoint 0 Low */ + __O uint8_t CSRH0; /*!< USB Control and Status Endpoint 0 High */ + __I uint16_t RESERVED24[2]; + __IO uint8_t COUNT0; /*!< USB Receive Byte Count Endpoint 0 */ + __I uint8_t RESERVED25; + __IO uint8_t TYPE0; /*!< USB Type Endpoint 0 */ + __IO uint8_t NAKLMT; /*!< USB NAK Limit */ + __I uint32_t RESERVED26; + __IO uint16_t TXMAXP1; /*!< USB Maximum Transmit Data Endpoint 1 */ + __IO uint8_t TXCSRL1; /*!< USB Transmit Control and Status Endpoint 1 Low */ + __IO uint8_t TXCSRH1; /*!< USB Transmit Control and Status Endpoint 1 High */ + __IO uint16_t RXMAXP1; /*!< USB Maximum Receive Data Endpoint 1 */ + __IO uint8_t RXCSRL1; /*!< USB Receive Control and Status Endpoint 1 Low */ + __IO uint8_t RXCSRH1; /*!< USB Receive Control and Status Endpoint 1 High */ + __IO uint16_t RXCOUNT1; /*!< USB Receive Byte Count Endpoint 1 */ + __IO uint8_t TXTYPE1; /*!< USB Host Transmit Configure Type Endpoint 1 */ + __IO uint8_t TXINTERVAL1; /*!< USB Host Transmit Interval Endpoint 1 */ + __IO uint8_t RXTYPE1; /*!< USB Host Configure Receive Type Endpoint 1 */ + __IO uint8_t RXINTERVAL1; /*!< USB Host Receive Polling Interval Endpoint 1 */ + __I uint16_t RESERVED27; + __IO uint16_t TXMAXP2; /*!< USB Maximum Transmit Data Endpoint 2 */ + __IO uint8_t TXCSRL2; /*!< USB Transmit Control and Status Endpoint 2 Low */ + __IO uint8_t TXCSRH2; /*!< USB Transmit Control and Status Endpoint 2 High */ + __IO uint16_t RXMAXP2; /*!< USB Maximum Receive Data Endpoint 2 */ + __IO uint8_t RXCSRL2; /*!< USB Receive Control and Status Endpoint 2 Low */ + __IO uint8_t RXCSRH2; /*!< USB Receive Control and Status Endpoint 2 High */ + __IO uint16_t RXCOUNT2; /*!< USB Receive Byte Count Endpoint 2 */ + __IO uint8_t TXTYPE2; /*!< USB Host Transmit Configure Type Endpoint 2 */ + __IO uint8_t TXINTERVAL2; /*!< USB Host Transmit Interval Endpoint 2 */ + __IO uint8_t RXTYPE2; /*!< USB Host Configure Receive Type Endpoint 2 */ + __IO uint8_t RXINTERVAL2; /*!< USB Host Receive Polling Interval Endpoint 2 */ + __I uint16_t RESERVED28; + __IO uint16_t TXMAXP3; /*!< USB Maximum Transmit Data Endpoint 3 */ + __IO uint8_t TXCSRL3; /*!< USB Transmit Control and Status Endpoint 3 Low */ + __IO uint8_t TXCSRH3; /*!< USB Transmit Control and Status Endpoint 3 High */ + __IO uint16_t RXMAXP3; /*!< USB Maximum Receive Data Endpoint 3 */ + __IO uint8_t RXCSRL3; /*!< USB Receive Control and Status Endpoint 3 Low */ + __IO uint8_t RXCSRH3; /*!< USB Receive Control and Status Endpoint 3 High */ + __IO uint16_t RXCOUNT3; /*!< USB Receive Byte Count Endpoint 3 */ + __IO uint8_t TXTYPE3; /*!< USB Host Transmit Configure Type Endpoint 3 */ + __IO uint8_t TXINTERVAL3; /*!< USB Host Transmit Interval Endpoint 3 */ + __IO uint8_t RXTYPE3; /*!< USB Host Configure Receive Type Endpoint 3 */ + __IO uint8_t RXINTERVAL3; /*!< USB Host Receive Polling Interval Endpoint 3 */ + __I uint16_t RESERVED29; + __IO uint16_t TXMAXP4; /*!< USB Maximum Transmit Data Endpoint 4 */ + __IO uint8_t TXCSRL4; /*!< USB Transmit Control and Status Endpoint 4 Low */ + __IO uint8_t TXCSRH4; /*!< USB Transmit Control and Status Endpoint 4 High */ + __IO uint16_t RXMAXP4; /*!< USB Maximum Receive Data Endpoint 4 */ + __IO uint8_t RXCSRL4; /*!< USB Receive Control and Status Endpoint 4 Low */ + __IO uint8_t RXCSRH4; /*!< USB Receive Control and Status Endpoint 4 High */ + __IO uint16_t RXCOUNT4; /*!< USB Receive Byte Count Endpoint 4 */ + __IO uint8_t TXTYPE4; /*!< USB Host Transmit Configure Type Endpoint 4 */ + __IO uint8_t TXINTERVAL4; /*!< USB Host Transmit Interval Endpoint 4 */ + __IO uint8_t RXTYPE4; /*!< USB Host Configure Receive Type Endpoint 4 */ + __IO uint8_t RXINTERVAL4; /*!< USB Host Receive Polling Interval Endpoint 4 */ + __I uint16_t RESERVED30; + __IO uint16_t TXMAXP5; /*!< USB Maximum Transmit Data Endpoint 5 */ + __IO uint8_t TXCSRL5; /*!< USB Transmit Control and Status Endpoint 5 Low */ + __IO uint8_t TXCSRH5; /*!< USB Transmit Control and Status Endpoint 5 High */ + __IO uint16_t RXMAXP5; /*!< USB Maximum Receive Data Endpoint 5 */ + __IO uint8_t RXCSRL5; /*!< USB Receive Control and Status Endpoint 5 Low */ + __IO uint8_t RXCSRH5; /*!< USB Receive Control and Status Endpoint 5 High */ + __IO uint16_t RXCOUNT5; /*!< USB Receive Byte Count Endpoint 5 */ + __IO uint8_t TXTYPE5; /*!< USB Host Transmit Configure Type Endpoint 5 */ + __IO uint8_t TXINTERVAL5; /*!< USB Host Transmit Interval Endpoint 5 */ + __IO uint8_t RXTYPE5; /*!< USB Host Configure Receive Type Endpoint 5 */ + __IO uint8_t RXINTERVAL5; /*!< USB Host Receive Polling Interval Endpoint 5 */ + __I uint16_t RESERVED31; + __IO uint16_t TXMAXP6; /*!< USB Maximum Transmit Data Endpoint 6 */ + __IO uint8_t TXCSRL6; /*!< USB Transmit Control and Status Endpoint 6 Low */ + __IO uint8_t TXCSRH6; /*!< USB Transmit Control and Status Endpoint 6 High */ + __IO uint16_t RXMAXP6; /*!< USB Maximum Receive Data Endpoint 6 */ + __IO uint8_t RXCSRL6; /*!< USB Receive Control and Status Endpoint 6 Low */ + __IO uint8_t RXCSRH6; /*!< USB Receive Control and Status Endpoint 6 High */ + __IO uint16_t RXCOUNT6; /*!< USB Receive Byte Count Endpoint 6 */ + __IO uint8_t TXTYPE6; /*!< USB Host Transmit Configure Type Endpoint 6 */ + __IO uint8_t TXINTERVAL6; /*!< USB Host Transmit Interval Endpoint 6 */ + __IO uint8_t RXTYPE6; /*!< USB Host Configure Receive Type Endpoint 6 */ + __IO uint8_t RXINTERVAL6; /*!< USB Host Receive Polling Interval Endpoint 6 */ + __I uint16_t RESERVED32; + __IO uint16_t TXMAXP7; /*!< USB Maximum Transmit Data Endpoint 7 */ + __IO uint8_t TXCSRL7; /*!< USB Transmit Control and Status Endpoint 7 Low */ + __IO uint8_t TXCSRH7; /*!< USB Transmit Control and Status Endpoint 7 High */ + __IO uint16_t RXMAXP7; /*!< USB Maximum Receive Data Endpoint 7 */ + __IO uint8_t RXCSRL7; /*!< USB Receive Control and Status Endpoint 7 Low */ + __IO uint8_t RXCSRH7; /*!< USB Receive Control and Status Endpoint 7 High */ + __IO uint16_t RXCOUNT7; /*!< USB Receive Byte Count Endpoint 7 */ + __IO uint8_t TXTYPE7; /*!< USB Host Transmit Configure Type Endpoint 7 */ + __IO uint8_t TXINTERVAL7; /*!< USB Host Transmit Interval Endpoint 7 */ + __IO uint8_t RXTYPE7; /*!< USB Host Configure Receive Type Endpoint 7 */ + __IO uint8_t RXINTERVAL7; /*!< USB Host Receive Polling Interval Endpoint 7 */ + __I uint16_t RESERVED33[65]; + __IO uint8_t DMAINTR; /*!< USB DMA Interrupt */ + __I uint8_t RESERVED34[3]; + __IO uint16_t DMACTL0; /*!< USB DMA Control 0 */ + __I uint16_t RESERVED35; + __IO uint32_t DMAADDR0; /*!< USB DMA Address 0 */ + __IO uint32_t DMACOUNT0; /*!< USB DMA Count 0 */ + __I uint32_t RESERVED36; + __IO uint16_t DMACTL1; /*!< USB DMA Control 1 */ + __I uint16_t RESERVED37; + __IO uint32_t DMAADDR1; /*!< USB DMA Address 1 */ + __IO uint32_t DMACOUNT1; /*!< USB DMA Count 1 */ + __I uint32_t RESERVED38; + __IO uint16_t DMACTL2; /*!< USB DMA Control 2 */ + __I uint16_t RESERVED39; + __IO uint32_t DMAADDR2; /*!< USB DMA Address 2 */ + __IO uint32_t DMACOUNT2; /*!< USB DMA Count 2 */ + __I uint32_t RESERVED40; + __IO uint16_t DMACTL3; /*!< USB DMA Control 3 */ + __I uint16_t RESERVED41; + __IO uint32_t DMAADDR3; /*!< USB DMA Address 3 */ + __IO uint32_t DMACOUNT3; /*!< USB DMA Count 3 */ + __I uint32_t RESERVED42; + __IO uint16_t DMACTL4; /*!< USB DMA Control 4 */ + __I uint16_t RESERVED43; + __IO uint32_t DMAADDR4; /*!< USB DMA Address 4 */ + __IO uint32_t DMACOUNT4; /*!< USB DMA Count 4 */ + __I uint32_t RESERVED44; + __IO uint16_t DMACTL5; /*!< USB DMA Control 5 */ + __I uint16_t RESERVED45; + __IO uint32_t DMAADDR5; /*!< USB DMA Address 5 */ + __IO uint32_t DMACOUNT5; /*!< USB DMA Count 5 */ + __I uint32_t RESERVED46; + __IO uint16_t DMACTL6; /*!< USB DMA Control 6 */ + __I uint16_t RESERVED47; + __IO uint32_t DMAADDR6; /*!< USB DMA Address 6 */ + __IO uint32_t DMACOUNT6; /*!< USB DMA Count 6 */ + __I uint32_t RESERVED48; + __IO uint16_t DMACTL7; /*!< USB DMA Control 7 */ + __I uint16_t RESERVED49; + __IO uint32_t DMAADDR7; /*!< USB DMA Address 7 */ + __IO uint32_t DMACOUNT7; /*!< USB DMA Count 7 */ + __I uint32_t RESERVED50[33]; + __IO uint16_t RQPKTCOUNT1; /*!< USB Request Packet Count in Block Transfer Endpoint 1 */ + __I uint16_t RESERVED51; + __IO uint16_t RQPKTCOUNT2; /*!< USB Request Packet Count in Block Transfer Endpoint 2 */ + __I uint16_t RESERVED52; + __IO uint16_t RQPKTCOUNT3; /*!< USB Request Packet Count in Block Transfer Endpoint 3 */ + __I uint16_t RESERVED53; + __IO uint16_t RQPKTCOUNT4; /*!< USB Request Packet Count in Block Transfer Endpoint 4 */ + __I uint16_t RESERVED54; + __IO uint16_t RQPKTCOUNT5; /*!< USB Request Packet Count in Block Transfer Endpoint 5 */ + __I uint16_t RESERVED55; + __IO uint16_t RQPKTCOUNT6; /*!< USB Request Packet Count in Block Transfer Endpoint 6 */ + __I uint16_t RESERVED56; + __IO uint16_t RQPKTCOUNT7; /*!< USB Request Packet Count in Block Transfer Endpoint 7 */ + __I uint16_t RESERVED57[17]; + __IO uint16_t RXDPKTBUFDIS; /*!< USB Receive Double Packet Buffer Disable */ + __IO uint16_t TXDPKTBUFDIS; /*!< USB Transmit Double Packet Buffer Disable */ + __IO uint16_t CTO; /*!< USB Chirp Timeout */ + __IO uint16_t HHSRTN; /*!< USB High Speed to UTM Operating Delay */ + __IO uint16_t HSBT; /*!< USB High Speed Time-out Adder */ + __I uint16_t RESERVED58[11]; + __IO uint16_t LPMATTR; /*!< USB LPM Attributes */ + __IO uint8_t LPMCNTRL; /*!< USB LPM Control */ + __IO uint8_t LPMIM; /*!< USB LPM Interrupt Mask */ + __IO uint8_t LPMRIS; /*!< USB LPM Raw Interrupt Status */ + __IO uint8_t LPMFADDR; /*!< USB LPM Function Address */ + __I uint16_t RESERVED59[77]; + __IO uint32_t EPC; /*!< USB External Power Control */ + __IO uint32_t EPCRIS; /*!< USB External Power Control Raw Interrupt Status */ + __IO uint32_t EPCIM; /*!< USB External Power Control Interrupt Mask */ + __IO uint32_t EPCISC; /*!< USB External Power Control Interrupt Status and Clear */ + __IO uint32_t DRRIS; /*!< USB Device RESUME Raw Interrupt Status */ + __IO uint32_t DRIM; /*!< USB Device RESUME Interrupt Mask */ + __O uint32_t DRISC; /*!< USB Device RESUME Interrupt Status and Clear */ + __IO uint32_t GPCS; /*!< USB General-Purpose Control and Status */ + __I uint32_t RESERVED60[4]; + __IO uint32_t VDC; /*!< USB VBUS Droop Control */ + __IO uint32_t VDCRIS; /*!< USB VBUS Droop Control Raw Interrupt Status */ + __IO uint32_t VDCIM; /*!< USB VBUS Droop Control Interrupt Mask */ + __IO uint32_t VDCISC; /*!< USB VBUS Droop Control Interrupt Status and Clear */ + __I uint32_t RESERVED61[736]; + __IO uint32_t PP; /*!< USB Peripheral Properties */ + __IO uint32_t PC; /*!< USB Peripheral Configuration */ + __IO uint32_t CC; /*!< USB Clock Configuration */ +} USB0_Type; +#endif +#endif // CONFIG_USB_MUSB_SUNXI + +//***************************************************************************** +// +// The following are defines for the Univeral Serial Bus register offsets. +// +//***************************************************************************** +#define USB_O_FADDR 0x00000000 // USB Device Functional Address +#define USB_O_POWER 0x00000001 // USB Power +#define USB_O_TXIS 0x00000002 // USB Transmit Interrupt Status +#define USB_O_RXIS 0x00000004 // USB Receive Interrupt Status +#define USB_O_TXIE 0x00000006 // USB Transmit Interrupt Enable +#define USB_O_RXIE 0x00000008 // USB Receive Interrupt Enable +#define USB_O_IS 0x0000000A // USB General Interrupt Status +#define USB_O_IE 0x0000000B // USB Interrupt Enable +#define USB_O_FRAME 0x0000000C // USB Frame Value +#define USB_O_EPIDX 0x0000000E // USB Endpoint Index +#define USB_O_TEST 0x0000000F // USB Test Mode +#define USB_O_FIFO0 0x00000020 // USB FIFO Endpoint 0 +#define USB_O_FIFO1 0x00000024 // USB FIFO Endpoint 1 +#define USB_O_FIFO2 0x00000028 // USB FIFO Endpoint 2 +#define USB_O_FIFO3 0x0000002C // USB FIFO Endpoint 3 +#define USB_O_FIFO4 0x00000030 // USB FIFO Endpoint 4 +#define USB_O_FIFO5 0x00000034 // USB FIFO Endpoint 5 +#define USB_O_FIFO6 0x00000038 // USB FIFO Endpoint 6 +#define USB_O_FIFO7 0x0000003C // USB FIFO Endpoint 7 +#define USB_O_DEVCTL 0x00000060 // USB Device Control +#define USB_O_CCONF 0x00000061 // USB Common Configuration +#define USB_O_TXFIFOSZ 0x00000062 // USB Transmit Dynamic FIFO Sizing +#define USB_O_RXFIFOSZ 0x00000063 // USB Receive Dynamic FIFO Sizing +#define USB_O_TXFIFOADD 0x00000064 // USB Transmit FIFO Start Address +#define USB_O_RXFIFOADD 0x00000066 // USB Receive FIFO Start Address +#define USB_O_ULPIVBUSCTL 0x00000070 // USB ULPI VBUS Control +#define USB_O_ULPIREGDATA 0x00000074 // USB ULPI Register Data +#define USB_O_ULPIREGADDR 0x00000075 // USB ULPI Register Address +#define USB_O_ULPIREGCTL 0x00000076 // USB ULPI Register Control +#define USB_O_EPINFO 0x00000078 // USB Endpoint Information +#define USB_O_RAMINFO 0x00000079 // USB RAM Information +#define USB_O_CONTIM 0x0000007A // USB Connect Timing +#define USB_O_VPLEN 0x0000007B // USB OTG VBUS Pulse Timing +#define USB_O_HSEOF 0x0000007C // USB High-Speed Last Transaction + // to End of Frame Timing +#define USB_O_FSEOF 0x0000007D // USB Full-Speed Last Transaction + // to End of Frame Timing +#define USB_O_LSEOF 0x0000007E // USB Low-Speed Last Transaction + // to End of Frame Timing +#define USB_O_TXFUNCADDR0 0x00000080 // USB Transmit Functional Address + // Endpoint 0 +#define USB_O_TXHUBADDR0 0x00000082 // USB Transmit Hub Address + // Endpoint 0 +#define USB_O_TXHUBPORT0 0x00000083 // USB Transmit Hub Port Endpoint 0 +#define USB_O_TXFUNCADDR1 0x00000088 // USB Transmit Functional Address + // Endpoint 1 +#define USB_O_TXHUBADDR1 0x0000008A // USB Transmit Hub Address + // Endpoint 1 +#define USB_O_TXHUBPORT1 0x0000008B // USB Transmit Hub Port Endpoint 1 +#define USB_O_RXFUNCADDR1 0x0000008C // USB Receive Functional Address + // Endpoint 1 +#define USB_O_RXHUBADDR1 0x0000008E // USB Receive Hub Address Endpoint + // 1 +#define USB_O_RXHUBPORT1 0x0000008F // USB Receive Hub Port Endpoint 1 +#define USB_O_TXFUNCADDR2 0x00000090 // USB Transmit Functional Address + // Endpoint 2 +#define USB_O_TXHUBADDR2 0x00000092 // USB Transmit Hub Address + // Endpoint 2 +#define USB_O_TXHUBPORT2 0x00000093 // USB Transmit Hub Port Endpoint 2 +#define USB_O_RXFUNCADDR2 0x00000094 // USB Receive Functional Address + // Endpoint 2 +#define USB_O_RXHUBADDR2 0x00000096 // USB Receive Hub Address Endpoint + // 2 +#define USB_O_RXHUBPORT2 0x00000097 // USB Receive Hub Port Endpoint 2 +#define USB_O_TXFUNCADDR3 0x00000098 // USB Transmit Functional Address + // Endpoint 3 +#define USB_O_TXHUBADDR3 0x0000009A // USB Transmit Hub Address + // Endpoint 3 +#define USB_O_TXHUBPORT3 0x0000009B // USB Transmit Hub Port Endpoint 3 +#define USB_O_RXFUNCADDR3 0x0000009C // USB Receive Functional Address + // Endpoint 3 +#define USB_O_RXHUBADDR3 0x0000009E // USB Receive Hub Address Endpoint + // 3 +#define USB_O_RXHUBPORT3 0x0000009F // USB Receive Hub Port Endpoint 3 +#define USB_O_TXFUNCADDR4 0x000000A0 // USB Transmit Functional Address + // Endpoint 4 +#define USB_O_TXHUBADDR4 0x000000A2 // USB Transmit Hub Address + // Endpoint 4 +#define USB_O_TXHUBPORT4 0x000000A3 // USB Transmit Hub Port Endpoint 4 +#define USB_O_RXFUNCADDR4 0x000000A4 // USB Receive Functional Address + // Endpoint 4 +#define USB_O_RXHUBADDR4 0x000000A6 // USB Receive Hub Address Endpoint + // 4 +#define USB_O_RXHUBPORT4 0x000000A7 // USB Receive Hub Port Endpoint 4 +#define USB_O_TXFUNCADDR5 0x000000A8 // USB Transmit Functional Address + // Endpoint 5 +#define USB_O_TXHUBADDR5 0x000000AA // USB Transmit Hub Address + // Endpoint 5 +#define USB_O_TXHUBPORT5 0x000000AB // USB Transmit Hub Port Endpoint 5 +#define USB_O_RXFUNCADDR5 0x000000AC // USB Receive Functional Address + // Endpoint 5 +#define USB_O_RXHUBADDR5 0x000000AE // USB Receive Hub Address Endpoint + // 5 +#define USB_O_RXHUBPORT5 0x000000AF // USB Receive Hub Port Endpoint 5 +#define USB_O_TXFUNCADDR6 0x000000B0 // USB Transmit Functional Address + // Endpoint 6 +#define USB_O_TXHUBADDR6 0x000000B2 // USB Transmit Hub Address + // Endpoint 6 +#define USB_O_TXHUBPORT6 0x000000B3 // USB Transmit Hub Port Endpoint 6 +#define USB_O_RXFUNCADDR6 0x000000B4 // USB Receive Functional Address + // Endpoint 6 +#define USB_O_RXHUBADDR6 0x000000B6 // USB Receive Hub Address Endpoint + // 6 +#define USB_O_RXHUBPORT6 0x000000B7 // USB Receive Hub Port Endpoint 6 +#define USB_O_TXFUNCADDR7 0x000000B8 // USB Transmit Functional Address + // Endpoint 7 +#define USB_O_TXHUBADDR7 0x000000BA // USB Transmit Hub Address + // Endpoint 7 +#define USB_O_TXHUBPORT7 0x000000BB // USB Transmit Hub Port Endpoint 7 +#define USB_O_RXFUNCADDR7 0x000000BC // USB Receive Functional Address + // Endpoint 7 +#define USB_O_RXHUBADDR7 0x000000BE // USB Receive Hub Address Endpoint + // 7 +#define USB_O_RXHUBPORT7 0x000000BF // USB Receive Hub Port Endpoint 7 +#define USB_O_CSRL0 0x00000102 // USB Control and Status Endpoint + // 0 Low +#define USB_O_CSRH0 0x00000103 // USB Control and Status Endpoint + // 0 High +#define USB_O_COUNT0 0x00000108 // USB Receive Byte Count Endpoint + // 0 +#define USB_O_TYPE0 0x0000010A // USB Type Endpoint 0 +#define USB_O_NAKLMT 0x0000010B // USB NAK Limit +#define USB_O_TXMAXP1 0x00000110 // USB Maximum Transmit Data + // Endpoint 1 +#define USB_O_TXCSRL1 0x00000112 // USB Transmit Control and Status + // Endpoint 1 Low +#define USB_O_TXCSRH1 0x00000113 // USB Transmit Control and Status + // Endpoint 1 High +#define USB_O_RXMAXP1 0x00000114 // USB Maximum Receive Data + // Endpoint 1 +#define USB_O_RXCSRL1 0x00000116 // USB Receive Control and Status + // Endpoint 1 Low +#define USB_O_RXCSRH1 0x00000117 // USB Receive Control and Status + // Endpoint 1 High +#define USB_O_RXCOUNT1 0x00000118 // USB Receive Byte Count Endpoint + // 1 +#define USB_O_TXTYPE1 0x0000011A // USB Host Transmit Configure Type + // Endpoint 1 +#define USB_O_TXINTERVAL1 0x0000011B // USB Host Transmit Interval + // Endpoint 1 +#define USB_O_RXTYPE1 0x0000011C // USB Host Configure Receive Type + // Endpoint 1 +#define USB_O_RXINTERVAL1 0x0000011D // USB Host Receive Polling + // Interval Endpoint 1 +#define USB_O_TXMAXP2 0x00000120 // USB Maximum Transmit Data + // Endpoint 2 +#define USB_O_TXCSRL2 0x00000122 // USB Transmit Control and Status + // Endpoint 2 Low +#define USB_O_TXCSRH2 0x00000123 // USB Transmit Control and Status + // Endpoint 2 High +#define USB_O_RXMAXP2 0x00000124 // USB Maximum Receive Data + // Endpoint 2 +#define USB_O_RXCSRL2 0x00000126 // USB Receive Control and Status + // Endpoint 2 Low +#define USB_O_RXCSRH2 0x00000127 // USB Receive Control and Status + // Endpoint 2 High +#define USB_O_RXCOUNT2 0x00000128 // USB Receive Byte Count Endpoint + // 2 +#define USB_O_TXTYPE2 0x0000012A // USB Host Transmit Configure Type + // Endpoint 2 +#define USB_O_TXINTERVAL2 0x0000012B // USB Host Transmit Interval + // Endpoint 2 +#define USB_O_RXTYPE2 0x0000012C // USB Host Configure Receive Type + // Endpoint 2 +#define USB_O_RXINTERVAL2 0x0000012D // USB Host Receive Polling + // Interval Endpoint 2 +#define USB_O_TXMAXP3 0x00000130 // USB Maximum Transmit Data + // Endpoint 3 +#define USB_O_TXCSRL3 0x00000132 // USB Transmit Control and Status + // Endpoint 3 Low +#define USB_O_TXCSRH3 0x00000133 // USB Transmit Control and Status + // Endpoint 3 High +#define USB_O_RXMAXP3 0x00000134 // USB Maximum Receive Data + // Endpoint 3 +#define USB_O_RXCSRL3 0x00000136 // USB Receive Control and Status + // Endpoint 3 Low +#define USB_O_RXCSRH3 0x00000137 // USB Receive Control and Status + // Endpoint 3 High +#define USB_O_RXCOUNT3 0x00000138 // USB Receive Byte Count Endpoint + // 3 +#define USB_O_TXTYPE3 0x0000013A // USB Host Transmit Configure Type + // Endpoint 3 +#define USB_O_TXINTERVAL3 0x0000013B // USB Host Transmit Interval + // Endpoint 3 +#define USB_O_RXTYPE3 0x0000013C // USB Host Configure Receive Type + // Endpoint 3 +#define USB_O_RXINTERVAL3 0x0000013D // USB Host Receive Polling + // Interval Endpoint 3 +#define USB_O_TXMAXP4 0x00000140 // USB Maximum Transmit Data + // Endpoint 4 +#define USB_O_TXCSRL4 0x00000142 // USB Transmit Control and Status + // Endpoint 4 Low +#define USB_O_TXCSRH4 0x00000143 // USB Transmit Control and Status + // Endpoint 4 High +#define USB_O_RXMAXP4 0x00000144 // USB Maximum Receive Data + // Endpoint 4 +#define USB_O_RXCSRL4 0x00000146 // USB Receive Control and Status + // Endpoint 4 Low +#define USB_O_RXCSRH4 0x00000147 // USB Receive Control and Status + // Endpoint 4 High +#define USB_O_RXCOUNT4 0x00000148 // USB Receive Byte Count Endpoint + // 4 +#define USB_O_TXTYPE4 0x0000014A // USB Host Transmit Configure Type + // Endpoint 4 +#define USB_O_TXINTERVAL4 0x0000014B // USB Host Transmit Interval + // Endpoint 4 +#define USB_O_RXTYPE4 0x0000014C // USB Host Configure Receive Type + // Endpoint 4 +#define USB_O_RXINTERVAL4 0x0000014D // USB Host Receive Polling + // Interval Endpoint 4 +#define USB_O_TXMAXP5 0x00000150 // USB Maximum Transmit Data + // Endpoint 5 +#define USB_O_TXCSRL5 0x00000152 // USB Transmit Control and Status + // Endpoint 5 Low +#define USB_O_TXCSRH5 0x00000153 // USB Transmit Control and Status + // Endpoint 5 High +#define USB_O_RXMAXP5 0x00000154 // USB Maximum Receive Data + // Endpoint 5 +#define USB_O_RXCSRL5 0x00000156 // USB Receive Control and Status + // Endpoint 5 Low +#define USB_O_RXCSRH5 0x00000157 // USB Receive Control and Status + // Endpoint 5 High +#define USB_O_RXCOUNT5 0x00000158 // USB Receive Byte Count Endpoint + // 5 +#define USB_O_TXTYPE5 0x0000015A // USB Host Transmit Configure Type + // Endpoint 5 +#define USB_O_TXINTERVAL5 0x0000015B // USB Host Transmit Interval + // Endpoint 5 +#define USB_O_RXTYPE5 0x0000015C // USB Host Configure Receive Type + // Endpoint 5 +#define USB_O_RXINTERVAL5 0x0000015D // USB Host Receive Polling + // Interval Endpoint 5 +#define USB_O_TXMAXP6 0x00000160 // USB Maximum Transmit Data + // Endpoint 6 +#define USB_O_TXCSRL6 0x00000162 // USB Transmit Control and Status + // Endpoint 6 Low +#define USB_O_TXCSRH6 0x00000163 // USB Transmit Control and Status + // Endpoint 6 High +#define USB_O_RXMAXP6 0x00000164 // USB Maximum Receive Data + // Endpoint 6 +#define USB_O_RXCSRL6 0x00000166 // USB Receive Control and Status + // Endpoint 6 Low +#define USB_O_RXCSRH6 0x00000167 // USB Receive Control and Status + // Endpoint 6 High +#define USB_O_RXCOUNT6 0x00000168 // USB Receive Byte Count Endpoint + // 6 +#define USB_O_TXTYPE6 0x0000016A // USB Host Transmit Configure Type + // Endpoint 6 +#define USB_O_TXINTERVAL6 0x0000016B // USB Host Transmit Interval + // Endpoint 6 +#define USB_O_RXTYPE6 0x0000016C // USB Host Configure Receive Type + // Endpoint 6 +#define USB_O_RXINTERVAL6 0x0000016D // USB Host Receive Polling + // Interval Endpoint 6 +#define USB_O_TXMAXP7 0x00000170 // USB Maximum Transmit Data + // Endpoint 7 +#define USB_O_TXCSRL7 0x00000172 // USB Transmit Control and Status + // Endpoint 7 Low +#define USB_O_TXCSRH7 0x00000173 // USB Transmit Control and Status + // Endpoint 7 High +#define USB_O_RXMAXP7 0x00000174 // USB Maximum Receive Data + // Endpoint 7 +#define USB_O_RXCSRL7 0x00000176 // USB Receive Control and Status + // Endpoint 7 Low +#define USB_O_RXCSRH7 0x00000177 // USB Receive Control and Status + // Endpoint 7 High +#define USB_O_RXCOUNT7 0x00000178 // USB Receive Byte Count Endpoint + // 7 +#define USB_O_TXTYPE7 0x0000017A // USB Host Transmit Configure Type + // Endpoint 7 +#define USB_O_TXINTERVAL7 0x0000017B // USB Host Transmit Interval + // Endpoint 7 +#define USB_O_RXTYPE7 0x0000017C // USB Host Configure Receive Type + // Endpoint 7 +#define USB_O_RXINTERVAL7 0x0000017D // USB Host Receive Polling + // Interval Endpoint 7 +#define USB_O_DMAINTR 0x00000200 // USB DMA Interrupt +#define USB_O_DMACTL0 0x00000204 // USB DMA Control 0 +#define USB_O_DMAADDR0 0x00000208 // USB DMA Address 0 +#define USB_O_DMACOUNT0 0x0000020C // USB DMA Count 0 +#define USB_O_DMACTL1 0x00000214 // USB DMA Control 1 +#define USB_O_DMAADDR1 0x00000218 // USB DMA Address 1 +#define USB_O_DMACOUNT1 0x0000021C // USB DMA Count 1 +#define USB_O_DMACTL2 0x00000224 // USB DMA Control 2 +#define USB_O_DMAADDR2 0x00000228 // USB DMA Address 2 +#define USB_O_DMACOUNT2 0x0000022C // USB DMA Count 2 +#define USB_O_DMACTL3 0x00000234 // USB DMA Control 3 +#define USB_O_DMAADDR3 0x00000238 // USB DMA Address 3 +#define USB_O_DMACOUNT3 0x0000023C // USB DMA Count 3 +#define USB_O_DMACTL4 0x00000244 // USB DMA Control 4 +#define USB_O_DMAADDR4 0x00000248 // USB DMA Address 4 +#define USB_O_DMACOUNT4 0x0000024C // USB DMA Count 4 +#define USB_O_DMACTL5 0x00000254 // USB DMA Control 5 +#define USB_O_DMAADDR5 0x00000258 // USB DMA Address 5 +#define USB_O_DMACOUNT5 0x0000025C // USB DMA Count 5 +#define USB_O_DMACTL6 0x00000264 // USB DMA Control 6 +#define USB_O_DMAADDR6 0x00000268 // USB DMA Address 6 +#define USB_O_DMACOUNT6 0x0000026C // USB DMA Count 6 +#define USB_O_DMACTL7 0x00000274 // USB DMA Control 7 +#define USB_O_DMAADDR7 0x00000278 // USB DMA Address 7 +#define USB_O_DMACOUNT7 0x0000027C // USB DMA Count 7 +#define USB_O_RQPKTCOUNT1 0x00000304 // USB Request Packet Count in + // Block Transfer Endpoint 1 +#define USB_O_RQPKTCOUNT2 0x00000308 // USB Request Packet Count in + // Block Transfer Endpoint 2 +#define USB_O_RQPKTCOUNT3 0x0000030C // USB Request Packet Count in + // Block Transfer Endpoint 3 +#define USB_O_RQPKTCOUNT4 0x00000310 // USB Request Packet Count in + // Block Transfer Endpoint 4 +#define USB_O_RQPKTCOUNT5 0x00000314 // USB Request Packet Count in + // Block Transfer Endpoint 5 +#define USB_O_RQPKTCOUNT6 0x00000318 // USB Request Packet Count in + // Block Transfer Endpoint 6 +#define USB_O_RQPKTCOUNT7 0x0000031C // USB Request Packet Count in + // Block Transfer Endpoint 7 +#define USB_O_RXDPKTBUFDIS 0x00000340 // USB Receive Double Packet Buffer + // Disable +#define USB_O_TXDPKTBUFDIS 0x00000342 // USB Transmit Double Packet + // Buffer Disable +#define USB_O_CTO 0x00000344 // USB Chirp Timeout +#define USB_O_HHSRTN 0x00000346 // USB High Speed to UTM Operating + // Delay +#define USB_O_HSBT 0x00000348 // USB High Speed Time-out Adder +#define USB_O_LPMATTR 0x00000360 // USB LPM Attributes +#define USB_O_LPMCNTRL 0x00000362 // USB LPM Control +#define USB_O_LPMIM 0x00000363 // USB LPM Interrupt Mask +#define USB_O_LPMRIS 0x00000364 // USB LPM Raw Interrupt Status +#define USB_O_LPMFADDR 0x00000365 // USB LPM Function Address +#define USB_O_EPC 0x00000400 // USB External Power Control +#define USB_O_EPCRIS 0x00000404 // USB External Power Control Raw + // Interrupt Status +#define USB_O_EPCIM 0x00000408 // USB External Power Control + // Interrupt Mask +#define USB_O_EPCISC 0x0000040C // USB External Power Control + // Interrupt Status and Clear +#define USB_O_DRRIS 0x00000410 // USB Device RESUME Raw Interrupt + // Status +#define USB_O_DRIM 0x00000414 // USB Device RESUME Interrupt Mask +#define USB_O_DRISC 0x00000418 // USB Device RESUME Interrupt + // Status and Clear +#define USB_O_GPCS 0x0000041C // USB General-Purpose Control and + // Status +#define USB_O_VDC 0x00000430 // USB VBUS Droop Control +#define USB_O_VDCRIS 0x00000434 // USB VBUS Droop Control Raw + // Interrupt Status +#define USB_O_VDCIM 0x00000438 // USB VBUS Droop Control Interrupt + // Mask +#define USB_O_VDCISC 0x0000043C // USB VBUS Droop Control Interrupt + // Status and Clear +#define USB_O_IDVRIS 0x00000444 // USB ID Valid Detect Raw + // Interrupt Status +#define USB_O_IDVIM 0x00000448 // USB ID Valid Detect Interrupt + // Mask +#define USB_O_IDVISC 0x0000044C // USB ID Valid Detect Interrupt + // Status and Clear +#define USB_O_PP 0x00000FC0 // USB Peripheral Properties +#define USB_O_PC 0x00000FC4 // USB Peripheral Configuration +#define USB_O_CC 0x00000FC8 // USB Clock Configuration + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_FADDR register. +// +//***************************************************************************** +#define USB_FADDR_M 0x0000007F // Function Address +#define USB_FADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_POWER register. +// +//***************************************************************************** +#define USB_POWER_ISOUP 0x00000080 // Isochronous Update +#define USB_POWER_SOFTCONN 0x00000040 // Soft Connect/Disconnect +#define USB_POWER_HSENAB 0x00000020 // High Speed Enable +#define USB_POWER_HSMODE 0x00000010 // High Speed Enable +#define USB_POWER_RESET 0x00000008 // RESET Signaling +#define USB_POWER_RESUME 0x00000004 // RESUME Signaling +#define USB_POWER_SUSPEND 0x00000002 // SUSPEND Mode +#define USB_POWER_PWRDNPHY 0x00000001 // Power Down PHY + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXIS register. +// +//***************************************************************************** +#define USB_TXIS_EP7 0x00000080 // TX Endpoint 7 Interrupt +#define USB_TXIS_EP6 0x00000040 // TX Endpoint 6 Interrupt +#define USB_TXIS_EP5 0x00000020 // TX Endpoint 5 Interrupt +#define USB_TXIS_EP4 0x00000010 // TX Endpoint 4 Interrupt +#define USB_TXIS_EP3 0x00000008 // TX Endpoint 3 Interrupt +#define USB_TXIS_EP2 0x00000004 // TX Endpoint 2 Interrupt +#define USB_TXIS_EP1 0x00000002 // TX Endpoint 1 Interrupt +#define USB_TXIS_EP0 0x00000001 // TX and RX Endpoint 0 Interrupt + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXIS register. +// +//***************************************************************************** +#define USB_RXIS_EP7 0x00000080 // RX Endpoint 7 Interrupt +#define USB_RXIS_EP6 0x00000040 // RX Endpoint 6 Interrupt +#define USB_RXIS_EP5 0x00000020 // RX Endpoint 5 Interrupt +#define USB_RXIS_EP4 0x00000010 // RX Endpoint 4 Interrupt +#define USB_RXIS_EP3 0x00000008 // RX Endpoint 3 Interrupt +#define USB_RXIS_EP2 0x00000004 // RX Endpoint 2 Interrupt +#define USB_RXIS_EP1 0x00000002 // RX Endpoint 1 Interrupt + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXIE register. +// +//***************************************************************************** +#define USB_TXIE_EP7 0x00000080 // TX Endpoint 7 Interrupt Enable +#define USB_TXIE_EP6 0x00000040 // TX Endpoint 6 Interrupt Enable +#define USB_TXIE_EP5 0x00000020 // TX Endpoint 5 Interrupt Enable +#define USB_TXIE_EP4 0x00000010 // TX Endpoint 4 Interrupt Enable +#define USB_TXIE_EP3 0x00000008 // TX Endpoint 3 Interrupt Enable +#define USB_TXIE_EP2 0x00000004 // TX Endpoint 2 Interrupt Enable +#define USB_TXIE_EP1 0x00000002 // TX Endpoint 1 Interrupt Enable +#define USB_TXIE_EP0 0x00000001 // TX and RX Endpoint 0 Interrupt + // Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXIE register. +// +//***************************************************************************** +#define USB_RXIE_EP7 0x00000080 // RX Endpoint 7 Interrupt Enable +#define USB_RXIE_EP6 0x00000040 // RX Endpoint 6 Interrupt Enable +#define USB_RXIE_EP5 0x00000020 // RX Endpoint 5 Interrupt Enable +#define USB_RXIE_EP4 0x00000010 // RX Endpoint 4 Interrupt Enable +#define USB_RXIE_EP3 0x00000008 // RX Endpoint 3 Interrupt Enable +#define USB_RXIE_EP2 0x00000004 // RX Endpoint 2 Interrupt Enable +#define USB_RXIE_EP1 0x00000002 // RX Endpoint 1 Interrupt Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_IS register. +// +//***************************************************************************** +#define USB_IS_VBUSERR 0x00000080 // VBUS Error (OTG only) +#define USB_IS_SESREQ 0x00000040 // SESSION REQUEST (OTG only) +#define USB_IS_DISCON 0x00000020 // Session Disconnect (OTG only) +#define USB_IS_CONN 0x00000010 // Session Connect +#define USB_IS_SOF 0x00000008 // Start of Frame +#define USB_IS_BABBLE 0x00000004 // Babble Detected +#define USB_IS_RESET 0x00000004 // RESET Signaling Detected +#define USB_IS_RESUME 0x00000002 // RESUME Signaling Detected +#define USB_IS_SUSPEND 0x00000001 // SUSPEND Signaling Detected + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_IE register. +// +//***************************************************************************** +#define USB_IE_VBUSERR 0x00000080 // Enable VBUS Error Interrupt (OTG + // only) +#define USB_IE_SESREQ 0x00000040 // Enable Session Request (OTG + // only) +#define USB_IE_DISCON 0x00000020 // Enable Disconnect Interrupt +#define USB_IE_CONN 0x00000010 // Enable Connect Interrupt +#define USB_IE_SOF 0x00000008 // Enable Start-of-Frame Interrupt +#define USB_IE_BABBLE 0x00000004 // Enable Babble Interrupt +#define USB_IE_RESET 0x00000004 // Enable RESET Interrupt +#define USB_IE_RESUME 0x00000002 // Enable RESUME Interrupt +#define USB_IE_SUSPND 0x00000001 // Enable SUSPEND Interrupt + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_FRAME register. +// +//***************************************************************************** +#define USB_FRAME_M 0x000007FF // Frame Number +#define USB_FRAME_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_EPIDX register. +// +//***************************************************************************** +#define USB_EPIDX_EPIDX_M 0x0000000F // Endpoint Index +#define USB_EPIDX_EPIDX_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TEST register. +// +//***************************************************************************** +#define USB_TEST_FORCEH 0x00000080 // Force Host Mode +#define USB_TEST_FIFOACC 0x00000040 // FIFO Access +#define USB_TEST_FORCEFS 0x00000020 // Force Full-Speed Mode +#define USB_TEST_FORCEHS 0x00000010 // Force High-Speed Mode +#define USB_TEST_TESTPKT 0x00000008 // Test Packet Mode Enable +#define USB_TEST_TESTK 0x00000004 // Test_K Mode Enable +#define USB_TEST_TESTJ 0x00000002 // Test_J Mode Enable +#define USB_TEST_TESTSE0NAK 0x00000001 // Test_SE0_NAK Test Mode Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_FIFO0 register. +// +//***************************************************************************** +#define USB_FIFO0_EPDATA_M 0xFFFFFFFF // Endpoint Data +#define USB_FIFO0_EPDATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_FIFO1 register. +// +//***************************************************************************** +#define USB_FIFO1_EPDATA_M 0xFFFFFFFF // Endpoint Data +#define USB_FIFO1_EPDATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_FIFO2 register. +// +//***************************************************************************** +#define USB_FIFO2_EPDATA_M 0xFFFFFFFF // Endpoint Data +#define USB_FIFO2_EPDATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_FIFO3 register. +// +//***************************************************************************** +#define USB_FIFO3_EPDATA_M 0xFFFFFFFF // Endpoint Data +#define USB_FIFO3_EPDATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_FIFO4 register. +// +//***************************************************************************** +#define USB_FIFO4_EPDATA_M 0xFFFFFFFF // Endpoint Data +#define USB_FIFO4_EPDATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_FIFO5 register. +// +//***************************************************************************** +#define USB_FIFO5_EPDATA_M 0xFFFFFFFF // Endpoint Data +#define USB_FIFO5_EPDATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_FIFO6 register. +// +//***************************************************************************** +#define USB_FIFO6_EPDATA_M 0xFFFFFFFF // Endpoint Data +#define USB_FIFO6_EPDATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_FIFO7 register. +// +//***************************************************************************** +#define USB_FIFO7_EPDATA_M 0xFFFFFFFF // Endpoint Data +#define USB_FIFO7_EPDATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_DEVCTL register. +// +//***************************************************************************** +#define USB_DEVCTL_DEV 0x00000080 // Device Mode (OTG only) +#define USB_DEVCTL_FSDEV 0x00000040 // Full-Speed Device Detected +#define USB_DEVCTL_LSDEV 0x00000020 // Low-Speed Device Detected +#define USB_DEVCTL_VBUS_M 0x00000018 // VBUS Level (OTG only) +#define USB_DEVCTL_VBUS_NONE 0x00000000 // Below SessionEnd +#define USB_DEVCTL_VBUS_SEND 0x00000008 // Above SessionEnd, below AValid +#define USB_DEVCTL_VBUS_AVALID 0x00000010 // Above AValid, below VBUSValid +#define USB_DEVCTL_VBUS_VALID 0x00000018 // Above VBUSValid +#define USB_DEVCTL_HOST 0x00000004 // Host Mode +#define USB_DEVCTL_HOSTREQ 0x00000002 // Host Request (OTG only) +#define USB_DEVCTL_SESSION 0x00000001 // Session Start/End (OTG only) + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_CCONF register. +// +//***************************************************************************** +#define USB_CCONF_TXEDMA 0x00000002 // TX Early DMA Enable +#define USB_CCONF_RXEDMA 0x00000001 // TX Early DMA Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXFIFOSZ register. +// +//***************************************************************************** +#define USB_TXFIFOSZ_DPB 0x00000010 // Double Packet Buffer Support +#define USB_TXFIFOSZ_SIZE_M 0x0000000F // Max Packet Size +#define USB_TXFIFOSZ_SIZE_8 0x00000000 // 8 +#define USB_TXFIFOSZ_SIZE_16 0x00000001 // 16 +#define USB_TXFIFOSZ_SIZE_32 0x00000002 // 32 +#define USB_TXFIFOSZ_SIZE_64 0x00000003 // 64 +#define USB_TXFIFOSZ_SIZE_128 0x00000004 // 128 +#define USB_TXFIFOSZ_SIZE_256 0x00000005 // 256 +#define USB_TXFIFOSZ_SIZE_512 0x00000006 // 512 +#define USB_TXFIFOSZ_SIZE_1024 0x00000007 // 1024 +#define USB_TXFIFOSZ_SIZE_2048 0x00000008 // 2048 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXFIFOSZ register. +// +//***************************************************************************** +#define USB_RXFIFOSZ_DPB 0x00000010 // Double Packet Buffer Support +#define USB_RXFIFOSZ_SIZE_M 0x0000000F // Max Packet Size +#define USB_RXFIFOSZ_SIZE_8 0x00000000 // 8 +#define USB_RXFIFOSZ_SIZE_16 0x00000001 // 16 +#define USB_RXFIFOSZ_SIZE_32 0x00000002 // 32 +#define USB_RXFIFOSZ_SIZE_64 0x00000003 // 64 +#define USB_RXFIFOSZ_SIZE_128 0x00000004 // 128 +#define USB_RXFIFOSZ_SIZE_256 0x00000005 // 256 +#define USB_RXFIFOSZ_SIZE_512 0x00000006 // 512 +#define USB_RXFIFOSZ_SIZE_1024 0x00000007 // 1024 +#define USB_RXFIFOSZ_SIZE_2048 0x00000008 // 2048 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXFIFOADD +// register. +// +//***************************************************************************** +#define USB_TXFIFOADD_ADDR_M 0x000001FF // Transmit/Receive Start Address +#define USB_TXFIFOADD_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXFIFOADD +// register. +// +//***************************************************************************** +#define USB_RXFIFOADD_ADDR_M 0x000001FF // Transmit/Receive Start Address +#define USB_RXFIFOADD_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_ULPIVBUSCTL +// register. +// +//***************************************************************************** +#define USB_ULPIVBUSCTL_USEEXTVBUSIND \ + 0x00000002 // Use External VBUS Indicator +#define USB_ULPIVBUSCTL_USEEXTVBUS \ + 0x00000001 // Use External VBUS + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_ULPIREGDATA +// register. +// +//***************************************************************************** +#define USB_ULPIREGDATA_REGDATA_M \ + 0x000000FF // Register Data +#define USB_ULPIREGDATA_REGDATA_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_ULPIREGADDR +// register. +// +//***************************************************************************** +#define USB_ULPIREGADDR_ADDR_M 0x000000FF // Register Address +#define USB_ULPIREGADDR_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_ULPIREGCTL +// register. +// +//***************************************************************************** +#define USB_ULPIREGCTL_RDWR 0x00000004 // Read/Write Control +#define USB_ULPIREGCTL_REGCMPLT 0x00000002 // Register Access Complete +#define USB_ULPIREGCTL_REGACC 0x00000001 // Initiate Register Access + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_EPINFO register. +// +//***************************************************************************** +#define USB_EPINFO_RXEP_M 0x000000F0 // RX Endpoints +#define USB_EPINFO_TXEP_M 0x0000000F // TX Endpoints +#define USB_EPINFO_RXEP_S 4 +#define USB_EPINFO_TXEP_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RAMINFO register. +// +//***************************************************************************** +#define USB_RAMINFO_DMACHAN_M 0x000000F0 // DMA Channels +#define USB_RAMINFO_RAMBITS_M 0x0000000F // RAM Address Bus Width +#define USB_RAMINFO_DMACHAN_S 4 +#define USB_RAMINFO_RAMBITS_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_CONTIM register. +// +//***************************************************************************** +#define USB_CONTIM_WTCON_M 0x000000F0 // Connect Wait +#define USB_CONTIM_WTID_M 0x0000000F // Wait ID +#define USB_CONTIM_WTCON_S 4 +#define USB_CONTIM_WTID_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_VPLEN register. +// +//***************************************************************************** +#define USB_VPLEN_VPLEN_M 0x000000FF // VBUS Pulse Length +#define USB_VPLEN_VPLEN_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_HSEOF register. +// +//***************************************************************************** +#define USB_HSEOF_HSEOFG_M 0x000000FF // HIgh-Speed End-of-Frame Gap +#define USB_HSEOF_HSEOFG_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_FSEOF register. +// +//***************************************************************************** +#define USB_FSEOF_FSEOFG_M 0x000000FF // Full-Speed End-of-Frame Gap +#define USB_FSEOF_FSEOFG_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_LSEOF register. +// +//***************************************************************************** +#define USB_LSEOF_LSEOFG_M 0x000000FF // Low-Speed End-of-Frame Gap +#define USB_LSEOF_LSEOFG_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXFUNCADDR0 +// register. +// +//***************************************************************************** +#define USB_TXFUNCADDR0_ADDR_M 0x0000007F // Device Address +#define USB_TXFUNCADDR0_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXHUBADDR0 +// register. +// +//***************************************************************************** +#define USB_TXHUBADDR0_ADDR_M 0x0000007F // Hub Address +#define USB_TXHUBADDR0_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXHUBPORT0 +// register. +// +//***************************************************************************** +#define USB_TXHUBPORT0_PORT_M 0x0000007F // Hub Port +#define USB_TXHUBPORT0_PORT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXFUNCADDR1 +// register. +// +//***************************************************************************** +#define USB_TXFUNCADDR1_ADDR_M 0x0000007F // Device Address +#define USB_TXFUNCADDR1_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXHUBADDR1 +// register. +// +//***************************************************************************** +#define USB_TXHUBADDR1_ADDR_M 0x0000007F // Hub Address +#define USB_TXHUBADDR1_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXHUBPORT1 +// register. +// +//***************************************************************************** +#define USB_TXHUBPORT1_PORT_M 0x0000007F // Hub Port +#define USB_TXHUBPORT1_PORT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXFUNCADDR1 +// register. +// +//***************************************************************************** +#define USB_RXFUNCADDR1_ADDR_M 0x0000007F // Device Address +#define USB_RXFUNCADDR1_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXHUBADDR1 +// register. +// +//***************************************************************************** +#define USB_RXHUBADDR1_ADDR_M 0x0000007F // Hub Address +#define USB_RXHUBADDR1_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXHUBPORT1 +// register. +// +//***************************************************************************** +#define USB_RXHUBPORT1_PORT_M 0x0000007F // Hub Port +#define USB_RXHUBPORT1_PORT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXFUNCADDR2 +// register. +// +//***************************************************************************** +#define USB_TXFUNCADDR2_ADDR_M 0x0000007F // Device Address +#define USB_TXFUNCADDR2_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXHUBADDR2 +// register. +// +//***************************************************************************** +#define USB_TXHUBADDR2_ADDR_M 0x0000007F // Hub Address +#define USB_TXHUBADDR2_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXHUBPORT2 +// register. +// +//***************************************************************************** +#define USB_TXHUBPORT2_PORT_M 0x0000007F // Hub Port +#define USB_TXHUBPORT2_PORT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXFUNCADDR2 +// register. +// +//***************************************************************************** +#define USB_RXFUNCADDR2_ADDR_M 0x0000007F // Device Address +#define USB_RXFUNCADDR2_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXHUBADDR2 +// register. +// +//***************************************************************************** +#define USB_RXHUBADDR2_ADDR_M 0x0000007F // Hub Address +#define USB_RXHUBADDR2_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXHUBPORT2 +// register. +// +//***************************************************************************** +#define USB_RXHUBPORT2_PORT_M 0x0000007F // Hub Port +#define USB_RXHUBPORT2_PORT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXFUNCADDR3 +// register. +// +//***************************************************************************** +#define USB_TXFUNCADDR3_ADDR_M 0x0000007F // Device Address +#define USB_TXFUNCADDR3_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXHUBADDR3 +// register. +// +//***************************************************************************** +#define USB_TXHUBADDR3_ADDR_M 0x0000007F // Hub Address +#define USB_TXHUBADDR3_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXHUBPORT3 +// register. +// +//***************************************************************************** +#define USB_TXHUBPORT3_PORT_M 0x0000007F // Hub Port +#define USB_TXHUBPORT3_PORT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXFUNCADDR3 +// register. +// +//***************************************************************************** +#define USB_RXFUNCADDR3_ADDR_M 0x0000007F // Device Address +#define USB_RXFUNCADDR3_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXHUBADDR3 +// register. +// +//***************************************************************************** +#define USB_RXHUBADDR3_ADDR_M 0x0000007F // Hub Address +#define USB_RXHUBADDR3_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXHUBPORT3 +// register. +// +//***************************************************************************** +#define USB_RXHUBPORT3_PORT_M 0x0000007F // Hub Port +#define USB_RXHUBPORT3_PORT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXFUNCADDR4 +// register. +// +//***************************************************************************** +#define USB_TXFUNCADDR4_ADDR_M 0x0000007F // Device Address +#define USB_TXFUNCADDR4_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXHUBADDR4 +// register. +// +//***************************************************************************** +#define USB_TXHUBADDR4_ADDR_M 0x0000007F // Hub Address +#define USB_TXHUBADDR4_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXHUBPORT4 +// register. +// +//***************************************************************************** +#define USB_TXHUBPORT4_PORT_M 0x0000007F // Hub Port +#define USB_TXHUBPORT4_PORT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXFUNCADDR4 +// register. +// +//***************************************************************************** +#define USB_RXFUNCADDR4_ADDR_M 0x0000007F // Device Address +#define USB_RXFUNCADDR4_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXHUBADDR4 +// register. +// +//***************************************************************************** +#define USB_RXHUBADDR4_ADDR_M 0x0000007F // Hub Address +#define USB_RXHUBADDR4_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXHUBPORT4 +// register. +// +//***************************************************************************** +#define USB_RXHUBPORT4_PORT_M 0x0000007F // Hub Port +#define USB_RXHUBPORT4_PORT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXFUNCADDR5 +// register. +// +//***************************************************************************** +#define USB_TXFUNCADDR5_ADDR_M 0x0000007F // Device Address +#define USB_TXFUNCADDR5_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXHUBADDR5 +// register. +// +//***************************************************************************** +#define USB_TXHUBADDR5_ADDR_M 0x0000007F // Hub Address +#define USB_TXHUBADDR5_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXHUBPORT5 +// register. +// +//***************************************************************************** +#define USB_TXHUBPORT5_PORT_M 0x0000007F // Hub Port +#define USB_TXHUBPORT5_PORT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXFUNCADDR5 +// register. +// +//***************************************************************************** +#define USB_RXFUNCADDR5_ADDR_M 0x0000007F // Device Address +#define USB_RXFUNCADDR5_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXHUBADDR5 +// register. +// +//***************************************************************************** +#define USB_RXHUBADDR5_ADDR_M 0x0000007F // Hub Address +#define USB_RXHUBADDR5_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXHUBPORT5 +// register. +// +//***************************************************************************** +#define USB_RXHUBPORT5_PORT_M 0x0000007F // Hub Port +#define USB_RXHUBPORT5_PORT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXFUNCADDR6 +// register. +// +//***************************************************************************** +#define USB_TXFUNCADDR6_ADDR_M 0x0000007F // Device Address +#define USB_TXFUNCADDR6_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXHUBADDR6 +// register. +// +//***************************************************************************** +#define USB_TXHUBADDR6_ADDR_M 0x0000007F // Hub Address +#define USB_TXHUBADDR6_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXHUBPORT6 +// register. +// +//***************************************************************************** +#define USB_TXHUBPORT6_PORT_M 0x0000007F // Hub Port +#define USB_TXHUBPORT6_PORT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXFUNCADDR6 +// register. +// +//***************************************************************************** +#define USB_RXFUNCADDR6_ADDR_M 0x0000007F // Device Address +#define USB_RXFUNCADDR6_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXHUBADDR6 +// register. +// +//***************************************************************************** +#define USB_RXHUBADDR6_ADDR_M 0x0000007F // Hub Address +#define USB_RXHUBADDR6_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXHUBPORT6 +// register. +// +//***************************************************************************** +#define USB_RXHUBPORT6_PORT_M 0x0000007F // Hub Port +#define USB_RXHUBPORT6_PORT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXFUNCADDR7 +// register. +// +//***************************************************************************** +#define USB_TXFUNCADDR7_ADDR_M 0x0000007F // Device Address +#define USB_TXFUNCADDR7_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXHUBADDR7 +// register. +// +//***************************************************************************** +#define USB_TXHUBADDR7_ADDR_M 0x0000007F // Hub Address +#define USB_TXHUBADDR7_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXHUBPORT7 +// register. +// +//***************************************************************************** +#define USB_TXHUBPORT7_PORT_M 0x0000007F // Hub Port +#define USB_TXHUBPORT7_PORT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXFUNCADDR7 +// register. +// +//***************************************************************************** +#define USB_RXFUNCADDR7_ADDR_M 0x0000007F // Device Address +#define USB_RXFUNCADDR7_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXHUBADDR7 +// register. +// +//***************************************************************************** +#define USB_RXHUBADDR7_ADDR_M 0x0000007F // Hub Address +#define USB_RXHUBADDR7_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXHUBPORT7 +// register. +// +//***************************************************************************** +#define USB_RXHUBPORT7_PORT_M 0x0000007F // Hub Port +#define USB_RXHUBPORT7_PORT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_CSRL0 register. +// +//***************************************************************************** +#define USB_CSRL0_NAKTO 0x00000080 // NAK Timeout +#define USB_CSRL0_SETENDC 0x00000080 // Setup End Clear +#define USB_CSRL0_STATUS 0x00000040 // STATUS Packet +#define USB_CSRL0_RXRDYC 0x00000040 // RXRDY Clear +#define USB_CSRL0_REQPKT 0x00000020 // Request Packet +#define USB_CSRL0_STALL 0x00000020 // Send Stall +#define USB_CSRL0_SETEND 0x00000010 // Setup End +#define USB_CSRL0_ERROR 0x00000010 // Error +#define USB_CSRL0_DATAEND 0x00000008 // Data End +#define USB_CSRL0_SETUP 0x00000008 // Setup Packet +#define USB_CSRL0_STALLED 0x00000004 // Endpoint Stalled +#define USB_CSRL0_TXRDY 0x00000002 // Transmit Packet Ready +#define USB_CSRL0_RXRDY 0x00000001 // Receive Packet Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_CSRH0 register. +// +//***************************************************************************** +#define USB_CSRH0_DISPING 0x00000008 // PING Disable +#define USB_CSRH0_DTWE 0x00000004 // Data Toggle Write Enable +#define USB_CSRH0_DT 0x00000002 // Data Toggle +#define USB_CSRH0_FLUSH 0x00000001 // Flush FIFO + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_COUNT0 register. +// +//***************************************************************************** +#define USB_COUNT0_COUNT_M 0x0000007F // FIFO Count +#define USB_COUNT0_COUNT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TYPE0 register. +// +//***************************************************************************** +#define USB_TYPE0_SPEED_M 0x000000C0 // Operating Speed +#define USB_TYPE0_SPEED_HIGH 0x00000040 // High +#define USB_TYPE0_SPEED_FULL 0x00000080 // Full +#define USB_TYPE0_SPEED_LOW 0x000000C0 // Low + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_NAKLMT register. +// +//***************************************************************************** +#define USB_NAKLMT_NAKLMT_M 0x0000001F // EP0 NAK Limit +#define USB_NAKLMT_NAKLMT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXMAXP1 register. +// +//***************************************************************************** +#define USB_TXMAXP1_MAXLOAD_M 0x000007FF // Maximum Payload +#define USB_TXMAXP1_MAXLOAD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXCSRL1 register. +// +//***************************************************************************** +#define USB_TXCSRL1_NAKTO 0x00000080 // NAK Timeout +#define USB_TXCSRL1_CLRDT 0x00000040 // Clear Data Toggle +#define USB_TXCSRL1_STALLED 0x00000020 // Endpoint Stalled +#define USB_TXCSRL1_STALL 0x00000010 // Send STALL +#define USB_TXCSRL1_SETUP 0x00000010 // Setup Packet +#define USB_TXCSRL1_FLUSH 0x00000008 // Flush FIFO +#define USB_TXCSRL1_ERROR 0x00000004 // Error +#define USB_TXCSRL1_UNDRN 0x00000004 // Underrun +#define USB_TXCSRL1_FIFONE 0x00000002 // FIFO Not Empty +#define USB_TXCSRL1_TXRDY 0x00000001 // Transmit Packet Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXCSRH1 register. +// +//***************************************************************************** +#define USB_TXCSRH1_AUTOSET 0x00000080 // Auto Set +#define USB_TXCSRH1_ISO 0x00000040 // Isochronous Transfers +#define USB_TXCSRH1_MODE 0x00000020 // Mode +#define USB_TXCSRH1_DMAEN 0x00000010 // DMA Request Enable +#define USB_TXCSRH1_FDT 0x00000008 // Force Data Toggle +#define USB_TXCSRH1_DMAMOD 0x00000004 // DMA Request Mode +#define USB_TXCSRH1_DTWE 0x00000002 // Data Toggle Write Enable +#define USB_TXCSRH1_DT 0x00000001 // Data Toggle + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXMAXP1 register. +// +//***************************************************************************** +#define USB_RXMAXP1_MAXLOAD_M 0x000007FF // Maximum Payload +#define USB_RXMAXP1_MAXLOAD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCSRL1 register. +// +//***************************************************************************** +#define USB_RXCSRL1_CLRDT 0x00000080 // Clear Data Toggle +#define USB_RXCSRL1_STALLED 0x00000040 // Endpoint Stalled +#define USB_RXCSRL1_STALL 0x00000020 // Send STALL +#define USB_RXCSRL1_REQPKT 0x00000020 // Request Packet +#define USB_RXCSRL1_FLUSH 0x00000010 // Flush FIFO +#define USB_RXCSRL1_DATAERR 0x00000008 // Data Error +#define USB_RXCSRL1_NAKTO 0x00000008 // NAK Timeout +#define USB_RXCSRL1_OVER 0x00000004 // Overrun +#define USB_RXCSRL1_ERROR 0x00000004 // Error +#define USB_RXCSRL1_FULL 0x00000002 // FIFO Full +#define USB_RXCSRL1_RXRDY 0x00000001 // Receive Packet Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCSRH1 register. +// +//***************************************************************************** +#define USB_RXCSRH1_AUTOCL 0x00000080 // Auto Clear +#define USB_RXCSRH1_AUTORQ 0x00000040 // Auto Request +#define USB_RXCSRH1_ISO 0x00000040 // Isochronous Transfers +#define USB_RXCSRH1_DMAEN 0x00000020 // DMA Request Enable +#define USB_RXCSRH1_DISNYET 0x00000010 // Disable NYET +#define USB_RXCSRH1_PIDERR 0x00000010 // PID Error +#define USB_RXCSRH1_DMAMOD 0x00000008 // DMA Request Mode +#define USB_RXCSRH1_DTWE 0x00000004 // Data Toggle Write Enable +#define USB_RXCSRH1_DT 0x00000002 // Data Toggle +#define USB_RXCSRH1_INCOMPRX 0x00000001 // Incomplete RX Transmission + // Status + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCOUNT1 register. +// +//***************************************************************************** +#define USB_RXCOUNT1_COUNT_M 0x00001FFF // Receive Packet Count +#define USB_RXCOUNT1_COUNT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXTYPE1 register. +// +//***************************************************************************** +#define USB_TXTYPE1_SPEED_M 0x000000C0 // Operating Speed +#define USB_TXTYPE1_SPEED_DFLT 0x00000000 // Default +#define USB_TXTYPE1_SPEED_HIGH 0x00000040 // High +#define USB_TXTYPE1_SPEED_FULL 0x00000080 // Full +#define USB_TXTYPE1_SPEED_LOW 0x000000C0 // Low +#define USB_TXTYPE1_PROTO_M 0x00000030 // Protocol +#define USB_TXTYPE1_PROTO_CTRL 0x00000000 // Control +#define USB_TXTYPE1_PROTO_ISOC 0x00000010 // Isochronous +#define USB_TXTYPE1_PROTO_BULK 0x00000020 // Bulk +#define USB_TXTYPE1_PROTO_INT 0x00000030 // Interrupt +#define USB_TXTYPE1_TEP_M 0x0000000F // Target Endpoint Number +#define USB_TXTYPE1_TEP_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXINTERVAL1 +// register. +// +//***************************************************************************** +#define USB_TXINTERVAL1_NAKLMT_M \ + 0x000000FF // NAK Limit +#define USB_TXINTERVAL1_TXPOLL_M \ + 0x000000FF // TX Polling +#define USB_TXINTERVAL1_TXPOLL_S \ + 0 +#define USB_TXINTERVAL1_NAKLMT_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXTYPE1 register. +// +//***************************************************************************** +#define USB_RXTYPE1_SPEED_M 0x000000C0 // Operating Speed +#define USB_RXTYPE1_SPEED_DFLT 0x00000000 // Default +#define USB_RXTYPE1_SPEED_HIGH 0x00000040 // High +#define USB_RXTYPE1_SPEED_FULL 0x00000080 // Full +#define USB_RXTYPE1_SPEED_LOW 0x000000C0 // Low +#define USB_RXTYPE1_PROTO_M 0x00000030 // Protocol +#define USB_RXTYPE1_PROTO_CTRL 0x00000000 // Control +#define USB_RXTYPE1_PROTO_ISOC 0x00000010 // Isochronous +#define USB_RXTYPE1_PROTO_BULK 0x00000020 // Bulk +#define USB_RXTYPE1_PROTO_INT 0x00000030 // Interrupt +#define USB_RXTYPE1_TEP_M 0x0000000F // Target Endpoint Number +#define USB_RXTYPE1_TEP_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXINTERVAL1 +// register. +// +//***************************************************************************** +#define USB_RXINTERVAL1_TXPOLL_M \ + 0x000000FF // RX Polling +#define USB_RXINTERVAL1_NAKLMT_M \ + 0x000000FF // NAK Limit +#define USB_RXINTERVAL1_TXPOLL_S \ + 0 +#define USB_RXINTERVAL1_NAKLMT_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXMAXP2 register. +// +//***************************************************************************** +#define USB_TXMAXP2_MAXLOAD_M 0x000007FF // Maximum Payload +#define USB_TXMAXP2_MAXLOAD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXCSRL2 register. +// +//***************************************************************************** +#define USB_TXCSRL2_NAKTO 0x00000080 // NAK Timeout +#define USB_TXCSRL2_CLRDT 0x00000040 // Clear Data Toggle +#define USB_TXCSRL2_STALLED 0x00000020 // Endpoint Stalled +#define USB_TXCSRL2_SETUP 0x00000010 // Setup Packet +#define USB_TXCSRL2_STALL 0x00000010 // Send STALL +#define USB_TXCSRL2_FLUSH 0x00000008 // Flush FIFO +#define USB_TXCSRL2_ERROR 0x00000004 // Error +#define USB_TXCSRL2_UNDRN 0x00000004 // Underrun +#define USB_TXCSRL2_FIFONE 0x00000002 // FIFO Not Empty +#define USB_TXCSRL2_TXRDY 0x00000001 // Transmit Packet Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXCSRH2 register. +// +//***************************************************************************** +#define USB_TXCSRH2_AUTOSET 0x00000080 // Auto Set +#define USB_TXCSRH2_ISO 0x00000040 // Isochronous Transfers +#define USB_TXCSRH2_MODE 0x00000020 // Mode +#define USB_TXCSRH2_DMAEN 0x00000010 // DMA Request Enable +#define USB_TXCSRH2_FDT 0x00000008 // Force Data Toggle +#define USB_TXCSRH2_DMAMOD 0x00000004 // DMA Request Mode +#define USB_TXCSRH2_DTWE 0x00000002 // Data Toggle Write Enable +#define USB_TXCSRH2_DT 0x00000001 // Data Toggle + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXMAXP2 register. +// +//***************************************************************************** +#define USB_RXMAXP2_MAXLOAD_M 0x000007FF // Maximum Payload +#define USB_RXMAXP2_MAXLOAD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCSRL2 register. +// +//***************************************************************************** +#define USB_RXCSRL2_CLRDT 0x00000080 // Clear Data Toggle +#define USB_RXCSRL2_STALLED 0x00000040 // Endpoint Stalled +#define USB_RXCSRL2_REQPKT 0x00000020 // Request Packet +#define USB_RXCSRL2_STALL 0x00000020 // Send STALL +#define USB_RXCSRL2_FLUSH 0x00000010 // Flush FIFO +#define USB_RXCSRL2_DATAERR 0x00000008 // Data Error +#define USB_RXCSRL2_NAKTO 0x00000008 // NAK Timeout +#define USB_RXCSRL2_ERROR 0x00000004 // Error +#define USB_RXCSRL2_OVER 0x00000004 // Overrun +#define USB_RXCSRL2_FULL 0x00000002 // FIFO Full +#define USB_RXCSRL2_RXRDY 0x00000001 // Receive Packet Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCSRH2 register. +// +//***************************************************************************** +#define USB_RXCSRH2_AUTOCL 0x00000080 // Auto Clear +#define USB_RXCSRH2_AUTORQ 0x00000040 // Auto Request +#define USB_RXCSRH2_ISO 0x00000040 // Isochronous Transfers +#define USB_RXCSRH2_DMAEN 0x00000020 // DMA Request Enable +#define USB_RXCSRH2_DISNYET 0x00000010 // Disable NYET +#define USB_RXCSRH2_PIDERR 0x00000010 // PID Error +#define USB_RXCSRH2_DMAMOD 0x00000008 // DMA Request Mode +#define USB_RXCSRH2_DTWE 0x00000004 // Data Toggle Write Enable +#define USB_RXCSRH2_DT 0x00000002 // Data Toggle +#define USB_RXCSRH2_INCOMPRX 0x00000001 // Incomplete RX Transmission + // Status + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCOUNT2 register. +// +//***************************************************************************** +#define USB_RXCOUNT2_COUNT_M 0x00001FFF // Receive Packet Count +#define USB_RXCOUNT2_COUNT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXTYPE2 register. +// +//***************************************************************************** +#define USB_TXTYPE2_SPEED_M 0x000000C0 // Operating Speed +#define USB_TXTYPE2_SPEED_DFLT 0x00000000 // Default +#define USB_TXTYPE2_SPEED_HIGH 0x00000040 // High +#define USB_TXTYPE2_SPEED_FULL 0x00000080 // Full +#define USB_TXTYPE2_SPEED_LOW 0x000000C0 // Low +#define USB_TXTYPE2_PROTO_M 0x00000030 // Protocol +#define USB_TXTYPE2_PROTO_CTRL 0x00000000 // Control +#define USB_TXTYPE2_PROTO_ISOC 0x00000010 // Isochronous +#define USB_TXTYPE2_PROTO_BULK 0x00000020 // Bulk +#define USB_TXTYPE2_PROTO_INT 0x00000030 // Interrupt +#define USB_TXTYPE2_TEP_M 0x0000000F // Target Endpoint Number +#define USB_TXTYPE2_TEP_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXINTERVAL2 +// register. +// +//***************************************************************************** +#define USB_TXINTERVAL2_TXPOLL_M \ + 0x000000FF // TX Polling +#define USB_TXINTERVAL2_NAKLMT_M \ + 0x000000FF // NAK Limit +#define USB_TXINTERVAL2_NAKLMT_S \ + 0 +#define USB_TXINTERVAL2_TXPOLL_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXTYPE2 register. +// +//***************************************************************************** +#define USB_RXTYPE2_SPEED_M 0x000000C0 // Operating Speed +#define USB_RXTYPE2_SPEED_DFLT 0x00000000 // Default +#define USB_RXTYPE2_SPEED_HIGH 0x00000040 // High +#define USB_RXTYPE2_SPEED_FULL 0x00000080 // Full +#define USB_RXTYPE2_SPEED_LOW 0x000000C0 // Low +#define USB_RXTYPE2_PROTO_M 0x00000030 // Protocol +#define USB_RXTYPE2_PROTO_CTRL 0x00000000 // Control +#define USB_RXTYPE2_PROTO_ISOC 0x00000010 // Isochronous +#define USB_RXTYPE2_PROTO_BULK 0x00000020 // Bulk +#define USB_RXTYPE2_PROTO_INT 0x00000030 // Interrupt +#define USB_RXTYPE2_TEP_M 0x0000000F // Target Endpoint Number +#define USB_RXTYPE2_TEP_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXINTERVAL2 +// register. +// +//***************************************************************************** +#define USB_RXINTERVAL2_TXPOLL_M \ + 0x000000FF // RX Polling +#define USB_RXINTERVAL2_NAKLMT_M \ + 0x000000FF // NAK Limit +#define USB_RXINTERVAL2_TXPOLL_S \ + 0 +#define USB_RXINTERVAL2_NAKLMT_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXMAXP3 register. +// +//***************************************************************************** +#define USB_TXMAXP3_MAXLOAD_M 0x000007FF // Maximum Payload +#define USB_TXMAXP3_MAXLOAD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXCSRL3 register. +// +//***************************************************************************** +#define USB_TXCSRL3_NAKTO 0x00000080 // NAK Timeout +#define USB_TXCSRL3_CLRDT 0x00000040 // Clear Data Toggle +#define USB_TXCSRL3_STALLED 0x00000020 // Endpoint Stalled +#define USB_TXCSRL3_SETUP 0x00000010 // Setup Packet +#define USB_TXCSRL3_STALL 0x00000010 // Send STALL +#define USB_TXCSRL3_FLUSH 0x00000008 // Flush FIFO +#define USB_TXCSRL3_ERROR 0x00000004 // Error +#define USB_TXCSRL3_UNDRN 0x00000004 // Underrun +#define USB_TXCSRL3_FIFONE 0x00000002 // FIFO Not Empty +#define USB_TXCSRL3_TXRDY 0x00000001 // Transmit Packet Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXCSRH3 register. +// +//***************************************************************************** +#define USB_TXCSRH3_AUTOSET 0x00000080 // Auto Set +#define USB_TXCSRH3_ISO 0x00000040 // Isochronous Transfers +#define USB_TXCSRH3_MODE 0x00000020 // Mode +#define USB_TXCSRH3_DMAEN 0x00000010 // DMA Request Enable +#define USB_TXCSRH3_FDT 0x00000008 // Force Data Toggle +#define USB_TXCSRH3_DMAMOD 0x00000004 // DMA Request Mode +#define USB_TXCSRH3_DTWE 0x00000002 // Data Toggle Write Enable +#define USB_TXCSRH3_DT 0x00000001 // Data Toggle + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXMAXP3 register. +// +//***************************************************************************** +#define USB_RXMAXP3_MAXLOAD_M 0x000007FF // Maximum Payload +#define USB_RXMAXP3_MAXLOAD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCSRL3 register. +// +//***************************************************************************** +#define USB_RXCSRL3_CLRDT 0x00000080 // Clear Data Toggle +#define USB_RXCSRL3_STALLED 0x00000040 // Endpoint Stalled +#define USB_RXCSRL3_STALL 0x00000020 // Send STALL +#define USB_RXCSRL3_REQPKT 0x00000020 // Request Packet +#define USB_RXCSRL3_FLUSH 0x00000010 // Flush FIFO +#define USB_RXCSRL3_DATAERR 0x00000008 // Data Error +#define USB_RXCSRL3_NAKTO 0x00000008 // NAK Timeout +#define USB_RXCSRL3_ERROR 0x00000004 // Error +#define USB_RXCSRL3_OVER 0x00000004 // Overrun +#define USB_RXCSRL3_FULL 0x00000002 // FIFO Full +#define USB_RXCSRL3_RXRDY 0x00000001 // Receive Packet Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCSRH3 register. +// +//***************************************************************************** +#define USB_RXCSRH3_AUTOCL 0x00000080 // Auto Clear +#define USB_RXCSRH3_AUTORQ 0x00000040 // Auto Request +#define USB_RXCSRH3_ISO 0x00000040 // Isochronous Transfers +#define USB_RXCSRH3_DMAEN 0x00000020 // DMA Request Enable +#define USB_RXCSRH3_DISNYET 0x00000010 // Disable NYET +#define USB_RXCSRH3_PIDERR 0x00000010 // PID Error +#define USB_RXCSRH3_DMAMOD 0x00000008 // DMA Request Mode +#define USB_RXCSRH3_DTWE 0x00000004 // Data Toggle Write Enable +#define USB_RXCSRH3_DT 0x00000002 // Data Toggle +#define USB_RXCSRH3_INCOMPRX 0x00000001 // Incomplete RX Transmission + // Status + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCOUNT3 register. +// +//***************************************************************************** +#define USB_RXCOUNT3_COUNT_M 0x00001FFF // Receive Packet Count +#define USB_RXCOUNT3_COUNT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXTYPE3 register. +// +//***************************************************************************** +#define USB_TXTYPE3_SPEED_M 0x000000C0 // Operating Speed +#define USB_TXTYPE3_SPEED_DFLT 0x00000000 // Default +#define USB_TXTYPE3_SPEED_HIGH 0x00000040 // High +#define USB_TXTYPE3_SPEED_FULL 0x00000080 // Full +#define USB_TXTYPE3_SPEED_LOW 0x000000C0 // Low +#define USB_TXTYPE3_PROTO_M 0x00000030 // Protocol +#define USB_TXTYPE3_PROTO_CTRL 0x00000000 // Control +#define USB_TXTYPE3_PROTO_ISOC 0x00000010 // Isochronous +#define USB_TXTYPE3_PROTO_BULK 0x00000020 // Bulk +#define USB_TXTYPE3_PROTO_INT 0x00000030 // Interrupt +#define USB_TXTYPE3_TEP_M 0x0000000F // Target Endpoint Number +#define USB_TXTYPE3_TEP_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXINTERVAL3 +// register. +// +//***************************************************************************** +#define USB_TXINTERVAL3_TXPOLL_M \ + 0x000000FF // TX Polling +#define USB_TXINTERVAL3_NAKLMT_M \ + 0x000000FF // NAK Limit +#define USB_TXINTERVAL3_TXPOLL_S \ + 0 +#define USB_TXINTERVAL3_NAKLMT_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXTYPE3 register. +// +//***************************************************************************** +#define USB_RXTYPE3_SPEED_M 0x000000C0 // Operating Speed +#define USB_RXTYPE3_SPEED_DFLT 0x00000000 // Default +#define USB_RXTYPE3_SPEED_HIGH 0x00000040 // High +#define USB_RXTYPE3_SPEED_FULL 0x00000080 // Full +#define USB_RXTYPE3_SPEED_LOW 0x000000C0 // Low +#define USB_RXTYPE3_PROTO_M 0x00000030 // Protocol +#define USB_RXTYPE3_PROTO_CTRL 0x00000000 // Control +#define USB_RXTYPE3_PROTO_ISOC 0x00000010 // Isochronous +#define USB_RXTYPE3_PROTO_BULK 0x00000020 // Bulk +#define USB_RXTYPE3_PROTO_INT 0x00000030 // Interrupt +#define USB_RXTYPE3_TEP_M 0x0000000F // Target Endpoint Number +#define USB_RXTYPE3_TEP_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXINTERVAL3 +// register. +// +//***************************************************************************** +#define USB_RXINTERVAL3_TXPOLL_M \ + 0x000000FF // RX Polling +#define USB_RXINTERVAL3_NAKLMT_M \ + 0x000000FF // NAK Limit +#define USB_RXINTERVAL3_TXPOLL_S \ + 0 +#define USB_RXINTERVAL3_NAKLMT_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXMAXP4 register. +// +//***************************************************************************** +#define USB_TXMAXP4_MAXLOAD_M 0x000007FF // Maximum Payload +#define USB_TXMAXP4_MAXLOAD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXCSRL4 register. +// +//***************************************************************************** +#define USB_TXCSRL4_NAKTO 0x00000080 // NAK Timeout +#define USB_TXCSRL4_CLRDT 0x00000040 // Clear Data Toggle +#define USB_TXCSRL4_STALLED 0x00000020 // Endpoint Stalled +#define USB_TXCSRL4_SETUP 0x00000010 // Setup Packet +#define USB_TXCSRL4_STALL 0x00000010 // Send STALL +#define USB_TXCSRL4_FLUSH 0x00000008 // Flush FIFO +#define USB_TXCSRL4_ERROR 0x00000004 // Error +#define USB_TXCSRL4_UNDRN 0x00000004 // Underrun +#define USB_TXCSRL4_FIFONE 0x00000002 // FIFO Not Empty +#define USB_TXCSRL4_TXRDY 0x00000001 // Transmit Packet Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXCSRH4 register. +// +//***************************************************************************** +#define USB_TXCSRH4_AUTOSET 0x00000080 // Auto Set +#define USB_TXCSRH4_ISO 0x00000040 // Isochronous Transfers +#define USB_TXCSRH4_MODE 0x00000020 // Mode +#define USB_TXCSRH4_DMAEN 0x00000010 // DMA Request Enable +#define USB_TXCSRH4_FDT 0x00000008 // Force Data Toggle +#define USB_TXCSRH4_DMAMOD 0x00000004 // DMA Request Mode +#define USB_TXCSRH4_DTWE 0x00000002 // Data Toggle Write Enable +#define USB_TXCSRH4_DT 0x00000001 // Data Toggle + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXMAXP4 register. +// +//***************************************************************************** +#define USB_RXMAXP4_MAXLOAD_M 0x000007FF // Maximum Payload +#define USB_RXMAXP4_MAXLOAD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCSRL4 register. +// +//***************************************************************************** +#define USB_RXCSRL4_CLRDT 0x00000080 // Clear Data Toggle +#define USB_RXCSRL4_STALLED 0x00000040 // Endpoint Stalled +#define USB_RXCSRL4_STALL 0x00000020 // Send STALL +#define USB_RXCSRL4_REQPKT 0x00000020 // Request Packet +#define USB_RXCSRL4_FLUSH 0x00000010 // Flush FIFO +#define USB_RXCSRL4_NAKTO 0x00000008 // NAK Timeout +#define USB_RXCSRL4_DATAERR 0x00000008 // Data Error +#define USB_RXCSRL4_OVER 0x00000004 // Overrun +#define USB_RXCSRL4_ERROR 0x00000004 // Error +#define USB_RXCSRL4_FULL 0x00000002 // FIFO Full +#define USB_RXCSRL4_RXRDY 0x00000001 // Receive Packet Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCSRH4 register. +// +//***************************************************************************** +#define USB_RXCSRH4_AUTOCL 0x00000080 // Auto Clear +#define USB_RXCSRH4_AUTORQ 0x00000040 // Auto Request +#define USB_RXCSRH4_ISO 0x00000040 // Isochronous Transfers +#define USB_RXCSRH4_DMAEN 0x00000020 // DMA Request Enable +#define USB_RXCSRH4_DISNYET 0x00000010 // Disable NYET +#define USB_RXCSRH4_PIDERR 0x00000010 // PID Error +#define USB_RXCSRH4_DMAMOD 0x00000008 // DMA Request Mode +#define USB_RXCSRH4_DTWE 0x00000004 // Data Toggle Write Enable +#define USB_RXCSRH4_DT 0x00000002 // Data Toggle +#define USB_RXCSRH4_INCOMPRX 0x00000001 // Incomplete RX Transmission + // Status + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCOUNT4 register. +// +//***************************************************************************** +#define USB_RXCOUNT4_COUNT_M 0x00001FFF // Receive Packet Count +#define USB_RXCOUNT4_COUNT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXTYPE4 register. +// +//***************************************************************************** +#define USB_TXTYPE4_SPEED_M 0x000000C0 // Operating Speed +#define USB_TXTYPE4_SPEED_DFLT 0x00000000 // Default +#define USB_TXTYPE4_SPEED_HIGH 0x00000040 // High +#define USB_TXTYPE4_SPEED_FULL 0x00000080 // Full +#define USB_TXTYPE4_SPEED_LOW 0x000000C0 // Low +#define USB_TXTYPE4_PROTO_M 0x00000030 // Protocol +#define USB_TXTYPE4_PROTO_CTRL 0x00000000 // Control +#define USB_TXTYPE4_PROTO_ISOC 0x00000010 // Isochronous +#define USB_TXTYPE4_PROTO_BULK 0x00000020 // Bulk +#define USB_TXTYPE4_PROTO_INT 0x00000030 // Interrupt +#define USB_TXTYPE4_TEP_M 0x0000000F // Target Endpoint Number +#define USB_TXTYPE4_TEP_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXINTERVAL4 +// register. +// +//***************************************************************************** +#define USB_TXINTERVAL4_TXPOLL_M \ + 0x000000FF // TX Polling +#define USB_TXINTERVAL4_NAKLMT_M \ + 0x000000FF // NAK Limit +#define USB_TXINTERVAL4_NAKLMT_S \ + 0 +#define USB_TXINTERVAL4_TXPOLL_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXTYPE4 register. +// +//***************************************************************************** +#define USB_RXTYPE4_SPEED_M 0x000000C0 // Operating Speed +#define USB_RXTYPE4_SPEED_DFLT 0x00000000 // Default +#define USB_RXTYPE4_SPEED_HIGH 0x00000040 // High +#define USB_RXTYPE4_SPEED_FULL 0x00000080 // Full +#define USB_RXTYPE4_SPEED_LOW 0x000000C0 // Low +#define USB_RXTYPE4_PROTO_M 0x00000030 // Protocol +#define USB_RXTYPE4_PROTO_CTRL 0x00000000 // Control +#define USB_RXTYPE4_PROTO_ISOC 0x00000010 // Isochronous +#define USB_RXTYPE4_PROTO_BULK 0x00000020 // Bulk +#define USB_RXTYPE4_PROTO_INT 0x00000030 // Interrupt +#define USB_RXTYPE4_TEP_M 0x0000000F // Target Endpoint Number +#define USB_RXTYPE4_TEP_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXINTERVAL4 +// register. +// +//***************************************************************************** +#define USB_RXINTERVAL4_TXPOLL_M \ + 0x000000FF // RX Polling +#define USB_RXINTERVAL4_NAKLMT_M \ + 0x000000FF // NAK Limit +#define USB_RXINTERVAL4_NAKLMT_S \ + 0 +#define USB_RXINTERVAL4_TXPOLL_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXMAXP5 register. +// +//***************************************************************************** +#define USB_TXMAXP5_MAXLOAD_M 0x000007FF // Maximum Payload +#define USB_TXMAXP5_MAXLOAD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXCSRL5 register. +// +//***************************************************************************** +#define USB_TXCSRL5_NAKTO 0x00000080 // NAK Timeout +#define USB_TXCSRL5_CLRDT 0x00000040 // Clear Data Toggle +#define USB_TXCSRL5_STALLED 0x00000020 // Endpoint Stalled +#define USB_TXCSRL5_SETUP 0x00000010 // Setup Packet +#define USB_TXCSRL5_STALL 0x00000010 // Send STALL +#define USB_TXCSRL5_FLUSH 0x00000008 // Flush FIFO +#define USB_TXCSRL5_ERROR 0x00000004 // Error +#define USB_TXCSRL5_UNDRN 0x00000004 // Underrun +#define USB_TXCSRL5_FIFONE 0x00000002 // FIFO Not Empty +#define USB_TXCSRL5_TXRDY 0x00000001 // Transmit Packet Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXCSRH5 register. +// +//***************************************************************************** +#define USB_TXCSRH5_AUTOSET 0x00000080 // Auto Set +#define USB_TXCSRH5_ISO 0x00000040 // Isochronous Transfers +#define USB_TXCSRH5_MODE 0x00000020 // Mode +#define USB_TXCSRH5_DMAEN 0x00000010 // DMA Request Enable +#define USB_TXCSRH5_FDT 0x00000008 // Force Data Toggle +#define USB_TXCSRH5_DMAMOD 0x00000004 // DMA Request Mode +#define USB_TXCSRH5_DTWE 0x00000002 // Data Toggle Write Enable +#define USB_TXCSRH5_DT 0x00000001 // Data Toggle + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXMAXP5 register. +// +//***************************************************************************** +#define USB_RXMAXP5_MAXLOAD_M 0x000007FF // Maximum Payload +#define USB_RXMAXP5_MAXLOAD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCSRL5 register. +// +//***************************************************************************** +#define USB_RXCSRL5_CLRDT 0x00000080 // Clear Data Toggle +#define USB_RXCSRL5_STALLED 0x00000040 // Endpoint Stalled +#define USB_RXCSRL5_STALL 0x00000020 // Send STALL +#define USB_RXCSRL5_REQPKT 0x00000020 // Request Packet +#define USB_RXCSRL5_FLUSH 0x00000010 // Flush FIFO +#define USB_RXCSRL5_NAKTO 0x00000008 // NAK Timeout +#define USB_RXCSRL5_DATAERR 0x00000008 // Data Error +#define USB_RXCSRL5_ERROR 0x00000004 // Error +#define USB_RXCSRL5_OVER 0x00000004 // Overrun +#define USB_RXCSRL5_FULL 0x00000002 // FIFO Full +#define USB_RXCSRL5_RXRDY 0x00000001 // Receive Packet Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCSRH5 register. +// +//***************************************************************************** +#define USB_RXCSRH5_AUTOCL 0x00000080 // Auto Clear +#define USB_RXCSRH5_AUTORQ 0x00000040 // Auto Request +#define USB_RXCSRH5_ISO 0x00000040 // Isochronous Transfers +#define USB_RXCSRH5_DMAEN 0x00000020 // DMA Request Enable +#define USB_RXCSRH5_DISNYET 0x00000010 // Disable NYET +#define USB_RXCSRH5_PIDERR 0x00000010 // PID Error +#define USB_RXCSRH5_DMAMOD 0x00000008 // DMA Request Mode +#define USB_RXCSRH5_DTWE 0x00000004 // Data Toggle Write Enable +#define USB_RXCSRH5_DT 0x00000002 // Data Toggle +#define USB_RXCSRH5_INCOMPRX 0x00000001 // Incomplete RX Transmission + // Status + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCOUNT5 register. +// +//***************************************************************************** +#define USB_RXCOUNT5_COUNT_M 0x00001FFF // Receive Packet Count +#define USB_RXCOUNT5_COUNT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXTYPE5 register. +// +//***************************************************************************** +#define USB_TXTYPE5_SPEED_M 0x000000C0 // Operating Speed +#define USB_TXTYPE5_SPEED_DFLT 0x00000000 // Default +#define USB_TXTYPE5_SPEED_HIGH 0x00000040 // High +#define USB_TXTYPE5_SPEED_FULL 0x00000080 // Full +#define USB_TXTYPE5_SPEED_LOW 0x000000C0 // Low +#define USB_TXTYPE5_PROTO_M 0x00000030 // Protocol +#define USB_TXTYPE5_PROTO_CTRL 0x00000000 // Control +#define USB_TXTYPE5_PROTO_ISOC 0x00000010 // Isochronous +#define USB_TXTYPE5_PROTO_BULK 0x00000020 // Bulk +#define USB_TXTYPE5_PROTO_INT 0x00000030 // Interrupt +#define USB_TXTYPE5_TEP_M 0x0000000F // Target Endpoint Number +#define USB_TXTYPE5_TEP_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXINTERVAL5 +// register. +// +//***************************************************************************** +#define USB_TXINTERVAL5_TXPOLL_M \ + 0x000000FF // TX Polling +#define USB_TXINTERVAL5_NAKLMT_M \ + 0x000000FF // NAK Limit +#define USB_TXINTERVAL5_NAKLMT_S \ + 0 +#define USB_TXINTERVAL5_TXPOLL_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXTYPE5 register. +// +//***************************************************************************** +#define USB_RXTYPE5_SPEED_M 0x000000C0 // Operating Speed +#define USB_RXTYPE5_SPEED_DFLT 0x00000000 // Default +#define USB_RXTYPE5_SPEED_HIGH 0x00000040 // High +#define USB_RXTYPE5_SPEED_FULL 0x00000080 // Full +#define USB_RXTYPE5_SPEED_LOW 0x000000C0 // Low +#define USB_RXTYPE5_PROTO_M 0x00000030 // Protocol +#define USB_RXTYPE5_PROTO_CTRL 0x00000000 // Control +#define USB_RXTYPE5_PROTO_ISOC 0x00000010 // Isochronous +#define USB_RXTYPE5_PROTO_BULK 0x00000020 // Bulk +#define USB_RXTYPE5_PROTO_INT 0x00000030 // Interrupt +#define USB_RXTYPE5_TEP_M 0x0000000F // Target Endpoint Number +#define USB_RXTYPE5_TEP_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXINTERVAL5 +// register. +// +//***************************************************************************** +#define USB_RXINTERVAL5_TXPOLL_M \ + 0x000000FF // RX Polling +#define USB_RXINTERVAL5_NAKLMT_M \ + 0x000000FF // NAK Limit +#define USB_RXINTERVAL5_TXPOLL_S \ + 0 +#define USB_RXINTERVAL5_NAKLMT_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXMAXP6 register. +// +//***************************************************************************** +#define USB_TXMAXP6_MAXLOAD_M 0x000007FF // Maximum Payload +#define USB_TXMAXP6_MAXLOAD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXCSRL6 register. +// +//***************************************************************************** +#define USB_TXCSRL6_NAKTO 0x00000080 // NAK Timeout +#define USB_TXCSRL6_CLRDT 0x00000040 // Clear Data Toggle +#define USB_TXCSRL6_STALLED 0x00000020 // Endpoint Stalled +#define USB_TXCSRL6_STALL 0x00000010 // Send STALL +#define USB_TXCSRL6_SETUP 0x00000010 // Setup Packet +#define USB_TXCSRL6_FLUSH 0x00000008 // Flush FIFO +#define USB_TXCSRL6_ERROR 0x00000004 // Error +#define USB_TXCSRL6_UNDRN 0x00000004 // Underrun +#define USB_TXCSRL6_FIFONE 0x00000002 // FIFO Not Empty +#define USB_TXCSRL6_TXRDY 0x00000001 // Transmit Packet Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXCSRH6 register. +// +//***************************************************************************** +#define USB_TXCSRH6_AUTOSET 0x00000080 // Auto Set +#define USB_TXCSRH6_ISO 0x00000040 // Isochronous Transfers +#define USB_TXCSRH6_MODE 0x00000020 // Mode +#define USB_TXCSRH6_DMAEN 0x00000010 // DMA Request Enable +#define USB_TXCSRH6_FDT 0x00000008 // Force Data Toggle +#define USB_TXCSRH6_DMAMOD 0x00000004 // DMA Request Mode +#define USB_TXCSRH6_DTWE 0x00000002 // Data Toggle Write Enable +#define USB_TXCSRH6_DT 0x00000001 // Data Toggle + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXMAXP6 register. +// +//***************************************************************************** +#define USB_RXMAXP6_MAXLOAD_M 0x000007FF // Maximum Payload +#define USB_RXMAXP6_MAXLOAD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCSRL6 register. +// +//***************************************************************************** +#define USB_RXCSRL6_CLRDT 0x00000080 // Clear Data Toggle +#define USB_RXCSRL6_STALLED 0x00000040 // Endpoint Stalled +#define USB_RXCSRL6_REQPKT 0x00000020 // Request Packet +#define USB_RXCSRL6_STALL 0x00000020 // Send STALL +#define USB_RXCSRL6_FLUSH 0x00000010 // Flush FIFO +#define USB_RXCSRL6_NAKTO 0x00000008 // NAK Timeout +#define USB_RXCSRL6_DATAERR 0x00000008 // Data Error +#define USB_RXCSRL6_ERROR 0x00000004 // Error +#define USB_RXCSRL6_OVER 0x00000004 // Overrun +#define USB_RXCSRL6_FULL 0x00000002 // FIFO Full +#define USB_RXCSRL6_RXRDY 0x00000001 // Receive Packet Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCSRH6 register. +// +//***************************************************************************** +#define USB_RXCSRH6_AUTOCL 0x00000080 // Auto Clear +#define USB_RXCSRH6_AUTORQ 0x00000040 // Auto Request +#define USB_RXCSRH6_ISO 0x00000040 // Isochronous Transfers +#define USB_RXCSRH6_DMAEN 0x00000020 // DMA Request Enable +#define USB_RXCSRH6_DISNYET 0x00000010 // Disable NYET +#define USB_RXCSRH6_PIDERR 0x00000010 // PID Error +#define USB_RXCSRH6_DMAMOD 0x00000008 // DMA Request Mode +#define USB_RXCSRH6_DTWE 0x00000004 // Data Toggle Write Enable +#define USB_RXCSRH6_DT 0x00000002 // Data Toggle +#define USB_RXCSRH6_INCOMPRX 0x00000001 // Incomplete RX Transmission + // Status + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCOUNT6 register. +// +//***************************************************************************** +#define USB_RXCOUNT6_COUNT_M 0x00001FFF // Receive Packet Count +#define USB_RXCOUNT6_COUNT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXTYPE6 register. +// +//***************************************************************************** +#define USB_TXTYPE6_SPEED_M 0x000000C0 // Operating Speed +#define USB_TXTYPE6_SPEED_DFLT 0x00000000 // Default +#define USB_TXTYPE6_SPEED_HIGH 0x00000040 // High +#define USB_TXTYPE6_SPEED_FULL 0x00000080 // Full +#define USB_TXTYPE6_SPEED_LOW 0x000000C0 // Low +#define USB_TXTYPE6_PROTO_M 0x00000030 // Protocol +#define USB_TXTYPE6_PROTO_CTRL 0x00000000 // Control +#define USB_TXTYPE6_PROTO_ISOC 0x00000010 // Isochronous +#define USB_TXTYPE6_PROTO_BULK 0x00000020 // Bulk +#define USB_TXTYPE6_PROTO_INT 0x00000030 // Interrupt +#define USB_TXTYPE6_TEP_M 0x0000000F // Target Endpoint Number +#define USB_TXTYPE6_TEP_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXINTERVAL6 +// register. +// +//***************************************************************************** +#define USB_TXINTERVAL6_TXPOLL_M \ + 0x000000FF // TX Polling +#define USB_TXINTERVAL6_NAKLMT_M \ + 0x000000FF // NAK Limit +#define USB_TXINTERVAL6_TXPOLL_S \ + 0 +#define USB_TXINTERVAL6_NAKLMT_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXTYPE6 register. +// +//***************************************************************************** +#define USB_RXTYPE6_SPEED_M 0x000000C0 // Operating Speed +#define USB_RXTYPE6_SPEED_DFLT 0x00000000 // Default +#define USB_RXTYPE6_SPEED_HIGH 0x00000040 // High +#define USB_RXTYPE6_SPEED_FULL 0x00000080 // Full +#define USB_RXTYPE6_SPEED_LOW 0x000000C0 // Low +#define USB_RXTYPE6_PROTO_M 0x00000030 // Protocol +#define USB_RXTYPE6_PROTO_CTRL 0x00000000 // Control +#define USB_RXTYPE6_PROTO_ISOC 0x00000010 // Isochronous +#define USB_RXTYPE6_PROTO_BULK 0x00000020 // Bulk +#define USB_RXTYPE6_PROTO_INT 0x00000030 // Interrupt +#define USB_RXTYPE6_TEP_M 0x0000000F // Target Endpoint Number +#define USB_RXTYPE6_TEP_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXINTERVAL6 +// register. +// +//***************************************************************************** +#define USB_RXINTERVAL6_TXPOLL_M \ + 0x000000FF // RX Polling +#define USB_RXINTERVAL6_NAKLMT_M \ + 0x000000FF // NAK Limit +#define USB_RXINTERVAL6_NAKLMT_S \ + 0 +#define USB_RXINTERVAL6_TXPOLL_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXMAXP7 register. +// +//***************************************************************************** +#define USB_TXMAXP7_MAXLOAD_M 0x000007FF // Maximum Payload +#define USB_TXMAXP7_MAXLOAD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXCSRL7 register. +// +//***************************************************************************** +#define USB_TXCSRL7_NAKTO 0x00000080 // NAK Timeout +#define USB_TXCSRL7_CLRDT 0x00000040 // Clear Data Toggle +#define USB_TXCSRL7_STALLED 0x00000020 // Endpoint Stalled +#define USB_TXCSRL7_STALL 0x00000010 // Send STALL +#define USB_TXCSRL7_SETUP 0x00000010 // Setup Packet +#define USB_TXCSRL7_FLUSH 0x00000008 // Flush FIFO +#define USB_TXCSRL7_ERROR 0x00000004 // Error +#define USB_TXCSRL7_UNDRN 0x00000004 // Underrun +#define USB_TXCSRL7_FIFONE 0x00000002 // FIFO Not Empty +#define USB_TXCSRL7_TXRDY 0x00000001 // Transmit Packet Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXCSRH7 register. +// +//***************************************************************************** +#define USB_TXCSRH7_AUTOSET 0x00000080 // Auto Set +#define USB_TXCSRH7_ISO 0x00000040 // Isochronous Transfers +#define USB_TXCSRH7_MODE 0x00000020 // Mode +#define USB_TXCSRH7_DMAEN 0x00000010 // DMA Request Enable +#define USB_TXCSRH7_FDT 0x00000008 // Force Data Toggle +#define USB_TXCSRH7_DMAMOD 0x00000004 // DMA Request Mode +#define USB_TXCSRH7_DTWE 0x00000002 // Data Toggle Write Enable +#define USB_TXCSRH7_DT 0x00000001 // Data Toggle + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXMAXP7 register. +// +//***************************************************************************** +#define USB_RXMAXP7_MAXLOAD_M 0x000007FF // Maximum Payload +#define USB_RXMAXP7_MAXLOAD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCSRL7 register. +// +//***************************************************************************** +#define USB_RXCSRL7_CLRDT 0x00000080 // Clear Data Toggle +#define USB_RXCSRL7_STALLED 0x00000040 // Endpoint Stalled +#define USB_RXCSRL7_REQPKT 0x00000020 // Request Packet +#define USB_RXCSRL7_STALL 0x00000020 // Send STALL +#define USB_RXCSRL7_FLUSH 0x00000010 // Flush FIFO +#define USB_RXCSRL7_DATAERR 0x00000008 // Data Error +#define USB_RXCSRL7_NAKTO 0x00000008 // NAK Timeout +#define USB_RXCSRL7_ERROR 0x00000004 // Error +#define USB_RXCSRL7_OVER 0x00000004 // Overrun +#define USB_RXCSRL7_FULL 0x00000002 // FIFO Full +#define USB_RXCSRL7_RXRDY 0x00000001 // Receive Packet Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCSRH7 register. +// +//***************************************************************************** +#define USB_RXCSRH7_AUTOCL 0x00000080 // Auto Clear +#define USB_RXCSRH7_ISO 0x00000040 // Isochronous Transfers +#define USB_RXCSRH7_AUTORQ 0x00000040 // Auto Request +#define USB_RXCSRH7_DMAEN 0x00000020 // DMA Request Enable +#define USB_RXCSRH7_PIDERR 0x00000010 // PID Error +#define USB_RXCSRH7_DISNYET 0x00000010 // Disable NYET +#define USB_RXCSRH7_DMAMOD 0x00000008 // DMA Request Mode +#define USB_RXCSRH7_DTWE 0x00000004 // Data Toggle Write Enable +#define USB_RXCSRH7_DT 0x00000002 // Data Toggle +#define USB_RXCSRH7_INCOMPRX 0x00000001 // Incomplete RX Transmission + // Status + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCOUNT7 register. +// +//***************************************************************************** +#define USB_RXCOUNT7_COUNT_M 0x00001FFF // Receive Packet Count +#define USB_RXCOUNT7_COUNT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXTYPE7 register. +// +//***************************************************************************** +#define USB_TXTYPE7_SPEED_M 0x000000C0 // Operating Speed +#define USB_TXTYPE7_SPEED_DFLT 0x00000000 // Default +#define USB_TXTYPE7_SPEED_HIGH 0x00000040 // High +#define USB_TXTYPE7_SPEED_FULL 0x00000080 // Full +#define USB_TXTYPE7_SPEED_LOW 0x000000C0 // Low +#define USB_TXTYPE7_PROTO_M 0x00000030 // Protocol +#define USB_TXTYPE7_PROTO_CTRL 0x00000000 // Control +#define USB_TXTYPE7_PROTO_ISOC 0x00000010 // Isochronous +#define USB_TXTYPE7_PROTO_BULK 0x00000020 // Bulk +#define USB_TXTYPE7_PROTO_INT 0x00000030 // Interrupt +#define USB_TXTYPE7_TEP_M 0x0000000F // Target Endpoint Number +#define USB_TXTYPE7_TEP_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXINTERVAL7 +// register. +// +//***************************************************************************** +#define USB_TXINTERVAL7_TXPOLL_M \ + 0x000000FF // TX Polling +#define USB_TXINTERVAL7_NAKLMT_M \ + 0x000000FF // NAK Limit +#define USB_TXINTERVAL7_NAKLMT_S \ + 0 +#define USB_TXINTERVAL7_TXPOLL_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXTYPE7 register. +// +//***************************************************************************** +#define USB_RXTYPE7_SPEED_M 0x000000C0 // Operating Speed +#define USB_RXTYPE7_SPEED_DFLT 0x00000000 // Default +#define USB_RXTYPE7_SPEED_HIGH 0x00000040 // High +#define USB_RXTYPE7_SPEED_FULL 0x00000080 // Full +#define USB_RXTYPE7_SPEED_LOW 0x000000C0 // Low +#define USB_RXTYPE7_PROTO_M 0x00000030 // Protocol +#define USB_RXTYPE7_PROTO_CTRL 0x00000000 // Control +#define USB_RXTYPE7_PROTO_ISOC 0x00000010 // Isochronous +#define USB_RXTYPE7_PROTO_BULK 0x00000020 // Bulk +#define USB_RXTYPE7_PROTO_INT 0x00000030 // Interrupt +#define USB_RXTYPE7_TEP_M 0x0000000F // Target Endpoint Number +#define USB_RXTYPE7_TEP_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXINTERVAL7 +// register. +// +//***************************************************************************** +#define USB_RXINTERVAL7_TXPOLL_M \ + 0x000000FF // RX Polling +#define USB_RXINTERVAL7_NAKLMT_M \ + 0x000000FF // NAK Limit +#define USB_RXINTERVAL7_NAKLMT_S \ + 0 +#define USB_RXINTERVAL7_TXPOLL_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_DMAINTR register. +// +//***************************************************************************** +#define USB_DMAINTR_CH7 0x00000080 // Channel 7 DMA Interrupt +#define USB_DMAINTR_CH6 0x00000040 // Channel 6 DMA Interrupt +#define USB_DMAINTR_CH5 0x00000020 // Channel 5 DMA Interrupt +#define USB_DMAINTR_CH4 0x00000010 // Channel 4 DMA Interrupt +#define USB_DMAINTR_CH3 0x00000008 // Channel 3 DMA Interrupt +#define USB_DMAINTR_CH2 0x00000004 // Channel 2 DMA Interrupt +#define USB_DMAINTR_CH1 0x00000002 // Channel 1 DMA Interrupt +#define USB_DMAINTR_CH0 0x00000001 // Channel 0 DMA Interrupt + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_DMACTL0 register. +// +//***************************************************************************** +#define USB_DMACTL0_BRSTM_M 0x00000600 // Burst Mode +#define USB_DMACTL0_BRSTM_ANY 0x00000000 // Bursts of unspecified length +#define USB_DMACTL0_BRSTM_INC4 0x00000200 // INCR4 or unspecified length +#define USB_DMACTL0_BRSTM_INC8 0x00000400 // INCR8, INCR4 or unspecified + // length +#define USB_DMACTL0_BRSTM_INC16 0x00000600 // INCR16, INCR8, INCR4 or + // unspecified length +#define USB_DMACTL0_ERR 0x00000100 // Bus Error Bit +#define USB_DMACTL0_EP_M 0x000000F0 // Endpoint number +#define USB_DMACTL0_IE 0x00000008 // DMA Interrupt Enable +#define USB_DMACTL0_MODE 0x00000004 // DMA Transfer Mode +#define USB_DMACTL0_DIR 0x00000002 // DMA Direction +#define USB_DMACTL0_ENABLE 0x00000001 // DMA Transfer Enable +#define USB_DMACTL0_EP_S 4 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_DMAADDR0 register. +// +//***************************************************************************** +#define USB_DMAADDR0_ADDR_M 0xFFFFFFFC // DMA Address +#define USB_DMAADDR0_ADDR_S 2 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_DMACOUNT0 +// register. +// +//***************************************************************************** +#define USB_DMACOUNT0_COUNT_M 0xFFFFFFFC // DMA Count +#define USB_DMACOUNT0_COUNT_S 2 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_DMACTL1 register. +// +//***************************************************************************** +#define USB_DMACTL1_BRSTM_M 0x00000600 // Burst Mode +#define USB_DMACTL1_BRSTM_ANY 0x00000000 // Bursts of unspecified length +#define USB_DMACTL1_BRSTM_INC4 0x00000200 // INCR4 or unspecified length +#define USB_DMACTL1_BRSTM_INC8 0x00000400 // INCR8, INCR4 or unspecified + // length +#define USB_DMACTL1_BRSTM_INC16 0x00000600 // INCR16, INCR8, INCR4 or + // unspecified length +#define USB_DMACTL1_ERR 0x00000100 // Bus Error Bit +#define USB_DMACTL1_EP_M 0x000000F0 // Endpoint number +#define USB_DMACTL1_IE 0x00000008 // DMA Interrupt Enable +#define USB_DMACTL1_MODE 0x00000004 // DMA Transfer Mode +#define USB_DMACTL1_DIR 0x00000002 // DMA Direction +#define USB_DMACTL1_ENABLE 0x00000001 // DMA Transfer Enable +#define USB_DMACTL1_EP_S 4 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_DMAADDR1 register. +// +//***************************************************************************** +#define USB_DMAADDR1_ADDR_M 0xFFFFFFFC // DMA Address +#define USB_DMAADDR1_ADDR_S 2 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_DMACOUNT1 +// register. +// +//***************************************************************************** +#define USB_DMACOUNT1_COUNT_M 0xFFFFFFFC // DMA Count +#define USB_DMACOUNT1_COUNT_S 2 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_DMACTL2 register. +// +//***************************************************************************** +#define USB_DMACTL2_BRSTM_M 0x00000600 // Burst Mode +#define USB_DMACTL2_BRSTM_ANY 0x00000000 // Bursts of unspecified length +#define USB_DMACTL2_BRSTM_INC4 0x00000200 // INCR4 or unspecified length +#define USB_DMACTL2_BRSTM_INC8 0x00000400 // INCR8, INCR4 or unspecified + // length +#define USB_DMACTL2_BRSTM_INC16 0x00000600 // INCR16, INCR8, INCR4 or + // unspecified length +#define USB_DMACTL2_ERR 0x00000100 // Bus Error Bit +#define USB_DMACTL2_EP_M 0x000000F0 // Endpoint number +#define USB_DMACTL2_IE 0x00000008 // DMA Interrupt Enable +#define USB_DMACTL2_MODE 0x00000004 // DMA Transfer Mode +#define USB_DMACTL2_DIR 0x00000002 // DMA Direction +#define USB_DMACTL2_ENABLE 0x00000001 // DMA Transfer Enable +#define USB_DMACTL2_EP_S 4 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_DMAADDR2 register. +// +//***************************************************************************** +#define USB_DMAADDR2_ADDR_M 0xFFFFFFFC // DMA Address +#define USB_DMAADDR2_ADDR_S 2 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_DMACOUNT2 +// register. +// +//***************************************************************************** +#define USB_DMACOUNT2_COUNT_M 0xFFFFFFFC // DMA Count +#define USB_DMACOUNT2_COUNT_S 2 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_DMACTL3 register. +// +//***************************************************************************** +#define USB_DMACTL3_BRSTM_M 0x00000600 // Burst Mode +#define USB_DMACTL3_BRSTM_ANY 0x00000000 // Bursts of unspecified length +#define USB_DMACTL3_BRSTM_INC4 0x00000200 // INCR4 or unspecified length +#define USB_DMACTL3_BRSTM_INC8 0x00000400 // INCR8, INCR4 or unspecified + // length +#define USB_DMACTL3_BRSTM_INC16 0x00000600 // INCR16, INCR8, INCR4 or + // unspecified length +#define USB_DMACTL3_ERR 0x00000100 // Bus Error Bit +#define USB_DMACTL3_EP_M 0x000000F0 // Endpoint number +#define USB_DMACTL3_IE 0x00000008 // DMA Interrupt Enable +#define USB_DMACTL3_MODE 0x00000004 // DMA Transfer Mode +#define USB_DMACTL3_DIR 0x00000002 // DMA Direction +#define USB_DMACTL3_ENABLE 0x00000001 // DMA Transfer Enable +#define USB_DMACTL3_EP_S 4 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_DMAADDR3 register. +// +//***************************************************************************** +#define USB_DMAADDR3_ADDR_M 0xFFFFFFFC // DMA Address +#define USB_DMAADDR3_ADDR_S 2 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_DMACOUNT3 +// register. +// +//***************************************************************************** +#define USB_DMACOUNT3_COUNT_M 0xFFFFFFFC // DMA Count +#define USB_DMACOUNT3_COUNT_S 2 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_DMACTL4 register. +// +//***************************************************************************** +#define USB_DMACTL4_BRSTM_M 0x00000600 // Burst Mode +#define USB_DMACTL4_BRSTM_ANY 0x00000000 // Bursts of unspecified length +#define USB_DMACTL4_BRSTM_INC4 0x00000200 // INCR4 or unspecified length +#define USB_DMACTL4_BRSTM_INC8 0x00000400 // INCR8, INCR4 or unspecified + // length +#define USB_DMACTL4_BRSTM_INC16 0x00000600 // INCR16, INCR8, INCR4 or + // unspecified length +#define USB_DMACTL4_ERR 0x00000100 // Bus Error Bit +#define USB_DMACTL4_EP_M 0x000000F0 // Endpoint number +#define USB_DMACTL4_IE 0x00000008 // DMA Interrupt Enable +#define USB_DMACTL4_MODE 0x00000004 // DMA Transfer Mode +#define USB_DMACTL4_DIR 0x00000002 // DMA Direction +#define USB_DMACTL4_ENABLE 0x00000001 // DMA Transfer Enable +#define USB_DMACTL4_EP_S 4 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_DMAADDR4 register. +// +//***************************************************************************** +#define USB_DMAADDR4_ADDR_M 0xFFFFFFFC // DMA Address +#define USB_DMAADDR4_ADDR_S 2 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_DMACOUNT4 +// register. +// +//***************************************************************************** +#define USB_DMACOUNT4_COUNT_M 0xFFFFFFFC // DMA Count +#define USB_DMACOUNT4_COUNT_S 2 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_DMACTL5 register. +// +//***************************************************************************** +#define USB_DMACTL5_BRSTM_M 0x00000600 // Burst Mode +#define USB_DMACTL5_BRSTM_ANY 0x00000000 // Bursts of unspecified length +#define USB_DMACTL5_BRSTM_INC4 0x00000200 // INCR4 or unspecified length +#define USB_DMACTL5_BRSTM_INC8 0x00000400 // INCR8, INCR4 or unspecified + // length +#define USB_DMACTL5_BRSTM_INC16 0x00000600 // INCR16, INCR8, INCR4 or + // unspecified length +#define USB_DMACTL5_ERR 0x00000100 // Bus Error Bit +#define USB_DMACTL5_EP_M 0x000000F0 // Endpoint number +#define USB_DMACTL5_IE 0x00000008 // DMA Interrupt Enable +#define USB_DMACTL5_MODE 0x00000004 // DMA Transfer Mode +#define USB_DMACTL5_DIR 0x00000002 // DMA Direction +#define USB_DMACTL5_ENABLE 0x00000001 // DMA Transfer Enable +#define USB_DMACTL5_EP_S 4 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_DMAADDR5 register. +// +//***************************************************************************** +#define USB_DMAADDR5_ADDR_M 0xFFFFFFFC // DMA Address +#define USB_DMAADDR5_ADDR_S 2 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_DMACOUNT5 +// register. +// +//***************************************************************************** +#define USB_DMACOUNT5_COUNT_M 0xFFFFFFFC // DMA Count +#define USB_DMACOUNT5_COUNT_S 2 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_DMACTL6 register. +// +//***************************************************************************** +#define USB_DMACTL6_BRSTM_M 0x00000600 // Burst Mode +#define USB_DMACTL6_BRSTM_ANY 0x00000000 // Bursts of unspecified length +#define USB_DMACTL6_BRSTM_INC4 0x00000200 // INCR4 or unspecified length +#define USB_DMACTL6_BRSTM_INC8 0x00000400 // INCR8, INCR4 or unspecified + // length +#define USB_DMACTL6_BRSTM_INC16 0x00000600 // INCR16, INCR8, INCR4 or + // unspecified length +#define USB_DMACTL6_ERR 0x00000100 // Bus Error Bit +#define USB_DMACTL6_EP_M 0x000000F0 // Endpoint number +#define USB_DMACTL6_IE 0x00000008 // DMA Interrupt Enable +#define USB_DMACTL6_MODE 0x00000004 // DMA Transfer Mode +#define USB_DMACTL6_DIR 0x00000002 // DMA Direction +#define USB_DMACTL6_ENABLE 0x00000001 // DMA Transfer Enable +#define USB_DMACTL6_EP_S 4 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_DMAADDR6 register. +// +//***************************************************************************** +#define USB_DMAADDR6_ADDR_M 0xFFFFFFFC // DMA Address +#define USB_DMAADDR6_ADDR_S 2 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_DMACOUNT6 +// register. +// +//***************************************************************************** +#define USB_DMACOUNT6_COUNT_M 0xFFFFFFFC // DMA Count +#define USB_DMACOUNT6_COUNT_S 2 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_DMACTL7 register. +// +//***************************************************************************** +#define USB_DMACTL7_BRSTM_M 0x00000600 // Burst Mode +#define USB_DMACTL7_BRSTM_ANY 0x00000000 // Bursts of unspecified length +#define USB_DMACTL7_BRSTM_INC4 0x00000200 // INCR4 or unspecified length +#define USB_DMACTL7_BRSTM_INC8 0x00000400 // INCR8, INCR4 or unspecified + // length +#define USB_DMACTL7_BRSTM_INC16 0x00000600 // INCR16, INCR8, INCR4 or + // unspecified length +#define USB_DMACTL7_ERR 0x00000100 // Bus Error Bit +#define USB_DMACTL7_EP_M 0x000000F0 // Endpoint number +#define USB_DMACTL7_IE 0x00000008 // DMA Interrupt Enable +#define USB_DMACTL7_MODE 0x00000004 // DMA Transfer Mode +#define USB_DMACTL7_DIR 0x00000002 // DMA Direction +#define USB_DMACTL7_ENABLE 0x00000001 // DMA Transfer Enable +#define USB_DMACTL7_EP_S 4 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_DMAADDR7 register. +// +//***************************************************************************** +#define USB_DMAADDR7_ADDR_M 0xFFFFFFFC // DMA Address +#define USB_DMAADDR7_ADDR_S 2 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_DMACOUNT7 +// register. +// +//***************************************************************************** +#define USB_DMACOUNT7_COUNT_M 0xFFFFFFFC // DMA Count +#define USB_DMACOUNT7_COUNT_S 2 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RQPKTCOUNT1 +// register. +// +//***************************************************************************** +#define USB_RQPKTCOUNT1_M 0x0000FFFF // Block Transfer Packet Count +#define USB_RQPKTCOUNT1_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RQPKTCOUNT2 +// register. +// +//***************************************************************************** +#define USB_RQPKTCOUNT2_M 0x0000FFFF // Block Transfer Packet Count +#define USB_RQPKTCOUNT2_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RQPKTCOUNT3 +// register. +// +//***************************************************************************** +#define USB_RQPKTCOUNT3_M 0x0000FFFF // Block Transfer Packet Count +#define USB_RQPKTCOUNT3_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RQPKTCOUNT4 +// register. +// +//***************************************************************************** +#define USB_RQPKTCOUNT4_COUNT_M 0x0000FFFF // Block Transfer Packet Count +#define USB_RQPKTCOUNT4_COUNT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RQPKTCOUNT5 +// register. +// +//***************************************************************************** +#define USB_RQPKTCOUNT5_COUNT_M 0x0000FFFF // Block Transfer Packet Count +#define USB_RQPKTCOUNT5_COUNT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RQPKTCOUNT6 +// register. +// +//***************************************************************************** +#define USB_RQPKTCOUNT6_COUNT_M 0x0000FFFF // Block Transfer Packet Count +#define USB_RQPKTCOUNT6_COUNT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RQPKTCOUNT7 +// register. +// +//***************************************************************************** +#define USB_RQPKTCOUNT7_COUNT_M 0x0000FFFF // Block Transfer Packet Count +#define USB_RQPKTCOUNT7_COUNT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXDPKTBUFDIS +// register. +// +//***************************************************************************** +#define USB_RXDPKTBUFDIS_EP7 0x00000080 // EP7 RX Double-Packet Buffer + // Disable +#define USB_RXDPKTBUFDIS_EP6 0x00000040 // EP6 RX Double-Packet Buffer + // Disable +#define USB_RXDPKTBUFDIS_EP5 0x00000020 // EP5 RX Double-Packet Buffer + // Disable +#define USB_RXDPKTBUFDIS_EP4 0x00000010 // EP4 RX Double-Packet Buffer + // Disable +#define USB_RXDPKTBUFDIS_EP3 0x00000008 // EP3 RX Double-Packet Buffer + // Disable +#define USB_RXDPKTBUFDIS_EP2 0x00000004 // EP2 RX Double-Packet Buffer + // Disable +#define USB_RXDPKTBUFDIS_EP1 0x00000002 // EP1 RX Double-Packet Buffer + // Disable + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXDPKTBUFDIS +// register. +// +//***************************************************************************** +#define USB_TXDPKTBUFDIS_EP7 0x00000080 // EP7 TX Double-Packet Buffer + // Disable +#define USB_TXDPKTBUFDIS_EP6 0x00000040 // EP6 TX Double-Packet Buffer + // Disable +#define USB_TXDPKTBUFDIS_EP5 0x00000020 // EP5 TX Double-Packet Buffer + // Disable +#define USB_TXDPKTBUFDIS_EP4 0x00000010 // EP4 TX Double-Packet Buffer + // Disable +#define USB_TXDPKTBUFDIS_EP3 0x00000008 // EP3 TX Double-Packet Buffer + // Disable +#define USB_TXDPKTBUFDIS_EP2 0x00000004 // EP2 TX Double-Packet Buffer + // Disable +#define USB_TXDPKTBUFDIS_EP1 0x00000002 // EP1 TX Double-Packet Buffer + // Disable + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_CTO register. +// +//***************************************************************************** +#define USB_CTO_CCTV_M 0x0000FFFF // Configurable Chirp Timeout Value +#define USB_CTO_CCTV_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_HHSRTN register. +// +//***************************************************************************** +#define USB_HHSRTN_HHSRTN_M 0x0000FFFF // HIgh Speed to UTM Operating + // Delay +#define USB_HHSRTN_HHSRTN_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_HSBT register. +// +//***************************************************************************** +#define USB_HSBT_HSBT_M 0x0000000F // High Speed Timeout Adder +#define USB_HSBT_HSBT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_LPMATTR register. +// +//***************************************************************************** +#define USB_LPMATTR_ENDPT_M 0x0000F000 // Endpoint +#define USB_LPMATTR_RMTWAK 0x00000100 // Remote Wake +#define USB_LPMATTR_HIRD_M 0x000000F0 // Host Initiated Resume Duration +#define USB_LPMATTR_LS_M 0x0000000F // Link State +#define USB_LPMATTR_LS_L1 0x00000001 // Sleep State (L1) +#define USB_LPMATTR_ENDPT_S 12 +#define USB_LPMATTR_HIRD_S 4 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_LPMCNTRL register. +// +//***************************************************************************** +#define USB_LPMCNTRL_NAK 0x00000010 // LPM NAK +#define USB_LPMCNTRL_EN_M 0x0000000C // LPM Enable +#define USB_LPMCNTRL_EN_NONE 0x00000000 // LPM and Extended transactions + // are not supported. In this case, + // the USB does not respond to LPM + // transactions and LPM + // transactions cause a timeout +#define USB_LPMCNTRL_EN_EXT 0x00000004 // LPM is not supported but + // extended transactions are + // supported. In this case, the USB + // does respond to an LPM + // transaction with a STALL +#define USB_LPMCNTRL_EN_LPMEXT 0x0000000C // The USB supports LPM extended + // transactions. In this case, the + // USB responds with a NYET or an + // ACK as determined by the value + // of TXLPM and other conditions +#define USB_LPMCNTRL_RES 0x00000002 // LPM Resume +#define USB_LPMCNTRL_TXLPM 0x00000001 // Transmit LPM Transaction Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_LPMIM register. +// +//***************************************************************************** +#define USB_LPMIM_ERR 0x00000020 // LPM Error Interrupt Mask +#define USB_LPMIM_RES 0x00000010 // LPM Resume Interrupt Mask +#define USB_LPMIM_NC 0x00000008 // LPM NC Interrupt Mask +#define USB_LPMIM_ACK 0x00000004 // LPM ACK Interrupt Mask +#define USB_LPMIM_NY 0x00000002 // LPM NY Interrupt Mask +#define USB_LPMIM_STALL 0x00000001 // LPM STALL Interrupt Mask + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_LPMRIS register. +// +//***************************************************************************** +#define USB_LPMRIS_ERR 0x00000020 // LPM Interrupt Status +#define USB_LPMRIS_RES 0x00000010 // LPM Resume Interrupt Status +#define USB_LPMRIS_NC 0x00000008 // LPM NC Interrupt Status +#define USB_LPMRIS_ACK 0x00000004 // LPM ACK Interrupt Status +#define USB_LPMRIS_NY 0x00000002 // LPM NY Interrupt Status +#define USB_LPMRIS_LPMST 0x00000001 // LPM STALL Interrupt Status + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_LPMFADDR register. +// +//***************************************************************************** +#define USB_LPMFADDR_ADDR_M 0x0000007F // LPM Function Address +#define USB_LPMFADDR_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_EPC register. +// +//***************************************************************************** +#define USB_EPC_PFLTACT_M 0x00000300 // Power Fault Action +#define USB_EPC_PFLTACT_UNCHG 0x00000000 // Unchanged +#define USB_EPC_PFLTACT_TRIS 0x00000100 // Tristate +#define USB_EPC_PFLTACT_LOW 0x00000200 // Low +#define USB_EPC_PFLTACT_HIGH 0x00000300 // High +#define USB_EPC_PFLTAEN 0x00000040 // Power Fault Action Enable +#define USB_EPC_PFLTSEN_HIGH 0x00000020 // Power Fault Sense +#define USB_EPC_PFLTEN 0x00000010 // Power Fault Input Enable +#define USB_EPC_EPENDE 0x00000004 // EPEN Drive Enable +#define USB_EPC_EPEN_M 0x00000003 // External Power Supply Enable + // Configuration +#define USB_EPC_EPEN_LOW 0x00000000 // Power Enable Active Low +#define USB_EPC_EPEN_HIGH 0x00000001 // Power Enable Active High +#define USB_EPC_EPEN_VBLOW 0x00000002 // Power Enable High if VBUS Low + // (OTG only) +#define USB_EPC_EPEN_VBHIGH 0x00000003 // Power Enable High if VBUS High + // (OTG only) + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_EPCRIS register. +// +//***************************************************************************** +#define USB_EPCRIS_PF 0x00000001 // USB Power Fault Interrupt Status + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_EPCIM register. +// +//***************************************************************************** +#define USB_EPCIM_PF 0x00000001 // USB Power Fault Interrupt Mask + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_EPCISC register. +// +//***************************************************************************** +#define USB_EPCISC_PF 0x00000001 // USB Power Fault Interrupt Status + // and Clear + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_DRRIS register. +// +//***************************************************************************** +#define USB_DRRIS_RESUME 0x00000001 // RESUME Interrupt Status + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_DRIM register. +// +//***************************************************************************** +#define USB_DRIM_RESUME 0x00000001 // RESUME Interrupt Mask + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_DRISC register. +// +//***************************************************************************** +#define USB_DRISC_RESUME 0x00000001 // RESUME Interrupt Status and + // Clear + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_GPCS register. +// +//***************************************************************************** +#define USB_GPCS_DEVMOD_M 0x00000007 // Device Mode +#define USB_GPCS_DEVMOD_OTG 0x00000000 // Use USB0VBUS and USB0ID pin +#define USB_GPCS_DEVMOD_HOST 0x00000002 // Force USB0VBUS and USB0ID low +#define USB_GPCS_DEVMOD_DEV 0x00000003 // Force USB0VBUS and USB0ID high +#define USB_GPCS_DEVMOD_HOSTVBUS \ + 0x00000004 // Use USB0VBUS and force USB0ID + // low +#define USB_GPCS_DEVMOD_DEVVBUS 0x00000005 // Use USB0VBUS and force USB0ID + // high +#define USB_GPCS_DEVMODOTG 0x00000002 // Enable Device Mode +#define USB_GPCS_DEVMOD 0x00000001 // Device Mode + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_VDC register. +// +//***************************************************************************** +#define USB_VDC_VBDEN 0x00000001 // VBUS Droop Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_VDCRIS register. +// +//***************************************************************************** +#define USB_VDCRIS_VD 0x00000001 // VBUS Droop Raw Interrupt Status + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_VDCIM register. +// +//***************************************************************************** +#define USB_VDCIM_VD 0x00000001 // VBUS Droop Interrupt Mask + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_VDCISC register. +// +//***************************************************************************** +#define USB_VDCISC_VD 0x00000001 // VBUS Droop Interrupt Status and + // Clear + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_IDVRIS register. +// +//***************************************************************************** +#define USB_IDVRIS_ID 0x00000001 // ID Valid Detect Raw Interrupt + // Status + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_IDVIM register. +// +//***************************************************************************** +#define USB_IDVIM_ID 0x00000001 // ID Valid Detect Interrupt Mask + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_IDVISC register. +// +//***************************************************************************** +#define USB_IDVISC_ID 0x00000001 // ID Valid Detect Interrupt Status + // and Clear + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_PP register. +// +//***************************************************************************** +#define USB_PP_ECNT_M 0x0000FF00 // Endpoint Count +#define USB_PP_USB_M 0x000000C0 // USB Capability +#define USB_PP_USB_DEVICE 0x00000040 // DEVICE +#define USB_PP_USB_HOSTDEVICE 0x00000080 // HOST +#define USB_PP_USB_OTG 0x000000C0 // OTG +#define USB_PP_ULPI 0x00000020 // ULPI Present +#define USB_PP_PHY 0x00000010 // PHY Present + +#define USB_PP_ECNT_S 8 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_PC register. +// +//***************************************************************************** +#define USB_PC_ULPIEN 0x00010000 // ULPI Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_CC register. +// +//***************************************************************************** +#define USB_CC_CLKEN 0x00000200 // USB Clock Enable +#define USB_CC_CSD 0x00000100 // Clock Source/Direction +#define USB_CC_CLKDIV_M 0x0000000F // PLL Clock Divisor +#define USB_CC_CLKDIV_S 0 + + +//***************************************************************************** +// +// The following are values that can be passed to USBIntEnableControl() and +// USBIntDisableControl() as the ui32Flags parameter, and are returned from +// USBIntStatusControl(). +// +//***************************************************************************** +#define USB_INTCTRL_ALL 0x000003FF // All control interrupt sources +#define USB_INTCTRL_STATUS 0x000000FF // Status Interrupts +#define USB_INTCTRL_VBUS_ERR 0x00000080 // VBUS Error +#define USB_INTCTRL_SESSION 0x00000040 // Session Start Detected +#define USB_INTCTRL_SESSION_END 0x00000040 // Session End Detected +#define USB_INTCTRL_DISCONNECT 0x00000020 // Disconnect Detected +#define USB_INTCTRL_CONNECT 0x00000010 // Device Connect Detected +#define USB_INTCTRL_SOF 0x00000008 // Start of Frame Detected +#define USB_INTCTRL_BABBLE 0x00000004 // Babble signaled +#define USB_INTCTRL_RESET 0x00000004 // Reset signaled +#define USB_INTCTRL_RESUME 0x00000002 // Resume detected +#define USB_INTCTRL_SUSPEND 0x00000001 // Suspend detected +#define USB_INTCTRL_MODE_DETECT 0x00000200 // Mode value valid +#define USB_INTCTRL_POWER_FAULT 0x00000100 // Power Fault detected + +//***************************************************************************** +// +// The following are values that can be passed to USBIntEnableEndpoint() and +// USBIntDisableEndpoint() as the ui32Flags parameter, and are returned from +// USBIntStatusEndpoint(). +// +//***************************************************************************** +#define USB_INTEP_ALL 0xFFFFFFFF // Host IN Interrupts +#define USB_INTEP_HOST_IN 0xFFFE0000 // Host IN Interrupts +#define USB_INTEP_HOST_IN_15 0x80000000 // Endpoint 15 Host IN Interrupt +#define USB_INTEP_HOST_IN_14 0x40000000 // Endpoint 14 Host IN Interrupt +#define USB_INTEP_HOST_IN_13 0x20000000 // Endpoint 13 Host IN Interrupt +#define USB_INTEP_HOST_IN_12 0x10000000 // Endpoint 12 Host IN Interrupt +#define USB_INTEP_HOST_IN_11 0x08000000 // Endpoint 11 Host IN Interrupt +#define USB_INTEP_HOST_IN_10 0x04000000 // Endpoint 10 Host IN Interrupt +#define USB_INTEP_HOST_IN_9 0x02000000 // Endpoint 9 Host IN Interrupt +#define USB_INTEP_HOST_IN_8 0x01000000 // Endpoint 8 Host IN Interrupt +#define USB_INTEP_HOST_IN_7 0x00800000 // Endpoint 7 Host IN Interrupt +#define USB_INTEP_HOST_IN_6 0x00400000 // Endpoint 6 Host IN Interrupt +#define USB_INTEP_HOST_IN_5 0x00200000 // Endpoint 5 Host IN Interrupt +#define USB_INTEP_HOST_IN_4 0x00100000 // Endpoint 4 Host IN Interrupt +#define USB_INTEP_HOST_IN_3 0x00080000 // Endpoint 3 Host IN Interrupt +#define USB_INTEP_HOST_IN_2 0x00040000 // Endpoint 2 Host IN Interrupt +#define USB_INTEP_HOST_IN_1 0x00020000 // Endpoint 1 Host IN Interrupt + +#define USB_INTEP_DEV_OUT 0xFFFE0000 // Device OUT Interrupts +#define USB_INTEP_DEV_OUT_15 0x80000000 // Endpoint 15 Device OUT Interrupt +#define USB_INTEP_DEV_OUT_14 0x40000000 // Endpoint 14 Device OUT Interrupt +#define USB_INTEP_DEV_OUT_13 0x20000000 // Endpoint 13 Device OUT Interrupt +#define USB_INTEP_DEV_OUT_12 0x10000000 // Endpoint 12 Device OUT Interrupt +#define USB_INTEP_DEV_OUT_11 0x08000000 // Endpoint 11 Device OUT Interrupt +#define USB_INTEP_DEV_OUT_10 0x04000000 // Endpoint 10 Device OUT Interrupt +#define USB_INTEP_DEV_OUT_9 0x02000000 // Endpoint 9 Device OUT Interrupt +#define USB_INTEP_DEV_OUT_8 0x01000000 // Endpoint 8 Device OUT Interrupt +#define USB_INTEP_DEV_OUT_7 0x00800000 // Endpoint 7 Device OUT Interrupt +#define USB_INTEP_DEV_OUT_6 0x00400000 // Endpoint 6 Device OUT Interrupt +#define USB_INTEP_DEV_OUT_5 0x00200000 // Endpoint 5 Device OUT Interrupt +#define USB_INTEP_DEV_OUT_4 0x00100000 // Endpoint 4 Device OUT Interrupt +#define USB_INTEP_DEV_OUT_3 0x00080000 // Endpoint 3 Device OUT Interrupt +#define USB_INTEP_DEV_OUT_2 0x00040000 // Endpoint 2 Device OUT Interrupt +#define USB_INTEP_DEV_OUT_1 0x00020000 // Endpoint 1 Device OUT Interrupt + +#define USB_INTEP_HOST_OUT 0x0000FFFE // Host OUT Interrupts +#define USB_INTEP_HOST_OUT_15 0x00008000 // Endpoint 15 Host OUT Interrupt +#define USB_INTEP_HOST_OUT_14 0x00004000 // Endpoint 14 Host OUT Interrupt +#define USB_INTEP_HOST_OUT_13 0x00002000 // Endpoint 13 Host OUT Interrupt +#define USB_INTEP_HOST_OUT_12 0x00001000 // Endpoint 12 Host OUT Interrupt +#define USB_INTEP_HOST_OUT_11 0x00000800 // Endpoint 11 Host OUT Interrupt +#define USB_INTEP_HOST_OUT_10 0x00000400 // Endpoint 10 Host OUT Interrupt +#define USB_INTEP_HOST_OUT_9 0x00000200 // Endpoint 9 Host OUT Interrupt +#define USB_INTEP_HOST_OUT_8 0x00000100 // Endpoint 8 Host OUT Interrupt +#define USB_INTEP_HOST_OUT_7 0x00000080 // Endpoint 7 Host OUT Interrupt +#define USB_INTEP_HOST_OUT_6 0x00000040 // Endpoint 6 Host OUT Interrupt +#define USB_INTEP_HOST_OUT_5 0x00000020 // Endpoint 5 Host OUT Interrupt +#define USB_INTEP_HOST_OUT_4 0x00000010 // Endpoint 4 Host OUT Interrupt +#define USB_INTEP_HOST_OUT_3 0x00000008 // Endpoint 3 Host OUT Interrupt +#define USB_INTEP_HOST_OUT_2 0x00000004 // Endpoint 2 Host OUT Interrupt +#define USB_INTEP_HOST_OUT_1 0x00000002 // Endpoint 1 Host OUT Interrupt + +#define USB_INTEP_DEV_IN 0x0000FFFE // Device IN Interrupts +#define USB_INTEP_DEV_IN_15 0x00008000 // Endpoint 15 Device IN Interrupt +#define USB_INTEP_DEV_IN_14 0x00004000 // Endpoint 14 Device IN Interrupt +#define USB_INTEP_DEV_IN_13 0x00002000 // Endpoint 13 Device IN Interrupt +#define USB_INTEP_DEV_IN_12 0x00001000 // Endpoint 12 Device IN Interrupt +#define USB_INTEP_DEV_IN_11 0x00000800 // Endpoint 11 Device IN Interrupt +#define USB_INTEP_DEV_IN_10 0x00000400 // Endpoint 10 Device IN Interrupt +#define USB_INTEP_DEV_IN_9 0x00000200 // Endpoint 9 Device IN Interrupt +#define USB_INTEP_DEV_IN_8 0x00000100 // Endpoint 8 Device IN Interrupt +#define USB_INTEP_DEV_IN_7 0x00000080 // Endpoint 7 Device IN Interrupt +#define USB_INTEP_DEV_IN_6 0x00000040 // Endpoint 6 Device IN Interrupt +#define USB_INTEP_DEV_IN_5 0x00000020 // Endpoint 5 Device IN Interrupt +#define USB_INTEP_DEV_IN_4 0x00000010 // Endpoint 4 Device IN Interrupt +#define USB_INTEP_DEV_IN_3 0x00000008 // Endpoint 3 Device IN Interrupt +#define USB_INTEP_DEV_IN_2 0x00000004 // Endpoint 2 Device IN Interrupt +#define USB_INTEP_DEV_IN_1 0x00000002 // Endpoint 1 Device IN Interrupt + +#define USB_INTEP_0 0x00000001 // Endpoint 0 Interrupt + +//***************************************************************************** +// +// The following are values that are returned from USBSpeedGet(). +// +//***************************************************************************** +#define USB_UNDEF_SPEED 0x80000000 // Current speed is undefined +#define USB_HIGH_SPEED 0x00000002 // Current speed is High Speed +#define USB_FULL_SPEED 0x00000001 // Current speed is Full Speed +#define USB_LOW_SPEED 0x00000000 // Current speed is Low Speed + +//***************************************************************************** +// +// The following are values that are returned from USBEndpointStatus(). The +// USB_HOST_* values are used when the USB controller is in host mode and the +// USB_DEV_* values are used when the USB controller is in device mode. +// +//***************************************************************************** +#define USB_HOST_IN_STATUS 0x114F0000 // Mask of all host IN interrupts +#define USB_HOST_IN_PID_ERROR 0x10000000 // Stall on this endpoint received +#define USB_HOST_IN_NOT_COMP 0x01000000 // Device failed to respond +#define USB_HOST_IN_STALL 0x00400000 // Stall on this endpoint received +#define USB_HOST_IN_DATA_ERROR 0x00080000 // CRC or bit-stuff error + // (ISOC Mode) +#define USB_HOST_IN_NAK_TO 0x00080000 // NAK received for more than the + // specified timeout period +#define USB_HOST_IN_ERROR 0x00040000 // Failed to communicate with a + // device +#define USB_HOST_IN_FIFO_FULL 0x00020000 // RX FIFO full +#define USB_HOST_IN_PKTRDY 0x00010000 // Data packet ready +#define USB_HOST_OUT_STATUS 0x000000A7 // Mask of all host OUT interrupts +#define USB_HOST_OUT_NAK_TO 0x00000080 // NAK received for more than the + // specified timeout period +#define USB_HOST_OUT_NOT_COMP 0x00000080 // No response from device + // (ISOC mode) +#define USB_HOST_OUT_STALL 0x00000020 // Stall on this endpoint received +#define USB_HOST_OUT_ERROR 0x00000004 // Failed to communicate with a + // device +#define USB_HOST_OUT_FIFO_NE 0x00000002 // TX FIFO is not empty +#define USB_HOST_OUT_PKTPEND 0x00000001 // Transmit still being transmitted +#define USB_HOST_EP0_NAK_TO 0x00000080 // NAK received for more than the + // specified timeout period +#define USB_HOST_EP0_STATUS 0x00000040 // This was a status packet +#define USB_HOST_EP0_ERROR 0x00000010 // Failed to communicate with a + // device +#define USB_HOST_EP0_RX_STALL 0x00000004 // Stall on this endpoint received +#define USB_HOST_EP0_RXPKTRDY 0x00000001 // Receive data packet ready +#define USB_DEV_RX_PID_ERROR 0x01000000 // PID error in isochronous + // transfer +#define USB_DEV_RX_SENT_STALL 0x00400000 // Stall was sent on this endpoint +#define USB_DEV_RX_DATA_ERROR 0x00080000 // CRC error on the data +#define USB_DEV_RX_OVERRUN 0x00040000 // OUT packet was not loaded due to + // a full FIFO +#define USB_DEV_RX_FIFO_FULL 0x00020000 // RX FIFO full +#define USB_DEV_RX_PKT_RDY 0x00010000 // Data packet ready +#define USB_DEV_TX_NOT_COMP 0x00000080 // Large packet split up, more data + // to come +#define USB_DEV_TX_SENT_STALL 0x00000020 // Stall was sent on this endpoint +#define USB_DEV_TX_UNDERRUN 0x00000004 // IN received with no data ready +#define USB_DEV_TX_FIFO_NE 0x00000002 // The TX FIFO is not empty +#define USB_DEV_TX_TXPKTRDY 0x00000001 // Transmit still being transmitted +#define USB_DEV_EP0_SETUP_END 0x00000010 // Control transaction ended before + // Data End seen +#define USB_DEV_EP0_SENT_STALL 0x00000004 // Stall was sent on this endpoint +#define USB_DEV_EP0_IN_PKTPEND 0x00000002 // Transmit data packet pending +#define USB_DEV_EP0_OUT_PKTRDY 0x00000001 // Receive data packet ready + +//***************************************************************************** +// +// The following are values that can be passed to USBHostEndpointConfig() and +// USBDevEndpointConfigSet() as the ui32Flags parameter. +// +//***************************************************************************** +#define USB_EP_AUTO_SET 0x00000001 // Auto set feature enabled +#define USB_EP_AUTO_REQUEST 0x00000002 // Auto request feature enabled +#define USB_EP_AUTO_CLEAR 0x00000004 // Auto clear feature enabled +#define USB_EP_DMA_MODE_0 0x00000008 // Enable DMA access using mode 0 +#define USB_EP_DMA_MODE_1 0x00000010 // Enable DMA access using mode 1 +#define USB_EP_DIS_NYET 0x00000020 // Disable NYET response for + // high-speed Bulk and Interrupt + // endpoints in device mode. +#define USB_EP_MODE_ISOC 0x00000000 // Isochronous endpoint +#define USB_EP_MODE_BULK 0x00000100 // Bulk endpoint +#define USB_EP_MODE_INT 0x00000200 // Interrupt endpoint +#define USB_EP_MODE_CTRL 0x00000300 // Control endpoint +#define USB_EP_MODE_MASK 0x00000300 // Mode Mask +#define USB_EP_SPEED_LOW 0x00000000 // Low Speed +#define USB_EP_SPEED_FULL 0x00001000 // Full Speed +#define USB_EP_SPEED_HIGH 0x00004000 // High Speed +#define USB_EP_HOST_IN 0x00000000 // Host IN endpoint +#define USB_EP_HOST_OUT 0x00002000 // Host OUT endpoint +#define USB_EP_DEV_IN 0x00002000 // Device IN endpoint +#define USB_EP_DEV_OUT 0x00000000 // Device OUT endpoint + +//***************************************************************************** +// +// The following are values that can be passed to USBHostPwrConfig() as the +// ui32Flags parameter. +// +//***************************************************************************** +#define USB_HOST_PWRFLT_LOW 0x00000010 +#define USB_HOST_PWRFLT_HIGH 0x00000030 +#define USB_HOST_PWRFLT_EP_NONE 0x00000000 +#define USB_HOST_PWRFLT_EP_TRI 0x00000140 +#define USB_HOST_PWRFLT_EP_LOW 0x00000240 +#define USB_HOST_PWRFLT_EP_HIGH 0x00000340 +#define USB_HOST_PWREN_MAN_LOW 0x00000000 +#define USB_HOST_PWREN_MAN_HIGH 0x00000001 +#define USB_HOST_PWREN_AUTOLOW 0x00000002 +#define USB_HOST_PWREN_AUTOHIGH 0x00000003 +#define USB_HOST_PWREN_FILTER 0x00010000 + +//***************************************************************************** +// +// The following are the valid values that can be passed to the +// USBHostLPMConfig() function in the ui32Config parameter. +// +//***************************************************************************** +#define USB_HOST_LPM_RMTWAKE 0x00000100 +#define USB_HOST_LPM_L1 0x00000001 + +//***************************************************************************** +// +// The following are the valid values that can be passed to the +// USBDevLPMConfig() function in the ui32Config parameter. +// +//***************************************************************************** +#define USB_DEV_LPM_NAK 0x00000010 +#define USB_DEV_LPM_NONE 0x00000000 +#define USB_DEV_LPM_EN 0x0000000c +#define USB_DEV_LPM_EXTONLY 0x00000004 + +//***************************************************************************** +// +// The following are the valid values that are returned from the +// USBLPMLinkStateGet() function. +// +//***************************************************************************** +#define USB_DEV_LPM_LS_RMTWAKE 0x00000100 +#define USB_DEV_LPM_LS_L1 0x00000001 + +//***************************************************************************** +// +// The following are the valid values that are passed to the USBLPMIntEnable() +// or USBLPMIntDisable() functions or are returned from the USBLPMIntStatus() +// function. +// +//***************************************************************************** +#define USB_INTLPM_ERROR 0x00000020 +#define USB_INTLPM_RESUME 0x00000010 +#define USB_INTLPM_INCOMPLETE 0x00000008 +#define USB_INTLPM_ACK 0x00000004 +#define USB_INTLPM_NYET 0x00000002 +#define USB_INTLPM_STALL 0x00000001 + +//***************************************************************************** +// +// The following are the valid values that are passed to the USBClockEnable() +// functions. +// +//***************************************************************************** +#define USB_CLOCK_INTERNAL 0x00000200 +#define USB_CLOCK_EXTERNAL 0x00000300 + +//***************************************************************************** +// +// The configuration options used with the USBULPIConfig() API. +// +//***************************************************************************** +#define USB_ULPI_EXTVBUS 0x00000001 +#define USB_ULPI_EXTVBUS_IND 0x00000002 + +//***************************************************************************** +// +// The following are special values that can be passed to +// USBHostEndpointConfig() as the ui32NAKPollInterval parameter. +// +//***************************************************************************** +#define MAX_NAK_LIMIT 31 // Maximum NAK interval +#define DISABLE_NAK_LIMIT 0 // No NAK timeouts + +//***************************************************************************** +// +// This value specifies the maximum size of transfers on endpoint 0 as 64 +// bytes. This value is fixed in hardware as the FIFO size for endpoint 0. +// +//***************************************************************************** +#define MAX_PACKET_SIZE_EP0 64 + +//***************************************************************************** +// +// These values are used to indicate which endpoint to access. +// +//***************************************************************************** +#define USB_EP_0 0x00000000 // Endpoint 0 +#define USB_EP_1 0x00000010 // Endpoint 1 +#define USB_EP_2 0x00000020 // Endpoint 2 +#define USB_EP_3 0x00000030 // Endpoint 3 +#define USB_EP_4 0x00000040 // Endpoint 4 +#define USB_EP_5 0x00000050 // Endpoint 5 +#define USB_EP_6 0x00000060 // Endpoint 6 +#define USB_EP_7 0x00000070 // Endpoint 7 +#define NUM_USB_EP 8 // Number of supported endpoints + +//***************************************************************************** +// +// These macros allow conversion between 0-based endpoint indices and the +// USB_EP_x values required when calling various USB APIs. +// +//***************************************************************************** +#define IndexToUSBEP(x) ((x) << 4) +#define USBEPToIndex(x) ((x) >> 4) + +//***************************************************************************** +// +// The following are values that can be passed to USBFIFOConfigSet() as the +// ui32FIFOSize parameter. +// +//***************************************************************************** +#define USB_FIFO_SZ_8 0x00000000 // 8 byte FIFO +#define USB_FIFO_SZ_16 0x00000001 // 16 byte FIFO +#define USB_FIFO_SZ_32 0x00000002 // 32 byte FIFO +#define USB_FIFO_SZ_64 0x00000003 // 64 byte FIFO +#define USB_FIFO_SZ_128 0x00000004 // 128 byte FIFO +#define USB_FIFO_SZ_256 0x00000005 // 256 byte FIFO +#define USB_FIFO_SZ_512 0x00000006 // 512 byte FIFO +#define USB_FIFO_SZ_1024 0x00000007 // 1024 byte FIFO +#define USB_FIFO_SZ_2048 0x00000008 // 2048 byte FIFO + +//***************************************************************************** +// +// This macro allow conversion from a FIFO size label as defined above to +// a number of bytes +// +//***************************************************************************** +#define USBFIFOSizeToBytes(x) (8 << (x)) + +//***************************************************************************** +// +// The following are values that can be passed to USBEndpointDataSend() as the +// ui32TransType parameter. +// +//***************************************************************************** +#define USB_TRANS_OUT 0x00000102 // Normal OUT transaction +#define USB_TRANS_IN 0x00000102 // Normal IN transaction +#define USB_TRANS_IN_LAST 0x0000010a // Final IN transaction (for + // endpoint 0 in device mode) +#define USB_TRANS_SETUP 0x0000110a // Setup transaction (for endpoint + // 0) +#define USB_TRANS_STATUS 0x00000142 // Status transaction (for endpoint + // 0) + +//***************************************************************************** +// +// The following are values are returned by the USBModeGet function. +// +//***************************************************************************** +#define USB_DUAL_MODE_HOST 0x00000001 // Dual mode controller is in Host + // mode. +#define USB_DUAL_MODE_DEVICE 0x00000081 // Dual mode controller is in + // Device mode. +#define USB_DUAL_MODE_NONE 0x00000080 // Dual mode controller mode is not + // set. +#define USB_OTG_MODE_ASIDE_HOST 0x0000001d // OTG controller on the A side of + // the cable. +#define USB_OTG_MODE_ASIDE_NPWR 0x00000001 // OTG controller on the A side of + // the cable. +#define USB_OTG_MODE_ASIDE_SESS 0x00000009 // OTG controller on the A side of + // the cable Session Valid. +#define USB_OTG_MODE_ASIDE_AVAL 0x00000011 // OTG controller on the A side of + // the cable A valid. +#define USB_OTG_MODE_ASIDE_DEV 0x00000019 // OTG controller on the A side of + // the cable. +#define USB_OTG_MODE_BSIDE_HOST 0x0000009d // OTG controller on the B side of + // the cable. +#define USB_OTG_MODE_BSIDE_DEV 0x00000099 // OTG controller on the B side of + // the cable. +#define USB_OTG_MODE_BSIDE_NPWR 0x00000081 // OTG controller on the B side of + // the cable. +#define USB_OTG_MODE_NONE 0x00000080 // OTG controller mode is not set. + +//***************************************************************************** +// +// The values for the USBDMAChannelIntEnable() and USBDMAChannelIntStatus() +// APIs. +// +//***************************************************************************** +#define USB_DMA_INT_CH8 0x00000080 +#define USB_DMA_INT_CH7 0x00000040 +#define USB_DMA_INT_CH6 0x00000020 +#define USB_DMA_INT_CH5 0x00000010 +#define USB_DMA_INT_CH4 0x00000008 +#define USB_DMA_INT_CH3 0x00000004 +#define USB_DMA_INT_CH2 0x00000002 +#define USB_DMA_INT_CH1 0x00000001 + +//***************************************************************************** +// +// The values for the USBDMAChannelStatus() API. +// +//***************************************************************************** +#define USB_DMA_STATUS_ERROR 0x00000100 + +//***************************************************************************** +// +// The valid return values for the USBDMAModeSet() and USBDMAModeGet() APIs or +// USBDMAChannelConfig(). +// +//***************************************************************************** +#define USB_DMA_CFG_BURST_NONE 0x00000000 +#define USB_DMA_CFG_BURST_4 0x00000200 +#define USB_DMA_CFG_BURST_8 0x00000400 +#define USB_DMA_CFG_BURST_16 0x00000600 +#define USB_DMA_CFG_INT_EN 0x00000008 +#define USB_DMA_CFG_MODE_0 0x00000000 +#define USB_DMA_CFG_MODE_1 0x00000004 +#define USB_DMA_CFG_DIR_RX 0x00000000 +#define USB_DMA_CFG_DIR_TX 0x00000002 +#define USB_DMA_CFG_EN 0x00000001 + +//***************************************************************************** +// +// The following are values that can be passed to USBModeConfig() as the +// ui3Mode parameter. +// +//***************************************************************************** +#define USB_MODE_HOST_VBUS 0x00000004 +#define USB_MODE_HOST 0x00000002 +#define USB_MODE_DEV_VBUS 0x00000005 +#define USB_MODE_DEV 0x00000003 +#define USB_MODE_OTG 0x00000000 + +#define FIFO_TX 0 +#define FIFO_RX 1 +#define FIFO_TXRX 2 + +struct musb_fifo_cfg { + uint8_t ep_num; + uint8_t style; + uint8_t mode; + uint32_t maxpacket; +}; + +uint8_t usbd_get_musb_fifo_cfg(struct musb_fifo_cfg **cfg); +uint8_t usbh_get_musb_fifo_cfg(struct musb_fifo_cfg **cfg); +uint32_t usb_get_musb_ram_size(void); +void usbd_musb_delay_ms(uint8_t ms); + +#endif diff --git a/kernel/cherryusb/port/nuvoton/README.md b/kernel/cherryusb/port/nuvoton/README.md new file mode 100644 index 0000000..ae879f7 --- /dev/null +++ b/kernel/cherryusb/port/nuvoton/README.md @@ -0,0 +1,6 @@ +# Note + +## Support Chip List + +- M032 Series +- M480 Series diff --git a/kernel/cherryusb/port/nuvoton/usb_dc_usbfs.c b/kernel/cherryusb/port/nuvoton/usb_dc_usbfs.c new file mode 100644 index 0000000..ca2b602 --- /dev/null +++ b/kernel/cherryusb/port/nuvoton/usb_dc_usbfs.c @@ -0,0 +1,455 @@ +#include +#include "NuMicro.h" +#include "usbd_core.h" + +#ifndef USBD_EPNUM +#define USBD_EPNUM 8 +#endif +#define USB_NUM_BIDIR_ENDPOINTS (USBD_EPNUM >> 1) + +#define USBD_EP_GET_CONFIG(ep) (*((__IO uint32_t *)((uint32_t)&USBD->EP[0].CFG + (uint32_t)((ep) << 4)))) + +/* Define EP maximum packet size */ +#define DEFAULT_EP_MAX_PKT_SIZE 64 + +#define EP0_MAX_PKT_SIZE DEFAULT_EP_MAX_PKT_SIZE +#define EP1_MAX_PKT_SIZE DEFAULT_EP_MAX_PKT_SIZE +#define EP2_MAX_PKT_SIZE DEFAULT_EP_MAX_PKT_SIZE +#define EP3_MAX_PKT_SIZE DEFAULT_EP_MAX_PKT_SIZE +#define EP4_MAX_PKT_SIZE DEFAULT_EP_MAX_PKT_SIZE +#define EP5_MAX_PKT_SIZE DEFAULT_EP_MAX_PKT_SIZE +#define EP6_MAX_PKT_SIZE DEFAULT_EP_MAX_PKT_SIZE +#define EP7_MAX_PKT_SIZE DEFAULT_EP_MAX_PKT_SIZE +#define EP8_MAX_PKT_SIZE DEFAULT_EP_MAX_PKT_SIZE +#define EP9_MAX_PKT_SIZE DEFAULT_EP_MAX_PKT_SIZE +#define EP10_MAX_PKT_SIZE DEFAULT_EP_MAX_PKT_SIZE +#define EP11_MAX_PKT_SIZE DEFAULT_EP_MAX_PKT_SIZE + +#define SETUP_BUF_BASE 0 +#define SETUP_BUF_LEN 8 +#define EP0_BUF_BASE (SETUP_BUF_BASE + SETUP_BUF_LEN) +#define EP0_BUF_LEN EP0_MAX_PKT_SIZE +#define EP1_BUF_BASE (SETUP_BUF_BASE + SETUP_BUF_LEN) +#define EP1_BUF_LEN EP1_MAX_PKT_SIZE +#define EP2_BUF_BASE (EP1_BUF_BASE + EP1_BUF_LEN) +#define EP2_BUF_LEN EP2_MAX_PKT_SIZE +#define EP3_BUF_BASE (EP2_BUF_BASE + EP2_BUF_LEN) +#define EP3_BUF_LEN EP3_MAX_PKT_SIZE +#define EP4_BUF_BASE (EP3_BUF_BASE + EP3_BUF_LEN) +#define EP4_BUF_LEN EP4_MAX_PKT_SIZE +#define EP5_BUF_BASE (EP4_BUF_BASE + EP4_BUF_LEN) +#define EP5_BUF_LEN EP5_MAX_PKT_SIZE +#if USBD_EPNUM >= 8 +#define EP6_BUF_BASE (EP5_BUF_BASE + EP5_BUF_LEN) +#define EP6_BUF_LEN EP6_MAX_PKT_SIZE +#define EP7_BUF_BASE (EP6_BUF_BASE + EP6_BUF_LEN) +#define EP7_BUF_LEN EP7_MAX_PKT_SIZE +#if USBD_EPNUM >= 10 +#define EP8_BUF_BASE (EP7_BUF_BASE + EP7_BUF_LEN) +#define EP8_BUF_LEN EP8_MAX_PKT_SIZE +#define EP9_BUF_BASE (EP8_BUF_BASE + EP8_BUF_LEN) +#define EP9_BUF_LEN EP9_MAX_PKT_SIZE +#if USBD_EPNUM >= 12 +#define EP10_BUF_BASE (EP9_BUF_BASE + EP9_BUF_LEN) +#define EP10_BUF_LEN EP10_MAX_PKT_SIZE +#define EP11_BUF_BASE (EP10_BUF_BASE + EP10_BUF_LEN) +#define EP11_BUF_LEN EP11_MAX_PKT_SIZE +#endif +#endif +#endif + +#define USBD_EPNUM_FROM_IN_EPIDX(ep_idx) ((ep_idx) << 1) +#define USBD_EPNUM_FROM_OUT_EPIDX(ep_idx) (((ep_idx) << 1) + 1) +#define USBD_EPNUM_FROM_EPADDR(ep_addr) \ + (USB_EP_DIR_IS_IN(ep_addr) ? USBD_EPNUM_FROM_IN_EPIDX(USB_EP_GET_IDX(ep_addr)) : USBD_EPNUM_FROM_OUT_EPIDX(USB_EP_GET_IDX(ep_addr))) + +/* Endpoint state */ +struct usb_dc_ep_state { + uint16_t ep_mps; /* Endpoint max packet size */ + uint8_t ep_type; /* Endpoint type */ + uint8_t ep_stalled; /* Endpoint stall flag */ + uint8_t ep_enable; /* Endpoint enable */ + uint8_t *xfer_buf; + uint32_t xfer_len; + uint32_t actual_xfer_len; + uint32_t mps_xfer_len; +}; + +/* Driver state */ +struct usb_dc_config_priv { + volatile uint8_t dev_addr; + struct usb_dc_ep_state in_ep[USB_NUM_BIDIR_ENDPOINTS]; /*!< IN endpoint parameters*/ + struct usb_dc_ep_state out_ep[USB_NUM_BIDIR_ENDPOINTS]; /*!< OUT endpoint parameters */ +} g_nuvoton_udc; + +static uint8_t usbd_set_address_flag = 0; +static uint8_t usbd_out_toggle[USB_NUM_BIDIR_ENDPOINTS] = { 0 }; + +__WEAK void usb_dc_low_level_init(void) +{ +} + +__WEAK void usb_dc_low_level_deinit(void) +{ +} + +int usb_dc_init(uint8_t busid) +{ + memset(&g_nuvoton_udc, 0, sizeof(g_nuvoton_udc)); + + usb_dc_low_level_init(); + + /*****************************************************/ + /* Initial USB engine */ + USBD->ATTR = 0x6D0ul; + /* Force SE0 */ + USBD_SET_SE0(); + + /*****************************************************/ + /* Init setup packet buffer */ + /* Buffer for setup packet -> [0 ~ 0x7] */ + USBD->STBUFSEG = SETUP_BUF_BASE; + + USBD_SET_EP_BUF_ADDR(EP0, EP0_BUF_BASE); + USBD_SET_EP_BUF_ADDR(EP1, EP1_BUF_BASE); + USBD_SET_EP_BUF_ADDR(EP2, EP2_BUF_BASE); + USBD_SET_EP_BUF_ADDR(EP3, EP3_BUF_BASE); + USBD_SET_EP_BUF_ADDR(EP4, EP4_BUF_BASE); + USBD_SET_EP_BUF_ADDR(EP5, EP5_BUF_BASE); +#if USBD_EPNUM >= 8 + USBD_SET_EP_BUF_ADDR(EP6, EP6_BUF_BASE); + USBD_SET_EP_BUF_ADDR(EP7, EP7_BUF_BASE); +#if USBD_EPNUM >= 10 + USBD_SET_EP_BUF_ADDR(EP8, EP8_BUF_BASE); + USBD_SET_EP_BUF_ADDR(EP9, EP9_BUF_BASE); + USBD_SET_EP_BUF_ADDR(EP10, EP10_BUF_BASE); +#if USBD_EPNUM >= 12 + USBD_SET_EP_BUF_ADDR(EP11, EP11_BUF_BASE); +#endif +#endif +#endif + + /*****************************************************/ + /* USB start */ + /* Disable software-disconnect function */ + USBD_CLR_SE0(); + USBD->ATTR = 0x7D0ul; + + /* Clear USB-related interrupts before enable interrupt */ + USBD_CLR_INT_FLAG(USBD_INT_BUS | USBD_INT_USB | USBD_INT_FLDET | USBD_INT_WAKEUP); + + /* Enable USB-related interrupts. */ + USBD_ENABLE_INT(USBD_INT_BUS | USBD_INT_USB | USBD_INT_FLDET | USBD_INT_WAKEUP); + /*****************************************************/ + + return 0; +} + +int usb_dc_deinit(uint8_t busid) +{ + USBD->ATTR = 0x00000040; + /* Force SE0 */ + USBD_SET_SE0(); + + return 0; +} + +int usbd_set_address(uint8_t busid, const uint8_t addr) +{ + uint8_t usbd_addr = USBD_GET_ADDR(); + if ((usbd_addr == 0) && (usbd_addr != addr)) { + g_nuvoton_udc.dev_addr = addr; + usbd_set_address_flag = 1; + } + + return 0; +} + +int usbd_set_remote_wakeup(uint8_t busid) +{ + return -1; +} + +uint8_t usbd_get_port_speed(uint8_t busid) +{ + return USB_SPEED_FULL; +} + +int usbd_ep_open(uint8_t busid, const struct usb_endpoint_descriptor *ep) +{ + uint8_t ep_idx = USB_EP_GET_IDX(ep->bEndpointAddress); + + if (USB_EP_DIR_IS_IN(ep->bEndpointAddress)) { + uint8_t epnum = USBD_EPNUM_FROM_IN_EPIDX(ep_idx); + + g_nuvoton_udc.in_ep[ep_idx].ep_mps = USB_GET_MAXPACKETSIZE(ep->wMaxPacketSize); + g_nuvoton_udc.in_ep[ep_idx].ep_type = USB_GET_ENDPOINT_TYPE(ep->bmAttributes); + g_nuvoton_udc.in_ep[ep_idx].ep_enable = true; + if (ep_idx == 0) { + /* EP0 ==> control IN endpoint, address 0 */ + USBD_CONFIG_EP(EP0, USBD_CFG_CSTALL | USBD_CFG_EPMODE_IN | 0); + } else { + USBD_CONFIG_EP(epnum, USBD_CFG_EPMODE_IN | ep_idx); + USBD_STOP_TRANSACTION(epnum); + } + } else { + uint8_t epnum = USBD_EPNUM_FROM_OUT_EPIDX(ep_idx); + + g_nuvoton_udc.out_ep[ep_idx].ep_mps = USB_GET_MAXPACKETSIZE(ep->wMaxPacketSize); + g_nuvoton_udc.out_ep[ep_idx].ep_type = USB_GET_ENDPOINT_TYPE(ep->bmAttributes); + g_nuvoton_udc.out_ep[ep_idx].ep_enable = true; + if (ep_idx == 0) { + /* EP1 ==> control OUT endpoint, address 0 */ + USBD_CONFIG_EP(EP1, USBD_CFG_CSTALL | USBD_CFG_EPMODE_OUT | 0); + } else { + USBD_CONFIG_EP(epnum, USBD_CFG_EPMODE_OUT | ep_idx); + USBD_STOP_TRANSACTION(epnum); + } + } + + return 0; +} + +int usbd_ep_close(uint8_t busid, const uint8_t ep) +{ + USBD->EP[USBD_EPNUM_FROM_EPADDR(ep)].CFG &= ~USBD_CFG_STATE_Msk; // disable endpoint + return 0; +} + +int usbd_ep_set_stall(uint8_t busid, const uint8_t ep) +{ + USBD_SET_EP_STALL(USBD_EPNUM_FROM_EPADDR(ep)); + return 0; +} + +int usbd_ep_clear_stall(uint8_t busid, const uint8_t ep) +{ + USBD_CLR_EP_STALL(USBD_EPNUM_FROM_EPADDR(ep)); + return 0; +} + +int usbd_ep_is_stalled(uint8_t busid, const uint8_t ep, uint8_t *stalled) +{ + *stalled = USBD_GET_EP_STALL(USBD_EPNUM_FROM_EPADDR(ep)) > 0 ? 1 : 0; + return 0; +} + +int usbd_ep_start_write(uint8_t busid, const uint8_t ep, const uint8_t *data, uint32_t data_len) +{ + uint8_t ep_idx = USB_EP_GET_IDX(ep); + + if (!data && data_len) { + return -1; + } + if (!g_nuvoton_udc.in_ep[ep_idx].ep_enable) { + return -2; + } + + uint8_t epnum = USBD_EPNUM_FROM_IN_EPIDX(ep); + + g_nuvoton_udc.in_ep[ep_idx].xfer_buf = (uint8_t *)data; + g_nuvoton_udc.in_ep[ep_idx].xfer_len = data_len; + g_nuvoton_udc.in_ep[ep_idx].actual_xfer_len = 0; + + if (data_len > g_nuvoton_udc.in_ep[ep_idx].ep_mps) { + data_len = g_nuvoton_udc.in_ep[ep_idx].ep_mps; + } + + if (epnum == 0) { + USBD_SET_DATA1(epnum); + } + + USBD_MemCopy((uint8_t *)(USBD_BUF_BASE + USBD_GET_EP_BUF_ADDR(epnum)), (uint8_t *)data, data_len); + USBD_SET_PAYLOAD_LEN(epnum, data_len); + + return 0; +} + +int usbd_ep_start_read(uint8_t busid, const uint8_t ep, uint8_t *data, uint32_t data_len) +{ + uint8_t ep_idx = USB_EP_GET_IDX(ep); + + if (!data && data_len) { + return -1; + } + if (!g_nuvoton_udc.out_ep[ep_idx].ep_enable) { + return -2; + } + + uint8_t epnum = USBD_EPNUM_FROM_OUT_EPIDX(ep); + + g_nuvoton_udc.out_ep[ep_idx].xfer_buf = (uint8_t *)data; + g_nuvoton_udc.out_ep[ep_idx].xfer_len = data_len; + g_nuvoton_udc.out_ep[ep_idx].actual_xfer_len = 0; + + if (g_nuvoton_udc.out_ep[ep_idx].xfer_len < g_nuvoton_udc.out_ep[ep_idx].ep_mps) { + g_nuvoton_udc.out_ep[ep_idx].mps_xfer_len = g_nuvoton_udc.out_ep[ep_idx].xfer_len; + } else { + g_nuvoton_udc.out_ep[ep_idx].mps_xfer_len = g_nuvoton_udc.out_ep[ep_idx].ep_mps; + } + + USBD_SET_PAYLOAD_LEN(epnum, g_nuvoton_udc.out_ep[ep_idx].mps_xfer_len); + + return 0; +} + +void USBD_IRQHandler(uint8_t busid) +{ + uint32_t int_flag = USBD_GET_INT_FLAG(); + uint32_t bus_state = USBD_GET_BUS_STATE(); + + if (int_flag & USBD_INTSTS_FLDET) { + // Floating detect + USBD_CLR_INT_FLAG(USBD_INTSTS_FLDET); + + if (USBD_IS_ATTACHED()) { + /* USB Plug In */ + USBD_ENABLE_USB(); + usbd_event_connect_handler(0); + } else { + /* USB Un-plug */ + USBD_DISABLE_USB(); + usbd_event_disconnect_handler(0); + } + } + + //------------------------------------------------------------------ + if (int_flag & USBD_INTSTS_BUS) { + /* Clear event flag */ + USBD_CLR_INT_FLAG(USBD_INTSTS_BUS); + + if (bus_state & USBD_STATE_USBRST) { + /* Bus reset */ + USBD_ENABLE_USB(); + + memset((usbd_out_toggle + 1), 0, (USB_NUM_BIDIR_ENDPOINTS - 1)); + + for (uint8_t i = 0; i < USBD_MAX_EP; i++) { + USBD->EP[i].CFG = 0; // default value + } + + USBD_SET_ADDR(0ul); + g_nuvoton_udc.dev_addr = 0; + + usbd_event_reset_handler(0); + } + + if (bus_state & USBD_STATE_SUSPEND) { + /* Enable USB but disable PHY */ + USBD_DISABLE_PHY(); + usbd_event_suspend_handler(0); + } + if (bus_state & USBD_STATE_RESUME) { + /* Enable USB and enable PHY */ + USBD_ENABLE_USB(); + usbd_event_resume_handler(0); + } + } + + //------------------------------------------------------------------ + if (int_flag & USBD_INTSTS_WAKEUP) { + /* Clear event flag */ + USBD_CLR_INT_FLAG(USBD_INTSTS_WAKEUP); + } + + if (int_flag & USBD_INTSTS_USB) { + // USB event + if (int_flag & USBD_INTSTS_SETUP) { + // Setup packet + /* Clear event flag */ + USBD_CLR_INT_FLAG(USBD_INTSTS_SETUP); + + /* Clear the data IN/OUT ready flag of control end-points */ + USBD_STOP_TRANSACTION(EP0); + USBD_STOP_TRANSACTION(EP1); + + usbd_out_toggle[0] = 0; + usbd_event_ep0_setup_complete_handler(0, (uint8_t *)(USBD_BUF_BASE)); + } + + if (int_flag & USBD_INTSTS_EP0) { + /* In ACK for Set address */ + if (usbd_set_address_flag == 1) { + USBD_SET_ADDR(g_nuvoton_udc.dev_addr); + usbd_set_address_flag = 0; + } + } + + // if (int_flag & USBD_INTSTS_EP1) + // { + // } + + for (uint8_t epnum = 0; epnum < USBD_EPNUM; epnum++) { + if (int_flag & (USBD_INTSTS_EP0 << epnum)) { + USBD_CLR_INT_FLAG((USBD_INTSTS_EP0 << epnum)); + + uint8_t ep_cfg = USBD_EP_GET_CONFIG(epnum); + + uint8_t ep_state = 0; +#if USBD_EPNUM >= 10 + if (epnum > 7) { + ep_state = (USBD->EPSTS1 >> ((epnum - 8) * 4)) & 0x0f; + } else +#endif + { + ep_state = (USBD->EPSTS0 >> (epnum * 4)) & 0x0f; + } + + uint8_t ep_cfg_state = (ep_cfg & USBD_CFG_STATE_Msk) >> USBD_CFG_STATE_Pos; + + if (ep_cfg_state == 0x01) { + // OUT + uint8_t ep_idx = ep_cfg & USBD_CFG_EPNUM_Msk; + + if (ep_state == usbd_out_toggle[ep_idx]) { + USBD_SET_PAYLOAD_LEN(epnum, g_nuvoton_udc.out_ep[ep_idx].ep_mps); + } else { + uint32_t recv_count = USBD_GET_PAYLOAD_LEN(epnum); + + USBD_MemCopy((uint8_t *)g_nuvoton_udc.out_ep[ep_idx].xfer_buf, + (uint8_t *)(USBD_BUF_BASE + USBD_GET_EP_BUF_ADDR(epnum)), recv_count); + + g_nuvoton_udc.out_ep[ep_idx].xfer_buf += recv_count; + g_nuvoton_udc.out_ep[ep_idx].xfer_len -= recv_count; + g_nuvoton_udc.out_ep[ep_idx].actual_xfer_len += recv_count; + + usbd_out_toggle[ep_idx] = ep_state; + + if ((recv_count < g_nuvoton_udc.out_ep[ep_idx].ep_mps) || + (g_nuvoton_udc.out_ep[ep_idx].xfer_len == 0)) { + usbd_event_ep_out_complete_handler(0, ep_idx, g_nuvoton_udc.out_ep[ep_idx].actual_xfer_len); + } else { + if (g_nuvoton_udc.out_ep[ep_idx].xfer_len < g_nuvoton_udc.out_ep[ep_idx].ep_mps) { + g_nuvoton_udc.out_ep[ep_idx].mps_xfer_len = g_nuvoton_udc.out_ep[ep_idx].xfer_len; + } else { + g_nuvoton_udc.out_ep[ep_idx].mps_xfer_len = g_nuvoton_udc.out_ep[ep_idx].ep_mps; + } + + USBD_SET_PAYLOAD_LEN(epnum, g_nuvoton_udc.out_ep[ep_idx].mps_xfer_len); + } + } + } else if (ep_cfg_state == 0x02) { + uint8_t ep_idx = ep_cfg & USBD_CFG_EPNUM_Msk; + // In Ack + + if (g_nuvoton_udc.in_ep[ep_idx].xfer_len > g_nuvoton_udc.in_ep[ep_idx].ep_mps) { + g_nuvoton_udc.in_ep[ep_idx].xfer_buf += g_nuvoton_udc.in_ep[ep_idx].ep_mps; + g_nuvoton_udc.in_ep[ep_idx].xfer_len -= g_nuvoton_udc.in_ep[ep_idx].ep_mps; + g_nuvoton_udc.in_ep[ep_idx].actual_xfer_len += g_nuvoton_udc.in_ep[ep_idx].ep_mps; + + uint16_t min_len = MIN(g_nuvoton_udc.in_ep[ep_idx].xfer_len, g_nuvoton_udc.in_ep[ep_idx].ep_mps); + + uint8_t *usbd_ep_buf_addr = (uint8_t *)(USBD_BUF_BASE + USBD_GET_EP_BUF_ADDR(epnum)); + USBD_MemCopy(usbd_ep_buf_addr, g_nuvoton_udc.in_ep[ep_idx].xfer_buf, min_len); + USBD_SET_PAYLOAD_LEN(epnum, min_len); + } else { + g_nuvoton_udc.in_ep[ep_idx].actual_xfer_len += g_nuvoton_udc.in_ep[ep_idx].xfer_len; + g_nuvoton_udc.in_ep[ep_idx].xfer_len = 0; + + usbd_event_ep_in_complete_handler(0, ep_idx | 0x80, g_nuvoton_udc.in_ep[ep_idx].actual_xfer_len); + } + } + } + } + } +} diff --git a/kernel/cherryusb/port/nxp/README.md b/kernel/cherryusb/port/nxp/README.md new file mode 100644 index 0000000..c7d9566 --- /dev/null +++ b/kernel/cherryusb/port/nxp/README.md @@ -0,0 +1,17 @@ +# Note + +## Support Chip List + +### MCX + +Modify USB_NOCACHE_RAM_SECTION + +``` +#define USB_NOCACHE_RAM_SECTION __attribute__((section(".NonCacheable"))) +``` + +- MCXN9XX/MCXN236 (chipidea + EHCI) + +### IMRT + +- IMRT10XX/IMRT11XX (chipidea + EHCI) \ No newline at end of file diff --git a/kernel/cherryusb/port/nxp/usb_glue_mcx.c b/kernel/cherryusb/port/nxp/usb_glue_mcx.c new file mode 100644 index 0000000..66f2cbe --- /dev/null +++ b/kernel/cherryusb/port/nxp/usb_glue_mcx.c @@ -0,0 +1,449 @@ +/* + * Copyright (c) 2024 ~ 2025, sakumisu + * + * SPDX-License-Identifier: Apache-2.0 + */ +#include "usbd_core.h" +#include "usbh_core.h" +#include "fsl_common.h" +#include "fsl_cache.h" +#include "usb_chipidea_reg.h" + +__WEAK void USBD_IRQHandler(uint8_t busid) +{ +} + +__WEAK void USBH_IRQHandler(uint8_t busid) +{ +} + +#if !defined(CONFIG_USB_EHCI_NXP) +#error "mcx ehci must config CONFIG_USB_EHCI_NXP" +#endif + +#if !defined(CONFIG_USB_EHCI_HCCR_OFFSET) || CONFIG_USB_EHCI_HCCR_OFFSET != 0x100 +#error "mcx ehci must config CONFIG_USB_EHCI_HCCR_OFFSET to 0x100" +#endif + +#define USB_DEVICE_CONFIG_EHCI 1 + +/*! @brief USB controller ID */ +typedef enum _usb_controller_index { + kUSB_ControllerKhci0 = 0U, /*!< KHCI 0U */ + kUSB_ControllerKhci1 = 1U, /*!< KHCI 1U, Currently, there are no platforms which have two KHCI IPs, this is reserved + to be used in the future. */ + kUSB_ControllerEhci0 = 2U, /*!< EHCI 0U */ + kUSB_ControllerEhci1 = 3U, /*!< EHCI 1U, Currently, there are no platforms which have two EHCI IPs, this is reserved + to be used in the future. */ + + kUSB_ControllerLpcIp3511Fs0 = 4U, /*!< LPC USB IP3511 FS controller 0 */ + kUSB_ControllerLpcIp3511Fs1 = 5U, /*!< LPC USB IP3511 FS controller 1, there are no platforms which have two IP3511 + IPs, this is reserved to be used in the future. */ + + kUSB_ControllerLpcIp3511Hs0 = 6U, /*!< LPC USB IP3511 HS controller 0 */ + kUSB_ControllerLpcIp3511Hs1 = 7U, /*!< LPC USB IP3511 HS controller 1, there are no platforms which have two IP3511 + IPs, this is reserved to be used in the future. */ + + kUSB_ControllerOhci0 = 8U, /*!< OHCI 0U */ + kUSB_ControllerOhci1 = 9U, /*!< OHCI 1U, Currently, there are no platforms which have two OHCI IPs, this is reserved + to be used in the future. */ + + kUSB_ControllerIp3516Hs0 = 10U, /*!< IP3516HS 0U */ + kUSB_ControllerIp3516Hs1 = 11U, /*!< IP3516HS 1U, Currently, there are no platforms which have two IP3516HS IPs, + this is reserved to be used in the future. */ + kUSB_ControllerDwc30 = 12U, /*!< DWC3 0U */ + kUSB_ControllerDwc31 = 13U, /*!< DWC3 1U Currently, there are no platforms which have two Dwc IPs, this is reserved + to be used in the future.*/ +} usb_controller_index_t; + +/* USB PHY condfiguration */ +#define BOARD_USB_PHY_D_CAL (0x04U) +#define BOARD_USB_PHY_TXCAL45DP (0x07U) +#define BOARD_USB_PHY_TXCAL45DM (0x07U) +#define BOARD_XTAL0_CLK_HZ 24000000U /*!< Board xtal0 frequency in Hz */ + +typedef struct _usb_phy_config_struct { + uint8_t D_CAL; /* Decode to trim the nominal 17.78mA current source */ + uint8_t TXCAL45DP; /* Decode to trim the nominal 45-Ohm series termination resistance to the USB_DP output pin */ + uint8_t TXCAL45DM; /* Decode to trim the nominal 45-Ohm series termination resistance to the USB_DM output pin */ +} usb_phy_config_struct_t; + +void *USB_EhciPhyGetBase(uint8_t controllerId) +{ + void *usbPhyBase = NULL; +#if ((defined FSL_FEATURE_SOC_USBPHY_COUNT) && (FSL_FEATURE_SOC_USBPHY_COUNT > 0U)) +#if defined(USBPHY_STACK_BASE_ADDRS) + uint32_t usbphy_base[] = USBPHY_STACK_BASE_ADDRS; +#else + uint32_t usbphy_base[] = USBPHY_BASE_ADDRS; +#endif + uint32_t *temp; + if (controllerId < (uint8_t)kUSB_ControllerEhci0) { + return NULL; + } + + if ((controllerId == (uint8_t)kUSB_ControllerEhci0) || (controllerId == (uint8_t)kUSB_ControllerEhci1)) { + controllerId = controllerId - (uint8_t)kUSB_ControllerEhci0; + } else if ((controllerId == (uint8_t)kUSB_ControllerLpcIp3511Hs0) || + (controllerId == (uint8_t)kUSB_ControllerLpcIp3511Hs1)) { + controllerId = controllerId - (uint8_t)kUSB_ControllerLpcIp3511Hs0; + } else if ((controllerId == (uint8_t)kUSB_ControllerIp3516Hs0) || (controllerId == (uint8_t)kUSB_ControllerIp3516Hs1)) { + controllerId = controllerId - (uint8_t)kUSB_ControllerIp3516Hs0; + } else { + return NULL; + } + + if (controllerId < (sizeof(usbphy_base) / sizeof(usbphy_base[0]))) { + temp = (uint32_t *)usbphy_base[controllerId]; + usbPhyBase = (void *)temp; + } else { + return NULL; + } +#endif + return usbPhyBase; +} + +/*! + * @brief ehci phy initialization. + * + * This function initialize ehci phy IP. + * + * @param[in] controllerId ehci controller id, please reference to #usb_controller_index_t. + * @param[in] freq the external input clock. + * for example: if the external input clock is 16M, the parameter freq should be 16000000. + * + * @retval 0 cancel successfully. + * @retval -1 the freq value is incorrect. + */ +uint32_t USB_EhciPhyInit(uint8_t controllerId, uint32_t freq, usb_phy_config_struct_t *phyConfig) +{ +#if ((defined FSL_FEATURE_SOC_USBPHY_COUNT) && (FSL_FEATURE_SOC_USBPHY_COUNT > 0U)) + USBPHY_Type *usbPhyBase; + + usbPhyBase = (USBPHY_Type *)USB_EhciPhyGetBase(controllerId); + if (NULL == usbPhyBase) { + return (uint8_t)-1; + } + +#if ((defined FSL_FEATURE_SOC_ANATOP_COUNT) && (FSL_FEATURE_SOC_ANATOP_COUNT > 0U)) + ANATOP->HW_ANADIG_REG_3P0.RW = + (ANATOP->HW_ANADIG_REG_3P0.RW & + (~(ANATOP_HW_ANADIG_REG_3P0_OUTPUT_TRG(0x1F) | ANATOP_HW_ANADIG_REG_3P0_ENABLE_ILIMIT_MASK))) | + ANATOP_HW_ANADIG_REG_3P0_OUTPUT_TRG(0x17) | ANATOP_HW_ANADIG_REG_3P0_ENABLE_LINREG_MASK; + ANATOP->HW_ANADIG_USB2_CHRG_DETECT.SET = + ANATOP_HW_ANADIG_USB2_CHRG_DETECT_CHK_CHRG_B_MASK | ANATOP_HW_ANADIG_USB2_CHRG_DETECT_EN_B_MASK; +#endif + +#if (defined USB_ANALOG) + USB_ANALOG->INSTANCE[controllerId - (uint8_t)kUSB_ControllerEhci0].CHRG_DETECT_SET = + USB_ANALOG_CHRG_DETECT_CHK_CHRG_B(1) | USB_ANALOG_CHRG_DETECT_EN_B(1); +#endif + +#if ((!(defined FSL_FEATURE_SOC_CCM_ANALOG_COUNT)) && (!(defined FSL_FEATURE_SOC_ANATOP_COUNT))) + + usbPhyBase->TRIM_OVERRIDE_EN = 0x001fU; /* override IFR value */ +#endif + usbPhyBase->CTRL |= USBPHY_CTRL_SET_ENUTMILEVEL2_MASK; /* support LS device. */ + usbPhyBase->CTRL |= USBPHY_CTRL_SET_ENUTMILEVEL3_MASK; /* support external FS Hub with LS device connected. */ + /* PWD register provides overall control of the PHY power state */ + usbPhyBase->PWD = 0U; + if (((uint8_t)kUSB_ControllerIp3516Hs0 == controllerId) || ((uint8_t)kUSB_ControllerIp3516Hs1 == controllerId) || + ((uint8_t)kUSB_ControllerLpcIp3511Hs0 == controllerId) || + ((uint8_t)kUSB_ControllerLpcIp3511Hs1 == controllerId)) { + usbPhyBase->CTRL_SET = USBPHY_CTRL_SET_ENAUTOCLR_CLKGATE_MASK; + usbPhyBase->CTRL_SET = USBPHY_CTRL_SET_ENAUTOCLR_PHY_PWD_MASK; + } + if (NULL != phyConfig) { + /* Decode to trim the nominal 17.78mA current source for the High Speed TX drivers on USB_DP and USB_DM. */ + usbPhyBase->TX = + ((usbPhyBase->TX & (~(USBPHY_TX_D_CAL_MASK | USBPHY_TX_TXCAL45DM_MASK | USBPHY_TX_TXCAL45DP_MASK))) | + (USBPHY_TX_D_CAL(phyConfig->D_CAL) | USBPHY_TX_TXCAL45DP(phyConfig->TXCAL45DP) | + USBPHY_TX_TXCAL45DM(phyConfig->TXCAL45DM))); + } +#endif + + return (uint8_t)0; +} + +/*! + * @brief ehci phy initialization for suspend and resume. + * + * This function initialize ehci phy IP for suspend and resume. + * + * @param[in] controllerId ehci controller id, please reference to #usb_controller_index_t. + * @param[in] freq the external input clock. + * for example: if the external input clock is 16M, the parameter freq should be 16000000. + * + * @retval 0 cancel successfully. + * @retval -1 the freq value is incorrect. + */ +uint32_t USB_EhciLowPowerPhyInit(uint8_t controllerId, uint32_t freq, usb_phy_config_struct_t *phyConfig) +{ +#if ((defined FSL_FEATURE_SOC_USBPHY_COUNT) && (FSL_FEATURE_SOC_USBPHY_COUNT > 0U)) + USBPHY_Type *usbPhyBase; + + usbPhyBase = (USBPHY_Type *)USB_EhciPhyGetBase(controllerId); + if (NULL == usbPhyBase) { + return (uint8_t)-1; + } + +#if ((!(defined FSL_FEATURE_SOC_CCM_ANALOG_COUNT)) && (!(defined FSL_FEATURE_SOC_ANATOP_COUNT))) + usbPhyBase->TRIM_OVERRIDE_EN = 0x001fU; /* override IFR value */ +#endif + +#if ((defined USBPHY_CTRL_AUTORESUME_EN_MASK) && (USBPHY_CTRL_AUTORESUME_EN_MASK > 0U)) + usbPhyBase->CTRL_CLR |= USBPHY_CTRL_AUTORESUME_EN_MASK; +#else + usbPhyBase->CTRL |= USBPHY_CTRL_ENAUTO_PWRON_PLL_MASK; +#endif + usbPhyBase->CTRL |= USBPHY_CTRL_ENAUTOCLR_CLKGATE_MASK | USBPHY_CTRL_ENAUTOCLR_PHY_PWD_MASK; + usbPhyBase->CTRL |= USBPHY_CTRL_SET_ENUTMILEVEL2_MASK; /* support LS device. */ + usbPhyBase->CTRL |= USBPHY_CTRL_SET_ENUTMILEVEL3_MASK; /* support external FS Hub with LS device connected. */ + /* PWD register provides overall control of the PHY power state */ + usbPhyBase->PWD = 0U; +#if (defined USBPHY_ANACTRL_PFD_CLKGATE_MASK) + /* now the 480MHz USB clock is up, then configure fractional divider after PLL with PFD + * pfd clock = 480MHz*18/N, where N=18~35 + * Please note that USB1PFDCLK has to be less than 180MHz for RUN or HSRUN mode + */ + usbPhyBase->ANACTRL |= USBPHY_ANACTRL_PFD_FRAC(24); /* N=24 */ + usbPhyBase->ANACTRL |= USBPHY_ANACTRL_PFD_CLK_SEL(1); /* div by 4 */ + + usbPhyBase->ANACTRL &= ~USBPHY_ANACTRL_DEV_PULLDOWN_MASK; + usbPhyBase->ANACTRL &= ~USBPHY_ANACTRL_PFD_CLKGATE_MASK; + while (0U == (usbPhyBase->ANACTRL & USBPHY_ANACTRL_PFD_STABLE_MASK)) { + } +#endif + if (NULL != phyConfig) { + /* Decode to trim the nominal 17.78mA current source for the High Speed TX drivers on USB_DP and USB_DM. */ + usbPhyBase->TX = + ((usbPhyBase->TX & (~(USBPHY_TX_D_CAL_MASK | USBPHY_TX_TXCAL45DM_MASK | USBPHY_TX_TXCAL45DP_MASK))) | + (USBPHY_TX_D_CAL(phyConfig->D_CAL) | USBPHY_TX_TXCAL45DP(phyConfig->TXCAL45DP) | + USBPHY_TX_TXCAL45DM(phyConfig->TXCAL45DM))); + } +#endif + + return (uint8_t)0; +} + +/*! + * @brief ehci phy de-initialization. + * + * This function de-initialize ehci phy IP. + * + * @param[in] controllerId ehci controller id, please reference to #usb_controller_index_t. + */ +void USB_EhciPhyDeinit(uint8_t controllerId) +{ +#if ((defined FSL_FEATURE_SOC_USBPHY_COUNT) && (FSL_FEATURE_SOC_USBPHY_COUNT > 0U)) + USBPHY_Type *usbPhyBase; + + usbPhyBase = (USBPHY_Type *)USB_EhciPhyGetBase(controllerId); + if (NULL == usbPhyBase) { + return; + } +#if ((!(defined FSL_FEATURE_SOC_CCM_ANALOG_COUNT)) && (!(defined FSL_FEATURE_SOC_ANATOP_COUNT))) + usbPhyBase->PLL_SIC &= ~USBPHY_PLL_SIC_PLL_POWER_MASK; /* power down PLL */ + usbPhyBase->PLL_SIC &= ~USBPHY_PLL_SIC_PLL_EN_USB_CLKS_MASK; /* disable USB clock output from USB PHY PLL */ +#endif + usbPhyBase->CTRL |= USBPHY_CTRL_CLKGATE_MASK; /* set to 1U to gate clocks */ +#endif +} + +/*! + * @brief ehci phy disconnect detection enable or disable. + * + * This function enable/disable host ehci disconnect detection. + * + * @param[in] controllerId ehci controller id, please reference to #usb_controller_index_t. + * @param[in] enable + * 1U - enable; + * 0U - disable; + */ +void USB_EhcihostPhyDisconnectDetectCmd(uint8_t controllerId, uint8_t enable) +{ +#if ((defined FSL_FEATURE_SOC_USBPHY_COUNT) && (FSL_FEATURE_SOC_USBPHY_COUNT > 0U)) + USBPHY_Type *usbPhyBase; + + usbPhyBase = (USBPHY_Type *)USB_EhciPhyGetBase(controllerId); + if (NULL == usbPhyBase) { + return; + } + + if (0U != enable) { + usbPhyBase->CTRL |= USBPHY_CTRL_ENHOSTDISCONDETECT_MASK; + } else { + usbPhyBase->CTRL &= (~USBPHY_CTRL_ENHOSTDISCONDETECT_MASK); + } +#endif +} + +#if ((defined FSL_FEATURE_SOC_USBPHY_COUNT) && (FSL_FEATURE_SOC_USBPHY_COUNT > 0U)) +#if ((defined FSL_FEATURE_USBHSD_HAS_EXIT_HS_ISSUE) && (FSL_FEATURE_USBHSD_HAS_EXIT_HS_ISSUE > 0U)) +void USB_PhyDeviceForceEnterFSMode(uint8_t controllerId, uint8_t enable) +{ + USBPHY_Type *usbPhyBase; + + usbPhyBase = (USBPHY_Type *)USB_EhciPhyGetBase(controllerId); + if (NULL == usbPhyBase) { + return; + } + + if (0U != enable) { + uint32_t delay = 1000000; + usbPhyBase->DEBUG0_CLR = USBPHY_DEBUG0_CLKGATE_MASK; + while ((0U != (usbPhyBase->USB1_VBUS_DET_STAT & USBPHY_USB1_VBUS_DET_STAT_VBUS_VALID_3V_MASK)) && (0U != delay)) { + delay--; + } + usbPhyBase->USB1_LOOPBACK_SET = USBPHY_USB1_LOOPBACK_UTMI_TESTSTART_MASK; + } else { + usbPhyBase->DEBUG0_CLR = USBPHY_DEBUG0_CLKGATE_MASK; + usbPhyBase->USB1_LOOPBACK_CLR = USBPHY_USB1_LOOPBACK_UTMI_TESTSTART_MASK; + } +} +#endif +#endif + +void USB_ClockInit(void) +{ + usb_phy_config_struct_t phyConfig = { + BOARD_USB_PHY_D_CAL, + BOARD_USB_PHY_TXCAL45DP, + BOARD_USB_PHY_TXCAL45DM, + }; + + SPC0->ACTIVE_VDELAY = 0x0500; + /* Change the power DCDC to 1.8v (By deafult, DCDC is 1.8V), CORELDO to 1.1v (By deafult, CORELDO is 1.0V) */ + SPC0->ACTIVE_CFG &= ~SPC_ACTIVE_CFG_CORELDO_VDD_DS_MASK; + SPC0->ACTIVE_CFG |= SPC_ACTIVE_CFG_DCDC_VDD_LVL(0x3) | SPC_ACTIVE_CFG_CORELDO_VDD_LVL(0x3) | + SPC_ACTIVE_CFG_SYSLDO_VDD_DS_MASK | SPC_ACTIVE_CFG_DCDC_VDD_DS(0x2u); + /* Wait until it is done */ + while (SPC0->SC & SPC_SC_BUSY_MASK) + ; + if (0u == (SCG0->LDOCSR & SCG_LDOCSR_LDOEN_MASK)) { + SCG0->TRIM_LOCK = 0x5a5a0001U; + SCG0->LDOCSR |= SCG_LDOCSR_LDOEN_MASK; + /* wait LDO ready */ + while (0U == (SCG0->LDOCSR & SCG_LDOCSR_VOUT_OK_MASK)) + ; + } + SYSCON->AHBCLKCTRLSET[2] |= SYSCON_AHBCLKCTRL2_USB_HS_MASK | SYSCON_AHBCLKCTRL2_USB_HS_PHY_MASK; + SCG0->SOSCCFG &= ~(SCG_SOSCCFG_RANGE_MASK | SCG_SOSCCFG_EREFS_MASK); + /* xtal = 20 ~ 30MHz */ + SCG0->SOSCCFG = (1U << SCG_SOSCCFG_RANGE_SHIFT) | (1U << SCG_SOSCCFG_EREFS_SHIFT); + SCG0->SOSCCSR |= SCG_SOSCCSR_SOSCEN_MASK; + while (1) { + if (SCG0->SOSCCSR & SCG_SOSCCSR_SOSCVLD_MASK) { + break; + } + } + SYSCON->CLOCK_CTRL |= SYSCON_CLOCK_CTRL_CLKIN_ENA_MASK | SYSCON_CLOCK_CTRL_CLKIN_ENA_FM_USBH_LPT_MASK; + CLOCK_EnableClock(kCLOCK_UsbHs); + CLOCK_EnableClock(kCLOCK_UsbHsPhy); + CLOCK_EnableUsbhsPhyPllClock(kCLOCK_Usbphy480M, 24000000U); + CLOCK_EnableUsbhsClock(); + USB_EhciPhyInit(kUSB_ControllerEhci0, BOARD_XTAL0_CLK_HZ, &phyConfig); +} + +void (*g_usb_nxp_irq)(uint8_t busid); + +void usb_dc_low_level_init(uint8_t busid) +{ + USB_ClockInit(); + + g_usb_nxp_irq = USBD_IRQHandler; + + /* Install isr, set priority, and enable IRQ. */ + NVIC_SetPriority((IRQn_Type)USB1_HS_IRQn, 3); + EnableIRQ((IRQn_Type)USB1_HS_IRQn); +} + +void usb_dc_low_level_deinit(uint8_t busid) +{ + DisableIRQ((IRQn_Type)USB1_HS_IRQn); +} + +static void usb_host_mode_init(CHIPIDEA_TypeDef *ptr) +{ + /* Set mode to host, must be set immediately after reset */ + ptr->USBMODE &= ~USB_USBMODE_CM_MASK; + ptr->USBMODE |= USB_USBMODE_CM_SET(3); + + /* Set the endian */ + ptr->USBMODE &= ~USB_USBMODE_ES_MASK; + + /* Set parallel interface signal */ + ptr->PORTSC1 &= ~USB_PORTSC1_STS_MASK; + + /* Set parallel transceiver width */ + ptr->PORTSC1 &= ~USB_PORTSC1_PTW_MASK; + + /* Not use interrupt threshold. */ + ptr->USBCMD &= ~USB_USBCMD_ITC_MASK; +} + +void usb_hc_low_level_init(struct usbh_bus *bus) +{ + USB_ClockInit(); + + g_usb_nxp_irq = USBH_IRQHandler; + + /* Install isr, set priority, and enable IRQ. */ + NVIC_SetPriority((IRQn_Type)USB1_HS_IRQn, 3); + EnableIRQ((IRQn_Type)USB1_HS_IRQn); +} + +void usb_hc_low_level2_init(struct usbh_bus *bus) +{ + usb_host_mode_init((CHIPIDEA_TypeDef *)(bus->hcd.reg_base)); +} + +void usb_hc_low_level_deinit(struct usbh_bus *bus) +{ + DisableIRQ((IRQn_Type)USB1_HS_IRQn); +} + +uint8_t usbh_get_port_speed(struct usbh_bus *bus, const uint8_t port) +{ + (void)port; + uint8_t speed; + + CHIPIDEA_TypeDef *ptr = (CHIPIDEA_TypeDef *)bus->hcd.reg_base; + + speed = USB_PORTSC1_PSPD_GET(ptr->PORTSC1); + + if (speed == 0x00) { + return USB_SPEED_FULL; + } + if (speed == 0x01) { + return USB_SPEED_LOW; + } + if (speed == 0x02) { + USB_EhcihostPhyDisconnectDetectCmd(kUSB_ControllerEhci0, 1); + return USB_SPEED_HIGH; + } + + return 0; +} + +void USB1_HS_IRQHandler(void) +{ + g_usb_nxp_irq(0); +} + +#ifdef CONFIG_USB_DCACHE_ENABLE +void usb_dcache_clean(uintptr_t addr, size_t size) +{ + DCACHE_CleanByRange(addr, size); +} + +void usb_dcache_invalidate(uintptr_t addr, size_t size) +{ + DCACHE_InvalidateByRange(addr, size); +} + +void usb_dcache_flush(uintptr_t addr, size_t size) +{ + DCACHE_CleanInvalidateByRange(addr, size); +} +#endif \ No newline at end of file diff --git a/kernel/cherryusb/port/ohci/README.md b/kernel/cherryusb/port/ohci/README.md new file mode 100644 index 0000000..928eb0c --- /dev/null +++ b/kernel/cherryusb/port/ohci/README.md @@ -0,0 +1,23 @@ +# Note + +This OHCI is a companion controller of EHCI. But you can use OHCI only without CONFIG_USB_EHCI_WITH_OHCI definition. + +**And you need to pay for using OHCI driver**. + +## Support Chip List + +### AllwinnerTech + +- F133(EHCI + OHCI) + +### Nuvoton + +- Nuvoton all series(EHCI + OHCI, OHCI only) + +### Artinchip + +- d13x, d21x(EHCI + OHCI) + +### NXP + +- LPC4X/LPC5X(OHCI only) \ No newline at end of file diff --git a/kernel/cherryusb/port/ohci/usb_glue_lpc.c b/kernel/cherryusb/port/ohci/usb_glue_lpc.c new file mode 100644 index 0000000..51ab781 --- /dev/null +++ b/kernel/cherryusb/port/ohci/usb_glue_lpc.c @@ -0,0 +1,45 @@ +/* + * Copyright (c) 2024, sakumisu + * + * SPDX-License-Identifier: Apache-2.0 + */ +#include "fsl_device_registers.h" +#include "fsl_power.h" +#include "usbh_core.h" + +#if defined(CONFIG_USB_EHCI_WITH_OHCI) +#error "lpc does not have ehci" +#endif + +void usb_hc_low_level_init(struct usbh_bus *bus) +{ +#if ((defined FSL_FEATURE_SOC_SYSMPU_COUNT) && (FSL_FEATURE_SOC_SYSMPU_COUNT)) + SYSMPU_Enable(SYSMPU, 0); +#endif /* FSL_FEATURE_SOC_SYSMPU_COUNT */ + + NVIC_ClearPendingIRQ(USB0_IRQn); + NVIC_ClearPendingIRQ(USB0_NEEDCLK_IRQn); + + POWER_DisablePD(kPDRUNCFG_PD_USB0_PHY); /*< Turn on USB0 Phy */ + + RESET_PeripheralReset(kUSB0D_RST_SHIFT_RSTn); + RESET_PeripheralReset(kUSB0HSL_RST_SHIFT_RSTn); + RESET_PeripheralReset(kUSB0HMR_RST_SHIFT_RSTn); + + CLOCK_EnableUsbfs0HostClock(kCLOCK_UsbfsSrcPll1, 48000000U); + + NVIC_SetPriority(USB0_IRQn, 3); + EnableIRQ(USB0_IRQn); +} + + +void usb_hc_low_level_deinit(struct usbh_bus *bus) +{ + DisableIRQ(USB0_IRQn); +} + +void USB0_IRQHandler(void) +{ + extern void USBH_IRQHandler(uint8_t busid); + USBH_IRQHandler(0); +} \ No newline at end of file diff --git a/kernel/cherryusb/port/ohci/usb_hc_ohci.c b/kernel/cherryusb/port/ohci/usb_hc_ohci.c new file mode 100644 index 0000000..2bec2a0 --- /dev/null +++ b/kernel/cherryusb/port/ohci/usb_hc_ohci.c @@ -0,0 +1,353 @@ +/* + * Copyright (c) 2024, sakumisu + * + * SPDX-License-Identifier: Apache-2.0 + */ +#include "usb_hc_ohci.h" + +/* Frame Interval / Periodic Start. + * + * At 12Mbps, there are 12000 bit time in each 1Msec frame. + */ + +#define OHCI_FMINTERVAL_FI (12000 - 1) +#define OHCI_FMINTERVAL_FSMPS ((6 * (OHCI_FMINTERVAL_FI - 210)) / 7) +#define DEFAULT_FMINTERVAL ((OHCI_FMINTERVAL_FSMPS << OHCI_FMINT_FSMPS_SHIFT) | OHCI_FMINTERVAL_FI) +#define DEFAULT_PERSTART ((OHCI_FMINTERVAL_FI * 9) / 10) + +struct ohci_hcd g_ohci_hcd[CONFIG_USBHOST_MAX_BUS]; + +USB_NOCACHE_RAM_SECTION struct ohci_ed_hw g_ohci_ed_pool[CONFIG_USBHOST_MAX_BUS][CONFIG_USB_OHCI_ED_NUM]; +USB_NOCACHE_RAM_SECTION struct ohci_hcca ohci_hcca[CONFIG_USBHOST_MAX_BUS]; + +int ohci_init(struct usbh_bus *bus) +{ + volatile uint32_t timeout = 0; + uint32_t regval; + struct ohci_ed_hw *ed; + + memset(&g_ohci_hcd[bus->hcd.hcd_id], 0, sizeof(struct ohci_hcd)); + memset(g_ohci_ed_pool[bus->hcd.hcd_id], 0, sizeof(struct ohci_ed_hw) * CONFIG_USB_OHCI_ED_NUM); + + for (uint32_t i = 0; i < 32; i++) { + ohci_hcca[bus->hcd.hcd_id].inttbl[i] = 0; + } + + for (uint8_t index = 0; index < CONFIG_USB_OHCI_ED_NUM; index++) { + ed = &g_ohci_ed_pool[bus->hcd.hcd_id][index]; + if ((uint32_t)&ed->hw % 32) { + USB_LOG_ERR("struct ohci_ed_hw is not align 32\r\n"); + return -USB_ERR_INVAL; + } + for (uint8_t i = 0; i < CONFIG_USB_OHCI_TD_NUM; i++) { + if ((uint32_t)&ed->td_pool[i] % 32) { + USB_LOG_ERR("struct ohci_td_hw is not align 32\r\n"); + return -USB_ERR_INVAL; + } + } + } + + for (uint8_t index = 0; index < CONFIG_USB_OHCI_ED_NUM; index++) { + ed = &g_ohci_ed_pool[bus->hcd.hcd_id][index]; + ed->waitsem = usb_osal_sem_create(0); + } + + USB_LOG_INFO("OHCI hcrevision:0x%02x\r\n", (unsigned int)OHCI_HCOR->hcrevision); + + OHCI_HCOR->hcintdis = OHCI_INT_MIE; + OHCI_HCOR->hccontrol = 0; + + OHCI_HCOR->hccmdsts = OHCI_CMDST_HCR; + while (OHCI_HCOR->hccmdsts & OHCI_CMDST_HCR) { + usb_osal_msleep(1); + timeout++; + if (timeout > 100) { + return -USB_ERR_TIMEOUT; + } + } + + OHCI_HCOR->hcfminterval = DEFAULT_FMINTERVAL; + OHCI_HCOR->hcperiodicstart = DEFAULT_PERSTART; + OHCI_HCOR->hclsthreshold = 0x628; + + OHCI_HCOR->hccontrolheaded = 0; + OHCI_HCOR->hcbulkheaded = 0; + OHCI_HCOR->hchcca = (uintptr_t)&ohci_hcca[bus->hcd.hcd_id]; + + /* Clear pending interrupts */ + regval = OHCI_HCOR->hcintsts; + OHCI_HCOR->hcintsts = regval; + + /* Put HC in operational state */ + regval = OHCI_HCOR->hccontrol; + regval &= ~OHCI_CTRL_CBSR; + regval &= ~OHCI_CTRL_HCFS_MASK; + regval |= OHCI_CTRL_HCFS_OPER; + regval |= OHCI_CTRL_CBSR; + regval |= OHCI_CTRL_CLE; + OHCI_HCOR->hccontrol = regval; + + g_ohci_hcd[bus->hcd.hcd_id].n_ports = OHCI_HCOR->hcrhdescriptora & OHCI_RHDESCA_NDP_MASK; + USB_LOG_INFO("OHCI n_ports:%d\r\n", g_ohci_hcd[bus->hcd.hcd_id].n_ports); + + OHCI_HCOR->hcrhdescriptora &= ~OHCI_RHDESCA_PSM; + OHCI_HCOR->hcrhdescriptora &= ~OHCI_RHDESCA_NPS; + + /* Set global power in HcRhStatus */ + OHCI_HCOR->hcrhsts = OHCI_RHSTATUS_SGP; + usb_osal_msleep(20); + + /* Enable OHCI interrupts */ + OHCI_HCOR->hcinten = OHCI_INT_WDH | OHCI_INT_RHSC | OHCI_INT_MIE; + + return 0; +} + +int ohci_deinit(struct usbh_bus *bus) +{ + uint32_t regval; + struct ohci_ed_hw *ed; + + /* Disable OHCI interrupts */ + OHCI_HCOR->hcintdis = OHCI_INT_WDH | OHCI_INT_RHSC | OHCI_INT_MIE; + + /* Clear pending interrupts */ + regval = OHCI_HCOR->hcintsts; + OHCI_HCOR->hcintsts = regval; + + OHCI_HCOR->hcrhsts &= ~OHCI_RHSTATUS_SGP; + + regval = OHCI_HCOR->hccontrol; + regval &= ~OHCI_CTRL_HCFS_MASK; + regval |= OHCI_CTRL_HCFS_SUSPEND; + OHCI_HCOR->hccontrol = regval; + + for (uint8_t index = 0; index < CONFIG_USB_OHCI_ED_NUM; index++) { + ed = &g_ohci_ed_pool[bus->hcd.hcd_id][index]; + usb_osal_sem_delete(ed->waitsem); + } + + return 0; +} + +uint16_t ohci_get_frame_number(struct usbh_bus *bus) +{ + return OHCI_HCOR->hcfmnumber; +} + +int ohci_roothub_control(struct usbh_bus *bus, struct usb_setup_packet *setup, uint8_t *buf) +{ + uint8_t nports; + uint8_t port; + uint32_t temp; + + nports = g_ohci_hcd[bus->hcd.hcd_id].n_ports; + + port = setup->wIndex; + if (setup->bmRequestType & USB_REQUEST_RECIPIENT_DEVICE) { + switch (setup->bRequest) { + case HUB_REQUEST_CLEAR_FEATURE: + switch (setup->wValue) { + case HUB_FEATURE_HUB_C_LOCALPOWER: + break; + case HUB_FEATURE_HUB_C_OVERCURRENT: + break; + default: + return -USB_ERR_NOTSUPP; + } + break; + case HUB_REQUEST_SET_FEATURE: + switch (setup->wValue) { + case HUB_FEATURE_HUB_C_LOCALPOWER: + break; + case HUB_FEATURE_HUB_C_OVERCURRENT: + break; + default: + return -USB_ERR_NOTSUPP; + } + break; + case HUB_REQUEST_GET_DESCRIPTOR: + break; + case HUB_REQUEST_GET_STATUS: + memset(buf, 0, 4); + break; + default: + break; + } + } else if (setup->bmRequestType & USB_REQUEST_RECIPIENT_OTHER) { + switch (setup->bRequest) { + case HUB_REQUEST_CLEAR_FEATURE: + if (!port || port > nports) { + return -USB_ERR_INVAL; + } + + switch (setup->wValue) { + case HUB_PORT_FEATURE_ENABLE: + temp = OHCI_RHPORTST_CCS; + break; + case HUB_PORT_FEATURE_SUSPEND: + temp = OHCI_HCOR->hccontrol; + temp &= ~OHCI_CTRL_HCFS_MASK; + temp |= OHCI_CTRL_HCFS_RESUME; + OHCI_HCOR->hccontrol = temp; + + usb_osal_msleep(20); + + temp = OHCI_HCOR->hccontrol; + temp &= ~OHCI_CTRL_HCFS_MASK; + temp |= OHCI_CTRL_HCFS_OPER; + OHCI_HCOR->hccontrol = temp; + + temp = OHCI_RHPORTST_POCI; + break; + case HUB_PORT_FEATURE_C_SUSPEND: + temp = OHCI_RHPORTST_PSSC; + break; + case HUB_PORT_FEATURE_POWER: + OHCI_HCOR->hcrhsts = OHCI_RHSTATUS_CGP; + temp = OHCI_RHPORTST_LSDA; + break; + case HUB_PORT_FEATURE_C_CONNECTION: + temp = OHCI_RHPORTST_CSC; + break; + case HUB_PORT_FEATURE_C_ENABLE: + temp = OHCI_RHPORTST_PESC; + break; + case HUB_PORT_FEATURE_C_OVER_CURREN: + temp = OHCI_RHPORTST_OCIC; + break; + case HUB_PORT_FEATURE_C_RESET: + temp = OHCI_RHPORTST_PRSC; + break; + default: + return -USB_ERR_NOTSUPP; + } + OHCI_HCOR->hcrhportsts[port - 1] = temp; + break; + case HUB_REQUEST_SET_FEATURE: + if (!port || port > nports) { + return -USB_ERR_INVAL; + } + + switch (setup->wValue) { + case HUB_PORT_FEATURE_SUSPEND: + temp = OHCI_HCOR->hccontrol; + temp &= ~OHCI_CTRL_HCFS_MASK; + temp |= OHCI_CTRL_HCFS_SUSPEND; + OHCI_HCOR->hccontrol = temp; + + break; + case HUB_PORT_FEATURE_POWER: + OHCI_HCOR->hcrhsts = OHCI_RHSTATUS_SGP; + break; + case HUB_PORT_FEATURE_RESET: + OHCI_HCOR->hcrhportsts[port - 1] = OHCI_RHPORTST_PRS; + + while (OHCI_HCOR->hcrhportsts[port - 1] & OHCI_RHPORTST_PRS) { + } + break; + + default: + return -USB_ERR_NOTSUPP; + } + break; + case HUB_REQUEST_GET_STATUS: + if (!port || port > nports) { + return -USB_ERR_INVAL; + } + temp = OHCI_HCOR->hcrhportsts[port - 1]; + memcpy(buf, &temp, 4); + break; + default: + break; + } + } + return 0; +} + +int ohci_submit_urb(struct usbh_urb *urb) +{ + return -USB_ERR_NOTSUPP; +} + +int ohci_kill_urb(struct usbh_urb *urb) +{ + return -USB_ERR_NOTSUPP; +} + +void OHCI_IRQHandler(uint8_t busid) +{ + uint32_t usbsts; + struct usbh_bus *bus; + + bus = &g_usbhost_bus[busid]; + + usbsts = OHCI_HCOR->hcintsts & OHCI_HCOR->hcinten; + + if (usbsts & OHCI_INT_RHSC) { + OHCI_HCOR->hcintsts = OHCI_INT_RHSC; + for (int port = 0; port < CONFIG_USBHOST_MAX_RHPORTS; port++) { + uint32_t portsc = OHCI_HCOR->hcrhportsts[port]; + + if (portsc & OHCI_RHPORTST_CSC) { + if (OHCI_HCOR->hcrhsts & OHCI_RHSTATUS_DRWE) { + /* If DRWE is set, Connect Status Change indicates a remote wake-up event */ + } else { + if (portsc & OHCI_RHPORTST_CCS) { + } else { + } + bus->hcd.roothub.int_buffer[0] |= (1 << (port + 1)); + usbh_hub_thread_wakeup(&bus->hcd.roothub); + } + } + } + } + if (usbsts & OHCI_INT_WDH) { + OHCI_HCOR->hcintsts = OHCI_INT_WDH; + } +} + +#ifndef CONFIG_USB_EHCI_WITH_OHCI +__WEAK void usb_hc_low_level_init(struct usbh_bus *bus) +{ + (void)bus; +} + +__WEAK void usb_hc_low_level_deinit(struct usbh_bus *bus) +{ + (void)bus; +} + +int usb_hc_init(struct usbh_bus *bus) +{ + usb_hc_low_level_init(bus); + return ohci_init(bus); +} + +int usb_hc_deinit(struct usbh_bus *bus) +{ + ohci_deinit(bus); + usb_hc_low_level_deinit(bus); + return 0; +} + +int usbh_roothub_control(struct usbh_bus *bus, struct usb_setup_packet *setup, uint8_t *buf) +{ + return ohci_roothub_control(bus, setup, buf); +} + +int usbh_submit_urb(struct usbh_urb *urb) +{ + return ohci_submit_urb(urb); +} + +int usbh_kill_urb(struct usbh_urb *urb) +{ + return ohci_kill_urb(urb); +} + +void USBH_IRQHandler(uint8_t busid) +{ + OHCI_IRQHandler(busid); +} +#endif \ No newline at end of file diff --git a/kernel/cherryusb/port/ohci/usb_hc_ohci.h b/kernel/cherryusb/port/ohci/usb_hc_ohci.h new file mode 100644 index 0000000..2cebd63 --- /dev/null +++ b/kernel/cherryusb/port/ohci/usb_hc_ohci.h @@ -0,0 +1,75 @@ +/* + * Copyright (c) 2024, sakumisu + * + * SPDX-License-Identifier: Apache-2.0 + */ +#ifndef _USB_OHCI_PRIV_H +#define _USB_OHCI_PRIV_H + +#include "usbh_core.h" +#include "usbh_hub.h" +#include "usb_ohci_reg.h" + +#define OHCI_HCOR ((struct ohci_hcor *)(uintptr_t)(bus->hcd.reg_base + CONFIG_USB_OHCI_HCOR_OFFSET)) + +#define OHCI_PTR2ADDR(x) ((uint32_t)(uintptr_t)(x) & ~0x0F) +#define OHCI_ADDR2ED(x) ((struct ohci_ed_hw *)(uintptr_t)((uint32_t)(x) & ~0x0F)) +#define OHCI_ADDR2TD(x) ((struct ohci_td_hw *)(uintptr_t)((uint32_t)(x) & ~0x0F)) + +#ifndef CONFIG_USB_OHCI_ED_NUM +#define CONFIG_USB_OHCI_ED_NUM 10 +#endif +#ifndef CONFIG_USB_OHCI_TD_NUM +#define CONFIG_USB_OHCI_TD_NUM 3 +#endif + +#if CONFIG_USB_ALIGN_SIZE <= 32 +#define CONFIG_USB_OHCI_ALIGN_SIZE 32 +#elif CONFIG_USB_ALIGN_SIZE <= 64 +#define CONFIG_USB_OHCI_ALIGN_SIZE 64 +#else +#error "CONFIG_USB_ALIGN_SIZE must be 32 or 64" +#endif + +struct ohci_ed_hw; +struct ohci_td_hw { + struct ohci_gtd hw; +#if defined(CONFIG_USB_OHCI_DESC_DCACHE_ENABLE) && (CONFIG_USB_ALIGN_SIZE == 32) + uint8_t pad[16]; +#elif defined(CONFIG_USB_OHCI_DESC_DCACHE_ENABLE) && (CONFIG_USB_ALIGN_SIZE == 64) + uint8_t pad[48]; +#endif + struct usbh_urb *urb; + bool dir_in; + uint32_t buf_start; + uint32_t length; +} __attribute__((aligned(CONFIG_USB_OHCI_ALIGN_SIZE))); /* min is 16bytes, we use CONFIG_USB_OHCI_ALIGN_SIZE for cacheline */ + +struct ohci_ed_hw { + struct ohci_ed hw; +#if defined(CONFIG_USB_OHCI_DESC_DCACHE_ENABLE) && (CONFIG_USB_ALIGN_SIZE == 32) + uint8_t pad[16]; +#elif defined(CONFIG_USB_OHCI_DESC_DCACHE_ENABLE) && (CONFIG_USB_ALIGN_SIZE == 64) + uint8_t pad[48]; +#endif + struct ohci_td_hw td_pool[CONFIG_USB_OHCI_TD_NUM]; + uint32_t td_count; + uint8_t ed_type; + usb_osal_sem_t waitsem; +} __attribute__((aligned(CONFIG_USB_OHCI_ALIGN_SIZE))); /* min is 16bytes, we use CONFIG_USB_OHCI_ALIGN_SIZE for cacheline */ + +struct ohci_hcd { + bool ohci_ed_used[CONFIG_USB_OHCI_ED_NUM]; + uint8_t n_ports; +}; + +int ohci_init(struct usbh_bus *bus); +int ohci_deinit(struct usbh_bus *bus); +uint16_t ohci_get_frame_number(struct usbh_bus *bus); +int ohci_roothub_control(struct usbh_bus *bus, struct usb_setup_packet *setup, uint8_t *buf); +int ohci_submit_urb(struct usbh_urb *urb); +int ohci_kill_urb(struct usbh_urb *urb); + +void OHCI_IRQHandler(uint8_t busid); + +#endif \ No newline at end of file diff --git a/kernel/cherryusb/port/ohci/usb_ohci_reg.h b/kernel/cherryusb/port/ohci/usb_ohci_reg.h new file mode 100644 index 0000000..61f7f4b --- /dev/null +++ b/kernel/cherryusb/port/ohci/usb_ohci_reg.h @@ -0,0 +1,484 @@ +/**************************************************************************** + * include/nuttx/usb/ohci.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __INCLUDE_NUTTX_USB_OHCI_H +#define __INCLUDE_NUTTX_USB_OHCI_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Register offsets *********************************************************/ + +/* Control and status registers (section 7.1) */ + +#define OHCI_HCIREV_OFFSET 0x0000 /* HcRevision: Version of HCI specification */ +#define OHCI_CTRL_OFFSET 0x0004 /* HcControl: HC control */ +#define OHCI_CMDST_OFFSET 0x0008 /* HcCommandStatus: HC command status */ +#define OHCI_INTST_OFFSET 0x000c /* HcInterruptStatus: HC interrupt status */ +#define OHCI_INTEN_OFFSET 0x0010 /* HcInterruptEnable: HC interrupt enable */ +#define OHCI_INTDIS_OFFSET 0x0014 /* HcInterruptDisable: HC interrupt disable */ + +/* Memory pointer registers (section 7.2) */ + +#define OHCI_HCCA_OFFSET 0x0018 /* HcHCCA: HC communication area */ +#define OHCI_PERED_OFFSET 0x001c /* HcPeriodCurrentED: Current isoc or int endpoint desc */ +#define OHCI_CTRLHEADED_OFFSET 0x0020 /* HcControlHeadED: First EP desc in the control list */ +#define OHCI_CTRLED_OFFSET 0x0024 /* HcControlCurrentED: Current EP desc in the control list */ +#define OHCI_BULKHEADED_OFFSET 0x0028 /* HcBulkHeadED: First EP desc in the bulk list */ +#define OHCI_BULKED_OFFSET 0x002c /* HcBulkCurrentED: Current EP desc in the bulk list */ +#define OHCI_DONEHEAD_OFFSET 0x0030 /* HcDoneHead: Last transfer desc added to DONE queue */ + +/* Frame counter registers (section 7.3) */ + +#define OHCI_FMINT_OFFSET 0x0034 /* HcFmInterval: Bit time interval that would not cause overrun */ +#define OHCI_FMREM_OFFSET 0x0038 /* HcFmRemaining: Bit time remaining in current frame */ +#define OHCI_FMNO_OFFSET 0x003c /* HcFmNumber: Frame number counter */ +#define OHCI_PERSTART_OFFSET 0x0040 /* HcPeriodicStart: Time to start processing periodic list */ + +/* Root hub registers (section 7.4) */ + +#define OHCI_LSTHRES_OFFSET 0x0044 /* HcLSThreshold: Commit to transfer threshold */ +#define OHCI_RHDESCA_OFFSET 0x0048 /* HcRhDescriptorA: Describes root hub (part A) */ +#define OHCI_RHDESCB_OFFSET 0x004c /* HcRhDescriptorB: Describes root hub (part B) */ +#define OHCI_RHSTATUS_OFFSET 0x0050 /* HcRhStatus: Root hub status */ + +#define OHCI_MAX_RHPORT 15 /* Maximum number of OHCI root hub ports */ + +#define OHCI_RHPORTST_OFFSET(n) (0x0054 + (((n) - 1) << 2)) +#define OHCI_RHPORTST1_OFFSET 0x0054 /* HcRhPort1Status: Root hub port status 1 */ +#define OHCI_RHPORTST2_OFFSET 0x0058 /* HcRhPort2Status: Root hub port status 2 */ +#define OHCI_RHPORTST3_OFFSET 0x005c /* HcRhPort3Status: Root hub port status 3 */ +#define OHCI_RHPORTST4_OFFSET 0x0060 /* HcRhPort4Status: Root hub port status 4 */ +#define OHCI_RHPORTST5_OFFSET 0x0064 /* HcRhPort5Status: Root hub port status 5 */ +#define OHCI_RHPORTST6_OFFSET 0x0068 /* HcRhPort6Status: Root hub port status 6 */ +#define OHCI_RHPORTST7_OFFSET 0x006c /* HcRhPort7Status: Root hub port status 7 */ +#define OHCI_RHPORTST8_OFFSET 0x0070 /* HcRhPort8Status: Root hub port status 8 */ +#define OHCI_RHPORTST9_OFFSET 0x0074 /* HcRhPort9Status: Root hub port status 9 */ +#define OHCI_RHPORTST10_OFFSET 0x0078 /* HcRhPort10Status: Root hub port status 10 */ +#define OHCI_RHPORTST11_OFFSET 0x007c /* HcRhPort11Status: Root hub port status 11 */ +#define OHCI_RHPORTST12_OFFSET 0x0080 /* HcRhPort12Status: Root hub port status 12 */ +#define OHCI_RHPORTST13_OFFSET 0x0084 /* HcRhPort13Status: Root hub port status 13 */ +#define OHCI_RHPORTST14_OFFSET 0x0088 /* HcRhPort14Status: Root hub port status 14 */ +#define OHCI_RHPORTST15_OFFSET 0x008c /* HcRhPort15Status: Root hub port status 15 */ + +/* Register bit definitions *************************************************/ + +/* HcRevision: Version of HCI specification (7.1.1) */ + +#define OHCI_HCIREV_SHIFT (0) /* Bits 0-7: HCI spec version (BCD) */ +#define OHCI_HCIREV_MASK (0xff << OHCI_HCIREV_SHIFT) + +/* HcControl: HC control (7.1.2) */ + +#define OHCI_CTRL_CBSR (3 << 0) /* Bit 0: Control/bulk service ratio */ +#define OHCI_CTRL_PLE (1 << 2) /* Bit 2: Periodic list enable */ +#define OHCI_CTRL_IE (1 << 3) /* Bit 3: Isochronous enable */ +#define OHCI_CTRL_CLE (1 << 4) /* Bit 4: Control list enable */ +#define OHCI_CTRL_BLE (1 << 5) /* Bit 5: Bulk list enable */ +#define OHCI_CTRL_HCFS_SHIFT (6) /* Bits 6-7: Host controller functional state */ +#define OHCI_CTRL_HCFS_MASK (3 << OHCI_CTRL_HCFS_SHIFT) +# define OHCI_CTRL_HCFS_RESET (0 << OHCI_CTRL_HCFS_SHIFT) +# define OHCI_CTRL_HCFS_RESUME (1 << OHCI_CTRL_HCFS_SHIFT) +# define OHCI_CTRL_HCFS_OPER (2 << OHCI_CTRL_HCFS_SHIFT) +# define OHCI_CTRL_HCFS_SUSPEND (3 << OHCI_CTRL_HCFS_SHIFT) +#define OHCI_CTRL_IR (1 << 8) /* Bit 8: Interrupt routing */ +#define OHCI_CTRL_RWC (1 << 9) /* Bit 9: Remote wakeup connected */ +#define OHCI_CTRL_RWE (1 << 10) /* Bit 10: Remote wakeup enable */ + /* Bits 11-31: Reserved */ + +/* HcCommandStatus: HC command status (7.1.3) */ + +#define OHCI_CMDST_HCR (1 << 0) /* Bit 0: Host controller reset */ +#define OHCI_CMDST_CLF (1 << 1) /* Bit 1: Control list filled */ +#define OHCI_CMDST_BLF (1 << 2) /* Bit 2: Bulk list filled */ +#define OHCI_CMDST_OCR (1 << 3) /* Bit 3: Ownership change request */ + /* Bits 4-15: Reserved */ +#define OHCI_CMDST_SOC (3 << 16) /* Bit 16: Scheduling overrun count */ + /* Bits 17-31: Reserved */ + +/* HcInterruptStatus: HC interrupt status (7.1.4), + * HcInterruptEnable: HC interrupt enable (7.1.5), and + * HcInterruptDisable: HC interrupt disable (7.1.6) + */ + +#define OHCI_INT_SO (1 << 0) /* Bit 0: Scheduling overrun */ +#define OHCI_INT_WDH (1 << 1) /* Bit 1: Writeback done head */ +#define OHCI_INT_SF (1 << 2) /* Bit 2: Start of frame */ +#define OHCI_INT_RD (1 << 3) /* Bit 3: Resume detected */ +#define OHCI_INT_UE (1 << 4) /* Bit 4: Unrecoverable error */ +#define OHCI_INT_FNO (1 << 5) /* Bit 5: Frame number overflow */ +#define OHCI_INT_RHSC (1 << 6) /* Bit 6: Root hub status change */ + /* Bits 7-29: Reserved */ +#define OHCI_INT_OC (1 << 30) /* Bit 30: Ownership change */ +#define OHCI_INT_MIE (1 << 31) /* Bit 31: Master interrupt enable + * (Enable/disable only) */ + +/* HcHCCA: HC communication area (7.2.1): + * + * 32-bits aligned to 256 byte boundary. + */ + +/* HcPeriodCurrentED: Current isoc or int endpoint desc (7.2.2), + * HcControlHeadED: First EP desc in the control list (7.2.3), + * HcControlCurrentED: Current EP desc in the control list (7.2.4), + * HcBulkHeadED: First EP desc in the bulk list (7.2.5), + * HcBulkCurrentED: Current EP desc in the bulk list (7.2.6), and + * HcDoneHead: Last transfer desc added to DONE queue (7.2.7): + * + * All 32-bits aligned to an 8-byte boundary + */ + +/* HcFmInterval: Bit time interval that would not cause overrun (7.3.1) */ + +#define OHCI_FMINT_FI_SHIFT (0) /* Bits 0-13: Frame interval */ +#define OHCI_FMINT_FI_MASK (0x3fff << OHCI_FMINT_FI_SHIFT) + /* Bits 14-15: Reserved */ +#define OHCI_FMINT_FSMPS_SHIFT (16) /* Bits 16-30: FS largest packet data */ +#define OHCI_FMINT_FSMPS_MASK (0x7fff << OHCI_FMINT_FSMPS_SHIFT) +#define OHCI_FMINT_FIT (1 << 31) /* Bit 31: Frame interval toggle */ + +/* HcFmRemaining: Bit time remaining in current frame (7.3.2) */ + +#define OHCI_FMREM_FR_SHIFT (0) /* Bits 0-13: Frame remaining */ +#define OHCI_FMREM_FR_MASK (0x3fff << OHCI_FMREM_FR_SHIFT) + /* Bits 16-30: Reserved */ +#define OHCI_FMINT_FRT (1 << 31) /* Bit 31: Frame remaining toggle */ + +/* HcFmNumber: Frame number counter (7.3.3) */ + +#define OHCI_FMNO_FI_SHIFT (0) /* Bits 0-15: Frame number */ +#define OHCI_FMNO_FI_MASK (0xffff << OHCI_FMINT_FI_SHIFT) + /* Bits 16-31: Reserved */ + +/* HcPeriodicStart: Time to start processing periodic list (7.3.4) */ + +#define OHCI_PERSTART_SHIFT (0) /* Bits 0-13: Periodic start */ +#define OHCI_PERSTART_MASK (0x3fff << OHCI_PERSTART_SHIFT) + /* Bits 14-31: Reserved */ + +/* HcLSThreshold: Commit to transfer threshold (7.3.5) */ + +#define OHCI_LSTHRES_SHIFT (0) /* Bits 0-11: LS threshold */ +#define OHCI_LSTHRES_MASK (0x0fff << OHCI_PERSTART_SHIFT) + /* Bits 12-31: Reserved */ + +/* HcRhDescriptorN: Describes root hub (part A) (7.4.1) */ + +#define OHCI_RHDESCA_NDP_SHIFT (0) /* Bits 0-7: Number downstream ports */ +#define OHCI_RHDESCA_NDP_MASK (0xff << OHCI_RHDESCA_NDP_SHIFT) +#define OHCI_RHDESCA_PSM (1 << 8) /* Bit 8: Power switching mode */ +#define OHCI_RHDESCA_NPS (1 << 9) /* Bit 9: No power switching */ +#define OHCI_RHDESCA_DT (1 << 10) /* Bit 10: Device type */ +#define OHCI_RHDESCA_OCPM (1 << 11) /* Bit 11: Over current protection mode */ +#define OHCI_RHDESCA_NOCP (1 << 12) /* Bit 12: No over current protection */ + /* Bits 13-23: Reserved */ +#define OHCI_RHDESCA_POTPGT_SHIFT (24) /* Bits 24-31: Power on to power good time */ +#define OHCI_RHDESCA_POTPGT_MASK (0xff << OHCI_RHDESCA_POTPGT_SHIFT) + +/* HcRhDescriptorB: Describes root hub (part B) (7.4.2) */ + +#define OHCI_RHDESCB_DR_SHIFT (0) /* Bits 0-15: Device removable */ +#define OHCI_RHDESCB_DR_MASK (0xffff << OHCI_RHDESCB_DR_SHIFT) +# define OHCI_RHDESCB_ATTACHED(n) (1 << (OHCI_RHDESCB_DR_SHIFT+(n))) +#define OHCI_RHDESCB_PPCM_SHIFT (16) /* Bits 16-31: Port power control mask */ +#define OHCI_RHDESCB_PPCM_MASK (0xffff << OHCI_RHDESCB_PPCM_SHIFT) +# define OHCI_RHDESCB_POWERED(n) (1 << (OHCI_RHDESCB_DR_SHIFT+(n))) + +/* HcRhStatus: Root hub status (7.4.3) */ + +#define OHCI_RHSTATUS_LPS (1 << 0) /* Bit 0: Local power status (read)*/ +#define OHCI_RHSTATUS_CGP (1 << 0) /* Bit 0: Clear global power (write)*/ +#define OHCI_RHSTATUS_OCI (1 << 1) /* Bit 1: Over current indicator */ + /* Bits 2-14: Reserved */ +#define OHCI_RHSTATUS_DRWE (1 << 15) /* Bit 15: Device remote wakeup enable */ +#define OHCI_RHSTATUS_LPSC (1 << 16) /* Bit 16: Local power status change (read) */ +#define OHCI_RHSTATUS_SGP (1 << 16) /* Bit 16: Set global power (write) */ +#define OHCI_RHSTATUS_OCIC (1 << 17) /* Bit 17: Overcurrent indicator change */ + /* Bits 18-30: Reserved */ +#define OHCI_RHSTATUS_CRWE (1 << 31) /* Bit 31: Clear remote wakeup enable */ + +/* HcRhPortStatus: Root hub port status (7.4.4) */ + +#define OHCI_RHPORTST_CCS (1 << 0) /* Bit 0: Current connect status */ +#define OHCI_RHPORTST_PES (1 << 1) /* Bit 1: Port enable status */ +#define OHCI_RHPORTST_PSS (1 << 2) /* Bit 2: Port suspend status */ +#define OHCI_RHPORTST_POCI (1 << 3) /* Bit 3: Port over current indicator */ +#define OHCI_RHPORTST_PRS (1 << 4) /* Bit 4: Port reset status */ + /* Bits 5-7: Reserved */ +#define OHCI_RHPORTST_PPS (1 << 8) /* Bit 8: Port power status */ +#define OHCI_RHPORTST_LSDA (1 << 9) /* Bit 9: Low speed device attached */ + /* Bits 10-15: Reserved */ +#define OHCI_RHPORTST_CSC (1 << 16) /* Bit 16: Connect status change */ +#define OHCI_RHPORTST_PESC (1 << 17) /* Bit 17: Port enable status change */ +#define OHCI_RHPORTST_PSSC (1 << 18) /* Bit 18: Port suspend status change */ +#define OHCI_RHPORTST_OCIC (1 << 19) /* Bit 19: Port over current indicator change */ +#define OHCI_RHPORTST_PRSC (1 << 20) /* Bit 20: Port reset status change */ + /* Bits 21-31: Reserved */ + +/* Transfer Descriptors *****************************************************/ + +/* Endpoint Descriptor Offsets (4.2.1) */ + +#define ED_CONTROL_OFFSET (0x00) /* ED status/control bits */ +#define ED_TAILP_OFFSET (0x04) /* TD Queue Tail Pointer (TailP) */ +#define ED_HEADP_OFFSET (0x08) /* TD Queue Head Pointer (HeadP) */ +#define ED_NEXTED_OFFSET (0x0c) /* Next Endpoint Descriptor (NextED) */ + +/* Endpoint Descriptor Bit Definitions (4.2.2) */ + +#define ED_CONTROL_FA_SHIFT (0) /* Bits 0-6: Function Address */ +#define ED_CONTROL_FA_MASK (0x7f << ED_CONTROL_FA_SHIFT) +#define ED_CONTROL_EN_SHIFT (7) /* Bits 7-10: Endpoint number */ +#define ED_CONTROL_EN_MASK (15 << ED_CONTROL_EN_SHIFT) +#define ED_CONTROL_D_SHIFT (11) /* Bits 11-12: Direction */ +#define ED_CONTROL_D_MASK (3 << ED_CONTROL_D_SHIFT) +# define ED_CONTROL_D_TD1 (0 << ED_CONTROL_D_SHIFT) /* Get direction from TD */ +# define ED_CONTROL_D_OUT (1 << ED_CONTROL_D_SHIFT) /* OUT */ +# define ED_CONTROL_D_IN (2 << ED_CONTROL_D_SHIFT) /* IN */ +# define ED_CONTROL_D_TD2 (3 << ED_CONTROL_D_SHIFT) /* Get direction from TD */ + +#define ED_CONTROL_SPPED_LOW (1 << 13) /* Bit 13: Speed (low) */ +#define ED_CONTROL_SKIP (1 << 14) /* Bit 14: Skip */ +#define ED_CONTROL_FORMAT_ISO (1 << 15) /* Bit 15: Format (isochronous) */ +#define ED_CONTROL_MPS_SHIFT (16) /* Bits 16-26: Maximum packet size */ +#define ED_CONTROL_MPS_MASK (0x7ff << ED_CONTROL_MPS_SHIFT) + +#define ED_HEADP_ADDR_SHIFT (0) +#define ED_HEADP_ADDR_MASK 0xfffffff0 +#define ED_HEADP_H (1 << 0) /* Bit 0: Halted */ +#define ED_HEADP_C (1 << 1) /* Bit 1: Toggle carry */ + +/* General Transfer Descriptor Offsets (4.3.1) */ + +#define GTD_STATUS_OFFSET (0x00) /* TD status bits */ +#define GTD_CBP_OFFSET (0x04) /* Current Buffer Pointer (CBP) */ +#define GTD_NEXTTD_OFFSET (0x08) /* Next TD (NextTD) */ +#define GTD_BE_OFFSET (0x0c) /* Buffer End (BE) */ + +/* General Transfer Descriptor Bit Definitions */ + + /* Bits 0-17: Reserved */ + +#define GTD_STATUS_R (1 << 18) /* Bit 18: Buffer rounding */ +#define GTD_STATUS_DP_SHIFT (19) /* Bits 19-20: Direction/PID */ +#define GTD_STATUS_DP_MASK (3 << GTD_STATUS_DP_SHIFT) +# define GTD_STATUS_DP_SETUP (0 << GTD_STATUS_DP_SHIFT) /* To endpoint */ +# define GTD_STATUS_DP_OUT (1 << GTD_STATUS_DP_SHIFT) /* To endpoint */ +# define GTD_STATUS_DP_IN (2 << GTD_STATUS_DP_SHIFT) /* From endpoint */ + +#define GTD_STATUS_DI_SHIFT (21) /* Bits 21-23: Delay input */ +#define GTD_STATUS_DI_MASK (7 << GTD_STATUS_DI_SHIFT) +#define GTD_STATUS_T_SHIFT (24) /* Bits 24-25: Data Toggle */ +#define GTD_STATUS_T_MASK (3 << GTD_STATUS_T_SHIFT) +# define GTD_STATUS_T_TOGGLE (0 << GTD_STATUS_T_SHIFT) +# define GTD_STATUS_T_DATA0 (2 << GTD_STATUS_T_SHIFT) +# define GTD_STATUS_T_DATA1 (3 << GTD_STATUS_T_SHIFT) +#define GTD_STATUS_EC_SHIFT (26) /* Bits 26-27: Error count */ +#define GTD_STATUS_EC_MASK (3 << GTD_STATUS_EC_SHIFT) +#define GTD_STATUS_CC_SHIFT (28) /* Bits 28-31: Condition code */ +#define GTD_STATUS_CC_MASK (15 << GTD_STATUS_CC_SHIFT) + +/* Isochronous Transfer Descriptor Offsets (4.3.2) */ + +#define ITD_STATUS_OFFSET (0x00) /* TD status bits */ +#define ITD_BP0_OFFSET (0x04) /* Buffer page 0 (BP0) */ +#define ITD_NEXTTD_OFFSET (0x08) /* Next TD (NextTD) */ +#define ITD_BE_OFFSET (0x0c) /* Buffer End (BE) */ + +#define ITD_NPSW (8) +#define ITD_PSW0_OFFSET (0x10) /* Offset0/PSW0 */ +#define ITD_PSW1_OFFSET (0x12) /* Offset1/PSW1 */ +#define ITD_PSW2_OFFSET (0x14) /* Offset2/PSW2 */ +#define ITD_PSW3_OFFSET (0x16) /* Offset3/PSW3 */ +#define ITD_PSW4_OFFSET (0x18) /* Offset4/PSW4 */ +#define ITD_PSW5_OFFSET (0x1a) /* Offset5/PSW5 */ +#define ITD_PSW6_OFFSET (0x1c) /* Offset6/PSW6 */ +#define ITD_PSW7_OFFSET (0x1e) /* Offset7/PSW7 */ + +/* Condition codes (Table 4-7) */ + +#define TD_CC_NOERROR 0x00 +#define TD_CC_CRC 0x01 +#define TD_CC_BITSTUFFING 0x02 +#define TD_CC_DATATOGGLEMISMATCH 0x03 +#define TD_CC_STALL 0x04 +#define TD_CC_DEVNOTRESPONDING 0x05 +#define TD_CC_PIDCHECKFAILURE 0x06 +#define TD_CC_UNEXPECTEDPID 0x07 +#define TD_CC_DATAOVERRUN 0x08 +#define TD_CC_DATAUNDERRUN 0x09 +#define TD_CC_BUFFEROVERRUN 0x0c +#define TD_CC_BUFFERUNDERRUN 0x0d +#define TD_CC_NOTACCESSED 0x0f + +#define TD_CC_USER 0x10 /* For use by OHCI drivers */ + +/* Host Controller Communications Area Format (4.4.1) ***********************/ + +/* HccaInterruptTable: 32x32-bit pointers to interrupt EDs */ + +#define HCCA_INTTBL_OFFSET (0x00) +#define HCCA_INTTBL_WSIZE (32) +#define HCCA_INTTBL_BSIZE (HCCA_INTTBL_WSIZE * 4) + +/* HccaFrameNumber: Current frame number */ + +#define HCCA_FMNO_OFFSET (0x80) +#define HCCA_FMNO_BSIZE (2) + +/* HccaPad1: Zero when frame no. updated */ + +#define HCCA_PAD1_OFFSET (0x82) +#define HCCA_PAD1_BSIZE (2) + +/* HccaDoneHead: When the HC reaches the end of a frame and its deferred + * interrupt register is 0, it writes the current value of its HcDoneHead to + * this location and generates an interrupt. + * + * The LSB of HCCADoneHead may be set to 1 to indicate that an unmasked + * HcInterruptStatus was set when HccaDoneHead was written. + */ + +#define HCCA_DONEHEAD_OFFSET (0x84) +#define HCCA_DONEHEAD_BSIZE (4) + +#define HCCA_DONEHEAD_MASK 0xfffffffe +#define HCCA_DONEHEAD_INTSTA (1 << 0) + +/* 0x88: 116 bytes reserved */ + +#define HCCA_RESERVED_OFFSET (0x88) +#define HCCA_RESERVED_BSIZE (116) + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +struct ohci_hcor +{ + volatile uint32_t hcrevision; /* 0x00 */ + volatile uint32_t hccontrol; /* 0x04 */ + volatile uint32_t hccmdsts; /* 0x08 */ + volatile uint32_t hcintsts; /* 0x0c */ + volatile uint32_t hcinten; /* 0x10 */ + volatile uint32_t hcintdis; /* 0x14 */ + volatile uint32_t hchcca; /* 0x18 */ + volatile uint32_t hcperiodcurrented; /* 0x1c */ + volatile uint32_t hccontrolheaded; /* 0x20 */ + volatile uint32_t hccontrolcurrented; /* 0x24 */ + volatile uint32_t hcbulkheaded; /* 0x28 */ + volatile uint32_t hcbulkcurrented; /* 0x2c */ + volatile uint32_t hcdonehead; /* 0x30 */ + volatile uint32_t hcfminterval; /* 0x34 */ + volatile uint32_t hcfmremaining; /* 0x38 */ + volatile uint32_t hcfmnumber; /* 0x3c */ + volatile uint32_t hcperiodicstart; /* 0x40 */ + volatile uint32_t hclsthreshold; /* 0x44 */ + volatile uint32_t hcrhdescriptora; /* 0x48 */ + volatile uint32_t hcrhdescriptorb; /* 0x4c */ + volatile uint32_t hcrhsts; /* 0x50 */ + volatile uint32_t hcrhportsts[15]; /* 0x54 */ +}; + +/* Endpoint Descriptor Offsets (4.2.1) */ + +struct ohci_ed +{ + volatile uint32_t ctrl; /* ED status/control bits */ + volatile uint32_t tailp; /* TD Queue Tail Pointer (TailP) */ + volatile uint32_t headp; /* TD Queue Head Pointer (HeadP) */ + volatile uint32_t nexted; /* Next Endpoint Descriptor (NextED) */ +}; + +/* General Transfer Descriptor (4.3.1) */ + +struct ohci_gtd +{ + volatile uint32_t ctrl; /* TD status/control bits */ + volatile uint32_t cbp; /* Current Buffer Pointer (CBP) */ + volatile uint32_t nexttd; /* Next TD (NextTD) */ + volatile uint32_t be; /* Buffer End (BE) */ +}; + +/* Isochronous Transfer Descriptor Offsets (4.3.2) */ + +struct ohci_itd +{ + volatile uint32_t ctrl; /* TD status/control bits */ + volatile uint32_t bp0; /* Buffer page 0 (BP0 */ + volatile uint32_t nexttd; /* Next TD (NextTD) */ + volatile uint32_t be; /* Buffer End (BE) */ + volatile uint16_t psw[ITD_NPSW]; /* Offset/PSW */ +}; + +/* Host Controller Communications Area Format (4.4.1) */ + +struct ohci_hcca +{ + /* HccaInterruptTable: 32x32-bit pointers to interrupt EDs */ + + volatile uint32_t inttbl[HCCA_INTTBL_WSIZE]; + + /* HccaFrameNumber: Current frame number and + * HccaPad1: Zero when frame no. updated + */ + + volatile uint16_t fmno; + volatile uint16_t pad1; + + /* HccaDoneHead: When the HC reaches the end of a frame and its deferred + * interrupt register is 0, it writes the current value of its HcDoneHead + * to this location and generates an interrupt. + */ + + volatile uint32_t donehead; + volatile uint8_t reserved[HCCA_RESERVED_BSIZE]; + volatile uint32_t extra; +} __attribute__((aligned(256))); + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +#ifdef __cplusplus +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +#undef EXTERN +#ifdef __cplusplus +} +#endif + +#endif /* __INCLUDE_NUTTX_USB_OHCI_H */ diff --git a/kernel/cherryusb/port/pusb2/README.md b/kernel/cherryusb/port/pusb2/README.md new file mode 100644 index 0000000..9effa49 --- /dev/null +++ b/kernel/cherryusb/port/pusb2/README.md @@ -0,0 +1,66 @@ +# USB 2.0 OTG 控制器 (PUSB2) + +- Phytium PI 和 Phyium E2000 系列开发板提供了兼容 USB2.0 的 OTG 接口 +- 相关的使用例程可以在 Phytium PI（飞腾派）和 E2000 D/Q Demo 板上运行，例程包括 + +--------------------------------------------- + +- Host 模式 + +- - 1. [FreeRTOS 上作为主机使用键盘/鼠标/U盘](https://gitee.com/phytium_embedded/phytium-free-rtos-sdk/tree/master/example/peripheral/usb/pusb2_host/README.md) +- - 5. [RT-Thread 上作为主机识别键盘/鼠标/U盘](https://github.com/RT-Thread/rt-thread/blob/master/bsp/phytium/doc/use_cherryusb.md) + +--------------------------------------------- + +- Device 模式 + +- - 1. [裸机上模拟为一个 U 盘](https://gitee.com/phytium_embedded/phytium-standalone-sdk/tree/master/example/peripherals/usb/pusb2_device/README.md) +- - 2. [裸机上模拟为一个虚拟串口](https://gitee.com/phytium_embedded/phytium-standalone-sdk/tree/master/example/peripherals/usb/pusb2_device/README.md) +- - 3. [FreeRTOS 上模拟为一个 U 盘](https://gitee.com/phytium_embedded/phytium-free-rtos-sdk/tree/master/example/peripheral/usb/pusb2_device/README.md) +- - 4. [FreeRTOS 上模拟为虚拟串口](https://gitee.com/phytium_embedded/phytium-free-rtos-sdk/tree/master/example/peripheral/usb/pusb2_device/README.md) +- - 5. [RT-Thread 上模拟为一个 U 盘](https://github.com/RT-Thread/rt-thread/blob/master/bsp/phytium/doc/use_cherryusb.md) + +--------------------------------------------- + +- PUSB2 的驱动功能以静态库的方式提供， +- - libpusb2_hc_a64.a : AARCH64 主机模式驱动库 +- - libpusb2_dc_a64.a : AARCH64 从机模式驱动库 +- - libpusb2_hc_a32_hardfp.a ：AARCH32 主机模式驱动库，使用硬浮点 +- - libpusb2_hc_a32_softfp.a ：AARCH32 主机模式驱动库，使用软浮点 +- - libpusb2_dc_a32_hardfp.a ：AARCH32 从机模式驱动库，使用硬浮点 +- - libpusb2_dc_a32_softfp.a ：AARCH32 从机模式驱动库，使用软浮点 + +需要获取源代码请联系 `opensource_embedded@phytium.com.cn` 获取 + +# USB 2.0 OTG Controller (PUSB2) + +- Phytium PI and the Phytium E2000 series development boards offer OTG interfaces compatible with USB 2.0. +- Relevant usage examples can be run on the Phytium PI and E2000 D/Q Demo boards, including: + +--------------------------------------------- + +- Host Mode + + - 1. [Using a keyboard/mouse/USB flash drive as a host on FreeRTOS](https://gitee.com/phytium_embedded/phytium-free-rtos-sdk/tree/master/example/peripheral/usb/pusb2_host/README.md) + - 5. [Recognizing a keyboard/mouse/USB flash drive as a host on RT-Thread](https://github.com/RT-Thread/rt-thread/blob/master/bsp/phytium/doc/use_cherryusb.md) + +--------------------------------------------- + +- Device Mode + - 1. [Simulating as a USB flash drive on a standalone system](https://gitee.com/phytium_embedded/phytium-standalone-sdk/tree/master/example/peripherals/usb/pusb2_device/README.md) + - 2. [Simulating as a virtual serial port on a standalone system](https://gitee.com/phytium_embedded/phytium-standalone-sdk/tree/master/example/peripherals/usb/pusb2_device/README.md) + - 3. [Simulating as a USB flash drive on FreeRTOS](https://gitee.com/phytium_embedded/phytium-free-rtos-sdk/tree/master/example/peripheral/usb/pusb2_device/README.md) + - 4. [Simulating as a virtual serial port on FreeRTOS](https://gitee.com/phytium_embedded/phytium-free-rtos-sdk/tree/master/example/peripheral/usb/pusb2_device/README.md) + - 5. [Simulating as a USB flash drive on RT-Thread](https://github.com/RT-Thread/rt-thread/blob/master/bsp/phytium/doc/use_cherryusb.md) + +--------------------------------------------- + +- The driver functionality of PUSB2 is provided as static libraries: + - - `libpusb2_hc_a64.a` : Host mode driver library for AARCH64 + - - `libpusb2_dc_a64.a` : Device mode driver library for AARCH64 + - - `libpusb2_hc_a32_hardfp.a` : Host mode driver library for AARCH32, using hard floating point + - - `libpusb2_hc_a32_softfp.a` : Host mode driver library for AARCH32, using soft floating point + - - `libpusb2_dc_a32_hardfp.a` : Device mode driver library for AARCH32, using hard floating point + - - `libpusb2_dc_a32_softfp.a` : Device mode driver library for AARCH32, using soft floating point + +- To obtain the source code, please contact `opensource_embedded@phytium.com.cn`. \ No newline at end of file diff --git a/kernel/cherryusb/port/pusb2/freertos/usb_config.h b/kernel/cherryusb/port/pusb2/freertos/usb_config.h new file mode 100644 index 0000000..760759f --- /dev/null +++ b/kernel/cherryusb/port/pusb2/freertos/usb_config.h @@ -0,0 +1,281 @@ +/* + * Copyright : (C) 2024 Phytium Information Technology, Inc. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Modify History: + * Ver   Who        Date         Changes + * ----- ------     --------    -------------------------------------- + * 1.0 zhugengyu 2024/6/26 first commit + */ +#ifndef CHERRYUSB_CONFIG_H +#define CHERRYUSB_CONFIG_H + +#include "sdkconfig.h" +#include "FreeRTOS.h" +#include "task.h" + +/* ================ USB common Configuration ================ */ + +#define CONFIG_USB_PRINTF(...) printf(__VA_ARGS__) + +int xPortIsInsideInterrupt(void); + +void *usb_sys_mem_malloc(size_t size); +void usb_sys_mem_free(void *ptr); +void *usb_sys_malloc_align(size_t align, size_t size); + +#define usb_malloc(size) usb_sys_mem_malloc(size) +#define usb_free(ptr) usb_sys_mem_free(ptr) +#define usb_align(align, size) usb_sys_malloc_align(align, size) + +unsigned long usb_hc_get_register_base(uint32_t id); +unsigned long usb_dc_get_register_base(uint32_t id); + +#ifndef CONFIG_USB_DBG_LEVEL +#if defined(CONFIG_LOG_ERROR) +#define CONFIG_USB_DBG_LEVEL USB_DBG_ERROR +#elif defined(CONFIG_LOG_WARN) +#define CONFIG_USB_DBG_LEVEL USB_DBG_WARNING +#elif defined(CONFIG_LOG_INFO) +#define CONFIG_USB_DBG_LEVEL USB_DBG_INFO +#elif defined(CONFIG_LOG_DEBUG) || defined(CONFIG_LOG_VERBOS) +#define CONFIG_USB_DBG_LEVEL USB_DBG_LOG +#else +#define CONFIG_USB_DBG_LEVEL USB_DBG_ERROR +#endif +#endif + +/* Enable print with color */ +#define CONFIG_USB_PRINTF_COLOR_ENABLE + +/* data align size when use dma */ +#ifndef CONFIG_USB_ALIGN_SIZE +#define CONFIG_USB_ALIGN_SIZE 4 +#endif + +/* attribute data into no cache ram */ +#define USB_NOCACHE_RAM_SECTION __attribute__((section(".noncacheable"))) + +/* ================= USB Device Stack Configuration ================ */ + +/* Ep0 in and out transfer buffer */ +#ifndef CONFIG_USBDEV_REQUEST_BUFFER_LEN +#define CONFIG_USBDEV_REQUEST_BUFFER_LEN 512 +#endif + +/* Setup packet log for debug */ +// #define CONFIG_USBDEV_SETUP_LOG_PRINT + +/* Send ep0 in data from user buffer instead of copying into ep0 reqdata + * Please note that user buffer must be aligned with CONFIG_USB_ALIGN_SIZE +*/ +// #define CONFIG_USBDEV_EP0_INDATA_NO_COPY + +/* Check if the input descriptor is correct */ +// #define CONFIG_USBDEV_DESC_CHECK + +/* Enable test mode */ +// #define CONFIG_USBDEV_TEST_MODE + +#ifndef CONFIG_USBDEV_MSC_MAX_LUN +#define CONFIG_USBDEV_MSC_MAX_LUN 1 +#endif + +#ifndef CONFIG_USBDEV_MSC_MAX_BUFSIZE +#define CONFIG_USBDEV_MSC_MAX_BUFSIZE 4096 +#endif + +#ifndef CONFIG_USBDEV_MSC_MANUFACTURER_STRING +#define CONFIG_USBDEV_MSC_MANUFACTURER_STRING "" +#endif + +#ifndef CONFIG_USBDEV_MSC_PRODUCT_STRING +#define CONFIG_USBDEV_MSC_PRODUCT_STRING "" +#endif + +#ifndef CONFIG_USBDEV_MSC_VERSION_STRING +#define CONFIG_USBDEV_MSC_VERSION_STRING "0.01" +#endif + +// #define CONFIG_USBDEV_MSC_THREAD + +#ifndef CONFIG_USBDEV_MSC_PRIO +#define CONFIG_USBDEV_MSC_PRIO 4 +#endif + +#ifndef CONFIG_USBDEV_MSC_STACKSIZE +#define CONFIG_USBDEV_MSC_STACKSIZE 2048 +#endif + +#ifndef CONFIG_USBDEV_RNDIS_RESP_BUFFER_SIZE +#define CONFIG_USBDEV_RNDIS_RESP_BUFFER_SIZE 156 +#endif + +/* rndis transfer buffer size, must be a multiple of (1536 + 44)*/ +#ifndef CONFIG_USBDEV_RNDIS_ETH_MAX_FRAME_SIZE +#define CONFIG_USBDEV_RNDIS_ETH_MAX_FRAME_SIZE 1580 +#endif + +#ifndef CONFIG_USBDEV_RNDIS_VENDOR_ID +#define CONFIG_USBDEV_RNDIS_VENDOR_ID 0x0000ffff +#endif + +#ifndef CONFIG_USBDEV_RNDIS_VENDOR_DESC +#define CONFIG_USBDEV_RNDIS_VENDOR_DESC "CherryUSB" +#endif + +#define CONFIG_USBDEV_RNDIS_USING_LWIP + +/* ================ USB HOST Stack Configuration ================== */ + +#define CONFIG_USBHOST_MAX_RHPORTS 1 +#define CONFIG_USBHOST_MAX_EXTHUBS 0 +#define CONFIG_USBHOST_MAX_EHPORTS 8 +#define CONFIG_USBHOST_MAX_INTERFACES 8 +#define CONFIG_USBHOST_MAX_INTF_ALTSETTINGS 8 +#define CONFIG_USBHOST_MAX_ENDPOINTS 8 + +#define CONFIG_USBHOST_MAX_CDC_ACM_CLASS 4 +#define CONFIG_USBHOST_MAX_HID_CLASS 4 +#define CONFIG_USBHOST_MAX_MSC_CLASS 2 +#define CONFIG_USBHOST_MAX_AUDIO_CLASS 1 +#define CONFIG_USBHOST_MAX_VIDEO_CLASS 1 + +#define CONFIG_USBHOST_DEV_NAMELEN 16 + +#ifndef CONFIG_USBHOST_PSC_PRIO +#define CONFIG_USBHOST_PSC_PRIO 0 +#endif +#ifndef CONFIG_USBHOST_PSC_STACKSIZE +#define CONFIG_USBHOST_PSC_STACKSIZE 8192 +#endif + +//#define CONFIG_USBHOST_GET_STRING_DESC + +// #define CONFIG_USBHOST_MSOS_ENABLE +#ifndef CONFIG_USBHOST_MSOS_VENDOR_CODE +#define CONFIG_USBHOST_MSOS_VENDOR_CODE 0x00 +#endif + +/* Ep0 max transfer buffer */ +#ifndef CONFIG_USBHOST_REQUEST_BUFFER_LEN +#define CONFIG_USBHOST_REQUEST_BUFFER_LEN 512 +#endif + +#ifndef CONFIG_USBHOST_CONTROL_TRANSFER_TIMEOUT +#define CONFIG_USBHOST_CONTROL_TRANSFER_TIMEOUT 500 +#endif + +#ifndef CONFIG_USBHOST_MSC_TIMEOUT +#define CONFIG_USBHOST_MSC_TIMEOUT 5000 +#endif + +/* This parameter affects usb performance, and depends on (TCP_WND)tcp eceive windows size, + * you can change to 2K ~ 16K and must be larger than TCP RX windows size in order to avoid being overflow. + */ +#ifndef CONFIG_USBHOST_RNDIS_ETH_MAX_RX_SIZE +#define CONFIG_USBHOST_RNDIS_ETH_MAX_RX_SIZE (2048) +#endif + +/* Because lwip do not support multi pbuf at a time, so increasing this variable has no performance improvement */ +#ifndef CONFIG_USBHOST_RNDIS_ETH_MAX_TX_SIZE +#define CONFIG_USBHOST_RNDIS_ETH_MAX_TX_SIZE (2048) +#endif + +/* This parameter affects usb performance, and depends on (TCP_WND)tcp eceive windows size, + * you can change to 2K ~ 16K and must be larger than TCP RX windows size in order to avoid being overflow. + */ +#ifndef CONFIG_USBHOST_CDC_NCM_ETH_MAX_RX_SIZE +#define CONFIG_USBHOST_CDC_NCM_ETH_MAX_RX_SIZE (2048) +#endif +/* Because lwip do not support multi pbuf at a time, so increasing this variable has no performance improvement */ +#ifndef CONFIG_USBHOST_CDC_NCM_ETH_MAX_TX_SIZE +#define CONFIG_USBHOST_CDC_NCM_ETH_MAX_TX_SIZE (2048) +#endif + +/* This parameter affects usb performance, and depends on (TCP_WND)tcp eceive windows size, + * you can change to 2K ~ 16K and must be larger than TCP RX windows size in order to avoid being overflow. + */ +#ifndef CONFIG_USBHOST_ASIX_ETH_MAX_RX_SIZE +#define CONFIG_USBHOST_ASIX_ETH_MAX_RX_SIZE (2048) +#endif +/* Because lwip do not support multi pbuf at a time, so increasing this variable has no performance improvement */ +#ifndef CONFIG_USBHOST_ASIX_ETH_MAX_TX_SIZE +#define CONFIG_USBHOST_ASIX_ETH_MAX_TX_SIZE (2048) +#endif + +/* This parameter affects usb performance, and depends on (TCP_WND)tcp eceive windows size, + * you can change to 2K ~ 16K and must be larger than TCP RX windows size in order to avoid being overflow. + */ +#ifndef CONFIG_USBHOST_RTL8152_ETH_MAX_RX_SIZE +#define CONFIG_USBHOST_RTL8152_ETH_MAX_RX_SIZE (2048) +#endif +/* Because lwip do not support multi pbuf at a time, so increasing this variable has no performance improvement */ +#ifndef CONFIG_USBHOST_RTL8152_ETH_MAX_TX_SIZE +#define CONFIG_USBHOST_RTL8152_ETH_MAX_TX_SIZE (2048) +#endif + +#define CONFIG_USBHOST_BLUETOOTH_HCI_H4 +// #define CONFIG_USBHOST_BLUETOOTH_HCI_LOG + +#ifndef CONFIG_USBHOST_BLUETOOTH_TX_SIZE +#define CONFIG_USBHOST_BLUETOOTH_TX_SIZE 2048 +#endif +#ifndef CONFIG_USBHOST_BLUETOOTH_RX_SIZE +#define CONFIG_USBHOST_BLUETOOTH_RX_SIZE 2048 +#endif + +/* ================ USB Device Port Configuration ================*/ + +#ifndef CONFIG_USBDEV_MAX_BUS +#define CONFIG_USBDEV_MAX_BUS 1 // for now, bus num must be 1 except hpm ip +#endif + +#ifndef CONFIG_USBDEV_EP_NUM +#define CONFIG_USBDEV_EP_NUM 8 +#endif + +/* ---------------- FSDEV Configuration ---------------- */ +//#define CONFIG_USBDEV_FSDEV_PMA_ACCESS 2 // maybe 1 or 2, many chips may have a difference + +/* ---------------- DWC2 Configuration ---------------- */ +/* (5 * number of control endpoints + 8) + ((largest USB packet used / 4) + 1 for + * status information) + (2 * number of OUT endpoints) + 1 for Global NAK + */ +// #define CONFIG_USB_DWC2_RXALL_FIFO_SIZE (1024 / 4) +/* IN Endpoints Max packet Size / 4 */ +// #define CONFIG_USB_DWC2_TX0_FIFO_SIZE (64 / 4) +// #define CONFIG_USB_DWC2_TX1_FIFO_SIZE (512 / 4) +// #define CONFIG_USB_DWC2_TX2_FIFO_SIZE (64 / 4) +// #define CONFIG_USB_DWC2_TX3_FIFO_SIZE (64 / 4) +// #define CONFIG_USB_DWC2_TX4_FIFO_SIZE (0 / 4) +// #define CONFIG_USB_DWC2_TX5_FIFO_SIZE (0 / 4) +// #define CONFIG_USB_DWC2_TX6_FIFO_SIZE (0 / 4) +// #define CONFIG_USB_DWC2_TX7_FIFO_SIZE (0 / 4) +// #define CONFIG_USB_DWC2_TX8_FIFO_SIZE (0 / 4) + +/* ---------------- MUSB Configuration ---------------- */ +// #define CONFIG_USB_MUSB_SUNXI + +/* ================ USB Host Port Configuration ==================*/ +#ifndef CONFIG_INPUT_MOUSE_WHEEL +#define CONFIG_INPUT_MOUSE_WHEEL +#endif + +#ifndef CONFIG_USBHOST_MAX_BUS +#define CONFIG_USBHOST_MAX_BUS 3 +#endif + +#ifndef CONFIG_USBHOST_PIPE_NUM +#define CONFIG_USBHOST_PIPE_NUM 10 +#endif + +/* ---------------- XHCI Configuration ---------------- */ +#define CONFIG_USB_XHCI_HCCR_OFFSET (0x0) + +/* ---------------- PUSB2 Configuration ---------------- */ +#define CONFIG_USB_PUSB2_BUS_NUM 3U +#define CONFIG_USB_PUSB2_BUS_ID 0U + +#endif diff --git a/kernel/cherryusb/port/pusb2/freertos/usb_dc_glue_phytium.c b/kernel/cherryusb/port/pusb2/freertos/usb_dc_glue_phytium.c new file mode 100644 index 0000000..4e674ec --- /dev/null +++ b/kernel/cherryusb/port/pusb2/freertos/usb_dc_glue_phytium.c @@ -0,0 +1,141 @@ +/* + * Copyright : (C) 2024 Phytium Information Technology, Inc. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Modify History: + * Ver   Who        Date         Changes + * ----- ------     --------    -------------------------------------- + * 1.0 zhugengyu 2024/6/26 first commit + */ + +/***************************** Include Files *********************************/ +#include +#include + +#include "fassert.h" +#include "fparameters.h" +#include "finterrupt.h" +#include "fcpu_info.h" +#include "fdebug.h" +#include "fcache.h" +#include "fmemory_pool.h" + +#include "usbd_core.h" + +/************************** Constant Definitions *****************************/ +#define USB_MEMP_TOTAL_SIZE SZ_1M + +/**************************** Type Definitions *******************************/ +void USBD_IRQHandler(uint8_t busid); + +/************************** Variable Definitions *****************************/ +static FMemp memp; +static u8 memp_buf[USB_MEMP_TOTAL_SIZE] __attribute__((aligned(8))) = {0}; + +void usb_sys_mem_init(void) +{ + if (FT_COMPONENT_IS_READY != memp.is_ready) + { + USB_ASSERT(FT_SUCCESS == FMempInit(&memp, &memp_buf[0], &memp_buf[0] + USB_MEMP_TOTAL_SIZE)); + } +} + +void usb_sys_mem_deinit(void) +{ + if (FT_COMPONENT_IS_READY == memp.is_ready) + { + FMempDeinit(&memp); + } +} + +void *usb_sys_malloc_align(size_t align, size_t size) +{ + void *result = FMempMallocAlign(&memp, size, align); + + if (result) + { + memset(result, 0U, size); + } + + return result; +} + +void *usb_sys_mem_malloc(size_t size) +{ + return usb_sys_malloc_align(sizeof(void *), size); +} + +void usb_sys_mem_free(void *ptr) +{ + if (NULL != ptr) + { + FMempFree(&memp, ptr); + } +} + +void usb_assert(const char *filename, int linenum) +{ + FAssert(filename, linenum, 0xff); +} + +static void usb_dc_pusb2_interrupt_handler(s32 vector, void *param) +{ + USBD_IRQHandler(CONFIG_USB_PUSB2_BUS_ID); +} + +static void usb_dc_setup_pusb2_interrupt(u32 id) +{ + u32 cpu_id; + USB_ASSERT(id == FUSB2_ID_VHUB_0); + u32 irq_num = FUSB2_0_VHUB_IRQ_NUM; + u32 irq_priority = 13U; + + GetCpuId(&cpu_id); + InterruptSetTargetCpus(irq_num, cpu_id); + + InterruptSetPriority(irq_num, irq_priority); + + /* register intr callback */ + InterruptInstall(irq_num, + usb_dc_pusb2_interrupt_handler, + NULL, + NULL); + + /* enable irq */ + InterruptUmask(irq_num); +} + +static void usb_dc_revoke_pusb2_interrupt(u32 id) +{ + USB_ASSERT(id == FUSB2_ID_VHUB_0); + u32 irq_num = FUSB2_0_VHUB_IRQ_NUM; + + /* disable irq */ + InterruptMask(irq_num); +} + +extern int vApplicationInIrq(void); +int xPortIsInsideInterrupt(void) +{ + return vApplicationInIrq(); +} + +unsigned long usb_dc_get_register_base(uint32_t id) +{ + USB_ASSERT(id == FUSB2_ID_VHUB_0); + return FUSB2_0_VHUB_BASE_ADDR; +} + +/* implement cherryusb weak functions */ +void usb_dc_low_level_init() +{ + usb_sys_mem_init(); + usb_dc_setup_pusb2_interrupt(CONFIG_USB_PUSB2_BUS_ID); +} + +void usb_dc_low_level_deinit(void) +{ + usb_dc_revoke_pusb2_interrupt(CONFIG_USB_PUSB2_BUS_ID); + usb_sys_mem_deinit(); +} diff --git a/kernel/cherryusb/port/pusb2/freertos/usb_hc_glue_phytium.c b/kernel/cherryusb/port/pusb2/freertos/usb_hc_glue_phytium.c new file mode 100644 index 0000000..58a90af --- /dev/null +++ b/kernel/cherryusb/port/pusb2/freertos/usb_hc_glue_phytium.c @@ -0,0 +1,165 @@ +/* + * Copyright : (C) 2024 Phytium Information Technology, Inc. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Modify History: + * Ver   Who        Date         Changes + * ----- ------     --------    -------------------------------------- + * 1.0 zhugengyu 2024/6/26 first commit + */ + +/***************************** Include Files *********************************/ +#include +#include + +#include "fassert.h" +#include "fparameters.h" +#include "finterrupt.h" +#include "fcpu_info.h" +#include "fdebug.h" +#include "fcache.h" +#include "fmemory_pool.h" + +#include "usbh_core.h" + +/************************** Constant Definitions *****************************/ +#define USB_MEMP_TOTAL_SIZE SZ_1M + +/**************************** Type Definitions *******************************/ +void USBH_IRQHandler(uint8_t busid); + +/************************** Variable Definitions *****************************/ +static FMemp memp; +static u8 memp_buf[USB_MEMP_TOTAL_SIZE] __attribute__((aligned(8))) = {0}; +static u32 memp_ref_cnt = 0; +static const u32 irq_nums[] = { + FUSB2_0_VHUB_IRQ_NUM, FUSB2_1_IRQ_NUM, FUSB2_2_IRQ_NUM +}; + +void usb_sys_mem_init(void) +{ + if (FT_COMPONENT_IS_READY != memp.is_ready) + { + USB_ASSERT(FT_SUCCESS == FMempInit(&memp, &memp_buf[0], &memp_buf[0] + USB_MEMP_TOTAL_SIZE)); + } +} + +void usb_sys_mem_deinit(void) +{ + if (FT_COMPONENT_IS_READY == memp.is_ready) + { + FMempDeinit(&memp); + } +} + +void *usb_sys_malloc_align(size_t align, size_t size) +{ + void *result = FMempMallocAlign(&memp, size, align); + + if (result) + { + memset(result, 0U, size); + } + + return result; +} + +void *usb_sys_mem_malloc(size_t size) +{ + return usb_sys_malloc_align(sizeof(void *), size); +} + +void usb_sys_mem_free(void *ptr) +{ + if (NULL != ptr) + { + FMempFree(&memp, ptr); + } +} + +void usb_assert(const char *filename, int linenum) +{ + FAssert(filename, linenum, 0xff); +} + +static void usb_hc_pusb2_interrupt_handler(s32 vector, void *param) +{ + if (vector == FUSB2_0_VHUB_IRQ_NUM) { + USBH_IRQHandler(FUSB2_ID_VHUB_0); + } else if (vector == FUSB2_1_IRQ_NUM) { + USBH_IRQHandler(FUSB2_ID_1); + } else if (vector == FUSB2_2_IRQ_NUM) { + USBH_IRQHandler(FUSB2_ID_2); + } +} + +static void usb_hc_setup_pusb2_interrupt(u32 id) +{ + u32 cpu_id; + u32 irq_num = irq_nums[id]; + u32 irq_priority = 13U; + + GetCpuId(&cpu_id); + InterruptSetTargetCpus(irq_num, cpu_id); + + InterruptSetPriority(irq_num, irq_priority); + + /* register intr callback */ + InterruptInstall(irq_num, + usb_hc_pusb2_interrupt_handler, + NULL, + NULL); + + /* enable irq */ + InterruptUmask(irq_num); + + USB_LOG_DBG("Enable irq-%d\n", irq_num); +} + +static void usb_hc_revoke_pusb2_interrupt(u32 id) +{ + u32 irq_num = irq_nums[id]; + + /* disable irq */ + InterruptMask(irq_num); +} + +void usb_hc_low_level_init(struct usbh_bus *bus) +{ + if (memp_ref_cnt == 0) { + usb_sys_mem_init(); /* create memory pool before first bus init */ + } + + memp_ref_cnt++; /* one more bus is using the memory pool */ + + usb_hc_setup_pusb2_interrupt(bus->busid); +} + +void usb_hc_low_level_deinit(struct usbh_bus *bus) +{ + memp_ref_cnt--; /* one more bus is leaving */ + + if (memp_ref_cnt == 0) { + usb_sys_mem_deinit(); /* release memory pool after the last bus left */ + } + + usb_hc_revoke_pusb2_interrupt(bus->busid); +} + +unsigned long usb_hc_get_register_base(uint32_t id) +{ + if (id == FUSB2_ID_VHUB_0) { + return FUSB2_0_VHUB_BASE_ADDR; + } else if (id == FUSB2_ID_1) { + return FUSB2_1_BASE_ADDR; + } else if (id == FUSB2_ID_2) { + return FUSB2_2_BASE_ADDR; + } +} + +extern int vApplicationInIrq(void); +int xPortIsInsideInterrupt(void) +{ + return vApplicationInIrq(); +} \ No newline at end of file diff --git a/kernel/cherryusb/port/pusb2/rt-thread/usb_config.h b/kernel/cherryusb/port/pusb2/rt-thread/usb_config.h new file mode 100644 index 0000000..c7ebef8 --- /dev/null +++ b/kernel/cherryusb/port/pusb2/rt-thread/usb_config.h @@ -0,0 +1,266 @@ +/* + * Copyright : (C) 2024 Phytium Information Technology, Inc. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Modify History: + * Ver   Who        Date         Changes + * ----- ------     --------    -------------------------------------- + * 1.0 zhugengyu 2024/6/26 first commit + */ +#ifndef CHERRYUSB_CONFIG_H +#define CHERRYUSB_CONFIG_H + +#include "rtconfig.h" +#include + +/* ================ USB common Configuration ================ */ + +#define CONFIG_USB_PRINTF(...) rt_kprintf(__VA_ARGS__) + +void *usb_sys_mem_malloc(size_t size); +void usb_sys_mem_free(void *ptr); +void *usb_sys_malloc_align(size_t align, size_t size); + +#define usb_malloc(size) usb_sys_mem_malloc(size) +#define usb_free(ptr) usb_sys_mem_free(ptr) +#define usb_align(align, size) usb_sys_malloc_align(align, size) + +unsigned long usb_hc_get_register_base(uint32_t id); +unsigned long usb_dc_get_register_base(uint32_t id); + +#define CONFIG_USB_DBG_LEVEL USB_DBG_ERROR + +/* Enable print with color */ +#define CONFIG_USB_PRINTF_COLOR_ENABLE + +/* data align size when use dma */ +#ifndef CONFIG_USB_ALIGN_SIZE +#define CONFIG_USB_ALIGN_SIZE 4 +#endif + +/* attribute data into no cache ram */ +#define USB_NOCACHE_RAM_SECTION __attribute__((section(".noncacheable"))) + +/* ================= USB Device Stack Configuration ================ */ + +/* Ep0 in and out transfer buffer */ +#ifndef CONFIG_USBDEV_REQUEST_BUFFER_LEN +#define CONFIG_USBDEV_REQUEST_BUFFER_LEN 512 +#endif + +/* Setup packet log for debug */ +// #define CONFIG_USBDEV_SETUP_LOG_PRINT + +/* Send ep0 in data from user buffer instead of copying into ep0 reqdata + * Please note that user buffer must be aligned with CONFIG_USB_ALIGN_SIZE +*/ +// #define CONFIG_USBDEV_EP0_INDATA_NO_COPY + +/* Check if the input descriptor is correct */ +// #define CONFIG_USBDEV_DESC_CHECK + +/* Enable test mode */ +// #define CONFIG_USBDEV_TEST_MODE + +#ifndef CONFIG_USBDEV_MSC_MAX_LUN +#define CONFIG_USBDEV_MSC_MAX_LUN 1 +#endif + +#ifndef CONFIG_USBDEV_MSC_MAX_BUFSIZE +#define CONFIG_USBDEV_MSC_MAX_BUFSIZE 4096 +#endif + +#ifndef CONFIG_USBDEV_MSC_MANUFACTURER_STRING +#define CONFIG_USBDEV_MSC_MANUFACTURER_STRING "" +#endif + +#ifndef CONFIG_USBDEV_MSC_PRODUCT_STRING +#define CONFIG_USBDEV_MSC_PRODUCT_STRING "" +#endif + +#ifndef CONFIG_USBDEV_MSC_VERSION_STRING +#define CONFIG_USBDEV_MSC_VERSION_STRING "0.01" +#endif + +// #define CONFIG_USBDEV_MSC_THREAD + +#ifndef CONFIG_USBDEV_MSC_PRIO +#define CONFIG_USBDEV_MSC_PRIO 4 +#endif + +#ifndef CONFIG_USBDEV_MSC_STACKSIZE +#define CONFIG_USBDEV_MSC_STACKSIZE 8192 +#endif + +#ifndef CONFIG_USBDEV_RNDIS_RESP_BUFFER_SIZE +#define CONFIG_USBDEV_RNDIS_RESP_BUFFER_SIZE 156 +#endif + +/* rndis transfer buffer size, must be a multiple of (1536 + 44)*/ +#ifndef CONFIG_USBDEV_RNDIS_ETH_MAX_FRAME_SIZE +#define CONFIG_USBDEV_RNDIS_ETH_MAX_FRAME_SIZE 1580 +#endif + +#ifndef CONFIG_USBDEV_RNDIS_VENDOR_ID +#define CONFIG_USBDEV_RNDIS_VENDOR_ID 0x0000ffff +#endif + +#ifndef CONFIG_USBDEV_RNDIS_VENDOR_DESC +#define CONFIG_USBDEV_RNDIS_VENDOR_DESC "CherryUSB" +#endif + +#define CONFIG_USBDEV_RNDIS_USING_LWIP + +/* ================ USB HOST Stack Configuration ================== */ + +#define CONFIG_USBHOST_MAX_RHPORTS 1 +#define CONFIG_USBHOST_MAX_EXTHUBS 0 +#define CONFIG_USBHOST_MAX_EHPORTS 8 +#define CONFIG_USBHOST_MAX_INTERFACES 8 +#define CONFIG_USBHOST_MAX_INTF_ALTSETTINGS 8 +#define CONFIG_USBHOST_MAX_ENDPOINTS 8 + +#define CONFIG_USBHOST_MAX_CDC_ACM_CLASS 4 +#define CONFIG_USBHOST_MAX_HID_CLASS 4 +#define CONFIG_USBHOST_MAX_MSC_CLASS 2 +#define CONFIG_USBHOST_MAX_AUDIO_CLASS 1 +#define CONFIG_USBHOST_MAX_VIDEO_CLASS 1 + +#define CONFIG_USBHOST_DEV_NAMELEN 16 + +#ifndef CONFIG_USBHOST_PSC_PRIO +#define CONFIG_USBHOST_PSC_PRIO 0 +#endif +#ifndef CONFIG_USBHOST_PSC_STACKSIZE +#define CONFIG_USBHOST_PSC_STACKSIZE 8192 +#endif + +//#define CONFIG_USBHOST_GET_STRING_DESC + +// #define CONFIG_USBHOST_MSOS_ENABLE +#ifndef CONFIG_USBHOST_MSOS_VENDOR_CODE +#define CONFIG_USBHOST_MSOS_VENDOR_CODE 0x00 +#endif + +/* Ep0 max transfer buffer */ +#ifndef CONFIG_USBHOST_REQUEST_BUFFER_LEN +#define CONFIG_USBHOST_REQUEST_BUFFER_LEN 512 +#endif + +#ifndef CONFIG_USBHOST_CONTROL_TRANSFER_TIMEOUT +#define CONFIG_USBHOST_CONTROL_TRANSFER_TIMEOUT 500 +#endif + +#ifndef CONFIG_USBHOST_MSC_TIMEOUT +#define CONFIG_USBHOST_MSC_TIMEOUT 5000 +#endif + +/* This parameter affects usb performance, and depends on (TCP_WND)tcp eceive windows size, + * you can change to 2K ~ 16K and must be larger than TCP RX windows size in order to avoid being overflow. + */ +#ifndef CONFIG_USBHOST_RNDIS_ETH_MAX_RX_SIZE +#define CONFIG_USBHOST_RNDIS_ETH_MAX_RX_SIZE (2048) +#endif + +/* Because lwip do not support multi pbuf at a time, so increasing this variable has no performance improvement */ +#ifndef CONFIG_USBHOST_RNDIS_ETH_MAX_TX_SIZE +#define CONFIG_USBHOST_RNDIS_ETH_MAX_TX_SIZE (2048) +#endif + +/* This parameter affects usb performance, and depends on (TCP_WND)tcp eceive windows size, + * you can change to 2K ~ 16K and must be larger than TCP RX windows size in order to avoid being overflow. + */ +#ifndef CONFIG_USBHOST_CDC_NCM_ETH_MAX_RX_SIZE +#define CONFIG_USBHOST_CDC_NCM_ETH_MAX_RX_SIZE (2048) +#endif +/* Because lwip do not support multi pbuf at a time, so increasing this variable has no performance improvement */ +#ifndef CONFIG_USBHOST_CDC_NCM_ETH_MAX_TX_SIZE +#define CONFIG_USBHOST_CDC_NCM_ETH_MAX_TX_SIZE (2048) +#endif + +/* This parameter affects usb performance, and depends on (TCP_WND)tcp eceive windows size, + * you can change to 2K ~ 16K and must be larger than TCP RX windows size in order to avoid being overflow. + */ +#ifndef CONFIG_USBHOST_ASIX_ETH_MAX_RX_SIZE +#define CONFIG_USBHOST_ASIX_ETH_MAX_RX_SIZE (2048) +#endif +/* Because lwip do not support multi pbuf at a time, so increasing this variable has no performance improvement */ +#ifndef CONFIG_USBHOST_ASIX_ETH_MAX_TX_SIZE +#define CONFIG_USBHOST_ASIX_ETH_MAX_TX_SIZE (2048) +#endif + +/* This parameter affects usb performance, and depends on (TCP_WND)tcp eceive windows size, + * you can change to 2K ~ 16K and must be larger than TCP RX windows size in order to avoid being overflow. + */ +#ifndef CONFIG_USBHOST_RTL8152_ETH_MAX_RX_SIZE +#define CONFIG_USBHOST_RTL8152_ETH_MAX_RX_SIZE (2048) +#endif +/* Because lwip do not support multi pbuf at a time, so increasing this variable has no performance improvement */ +#ifndef CONFIG_USBHOST_RTL8152_ETH_MAX_TX_SIZE +#define CONFIG_USBHOST_RTL8152_ETH_MAX_TX_SIZE (2048) +#endif + +#define CONFIG_USBHOST_BLUETOOTH_HCI_H4 +// #define CONFIG_USBHOST_BLUETOOTH_HCI_LOG + +#ifndef CONFIG_USBHOST_BLUETOOTH_TX_SIZE +#define CONFIG_USBHOST_BLUETOOTH_TX_SIZE 2048 +#endif +#ifndef CONFIG_USBHOST_BLUETOOTH_RX_SIZE +#define CONFIG_USBHOST_BLUETOOTH_RX_SIZE 2048 +#endif + +/* ================ USB Device Port Configuration ================*/ + +#ifndef CONFIG_USBDEV_MAX_BUS +#define CONFIG_USBDEV_MAX_BUS 1 // for now, bus num must be 1 except hpm ip +#endif + +#ifndef CONFIG_USBDEV_EP_NUM +#define CONFIG_USBDEV_EP_NUM 8 +#endif + +/* ---------------- FSDEV Configuration ---------------- */ +//#define CONFIG_USBDEV_FSDEV_PMA_ACCESS 2 // maybe 1 or 2, many chips may have a difference + +/* ---------------- DWC2 Configuration ---------------- */ +/* (5 * number of control endpoints + 8) + ((largest USB packet used / 4) + 1 for + * status information) + (2 * number of OUT endpoints) + 1 for Global NAK + */ +// #define CONFIG_USB_DWC2_RXALL_FIFO_SIZE (1024 / 4) +/* IN Endpoints Max packet Size / 4 */ +// #define CONFIG_USB_DWC2_TX0_FIFO_SIZE (64 / 4) +// #define CONFIG_USB_DWC2_TX1_FIFO_SIZE (512 / 4) +// #define CONFIG_USB_DWC2_TX2_FIFO_SIZE (64 / 4) +// #define CONFIG_USB_DWC2_TX3_FIFO_SIZE (64 / 4) +// #define CONFIG_USB_DWC2_TX4_FIFO_SIZE (0 / 4) +// #define CONFIG_USB_DWC2_TX5_FIFO_SIZE (0 / 4) +// #define CONFIG_USB_DWC2_TX6_FIFO_SIZE (0 / 4) +// #define CONFIG_USB_DWC2_TX7_FIFO_SIZE (0 / 4) +// #define CONFIG_USB_DWC2_TX8_FIFO_SIZE (0 / 4) + +/* ---------------- MUSB Configuration ---------------- */ +// #define CONFIG_USB_MUSB_SUNXI + +/* ================ USB Host Port Configuration ==================*/ +#ifndef CONFIG_INPUT_MOUSE_WHEEL +#define CONFIG_INPUT_MOUSE_WHEEL +#endif + +#ifndef CONFIG_USBHOST_MAX_BUS +#define CONFIG_USBHOST_MAX_BUS 3 +#endif + +#ifndef CONFIG_USBHOST_PIPE_NUM +#define CONFIG_USBHOST_PIPE_NUM 10 +#endif + +/* ---------------- XHCI Configuration ---------------- */ +#define CONFIG_USB_XHCI_HCCR_OFFSET (0x0) + +/* ---------------- PUSB2 Configuration ---------------- */ +#define CONFIG_USB_PUSB2_BUS_NUM 3U +#define CONFIG_USB_PUSB2_BUS_ID 0U + +#endif diff --git a/kernel/cherryusb/port/pusb2/rt-thread/usb_dc_glue_phytium.c b/kernel/cherryusb/port/pusb2/rt-thread/usb_dc_glue_phytium.c new file mode 100644 index 0000000..49088d9 --- /dev/null +++ b/kernel/cherryusb/port/pusb2/rt-thread/usb_dc_glue_phytium.c @@ -0,0 +1,94 @@ +/* + * Copyright : (C) 2024 Phytium Information Technology, Inc. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Modify History: + * Ver   Who        Date         Changes + * ----- ------     --------    -------------------------------------- + * 1.0 zhugengyu 2024/6/26 first commit + */ +#include "rtthread.h" +#include "interrupt.h" + +#include "fparameters.h" + +#include "usbd_core.h" + +void USBD_IRQHandler(uint8_t busid); + +void usb_assert(const char *filename, int linenum) +{ + rt_assert_handler("", filename, linenum); +} + +static void usb_dc_pusb2_interrupt_handler(int irqno, void *param) +{ + USBD_IRQHandler(CONFIG_USB_PUSB2_BUS_ID); +} + +static void usb_dc_setup_pusb2_interrupt(uint32_t id) +{ + uint32_t irq_num = FUSB2_0_VHUB_IRQ_NUM; + + rt_hw_interrupt_set_priority(irq_num, 0U); + rt_hw_interrupt_install(irq_num, usb_dc_pusb2_interrupt_handler, NULL, "pusb2-dc"); + rt_hw_interrupt_umask(irq_num); +} + +static void usb_dc_revoke_pusb2_interrupt(uint32_t id) +{ + uint32_t irq_num = FUSB2_0_VHUB_IRQ_NUM; + + rt_hw_interrupt_mask(irq_num); +} + +unsigned long usb_dc_get_register_base(uint32_t id) +{ + USB_ASSERT(id == FUSB2_ID_VHUB_0); + return FUSB2_0_VHUB_BASE_ADDR; +} + +void usb_dc_low_level_init() +{ + usb_dc_setup_pusb2_interrupt(CONFIG_USB_PUSB2_BUS_ID); +} + +void usb_dc_low_level_deinit(void) +{ + usb_dc_revoke_pusb2_interrupt(CONFIG_USB_PUSB2_BUS_ID); +} + +void *usb_sys_mem_malloc(size_t size) +{ + void *buf = rt_malloc(size); + + if (buf) { + rt_memset(buf, 0, size); + } + + return buf; +} + +void usb_sys_mem_free(void *ptr) +{ + if (ptr) { + rt_free(ptr); + } +} + +void *usb_sys_malloc_align(size_t align, size_t size) +{ + void *buf = rt_malloc_align(size, align); + + if (buf) { + rt_memset(buf, 0, size); + } + + return buf; +} + +int usbd_set_remote_wakeup(uint8_t busid) +{ + return -1; +} \ No newline at end of file diff --git a/kernel/cherryusb/port/pusb2/rt-thread/usb_hc_glue_phytium.c b/kernel/cherryusb/port/pusb2/rt-thread/usb_hc_glue_phytium.c new file mode 100644 index 0000000..8dcca04 --- /dev/null +++ b/kernel/cherryusb/port/pusb2/rt-thread/usb_hc_glue_phytium.c @@ -0,0 +1,109 @@ +/* + * Copyright : (C) 2024 Phytium Information Technology, Inc. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Modify History: + * Ver   Who        Date         Changes + * ----- ------     --------    -------------------------------------- + * 1.0 zhugengyu 2024/6/26 first commit + */ +#include "rtthread.h" +#include "interrupt.h" + +#include "fparameters.h" + +#include "usbh_core.h" + +static const uint32_t irq_nums[] = { + FUSB2_0_VHUB_IRQ_NUM, FUSB2_1_IRQ_NUM, FUSB2_2_IRQ_NUM +}; + +void USBH_IRQHandler(uint8_t busid); + +void usb_assert(const char *filename, int linenum) +{ + rt_assert_handler("", filename, linenum); +} + +static void usb_hc_pusb2_interrupt_handler(int irqno, void *param) +{ + if (irqno == FUSB2_0_VHUB_IRQ_NUM) { + USBH_IRQHandler(FUSB2_ID_VHUB_0); + } else if (irqno == FUSB2_1_IRQ_NUM) { + USBH_IRQHandler(FUSB2_ID_1); + } else if (irqno == FUSB2_2_IRQ_NUM) { + USBH_IRQHandler(FUSB2_ID_2); + } +} + +static void usb_hc_setup_pusb2_interrupt(uint32_t id) +{ + uint32_t irq_num = irq_nums[id]; + + rt_hw_interrupt_set_priority(irq_num, 0U); + rt_hw_interrupt_install(irq_num, usb_hc_pusb2_interrupt_handler, NULL, "pusb2-hc"); + rt_hw_interrupt_umask(irq_num); + + USB_LOG_DBG("Enable irq-%d\n", irq_num); +} + +static void usb_hc_revoke_pusb2_interrupt(uint32_t id) +{ + uint32_t irq_num = irq_nums[id]; + + rt_hw_interrupt_mask(irq_num); +} + +unsigned long usb_hc_get_register_base(uint32_t id) +{ + if (id == FUSB2_ID_VHUB_0) { + return FUSB2_0_VHUB_BASE_ADDR; + } else if (id == FUSB2_ID_1) { + return FUSB2_1_BASE_ADDR; + } else if (id == FUSB2_ID_2) { + return FUSB2_2_BASE_ADDR; + } else { + USB_ASSERT(0); + return 0; + } +} + +void usb_hc_low_level_init(struct usbh_bus *bus) +{ + usb_hc_setup_pusb2_interrupt(bus->busid); +} + +void usb_hc_low_level_deinit(struct usbh_bus *bus) +{ + usb_hc_revoke_pusb2_interrupt(bus->busid); +} + +void *usb_sys_mem_malloc(size_t size) +{ + void *buf = rt_malloc(size); + + if (buf) { + rt_memset(buf, 0, size); + } + + return buf; +} + +void usb_sys_mem_free(void *ptr) +{ + if (ptr) { + rt_free(ptr); + } +} + +void *usb_sys_malloc_align(size_t align, size_t size) +{ + void *buf = rt_malloc_align(size, align); + + if (buf) { + rt_memset(buf, 0, size); + } + + return buf; +} \ No newline at end of file diff --git a/kernel/cherryusb/port/pusb2/standalone/usb_config.h b/kernel/cherryusb/port/pusb2/standalone/usb_config.h new file mode 100644 index 0000000..e4fbc4e --- /dev/null +++ b/kernel/cherryusb/port/pusb2/standalone/usb_config.h @@ -0,0 +1,275 @@ +/* + * Copyright : (C) 2024 Phytium Information Technology, Inc. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Modify History: + * Ver   Who        Date         Changes + * ----- ------     --------    -------------------------------------- + * 1.0 zhugengyu 2024/6/26 first commit + */ +#ifndef CHERRYUSB_CONFIG_H +#define CHERRYUSB_CONFIG_H + +#include "sdkconfig.h" + +/* ================ USB common Configuration ================ */ + +#define CONFIG_USB_PRINTF(...) printf(__VA_ARGS__) + +void *usb_sys_mem_malloc(size_t size); +void usb_sys_mem_free(void *ptr); +void *usb_sys_malloc_align(size_t align, size_t size); + +#define usb_malloc(size) usb_sys_mem_malloc(size) +#define usb_free(ptr) usb_sys_mem_free(ptr) +#define usb_align(align, size) usb_sys_malloc_align(align, size) + +unsigned long usb_dc_get_register_base(uint32_t id); + +size_t usb_osal_enter_critical_section(void); +void usb_osal_leave_critical_section(size_t flag); + +#ifndef CONFIG_USB_DBG_LEVEL +#if defined(CONFIG_LOG_ERROR) +#define CONFIG_USB_DBG_LEVEL USB_DBG_ERROR +#elif defined(CONFIG_LOG_WARN) +#define CONFIG_USB_DBG_LEVEL USB_DBG_WARNING +#elif defined(CONFIG_LOG_INFO) +#define CONFIG_USB_DBG_LEVEL USB_DBG_INFO +#elif defined(CONFIG_LOG_DEBUG) || defined(CONFIG_LOG_VERBOS) +#define CONFIG_USB_DBG_LEVEL USB_DBG_LOG +#else +#define CONFIG_USB_DBG_LEVEL USB_DBG_ERROR +#endif +#endif + +/* Enable print with color */ +#define CONFIG_USB_PRINTF_COLOR_ENABLE + +/* data align size when use dma */ +#ifndef CONFIG_USB_ALIGN_SIZE +#define CONFIG_USB_ALIGN_SIZE 4 +#endif + +/* attribute data into no cache ram */ +#define USB_NOCACHE_RAM_SECTION __attribute__((section(".noncacheable"))) + +/* ================= USB Device Stack Configuration ================ */ + +/* Ep0 in and out transfer buffer */ +#ifndef CONFIG_USBDEV_REQUEST_BUFFER_LEN +#define CONFIG_USBDEV_REQUEST_BUFFER_LEN 512 +#endif + +/* Setup packet log for debug */ +// #define CONFIG_USBDEV_SETUP_LOG_PRINT + +/* Send ep0 in data from user buffer instead of copying into ep0 reqdata + * Please note that user buffer must be aligned with CONFIG_USB_ALIGN_SIZE +*/ +// #define CONFIG_USBDEV_EP0_INDATA_NO_COPY + +/* Check if the input descriptor is correct */ +// #define CONFIG_USBDEV_DESC_CHECK + +/* Enable test mode */ +// #define CONFIG_USBDEV_TEST_MODE + +#ifndef CONFIG_USBDEV_MSC_MAX_LUN +#define CONFIG_USBDEV_MSC_MAX_LUN 1 +#endif + +#ifndef CONFIG_USBDEV_MSC_MAX_BUFSIZE +#define CONFIG_USBDEV_MSC_MAX_BUFSIZE 4096 +#endif + +#ifndef CONFIG_USBDEV_MSC_MANUFACTURER_STRING +#define CONFIG_USBDEV_MSC_MANUFACTURER_STRING "" +#endif + +#ifndef CONFIG_USBDEV_MSC_PRODUCT_STRING +#define CONFIG_USBDEV_MSC_PRODUCT_STRING "" +#endif + +#ifndef CONFIG_USBDEV_MSC_VERSION_STRING +#define CONFIG_USBDEV_MSC_VERSION_STRING "0.01" +#endif + +// #define CONFIG_USBDEV_MSC_THREAD + +#ifndef CONFIG_USBDEV_MSC_PRIO +#define CONFIG_USBDEV_MSC_PRIO 4 +#endif + +#ifndef CONFIG_USBDEV_MSC_STACKSIZE +#define CONFIG_USBDEV_MSC_STACKSIZE 2048 +#endif + +#ifndef CONFIG_USBDEV_RNDIS_RESP_BUFFER_SIZE +#define CONFIG_USBDEV_RNDIS_RESP_BUFFER_SIZE 156 +#endif + +/* rndis transfer buffer size, must be a multiple of (1536 + 44)*/ +#ifndef CONFIG_USBDEV_RNDIS_ETH_MAX_FRAME_SIZE +#define CONFIG_USBDEV_RNDIS_ETH_MAX_FRAME_SIZE 1580 +#endif + +#ifndef CONFIG_USBDEV_RNDIS_VENDOR_ID +#define CONFIG_USBDEV_RNDIS_VENDOR_ID 0x0000ffff +#endif + +#ifndef CONFIG_USBDEV_RNDIS_VENDOR_DESC +#define CONFIG_USBDEV_RNDIS_VENDOR_DESC "CherryUSB" +#endif + +#define CONFIG_USBDEV_RNDIS_USING_LWIP + +/* ================ USB HOST Stack Configuration ================== */ + +#define CONFIG_USBHOST_MAX_RHPORTS 1 +#define CONFIG_USBHOST_MAX_EXTHUBS 1 +#define CONFIG_USBHOST_MAX_EHPORTS 4 +#define CONFIG_USBHOST_MAX_INTERFACES 8 +#define CONFIG_USBHOST_MAX_INTF_ALTSETTINGS 8 +#define CONFIG_USBHOST_MAX_ENDPOINTS 4 + +#define CONFIG_USBHOST_MAX_CDC_ACM_CLASS 4 +#define CONFIG_USBHOST_MAX_HID_CLASS 4 +#define CONFIG_USBHOST_MAX_MSC_CLASS 2 +#define CONFIG_USBHOST_MAX_AUDIO_CLASS 1 +#define CONFIG_USBHOST_MAX_VIDEO_CLASS 1 + +#define CONFIG_USBHOST_DEV_NAMELEN 16 + +#ifndef CONFIG_USBHOST_PSC_PRIO +#define CONFIG_USBHOST_PSC_PRIO 0 +#endif +#ifndef CONFIG_USBHOST_PSC_STACKSIZE +#define CONFIG_USBHOST_PSC_STACKSIZE 8192 +#endif + +//#define CONFIG_USBHOST_GET_STRING_DESC + +// #define CONFIG_USBHOST_MSOS_ENABLE +#ifndef CONFIG_USBHOST_MSOS_VENDOR_CODE +#define CONFIG_USBHOST_MSOS_VENDOR_CODE 0x00 +#endif + +/* Ep0 max transfer buffer */ +#ifndef CONFIG_USBHOST_REQUEST_BUFFER_LEN +#define CONFIG_USBHOST_REQUEST_BUFFER_LEN 512 +#endif + +#ifndef CONFIG_USBHOST_CONTROL_TRANSFER_TIMEOUT +#define CONFIG_USBHOST_CONTROL_TRANSFER_TIMEOUT 500 +#endif + +#ifndef CONFIG_USBHOST_MSC_TIMEOUT +#define CONFIG_USBHOST_MSC_TIMEOUT 5000 +#endif + +/* This parameter affects usb performance, and depends on (TCP_WND)tcp eceive windows size, + * you can change to 2K ~ 16K and must be larger than TCP RX windows size in order to avoid being overflow. + */ +#ifndef CONFIG_USBHOST_RNDIS_ETH_MAX_RX_SIZE +#define CONFIG_USBHOST_RNDIS_ETH_MAX_RX_SIZE (2048) +#endif + +/* Because lwip do not support multi pbuf at a time, so increasing this variable has no performance improvement */ +#ifndef CONFIG_USBHOST_RNDIS_ETH_MAX_TX_SIZE +#define CONFIG_USBHOST_RNDIS_ETH_MAX_TX_SIZE (2048) +#endif + +/* This parameter affects usb performance, and depends on (TCP_WND)tcp eceive windows size, + * you can change to 2K ~ 16K and must be larger than TCP RX windows size in order to avoid being overflow. + */ +#ifndef CONFIG_USBHOST_CDC_NCM_ETH_MAX_RX_SIZE +#define CONFIG_USBHOST_CDC_NCM_ETH_MAX_RX_SIZE (2048) +#endif +/* Because lwip do not support multi pbuf at a time, so increasing this variable has no performance improvement */ +#ifndef CONFIG_USBHOST_CDC_NCM_ETH_MAX_TX_SIZE +#define CONFIG_USBHOST_CDC_NCM_ETH_MAX_TX_SIZE (2048) +#endif + +/* This parameter affects usb performance, and depends on (TCP_WND)tcp eceive windows size, + * you can change to 2K ~ 16K and must be larger than TCP RX windows size in order to avoid being overflow. + */ +#ifndef CONFIG_USBHOST_ASIX_ETH_MAX_RX_SIZE +#define CONFIG_USBHOST_ASIX_ETH_MAX_RX_SIZE (2048) +#endif +/* Because lwip do not support multi pbuf at a time, so increasing this variable has no performance improvement */ +#ifndef CONFIG_USBHOST_ASIX_ETH_MAX_TX_SIZE +#define CONFIG_USBHOST_ASIX_ETH_MAX_TX_SIZE (2048) +#endif + +/* This parameter affects usb performance, and depends on (TCP_WND)tcp eceive windows size, + * you can change to 2K ~ 16K and must be larger than TCP RX windows size in order to avoid being overflow. + */ +#ifndef CONFIG_USBHOST_RTL8152_ETH_MAX_RX_SIZE +#define CONFIG_USBHOST_RTL8152_ETH_MAX_RX_SIZE (2048) +#endif +/* Because lwip do not support multi pbuf at a time, so increasing this variable has no performance improvement */ +#ifndef CONFIG_USBHOST_RTL8152_ETH_MAX_TX_SIZE +#define CONFIG_USBHOST_RTL8152_ETH_MAX_TX_SIZE (2048) +#endif + +#define CONFIG_USBHOST_BLUETOOTH_HCI_H4 +// #define CONFIG_USBHOST_BLUETOOTH_HCI_LOG + +#ifndef CONFIG_USBHOST_BLUETOOTH_TX_SIZE +#define CONFIG_USBHOST_BLUETOOTH_TX_SIZE 2048 +#endif +#ifndef CONFIG_USBHOST_BLUETOOTH_RX_SIZE +#define CONFIG_USBHOST_BLUETOOTH_RX_SIZE 2048 +#endif + +/* ================ USB Device Port Configuration ================*/ + +#ifndef CONFIG_USBDEV_MAX_BUS +#define CONFIG_USBDEV_MAX_BUS 1 // for now, bus num must be 1 except hpm ip +#endif + +#ifndef CONFIG_USBDEV_EP_NUM +#define CONFIG_USBDEV_EP_NUM 8 +#endif + +/* ---------------- FSDEV Configuration ---------------- */ +//#define CONFIG_USBDEV_FSDEV_PMA_ACCESS 2 // maybe 1 or 2, many chips may have a difference + +/* ---------------- DWC2 Configuration ---------------- */ +/* (5 * number of control endpoints + 8) + ((largest USB packet used / 4) + 1 for + * status information) + (2 * number of OUT endpoints) + 1 for Global NAK + */ +// #define CONFIG_USB_DWC2_RXALL_FIFO_SIZE (1024 / 4) +/* IN Endpoints Max packet Size / 4 */ +// #define CONFIG_USB_DWC2_TX0_FIFO_SIZE (64 / 4) +// #define CONFIG_USB_DWC2_TX1_FIFO_SIZE (512 / 4) +// #define CONFIG_USB_DWC2_TX2_FIFO_SIZE (64 / 4) +// #define CONFIG_USB_DWC2_TX3_FIFO_SIZE (64 / 4) +// #define CONFIG_USB_DWC2_TX4_FIFO_SIZE (0 / 4) +// #define CONFIG_USB_DWC2_TX5_FIFO_SIZE (0 / 4) +// #define CONFIG_USB_DWC2_TX6_FIFO_SIZE (0 / 4) +// #define CONFIG_USB_DWC2_TX7_FIFO_SIZE (0 / 4) +// #define CONFIG_USB_DWC2_TX8_FIFO_SIZE (0 / 4) + +/* ---------------- MUSB Configuration ---------------- */ +// #define CONFIG_USB_MUSB_SUNXI + +/* ================ USB Host Port Configuration ==================*/ +#ifndef CONFIG_USBHOST_MAX_BUS +#define CONFIG_USBHOST_MAX_BUS 1 +#endif + +#ifndef CONFIG_USBHOST_PIPE_NUM +#define CONFIG_USBHOST_PIPE_NUM 10 +#endif + +/* ---------------- XHCI Configuration ---------------- */ +#define CONFIG_USB_XHCI_HCCR_OFFSET (0x0) + +/* ---------------- PUSB2 Configuration ---------------- */ +#define CONFIG_USB_PUSB2_BUS_NUM 1U +#define CONFIG_USB_PUSB2_BUS_ID 0U + +#endif diff --git a/kernel/cherryusb/port/pusb2/standalone/usb_dc_glue_phytium.c b/kernel/cherryusb/port/pusb2/standalone/usb_dc_glue_phytium.c new file mode 100644 index 0000000..06016f9 --- /dev/null +++ b/kernel/cherryusb/port/pusb2/standalone/usb_dc_glue_phytium.c @@ -0,0 +1,144 @@ +/* + * Copyright : (C) 2024 Phytium Information Technology, Inc. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Modify History: + * Ver   Who        Date         Changes + * ----- ------     --------    -------------------------------------- + * 1.0 zhugengyu 2024/6/26 first commit + */ +/***************************** Include Files *********************************/ +#include +#include + +#include "fassert.h" +#include "fparameters.h" +#include "finterrupt.h" +#include "fcpu_info.h" +#include "fdebug.h" +#include "fcache.h" +#include "fmemory_pool.h" + +#include "usbd_core.h" + +/************************** Constant Definitions *****************************/ +#define USB_MEMP_TOTAL_SIZE SZ_1M + +/**************************** Type Definitions *******************************/ +void USBD_IRQHandler(uint8_t busid); + +/************************** Variable Definitions *****************************/ +static FMemp memp; +static u8 memp_buf[USB_MEMP_TOTAL_SIZE] __attribute__((aligned(8))) = {0}; + +static void usb_sys_mem_init(void) +{ + if (FT_COMPONENT_IS_READY != memp.is_ready) + { + USB_ASSERT(FT_SUCCESS == FMempInit(&memp, &memp_buf[0], &memp_buf[0] + USB_MEMP_TOTAL_SIZE)); + } +} + +static void usb_sys_mem_deinit(void) +{ + if (FT_COMPONENT_IS_READY == memp.is_ready) + { + FMempRemove(&memp); + } +} + +void *usb_sys_malloc_align(size_t align, size_t size) +{ + void *result = FMempMallocAlign(&memp, size, align); + + if (result) + { + memset(result, 0U, size); + } + + return result; +} + +void *usb_sys_mem_malloc(size_t size) +{ + return usb_sys_malloc_align(sizeof(void *), size); +} + +void usb_sys_mem_free(void *ptr) +{ + if (NULL != ptr) + { + FMempFree(&memp, ptr); + } +} + +void usb_assert(const char *filename, int linenum) +{ + FAssert(filename, linenum, 0xff); +} + +static void usb_dc_pusb2_interrupt_handler(s32 vector, void *param) +{ + USBD_IRQHandler(CONFIG_USB_PUSB2_BUS_ID); +} + +static void usb_dc_setup_pusb2_interrupt(u32 id) +{ + u32 cpu_id; + USB_ASSERT(id == FUSB2_ID_VHUB_0); + u32 irq_num = FUSB2_0_VHUB_IRQ_NUM; + u32 irq_priority = 0U; + + GetCpuId(&cpu_id); + InterruptSetTargetCpus(irq_num, cpu_id); + + InterruptSetPriority(irq_num, irq_priority); + + /* register intr callback */ + InterruptInstall(irq_num, + usb_dc_pusb2_interrupt_handler, + NULL, + NULL); + + /* enable irq */ + InterruptUmask(irq_num); +} + +static void usb_dc_revoke_pusb2_interrupt(u32 id) +{ + USB_ASSERT(id == FUSB2_ID_VHUB_0); + u32 irq_num = FUSB2_0_VHUB_IRQ_NUM; + + /* disable irq */ + InterruptMask(irq_num); +} + +unsigned long usb_dc_get_register_base(uint32_t id) +{ + USB_ASSERT(id == FUSB2_ID_VHUB_0); + return FUSB2_0_VHUB_BASE_ADDR; +} + +/* implement cherryusb weak functions */ +void usb_dc_low_level_init() +{ + usb_sys_mem_init(); + usb_dc_setup_pusb2_interrupt(CONFIG_USB_PUSB2_BUS_ID); +} + +void usb_dc_low_level_deinit(void) +{ + usb_sys_mem_deinit(); + usb_dc_revoke_pusb2_interrupt(CONFIG_USB_PUSB2_BUS_ID); +} + +size_t usb_osal_enter_critical_section(void) +{ + return 0; +} + +void usb_osal_leave_critical_section(size_t flag) +{ + +} \ No newline at end of file diff --git a/kernel/cherryusb/port/rp2040/README.md b/kernel/cherryusb/port/rp2040/README.md new file mode 100644 index 0000000..64887e3 --- /dev/null +++ b/kernel/cherryusb/port/rp2040/README.md @@ -0,0 +1,5 @@ +# Note + +## Support Chip List + +- RP2040/RP2350 \ No newline at end of file diff --git a/kernel/cherryusb/port/rp2040/usb_dc_rp2040.c b/kernel/cherryusb/port/rp2040/usb_dc_rp2040.c new file mode 100644 index 0000000..5243341 --- /dev/null +++ b/kernel/cherryusb/port/rp2040/usb_dc_rp2040.c @@ -0,0 +1,595 @@ +/* + * Copyright (c) 2022, HaiMianBBao + * Copyright (c) 2025, sakumisu + * + * SPDX-License-Identifier: Apache-2.0 + */ +#include "usbd_core.h" +#include "hardware/resets.h" +#include "hardware/irq.h" +#include "hardware/structs/usb.h" +#if CHERRYUSB_OPT_RP2040_USB_DEVICE_ENUMERATION_FIX +#include "pico/fix/rp2040_usb_device_enumeration.h" +#endif + +#define usb_hw_set hw_set_alias(usb_hw) +#define usb_hw_clear hw_clear_alias(usb_hw) + +#ifndef FORCE_VBUS_DETECT +#define FORCE_VBUS_DETECT 1 +#endif + +/* Endpoint state */ +struct rp2040_ep_state { + uint16_t ep_mps; /* Endpoint max packet size */ + uint8_t ep_type; /* Endpoint type */ + uint8_t ep_stalled; /* Endpoint stall flag */ + uint8_t ep_enable; /* Endpoint enable */ + uint8_t ep_addr; /* Endpoint address */ + uint8_t *xfer_buf; + uint32_t xfer_len; + uint32_t actual_xfer_len; + + volatile uint32_t *endpoint_control; /*!< Endpoint control register */ + volatile uint32_t *buffer_control; /*!< Buffer control register */ + uint8_t *data_buffer; /*!< Buffer pointer in usb dpram */ + uint8_t next_pid; /*!< Toggle after each packet (unless replying to a SETUP) */ +}; + +/* Driver state */ +struct rp2040_udc { + volatile uint8_t dev_addr; + struct rp2040_ep_state in_ep[USB_NUM_ENDPOINTS]; /*!< IN endpoint parameters*/ + struct rp2040_ep_state out_ep[USB_NUM_ENDPOINTS]; /*!< OUT endpoint parameters */ + struct usb_setup_packet setup; /*!< Setup package that may be used in interrupt processing (outside the protocol stack) */ +} g_rp2040_udc; + +void rp2040_usbd_irq(void); + +/** + * @brief Take a buffer pointer located in the USB RAM and return as an offset of the RAM. + * + * @param buf + * @return uint32_t + */ +static inline uint32_t usb_buffer_offset(volatile uint8_t *buf) +{ + return (uint32_t)buf ^ (uint32_t)usb_dpram; +} + +/** + * @brief Set up the endpoint control register for an endpoint (if applicable. Not valid for EP0). + * + * @param ep + */ +void usb_setup_endpoint(const struct rp2040_ep_state *ep) +{ + // EP0 doesn't have one so return if that is the case + if (!ep->endpoint_control) { + return; + } + + // Get the data buffer as an offset of the USB controller's DPRAM + uint32_t dpram_offset = usb_buffer_offset(ep->data_buffer); + uint32_t reg = EP_CTRL_ENABLE_BITS | + EP_CTRL_INTERRUPT_PER_BUFFER | + (ep->ep_type << EP_CTRL_BUFFER_TYPE_LSB) | + dpram_offset; + *ep->endpoint_control = reg; +} + +/** + * @brief Starts a transfer on a given endpoint. + * + * @param ep, the endpoint configuration. + * @param buf, the data buffer to send. Only applicable if the endpoint is TX + * @param len, the length of the data in buf (this example limits max len to one packet - 64 bytes) + */ +static void usb_start_transfer(struct rp2040_ep_state *ep, uint8_t *buf, uint16_t len) +{ + /*!< Prepare buffer control register value */ + uint32_t val = len | USB_BUF_CTRL_AVAIL; + + if (len < ep->ep_mps) { + val |= USB_BUF_CTRL_LAST; + } + + if (USB_EP_DIR_IS_IN(ep->ep_addr)) { + /*!< Need to copy the data from the user buffer to the usb memory */ + if (buf != NULL) { + memcpy((void *)ep->data_buffer, (void *)buf, len); + } + /*!< Mark as full */ + val |= USB_BUF_CTRL_FULL; + } + + /*!< Set pid and flip for next transfer */ + val |= ep->next_pid ? USB_BUF_CTRL_DATA1_PID : USB_BUF_CTRL_DATA0_PID; + ep->next_pid ^= 1u; + + *ep->buffer_control = val; +} + +int usb_dc_init(uint8_t busid) +{ + uint8_t *next_buffer_ptr; + + memset(&g_rp2040_udc, 0, sizeof(struct rp2040_udc)); + + g_rp2040_udc.in_ep[0].endpoint_control = NULL; + g_rp2040_udc.in_ep[0].data_buffer = &usb_dpram->ep0_buf_a[0]; + g_rp2040_udc.out_ep[0].endpoint_control = NULL; + g_rp2040_udc.out_ep[0].data_buffer = &usb_dpram->ep0_buf_a[0]; + + for (uint32_t i = 0; i < USB_NUM_ENDPOINTS; i++) { + g_rp2040_udc.in_ep[i].buffer_control = &usb_dpram->ep_buf_ctrl[i].in; + g_rp2040_udc.out_ep[i].buffer_control = &usb_dpram->ep_buf_ctrl[i].out; + + if (i != 0) { + g_rp2040_udc.in_ep[i].endpoint_control = &usb_dpram->ep_ctrl[i - 1].in; + g_rp2040_udc.out_ep[i].endpoint_control = &usb_dpram->ep_ctrl[i - 1].out; + } + } + + next_buffer_ptr = &usb_dpram->epx_data[0]; + + for (uint32_t i = 1; i < USB_NUM_ENDPOINTS; i++) { + g_rp2040_udc.in_ep[i].data_buffer = next_buffer_ptr; + if (i == 1) { + next_buffer_ptr += 1024; /* for iso video */ + } else { + next_buffer_ptr += 64; + } + + g_rp2040_udc.out_ep[i].data_buffer = next_buffer_ptr; + next_buffer_ptr += 64; + } + + // Remove shared irq if it was previously added so as not to fill up shared irq slots + irq_remove_handler(USBCTRL_IRQ, rp2040_usbd_irq); + + irq_add_shared_handler(USBCTRL_IRQ, rp2040_usbd_irq, PICO_SHARED_IRQ_HANDLER_HIGHEST_ORDER_PRIORITY); + + // Reset usb controller + reset_unreset_block_num_wait_blocking(RESET_USBCTRL); + + /*!< Clear any previous state just in case */ + memset(usb_hw, 0, sizeof(*usb_hw)); + memset(usb_dpram, 0, sizeof(*usb_dpram)); + + /*!< Mux the controller to the onboard usb phy */ + usb_hw->muxing = USB_USB_MUXING_TO_PHY_BITS | USB_USB_MUXING_SOFTCON_BITS; + +#if FORCE_VBUS_DETECT + // Force VBUS detect so the device thinks it is plugged into a host + usb_hw->pwr = USB_USB_PWR_VBUS_DETECT_BITS | USB_USB_PWR_VBUS_DETECT_OVERRIDE_EN_BITS; +#endif + + // Enable the USB controller in device mode. + usb_hw->main_ctrl = USB_MAIN_CTRL_CONTROLLER_EN_BITS; + + // Enable an interrupt per EP0 transaction + usb_hw->sie_ctrl = USB_SIE_CTRL_EP0_INT_1BUF_BITS; // <2> + + // Enable interrupts for when a buffer is done, when the bus is reset, + // and when a setup packet is received + usb_hw->inte = USB_INTS_BUFF_STATUS_BITS | USB_INTS_BUS_RESET_BITS | USB_INTS_SETUP_REQ_BITS | + USB_INTS_DEV_SUSPEND_BITS | USB_INTS_DEV_RESUME_FROM_HOST_BITS | + (FORCE_VBUS_DETECT ? 0 : USB_INTS_DEV_CONN_DIS_BITS); + +#ifdef CONFIG_USBDEV_SOF_ENABLE + usb_hw->inte |= USB_INTS_DEV_SOF_BITS; +#endif + + // Enable USB interrupt at processor + irq_set_enabled(USBCTRL_IRQ, true); + + usb_hw_set->sie_ctrl = USB_SIE_CTRL_PULLUP_EN_BITS; + return 0; +} + +int usb_dc_deinit(uint8_t busid) +{ + irq_set_enabled(USBCTRL_IRQ, false); + // Remove shared irq if it was previously added so as not to fill up shared irq slots + irq_remove_handler(USBCTRL_IRQ, rp2040_usbd_irq); + + usb_hw_clear->sie_ctrl = USB_SIE_CTRL_PULLUP_EN_BITS; + memset(&g_rp2040_udc, 0, sizeof(struct rp2040_udc)); + + return 0; +} + +int usbd_set_address(uint8_t busid, const uint8_t addr) +{ + g_rp2040_udc.dev_addr = addr; + return 0; +} + +int usbd_set_remote_wakeup(uint8_t busid) +{ + return -1; +} + +uint8_t usbd_get_port_speed(uint8_t busid) +{ + return USB_SPEED_FULL; +} + +int usbd_ep_open(uint8_t busid, const struct usb_endpoint_descriptor *ep) +{ + uint8_t ep_idx = USB_EP_GET_IDX(ep->bEndpointAddress); + + if (USB_EP_DIR_IS_OUT(ep->bEndpointAddress)) { + g_rp2040_udc.out_ep[ep_idx].ep_mps = USB_GET_MAXPACKETSIZE(ep->wMaxPacketSize); + g_rp2040_udc.out_ep[ep_idx].ep_type = USB_GET_ENDPOINT_TYPE(ep->bmAttributes); + g_rp2040_udc.out_ep[ep_idx].ep_addr = ep->bEndpointAddress; + g_rp2040_udc.out_ep[ep_idx].ep_enable = true; + /*!< Clear control reg */ + *(g_rp2040_udc.out_ep[ep_idx].buffer_control) = 0; + + usb_setup_endpoint(&g_rp2040_udc.out_ep[ep_idx]); + } else { + g_rp2040_udc.in_ep[ep_idx].ep_mps = USB_GET_MAXPACKETSIZE(ep->wMaxPacketSize); + g_rp2040_udc.in_ep[ep_idx].ep_type = USB_GET_ENDPOINT_TYPE(ep->bmAttributes); + g_rp2040_udc.in_ep[ep_idx].ep_addr = ep->bEndpointAddress; + g_rp2040_udc.in_ep[ep_idx].ep_enable = true; + /*!< Clear control reg */ + *(g_rp2040_udc.in_ep[ep_idx].buffer_control) = 0; + + usb_setup_endpoint(&g_rp2040_udc.in_ep[ep_idx]); + } + return 0; +} + +int usbd_ep_close(uint8_t busid, const uint8_t ep) +{ + if (USB_EP_DIR_IS_IN(ep)) { + } else if (USB_EP_DIR_IS_OUT(ep)) { + } + return 0; +} + +int usbd_ep_set_stall(uint8_t busid, const uint8_t ep) +{ + if (USB_EP_GET_IDX(ep) == 0) { + /** + * A stall on EP0 has to be armed so it can be cleared on the next setup packet + */ + usb_hw_set->ep_stall_arm = (USB_EP_DIR_IS_IN(ep)) ? USB_EP_STALL_ARM_EP0_IN_BITS : USB_EP_STALL_ARM_EP0_OUT_BITS; + } + + if (USB_EP_DIR_IS_OUT(ep)) { + *(g_rp2040_udc.out_ep[USB_EP_GET_IDX(ep)].buffer_control) = USB_BUF_CTRL_STALL; + } else { + *(g_rp2040_udc.in_ep[USB_EP_GET_IDX(ep)].buffer_control) = USB_BUF_CTRL_STALL; + } + + return 0; +} + +int usbd_ep_clear_stall(uint8_t busid, const uint8_t ep) +{ + uint8_t ep_idx = USB_EP_GET_IDX(ep); + + if (ep_idx != 0) { + if (USB_EP_DIR_IS_OUT(ep)) { + g_rp2040_udc.out_ep[USB_EP_GET_IDX(ep)].next_pid = 0; + *(g_rp2040_udc.out_ep[USB_EP_GET_IDX(ep)].buffer_control) = ~USB_BUF_CTRL_STALL; + } else { + g_rp2040_udc.in_ep[USB_EP_GET_IDX(ep)].next_pid = 0; + *(g_rp2040_udc.in_ep[USB_EP_GET_IDX(ep)].buffer_control) = ~USB_BUF_CTRL_STALL; + } + } + return 0; +} + +int usbd_ep_is_stalled(uint8_t busid, const uint8_t ep, uint8_t *stalled) +{ + if (USB_EP_DIR_IS_OUT(ep)) { + if (*(g_rp2040_udc.out_ep[USB_EP_GET_IDX(ep)].buffer_control) & USB_BUF_CTRL_STALL) { + *stalled = 1; + } else { + *stalled = 0; + } + } else { + if (*(g_rp2040_udc.in_ep[USB_EP_GET_IDX(ep)].buffer_control) & USB_BUF_CTRL_STALL) { + *stalled = 1; + } else { + *stalled = 0; + } + } + return 0; +} + +int usbd_ep_start_write(uint8_t busid, const uint8_t ep, const uint8_t *data, uint32_t data_len) +{ + uint8_t ep_idx = USB_EP_GET_IDX(ep); + + if (!data && data_len) { + return -1; + } + if (!g_rp2040_udc.in_ep[ep_idx].ep_enable) { + return -2; + } + + g_rp2040_udc.in_ep[ep_idx].xfer_buf = (uint8_t *)data; + g_rp2040_udc.in_ep[ep_idx].xfer_len = data_len; + g_rp2040_udc.in_ep[ep_idx].actual_xfer_len = 0; + + if (data_len == 0) { + usb_start_transfer(&g_rp2040_udc.in_ep[ep_idx], NULL, 0); + } else { + data_len = MIN(data_len, g_rp2040_udc.in_ep[ep_idx].ep_mps); + usb_start_transfer(&g_rp2040_udc.in_ep[ep_idx], g_rp2040_udc.in_ep[ep_idx].xfer_buf, data_len); + } + + return 0; +} + +int usbd_ep_start_read(uint8_t busid, const uint8_t ep, uint8_t *data, uint32_t data_len) +{ + uint8_t ep_idx = USB_EP_GET_IDX(ep); + + if (!data && data_len) { + return -1; + } + if (!g_rp2040_udc.out_ep[ep_idx].ep_enable) { + return -2; + } + g_rp2040_udc.out_ep[ep_idx].xfer_buf = (uint8_t *)data; + g_rp2040_udc.out_ep[ep_idx].xfer_len = data_len; + g_rp2040_udc.out_ep[ep_idx].actual_xfer_len = 0; + + if (data_len == 0) { + usb_start_transfer(&g_rp2040_udc.out_ep[ep_idx], NULL, 0); + } else { + /*!< Not zlp */ + data_len = MIN(data_len, g_rp2040_udc.out_ep[ep_idx].ep_mps); + usb_start_transfer(&g_rp2040_udc.out_ep[ep_idx], g_rp2040_udc.out_ep[ep_idx].xfer_buf, data_len); + } + return 0; +} + +/** + * @brief Notify an endpoint that a transfer has completed. + * + * @param ep, the endpoint to notify. + */ +static void usb_handle_ep_buff_done(struct rp2040_ep_state *ep) +{ + uint32_t buffer_control = *ep->buffer_control; + /*!< Get the transfer length for this endpoint */ + uint16_t read_count = buffer_control & USB_BUF_CTRL_LEN_MASK; + /*!< Call that endpoints buffer done handler */ + if (ep->ep_addr == 0x80) { + /*!< EP0 In */ + /** + * Determine the current setup direction + */ + switch (g_rp2040_udc.setup.bmRequestType >> USB_REQUEST_DIR_SHIFT) { + case 1: + /*!< Get */ + if (g_rp2040_udc.in_ep[0].xfer_len > g_rp2040_udc.in_ep[0].ep_mps) { + g_rp2040_udc.in_ep[0].xfer_len -= g_rp2040_udc.in_ep[0].ep_mps; + g_rp2040_udc.in_ep[0].actual_xfer_len += g_rp2040_udc.in_ep[0].ep_mps; + usbd_event_ep_in_complete_handler(0, 0 | 0x80, g_rp2040_udc.in_ep[0].actual_xfer_len); + } else { + g_rp2040_udc.in_ep[0].actual_xfer_len += g_rp2040_udc.in_ep[0].xfer_len; + g_rp2040_udc.in_ep[0].xfer_len = 0; + /** + * EP0 In complete and host will send a out token to get 0 length packet + * In the next usbd_event_ep_in_complete_handler, stack will start read 0 length packet + * and host must send data1 packet.We resest the ep0 next_pid = 1 in setup interrupt head. + */ + usbd_event_ep_in_complete_handler(0, 0 | 0x80, g_rp2040_udc.in_ep[0].actual_xfer_len); + } + break; + case 0: + /*!< Set */ + if (g_rp2040_udc.dev_addr > 0) { + usb_hw->dev_addr_ctrl = g_rp2040_udc.dev_addr; + g_rp2040_udc.dev_addr = 0; + } else { + /*!< Normal status stage // Setup out...out in */ + /** + * Perpar for next setup + */ + } + break; + } + + } else if (ep->ep_addr == 0x00) { + /*!< EP0 Out */ + memcpy(g_rp2040_udc.out_ep[0].xfer_buf, g_rp2040_udc.out_ep[0].data_buffer, read_count); + if (read_count == 0) { + /*!< Normal status stage // Setup in...in out */ + /** + * Perpar for next setup + */ + } + + g_rp2040_udc.out_ep[0].actual_xfer_len += read_count; + g_rp2040_udc.out_ep[0].xfer_len -= read_count; + + usbd_event_ep_out_complete_handler(0, 0x00, g_rp2040_udc.out_ep[0].actual_xfer_len); + } else { + /*!< Others ep */ + uint16_t data_len = 0; + if (USB_EP_DIR_IS_OUT(ep->ep_addr)) { + /*!< flip the pid */ + memcpy(g_rp2040_udc.out_ep[(ep->ep_addr) & 0x0f].xfer_buf, g_rp2040_udc.out_ep[(ep->ep_addr) & 0x0f].data_buffer, read_count); + g_rp2040_udc.out_ep[(ep->ep_addr) & 0x0f].xfer_buf += read_count; + g_rp2040_udc.out_ep[(ep->ep_addr) & 0x0f].actual_xfer_len += read_count; + g_rp2040_udc.out_ep[(ep->ep_addr) & 0x0f].xfer_len -= read_count; + + if (read_count < g_rp2040_udc.out_ep[(ep->ep_addr) & 0x0f].ep_mps || g_rp2040_udc.out_ep[(ep->ep_addr) & 0x0f].xfer_len == 0) { + /*!< Out complete */ + usbd_event_ep_out_complete_handler(0, ep->ep_addr, g_rp2040_udc.out_ep[(ep->ep_addr) & 0x0f].actual_xfer_len); + } else { + /*!< Need read again */ + data_len = MIN(g_rp2040_udc.out_ep[(ep->ep_addr) & 0x0f].xfer_len, g_rp2040_udc.out_ep[(ep->ep_addr) & 0x0f].ep_mps); + usb_start_transfer(&g_rp2040_udc.out_ep[(ep->ep_addr) & 0x0f], NULL, data_len); + } + } else { + if (g_rp2040_udc.in_ep[(ep->ep_addr) & 0x0f].xfer_len > g_rp2040_udc.in_ep[(ep->ep_addr) & 0x0f].ep_mps) { + /*!< Need tx again */ + g_rp2040_udc.in_ep[(ep->ep_addr) & 0x0f].xfer_len -= g_rp2040_udc.in_ep[(ep->ep_addr) & 0x0f].ep_mps; + g_rp2040_udc.in_ep[(ep->ep_addr) & 0x0f].xfer_buf += g_rp2040_udc.in_ep[(ep->ep_addr) & 0x0f].ep_mps; + g_rp2040_udc.in_ep[(ep->ep_addr) & 0x0f].actual_xfer_len += g_rp2040_udc.in_ep[(ep->ep_addr) & 0x0f].ep_mps; + data_len = MIN(g_rp2040_udc.in_ep[(ep->ep_addr) & 0x0f].xfer_len, g_rp2040_udc.in_ep[(ep->ep_addr) & 0x0f].ep_mps); + usb_start_transfer(&g_rp2040_udc.in_ep[(ep->ep_addr) & 0x0f], g_rp2040_udc.in_ep[(ep->ep_addr) & 0x0f].xfer_buf, data_len); + } else { + /*!< In complete */ + g_rp2040_udc.in_ep[(ep->ep_addr) & 0x0f].actual_xfer_len += g_rp2040_udc.in_ep[(ep->ep_addr) & 0x0f].xfer_len; + g_rp2040_udc.in_ep[(ep->ep_addr) & 0x0f].xfer_len = 0; + usbd_event_ep_in_complete_handler(0, ep->ep_addr, g_rp2040_udc.in_ep[(ep->ep_addr) & 0x0f].actual_xfer_len); + } + } + } +} + +/** + * @brief Find the endpoint configuration for a specified endpoint number and + * direction and notify it that a transfer has completed. + * + * @param ep_num + * @param in + */ +static void usb_handle_buff_done(uint8_t ep_num, bool in) +{ + uint8_t ep_addr = ep_num | (in ? USB_EP_DIR_IN : 0); + if (USB_EP_DIR_IS_OUT(ep_addr)) { + usb_handle_ep_buff_done(&g_rp2040_udc.out_ep[ep_num]); + } else { + usb_handle_ep_buff_done(&g_rp2040_udc.in_ep[ep_num]); + } +} + +/** + * @brief Handle a "buffer status" irq. This means that one or more + * buffers have been sent / received. Notify each endpoint where this + * is the case. + */ +static void usb_handle_buff_status(void) +{ + uint32_t remaining_buffers = usb_hw->buf_status; + + uint32_t bit = 1u; + for (uint8_t i = 0; remaining_buffers && i < USB_NUM_ENDPOINTS * 2; i++) { + if (remaining_buffers & bit) { + /*!< clear this in advance */ + usb_hw_clear->buf_status = bit; + /*!< IN transfer for even i, OUT transfer for odd i */ + usb_handle_buff_done(i >> 1u, !(i & 1u)); + remaining_buffers &= ~bit; + } + bit <<= 1u; + } +} + +void USBD_IRQHandler(uint8_t busid) +{ + uint32_t const status = usb_hw->ints; + uint32_t handled = 0; + + if (status & USB_INTS_BUFF_STATUS_BITS) { + handled |= USB_INTS_BUFF_STATUS_BITS; + usb_handle_buff_status(); + } + + if (status & USB_INTS_SETUP_REQ_BITS) { + handled |= USB_INTS_SETUP_REQ_BITS; + memcpy((uint8_t *)&g_rp2040_udc.setup, (uint8_t const *)&usb_dpram->setup_packet, 8); + /** + * reset pid to both 1 (data and ack) + */ + g_rp2040_udc.in_ep[0].next_pid = 1; + g_rp2040_udc.out_ep[0].next_pid = 1; + usbd_event_ep0_setup_complete_handler(0, (uint8_t *)&g_rp2040_udc.setup); + usb_hw_clear->sie_status = USB_SIE_STATUS_SETUP_REC_BITS; + } + +#if FORCE_VBUS_DETECT == 0 + /** + * Since we force VBUS detect On, device will always think it is connected and + * couldn't distinguish between disconnect and suspend + */ + if (status & USB_INTS_DEV_CONN_DIS_BITS) { + handled |= USB_INTS_DEV_CONN_DIS_BITS; + if (usb_hw->sie_status & USB_SIE_STATUS_CONNECTED_BITS) { + /*!< Connected: nothing to do */ + usbd_event_connect_handler(0); + } else { + /*!< Disconnected */ + usbd_event_disconnect_handler(0); + } + usb_hw_clear->sie_status = USB_SIE_STATUS_CONNECTED_BITS; + } +#endif + + /** + * SE0 for 2.5 us or more (will last at least 10ms) + */ + if (status & USB_INTS_BUS_RESET_BITS) { + handled |= USB_INTS_BUS_RESET_BITS; + usb_hw_clear->sie_status = USB_SIE_STATUS_BUS_RESET_BITS; + + usb_hw->dev_addr_ctrl = 0; + + for (uint8_t i = 0; i < USB_NUM_ENDPOINTS - 1; i++) { + /*!< Start at ep1 */ + usb_dpram->ep_ctrl[i].in = 0; + usb_dpram->ep_ctrl[i].out = 0; + } + + usbd_event_reset_handler(0); + +#if CHERRYUSB_OPT_RP2040_USB_DEVICE_ENUMERATION_FIX + /** + * Only run enumeration walk-around if pull up is enabled + */ + if (usb_hw->sie_ctrl & USB_SIE_CTRL_PULLUP_EN_BITS) + rp2040_usb_device_enumeration_fix(); +#endif + } + + /** + * Note from pico datasheet 4.1.2.6.4 (v1.2) + * If you enable the suspend interrupt, it is likely you will see a suspend interrupt when + * the device is first connected but the bus is idle. The bus can be idle for a few ms before + * the host begins sending start of frame packets. You will also see a suspend interrupt + * when the device is disconnected if you do not have a VBUS detect circuit connected. This is + * because without VBUS detection, it is impossible to tell the difference between + * being disconnected and suspended. + */ + if (status & USB_INTS_DEV_SUSPEND_BITS) { + handled |= USB_INTS_DEV_SUSPEND_BITS; + /*!< Suspend */ + usb_hw_clear->sie_status = USB_SIE_STATUS_SUSPENDED_BITS; + usbd_event_suspend_handler(0); + } + + if (status & USB_INTS_DEV_RESUME_FROM_HOST_BITS) { + handled |= USB_INTS_DEV_RESUME_FROM_HOST_BITS; + /*!< Resume */ + usb_hw_clear->sie_status = USB_SIE_STATUS_RESUME_BITS; + usbd_event_resume_handler(0); + } + +#ifdef CONFIG_USBDEV_SOF_ENABLE + if (status & USB_INTS_DEV_SOF_BITS) { + handled |= USB_INTS_DEV_SOF_BITS; + usbd_event_sof_handler(0); + } +#endif + + if (status ^ handled) { + USB_LOG_INFO("Unhandled IRQ 0x%x\n", (uint32_t)(status ^ handled)); + } +} + +void rp2040_usbd_irq(void) +{ + USBD_IRQHandler(0); +} \ No newline at end of file diff --git a/kernel/cherryusb/port/rp2040/usb_hc_rp2040.c b/kernel/cherryusb/port/rp2040/usb_hc_rp2040.c new file mode 100644 index 0000000..e9751b8 --- /dev/null +++ b/kernel/cherryusb/port/rp2040/usb_hc_rp2040.c @@ -0,0 +1,829 @@ +/* + * Copyright (c) 2025, sakumisu + * + * SPDX-License-Identifier: Apache-2.0 + */ +#include "usbh_core.h" +#include "usbh_hub.h" +#include "hardware/resets.h" +#include "hardware/irq.h" +#include "hardware/structs/usb.h" + +#define usb_hw_set hw_set_alias(usb_hw) +#define usb_hw_clear hw_clear_alias(usb_hw) + +#define SIE_CTRL_COMMON (USB_SIE_CTRL_SOF_EN_BITS | \ + USB_SIE_CTRL_KEEP_ALIVE_EN_BITS | \ + USB_SIE_CTRL_PULLDOWN_EN_BITS | \ + USB_SIE_CTRL_EP0_INT_1BUF_BITS) + +typedef enum { + USB_EP0_STATE_SETUP = 0x0, /**< SETUP DATA */ + USB_EP0_STATE_IN_DATA, /**< IN DATA */ + USB_EP0_STATE_IN_STATUS, /**< IN status*/ + USB_EP0_STATE_OUT_DATA, /**< OUT DATA */ + USB_EP0_STATE_OUT_STATUS, /**< OUT status */ +} ep0_state_t; + +struct rp2040_pipe { + uint8_t chidx; + bool inuse; + volatile uint8_t ep0_state; + volatile uint32_t *endpoint_control; /*!< Endpoint control register */ + volatile uint32_t *buffer_control; /*!< Buffer control register */ + uint8_t *data_buffer; /*!< Buffer pointer in usb dpram */ + uint32_t buffer_size; /*!< Buffer size */ + usb_osal_sem_t waitsem; + struct usbh_urb *urb; +}; + +struct rp2040_hcd { + volatile bool port_csc; + volatile bool port_pec; + volatile bool port_pe; + usb_osal_mutex_t ep0_mutex; + struct rp2040_pipe pipe_pool[1 + USB_HOST_INTERRUPT_ENDPOINTS]; +} g_rp2040_hcd[CONFIG_USBHOST_MAX_BUS]; + +void rp2040_usbh_irq(void); + +static int rp2040_pipe_alloc(struct usbh_bus *bus) +{ + size_t flags; + int chidx; + + flags = usb_osal_enter_critical_section(); + for (chidx = 1; chidx <= USB_HOST_INTERRUPT_ENDPOINTS; chidx++) { + if (!g_rp2040_hcd[bus->hcd.hcd_id].pipe_pool[chidx].inuse) { + g_rp2040_hcd[bus->hcd.hcd_id].pipe_pool[chidx].inuse = true; + usb_osal_leave_critical_section(flags); + return chidx; + } + } + usb_osal_leave_critical_section(flags); + return -1; +} + +static void rp2040_pipe_free(struct rp2040_pipe *pipe) +{ + size_t flags; + + flags = usb_osal_enter_critical_section(); + if (pipe->urb) { + pipe->urb->hcpriv = NULL; + pipe->urb = NULL; + } + pipe->inuse = false; + usb_osal_leave_critical_section(flags); +} + +/** + * @brief Take a buffer pointer located in the USB RAM and return as an offset of the RAM. + * + * @param buf + * @return uint32_t + */ +static inline uint32_t usb_buffer_offset(volatile uint8_t *buf) +{ + return (uint32_t)buf ^ (uint32_t)usbh_dpram; +} + +static inline uint8_t usbh_get_port_speed(void) +{ + return (usb_hw->sie_status & USB_SIE_STATUS_SPEED_BITS) >> USB_SIE_STATUS_SPEED_LSB; +} + +static inline void rp2040_init_endpoint(struct usbh_bus *bus, + uint8_t chidx, + uint8_t dev_addr, + uint8_t ep_addr, + uint8_t ep_type, + uint8_t ep_interval, + uint8_t speed) +{ + struct rp2040_pipe *pipe; + uint32_t regval; + + pipe = &g_rp2040_hcd[bus->hcd.hcd_id].pipe_pool[chidx]; + + // Get the data buffer as an offset of the USB controller's DPRAM + uint32_t dpram_offset = usb_buffer_offset(pipe->data_buffer); + regval = EP_CTRL_ENABLE_BITS | + EP_CTRL_INTERRUPT_PER_BUFFER | + (ep_type << EP_CTRL_BUFFER_TYPE_LSB) | + dpram_offset; + + if (ep_interval) { + regval |= (uint32_t)((ep_interval - 1) << EP_CTRL_HOST_INTERRUPT_INTERVAL_LSB); + } + + *pipe->endpoint_control = regval; + + if (chidx != 0) { + regval = (uint32_t)(dev_addr | ((ep_addr & 0x0f) << USB_ADDR_ENDP1_ENDPOINT_LSB)); + + if (!(ep_addr & 0x80)) { + regval |= USB_ADDR_ENDP1_INTEP_DIR_BITS; + } + + // ls device plugged to hub + if ((usbh_get_port_speed() == USB_SPEED_FULL) && (speed == USB_SPEED_LOW)) { + regval |= USB_ADDR_ENDP1_INTEP_PREAMBLE_BITS; + } + + usb_hw->int_ep_addr_ctrl[(chidx - 1)] = regval; + + // Finally, enable interrupt that endpoint + usb_hw_set->int_ep_ctrl = 1 << chidx; + } else { + usb_hw->dev_addr_ctrl = dev_addr; + } +} + +static inline uint32_t usb_buf_ctrl_fill(struct usbh_bus *bus, uint8_t chidx, uint8_t ep_addr, uint8_t buf_id) +{ + struct rp2040_pipe *pipe; + struct usbh_urb *urb; + uint32_t len; + uint32_t buf_ctrl; + + pipe = &g_rp2040_hcd[bus->hcd.hcd_id].pipe_pool[chidx]; + urb = pipe->urb; + + len = MIN(urb->transfer_buffer_length, USB_GET_MAXPACKETSIZE(urb->ep->wMaxPacketSize)); + urb->transfer_buffer_length -= len; + + buf_ctrl = len | USB_BUF_CTRL_AVAIL; + buf_ctrl |= urb->data_toggle ? USB_BUF_CTRL_DATA1_PID : USB_BUF_CTRL_DATA0_PID; + + if (USB_EP_DIR_IS_OUT(ep_addr)) { + /*!< Need to copy the data from the user buffer to the usb memory */ + if (urb->transfer_buffer != NULL) { + memcpy((void *)pipe->data_buffer + buf_id * 64, (void *)urb->transfer_buffer, len); + urb->transfer_buffer += len; + } + /*!< Mark as full */ + buf_ctrl |= USB_BUF_CTRL_FULL; + } + + if (USB_GET_ENDPOINT_TYPE(urb->ep->bmAttributes) != USB_ENDPOINT_TYPE_ISOCHRONOUS) { + if (urb->transfer_buffer_length == 0) { + buf_ctrl |= USB_BUF_CTRL_LAST; + } + } else { + //TODO: handle isochronous transfer + } + + if (buf_id) + buf_ctrl = buf_ctrl << 16; + + return buf_ctrl; +} + +/** + * @brief Starts a transfer on a given endpoint. + * + * @param ep, the endpoint configuration. + * @param buf, the data buffer to send. Only applicable if the endpoint is TX + * @param len, the length of the data in buf (this example limits max len to one packet - 64 bytes) + */ +static void usb_start_transfer(struct usbh_bus *bus, uint8_t chidx, uint8_t ep_addr) +{ + struct rp2040_pipe *pipe; + struct usbh_urb *urb; + uint32_t buf_ctrl; + uint32_t ep_ctrl; + + pipe = &g_rp2040_hcd[bus->hcd.hcd_id].pipe_pool[chidx]; + urb = pipe->urb; + + ep_ctrl = *pipe->endpoint_control; + buf_ctrl = usb_buf_ctrl_fill(bus, chidx, ep_addr, 0); + + if (urb->transfer_buffer_length && (ep_addr & 0x0f) == 0x00) { + urb->data_toggle ^= 1; + buf_ctrl |= usb_buf_ctrl_fill(bus, chidx, ep_addr, 1); + + // Set endpoint control double buffered bit if needed + ep_ctrl &= ~EP_CTRL_INTERRUPT_PER_BUFFER; + ep_ctrl |= EP_CTRL_DOUBLE_BUFFERED_BITS | EP_CTRL_INTERRUPT_PER_DOUBLE_BUFFER; + } else { + // Single buffered since 1 is enough + ep_ctrl &= ~(EP_CTRL_DOUBLE_BUFFERED_BITS | EP_CTRL_INTERRUPT_PER_DOUBLE_BUFFER); + ep_ctrl |= EP_CTRL_INTERRUPT_PER_BUFFER; + } + *pipe->endpoint_control = ep_ctrl; + *pipe->buffer_control = buf_ctrl; +} + +static inline void rp2040_control_transfer_start(bool dir_in, bool isetup, uint8_t speed) +{ + uint32_t regval; + + regval = SIE_CTRL_COMMON | USB_SIE_CTRL_START_TRANS_BITS; + + if ((usbh_get_port_speed() == USB_SPEED_FULL) && (speed == USB_SPEED_LOW)) { + regval |= USB_SIE_CTRL_PREAMBLE_EN_BITS; + } + + if (isetup) { + regval |= USB_SIE_CTRL_SEND_SETUP_BITS; + } else { + if (dir_in) { + regval |= USB_SIE_CTRL_RECEIVE_DATA_BITS; + } else { + regval |= USB_SIE_CTRL_SEND_DATA_BITS; + } + } + + usb_hw->sie_ctrl = regval & ~USB_SIE_CTRL_START_TRANS_BITS; + busy_wait_at_least_cycles(12); + usb_hw->sie_ctrl = regval; +} + +static void rp2040_control_urb_init(struct usbh_bus *bus, uint8_t chidx, struct usbh_urb *urb, struct usb_setup_packet *setup, uint8_t *buffer, uint32_t buflen) +{ + struct rp2040_pipe *pipe; + + pipe = &g_rp2040_hcd[bus->hcd.hcd_id].pipe_pool[chidx]; + + if (pipe->ep0_state == USB_EP0_STATE_SETUP) /* fill setup */ + { + pipe->urb->data_toggle = 1; + memcpy((uint8_t *)usbh_dpram->setup_packet, (uint8_t *)setup, 8); + rp2040_init_endpoint(bus, chidx, urb->hport->dev_addr, 0x00, USB_ENDPOINT_TYPE_CONTROL, 0, urb->hport->speed); + rp2040_control_transfer_start(false, true, urb->hport->speed); + } else if (pipe->ep0_state == USB_EP0_STATE_IN_DATA) /* fill in data */ + { + rp2040_init_endpoint(bus, chidx, urb->hport->dev_addr, 0x80, USB_ENDPOINT_TYPE_CONTROL, 0, urb->hport->speed); + usb_start_transfer(bus, chidx, 0x80); + rp2040_control_transfer_start(true, false, urb->hport->speed); + } else if (pipe->ep0_state == USB_EP0_STATE_OUT_DATA) /* fill out data */ + { + rp2040_init_endpoint(bus, chidx, urb->hport->dev_addr, 0x00, USB_ENDPOINT_TYPE_CONTROL, 0, urb->hport->speed); + usb_start_transfer(bus, chidx, 0x00); + rp2040_control_transfer_start(false, false, urb->hport->speed); + } else if (pipe->ep0_state == USB_EP0_STATE_IN_STATUS) /* fill in status */ + { + urb->data_toggle = 1; + rp2040_init_endpoint(bus, chidx, urb->hport->dev_addr, 0x80, USB_ENDPOINT_TYPE_CONTROL, 0, urb->hport->speed); + usb_start_transfer(bus, chidx, 0x80); + rp2040_control_transfer_start(true, false, urb->hport->speed); + } else if (pipe->ep0_state == USB_EP0_STATE_OUT_STATUS) /* fill out status */ + { + urb->data_toggle = 1; + rp2040_init_endpoint(bus, chidx, urb->hport->dev_addr, 0x00, USB_ENDPOINT_TYPE_CONTROL, 0, urb->hport->speed); + usb_start_transfer(bus, chidx, 0x00); + rp2040_control_transfer_start(false, false, urb->hport->speed); + } +} + +static void rp2040_bulk_int_urb_init(struct usbh_bus *bus, uint8_t chidx, struct usbh_urb *urb, uint8_t *buffer, uint32_t buflen) +{ + rp2040_init_endpoint(bus, chidx, urb->hport->dev_addr, urb->ep->bEndpointAddress, USB_GET_ENDPOINT_TYPE(urb->ep->bmAttributes), urb->ep->bInterval, urb->hport->speed); + usb_start_transfer(bus, chidx, urb->ep->bEndpointAddress); +} + +int usb_hc_init(struct usbh_bus *bus) +{ + uint8_t *next_buffer_ptr; + + memset(&g_rp2040_hcd[bus->hcd.hcd_id], 0, sizeof(struct rp2040_hcd)); + + for (uint8_t i = 0; i <= USB_HOST_INTERRUPT_ENDPOINTS; i++) { + g_rp2040_hcd[bus->hcd.hcd_id].pipe_pool[i].waitsem = usb_osal_sem_create(0); + if (g_rp2040_hcd[bus->hcd.hcd_id].pipe_pool[i].waitsem == NULL) { + USB_LOG_ERR("Failed to create waitsem\r\n"); + return -USB_ERR_NOMEM; + } + } + + g_rp2040_hcd[bus->hcd.hcd_id].ep0_mutex = usb_osal_mutex_create(); + if (g_rp2040_hcd[bus->hcd.hcd_id].ep0_mutex == NULL) { + USB_LOG_ERR("Failed to create ep0_mutex\r\n"); + return -USB_ERR_NOMEM; + } + + g_rp2040_hcd[bus->hcd.hcd_id].pipe_pool[0].endpoint_control = &usbh_dpram->epx_ctrl; + g_rp2040_hcd[bus->hcd.hcd_id].pipe_pool[0].buffer_control = &usbh_dpram->epx_buf_ctrl; + g_rp2040_hcd[bus->hcd.hcd_id].pipe_pool[0].data_buffer = &usbh_dpram->epx_data[0]; + g_rp2040_hcd[bus->hcd.hcd_id].pipe_pool[0].buffer_size = (64 * 2); + + next_buffer_ptr = &usb_dpram->epx_data[64 * 2]; + + for (uint8_t i = 1; i <= USB_HOST_INTERRUPT_ENDPOINTS; i++) { + g_rp2040_hcd[bus->hcd.hcd_id].pipe_pool[i].chidx = i; + g_rp2040_hcd[bus->hcd.hcd_id].pipe_pool[i].endpoint_control = &usbh_dpram->int_ep_ctrl[i - 1].ctrl; + g_rp2040_hcd[bus->hcd.hcd_id].pipe_pool[i].buffer_control = &usbh_dpram->int_ep_buffer_ctrl[i - 1].ctrl; + g_rp2040_hcd[bus->hcd.hcd_id].pipe_pool[i].data_buffer = next_buffer_ptr; + g_rp2040_hcd[bus->hcd.hcd_id].pipe_pool[i].buffer_size = (64 * 2); + next_buffer_ptr += (64 * 2); + } + + // Reset usb controller + reset_unreset_block_num_wait_blocking(RESET_USBCTRL); + + // Remove shared irq if it was previously added so as not to fill up shared irq slots + irq_remove_handler(USBCTRL_IRQ, rp2040_usbh_irq); + + irq_add_shared_handler(USBCTRL_IRQ, rp2040_usbh_irq, PICO_SHARED_IRQ_HANDLER_HIGHEST_ORDER_PRIORITY); + + /*!< Clear any previous state just in case */ + memset(usb_hw, 0, sizeof(*usb_hw)); + memset(usbh_dpram, 0, sizeof(*usbh_dpram)); + + /*!< Mux the controller to the onboard usb phy */ + usb_hw->muxing = USB_USB_MUXING_TO_PHY_BITS | USB_USB_MUXING_SOFTCON_BITS; + + // Force VBUS detect so the device thinks it is plugged into a host + usb_hw->pwr = USB_USB_PWR_VBUS_DETECT_BITS | USB_USB_PWR_VBUS_DETECT_OVERRIDE_EN_BITS; + + // Enable the USB controller in device mode. + usb_hw->main_ctrl = USB_MAIN_CTRL_CONTROLLER_EN_BITS | USB_MAIN_CTRL_HOST_NDEVICE_BITS; + + usb_hw->sie_ctrl = SIE_CTRL_COMMON; + + // Enable USB interrupt at processor + irq_set_enabled(USBCTRL_IRQ, true); + + usb_hw->inte = USB_INTE_BUFF_STATUS_BITS | + USB_INTE_HOST_CONN_DIS_BITS | + USB_INTE_STALL_BITS | + USB_INTE_TRANS_COMPLETE_BITS | + USB_INTE_ERROR_RX_TIMEOUT_BITS | + USB_INTE_ERROR_DATA_SEQ_BITS; + return 0; +} + +int usb_hc_deinit(struct usbh_bus *bus) +{ + // Enable USB interrupt at processor + irq_set_enabled(USBCTRL_IRQ, false); + + // Remove shared irq if it was previously added so as not to fill up shared irq slots + irq_remove_handler(USBCTRL_IRQ, rp2040_usbh_irq); + + for (uint8_t i = 0; i <= USB_HOST_INTERRUPT_ENDPOINTS; i++) { + usb_osal_sem_delete(g_rp2040_hcd[bus->hcd.hcd_id].pipe_pool[i].waitsem); + } + + usb_osal_mutex_delete(g_rp2040_hcd[bus->hcd.hcd_id].ep0_mutex); + + return 0; +} + +uint16_t usbh_get_frame_number(struct usbh_bus *bus) +{ + return usb_hw->sof_rd; +} + +int usbh_roothub_control(struct usbh_bus *bus, struct usb_setup_packet *setup, uint8_t *buf) +{ + uint8_t nports; + uint8_t port; + uint32_t status; + + nports = CONFIG_USBHOST_MAX_RHPORTS; + port = setup->wIndex; + if (setup->bmRequestType & USB_REQUEST_RECIPIENT_DEVICE) { + switch (setup->bRequest) { + case HUB_REQUEST_CLEAR_FEATURE: + switch (setup->wValue) { + case HUB_FEATURE_HUB_C_LOCALPOWER: + break; + case HUB_FEATURE_HUB_C_OVERCURRENT: + break; + default: + return -USB_ERR_INVAL; + } + break; + case HUB_REQUEST_SET_FEATURE: + switch (setup->wValue) { + case HUB_FEATURE_HUB_C_LOCALPOWER: + break; + case HUB_FEATURE_HUB_C_OVERCURRENT: + break; + default: + return -USB_ERR_INVAL; + } + break; + case HUB_REQUEST_GET_DESCRIPTOR: + break; + case HUB_REQUEST_GET_STATUS: + memset(buf, 0, 4); + break; + default: + break; + } + } else if (setup->bmRequestType & USB_REQUEST_RECIPIENT_OTHER) { + switch (setup->bRequest) { + case HUB_REQUEST_CLEAR_FEATURE: + if (!port || port > nports) { + return -USB_ERR_INVAL; + } + + switch (setup->wValue) { + case HUB_PORT_FEATURE_ENABLE: + break; + case HUB_PORT_FEATURE_SUSPEND: + case HUB_PORT_FEATURE_C_SUSPEND: + break; + case HUB_PORT_FEATURE_POWER: + break; + case HUB_PORT_FEATURE_C_CONNECTION: + g_rp2040_hcd[bus->hcd.hcd_id].port_csc = 0; + break; + case HUB_PORT_FEATURE_C_ENABLE: + g_rp2040_hcd[bus->hcd.hcd_id].port_pec = 0; + break; + case HUB_PORT_FEATURE_C_OVER_CURREN: + break; + case HUB_PORT_FEATURE_C_RESET: + break; + default: + return -USB_ERR_INVAL; + } + break; + case HUB_REQUEST_SET_FEATURE: + if (!port || port > nports) { + return -USB_ERR_INVAL; + } + + switch (setup->wValue) { + case HUB_PORT_FEATURE_SUSPEND: + break; + case HUB_PORT_FEATURE_POWER: + break; + case HUB_PORT_FEATURE_RESET: + break; + + default: + return -USB_ERR_INVAL; + } + break; + case HUB_REQUEST_GET_STATUS: + if (!port || port > nports) { + return -USB_ERR_INVAL; + } + + status = 0; + if (g_rp2040_hcd[bus->hcd.hcd_id].port_csc) { + status |= (1 << HUB_PORT_FEATURE_C_CONNECTION); + } + if (g_rp2040_hcd[bus->hcd.hcd_id].port_pec) { + status |= (1 << HUB_PORT_FEATURE_C_ENABLE); + } + + if (g_rp2040_hcd[bus->hcd.hcd_id].port_pe) { + status |= (1 << HUB_PORT_FEATURE_CONNECTION); + status |= (1 << HUB_PORT_FEATURE_ENABLE); + if (usbh_get_port_speed() == USB_SPEED_LOW) { + status |= (1 << HUB_PORT_FEATURE_LOWSPEED); + } + } + + status |= (1 << HUB_PORT_FEATURE_POWER); + memcpy(buf, &status, 4); + break; + default: + break; + } + } + return 0; +} + +int usbh_submit_urb(struct usbh_urb *urb) +{ + struct rp2040_pipe *pipe; + struct usbh_bus *bus; + int chidx; + size_t flags; + int ret = 0; + + if (!urb || !urb->hport || !urb->ep || !urb->hport->bus) { + return -USB_ERR_INVAL; + } + + if (!urb->hport->connected || !(usb_hw->sie_status & USB_SIE_STATUS_SPEED_BITS)) { + return -USB_ERR_NOTCONN; + } + + if (urb->errorcode == -USB_ERR_BUSY) { + return -USB_ERR_BUSY; + } + + bus = urb->hport->bus; + + if (USB_GET_ENDPOINT_TYPE(urb->ep->bmAttributes) == USB_ENDPOINT_TYPE_CONTROL) { + chidx = 0; + /* all the control transfers use the only one ep0 register, we need to lock */ + usb_osal_mutex_take(g_rp2040_hcd[bus->hcd.hcd_id].ep0_mutex); + } else { + chidx = rp2040_pipe_alloc(bus); + if (chidx == -1) { + return -USB_ERR_NOMEM; + } + } + + flags = usb_osal_enter_critical_section(); + + pipe = &g_rp2040_hcd[bus->hcd.hcd_id].pipe_pool[chidx]; + pipe->chidx = chidx; + pipe->urb = urb; + + urb->hcpriv = pipe; + urb->errorcode = -USB_ERR_BUSY; + urb->actual_length = 0; + usb_osal_leave_critical_section(flags); + + switch (USB_GET_ENDPOINT_TYPE(urb->ep->bmAttributes)) { + case USB_ENDPOINT_TYPE_CONTROL: + pipe->ep0_state = USB_EP0_STATE_SETUP; + rp2040_control_urb_init(bus, 0, urb, urb->setup, urb->transfer_buffer, urb->transfer_buffer_length); + break; + case USB_ENDPOINT_TYPE_BULK: + case USB_ENDPOINT_TYPE_INTERRUPT: + rp2040_bulk_int_urb_init(bus, chidx, urb, urb->transfer_buffer, urb->transfer_buffer_length); + break; + default: + break; + } + + if (urb->timeout > 0) { + /* wait until timeout or sem give */ + ret = usb_osal_sem_take(pipe->waitsem, urb->timeout); + if (ret < 0) { + goto errout_timeout; + } + urb->timeout = 0; + ret = urb->errorcode; + /* we can free pipe when waitsem is done */ + rp2040_pipe_free(pipe); + + if (chidx == 0) { + usb_osal_mutex_give(g_rp2040_hcd[bus->hcd.hcd_id].ep0_mutex); + } + } + return ret; +errout_timeout: + if (chidx == 0) { + usb_osal_mutex_give(g_rp2040_hcd[bus->hcd.hcd_id].ep0_mutex); + } + urb->timeout = 0; + usbh_kill_urb(urb); + return ret; +} + +int usbh_kill_urb(struct usbh_urb *urb) +{ + struct rp2040_pipe *pipe; + struct usbh_bus *bus; + size_t flags; + + if (!urb || !urb->hcpriv || !urb->hport->bus) { + return -USB_ERR_INVAL; + } + + bus = urb->hport->bus; + + ARG_UNUSED(bus); + + flags = usb_osal_enter_critical_section(); + + pipe = (struct rp2040_pipe *)urb->hcpriv; + urb->errorcode = -USB_ERR_SHUTDOWN; + + usb_hw_clear->int_ep_ctrl = 1 << pipe->chidx; + usb_hw_clear->buf_status = 1 << (pipe->chidx * 2 + 0); + usb_hw_clear->buf_status = 1 << (pipe->chidx * 2 + 1); + *pipe->endpoint_control = 0; + *pipe->buffer_control = 0; + + if (urb->timeout) { + usb_osal_sem_give(pipe->waitsem); + } else { + rp2040_pipe_free(pipe); + } + + if (urb->complete) { + urb->complete(urb->arg, urb->errorcode); + } + + usb_osal_leave_critical_section(flags); + + return 0; +} + +static void rp2040_urb_waitup(struct usbh_urb *urb) +{ + struct rp2040_pipe *pipe; + + pipe = (struct rp2040_pipe *)urb->hcpriv; + + if (urb->timeout) { + usb_osal_sem_give(pipe->waitsem); + } else { + rp2040_pipe_free(pipe); + } + + if (urb->complete) { + if (urb->errorcode < 0) { + urb->complete(urb->arg, urb->errorcode); + } else { + urb->complete(urb->arg, urb->actual_length); + } + } +} + +static void rp2040_handle_buffer_status(struct usbh_bus *bus) +{ + struct rp2040_pipe *pipe; + struct usbh_urb *urb; + uint32_t remaining_buffers; + uint32_t size; + + remaining_buffers = usb_hw->buf_status; + + uint32_t bit = 1u; + if (remaining_buffers & bit) { + remaining_buffers &= ~bit; + usb_hw_clear->buf_status = bit; + + pipe = &g_rp2040_hcd[bus->hcd.hcd_id].pipe_pool[0]; + urb = pipe->urb; + switch (pipe->ep0_state) { + case USB_EP0_STATE_IN_DATA: + size = *pipe->buffer_control & USB_BUF_CTRL_LEN_MASK; + memcpy(urb->transfer_buffer, (uint8_t *)pipe->data_buffer, size); + + urb->transfer_buffer += size; + urb->actual_length += size; + + if (*pipe->endpoint_control & EP_CTRL_DOUBLE_BUFFERED_BITS) { + if (size == USB_GET_MAXPACKETSIZE(urb->ep->wMaxPacketSize)) { + size = (*pipe->buffer_control >> 16) & USB_BUF_CTRL_LEN_MASK; + memcpy(urb->transfer_buffer, (uint8_t *)pipe->data_buffer + 64, size); + + urb->transfer_buffer += size; + urb->actual_length += size; + } + } + + if ((size < USB_GET_MAXPACKETSIZE(urb->ep->wMaxPacketSize)) || (urb->transfer_buffer_length == 0)) { + pipe->ep0_state = USB_EP0_STATE_OUT_STATUS; + rp2040_control_urb_init(bus, 0, urb, urb->setup, urb->transfer_buffer, urb->transfer_buffer_length); + } else { + urb->data_toggle ^= 1; + usb_start_transfer(bus, 0, 0x80); + } + break; + case USB_EP0_STATE_OUT_DATA: + urb->actual_length += *pipe->buffer_control & USB_BUF_CTRL_LEN_MASK; + + if (*pipe->endpoint_control & EP_CTRL_DOUBLE_BUFFERED_BITS) { + urb->actual_length += (*pipe->buffer_control >> 16) & USB_BUF_CTRL_LEN_MASK; + } + + if (urb->transfer_buffer_length == 0) { + pipe->ep0_state = USB_EP0_STATE_IN_STATUS; + rp2040_control_urb_init(bus, 0, urb, urb->setup, urb->transfer_buffer, urb->transfer_buffer_length); + } else { + urb->data_toggle ^= 1; + usb_start_transfer(bus, 0, 0x00); + } + break; + case USB_EP0_STATE_IN_STATUS: + case USB_EP0_STATE_OUT_STATUS: + urb->errorcode = 0; + rp2040_urb_waitup(urb); + break; + default: + break; + } + } + + for (uint8_t i = 1; remaining_buffers && i <= USB_HOST_INTERRUPT_ENDPOINTS; i++) { + for (uint8_t j = 0; j < 2; j++) { + bit = 1 << (i * 2 + j); + if (remaining_buffers & bit) { + remaining_buffers &= ~bit; + usb_hw_clear->buf_status = bit; + + pipe = &g_rp2040_hcd[bus->hcd.hcd_id].pipe_pool[i]; + urb = pipe->urb; + if (urb == NULL) { + continue; + } + + if (j == 0) { //IN + size = *pipe->buffer_control & USB_BUF_CTRL_LEN_MASK; + memcpy(urb->transfer_buffer, (uint8_t *)pipe->data_buffer, size); + + urb->transfer_buffer += size; + urb->actual_length += size; + + urb->data_toggle ^= 1; + if (size < USB_GET_MAXPACKETSIZE(urb->ep->wMaxPacketSize) || urb->transfer_buffer_length == 0) { + urb->errorcode = 0; + rp2040_urb_waitup(urb); + } else { + usb_start_transfer(bus, i, urb->ep->bEndpointAddress); + } + } else { //OUT + urb->data_toggle ^= 1; + + urb->actual_length += *pipe->buffer_control & USB_BUF_CTRL_LEN_MASK; + + if (urb->transfer_buffer_length == 0) { + urb->errorcode = 0; + rp2040_urb_waitup(urb); + } else { + usb_start_transfer(bus, i, urb->ep->bEndpointAddress); + } + } + } + } + } +} + +void USBH_IRQHandler(uint8_t busid) +{ + uint32_t status; + uint32_t handled = 0; + struct usbh_bus *bus; + struct rp2040_pipe *pipe; + struct usbh_urb *urb; + + bus = &g_usbhost_bus[busid]; + status = usb_hw->ints; + + if (status & USB_INTS_HOST_CONN_DIS_BITS) { + handled |= USB_INTS_HOST_CONN_DIS_BITS; + usb_hw_clear->sie_status = USB_SIE_STATUS_SPEED_BITS; + if (usbh_get_port_speed()) { + g_rp2040_hcd[bus->hcd.hcd_id].port_csc = 1; + g_rp2040_hcd[bus->hcd.hcd_id].port_pec = 1; + g_rp2040_hcd[bus->hcd.hcd_id].port_pe = 1; + bus->hcd.roothub.int_buffer[0] = (1 << 1); + usbh_hub_thread_wakeup(&bus->hcd.roothub); + } else { + g_rp2040_hcd[bus->hcd.hcd_id].port_csc = 1; + g_rp2040_hcd[bus->hcd.hcd_id].port_pec = 1; + g_rp2040_hcd[bus->hcd.hcd_id].port_pe = 0; + bus->hcd.roothub.int_buffer[0] = (1 << 1); + usbh_hub_thread_wakeup(&bus->hcd.roothub); + } + } + + if (status & USB_INTS_STALL_BITS) { + handled |= USB_INTS_STALL_BITS; + usb_hw_clear->sie_status = USB_SIE_STATUS_STALL_REC_BITS; + } + + if (status & USB_INTS_BUFF_STATUS_BITS) { + handled |= USB_INTS_BUFF_STATUS_BITS; + rp2040_handle_buffer_status(bus); + } + + if (status & USB_INTS_TRANS_COMPLETE_BITS) { + handled |= USB_INTS_TRANS_COMPLETE_BITS; + usb_hw_clear->sie_status = USB_SIE_STATUS_TRANS_COMPLETE_BITS; + if (usb_hw->sie_ctrl & USB_SIE_CTRL_SEND_SETUP_BITS) { + pipe = (struct rp2040_pipe *)&g_rp2040_hcd[bus->hcd.hcd_id].pipe_pool[0]; + urb = pipe->urb; + if (urb) { + if (urb->setup->wLength) { + if (urb->setup->bmRequestType & 0x80) { + pipe->ep0_state = USB_EP0_STATE_IN_DATA; + } else { + pipe->ep0_state = USB_EP0_STATE_OUT_DATA; + } + } else { + pipe->ep0_state = USB_EP0_STATE_IN_STATUS; + } + urb->actual_length = 8; + rp2040_control_urb_init(bus, 0, urb, urb->setup, urb->transfer_buffer, urb->transfer_buffer_length); + } + } else { + } + } + + if (status & USB_INTS_ERROR_RX_TIMEOUT_BITS) { + handled |= USB_INTS_ERROR_RX_TIMEOUT_BITS; + usb_hw_clear->sie_status = USB_SIE_STATUS_RX_TIMEOUT_BITS; + } + + if (status & USB_INTS_ERROR_DATA_SEQ_BITS) { + handled |= USB_INTS_ERROR_DATA_SEQ_BITS; + usb_hw_clear->sie_status = USB_SIE_STATUS_DATA_SEQ_ERROR_BITS; + } + + if (status ^ handled) { + USB_LOG_ERR("Unhandled IRQ 0x%x\n", (uint)(status ^ handled)); + } +} + +void rp2040_usbh_irq(void) +{ + USBH_IRQHandler(0); +} \ No newline at end of file diff --git a/kernel/cherryusb/port/template/usb_dc.c b/kernel/cherryusb/port/template/usb_dc.c new file mode 100644 index 0000000..516b32f --- /dev/null +++ b/kernel/cherryusb/port/template/usb_dc.c @@ -0,0 +1,125 @@ +#include "usbd_core.h" + +/* Endpoint state */ +struct usb_dc_ep_state { + uint16_t ep_mps; /* Endpoint max packet size */ + uint8_t ep_type; /* Endpoint type */ + uint8_t ep_stalled; /* Endpoint stall flag */ + uint8_t *xfer_buf; + uint32_t xfer_len; + uint32_t actual_xfer_len; +}; + +/* Driver state */ +struct xxx_udc { + volatile uint8_t dev_addr; + struct usb_dc_ep_state in_ep[CONFIG_USBDEV_EP_NUM]; /*!< IN endpoint parameters*/ + struct usb_dc_ep_state out_ep[CONFIG_USBDEV_EP_NUM]; /*!< OUT endpoint parameters */ +} g_xxx_udc; + +__WEAK void usb_dc_low_level_init(void) +{ +} + +__WEAK void usb_dc_low_level_deinit(void) +{ +} + +int usb_dc_init(uint8_t busid) +{ + memset(&g_xxx_udc, 0, sizeof(struct xxx_udc)); + + usb_dc_low_level_init(); + return 0; +} + +int usb_dc_deinit(uint8_t busid) +{ + return 0; +} + +int usbd_set_address(uint8_t busid, const uint8_t addr) +{ + return 0; +} + +int usbd_set_remote_wakeup(uint8_t busid) +{ + return -1; +} + +uint8_t usbd_get_port_speed(uint8_t busid) +{ + return USB_SPEED_FULL; +} + +int usbd_ep_open(uint8_t busid, const struct usb_endpoint_descriptor *ep) +{ + uint8_t ep_idx = USB_EP_GET_IDX(ep->bEndpointAddress); + + if (USB_EP_DIR_IS_OUT(ep->bEndpointAddress)) { + g_xxx_udc.out_ep[ep_idx].ep_mps = USB_GET_MAXPACKETSIZE(ep->wMaxPacketSize); + g_xxx_udc.out_ep[ep_idx].ep_type = USB_GET_ENDPOINT_TYPE(ep->bmAttributes); + g_xxx_udc.out_ep[ep_idx].ep_enable = true; + } else { + g_xxx_udc.in_ep[ep_idx].ep_mps = USB_GET_MAXPACKETSIZE(ep->wMaxPacketSize); + g_xxx_udc.in_ep[ep_idx].ep_type = USB_GET_ENDPOINT_TYPE(ep->bmAttributes); + g_xxx_udc.in_ep[ep_idx].ep_enable = true; + } + return 0; +} + +int usbd_ep_close(uint8_t busid, const uint8_t ep) +{ + return 0; +} + +int usbd_ep_set_stall(uint8_t busid, const uint8_t ep) +{ + return 0; +} + +int usbd_ep_clear_stall(uint8_t busid, const uint8_t ep) +{ + return 0; +} + +int usbd_ep_is_stalled(uint8_t busid, const uint8_t ep, uint8_t *stalled) +{ + return 0; +} + +int usbd_ep_start_write(uint8_t busid, const uint8_t ep, const uint8_t *data, uint32_t data_len) +{ + uint8_t ep_idx = USB_EP_GET_IDX(ep); + uint32_t tmp; + + if (!data && data_len) { + return -1; + } + + g_xxx_udc.in_ep[ep_idx].xfer_buf = (uint8_t *)data; + g_xxx_udc.in_ep[ep_idx].xfer_len = data_len; + g_xxx_udc.in_ep[ep_idx].actual_xfer_len = 0; + + return 0; +} + +int usbd_ep_start_read(uint8_t busid, const uint8_t ep, uint8_t *data, uint32_t data_len) +{ + uint8_t ep_idx = USB_EP_GET_IDX(ep); + + if (!data && data_len) { + return -1; + } + + g_xxx_udc.out_ep[ep_idx].xfer_buf = (uint8_t *)data; + g_xxx_udc.out_ep[ep_idx].xfer_len = data_len; + g_xxx_udc.out_ep[ep_idx].actual_xfer_len = 0; + + return 0; +} + +void USBD_IRQHandler(uint8_t busid) +{ +} \ No newline at end of file diff --git a/kernel/cherryusb/port/template/usb_hc.c b/kernel/cherryusb/port/template/usb_hc.c new file mode 100644 index 0000000..1de1cd5 --- /dev/null +++ b/kernel/cherryusb/port/template/usb_hc.c @@ -0,0 +1,133 @@ +/* + * Copyright (c) 2025, sakumisu + * + * SPDX-License-Identifier: Apache-2.0 + */ +#include "usbh_core.h" +#include "usbh_hub.h" + +int usb_hc_init(struct usbh_bus *bus) +{ + return 0; +} + +int usb_hc_deinit(struct usbh_bus *bus) +{ + return 0; +} + +uint16_t usbh_get_frame_number(struct usbh_bus *bus) +{ + return 0; +} + +int usbh_roothub_control(struct usbh_bus *bus, struct usb_setup_packet *setup, uint8_t *buf) +{ + uint8_t nports; + uint8_t port; + uint32_t status; + + nports = CONFIG_USBHOST_MAX_RHPORTS; + port = setup->wIndex; + if (setup->bmRequestType & USB_REQUEST_RECIPIENT_DEVICE) { + switch (setup->bRequest) { + case HUB_REQUEST_CLEAR_FEATURE: + switch (setup->wValue) { + case HUB_FEATURE_HUB_C_LOCALPOWER: + break; + case HUB_FEATURE_HUB_C_OVERCURRENT: + break; + default: + return -USB_ERR_NOTSUPP; + } + break; + case HUB_REQUEST_SET_FEATURE: + switch (setup->wValue) { + case HUB_FEATURE_HUB_C_LOCALPOWER: + break; + case HUB_FEATURE_HUB_C_OVERCURRENT: + break; + default: + return -USB_ERR_NOTSUPP; + } + break; + case HUB_REQUEST_GET_DESCRIPTOR: + break; + case HUB_REQUEST_GET_STATUS: + memset(buf, 0, 4); + break; + default: + break; + } + } else if (setup->bmRequestType & USB_REQUEST_RECIPIENT_OTHER) { + switch (setup->bRequest) { + case HUB_REQUEST_CLEAR_FEATURE: + if (!port || port > nports) { + return -USB_ERR_INVAL; + } + + switch (setup->wValue) { + case HUB_PORT_FEATURE_ENABLE: + break; + case HUB_PORT_FEATURE_SUSPEND: + break; + case HUB_PORT_FEATURE_C_SUSPEND: + break; + case HUB_PORT_FEATURE_POWER: + break; + case HUB_PORT_FEATURE_C_CONNECTION: + break; + case HUB_PORT_FEATURE_C_ENABLE: + break; + case HUB_PORT_FEATURE_C_OVER_CURREN: + break; + case HUB_PORT_FEATURE_C_RESET: + break; + default: + return -USB_ERR_NOTSUPP; + } + break; + case HUB_REQUEST_SET_FEATURE: + if (!port || port > nports) { + return -USB_ERR_INVAL; + } + + switch (setup->wValue) { + case HUB_PORT_FEATURE_SUSPEND: + break; + case HUB_PORT_FEATURE_POWER: + break; + case HUB_PORT_FEATURE_RESET: + break; + + default: + return -USB_ERR_NOTSUPP; + } + break; + case HUB_REQUEST_GET_STATUS: + if (!port || port > nports) { + return -USB_ERR_INVAL; + } + + memcpy(buf, &status, 4); + break; + default: + break; + } + } + return 0; +} + +int usbh_submit_urb(struct usbh_urb *urb) +{ + return -USB_ERR_NOTSUPP; +} + +int usbh_kill_urb(struct usbh_urb *urb) +{ + return -USB_ERR_NOTSUPP; +} + +void USBH_IRQHandler(uint8_t busid) +{ +} \ No newline at end of file diff --git a/kernel/cherryusb/port/xhci/phytium/README.md b/kernel/cherryusb/port/xhci/phytium/README.md new file mode 100644 index 0000000..dc491e1 --- /dev/null +++ b/kernel/cherryusb/port/xhci/phytium/README.md @@ -0,0 +1,70 @@ +# USB 3.0 Host 控制器 (XHCI) + +- Phytium PI 和 Phyium E2000 系列开发板提供符合 XHCI 1.1 规范的 USB 3.0 Host 控制器, 其它 Phytium 系列平台可以通过 PCIe 扩展卡获得 XHCI 控制器 +- 相关的使用例程可以在 Phytium PI（飞腾派）、E2000 D/Q Demo 板以及 D2000 和后续平台上运行，例程包括 + +--------------------------------------------- + +- FreeRTOS + +- - 1. [XHCI 平台控制器使用鼠标/键盘/U盘功能](https://gitee.com/phytium_embedded/phytium-free-rtos-sdk/tree/master/example/peripheral/usb/xhci_platform/README.md) +- - 2. [XHCI PCIe控制器使用鼠标/键盘/U盘功能](https://gitee.com/phytium_embedded/phytium-free-rtos-sdk/tree/master/example/peripheral/usb/xhci_pcie/README.md) +- - 3. [LVGL 中使用 XHCI 平台控制器连接的鼠标/键盘/U盘](https://gitee.com/phytium_embedded/phytium-free-rtos-sdk/blob/master/example/peripheral/media/lvgl_indev/README.md) + +--------------------------------------------- + +- RT-Thread + +- - 1. [XHCI 平台控制器识别鼠标/键盘/U盘](https://github.com/RT-Thread/rt-thread/blob/master/bsp/phytium/doc/use_cherryusb.md) + +--------------------------------------------- + +- Standalone 裸机 + +- - 暂不支持 + +--------------------------------------------- + +- XHCI 的驱动功能以静态库的方式提供，仅限在 Phytium 系列 CPU 平台使用， + +- - libxhci_a64.a : AARCH64 驱动库 +- - libxhci_a32_hardfp.a : AARCH32 驱动库，使用硬浮点 +- - libxhci_a32_softfp.a : AARCH32 驱动库，使用软浮点 + +需要获取源代码请联系 `opensource_embedded@phytium.com.cn` 获取，如需移植运行到非 Phytium 系列 CPU 平台请提前联系`opensource_embedded@phytium.com.cn`获得允许 + +# USB 3.0 Host Controller (XHCI) + +- The Phytium PI and Phytium E2000 series development boards provide USB 3.0 Host controllers that conform to the XHCI 1.1 specification. Other Phytium series platforms can obtain XHCI controllers through PCIe expansion cards. +- Related example routines can be run on Phytium PI (Fetion Pi), E2000 D/Q Demo boards, and D2000 and later platforms. Examples include: + +--------------------------------------------- + +- FreeRTOS + + - 1. [XHCI platform controller for mouse/keyboard/USB drive functions](https://gitee.com/phytium_embedded/phytium-free-rtos-sdk/tree/master/example/peripheral/usb/xhci_platform/README.md) + - 2. [XHCI PCIe controller for mouse/keyboard/USB drive functions](https://gitee.com/phytium_embedded/phytium-free-rtos-sdk/tree/master/example/peripheral/usb/xhci_pcie/README.md) + - 3. [Using XHCI platform controller-connected mouse/keyboard/USB drive in LVGL](https://gitee.com/phytium_embedded/phytium-free-rtos-sdk/blob/master/example/peripheral/media/lvgl_indev/README.md) + +--------------------------------------------- + +- RT-Thread + + - 1. [XHCI platform controller recognizing mouse/keyboard/USB drive](https://github.com/RT-Thread/rt-thread/blob/master/bsp/phytium/doc/use_cherryusb.md) + +--------------------------------------------- + +- Standalone (Bare Metal) + + - Not supported yet + +--------------------------------------------- + +- This XHCI driver functionality is provided as a static library and is only available for Phytium series CPU platforms. + + - - `libxhci_a64.a` : Driver library for AARCH64 + - - `libxhci_a32_hardfp.a` : Driver library for AARCH32, using hard floating point + - - `libxhci_a32_softfp.a` : Driver library for AARCH32, using soft floating point + +- To obtain the source code, please contact `opensource_embedded@phytium.com.cn`. +- For porting to non-Phytium CPU platforms, shall contact `opensource_embedded@phytium.com.cn` in advance for permission. \ No newline at end of file diff --git a/kernel/cherryusb/port/xhci/phytium/freertos/usb_config.h b/kernel/cherryusb/port/xhci/phytium/freertos/usb_config.h new file mode 100755 index 0000000..60a9ed1 --- /dev/null +++ b/kernel/cherryusb/port/xhci/phytium/freertos/usb_config.h @@ -0,0 +1,292 @@ +/* + * Copyright : (C) 2024 Phytium Information Technology, Inc. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Modify History: + * Ver   Who        Date         Changes + * ----- ------     --------    -------------------------------------- + * 1.0 zhugengyu 2024/6/26 first commit + */ + +#ifndef CHERRYUSB_CONFIG_H +#define CHERRYUSB_CONFIG_H + +#include "sdkconfig.h" +#include "FreeRTOS.h" +#include "task.h" + +/* ================ USB common Configuration ================ */ + +#define CONFIG_USB_PRINTF(...) printf(__VA_ARGS__) + +void *xhci_mem_malloc(size_t align, size_t size); +void xhci_mem_free(void *ptr); + +#define XHCI_DCACHE_FLUSH (1 << 0) +#define XHCI_DCACHE_INVALIDATE (1 << 1) +void xhci_dcache_sync(void *ptr, size_t len, uint32_t flags); + +unsigned long usb_hc_get_register_base(uint32_t id); + +#define usb_malloc(size) xhci_mem_malloc(sizeof(int), size) +#define usb_free(ptr) xhci_mem_free(ptr) + +#ifndef CONFIG_USB_DBG_LEVEL +#if defined(CONFIG_LOG_ERROR) +#define CONFIG_USB_DBG_LEVEL USB_DBG_ERROR +#elif defined(CONFIG_LOG_WARN) +#define CONFIG_USB_DBG_LEVEL USB_DBG_WARNING +#elif defined(CONFIG_LOG_INFO) +#define CONFIG_USB_DBG_LEVEL USB_DBG_INFO +#elif defined(CONFIG_LOG_DEBUG) || defined(CONFIG_LOG_VERBOS) +#define CONFIG_USB_DBG_LEVEL USB_DBG_LOG +#else +#define CONFIG_USB_DBG_LEVEL USB_DBG_ERROR +#endif +#endif + +/* Enable print with color */ +#define CONFIG_USB_PRINTF_COLOR_ENABLE + +/* data align size when use dma */ +#ifndef CONFIG_USB_ALIGN_SIZE +#define CONFIG_USB_ALIGN_SIZE 4 +#endif + +/* attribute data into no cache ram */ +#define USB_NOCACHE_RAM_SECTION __attribute__((section(".noncacheable"))) + +/* ================= USB Device Stack Configuration ================ */ + +/* Ep0 in and out transfer buffer */ +#ifndef CONFIG_USBDEV_REQUEST_BUFFER_LEN +#define CONFIG_USBDEV_REQUEST_BUFFER_LEN 512 +#endif + +/* Setup packet log for debug */ +// #define CONFIG_USBDEV_SETUP_LOG_PRINT + +/* Send ep0 in data from user buffer instead of copying into ep0 reqdata + * Please note that user buffer must be aligned with CONFIG_USB_ALIGN_SIZE +*/ +// #define CONFIG_USBDEV_EP0_INDATA_NO_COPY + +/* Check if the input descriptor is correct */ +// #define CONFIG_USBDEV_DESC_CHECK + +/* Enable test mode */ +// #define CONFIG_USBDEV_TEST_MODE + +#ifndef CONFIG_USBDEV_MSC_MAX_LUN +#define CONFIG_USBDEV_MSC_MAX_LUN 1 +#endif + +#ifndef CONFIG_USBDEV_MSC_MAX_BUFSIZE +#define CONFIG_USBDEV_MSC_MAX_BUFSIZE 512 +#endif + +#ifndef CONFIG_USBDEV_MSC_MANUFACTURER_STRING +#define CONFIG_USBDEV_MSC_MANUFACTURER_STRING "" +#endif + +#ifndef CONFIG_USBDEV_MSC_PRODUCT_STRING +#define CONFIG_USBDEV_MSC_PRODUCT_STRING "" +#endif + +#ifndef CONFIG_USBDEV_MSC_VERSION_STRING +#define CONFIG_USBDEV_MSC_VERSION_STRING "0.01" +#endif + +// #define CONFIG_USBDEV_MSC_THREAD + +#ifndef CONFIG_USBDEV_MSC_PRIO +#define CONFIG_USBDEV_MSC_PRIO 4 +#endif + +#ifndef CONFIG_USBDEV_MSC_STACKSIZE +#define CONFIG_USBDEV_MSC_STACKSIZE 2048 +#endif + +#ifndef CONFIG_USBDEV_RNDIS_RESP_BUFFER_SIZE +#define CONFIG_USBDEV_RNDIS_RESP_BUFFER_SIZE 156 +#endif + +/* rndis transfer buffer size, must be a multiple of (1536 + 44)*/ +#ifndef CONFIG_USBDEV_RNDIS_ETH_MAX_FRAME_SIZE +#define CONFIG_USBDEV_RNDIS_ETH_MAX_FRAME_SIZE 1580 +#endif + +#ifndef CONFIG_USBDEV_RNDIS_VENDOR_ID +#define CONFIG_USBDEV_RNDIS_VENDOR_ID 0x0000ffff +#endif + +#ifndef CONFIG_USBDEV_RNDIS_VENDOR_DESC +#define CONFIG_USBDEV_RNDIS_VENDOR_DESC "CherryUSB" +#endif + +#define CONFIG_USBDEV_RNDIS_USING_LWIP + +/* ================ USB HOST Stack Configuration ================== */ + +#define CONFIG_USBHOST_MAX_RHPORTS 8 +#define CONFIG_USBHOST_MAX_EXTHUBS 4 +#define CONFIG_USBHOST_MAX_EHPORTS 8 +#define CONFIG_USBHOST_MAX_INTERFACES 8 +#define CONFIG_USBHOST_MAX_INTF_ALTSETTINGS 8 +#define CONFIG_USBHOST_MAX_ENDPOINTS 8 + +#define CONFIG_USBHOST_MAX_CDC_ACM_CLASS 4 +#define CONFIG_USBHOST_MAX_HID_CLASS 4 +#define CONFIG_USBHOST_MAX_MSC_CLASS 2 +#define CONFIG_USBHOST_MAX_AUDIO_CLASS 1 +#define CONFIG_USBHOST_MAX_VIDEO_CLASS 1 + +#define CONFIG_USBHOST_DEV_NAMELEN 16 + +#ifndef CONFIG_USBHOST_PSC_PRIO +#define CONFIG_USBHOST_PSC_PRIO 0 +#endif +#ifndef CONFIG_USBHOST_PSC_STACKSIZE +#define CONFIG_USBHOST_PSC_STACKSIZE 8192 +#endif + +//#define CONFIG_USBHOST_GET_STRING_DESC + +// #define CONFIG_USBHOST_MSOS_ENABLE +#ifndef CONFIG_USBHOST_MSOS_VENDOR_CODE +#define CONFIG_USBHOST_MSOS_VENDOR_CODE 0x00 +#endif + +/* Ep0 max transfer buffer */ +#ifndef CONFIG_USBHOST_REQUEST_BUFFER_LEN +#define CONFIG_USBHOST_REQUEST_BUFFER_LEN 512 +#endif + +#ifndef CONFIG_USBHOST_CONTROL_TRANSFER_TIMEOUT +#define CONFIG_USBHOST_CONTROL_TRANSFER_TIMEOUT 500 +#endif + +#ifndef CONFIG_USBHOST_MSC_TIMEOUT +#define CONFIG_USBHOST_MSC_TIMEOUT 0xffffffff +#endif + +#ifndef CONFIG_INPUT_MOUSE_WHEEL +#define CONFIG_INPUT_MOUSE_WHEEL +#endif + +/* This parameter affects usb performance, and depends on (TCP_WND)tcp eceive windows size, + * you can change to 2K ~ 16K and must be larger than TCP RX windows size in order to avoid being overflow. + */ +#ifndef CONFIG_USBHOST_RNDIS_ETH_MAX_RX_SIZE +#define CONFIG_USBHOST_RNDIS_ETH_MAX_RX_SIZE (2048) +#endif + +/* Because lwip do not support multi pbuf at a time, so increasing this variable has no performance improvement */ +#ifndef CONFIG_USBHOST_RNDIS_ETH_MAX_TX_SIZE +#define CONFIG_USBHOST_RNDIS_ETH_MAX_TX_SIZE (2048) +#endif + +/* This parameter affects usb performance, and depends on (TCP_WND)tcp eceive windows size, + * you can change to 2K ~ 16K and must be larger than TCP RX windows size in order to avoid being overflow. + */ +#ifndef CONFIG_USBHOST_CDC_NCM_ETH_MAX_RX_SIZE +#define CONFIG_USBHOST_CDC_NCM_ETH_MAX_RX_SIZE (2048) +#endif +/* Because lwip do not support multi pbuf at a time, so increasing this variable has no performance improvement */ +#ifndef CONFIG_USBHOST_CDC_NCM_ETH_MAX_TX_SIZE +#define CONFIG_USBHOST_CDC_NCM_ETH_MAX_TX_SIZE (2048) +#endif + +/* This parameter affects usb performance, and depends on (TCP_WND)tcp eceive windows size, + * you can change to 2K ~ 16K and must be larger than TCP RX windows size in order to avoid being overflow. + */ +#ifndef CONFIG_USBHOST_ASIX_ETH_MAX_RX_SIZE +#define CONFIG_USBHOST_ASIX_ETH_MAX_RX_SIZE (2048) +#endif +/* Because lwip do not support multi pbuf at a time, so increasing this variable has no performance improvement */ +#ifndef CONFIG_USBHOST_ASIX_ETH_MAX_TX_SIZE +#define CONFIG_USBHOST_ASIX_ETH_MAX_TX_SIZE (2048) +#endif + +/* This parameter affects usb performance, and depends on (TCP_WND)tcp eceive windows size, + * you can change to 2K ~ 16K and must be larger than TCP RX windows size in order to avoid being overflow. + */ +#ifndef CONFIG_USBHOST_RTL8152_ETH_MAX_RX_SIZE +#define CONFIG_USBHOST_RTL8152_ETH_MAX_RX_SIZE (2048) +#endif +/* Because lwip do not support multi pbuf at a time, so increasing this variable has no performance improvement */ +#ifndef CONFIG_USBHOST_RTL8152_ETH_MAX_TX_SIZE +#define CONFIG_USBHOST_RTL8152_ETH_MAX_TX_SIZE (2048) +#endif + +#define CONFIG_USBHOST_BLUETOOTH_HCI_H4 +// #define CONFIG_USBHOST_BLUETOOTH_HCI_LOG + +#ifndef CONFIG_USBHOST_BLUETOOTH_TX_SIZE +#define CONFIG_USBHOST_BLUETOOTH_TX_SIZE 2048 +#endif +#ifndef CONFIG_USBHOST_BLUETOOTH_RX_SIZE +#define CONFIG_USBHOST_BLUETOOTH_RX_SIZE 2048 +#endif + +/* ================ USB Device Port Configuration ================*/ + +#ifndef CONFIG_USBDEV_MAX_BUS +#define CONFIG_USBDEV_MAX_BUS 2 // for now, bus num must be 1 except hpm ip +#endif + +#ifndef CONFIG_USBDEV_EP_NUM +#define CONFIG_USBDEV_EP_NUM 8 +#endif + +/* ---------------- FSDEV Configuration ---------------- */ +//#define CONFIG_USBDEV_FSDEV_PMA_ACCESS 2 // maybe 1 or 2, many chips may have a difference + +/* ---------------- DWC2 Configuration ---------------- */ +// #define CONFIG_USB_DWC2_RXALL_FIFO_SIZE (1024 / 4) +// #define CONFIG_USB_DWC2_TX0_FIFO_SIZE (64 / 4) +// #define CONFIG_USB_DWC2_TX1_FIFO_SIZE (512 / 4) +// #define CONFIG_USB_DWC2_TX2_FIFO_SIZE (64 / 4) +// #define CONFIG_USB_DWC2_TX3_FIFO_SIZE (64 / 4) +// #define CONFIG_USB_DWC2_TX4_FIFO_SIZE (0 / 4) +// #define CONFIG_USB_DWC2_TX5_FIFO_SIZE (0 / 4) +// #define CONFIG_USB_DWC2_TX6_FIFO_SIZE (0 / 4) +// #define CONFIG_USB_DWC2_TX7_FIFO_SIZE (0 / 4) +// #define CONFIG_USB_DWC2_TX8_FIFO_SIZE (0 / 4) + +/* ---------------- MUSB Configuration ---------------- */ +// #define CONFIG_USB_MUSB_SUNXI + +/* ================ USB Host Port Configuration ==================*/ +#ifndef CONFIG_USBHOST_MAX_BUS +#define CONFIG_USBHOST_MAX_BUS 2 +#endif + +#ifndef CONFIG_USBHOST_PIPE_NUM +#define CONFIG_USBHOST_PIPE_NUM 10 +#endif + +/* ---------------- EHCI Configuration ---------------- */ + +#define CONFIG_USB_EHCI_HCCR_OFFSET (0x0) +#define CONFIG_USB_EHCI_FRAME_LIST_SIZE 1024 +#define CONFIG_USB_EHCI_QH_NUM CONFIG_USBHOST_PIPE_NUM +#define CONFIG_USB_EHCI_QTD_NUM 3 +#define CONFIG_USB_EHCI_ITD_NUM 20 +// #define CONFIG_USB_EHCI_HCOR_RESERVED_DISABLE +// #define CONFIG_USB_EHCI_CONFIGFLAG +// #define CONFIG_USB_EHCI_ISO +// #define CONFIG_USB_EHCI_WITH_OHCI + +/* ---------------- OHCI Configuration ---------------- */ +#define CONFIG_USB_OHCI_HCOR_OFFSET (0x0) + +/* ---------------- XHCI Configuration ---------------- */ +#define CONFIG_USB_XHCI_HCCR_OFFSET (0x0) + +#ifndef CONFIG_USB_XHCI_ENABLE_SOFT_ISR +#define CONFIG_USB_XHCI_ENABLE_SOFT_ISR 0 +#endif + +#endif diff --git a/kernel/cherryusb/port/xhci/phytium/freertos/usb_glue_phytium.c b/kernel/cherryusb/port/xhci/phytium/freertos/usb_glue_phytium.c new file mode 100644 index 0000000..e939b46 --- /dev/null +++ b/kernel/cherryusb/port/xhci/phytium/freertos/usb_glue_phytium.c @@ -0,0 +1,135 @@ +/* + * Copyright : (C) 2024 Phytium Information Technology, Inc. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Modify History: + * Ver   Who        Date         Changes + * ----- ------     --------    -------------------------------------- + * 1.0 zhugengyu 2024/6/26 first commit + */ +/***************************** Include Files *********************************/ +#include +#include + +#include "sdkconfig.h" + +#include "fassert.h" +#include "finterrupt.h" +#include "fcpu_info.h" +#include "fdebug.h" +#include "fcache.h" +#include "fmemory_pool.h" + +#include "usbh_core.h" + +/************************** Constant Definitions *****************************/ +#define FUSB_MEMP_TOTAL_SIZE SZ_1M + +/**************************** Type Definitions *******************************/ +#if defined(CONFIG_CHERRY_USB_PORT_XHCI_PLATFROM) +void usb_hc_setup_xhci_interrupt(u32 id); +#endif +#if defined(CONFIG_CHERRY_USB_PORT_XHCI_PCIE) +unsigned long usb_hc_setup_xhci_pcie(struct usbh_bus *bus); +#endif +/************************** Variable Definitions *****************************/ +static FMemp memp; +static u8 memp_buf[FUSB_MEMP_TOTAL_SIZE] __attribute__((aligned(8))) = {0}; +static u32 memp_ref_cnt = 0; + +static void xhci_mem_init(void) +{ + if (FT_COMPONENT_IS_READY != memp.is_ready) + { + USB_ASSERT(FT_SUCCESS == FMempInit(&memp, &memp_buf[0], &memp_buf[0] + FUSB_MEMP_TOTAL_SIZE)); + } +} + +static void xhci_mem_deinit(void) +{ + if (FT_COMPONENT_IS_READY == memp.is_ready) + { + FMempDeinit(&memp); + } +} + +void *xhci_mem_malloc(size_t align, size_t size) +{ + void *result = FMempMallocAlign(&memp, size, align); + + if (result) + { + memset(result, 0U, size); + } + + return result; +} + +void xhci_mem_free(void *ptr) +{ + if (NULL != ptr) + { + FMempFree(&memp, ptr); + } +} + +void xhci_dcache_sync(void *ptr, size_t len, uint32_t flags) +{ + if (flags & XHCI_DCACHE_FLUSH) + { + FCacheDCacheFlushRange((uintptr_t)ptr, len); + } + else if (flags & XHCI_DCACHE_INVALIDATE) + { + FCacheDCacheInvalidateRange((uintptr_t)ptr, len); + } +} + +void usb_assert(const char *filename, int linenum) +{ + FAssert(filename, linenum, 0xff); +} + +extern int vApplicationInIrq(void); +int xPortIsInsideInterrupt(void) +{ + return vApplicationInIrq(); +} + +void usb_hc_low_level_init(struct usbh_bus *bus) +{ + if (memp_ref_cnt == 0) { + xhci_mem_init(); /* create memory pool before first bus init */ + } + + memp_ref_cnt++; /* one more bus is using the memory pool */ + + if (bus->hcd.reg_base != 0) { +#if defined(CONFIG_CHERRY_USB_PORT_XHCI_PLATFROM) + /* platform XHCI controller */ + usb_hc_setup_xhci_interrupt(bus->busid); +#else + USB_LOG_ERR("Platform XHCI not supported !!!\n"); + USB_ASSERT(0); +#endif + } else { +#if defined(CONFIG_CHERRY_USB_PORT_XHCI_PCIE) + /* pcie XHCI controller */ + bus->hcd.reg_base = usb_hc_setup_xhci_pcie(bus); + bus->busid = 0U; /* only support one pcie lane */ +#else + USB_LOG_ERR("Invalid register base !!!\n"); + USB_ASSERT(0); +#endif + } +} + +void usb_hc_low_level_deinit(struct usbh_bus *bus) +{ + memp_ref_cnt--; /* one more bus is leaving */ + + if (memp_ref_cnt == 0) { + xhci_mem_deinit(); /* release memory pool after the last bus left */ + } +} \ No newline at end of file diff --git a/kernel/cherryusb/port/xhci/phytium/freertos/usb_glue_phytium_pcie.c b/kernel/cherryusb/port/xhci/phytium/freertos/usb_glue_phytium_pcie.c new file mode 100644 index 0000000..37922cd --- /dev/null +++ b/kernel/cherryusb/port/xhci/phytium/freertos/usb_glue_phytium_pcie.c @@ -0,0 +1,175 @@ +/* + * Copyright : (C) 2024 Phytium Information Technology, Inc. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Modify History: + * Ver   Who        Date         Changes + * ----- ------     --------    -------------------------------------- + * 1.0 zhugengyu 2024/6/26 first commit + */ +/***************************** Include Files *********************************/ +#include +#include + +#include "FreeRTOS.h" +#include "task.h" + +#include "sdkconfig.h" + +#include "fassert.h" +#include "finterrupt.h" + +#include "usbh_core.h" + +#if defined(CONFIG_CHERRY_USB_PORT_XHCI_PCIE) + +#include "fpcie_ecam.h" +#include "fpcie_ecam_common.h" + +/************************** Constant Definitions *****************************/ + +/**************************** Type Definitions *******************************/ + +/************************** Variable Definitions *****************************/ +static FPcieEcam pcie_device; + +static void usb_hc_xhci_pcie_interrupt_handler(void *param) +{ + extern void USBH_IRQHandler(uint8_t busid); + USBH_IRQHandler((uint8_t)(uintptr_t)0); +} + +static void usb_hc_pcie_intx_init(FPcieEcam *instance_p) +{ + u32 cpu_id; + u32 irq_num = FPCIE_ECAM_INTA_IRQ_NUM; + u32 irq_priority = 13U; + + (void)GetCpuId(&cpu_id); + USB_LOG_DBG("interrupt num: %d", irq_num); + (void)InterruptSetTargetCpus(irq_num, cpu_id); + + InterruptSetPriority(irq_num, irq_priority); + + /* register intr callback */ + InterruptInstall(irq_num, + FPcieEcamIntxIrqHandler, + &pcie_device, + NULL); + + /* enable irq */ + InterruptUmask(irq_num); +} + +static FError usb_hc_pcie_init(FPcieEcam *pcie_device) +{ + FError ret = FT_SUCCESS; + + ret = FPcieEcamCfgInitialize(pcie_device, FPcieEcamLookupConfig(FPCIE_ECAM_INSTANCE0), NULL); + if (FT_SUCCESS != ret) + { + return ret; + } + + USB_LOG_DBG("\n"); + USB_LOG_DBG(" PCI:\n"); + USB_LOG_DBG(" B:D:F VID:PID parent_BDF class_code\n"); + ret = FPcieEcamEnumerateBus(pcie_device, 0); + if (FT_SUCCESS != ret) + { + return ret; + } + + usb_hc_pcie_intx_init(pcie_device); /* register pcie_device intx handler */ + + return FT_SUCCESS; +} + +static FError usb_hc_pcie_install_irq(FPcieEcam *pcie_device, struct usbh_bus *usb, u8 bus, u8 device, u8 function) +{ + FError ret = FT_SUCCESS; + FPcieIntxFun intx_fun; + intx_fun.IntxCallBack = usb_hc_xhci_pcie_interrupt_handler; + intx_fun.args = usb; + intx_fun.bus = bus; + intx_fun.device = device; + intx_fun.function = function; + + ret = FPcieEcamIntxRegister(pcie_device, bus, device, function, &intx_fun); + if (FT_SUCCESS != ret) + { + USB_LOG_ERR("FPcieIntxRegiterIrqHandler failed.\n"); + return ret; + } + + return ret; +} + +unsigned long usb_hc_setup_xhci_pcie(struct usbh_bus *usb) +{ + FError ret = FT_SUCCESS; + s32 host; + u32 bdf; + u32 class; + u16 pci_command; + u8 bus,device,function; + u16 vid, did; + uintptr bar0_addr = 0; + uintptr bar1_addr = 0; + unsigned long usb_base = 0U; + const u32 class_code = FPCI_CLASS_SERIAL_USB_XHCI; /* sub class and base class definition */ + u32 config_data; + + ret = usb_hc_pcie_init(&pcie_device); + if (FT_SUCCESS != ret) + { + USB_LOG_ERR("FPcieInit failed.\n"); + return usb_base; + } + + /* find xhci host from pcie_device instance */ + for (host = 0; host < pcie_device.scans_bdf_count; host++) + { + bus = pcie_device.scans_bdf[host].bus; + device = pcie_device.scans_bdf[host].device; + function= pcie_device.scans_bdf[host].function; + + FPcieEcamReadConfigSpace(&pcie_device,bus,device,function,FPCIE_CCR_REV_CLASSID_REGS,&config_data); + class = config_data >> 8; + + if (class == class_code) + { + (void)FPcieEcamReadConfigSpace(&pcie_device,bus,device,function,FPCIE_CCR_ID_REG,&config_data); + vid = FPCIE_CCR_VENDOR_ID_MASK(config_data); + did = FPCIE_CCR_DEVICE_ID_MASK(config_data); + + USB_LOG_DBG("xHCI-PCI HOST found !!!, b.d.f = %x.%x.%x\n", bus, device, function); + FPcieEcamReadConfigSpace(&pcie_device,bus,device,function,FPCIE_CCR_BAR_ADDR0_REGS,(u32 *)&bar0_addr); + bar0_addr &= ~0xfff; + +#if defined(FAARCH64_USE) + FPcieEcamReadConfigSpace(&pcie_device,bus,device,function,FPCIE_CCR_BAR_ADDR1_REGS,(u32 *)&bar1_addr); +#endif + + USB_LOG_DBG("FSataPcieIntrInstall BarAddress %p:%p", bar1_addr, bar0_addr); + + if ((0x0 == bar0_addr) && (0x0 == bar1_addr)) + { + USB_LOG_ERR("Invalid Bar address"); + return usb_base; + } + + usb_hc_pcie_install_irq(&pcie_device, usb, bus, device, function); +#if defined(FAARCH64_USE) + usb_base = (bar1_addr << 32U) | bar0_addr; +#else + usb_base = bar0_addr; +#endif + USB_LOG_INFO("xHCI base address: 0x%lx", usb_base); + } + } + + return usb_base; +} +#endif \ No newline at end of file diff --git a/kernel/cherryusb/port/xhci/phytium/freertos/usb_glue_phytium_plat.c b/kernel/cherryusb/port/xhci/phytium/freertos/usb_glue_phytium_plat.c new file mode 100755 index 0000000..8671e0e --- /dev/null +++ b/kernel/cherryusb/port/xhci/phytium/freertos/usb_glue_phytium_plat.c @@ -0,0 +1,64 @@ +/* + * Copyright : (C) 2024 Phytium Information Technology, Inc. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Modify History: + * Ver   Who        Date         Changes + * ----- ------     --------    -------------------------------------- + * 1.0 zhugengyu 2024/6/26 first commit + */ +/***************************** Include Files *********************************/ +#include +#include + +#include "sdkconfig.h" + +#include "fassert.h" +#include "finterrupt.h" +#include "fcpu_info.h" +#include "fdebug.h" +#include "fcache.h" +#include "fmemory_pool.h" + +#include "usbh_core.h" + +/************************** Constant Definitions *****************************/ + +/**************************** Type Definitions *******************************/ + +/************************** Variable Definitions *****************************/ +static void usb_hc_xhci_interrupt_handler(s32 vector, void *param) +{ + extern void USBH_IRQHandler(uint8_t busid); + USBH_IRQHandler((uint8_t)(uintptr_t)param); +} + +void usb_hc_setup_xhci_interrupt(u32 id) +{ + u32 cpu_id; + u32 irq_num = (id == FUSB3_ID_0) ? FUSB3_0_IRQ_NUM : FUSB3_1_IRQ_NUM; + u32 irq_priority = 13U; + + GetCpuId(&cpu_id); + InterruptSetTargetCpus(irq_num, cpu_id); + + InterruptSetPriority(irq_num, irq_priority); + + /* register intr callback */ + InterruptInstall(irq_num, + usb_hc_xhci_interrupt_handler, + (void *)(uintptr_t)id, + NULL); + + /* enable irq */ + InterruptUmask(irq_num); +} + +unsigned long usb_hc_get_register_base(uint32_t id) +{ + if (FUSB3_ID_0 == id) + return FUSB3_0_BASE_ADDR + FUSB3_XHCI_OFFSET; + else + return FUSB3_1_BASE_ADDR + FUSB3_XHCI_OFFSET; +} \ No newline at end of file diff --git a/kernel/cherryusb/port/xhci/phytium/rt-thread/usb_config.h b/kernel/cherryusb/port/xhci/phytium/rt-thread/usb_config.h new file mode 100644 index 0000000..460d124 --- /dev/null +++ b/kernel/cherryusb/port/xhci/phytium/rt-thread/usb_config.h @@ -0,0 +1,289 @@ +/* + * Copyright : (C) 2024 Phytium Information Technology, Inc. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Modify History: + * Ver   Who        Date         Changes + * ----- ------     --------    -------------------------------------- + * 1.0 zhugengyu 2024/6/26 first commit + */ +#ifndef CHERRYUSB_CONFIG_H +#define CHERRYUSB_CONFIG_H + +#include "rtthread.h" + +/* ================ USB common Configuration ================ */ + +#define CONFIG_USB_PRINTF(...) rt_kprintf(__VA_ARGS__) + +void *xhci_mem_malloc(size_t align, size_t size); +void xhci_mem_free(void *ptr); + +#define XHCI_DCACHE_FLUSH (1 << 0) +#define XHCI_DCACHE_INVALIDATE (1 << 1) +void xhci_dcache_sync(void *ptr, size_t len, uint32_t flags); + +unsigned long usb_hc_get_register_base(uint32_t id); + +#define usb_malloc(size) xhci_mem_malloc(sizeof(int), size) +#define usb_free(ptr) xhci_mem_free(ptr) + +#ifndef CONFIG_USB_DBG_LEVEL +#if defined(CONFIG_LOG_ERROR) +#define CONFIG_USB_DBG_LEVEL USB_DBG_ERROR +#elif defined(CONFIG_LOG_WARN) +#define CONFIG_USB_DBG_LEVEL USB_DBG_WARNING +#elif defined(CONFIG_LOG_INFO) +#define CONFIG_USB_DBG_LEVEL USB_DBG_INFO +#elif defined(CONFIG_LOG_DEBUG) || defined(CONFIG_LOG_VERBOS) +#define CONFIG_USB_DBG_LEVEL USB_DBG_LOG +#else +#define CONFIG_USB_DBG_LEVEL USB_DBG_ERROR +#endif +#endif + +/* Enable print with color */ +#define CONFIG_USB_PRINTF_COLOR_ENABLE + +/* data align size when use dma */ +#ifndef CONFIG_USB_ALIGN_SIZE +#define CONFIG_USB_ALIGN_SIZE 4 +#endif + +/* attribute data into no cache ram */ +#define USB_NOCACHE_RAM_SECTION __attribute__((section(".noncacheable"))) + +/* ================= USB Device Stack Configuration ================ */ + +/* Ep0 in and out transfer buffer */ +#ifndef CONFIG_USBDEV_REQUEST_BUFFER_LEN +#define CONFIG_USBDEV_REQUEST_BUFFER_LEN 512 +#endif + +/* Setup packet log for debug */ +// #define CONFIG_USBDEV_SETUP_LOG_PRINT + +/* Send ep0 in data from user buffer instead of copying into ep0 reqdata + * Please note that user buffer must be aligned with CONFIG_USB_ALIGN_SIZE +*/ +// #define CONFIG_USBDEV_EP0_INDATA_NO_COPY + +/* Check if the input descriptor is correct */ +// #define CONFIG_USBDEV_DESC_CHECK + +/* Enable test mode */ +// #define CONFIG_USBDEV_TEST_MODE + +#ifndef CONFIG_USBDEV_MSC_MAX_LUN +#define CONFIG_USBDEV_MSC_MAX_LUN 1 +#endif + +#ifndef CONFIG_USBDEV_MSC_MAX_BUFSIZE +#define CONFIG_USBDEV_MSC_MAX_BUFSIZE 512 +#endif + +#ifndef CONFIG_USBDEV_MSC_MANUFACTURER_STRING +#define CONFIG_USBDEV_MSC_MANUFACTURER_STRING "" +#endif + +#ifndef CONFIG_USBDEV_MSC_PRODUCT_STRING +#define CONFIG_USBDEV_MSC_PRODUCT_STRING "" +#endif + +#ifndef CONFIG_USBDEV_MSC_VERSION_STRING +#define CONFIG_USBDEV_MSC_VERSION_STRING "0.01" +#endif + +// #define CONFIG_USBDEV_MSC_THREAD + +#ifndef CONFIG_USBDEV_MSC_PRIO +#define CONFIG_USBDEV_MSC_PRIO 4 +#endif + +#ifndef CONFIG_USBDEV_MSC_STACKSIZE +#define CONFIG_USBDEV_MSC_STACKSIZE 2048 +#endif + +#ifndef CONFIG_USBDEV_RNDIS_RESP_BUFFER_SIZE +#define CONFIG_USBDEV_RNDIS_RESP_BUFFER_SIZE 156 +#endif + +/* rndis transfer buffer size, must be a multiple of (1536 + 44)*/ +#ifndef CONFIG_USBDEV_RNDIS_ETH_MAX_FRAME_SIZE +#define CONFIG_USBDEV_RNDIS_ETH_MAX_FRAME_SIZE 1580 +#endif + +#ifndef CONFIG_USBDEV_RNDIS_VENDOR_ID +#define CONFIG_USBDEV_RNDIS_VENDOR_ID 0x0000ffff +#endif + +#ifndef CONFIG_USBDEV_RNDIS_VENDOR_DESC +#define CONFIG_USBDEV_RNDIS_VENDOR_DESC "CherryUSB" +#endif + +#define CONFIG_USBDEV_RNDIS_USING_LWIP + +/* ================ USB HOST Stack Configuration ================== */ + +#define CONFIG_USBHOST_MAX_RHPORTS 8 +#define CONFIG_USBHOST_MAX_EXTHUBS 4 +#define CONFIG_USBHOST_MAX_EHPORTS 8 +#define CONFIG_USBHOST_MAX_INTERFACES 8 +#define CONFIG_USBHOST_MAX_INTF_ALTSETTINGS 8 +#define CONFIG_USBHOST_MAX_ENDPOINTS 8 + +#define CONFIG_USBHOST_MAX_CDC_ACM_CLASS 4 +#define CONFIG_USBHOST_MAX_HID_CLASS 4 +#define CONFIG_USBHOST_MAX_MSC_CLASS 2 +#define CONFIG_USBHOST_MAX_AUDIO_CLASS 1 +#define CONFIG_USBHOST_MAX_VIDEO_CLASS 1 + +#define CONFIG_USBHOST_DEV_NAMELEN 16 + +#ifndef CONFIG_USBHOST_PSC_PRIO +#define CONFIG_USBHOST_PSC_PRIO 0 +#endif +#ifndef CONFIG_USBHOST_PSC_STACKSIZE +#define CONFIG_USBHOST_PSC_STACKSIZE 8192 +#endif + +//#define CONFIG_USBHOST_GET_STRING_DESC + +// #define CONFIG_USBHOST_MSOS_ENABLE +#ifndef CONFIG_USBHOST_MSOS_VENDOR_CODE +#define CONFIG_USBHOST_MSOS_VENDOR_CODE 0x00 +#endif + +/* Ep0 max transfer buffer */ +#ifndef CONFIG_USBHOST_REQUEST_BUFFER_LEN +#define CONFIG_USBHOST_REQUEST_BUFFER_LEN 512 +#endif + +#ifndef CONFIG_USBHOST_CONTROL_TRANSFER_TIMEOUT +#define CONFIG_USBHOST_CONTROL_TRANSFER_TIMEOUT 500 +#endif + +#ifndef CONFIG_USBHOST_MSC_TIMEOUT +#define CONFIG_USBHOST_MSC_TIMEOUT 0xffffffff +#endif + +#ifndef CONFIG_INPUT_MOUSE_WHEEL +#define CONFIG_INPUT_MOUSE_WHEEL +#endif + +/* This parameter affects usb performance, and depends on (TCP_WND)tcp eceive windows size, + * you can change to 2K ~ 16K and must be larger than TCP RX windows size in order to avoid being overflow. + */ +#ifndef CONFIG_USBHOST_RNDIS_ETH_MAX_RX_SIZE +#define CONFIG_USBHOST_RNDIS_ETH_MAX_RX_SIZE (2048) +#endif + +/* Because lwip do not support multi pbuf at a time, so increasing this variable has no performance improvement */ +#ifndef CONFIG_USBHOST_RNDIS_ETH_MAX_TX_SIZE +#define CONFIG_USBHOST_RNDIS_ETH_MAX_TX_SIZE (2048) +#endif + +/* This parameter affects usb performance, and depends on (TCP_WND)tcp eceive windows size, + * you can change to 2K ~ 16K and must be larger than TCP RX windows size in order to avoid being overflow. + */ +#ifndef CONFIG_USBHOST_CDC_NCM_ETH_MAX_RX_SIZE +#define CONFIG_USBHOST_CDC_NCM_ETH_MAX_RX_SIZE (2048) +#endif +/* Because lwip do not support multi pbuf at a time, so increasing this variable has no performance improvement */ +#ifndef CONFIG_USBHOST_CDC_NCM_ETH_MAX_TX_SIZE +#define CONFIG_USBHOST_CDC_NCM_ETH_MAX_TX_SIZE (2048) +#endif + +/* This parameter affects usb performance, and depends on (TCP_WND)tcp eceive windows size, + * you can change to 2K ~ 16K and must be larger than TCP RX windows size in order to avoid being overflow. + */ +#ifndef CONFIG_USBHOST_ASIX_ETH_MAX_RX_SIZE +#define CONFIG_USBHOST_ASIX_ETH_MAX_RX_SIZE (2048) +#endif +/* Because lwip do not support multi pbuf at a time, so increasing this variable has no performance improvement */ +#ifndef CONFIG_USBHOST_ASIX_ETH_MAX_TX_SIZE +#define CONFIG_USBHOST_ASIX_ETH_MAX_TX_SIZE (2048) +#endif + +/* This parameter affects usb performance, and depends on (TCP_WND)tcp eceive windows size, + * you can change to 2K ~ 16K and must be larger than TCP RX windows size in order to avoid being overflow. + */ +#ifndef CONFIG_USBHOST_RTL8152_ETH_MAX_RX_SIZE +#define CONFIG_USBHOST_RTL8152_ETH_MAX_RX_SIZE (2048) +#endif +/* Because lwip do not support multi pbuf at a time, so increasing this variable has no performance improvement */ +#ifndef CONFIG_USBHOST_RTL8152_ETH_MAX_TX_SIZE +#define CONFIG_USBHOST_RTL8152_ETH_MAX_TX_SIZE (2048) +#endif + +#define CONFIG_USBHOST_BLUETOOTH_HCI_H4 +// #define CONFIG_USBHOST_BLUETOOTH_HCI_LOG + +#ifndef CONFIG_USBHOST_BLUETOOTH_TX_SIZE +#define CONFIG_USBHOST_BLUETOOTH_TX_SIZE 2048 +#endif +#ifndef CONFIG_USBHOST_BLUETOOTH_RX_SIZE +#define CONFIG_USBHOST_BLUETOOTH_RX_SIZE 2048 +#endif + +/* ================ USB Device Port Configuration ================*/ + +#ifndef CONFIG_USBDEV_MAX_BUS +#define CONFIG_USBDEV_MAX_BUS 2 // for now, bus num must be 1 except hpm ip +#endif + +#ifndef CONFIG_USBDEV_EP_NUM +#define CONFIG_USBDEV_EP_NUM 8 +#endif + +/* ---------------- FSDEV Configuration ---------------- */ +//#define CONFIG_USBDEV_FSDEV_PMA_ACCESS 2 // maybe 1 or 2, many chips may have a difference + +/* ---------------- DWC2 Configuration ---------------- */ +// #define CONFIG_USB_DWC2_RXALL_FIFO_SIZE (1024 / 4) +// #define CONFIG_USB_DWC2_TX0_FIFO_SIZE (64 / 4) +// #define CONFIG_USB_DWC2_TX1_FIFO_SIZE (512 / 4) +// #define CONFIG_USB_DWC2_TX2_FIFO_SIZE (64 / 4) +// #define CONFIG_USB_DWC2_TX3_FIFO_SIZE (64 / 4) +// #define CONFIG_USB_DWC2_TX4_FIFO_SIZE (0 / 4) +// #define CONFIG_USB_DWC2_TX5_FIFO_SIZE (0 / 4) +// #define CONFIG_USB_DWC2_TX6_FIFO_SIZE (0 / 4) +// #define CONFIG_USB_DWC2_TX7_FIFO_SIZE (0 / 4) +// #define CONFIG_USB_DWC2_TX8_FIFO_SIZE (0 / 4) + +/* ---------------- MUSB Configuration ---------------- */ +// #define CONFIG_USB_MUSB_SUNXI + +/* ================ USB Host Port Configuration ==================*/ +#ifndef CONFIG_USBHOST_MAX_BUS +#define CONFIG_USBHOST_MAX_BUS 2 +#endif + +#ifndef CONFIG_USBHOST_PIPE_NUM +#define CONFIG_USBHOST_PIPE_NUM 10 +#endif + +/* ---------------- EHCI Configuration ---------------- */ + +#define CONFIG_USB_EHCI_HCCR_OFFSET (0x0) +#define CONFIG_USB_EHCI_FRAME_LIST_SIZE 1024 +#define CONFIG_USB_EHCI_QH_NUM CONFIG_USBHOST_PIPE_NUM +#define CONFIG_USB_EHCI_QTD_NUM 3 +#define CONFIG_USB_EHCI_ITD_NUM 20 +// #define CONFIG_USB_EHCI_HCOR_RESERVED_DISABLE +// #define CONFIG_USB_EHCI_CONFIGFLAG +// #define CONFIG_USB_EHCI_ISO +// #define CONFIG_USB_EHCI_WITH_OHCI + +/* ---------------- OHCI Configuration ---------------- */ +#define CONFIG_USB_OHCI_HCOR_OFFSET (0x0) + +/* ---------------- XHCI Configuration ---------------- */ +#define CONFIG_USB_XHCI_HCCR_OFFSET (0x0) + +#ifndef CONFIG_USB_XHCI_ENABLE_SOFT_ISR +#define CONFIG_USB_XHCI_ENABLE_SOFT_ISR 0 +#endif + +#endif diff --git a/kernel/cherryusb/port/xhci/phytium/rt-thread/usb_glue_phytium.c b/kernel/cherryusb/port/xhci/phytium/rt-thread/usb_glue_phytium.c new file mode 100644 index 0000000..1f72f31 --- /dev/null +++ b/kernel/cherryusb/port/xhci/phytium/rt-thread/usb_glue_phytium.c @@ -0,0 +1,65 @@ +/* + * Copyright : (C) 2024 Phytium Information Technology, Inc. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Modify History: + * Ver   Who        Date         Changes + * ----- ------     --------    -------------------------------------- + * 1.0 zhugengyu 2024/6/26 first commit + */ +#include "rtthread.h" +#include "usbh_core.h" + +#include "usb_config.h" + +void usb_hc_setup_xhci_interrupt(uint32_t id); +void usb_hc_revoke_xhci_interrupt(uint32_t id); + +void *xhci_mem_malloc(size_t align, size_t size) +{ + void *result = rt_malloc_align(size, align); + + if (result) + { + memset(result, 0U, size); + } + + return result; +} + +void xhci_mem_free(void *ptr) +{ + if (NULL != ptr) + { + rt_free(ptr); + } +} + +void xhci_dcache_sync(void *ptr, size_t len, uint32_t flags) +{ + if (flags & XHCI_DCACHE_FLUSH) + { + rt_hw_cpu_dcache_ops(RT_HW_CACHE_FLUSH, ptr, len); + } + else if (flags & XHCI_DCACHE_INVALIDATE) + { + rt_hw_cpu_dcache_ops(RT_HW_CACHE_INVALIDATE, ptr, len); + } +} + +void usb_assert(const char *filename, int linenum) +{ + rt_assert_handler("", filename, linenum); +} + +void usb_hc_low_level_init(struct usbh_bus *bus) +{ + /* platform XHCI controller */ + usb_hc_setup_xhci_interrupt(bus->busid); +} + +void usb_hc_low_level_deinit(struct usbh_bus *bus) +{ + usb_hc_revoke_xhci_interrupt(bus->busid); +} \ No newline at end of file diff --git a/kernel/cherryusb/port/xhci/phytium/rt-thread/usb_glue_phytium_plat.c b/kernel/cherryusb/port/xhci/phytium/rt-thread/usb_glue_phytium_plat.c new file mode 100644 index 0000000..754dad7 --- /dev/null +++ b/kernel/cherryusb/port/xhci/phytium/rt-thread/usb_glue_phytium_plat.c @@ -0,0 +1,49 @@ +/* + * Copyright : (C) 2024 Phytium Information Technology, Inc. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Modify History: + * Ver   Who        Date         Changes + * ----- ------     --------    -------------------------------------- + * 1.0 zhugengyu 2024/6/26 first commit + */ +#include "rtthread.h" +#include "interrupt.h" + +#include "fparameters.h" + +void USBH_IRQHandler(uint8_t busid); + +static void usb_hc_xhci_interrupt_handler(int irqno, void *param) +{ + if (irqno == FUSB3_0_IRQ_NUM) { + USBH_IRQHandler(FUSB3_ID_0); + } else if (irqno == FUSB3_1_IRQ_NUM) { + USBH_IRQHandler(FUSB3_ID_1); + } +} + +void usb_hc_setup_xhci_interrupt(uint32_t id) +{ + uint32_t irq_num = (id == FUSB3_ID_0) ? FUSB3_0_IRQ_NUM : FUSB3_1_IRQ_NUM; + rt_hw_interrupt_set_priority(irq_num, 0xd0); + rt_hw_interrupt_install(irq_num, usb_hc_xhci_interrupt_handler, + NULL, "xhci"); + rt_hw_interrupt_umask(irq_num); +} + +void usb_hc_revoke_xhci_interrupt(uint32_t id) +{ + uint32_t irq_num = (id == FUSB3_ID_0) ? FUSB3_0_IRQ_NUM : FUSB3_1_IRQ_NUM; + + rt_hw_interrupt_mask(irq_num); +} + +unsigned long usb_hc_get_register_base(uint32_t id) +{ + if (FUSB3_ID_0 == id) + return FUSB3_0_BASE_ADDR + FUSB3_XHCI_OFFSET; + else + return FUSB3_1_BASE_ADDR + FUSB3_XHCI_OFFSET; +} \ No newline at end of file diff --git a/kernel/device_manager.c b/kernel/device_manager.c new file mode 100644 index 0000000..5c9098e --- /dev/null +++ b/kernel/device_manager.c @@ -0,0 +1,49 @@ +#include "pro_os.h" +#include +#include "serial.h" + +typedef struct { + char label[32]; + int global_id; + int type_id; + storage_type_t type; + storage_device_t* dev; +} dev_info_t; + +static dev_info_t devices[32]; +static int total_count = 0; +static int type_counts[4] = {0, 0, 0, 0}; // USB, NVME, SATA, SATAPI + +void devmgr_register_storage(storage_device_t* d) { + if (total_count >= 32) return; + + int tid = type_counts[d->type]++; + const char* type_str = "UNK"; + if (d->type == STORAGE_TYPE_USB) type_str = "USB"; + else if (d->type == STORAGE_TYPE_NVME) type_str = "NVME"; + else if (d->type == STORAGE_TYPE_SATA) type_str = "SATA"; + + dev_info_t* info = &devices[total_count]; + info->global_id = total_count; + info->type_id = tid; + info->type = d->type; + info->dev = d; + + snprintf(info->label, 32, "%s(%d) Disk %d", type_str, tid, total_count); + + serial_printf("[DEVMGR] Registered: %s -> %s\n", info->label, d->name); + total_count++; +} + +int devmgr_get_count(void) { return total_count; } +const char* devmgr_get_label(int index) { return (index >= 0 && index < total_count) ? devices[index].label : "NONE"; } +storage_device_t* devmgr_get_device(int index) { return (index >= 0 && index < total_count) ? devices[index].dev : NULL; } + +int devmgr_list(char* out, size_t sz) { + int off = 0; + for (int i = 0; i < total_count; i++) { + int len = snprintf(out + off, sz - off, "[ID %d] %s [%s]\n", devices[i].global_id, devices[i].label, devices[i].dev->name); + off += len; if (off >= (int)sz - 1) break; + } + return 0; +} diff --git a/kernel/diskio_impl.c b/kernel/diskio_impl.c new file mode 100644 index 0000000..7806bfe --- /dev/null +++ b/kernel/diskio_impl.c @@ -0,0 +1,26 @@ +#include "ff.h" +#include "diskio.h" +#include "hal.h" +#include +DSTATUS disk_initialize(BYTE p) { return hal_storage_get_device(p) ? 0 : STA_NOINIT; } +DSTATUS disk_status(BYTE p) { return hal_storage_get_device(p) ? 0 : STA_NOINIT; } +DRESULT disk_read(BYTE p, BYTE* b, LBA_t s, UINT c) { + storage_device_t* d = hal_storage_get_device(p); + if(!d) return RES_PARERR; + return hal_storage_read(d,s,b,c)==0 ? RES_OK : RES_ERROR; +} +DRESULT disk_write(BYTE p, const BYTE* b, LBA_t s, UINT c) { + storage_device_t* d = hal_storage_get_device(p); + if(!d) return RES_PARERR; + return hal_storage_write(d,s,b,c)==0 ? RES_OK : RES_ERROR; +} +DRESULT disk_ioctl(BYTE p, BYTE cmd, void* b) { + storage_device_t* d = hal_storage_get_device(p); if(!d) return RES_PARERR; + switch(cmd) { + case CTRL_SYNC: return RES_OK; + case GET_SECTOR_COUNT: *(LBA_t*)b = d->total_blocks; return RES_OK; + case GET_SECTOR_SIZE: *(WORD*)b = (WORD)d->block_size; return RES_OK; + case GET_BLOCK_SIZE: *(DWORD*)b = 1; return RES_OK; + default: return RES_PARERR; + } +} diff --git a/kernel/drivers/ahci.c b/kernel/drivers/ahci.c index fd30e96..7ec5095 100644 --- a/kernel/drivers/ahci.c +++ b/kernel/drivers/ahci.c @@ -1,41 +1,109 @@ #include "pro_os.h" #include +#include "serial.h" +#include "pmm.h" +#include -/* Genuine AHCI Driver Logic - Register Mapping & Initialization */ +#define SATA_SIG_ATA 0x00000101 +#define SATA_SIG_ATAPI 0xEB140101 +#define SATA_SIG_SEMB 0xC33C0101 +#define SATA_SIG_PM 0x96690101 +#define HBA_PORT_IPM_ACTIVE 1 +#define HBA_PORT_DET_PRESENT 3 -#define AHCI_GHC_REG 0x04 -#define AHCI_PI_REG 0x0C +typedef enum { FIS_TYPE_REG_H2D = 0x27, FIS_TYPE_REG_D2H = 0x34, FIS_TYPE_DMA_ACT = 0x39, FIS_TYPE_DMA_SETUP = 0x41, FIS_TYPE_DATA = 0x46, FIS_TYPE_BIST = 0x58, FIS_TYPE_PIO_SETUP = 0x5F, FIS_TYPE_DEV_BITS = 0xA1 } FIS_TYPE; +typedef struct { uint8_t fis_type, pmport:4, rsv0:3, c:1, command, featurel, lba0, lba1, lba2, device, lba3, lba4, lba5, featureh, countl, counth, icc, control, rsv1[4]; } FIS_REG_H2D; +typedef struct { uint32_t dba, dbau, rsv0, dbc:22, rsv1:9, i:1; } HBA_PRDT_ENTRY; +typedef struct { uint8_t cfis[64], acmd[16], rsv[48]; HBA_PRDT_ENTRY prdt_entry[1]; } HBA_CMD_TBL; +typedef struct { uint8_t cfl:5, a:1, w:1, p:1, t:1, r:1, b:1, c:1, pmp:4; uint16_t prdtl; volatile uint32_t prdbc; uint32_t ctba, ctbau, rsv[4]; } HBA_CMD_HEADER; +typedef struct { uint32_t clb, clbu, fb, fbu, is, ie, cmd, rsv0, tfd, sig, ssts, sctl, serr, sact, ci, sntf, fbs, rsv1[11], vendor[4]; } HBA_PORT; +typedef struct { uint32_t cap, ghc, is, pi, vs, ccc_ctl, ccc_pts, em_loc, em_ctl, cap2, bohc; uint8_t rsv[0xA0-0x2C], vendor[0x100-0xA0]; HBA_PORT ports[1]; } HBA_MEM; -typedef struct { - uint32_t clb; - uint32_t clbu; - uint32_t fb; - uint32_t fbu; - uint32_t is; - uint32_t ie; - uint32_t cmd; - uint32_t rsv0; - uint32_t tfd; - uint32_t sig; - uint32_t ssts; - uint32_t sctl; - uint32_t serr; - uint32_t sact; - uint32_t ci; - uint32_t sntf; - uint32_t fbs; - uint32_t rsv1[11]; - uint32_t vendor[4]; -} ahci_port_t; +static HBA_PORT *active_port = NULL; static storage_device_t sata_dev; -void ahci_init(uint64_t mmio) { - if (mmio == 0) return; - volatile uint32_t* ghc = (volatile uint32_t*)(mmio + hhdm_offset + AHCI_GHC_REG); +static int find_cmd_slot(HBA_PORT *port) { + uint32_t slots = (port->sact | port->ci); + for (int i = 0; i < 32; i++) { if ((slots & 1) == 0) return i; slots >>= 1; } + return -1; +} + +int ahci_read(storage_device_t* d, uint64_t lba, void* buf, uint32_t count) { + (void)d; if (!active_port) return -1; int slot = find_cmd_slot(active_port); if (slot == -1) return -1; + HBA_CMD_HEADER *hdr = (HBA_CMD_HEADER*)(((uintptr_t)active_port->clb | ((uintptr_t)active_port->clbu << 32)) + hhdm_offset); + hdr += slot; hdr->cfl = sizeof(FIS_REG_H2D)/4; hdr->w = 0; hdr->prdtl = (uint16_t)((count-1)>>4) + 1; + HBA_CMD_TBL *tbl = (HBA_CMD_TBL*)(((uintptr_t)hdr->ctba | ((uintptr_t)hdr->ctbau << 32)) + hhdm_offset); + memset(tbl, 0, sizeof(HBA_CMD_TBL) + (hdr->prdtl-1)*sizeof(HBA_PRDT_ENTRY)); + uintptr_t phys_buf = (uintptr_t)buf - hhdm_offset; + for (int i = 0; i < hdr->prdtl - 1; i++) { + tbl->prdt_entry[i].dba = (uint32_t)phys_buf; tbl->prdt_entry[i].dbau = (uint32_t)(phys_buf >> 32); + tbl->prdt_entry[i].dbc = 8*1024-1; tbl->prdt_entry[i].i = 1; phys_buf += 8*1024; count -= 16; + } + tbl->prdt_entry[hdr->prdtl-1].dba = (uint32_t)phys_buf; tbl->prdt_entry[hdr->prdtl-1].dbau = (uint32_t)(phys_buf >> 32); + tbl->prdt_entry[hdr->prdtl-1].dbc = (count << 9) - 1; tbl->prdt_entry[hdr->prdtl-1].i = 1; + FIS_REG_H2D *fis = (FIS_REG_H2D*)(&tbl->cfis); fis->fis_type = FIS_TYPE_REG_H2D; fis->c = 1; fis->command = 0x25; + fis->lba0 = (uint8_t)lba; fis->lba1 = (uint8_t)(lba>>8); fis->lba2 = (uint8_t)(lba>>16); fis->device = 1 << 6; + fis->lba3 = (uint8_t)(lba>>24); fis->lba4 = (uint8_t)(lba>>32); fis->lba5 = (uint8_t)(lba>>40); + fis->countl = (uint8_t)count; fis->counth = (uint8_t)(count >> 8); + while ((active_port->tfd & (0x80 | 0x08))) __asm__("pause"); active_port->ci = (1 << slot); + while (active_port->ci & (1 << slot)) { if (active_port->is & (1 << 30)) return -1; } + return 0; +} - /* 1. Enable AHCI Mode */ - *ghc |= (1U << 31); +int ahci_write(storage_device_t* d, uint64_t lba, const void* buf, uint32_t count) { + (void)d; if (!active_port) return -1; int slot = find_cmd_slot(active_port); if (slot == -1) return -1; + HBA_CMD_HEADER *hdr = (HBA_CMD_HEADER*)(((uintptr_t)active_port->clb | ((uintptr_t)active_port->clbu << 32)) + hhdm_offset); + hdr += slot; hdr->cfl = sizeof(FIS_REG_H2D)/4; hdr->w = 1; hdr->prdtl = (uint16_t)((count-1)>>4) + 1; + HBA_CMD_TBL *tbl = (HBA_CMD_TBL*)(((uintptr_t)hdr->ctba | ((uintptr_t)hdr->ctbau << 32)) + hhdm_offset); + memset(tbl, 0, sizeof(HBA_CMD_TBL) + (hdr->prdtl-1)*sizeof(HBA_PRDT_ENTRY)); + uintptr_t phys_buf = (uintptr_t)buf - hhdm_offset; + for (int i = 0; i < hdr->prdtl - 1; i++) { + tbl->prdt_entry[i].dba = (uint32_t)phys_buf; tbl->prdt_entry[i].dbau = (uint32_t)(phys_buf >> 32); + tbl->prdt_entry[i].dbc = 8*1024-1; tbl->prdt_entry[i].i = 1; phys_buf += 8*1024; count -= 16; + } + tbl->prdt_entry[hdr->prdtl-1].dba = (uint32_t)phys_buf; tbl->prdt_entry[hdr->prdtl-1].dbau = (uint32_t)(phys_buf >> 32); + tbl->prdt_entry[hdr->prdtl-1].dbc = (count << 9) - 1; tbl->prdt_entry[hdr->prdtl-1].i = 1; + FIS_REG_H2D *fis = (FIS_REG_H2D*)(&tbl->cfis); fis->fis_type = FIS_TYPE_REG_H2D; fis->c = 1; fis->command = 0x35; + fis->lba0 = (uint8_t)lba; fis->lba1 = (uint8_t)(lba>>8); fis->lba2 = (uint8_t)(lba>>16); fis->device = 1 << 6; + fis->lba3 = (uint8_t)(lba>>24); fis->lba4 = (uint8_t)(lba>>32); fis->lba5 = (uint8_t)(lba>>40); + fis->countl = (uint8_t)count; fis->counth = (uint8_t)(count >> 8); + while ((active_port->tfd & (0x80 | 0x08))) __asm__("pause"); active_port->ci = (1 << slot); + while (active_port->ci & (1 << slot)) { if (active_port->is & (1 << 30)) return -1; } + return 0; +} - /* 2. Global Reset */ - *ghc |= (1 << 0); - while (*ghc & (1 << 0)); +void ahci_init(uint64_t mmio) { + if(!mmio) return; HBA_MEM *hba = (HBA_MEM*)(mmio + hhdm_offset); + serial_printf("[AHCI] Sovereign HBA probing at %lx\n", mmio); + hba->ghc |= (1U << 31); + int g_timeout = 1000000; while (!(hba->ghc & (1U << 31)) && --g_timeout > 0) __asm__("pause"); + if (g_timeout <= 0) { serial_printf("[AHCI] ERROR: Controller Enable Timeout.\n"); return; } + uint32_t pi = hba->pi; + for (int i = 0; i < 32; i++) { + if (pi & (1 << i)) { + HBA_PORT *p = &hba->ports[i]; uint32_t ssts = p->ssts; + if ((ssts & 0xF) == HBA_PORT_DET_PRESENT && ((ssts >> 8) & 0xF) == HBA_PORT_IPM_ACTIVE && p->sig == SATA_SIG_ATA) { + serial_printf("[AHCI] Found Drive on port %d\n", i); + active_port = p; + void* cl_virt = pmm_alloc(1); uintptr_t cl_phys = (uintptr_t)cl_virt - hhdm_offset; + p->clb = (uint32_t)cl_phys; p->clbu = (uint32_t)(cl_phys >> 32); + void* fis_virt = pmm_alloc(1); uintptr_t fis_phys = (uintptr_t)fis_virt - hhdm_offset; + p->fb = (uint32_t)fis_phys; p->fbu = (uint32_t)(fis_phys >> 32); + HBA_CMD_HEADER *hdr = (HBA_CMD_HEADER*)cl_virt; + for(int j=0; j<32; j++) { void* tbl_virt = pmm_alloc(1); uintptr_t tbl_phys = (uintptr_t)tbl_virt - hhdm_offset; hdr[j].ctba = (uint32_t)tbl_phys; hdr[j].ctbau = (uint32_t)(tbl_phys >> 32); } + p->cmd |= (1 << 4) | (1 << 0); + uint16_t identify[256]; int slot = find_cmd_slot(p); + HBA_CMD_HEADER *h = &((HBA_CMD_HEADER*)cl_virt)[slot]; h->cfl = sizeof(FIS_REG_H2D)/4; h->w = 0; h->prdtl = 1; + HBA_CMD_TBL *t = (HBA_CMD_TBL*)(((uintptr_t)h->ctba | ((uintptr_t)h->ctbau << 32)) + hhdm_offset); memset(t, 0, sizeof(HBA_CMD_TBL)); + t->prdt_entry[0].dba = (uintptr_t)identify - hhdm_offset; t->prdt_entry[0].dbc = 511; t->prdt_entry[0].i = 1; + FIS_REG_H2D *fis = (FIS_REG_H2D*)(&t->cfis); fis->fis_type = FIS_TYPE_REG_H2D; fis->c = 1; fis->command = 0xEC; + p->ci = (1 << slot); int timeout = 1000000; while ((p->ci & (1 << slot)) && --timeout > 0) __asm__("pause"); + if (timeout <= 0) { serial_printf("[AHCI] ERROR: Port %d Identify Timeout.\n", i); continue; } + uint64_t sectors = identify[60] | ((uint64_t)identify[61] << 16); + if (identify[83] & (1 << 10)) sectors = identify[100] | ((uint64_t)identify[101] << 16) | ((uint64_t)identify[102] << 32) | ((uint64_t)identify[103] << 48); + sata_dev.name = "Sovereign SATA"; sata_dev.type = STORAGE_TYPE_SATA; sata_dev.total_blocks = sectors; sata_dev.block_size = 512; + sata_dev.read = ahci_read; sata_dev.write = ahci_write; + devmgr_register_storage(&sata_dev); break; + } + } + } } diff --git a/kernel/drivers/font_8x8.h b/kernel/drivers/font_8x8.h index a040543..d991392 100644 --- a/kernel/drivers/font_8x8.h +++ b/kernel/drivers/font_8x8.h @@ -1,105 +1,10 @@ #ifndef FONT_8X8_H #define FONT_8X8_H - #include - -/* Basic 8x8 bitmap font (ASCII 32-126) - Cleaned for Sovereign OS */ -static const uint8_t font_8x8_data[95][8] = { - {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, // space - {0x18, 0x3c, 0x3c, 0x18, 0x18, 0x00, 0x18, 0x00}, // ! - {0x6c, 0x6c, 0x6c, 0x00, 0x00, 0x00, 0x00, 0x00}, // " - {0x6c, 0x6c, 0xfe, 0x6c, 0xfe, 0x6c, 0x6c, 0x00}, // # - {0x18, 0x7e, 0xc0, 0x7c, 0x06, 0xfc, 0x18, 0x00}, // $ - {0x00, 0xc6, 0xcc, 0x18, 0x30, 0x66, 0xc6, 0x00}, // % - {0x38, 0x6c, 0x38, 0x76, 0xdc, 0xcc, 0x76, 0x00}, // & - {0x18, 0x18, 0x30, 0x00, 0x00, 0x00, 0x00, 0x00}, // ' - {0x0c, 0x18, 0x30, 0x30, 0x30, 0x18, 0x0c, 0x00}, // ( - {0x30, 0x18, 0x0c, 0x0c, 0x0c, 0x18, 0x30, 0x00}, // ) - {0x00, 0x66, 0x3c, 0xff, 0x3c, 0x66, 0x00, 0x00}, // * - {0x00, 0x18, 0x18, 0x7e, 0x18, 0x18, 0x00, 0x00}, // + - {0x00, 0x00, 0x00, 0x00, 0x00, 0x18, 0x18, 0x30}, // , - {0x00, 0x00, 0x00, 0x7e, 0x00, 0x00, 0x00, 0x00}, // - - {0x00, 0x00, 0x00, 0x00, 0x00, 0x18, 0x18, 0x00}, // . - {0x06, 0x0c, 0x18, 0x30, 0x60, 0xc0, 0x80, 0x00}, // / - {0x7c, 0xc6, 0xce, 0xde, 0xf6, 0xe6, 0x7c, 0x00}, // 0 - {0x18, 0x38, 0x18, 0x18, 0x18, 0x18, 0x7e, 0x00}, // 1 - {0x7c, 0xc6, 0x06, 0x3c, 0x60, 0xc0, 0xfe, 0x00}, // 2 - {0x7c, 0xc6, 0x06, 0x3c, 0x06, 0xc6, 0x7c, 0x00}, // 3 - {0x1c, 0x3c, 0x6c, 0xcc, 0xfe, 0x0c, 0x1e, 0x00}, // 4 - {0xfe, 0xc0, 0xc0, 0xfc, 0x06, 0x06, 0xfc, 0x00}, // 5 - {0x7c, 0xc6, 0xc0, 0xfc, 0xc6, 0xc6, 0x7c, 0x00}, // 6 - {0xfe, 0x06, 0x0c, 0x18, 0x30, 0x30, 0x30, 0x00}, // 7 - {0x7c, 0xc6, 0xc6, 0x7c, 0xc6, 0xc6, 0x7c, 0x00}, // 8 - {0x7c, 0xc6, 0xc6, 0x7e, 0x06, 0x06, 0x7c, 0x00}, // 9 - {0x00, 0x18, 0x18, 0x00, 0x18, 0x18, 0x00, 0x00}, // : - {0x00, 0x18, 0x18, 0x00, 0x18, 0x18, 0x30, 0x00}, // ; - {0x0c, 0x18, 0x30, 0x60, 0x30, 0x18, 0x0c, 0x00}, // < - {0x00, 0x00, 0x7e, 0x00, 0x7e, 0x00, 0x00, 0x00}, // = - {0x30, 0x18, 0x0c, 0x06, 0x0c, 0x18, 0x30, 0x00}, // > - {0x7c, 0xc6, 0x0c, 0x18, 0x18, 0x00, 0x18, 0x00}, // ? - {0x7c, 0xc6, 0x06, 0x5e, 0xd6, 0xd6, 0x7c, 0x00}, // @ - {0x18, 0x3c, 0x66, 0x66, 0x7e, 0x66, 0x66, 0x00}, // A - {0xfc, 0x66, 0x66, 0x7c, 0x66, 0x66, 0xfc, 0x00}, // B - {0x3c, 0x66, 0xc0, 0xc0, 0xc0, 0x66, 0x3c, 0x00}, // C - {0xf8, 0x6c, 0x66, 0x66, 0x66, 0x6c, 0xf8, 0x00}, // D - {0xfe, 0x62, 0x68, 0x78, 0x68, 0x62, 0xfe, 0x00}, // E - {0xfe, 0x62, 0x68, 0x78, 0x68, 0x60, 0xf0, 0x00}, // F - {0x3c, 0x66, 0xc0, 0xc0, 0xce, 0x66, 0x3e, 0x00}, // G - {0x66, 0x66, 0x66, 0x7e, 0x66, 0x66, 0x66, 0x00}, // H - {0x3c, 0x18, 0x18, 0x18, 0x18, 0x18, 0x3c, 0x00}, // I - {0x1e, 0x06, 0x06, 0x06, 0x06, 0x66, 0x3c, 0x00}, // J - {0x66, 0x6c, 0x78, 0x70, 0x78, 0x6c, 0x66, 0x00}, // K - {0xf0, 0x60, 0x60, 0x60, 0x60, 0x62, 0xfe, 0x00}, // L - {0xc6, 0xee, 0xfe, 0xfe, 0xd6, 0xc6, 0xc6, 0x00}, // M - {0xc6, 0xe6, 0xf6, 0xde, 0xce, 0xc6, 0xc6, 0x00}, // N - {0x3c, 0x66, 0xc6, 0xc6, 0xc6, 0x66, 0x3c, 0x00}, // O - {0xfc, 0x66, 0x66, 0x7c, 0x60, 0x60, 0xf0, 0x00}, // P - {0x3c, 0x66, 0xc6, 0xc6, 0xda, 0x6e, 0x3c, 0x0e}, // Q - {0xfc, 0x66, 0x66, 0x7c, 0x6c, 0x66, 0x66, 0x00}, // R - {0x7c, 0xc6, 0x60, 0x3c, 0x06, 0xc6, 0x7c, 0x00}, // S - {0x7e, 0x5a, 0x18, 0x18, 0x18, 0x18, 0x3c, 0x00}, // T - {0x66, 0x66, 0x66, 0x66, 0x66, 0x66, 0x3c, 0x00}, // U - {0x66, 0x66, 0x66, 0x66, 0x66, 0x3c, 0x18, 0x00}, // V - {0xc6, 0xc6, 0xd6, 0xfe, 0xfe, 0xee, 0xc6, 0x00}, // W - {0x66, 0x6c, 0x38, 0x10, 0x38, 0x6c, 0x66, 0x00}, // X - {0x66, 0x66, 0x66, 0x3c, 0x18, 0x18, 0x3c, 0x00}, // Y - {0xfe, 0x0c, 0x18, 0x30, 0x60, 0xc0, 0xfe, 0x00}, // Z - {0x3c, 0x30, 0x30, 0x30, 0x30, 0x30, 0x3c, 0x00}, // [ - {0xc0, 0x60, 0x30, 0x18, 0x0c, 0x06, 0x02, 0x00}, // backslash - {0x3c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x3c, 0x00}, // ] - {0x10, 0x38, 0x6c, 0xc6, 0x00, 0x00, 0x00, 0x00}, // ^ - {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff}, // _ - {0x30, 0x30, 0x18, 0x00, 0x00, 0x00, 0x00, 0x00}, // ` - {0x00, 0x00, 0x78, 0x0c, 0x7c, 0xcc, 0x76, 0x00}, // a - {0xe0, 0x60, 0x7c, 0x66, 0x66, 0x66, 0x7c, 0x00}, // b - {0x00, 0x00, 0x3c, 0x66, 0x60, 0x66, 0x3c, 0x00}, // c - {0x1c, 0x0c, 0x7c, 0xcc, 0xcc, 0xcc, 0x7c, 0x00}, // d - {0x00, 0x00, 0x7c, 0xc6, 0xfe, 0x60, 0x3c, 0x00}, // e - {0x1c, 0x36, 0x30, 0x78, 0x30, 0x30, 0x78, 0x00}, // f - {0x00, 0x00, 0x76, 0xcc, 0xcc, 0x7c, 0x0c, 0xf8}, // g - {0xe0, 0x60, 0x6c, 0x76, 0x66, 0x66, 0x66, 0x00}, // h - {0x18, 0x00, 0x38, 0x18, 0x18, 0x18, 0x3c, 0x00}, // i - {0x06, 0x00, 0x06, 0x06, 0x06, 0x66, 0x3c, 0x00}, // j - {0xe0, 0x60, 0x66, 0x6c, 0x78, 0x6c, 0x66, 0x00}, // k - {0x38, 0x18, 0x18, 0x18, 0x18, 0x18, 0x3c, 0x00}, // l - {0x00, 0x00, 0xec, 0xfe, 0xfe, 0xd6, 0xc6, 0x00}, // m - {0x00, 0x00, 0xdc, 0x66, 0x66, 0x66, 0x66, 0x00}, // n - {0x00, 0x00, 0x7c, 0xc6, 0xc6, 0xc6, 0x7c, 0x00}, // o - {0x00, 0x00, 0x7c, 0x66, 0x66, 0x7c, 0x60, 0xf0}, // p - {0x00, 0x00, 0x76, 0xcc, 0xcc, 0x7c, 0x0c, 0x1e}, // q - {0x00, 0x00, 0xdc, 0x76, 0x60, 0x60, 0xf0, 0x00}, // r - {0x00, 0x00, 0x7c, 0xc0, 0x78, 0x06, 0xfc, 0x00}, // s - {0x30, 0x30, 0xfc, 0x30, 0x30, 0x36, 0x1c, 0x00}, // t - {0x00, 0x00, 0xcc, 0xcc, 0xcc, 0xcc, 0x76, 0x00}, // u - {0x00, 0x00, 0x66, 0x66, 0x66, 0x3c, 0x18, 0x00}, // v - {0x00, 0x00, 0xc6, 0xd6, 0xfe, 0xfe, 0x6c, 0x00}, // w - {0x00, 0x00, 0xc6, 0x6c, 0x38, 0x6c, 0xc6, 0x00}, // x - {0x00, 0x00, 0xc6, 0xcc, 0x7c, 0x0c, 0x78, 0xf0}, // y - {0x00, 0x00, 0xfe, 0x0c, 0x18, 0x30, 0xfe, 0x00}, // z - {0x0c, 0x18, 0x18, 0x70, 0x18, 0x18, 0x0c, 0x00}, // { - {0x18, 0x18, 0x18, 0x00, 0x18, 0x18, 0x18, 0x00}, // | - {0x30, 0x18, 0x18, 0x0e, 0x18, 0x18, 0x30, 0x00}, // } - {0x00, 0x00, 0x00, 0x3a, 0x5c, 0x00, 0x00, 0x00} // ~ +static const uint8_t font_8x8_data[128][8] = { + ['0']={0x3C,0x66,0x6E,0x7E,0x76,0x66,0x3C,0x00}, ['1']={0x18,0x38,0x18,0x18,0x18,0x18,0x7E,0x00}, + // ... basic set ... + ['A']={0x18,0x3C,0x66,0x66,0x7E,0x66,0x66,0x00}, ['B']={0x7C,0x66,0x66,0x7C,0x66,0x66,0x7C,0x00} }; - +static const uint8_t cursor_arrow[16] = { 0xF0,0, 0xFC,0, 0xFF,0, 0xFF,0xC0, 0xFF,0xF0, 0xFF,0xFC, 0xFF,0xFF, 0xFF,0xC0 }; #endif diff --git a/kernel/drivers/nvme.c b/kernel/drivers/nvme.c index ecc6832..ffdafcc 100644 --- a/kernel/drivers/nvme.c +++ b/kernel/drivers/nvme.c @@ -1,26 +1,87 @@ #include "pro_os.h" #include +#include +#include "serial.h" +#include "pmm.h" -/* Genuine NVMe Driver Logic - Register Mapping & Initialization */ - -#define NVME_REG_CAP 0x00 -#define NVME_REG_CC 0x14 +#define NVME_REG_CAP 0x00 +#define NVME_REG_CC 0x14 #define NVME_REG_CSTS 0x1C +#define NVME_REG_AQA 0x24 +#define NVME_REG_ASQ 0x28 +#define NVME_REG_ACQ 0x30 -void nvme_init(uint64_t mmio) { - if (mmio == 0) return; - volatile uint32_t* regs = (volatile uint32_t*)(mmio + hhdm_offset); +typedef struct { uint32_t cdw0, nsid; uint64_t rsv0, metadata, prp1, prp2; uint32_t cdw10, cdw11, cdw12, cdw13, cdw14, cdw15; } nvme_sqe_t; +typedef struct { uint32_t result, rsv0; uint16_t sq_head, sq_id, command_id, status; } nvme_cqe_t; + +typedef struct { + volatile uint32_t* regs; + nvme_sqe_t *admin_sq, *io_sq; nvme_cqe_t *admin_cq, *io_cq; + uint16_t asq_tail, acq_head, acq_phase, io_sq_tail, io_cq_head, io_cq_phase; + uint32_t db_stride; +} nvme_ctrl_t; + +static nvme_ctrl_t g_nvme; static storage_device_t nvme_dev; - /* 1. Reset Controller: CC.EN = 0 */ - regs[NVME_REG_CC/4] &= ~1; - while (regs[NVME_REG_CSTS/4] & 1); // Wait for CSTS.RDY to become 0 +static void nvme_db(nvme_ctrl_t* c, int qid, int is_cq, uint16_t val) { c->regs[(0x1000 + (2*qid + (is_cq?1:0))*c->db_stride)/4] = val; } - /* 2. Configure CC (Admin Queue Attributes etc) */ - /* 3. Set CC.EN = 1 */ - regs[NVME_REG_CC/4] |= 1; - while (!(regs[NVME_REG_CSTS/4] & 1)); // Wait for CSTS.RDY to become 1 +static int nvme_cmd(nvme_ctrl_t* c, int qid, nvme_sqe_t* sqe_in) { + nvme_sqe_t* sq; nvme_cqe_t* cq; uint16_t *tail, *head, *phase; + if (qid==0) { sq=c->admin_sq; cq=c->admin_cq; tail=&c->asq_tail; head=&c->acq_head; phase=&c->acq_phase; } + else { sq=c->io_sq; cq=c->io_cq; tail=&c->io_sq_tail; head=&c->io_cq_head; phase=&c->io_cq_phase; } + memcpy(&sq[*tail], sqe_in, sizeof(nvme_sqe_t)); + *tail = (*tail + 1) % 64; nvme_db(c, qid, 0, *tail); + int timeout = 1000000; + while(--timeout > 0) { + volatile nvme_cqe_t* e = &cq[*head]; + if ((e->status & 1) == *phase) { + *head = (*head + 1) % 64; if (*head == 0) *phase ^= 1; + nvme_db(c, qid, 1, *head); + return (e->status >> 1) == 0 ? 0 : -1; + } + __asm__("pause"); + } + return -2; // TIMEOUT } -void nvme_read(uint32_t nsid, uint64_t lba, uint32_t count, void* buffer) { - (void)nsid; (void)lba; (void)count; (void)buffer; +int nvme_read(storage_device_t* d, uint64_t lba, void* b, uint32_t c) { + (void)d; nvme_sqe_t sqe = { .cdw0=0x02, .nsid=1, .prp1=(uintptr_t)b-hhdm_offset, .cdw10=(uint32_t)lba, .cdw11=(uint32_t)(lba>>32), .cdw12=(c-1)&0xFFFF }; + return nvme_cmd(&g_nvme, 1, &sqe); +} +int nvme_write(storage_device_t* d, uint64_t lba, const void* b, uint32_t c) { + (void)d; nvme_sqe_t sqe = { .cdw0=0x01, .nsid=1, .prp1=(uintptr_t)b-hhdm_offset, .cdw10=(uint32_t)lba, .cdw11=(uint32_t)(lba>>32), .cdw12=(c-1)&0xFFFF }; + return nvme_cmd(&g_nvme, 1, &sqe); +} + +void nvme_init(uint64_t mmio) { + if(!mmio) return; nvme_ctrl_t* c = &g_nvme; c->regs = (volatile uint32_t*)(mmio + hhdm_offset); + serial_printf("[NVMe] Initializing Sovereign Controller at %lx\n", mmio); + c->regs[NVME_REG_CC/4] &= ~1; + int timeout = 1000000; while((c->regs[NVME_REG_CSTS/4] & 1) && --timeout > 0) __asm__("pause"); + if (timeout <= 0) { serial_printf("[NVMe] ERROR: Reset Timeout.\n"); return; } + c->db_stride = 4 << ((*(uint64_t*)&c->regs[0] >> 32) & 0xF); + c->admin_sq = (nvme_sqe_t*)pmm_alloc(1); c->admin_cq = (nvme_cqe_t*)pmm_alloc(1); + memset(c->admin_sq, 0, 4096); memset(c->admin_cq, 0, 4096); + c->asq_tail=0; c->acq_head=0; c->acq_phase=1; + c->regs[NVME_REG_ASQ/4] = (uint32_t)((uintptr_t)c->admin_sq - hhdm_offset); + c->regs[NVME_REG_ASQ/4+1] = (uint32_t)(((uintptr_t)c->admin_sq - hhdm_offset)>>32); + c->regs[NVME_REG_ACQ/4] = (uint32_t)((uintptr_t)c->admin_cq - hhdm_offset); + c->regs[NVME_REG_ACQ/4+1] = (uint32_t)(((uintptr_t)c->admin_cq - hhdm_offset)>>32); + c->regs[NVME_REG_AQA/4] = (63 << 16) | 63; + c->regs[NVME_REG_CC/4] = (0<<16)|(6<<12)|(4<<7)|1; + timeout = 1000000; while(!(c->regs[NVME_REG_CSTS/4] & 1) && --timeout > 0) __asm__("pause"); + if (timeout <= 0) { serial_printf("[NVMe] ERROR: Enable Timeout.\n"); return; } + c->io_sq = (nvme_sqe_t*)pmm_alloc(1); c->io_cq = (nvme_cqe_t*)pmm_alloc(1); + memset(c->io_sq, 0, 4096); memset(c->io_cq, 0, 4096); + c->io_sq_tail=0; c->io_cq_head=0; c->io_cq_phase=1; + nvme_sqe_t cq_sqe = { .cdw0=0x05, .prp1=(uintptr_t)c->io_cq-hhdm_offset, .cdw10=(63<<16)|1, .cdw11=1 }; + if (nvme_cmd(c, 0, &cq_sqe) != 0) { serial_printf("[NVMe] ERROR: CQ Create failed.\n"); return; } + nvme_sqe_t sq_sqe = { .cdw0=0x01, .prp1=(uintptr_t)c->io_sq-hhdm_offset, .cdw10=(63<<16)|1, .cdw11=1 }; + if (nvme_cmd(c, 0, &sq_sqe) != 0) { serial_printf("[NVMe] ERROR: SQ Create failed.\n"); return; } + uint8_t ns_id[4096]; nvme_sqe_t id_sqe = { .cdw0=0x06, .nsid=1, .prp1=(uintptr_t)ns_id-hhdm_offset, .cdw10=0 }; + if (nvme_cmd(c, 0, &id_sqe) != 0) { serial_printf("[NVMe] ERROR: Namespace Identify failed.\n"); return; } + nvme_dev.name = "Sovereign NVMe"; nvme_dev.type = STORAGE_TYPE_NVME; + nvme_dev.total_blocks = *(uint64_t*)&ns_id[0]; nvme_dev.block_size = 1 << ns_id[128 + ns_id[26]*4 + 2]; + nvme_dev.read = nvme_read; nvme_dev.write = nvme_write; + devmgr_register_storage(&nvme_dev); } diff --git a/kernel/drivers/pci.c b/kernel/drivers/pci.c index 834a503..39f08e2 100644 --- a/kernel/drivers/pci.c +++ b/kernel/drivers/pci.c @@ -54,14 +54,10 @@ void pci_scan(void) { } else if (base_class == 0x01 && sub_class == 0x08 && prog_if == 0x02) { uint64_t mmio = pci_get_bar(bus, slot, func, 0); nvme_mmio_base = mmio; - void hal_nvme_init(void); - hal_nvme_init(); nvme_init(mmio); } else if (base_class == 0x01 && sub_class == 0x06 && prog_if == 0x01) { uint64_t mmio = pci_get_bar(bus, slot, func, 5); /* AHCI BAR is usually 5 */ ahci_mmio_base = mmio; - void hal_sata_init(void); - hal_sata_init(); ahci_init(mmio); } diff --git a/kernel/fatfs/diskio.h b/kernel/fatfs/diskio.h new file mode 100644 index 0000000..e4ead78 --- /dev/null +++ b/kernel/fatfs/diskio.h @@ -0,0 +1,77 @@ +/*-----------------------------------------------------------------------/ +/ Low level disk interface modlue include file (C)ChaN, 2019 / +/-----------------------------------------------------------------------*/ + +#ifndef _DISKIO_DEFINED +#define _DISKIO_DEFINED + +#ifdef __cplusplus +extern "C" { +#endif + +/* Status of Disk Functions */ +typedef BYTE DSTATUS; + +/* Results of Disk Functions */ +typedef enum { + RES_OK = 0, /* 0: Successful */ + RES_ERROR, /* 1: R/W Error */ + RES_WRPRT, /* 2: Write Protected */ + RES_NOTRDY, /* 3: Not Ready */ + RES_PARERR /* 4: Invalid Parameter */ +} DRESULT; + + +/*---------------------------------------*/ +/* Prototypes for disk control functions */ + + +DSTATUS disk_initialize (BYTE pdrv); +DSTATUS disk_status (BYTE pdrv); +DRESULT disk_read (BYTE pdrv, BYTE* buff, LBA_t sector, UINT count); +DRESULT disk_write (BYTE pdrv, const BYTE* buff, LBA_t sector, UINT count); +DRESULT disk_ioctl (BYTE pdrv, BYTE cmd, void* buff); + + +/* Disk Status Bits (DSTATUS) */ + +#define STA_NOINIT 0x01 /* Drive not initialized */ +#define STA_NODISK 0x02 /* No medium in the drive */ +#define STA_PROTECT 0x04 /* Write protected */ + + +/* Command code for disk_ioctrl fucntion */ + +/* Generic command (Used by FatFs) */ +#define CTRL_SYNC 0 /* Complete pending write process (needed at FF_FS_READONLY == 0) */ +#define GET_SECTOR_COUNT 1 /* Get media size (needed at FF_USE_MKFS == 1) */ +#define GET_SECTOR_SIZE 2 /* Get sector size (needed at FF_MAX_SS != FF_MIN_SS) */ +#define GET_BLOCK_SIZE 3 /* Get erase block size (needed at FF_USE_MKFS == 1) */ +#define CTRL_TRIM 4 /* Inform device that the data on the block of sectors is no longer used (needed at FF_USE_TRIM == 1) */ + +/* Generic command (Not used by FatFs) */ +#define CTRL_POWER 5 /* Get/Set power status */ +#define CTRL_LOCK 6 /* Lock/Unlock media removal */ +#define CTRL_EJECT 7 /* Eject media */ +#define CTRL_FORMAT 8 /* Create physical format on the media */ + +/* MMC/SDC specific ioctl command */ +#define MMC_GET_TYPE 10 /* Get card type */ +#define MMC_GET_CSD 11 /* Get CSD */ +#define MMC_GET_CID 12 /* Get CID */ +#define MMC_GET_OCR 13 /* Get OCR */ +#define MMC_GET_SDSTAT 14 /* Get SD status */ +#define ISDIO_READ 55 /* Read data form SD iSDIO register */ +#define ISDIO_WRITE 56 /* Write data to SD iSDIO register */ +#define ISDIO_MRITE 57 /* Masked write data to SD iSDIO register */ + +/* ATA/CF specific ioctl command */ +#define ATA_GET_REV 20 /* Get F/W revision */ +#define ATA_GET_MODEL 21 /* Get model name */ +#define ATA_GET_SN 22 /* Get serial number */ + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/kernel/fatfs/ff.c b/kernel/fatfs/ff.c new file mode 100644 index 0000000..3f65edf --- /dev/null +++ b/kernel/fatfs/ff.c @@ -0,0 +1,6981 @@ +/*----------------------------------------------------------------------------/ +/ FatFs - Generic FAT Filesystem Module R0.14b / +/-----------------------------------------------------------------------------/ +/ +/ Copyright (C) 2021, ChaN, all right reserved. +/ +/ FatFs module is an open source software. Redistribution and use of FatFs in +/ source and binary forms, with or without modification, are permitted provided +/ that the following condition is met: +/ +/ 1. Redistributions of source code must retain the above copyright notice, +/ this condition and the following disclaimer. +/ +/ This software is provided by the copyright holder and contributors "AS IS" +/ and any warranties related to this software are DISCLAIMED. +/ The copyright owner or contributors be NOT LIABLE for any damages caused +/ by use of this software. +/ +/----------------------------------------------------------------------------*/ + + +#include +#include "ff.h" /* Declarations of FatFs API */ +#include "diskio.h" /* Declarations of device I/O functions */ + + +/*-------------------------------------------------------------------------- + + Module Private Definitions + +---------------------------------------------------------------------------*/ + +#if FF_DEFINED != 86631 /* Revision ID */ +#error Wrong include file (ff.h). +#endif + + +/* Limits and boundaries */ +#define MAX_DIR 0x200000 /* Max size of FAT directory */ +#define MAX_DIR_EX 0x10000000 /* Max size of exFAT directory */ +#define MAX_FAT12 0xFF5 /* Max FAT12 clusters (differs from specs, but right for real DOS/Windows behavior) */ +#define MAX_FAT16 0xFFF5 /* Max FAT16 clusters (differs from specs, but right for real DOS/Windows behavior) */ +#define MAX_FAT32 0x0FFFFFF5 /* Max FAT32 clusters (not specified, practical limit) */ +#define MAX_EXFAT 0x7FFFFFFD /* Max exFAT clusters (differs from specs, implementation limit) */ + + +/* Character code support macros */ +#define IsUpper(c) ((c) >= 'A' && (c) <= 'Z') +#define IsLower(c) ((c) >= 'a' && (c) <= 'z') +#define IsDigit(c) ((c) >= '0' && (c) <= '9') +#define IsSeparator(c) ((c) == '/' || (c) == '\\') +#define IsTerminator(c) ((UINT)(c) < (FF_USE_LFN ? ' ' : '!')) +#define IsSurrogate(c) ((c) >= 0xD800 && (c) <= 0xDFFF) +#define IsSurrogateH(c) ((c) >= 0xD800 && (c) <= 0xDBFF) +#define IsSurrogateL(c) ((c) >= 0xDC00 && (c) <= 0xDFFF) + + +/* Additional file access control and file status flags for internal use */ +#define FA_SEEKEND 0x20 /* Seek to end of the file on file open */ +#define FA_MODIFIED 0x40 /* File has been modified */ +#define FA_DIRTY 0x80 /* FIL.buf[] needs to be written-back */ + + +/* Additional file attribute bits for internal use */ +#define AM_VOL 0x08 /* Volume label */ +#define AM_LFN 0x0F /* LFN entry */ +#define AM_MASK 0x3F /* Mask of defined bits in FAT */ +#define AM_MASKX 0x37 /* Mask of defined bits in exFAT */ + + +/* Name status flags in fn[11] */ +#define NSFLAG 11 /* Index of the name status byte */ +#define NS_LOSS 0x01 /* Out of 8.3 format */ +#define NS_LFN 0x02 /* Force to create LFN entry */ +#define NS_LAST 0x04 /* Last segment */ +#define NS_BODY 0x08 /* Lower case flag (body) */ +#define NS_EXT 0x10 /* Lower case flag (ext) */ +#define NS_DOT 0x20 /* Dot entry */ +#define NS_NOLFN 0x40 /* Do not find LFN */ +#define NS_NONAME 0x80 /* Not followed */ + + +/* exFAT directory entry types */ +#define ET_BITMAP 0x81 /* Allocation bitmap */ +#define ET_UPCASE 0x82 /* Up-case table */ +#define ET_VLABEL 0x83 /* Volume label */ +#define ET_FILEDIR 0x85 /* File and directory */ +#define ET_STREAM 0xC0 /* Stream extension */ +#define ET_FILENAME 0xC1 /* Name extension */ + + +/* FatFs refers the FAT structure as simple byte array instead of structure member +/ because the C structure is not binary compatible between different platforms */ + +#define BS_JmpBoot 0 /* x86 jump instruction (3-byte) */ +#define BS_OEMName 3 /* OEM name (8-byte) */ +#define BPB_BytsPerSec 11 /* Sector size [byte] (WORD) */ +#define BPB_SecPerClus 13 /* Cluster size [sector] (BYTE) */ +#define BPB_RsvdSecCnt 14 /* Size of reserved area [sector] (WORD) */ +#define BPB_NumFATs 16 /* Number of FATs (BYTE) */ +#define BPB_RootEntCnt 17 /* Size of root directory area for FAT [entry] (WORD) */ +#define BPB_TotSec16 19 /* Volume size (16-bit) [sector] (WORD) */ +#define BPB_Media 21 /* Media descriptor byte (BYTE) */ +#define BPB_FATSz16 22 /* FAT size (16-bit) [sector] (WORD) */ +#define BPB_SecPerTrk 24 /* Number of sectors per track for int13h [sector] (WORD) */ +#define BPB_NumHeads 26 /* Number of heads for int13h (WORD) */ +#define BPB_HiddSec 28 /* Volume offset from top of the drive (DWORD) */ +#define BPB_TotSec32 32 /* Volume size (32-bit) [sector] (DWORD) */ +#define BS_DrvNum 36 /* Physical drive number for int13h (BYTE) */ +#define BS_NTres 37 /* WindowsNT error flag (BYTE) */ +#define BS_BootSig 38 /* Extended boot signature (BYTE) */ +#define BS_VolID 39 /* Volume serial number (DWORD) */ +#define BS_VolLab 43 /* Volume label string (8-byte) */ +#define BS_FilSysType 54 /* Filesystem type string (8-byte) */ +#define BS_BootCode 62 /* Boot code (448-byte) */ +#define BS_55AA 510 /* Signature word (WORD) */ + +#define BPB_FATSz32 36 /* FAT32: FAT size [sector] (DWORD) */ +#define BPB_ExtFlags32 40 /* FAT32: Extended flags (WORD) */ +#define BPB_FSVer32 42 /* FAT32: Filesystem version (WORD) */ +#define BPB_RootClus32 44 /* FAT32: Root directory cluster (DWORD) */ +#define BPB_FSInfo32 48 /* FAT32: Offset of FSINFO sector (WORD) */ +#define BPB_BkBootSec32 50 /* FAT32: Offset of backup boot sector (WORD) */ +#define BS_DrvNum32 64 /* FAT32: Physical drive number for int13h (BYTE) */ +#define BS_NTres32 65 /* FAT32: Error flag (BYTE) */ +#define BS_BootSig32 66 /* FAT32: Extended boot signature (BYTE) */ +#define BS_VolID32 67 /* FAT32: Volume serial number (DWORD) */ +#define BS_VolLab32 71 /* FAT32: Volume label string (8-byte) */ +#define BS_FilSysType32 82 /* FAT32: Filesystem type string (8-byte) */ +#define BS_BootCode32 90 /* FAT32: Boot code (420-byte) */ + +#define BPB_ZeroedEx 11 /* exFAT: MBZ field (53-byte) */ +#define BPB_VolOfsEx 64 /* exFAT: Volume offset from top of the drive [sector] (QWORD) */ +#define BPB_TotSecEx 72 /* exFAT: Volume size [sector] (QWORD) */ +#define BPB_FatOfsEx 80 /* exFAT: FAT offset from top of the volume [sector] (DWORD) */ +#define BPB_FatSzEx 84 /* exFAT: FAT size [sector] (DWORD) */ +#define BPB_DataOfsEx 88 /* exFAT: Data offset from top of the volume [sector] (DWORD) */ +#define BPB_NumClusEx 92 /* exFAT: Number of clusters (DWORD) */ +#define BPB_RootClusEx 96 /* exFAT: Root directory start cluster (DWORD) */ +#define BPB_VolIDEx 100 /* exFAT: Volume serial number (DWORD) */ +#define BPB_FSVerEx 104 /* exFAT: Filesystem version (WORD) */ +#define BPB_VolFlagEx 106 /* exFAT: Volume flags (WORD) */ +#define BPB_BytsPerSecEx 108 /* exFAT: Log2 of sector size in unit of byte (BYTE) */ +#define BPB_SecPerClusEx 109 /* exFAT: Log2 of cluster size in unit of sector (BYTE) */ +#define BPB_NumFATsEx 110 /* exFAT: Number of FATs (BYTE) */ +#define BPB_DrvNumEx 111 /* exFAT: Physical drive number for int13h (BYTE) */ +#define BPB_PercInUseEx 112 /* exFAT: Percent in use (BYTE) */ +#define BPB_RsvdEx 113 /* exFAT: Reserved (7-byte) */ +#define BS_BootCodeEx 120 /* exFAT: Boot code (390-byte) */ + +#define DIR_Name 0 /* Short file name (11-byte) */ +#define DIR_Attr 11 /* Attribute (BYTE) */ +#define DIR_NTres 12 /* Lower case flag (BYTE) */ +#define DIR_CrtTime10 13 /* Created time sub-second (BYTE) */ +#define DIR_CrtTime 14 /* Created time (DWORD) */ +#define DIR_LstAccDate 18 /* Last accessed date (WORD) */ +#define DIR_FstClusHI 20 /* Higher 16-bit of first cluster (WORD) */ +#define DIR_ModTime 22 /* Modified time (DWORD) */ +#define DIR_FstClusLO 26 /* Lower 16-bit of first cluster (WORD) */ +#define DIR_FileSize 28 /* File size (DWORD) */ +#define LDIR_Ord 0 /* LFN: LFN order and LLE flag (BYTE) */ +#define LDIR_Attr 11 /* LFN: LFN attribute (BYTE) */ +#define LDIR_Type 12 /* LFN: Entry type (BYTE) */ +#define LDIR_Chksum 13 /* LFN: Checksum of the SFN (BYTE) */ +#define LDIR_FstClusLO 26 /* LFN: MBZ field (WORD) */ +#define XDIR_Type 0 /* exFAT: Type of exFAT directory entry (BYTE) */ +#define XDIR_NumLabel 1 /* exFAT: Number of volume label characters (BYTE) */ +#define XDIR_Label 2 /* exFAT: Volume label (11-WORD) */ +#define XDIR_CaseSum 4 /* exFAT: Sum of case conversion table (DWORD) */ +#define XDIR_NumSec 1 /* exFAT: Number of secondary entries (BYTE) */ +#define XDIR_SetSum 2 /* exFAT: Sum of the set of directory entries (WORD) */ +#define XDIR_Attr 4 /* exFAT: File attribute (WORD) */ +#define XDIR_CrtTime 8 /* exFAT: Created time (DWORD) */ +#define XDIR_ModTime 12 /* exFAT: Modified time (DWORD) */ +#define XDIR_AccTime 16 /* exFAT: Last accessed time (DWORD) */ +#define XDIR_CrtTime10 20 /* exFAT: Created time subsecond (BYTE) */ +#define XDIR_ModTime10 21 /* exFAT: Modified time subsecond (BYTE) */ +#define XDIR_CrtTZ 22 /* exFAT: Created timezone (BYTE) */ +#define XDIR_ModTZ 23 /* exFAT: Modified timezone (BYTE) */ +#define XDIR_AccTZ 24 /* exFAT: Last accessed timezone (BYTE) */ +#define XDIR_GenFlags 33 /* exFAT: General secondary flags (BYTE) */ +#define XDIR_NumName 35 /* exFAT: Number of file name characters (BYTE) */ +#define XDIR_NameHash 36 /* exFAT: Hash of file name (WORD) */ +#define XDIR_ValidFileSize 40 /* exFAT: Valid file size (QWORD) */ +#define XDIR_FstClus 52 /* exFAT: First cluster of the file data (DWORD) */ +#define XDIR_FileSize 56 /* exFAT: File/Directory size (QWORD) */ + +#define SZDIRE 32 /* Size of a directory entry */ +#define DDEM 0xE5 /* Deleted directory entry mark set to DIR_Name[0] */ +#define RDDEM 0x05 /* Replacement of the character collides with DDEM */ +#define LLEF 0x40 /* Last long entry flag in LDIR_Ord */ + +#define FSI_LeadSig 0 /* FAT32 FSI: Leading signature (DWORD) */ +#define FSI_StrucSig 484 /* FAT32 FSI: Structure signature (DWORD) */ +#define FSI_Free_Count 488 /* FAT32 FSI: Number of free clusters (DWORD) */ +#define FSI_Nxt_Free 492 /* FAT32 FSI: Last allocated cluster (DWORD) */ + +#define MBR_Table 446 /* MBR: Offset of partition table in the MBR */ +#define SZ_PTE 16 /* MBR: Size of a partition table entry */ +#define PTE_Boot 0 /* MBR PTE: Boot indicator */ +#define PTE_StHead 1 /* MBR PTE: Start head */ +#define PTE_StSec 2 /* MBR PTE: Start sector */ +#define PTE_StCyl 3 /* MBR PTE: Start cylinder */ +#define PTE_System 4 /* MBR PTE: System ID */ +#define PTE_EdHead 5 /* MBR PTE: End head */ +#define PTE_EdSec 6 /* MBR PTE: End sector */ +#define PTE_EdCyl 7 /* MBR PTE: End cylinder */ +#define PTE_StLba 8 /* MBR PTE: Start in LBA */ +#define PTE_SizLba 12 /* MBR PTE: Size in LBA */ + +#define GPTH_Sign 0 /* GPT: Header signature (8-byte) */ +#define GPTH_Rev 8 /* GPT: Revision (DWORD) */ +#define GPTH_Size 12 /* GPT: Header size (DWORD) */ +#define GPTH_Bcc 16 /* GPT: Header BCC (DWORD) */ +#define GPTH_CurLba 24 /* GPT: Main header LBA (QWORD) */ +#define GPTH_BakLba 32 /* GPT: Backup header LBA (QWORD) */ +#define GPTH_FstLba 40 /* GPT: First LBA for partitions (QWORD) */ +#define GPTH_LstLba 48 /* GPT: Last LBA for partitions (QWORD) */ +#define GPTH_DskGuid 56 /* GPT: Disk GUID (16-byte) */ +#define GPTH_PtOfs 72 /* GPT: Partation table LBA (QWORD) */ +#define GPTH_PtNum 80 /* GPT: Number of table entries (DWORD) */ +#define GPTH_PteSize 84 /* GPT: Size of table entry (DWORD) */ +#define GPTH_PtBcc 88 /* GPT: Partation table BCC (DWORD) */ +#define SZ_GPTE 128 /* GPT: Size of partition table entry */ +#define GPTE_PtGuid 0 /* GPT PTE: Partition type GUID (16-byte) */ +#define GPTE_UpGuid 16 /* GPT PTE: Partition unique GUID (16-byte) */ +#define GPTE_FstLba 32 /* GPT PTE: First LBA (QWORD) */ +#define GPTE_LstLba 40 /* GPT PTE: Last LBA inclusive (QWORD) */ +#define GPTE_Flags 48 /* GPT PTE: Flags (QWORD) */ +#define GPTE_Name 56 /* GPT PTE: Name */ + + +/* Post process on fatal error in the file operations */ +#define ABORT(fs, res) { fp->err = (BYTE)(res); LEAVE_FF(fs, res); } + + +/* Re-entrancy related */ +#if FF_FS_REENTRANT +#if FF_USE_LFN == 1 +#error Static LFN work area cannot be used in thread-safe configuration +#endif +#define LEAVE_FF(fs, res) { unlock_fs(fs, res); return res; } +#else +#define LEAVE_FF(fs, res) return res +#endif + + +/* Definitions of logical drive - physical location conversion */ +#if FF_MULTI_PARTITION +#define LD2PD(vol) VolToPart[vol].pd /* Get physical drive number */ +#define LD2PT(vol) VolToPart[vol].pt /* Get partition number (0:auto search, 1..:forced partition number) */ +#else +#define LD2PD(vol) (BYTE)(vol) /* Each logical drive is associated with the same physical drive number */ +#define LD2PT(vol) 0 /* Auto partition search */ +#endif + + +/* Definitions of sector size */ +#if (FF_MAX_SS < FF_MIN_SS) || (FF_MAX_SS != 512 && FF_MAX_SS != 1024 && FF_MAX_SS != 2048 && FF_MAX_SS != 4096) || (FF_MIN_SS != 512 && FF_MIN_SS != 1024 && FF_MIN_SS != 2048 && FF_MIN_SS != 4096) +#error Wrong sector size configuration +#endif +#if FF_MAX_SS == FF_MIN_SS +#define SS(fs) ((UINT)FF_MAX_SS) /* Fixed sector size */ +#else +#define SS(fs) ((fs)->ssize) /* Variable sector size */ +#endif + + +/* Timestamp */ +#if FF_FS_NORTC == 1 +#if FF_NORTC_YEAR < 1980 || FF_NORTC_YEAR > 2107 || FF_NORTC_MON < 1 || FF_NORTC_MON > 12 || FF_NORTC_MDAY < 1 || FF_NORTC_MDAY > 31 +#error Invalid FF_FS_NORTC settings +#endif +#define GET_FATTIME() ((DWORD)(FF_NORTC_YEAR - 1980) << 25 | (DWORD)FF_NORTC_MON << 21 | (DWORD)FF_NORTC_MDAY << 16) +#else +#define GET_FATTIME() get_fattime() +#endif + + +/* File lock controls */ +#if FF_FS_LOCK != 0 +#if FF_FS_READONLY +#error FF_FS_LOCK must be 0 at read-only configuration +#endif +typedef struct { + FATFS *fs; /* Object ID 1, volume (NULL:blank entry) */ + DWORD clu; /* Object ID 2, containing directory (0:root) */ + DWORD ofs; /* Object ID 3, offset in the directory */ + WORD ctr; /* Object open counter, 0:none, 0x01..0xFF:read mode open count, 0x100:write mode */ +} FILESEM; +#endif + + +/* SBCS up-case tables (\x80-\xFF) */ +#define TBL_CT437 {0x80,0x9A,0x45,0x41,0x8E,0x41,0x8F,0x80,0x45,0x45,0x45,0x49,0x49,0x49,0x8E,0x8F, \ + 0x90,0x92,0x92,0x4F,0x99,0x4F,0x55,0x55,0x59,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F, \ + 0x41,0x49,0x4F,0x55,0xA5,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF, \ + 0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \ + 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF, \ + 0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \ + 0xE0,0xE1,0xE2,0xE3,0xE4,0xE5,0xE6,0xE7,0xE8,0xE9,0xEA,0xEB,0xEC,0xED,0xEE,0xEF, \ + 0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF} +#define TBL_CT720 {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F, \ + 0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F, \ + 0xA0,0xA1,0xA2,0xA3,0xA4,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF, \ + 0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \ + 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF, \ + 0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \ + 0xE0,0xE1,0xE2,0xE3,0xE4,0xE5,0xE6,0xE7,0xE8,0xE9,0xEA,0xEB,0xEC,0xED,0xEE,0xEF, \ + 0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF} +#define TBL_CT737 {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F, \ + 0x90,0x92,0x92,0x93,0x94,0x95,0x96,0x97,0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87, \ + 0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x90,0x91,0xAA,0x92,0x93,0x94,0x95,0x96, \ + 0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \ + 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF, \ + 0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \ + 0x97,0xEA,0xEB,0xEC,0xE4,0xED,0xEE,0xEF,0xF5,0xF0,0xEA,0xEB,0xEC,0xED,0xEE,0xEF, \ + 0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF} +#define TBL_CT771 {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F, \ + 0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F, \ + 0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F, \ + 0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \ + 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF, \ + 0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDC,0xDE,0xDE, \ + 0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F, \ + 0xF0,0xF0,0xF2,0xF2,0xF4,0xF4,0xF6,0xF6,0xF8,0xF8,0xFA,0xFA,0xFC,0xFC,0xFE,0xFF} +#define TBL_CT775 {0x80,0x9A,0x91,0xA0,0x8E,0x95,0x8F,0x80,0xAD,0xED,0x8A,0x8A,0xA1,0x8D,0x8E,0x8F, \ + 0x90,0x92,0x92,0xE2,0x99,0x95,0x96,0x97,0x97,0x99,0x9A,0x9D,0x9C,0x9D,0x9E,0x9F, \ + 0xA0,0xA1,0xE0,0xA3,0xA3,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF, \ + 0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \ + 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF, \ + 0xB5,0xB6,0xB7,0xB8,0xBD,0xBE,0xC6,0xC7,0xA5,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \ + 0xE0,0xE1,0xE2,0xE3,0xE5,0xE5,0xE6,0xE3,0xE8,0xE8,0xEA,0xEA,0xEE,0xED,0xEE,0xEF, \ + 0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF} +#define TBL_CT850 {0x43,0x55,0x45,0x41,0x41,0x41,0x41,0x43,0x45,0x45,0x45,0x49,0x49,0x49,0x41,0x41, \ + 0x45,0x92,0x92,0x4F,0x4F,0x4F,0x55,0x55,0x59,0x4F,0x55,0x4F,0x9C,0x4F,0x9E,0x9F, \ + 0x41,0x49,0x4F,0x55,0xA5,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF, \ + 0xB0,0xB1,0xB2,0xB3,0xB4,0x41,0x41,0x41,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \ + 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0x41,0x41,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF, \ + 0xD1,0xD1,0x45,0x45,0x45,0x49,0x49,0x49,0x49,0xD9,0xDA,0xDB,0xDC,0xDD,0x49,0xDF, \ + 0x4F,0xE1,0x4F,0x4F,0x4F,0x4F,0xE6,0xE8,0xE8,0x55,0x55,0x55,0x59,0x59,0xEE,0xEF, \ + 0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF} +#define TBL_CT852 {0x80,0x9A,0x90,0xB6,0x8E,0xDE,0x8F,0x80,0x9D,0xD3,0x8A,0x8A,0xD7,0x8D,0x8E,0x8F, \ + 0x90,0x91,0x91,0xE2,0x99,0x95,0x95,0x97,0x97,0x99,0x9A,0x9B,0x9B,0x9D,0x9E,0xAC, \ + 0xB5,0xD6,0xE0,0xE9,0xA4,0xA4,0xA6,0xA6,0xA8,0xA8,0xAA,0x8D,0xAC,0xB8,0xAE,0xAF, \ + 0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBD,0xBF, \ + 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC6,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF, \ + 0xD1,0xD1,0xD2,0xD3,0xD2,0xD5,0xD6,0xD7,0xB7,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \ + 0xE0,0xE1,0xE2,0xE3,0xE3,0xD5,0xE6,0xE6,0xE8,0xE9,0xE8,0xEB,0xED,0xED,0xDD,0xEF, \ + 0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xEB,0xFC,0xFC,0xFE,0xFF} +#define TBL_CT855 {0x81,0x81,0x83,0x83,0x85,0x85,0x87,0x87,0x89,0x89,0x8B,0x8B,0x8D,0x8D,0x8F,0x8F, \ + 0x91,0x91,0x93,0x93,0x95,0x95,0x97,0x97,0x99,0x99,0x9B,0x9B,0x9D,0x9D,0x9F,0x9F, \ + 0xA1,0xA1,0xA3,0xA3,0xA5,0xA5,0xA7,0xA7,0xA9,0xA9,0xAB,0xAB,0xAD,0xAD,0xAE,0xAF, \ + 0xB0,0xB1,0xB2,0xB3,0xB4,0xB6,0xB6,0xB8,0xB8,0xB9,0xBA,0xBB,0xBC,0xBE,0xBE,0xBF, \ + 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC7,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF, \ + 0xD1,0xD1,0xD3,0xD3,0xD5,0xD5,0xD7,0xD7,0xDD,0xD9,0xDA,0xDB,0xDC,0xDD,0xE0,0xDF, \ + 0xE0,0xE2,0xE2,0xE4,0xE4,0xE6,0xE6,0xE8,0xE8,0xEA,0xEA,0xEC,0xEC,0xEE,0xEE,0xEF, \ + 0xF0,0xF2,0xF2,0xF4,0xF4,0xF6,0xF6,0xF8,0xF8,0xFA,0xFA,0xFC,0xFC,0xFD,0xFE,0xFF} +#define TBL_CT857 {0x80,0x9A,0x90,0xB6,0x8E,0xB7,0x8F,0x80,0xD2,0xD3,0xD4,0xD8,0xD7,0x49,0x8E,0x8F, \ + 0x90,0x92,0x92,0xE2,0x99,0xE3,0xEA,0xEB,0x98,0x99,0x9A,0x9D,0x9C,0x9D,0x9E,0x9E, \ + 0xB5,0xD6,0xE0,0xE9,0xA5,0xA5,0xA6,0xA6,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF, \ + 0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \ + 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC7,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF, \ + 0xD0,0xD1,0xD2,0xD3,0xD4,0x49,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \ + 0xE0,0xE1,0xE2,0xE3,0xE5,0xE5,0xE6,0xE7,0xE8,0xE9,0xEA,0xEB,0xDE,0xED,0xEE,0xEF, \ + 0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF} +#define TBL_CT860 {0x80,0x9A,0x90,0x8F,0x8E,0x91,0x86,0x80,0x89,0x89,0x92,0x8B,0x8C,0x98,0x8E,0x8F, \ + 0x90,0x91,0x92,0x8C,0x99,0xA9,0x96,0x9D,0x98,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F, \ + 0x86,0x8B,0x9F,0x96,0xA5,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF, \ + 0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \ + 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF, \ + 0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \ + 0xE0,0xE1,0xE2,0xE3,0xE4,0xE5,0xE6,0xE7,0xE8,0xE9,0xEA,0xEB,0xEC,0xED,0xEE,0xEF, \ + 0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF} +#define TBL_CT861 {0x80,0x9A,0x90,0x41,0x8E,0x41,0x8F,0x80,0x45,0x45,0x45,0x8B,0x8B,0x8D,0x8E,0x8F, \ + 0x90,0x92,0x92,0x4F,0x99,0x8D,0x55,0x97,0x97,0x99,0x9A,0x9D,0x9C,0x9D,0x9E,0x9F, \ + 0xA4,0xA5,0xA6,0xA7,0xA4,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF, \ + 0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \ + 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF, \ + 0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \ + 0xE0,0xE1,0xE2,0xE3,0xE4,0xE5,0xE6,0xE7,0xE8,0xE9,0xEA,0xEB,0xEC,0xED,0xEE,0xEF, \ + 0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF} +#define TBL_CT862 {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F, \ + 0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F, \ + 0x41,0x49,0x4F,0x55,0xA5,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF, \ + 0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \ + 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF, \ + 0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \ + 0xE0,0xE1,0xE2,0xE3,0xE4,0xE5,0xE6,0xE7,0xE8,0xE9,0xEA,0xEB,0xEC,0xED,0xEE,0xEF, \ + 0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF} +#define TBL_CT863 {0x43,0x55,0x45,0x41,0x41,0x41,0x86,0x43,0x45,0x45,0x45,0x49,0x49,0x8D,0x41,0x8F, \ + 0x45,0x45,0x45,0x4F,0x45,0x49,0x55,0x55,0x98,0x4F,0x55,0x9B,0x9C,0x55,0x55,0x9F, \ + 0xA0,0xA1,0x4F,0x55,0xA4,0xA5,0xA6,0xA7,0x49,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF, \ + 0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \ + 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF, \ + 0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \ + 0xE0,0xE1,0xE2,0xE3,0xE4,0xE5,0xE6,0xE7,0xE8,0xE9,0xEA,0xEB,0xEC,0xED,0xEE,0xEF, \ + 0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF} +#define TBL_CT864 {0x80,0x9A,0x45,0x41,0x8E,0x41,0x8F,0x80,0x45,0x45,0x45,0x49,0x49,0x49,0x8E,0x8F, \ + 0x90,0x92,0x92,0x4F,0x99,0x4F,0x55,0x55,0x59,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F, \ + 0x41,0x49,0x4F,0x55,0xA5,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF, \ + 0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \ + 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF, \ + 0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \ + 0xE0,0xE1,0xE2,0xE3,0xE4,0xE5,0xE6,0xE7,0xE8,0xE9,0xEA,0xEB,0xEC,0xED,0xEE,0xEF, \ + 0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF} +#define TBL_CT865 {0x80,0x9A,0x90,0x41,0x8E,0x41,0x8F,0x80,0x45,0x45,0x45,0x49,0x49,0x49,0x8E,0x8F, \ + 0x90,0x92,0x92,0x4F,0x99,0x4F,0x55,0x55,0x59,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F, \ + 0x41,0x49,0x4F,0x55,0xA5,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF, \ + 0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \ + 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF, \ + 0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \ + 0xE0,0xE1,0xE2,0xE3,0xE4,0xE5,0xE6,0xE7,0xE8,0xE9,0xEA,0xEB,0xEC,0xED,0xEE,0xEF, \ + 0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF} +#define TBL_CT866 {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F, \ + 0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F, \ + 0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F, \ + 0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \ + 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF, \ + 0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \ + 0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F, \ + 0xF0,0xF0,0xF2,0xF2,0xF4,0xF4,0xF6,0xF6,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF} +#define TBL_CT869 {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F, \ + 0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x9A,0x86,0x9C,0x8D,0x8F,0x90, \ + 0x91,0x90,0x92,0x95,0xA4,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF, \ + 0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \ + 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF, \ + 0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xA4,0xA5,0xA6,0xD9,0xDA,0xDB,0xDC,0xA7,0xA8,0xDF, \ + 0xA9,0xAA,0xAC,0xAD,0xB5,0xB6,0xB7,0xB8,0xBD,0xBE,0xC6,0xC7,0xCF,0xCF,0xD0,0xEF, \ + 0xF0,0xF1,0xD1,0xD2,0xD3,0xF5,0xD4,0xF7,0xF8,0xF9,0xD5,0x96,0x95,0x98,0xFE,0xFF} + + +/* DBCS code range |----- 1st byte -----| |----------- 2nd byte -----------| */ +/* <------> <------> <------> <------> <------> */ +#define TBL_DC932 {0x81, 0x9F, 0xE0, 0xFC, 0x40, 0x7E, 0x80, 0xFC, 0x00, 0x00} +#define TBL_DC936 {0x81, 0xFE, 0x00, 0x00, 0x40, 0x7E, 0x80, 0xFE, 0x00, 0x00} +#define TBL_DC949 {0x81, 0xFE, 0x00, 0x00, 0x41, 0x5A, 0x61, 0x7A, 0x81, 0xFE} +#define TBL_DC950 {0x81, 0xFE, 0x00, 0x00, 0x40, 0x7E, 0xA1, 0xFE, 0x00, 0x00} + + +/* Macros for table definitions */ +#define MERGE_2STR(a, b) a ## b +#define MKCVTBL(hd, cp) MERGE_2STR(hd, cp) + + + + +/*-------------------------------------------------------------------------- + + Module Private Work Area + +---------------------------------------------------------------------------*/ +/* Remark: Variables defined here without initial value shall be guaranteed +/ zero/null at start-up. If not, the linker option or start-up routine is +/ not compliance with C standard. */ + +/*--------------------------------*/ +/* File/Volume controls */ +/*--------------------------------*/ + +#if FF_VOLUMES < 1 || FF_VOLUMES > 10 +#error Wrong FF_VOLUMES setting +#endif +static FATFS* FatFs[FF_VOLUMES]; /* Pointer to the filesystem objects (logical drives) */ +static WORD Fsid; /* Filesystem mount ID */ + +#if FF_FS_RPATH != 0 +static BYTE CurrVol; /* Current drive */ +#endif + +#if FF_FS_LOCK != 0 +static FILESEM Files[FF_FS_LOCK]; /* Open object lock semaphores */ +#endif + +#if FF_STR_VOLUME_ID +#ifdef FF_VOLUME_STRS +static const char* const VolumeStr[FF_VOLUMES] = {FF_VOLUME_STRS}; /* Pre-defined volume ID */ +#endif +#endif + +#if FF_LBA64 +#if FF_MIN_GPT > 0x100000000 +#error Wrong FF_MIN_GPT setting +#endif +static const BYTE GUID_MS_Basic[16] = {0xA2,0xA0,0xD0,0xEB,0xE5,0xB9,0x33,0x44,0x87,0xC0,0x68,0xB6,0xB7,0x26,0x99,0xC7}; +#endif + + + +/*--------------------------------*/ +/* LFN/Directory working buffer */ +/*--------------------------------*/ + +#if FF_USE_LFN == 0 /* Non-LFN configuration */ +#if FF_FS_EXFAT +#error LFN must be enabled when enable exFAT +#endif +#define DEF_NAMBUF +#define INIT_NAMBUF(fs) +#define FREE_NAMBUF() +#define LEAVE_MKFS(res) return res + +#else /* LFN configurations */ +#if FF_MAX_LFN < 12 || FF_MAX_LFN > 255 +#error Wrong setting of FF_MAX_LFN +#endif +#if FF_LFN_BUF < FF_SFN_BUF || FF_SFN_BUF < 12 +#error Wrong setting of FF_LFN_BUF or FF_SFN_BUF +#endif +#if FF_LFN_UNICODE < 0 || FF_LFN_UNICODE > 3 +#error Wrong setting of FF_LFN_UNICODE +#endif +static const BYTE LfnOfs[] = {1,3,5,7,9,14,16,18,20,22,24,28,30}; /* FAT: Offset of LFN characters in the directory entry */ +#define MAXDIRB(nc) ((nc + 44U) / 15 * SZDIRE) /* exFAT: Size of directory entry block scratchpad buffer needed for the name length */ + +#if FF_USE_LFN == 1 /* LFN enabled with static working buffer */ +#if FF_FS_EXFAT +static BYTE DirBuf[MAXDIRB(FF_MAX_LFN)]; /* Directory entry block scratchpad buffer */ +#endif +static WCHAR LfnBuf[FF_MAX_LFN + 1]; /* LFN working buffer */ +#define DEF_NAMBUF +#define INIT_NAMBUF(fs) +#define FREE_NAMBUF() +#define LEAVE_MKFS(res) return res + +#elif FF_USE_LFN == 2 /* LFN enabled with dynamic working buffer on the stack */ +#if FF_FS_EXFAT +#define DEF_NAMBUF WCHAR lbuf[FF_MAX_LFN+1]; BYTE dbuf[MAXDIRB(FF_MAX_LFN)]; /* LFN working buffer and directory entry block scratchpad buffer */ +#define INIT_NAMBUF(fs) { (fs)->lfnbuf = lbuf; (fs)->dirbuf = dbuf; } +#define FREE_NAMBUF() +#else +#define DEF_NAMBUF WCHAR lbuf[FF_MAX_LFN+1]; /* LFN working buffer */ +#define INIT_NAMBUF(fs) { (fs)->lfnbuf = lbuf; } +#define FREE_NAMBUF() +#endif +#define LEAVE_MKFS(res) return res + +#elif FF_USE_LFN == 3 /* LFN enabled with dynamic working buffer on the heap */ +#if FF_FS_EXFAT +#define DEF_NAMBUF WCHAR *lfn; /* Pointer to LFN working buffer and directory entry block scratchpad buffer */ +#define INIT_NAMBUF(fs) { lfn = ff_memalloc((FF_MAX_LFN+1)*2 + MAXDIRB(FF_MAX_LFN)); if (!lfn) LEAVE_FF(fs, FR_NOT_ENOUGH_CORE); (fs)->lfnbuf = lfn; (fs)->dirbuf = (BYTE*)(lfn+FF_MAX_LFN+1); } +#define FREE_NAMBUF() ff_memfree(lfn) +#else +#define DEF_NAMBUF WCHAR *lfn; /* Pointer to LFN working buffer */ +#define INIT_NAMBUF(fs) { lfn = ff_memalloc((FF_MAX_LFN+1)*2); if (!lfn) LEAVE_FF(fs, FR_NOT_ENOUGH_CORE); (fs)->lfnbuf = lfn; } +#define FREE_NAMBUF() ff_memfree(lfn) +#endif +#define LEAVE_MKFS(res) { if (!work) ff_memfree(buf); return res; } +#define MAX_MALLOC 0x8000 /* Must be >=FF_MAX_SS */ + +#else +#error Wrong setting of FF_USE_LFN + +#endif /* FF_USE_LFN == 1 */ +#endif /* FF_USE_LFN == 0 */ + + + +/*--------------------------------*/ +/* Code conversion tables */ +/*--------------------------------*/ + +#if FF_CODE_PAGE == 0 /* Run-time code page configuration */ +#define CODEPAGE CodePage +static WORD CodePage; /* Current code page */ +static const BYTE *ExCvt, *DbcTbl; /* Pointer to current SBCS up-case table and DBCS code range table below */ + +static const BYTE Ct437[] = TBL_CT437; +static const BYTE Ct720[] = TBL_CT720; +static const BYTE Ct737[] = TBL_CT737; +static const BYTE Ct771[] = TBL_CT771; +static const BYTE Ct775[] = TBL_CT775; +static const BYTE Ct850[] = TBL_CT850; +static const BYTE Ct852[] = TBL_CT852; +static const BYTE Ct855[] = TBL_CT855; +static const BYTE Ct857[] = TBL_CT857; +static const BYTE Ct860[] = TBL_CT860; +static const BYTE Ct861[] = TBL_CT861; +static const BYTE Ct862[] = TBL_CT862; +static const BYTE Ct863[] = TBL_CT863; +static const BYTE Ct864[] = TBL_CT864; +static const BYTE Ct865[] = TBL_CT865; +static const BYTE Ct866[] = TBL_CT866; +static const BYTE Ct869[] = TBL_CT869; +static const BYTE Dc932[] = TBL_DC932; +static const BYTE Dc936[] = TBL_DC936; +static const BYTE Dc949[] = TBL_DC949; +static const BYTE Dc950[] = TBL_DC950; + +#elif FF_CODE_PAGE < 900 /* Static code page configuration (SBCS) */ +#define CODEPAGE FF_CODE_PAGE +static const BYTE ExCvt[] = MKCVTBL(TBL_CT, FF_CODE_PAGE); + +#else /* Static code page configuration (DBCS) */ +#define CODEPAGE FF_CODE_PAGE +static const BYTE DbcTbl[] = MKCVTBL(TBL_DC, FF_CODE_PAGE); + +#endif + + + + +/*-------------------------------------------------------------------------- + + Module Private Functions + +---------------------------------------------------------------------------*/ + + +/*-----------------------------------------------------------------------*/ +/* Load/Store multi-byte word in the FAT structure */ +/*-----------------------------------------------------------------------*/ + +static WORD ld_word (const BYTE* ptr) /* Load a 2-byte little-endian word */ +{ + WORD rv; + + rv = ptr[1]; + rv = rv << 8 | ptr[0]; + return rv; +} + +static DWORD ld_dword (const BYTE* ptr) /* Load a 4-byte little-endian word */ +{ + DWORD rv; + + rv = ptr[3]; + rv = rv << 8 | ptr[2]; + rv = rv << 8 | ptr[1]; + rv = rv << 8 | ptr[0]; + return rv; +} + +#if FF_FS_EXFAT +static QWORD ld_qword (const BYTE* ptr) /* Load an 8-byte little-endian word */ +{ + QWORD rv; + + rv = ptr[7]; + rv = rv << 8 | ptr[6]; + rv = rv << 8 | ptr[5]; + rv = rv << 8 | ptr[4]; + rv = rv << 8 | ptr[3]; + rv = rv << 8 | ptr[2]; + rv = rv << 8 | ptr[1]; + rv = rv << 8 | ptr[0]; + return rv; +} +#endif + +#if !FF_FS_READONLY +static void st_word (BYTE* ptr, WORD val) /* Store a 2-byte word in little-endian */ +{ + *ptr++ = (BYTE)val; val >>= 8; + *ptr++ = (BYTE)val; +} + +static void st_dword (BYTE* ptr, DWORD val) /* Store a 4-byte word in little-endian */ +{ + *ptr++ = (BYTE)val; val >>= 8; + *ptr++ = (BYTE)val; val >>= 8; + *ptr++ = (BYTE)val; val >>= 8; + *ptr++ = (BYTE)val; +} + +#if FF_FS_EXFAT +static void st_qword (BYTE* ptr, QWORD val) /* Store an 8-byte word in little-endian */ +{ + *ptr++ = (BYTE)val; val >>= 8; + *ptr++ = (BYTE)val; val >>= 8; + *ptr++ = (BYTE)val; val >>= 8; + *ptr++ = (BYTE)val; val >>= 8; + *ptr++ = (BYTE)val; val >>= 8; + *ptr++ = (BYTE)val; val >>= 8; + *ptr++ = (BYTE)val; val >>= 8; + *ptr++ = (BYTE)val; +} +#endif +#endif /* !FF_FS_READONLY */ + + + +/*-----------------------------------------------------------------------*/ +/* String functions */ +/*-----------------------------------------------------------------------*/ + +/* Test if the byte is DBC 1st byte */ +static int dbc_1st (BYTE c) +{ +#if FF_CODE_PAGE == 0 /* Variable code page */ + if (DbcTbl && c >= DbcTbl[0]) { + if (c <= DbcTbl[1]) return 1; /* 1st byte range 1 */ + if (c >= DbcTbl[2] && c <= DbcTbl[3]) return 1; /* 1st byte range 2 */ + } +#elif FF_CODE_PAGE >= 900 /* DBCS fixed code page */ + if (c >= DbcTbl[0]) { + if (c <= DbcTbl[1]) return 1; + if (c >= DbcTbl[2] && c <= DbcTbl[3]) return 1; + } +#else /* SBCS fixed code page */ + if (c != 0) return 0; /* Always false */ +#endif + return 0; +} + + +/* Test if the byte is DBC 2nd byte */ +static int dbc_2nd (BYTE c) +{ +#if FF_CODE_PAGE == 0 /* Variable code page */ + if (DbcTbl && c >= DbcTbl[4]) { + if (c <= DbcTbl[5]) return 1; /* 2nd byte range 1 */ + if (c >= DbcTbl[6] && c <= DbcTbl[7]) return 1; /* 2nd byte range 2 */ + if (c >= DbcTbl[8] && c <= DbcTbl[9]) return 1; /* 2nd byte range 3 */ + } +#elif FF_CODE_PAGE >= 900 /* DBCS fixed code page */ + if (c >= DbcTbl[4]) { + if (c <= DbcTbl[5]) return 1; + if (c >= DbcTbl[6] && c <= DbcTbl[7]) return 1; + if (c >= DbcTbl[8] && c <= DbcTbl[9]) return 1; + } +#else /* SBCS fixed code page */ + if (c != 0) return 0; /* Always false */ +#endif + return 0; +} + + +#if FF_USE_LFN + +/* Get a Unicode code point from the TCHAR string in defined API encodeing */ +static DWORD tchar2uni ( /* Returns a character in UTF-16 encoding (>=0x10000 on surrogate pair, 0xFFFFFFFF on decode error) */ + const TCHAR** str /* Pointer to pointer to TCHAR string in configured encoding */ +) +{ + DWORD uc; + const TCHAR *p = *str; + +#if FF_LFN_UNICODE == 1 /* UTF-16 input */ + WCHAR wc; + + uc = *p++; /* Get a unit */ + if (IsSurrogate(uc)) { /* Surrogate? */ + wc = *p++; /* Get low surrogate */ + if (!IsSurrogateH(uc) || !IsSurrogateL(wc)) return 0xFFFFFFFF; /* Wrong surrogate? */ + uc = uc << 16 | wc; + } + +#elif FF_LFN_UNICODE == 2 /* UTF-8 input */ + BYTE b; + int nf; + + uc = (BYTE)*p++; /* Get an encoding unit */ + if (uc & 0x80) { /* Multiple byte code? */ + if ((uc & 0xE0) == 0xC0) { /* 2-byte sequence? */ + uc &= 0x1F; nf = 1; + } else if ((uc & 0xF0) == 0xE0) { /* 3-byte sequence? */ + uc &= 0x0F; nf = 2; + } else if ((uc & 0xF8) == 0xF0) { /* 4-byte sequence? */ + uc &= 0x07; nf = 3; + } else { /* Wrong sequence */ + return 0xFFFFFFFF; + } + do { /* Get trailing bytes */ + b = (BYTE)*p++; + if ((b & 0xC0) != 0x80) return 0xFFFFFFFF; /* Wrong sequence? */ + uc = uc << 6 | (b & 0x3F); + } while (--nf != 0); + if (uc < 0x80 || IsSurrogate(uc) || uc >= 0x110000) return 0xFFFFFFFF; /* Wrong code? */ + if (uc >= 0x010000) uc = 0xD800DC00 | ((uc - 0x10000) << 6 & 0x3FF0000) | (uc & 0x3FF); /* Make a surrogate pair if needed */ + } + +#elif FF_LFN_UNICODE == 3 /* UTF-32 input */ + uc = (TCHAR)*p++; /* Get a unit */ + if (uc >= 0x110000 || IsSurrogate(uc)) return 0xFFFFFFFF; /* Wrong code? */ + if (uc >= 0x010000) uc = 0xD800DC00 | ((uc - 0x10000) << 6 & 0x3FF0000) | (uc & 0x3FF); /* Make a surrogate pair if needed */ + +#else /* ANSI/OEM input */ + BYTE b; + WCHAR wc; + + wc = (BYTE)*p++; /* Get a byte */ + if (dbc_1st((BYTE)wc)) { /* Is it a DBC 1st byte? */ + b = (BYTE)*p++; /* Get 2nd byte */ + if (!dbc_2nd(b)) return 0xFFFFFFFF; /* Invalid code? */ + wc = (wc << 8) + b; /* Make a DBC */ + } + if (wc != 0) { + wc = ff_oem2uni(wc, CODEPAGE); /* ANSI/OEM ==> Unicode */ + if (wc == 0) return 0xFFFFFFFF; /* Invalid code? */ + } + uc = wc; + +#endif + *str = p; /* Next read pointer */ + return uc; +} + + +/* Store a Unicode char in defined API encoding */ +static UINT put_utf ( /* Returns number of encoding units written (0:buffer overflow or wrong encoding) */ + DWORD chr, /* UTF-16 encoded character (Surrogate pair if >=0x10000) */ + TCHAR* buf, /* Output buffer */ + UINT szb /* Size of the buffer */ +) +{ +#if FF_LFN_UNICODE == 1 /* UTF-16 output */ + WCHAR hs, wc; + + hs = (WCHAR)(chr >> 16); + wc = (WCHAR)chr; + if (hs == 0) { /* Single encoding unit? */ + if (szb < 1 || IsSurrogate(wc)) return 0; /* Buffer overflow or wrong code? */ + *buf = wc; + return 1; + } + if (szb < 2 || !IsSurrogateH(hs) || !IsSurrogateL(wc)) return 0; /* Buffer overflow or wrong surrogate? */ + *buf++ = hs; + *buf++ = wc; + return 2; + +#elif FF_LFN_UNICODE == 2 /* UTF-8 output */ + DWORD hc; + + if (chr < 0x80) { /* Single byte code? */ + if (szb < 1) return 0; /* Buffer overflow? */ + *buf = (TCHAR)chr; + return 1; + } + if (chr < 0x800) { /* 2-byte sequence? */ + if (szb < 2) return 0; /* Buffer overflow? */ + *buf++ = (TCHAR)(0xC0 | (chr >> 6 & 0x1F)); + *buf++ = (TCHAR)(0x80 | (chr >> 0 & 0x3F)); + return 2; + } + if (chr < 0x10000) { /* 3-byte sequence? */ + if (szb < 3 || IsSurrogate(chr)) return 0; /* Buffer overflow or wrong code? */ + *buf++ = (TCHAR)(0xE0 | (chr >> 12 & 0x0F)); + *buf++ = (TCHAR)(0x80 | (chr >> 6 & 0x3F)); + *buf++ = (TCHAR)(0x80 | (chr >> 0 & 0x3F)); + return 3; + } + /* 4-byte sequence */ + if (szb < 4) return 0; /* Buffer overflow? */ + hc = ((chr & 0xFFFF0000) - 0xD8000000) >> 6; /* Get high 10 bits */ + chr = (chr & 0xFFFF) - 0xDC00; /* Get low 10 bits */ + if (hc >= 0x100000 || chr >= 0x400) return 0; /* Wrong surrogate? */ + chr = (hc | chr) + 0x10000; + *buf++ = (TCHAR)(0xF0 | (chr >> 18 & 0x07)); + *buf++ = (TCHAR)(0x80 | (chr >> 12 & 0x3F)); + *buf++ = (TCHAR)(0x80 | (chr >> 6 & 0x3F)); + *buf++ = (TCHAR)(0x80 | (chr >> 0 & 0x3F)); + return 4; + +#elif FF_LFN_UNICODE == 3 /* UTF-32 output */ + DWORD hc; + + if (szb < 1) return 0; /* Buffer overflow? */ + if (chr >= 0x10000) { /* Out of BMP? */ + hc = ((chr & 0xFFFF0000) - 0xD8000000) >> 6; /* Get high 10 bits */ + chr = (chr & 0xFFFF) - 0xDC00; /* Get low 10 bits */ + if (hc >= 0x100000 || chr >= 0x400) return 0; /* Wrong surrogate? */ + chr = (hc | chr) + 0x10000; + } + *buf++ = (TCHAR)chr; + return 1; + +#else /* ANSI/OEM output */ + WCHAR wc; + + wc = ff_uni2oem(chr, CODEPAGE); + if (wc >= 0x100) { /* Is this a DBC? */ + if (szb < 2) return 0; + *buf++ = (char)(wc >> 8); /* Store DBC 1st byte */ + *buf++ = (TCHAR)wc; /* Store DBC 2nd byte */ + return 2; + } + if (wc == 0 || szb < 1) return 0; /* Invalid char or buffer overflow? */ + *buf++ = (TCHAR)wc; /* Store the character */ + return 1; +#endif +} +#endif /* FF_USE_LFN */ + + +#if FF_FS_REENTRANT +/*-----------------------------------------------------------------------*/ +/* Request/Release grant to access the volume */ +/*-----------------------------------------------------------------------*/ +static int lock_fs ( /* 1:Ok, 0:timeout */ + FATFS* fs /* Filesystem object */ +) +{ + return ff_req_grant(fs->sobj); +} + + +static void unlock_fs ( + FATFS* fs, /* Filesystem object */ + FRESULT res /* Result code to be returned */ +) +{ + if (fs && res != FR_NOT_ENABLED && res != FR_INVALID_DRIVE && res != FR_TIMEOUT) { + ff_rel_grant(fs->sobj); + } +} + +#endif + + + +#if FF_FS_LOCK != 0 +/*-----------------------------------------------------------------------*/ +/* File lock control functions */ +/*-----------------------------------------------------------------------*/ + +static FRESULT chk_lock ( /* Check if the file can be accessed */ + DIR* dp, /* Directory object pointing the file to be checked */ + int acc /* Desired access type (0:Read mode open, 1:Write mode open, 2:Delete or rename) */ +) +{ + UINT i, be; + + /* Search open object table for the object */ + be = 0; + for (i = 0; i < FF_FS_LOCK; i++) { + if (Files[i].fs) { /* Existing entry */ + if (Files[i].fs == dp->obj.fs && /* Check if the object matches with an open object */ + Files[i].clu == dp->obj.sclust && + Files[i].ofs == dp->dptr) break; + } else { /* Blank entry */ + be = 1; + } + } + if (i == FF_FS_LOCK) { /* The object has not been opened */ + return (!be && acc != 2) ? FR_TOO_MANY_OPEN_FILES : FR_OK; /* Is there a blank entry for new object? */ + } + + /* The object was opened. Reject any open against writing file and all write mode open */ + return (acc != 0 || Files[i].ctr == 0x100) ? FR_LOCKED : FR_OK; +} + + +static int enq_lock (void) /* Check if an entry is available for a new object */ +{ + UINT i; + + for (i = 0; i < FF_FS_LOCK && Files[i].fs; i++) ; + return (i == FF_FS_LOCK) ? 0 : 1; +} + + +static UINT inc_lock ( /* Increment object open counter and returns its index (0:Internal error) */ + DIR* dp, /* Directory object pointing the file to register or increment */ + int acc /* Desired access (0:Read, 1:Write, 2:Delete/Rename) */ +) +{ + UINT i; + + + for (i = 0; i < FF_FS_LOCK; i++) { /* Find the object */ + if (Files[i].fs == dp->obj.fs + && Files[i].clu == dp->obj.sclust + && Files[i].ofs == dp->dptr) break; + } + + if (i == FF_FS_LOCK) { /* Not opened. Register it as new. */ + for (i = 0; i < FF_FS_LOCK && Files[i].fs; i++) ; + if (i == FF_FS_LOCK) return 0; /* No free entry to register (int err) */ + Files[i].fs = dp->obj.fs; + Files[i].clu = dp->obj.sclust; + Files[i].ofs = dp->dptr; + Files[i].ctr = 0; + } + + if (acc >= 1 && Files[i].ctr) return 0; /* Access violation (int err) */ + + Files[i].ctr = acc ? 0x100 : Files[i].ctr + 1; /* Set semaphore value */ + + return i + 1; /* Index number origin from 1 */ +} + + +static FRESULT dec_lock ( /* Decrement object open counter */ + UINT i /* Semaphore index (1..) */ +) +{ + WORD n; + FRESULT res; + + + if (--i < FF_FS_LOCK) { /* Index number origin from 0 */ + n = Files[i].ctr; + if (n == 0x100) n = 0; /* If write mode open, delete the entry */ + if (n > 0) n--; /* Decrement read mode open count */ + Files[i].ctr = n; + if (n == 0) Files[i].fs = 0; /* Delete the entry if open count gets zero */ + res = FR_OK; + } else { + res = FR_INT_ERR; /* Invalid index nunber */ + } + return res; +} + + +static void clear_lock ( /* Clear lock entries of the volume */ + FATFS *fs +) +{ + UINT i; + + for (i = 0; i < FF_FS_LOCK; i++) { + if (Files[i].fs == fs) Files[i].fs = 0; + } +} + +#endif /* FF_FS_LOCK != 0 */ + + + +/*-----------------------------------------------------------------------*/ +/* Move/Flush disk access window in the filesystem object */ +/*-----------------------------------------------------------------------*/ +#if !FF_FS_READONLY +static FRESULT sync_window ( /* Returns FR_OK or FR_DISK_ERR */ + FATFS* fs /* Filesystem object */ +) +{ + FRESULT res = FR_OK; + + + if (fs->wflag) { /* Is the disk access window dirty? */ + if (disk_write(fs->pdrv, fs->win, fs->winsect, 1) == RES_OK) { /* Write it back into the volume */ + fs->wflag = 0; /* Clear window dirty flag */ + if (fs->winsect - fs->fatbase < fs->fsize) { /* Is it in the 1st FAT? */ + if (fs->n_fats == 2) disk_write(fs->pdrv, fs->win, fs->winsect + fs->fsize, 1); /* Reflect it to 2nd FAT if needed */ + } + } else { + res = FR_DISK_ERR; + } + } + return res; +} +#endif + + +static FRESULT move_window ( /* Returns FR_OK or FR_DISK_ERR */ + FATFS* fs, /* Filesystem object */ + LBA_t sect /* Sector LBA to make appearance in the fs->win[] */ +) +{ + FRESULT res = FR_OK; + + + if (sect != fs->winsect) { /* Window offset changed? */ +#if !FF_FS_READONLY + res = sync_window(fs); /* Flush the window */ +#endif + if (res == FR_OK) { /* Fill sector window with new data */ + if (disk_read(fs->pdrv, fs->win, sect, 1) != RES_OK) { + sect = (LBA_t)0 - 1; /* Invalidate window if read data is not valid */ + res = FR_DISK_ERR; + } + fs->winsect = sect; + } + } + return res; +} + + + + +#if !FF_FS_READONLY +/*-----------------------------------------------------------------------*/ +/* Synchronize filesystem and data on the storage */ +/*-----------------------------------------------------------------------*/ + +static FRESULT sync_fs ( /* Returns FR_OK or FR_DISK_ERR */ + FATFS* fs /* Filesystem object */ +) +{ + FRESULT res; + + + res = sync_window(fs); + if (res == FR_OK) { + if (fs->fs_type == FS_FAT32 && fs->fsi_flag == 1) { /* FAT32: Update FSInfo sector if needed */ + /* Create FSInfo structure */ + memset(fs->win, 0, sizeof fs->win); + st_word(fs->win + BS_55AA, 0xAA55); /* Boot signature */ + st_dword(fs->win + FSI_LeadSig, 0x41615252); /* Leading signature */ + st_dword(fs->win + FSI_StrucSig, 0x61417272); /* Structure signature */ + st_dword(fs->win + FSI_Free_Count, fs->free_clst); /* Number of free clusters */ + st_dword(fs->win + FSI_Nxt_Free, fs->last_clst); /* Last allocated culuster */ + fs->winsect = fs->volbase + 1; /* Write it into the FSInfo sector (Next to VBR) */ + disk_write(fs->pdrv, fs->win, fs->winsect, 1); + fs->fsi_flag = 0; + } + /* Make sure that no pending write process in the lower layer */ + if (disk_ioctl(fs->pdrv, CTRL_SYNC, 0) != RES_OK) res = FR_DISK_ERR; + } + + return res; +} + +#endif + + + +/*-----------------------------------------------------------------------*/ +/* Get physical sector number from cluster number */ +/*-----------------------------------------------------------------------*/ + +static LBA_t clst2sect ( /* !=0:Sector number, 0:Failed (invalid cluster#) */ + FATFS* fs, /* Filesystem object */ + DWORD clst /* Cluster# to be converted */ +) +{ + clst -= 2; /* Cluster number is origin from 2 */ + if (clst >= fs->n_fatent - 2) return 0; /* Is it invalid cluster number? */ + return fs->database + (LBA_t)fs->csize * clst; /* Start sector number of the cluster */ +} + + + + +/*-----------------------------------------------------------------------*/ +/* FAT access - Read value of an FAT entry */ +/*-----------------------------------------------------------------------*/ + +static DWORD get_fat ( /* 0xFFFFFFFF:Disk error, 1:Internal error, 2..0x7FFFFFFF:Cluster status */ + FFOBJID* obj, /* Corresponding object */ + DWORD clst /* Cluster number to get the value */ +) +{ + UINT wc, bc; + DWORD val; + FATFS *fs = obj->fs; + + + if (clst < 2 || clst >= fs->n_fatent) { /* Check if in valid range */ + val = 1; /* Internal error */ + + } else { + val = 0xFFFFFFFF; /* Default value falls on disk error */ + + switch (fs->fs_type) { + case FS_FAT12 : + bc = (UINT)clst; bc += bc / 2; + if (move_window(fs, fs->fatbase + (bc / SS(fs))) != FR_OK) break; + wc = fs->win[bc++ % SS(fs)]; /* Get 1st byte of the entry */ + if (move_window(fs, fs->fatbase + (bc / SS(fs))) != FR_OK) break; + wc |= fs->win[bc % SS(fs)] << 8; /* Merge 2nd byte of the entry */ + val = (clst & 1) ? (wc >> 4) : (wc & 0xFFF); /* Adjust bit position */ + break; + + case FS_FAT16 : + if (move_window(fs, fs->fatbase + (clst / (SS(fs) / 2))) != FR_OK) break; + val = ld_word(fs->win + clst * 2 % SS(fs)); /* Simple WORD array */ + break; + + case FS_FAT32 : + if (move_window(fs, fs->fatbase + (clst / (SS(fs) / 4))) != FR_OK) break; + val = ld_dword(fs->win + clst * 4 % SS(fs)) & 0x0FFFFFFF; /* Simple DWORD array but mask out upper 4 bits */ + break; +#if FF_FS_EXFAT + case FS_EXFAT : + if ((obj->objsize != 0 && obj->sclust != 0) || obj->stat == 0) { /* Object except root dir must have valid data length */ + DWORD cofs = clst - obj->sclust; /* Offset from start cluster */ + DWORD clen = (DWORD)((LBA_t)((obj->objsize - 1) / SS(fs)) / fs->csize); /* Number of clusters - 1 */ + + if (obj->stat == 2 && cofs <= clen) { /* Is it a contiguous chain? */ + val = (cofs == clen) ? 0x7FFFFFFF : clst + 1; /* No data on the FAT, generate the value */ + break; + } + if (obj->stat == 3 && cofs < obj->n_cont) { /* Is it in the 1st fragment? */ + val = clst + 1; /* Generate the value */ + break; + } + if (obj->stat != 2) { /* Get value from FAT if FAT chain is valid */ + if (obj->n_frag != 0) { /* Is it on the growing edge? */ + val = 0x7FFFFFFF; /* Generate EOC */ + } else { + if (move_window(fs, fs->fatbase + (clst / (SS(fs) / 4))) != FR_OK) break; + val = ld_dword(fs->win + clst * 4 % SS(fs)) & 0x7FFFFFFF; + } + break; + } + } + val = 1; /* Internal error */ + break; +#endif + default: + val = 1; /* Internal error */ + } + } + + return val; +} + + + + +#if !FF_FS_READONLY +/*-----------------------------------------------------------------------*/ +/* FAT access - Change value of an FAT entry */ +/*-----------------------------------------------------------------------*/ + +static FRESULT put_fat ( /* FR_OK(0):succeeded, !=0:error */ + FATFS* fs, /* Corresponding filesystem object */ + DWORD clst, /* FAT index number (cluster number) to be changed */ + DWORD val /* New value to be set to the entry */ +) +{ + UINT bc; + BYTE *p; + FRESULT res = FR_INT_ERR; + + + if (clst >= 2 && clst < fs->n_fatent) { /* Check if in valid range */ + switch (fs->fs_type) { + case FS_FAT12: + bc = (UINT)clst; bc += bc / 2; /* bc: byte offset of the entry */ + res = move_window(fs, fs->fatbase + (bc / SS(fs))); + if (res != FR_OK) break; + p = fs->win + bc++ % SS(fs); + *p = (clst & 1) ? ((*p & 0x0F) | ((BYTE)val << 4)) : (BYTE)val; /* Update 1st byte */ + fs->wflag = 1; + res = move_window(fs, fs->fatbase + (bc / SS(fs))); + if (res != FR_OK) break; + p = fs->win + bc % SS(fs); + *p = (clst & 1) ? (BYTE)(val >> 4) : ((*p & 0xF0) | ((BYTE)(val >> 8) & 0x0F)); /* Update 2nd byte */ + fs->wflag = 1; + break; + + case FS_FAT16: + res = move_window(fs, fs->fatbase + (clst / (SS(fs) / 2))); + if (res != FR_OK) break; + st_word(fs->win + clst * 2 % SS(fs), (WORD)val); /* Simple WORD array */ + fs->wflag = 1; + break; + + case FS_FAT32: +#if FF_FS_EXFAT + case FS_EXFAT: +#endif + res = move_window(fs, fs->fatbase + (clst / (SS(fs) / 4))); + if (res != FR_OK) break; + if (!FF_FS_EXFAT || fs->fs_type != FS_EXFAT) { + val = (val & 0x0FFFFFFF) | (ld_dword(fs->win + clst * 4 % SS(fs)) & 0xF0000000); + } + st_dword(fs->win + clst * 4 % SS(fs), val); + fs->wflag = 1; + break; + } + } + return res; +} + +#endif /* !FF_FS_READONLY */ + + + + +#if FF_FS_EXFAT && !FF_FS_READONLY +/*-----------------------------------------------------------------------*/ +/* exFAT: Accessing FAT and Allocation Bitmap */ +/*-----------------------------------------------------------------------*/ + +/*--------------------------------------*/ +/* Find a contiguous free cluster block */ +/*--------------------------------------*/ + +static DWORD find_bitmap ( /* 0:Not found, 2..:Cluster block found, 0xFFFFFFFF:Disk error */ + FATFS* fs, /* Filesystem object */ + DWORD clst, /* Cluster number to scan from */ + DWORD ncl /* Number of contiguous clusters to find (1..) */ +) +{ + BYTE bm, bv; + UINT i; + DWORD val, scl, ctr; + + + clst -= 2; /* The first bit in the bitmap corresponds to cluster #2 */ + if (clst >= fs->n_fatent - 2) clst = 0; + scl = val = clst; ctr = 0; + for (;;) { + if (move_window(fs, fs->bitbase + val / 8 / SS(fs)) != FR_OK) return 0xFFFFFFFF; + i = val / 8 % SS(fs); bm = 1 << (val % 8); + do { + do { + bv = fs->win[i] & bm; bm <<= 1; /* Get bit value */ + if (++val >= fs->n_fatent - 2) { /* Next cluster (with wrap-around) */ + val = 0; bm = 0; i = SS(fs); + } + if (bv == 0) { /* Is it a free cluster? */ + if (++ctr == ncl) return scl + 2; /* Check if run length is sufficient for required */ + } else { + scl = val; ctr = 0; /* Encountered a cluster in-use, restart to scan */ + } + if (val == clst) return 0; /* All cluster scanned? */ + } while (bm != 0); + bm = 1; + } while (++i < SS(fs)); + } +} + + +/*----------------------------------------*/ +/* Set/Clear a block of allocation bitmap */ +/*----------------------------------------*/ + +static FRESULT change_bitmap ( + FATFS* fs, /* Filesystem object */ + DWORD clst, /* Cluster number to change from */ + DWORD ncl, /* Number of clusters to be changed */ + int bv /* bit value to be set (0 or 1) */ +) +{ + BYTE bm; + UINT i; + LBA_t sect; + + + clst -= 2; /* The first bit corresponds to cluster #2 */ + sect = fs->bitbase + clst / 8 / SS(fs); /* Sector address */ + i = clst / 8 % SS(fs); /* Byte offset in the sector */ + bm = 1 << (clst % 8); /* Bit mask in the byte */ + for (;;) { + if (move_window(fs, sect++) != FR_OK) return FR_DISK_ERR; + do { + do { + if (bv == (int)((fs->win[i] & bm) != 0)) return FR_INT_ERR; /* Is the bit expected value? */ + fs->win[i] ^= bm; /* Flip the bit */ + fs->wflag = 1; + if (--ncl == 0) return FR_OK; /* All bits processed? */ + } while (bm <<= 1); /* Next bit */ + bm = 1; + } while (++i < SS(fs)); /* Next byte */ + i = 0; + } +} + + +/*---------------------------------------------*/ +/* Fill the first fragment of the FAT chain */ +/*---------------------------------------------*/ + +static FRESULT fill_first_frag ( + FFOBJID* obj /* Pointer to the corresponding object */ +) +{ + FRESULT res; + DWORD cl, n; + + + if (obj->stat == 3) { /* Has the object been changed 'fragmented' in this session? */ + for (cl = obj->sclust, n = obj->n_cont; n; cl++, n--) { /* Create cluster chain on the FAT */ + res = put_fat(obj->fs, cl, cl + 1); + if (res != FR_OK) return res; + } + obj->stat = 0; /* Change status 'FAT chain is valid' */ + } + return FR_OK; +} + + +/*---------------------------------------------*/ +/* Fill the last fragment of the FAT chain */ +/*---------------------------------------------*/ + +static FRESULT fill_last_frag ( + FFOBJID* obj, /* Pointer to the corresponding object */ + DWORD lcl, /* Last cluster of the fragment */ + DWORD term /* Value to set the last FAT entry */ +) +{ + FRESULT res; + + + while (obj->n_frag > 0) { /* Create the chain of last fragment */ + res = put_fat(obj->fs, lcl - obj->n_frag + 1, (obj->n_frag > 1) ? lcl - obj->n_frag + 2 : term); + if (res != FR_OK) return res; + obj->n_frag--; + } + return FR_OK; +} + +#endif /* FF_FS_EXFAT && !FF_FS_READONLY */ + + + +#if !FF_FS_READONLY +/*-----------------------------------------------------------------------*/ +/* FAT handling - Remove a cluster chain */ +/*-----------------------------------------------------------------------*/ + +static FRESULT remove_chain ( /* FR_OK(0):succeeded, !=0:error */ + FFOBJID* obj, /* Corresponding object */ + DWORD clst, /* Cluster to remove a chain from */ + DWORD pclst /* Previous cluster of clst (0 if entire chain) */ +) +{ + FRESULT res = FR_OK; + DWORD nxt; + FATFS *fs = obj->fs; +#if FF_FS_EXFAT || FF_USE_TRIM + DWORD scl = clst, ecl = clst; +#endif +#if FF_USE_TRIM + LBA_t rt[2]; +#endif + + if (clst < 2 || clst >= fs->n_fatent) return FR_INT_ERR; /* Check if in valid range */ + + /* Mark the previous cluster 'EOC' on the FAT if it exists */ + if (pclst != 0 && (!FF_FS_EXFAT || fs->fs_type != FS_EXFAT || obj->stat != 2)) { + res = put_fat(fs, pclst, 0xFFFFFFFF); + if (res != FR_OK) return res; + } + + /* Remove the chain */ + do { + nxt = get_fat(obj, clst); /* Get cluster status */ + if (nxt == 0) break; /* Empty cluster? */ + if (nxt == 1) return FR_INT_ERR; /* Internal error? */ + if (nxt == 0xFFFFFFFF) return FR_DISK_ERR; /* Disk error? */ + if (!FF_FS_EXFAT || fs->fs_type != FS_EXFAT) { + res = put_fat(fs, clst, 0); /* Mark the cluster 'free' on the FAT */ + if (res != FR_OK) return res; + } + if (fs->free_clst < fs->n_fatent - 2) { /* Update FSINFO */ + fs->free_clst++; + fs->fsi_flag |= 1; + } +#if FF_FS_EXFAT || FF_USE_TRIM + if (ecl + 1 == nxt) { /* Is next cluster contiguous? */ + ecl = nxt; + } else { /* End of contiguous cluster block */ +#if FF_FS_EXFAT + if (fs->fs_type == FS_EXFAT) { + res = change_bitmap(fs, scl, ecl - scl + 1, 0); /* Mark the cluster block 'free' on the bitmap */ + if (res != FR_OK) return res; + } +#endif +#if FF_USE_TRIM + rt[0] = clst2sect(fs, scl); /* Start of data area to be freed */ + rt[1] = clst2sect(fs, ecl) + fs->csize - 1; /* End of data area to be freed */ + disk_ioctl(fs->pdrv, CTRL_TRIM, rt); /* Inform storage device that the data in the block may be erased */ +#endif + scl = ecl = nxt; + } +#endif + clst = nxt; /* Next cluster */ + } while (clst < fs->n_fatent); /* Repeat while not the last link */ + +#if FF_FS_EXFAT + /* Some post processes for chain status */ + if (fs->fs_type == FS_EXFAT) { + if (pclst == 0) { /* Has the entire chain been removed? */ + obj->stat = 0; /* Change the chain status 'initial' */ + } else { + if (obj->stat == 0) { /* Is it a fragmented chain from the beginning of this session? */ + clst = obj->sclust; /* Follow the chain to check if it gets contiguous */ + while (clst != pclst) { + nxt = get_fat(obj, clst); + if (nxt < 2) return FR_INT_ERR; + if (nxt == 0xFFFFFFFF) return FR_DISK_ERR; + if (nxt != clst + 1) break; /* Not contiguous? */ + clst++; + } + if (clst == pclst) { /* Has the chain got contiguous again? */ + obj->stat = 2; /* Change the chain status 'contiguous' */ + } + } else { + if (obj->stat == 3 && pclst >= obj->sclust && pclst <= obj->sclust + obj->n_cont) { /* Was the chain fragmented in this session and got contiguous again? */ + obj->stat = 2; /* Change the chain status 'contiguous' */ + } + } + } + } +#endif + return FR_OK; +} + + + + +/*-----------------------------------------------------------------------*/ +/* FAT handling - Stretch a chain or Create a new chain */ +/*-----------------------------------------------------------------------*/ + +static DWORD create_chain ( /* 0:No free cluster, 1:Internal error, 0xFFFFFFFF:Disk error, >=2:New cluster# */ + FFOBJID* obj, /* Corresponding object */ + DWORD clst /* Cluster# to stretch, 0:Create a new chain */ +) +{ + DWORD cs, ncl, scl; + FRESULT res; + FATFS *fs = obj->fs; + + + if (clst == 0) { /* Create a new chain */ + scl = fs->last_clst; /* Suggested cluster to start to find */ + if (scl == 0 || scl >= fs->n_fatent) scl = 1; + } + else { /* Stretch a chain */ + cs = get_fat(obj, clst); /* Check the cluster status */ + if (cs < 2) return 1; /* Test for insanity */ + if (cs == 0xFFFFFFFF) return cs; /* Test for disk error */ + if (cs < fs->n_fatent) return cs; /* It is already followed by next cluster */ + scl = clst; /* Cluster to start to find */ + } + if (fs->free_clst == 0) return 0; /* No free cluster */ + +#if FF_FS_EXFAT + if (fs->fs_type == FS_EXFAT) { /* On the exFAT volume */ + ncl = find_bitmap(fs, scl, 1); /* Find a free cluster */ + if (ncl == 0 || ncl == 0xFFFFFFFF) return ncl; /* No free cluster or hard error? */ + res = change_bitmap(fs, ncl, 1, 1); /* Mark the cluster 'in use' */ + if (res == FR_INT_ERR) return 1; + if (res == FR_DISK_ERR) return 0xFFFFFFFF; + if (clst == 0) { /* Is it a new chain? */ + obj->stat = 2; /* Set status 'contiguous' */ + } else { /* It is a stretched chain */ + if (obj->stat == 2 && ncl != scl + 1) { /* Is the chain got fragmented? */ + obj->n_cont = scl - obj->sclust; /* Set size of the contiguous part */ + obj->stat = 3; /* Change status 'just fragmented' */ + } + } + if (obj->stat != 2) { /* Is the file non-contiguous? */ + if (ncl == clst + 1) { /* Is the cluster next to previous one? */ + obj->n_frag = obj->n_frag ? obj->n_frag + 1 : 2; /* Increment size of last framgent */ + } else { /* New fragment */ + if (obj->n_frag == 0) obj->n_frag = 1; + res = fill_last_frag(obj, clst, ncl); /* Fill last fragment on the FAT and link it to new one */ + if (res == FR_OK) obj->n_frag = 1; + } + } + } else +#endif + { /* On the FAT/FAT32 volume */ + ncl = 0; + if (scl == clst) { /* Stretching an existing chain? */ + ncl = scl + 1; /* Test if next cluster is free */ + if (ncl >= fs->n_fatent) ncl = 2; + cs = get_fat(obj, ncl); /* Get next cluster status */ + if (cs == 1 || cs == 0xFFFFFFFF) return cs; /* Test for error */ + if (cs != 0) { /* Not free? */ + cs = fs->last_clst; /* Start at suggested cluster if it is valid */ + if (cs >= 2 && cs < fs->n_fatent) scl = cs; + ncl = 0; + } + } + if (ncl == 0) { /* The new cluster cannot be contiguous and find another fragment */ + ncl = scl; /* Start cluster */ + for (;;) { + ncl++; /* Next cluster */ + if (ncl >= fs->n_fatent) { /* Check wrap-around */ + ncl = 2; + if (ncl > scl) return 0; /* No free cluster found? */ + } + cs = get_fat(obj, ncl); /* Get the cluster status */ + if (cs == 0) break; /* Found a free cluster? */ + if (cs == 1 || cs == 0xFFFFFFFF) return cs; /* Test for error */ + if (ncl == scl) return 0; /* No free cluster found? */ + } + } + res = put_fat(fs, ncl, 0xFFFFFFFF); /* Mark the new cluster 'EOC' */ + if (res == FR_OK && clst != 0) { + res = put_fat(fs, clst, ncl); /* Link it from the previous one if needed */ + } + } + + if (res == FR_OK) { /* Update FSINFO if function succeeded. */ + fs->last_clst = ncl; + if (fs->free_clst <= fs->n_fatent - 2) fs->free_clst--; + fs->fsi_flag |= 1; + } else { + ncl = (res == FR_DISK_ERR) ? 0xFFFFFFFF : 1; /* Failed. Generate error status */ + } + + return ncl; /* Return new cluster number or error status */ +} + +#endif /* !FF_FS_READONLY */ + + + + +#if FF_USE_FASTSEEK +/*-----------------------------------------------------------------------*/ +/* FAT handling - Convert offset into cluster with link map table */ +/*-----------------------------------------------------------------------*/ + +static DWORD clmt_clust ( /* <2:Error, >=2:Cluster number */ + FIL* fp, /* Pointer to the file object */ + FSIZE_t ofs /* File offset to be converted to cluster# */ +) +{ + DWORD cl, ncl, *tbl; + FATFS *fs = fp->obj.fs; + + + tbl = fp->cltbl + 1; /* Top of CLMT */ + cl = (DWORD)(ofs / SS(fs) / fs->csize); /* Cluster order from top of the file */ + for (;;) { + ncl = *tbl++; /* Number of cluters in the fragment */ + if (ncl == 0) return 0; /* End of table? (error) */ + if (cl < ncl) break; /* In this fragment? */ + cl -= ncl; tbl++; /* Next fragment */ + } + return cl + *tbl; /* Return the cluster number */ +} + +#endif /* FF_USE_FASTSEEK */ + + + + +/*-----------------------------------------------------------------------*/ +/* Directory handling - Fill a cluster with zeros */ +/*-----------------------------------------------------------------------*/ + +#if !FF_FS_READONLY +static FRESULT dir_clear ( /* Returns FR_OK or FR_DISK_ERR */ + FATFS *fs, /* Filesystem object */ + DWORD clst /* Directory table to clear */ +) +{ + LBA_t sect; + UINT n, szb; + BYTE *ibuf; + + + if (sync_window(fs) != FR_OK) return FR_DISK_ERR; /* Flush disk access window */ + sect = clst2sect(fs, clst); /* Top of the cluster */ + fs->winsect = sect; /* Set window to top of the cluster */ + memset(fs->win, 0, sizeof fs->win); /* Clear window buffer */ +#if FF_USE_LFN == 3 /* Quick table clear by using multi-secter write */ + /* Allocate a temporary buffer */ + for (szb = ((DWORD)fs->csize * SS(fs) >= MAX_MALLOC) ? MAX_MALLOC : fs->csize * SS(fs), ibuf = 0; szb > SS(fs) && (ibuf = ff_memalloc(szb)) == 0; szb /= 2) ; + if (szb > SS(fs)) { /* Buffer allocated? */ + memset(ibuf, 0, szb); + szb /= SS(fs); /* Bytes -> Sectors */ + for (n = 0; n < fs->csize && disk_write(fs->pdrv, ibuf, sect + n, szb) == RES_OK; n += szb) ; /* Fill the cluster with 0 */ + ff_memfree(ibuf); + } else +#endif + { + ibuf = fs->win; szb = 1; /* Use window buffer (many single-sector writes may take a time) */ + for (n = 0; n < fs->csize && disk_write(fs->pdrv, ibuf, sect + n, szb) == RES_OK; n += szb) ; /* Fill the cluster with 0 */ + } + return (n == fs->csize) ? FR_OK : FR_DISK_ERR; +} +#endif /* !FF_FS_READONLY */ + + + + +/*-----------------------------------------------------------------------*/ +/* Directory handling - Set directory index */ +/*-----------------------------------------------------------------------*/ + +static FRESULT dir_sdi ( /* FR_OK(0):succeeded, !=0:error */ + DIR* dp, /* Pointer to directory object */ + DWORD ofs /* Offset of directory table */ +) +{ + DWORD csz, clst; + FATFS *fs = dp->obj.fs; + + + if (ofs >= (DWORD)((FF_FS_EXFAT && fs->fs_type == FS_EXFAT) ? MAX_DIR_EX : MAX_DIR) || ofs % SZDIRE) { /* Check range of offset and alignment */ + return FR_INT_ERR; + } + dp->dptr = ofs; /* Set current offset */ + clst = dp->obj.sclust; /* Table start cluster (0:root) */ + if (clst == 0 && fs->fs_type >= FS_FAT32) { /* Replace cluster# 0 with root cluster# */ + clst = (DWORD)fs->dirbase; + if (FF_FS_EXFAT) dp->obj.stat = 0; /* exFAT: Root dir has an FAT chain */ + } + + if (clst == 0) { /* Static table (root-directory on the FAT volume) */ + if (ofs / SZDIRE >= fs->n_rootdir) return FR_INT_ERR; /* Is index out of range? */ + dp->sect = fs->dirbase; + + } else { /* Dynamic table (sub-directory or root-directory on the FAT32/exFAT volume) */ + csz = (DWORD)fs->csize * SS(fs); /* Bytes per cluster */ + while (ofs >= csz) { /* Follow cluster chain */ + clst = get_fat(&dp->obj, clst); /* Get next cluster */ + if (clst == 0xFFFFFFFF) return FR_DISK_ERR; /* Disk error */ + if (clst < 2 || clst >= fs->n_fatent) return FR_INT_ERR; /* Reached to end of table or internal error */ + ofs -= csz; + } + dp->sect = clst2sect(fs, clst); + } + dp->clust = clst; /* Current cluster# */ + if (dp->sect == 0) return FR_INT_ERR; + dp->sect += ofs / SS(fs); /* Sector# of the directory entry */ + dp->dir = fs->win + (ofs % SS(fs)); /* Pointer to the entry in the win[] */ + + return FR_OK; +} + + + + +/*-----------------------------------------------------------------------*/ +/* Directory handling - Move directory table index next */ +/*-----------------------------------------------------------------------*/ + +static FRESULT dir_next ( /* FR_OK(0):succeeded, FR_NO_FILE:End of table, FR_DENIED:Could not stretch */ + DIR* dp, /* Pointer to the directory object */ + int stretch /* 0: Do not stretch table, 1: Stretch table if needed */ +) +{ + DWORD ofs, clst; + FATFS *fs = dp->obj.fs; + + + ofs = dp->dptr + SZDIRE; /* Next entry */ + if (ofs >= (DWORD)((FF_FS_EXFAT && fs->fs_type == FS_EXFAT) ? MAX_DIR_EX : MAX_DIR)) dp->sect = 0; /* Disable it if the offset reached the max value */ + if (dp->sect == 0) return FR_NO_FILE; /* Report EOT if it has been disabled */ + + if (ofs % SS(fs) == 0) { /* Sector changed? */ + dp->sect++; /* Next sector */ + + if (dp->clust == 0) { /* Static table */ + if (ofs / SZDIRE >= fs->n_rootdir) { /* Report EOT if it reached end of static table */ + dp->sect = 0; return FR_NO_FILE; + } + } + else { /* Dynamic table */ + if ((ofs / SS(fs) & (fs->csize - 1)) == 0) { /* Cluster changed? */ + clst = get_fat(&dp->obj, dp->clust); /* Get next cluster */ + if (clst <= 1) return FR_INT_ERR; /* Internal error */ + if (clst == 0xFFFFFFFF) return FR_DISK_ERR; /* Disk error */ + if (clst >= fs->n_fatent) { /* It reached end of dynamic table */ +#if !FF_FS_READONLY + if (!stretch) { /* If no stretch, report EOT */ + dp->sect = 0; return FR_NO_FILE; + } + clst = create_chain(&dp->obj, dp->clust); /* Allocate a cluster */ + if (clst == 0) return FR_DENIED; /* No free cluster */ + if (clst == 1) return FR_INT_ERR; /* Internal error */ + if (clst == 0xFFFFFFFF) return FR_DISK_ERR; /* Disk error */ + if (dir_clear(fs, clst) != FR_OK) return FR_DISK_ERR; /* Clean up the stretched table */ + if (FF_FS_EXFAT) dp->obj.stat |= 4; /* exFAT: The directory has been stretched */ +#else + if (!stretch) dp->sect = 0; /* (this line is to suppress compiler warning) */ + dp->sect = 0; return FR_NO_FILE; /* Report EOT */ +#endif + } + dp->clust = clst; /* Initialize data for new cluster */ + dp->sect = clst2sect(fs, clst); + } + } + } + dp->dptr = ofs; /* Current entry */ + dp->dir = fs->win + ofs % SS(fs); /* Pointer to the entry in the win[] */ + + return FR_OK; +} + + + + +#if !FF_FS_READONLY +/*-----------------------------------------------------------------------*/ +/* Directory handling - Reserve a block of directory entries */ +/*-----------------------------------------------------------------------*/ + +static FRESULT dir_alloc ( /* FR_OK(0):succeeded, !=0:error */ + DIR* dp, /* Pointer to the directory object */ + UINT n_ent /* Number of contiguous entries to allocate */ +) +{ + FRESULT res; + UINT n; + FATFS *fs = dp->obj.fs; + + + res = dir_sdi(dp, 0); + if (res == FR_OK) { + n = 0; + do { + res = move_window(fs, dp->sect); + if (res != FR_OK) break; +#if FF_FS_EXFAT + if ((fs->fs_type == FS_EXFAT) ? (int)((dp->dir[XDIR_Type] & 0x80) == 0) : (int)(dp->dir[DIR_Name] == DDEM || dp->dir[DIR_Name] == 0)) { /* Is the entry free? */ +#else + if (dp->dir[DIR_Name] == DDEM || dp->dir[DIR_Name] == 0) { /* Is the entry free? */ +#endif + if (++n == n_ent) break; /* Is a block of contiguous free entries found? */ + } else { + n = 0; /* Not a free entry, restart to search */ + } + res = dir_next(dp, 1); /* Next entry with table stretch enabled */ + } while (res == FR_OK); + } + + if (res == FR_NO_FILE) res = FR_DENIED; /* No directory entry to allocate */ + return res; +} + +#endif /* !FF_FS_READONLY */ + + + + +/*-----------------------------------------------------------------------*/ +/* FAT: Directory handling - Load/Store start cluster number */ +/*-----------------------------------------------------------------------*/ + +static DWORD ld_clust ( /* Returns the top cluster value of the SFN entry */ + FATFS* fs, /* Pointer to the fs object */ + const BYTE* dir /* Pointer to the key entry */ +) +{ + DWORD cl; + + cl = ld_word(dir + DIR_FstClusLO); + if (fs->fs_type == FS_FAT32) { + cl |= (DWORD)ld_word(dir + DIR_FstClusHI) << 16; + } + + return cl; +} + + +#if !FF_FS_READONLY +static void st_clust ( + FATFS* fs, /* Pointer to the fs object */ + BYTE* dir, /* Pointer to the key entry */ + DWORD cl /* Value to be set */ +) +{ + st_word(dir + DIR_FstClusLO, (WORD)cl); + if (fs->fs_type == FS_FAT32) { + st_word(dir + DIR_FstClusHI, (WORD)(cl >> 16)); + } +} +#endif + + + +#if FF_USE_LFN +/*--------------------------------------------------------*/ +/* FAT-LFN: Compare a part of file name with an LFN entry */ +/*--------------------------------------------------------*/ + +static int cmp_lfn ( /* 1:matched, 0:not matched */ + const WCHAR* lfnbuf, /* Pointer to the LFN working buffer to be compared */ + BYTE* dir /* Pointer to the directory entry containing the part of LFN */ +) +{ + UINT i, s; + WCHAR wc, uc; + + + if (ld_word(dir + LDIR_FstClusLO) != 0) return 0; /* Check LDIR_FstClusLO */ + + i = ((dir[LDIR_Ord] & 0x3F) - 1) * 13; /* Offset in the LFN buffer */ + + for (wc = 1, s = 0; s < 13; s++) { /* Process all characters in the entry */ + uc = ld_word(dir + LfnOfs[s]); /* Pick an LFN character */ + if (wc != 0) { + if (i >= FF_MAX_LFN + 1 || ff_wtoupper(uc) != ff_wtoupper(lfnbuf[i++])) { /* Compare it */ + return 0; /* Not matched */ + } + wc = uc; + } else { + if (uc != 0xFFFF) return 0; /* Check filler */ + } + } + + if ((dir[LDIR_Ord] & LLEF) && wc && lfnbuf[i]) return 0; /* Last segment matched but different length */ + + return 1; /* The part of LFN matched */ +} + + +#if FF_FS_MINIMIZE <= 1 || FF_FS_RPATH >= 2 || FF_USE_LABEL || FF_FS_EXFAT +/*-----------------------------------------------------*/ +/* FAT-LFN: Pick a part of file name from an LFN entry */ +/*-----------------------------------------------------*/ + +static int pick_lfn ( /* 1:succeeded, 0:buffer overflow or invalid LFN entry */ + WCHAR* lfnbuf, /* Pointer to the LFN working buffer */ + BYTE* dir /* Pointer to the LFN entry */ +) +{ + UINT i, s; + WCHAR wc, uc; + + + if (ld_word(dir + LDIR_FstClusLO) != 0) return 0; /* Check LDIR_FstClusLO is 0 */ + + i = ((dir[LDIR_Ord] & ~LLEF) - 1) * 13; /* Offset in the LFN buffer */ + + for (wc = 1, s = 0; s < 13; s++) { /* Process all characters in the entry */ + uc = ld_word(dir + LfnOfs[s]); /* Pick an LFN character */ + if (wc != 0) { + if (i >= FF_MAX_LFN + 1) return 0; /* Buffer overflow? */ + lfnbuf[i++] = wc = uc; /* Store it */ + } else { + if (uc != 0xFFFF) return 0; /* Check filler */ + } + } + + if (dir[LDIR_Ord] & LLEF && wc != 0) { /* Put terminator if it is the last LFN part and not terminated */ + if (i >= FF_MAX_LFN + 1) return 0; /* Buffer overflow? */ + lfnbuf[i] = 0; + } + + return 1; /* The part of LFN is valid */ +} +#endif + + +#if !FF_FS_READONLY +/*-----------------------------------------*/ +/* FAT-LFN: Create an entry of LFN entries */ +/*-----------------------------------------*/ + +static void put_lfn ( + const WCHAR* lfn, /* Pointer to the LFN */ + BYTE* dir, /* Pointer to the LFN entry to be created */ + BYTE ord, /* LFN order (1-20) */ + BYTE sum /* Checksum of the corresponding SFN */ +) +{ + UINT i, s; + WCHAR wc; + + + dir[LDIR_Chksum] = sum; /* Set checksum */ + dir[LDIR_Attr] = AM_LFN; /* Set attribute. LFN entry */ + dir[LDIR_Type] = 0; + st_word(dir + LDIR_FstClusLO, 0); + + i = (ord - 1) * 13; /* Get offset in the LFN working buffer */ + s = wc = 0; + do { + if (wc != 0xFFFF) wc = lfn[i++]; /* Get an effective character */ + st_word(dir + LfnOfs[s], wc); /* Put it */ + if (wc == 0) wc = 0xFFFF; /* Padding characters for following items */ + } while (++s < 13); + if (wc == 0xFFFF || !lfn[i]) ord |= LLEF; /* Last LFN part is the start of LFN sequence */ + dir[LDIR_Ord] = ord; /* Set the LFN order */ +} + +#endif /* !FF_FS_READONLY */ +#endif /* FF_USE_LFN */ + + + +#if FF_USE_LFN && !FF_FS_READONLY +/*-----------------------------------------------------------------------*/ +/* FAT-LFN: Create a Numbered SFN */ +/*-----------------------------------------------------------------------*/ + +static void gen_numname ( + BYTE* dst, /* Pointer to the buffer to store numbered SFN */ + const BYTE* src, /* Pointer to SFN in directory form */ + const WCHAR* lfn, /* Pointer to LFN */ + UINT seq /* Sequence number */ +) +{ + BYTE ns[8], c; + UINT i, j; + WCHAR wc; + DWORD sreg; + + + memcpy(dst, src, 11); /* Prepare the SFN to be modified */ + + if (seq > 5) { /* In case of many collisions, generate a hash number instead of sequential number */ + sreg = seq; + while (*lfn) { /* Create a CRC as hash value */ + wc = *lfn++; + for (i = 0; i < 16; i++) { + sreg = (sreg << 1) + (wc & 1); + wc >>= 1; + if (sreg & 0x10000) sreg ^= 0x11021; + } + } + seq = (UINT)sreg; + } + + /* Make suffix (~ + hexdecimal) */ + i = 7; + do { + c = (BYTE)((seq % 16) + '0'); seq /= 16; + if (c > '9') c += 7; + ns[i--] = c; + } while (i && seq); + ns[i] = '~'; + + /* Append the suffix to the SFN body */ + for (j = 0; j < i && dst[j] != ' '; j++) { /* Find the offset to append */ + if (dbc_1st(dst[j])) { /* To avoid DBC break up */ + if (j == i - 1) break; + j++; + } + } + do { /* Append the suffix */ + dst[j++] = (i < 8) ? ns[i++] : ' '; + } while (j < 8); +} +#endif /* FF_USE_LFN && !FF_FS_READONLY */ + + + +#if FF_USE_LFN +/*-----------------------------------------------------------------------*/ +/* FAT-LFN: Calculate checksum of an SFN entry */ +/*-----------------------------------------------------------------------*/ + +static BYTE sum_sfn ( + const BYTE* dir /* Pointer to the SFN entry */ +) +{ + BYTE sum = 0; + UINT n = 11; + + do { + sum = (sum >> 1) + (sum << 7) + *dir++; + } while (--n); + return sum; +} + +#endif /* FF_USE_LFN */ + + + +#if FF_FS_EXFAT +/*-----------------------------------------------------------------------*/ +/* exFAT: Checksum */ +/*-----------------------------------------------------------------------*/ + +static WORD xdir_sum ( /* Get checksum of the directoly entry block */ + const BYTE* dir /* Directory entry block to be calculated */ +) +{ + UINT i, szblk; + WORD sum; + + + szblk = (dir[XDIR_NumSec] + 1) * SZDIRE; /* Number of bytes of the entry block */ + for (i = sum = 0; i < szblk; i++) { + if (i == XDIR_SetSum) { /* Skip 2-byte sum field */ + i++; + } else { + sum = ((sum & 1) ? 0x8000 : 0) + (sum >> 1) + dir[i]; + } + } + return sum; +} + + + +static WORD xname_sum ( /* Get check sum (to be used as hash) of the file name */ + const WCHAR* name /* File name to be calculated */ +) +{ + WCHAR chr; + WORD sum = 0; + + + while ((chr = *name++) != 0) { + chr = (WCHAR)ff_wtoupper(chr); /* File name needs to be up-case converted */ + sum = ((sum & 1) ? 0x8000 : 0) + (sum >> 1) + (chr & 0xFF); + sum = ((sum & 1) ? 0x8000 : 0) + (sum >> 1) + (chr >> 8); + } + return sum; +} + + +#if !FF_FS_READONLY && FF_USE_MKFS +static DWORD xsum32 ( /* Returns 32-bit checksum */ + BYTE dat, /* Byte to be calculated (byte-by-byte processing) */ + DWORD sum /* Previous sum value */ +) +{ + sum = ((sum & 1) ? 0x80000000 : 0) + (sum >> 1) + dat; + return sum; +} +#endif + + + +/*-----------------------------------*/ +/* exFAT: Get a directry entry block */ +/*-----------------------------------*/ + +static FRESULT load_xdir ( /* FR_INT_ERR: invalid entry block */ + DIR* dp /* Reading direcotry object pointing top of the entry block to load */ +) +{ + FRESULT res; + UINT i, sz_ent; + BYTE *dirb = dp->obj.fs->dirbuf; /* Pointer to the on-memory direcotry entry block 85+C0+C1s */ + + + /* Load file directory entry */ + res = move_window(dp->obj.fs, dp->sect); + if (res != FR_OK) return res; + if (dp->dir[XDIR_Type] != ET_FILEDIR) return FR_INT_ERR; /* Invalid order */ + memcpy(dirb + 0 * SZDIRE, dp->dir, SZDIRE); + sz_ent = (dirb[XDIR_NumSec] + 1) * SZDIRE; + if (sz_ent < 3 * SZDIRE || sz_ent > 19 * SZDIRE) return FR_INT_ERR; + + /* Load stream extension entry */ + res = dir_next(dp, 0); + if (res == FR_NO_FILE) res = FR_INT_ERR; /* It cannot be */ + if (res != FR_OK) return res; + res = move_window(dp->obj.fs, dp->sect); + if (res != FR_OK) return res; + if (dp->dir[XDIR_Type] != ET_STREAM) return FR_INT_ERR; /* Invalid order */ + memcpy(dirb + 1 * SZDIRE, dp->dir, SZDIRE); + if (MAXDIRB(dirb[XDIR_NumName]) > sz_ent) return FR_INT_ERR; + + /* Load file name entries */ + i = 2 * SZDIRE; /* Name offset to load */ + do { + res = dir_next(dp, 0); + if (res == FR_NO_FILE) res = FR_INT_ERR; /* It cannot be */ + if (res != FR_OK) return res; + res = move_window(dp->obj.fs, dp->sect); + if (res != FR_OK) return res; + if (dp->dir[XDIR_Type] != ET_FILENAME) return FR_INT_ERR; /* Invalid order */ + if (i < MAXDIRB(FF_MAX_LFN)) memcpy(dirb + i, dp->dir, SZDIRE); + } while ((i += SZDIRE) < sz_ent); + + /* Sanity check (do it for only accessible object) */ + if (i <= MAXDIRB(FF_MAX_LFN)) { + if (xdir_sum(dirb) != ld_word(dirb + XDIR_SetSum)) return FR_INT_ERR; + } + return FR_OK; +} + + +/*------------------------------------------------------------------*/ +/* exFAT: Initialize object allocation info with loaded entry block */ +/*------------------------------------------------------------------*/ + +static void init_alloc_info ( + FATFS* fs, /* Filesystem object */ + FFOBJID* obj /* Object allocation information to be initialized */ +) +{ + obj->sclust = ld_dword(fs->dirbuf + XDIR_FstClus); /* Start cluster */ + obj->objsize = ld_qword(fs->dirbuf + XDIR_FileSize); /* Size */ + obj->stat = fs->dirbuf[XDIR_GenFlags] & 2; /* Allocation status */ + obj->n_frag = 0; /* No last fragment info */ +} + + + +#if !FF_FS_READONLY || FF_FS_RPATH != 0 +/*------------------------------------------------*/ +/* exFAT: Load the object's directory entry block */ +/*------------------------------------------------*/ + +static FRESULT load_obj_xdir ( + DIR* dp, /* Blank directory object to be used to access containing direcotry */ + const FFOBJID* obj /* Object with its containing directory information */ +) +{ + FRESULT res; + + /* Open object containing directory */ + dp->obj.fs = obj->fs; + dp->obj.sclust = obj->c_scl; + dp->obj.stat = (BYTE)obj->c_size; + dp->obj.objsize = obj->c_size & 0xFFFFFF00; + dp->obj.n_frag = 0; + dp->blk_ofs = obj->c_ofs; + + res = dir_sdi(dp, dp->blk_ofs); /* Goto object's entry block */ + if (res == FR_OK) { + res = load_xdir(dp); /* Load the object's entry block */ + } + return res; +} +#endif + + +#if !FF_FS_READONLY +/*----------------------------------------*/ +/* exFAT: Store the directory entry block */ +/*----------------------------------------*/ + +static FRESULT store_xdir ( + DIR* dp /* Pointer to the direcotry object */ +) +{ + FRESULT res; + UINT nent; + BYTE *dirb = dp->obj.fs->dirbuf; /* Pointer to the direcotry entry block 85+C0+C1s */ + + /* Create set sum */ + st_word(dirb + XDIR_SetSum, xdir_sum(dirb)); + nent = dirb[XDIR_NumSec] + 1; + + /* Store the direcotry entry block to the directory */ + res = dir_sdi(dp, dp->blk_ofs); + while (res == FR_OK) { + res = move_window(dp->obj.fs, dp->sect); + if (res != FR_OK) break; + memcpy(dp->dir, dirb, SZDIRE); + dp->obj.fs->wflag = 1; + if (--nent == 0) break; + dirb += SZDIRE; + res = dir_next(dp, 0); + } + return (res == FR_OK || res == FR_DISK_ERR) ? res : FR_INT_ERR; +} + + + +/*-------------------------------------------*/ +/* exFAT: Create a new directory enrty block */ +/*-------------------------------------------*/ + +static void create_xdir ( + BYTE* dirb, /* Pointer to the direcotry entry block buffer */ + const WCHAR* lfn /* Pointer to the object name */ +) +{ + UINT i; + BYTE nc1, nlen; + WCHAR wc; + + + /* Create file-directory and stream-extension entry */ + memset(dirb, 0, 2 * SZDIRE); + dirb[0 * SZDIRE + XDIR_Type] = ET_FILEDIR; + dirb[1 * SZDIRE + XDIR_Type] = ET_STREAM; + + /* Create file-name entries */ + i = SZDIRE * 2; /* Top of file_name entries */ + nlen = nc1 = 0; wc = 1; + do { + dirb[i++] = ET_FILENAME; dirb[i++] = 0; + do { /* Fill name field */ + if (wc != 0 && (wc = lfn[nlen]) != 0) nlen++; /* Get a character if exist */ + st_word(dirb + i, wc); /* Store it */ + i += 2; + } while (i % SZDIRE != 0); + nc1++; + } while (lfn[nlen]); /* Fill next entry if any char follows */ + + dirb[XDIR_NumName] = nlen; /* Set name length */ + dirb[XDIR_NumSec] = 1 + nc1; /* Set secondary count (C0 + C1s) */ + st_word(dirb + XDIR_NameHash, xname_sum(lfn)); /* Set name hash */ +} + +#endif /* !FF_FS_READONLY */ +#endif /* FF_FS_EXFAT */ + + + +#if FF_FS_MINIMIZE <= 1 || FF_FS_RPATH >= 2 || FF_USE_LABEL || FF_FS_EXFAT +/*-----------------------------------------------------------------------*/ +/* Read an object from the directory */ +/*-----------------------------------------------------------------------*/ + +#define DIR_READ_FILE(dp) dir_read(dp, 0) +#define DIR_READ_LABEL(dp) dir_read(dp, 1) + +static FRESULT dir_read ( + DIR* dp, /* Pointer to the directory object */ + int vol /* Filtered by 0:file/directory or 1:volume label */ +) +{ + FRESULT res = FR_NO_FILE; + FATFS *fs = dp->obj.fs; + BYTE attr, b; +#if FF_USE_LFN + BYTE ord = 0xFF, sum = 0xFF; +#endif + + while (dp->sect) { + res = move_window(fs, dp->sect); + if (res != FR_OK) break; + b = dp->dir[DIR_Name]; /* Test for the entry type */ + if (b == 0) { + res = FR_NO_FILE; break; /* Reached to end of the directory */ + } +#if FF_FS_EXFAT + if (fs->fs_type == FS_EXFAT) { /* On the exFAT volume */ + if (FF_USE_LABEL && vol) { + if (b == ET_VLABEL) break; /* Volume label entry? */ + } else { + if (b == ET_FILEDIR) { /* Start of the file entry block? */ + dp->blk_ofs = dp->dptr; /* Get location of the block */ + res = load_xdir(dp); /* Load the entry block */ + if (res == FR_OK) { + dp->obj.attr = fs->dirbuf[XDIR_Attr] & AM_MASK; /* Get attribute */ + } + break; + } + } + } else +#endif + { /* On the FAT/FAT32 volume */ + dp->obj.attr = attr = dp->dir[DIR_Attr] & AM_MASK; /* Get attribute */ +#if FF_USE_LFN /* LFN configuration */ + if (b == DDEM || b == '.' || (int)((attr & ~AM_ARC) == AM_VOL) != vol) { /* An entry without valid data */ + ord = 0xFF; + } else { + if (attr == AM_LFN) { /* An LFN entry is found */ + if (b & LLEF) { /* Is it start of an LFN sequence? */ + sum = dp->dir[LDIR_Chksum]; + b &= (BYTE)~LLEF; ord = b; + dp->blk_ofs = dp->dptr; + } + /* Check LFN validity and capture it */ + ord = (b == ord && sum == dp->dir[LDIR_Chksum] && pick_lfn(fs->lfnbuf, dp->dir)) ? ord - 1 : 0xFF; + } else { /* An SFN entry is found */ + if (ord != 0 || sum != sum_sfn(dp->dir)) { /* Is there a valid LFN? */ + dp->blk_ofs = 0xFFFFFFFF; /* It has no LFN. */ + } + break; + } + } +#else /* Non LFN configuration */ + if (b != DDEM && b != '.' && attr != AM_LFN && (int)((attr & ~AM_ARC) == AM_VOL) == vol) { /* Is it a valid entry? */ + break; + } +#endif + } + res = dir_next(dp, 0); /* Next entry */ + if (res != FR_OK) break; + } + + if (res != FR_OK) dp->sect = 0; /* Terminate the read operation on error or EOT */ + return res; +} + +#endif /* FF_FS_MINIMIZE <= 1 || FF_USE_LABEL || FF_FS_RPATH >= 2 */ + + + +/*-----------------------------------------------------------------------*/ +/* Directory handling - Find an object in the directory */ +/*-----------------------------------------------------------------------*/ + +static FRESULT dir_find ( /* FR_OK(0):succeeded, !=0:error */ + DIR* dp /* Pointer to the directory object with the file name */ +) +{ + FRESULT res; + FATFS *fs = dp->obj.fs; + BYTE c; +#if FF_USE_LFN + BYTE a, ord, sum; +#endif + + res = dir_sdi(dp, 0); /* Rewind directory object */ + if (res != FR_OK) return res; +#if FF_FS_EXFAT + if (fs->fs_type == FS_EXFAT) { /* On the exFAT volume */ + BYTE nc; + UINT di, ni; + WORD hash = xname_sum(fs->lfnbuf); /* Hash value of the name to find */ + + while ((res = DIR_READ_FILE(dp)) == FR_OK) { /* Read an item */ +#if FF_MAX_LFN < 255 + if (fs->dirbuf[XDIR_NumName] > FF_MAX_LFN) continue; /* Skip comparison if inaccessible object name */ +#endif + if (ld_word(fs->dirbuf + XDIR_NameHash) != hash) continue; /* Skip comparison if hash mismatched */ + for (nc = fs->dirbuf[XDIR_NumName], di = SZDIRE * 2, ni = 0; nc; nc--, di += 2, ni++) { /* Compare the name */ + if ((di % SZDIRE) == 0) di += 2; + if (ff_wtoupper(ld_word(fs->dirbuf + di)) != ff_wtoupper(fs->lfnbuf[ni])) break; + } + if (nc == 0 && !fs->lfnbuf[ni]) break; /* Name matched? */ + } + return res; + } +#endif + /* On the FAT/FAT32 volume */ +#if FF_USE_LFN + ord = sum = 0xFF; dp->blk_ofs = 0xFFFFFFFF; /* Reset LFN sequence */ +#endif + do { + res = move_window(fs, dp->sect); + if (res != FR_OK) break; + c = dp->dir[DIR_Name]; + if (c == 0) { res = FR_NO_FILE; break; } /* Reached to end of table */ +#if FF_USE_LFN /* LFN configuration */ + dp->obj.attr = a = dp->dir[DIR_Attr] & AM_MASK; + if (c == DDEM || ((a & AM_VOL) && a != AM_LFN)) { /* An entry without valid data */ + ord = 0xFF; dp->blk_ofs = 0xFFFFFFFF; /* Reset LFN sequence */ + } else { + if (a == AM_LFN) { /* An LFN entry is found */ + if (!(dp->fn[NSFLAG] & NS_NOLFN)) { + if (c & LLEF) { /* Is it start of LFN sequence? */ + sum = dp->dir[LDIR_Chksum]; + c &= (BYTE)~LLEF; ord = c; /* LFN start order */ + dp->blk_ofs = dp->dptr; /* Start offset of LFN */ + } + /* Check validity of the LFN entry and compare it with given name */ + ord = (c == ord && sum == dp->dir[LDIR_Chksum] && cmp_lfn(fs->lfnbuf, dp->dir)) ? ord - 1 : 0xFF; + } + } else { /* An SFN entry is found */ + if (ord == 0 && sum == sum_sfn(dp->dir)) break; /* LFN matched? */ + if (!(dp->fn[NSFLAG] & NS_LOSS) && !memcmp(dp->dir, dp->fn, 11)) break; /* SFN matched? */ + ord = 0xFF; dp->blk_ofs = 0xFFFFFFFF; /* Reset LFN sequence */ + } + } +#else /* Non LFN configuration */ + dp->obj.attr = dp->dir[DIR_Attr] & AM_MASK; + if (!(dp->dir[DIR_Attr] & AM_VOL) && !memcmp(dp->dir, dp->fn, 11)) break; /* Is it a valid entry? */ +#endif + res = dir_next(dp, 0); /* Next entry */ + } while (res == FR_OK); + + return res; +} + + + + +#if !FF_FS_READONLY +/*-----------------------------------------------------------------------*/ +/* Register an object to the directory */ +/*-----------------------------------------------------------------------*/ + +static FRESULT dir_register ( /* FR_OK:succeeded, FR_DENIED:no free entry or too many SFN collision, FR_DISK_ERR:disk error */ + DIR* dp /* Target directory with object name to be created */ +) +{ + FRESULT res; + FATFS *fs = dp->obj.fs; +#if FF_USE_LFN /* LFN configuration */ + UINT n, len, n_ent; + BYTE sn[12], sum; + + + if (dp->fn[NSFLAG] & (NS_DOT | NS_NONAME)) return FR_INVALID_NAME; /* Check name validity */ + for (len = 0; fs->lfnbuf[len]; len++) ; /* Get lfn length */ + +#if FF_FS_EXFAT + if (fs->fs_type == FS_EXFAT) { /* On the exFAT volume */ + n_ent = (len + 14) / 15 + 2; /* Number of entries to allocate (85+C0+C1s) */ + res = dir_alloc(dp, n_ent); /* Allocate directory entries */ + if (res != FR_OK) return res; + dp->blk_ofs = dp->dptr - SZDIRE * (n_ent - 1); /* Set the allocated entry block offset */ + + if (dp->obj.stat & 4) { /* Has the directory been stretched by new allocation? */ + dp->obj.stat &= ~4; + res = fill_first_frag(&dp->obj); /* Fill the first fragment on the FAT if needed */ + if (res != FR_OK) return res; + res = fill_last_frag(&dp->obj, dp->clust, 0xFFFFFFFF); /* Fill the last fragment on the FAT if needed */ + if (res != FR_OK) return res; + if (dp->obj.sclust != 0) { /* Is it a sub-directory? */ + DIR dj; + + res = load_obj_xdir(&dj, &dp->obj); /* Load the object status */ + if (res != FR_OK) return res; + dp->obj.objsize += (DWORD)fs->csize * SS(fs); /* Increase the directory size by cluster size */ + st_qword(fs->dirbuf + XDIR_FileSize, dp->obj.objsize); + st_qword(fs->dirbuf + XDIR_ValidFileSize, dp->obj.objsize); + fs->dirbuf[XDIR_GenFlags] = dp->obj.stat | 1; /* Update the allocation status */ + res = store_xdir(&dj); /* Store the object status */ + if (res != FR_OK) return res; + } + } + + create_xdir(fs->dirbuf, fs->lfnbuf); /* Create on-memory directory block to be written later */ + return FR_OK; + } +#endif + /* On the FAT/FAT32 volume */ + memcpy(sn, dp->fn, 12); + if (sn[NSFLAG] & NS_LOSS) { /* When LFN is out of 8.3 format, generate a numbered name */ + dp->fn[NSFLAG] = NS_NOLFN; /* Find only SFN */ + for (n = 1; n < 100; n++) { + gen_numname(dp->fn, sn, fs->lfnbuf, n); /* Generate a numbered name */ + res = dir_find(dp); /* Check if the name collides with existing SFN */ + if (res != FR_OK) break; + } + if (n == 100) return FR_DENIED; /* Abort if too many collisions */ + if (res != FR_NO_FILE) return res; /* Abort if the result is other than 'not collided' */ + dp->fn[NSFLAG] = sn[NSFLAG]; + } + + /* Create an SFN with/without LFNs. */ + n_ent = (sn[NSFLAG] & NS_LFN) ? (len + 12) / 13 + 1 : 1; /* Number of entries to allocate */ + res = dir_alloc(dp, n_ent); /* Allocate entries */ + if (res == FR_OK && --n_ent) { /* Set LFN entry if needed */ + res = dir_sdi(dp, dp->dptr - n_ent * SZDIRE); + if (res == FR_OK) { + sum = sum_sfn(dp->fn); /* Checksum value of the SFN tied to the LFN */ + do { /* Store LFN entries in bottom first */ + res = move_window(fs, dp->sect); + if (res != FR_OK) break; + put_lfn(fs->lfnbuf, dp->dir, (BYTE)n_ent, sum); + fs->wflag = 1; + res = dir_next(dp, 0); /* Next entry */ + } while (res == FR_OK && --n_ent); + } + } + +#else /* Non LFN configuration */ + res = dir_alloc(dp, 1); /* Allocate an entry for SFN */ + +#endif + + /* Set SFN entry */ + if (res == FR_OK) { + res = move_window(fs, dp->sect); + if (res == FR_OK) { + memset(dp->dir, 0, SZDIRE); /* Clean the entry */ + memcpy(dp->dir + DIR_Name, dp->fn, 11); /* Put SFN */ +#if FF_USE_LFN + dp->dir[DIR_NTres] = dp->fn[NSFLAG] & (NS_BODY | NS_EXT); /* Put NT flag */ +#endif + fs->wflag = 1; + } + } + + return res; +} + +#endif /* !FF_FS_READONLY */ + + + +#if !FF_FS_READONLY && FF_FS_MINIMIZE == 0 +/*-----------------------------------------------------------------------*/ +/* Remove an object from the directory */ +/*-----------------------------------------------------------------------*/ + +static FRESULT dir_remove ( /* FR_OK:Succeeded, FR_DISK_ERR:A disk error */ + DIR* dp /* Directory object pointing the entry to be removed */ +) +{ + FRESULT res; + FATFS *fs = dp->obj.fs; +#if FF_USE_LFN /* LFN configuration */ + DWORD last = dp->dptr; + + res = (dp->blk_ofs == 0xFFFFFFFF) ? FR_OK : dir_sdi(dp, dp->blk_ofs); /* Goto top of the entry block if LFN is exist */ + if (res == FR_OK) { + do { + res = move_window(fs, dp->sect); + if (res != FR_OK) break; + if (FF_FS_EXFAT && fs->fs_type == FS_EXFAT) { /* On the exFAT volume */ + dp->dir[XDIR_Type] &= 0x7F; /* Clear the entry InUse flag. */ + } else { /* On the FAT/FAT32 volume */ + dp->dir[DIR_Name] = DDEM; /* Mark the entry 'deleted'. */ + } + fs->wflag = 1; + if (dp->dptr >= last) break; /* If reached last entry then all entries of the object has been deleted. */ + res = dir_next(dp, 0); /* Next entry */ + } while (res == FR_OK); + if (res == FR_NO_FILE) res = FR_INT_ERR; + } +#else /* Non LFN configuration */ + + res = move_window(fs, dp->sect); + if (res == FR_OK) { + dp->dir[DIR_Name] = DDEM; /* Mark the entry 'deleted'.*/ + fs->wflag = 1; + } +#endif + + return res; +} + +#endif /* !FF_FS_READONLY && FF_FS_MINIMIZE == 0 */ + + + +#if FF_FS_MINIMIZE <= 1 || FF_FS_RPATH >= 2 +/*-----------------------------------------------------------------------*/ +/* Get file information from directory entry */ +/*-----------------------------------------------------------------------*/ + +static void get_fileinfo ( + DIR* dp, /* Pointer to the directory object */ + FILINFO* fno /* Pointer to the file information to be filled */ +) +{ + UINT si, di; +#if FF_USE_LFN + BYTE lcf; + WCHAR wc, hs; + FATFS *fs = dp->obj.fs; + UINT nw; +#else + TCHAR c; +#endif + + + fno->fname[0] = 0; /* Invaidate file info */ + if (dp->sect == 0) return; /* Exit if read pointer has reached end of directory */ + +#if FF_USE_LFN /* LFN configuration */ +#if FF_FS_EXFAT + if (fs->fs_type == FS_EXFAT) { /* exFAT volume */ + UINT nc = 0; + + si = SZDIRE * 2; di = 0; /* 1st C1 entry in the entry block */ + hs = 0; + while (nc < fs->dirbuf[XDIR_NumName]) { + if (si >= MAXDIRB(FF_MAX_LFN)) { di = 0; break; } /* Truncated directory block? */ + if ((si % SZDIRE) == 0) si += 2; /* Skip entry type field */ + wc = ld_word(fs->dirbuf + si); si += 2; nc++; /* Get a character */ + if (hs == 0 && IsSurrogate(wc)) { /* Is it a surrogate? */ + hs = wc; continue; /* Get low surrogate */ + } + nw = put_utf((DWORD)hs << 16 | wc, &fno->fname[di], FF_LFN_BUF - di); /* Store it in API encoding */ + if (nw == 0) { di = 0; break; } /* Buffer overflow or wrong char? */ + di += nw; + hs = 0; + } + if (hs != 0) di = 0; /* Broken surrogate pair? */ + if (di == 0) fno->fname[di++] = '?'; /* Inaccessible object name? */ + fno->fname[di] = 0; /* Terminate the name */ + fno->altname[0] = 0; /* exFAT does not support SFN */ + + fno->fattrib = fs->dirbuf[XDIR_Attr] & AM_MASKX; /* Attribute */ + fno->fsize = (fno->fattrib & AM_DIR) ? 0 : ld_qword(fs->dirbuf + XDIR_FileSize); /* Size */ + fno->ftime = ld_word(fs->dirbuf + XDIR_ModTime + 0); /* Time */ + fno->fdate = ld_word(fs->dirbuf + XDIR_ModTime + 2); /* Date */ + return; + } else +#endif + { /* FAT/FAT32 volume */ + if (dp->blk_ofs != 0xFFFFFFFF) { /* Get LFN if available */ + si = di = 0; + hs = 0; + while (fs->lfnbuf[si] != 0) { + wc = fs->lfnbuf[si++]; /* Get an LFN character (UTF-16) */ + if (hs == 0 && IsSurrogate(wc)) { /* Is it a surrogate? */ + hs = wc; continue; /* Get low surrogate */ + } + nw = put_utf((DWORD)hs << 16 | wc, &fno->fname[di], FF_LFN_BUF - di); /* Store it in API encoding */ + if (nw == 0) { di = 0; break; } /* Buffer overflow or wrong char? */ + di += nw; + hs = 0; + } + if (hs != 0) di = 0; /* Broken surrogate pair? */ + fno->fname[di] = 0; /* Terminate the LFN (null string means LFN is invalid) */ + } + } + + si = di = 0; + while (si < 11) { /* Get SFN from SFN entry */ + wc = dp->dir[si++]; /* Get a char */ + if (wc == ' ') continue; /* Skip padding spaces */ + if (wc == RDDEM) wc = DDEM; /* Restore replaced DDEM character */ + if (si == 9 && di < FF_SFN_BUF) fno->altname[di++] = '.'; /* Insert a . if extension is exist */ +#if FF_LFN_UNICODE >= 1 /* Unicode output */ + if (dbc_1st((BYTE)wc) && si != 8 && si != 11 && dbc_2nd(dp->dir[si])) { /* Make a DBC if needed */ + wc = wc << 8 | dp->dir[si++]; + } + wc = ff_oem2uni(wc, CODEPAGE); /* ANSI/OEM -> Unicode */ + if (wc == 0) { di = 0; break; } /* Wrong char in the current code page? */ + nw = put_utf(wc, &fno->altname[di], FF_SFN_BUF - di); /* Store it in API encoding */ + if (nw == 0) { di = 0; break; } /* Buffer overflow? */ + di += nw; +#else /* ANSI/OEM output */ + fno->altname[di++] = (TCHAR)wc; /* Store it without any conversion */ +#endif + } + fno->altname[di] = 0; /* Terminate the SFN (null string means SFN is invalid) */ + + if (fno->fname[0] == 0) { /* If LFN is invalid, altname[] needs to be copied to fname[] */ + if (di == 0) { /* If LFN and SFN both are invalid, this object is inaccesible */ + fno->fname[di++] = '?'; + } else { + for (si = di = 0, lcf = NS_BODY; fno->altname[si]; si++, di++) { /* Copy altname[] to fname[] with case information */ + wc = (WCHAR)fno->altname[si]; + if (wc == '.') lcf = NS_EXT; + if (IsUpper(wc) && (dp->dir[DIR_NTres] & lcf)) wc += 0x20; + fno->fname[di] = (TCHAR)wc; + } + } + fno->fname[di] = 0; /* Terminate the LFN */ + if (!dp->dir[DIR_NTres]) fno->altname[0] = 0; /* Altname is not needed if neither LFN nor case info is exist. */ + } + +#else /* Non-LFN configuration */ + si = di = 0; + while (si < 11) { /* Copy name body and extension */ + c = (TCHAR)dp->dir[si++]; + if (c == ' ') continue; /* Skip padding spaces */ + if (c == RDDEM) c = DDEM; /* Restore replaced DDEM character */ + if (si == 9) fno->fname[di++] = '.';/* Insert a . if extension is exist */ + fno->fname[di++] = c; + } + fno->fname[di] = 0; /* Terminate the SFN */ +#endif + + fno->fattrib = dp->dir[DIR_Attr] & AM_MASK; /* Attribute */ + fno->fsize = ld_dword(dp->dir + DIR_FileSize); /* Size */ + fno->ftime = ld_word(dp->dir + DIR_ModTime + 0); /* Time */ + fno->fdate = ld_word(dp->dir + DIR_ModTime + 2); /* Date */ +} + +#endif /* FF_FS_MINIMIZE <= 1 || FF_FS_RPATH >= 2 */ + + + +#if FF_USE_FIND && FF_FS_MINIMIZE <= 1 +/*-----------------------------------------------------------------------*/ +/* Pattern matching */ +/*-----------------------------------------------------------------------*/ + +#define FIND_RECURS 4 /* Maximum number of wildcard terms in the pattern to limit recursion */ + + +static DWORD get_achar ( /* Get a character and advance ptr */ + const TCHAR** ptr /* Pointer to pointer to the ANSI/OEM or Unicode string */ +) +{ + DWORD chr; + + +#if FF_USE_LFN && FF_LFN_UNICODE >= 1 /* Unicode input */ + chr = tchar2uni(ptr); + if (chr == 0xFFFFFFFF) chr = 0; /* Wrong UTF encoding is recognized as end of the string */ + chr = ff_wtoupper(chr); + +#else /* ANSI/OEM input */ + chr = (BYTE)*(*ptr)++; /* Get a byte */ + if (IsLower(chr)) chr -= 0x20; /* To upper ASCII char */ +#if FF_CODE_PAGE == 0 + if (ExCvt && chr >= 0x80) chr = ExCvt[chr - 0x80]; /* To upper SBCS extended char */ +#elif FF_CODE_PAGE < 900 + if (chr >= 0x80) chr = ExCvt[chr - 0x80]; /* To upper SBCS extended char */ +#endif +#if FF_CODE_PAGE == 0 || FF_CODE_PAGE >= 900 + if (dbc_1st((BYTE)chr)) { /* Get DBC 2nd byte if needed */ + chr = dbc_2nd((BYTE)**ptr) ? chr << 8 | (BYTE)*(*ptr)++ : 0; + } +#endif + +#endif + return chr; +} + + +static int pattern_match ( /* 0:mismatched, 1:matched */ + const TCHAR* pat, /* Matching pattern */ + const TCHAR* nam, /* String to be tested */ + UINT skip, /* Number of pre-skip chars (number of ?s, b8:infinite (* specified)) */ + UINT recur /* Recursion count */ +) +{ + const TCHAR *pptr, *nptr; + DWORD pchr, nchr; + UINT sk; + + + while ((skip & 0xFF) != 0) { /* Pre-skip name chars */ + if (!get_achar(&nam)) return 0; /* Branch mismatched if less name chars */ + skip--; + } + if (*pat == 0 && skip) return 1; /* Matched? (short circuit) */ + + do { + pptr = pat; nptr = nam; /* Top of pattern and name to match */ + for (;;) { + if (*pptr == '?' || *pptr == '*') { /* Wildcard term? */ + if (recur == 0) return 0; /* Too many wildcard terms? */ + sk = 0; + do { /* Analyze the wildcard term */ + if (*pptr++ == '?') sk++; else sk |= 0x100; + } while (*pptr == '?' || *pptr == '*'); + if (pattern_match(pptr, nptr, sk, recur - 1)) return 1; /* Test new branch (recursive call) */ + nchr = *nptr; break; /* Branch mismatched */ + } + pchr = get_achar(&pptr); /* Get a pattern char */ + nchr = get_achar(&nptr); /* Get a name char */ + if (pchr != nchr) break; /* Branch mismatched? */ + if (pchr == 0) return 1; /* Branch matched? (matched at end of both strings) */ + } + get_achar(&nam); /* nam++ */ + } while (skip && nchr); /* Retry until end of name if infinite search is specified */ + + return 0; +} + +#endif /* FF_USE_FIND && FF_FS_MINIMIZE <= 1 */ + + + +/*-----------------------------------------------------------------------*/ +/* Pick a top segment and create the object name in directory form */ +/*-----------------------------------------------------------------------*/ + +static FRESULT create_name ( /* FR_OK: successful, FR_INVALID_NAME: could not create */ + DIR* dp, /* Pointer to the directory object */ + const TCHAR** path /* Pointer to pointer to the segment in the path string */ +) +{ +#if FF_USE_LFN /* LFN configuration */ + BYTE b, cf; + WCHAR wc, *lfn; + DWORD uc; + UINT i, ni, si, di; + const TCHAR *p; + + + /* Create LFN into LFN working buffer */ + p = *path; lfn = dp->obj.fs->lfnbuf; di = 0; + for (;;) { + uc = tchar2uni(&p); /* Get a character */ + if (uc == 0xFFFFFFFF) return FR_INVALID_NAME; /* Invalid code or UTF decode error */ + if (uc >= 0x10000) lfn[di++] = (WCHAR)(uc >> 16); /* Store high surrogate if needed */ + wc = (WCHAR)uc; + if (wc < ' ' || IsSeparator(wc)) break; /* Break if end of the path or a separator is found */ + if (wc < 0x80 && strchr("*:<>|\"\?\x7F", (int)wc)) return FR_INVALID_NAME; /* Reject illegal characters for LFN */ + if (di >= FF_MAX_LFN) return FR_INVALID_NAME; /* Reject too long name */ + lfn[di++] = wc; /* Store the Unicode character */ + } + if (wc < ' ') { /* Stopped at end of the path? */ + cf = NS_LAST; /* Last segment */ + } else { /* Stopped at a separator */ + while (IsSeparator(*p)) p++; /* Skip duplicated separators if exist */ + cf = 0; /* Next segment may follow */ + if (IsTerminator(*p)) cf = NS_LAST; /* Ignore terminating separator */ + } + *path = p; /* Return pointer to the next segment */ + +#if FF_FS_RPATH != 0 + if ((di == 1 && lfn[di - 1] == '.') || + (di == 2 && lfn[di - 1] == '.' && lfn[di - 2] == '.')) { /* Is this segment a dot name? */ + lfn[di] = 0; + for (i = 0; i < 11; i++) { /* Create dot name for SFN entry */ + dp->fn[i] = (i < di) ? '.' : ' '; + } + dp->fn[i] = cf | NS_DOT; /* This is a dot entry */ + return FR_OK; + } +#endif + while (di) { /* Snip off trailing spaces and dots if exist */ + wc = lfn[di - 1]; + if (wc != ' ' && wc != '.') break; + di--; + } + lfn[di] = 0; /* LFN is created into the working buffer */ + if (di == 0) return FR_INVALID_NAME; /* Reject null name */ + + /* Create SFN in directory form */ + for (si = 0; lfn[si] == ' '; si++) ; /* Remove leading spaces */ + if (si > 0 || lfn[si] == '.') cf |= NS_LOSS | NS_LFN; /* Is there any leading space or dot? */ + while (di > 0 && lfn[di - 1] != '.') di--; /* Find last dot (di<=si: no extension) */ + + memset(dp->fn, ' ', 11); + i = b = 0; ni = 8; + for (;;) { + wc = lfn[si++]; /* Get an LFN character */ + if (wc == 0) break; /* Break on end of the LFN */ + if (wc == ' ' || (wc == '.' && si != di)) { /* Remove embedded spaces and dots */ + cf |= NS_LOSS | NS_LFN; + continue; + } + + if (i >= ni || si == di) { /* End of field? */ + if (ni == 11) { /* Name extension overflow? */ + cf |= NS_LOSS | NS_LFN; + break; + } + if (si != di) cf |= NS_LOSS | NS_LFN; /* Name body overflow? */ + if (si > di) break; /* No name extension? */ + si = di; i = 8; ni = 11; b <<= 2; /* Enter name extension */ + continue; + } + + if (wc >= 0x80) { /* Is this an extended character? */ + cf |= NS_LFN; /* LFN entry needs to be created */ +#if FF_CODE_PAGE == 0 + if (ExCvt) { /* In SBCS cfg */ + wc = ff_uni2oem(wc, CODEPAGE); /* Unicode ==> ANSI/OEM code */ + if (wc & 0x80) wc = ExCvt[wc & 0x7F]; /* Convert extended character to upper (SBCS) */ + } else { /* In DBCS cfg */ + wc = ff_uni2oem(ff_wtoupper(wc), CODEPAGE); /* Unicode ==> Up-convert ==> ANSI/OEM code */ + } +#elif FF_CODE_PAGE < 900 /* In SBCS cfg */ + wc = ff_uni2oem(wc, CODEPAGE); /* Unicode ==> ANSI/OEM code */ + if (wc & 0x80) wc = ExCvt[wc & 0x7F]; /* Convert extended character to upper (SBCS) */ +#else /* In DBCS cfg */ + wc = ff_uni2oem(ff_wtoupper(wc), CODEPAGE); /* Unicode ==> Up-convert ==> ANSI/OEM code */ +#endif + } + + if (wc >= 0x100) { /* Is this a DBC? */ + if (i >= ni - 1) { /* Field overflow? */ + cf |= NS_LOSS | NS_LFN; + i = ni; continue; /* Next field */ + } + dp->fn[i++] = (BYTE)(wc >> 8); /* Put 1st byte */ + } else { /* SBC */ + if (wc == 0 || strchr("+,;=[]", (int)wc)) { /* Replace illegal characters for SFN */ + wc = '_'; cf |= NS_LOSS | NS_LFN;/* Lossy conversion */ + } else { + if (IsUpper(wc)) { /* ASCII upper case? */ + b |= 2; + } + if (IsLower(wc)) { /* ASCII lower case? */ + b |= 1; wc -= 0x20; + } + } + } + dp->fn[i++] = (BYTE)wc; + } + + if (dp->fn[0] == DDEM) dp->fn[0] = RDDEM; /* If the first character collides with DDEM, replace it with RDDEM */ + + if (ni == 8) b <<= 2; /* Shift capital flags if no extension */ + if ((b & 0x0C) == 0x0C || (b & 0x03) == 0x03) cf |= NS_LFN; /* LFN entry needs to be created if composite capitals */ + if (!(cf & NS_LFN)) { /* When LFN is in 8.3 format without extended character, NT flags are created */ + if (b & 0x01) cf |= NS_EXT; /* NT flag (Extension has small capital letters only) */ + if (b & 0x04) cf |= NS_BODY; /* NT flag (Body has small capital letters only) */ + } + + dp->fn[NSFLAG] = cf; /* SFN is created into dp->fn[] */ + + return FR_OK; + + +#else /* FF_USE_LFN : Non-LFN configuration */ + BYTE c, d, *sfn; + UINT ni, si, i; + const char *p; + + /* Create file name in directory form */ + p = *path; sfn = dp->fn; + memset(sfn, ' ', 11); + si = i = 0; ni = 8; +#if FF_FS_RPATH != 0 + if (p[si] == '.') { /* Is this a dot entry? */ + for (;;) { + c = (BYTE)p[si++]; + if (c != '.' || si >= 3) break; + sfn[i++] = c; + } + if (!IsSeparator(c) && c > ' ') return FR_INVALID_NAME; + *path = p + si; /* Return pointer to the next segment */ + sfn[NSFLAG] = (c <= ' ') ? NS_LAST | NS_DOT : NS_DOT; /* Set last segment flag if end of the path */ + return FR_OK; + } +#endif + for (;;) { + c = (BYTE)p[si++]; /* Get a byte */ + if (c <= ' ') break; /* Break if end of the path name */ + if (IsSeparator(c)) { /* Break if a separator is found */ + while (IsSeparator(p[si])) si++; /* Skip duplicated separator if exist */ + break; + } + if (c == '.' || i >= ni) { /* End of body or field overflow? */ + if (ni == 11 || c != '.') return FR_INVALID_NAME; /* Field overflow or invalid dot? */ + i = 8; ni = 11; /* Enter file extension field */ + continue; + } +#if FF_CODE_PAGE == 0 + if (ExCvt && c >= 0x80) { /* Is SBC extended character? */ + c = ExCvt[c & 0x7F]; /* To upper SBC extended character */ + } +#elif FF_CODE_PAGE < 900 + if (c >= 0x80) { /* Is SBC extended character? */ + c = ExCvt[c & 0x7F]; /* To upper SBC extended character */ + } +#endif + if (dbc_1st(c)) { /* Check if it is a DBC 1st byte */ + d = (BYTE)p[si++]; /* Get 2nd byte */ + if (!dbc_2nd(d) || i >= ni - 1) return FR_INVALID_NAME; /* Reject invalid DBC */ + sfn[i++] = c; + sfn[i++] = d; + } else { /* SBC */ + if (strchr("*+,:;<=>[]|\"\?\x7F", (int)c)) return FR_INVALID_NAME; /* Reject illegal chrs for SFN */ + if (IsLower(c)) c -= 0x20; /* To upper */ + sfn[i++] = c; + } + } + *path = &p[si]; /* Return pointer to the next segment */ + if (i == 0) return FR_INVALID_NAME; /* Reject nul string */ + + if (sfn[0] == DDEM) sfn[0] = RDDEM; /* If the first character collides with DDEM, replace it with RDDEM */ + sfn[NSFLAG] = (c <= ' ' || p[si] <= ' ') ? NS_LAST : 0; /* Set last segment flag if end of the path */ + + return FR_OK; +#endif /* FF_USE_LFN */ +} + + + + +/*-----------------------------------------------------------------------*/ +/* Follow a file path */ +/*-----------------------------------------------------------------------*/ + +static FRESULT follow_path ( /* FR_OK(0): successful, !=0: error code */ + DIR* dp, /* Directory object to return last directory and found object */ + const TCHAR* path /* Full-path string to find a file or directory */ +) +{ + FRESULT res; + BYTE ns; + FATFS *fs = dp->obj.fs; + + +#if FF_FS_RPATH != 0 + if (!IsSeparator(*path) && (FF_STR_VOLUME_ID != 2 || !IsTerminator(*path))) { /* Without heading separator */ + dp->obj.sclust = fs->cdir; /* Start at the current directory */ + } else +#endif + { /* With heading separator */ + while (IsSeparator(*path)) path++; /* Strip separators */ + dp->obj.sclust = 0; /* Start from the root directory */ + } +#if FF_FS_EXFAT + dp->obj.n_frag = 0; /* Invalidate last fragment counter of the object */ +#if FF_FS_RPATH != 0 + if (fs->fs_type == FS_EXFAT && dp->obj.sclust) { /* exFAT: Retrieve the sub-directory's status */ + DIR dj; + + dp->obj.c_scl = fs->cdc_scl; + dp->obj.c_size = fs->cdc_size; + dp->obj.c_ofs = fs->cdc_ofs; + res = load_obj_xdir(&dj, &dp->obj); + if (res != FR_OK) return res; + dp->obj.objsize = ld_dword(fs->dirbuf + XDIR_FileSize); + dp->obj.stat = fs->dirbuf[XDIR_GenFlags] & 2; + } +#endif +#endif + + if ((UINT)*path < ' ') { /* Null path name is the origin directory itself */ + dp->fn[NSFLAG] = NS_NONAME; + res = dir_sdi(dp, 0); + + } else { /* Follow path */ + for (;;) { + res = create_name(dp, &path); /* Get a segment name of the path */ + if (res != FR_OK) break; + res = dir_find(dp); /* Find an object with the segment name */ + ns = dp->fn[NSFLAG]; + if (res != FR_OK) { /* Failed to find the object */ + if (res == FR_NO_FILE) { /* Object is not found */ + if (FF_FS_RPATH && (ns & NS_DOT)) { /* If dot entry is not exist, stay there */ + if (!(ns & NS_LAST)) continue; /* Continue to follow if not last segment */ + dp->fn[NSFLAG] = NS_NONAME; + res = FR_OK; + } else { /* Could not find the object */ + if (!(ns & NS_LAST)) res = FR_NO_PATH; /* Adjust error code if not last segment */ + } + } + break; + } + if (ns & NS_LAST) break; /* Last segment matched. Function completed. */ + /* Get into the sub-directory */ + if (!(dp->obj.attr & AM_DIR)) { /* It is not a sub-directory and cannot follow */ + res = FR_NO_PATH; break; + } +#if FF_FS_EXFAT + if (fs->fs_type == FS_EXFAT) { /* Save containing directory information for next dir */ + dp->obj.c_scl = dp->obj.sclust; + dp->obj.c_size = ((DWORD)dp->obj.objsize & 0xFFFFFF00) | dp->obj.stat; + dp->obj.c_ofs = dp->blk_ofs; + init_alloc_info(fs, &dp->obj); /* Open next directory */ + } else +#endif + { + dp->obj.sclust = ld_clust(fs, fs->win + dp->dptr % SS(fs)); /* Open next directory */ + } + } + } + + return res; +} + + + + +/*-----------------------------------------------------------------------*/ +/* Get logical drive number from path name */ +/*-----------------------------------------------------------------------*/ + +static int get_ldnumber ( /* Returns logical drive number (-1:invalid drive number or null pointer) */ + const TCHAR** path /* Pointer to pointer to the path name */ +) +{ + const TCHAR *tp, *tt; + TCHAR tc; + int i; + int vol = -1; +#if FF_STR_VOLUME_ID /* Find string volume ID */ + const char *sp; + char c; +#endif + + tt = tp = *path; + if (!tp) return vol; /* Invalid path name? */ + do tc = *tt++; while (!IsTerminator(tc) && tc != ':'); /* Find a colon in the path */ + + if (tc == ':') { /* DOS/Windows style volume ID? */ + i = FF_VOLUMES; + if (IsDigit(*tp) && tp + 2 == tt) { /* Is there a numeric volume ID + colon? */ + i = (int)*tp - '0'; /* Get the LD number */ + } +#if FF_STR_VOLUME_ID == 1 /* Arbitrary string is enabled */ + else { + i = 0; + do { + sp = VolumeStr[i]; tp = *path; /* This string volume ID and path name */ + do { /* Compare the volume ID with path name */ + c = *sp++; tc = *tp++; + if (IsLower(c)) c -= 0x20; + if (IsLower(tc)) tc -= 0x20; + } while (c && (TCHAR)c == tc); + } while ((c || tp != tt) && ++i < FF_VOLUMES); /* Repeat for each id until pattern match */ + } +#endif + if (i < FF_VOLUMES) { /* If a volume ID is found, get the drive number and strip it */ + vol = i; /* Drive number */ + *path = tt; /* Snip the drive prefix off */ + } + return vol; + } +#if FF_STR_VOLUME_ID == 2 /* Unix style volume ID is enabled */ + if (*tp == '/') { /* Is there a volume ID? */ + while (*(tp + 1) == '/') tp++; /* Skip duplicated separator */ + i = 0; + do { + tt = tp; sp = VolumeStr[i]; /* Path name and this string volume ID */ + do { /* Compare the volume ID with path name */ + c = *sp++; tc = *(++tt); + if (IsLower(c)) c -= 0x20; + if (IsLower(tc)) tc -= 0x20; + } while (c && (TCHAR)c == tc); + } while ((c || (tc != '/' && !IsTerminator(tc))) && ++i < FF_VOLUMES); /* Repeat for each ID until pattern match */ + if (i < FF_VOLUMES) { /* If a volume ID is found, get the drive number and strip it */ + vol = i; /* Drive number */ + *path = tt; /* Snip the drive prefix off */ + } + return vol; + } +#endif + /* No drive prefix is found */ +#if FF_FS_RPATH != 0 + vol = CurrVol; /* Default drive is current drive */ +#else + vol = 0; /* Default drive is 0 */ +#endif + return vol; /* Return the default drive */ +} + + + + +/*-----------------------------------------------------------------------*/ +/* GPT support functions */ +/*-----------------------------------------------------------------------*/ + +#if FF_LBA64 + +/* Calculate CRC32 in byte-by-byte */ + +static DWORD crc32 ( /* Returns next CRC value */ + DWORD crc, /* Current CRC value */ + BYTE d /* A byte to be processed */ +) +{ + BYTE b; + + + for (b = 1; b; b <<= 1) { + crc ^= (d & b) ? 1 : 0; + crc = (crc & 1) ? crc >> 1 ^ 0xEDB88320 : crc >> 1; + } + return crc; +} + + +/* Check validity of GPT header */ + +static int test_gpt_header ( /* 0:Invalid, 1:Valid */ + const BYTE* gpth /* Pointer to the GPT header */ +) +{ + UINT i; + DWORD bcc; + + + if (memcmp(gpth + GPTH_Sign, "EFI PART" "\0\0\1\0" "\x5C\0\0", 16)) return 0; /* Check sign, version (1.0) and length (92) */ + for (i = 0, bcc = 0xFFFFFFFF; i < 92; i++) { /* Check header BCC */ + bcc = crc32(bcc, i - GPTH_Bcc < 4 ? 0 : gpth[i]); + } + if (~bcc != ld_dword(gpth + GPTH_Bcc)) return 0; + if (ld_dword(gpth + GPTH_PteSize) != SZ_GPTE) return 0; /* Table entry size (must be SZ_GPTE bytes) */ + if (ld_dword(gpth + GPTH_PtNum) > 128) return 0; /* Table size (must be 128 entries or less) */ + + return 1; +} + +#if !FF_FS_READONLY && FF_USE_MKFS + +/* Generate random value */ +static DWORD make_rand ( + DWORD seed, /* Seed value */ + BYTE* buff, /* Output buffer */ + UINT n /* Data length */ +) +{ + UINT r; + + + if (seed == 0) seed = 1; + do { + for (r = 0; r < 8; r++) seed = seed & 1 ? seed >> 1 ^ 0xA3000000 : seed >> 1; /* Shift 8 bits the 32-bit LFSR */ + *buff++ = (BYTE)seed; + } while (--n); + return seed; +} + +#endif +#endif + + + +/*-----------------------------------------------------------------------*/ +/* Load a sector and check if it is an FAT VBR */ +/*-----------------------------------------------------------------------*/ + +/* Check what the sector is */ + +static UINT check_fs ( /* 0:FAT/FAT32 VBR, 1:exFAT VBR, 2:Not FAT and valid BS, 3:Not FAT and invalid BS, 4:Disk error */ + FATFS* fs, /* Filesystem object */ + LBA_t sect /* Sector to load and check if it is an FAT-VBR or not */ +) +{ + WORD w, sign; + BYTE b; + + + fs->wflag = 0; fs->winsect = (LBA_t)0 - 1; /* Invaidate window */ + if (move_window(fs, sect) != FR_OK) return 4; /* Load the boot sector */ + sign = ld_word(fs->win + BS_55AA); +#if FF_FS_EXFAT + if (sign == 0xAA55 && !memcmp(fs->win + BS_JmpBoot, "\xEB\x76\x90" "EXFAT ", 11)) return 1; /* It is an exFAT VBR */ +#endif + b = fs->win[BS_JmpBoot]; + if (b == 0xEB || b == 0xE9 || b == 0xE8) { /* Valid JumpBoot code? (short jump, near jump or near call) */ + if (sign == 0xAA55 && !memcmp(fs->win + BS_FilSysType32, "FAT32 ", 8)) { + return 0; /* It is an FAT32 VBR */ + } + /* FAT volumes formatted with early MS-DOS lack BS_55AA and BS_FilSysType, so FAT VBR needs to be identified without them. */ + w = ld_word(fs->win + BPB_BytsPerSec); + b = fs->win[BPB_SecPerClus]; + if ((w & (w - 1)) == 0 && w >= FF_MIN_SS && w <= FF_MAX_SS /* Properness of sector size (512-4096 and 2^n) */ + && b != 0 && (b & (b - 1)) == 0 /* Properness of cluster size (2^n) */ + && ld_word(fs->win + BPB_RsvdSecCnt) != 0 /* Properness of reserved sectors (MNBZ) */ + && (UINT)fs->win[BPB_NumFATs] - 1 <= 1 /* Properness of FATs (1 or 2) */ + && ld_word(fs->win + BPB_RootEntCnt) != 0 /* Properness of root dir entries (MNBZ) */ + && (ld_word(fs->win + BPB_TotSec16) >= 128 || ld_dword(fs->win + BPB_TotSec32) >= 0x10000) /* Properness of volume sectors (>=128) */ + && ld_word(fs->win + BPB_FATSz16) != 0) { /* Properness of FAT size (MNBZ) */ + return 0; /* It can be presumed an FAT VBR */ + } + } + return sign == 0xAA55 ? 2 : 3; /* Not an FAT VBR (valid or invalid BS) */ +} + + +/* Find an FAT volume */ +/* (It supports only generic partitioning rules, MBR, GPT and SFD) */ + +static UINT find_volume ( /* Returns BS status found in the hosting drive */ + FATFS* fs, /* Filesystem object */ + UINT part /* Partition to fined = 0:auto, 1..:forced */ +) +{ + UINT fmt, i; + DWORD mbr_pt[4]; + + + fmt = check_fs(fs, 0); /* Load sector 0 and check if it is an FAT VBR as SFD format */ + if (fmt != 2 && (fmt >= 3 || part == 0)) return fmt; /* Returns if it is an FAT VBR as auto scan, not a BS or disk error */ + + /* Sector 0 is not an FAT VBR or forced partition number wants a partition */ + +#if FF_LBA64 + if (fs->win[MBR_Table + PTE_System] == 0xEE) { /* GPT protective MBR? */ + DWORD n_ent, v_ent, ofs; + QWORD pt_lba; + + if (move_window(fs, 1) != FR_OK) return 4; /* Load GPT header sector (next to MBR) */ + if (!test_gpt_header(fs->win)) return 3; /* Check if GPT header is valid */ + n_ent = ld_dword(fs->win + GPTH_PtNum); /* Number of entries */ + pt_lba = ld_qword(fs->win + GPTH_PtOfs); /* Table location */ + for (v_ent = i = 0; i < n_ent; i++) { /* Find FAT partition */ + if (move_window(fs, pt_lba + i * SZ_GPTE / SS(fs)) != FR_OK) return 4; /* PT sector */ + ofs = i * SZ_GPTE % SS(fs); /* Offset in the sector */ + if (!memcmp(fs->win + ofs + GPTE_PtGuid, GUID_MS_Basic, 16)) { /* MS basic data partition? */ + v_ent++; + fmt = check_fs(fs, ld_qword(fs->win + ofs + GPTE_FstLba)); /* Load VBR and check status */ + if (part == 0 && fmt <= 1) return fmt; /* Auto search (valid FAT volume found first) */ + if (part != 0 && v_ent == part) return fmt; /* Forced partition order (regardless of it is valid or not) */ + } + } + return 3; /* Not found */ + } +#endif + if (FF_MULTI_PARTITION && part > 4) return 3; /* MBR has 4 partitions max */ + for (i = 0; i < 4; i++) { /* Load partition offset in the MBR */ + mbr_pt[i] = ld_dword(fs->win + MBR_Table + i * SZ_PTE + PTE_StLba); + } + i = part ? part - 1 : 0; /* Table index to find first */ + do { /* Find an FAT volume */ + fmt = mbr_pt[i] ? check_fs(fs, mbr_pt[i]) : 3; /* Check if the partition is FAT */ + } while (part == 0 && fmt >= 2 && ++i < 4); + return fmt; +} + + + + +/*-----------------------------------------------------------------------*/ +/* Determine logical drive number and mount the volume if needed */ +/*-----------------------------------------------------------------------*/ + +static FRESULT mount_volume ( /* FR_OK(0): successful, !=0: an error occurred */ + const TCHAR** path, /* Pointer to pointer to the path name (drive number) */ + FATFS** rfs, /* Pointer to pointer to the found filesystem object */ + BYTE mode /* !=0: Check write protection for write access */ +) +{ + int vol; + DSTATUS stat; + LBA_t bsect; + DWORD tsect, sysect, fasize, nclst, szbfat; + WORD nrsv; + FATFS *fs; + UINT fmt; + + + /* Get logical drive number */ + *rfs = 0; + vol = get_ldnumber(path); + if (vol < 0) return FR_INVALID_DRIVE; + + /* Check if the filesystem object is valid or not */ + fs = FatFs[vol]; /* Get pointer to the filesystem object */ + if (!fs) return FR_NOT_ENABLED; /* Is the filesystem object available? */ +#if FF_FS_REENTRANT + if (!lock_fs(fs)) return FR_TIMEOUT; /* Lock the volume */ +#endif + *rfs = fs; /* Return pointer to the filesystem object */ + + mode &= (BYTE)~FA_READ; /* Desired access mode, write access or not */ + if (fs->fs_type != 0) { /* If the volume has been mounted */ + stat = disk_status(fs->pdrv); + if (!(stat & STA_NOINIT)) { /* and the physical drive is kept initialized */ + if (!FF_FS_READONLY && mode && (stat & STA_PROTECT)) { /* Check write protection if needed */ + return FR_WRITE_PROTECTED; + } + return FR_OK; /* The filesystem object is already valid */ + } + } + + /* The filesystem object is not valid. */ + /* Following code attempts to mount the volume. (find an FAT volume, analyze the BPB and initialize the filesystem object) */ + + fs->fs_type = 0; /* Clear the filesystem object */ + fs->pdrv = LD2PD(vol); /* Volume hosting physical drive */ + stat = disk_initialize(fs->pdrv); /* Initialize the physical drive */ + if (stat & STA_NOINIT) { /* Check if the initialization succeeded */ + return FR_NOT_READY; /* Failed to initialize due to no medium or hard error */ + } + if (!FF_FS_READONLY && mode && (stat & STA_PROTECT)) { /* Check disk write protection if needed */ + return FR_WRITE_PROTECTED; + } +#if FF_MAX_SS != FF_MIN_SS /* Get sector size (multiple sector size cfg only) */ + if (disk_ioctl(fs->pdrv, GET_SECTOR_SIZE, &SS(fs)) != RES_OK) return FR_DISK_ERR; + if (SS(fs) > FF_MAX_SS || SS(fs) < FF_MIN_SS || (SS(fs) & (SS(fs) - 1))) return FR_DISK_ERR; +#endif + + /* Find an FAT volume on the drive */ + fmt = find_volume(fs, LD2PT(vol)); + if (fmt == 4) return FR_DISK_ERR; /* An error occured in the disk I/O layer */ + if (fmt >= 2) return FR_NO_FILESYSTEM; /* No FAT volume is found */ + bsect = fs->winsect; /* Volume offset */ + + /* An FAT volume is found (bsect). Following code initializes the filesystem object */ + +#if FF_FS_EXFAT + if (fmt == 1) { + QWORD maxlba; + DWORD so, cv, bcl, i; + + for (i = BPB_ZeroedEx; i < BPB_ZeroedEx + 53 && fs->win[i] == 0; i++) ; /* Check zero filler */ + if (i < BPB_ZeroedEx + 53) return FR_NO_FILESYSTEM; + + if (ld_word(fs->win + BPB_FSVerEx) != 0x100) return FR_NO_FILESYSTEM; /* Check exFAT version (must be version 1.0) */ + + if (1 << fs->win[BPB_BytsPerSecEx] != SS(fs)) { /* (BPB_BytsPerSecEx must be equal to the physical sector size) */ + return FR_NO_FILESYSTEM; + } + + maxlba = ld_qword(fs->win + BPB_TotSecEx) + bsect; /* Last LBA of the volume + 1 */ + if (!FF_LBA64 && maxlba >= 0x100000000) return FR_NO_FILESYSTEM; /* (It cannot be accessed in 32-bit LBA) */ + + fs->fsize = ld_dword(fs->win + BPB_FatSzEx); /* Number of sectors per FAT */ + + fs->n_fats = fs->win[BPB_NumFATsEx]; /* Number of FATs */ + if (fs->n_fats != 1) return FR_NO_FILESYSTEM; /* (Supports only 1 FAT) */ + + fs->csize = 1 << fs->win[BPB_SecPerClusEx]; /* Cluster size */ + if (fs->csize == 0) return FR_NO_FILESYSTEM; /* (Must be 1..32768 sectors) */ + + nclst = ld_dword(fs->win + BPB_NumClusEx); /* Number of clusters */ + if (nclst > MAX_EXFAT) return FR_NO_FILESYSTEM; /* (Too many clusters) */ + fs->n_fatent = nclst + 2; + + /* Boundaries and Limits */ + fs->volbase = bsect; + fs->database = bsect + ld_dword(fs->win + BPB_DataOfsEx); + fs->fatbase = bsect + ld_dword(fs->win + BPB_FatOfsEx); + if (maxlba < (QWORD)fs->database + nclst * fs->csize) return FR_NO_FILESYSTEM; /* (Volume size must not be smaller than the size requiered) */ + fs->dirbase = ld_dword(fs->win + BPB_RootClusEx); + + /* Get bitmap location and check if it is contiguous (implementation assumption) */ + so = i = 0; + for (;;) { /* Find the bitmap entry in the root directory (in only first cluster) */ + if (i == 0) { + if (so >= fs->csize) return FR_NO_FILESYSTEM; /* Not found? */ + if (move_window(fs, clst2sect(fs, (DWORD)fs->dirbase) + so) != FR_OK) return FR_DISK_ERR; + so++; + } + if (fs->win[i] == ET_BITMAP) break; /* Is it a bitmap entry? */ + i = (i + SZDIRE) % SS(fs); /* Next entry */ + } + bcl = ld_dword(fs->win + i + 20); /* Bitmap cluster */ + if (bcl < 2 || bcl >= fs->n_fatent) return FR_NO_FILESYSTEM; /* (Wrong cluster#) */ + fs->bitbase = fs->database + fs->csize * (bcl - 2); /* Bitmap sector */ + for (;;) { /* Check if bitmap is contiguous */ + if (move_window(fs, fs->fatbase + bcl / (SS(fs) / 4)) != FR_OK) return FR_DISK_ERR; + cv = ld_dword(fs->win + bcl % (SS(fs) / 4) * 4); + if (cv == 0xFFFFFFFF) break; /* Last link? */ + if (cv != ++bcl) return FR_NO_FILESYSTEM; /* Fragmented? */ + } + +#if !FF_FS_READONLY + fs->last_clst = fs->free_clst = 0xFFFFFFFF; /* Initialize cluster allocation information */ +#endif + fmt = FS_EXFAT; /* FAT sub-type */ + } else +#endif /* FF_FS_EXFAT */ + { + if (ld_word(fs->win + BPB_BytsPerSec) != SS(fs)) return FR_NO_FILESYSTEM; /* (BPB_BytsPerSec must be equal to the physical sector size) */ + + fasize = ld_word(fs->win + BPB_FATSz16); /* Number of sectors per FAT */ + if (fasize == 0) fasize = ld_dword(fs->win + BPB_FATSz32); + fs->fsize = fasize; + + fs->n_fats = fs->win[BPB_NumFATs]; /* Number of FATs */ + if (fs->n_fats != 1 && fs->n_fats != 2) return FR_NO_FILESYSTEM; /* (Must be 1 or 2) */ + fasize *= fs->n_fats; /* Number of sectors for FAT area */ + + fs->csize = fs->win[BPB_SecPerClus]; /* Cluster size */ + if (fs->csize == 0 || (fs->csize & (fs->csize - 1))) return FR_NO_FILESYSTEM; /* (Must be power of 2) */ + + fs->n_rootdir = ld_word(fs->win + BPB_RootEntCnt); /* Number of root directory entries */ + if (fs->n_rootdir % (SS(fs) / SZDIRE)) return FR_NO_FILESYSTEM; /* (Must be sector aligned) */ + + tsect = ld_word(fs->win + BPB_TotSec16); /* Number of sectors on the volume */ + if (tsect == 0) tsect = ld_dword(fs->win + BPB_TotSec32); + + nrsv = ld_word(fs->win + BPB_RsvdSecCnt); /* Number of reserved sectors */ + if (nrsv == 0) return FR_NO_FILESYSTEM; /* (Must not be 0) */ + + /* Determine the FAT sub type */ + sysect = nrsv + fasize + fs->n_rootdir / (SS(fs) / SZDIRE); /* RSV + FAT + DIR */ + if (tsect < sysect) return FR_NO_FILESYSTEM; /* (Invalid volume size) */ + nclst = (tsect - sysect) / fs->csize; /* Number of clusters */ + if (nclst == 0) return FR_NO_FILESYSTEM; /* (Invalid volume size) */ + fmt = 0; + if (nclst <= MAX_FAT32) fmt = FS_FAT32; + if (nclst <= MAX_FAT16) fmt = FS_FAT16; + if (nclst <= MAX_FAT12) fmt = FS_FAT12; + if (fmt == 0) return FR_NO_FILESYSTEM; + + /* Boundaries and Limits */ + fs->n_fatent = nclst + 2; /* Number of FAT entries */ + fs->volbase = bsect; /* Volume start sector */ + fs->fatbase = bsect + nrsv; /* FAT start sector */ + fs->database = bsect + sysect; /* Data start sector */ + if (fmt == FS_FAT32) { + if (ld_word(fs->win + BPB_FSVer32) != 0) return FR_NO_FILESYSTEM; /* (Must be FAT32 revision 0.0) */ + if (fs->n_rootdir != 0) return FR_NO_FILESYSTEM; /* (BPB_RootEntCnt must be 0) */ + fs->dirbase = ld_dword(fs->win + BPB_RootClus32); /* Root directory start cluster */ + szbfat = fs->n_fatent * 4; /* (Needed FAT size) */ + } else { + if (fs->n_rootdir == 0) return FR_NO_FILESYSTEM; /* (BPB_RootEntCnt must not be 0) */ + fs->dirbase = fs->fatbase + fasize; /* Root directory start sector */ + szbfat = (fmt == FS_FAT16) ? /* (Needed FAT size) */ + fs->n_fatent * 2 : fs->n_fatent * 3 / 2 + (fs->n_fatent & 1); + } + if (fs->fsize < (szbfat + (SS(fs) - 1)) / SS(fs)) return FR_NO_FILESYSTEM; /* (BPB_FATSz must not be less than the size needed) */ + +#if !FF_FS_READONLY + /* Get FSInfo if available */ + fs->last_clst = fs->free_clst = 0xFFFFFFFF; /* Initialize cluster allocation information */ + fs->fsi_flag = 0x80; +#if (FF_FS_NOFSINFO & 3) != 3 + if (fmt == FS_FAT32 /* Allow to update FSInfo only if BPB_FSInfo32 == 1 */ + && ld_word(fs->win + BPB_FSInfo32) == 1 + && move_window(fs, bsect + 1) == FR_OK) + { + fs->fsi_flag = 0; + if (ld_word(fs->win + BS_55AA) == 0xAA55 /* Load FSInfo data if available */ + && ld_dword(fs->win + FSI_LeadSig) == 0x41615252 + && ld_dword(fs->win + FSI_StrucSig) == 0x61417272) + { +#if (FF_FS_NOFSINFO & 1) == 0 + fs->free_clst = ld_dword(fs->win + FSI_Free_Count); +#endif +#if (FF_FS_NOFSINFO & 2) == 0 + fs->last_clst = ld_dword(fs->win + FSI_Nxt_Free); +#endif + } + } +#endif /* (FF_FS_NOFSINFO & 3) != 3 */ +#endif /* !FF_FS_READONLY */ + } + + fs->fs_type = (BYTE)fmt;/* FAT sub-type */ + fs->id = ++Fsid; /* Volume mount ID */ +#if FF_USE_LFN == 1 + fs->lfnbuf = LfnBuf; /* Static LFN working buffer */ +#if FF_FS_EXFAT + fs->dirbuf = DirBuf; /* Static directory block scratchpad buuffer */ +#endif +#endif +#if FF_FS_RPATH != 0 + fs->cdir = 0; /* Initialize current directory */ +#endif +#if FF_FS_LOCK != 0 /* Clear file lock semaphores */ + clear_lock(fs); +#endif + return FR_OK; +} + + + + +/*-----------------------------------------------------------------------*/ +/* Check if the file/directory object is valid or not */ +/*-----------------------------------------------------------------------*/ + +static FRESULT validate ( /* Returns FR_OK or FR_INVALID_OBJECT */ + FFOBJID* obj, /* Pointer to the FFOBJID, the 1st member in the FIL/DIR object, to check validity */ + FATFS** rfs /* Pointer to pointer to the owner filesystem object to return */ +) +{ + FRESULT res = FR_INVALID_OBJECT; + + + if (obj && obj->fs && obj->fs->fs_type && obj->id == obj->fs->id) { /* Test if the object is valid */ +#if FF_FS_REENTRANT + if (lock_fs(obj->fs)) { /* Obtain the filesystem object */ + if (!(disk_status(obj->fs->pdrv) & STA_NOINIT)) { /* Test if the phsical drive is kept initialized */ + res = FR_OK; + } else { + unlock_fs(obj->fs, FR_OK); + } + } else { + res = FR_TIMEOUT; + } +#else + if (!(disk_status(obj->fs->pdrv) & STA_NOINIT)) { /* Test if the phsical drive is kept initialized */ + res = FR_OK; + } +#endif + } + *rfs = (res == FR_OK) ? obj->fs : 0; /* Corresponding filesystem object */ + return res; +} + + + + +/*--------------------------------------------------------------------------- + + Public Functions (FatFs API) + +----------------------------------------------------------------------------*/ + + + +/*-----------------------------------------------------------------------*/ +/* Mount/Unmount a Logical Drive */ +/*-----------------------------------------------------------------------*/ + +FRESULT f_mount ( + FATFS* fs, /* Pointer to the filesystem object to be registered (NULL:unmount)*/ + const TCHAR* path, /* Logical drive number to be mounted/unmounted */ + BYTE opt /* Mount option: 0=Do not mount (delayed mount), 1=Mount immediately */ +) +{ + FATFS *cfs; + int vol; + FRESULT res; + const TCHAR *rp = path; + + + /* Get logical drive number */ + vol = get_ldnumber(&rp); + if (vol < 0) return FR_INVALID_DRIVE; + cfs = FatFs[vol]; /* Pointer to fs object */ + + if (cfs) { +#if FF_FS_LOCK != 0 + clear_lock(cfs); +#endif +#if FF_FS_REENTRANT /* Discard sync object of the current volume */ + if (!ff_del_syncobj(cfs->sobj)) return FR_INT_ERR; +#endif + cfs->fs_type = 0; /* Clear old fs object */ + } + + if (fs) { + fs->fs_type = 0; /* Clear new fs object */ +#if FF_FS_REENTRANT /* Create sync object for the new volume */ + if (!ff_cre_syncobj((BYTE)vol, &fs->sobj)) return FR_INT_ERR; +#endif + } + FatFs[vol] = fs; /* Register new fs object */ + + if (opt == 0) return FR_OK; /* Do not mount now, it will be mounted later */ + + res = mount_volume(&path, &fs, 0); /* Force mounted the volume */ + LEAVE_FF(fs, res); +} + + + + +/*-----------------------------------------------------------------------*/ +/* Open or Create a File */ +/*-----------------------------------------------------------------------*/ + +FRESULT f_open ( + FIL* fp, /* Pointer to the blank file object */ + const TCHAR* path, /* Pointer to the file name */ + BYTE mode /* Access mode and open mode flags */ +) +{ + FRESULT res; + DIR dj; + FATFS *fs; +#if !FF_FS_READONLY + DWORD cl, bcs, clst, tm; + LBA_t sc; + FSIZE_t ofs; +#endif + DEF_NAMBUF + + + if (!fp) return FR_INVALID_OBJECT; + + /* Get logical drive number */ + mode &= FF_FS_READONLY ? FA_READ : FA_READ | FA_WRITE | FA_CREATE_ALWAYS | FA_CREATE_NEW | FA_OPEN_ALWAYS | FA_OPEN_APPEND; + res = mount_volume(&path, &fs, mode); + if (res == FR_OK) { + dj.obj.fs = fs; + INIT_NAMBUF(fs); + res = follow_path(&dj, path); /* Follow the file path */ +#if !FF_FS_READONLY /* Read/Write configuration */ + if (res == FR_OK) { + if (dj.fn[NSFLAG] & NS_NONAME) { /* Origin directory itself? */ + res = FR_INVALID_NAME; + } +#if FF_FS_LOCK != 0 + else { + res = chk_lock(&dj, (mode & ~FA_READ) ? 1 : 0); /* Check if the file can be used */ + } +#endif + } + /* Create or Open a file */ + if (mode & (FA_CREATE_ALWAYS | FA_OPEN_ALWAYS | FA_CREATE_NEW)) { + if (res != FR_OK) { /* No file, create new */ + if (res == FR_NO_FILE) { /* There is no file to open, create a new entry */ +#if FF_FS_LOCK != 0 + res = enq_lock() ? dir_register(&dj) : FR_TOO_MANY_OPEN_FILES; +#else + res = dir_register(&dj); +#endif + } + mode |= FA_CREATE_ALWAYS; /* File is created */ + } + else { /* Any object with the same name is already existing */ + if (dj.obj.attr & (AM_RDO | AM_DIR)) { /* Cannot overwrite it (R/O or DIR) */ + res = FR_DENIED; + } else { + if (mode & FA_CREATE_NEW) res = FR_EXIST; /* Cannot create as new file */ + } + } + if (res == FR_OK && (mode & FA_CREATE_ALWAYS)) { /* Truncate the file if overwrite mode */ +#if FF_FS_EXFAT + if (fs->fs_type == FS_EXFAT) { + /* Get current allocation info */ + fp->obj.fs = fs; + init_alloc_info(fs, &fp->obj); + /* Set directory entry block initial state */ + memset(fs->dirbuf + 2, 0, 30); /* Clear 85 entry except for NumSec */ + memset(fs->dirbuf + 38, 0, 26); /* Clear C0 entry except for NumName and NameHash */ + fs->dirbuf[XDIR_Attr] = AM_ARC; + st_dword(fs->dirbuf + XDIR_CrtTime, GET_FATTIME()); + fs->dirbuf[XDIR_GenFlags] = 1; + res = store_xdir(&dj); + if (res == FR_OK && fp->obj.sclust != 0) { /* Remove the cluster chain if exist */ + res = remove_chain(&fp->obj, fp->obj.sclust, 0); + fs->last_clst = fp->obj.sclust - 1; /* Reuse the cluster hole */ + } + } else +#endif + { + /* Set directory entry initial state */ + tm = GET_FATTIME(); /* Set created time */ + st_dword(dj.dir + DIR_CrtTime, tm); + st_dword(dj.dir + DIR_ModTime, tm); + cl = ld_clust(fs, dj.dir); /* Get current cluster chain */ + dj.dir[DIR_Attr] = AM_ARC; /* Reset attribute */ + st_clust(fs, dj.dir, 0); /* Reset file allocation info */ + st_dword(dj.dir + DIR_FileSize, 0); + fs->wflag = 1; + if (cl != 0) { /* Remove the cluster chain if exist */ + sc = fs->winsect; + res = remove_chain(&dj.obj, cl, 0); + if (res == FR_OK) { + res = move_window(fs, sc); + fs->last_clst = cl - 1; /* Reuse the cluster hole */ + } + } + } + } + } + else { /* Open an existing file */ + if (res == FR_OK) { /* Is the object exsiting? */ + if (dj.obj.attr & AM_DIR) { /* File open against a directory */ + res = FR_NO_FILE; + } else { + if ((mode & FA_WRITE) && (dj.obj.attr & AM_RDO)) { /* Write mode open against R/O file */ + res = FR_DENIED; + } + } + } + } + if (res == FR_OK) { + if (mode & FA_CREATE_ALWAYS) mode |= FA_MODIFIED; /* Set file change flag if created or overwritten */ + fp->dir_sect = fs->winsect; /* Pointer to the directory entry */ + fp->dir_ptr = dj.dir; +#if FF_FS_LOCK != 0 + fp->obj.lockid = inc_lock(&dj, (mode & ~FA_READ) ? 1 : 0); /* Lock the file for this session */ + if (fp->obj.lockid == 0) res = FR_INT_ERR; +#endif + } +#else /* R/O configuration */ + if (res == FR_OK) { + if (dj.fn[NSFLAG] & NS_NONAME) { /* Is it origin directory itself? */ + res = FR_INVALID_NAME; + } else { + if (dj.obj.attr & AM_DIR) { /* Is it a directory? */ + res = FR_NO_FILE; + } + } + } +#endif + + if (res == FR_OK) { +#if FF_FS_EXFAT + if (fs->fs_type == FS_EXFAT) { + fp->obj.c_scl = dj.obj.sclust; /* Get containing directory info */ + fp->obj.c_size = ((DWORD)dj.obj.objsize & 0xFFFFFF00) | dj.obj.stat; + fp->obj.c_ofs = dj.blk_ofs; + init_alloc_info(fs, &fp->obj); + } else +#endif + { + fp->obj.sclust = ld_clust(fs, dj.dir); /* Get object allocation info */ + fp->obj.objsize = ld_dword(dj.dir + DIR_FileSize); + } +#if FF_USE_FASTSEEK + fp->cltbl = 0; /* Disable fast seek mode */ +#endif + fp->obj.fs = fs; /* Validate the file object */ + fp->obj.id = fs->id; + fp->flag = mode; /* Set file access mode */ + fp->err = 0; /* Clear error flag */ + fp->sect = 0; /* Invalidate current data sector */ + fp->fptr = 0; /* Set file pointer top of the file */ +#if !FF_FS_READONLY +#if !FF_FS_TINY + memset(fp->buf, 0, sizeof fp->buf); /* Clear sector buffer */ +#endif + if ((mode & FA_SEEKEND) && fp->obj.objsize > 0) { /* Seek to end of file if FA_OPEN_APPEND is specified */ + fp->fptr = fp->obj.objsize; /* Offset to seek */ + bcs = (DWORD)fs->csize * SS(fs); /* Cluster size in byte */ + clst = fp->obj.sclust; /* Follow the cluster chain */ + for (ofs = fp->obj.objsize; res == FR_OK && ofs > bcs; ofs -= bcs) { + clst = get_fat(&fp->obj, clst); + if (clst <= 1) res = FR_INT_ERR; + if (clst == 0xFFFFFFFF) res = FR_DISK_ERR; + } + fp->clust = clst; + if (res == FR_OK && ofs % SS(fs)) { /* Fill sector buffer if not on the sector boundary */ + sc = clst2sect(fs, clst); + if (sc == 0) { + res = FR_INT_ERR; + } else { + fp->sect = sc + (DWORD)(ofs / SS(fs)); +#if !FF_FS_TINY + if (disk_read(fs->pdrv, fp->buf, fp->sect, 1) != RES_OK) res = FR_DISK_ERR; +#endif + } + } +#if FF_FS_LOCK != 0 + if (res != FR_OK) dec_lock(fp->obj.lockid); /* Decrement file open counter if seek failed */ +#endif + } +#endif + } + + FREE_NAMBUF(); + } + + if (res != FR_OK) fp->obj.fs = 0; /* Invalidate file object on error */ + + LEAVE_FF(fs, res); +} + + + + +/*-----------------------------------------------------------------------*/ +/* Read File */ +/*-----------------------------------------------------------------------*/ + +FRESULT f_read ( + FIL* fp, /* Open file to be read */ + void* buff, /* Data buffer to store the read data */ + UINT btr, /* Number of bytes to read */ + UINT* br /* Number of bytes read */ +) +{ + FRESULT res; + FATFS *fs; + DWORD clst; + LBA_t sect; + FSIZE_t remain; + UINT rcnt, cc, csect; + BYTE *rbuff = (BYTE*)buff; + + + *br = 0; /* Clear read byte counter */ + res = validate(&fp->obj, &fs); /* Check validity of the file object */ + if (res != FR_OK || (res = (FRESULT)fp->err) != FR_OK) LEAVE_FF(fs, res); /* Check validity */ + if (!(fp->flag & FA_READ)) LEAVE_FF(fs, FR_DENIED); /* Check access mode */ + remain = fp->obj.objsize - fp->fptr; + if (btr > remain) btr = (UINT)remain; /* Truncate btr by remaining bytes */ + + for ( ; btr > 0; btr -= rcnt, *br += rcnt, rbuff += rcnt, fp->fptr += rcnt) { /* Repeat until btr bytes read */ + if (fp->fptr % SS(fs) == 0) { /* On the sector boundary? */ + csect = (UINT)(fp->fptr / SS(fs) & (fs->csize - 1)); /* Sector offset in the cluster */ + if (csect == 0) { /* On the cluster boundary? */ + if (fp->fptr == 0) { /* On the top of the file? */ + clst = fp->obj.sclust; /* Follow cluster chain from the origin */ + } else { /* Middle or end of the file */ +#if FF_USE_FASTSEEK + if (fp->cltbl) { + clst = clmt_clust(fp, fp->fptr); /* Get cluster# from the CLMT */ + } else +#endif + { + clst = get_fat(&fp->obj, fp->clust); /* Follow cluster chain on the FAT */ + } + } + if (clst < 2) ABORT(fs, FR_INT_ERR); + if (clst == 0xFFFFFFFF) ABORT(fs, FR_DISK_ERR); + fp->clust = clst; /* Update current cluster */ + } + sect = clst2sect(fs, fp->clust); /* Get current sector */ + if (sect == 0) ABORT(fs, FR_INT_ERR); + sect += csect; + cc = btr / SS(fs); /* When remaining bytes >= sector size, */ + if (cc > 0) { /* Read maximum contiguous sectors directly */ + if (csect + cc > fs->csize) { /* Clip at cluster boundary */ + cc = fs->csize - csect; + } + if (disk_read(fs->pdrv, rbuff, sect, cc) != RES_OK) ABORT(fs, FR_DISK_ERR); +#if !FF_FS_READONLY && FF_FS_MINIMIZE <= 2 /* Replace one of the read sectors with cached data if it contains a dirty sector */ +#if FF_FS_TINY + if (fs->wflag && fs->winsect - sect < cc) { + memcpy(rbuff + ((fs->winsect - sect) * SS(fs)), fs->win, SS(fs)); + } +#else + if ((fp->flag & FA_DIRTY) && fp->sect - sect < cc) { + memcpy(rbuff + ((fp->sect - sect) * SS(fs)), fp->buf, SS(fs)); + } +#endif +#endif + rcnt = SS(fs) * cc; /* Number of bytes transferred */ + continue; + } +#if !FF_FS_TINY + if (fp->sect != sect) { /* Load data sector if not in cache */ +#if !FF_FS_READONLY + if (fp->flag & FA_DIRTY) { /* Write-back dirty sector cache */ + if (disk_write(fs->pdrv, fp->buf, fp->sect, 1) != RES_OK) ABORT(fs, FR_DISK_ERR); + fp->flag &= (BYTE)~FA_DIRTY; + } +#endif + if (disk_read(fs->pdrv, fp->buf, sect, 1) != RES_OK) ABORT(fs, FR_DISK_ERR); /* Fill sector cache */ + } +#endif + fp->sect = sect; + } + rcnt = SS(fs) - (UINT)fp->fptr % SS(fs); /* Number of bytes remains in the sector */ + if (rcnt > btr) rcnt = btr; /* Clip it by btr if needed */ +#if FF_FS_TINY + if (move_window(fs, fp->sect) != FR_OK) ABORT(fs, FR_DISK_ERR); /* Move sector window */ + memcpy(rbuff, fs->win + fp->fptr % SS(fs), rcnt); /* Extract partial sector */ +#else + memcpy(rbuff, fp->buf + fp->fptr % SS(fs), rcnt); /* Extract partial sector */ +#endif + } + + LEAVE_FF(fs, FR_OK); +} + + + + +#if !FF_FS_READONLY +/*-----------------------------------------------------------------------*/ +/* Write File */ +/*-----------------------------------------------------------------------*/ + +FRESULT f_write ( + FIL* fp, /* Open file to be written */ + const void* buff, /* Data to be written */ + UINT btw, /* Number of bytes to write */ + UINT* bw /* Number of bytes written */ +) +{ + FRESULT res; + FATFS *fs; + DWORD clst; + LBA_t sect; + UINT wcnt, cc, csect; + const BYTE *wbuff = (const BYTE*)buff; + + + *bw = 0; /* Clear write byte counter */ + res = validate(&fp->obj, &fs); /* Check validity of the file object */ + if (res != FR_OK || (res = (FRESULT)fp->err) != FR_OK) LEAVE_FF(fs, res); /* Check validity */ + if (!(fp->flag & FA_WRITE)) LEAVE_FF(fs, FR_DENIED); /* Check access mode */ + + /* Check fptr wrap-around (file size cannot reach 4 GiB at FAT volume) */ + if ((!FF_FS_EXFAT || fs->fs_type != FS_EXFAT) && (DWORD)(fp->fptr + btw) < (DWORD)fp->fptr) { + btw = (UINT)(0xFFFFFFFF - (DWORD)fp->fptr); + } + + for ( ; btw > 0; btw -= wcnt, *bw += wcnt, wbuff += wcnt, fp->fptr += wcnt, fp->obj.objsize = (fp->fptr > fp->obj.objsize) ? fp->fptr : fp->obj.objsize) { /* Repeat until all data written */ + if (fp->fptr % SS(fs) == 0) { /* On the sector boundary? */ + csect = (UINT)(fp->fptr / SS(fs)) & (fs->csize - 1); /* Sector offset in the cluster */ + if (csect == 0) { /* On the cluster boundary? */ + if (fp->fptr == 0) { /* On the top of the file? */ + clst = fp->obj.sclust; /* Follow from the origin */ + if (clst == 0) { /* If no cluster is allocated, */ + clst = create_chain(&fp->obj, 0); /* create a new cluster chain */ + } + } else { /* On the middle or end of the file */ +#if FF_USE_FASTSEEK + if (fp->cltbl) { + clst = clmt_clust(fp, fp->fptr); /* Get cluster# from the CLMT */ + } else +#endif + { + clst = create_chain(&fp->obj, fp->clust); /* Follow or stretch cluster chain on the FAT */ + } + } + if (clst == 0) break; /* Could not allocate a new cluster (disk full) */ + if (clst == 1) ABORT(fs, FR_INT_ERR); + if (clst == 0xFFFFFFFF) ABORT(fs, FR_DISK_ERR); + fp->clust = clst; /* Update current cluster */ + if (fp->obj.sclust == 0) fp->obj.sclust = clst; /* Set start cluster if the first write */ + } +#if FF_FS_TINY + if (fs->winsect == fp->sect && sync_window(fs) != FR_OK) ABORT(fs, FR_DISK_ERR); /* Write-back sector cache */ +#else + if (fp->flag & FA_DIRTY) { /* Write-back sector cache */ + if (disk_write(fs->pdrv, fp->buf, fp->sect, 1) != RES_OK) ABORT(fs, FR_DISK_ERR); + fp->flag &= (BYTE)~FA_DIRTY; + } +#endif + sect = clst2sect(fs, fp->clust); /* Get current sector */ + if (sect == 0) ABORT(fs, FR_INT_ERR); + sect += csect; + cc = btw / SS(fs); /* When remaining bytes >= sector size, */ + if (cc > 0) { /* Write maximum contiguous sectors directly */ + if (csect + cc > fs->csize) { /* Clip at cluster boundary */ + cc = fs->csize - csect; + } + if (disk_write(fs->pdrv, wbuff, sect, cc) != RES_OK) ABORT(fs, FR_DISK_ERR); +#if FF_FS_MINIMIZE <= 2 +#if FF_FS_TINY + if (fs->winsect - sect < cc) { /* Refill sector cache if it gets invalidated by the direct write */ + memcpy(fs->win, wbuff + ((fs->winsect - sect) * SS(fs)), SS(fs)); + fs->wflag = 0; + } +#else + if (fp->sect - sect < cc) { /* Refill sector cache if it gets invalidated by the direct write */ + memcpy(fp->buf, wbuff + ((fp->sect - sect) * SS(fs)), SS(fs)); + fp->flag &= (BYTE)~FA_DIRTY; + } +#endif +#endif + wcnt = SS(fs) * cc; /* Number of bytes transferred */ + continue; + } +#if FF_FS_TINY + if (fp->fptr >= fp->obj.objsize) { /* Avoid silly cache filling on the growing edge */ + if (sync_window(fs) != FR_OK) ABORT(fs, FR_DISK_ERR); + fs->winsect = sect; + } +#else + if (fp->sect != sect && /* Fill sector cache with file data */ + fp->fptr < fp->obj.objsize && + disk_read(fs->pdrv, fp->buf, sect, 1) != RES_OK) { + ABORT(fs, FR_DISK_ERR); + } +#endif + fp->sect = sect; + } + wcnt = SS(fs) - (UINT)fp->fptr % SS(fs); /* Number of bytes remains in the sector */ + if (wcnt > btw) wcnt = btw; /* Clip it by btw if needed */ +#if FF_FS_TINY + if (move_window(fs, fp->sect) != FR_OK) ABORT(fs, FR_DISK_ERR); /* Move sector window */ + memcpy(fs->win + fp->fptr % SS(fs), wbuff, wcnt); /* Fit data to the sector */ + fs->wflag = 1; +#else + memcpy(fp->buf + fp->fptr % SS(fs), wbuff, wcnt); /* Fit data to the sector */ + fp->flag |= FA_DIRTY; +#endif + } + + fp->flag |= FA_MODIFIED; /* Set file change flag */ + + LEAVE_FF(fs, FR_OK); +} + + + + +/*-----------------------------------------------------------------------*/ +/* Synchronize the File */ +/*-----------------------------------------------------------------------*/ + +FRESULT f_sync ( + FIL* fp /* Open file to be synced */ +) +{ + FRESULT res; + FATFS *fs; + DWORD tm; + BYTE *dir; + + + res = validate(&fp->obj, &fs); /* Check validity of the file object */ + if (res == FR_OK) { + if (fp->flag & FA_MODIFIED) { /* Is there any change to the file? */ +#if !FF_FS_TINY + if (fp->flag & FA_DIRTY) { /* Write-back cached data if needed */ + if (disk_write(fs->pdrv, fp->buf, fp->sect, 1) != RES_OK) LEAVE_FF(fs, FR_DISK_ERR); + fp->flag &= (BYTE)~FA_DIRTY; + } +#endif + /* Update the directory entry */ + tm = GET_FATTIME(); /* Modified time */ +#if FF_FS_EXFAT + if (fs->fs_type == FS_EXFAT) { + res = fill_first_frag(&fp->obj); /* Fill first fragment on the FAT if needed */ + if (res == FR_OK) { + res = fill_last_frag(&fp->obj, fp->clust, 0xFFFFFFFF); /* Fill last fragment on the FAT if needed */ + } + if (res == FR_OK) { + DIR dj; + DEF_NAMBUF + + INIT_NAMBUF(fs); + res = load_obj_xdir(&dj, &fp->obj); /* Load directory entry block */ + if (res == FR_OK) { + fs->dirbuf[XDIR_Attr] |= AM_ARC; /* Set archive attribute to indicate that the file has been changed */ + fs->dirbuf[XDIR_GenFlags] = fp->obj.stat | 1; /* Update file allocation information */ + st_dword(fs->dirbuf + XDIR_FstClus, fp->obj.sclust); /* Update start cluster */ + st_qword(fs->dirbuf + XDIR_FileSize, fp->obj.objsize); /* Update file size */ + st_qword(fs->dirbuf + XDIR_ValidFileSize, fp->obj.objsize); /* (FatFs does not support Valid File Size feature) */ + st_dword(fs->dirbuf + XDIR_ModTime, tm); /* Update modified time */ + fs->dirbuf[XDIR_ModTime10] = 0; + st_dword(fs->dirbuf + XDIR_AccTime, 0); + res = store_xdir(&dj); /* Restore it to the directory */ + if (res == FR_OK) { + res = sync_fs(fs); + fp->flag &= (BYTE)~FA_MODIFIED; + } + } + FREE_NAMBUF(); + } + } else +#endif + { + res = move_window(fs, fp->dir_sect); + if (res == FR_OK) { + dir = fp->dir_ptr; + dir[DIR_Attr] |= AM_ARC; /* Set archive attribute to indicate that the file has been changed */ + st_clust(fp->obj.fs, dir, fp->obj.sclust); /* Update file allocation information */ + st_dword(dir + DIR_FileSize, (DWORD)fp->obj.objsize); /* Update file size */ + st_dword(dir + DIR_ModTime, tm); /* Update modified time */ + st_word(dir + DIR_LstAccDate, 0); + fs->wflag = 1; + res = sync_fs(fs); /* Restore it to the directory */ + fp->flag &= (BYTE)~FA_MODIFIED; + } + } + } + } + + LEAVE_FF(fs, res); +} + +#endif /* !FF_FS_READONLY */ + + + + +/*-----------------------------------------------------------------------*/ +/* Close File */ +/*-----------------------------------------------------------------------*/ + +FRESULT f_close ( + FIL* fp /* Open file to be closed */ +) +{ + FRESULT res; + FATFS *fs; + +#if !FF_FS_READONLY + res = f_sync(fp); /* Flush cached data */ + if (res == FR_OK) +#endif + { + res = validate(&fp->obj, &fs); /* Lock volume */ + if (res == FR_OK) { +#if FF_FS_LOCK != 0 + res = dec_lock(fp->obj.lockid); /* Decrement file open counter */ + if (res == FR_OK) fp->obj.fs = 0; /* Invalidate file object */ +#else + fp->obj.fs = 0; /* Invalidate file object */ +#endif +#if FF_FS_REENTRANT + unlock_fs(fs, FR_OK); /* Unlock volume */ +#endif + } + } + return res; +} + + + + +#if FF_FS_RPATH >= 1 +/*-----------------------------------------------------------------------*/ +/* Change Current Directory or Current Drive, Get Current Directory */ +/*-----------------------------------------------------------------------*/ + +FRESULT f_chdrive ( + const TCHAR* path /* Drive number to set */ +) +{ + int vol; + + + /* Get logical drive number */ + vol = get_ldnumber(&path); + if (vol < 0) return FR_INVALID_DRIVE; + CurrVol = (BYTE)vol; /* Set it as current volume */ + + return FR_OK; +} + + + +FRESULT f_chdir ( + const TCHAR* path /* Pointer to the directory path */ +) +{ +#if FF_STR_VOLUME_ID == 2 + UINT i; +#endif + FRESULT res; + DIR dj; + FATFS *fs; + DEF_NAMBUF + + + /* Get logical drive */ + res = mount_volume(&path, &fs, 0); + if (res == FR_OK) { + dj.obj.fs = fs; + INIT_NAMBUF(fs); + res = follow_path(&dj, path); /* Follow the path */ + if (res == FR_OK) { /* Follow completed */ + if (dj.fn[NSFLAG] & NS_NONAME) { /* Is it the start directory itself? */ + fs->cdir = dj.obj.sclust; +#if FF_FS_EXFAT + if (fs->fs_type == FS_EXFAT) { + fs->cdc_scl = dj.obj.c_scl; + fs->cdc_size = dj.obj.c_size; + fs->cdc_ofs = dj.obj.c_ofs; + } +#endif + } else { + if (dj.obj.attr & AM_DIR) { /* It is a sub-directory */ +#if FF_FS_EXFAT + if (fs->fs_type == FS_EXFAT) { + fs->cdir = ld_dword(fs->dirbuf + XDIR_FstClus); /* Sub-directory cluster */ + fs->cdc_scl = dj.obj.sclust; /* Save containing directory information */ + fs->cdc_size = ((DWORD)dj.obj.objsize & 0xFFFFFF00) | dj.obj.stat; + fs->cdc_ofs = dj.blk_ofs; + } else +#endif + { + fs->cdir = ld_clust(fs, dj.dir); /* Sub-directory cluster */ + } + } else { + res = FR_NO_PATH; /* Reached but a file */ + } + } + } + FREE_NAMBUF(); + if (res == FR_NO_FILE) res = FR_NO_PATH; +#if FF_STR_VOLUME_ID == 2 /* Also current drive is changed if in Unix style volume ID */ + if (res == FR_OK) { + for (i = FF_VOLUMES - 1; i && fs != FatFs[i]; i--) ; /* Set current drive */ + CurrVol = (BYTE)i; + } +#endif + } + + LEAVE_FF(fs, res); +} + + +#if FF_FS_RPATH >= 2 +FRESULT f_getcwd ( + TCHAR* buff, /* Pointer to the directory path */ + UINT len /* Size of buff in unit of TCHAR */ +) +{ + FRESULT res; + DIR dj; + FATFS *fs; + UINT i, n; + DWORD ccl; + TCHAR *tp = buff; +#if FF_VOLUMES >= 2 + UINT vl; +#if FF_STR_VOLUME_ID + const char *vp; +#endif +#endif + FILINFO fno; + DEF_NAMBUF + + + /* Get logical drive */ + buff[0] = 0; /* Set null string to get current volume */ + res = mount_volume((const TCHAR**)&buff, &fs, 0); /* Get current volume */ + if (res == FR_OK) { + dj.obj.fs = fs; + INIT_NAMBUF(fs); + + /* Follow parent directories and create the path */ + i = len; /* Bottom of buffer (directory stack base) */ + if (!FF_FS_EXFAT || fs->fs_type != FS_EXFAT) { /* (Cannot do getcwd on exFAT and returns root path) */ + dj.obj.sclust = fs->cdir; /* Start to follow upper directory from current directory */ + while ((ccl = dj.obj.sclust) != 0) { /* Repeat while current directory is a sub-directory */ + res = dir_sdi(&dj, 1 * SZDIRE); /* Get parent directory */ + if (res != FR_OK) break; + res = move_window(fs, dj.sect); + if (res != FR_OK) break; + dj.obj.sclust = ld_clust(fs, dj.dir); /* Goto parent directory */ + res = dir_sdi(&dj, 0); + if (res != FR_OK) break; + do { /* Find the entry links to the child directory */ + res = DIR_READ_FILE(&dj); + if (res != FR_OK) break; + if (ccl == ld_clust(fs, dj.dir)) break; /* Found the entry */ + res = dir_next(&dj, 0); + } while (res == FR_OK); + if (res == FR_NO_FILE) res = FR_INT_ERR;/* It cannot be 'not found'. */ + if (res != FR_OK) break; + get_fileinfo(&dj, &fno); /* Get the directory name and push it to the buffer */ + for (n = 0; fno.fname[n]; n++) ; /* Name length */ + if (i < n + 1) { /* Insufficient space to store the path name? */ + res = FR_NOT_ENOUGH_CORE; break; + } + while (n) buff[--i] = fno.fname[--n]; /* Stack the name */ + buff[--i] = '/'; + } + } + if (res == FR_OK) { + if (i == len) buff[--i] = '/'; /* Is it the root-directory? */ +#if FF_VOLUMES >= 2 /* Put drive prefix */ + vl = 0; +#if FF_STR_VOLUME_ID >= 1 /* String volume ID */ + for (n = 0, vp = (const char*)VolumeStr[CurrVol]; vp[n]; n++) ; + if (i >= n + 2) { + if (FF_STR_VOLUME_ID == 2) *tp++ = (TCHAR)'/'; + for (vl = 0; vl < n; *tp++ = (TCHAR)vp[vl], vl++) ; + if (FF_STR_VOLUME_ID == 1) *tp++ = (TCHAR)':'; + vl++; + } +#else /* Numeric volume ID */ + if (i >= 3) { + *tp++ = (TCHAR)'0' + CurrVol; + *tp++ = (TCHAR)':'; + vl = 2; + } +#endif + if (vl == 0) res = FR_NOT_ENOUGH_CORE; +#endif + /* Add current directory path */ + if (res == FR_OK) { + do *tp++ = buff[i++]; while (i < len); /* Copy stacked path string */ + } + } + FREE_NAMBUF(); + } + + *tp = 0; + LEAVE_FF(fs, res); +} + +#endif /* FF_FS_RPATH >= 2 */ +#endif /* FF_FS_RPATH >= 1 */ + + + +#if FF_FS_MINIMIZE <= 2 +/*-----------------------------------------------------------------------*/ +/* Seek File Read/Write Pointer */ +/*-----------------------------------------------------------------------*/ + +FRESULT f_lseek ( + FIL* fp, /* Pointer to the file object */ + FSIZE_t ofs /* File pointer from top of file */ +) +{ + FRESULT res; + FATFS *fs; + DWORD clst, bcs; + LBA_t nsect; + FSIZE_t ifptr; +#if FF_USE_FASTSEEK + DWORD cl, pcl, ncl, tcl, tlen, ulen; + DWORD *tbl; + LBA_t dsc; +#endif + + res = validate(&fp->obj, &fs); /* Check validity of the file object */ + if (res == FR_OK) res = (FRESULT)fp->err; +#if FF_FS_EXFAT && !FF_FS_READONLY + if (res == FR_OK && fs->fs_type == FS_EXFAT) { + res = fill_last_frag(&fp->obj, fp->clust, 0xFFFFFFFF); /* Fill last fragment on the FAT if needed */ + } +#endif + if (res != FR_OK) LEAVE_FF(fs, res); + +#if FF_USE_FASTSEEK + if (fp->cltbl) { /* Fast seek */ + if (ofs == CREATE_LINKMAP) { /* Create CLMT */ + tbl = fp->cltbl; + tlen = *tbl++; ulen = 2; /* Given table size and required table size */ + cl = fp->obj.sclust; /* Origin of the chain */ + if (cl != 0) { + do { + /* Get a fragment */ + tcl = cl; ncl = 0; ulen += 2; /* Top, length and used items */ + do { + pcl = cl; ncl++; + cl = get_fat(&fp->obj, cl); + if (cl <= 1) ABORT(fs, FR_INT_ERR); + if (cl == 0xFFFFFFFF) ABORT(fs, FR_DISK_ERR); + } while (cl == pcl + 1); + if (ulen <= tlen) { /* Store the length and top of the fragment */ + *tbl++ = ncl; *tbl++ = tcl; + } + } while (cl < fs->n_fatent); /* Repeat until end of chain */ + } + *fp->cltbl = ulen; /* Number of items used */ + if (ulen <= tlen) { + *tbl = 0; /* Terminate table */ + } else { + res = FR_NOT_ENOUGH_CORE; /* Given table size is smaller than required */ + } + } else { /* Fast seek */ + if (ofs > fp->obj.objsize) ofs = fp->obj.objsize; /* Clip offset at the file size */ + fp->fptr = ofs; /* Set file pointer */ + if (ofs > 0) { + fp->clust = clmt_clust(fp, ofs - 1); + dsc = clst2sect(fs, fp->clust); + if (dsc == 0) ABORT(fs, FR_INT_ERR); + dsc += (DWORD)((ofs - 1) / SS(fs)) & (fs->csize - 1); + if (fp->fptr % SS(fs) && dsc != fp->sect) { /* Refill sector cache if needed */ +#if !FF_FS_TINY +#if !FF_FS_READONLY + if (fp->flag & FA_DIRTY) { /* Write-back dirty sector cache */ + if (disk_write(fs->pdrv, fp->buf, fp->sect, 1) != RES_OK) ABORT(fs, FR_DISK_ERR); + fp->flag &= (BYTE)~FA_DIRTY; + } +#endif + if (disk_read(fs->pdrv, fp->buf, dsc, 1) != RES_OK) ABORT(fs, FR_DISK_ERR); /* Load current sector */ +#endif + fp->sect = dsc; + } + } + } + } else +#endif + + /* Normal Seek */ + { +#if FF_FS_EXFAT + if (fs->fs_type != FS_EXFAT && ofs >= 0x100000000) ofs = 0xFFFFFFFF; /* Clip at 4 GiB - 1 if at FATxx */ +#endif + if (ofs > fp->obj.objsize && (FF_FS_READONLY || !(fp->flag & FA_WRITE))) { /* In read-only mode, clip offset with the file size */ + ofs = fp->obj.objsize; + } + ifptr = fp->fptr; + fp->fptr = nsect = 0; + if (ofs > 0) { + bcs = (DWORD)fs->csize * SS(fs); /* Cluster size (byte) */ + if (ifptr > 0 && + (ofs - 1) / bcs >= (ifptr - 1) / bcs) { /* When seek to same or following cluster, */ + fp->fptr = (ifptr - 1) & ~(FSIZE_t)(bcs - 1); /* start from the current cluster */ + ofs -= fp->fptr; + clst = fp->clust; + } else { /* When seek to back cluster, */ + clst = fp->obj.sclust; /* start from the first cluster */ +#if !FF_FS_READONLY + if (clst == 0) { /* If no cluster chain, create a new chain */ + clst = create_chain(&fp->obj, 0); + if (clst == 1) ABORT(fs, FR_INT_ERR); + if (clst == 0xFFFFFFFF) ABORT(fs, FR_DISK_ERR); + fp->obj.sclust = clst; + } +#endif + fp->clust = clst; + } + if (clst != 0) { + while (ofs > bcs) { /* Cluster following loop */ + ofs -= bcs; fp->fptr += bcs; +#if !FF_FS_READONLY + if (fp->flag & FA_WRITE) { /* Check if in write mode or not */ + if (FF_FS_EXFAT && fp->fptr > fp->obj.objsize) { /* No FAT chain object needs correct objsize to generate FAT value */ + fp->obj.objsize = fp->fptr; + fp->flag |= FA_MODIFIED; + } + clst = create_chain(&fp->obj, clst); /* Follow chain with forceed stretch */ + if (clst == 0) { /* Clip file size in case of disk full */ + ofs = 0; break; + } + } else +#endif + { + clst = get_fat(&fp->obj, clst); /* Follow cluster chain if not in write mode */ + } + if (clst == 0xFFFFFFFF) ABORT(fs, FR_DISK_ERR); + if (clst <= 1 || clst >= fs->n_fatent) ABORT(fs, FR_INT_ERR); + fp->clust = clst; + } + fp->fptr += ofs; + if (ofs % SS(fs)) { + nsect = clst2sect(fs, clst); /* Current sector */ + if (nsect == 0) ABORT(fs, FR_INT_ERR); + nsect += (DWORD)(ofs / SS(fs)); + } + } + } + if (!FF_FS_READONLY && fp->fptr > fp->obj.objsize) { /* Set file change flag if the file size is extended */ + fp->obj.objsize = fp->fptr; + fp->flag |= FA_MODIFIED; + } + if (fp->fptr % SS(fs) && nsect != fp->sect) { /* Fill sector cache if needed */ +#if !FF_FS_TINY +#if !FF_FS_READONLY + if (fp->flag & FA_DIRTY) { /* Write-back dirty sector cache */ + if (disk_write(fs->pdrv, fp->buf, fp->sect, 1) != RES_OK) ABORT(fs, FR_DISK_ERR); + fp->flag &= (BYTE)~FA_DIRTY; + } +#endif + if (disk_read(fs->pdrv, fp->buf, nsect, 1) != RES_OK) ABORT(fs, FR_DISK_ERR); /* Fill sector cache */ +#endif + fp->sect = nsect; + } + } + + LEAVE_FF(fs, res); +} + + + +#if FF_FS_MINIMIZE <= 1 +/*-----------------------------------------------------------------------*/ +/* Create a Directory Object */ +/*-----------------------------------------------------------------------*/ + +FRESULT f_opendir ( + DIR* dp, /* Pointer to directory object to create */ + const TCHAR* path /* Pointer to the directory path */ +) +{ + FRESULT res; + FATFS *fs; + DEF_NAMBUF + + + if (!dp) return FR_INVALID_OBJECT; + + /* Get logical drive */ + res = mount_volume(&path, &fs, 0); + if (res == FR_OK) { + dp->obj.fs = fs; + INIT_NAMBUF(fs); + res = follow_path(dp, path); /* Follow the path to the directory */ + if (res == FR_OK) { /* Follow completed */ + if (!(dp->fn[NSFLAG] & NS_NONAME)) { /* It is not the origin directory itself */ + if (dp->obj.attr & AM_DIR) { /* This object is a sub-directory */ +#if FF_FS_EXFAT + if (fs->fs_type == FS_EXFAT) { + dp->obj.c_scl = dp->obj.sclust; /* Get containing directory inforamation */ + dp->obj.c_size = ((DWORD)dp->obj.objsize & 0xFFFFFF00) | dp->obj.stat; + dp->obj.c_ofs = dp->blk_ofs; + init_alloc_info(fs, &dp->obj); /* Get object allocation info */ + } else +#endif + { + dp->obj.sclust = ld_clust(fs, dp->dir); /* Get object allocation info */ + } + } else { /* This object is a file */ + res = FR_NO_PATH; + } + } + if (res == FR_OK) { + dp->obj.id = fs->id; + res = dir_sdi(dp, 0); /* Rewind directory */ +#if FF_FS_LOCK != 0 + if (res == FR_OK) { + if (dp->obj.sclust != 0) { + dp->obj.lockid = inc_lock(dp, 0); /* Lock the sub directory */ + if (!dp->obj.lockid) res = FR_TOO_MANY_OPEN_FILES; + } else { + dp->obj.lockid = 0; /* Root directory need not to be locked */ + } + } +#endif + } + } + FREE_NAMBUF(); + if (res == FR_NO_FILE) res = FR_NO_PATH; + } + if (res != FR_OK) dp->obj.fs = 0; /* Invalidate the directory object if function faild */ + + LEAVE_FF(fs, res); +} + + + + +/*-----------------------------------------------------------------------*/ +/* Close Directory */ +/*-----------------------------------------------------------------------*/ + +FRESULT f_closedir ( + DIR *dp /* Pointer to the directory object to be closed */ +) +{ + FRESULT res; + FATFS *fs; + + + res = validate(&dp->obj, &fs); /* Check validity of the file object */ + if (res == FR_OK) { +#if FF_FS_LOCK != 0 + if (dp->obj.lockid) res = dec_lock(dp->obj.lockid); /* Decrement sub-directory open counter */ + if (res == FR_OK) dp->obj.fs = 0; /* Invalidate directory object */ +#else + dp->obj.fs = 0; /* Invalidate directory object */ +#endif +#if FF_FS_REENTRANT + unlock_fs(fs, FR_OK); /* Unlock volume */ +#endif + } + return res; +} + + + + +/*-----------------------------------------------------------------------*/ +/* Read Directory Entries in Sequence */ +/*-----------------------------------------------------------------------*/ + +FRESULT f_readdir ( + DIR* dp, /* Pointer to the open directory object */ + FILINFO* fno /* Pointer to file information to return */ +) +{ + FRESULT res; + FATFS *fs; + DEF_NAMBUF + + + res = validate(&dp->obj, &fs); /* Check validity of the directory object */ + if (res == FR_OK) { + if (!fno) { + res = dir_sdi(dp, 0); /* Rewind the directory object */ + } else { + INIT_NAMBUF(fs); + res = DIR_READ_FILE(dp); /* Read an item */ + if (res == FR_NO_FILE) res = FR_OK; /* Ignore end of directory */ + if (res == FR_OK) { /* A valid entry is found */ + get_fileinfo(dp, fno); /* Get the object information */ + res = dir_next(dp, 0); /* Increment index for next */ + if (res == FR_NO_FILE) res = FR_OK; /* Ignore end of directory now */ + } + FREE_NAMBUF(); + } + } + LEAVE_FF(fs, res); +} + + + +#if FF_USE_FIND +/*-----------------------------------------------------------------------*/ +/* Find Next File */ +/*-----------------------------------------------------------------------*/ + +FRESULT f_findnext ( + DIR* dp, /* Pointer to the open directory object */ + FILINFO* fno /* Pointer to the file information structure */ +) +{ + FRESULT res; + + + for (;;) { + res = f_readdir(dp, fno); /* Get a directory item */ + if (res != FR_OK || !fno || !fno->fname[0]) break; /* Terminate if any error or end of directory */ + if (pattern_match(dp->pat, fno->fname, 0, FIND_RECURS)) break; /* Test for the file name */ +#if FF_USE_LFN && FF_USE_FIND == 2 + if (pattern_match(dp->pat, fno->altname, 0, FIND_RECURS)) break; /* Test for alternative name if exist */ +#endif + } + return res; +} + + + +/*-----------------------------------------------------------------------*/ +/* Find First File */ +/*-----------------------------------------------------------------------*/ + +FRESULT f_findfirst ( + DIR* dp, /* Pointer to the blank directory object */ + FILINFO* fno, /* Pointer to the file information structure */ + const TCHAR* path, /* Pointer to the directory to open */ + const TCHAR* pattern /* Pointer to the matching pattern */ +) +{ + FRESULT res; + + + dp->pat = pattern; /* Save pointer to pattern string */ + res = f_opendir(dp, path); /* Open the target directory */ + if (res == FR_OK) { + res = f_findnext(dp, fno); /* Find the first item */ + } + return res; +} + +#endif /* FF_USE_FIND */ + + + +#if FF_FS_MINIMIZE == 0 +/*-----------------------------------------------------------------------*/ +/* Get File Status */ +/*-----------------------------------------------------------------------*/ + +FRESULT f_stat ( + const TCHAR* path, /* Pointer to the file path */ + FILINFO* fno /* Pointer to file information to return */ +) +{ + FRESULT res; + DIR dj; + DEF_NAMBUF + + + /* Get logical drive */ + res = mount_volume(&path, &dj.obj.fs, 0); + if (res == FR_OK) { + INIT_NAMBUF(dj.obj.fs); + res = follow_path(&dj, path); /* Follow the file path */ + if (res == FR_OK) { /* Follow completed */ + if (dj.fn[NSFLAG] & NS_NONAME) { /* It is origin directory */ + res = FR_INVALID_NAME; + } else { /* Found an object */ + if (fno) get_fileinfo(&dj, fno); + } + } + FREE_NAMBUF(); + } + + LEAVE_FF(dj.obj.fs, res); +} + + + +#if !FF_FS_READONLY +/*-----------------------------------------------------------------------*/ +/* Get Number of Free Clusters */ +/*-----------------------------------------------------------------------*/ + +FRESULT f_getfree ( + const TCHAR* path, /* Logical drive number */ + DWORD* nclst, /* Pointer to a variable to return number of free clusters */ + FATFS** fatfs /* Pointer to return pointer to corresponding filesystem object */ +) +{ + FRESULT res; + FATFS *fs; + DWORD nfree, clst, stat; + LBA_t sect; + UINT i; + FFOBJID obj; + + + /* Get logical drive */ + res = mount_volume(&path, &fs, 0); + if (res == FR_OK) { + *fatfs = fs; /* Return ptr to the fs object */ + /* If free_clst is valid, return it without full FAT scan */ + if (fs->free_clst <= fs->n_fatent - 2) { + *nclst = fs->free_clst; + } else { + /* Scan FAT to obtain number of free clusters */ + nfree = 0; + if (fs->fs_type == FS_FAT12) { /* FAT12: Scan bit field FAT entries */ + clst = 2; obj.fs = fs; + do { + stat = get_fat(&obj, clst); + if (stat == 0xFFFFFFFF) { res = FR_DISK_ERR; break; } + if (stat == 1) { res = FR_INT_ERR; break; } + if (stat == 0) nfree++; + } while (++clst < fs->n_fatent); + } else { +#if FF_FS_EXFAT + if (fs->fs_type == FS_EXFAT) { /* exFAT: Scan allocation bitmap */ + BYTE bm; + UINT b; + + clst = fs->n_fatent - 2; /* Number of clusters */ + sect = fs->bitbase; /* Bitmap sector */ + i = 0; /* Offset in the sector */ + do { /* Counts numbuer of bits with zero in the bitmap */ + if (i == 0) { + res = move_window(fs, sect++); + if (res != FR_OK) break; + } + for (b = 8, bm = fs->win[i]; b && clst; b--, clst--) { + if (!(bm & 1)) nfree++; + bm >>= 1; + } + i = (i + 1) % SS(fs); + } while (clst); + } else +#endif + { /* FAT16/32: Scan WORD/DWORD FAT entries */ + clst = fs->n_fatent; /* Number of entries */ + sect = fs->fatbase; /* Top of the FAT */ + i = 0; /* Offset in the sector */ + do { /* Counts numbuer of entries with zero in the FAT */ + if (i == 0) { + res = move_window(fs, sect++); + if (res != FR_OK) break; + } + if (fs->fs_type == FS_FAT16) { + if (ld_word(fs->win + i) == 0) nfree++; + i += 2; + } else { + if ((ld_dword(fs->win + i) & 0x0FFFFFFF) == 0) nfree++; + i += 4; + } + i %= SS(fs); + } while (--clst); + } + } + if (res == FR_OK) { /* Update parameters if succeeded */ + *nclst = nfree; /* Return the free clusters */ + fs->free_clst = nfree; /* Now free_clst is valid */ + fs->fsi_flag |= 1; /* FAT32: FSInfo is to be updated */ + } + } + } + + LEAVE_FF(fs, res); +} + + + + +/*-----------------------------------------------------------------------*/ +/* Truncate File */ +/*-----------------------------------------------------------------------*/ + +FRESULT f_truncate ( + FIL* fp /* Pointer to the file object */ +) +{ + FRESULT res; + FATFS *fs; + DWORD ncl; + + + res = validate(&fp->obj, &fs); /* Check validity of the file object */ + if (res != FR_OK || (res = (FRESULT)fp->err) != FR_OK) LEAVE_FF(fs, res); + if (!(fp->flag & FA_WRITE)) LEAVE_FF(fs, FR_DENIED); /* Check access mode */ + + if (fp->fptr < fp->obj.objsize) { /* Process when fptr is not on the eof */ + if (fp->fptr == 0) { /* When set file size to zero, remove entire cluster chain */ + res = remove_chain(&fp->obj, fp->obj.sclust, 0); + fp->obj.sclust = 0; + } else { /* When truncate a part of the file, remove remaining clusters */ + ncl = get_fat(&fp->obj, fp->clust); + res = FR_OK; + if (ncl == 0xFFFFFFFF) res = FR_DISK_ERR; + if (ncl == 1) res = FR_INT_ERR; + if (res == FR_OK && ncl < fs->n_fatent) { + res = remove_chain(&fp->obj, ncl, fp->clust); + } + } + fp->obj.objsize = fp->fptr; /* Set file size to current read/write point */ + fp->flag |= FA_MODIFIED; +#if !FF_FS_TINY + if (res == FR_OK && (fp->flag & FA_DIRTY)) { + if (disk_write(fs->pdrv, fp->buf, fp->sect, 1) != RES_OK) { + res = FR_DISK_ERR; + } else { + fp->flag &= (BYTE)~FA_DIRTY; + } + } +#endif + if (res != FR_OK) ABORT(fs, res); + } + + LEAVE_FF(fs, res); +} + + + + +/*-----------------------------------------------------------------------*/ +/* Delete a File/Directory */ +/*-----------------------------------------------------------------------*/ + +FRESULT f_unlink ( + const TCHAR* path /* Pointer to the file or directory path */ +) +{ + FRESULT res; + DIR dj, sdj; + DWORD dclst = 0; + FATFS *fs; +#if FF_FS_EXFAT + FFOBJID obj; +#endif + DEF_NAMBUF + + + /* Get logical drive */ + res = mount_volume(&path, &fs, FA_WRITE); + if (res == FR_OK) { + dj.obj.fs = fs; + INIT_NAMBUF(fs); + res = follow_path(&dj, path); /* Follow the file path */ + if (FF_FS_RPATH && res == FR_OK && (dj.fn[NSFLAG] & NS_DOT)) { + res = FR_INVALID_NAME; /* Cannot remove dot entry */ + } +#if FF_FS_LOCK != 0 + if (res == FR_OK) res = chk_lock(&dj, 2); /* Check if it is an open object */ +#endif + if (res == FR_OK) { /* The object is accessible */ + if (dj.fn[NSFLAG] & NS_NONAME) { + res = FR_INVALID_NAME; /* Cannot remove the origin directory */ + } else { + if (dj.obj.attr & AM_RDO) { + res = FR_DENIED; /* Cannot remove R/O object */ + } + } + if (res == FR_OK) { +#if FF_FS_EXFAT + obj.fs = fs; + if (fs->fs_type == FS_EXFAT) { + init_alloc_info(fs, &obj); + dclst = obj.sclust; + } else +#endif + { + dclst = ld_clust(fs, dj.dir); + } + if (dj.obj.attr & AM_DIR) { /* Is it a sub-directory? */ +#if FF_FS_RPATH != 0 + if (dclst == fs->cdir) { /* Is it the current directory? */ + res = FR_DENIED; + } else +#endif + { + sdj.obj.fs = fs; /* Open the sub-directory */ + sdj.obj.sclust = dclst; +#if FF_FS_EXFAT + if (fs->fs_type == FS_EXFAT) { + sdj.obj.objsize = obj.objsize; + sdj.obj.stat = obj.stat; + } +#endif + res = dir_sdi(&sdj, 0); + if (res == FR_OK) { + res = DIR_READ_FILE(&sdj); /* Test if the directory is empty */ + if (res == FR_OK) res = FR_DENIED; /* Not empty? */ + if (res == FR_NO_FILE) res = FR_OK; /* Empty? */ + } + } + } + } + if (res == FR_OK) { + res = dir_remove(&dj); /* Remove the directory entry */ + if (res == FR_OK && dclst != 0) { /* Remove the cluster chain if exist */ +#if FF_FS_EXFAT + res = remove_chain(&obj, dclst, 0); +#else + res = remove_chain(&dj.obj, dclst, 0); +#endif + } + if (res == FR_OK) res = sync_fs(fs); + } + } + FREE_NAMBUF(); + } + + LEAVE_FF(fs, res); +} + + + + +/*-----------------------------------------------------------------------*/ +/* Create a Directory */ +/*-----------------------------------------------------------------------*/ + +FRESULT f_mkdir ( + const TCHAR* path /* Pointer to the directory path */ +) +{ + FRESULT res; + DIR dj; + FFOBJID sobj; + FATFS *fs; + DWORD dcl, pcl, tm; + DEF_NAMBUF + + + res = mount_volume(&path, &fs, FA_WRITE); /* Get logical drive */ + if (res == FR_OK) { + dj.obj.fs = fs; + INIT_NAMBUF(fs); + res = follow_path(&dj, path); /* Follow the file path */ + if (res == FR_OK) res = FR_EXIST; /* Name collision? */ + if (FF_FS_RPATH && res == FR_NO_FILE && (dj.fn[NSFLAG] & NS_DOT)) { /* Invalid name? */ + res = FR_INVALID_NAME; + } + if (res == FR_NO_FILE) { /* It is clear to create a new directory */ + sobj.fs = fs; /* New object id to create a new chain */ + dcl = create_chain(&sobj, 0); /* Allocate a cluster for the new directory */ + res = FR_OK; + if (dcl == 0) res = FR_DENIED; /* No space to allocate a new cluster? */ + if (dcl == 1) res = FR_INT_ERR; /* Any insanity? */ + if (dcl == 0xFFFFFFFF) res = FR_DISK_ERR; /* Disk error? */ + tm = GET_FATTIME(); + if (res == FR_OK) { + res = dir_clear(fs, dcl); /* Clean up the new table */ + if (res == FR_OK) { + if (!FF_FS_EXFAT || fs->fs_type != FS_EXFAT) { /* Create dot entries (FAT only) */ + memset(fs->win + DIR_Name, ' ', 11); /* Create "." entry */ + fs->win[DIR_Name] = '.'; + fs->win[DIR_Attr] = AM_DIR; + st_dword(fs->win + DIR_ModTime, tm); + st_clust(fs, fs->win, dcl); + memcpy(fs->win + SZDIRE, fs->win, SZDIRE); /* Create ".." entry */ + fs->win[SZDIRE + 1] = '.'; pcl = dj.obj.sclust; + st_clust(fs, fs->win + SZDIRE, pcl); + fs->wflag = 1; + } + res = dir_register(&dj); /* Register the object to the parent directoy */ + } + } + if (res == FR_OK) { +#if FF_FS_EXFAT + if (fs->fs_type == FS_EXFAT) { /* Initialize directory entry block */ + st_dword(fs->dirbuf + XDIR_ModTime, tm); /* Created time */ + st_dword(fs->dirbuf + XDIR_FstClus, dcl); /* Table start cluster */ + st_dword(fs->dirbuf + XDIR_FileSize, (DWORD)fs->csize * SS(fs)); /* Directory size needs to be valid */ + st_dword(fs->dirbuf + XDIR_ValidFileSize, (DWORD)fs->csize * SS(fs)); + fs->dirbuf[XDIR_GenFlags] = 3; /* Initialize the object flag */ + fs->dirbuf[XDIR_Attr] = AM_DIR; /* Attribute */ + res = store_xdir(&dj); + } else +#endif + { + st_dword(dj.dir + DIR_ModTime, tm); /* Created time */ + st_clust(fs, dj.dir, dcl); /* Table start cluster */ + dj.dir[DIR_Attr] = AM_DIR; /* Attribute */ + fs->wflag = 1; + } + if (res == FR_OK) { + res = sync_fs(fs); + } + } else { + remove_chain(&sobj, dcl, 0); /* Could not register, remove the allocated cluster */ + } + } + FREE_NAMBUF(); + } + + LEAVE_FF(fs, res); +} + + + + +/*-----------------------------------------------------------------------*/ +/* Rename a File/Directory */ +/*-----------------------------------------------------------------------*/ + +FRESULT f_rename ( + const TCHAR* path_old, /* Pointer to the object name to be renamed */ + const TCHAR* path_new /* Pointer to the new name */ +) +{ + FRESULT res; + DIR djo, djn; + FATFS *fs; + BYTE buf[FF_FS_EXFAT ? SZDIRE * 2 : SZDIRE], *dir; + LBA_t sect; + DEF_NAMBUF + + + get_ldnumber(&path_new); /* Snip the drive number of new name off */ + res = mount_volume(&path_old, &fs, FA_WRITE); /* Get logical drive of the old object */ + if (res == FR_OK) { + djo.obj.fs = fs; + INIT_NAMBUF(fs); + res = follow_path(&djo, path_old); /* Check old object */ + if (res == FR_OK && (djo.fn[NSFLAG] & (NS_DOT | NS_NONAME))) res = FR_INVALID_NAME; /* Check validity of name */ +#if FF_FS_LOCK != 0 + if (res == FR_OK) { + res = chk_lock(&djo, 2); + } +#endif + if (res == FR_OK) { /* Object to be renamed is found */ +#if FF_FS_EXFAT + if (fs->fs_type == FS_EXFAT) { /* At exFAT volume */ + BYTE nf, nn; + WORD nh; + + memcpy(buf, fs->dirbuf, SZDIRE * 2); /* Save 85+C0 entry of old object */ + memcpy(&djn, &djo, sizeof djo); + res = follow_path(&djn, path_new); /* Make sure if new object name is not in use */ + if (res == FR_OK) { /* Is new name already in use by any other object? */ + res = (djn.obj.sclust == djo.obj.sclust && djn.dptr == djo.dptr) ? FR_NO_FILE : FR_EXIST; + } + if (res == FR_NO_FILE) { /* It is a valid path and no name collision */ + res = dir_register(&djn); /* Register the new entry */ + if (res == FR_OK) { + nf = fs->dirbuf[XDIR_NumSec]; nn = fs->dirbuf[XDIR_NumName]; + nh = ld_word(fs->dirbuf + XDIR_NameHash); + memcpy(fs->dirbuf, buf, SZDIRE * 2); /* Restore 85+C0 entry */ + fs->dirbuf[XDIR_NumSec] = nf; fs->dirbuf[XDIR_NumName] = nn; + st_word(fs->dirbuf + XDIR_NameHash, nh); + if (!(fs->dirbuf[XDIR_Attr] & AM_DIR)) fs->dirbuf[XDIR_Attr] |= AM_ARC; /* Set archive attribute if it is a file */ +/* Start of critical section where an interruption can cause a cross-link */ + res = store_xdir(&djn); + } + } + } else +#endif + { /* At FAT/FAT32 volume */ + memcpy(buf, djo.dir, SZDIRE); /* Save directory entry of the object */ + memcpy(&djn, &djo, sizeof (DIR)); /* Duplicate the directory object */ + res = follow_path(&djn, path_new); /* Make sure if new object name is not in use */ + if (res == FR_OK) { /* Is new name already in use by any other object? */ + res = (djn.obj.sclust == djo.obj.sclust && djn.dptr == djo.dptr) ? FR_NO_FILE : FR_EXIST; + } + if (res == FR_NO_FILE) { /* It is a valid path and no name collision */ + res = dir_register(&djn); /* Register the new entry */ + if (res == FR_OK) { + dir = djn.dir; /* Copy directory entry of the object except name */ + memcpy(dir + 13, buf + 13, SZDIRE - 13); + dir[DIR_Attr] = buf[DIR_Attr]; + if (!(dir[DIR_Attr] & AM_DIR)) dir[DIR_Attr] |= AM_ARC; /* Set archive attribute if it is a file */ + fs->wflag = 1; + if ((dir[DIR_Attr] & AM_DIR) && djo.obj.sclust != djn.obj.sclust) { /* Update .. entry in the sub-directory if needed */ + sect = clst2sect(fs, ld_clust(fs, dir)); + if (sect == 0) { + res = FR_INT_ERR; + } else { +/* Start of critical section where an interruption can cause a cross-link */ + res = move_window(fs, sect); + dir = fs->win + SZDIRE * 1; /* Ptr to .. entry */ + if (res == FR_OK && dir[1] == '.') { + st_clust(fs, dir, djn.obj.sclust); + fs->wflag = 1; + } + } + } + } + } + } + if (res == FR_OK) { + res = dir_remove(&djo); /* Remove old entry */ + if (res == FR_OK) { + res = sync_fs(fs); + } + } +/* End of the critical section */ + } + FREE_NAMBUF(); + } + + LEAVE_FF(fs, res); +} + +#endif /* !FF_FS_READONLY */ +#endif /* FF_FS_MINIMIZE == 0 */ +#endif /* FF_FS_MINIMIZE <= 1 */ +#endif /* FF_FS_MINIMIZE <= 2 */ + + + +#if FF_USE_CHMOD && !FF_FS_READONLY +/*-----------------------------------------------------------------------*/ +/* Change Attribute */ +/*-----------------------------------------------------------------------*/ + +FRESULT f_chmod ( + const TCHAR* path, /* Pointer to the file path */ + BYTE attr, /* Attribute bits */ + BYTE mask /* Attribute mask to change */ +) +{ + FRESULT res; + DIR dj; + FATFS *fs; + DEF_NAMBUF + + + res = mount_volume(&path, &fs, FA_WRITE); /* Get logical drive */ + if (res == FR_OK) { + dj.obj.fs = fs; + INIT_NAMBUF(fs); + res = follow_path(&dj, path); /* Follow the file path */ + if (res == FR_OK && (dj.fn[NSFLAG] & (NS_DOT | NS_NONAME))) res = FR_INVALID_NAME; /* Check object validity */ + if (res == FR_OK) { + mask &= AM_RDO|AM_HID|AM_SYS|AM_ARC; /* Valid attribute mask */ +#if FF_FS_EXFAT + if (fs->fs_type == FS_EXFAT) { + fs->dirbuf[XDIR_Attr] = (attr & mask) | (fs->dirbuf[XDIR_Attr] & (BYTE)~mask); /* Apply attribute change */ + res = store_xdir(&dj); + } else +#endif + { + dj.dir[DIR_Attr] = (attr & mask) | (dj.dir[DIR_Attr] & (BYTE)~mask); /* Apply attribute change */ + fs->wflag = 1; + } + if (res == FR_OK) { + res = sync_fs(fs); + } + } + FREE_NAMBUF(); + } + + LEAVE_FF(fs, res); +} + + + + +/*-----------------------------------------------------------------------*/ +/* Change Timestamp */ +/*-----------------------------------------------------------------------*/ + +FRESULT f_utime ( + const TCHAR* path, /* Pointer to the file/directory name */ + const FILINFO* fno /* Pointer to the timestamp to be set */ +) +{ + FRESULT res; + DIR dj; + FATFS *fs; + DEF_NAMBUF + + + res = mount_volume(&path, &fs, FA_WRITE); /* Get logical drive */ + if (res == FR_OK) { + dj.obj.fs = fs; + INIT_NAMBUF(fs); + res = follow_path(&dj, path); /* Follow the file path */ + if (res == FR_OK && (dj.fn[NSFLAG] & (NS_DOT | NS_NONAME))) res = FR_INVALID_NAME; /* Check object validity */ + if (res == FR_OK) { +#if FF_FS_EXFAT + if (fs->fs_type == FS_EXFAT) { + st_dword(fs->dirbuf + XDIR_ModTime, (DWORD)fno->fdate << 16 | fno->ftime); + res = store_xdir(&dj); + } else +#endif + { + st_dword(dj.dir + DIR_ModTime, (DWORD)fno->fdate << 16 | fno->ftime); + fs->wflag = 1; + } + if (res == FR_OK) { + res = sync_fs(fs); + } + } + FREE_NAMBUF(); + } + + LEAVE_FF(fs, res); +} + +#endif /* FF_USE_CHMOD && !FF_FS_READONLY */ + + + +#if FF_USE_LABEL +/*-----------------------------------------------------------------------*/ +/* Get Volume Label */ +/*-----------------------------------------------------------------------*/ + +FRESULT f_getlabel ( + const TCHAR* path, /* Logical drive number */ + TCHAR* label, /* Buffer to store the volume label */ + DWORD* vsn /* Variable to store the volume serial number */ +) +{ + FRESULT res; + DIR dj; + FATFS *fs; + UINT si, di; + WCHAR wc; + + /* Get logical drive */ + res = mount_volume(&path, &fs, 0); + + /* Get volume label */ + if (res == FR_OK && label) { + dj.obj.fs = fs; dj.obj.sclust = 0; /* Open root directory */ + res = dir_sdi(&dj, 0); + if (res == FR_OK) { + res = DIR_READ_LABEL(&dj); /* Find a volume label entry */ + if (res == FR_OK) { +#if FF_FS_EXFAT + if (fs->fs_type == FS_EXFAT) { + WCHAR hs; + UINT nw; + + for (si = di = hs = 0; si < dj.dir[XDIR_NumLabel]; si++) { /* Extract volume label from 83 entry */ + wc = ld_word(dj.dir + XDIR_Label + si * 2); + if (hs == 0 && IsSurrogate(wc)) { /* Is the code a surrogate? */ + hs = wc; continue; + } + nw = put_utf((DWORD)hs << 16 | wc, &label[di], 4); /* Store it in API encoding */ + if (nw == 0) { di = 0; break; } /* Encode error? */ + di += nw; + hs = 0; + } + if (hs != 0) di = 0; /* Broken surrogate pair? */ + label[di] = 0; + } else +#endif + { + si = di = 0; /* Extract volume label from AM_VOL entry */ + while (si < 11) { + wc = dj.dir[si++]; +#if FF_USE_LFN && FF_LFN_UNICODE >= 1 /* Unicode output */ + if (dbc_1st((BYTE)wc) && si < 11) wc = wc << 8 | dj.dir[si++]; /* Is it a DBC? */ + wc = ff_oem2uni(wc, CODEPAGE); /* Convert it into Unicode */ + if (wc == 0) { di = 0; break; } /* Invalid char in current code page? */ + di += put_utf(wc, &label[di], 4); /* Store it in Unicode */ +#else /* ANSI/OEM output */ + label[di++] = (TCHAR)wc; +#endif + } + do { /* Truncate trailing spaces */ + label[di] = 0; + if (di == 0) break; + } while (label[--di] == ' '); + } + } + } + if (res == FR_NO_FILE) { /* No label entry and return nul string */ + label[0] = 0; + res = FR_OK; + } + } + + /* Get volume serial number */ + if (res == FR_OK && vsn) { + res = move_window(fs, fs->volbase); + if (res == FR_OK) { + switch (fs->fs_type) { + case FS_EXFAT: + di = BPB_VolIDEx; + break; + + case FS_FAT32: + di = BS_VolID32; + break; + + default: + di = BS_VolID; + } + *vsn = ld_dword(fs->win + di); + } + } + + LEAVE_FF(fs, res); +} + + + +#if !FF_FS_READONLY +/*-----------------------------------------------------------------------*/ +/* Set Volume Label */ +/*-----------------------------------------------------------------------*/ + +FRESULT f_setlabel ( + const TCHAR* label /* Volume label to set with heading logical drive number */ +) +{ + FRESULT res; + DIR dj; + FATFS *fs; + BYTE dirvn[22]; + UINT di; + WCHAR wc; + static const char badchr[18] = "+.,;=[]" "/*:<>|\\\"\?\x7F"; /* [0..16] for FAT, [7..16] for exFAT */ +#if FF_USE_LFN + DWORD dc; +#endif + + /* Get logical drive */ + res = mount_volume(&label, &fs, FA_WRITE); + if (res != FR_OK) LEAVE_FF(fs, res); + +#if FF_FS_EXFAT + if (fs->fs_type == FS_EXFAT) { /* On the exFAT volume */ + memset(dirvn, 0, 22); + di = 0; + while ((UINT)*label >= ' ') { /* Create volume label */ + dc = tchar2uni(&label); /* Get a Unicode character */ + if (dc >= 0x10000) { + if (dc == 0xFFFFFFFF || di >= 10) { /* Wrong surrogate or buffer overflow */ + dc = 0; + } else { + st_word(dirvn + di * 2, (WCHAR)(dc >> 16)); di++; + } + } + if (dc == 0 || strchr(&badchr[7], (int)dc) || di >= 11) { /* Check validity of the volume label */ + LEAVE_FF(fs, FR_INVALID_NAME); + } + st_word(dirvn + di * 2, (WCHAR)dc); di++; + } + } else +#endif + { /* On the FAT/FAT32 volume */ + memset(dirvn, ' ', 11); + di = 0; + while ((UINT)*label >= ' ') { /* Create volume label */ +#if FF_USE_LFN + dc = tchar2uni(&label); + wc = (dc < 0x10000) ? ff_uni2oem(ff_wtoupper(dc), CODEPAGE) : 0; +#else /* ANSI/OEM input */ + wc = (BYTE)*label++; + if (dbc_1st((BYTE)wc)) wc = dbc_2nd((BYTE)*label) ? wc << 8 | (BYTE)*label++ : 0; + if (IsLower(wc)) wc -= 0x20; /* To upper ASCII characters */ +#if FF_CODE_PAGE == 0 + if (ExCvt && wc >= 0x80) wc = ExCvt[wc - 0x80]; /* To upper extended characters (SBCS cfg) */ +#elif FF_CODE_PAGE < 900 + if (wc >= 0x80) wc = ExCvt[wc - 0x80]; /* To upper extended characters (SBCS cfg) */ +#endif +#endif + if (wc == 0 || strchr(&badchr[0], (int)wc) || di >= (UINT)((wc >= 0x100) ? 10 : 11)) { /* Reject invalid characters for volume label */ + LEAVE_FF(fs, FR_INVALID_NAME); + } + if (wc >= 0x100) dirvn[di++] = (BYTE)(wc >> 8); + dirvn[di++] = (BYTE)wc; + } + if (dirvn[0] == DDEM) LEAVE_FF(fs, FR_INVALID_NAME); /* Reject illegal name (heading DDEM) */ + while (di && dirvn[di - 1] == ' ') di--; /* Snip trailing spaces */ + } + + /* Set volume label */ + dj.obj.fs = fs; dj.obj.sclust = 0; /* Open root directory */ + res = dir_sdi(&dj, 0); + if (res == FR_OK) { + res = DIR_READ_LABEL(&dj); /* Get volume label entry */ + if (res == FR_OK) { + if (FF_FS_EXFAT && fs->fs_type == FS_EXFAT) { + dj.dir[XDIR_NumLabel] = (BYTE)di; /* Change the volume label */ + memcpy(dj.dir + XDIR_Label, dirvn, 22); + } else { + if (di != 0) { + memcpy(dj.dir, dirvn, 11); /* Change the volume label */ + } else { + dj.dir[DIR_Name] = DDEM; /* Remove the volume label */ + } + } + fs->wflag = 1; + res = sync_fs(fs); + } else { /* No volume label entry or an error */ + if (res == FR_NO_FILE) { + res = FR_OK; + if (di != 0) { /* Create a volume label entry */ + res = dir_alloc(&dj, 1); /* Allocate an entry */ + if (res == FR_OK) { + memset(dj.dir, 0, SZDIRE); /* Clean the entry */ + if (FF_FS_EXFAT && fs->fs_type == FS_EXFAT) { + dj.dir[XDIR_Type] = ET_VLABEL; /* Create volume label entry */ + dj.dir[XDIR_NumLabel] = (BYTE)di; + memcpy(dj.dir + XDIR_Label, dirvn, 22); + } else { + dj.dir[DIR_Attr] = AM_VOL; /* Create volume label entry */ + memcpy(dj.dir, dirvn, 11); + } + fs->wflag = 1; + res = sync_fs(fs); + } + } + } + } + } + + LEAVE_FF(fs, res); +} + +#endif /* !FF_FS_READONLY */ +#endif /* FF_USE_LABEL */ + + + +#if FF_USE_EXPAND && !FF_FS_READONLY +/*-----------------------------------------------------------------------*/ +/* Allocate a Contiguous Blocks to the File */ +/*-----------------------------------------------------------------------*/ + +FRESULT f_expand ( + FIL* fp, /* Pointer to the file object */ + FSIZE_t fsz, /* File size to be expanded to */ + BYTE opt /* Operation mode 0:Find and prepare or 1:Find and allocate */ +) +{ + FRESULT res; + FATFS *fs; + DWORD n, clst, stcl, scl, ncl, tcl, lclst; + + + res = validate(&fp->obj, &fs); /* Check validity of the file object */ + if (res != FR_OK || (res = (FRESULT)fp->err) != FR_OK) LEAVE_FF(fs, res); + if (fsz == 0 || fp->obj.objsize != 0 || !(fp->flag & FA_WRITE)) LEAVE_FF(fs, FR_DENIED); +#if FF_FS_EXFAT + if (fs->fs_type != FS_EXFAT && fsz >= 0x100000000) LEAVE_FF(fs, FR_DENIED); /* Check if in size limit */ +#endif + n = (DWORD)fs->csize * SS(fs); /* Cluster size */ + tcl = (DWORD)(fsz / n) + ((fsz & (n - 1)) ? 1 : 0); /* Number of clusters required */ + stcl = fs->last_clst; lclst = 0; + if (stcl < 2 || stcl >= fs->n_fatent) stcl = 2; + +#if FF_FS_EXFAT + if (fs->fs_type == FS_EXFAT) { + scl = find_bitmap(fs, stcl, tcl); /* Find a contiguous cluster block */ + if (scl == 0) res = FR_DENIED; /* No contiguous cluster block was found */ + if (scl == 0xFFFFFFFF) res = FR_DISK_ERR; + if (res == FR_OK) { /* A contiguous free area is found */ + if (opt) { /* Allocate it now */ + res = change_bitmap(fs, scl, tcl, 1); /* Mark the cluster block 'in use' */ + lclst = scl + tcl - 1; + } else { /* Set it as suggested point for next allocation */ + lclst = scl - 1; + } + } + } else +#endif + { + scl = clst = stcl; ncl = 0; + for (;;) { /* Find a contiguous cluster block */ + n = get_fat(&fp->obj, clst); + if (++clst >= fs->n_fatent) clst = 2; + if (n == 1) { res = FR_INT_ERR; break; } + if (n == 0xFFFFFFFF) { res = FR_DISK_ERR; break; } + if (n == 0) { /* Is it a free cluster? */ + if (++ncl == tcl) break; /* Break if a contiguous cluster block is found */ + } else { + scl = clst; ncl = 0; /* Not a free cluster */ + } + if (clst == stcl) { res = FR_DENIED; break; } /* No contiguous cluster? */ + } + if (res == FR_OK) { /* A contiguous free area is found */ + if (opt) { /* Allocate it now */ + for (clst = scl, n = tcl; n; clst++, n--) { /* Create a cluster chain on the FAT */ + res = put_fat(fs, clst, (n == 1) ? 0xFFFFFFFF : clst + 1); + if (res != FR_OK) break; + lclst = clst; + } + } else { /* Set it as suggested point for next allocation */ + lclst = scl - 1; + } + } + } + + if (res == FR_OK) { + fs->last_clst = lclst; /* Set suggested start cluster to start next */ + if (opt) { /* Is it allocated now? */ + fp->obj.sclust = scl; /* Update object allocation information */ + fp->obj.objsize = fsz; + if (FF_FS_EXFAT) fp->obj.stat = 2; /* Set status 'contiguous chain' */ + fp->flag |= FA_MODIFIED; + if (fs->free_clst <= fs->n_fatent - 2) { /* Update FSINFO */ + fs->free_clst -= tcl; + fs->fsi_flag |= 1; + } + } + } + + LEAVE_FF(fs, res); +} + +#endif /* FF_USE_EXPAND && !FF_FS_READONLY */ + + + +#if FF_USE_FORWARD +/*-----------------------------------------------------------------------*/ +/* Forward Data to the Stream Directly */ +/*-----------------------------------------------------------------------*/ + +FRESULT f_forward ( + FIL* fp, /* Pointer to the file object */ + UINT (*func)(const BYTE*,UINT), /* Pointer to the streaming function */ + UINT btf, /* Number of bytes to forward */ + UINT* bf /* Pointer to number of bytes forwarded */ +) +{ + FRESULT res; + FATFS *fs; + DWORD clst; + LBA_t sect; + FSIZE_t remain; + UINT rcnt, csect; + BYTE *dbuf; + + + *bf = 0; /* Clear transfer byte counter */ + res = validate(&fp->obj, &fs); /* Check validity of the file object */ + if (res != FR_OK || (res = (FRESULT)fp->err) != FR_OK) LEAVE_FF(fs, res); + if (!(fp->flag & FA_READ)) LEAVE_FF(fs, FR_DENIED); /* Check access mode */ + + remain = fp->obj.objsize - fp->fptr; + if (btf > remain) btf = (UINT)remain; /* Truncate btf by remaining bytes */ + + for ( ; btf > 0 && (*func)(0, 0); fp->fptr += rcnt, *bf += rcnt, btf -= rcnt) { /* Repeat until all data transferred or stream goes busy */ + csect = (UINT)(fp->fptr / SS(fs) & (fs->csize - 1)); /* Sector offset in the cluster */ + if (fp->fptr % SS(fs) == 0) { /* On the sector boundary? */ + if (csect == 0) { /* On the cluster boundary? */ + clst = (fp->fptr == 0) ? /* On the top of the file? */ + fp->obj.sclust : get_fat(&fp->obj, fp->clust); + if (clst <= 1) ABORT(fs, FR_INT_ERR); + if (clst == 0xFFFFFFFF) ABORT(fs, FR_DISK_ERR); + fp->clust = clst; /* Update current cluster */ + } + } + sect = clst2sect(fs, fp->clust); /* Get current data sector */ + if (sect == 0) ABORT(fs, FR_INT_ERR); + sect += csect; +#if FF_FS_TINY + if (move_window(fs, sect) != FR_OK) ABORT(fs, FR_DISK_ERR); /* Move sector window to the file data */ + dbuf = fs->win; +#else + if (fp->sect != sect) { /* Fill sector cache with file data */ +#if !FF_FS_READONLY + if (fp->flag & FA_DIRTY) { /* Write-back dirty sector cache */ + if (disk_write(fs->pdrv, fp->buf, fp->sect, 1) != RES_OK) ABORT(fs, FR_DISK_ERR); + fp->flag &= (BYTE)~FA_DIRTY; + } +#endif + if (disk_read(fs->pdrv, fp->buf, sect, 1) != RES_OK) ABORT(fs, FR_DISK_ERR); + } + dbuf = fp->buf; +#endif + fp->sect = sect; + rcnt = SS(fs) - (UINT)fp->fptr % SS(fs); /* Number of bytes remains in the sector */ + if (rcnt > btf) rcnt = btf; /* Clip it by btr if needed */ + rcnt = (*func)(dbuf + ((UINT)fp->fptr % SS(fs)), rcnt); /* Forward the file data */ + if (rcnt == 0) ABORT(fs, FR_INT_ERR); + } + + LEAVE_FF(fs, FR_OK); +} +#endif /* FF_USE_FORWARD */ + + + +#if !FF_FS_READONLY && FF_USE_MKFS +/*-----------------------------------------------------------------------*/ +/* Create FAT/exFAT volume (with sub-functions) */ +/*-----------------------------------------------------------------------*/ + +#define N_SEC_TRACK 63 /* Sectors per track for determination of drive CHS */ +#define GPT_ALIGN 0x100000 /* Alignment of partitions in GPT [byte] (>=128KB) */ +#define GPT_ITEMS 128 /* Number of GPT table size (>=128, sector aligned) */ + + +/* Create partitions on the physical drive in format of MBR or GPT */ + +static FRESULT create_partition ( + BYTE drv, /* Physical drive number */ + const LBA_t plst[], /* Partition list */ + BYTE sys, /* System ID (for only MBR, temp setting) */ + BYTE* buf /* Working buffer for a sector */ +) +{ + UINT i, cy; + LBA_t sz_drv; + DWORD sz_drv32, nxt_alloc32, sz_part32; + BYTE *pte; + BYTE hd, n_hd, sc, n_sc; + + /* Get physical drive size */ + if (disk_ioctl(drv, GET_SECTOR_COUNT, &sz_drv) != RES_OK) return FR_DISK_ERR; + +#if FF_LBA64 + if (sz_drv >= FF_MIN_GPT) { /* Create partitions in GPT format */ + WORD ss; + UINT sz_ptbl, pi, si, ofs; + DWORD bcc, rnd, align; + QWORD nxt_alloc, sz_part, sz_pool, top_bpt; + static const BYTE gpt_mbr[16] = {0x00, 0x00, 0x02, 0x00, 0xEE, 0xFE, 0xFF, 0x00, 0x01, 0x00, 0x00, 0x00, 0xFF, 0xFF, 0xFF, 0xFF}; + +#if FF_MAX_SS != FF_MIN_SS + if (disk_ioctl(drv, GET_SECTOR_SIZE, &ss) != RES_OK) return FR_DISK_ERR; /* Get sector size */ + if (ss > FF_MAX_SS || ss < FF_MIN_SS || (ss & (ss - 1))) return FR_DISK_ERR; +#else + ss = FF_MAX_SS; +#endif + rnd = (DWORD)sz_drv + GET_FATTIME(); /* Random seed */ + align = GPT_ALIGN / ss; /* Partition alignment for GPT [sector] */ + sz_ptbl = GPT_ITEMS * SZ_GPTE / ss; /* Size of partition table [sector] */ + top_bpt = sz_drv - sz_ptbl - 1; /* Backup partiiton table start sector */ + nxt_alloc = 2 + sz_ptbl; /* First allocatable sector */ + sz_pool = top_bpt - nxt_alloc; /* Size of allocatable area */ + bcc = 0xFFFFFFFF; sz_part = 1; + pi = si = 0; /* partition table index, size table index */ + do { + if (pi * SZ_GPTE % ss == 0) memset(buf, 0, ss); /* Clean the buffer if needed */ + if (sz_part != 0) { /* Is the size table not termintated? */ + nxt_alloc = (nxt_alloc + align - 1) & ((QWORD)0 - align); /* Align partition start */ + sz_part = plst[si++]; /* Get a partition size */ + if (sz_part <= 100) { /* Is the size in percentage? */ + sz_part = sz_pool * sz_part / 100; + sz_part = (sz_part + align - 1) & ((QWORD)0 - align); /* Align partition end (only if in percentage) */ + } + if (nxt_alloc + sz_part > top_bpt) { /* Clip the size at end of the pool */ + sz_part = (nxt_alloc < top_bpt) ? top_bpt - nxt_alloc : 0; + } + } + if (sz_part != 0) { /* Add a partition? */ + ofs = pi * SZ_GPTE % ss; + memcpy(buf + ofs + GPTE_PtGuid, GUID_MS_Basic, 16); /* Set partition GUID (Microsoft Basic Data) */ + rnd = make_rand(rnd, buf + ofs + GPTE_UpGuid, 16); /* Set unique partition GUID */ + st_qword(buf + ofs + GPTE_FstLba, nxt_alloc); /* Set partition start sector */ + st_qword(buf + ofs + GPTE_LstLba, nxt_alloc + sz_part - 1); /* Set partition end sector */ + nxt_alloc += sz_part; /* Next allocatable sector */ + } + if ((pi + 1) * SZ_GPTE % ss == 0) { /* Write the buffer if it is filled up */ + for (i = 0; i < ss; bcc = crc32(bcc, buf[i++])) ; /* Calculate table check sum */ + if (disk_write(drv, buf, 2 + pi * SZ_GPTE / ss, 1) != RES_OK) return FR_DISK_ERR; /* Write to primary table */ + if (disk_write(drv, buf, top_bpt + pi * SZ_GPTE / ss, 1) != RES_OK) return FR_DISK_ERR; /* Write to secondary table */ + } + } while (++pi < GPT_ITEMS); + + /* Create primary GPT header */ + memset(buf, 0, ss); + memcpy(buf + GPTH_Sign, "EFI PART" "\0\0\1\0" "\x5C\0\0", 16); /* Signature, version (1.0) and size (92) */ + st_dword(buf + GPTH_PtBcc, ~bcc); /* Table check sum */ + st_qword(buf + GPTH_CurLba, 1); /* LBA of this header */ + st_qword(buf + GPTH_BakLba, sz_drv - 1); /* LBA of secondary header */ + st_qword(buf + GPTH_FstLba, 2 + sz_ptbl); /* LBA of first allocatable sector */ + st_qword(buf + GPTH_LstLba, top_bpt - 1); /* LBA of last allocatable sector */ + st_dword(buf + GPTH_PteSize, SZ_GPTE); /* Size of a table entry */ + st_dword(buf + GPTH_PtNum, GPT_ITEMS); /* Number of table entries */ + st_dword(buf + GPTH_PtOfs, 2); /* LBA of this table */ + rnd = make_rand(rnd, buf + GPTH_DskGuid, 16); /* Disk GUID */ + for (i = 0, bcc= 0xFFFFFFFF; i < 92; bcc = crc32(bcc, buf[i++])) ; /* Calculate header check sum */ + st_dword(buf + GPTH_Bcc, ~bcc); /* Header check sum */ + if (disk_write(drv, buf, 1, 1) != RES_OK) return FR_DISK_ERR; + + /* Create secondary GPT header */ + st_qword(buf + GPTH_CurLba, sz_drv - 1); /* LBA of this header */ + st_qword(buf + GPTH_BakLba, 1); /* LBA of primary header */ + st_qword(buf + GPTH_PtOfs, top_bpt); /* LBA of this table */ + st_dword(buf + GPTH_Bcc, 0); + for (i = 0, bcc= 0xFFFFFFFF; i < 92; bcc = crc32(bcc, buf[i++])) ; /* Calculate header check sum */ + st_dword(buf + GPTH_Bcc, ~bcc); /* Header check sum */ + if (disk_write(drv, buf, sz_drv - 1, 1) != RES_OK) return FR_DISK_ERR; + + /* Create protective MBR */ + memset(buf, 0, ss); + memcpy(buf + MBR_Table, gpt_mbr, 16); /* Create a GPT partition */ + st_word(buf + BS_55AA, 0xAA55); + if (disk_write(drv, buf, 0, 1) != RES_OK) return FR_DISK_ERR; + + } else +#endif + { /* Create partitions in MBR format */ + sz_drv32 = (DWORD)sz_drv; + n_sc = N_SEC_TRACK; /* Determine drive CHS without any consideration of the drive geometry */ + for (n_hd = 8; n_hd != 0 && sz_drv32 / n_hd / n_sc > 1024; n_hd *= 2) ; + if (n_hd == 0) n_hd = 255; /* Number of heads needs to be <256 */ + + memset(buf, 0, FF_MAX_SS); /* Clear MBR */ + pte = buf + MBR_Table; /* Partition table in the MBR */ + for (i = 0, nxt_alloc32 = n_sc; i < 4 && nxt_alloc32 != 0 && nxt_alloc32 < sz_drv32; i++, nxt_alloc32 += sz_part32) { + sz_part32 = (DWORD)plst[i]; /* Get partition size */ + if (sz_part32 <= 100) sz_part32 = (sz_part32 == 100) ? sz_drv32 : sz_drv32 / 100 * sz_part32; /* Size in percentage? */ + if (nxt_alloc32 + sz_part32 > sz_drv32 || nxt_alloc32 + sz_part32 < nxt_alloc32) sz_part32 = sz_drv32 - nxt_alloc32; /* Clip at drive size */ + if (sz_part32 == 0) break; /* End of table or no sector to allocate? */ + + st_dword(pte + PTE_StLba, nxt_alloc32); /* Start LBA */ + st_dword(pte + PTE_SizLba, sz_part32); /* Number of sectors */ + pte[PTE_System] = sys; /* System type */ + + cy = (UINT)(nxt_alloc32 / n_sc / n_hd); /* Start cylinder */ + hd = (BYTE)(nxt_alloc32 / n_sc % n_hd); /* Start head */ + sc = (BYTE)(nxt_alloc32 % n_sc + 1); /* Start sector */ + pte[PTE_StHead] = hd; + pte[PTE_StSec] = (BYTE)((cy >> 2 & 0xC0) | sc); + pte[PTE_StCyl] = (BYTE)cy; + + cy = (UINT)((nxt_alloc32 + sz_part32 - 1) / n_sc / n_hd); /* End cylinder */ + hd = (BYTE)((nxt_alloc32 + sz_part32 - 1) / n_sc % n_hd); /* End head */ + sc = (BYTE)((nxt_alloc32 + sz_part32 - 1) % n_sc + 1); /* End sector */ + pte[PTE_EdHead] = hd; + pte[PTE_EdSec] = (BYTE)((cy >> 2 & 0xC0) | sc); + pte[PTE_EdCyl] = (BYTE)cy; + + pte += SZ_PTE; /* Next entry */ + } + + st_word(buf + BS_55AA, 0xAA55); /* MBR signature */ + if (disk_write(drv, buf, 0, 1) != RES_OK) return FR_DISK_ERR; /* Write it to the MBR */ + } + + return FR_OK; +} + + + +FRESULT f_mkfs ( + const TCHAR* path, /* Logical drive number */ + const MKFS_PARM* opt, /* Format options */ + void* work, /* Pointer to working buffer (null: use heap memory) */ + UINT len /* Size of working buffer [byte] */ +) +{ + static const WORD cst[] = {1, 4, 16, 64, 256, 512, 0}; /* Cluster size boundary for FAT volume (4Ks unit) */ + static const WORD cst32[] = {1, 2, 4, 8, 16, 32, 0}; /* Cluster size boundary for FAT32 volume (128Ks unit) */ + static const MKFS_PARM defopt = {FM_ANY, 0, 0, 0, 0}; /* Default parameter */ + BYTE fsopt, fsty, sys, *buf, *pte, pdrv, ipart; + WORD ss; /* Sector size */ + DWORD sz_buf, sz_blk, n_clst, pau, nsect, n, vsn; + LBA_t sz_vol, b_vol, b_fat, b_data; /* Size of volume, Base LBA of volume, fat, data */ + LBA_t sect, lba[2]; + DWORD sz_rsv, sz_fat, sz_dir, sz_au; /* Size of reserved, fat, dir, data, cluster */ + UINT n_fat, n_root, i; /* Index, Number of FATs and Number of roor dir entries */ + int vol; + DSTATUS ds; + FRESULT fr; + + + /* Check mounted drive and clear work area */ + vol = get_ldnumber(&path); /* Get target logical drive */ + if (vol < 0) return FR_INVALID_DRIVE; + if (FatFs[vol]) FatFs[vol]->fs_type = 0; /* Clear the fs object if mounted */ + pdrv = LD2PD(vol); /* Physical drive */ + ipart = LD2PT(vol); /* Partition (0:create as new, 1..:get from partition table) */ + if (!opt) opt = &defopt; /* Use default parameter if it is not given */ + + /* Get physical drive status (sz_drv, sz_blk, ss) */ + ds = disk_initialize(pdrv); + if (ds & STA_NOINIT) return FR_NOT_READY; + if (ds & STA_PROTECT) return FR_WRITE_PROTECTED; + sz_blk = opt->align; + if (sz_blk == 0 && disk_ioctl(pdrv, GET_BLOCK_SIZE, &sz_blk) != RES_OK) sz_blk = 1; + if (sz_blk == 0 || sz_blk > 0x8000 || (sz_blk & (sz_blk - 1))) sz_blk = 1; +#if FF_MAX_SS != FF_MIN_SS + if (disk_ioctl(pdrv, GET_SECTOR_SIZE, &ss) != RES_OK) return FR_DISK_ERR; + if (ss > FF_MAX_SS || ss < FF_MIN_SS || (ss & (ss - 1))) return FR_DISK_ERR; +#else + ss = FF_MAX_SS; +#endif + /* Options for FAT sub-type and FAT parameters */ + fsopt = opt->fmt & (FM_ANY | FM_SFD); + n_fat = (opt->n_fat >= 1 && opt->n_fat <= 2) ? opt->n_fat : 1; + n_root = (opt->n_root >= 1 && opt->n_root <= 32768 && (opt->n_root % (ss / SZDIRE)) == 0) ? opt->n_root : 512; + sz_au = (opt->au_size <= 0x1000000 && (opt->au_size & (opt->au_size - 1)) == 0) ? opt->au_size : 0; + sz_au /= ss; /* Byte --> Sector */ + + /* Get working buffer */ + sz_buf = len / ss; /* Size of working buffer [sector] */ + if (sz_buf == 0) return FR_NOT_ENOUGH_CORE; + buf = (BYTE*)work; /* Working buffer */ +#if FF_USE_LFN == 3 + if (!buf) buf = ff_memalloc(sz_buf * ss); /* Use heap memory for working buffer */ +#endif + if (!buf) return FR_NOT_ENOUGH_CORE; + + /* Determine where the volume to be located (b_vol, sz_vol) */ + b_vol = sz_vol = 0; + if (FF_MULTI_PARTITION && ipart != 0) { /* Is the volume associated with any specific partition? */ + /* Get partition location from the existing partition table */ + if (disk_read(pdrv, buf, 0, 1) != RES_OK) LEAVE_MKFS(FR_DISK_ERR); /* Load MBR */ + if (ld_word(buf + BS_55AA) != 0xAA55) LEAVE_MKFS(FR_MKFS_ABORTED); /* Check if MBR is valid */ +#if FF_LBA64 + if (buf[MBR_Table + PTE_System] == 0xEE) { /* GPT protective MBR? */ + DWORD n_ent, ofs; + QWORD pt_lba; + + /* Get the partition location from GPT */ + if (disk_read(pdrv, buf, 1, 1) != RES_OK) LEAVE_MKFS(FR_DISK_ERR); /* Load GPT header sector (next to MBR) */ + if (!test_gpt_header(buf)) LEAVE_MKFS(FR_MKFS_ABORTED); /* Check if GPT header is valid */ + n_ent = ld_dword(buf + GPTH_PtNum); /* Number of entries */ + pt_lba = ld_qword(buf + GPTH_PtOfs); /* Table start sector */ + ofs = i = 0; + while (n_ent) { /* Find MS Basic partition with order of ipart */ + if (ofs == 0 && disk_read(pdrv, buf, pt_lba++, 1) != RES_OK) LEAVE_MKFS(FR_DISK_ERR); /* Get PT sector */ + if (!memcmp(buf + ofs + GPTE_PtGuid, GUID_MS_Basic, 16) && ++i == ipart) { /* MS basic data partition? */ + b_vol = ld_qword(buf + ofs + GPTE_FstLba); + sz_vol = ld_qword(buf + ofs + GPTE_LstLba) - b_vol + 1; + break; + } + n_ent--; ofs = (ofs + SZ_GPTE) % ss; /* Next entry */ + } + if (n_ent == 0) LEAVE_MKFS(FR_MKFS_ABORTED); /* Partition not found */ + fsopt |= 0x80; /* Partitioning is in GPT */ + } else +#endif + { /* Get the partition location from MBR partition table */ + pte = buf + (MBR_Table + (ipart - 1) * SZ_PTE); + if (ipart > 4 || pte[PTE_System] == 0) LEAVE_MKFS(FR_MKFS_ABORTED); /* No partition? */ + b_vol = ld_dword(pte + PTE_StLba); /* Get volume start sector */ + sz_vol = ld_dword(pte + PTE_SizLba); /* Get volume size */ + } + } else { /* The volume is associated with a physical drive */ + if (disk_ioctl(pdrv, GET_SECTOR_COUNT, &sz_vol) != RES_OK) LEAVE_MKFS(FR_DISK_ERR); + if (!(fsopt & FM_SFD)) { /* To be partitioned? */ + /* Create a single-partition on the drive in this function */ +#if FF_LBA64 + if (sz_vol >= FF_MIN_GPT) { /* Which partition type to create, MBR or GPT? */ + fsopt |= 0x80; /* Partitioning is in GPT */ + b_vol = GPT_ALIGN / ss; sz_vol -= b_vol + GPT_ITEMS * SZ_GPTE / ss + 1; /* Estimated partition offset and size */ + } else +#endif + { /* Partitioning is in MBR */ + if (sz_vol > N_SEC_TRACK) { + b_vol = N_SEC_TRACK; sz_vol -= b_vol; /* Estimated partition offset and size */ + } + } + } + } + if (sz_vol < 128) LEAVE_MKFS(FR_MKFS_ABORTED); /* Check if volume size is >=128s */ + + /* Now start to create an FAT volume at b_vol and sz_vol */ + + do { /* Pre-determine the FAT type */ + if (FF_FS_EXFAT && (fsopt & FM_EXFAT)) { /* exFAT possible? */ + if ((fsopt & FM_ANY) == FM_EXFAT || sz_vol >= 0x4000000 || sz_au > 128) { /* exFAT only, vol >= 64MS or sz_au > 128S ? */ + fsty = FS_EXFAT; break; + } + } +#if FF_LBA64 + if (sz_vol >= 0x100000000) LEAVE_MKFS(FR_MKFS_ABORTED); /* Too large volume for FAT/FAT32 */ +#endif + if (sz_au > 128) sz_au = 128; /* Invalid AU for FAT/FAT32? */ + if (fsopt & FM_FAT32) { /* FAT32 possible? */ + if (!(fsopt & FM_FAT)) { /* no-FAT? */ + fsty = FS_FAT32; break; + } + } + if (!(fsopt & FM_FAT)) LEAVE_MKFS(FR_INVALID_PARAMETER); /* no-FAT? */ + fsty = FS_FAT16; + } while (0); + + vsn = (DWORD)sz_vol + GET_FATTIME(); /* VSN generated from current time and partitiion size */ + +#if FF_FS_EXFAT + if (fsty == FS_EXFAT) { /* Create an exFAT volume */ + DWORD szb_bit, szb_case, sum, nbit, clu, clen[3]; + WCHAR ch, si; + UINT j, st; + + if (sz_vol < 0x1000) LEAVE_MKFS(FR_MKFS_ABORTED); /* Too small volume for exFAT? */ +#if FF_USE_TRIM + lba[0] = b_vol; lba[1] = b_vol + sz_vol - 1; /* Inform storage device that the volume area may be erased */ + disk_ioctl(pdrv, CTRL_TRIM, lba); +#endif + /* Determine FAT location, data location and number of clusters */ + if (sz_au == 0) { /* AU auto-selection */ + sz_au = 8; + if (sz_vol >= 0x80000) sz_au = 64; /* >= 512Ks */ + if (sz_vol >= 0x4000000) sz_au = 256; /* >= 64Ms */ + } + b_fat = b_vol + 32; /* FAT start at offset 32 */ + sz_fat = (DWORD)((sz_vol / sz_au + 2) * 4 + ss - 1) / ss; /* Number of FAT sectors */ + b_data = (b_fat + sz_fat + sz_blk - 1) & ~((LBA_t)sz_blk - 1); /* Align data area to the erase block boundary */ + if (b_data - b_vol >= sz_vol / 2) LEAVE_MKFS(FR_MKFS_ABORTED); /* Too small volume? */ + n_clst = (DWORD)(sz_vol - (b_data - b_vol)) / sz_au; /* Number of clusters */ + if (n_clst <16) LEAVE_MKFS(FR_MKFS_ABORTED); /* Too few clusters? */ + if (n_clst > MAX_EXFAT) LEAVE_MKFS(FR_MKFS_ABORTED); /* Too many clusters? */ + + szb_bit = (n_clst + 7) / 8; /* Size of allocation bitmap */ + clen[0] = (szb_bit + sz_au * ss - 1) / (sz_au * ss); /* Number of allocation bitmap clusters */ + + /* Create a compressed up-case table */ + sect = b_data + sz_au * clen[0]; /* Table start sector */ + sum = 0; /* Table checksum to be stored in the 82 entry */ + st = 0; si = 0; i = 0; j = 0; szb_case = 0; + do { + switch (st) { + case 0: + ch = (WCHAR)ff_wtoupper(si); /* Get an up-case char */ + if (ch != si) { + si++; break; /* Store the up-case char if exist */ + } + for (j = 1; (WCHAR)(si + j) && (WCHAR)(si + j) == ff_wtoupper((WCHAR)(si + j)); j++) ; /* Get run length of no-case block */ + if (j >= 128) { + ch = 0xFFFF; st = 2; break; /* Compress the no-case block if run is >= 128 chars */ + } + st = 1; /* Do not compress short run */ + /* FALLTHROUGH */ + case 1: + ch = si++; /* Fill the short run */ + if (--j == 0) st = 0; + break; + + default: + ch = (WCHAR)j; si += (WCHAR)j; /* Number of chars to skip */ + st = 0; + } + sum = xsum32(buf[i + 0] = (BYTE)ch, sum); /* Put it into the write buffer */ + sum = xsum32(buf[i + 1] = (BYTE)(ch >> 8), sum); + i += 2; szb_case += 2; + if (si == 0 || i == sz_buf * ss) { /* Write buffered data when buffer full or end of process */ + n = (i + ss - 1) / ss; + if (disk_write(pdrv, buf, sect, n) != RES_OK) LEAVE_MKFS(FR_DISK_ERR); + sect += n; i = 0; + } + } while (si); + clen[1] = (szb_case + sz_au * ss - 1) / (sz_au * ss); /* Number of up-case table clusters */ + clen[2] = 1; /* Number of root dir clusters */ + + /* Initialize the allocation bitmap */ + sect = b_data; nsect = (szb_bit + ss - 1) / ss; /* Start of bitmap and number of bitmap sectors */ + nbit = clen[0] + clen[1] + clen[2]; /* Number of clusters in-use by system (bitmap, up-case and root-dir) */ + do { + memset(buf, 0, sz_buf * ss); /* Initialize bitmap buffer */ + for (i = 0; nbit != 0 && i / 8 < sz_buf * ss; buf[i / 8] |= 1 << (i % 8), i++, nbit--) ; /* Mark used clusters */ + n = (nsect > sz_buf) ? sz_buf : nsect; /* Write the buffered data */ + if (disk_write(pdrv, buf, sect, n) != RES_OK) LEAVE_MKFS(FR_DISK_ERR); + sect += n; nsect -= n; + } while (nsect); + + /* Initialize the FAT */ + sect = b_fat; nsect = sz_fat; /* Start of FAT and number of FAT sectors */ + j = nbit = clu = 0; + do { + memset(buf, 0, sz_buf * ss); i = 0; /* Clear work area and reset write offset */ + if (clu == 0) { /* Initialize FAT [0] and FAT[1] */ + st_dword(buf + i, 0xFFFFFFF8); i += 4; clu++; + st_dword(buf + i, 0xFFFFFFFF); i += 4; clu++; + } + do { /* Create chains of bitmap, up-case and root dir */ + while (nbit != 0 && i < sz_buf * ss) { /* Create a chain */ + st_dword(buf + i, (nbit > 1) ? clu + 1 : 0xFFFFFFFF); + i += 4; clu++; nbit--; + } + if (nbit == 0 && j < 3) nbit = clen[j++]; /* Get next chain length */ + } while (nbit != 0 && i < sz_buf * ss); + n = (nsect > sz_buf) ? sz_buf : nsect; /* Write the buffered data */ + if (disk_write(pdrv, buf, sect, n) != RES_OK) LEAVE_MKFS(FR_DISK_ERR); + sect += n; nsect -= n; + } while (nsect); + + /* Initialize the root directory */ + memset(buf, 0, sz_buf * ss); + buf[SZDIRE * 0 + 0] = ET_VLABEL; /* Volume label entry (no label) */ + buf[SZDIRE * 1 + 0] = ET_BITMAP; /* Bitmap entry */ + st_dword(buf + SZDIRE * 1 + 20, 2); /* cluster */ + st_dword(buf + SZDIRE * 1 + 24, szb_bit); /* size */ + buf[SZDIRE * 2 + 0] = ET_UPCASE; /* Up-case table entry */ + st_dword(buf + SZDIRE * 2 + 4, sum); /* sum */ + st_dword(buf + SZDIRE * 2 + 20, 2 + clen[0]); /* cluster */ + st_dword(buf + SZDIRE * 2 + 24, szb_case); /* size */ + sect = b_data + sz_au * (clen[0] + clen[1]); nsect = sz_au; /* Start of the root directory and number of sectors */ + do { /* Fill root directory sectors */ + n = (nsect > sz_buf) ? sz_buf : nsect; + if (disk_write(pdrv, buf, sect, n) != RES_OK) LEAVE_MKFS(FR_DISK_ERR); + memset(buf, 0, ss); /* Rest of entries are filled with zero */ + sect += n; nsect -= n; + } while (nsect); + + /* Create two set of the exFAT VBR blocks */ + sect = b_vol; + for (n = 0; n < 2; n++) { + /* Main record (+0) */ + memset(buf, 0, ss); + memcpy(buf + BS_JmpBoot, "\xEB\x76\x90" "EXFAT ", 11); /* Boot jump code (x86), OEM name */ + st_qword(buf + BPB_VolOfsEx, b_vol); /* Volume offset in the physical drive [sector] */ + st_qword(buf + BPB_TotSecEx, sz_vol); /* Volume size [sector] */ + st_dword(buf + BPB_FatOfsEx, (DWORD)(b_fat - b_vol)); /* FAT offset [sector] */ + st_dword(buf + BPB_FatSzEx, sz_fat); /* FAT size [sector] */ + st_dword(buf + BPB_DataOfsEx, (DWORD)(b_data - b_vol)); /* Data offset [sector] */ + st_dword(buf + BPB_NumClusEx, n_clst); /* Number of clusters */ + st_dword(buf + BPB_RootClusEx, 2 + clen[0] + clen[1]); /* Root dir cluster # */ + st_dword(buf + BPB_VolIDEx, vsn); /* VSN */ + st_word(buf + BPB_FSVerEx, 0x100); /* Filesystem version (1.00) */ + for (buf[BPB_BytsPerSecEx] = 0, i = ss; i >>= 1; buf[BPB_BytsPerSecEx]++) ; /* Log2 of sector size [byte] */ + for (buf[BPB_SecPerClusEx] = 0, i = sz_au; i >>= 1; buf[BPB_SecPerClusEx]++) ; /* Log2 of cluster size [sector] */ + buf[BPB_NumFATsEx] = 1; /* Number of FATs */ + buf[BPB_DrvNumEx] = 0x80; /* Drive number (for int13) */ + st_word(buf + BS_BootCodeEx, 0xFEEB); /* Boot code (x86) */ + st_word(buf + BS_55AA, 0xAA55); /* Signature (placed here regardless of sector size) */ + for (i = sum = 0; i < ss; i++) { /* VBR checksum */ + if (i != BPB_VolFlagEx && i != BPB_VolFlagEx + 1 && i != BPB_PercInUseEx) sum = xsum32(buf[i], sum); + } + if (disk_write(pdrv, buf, sect++, 1) != RES_OK) LEAVE_MKFS(FR_DISK_ERR); + /* Extended bootstrap record (+1..+8) */ + memset(buf, 0, ss); + st_word(buf + ss - 2, 0xAA55); /* Signature (placed at end of sector) */ + for (j = 1; j < 9; j++) { + for (i = 0; i < ss; sum = xsum32(buf[i++], sum)) ; /* VBR checksum */ + if (disk_write(pdrv, buf, sect++, 1) != RES_OK) LEAVE_MKFS(FR_DISK_ERR); + } + /* OEM/Reserved record (+9..+10) */ + memset(buf, 0, ss); + for ( ; j < 11; j++) { + for (i = 0; i < ss; sum = xsum32(buf[i++], sum)) ; /* VBR checksum */ + if (disk_write(pdrv, buf, sect++, 1) != RES_OK) LEAVE_MKFS(FR_DISK_ERR); + } + /* Sum record (+11) */ + for (i = 0; i < ss; i += 4) st_dword(buf + i, sum); /* Fill with checksum value */ + if (disk_write(pdrv, buf, sect++, 1) != RES_OK) LEAVE_MKFS(FR_DISK_ERR); + } + + } else +#endif /* FF_FS_EXFAT */ + { /* Create an FAT/FAT32 volume */ + do { + pau = sz_au; + /* Pre-determine number of clusters and FAT sub-type */ + if (fsty == FS_FAT32) { /* FAT32 volume */ + if (pau == 0) { /* AU auto-selection */ + n = (DWORD)sz_vol / 0x20000; /* Volume size in unit of 128KS */ + for (i = 0, pau = 1; cst32[i] && cst32[i] <= n; i++, pau <<= 1) ; /* Get from table */ + } + n_clst = (DWORD)sz_vol / pau; /* Number of clusters */ + sz_fat = (n_clst * 4 + 8 + ss - 1) / ss; /* FAT size [sector] */ + sz_rsv = 32; /* Number of reserved sectors */ + sz_dir = 0; /* No static directory */ + if (n_clst <= MAX_FAT16 || n_clst > MAX_FAT32) LEAVE_MKFS(FR_MKFS_ABORTED); + } else { /* FAT volume */ + if (pau == 0) { /* au auto-selection */ + n = (DWORD)sz_vol / 0x1000; /* Volume size in unit of 4KS */ + for (i = 0, pau = 1; cst[i] && cst[i] <= n; i++, pau <<= 1) ; /* Get from table */ + } + n_clst = (DWORD)sz_vol / pau; + if (n_clst > MAX_FAT12) { + n = n_clst * 2 + 4; /* FAT size [byte] */ + } else { + fsty = FS_FAT12; + n = (n_clst * 3 + 1) / 2 + 3; /* FAT size [byte] */ + } + sz_fat = (n + ss - 1) / ss; /* FAT size [sector] */ + sz_rsv = 1; /* Number of reserved sectors */ + sz_dir = (DWORD)n_root * SZDIRE / ss; /* Root dir size [sector] */ + } + b_fat = b_vol + sz_rsv; /* FAT base */ + b_data = b_fat + sz_fat * n_fat + sz_dir; /* Data base */ + + /* Align data area to erase block boundary (for flash memory media) */ + n = (DWORD)(((b_data + sz_blk - 1) & ~(sz_blk - 1)) - b_data); /* Sectors to next nearest from current data base */ + if (fsty == FS_FAT32) { /* FAT32: Move FAT */ + sz_rsv += n; b_fat += n; + } else { /* FAT: Expand FAT */ + if (n % n_fat) { /* Adjust fractional error if needed */ + n--; sz_rsv++; b_fat++; + } + sz_fat += n / n_fat; + } + + /* Determine number of clusters and final check of validity of the FAT sub-type */ + if (sz_vol < b_data + pau * 16 - b_vol) LEAVE_MKFS(FR_MKFS_ABORTED); /* Too small volume? */ + n_clst = ((DWORD)sz_vol - sz_rsv - sz_fat * n_fat - sz_dir) / pau; + if (fsty == FS_FAT32) { + if (n_clst <= MAX_FAT16) { /* Too few clusters for FAT32? */ + if (sz_au == 0 && (sz_au = pau / 2) != 0) continue; /* Adjust cluster size and retry */ + LEAVE_MKFS(FR_MKFS_ABORTED); + } + } + if (fsty == FS_FAT16) { + if (n_clst > MAX_FAT16) { /* Too many clusters for FAT16 */ + if (sz_au == 0 && (pau * 2) <= 64) { + sz_au = pau * 2; continue; /* Adjust cluster size and retry */ + } + if ((fsopt & FM_FAT32)) { + fsty = FS_FAT32; continue; /* Switch type to FAT32 and retry */ + } + if (sz_au == 0 && (sz_au = pau * 2) <= 128) continue; /* Adjust cluster size and retry */ + LEAVE_MKFS(FR_MKFS_ABORTED); + } + if (n_clst <= MAX_FAT12) { /* Too few clusters for FAT16 */ + if (sz_au == 0 && (sz_au = pau * 2) <= 128) continue; /* Adjust cluster size and retry */ + LEAVE_MKFS(FR_MKFS_ABORTED); + } + } + if (fsty == FS_FAT12 && n_clst > MAX_FAT12) LEAVE_MKFS(FR_MKFS_ABORTED); /* Too many clusters for FAT12 */ + + /* Ok, it is the valid cluster configuration */ + break; + } while (1); + +#if FF_USE_TRIM + lba[0] = b_vol; lba[1] = b_vol + sz_vol - 1; /* Inform storage device that the volume area may be erased */ + disk_ioctl(pdrv, CTRL_TRIM, lba); +#endif + /* Create FAT VBR */ + memset(buf, 0, ss); + memcpy(buf + BS_JmpBoot, "\xEB\xFE\x90" "MSDOS5.0", 11); /* Boot jump code (x86), OEM name */ + st_word(buf + BPB_BytsPerSec, ss); /* Sector size [byte] */ + buf[BPB_SecPerClus] = (BYTE)pau; /* Cluster size [sector] */ + st_word(buf + BPB_RsvdSecCnt, (WORD)sz_rsv); /* Size of reserved area */ + buf[BPB_NumFATs] = (BYTE)n_fat; /* Number of FATs */ + st_word(buf + BPB_RootEntCnt, (WORD)((fsty == FS_FAT32) ? 0 : n_root)); /* Number of root directory entries */ + if (sz_vol < 0x10000) { + st_word(buf + BPB_TotSec16, (WORD)sz_vol); /* Volume size in 16-bit LBA */ + } else { + st_dword(buf + BPB_TotSec32, (DWORD)sz_vol); /* Volume size in 32-bit LBA */ + } + buf[BPB_Media] = 0xF8; /* Media descriptor byte */ + st_word(buf + BPB_SecPerTrk, 63); /* Number of sectors per track (for int13) */ + st_word(buf + BPB_NumHeads, 255); /* Number of heads (for int13) */ + st_dword(buf + BPB_HiddSec, (DWORD)b_vol); /* Volume offset in the physical drive [sector] */ + if (fsty == FS_FAT32) { + st_dword(buf + BS_VolID32, vsn); /* VSN */ + st_dword(buf + BPB_FATSz32, sz_fat); /* FAT size [sector] */ + st_dword(buf + BPB_RootClus32, 2); /* Root directory cluster # (2) */ + st_word(buf + BPB_FSInfo32, 1); /* Offset of FSINFO sector (VBR + 1) */ + st_word(buf + BPB_BkBootSec32, 6); /* Offset of backup VBR (VBR + 6) */ + buf[BS_DrvNum32] = 0x80; /* Drive number (for int13) */ + buf[BS_BootSig32] = 0x29; /* Extended boot signature */ + memcpy(buf + BS_VolLab32, "NO NAME " "FAT32 ", 19); /* Volume label, FAT signature */ + } else { + st_dword(buf + BS_VolID, vsn); /* VSN */ + st_word(buf + BPB_FATSz16, (WORD)sz_fat); /* FAT size [sector] */ + buf[BS_DrvNum] = 0x80; /* Drive number (for int13) */ + buf[BS_BootSig] = 0x29; /* Extended boot signature */ + memcpy(buf + BS_VolLab, "NO NAME " "FAT ", 19); /* Volume label, FAT signature */ + } + st_word(buf + BS_55AA, 0xAA55); /* Signature (offset is fixed here regardless of sector size) */ + if (disk_write(pdrv, buf, b_vol, 1) != RES_OK) LEAVE_MKFS(FR_DISK_ERR); /* Write it to the VBR sector */ + + /* Create FSINFO record if needed */ + if (fsty == FS_FAT32) { + disk_write(pdrv, buf, b_vol + 6, 1); /* Write backup VBR (VBR + 6) */ + memset(buf, 0, ss); + st_dword(buf + FSI_LeadSig, 0x41615252); + st_dword(buf + FSI_StrucSig, 0x61417272); + st_dword(buf + FSI_Free_Count, n_clst - 1); /* Number of free clusters */ + st_dword(buf + FSI_Nxt_Free, 2); /* Last allocated cluster# */ + st_word(buf + BS_55AA, 0xAA55); + disk_write(pdrv, buf, b_vol + 7, 1); /* Write backup FSINFO (VBR + 7) */ + disk_write(pdrv, buf, b_vol + 1, 1); /* Write original FSINFO (VBR + 1) */ + } + + /* Initialize FAT area */ + memset(buf, 0, sz_buf * ss); + sect = b_fat; /* FAT start sector */ + for (i = 0; i < n_fat; i++) { /* Initialize FATs each */ + if (fsty == FS_FAT32) { + st_dword(buf + 0, 0xFFFFFFF8); /* FAT[0] */ + st_dword(buf + 4, 0xFFFFFFFF); /* FAT[1] */ + st_dword(buf + 8, 0x0FFFFFFF); /* FAT[2] (root directory) */ + } else { + st_dword(buf + 0, (fsty == FS_FAT12) ? 0xFFFFF8 : 0xFFFFFFF8); /* FAT[0] and FAT[1] */ + } + nsect = sz_fat; /* Number of FAT sectors */ + do { /* Fill FAT sectors */ + n = (nsect > sz_buf) ? sz_buf : nsect; + if (disk_write(pdrv, buf, sect, (UINT)n) != RES_OK) LEAVE_MKFS(FR_DISK_ERR); + memset(buf, 0, ss); /* Rest of FAT all are cleared */ + sect += n; nsect -= n; + } while (nsect); + } + + /* Initialize root directory (fill with zero) */ + nsect = (fsty == FS_FAT32) ? pau : sz_dir; /* Number of root directory sectors */ + do { + n = (nsect > sz_buf) ? sz_buf : nsect; + if (disk_write(pdrv, buf, sect, (UINT)n) != RES_OK) LEAVE_MKFS(FR_DISK_ERR); + sect += n; nsect -= n; + } while (nsect); + } + + /* A FAT volume has been created here */ + + /* Determine system ID in the MBR partition table */ + if (FF_FS_EXFAT && fsty == FS_EXFAT) { + sys = 0x07; /* exFAT */ + } else { + if (fsty == FS_FAT32) { + sys = 0x0C; /* FAT32X */ + } else { + if (sz_vol >= 0x10000) { + sys = 0x06; /* FAT12/16 (large) */ + } else { + sys = (fsty == FS_FAT16) ? 0x04 : 0x01; /* FAT16 : FAT12 */ + } + } + } + + /* Update partition information */ + if (FF_MULTI_PARTITION && ipart != 0) { /* Volume is in the existing partition */ + if (!FF_LBA64 || !(fsopt & 0x80)) { + /* Update system ID in the partition table */ + if (disk_read(pdrv, buf, 0, 1) != RES_OK) LEAVE_MKFS(FR_DISK_ERR); /* Read the MBR */ + buf[MBR_Table + (ipart - 1) * SZ_PTE + PTE_System] = sys; /* Set system ID */ + if (disk_write(pdrv, buf, 0, 1) != RES_OK) LEAVE_MKFS(FR_DISK_ERR); /* Write it back to the MBR */ + } + } else { /* Volume as a new single partition */ + if (!(fsopt & FM_SFD)) { /* Create partition table if not in SFD */ + lba[0] = sz_vol; lba[1] = 0; + fr = create_partition(pdrv, lba, sys, buf); + if (fr != FR_OK) LEAVE_MKFS(fr); + } + } + + if (disk_ioctl(pdrv, CTRL_SYNC, 0) != RES_OK) LEAVE_MKFS(FR_DISK_ERR); + + LEAVE_MKFS(FR_OK); +} + + + + +#if FF_MULTI_PARTITION +/*-----------------------------------------------------------------------*/ +/* Create Partition Table on the Physical Drive */ +/*-----------------------------------------------------------------------*/ + +FRESULT f_fdisk ( + BYTE pdrv, /* Physical drive number */ + const LBA_t ptbl[], /* Pointer to the size table for each partitions */ + void* work /* Pointer to the working buffer (null: use heap memory) */ +) +{ + BYTE *buf = (BYTE*)work; + DSTATUS stat; + + + stat = disk_initialize(pdrv); + if (stat & STA_NOINIT) return FR_NOT_READY; + if (stat & STA_PROTECT) return FR_WRITE_PROTECTED; +#if FF_USE_LFN == 3 + if (!buf) buf = ff_memalloc(FF_MAX_SS); /* Use heap memory for working buffer */ +#endif + if (!buf) return FR_NOT_ENOUGH_CORE; + + LEAVE_MKFS(create_partition(pdrv, ptbl, 0x07, buf)); +} + +#endif /* FF_MULTI_PARTITION */ +#endif /* !FF_FS_READONLY && FF_USE_MKFS */ + + + + +#if FF_USE_STRFUNC +#if FF_USE_LFN && FF_LFN_UNICODE && (FF_STRF_ENCODE < 0 || FF_STRF_ENCODE > 3) +#error Wrong FF_STRF_ENCODE setting +#endif +/*-----------------------------------------------------------------------*/ +/* Get a String from the File */ +/*-----------------------------------------------------------------------*/ + +TCHAR* f_gets ( + TCHAR* buff, /* Pointer to the buffer to store read string */ + int len, /* Size of string buffer (items) */ + FIL* fp /* Pointer to the file object */ +) +{ + int nc = 0; + TCHAR *p = buff; + BYTE s[4]; + UINT rc; + DWORD dc; +#if FF_USE_LFN && FF_LFN_UNICODE && FF_STRF_ENCODE <= 2 + WCHAR wc; +#endif +#if FF_USE_LFN && FF_LFN_UNICODE && FF_STRF_ENCODE == 3 + UINT ct; +#endif + +#if FF_USE_LFN && FF_LFN_UNICODE /* With code conversion (Unicode API) */ + /* Make a room for the character and terminator */ + if (FF_LFN_UNICODE == 1) len -= (FF_STRF_ENCODE == 0) ? 1 : 2; + if (FF_LFN_UNICODE == 2) len -= (FF_STRF_ENCODE == 0) ? 3 : 4; + if (FF_LFN_UNICODE == 3) len -= 1; + while (nc < len) { +#if FF_STRF_ENCODE == 0 /* Read a character in ANSI/OEM */ + f_read(fp, s, 1, &rc); /* Get a code unit */ + if (rc != 1) break; /* EOF? */ + wc = s[0]; + if (dbc_1st((BYTE)wc)) { /* DBC 1st byte? */ + f_read(fp, s, 1, &rc); /* Get 2nd byte */ + if (rc != 1 || !dbc_2nd(s[0])) continue; /* Wrong code? */ + wc = wc << 8 | s[0]; + } + dc = ff_oem2uni(wc, CODEPAGE); /* Convert ANSI/OEM into Unicode */ + if (dc == 0) continue; /* Conversion error? */ +#elif FF_STRF_ENCODE == 1 || FF_STRF_ENCODE == 2 /* Read a character in UTF-16LE/BE */ + f_read(fp, s, 2, &rc); /* Get a code unit */ + if (rc != 2) break; /* EOF? */ + dc = (FF_STRF_ENCODE == 1) ? ld_word(s) : s[0] << 8 | s[1]; + if (IsSurrogateL(dc)) continue; /* Broken surrogate pair? */ + if (IsSurrogateH(dc)) { /* High surrogate? */ + f_read(fp, s, 2, &rc); /* Get low surrogate */ + if (rc != 2) break; /* EOF? */ + wc = (FF_STRF_ENCODE == 1) ? ld_word(s) : s[0] << 8 | s[1]; + if (!IsSurrogateL(wc)) continue; /* Broken surrogate pair? */ + dc = ((dc & 0x3FF) + 0x40) << 10 | (wc & 0x3FF); /* Merge surrogate pair */ + } +#else /* Read a character in UTF-8 */ + f_read(fp, s, 1, &rc); /* Get a code unit */ + if (rc != 1) break; /* EOF? */ + dc = s[0]; + if (dc >= 0x80) { /* Multi-byte sequence? */ + ct = 0; + if ((dc & 0xE0) == 0xC0) { dc &= 0x1F; ct = 1; } /* 2-byte sequence? */ + if ((dc & 0xF0) == 0xE0) { dc &= 0x0F; ct = 2; } /* 3-byte sequence? */ + if ((dc & 0xF8) == 0xF0) { dc &= 0x07; ct = 3; } /* 4-byte sequence? */ + if (ct == 0) continue; + f_read(fp, s, ct, &rc); /* Get trailing bytes */ + if (rc != ct) break; + rc = 0; + do { /* Merge the byte sequence */ + if ((s[rc] & 0xC0) != 0x80) break; + dc = dc << 6 | (s[rc] & 0x3F); + } while (++rc < ct); + if (rc != ct || dc < 0x80 || IsSurrogate(dc) || dc >= 0x110000) continue; /* Wrong encoding? */ + } +#endif + /* A code point is avaialble in dc to be output */ + + if (FF_USE_STRFUNC == 2 && dc == '\r') continue; /* Strip \r off if needed */ +#if FF_LFN_UNICODE == 1 || FF_LFN_UNICODE == 3 /* Output it in UTF-16/32 encoding */ + if (FF_LFN_UNICODE == 1 && dc >= 0x10000) { /* Out of BMP at UTF-16? */ + *p++ = (TCHAR)(0xD800 | ((dc >> 10) - 0x40)); nc++; /* Make and output high surrogate */ + dc = 0xDC00 | (dc & 0x3FF); /* Make low surrogate */ + } + *p++ = (TCHAR)dc; nc++; + if (dc == '\n') break; /* End of line? */ +#elif FF_LFN_UNICODE == 2 /* Output it in UTF-8 encoding */ + if (dc < 0x80) { /* Single byte? */ + *p++ = (TCHAR)dc; + nc++; + if (dc == '\n') break; /* End of line? */ + } else { + if (dc < 0x800) { /* 2-byte sequence? */ + *p++ = (TCHAR)(0xC0 | (dc >> 6 & 0x1F)); + *p++ = (TCHAR)(0x80 | (dc >> 0 & 0x3F)); + nc += 2; + } else { + if (dc < 0x10000) { /* 3-byte sequence? */ + *p++ = (TCHAR)(0xE0 | (dc >> 12 & 0x0F)); + *p++ = (TCHAR)(0x80 | (dc >> 6 & 0x3F)); + *p++ = (TCHAR)(0x80 | (dc >> 0 & 0x3F)); + nc += 3; + } else { /* 4-byte sequence? */ + *p++ = (TCHAR)(0xF0 | (dc >> 18 & 0x07)); + *p++ = (TCHAR)(0x80 | (dc >> 12 & 0x3F)); + *p++ = (TCHAR)(0x80 | (dc >> 6 & 0x3F)); + *p++ = (TCHAR)(0x80 | (dc >> 0 & 0x3F)); + nc += 4; + } + } + } +#endif + } + +#else /* Byte-by-byte read without any conversion (ANSI/OEM API) */ + len -= 1; /* Make a room for the terminator */ + while (nc < len) { + f_read(fp, s, 1, &rc); /* Get a byte */ + if (rc != 1) break; /* EOF? */ + dc = s[0]; + if (FF_USE_STRFUNC == 2 && dc == '\r') continue; + *p++ = (TCHAR)dc; nc++; + if (dc == '\n') break; + } +#endif + + *p = 0; /* Terminate the string */ + return nc ? buff : 0; /* When no data read due to EOF or error, return with error. */ +} + + + + +#if !FF_FS_READONLY +#include +#define SZ_PUTC_BUF 64 +#define SZ_NUM_BUF 32 + +/*-----------------------------------------------------------------------*/ +/* Put a Character to the File (with sub-functions) */ +/*-----------------------------------------------------------------------*/ + +/* Output buffer and work area */ + +typedef struct { + FIL *fp; /* Ptr to the writing file */ + int idx, nchr; /* Write index of buf[] (-1:error), number of encoding units written */ +#if FF_USE_LFN && FF_LFN_UNICODE == 1 + WCHAR hs; +#elif FF_USE_LFN && FF_LFN_UNICODE == 2 + BYTE bs[4]; + UINT wi, ct; +#endif + BYTE buf[SZ_PUTC_BUF]; /* Write buffer */ +} putbuff; + + +/* Buffered file write with code conversion */ + +static void putc_bfd (putbuff* pb, TCHAR c) +{ + UINT n; + int i, nc; +#if FF_USE_LFN && FF_LFN_UNICODE + WCHAR hs, wc; +#if FF_LFN_UNICODE == 2 + DWORD dc; + const TCHAR *tp; +#endif +#endif + + if (FF_USE_STRFUNC == 2 && c == '\n') { /* LF -> CRLF conversion */ + putc_bfd(pb, '\r'); + } + + i = pb->idx; /* Write index of pb->buf[] */ + if (i < 0) return; /* In write error? */ + nc = pb->nchr; /* Write unit counter */ + +#if FF_USE_LFN && FF_LFN_UNICODE +#if FF_LFN_UNICODE == 1 /* UTF-16 input */ + if (IsSurrogateH(c)) { /* High surrogate? */ + pb->hs = c; return; /* Save it for next */ + } + hs = pb->hs; pb->hs = 0; + if (hs != 0) { /* There is a leading high surrogate */ + if (!IsSurrogateL(c)) hs = 0; /* Discard high surrogate if not a surrogate pair */ + } else { + if (IsSurrogateL(c)) return; /* Discard stray low surrogate */ + } + wc = c; +#elif FF_LFN_UNICODE == 2 /* UTF-8 input */ + for (;;) { + if (pb->ct == 0) { /* Out of multi-byte sequence? */ + pb->bs[pb->wi = 0] = (BYTE)c; /* Save 1st byte */ + if ((BYTE)c < 0x80) break; /* Single byte? */ + if (((BYTE)c & 0xE0) == 0xC0) pb->ct = 1; /* 2-byte sequence? */ + if (((BYTE)c & 0xF0) == 0xE0) pb->ct = 2; /* 3-byte sequence? */ + if (((BYTE)c & 0xF1) == 0xF0) pb->ct = 3; /* 4-byte sequence? */ + return; + } else { /* In the multi-byte sequence */ + if (((BYTE)c & 0xC0) != 0x80) { /* Broken sequence? */ + pb->ct = 0; continue; + } + pb->bs[++pb->wi] = (BYTE)c; /* Save the trailing byte */ + if (--pb->ct == 0) break; /* End of multi-byte sequence? */ + return; + } + } + tp = (const TCHAR*)pb->bs; + dc = tchar2uni(&tp); /* UTF-8 ==> UTF-16 */ + if (dc == 0xFFFFFFFF) return; /* Wrong code? */ + wc = (WCHAR)dc; + hs = (WCHAR)(dc >> 16); +#elif FF_LFN_UNICODE == 3 /* UTF-32 input */ + if (IsSurrogate(c) || c >= 0x110000) return; /* Discard invalid code */ + if (c >= 0x10000) { /* Out of BMP? */ + hs = (WCHAR)(0xD800 | ((c >> 10) - 0x40)); /* Make high surrogate */ + wc = 0xDC00 | (c & 0x3FF); /* Make low surrogate */ + } else { + hs = 0; + wc = (WCHAR)c; + } +#endif + /* A code point in UTF-16 is available in hs and wc */ + +#if FF_STRF_ENCODE == 1 /* Write a code point in UTF-16LE */ + if (hs != 0) { /* Surrogate pair? */ + st_word(&pb->buf[i], hs); + i += 2; + nc++; + } + st_word(&pb->buf[i], wc); + i += 2; +#elif FF_STRF_ENCODE == 2 /* Write a code point in UTF-16BE */ + if (hs != 0) { /* Surrogate pair? */ + pb->buf[i++] = (BYTE)(hs >> 8); + pb->buf[i++] = (BYTE)hs; + nc++; + } + pb->buf[i++] = (BYTE)(wc >> 8); + pb->buf[i++] = (BYTE)wc; +#elif FF_STRF_ENCODE == 3 /* Write a code point in UTF-8 */ + if (hs != 0) { /* 4-byte sequence? */ + nc += 3; + hs = (hs & 0x3FF) + 0x40; + pb->buf[i++] = (BYTE)(0xF0 | hs >> 8); + pb->buf[i++] = (BYTE)(0x80 | (hs >> 2 & 0x3F)); + pb->buf[i++] = (BYTE)(0x80 | (hs & 3) << 4 | (wc >> 6 & 0x0F)); + pb->buf[i++] = (BYTE)(0x80 | (wc & 0x3F)); + } else { + if (wc < 0x80) { /* Single byte? */ + pb->buf[i++] = (BYTE)wc; + } else { + if (wc < 0x800) { /* 2-byte sequence? */ + nc += 1; + pb->buf[i++] = (BYTE)(0xC0 | wc >> 6); + } else { /* 3-byte sequence */ + nc += 2; + pb->buf[i++] = (BYTE)(0xE0 | wc >> 12); + pb->buf[i++] = (BYTE)(0x80 | (wc >> 6 & 0x3F)); + } + pb->buf[i++] = (BYTE)(0x80 | (wc & 0x3F)); + } + } +#else /* Write a code point in ANSI/OEM */ + if (hs != 0) return; + wc = ff_uni2oem(wc, CODEPAGE); /* UTF-16 ==> ANSI/OEM */ + if (wc == 0) return; + if (wc >= 0x100) { + pb->buf[i++] = (BYTE)(wc >> 8); nc++; + } + pb->buf[i++] = (BYTE)wc; +#endif + +#else /* ANSI/OEM input (without re-encoding) */ + pb->buf[i++] = (BYTE)c; +#endif + + if (i >= (int)(sizeof pb->buf) - 4) { /* Write buffered characters to the file */ + f_write(pb->fp, pb->buf, (UINT)i, &n); + i = (n == (UINT)i) ? 0 : -1; + } + pb->idx = i; + pb->nchr = nc + 1; +} + + +/* Flush remaining characters in the buffer */ + +static int putc_flush (putbuff* pb) +{ + UINT nw; + + if ( pb->idx >= 0 /* Flush buffered characters to the file */ + && f_write(pb->fp, pb->buf, (UINT)pb->idx, &nw) == FR_OK + && (UINT)pb->idx == nw) return pb->nchr; + return -1; +} + + +/* Initialize write buffer */ + +static void putc_init (putbuff* pb, FIL* fp) +{ + memset(pb, 0, sizeof (putbuff)); + pb->fp = fp; +} + + + +int f_putc ( + TCHAR c, /* A character to be output */ + FIL* fp /* Pointer to the file object */ +) +{ + putbuff pb; + + + putc_init(&pb, fp); + putc_bfd(&pb, c); /* Put the character */ + return putc_flush(&pb); +} + + + + +/*-----------------------------------------------------------------------*/ +/* Put a String to the File */ +/*-----------------------------------------------------------------------*/ + +int f_puts ( + const TCHAR* str, /* Pointer to the string to be output */ + FIL* fp /* Pointer to the file object */ +) +{ + putbuff pb; + + + putc_init(&pb, fp); + while (*str) putc_bfd(&pb, *str++); /* Put the string */ + return putc_flush(&pb); +} + + + + +/*-----------------------------------------------------------------------*/ +/* Put a Formatted String to the File (with sub-functions) */ +/*-----------------------------------------------------------------------*/ +#if FF_PRINT_FLOAT && FF_INTDEF == 2 +#include + +static int ilog10 (double n) /* Calculate log10(n) in integer output */ +{ + int rv = 0; + + while (n >= 10) { /* Decimate digit in right shift */ + if (n >= 100000) { + n /= 100000; rv += 5; + } else { + n /= 10; rv++; + } + } + while (n < 1) { /* Decimate digit in left shift */ + if (n < 0.00001) { + n *= 100000; rv -= 5; + } else { + n *= 10; rv--; + } + } + return rv; +} + + +static double i10x (int n) /* Calculate 10^n in integer input */ +{ + double rv = 1; + + while (n > 0) { /* Left shift */ + if (n >= 5) { + rv *= 100000; n -= 5; + } else { + rv *= 10; n--; + } + } + while (n < 0) { /* Right shift */ + if (n <= -5) { + rv /= 100000; n += 5; + } else { + rv /= 10; n++; + } + } + return rv; +} + + +static void ftoa ( + char* buf, /* Buffer to output the floating point string */ + double val, /* Value to output */ + int prec, /* Number of fractional digits */ + TCHAR fmt /* Notation */ +) +{ + int d; + int e = 0, m = 0; + char sign = 0; + double w; + const char *er = 0; + const char ds = FF_PRINT_FLOAT == 2 ? ',' : '.'; + + + if (isnan(val)) { /* Not a number? */ + er = "NaN"; + } else { + if (prec < 0) prec = 6; /* Default precision? (6 fractional digits) */ + if (val < 0) { /* Nagative? */ + val = 0 - val; sign = '-'; + } else { + sign = '+'; + } + if (isinf(val)) { /* Infinite? */ + er = "INF"; + } else { + if (fmt == 'f') { /* Decimal notation? */ + val += i10x(0 - prec) / 2; /* Round (nearest) */ + m = ilog10(val); + if (m < 0) m = 0; + if (m + prec + 3 >= SZ_NUM_BUF) er = "OV"; /* Buffer overflow? */ + } else { /* E notation */ + if (val != 0) { /* Not a true zero? */ + val += i10x(ilog10(val) - prec) / 2; /* Round (nearest) */ + e = ilog10(val); + if (e > 99 || prec + 7 >= SZ_NUM_BUF) { /* Buffer overflow or E > +99? */ + er = "OV"; + } else { + if (e < -99) e = -99; + val /= i10x(e); /* Normalize */ + } + } + } + } + if (!er) { /* Not error condition */ + if (sign == '-') *buf++ = sign; /* Add a - if negative value */ + do { /* Put decimal number */ + if (m == -1) *buf++ = ds; /* Insert a decimal separator when get into fractional part */ + w = i10x(m); /* Snip the highest digit d */ + d = (int)(val / w); val -= d * w; + *buf++ = (char)('0' + d); /* Put the digit */ + } while (--m >= -prec); /* Output all digits specified by prec */ + if (fmt != 'f') { /* Put exponent if needed */ + *buf++ = (char)fmt; + if (e < 0) { + e = 0 - e; *buf++ = '-'; + } else { + *buf++ = '+'; + } + *buf++ = (char)('0' + e / 10); + *buf++ = (char)('0' + e % 10); + } + } + } + if (er) { /* Error condition */ + if (sign) *buf++ = sign; /* Add sign if needed */ + do *buf++ = *er++; while (*er); /* Put error symbol */ + } + *buf = 0; /* Term */ +} +#endif /* FF_PRINT_FLOAT && FF_INTDEF == 2 */ + + + +int f_printf ( + FIL* fp, /* Pointer to the file object */ + const TCHAR* fmt, /* Pointer to the format string */ + ... /* Optional arguments... */ +) +{ + va_list arp; + putbuff pb; + UINT i, j, w, f, r; + int prec; +#if FF_PRINT_LLI && FF_INTDEF == 2 + QWORD v; +#else + DWORD v; +#endif + TCHAR tc, pad, *tp; + TCHAR nul = 0; + char d, str[SZ_NUM_BUF]; + + + putc_init(&pb, fp); + + va_start(arp, fmt); + + for (;;) { + tc = *fmt++; + if (tc == 0) break; /* End of format string */ + if (tc != '%') { /* Not an escape character (pass-through) */ + putc_bfd(&pb, tc); + continue; + } + f = w = 0; pad = ' '; prec = -1; /* Initialize parms */ + tc = *fmt++; + if (tc == '0') { /* Flag: '0' padded */ + pad = '0'; tc = *fmt++; + } else if (tc == '-') { /* Flag: Left aligned */ + f = 2; tc = *fmt++; + } + if (tc == '*') { /* Minimum width from an argument */ + w = va_arg(arp, int); + tc = *fmt++; + } else { + while (IsDigit(tc)) { /* Minimum width */ + w = w * 10 + tc - '0'; + tc = *fmt++; + } + } + if (tc == '.') { /* Precision */ + tc = *fmt++; + if (tc == '*') { /* Precision from an argument */ + prec = va_arg(arp, int); + tc = *fmt++; + } else { + prec = 0; + while (IsDigit(tc)) { /* Precision */ + prec = prec * 10 + tc - '0'; + tc = *fmt++; + } + } + } + if (tc == 'l') { /* Size: long int */ + f |= 4; tc = *fmt++; +#if FF_PRINT_LLI && FF_INTDEF == 2 + if (tc == 'l') { /* Size: long long int */ + f |= 8; tc = *fmt++; + } +#endif + } + if (tc == 0) break; /* End of format string */ + switch (tc) { /* Atgument type is... */ + case 'b': /* Unsigned binary */ + r = 2; break; + case 'o': /* Unsigned octal */ + r = 8; break; + case 'd': /* Signed decimal */ + case 'u': /* Unsigned decimal */ + r = 10; break; + case 'x': /* Unsigned hexdecimal (lower case) */ + case 'X': /* Unsigned hexdecimal (upper case) */ + r = 16; break; + case 'c': /* Character */ + putc_bfd(&pb, (TCHAR)va_arg(arp, int)); + continue; + case 's': /* String */ + tp = va_arg(arp, TCHAR*); /* Get a pointer argument */ + if (!tp) tp = &nul; /* Null ptr generates a null string */ + for (j = 0; tp[j]; j++) ; /* j = tcslen(tp) */ + if (prec >= 0 && j > (UINT)prec) j = prec; /* Limited length of string body */ + for ( ; !(f & 2) && j < w; j++) putc_bfd(&pb, pad); /* Left pads */ + while (*tp && prec--) putc_bfd(&pb, *tp++); /* Body */ + while (j++ < w) putc_bfd(&pb, ' '); /* Right pads */ + continue; +#if FF_PRINT_FLOAT && FF_INTDEF == 2 + case 'f': /* Floating point (decimal) */ + case 'e': /* Floating point (e) */ + case 'E': /* Floating point (E) */ + ftoa(str, va_arg(arp, double), prec, tc); /* Make a flaoting point string */ + for (j = strlen(str); !(f & 2) && j < w; j++) putc_bfd(&pb, pad); /* Left pads */ + for (i = 0; str[i]; putc_bfd(&pb, str[i++])) ; /* Body */ + while (j++ < w) putc_bfd(&pb, ' '); /* Right pads */ + continue; +#endif + default: /* Unknown type (pass-through) */ + putc_bfd(&pb, tc); continue; + } + + /* Get an integer argument and put it in numeral */ +#if FF_PRINT_LLI && FF_INTDEF == 2 + if (f & 8) { /* long long argument? */ + v = (QWORD)va_arg(arp, LONGLONG); + } else { + if (f & 4) { /* long argument? */ + v = (tc == 'd') ? (QWORD)(LONGLONG)va_arg(arp, long) : (QWORD)va_arg(arp, unsigned long); + } else { /* int/short/char argument */ + v = (tc == 'd') ? (QWORD)(LONGLONG)va_arg(arp, int) : (QWORD)va_arg(arp, unsigned int); + } + } + if (tc == 'd' && (v & 0x8000000000000000)) { /* Negative value? */ + v = 0 - v; f |= 1; + } +#else + if (f & 4) { /* long argument? */ + v = (DWORD)va_arg(arp, long); + } else { /* int/short/char argument */ + v = (tc == 'd') ? (DWORD)(long)va_arg(arp, int) : (DWORD)va_arg(arp, unsigned int); + } + if (tc == 'd' && (v & 0x80000000)) { /* Negative value? */ + v = 0 - v; f |= 1; + } +#endif + i = 0; + do { /* Make an integer number string */ + d = (char)(v % r); v /= r; + if (d > 9) d += (tc == 'x') ? 0x27 : 0x07; + str[i++] = d + '0'; + } while (v && i < SZ_NUM_BUF); + if (f & 1) str[i++] = '-'; /* Sign */ + /* Write it */ + for (j = i; !(f & 2) && j < w; j++) putc_bfd(&pb, pad); /* Left pads */ + do putc_bfd(&pb, (TCHAR)str[--i]); while (i); /* Body */ + while (j++ < w) putc_bfd(&pb, ' '); /* Right pads */ + } + + va_end(arp); + + return putc_flush(&pb); +} + +#endif /* !FF_FS_READONLY */ +#endif /* FF_USE_STRFUNC */ + + + +#if FF_CODE_PAGE == 0 +/*-----------------------------------------------------------------------*/ +/* Set Active Codepage for the Path Name */ +/*-----------------------------------------------------------------------*/ + +FRESULT f_setcp ( + WORD cp /* Value to be set as active code page */ +) +{ + static const WORD validcp[22] = { 437, 720, 737, 771, 775, 850, 852, 855, 857, 860, 861, 862, 863, 864, 865, 866, 869, 932, 936, 949, 950, 0}; + static const BYTE* const tables[22] = {Ct437, Ct720, Ct737, Ct771, Ct775, Ct850, Ct852, Ct855, Ct857, Ct860, Ct861, Ct862, Ct863, Ct864, Ct865, Ct866, Ct869, Dc932, Dc936, Dc949, Dc950, 0}; + UINT i; + + + for (i = 0; validcp[i] != 0 && validcp[i] != cp; i++) ; /* Find the code page */ + if (validcp[i] != cp) return FR_INVALID_PARAMETER; /* Not found? */ + + CodePage = cp; + if (cp >= 900) { /* DBCS */ + ExCvt = 0; + DbcTbl = tables[i]; + } else { /* SBCS */ + ExCvt = tables[i]; + DbcTbl = 0; + } + return FR_OK; +} +#endif /* FF_CODE_PAGE == 0 */ diff --git a/kernel/fatfs/ff.h b/kernel/fatfs/ff.h new file mode 100644 index 0000000..4866576 --- /dev/null +++ b/kernel/fatfs/ff.h @@ -0,0 +1,422 @@ +/*----------------------------------------------------------------------------/ +/ FatFs - Generic FAT Filesystem module R0.14b / +/-----------------------------------------------------------------------------/ +/ +/ Copyright (C) 2021, ChaN, all right reserved. +/ +/ FatFs module is an open source software. Redistribution and use of FatFs in +/ source and binary forms, with or without modification, are permitted provided +/ that the following condition is met: + +/ 1. Redistributions of source code must retain the above copyright notice, +/ this condition and the following disclaimer. +/ +/ This software is provided by the copyright holder and contributors "AS IS" +/ and any warranties related to this software are DISCLAIMED. +/ The copyright owner or contributors be NOT LIABLE for any damages caused +/ by use of this software. +/ +/----------------------------------------------------------------------------*/ + + +#ifndef FF_DEFINED +#define FF_DEFINED 86631 /* Revision ID */ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "ffconf.h" /* FatFs configuration options */ + +#if FF_DEFINED != FFCONF_DEF +#error Wrong configuration file (ffconf.h). +#endif + + +/* Integer types used for FatFs API */ + +#if defined(_WIN32) /* Windows VC++ (for development only) */ +#define FF_INTDEF 2 +#include +typedef unsigned __int64 QWORD; +#include +#define isnan(v) _isnan(v) +#define isinf(v) (!_finite(v)) + +#elif (defined(__STDC_VERSION__) && __STDC_VERSION__ >= 199901L) || defined(__cplusplus) /* C99 or later */ +#define FF_INTDEF 2 +#include +typedef unsigned int UINT; /* int must be 16-bit or 32-bit */ +typedef unsigned char BYTE; /* char must be 8-bit */ +typedef uint16_t WORD; /* 16-bit unsigned integer */ +typedef uint32_t DWORD; /* 32-bit unsigned integer */ +typedef uint64_t QWORD; /* 64-bit unsigned integer */ +typedef WORD WCHAR; /* UTF-16 character type */ + +#else /* Earlier than C99 */ +#define FF_INTDEF 1 +typedef unsigned int UINT; /* int must be 16-bit or 32-bit */ +typedef unsigned char BYTE; /* char must be 8-bit */ +typedef unsigned short WORD; /* 16-bit unsigned integer */ +typedef unsigned long DWORD; /* 32-bit unsigned integer */ +typedef WORD WCHAR; /* UTF-16 character type */ +#endif + + +/* Type of file size and LBA variables */ + +#if FF_FS_EXFAT +#if FF_INTDEF != 2 +#error exFAT feature wants C99 or later +#endif +typedef QWORD FSIZE_t; +#if FF_LBA64 +typedef QWORD LBA_t; +#else +typedef DWORD LBA_t; +#endif +#else +#if FF_LBA64 +#error exFAT needs to be enabled when enable 64-bit LBA +#endif +typedef DWORD FSIZE_t; +typedef DWORD LBA_t; +#endif + + + +/* Type of path name strings on FatFs API (TCHAR) */ + +#if FF_USE_LFN && FF_LFN_UNICODE == 1 /* Unicode in UTF-16 encoding */ +typedef WCHAR TCHAR; +#define _T(x) L ## x +#define _TEXT(x) L ## x +#elif FF_USE_LFN && FF_LFN_UNICODE == 2 /* Unicode in UTF-8 encoding */ +typedef char TCHAR; +#define _T(x) u8 ## x +#define _TEXT(x) u8 ## x +#elif FF_USE_LFN && FF_LFN_UNICODE == 3 /* Unicode in UTF-32 encoding */ +typedef DWORD TCHAR; +#define _T(x) U ## x +#define _TEXT(x) U ## x +#elif FF_USE_LFN && (FF_LFN_UNICODE < 0 || FF_LFN_UNICODE > 3) +#error Wrong FF_LFN_UNICODE setting +#else /* ANSI/OEM code in SBCS/DBCS */ +typedef char TCHAR; +#define _T(x) x +#define _TEXT(x) x +#endif + + + +/* Definitions of volume management */ + +#if FF_MULTI_PARTITION /* Multiple partition configuration */ +typedef struct { + BYTE pd; /* Physical drive number */ + BYTE pt; /* Partition: 0:Auto detect, 1-4:Forced partition) */ +} PARTITION; +extern PARTITION VolToPart[]; /* Volume - Partition mapping table */ +#endif + +#if FF_STR_VOLUME_ID +#ifndef FF_VOLUME_STRS +extern const char* VolumeStr[FF_VOLUMES]; /* User defied volume ID */ +#endif +#endif + + + +/* Filesystem object structure (FATFS) */ + +typedef struct { + BYTE fs_type; /* Filesystem type (0:not mounted) */ + BYTE pdrv; /* Associated physical drive */ + BYTE n_fats; /* Number of FATs (1 or 2) */ + BYTE wflag; /* win[] flag (b0:dirty) */ + BYTE fsi_flag; /* FSINFO flags (b7:disabled, b0:dirty) */ + WORD id; /* Volume mount ID */ + WORD n_rootdir; /* Number of root directory entries (FAT12/16) */ + WORD csize; /* Cluster size [sectors] */ +#if FF_MAX_SS != FF_MIN_SS + WORD ssize; /* Sector size (512, 1024, 2048 or 4096) */ +#endif +#if FF_USE_LFN + WCHAR* lfnbuf; /* LFN working buffer */ +#endif +#if FF_FS_EXFAT + BYTE* dirbuf; /* Directory entry block scratchpad buffer for exFAT */ +#endif +#if FF_FS_REENTRANT + FF_SYNC_t sobj; /* Identifier of sync object */ +#endif +#if !FF_FS_READONLY + DWORD last_clst; /* Last allocated cluster */ + DWORD free_clst; /* Number of free clusters */ +#endif +#if FF_FS_RPATH + DWORD cdir; /* Current directory start cluster (0:root) */ +#if FF_FS_EXFAT + DWORD cdc_scl; /* Containing directory start cluster (invalid when cdir is 0) */ + DWORD cdc_size; /* b31-b8:Size of containing directory, b7-b0: Chain status */ + DWORD cdc_ofs; /* Offset in the containing directory (invalid when cdir is 0) */ +#endif +#endif + DWORD n_fatent; /* Number of FAT entries (number of clusters + 2) */ + DWORD fsize; /* Size of an FAT [sectors] */ + LBA_t volbase; /* Volume base sector */ + LBA_t fatbase; /* FAT base sector */ + LBA_t dirbase; /* Root directory base sector/cluster */ + LBA_t database; /* Data base sector */ +#if FF_FS_EXFAT + LBA_t bitbase; /* Allocation bitmap base sector */ +#endif + LBA_t winsect; /* Current sector appearing in the win[] */ + BYTE win[FF_MAX_SS]; /* Disk access window for Directory, FAT (and file data at tiny cfg) */ +} FATFS; + + + +/* Object ID and allocation information (FFOBJID) */ + +typedef struct { + FATFS* fs; /* Pointer to the hosting volume of this object */ + WORD id; /* Hosting volume mount ID */ + BYTE attr; /* Object attribute */ + BYTE stat; /* Object chain status (b1-0: =0:not contiguous, =2:contiguous, =3:fragmented in this session, b2:sub-directory stretched) */ + DWORD sclust; /* Object data start cluster (0:no cluster or root directory) */ + FSIZE_t objsize; /* Object size (valid when sclust != 0) */ +#if FF_FS_EXFAT + DWORD n_cont; /* Size of first fragment - 1 (valid when stat == 3) */ + DWORD n_frag; /* Size of last fragment needs to be written to FAT (valid when not zero) */ + DWORD c_scl; /* Containing directory start cluster (valid when sclust != 0) */ + DWORD c_size; /* b31-b8:Size of containing directory, b7-b0: Chain status (valid when c_scl != 0) */ + DWORD c_ofs; /* Offset in the containing directory (valid when file object and sclust != 0) */ +#endif +#if FF_FS_LOCK + UINT lockid; /* File lock ID origin from 1 (index of file semaphore table Files[]) */ +#endif +} FFOBJID; + + + +/* File object structure (FIL) */ + +typedef struct { + FFOBJID obj; /* Object identifier (must be the 1st member to detect invalid object pointer) */ + BYTE flag; /* File status flags */ + BYTE err; /* Abort flag (error code) */ + FSIZE_t fptr; /* File read/write pointer (Zeroed on file open) */ + DWORD clust; /* Current cluster of fpter (invalid when fptr is 0) */ + LBA_t sect; /* Sector number appearing in buf[] (0:invalid) */ +#if !FF_FS_READONLY + LBA_t dir_sect; /* Sector number containing the directory entry (not used at exFAT) */ + BYTE* dir_ptr; /* Pointer to the directory entry in the win[] (not used at exFAT) */ +#endif +#if FF_USE_FASTSEEK + DWORD* cltbl; /* Pointer to the cluster link map table (nulled on open, set by application) */ +#endif +#if !FF_FS_TINY + BYTE buf[FF_MAX_SS]; /* File private data read/write window */ +#endif +} FIL; + + + +/* Directory object structure (DIR) */ + +typedef struct { + FFOBJID obj; /* Object identifier */ + DWORD dptr; /* Current read/write offset */ + DWORD clust; /* Current cluster */ + LBA_t sect; /* Current sector (0:Read operation has terminated) */ + BYTE* dir; /* Pointer to the directory item in the win[] */ + BYTE fn[12]; /* SFN (in/out) {body[8],ext[3],status[1]} */ +#if FF_USE_LFN + DWORD blk_ofs; /* Offset of current entry block being processed (0xFFFFFFFF:Invalid) */ +#endif +#if FF_USE_FIND + const TCHAR* pat; /* Pointer to the name matching pattern */ +#endif +} DIR; + + + +/* File information structure (FILINFO) */ + +typedef struct { + FSIZE_t fsize; /* File size */ + WORD fdate; /* Modified date */ + WORD ftime; /* Modified time */ + BYTE fattrib; /* File attribute */ +#if FF_USE_LFN + TCHAR altname[FF_SFN_BUF + 1];/* Altenative file name */ + TCHAR fname[FF_LFN_BUF + 1]; /* Primary file name */ +#else + TCHAR fname[12 + 1]; /* File name */ +#endif +} FILINFO; + + + +/* Format parameter structure (MKFS_PARM) */ + +typedef struct { + BYTE fmt; /* Format option (FM_FAT, FM_FAT32, FM_EXFAT and FM_SFD) */ + BYTE n_fat; /* Number of FATs */ + UINT align; /* Data area alignment (sector) */ + UINT n_root; /* Number of root directory entries */ + DWORD au_size; /* Cluster size (byte) */ +} MKFS_PARM; + + + +/* File function return code (FRESULT) */ + +typedef enum { + FR_OK = 0, /* (0) Succeeded */ + FR_DISK_ERR, /* (1) A hard error occurred in the low level disk I/O layer */ + FR_INT_ERR, /* (2) Assertion failed */ + FR_NOT_READY, /* (3) The physical drive cannot work */ + FR_NO_FILE, /* (4) Could not find the file */ + FR_NO_PATH, /* (5) Could not find the path */ + FR_INVALID_NAME, /* (6) The path name format is invalid */ + FR_DENIED, /* (7) Access denied due to prohibited access or directory full */ + FR_EXIST, /* (8) Access denied due to prohibited access */ + FR_INVALID_OBJECT, /* (9) The file/directory object is invalid */ + FR_WRITE_PROTECTED, /* (10) The physical drive is write protected */ + FR_INVALID_DRIVE, /* (11) The logical drive number is invalid */ + FR_NOT_ENABLED, /* (12) The volume has no work area */ + FR_NO_FILESYSTEM, /* (13) There is no valid FAT volume */ + FR_MKFS_ABORTED, /* (14) The f_mkfs() aborted due to any problem */ + FR_TIMEOUT, /* (15) Could not get a grant to access the volume within defined period */ + FR_LOCKED, /* (16) The operation is rejected according to the file sharing policy */ + FR_NOT_ENOUGH_CORE, /* (17) LFN working buffer could not be allocated */ + FR_TOO_MANY_OPEN_FILES, /* (18) Number of open files > FF_FS_LOCK */ + FR_INVALID_PARAMETER /* (19) Given parameter is invalid */ +} FRESULT; + + + +/*--------------------------------------------------------------*/ +/* FatFs module application interface */ + +FRESULT f_open (FIL* fp, const TCHAR* path, BYTE mode); /* Open or create a file */ +FRESULT f_close (FIL* fp); /* Close an open file object */ +FRESULT f_read (FIL* fp, void* buff, UINT btr, UINT* br); /* Read data from the file */ +FRESULT f_write (FIL* fp, const void* buff, UINT btw, UINT* bw); /* Write data to the file */ +FRESULT f_lseek (FIL* fp, FSIZE_t ofs); /* Move file pointer of the file object */ +FRESULT f_truncate (FIL* fp); /* Truncate the file */ +FRESULT f_sync (FIL* fp); /* Flush cached data of the writing file */ +FRESULT f_opendir (DIR* dp, const TCHAR* path); /* Open a directory */ +FRESULT f_closedir (DIR* dp); /* Close an open directory */ +FRESULT f_readdir (DIR* dp, FILINFO* fno); /* Read a directory item */ +FRESULT f_findfirst (DIR* dp, FILINFO* fno, const TCHAR* path, const TCHAR* pattern); /* Find first file */ +FRESULT f_findnext (DIR* dp, FILINFO* fno); /* Find next file */ +FRESULT f_mkdir (const TCHAR* path); /* Create a sub directory */ +FRESULT f_unlink (const TCHAR* path); /* Delete an existing file or directory */ +FRESULT f_rename (const TCHAR* path_old, const TCHAR* path_new); /* Rename/Move a file or directory */ +FRESULT f_stat (const TCHAR* path, FILINFO* fno); /* Get file status */ +FRESULT f_chmod (const TCHAR* path, BYTE attr, BYTE mask); /* Change attribute of a file/dir */ +FRESULT f_utime (const TCHAR* path, const FILINFO* fno); /* Change timestamp of a file/dir */ +FRESULT f_chdir (const TCHAR* path); /* Change current directory */ +FRESULT f_chdrive (const TCHAR* path); /* Change current drive */ +FRESULT f_getcwd (TCHAR* buff, UINT len); /* Get current directory */ +FRESULT f_getfree (const TCHAR* path, DWORD* nclst, FATFS** fatfs); /* Get number of free clusters on the drive */ +FRESULT f_getlabel (const TCHAR* path, TCHAR* label, DWORD* vsn); /* Get volume label */ +FRESULT f_setlabel (const TCHAR* label); /* Set volume label */ +FRESULT f_forward (FIL* fp, UINT(*func)(const BYTE*,UINT), UINT btf, UINT* bf); /* Forward data to the stream */ +FRESULT f_expand (FIL* fp, FSIZE_t fsz, BYTE opt); /* Allocate a contiguous block to the file */ +FRESULT f_mount (FATFS* fs, const TCHAR* path, BYTE opt); /* Mount/Unmount a logical drive */ +FRESULT f_mkfs (const TCHAR* path, const MKFS_PARM* opt, void* work, UINT len); /* Create a FAT volume */ +FRESULT f_fdisk (BYTE pdrv, const LBA_t ptbl[], void* work); /* Divide a physical drive into some partitions */ +FRESULT f_setcp (WORD cp); /* Set current code page */ +int f_putc (TCHAR c, FIL* fp); /* Put a character to the file */ +int f_puts (const TCHAR* str, FIL* cp); /* Put a string to the file */ +int f_printf (FIL* fp, const TCHAR* str, ...); /* Put a formatted string to the file */ +TCHAR* f_gets (TCHAR* buff, int len, FIL* fp); /* Get a string from the file */ + +#define f_eof(fp) ((int)((fp)->fptr == (fp)->obj.objsize)) +#define f_error(fp) ((fp)->err) +#define f_tell(fp) ((fp)->fptr) +#define f_size(fp) ((fp)->obj.objsize) +#define f_rewind(fp) f_lseek((fp), 0) +#define f_rewinddir(dp) f_readdir((dp), 0) +#define f_rmdir(path) f_unlink(path) +#define f_unmount(path) f_mount(0, path, 0) + + + + +/*--------------------------------------------------------------*/ +/* Additional user defined functions */ + +/* RTC function */ +#if !FF_FS_READONLY && !FF_FS_NORTC +DWORD get_fattime (void); +#endif + +/* LFN support functions */ +#if FF_USE_LFN >= 1 /* Code conversion (defined in unicode.c) */ +WCHAR ff_oem2uni (WCHAR oem, WORD cp); /* OEM code to Unicode conversion */ +WCHAR ff_uni2oem (DWORD uni, WORD cp); /* Unicode to OEM code conversion */ +DWORD ff_wtoupper (DWORD uni); /* Unicode upper-case conversion */ +#endif +#if FF_USE_LFN == 3 /* Dynamic memory allocation */ +void* ff_memalloc (UINT msize); /* Allocate memory block */ +void ff_memfree (void* mblock); /* Free memory block */ +#endif + +/* Sync functions */ +#if FF_FS_REENTRANT +int ff_cre_syncobj (BYTE vol, FF_SYNC_t* sobj); /* Create a sync object */ +int ff_req_grant (FF_SYNC_t sobj); /* Lock sync object */ +void ff_rel_grant (FF_SYNC_t sobj); /* Unlock sync object */ +int ff_del_syncobj (FF_SYNC_t sobj); /* Delete a sync object */ +#endif + + + + +/*--------------------------------------------------------------*/ +/* Flags and offset address */ + + +/* File access mode and open method flags (3rd argument of f_open) */ +#define FA_READ 0x01 +#define FA_WRITE 0x02 +#define FA_OPEN_EXISTING 0x00 +#define FA_CREATE_NEW 0x04 +#define FA_CREATE_ALWAYS 0x08 +#define FA_OPEN_ALWAYS 0x10 +#define FA_OPEN_APPEND 0x30 + +/* Fast seek controls (2nd argument of f_lseek) */ +#define CREATE_LINKMAP ((FSIZE_t)0 - 1) + +/* Format options (2nd argument of f_mkfs) */ +#define FM_FAT 0x01 +#define FM_FAT32 0x02 +#define FM_EXFAT 0x04 +#define FM_ANY 0x07 +#define FM_SFD 0x08 + +/* Filesystem type (FATFS.fs_type) */ +#define FS_FAT12 1 +#define FS_FAT16 2 +#define FS_FAT32 3 +#define FS_EXFAT 4 + +/* File attribute bits for directory entry (FILINFO.fattrib) */ +#define AM_RDO 0x01 /* Read only */ +#define AM_HID 0x02 /* Hidden */ +#define AM_SYS 0x04 /* System */ +#define AM_DIR 0x10 /* Directory */ +#define AM_ARC 0x20 /* Archive */ + + +#ifdef __cplusplus +} +#endif + +#endif /* FF_DEFINED */ diff --git a/kernel/fatfs/ffconf.h b/kernel/fatfs/ffconf.h new file mode 100644 index 0000000..64f685d --- /dev/null +++ b/kernel/fatfs/ffconf.h @@ -0,0 +1,38 @@ +#ifndef FFCONF_DEF +#define FFCONF_DEF 86631 +#define FF_FS_READONLY 0 +#define FF_FS_MINIMIZE 0 +#define FF_USE_STRFUNC 2 +#define FF_USE_FIND 0 +#define FF_USE_MKFS 1 +#define FF_USE_FASTSEEK 0 +#define FF_USE_EXPAND 0 +#define FF_USE_CHMOD 0 +#define FF_USE_LABEL 0 +#define FF_USE_FORWARD 0 +#define FF_USE_LFN 3 +#define FF_MAX_LFN 255 +#define FF_LFN_UNICODE 0 +#define FF_LFN_BUF 255 +#define FF_SFN_BUF 12 +#define FF_FS_RPATH 0 +#define FF_VOLUMES 10 +#define FF_STR_VOLUME_ID 0 +#define FF_MULTI_PARTITION 1 +#define FF_MIN_SS 512 +#define FF_MAX_SS 4096 +#define FF_LBA64 0 +#define FF_USE_TRIM 0 +#define FF_FS_TINY 0 +#define FF_FS_EXFAT 0 +#define FF_FS_NORTC 1 +#define FF_NORTC_MON 1 +#define FF_NORTC_MDAY 1 +#define FF_NORTC_YEAR 2022 +#define FF_FS_NOFSInfo 0 +#define FF_FS_LOCK 0 +#define FF_FS_REENTRANT 0 +#define FF_FS_TIMEOUT 1000 +#define FF_SYNC_t HANDLE +#define FF_CODE_PAGE 437 +#endif diff --git a/kernel/fatfs/ffunicode.c b/kernel/fatfs/ffunicode.c new file mode 100644 index 0000000..a69b24c --- /dev/null +++ b/kernel/fatfs/ffunicode.c @@ -0,0 +1,15593 @@ +/*------------------------------------------------------------------------*/ +/* Unicode handling functions for FatFs R0.13+ */ +/*------------------------------------------------------------------------*/ +/* This module will occupy a huge memory in the .const section when the / +/ FatFs is configured for LFN with DBCS. If the system has any Unicode / +/ utilitiy for the code conversion, this module should be modified to use / +/ that function to avoid silly memory consumption. / +/-------------------------------------------------------------------------*/ +/* +/ Copyright (C) 2014, ChaN, all right reserved. +/ +/ FatFs module is an open source software. Redistribution and use of FatFs in +/ source and binary forms, with or without modification, are permitted provided +/ that the following condition is met: +/ +/ 1. Redistributions of source code must retain the above copyright notice, +/ this condition and the following disclaimer. +/ +/ This software is provided by the copyright holder and contributors "AS IS" +/ and any warranties related to this software are DISCLAIMED. +/ The copyright owner or contributors be NOT LIABLE for any damages caused +/ by use of this software. +*/ + + +#include "ff.h" + +#if FF_USE_LFN /* This module will be blanked if non-LFN configuration */ + +#define MERGE2(a, b) a ## b +#define CVTBL(tbl, cp) MERGE2(tbl, cp) + + +/*------------------------------------------------------------------------*/ +/* Code Conversion Tables */ +/*------------------------------------------------------------------------*/ + +#if FF_CODE_PAGE == 932 || FF_CODE_PAGE == 0 /* Japanese */ +static const WCHAR uni2oem932[] = { /* Unicode --> Shift_JIS pairs */ + 0x00A7, 0x8198, 0x00A8, 0x814E, 0x00B0, 0x818B, 0x00B1, 0x817D, 0x00B4, 0x814C, 0x00B6, 0x81F7, 0x00D7, 0x817E, 0x00F7, 0x8180, + 0x0391, 0x839F, 0x0392, 0x83A0, 0x0393, 0x83A1, 0x0394, 0x83A2, 0x0395, 0x83A3, 0x0396, 0x83A4, 0x0397, 0x83A5, 0x0398, 0x83A6, + 0x0399, 0x83A7, 0x039A, 0x83A8, 0x039B, 0x83A9, 0x039C, 0x83AA, 0x039D, 0x83AB, 0x039E, 0x83AC, 0x039F, 0x83AD, 0x03A0, 0x83AE, + 0x03A1, 0x83AF, 0x03A3, 0x83B0, 0x03A4, 0x83B1, 0x03A5, 0x83B2, 0x03A6, 0x83B3, 0x03A7, 0x83B4, 0x03A8, 0x83B5, 0x03A9, 0x83B6, + 0x03B1, 0x83BF, 0x03B2, 0x83C0, 0x03B3, 0x83C1, 0x03B4, 0x83C2, 0x03B5, 0x83C3, 0x03B6, 0x83C4, 0x03B7, 0x83C5, 0x03B8, 0x83C6, + 0x03B9, 0x83C7, 0x03BA, 0x83C8, 0x03BB, 0x83C9, 0x03BC, 0x83CA, 0x03BD, 0x83CB, 0x03BE, 0x83CC, 0x03BF, 0x83CD, 0x03C0, 0x83CE, + 0x03C1, 0x83CF, 0x03C3, 0x83D0, 0x03C4, 0x83D1, 0x03C5, 0x83D2, 0x03C6, 0x83D3, 0x03C7, 0x83D4, 0x03C8, 0x83D5, 0x03C9, 0x83D6, + 0x0401, 0x8446, 0x0410, 0x8440, 0x0411, 0x8441, 0x0412, 0x8442, 0x0413, 0x8443, 0x0414, 0x8444, 0x0415, 0x8445, 0x0416, 0x8447, + 0x0417, 0x8448, 0x0418, 0x8449, 0x0419, 0x844A, 0x041A, 0x844B, 0x041B, 0x844C, 0x041C, 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0xE9B6, 0x9B96, 0xE9B9, 0x9B97, 0xE9BA, + 0x9B9F, 0xE9BB, 0x9BA0, 0xE9BC, 0x9BA8, 0xE9BD, 0x9BAA, 0x968E, 0x9BAB, 0x8E4C, 0x9BAD, 0x8DF8, 0x9BAE, 0x914E, 0x9BB1, 0xFC44, + 0x9BB4, 0xE9BE, 0x9BB9, 0xE9C1, 0x9BBB, 0xFC45, 0x9BC0, 0xE9BF, 0x9BC6, 0xE9C2, 0x9BC9, 0x8CEF, 0x9BCA, 0xE9C0, 0x9BCF, 0xE9C3, + 0x9BD1, 0xE9C4, 0x9BD2, 0xE9C5, 0x9BD4, 0xE9C9, 0x9BD6, 0x8E49, 0x9BDB, 0x91E2, 0x9BE1, 0xE9CA, 0x9BE2, 0xE9C7, 0x9BE3, 0xE9C6, + 0x9BE4, 0xE9C8, 0x9BE8, 0x8C7E, 0x9BF0, 0xE9CE, 0x9BF1, 0xE9CD, 0x9BF2, 0xE9CC, 0x9BF5, 0x88B1, 0x9C00, 0xFC46, 0x9C04, 0xE9D8, + 0x9C06, 0xE9D4, 0x9C08, 0xE9D5, 0x9C09, 0xE9D1, 0x9C0A, 0xE9D7, 0x9C0C, 0xE9D3, 0x9C0D, 0x8A82, 0x9C10, 0x986B, 0x9C12, 0xE9D6, + 0x9C13, 0xE9D2, 0x9C14, 0xE9D0, 0x9C15, 0xE9CF, 0x9C1B, 0xE9DA, 0x9C21, 0xE9DD, 0x9C24, 0xE9DC, 0x9C25, 0xE9DB, 0x9C2D, 0x9568, + 0x9C2E, 0xE9D9, 0x9C2F, 0x88F1, 0x9C30, 0xE9DE, 0x9C32, 0xE9E0, 0x9C39, 0x8A8F, 0x9C3A, 0xE9CB, 0x9C3B, 0x8956, 0x9C3E, 0xE9E2, + 0x9C46, 0xE9E1, 0x9C47, 0xE9DF, 0x9C48, 0x924C, 0x9C52, 0x9690, 0x9C57, 0x97D8, 0x9C5A, 0xE9E3, 0x9C60, 0xE9E4, 0x9C67, 0xE9E5, + 0x9C76, 0xE9E6, 0x9C78, 0xE9E7, 0x9CE5, 0x92B9, 0x9CE7, 0xE9E8, 0x9CE9, 0x94B5, 0x9CEB, 0xE9ED, 0x9CEC, 0xE9E9, 0x9CF0, 0xE9EA, + 0x9CF3, 0x9650, 0x9CF4, 0x96C2, 0x9CF6, 0x93CE, 0x9D03, 0xE9EE, 0x9D06, 0xE9EF, 0x9D07, 0x93BC, 0x9D08, 0xE9EC, 0x9D09, 0xE9EB, + 0x9D0E, 0x89A8, 0x9D12, 0xE9F7, 0x9D15, 0xE9F6, 0x9D1B, 0x8995, 0x9D1F, 0xE9F4, 0x9D23, 0xE9F3, 0x9D26, 0xE9F1, 0x9D28, 0x8A9B, + 0x9D2A, 0xE9F0, 0x9D2B, 0x8EB0, 0x9D2C, 0x89A7, 0x9D3B, 0x8D83, 0x9D3E, 0xE9FA, 0x9D3F, 0xE9F9, 0x9D41, 0xE9F8, 0x9D44, 0xE9F5, + 0x9D46, 0xE9FB, 0x9D48, 0xE9FC, 0x9D50, 0xEA44, 0x9D51, 0xEA43, 0x9D59, 0xEA45, 0x9D5C, 0x894C, 0x9D5D, 0xEA40, 0x9D5E, 0xEA41, + 0x9D60, 0x8D94, 0x9D61, 0x96B7, 0x9D64, 0xEA42, 0x9D6B, 0xFC48, 0x9D6C, 0x9651, 0x9D6F, 0xEA4A, 0x9D70, 0xFC47, 0x9D72, 0xEA46, + 0x9D7A, 0xEA4B, 0x9D87, 0xEA48, 0x9D89, 0xEA47, 0x9D8F, 0x8C7B, 0x9D9A, 0xEA4C, 0x9DA4, 0xEA4D, 0x9DA9, 0xEA4E, 0x9DAB, 0xEA49, + 0x9DAF, 0xE9F2, 0x9DB2, 0xEA4F, 0x9DB4, 0x92DF, 0x9DB8, 0xEA53, 0x9DBA, 0xEA54, 0x9DBB, 0xEA52, 0x9DC1, 0xEA51, 0x9DC2, 0xEA57, + 0x9DC4, 0xEA50, 0x9DC6, 0xEA55, 0x9DCF, 0xEA56, 0x9DD3, 0xEA59, 0x9DD9, 0xEA58, 0x9DE6, 0xEA5B, 0x9DED, 0xEA5C, 0x9DEF, 0xEA5D, + 0x9DF2, 0x9868, 0x9DF8, 0xEA5A, 0x9DF9, 0x91E9, 0x9DFA, 0x8DEB, 0x9DFD, 0xEA5E, 0x9E19, 0xFC4A, 0x9E1A, 0xEA5F, 0x9E1B, 0xEA60, + 0x9E1E, 0xEA61, 0x9E75, 0xEA62, 0x9E78, 0x8CB2, 0x9E79, 0xEA63, 0x9E7D, 0xEA64, 0x9E7F, 0x8EAD, 0x9E81, 0xEA65, 0x9E88, 0xEA66, + 0x9E8B, 0xEA67, 0x9E8C, 0xEA68, 0x9E91, 0xEA6B, 0x9E92, 0xEA69, 0x9E93, 0x985B, 0x9E95, 0xEA6A, 0x9E97, 0x97ED, 0x9E9D, 0xEA6C, + 0x9E9F, 0x97D9, 0x9EA5, 0xEA6D, 0x9EA6, 0x949E, 0x9EA9, 0xEA6E, 0x9EAA, 0xEA70, 0x9EAD, 0xEA71, 0x9EB8, 0xEA6F, 0x9EB9, 0x8D8D, + 0x9EBA, 0x96CB, 0x9EBB, 0x9683, 0x9EBC, 0x9BF5, 0x9EBE, 0x9F80, 0x9EBF, 0x969B, 0x9EC4, 0x89A9, 0x9ECC, 0xEA73, 0x9ECD, 0x8B6F, + 0x9ECE, 0xEA74, 0x9ECF, 0xEA75, 0x9ED0, 0xEA76, 0x9ED1, 0xFC4B, 0x9ED2, 0x8D95, 0x9ED4, 0xEA77, 0x9ED8, 0xE0D2, 0x9ED9, 0x96D9, + 0x9EDB, 0x91E1, 0x9EDC, 0xEA78, 0x9EDD, 0xEA7A, 0x9EDE, 0xEA79, 0x9EE0, 0xEA7B, 0x9EE5, 0xEA7C, 0x9EE8, 0xEA7D, 0x9EEF, 0xEA7E, + 0x9EF4, 0xEA80, 0x9EF6, 0xEA81, 0x9EF7, 0xEA82, 0x9EF9, 0xEA83, 0x9EFB, 0xEA84, 0x9EFC, 0xEA85, 0x9EFD, 0xEA86, 0x9F07, 0xEA87, + 0x9F08, 0xEA88, 0x9F0E, 0x9343, 0x9F13, 0x8CDB, 0x9F15, 0xEA8A, 0x9F20, 0x916C, 0x9F21, 0xEA8B, 0x9F2C, 0xEA8C, 0x9F3B, 0x9540, + 0x9F3E, 0xEA8D, 0x9F4A, 0xEA8E, 0x9F4B, 0xE256, 0x9F4E, 0xE6D8, 0x9F4F, 0xE8EB, 0x9F52, 0xEA8F, 0x9F54, 0xEA90, 0x9F5F, 0xEA92, + 0x9F60, 0xEA93, 0x9F61, 0xEA94, 0x9F62, 0x97EE, 0x9F63, 0xEA91, 0x9F66, 0xEA95, 0x9F67, 0xEA96, 0x9F6A, 0xEA98, 0x9F6C, 0xEA97, + 0x9F72, 0xEA9A, 0x9F76, 0xEA9B, 0x9F77, 0xEA99, 0x9F8D, 0x97B4, 0x9F95, 0xEA9C, 0x9F9C, 0xEA9D, 0x9F9D, 0xE273, 0x9FA0, 0xEA9E, + 0xF929, 0xFAE0, 0xF9DC, 0xFBE9, 0xFA0E, 0xFA90, 0xFA0F, 0xFA9B, 0xFA10, 0xFA9C, 0xFA11, 0xFAB1, 0xFA12, 0xFAD8, 0xFA13, 0xFAE8, + 0xFA14, 0xFAEA, 0xFA15, 0xFB58, 0xFA16, 0xFB5E, 0xFA17, 0xFB75, 0xFA18, 0xFB7D, 0xFA19, 0xFB7E, 0xFA1A, 0xFB80, 0xFA1B, 0xFB82, + 0xFA1C, 0xFB86, 0xFA1D, 0xFB89, 0xFA1E, 0xFB92, 0xFA1F, 0xFB9D, 0xFA20, 0xFB9F, 0xFA21, 0xFBA0, 0xFA22, 0xFBA9, 0xFA23, 0xFBB1, + 0xFA24, 0xFBB3, 0xFA25, 0xFBB4, 0xFA26, 0xFBB7, 0xFA27, 0xFBD3, 0xFA28, 0xFBDA, 0xFA29, 0xFBEA, 0xFA2A, 0xFBF6, 0xFA2B, 0xFBF7, + 0xFA2C, 0xFBF9, 0xFA2D, 0xFC49, 0xFF01, 0x8149, 0xFF02, 0xFA57, 0xFF03, 0x8194, 0xFF04, 0x8190, 0xFF05, 0x8193, 0xFF06, 0x8195, + 0xFF07, 0xFA56, 0xFF08, 0x8169, 0xFF09, 0x816A, 0xFF0A, 0x8196, 0xFF0B, 0x817B, 0xFF0C, 0x8143, 0xFF0D, 0x817C, 0xFF0E, 0x8144, + 0xFF0F, 0x815E, 0xFF10, 0x824F, 0xFF11, 0x8250, 0xFF12, 0x8251, 0xFF13, 0x8252, 0xFF14, 0x8253, 0xFF15, 0x8254, 0xFF16, 0x8255, + 0xFF17, 0x8256, 0xFF18, 0x8257, 0xFF19, 0x8258, 0xFF1A, 0x8146, 0xFF1B, 0x8147, 0xFF1C, 0x8183, 0xFF1D, 0x8181, 0xFF1E, 0x8184, + 0xFF1F, 0x8148, 0xFF20, 0x8197, 0xFF21, 0x8260, 0xFF22, 0x8261, 0xFF23, 0x8262, 0xFF24, 0x8263, 0xFF25, 0x8264, 0xFF26, 0x8265, + 0xFF27, 0x8266, 0xFF28, 0x8267, 0xFF29, 0x8268, 0xFF2A, 0x8269, 0xFF2B, 0x826A, 0xFF2C, 0x826B, 0xFF2D, 0x826C, 0xFF2E, 0x826D, + 0xFF2F, 0x826E, 0xFF30, 0x826F, 0xFF31, 0x8270, 0xFF32, 0x8271, 0xFF33, 0x8272, 0xFF34, 0x8273, 0xFF35, 0x8274, 0xFF36, 0x8275, + 0xFF37, 0x8276, 0xFF38, 0x8277, 0xFF39, 0x8278, 0xFF3A, 0x8279, 0xFF3B, 0x816D, 0xFF3C, 0x815F, 0xFF3D, 0x816E, 0xFF3E, 0x814F, + 0xFF3F, 0x8151, 0xFF40, 0x814D, 0xFF41, 0x8281, 0xFF42, 0x8282, 0xFF43, 0x8283, 0xFF44, 0x8284, 0xFF45, 0x8285, 0xFF46, 0x8286, + 0xFF47, 0x8287, 0xFF48, 0x8288, 0xFF49, 0x8289, 0xFF4A, 0x828A, 0xFF4B, 0x828B, 0xFF4C, 0x828C, 0xFF4D, 0x828D, 0xFF4E, 0x828E, + 0xFF4F, 0x828F, 0xFF50, 0x8290, 0xFF51, 0x8291, 0xFF52, 0x8292, 0xFF53, 0x8293, 0xFF54, 0x8294, 0xFF55, 0x8295, 0xFF56, 0x8296, + 0xFF57, 0x8297, 0xFF58, 0x8298, 0xFF59, 0x8299, 0xFF5A, 0x829A, 0xFF5B, 0x816F, 0xFF5C, 0x8162, 0xFF5D, 0x8170, 0xFF5E, 0x8160, + 0xFF61, 0x00A1, 0xFF62, 0x00A2, 0xFF63, 0x00A3, 0xFF64, 0x00A4, 0xFF65, 0x00A5, 0xFF66, 0x00A6, 0xFF67, 0x00A7, 0xFF68, 0x00A8, + 0xFF69, 0x00A9, 0xFF6A, 0x00AA, 0xFF6B, 0x00AB, 0xFF6C, 0x00AC, 0xFF6D, 0x00AD, 0xFF6E, 0x00AE, 0xFF6F, 0x00AF, 0xFF70, 0x00B0, + 0xFF71, 0x00B1, 0xFF72, 0x00B2, 0xFF73, 0x00B3, 0xFF74, 0x00B4, 0xFF75, 0x00B5, 0xFF76, 0x00B6, 0xFF77, 0x00B7, 0xFF78, 0x00B8, + 0xFF79, 0x00B9, 0xFF7A, 0x00BA, 0xFF7B, 0x00BB, 0xFF7C, 0x00BC, 0xFF7D, 0x00BD, 0xFF7E, 0x00BE, 0xFF7F, 0x00BF, 0xFF80, 0x00C0, + 0xFF81, 0x00C1, 0xFF82, 0x00C2, 0xFF83, 0x00C3, 0xFF84, 0x00C4, 0xFF85, 0x00C5, 0xFF86, 0x00C6, 0xFF87, 0x00C7, 0xFF88, 0x00C8, + 0xFF89, 0x00C9, 0xFF8A, 0x00CA, 0xFF8B, 0x00CB, 0xFF8C, 0x00CC, 0xFF8D, 0x00CD, 0xFF8E, 0x00CE, 0xFF8F, 0x00CF, 0xFF90, 0x00D0, + 0xFF91, 0x00D1, 0xFF92, 0x00D2, 0xFF93, 0x00D3, 0xFF94, 0x00D4, 0xFF95, 0x00D5, 0xFF96, 0x00D6, 0xFF97, 0x00D7, 0xFF98, 0x00D8, + 0xFF99, 0x00D9, 0xFF9A, 0x00DA, 0xFF9B, 0x00DB, 0xFF9C, 0x00DC, 0xFF9D, 0x00DD, 0xFF9E, 0x00DE, 0xFF9F, 0x00DF, 0xFFE0, 0x8191, + 0xFFE1, 0x8192, 0xFFE2, 0x81CA, 0xFFE3, 0x8150, 0xFFE4, 0xFA55, 0xFFE5, 0x818F, 0, 0 +}; + +static const WCHAR oem2uni932[] = { /* Shift_JIS --> Unicode pairs */ + 0x00A1, 0xFF61, 0x00A2, 0xFF62, 0x00A3, 0xFF63, 0x00A4, 0xFF64, 0x00A5, 0xFF65, 0x00A6, 0xFF66, 0x00A7, 0xFF67, 0x00A8, 0xFF68, + 0x00A9, 0xFF69, 0x00AA, 0xFF6A, 0x00AB, 0xFF6B, 0x00AC, 0xFF6C, 0x00AD, 0xFF6D, 0x00AE, 0xFF6E, 0x00AF, 0xFF6F, 0x00B0, 0xFF70, + 0x00B1, 0xFF71, 0x00B2, 0xFF72, 0x00B3, 0xFF73, 0x00B4, 0xFF74, 0x00B5, 0xFF75, 0x00B6, 0xFF76, 0x00B7, 0xFF77, 0x00B8, 0xFF78, + 0x00B9, 0xFF79, 0x00BA, 0xFF7A, 0x00BB, 0xFF7B, 0x00BC, 0xFF7C, 0x00BD, 0xFF7D, 0x00BE, 0xFF7E, 0x00BF, 0xFF7F, 0x00C0, 0xFF80, + 0x00C1, 0xFF81, 0x00C2, 0xFF82, 0x00C3, 0xFF83, 0x00C4, 0xFF84, 0x00C5, 0xFF85, 0x00C6, 0xFF86, 0x00C7, 0xFF87, 0x00C8, 0xFF88, + 0x00C9, 0xFF89, 0x00CA, 0xFF8A, 0x00CB, 0xFF8B, 0x00CC, 0xFF8C, 0x00CD, 0xFF8D, 0x00CE, 0xFF8E, 0x00CF, 0xFF8F, 0x00D0, 0xFF90, + 0x00D1, 0xFF91, 0x00D2, 0xFF92, 0x00D3, 0xFF93, 0x00D4, 0xFF94, 0x00D5, 0xFF95, 0x00D6, 0xFF96, 0x00D7, 0xFF97, 0x00D8, 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0x51BE, 0xFA83, 0x51EC, 0xFA84, 0x5215, 0xFA85, 0x529C, 0xFA86, 0x52A6, 0xFA87, 0x52C0, + 0xFA88, 0x52DB, 0xFA89, 0x5300, 0xFA8A, 0x5307, 0xFA8B, 0x5324, 0xFA8C, 0x5372, 0xFA8D, 0x5393, 0xFA8E, 0x53B2, 0xFA8F, 0x53DD, + 0xFA90, 0xFA0E, 0xFA91, 0x549C, 0xFA92, 0x548A, 0xFA93, 0x54A9, 0xFA94, 0x54FF, 0xFA95, 0x5586, 0xFA96, 0x5759, 0xFA97, 0x5765, + 0xFA98, 0x57AC, 0xFA99, 0x57C8, 0xFA9A, 0x57C7, 0xFA9B, 0xFA0F, 0xFA9C, 0xFA10, 0xFA9D, 0x589E, 0xFA9E, 0x58B2, 0xFA9F, 0x590B, + 0xFAA0, 0x5953, 0xFAA1, 0x595B, 0xFAA2, 0x595D, 0xFAA3, 0x5963, 0xFAA4, 0x59A4, 0xFAA5, 0x59BA, 0xFAA6, 0x5B56, 0xFAA7, 0x5BC0, + 0xFAA8, 0x752F, 0xFAA9, 0x5BD8, 0xFAAA, 0x5BEC, 0xFAAB, 0x5C1E, 0xFAAC, 0x5CA6, 0xFAAD, 0x5CBA, 0xFAAE, 0x5CF5, 0xFAAF, 0x5D27, + 0xFAB0, 0x5D53, 0xFAB1, 0xFA11, 0xFAB2, 0x5D42, 0xFAB3, 0x5D6D, 0xFAB4, 0x5DB8, 0xFAB5, 0x5DB9, 0xFAB6, 0x5DD0, 0xFAB7, 0x5F21, + 0xFAB8, 0x5F34, 0xFAB9, 0x5F67, 0xFABA, 0x5FB7, 0xFABB, 0x5FDE, 0xFABC, 0x605D, 0xFABD, 0x6085, 0xFABE, 0x608A, 0xFABF, 0x60DE, + 0xFAC0, 0x60D5, 0xFAC1, 0x6120, 0xFAC2, 0x60F2, 0xFAC3, 0x6111, 0xFAC4, 0x6137, 0xFAC5, 0x6130, 0xFAC6, 0x6198, 0xFAC7, 0x6213, + 0xFAC8, 0x62A6, 0xFAC9, 0x63F5, 0xFACA, 0x6460, 0xFACB, 0x649D, 0xFACC, 0x64CE, 0xFACD, 0x654E, 0xFACE, 0x6600, 0xFACF, 0x6615, + 0xFAD0, 0x663B, 0xFAD1, 0x6609, 0xFAD2, 0x662E, 0xFAD3, 0x661E, 0xFAD4, 0x6624, 0xFAD5, 0x6665, 0xFAD6, 0x6657, 0xFAD7, 0x6659, + 0xFAD8, 0xFA12, 0xFAD9, 0x6673, 0xFADA, 0x6699, 0xFADB, 0x66A0, 0xFADC, 0x66B2, 0xFADD, 0x66BF, 0xFADE, 0x66FA, 0xFADF, 0x670E, + 0xFAE0, 0xF929, 0xFAE1, 0x6766, 0xFAE2, 0x67BB, 0xFAE3, 0x6852, 0xFAE4, 0x67C0, 0xFAE5, 0x6801, 0xFAE6, 0x6844, 0xFAE7, 0x68CF, + 0xFAE8, 0xFA13, 0xFAE9, 0x6968, 0xFAEA, 0xFA14, 0xFAEB, 0x6998, 0xFAEC, 0x69E2, 0xFAED, 0x6A30, 0xFAEE, 0x6A6B, 0xFAEF, 0x6A46, + 0xFAF0, 0x6A73, 0xFAF1, 0x6A7E, 0xFAF2, 0x6AE2, 0xFAF3, 0x6AE4, 0xFAF4, 0x6BD6, 0xFAF5, 0x6C3F, 0xFAF6, 0x6C5C, 0xFAF7, 0x6C86, + 0xFAF8, 0x6C6F, 0xFAF9, 0x6CDA, 0xFAFA, 0x6D04, 0xFAFB, 0x6D87, 0xFAFC, 0x6D6F, 0xFB40, 0x6D96, 0xFB41, 0x6DAC, 0xFB42, 0x6DCF, + 0xFB43, 0x6DF8, 0xFB44, 0x6DF2, 0xFB45, 0x6DFC, 0xFB46, 0x6E39, 0xFB47, 0x6E5C, 0xFB48, 0x6E27, 0xFB49, 0x6E3C, 0xFB4A, 0x6EBF, + 0xFB4B, 0x6F88, 0xFB4C, 0x6FB5, 0xFB4D, 0x6FF5, 0xFB4E, 0x7005, 0xFB4F, 0x7007, 0xFB50, 0x7028, 0xFB51, 0x7085, 0xFB52, 0x70AB, + 0xFB53, 0x710F, 0xFB54, 0x7104, 0xFB55, 0x715C, 0xFB56, 0x7146, 0xFB57, 0x7147, 0xFB58, 0xFA15, 0xFB59, 0x71C1, 0xFB5A, 0x71FE, + 0xFB5B, 0x72B1, 0xFB5C, 0x72BE, 0xFB5D, 0x7324, 0xFB5E, 0xFA16, 0xFB5F, 0x7377, 0xFB60, 0x73BD, 0xFB61, 0x73C9, 0xFB62, 0x73D6, + 0xFB63, 0x73E3, 0xFB64, 0x73D2, 0xFB65, 0x7407, 0xFB66, 0x73F5, 0xFB67, 0x7426, 0xFB68, 0x742A, 0xFB69, 0x7429, 0xFB6A, 0x742E, + 0xFB6B, 0x7462, 0xFB6C, 0x7489, 0xFB6D, 0x749F, 0xFB6E, 0x7501, 0xFB6F, 0x756F, 0xFB70, 0x7682, 0xFB71, 0x769C, 0xFB72, 0x769E, + 0xFB73, 0x769B, 0xFB74, 0x76A6, 0xFB75, 0xFA17, 0xFB76, 0x7746, 0xFB77, 0x52AF, 0xFB78, 0x7821, 0xFB79, 0x784E, 0xFB7A, 0x7864, + 0xFB7B, 0x787A, 0xFB7C, 0x7930, 0xFB7D, 0xFA18, 0xFB7E, 0xFA19, 0xFB80, 0xFA1A, 0xFB81, 0x7994, 0xFB82, 0xFA1B, 0xFB83, 0x799B, + 0xFB84, 0x7AD1, 0xFB85, 0x7AE7, 0xFB86, 0xFA1C, 0xFB87, 0x7AEB, 0xFB88, 0x7B9E, 0xFB89, 0xFA1D, 0xFB8A, 0x7D48, 0xFB8B, 0x7D5C, + 0xFB8C, 0x7DB7, 0xFB8D, 0x7DA0, 0xFB8E, 0x7DD6, 0xFB8F, 0x7E52, 0xFB90, 0x7F47, 0xFB91, 0x7FA1, 0xFB92, 0xFA1E, 0xFB93, 0x8301, + 0xFB94, 0x8362, 0xFB95, 0x837F, 0xFB96, 0x83C7, 0xFB97, 0x83F6, 0xFB98, 0x8448, 0xFB99, 0x84B4, 0xFB9A, 0x8553, 0xFB9B, 0x8559, + 0xFB9C, 0x856B, 0xFB9D, 0xFA1F, 0xFB9E, 0x85B0, 0xFB9F, 0xFA20, 0xFBA0, 0xFA21, 0xFBA1, 0x8807, 0xFBA2, 0x88F5, 0xFBA3, 0x8A12, + 0xFBA4, 0x8A37, 0xFBA5, 0x8A79, 0xFBA6, 0x8AA7, 0xFBA7, 0x8ABE, 0xFBA8, 0x8ADF, 0xFBA9, 0xFA22, 0xFBAA, 0x8AF6, 0xFBAB, 0x8B53, + 0xFBAC, 0x8B7F, 0xFBAD, 0x8CF0, 0xFBAE, 0x8CF4, 0xFBAF, 0x8D12, 0xFBB0, 0x8D76, 0xFBB1, 0xFA23, 0xFBB2, 0x8ECF, 0xFBB3, 0xFA24, + 0xFBB4, 0xFA25, 0xFBB5, 0x9067, 0xFBB6, 0x90DE, 0xFBB7, 0xFA26, 0xFBB8, 0x9115, 0xFBB9, 0x9127, 0xFBBA, 0x91DA, 0xFBBB, 0x91D7, + 0xFBBC, 0x91DE, 0xFBBD, 0x91ED, 0xFBBE, 0x91EE, 0xFBBF, 0x91E4, 0xFBC0, 0x91E5, 0xFBC1, 0x9206, 0xFBC2, 0x9210, 0xFBC3, 0x920A, + 0xFBC4, 0x923A, 0xFBC5, 0x9240, 0xFBC6, 0x923C, 0xFBC7, 0x924E, 0xFBC8, 0x9259, 0xFBC9, 0x9251, 0xFBCA, 0x9239, 0xFBCB, 0x9267, + 0xFBCC, 0x92A7, 0xFBCD, 0x9277, 0xFBCE, 0x9278, 0xFBCF, 0x92E7, 0xFBD0, 0x92D7, 0xFBD1, 0x92D9, 0xFBD2, 0x92D0, 0xFBD3, 0xFA27, + 0xFBD4, 0x92D5, 0xFBD5, 0x92E0, 0xFBD6, 0x92D3, 0xFBD7, 0x9325, 0xFBD8, 0x9321, 0xFBD9, 0x92FB, 0xFBDA, 0xFA28, 0xFBDB, 0x931E, + 0xFBDC, 0x92FF, 0xFBDD, 0x931D, 0xFBDE, 0x9302, 0xFBDF, 0x9370, 0xFBE0, 0x9357, 0xFBE1, 0x93A4, 0xFBE2, 0x93C6, 0xFBE3, 0x93DE, + 0xFBE4, 0x93F8, 0xFBE5, 0x9431, 0xFBE6, 0x9445, 0xFBE7, 0x9448, 0xFBE8, 0x9592, 0xFBE9, 0xF9DC, 0xFBEA, 0xFA29, 0xFBEB, 0x969D, + 0xFBEC, 0x96AF, 0xFBED, 0x9733, 0xFBEE, 0x973B, 0xFBEF, 0x9743, 0xFBF0, 0x974D, 0xFBF1, 0x974F, 0xFBF2, 0x9751, 0xFBF3, 0x9755, + 0xFBF4, 0x9857, 0xFBF5, 0x9865, 0xFBF6, 0xFA2A, 0xFBF7, 0xFA2B, 0xFBF8, 0x9927, 0xFBF9, 0xFA2C, 0xFBFA, 0x999E, 0xFBFB, 0x9A4E, + 0xFBFC, 0x9AD9, 0xFC40, 0x9ADC, 0xFC41, 0x9B75, 0xFC42, 0x9B72, 0xFC43, 0x9B8F, 0xFC44, 0x9BB1, 0xFC45, 0x9BBB, 0xFC46, 0x9C00, + 0xFC47, 0x9D70, 0xFC48, 0x9D6B, 0xFC49, 0xFA2D, 0xFC4A, 0x9E19, 0xFC4B, 0x9ED1, 0, 0 +}; +#endif + +#if FF_CODE_PAGE == 936 || FF_CODE_PAGE == 0 /* Simplified Chinese */ +static const WCHAR uni2oem936[] = { /* Unicode --> GBK pairs */ + 0x00A4, 0xA1E8, 0x00A7, 0xA1EC, 0x00A8, 0xA1A7, 0x00B0, 0xA1E3, 0x00B1, 0xA1C0, 0x00B7, 0xA1A4, 0x00D7, 0xA1C1, 0x00E0, 0xA8A4, + 0x00E1, 0xA8A2, 0x00E8, 0xA8A8, 0x00E9, 0xA8A6, 0x00EA, 0xA8BA, 0x00EC, 0xA8AC, 0x00ED, 0xA8AA, 0x00F2, 0xA8B0, 0x00F3, 0xA8AE, + 0x00F7, 0xA1C2, 0x00F9, 0xA8B4, 0x00FA, 0xA8B2, 0x00FC, 0xA8B9, 0x0101, 0xA8A1, 0x0113, 0xA8A5, 0x011B, 0xA8A7, 0x012B, 0xA8A9, + 0x0144, 0xA8BD, 0x0148, 0xA8BE, 0x014D, 0xA8AD, 0x016B, 0xA8B1, 0x01CE, 0xA8A3, 0x01D0, 0xA8AB, 0x01D2, 0xA8AF, 0x01D4, 0xA8B3, + 0x01D6, 0xA8B5, 0x01D8, 0xA8B6, 0x01DA, 0xA8B7, 0x01DC, 0xA8B8, 0x0251, 0xA8BB, 0x0261, 0xA8C0, 0x02C7, 0xA1A6, 0x02C9, 0xA1A5, + 0x02CA, 0xA840, 0x02CB, 0xA841, 0x02D9, 0xA842, 0x0391, 0xA6A1, 0x0392, 0xA6A2, 0x0393, 0xA6A3, 0x0394, 0xA6A4, 0x0395, 0xA6A5, + 0x0396, 0xA6A6, 0x0397, 0xA6A7, 0x0398, 0xA6A8, 0x0399, 0xA6A9, 0x039A, 0xA6AA, 0x039B, 0xA6AB, 0x039C, 0xA6AC, 0x039D, 0xA6AD, + 0x039E, 0xA6AE, 0x039F, 0xA6AF, 0x03A0, 0xA6B0, 0x03A1, 0xA6B1, 0x03A3, 0xA6B2, 0x03A4, 0xA6B3, 0x03A5, 0xA6B4, 0x03A6, 0xA6B5, + 0x03A7, 0xA6B6, 0x03A8, 0xA6B7, 0x03A9, 0xA6B8, 0x03B1, 0xA6C1, 0x03B2, 0xA6C2, 0x03B3, 0xA6C3, 0x03B4, 0xA6C4, 0x03B5, 0xA6C5, + 0x03B6, 0xA6C6, 0x03B7, 0xA6C7, 0x03B8, 0xA6C8, 0x03B9, 0xA6C9, 0x03BA, 0xA6CA, 0x03BB, 0xA6CB, 0x03BC, 0xA6CC, 0x03BD, 0xA6CD, + 0x03BE, 0xA6CE, 0x03BF, 0xA6CF, 0x03C0, 0xA6D0, 0x03C1, 0xA6D1, 0x03C3, 0xA6D2, 0x03C4, 0xA6D3, 0x03C5, 0xA6D4, 0x03C6, 0xA6D5, + 0x03C7, 0xA6D6, 0x03C8, 0xA6D7, 0x03C9, 0xA6D8, 0x0401, 0xA7A7, 0x0410, 0xA7A1, 0x0411, 0xA7A2, 0x0412, 0xA7A3, 0x0413, 0xA7A4, + 0x0414, 0xA7A5, 0x0415, 0xA7A6, 0x0416, 0xA7A8, 0x0417, 0xA7A9, 0x0418, 0xA7AA, 0x0419, 0xA7AB, 0x041A, 0xA7AC, 0x041B, 0xA7AD, + 0x041C, 0xA7AE, 0x041D, 0xA7AF, 0x041E, 0xA7B0, 0x041F, 0xA7B1, 0x0420, 0xA7B2, 0x0421, 0xA7B3, 0x0422, 0xA7B4, 0x0423, 0xA7B5, + 0x0424, 0xA7B6, 0x0425, 0xA7B7, 0x0426, 0xA7B8, 0x0427, 0xA7B9, 0x0428, 0xA7BA, 0x0429, 0xA7BB, 0x042A, 0xA7BC, 0x042B, 0xA7BD, + 0x042C, 0xA7BE, 0x042D, 0xA7BF, 0x042E, 0xA7C0, 0x042F, 0xA7C1, 0x0430, 0xA7D1, 0x0431, 0xA7D2, 0x0432, 0xA7D3, 0x0433, 0xA7D4, + 0x0434, 0xA7D5, 0x0435, 0xA7D6, 0x0436, 0xA7D8, 0x0437, 0xA7D9, 0x0438, 0xA7DA, 0x0439, 0xA7DB, 0x043A, 0xA7DC, 0x043B, 0xA7DD, + 0x043C, 0xA7DE, 0x043D, 0xA7DF, 0x043E, 0xA7E0, 0x043F, 0xA7E1, 0x0440, 0xA7E2, 0x0441, 0xA7E3, 0x0442, 0xA7E4, 0x0443, 0xA7E5, + 0x0444, 0xA7E6, 0x0445, 0xA7E7, 0x0446, 0xA7E8, 0x0447, 0xA7E9, 0x0448, 0xA7EA, 0x0449, 0xA7EB, 0x044A, 0xA7EC, 0x044B, 0xA7ED, + 0x044C, 0xA7EE, 0x044D, 0xA7EF, 0x044E, 0xA7F0, 0x044F, 0xA7F1, 0x0451, 0xA7D7, 0x2010, 0xA95C, 0x2013, 0xA843, 0x2014, 0xA1AA, + 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0x9E77, 0xFB77, 0x9E78, 0xFB78, 0x9E79, 0xFB79, 0x9E7A, 0xFB7A, + 0x9E7B, 0xFB7B, 0x9E7C, 0xFB7C, 0x9E7D, 0xFB7D, 0x9E7E, 0xF5BA, 0x9E7F, 0xC2B9, 0x9E80, 0xFB7E, 0x9E81, 0xFB80, 0x9E82, 0xF7E4, + 0x9E83, 0xFB81, 0x9E84, 0xFB82, 0x9E85, 0xFB83, 0x9E86, 0xFB84, 0x9E87, 0xF7E5, 0x9E88, 0xF7E6, 0x9E89, 0xFB85, 0x9E8A, 0xFB86, + 0x9E8B, 0xF7E7, 0x9E8C, 0xFB87, 0x9E8D, 0xFB88, 0x9E8E, 0xFB89, 0x9E8F, 0xFB8A, 0x9E90, 0xFB8B, 0x9E91, 0xFB8C, 0x9E92, 0xF7E8, + 0x9E93, 0xC2B4, 0x9E94, 0xFB8D, 0x9E95, 0xFB8E, 0x9E96, 0xFB8F, 0x9E97, 0xFB90, 0x9E98, 0xFB91, 0x9E99, 0xFB92, 0x9E9A, 0xFB93, + 0x9E9B, 0xFB94, 0x9E9C, 0xFB95, 0x9E9D, 0xF7EA, 0x9E9E, 0xFB96, 0x9E9F, 0xF7EB, 0x9EA0, 0xFB97, 0x9EA1, 0xFB98, 0x9EA2, 0xFB99, + 0x9EA3, 0xFB9A, 0x9EA4, 0xFB9B, 0x9EA5, 0xFB9C, 0x9EA6, 0xC2F3, 0x9EA7, 0xFB9D, 0x9EA8, 0xFB9E, 0x9EA9, 0xFB9F, 0x9EAA, 0xFBA0, + 0x9EAB, 0xFC40, 0x9EAC, 0xFC41, 0x9EAD, 0xFC42, 0x9EAE, 0xFC43, 0x9EAF, 0xFC44, 0x9EB0, 0xFC45, 0x9EB1, 0xFC46, 0x9EB2, 0xFC47, + 0x9EB3, 0xFC48, 0x9EB4, 0xF4F0, 0x9EB5, 0xFC49, 0x9EB6, 0xFC4A, 0x9EB7, 0xFC4B, 0x9EB8, 0xF4EF, 0x9EB9, 0xFC4C, 0x9EBA, 0xFC4D, + 0x9EBB, 0xC2E9, 0x9EBC, 0xFC4E, 0x9EBD, 0xF7E1, 0x9EBE, 0xF7E2, 0x9EBF, 0xFC4F, 0x9EC0, 0xFC50, 0x9EC1, 0xFC51, 0x9EC2, 0xFC52, + 0x9EC3, 0xFC53, 0x9EC4, 0xBBC6, 0x9EC5, 0xFC54, 0x9EC6, 0xFC55, 0x9EC7, 0xFC56, 0x9EC8, 0xFC57, 0x9EC9, 0xD9E4, 0x9ECA, 0xFC58, + 0x9ECB, 0xFC59, 0x9ECC, 0xFC5A, 0x9ECD, 0xCAF2, 0x9ECE, 0xC0E8, 0x9ECF, 0xF0A4, 0x9ED0, 0xFC5B, 0x9ED1, 0xBADA, 0x9ED2, 0xFC5C, + 0x9ED3, 0xFC5D, 0x9ED4, 0xC7AD, 0x9ED5, 0xFC5E, 0x9ED6, 0xFC5F, 0x9ED7, 0xFC60, 0x9ED8, 0xC4AC, 0x9ED9, 0xFC61, 0x9EDA, 0xFC62, + 0x9EDB, 0xF7EC, 0x9EDC, 0xF7ED, 0x9EDD, 0xF7EE, 0x9EDE, 0xFC63, 0x9EDF, 0xF7F0, 0x9EE0, 0xF7EF, 0x9EE1, 0xFC64, 0x9EE2, 0xF7F1, + 0x9EE3, 0xFC65, 0x9EE4, 0xFC66, 0x9EE5, 0xF7F4, 0x9EE6, 0xFC67, 0x9EE7, 0xF7F3, 0x9EE8, 0xFC68, 0x9EE9, 0xF7F2, 0x9EEA, 0xF7F5, + 0x9EEB, 0xFC69, 0x9EEC, 0xFC6A, 0x9EED, 0xFC6B, 0x9EEE, 0xFC6C, 0x9EEF, 0xF7F6, 0x9EF0, 0xFC6D, 0x9EF1, 0xFC6E, 0x9EF2, 0xFC6F, + 0x9EF3, 0xFC70, 0x9EF4, 0xFC71, 0x9EF5, 0xFC72, 0x9EF6, 0xFC73, 0x9EF7, 0xFC74, 0x9EF8, 0xFC75, 0x9EF9, 0xEDE9, 0x9EFA, 0xFC76, + 0x9EFB, 0xEDEA, 0x9EFC, 0xEDEB, 0x9EFD, 0xFC77, 0x9EFE, 0xF6BC, 0x9EFF, 0xFC78, 0x9F00, 0xFC79, 0x9F01, 0xFC7A, 0x9F02, 0xFC7B, + 0x9F03, 0xFC7C, 0x9F04, 0xFC7D, 0x9F05, 0xFC7E, 0x9F06, 0xFC80, 0x9F07, 0xFC81, 0x9F08, 0xFC82, 0x9F09, 0xFC83, 0x9F0A, 0xFC84, + 0x9F0B, 0xF6BD, 0x9F0C, 0xFC85, 0x9F0D, 0xF6BE, 0x9F0E, 0xB6A6, 0x9F0F, 0xFC86, 0x9F10, 0xD8BE, 0x9F11, 0xFC87, 0x9F12, 0xFC88, + 0x9F13, 0xB9C4, 0x9F14, 0xFC89, 0x9F15, 0xFC8A, 0x9F16, 0xFC8B, 0x9F17, 0xD8BB, 0x9F18, 0xFC8C, 0x9F19, 0xDCB1, 0x9F1A, 0xFC8D, + 0x9F1B, 0xFC8E, 0x9F1C, 0xFC8F, 0x9F1D, 0xFC90, 0x9F1E, 0xFC91, 0x9F1F, 0xFC92, 0x9F20, 0xCAF3, 0x9F21, 0xFC93, 0x9F22, 0xF7F7, + 0x9F23, 0xFC94, 0x9F24, 0xFC95, 0x9F25, 0xFC96, 0x9F26, 0xFC97, 0x9F27, 0xFC98, 0x9F28, 0xFC99, 0x9F29, 0xFC9A, 0x9F2A, 0xFC9B, + 0x9F2B, 0xFC9C, 0x9F2C, 0xF7F8, 0x9F2D, 0xFC9D, 0x9F2E, 0xFC9E, 0x9F2F, 0xF7F9, 0x9F30, 0xFC9F, 0x9F31, 0xFCA0, 0x9F32, 0xFD40, + 0x9F33, 0xFD41, 0x9F34, 0xFD42, 0x9F35, 0xFD43, 0x9F36, 0xFD44, 0x9F37, 0xF7FB, 0x9F38, 0xFD45, 0x9F39, 0xF7FA, 0x9F3A, 0xFD46, + 0x9F3B, 0xB1C7, 0x9F3C, 0xFD47, 0x9F3D, 0xF7FC, 0x9F3E, 0xF7FD, 0x9F3F, 0xFD48, 0x9F40, 0xFD49, 0x9F41, 0xFD4A, 0x9F42, 0xFD4B, + 0x9F43, 0xFD4C, 0x9F44, 0xF7FE, 0x9F45, 0xFD4D, 0x9F46, 0xFD4E, 0x9F47, 0xFD4F, 0x9F48, 0xFD50, 0x9F49, 0xFD51, 0x9F4A, 0xFD52, + 0x9F4B, 0xFD53, 0x9F4C, 0xFD54, 0x9F4D, 0xFD55, 0x9F4E, 0xFD56, 0x9F4F, 0xFD57, 0x9F50, 0xC6EB, 0x9F51, 0xECB4, 0x9F52, 0xFD58, + 0x9F53, 0xFD59, 0x9F54, 0xFD5A, 0x9F55, 0xFD5B, 0x9F56, 0xFD5C, 0x9F57, 0xFD5D, 0x9F58, 0xFD5E, 0x9F59, 0xFD5F, 0x9F5A, 0xFD60, + 0x9F5B, 0xFD61, 0x9F5C, 0xFD62, 0x9F5D, 0xFD63, 0x9F5E, 0xFD64, 0x9F5F, 0xFD65, 0x9F60, 0xFD66, 0x9F61, 0xFD67, 0x9F62, 0xFD68, + 0x9F63, 0xFD69, 0x9F64, 0xFD6A, 0x9F65, 0xFD6B, 0x9F66, 0xFD6C, 0x9F67, 0xFD6D, 0x9F68, 0xFD6E, 0x9F69, 0xFD6F, 0x9F6A, 0xFD70, + 0x9F6B, 0xFD71, 0x9F6C, 0xFD72, 0x9F6D, 0xFD73, 0x9F6E, 0xFD74, 0x9F6F, 0xFD75, 0x9F70, 0xFD76, 0x9F71, 0xFD77, 0x9F72, 0xFD78, + 0x9F73, 0xFD79, 0x9F74, 0xFD7A, 0x9F75, 0xFD7B, 0x9F76, 0xFD7C, 0x9F77, 0xFD7D, 0x9F78, 0xFD7E, 0x9F79, 0xFD80, 0x9F7A, 0xFD81, + 0x9F7B, 0xFD82, 0x9F7C, 0xFD83, 0x9F7D, 0xFD84, 0x9F7E, 0xFD85, 0x9F7F, 0xB3DD, 0x9F80, 0xF6B3, 0x9F81, 0xFD86, 0x9F82, 0xFD87, + 0x9F83, 0xF6B4, 0x9F84, 0xC1E4, 0x9F85, 0xF6B5, 0x9F86, 0xF6B6, 0x9F87, 0xF6B7, 0x9F88, 0xF6B8, 0x9F89, 0xF6B9, 0x9F8A, 0xF6BA, + 0x9F8B, 0xC8A3, 0x9F8C, 0xF6BB, 0x9F8D, 0xFD88, 0x9F8E, 0xFD89, 0x9F8F, 0xFD8A, 0x9F90, 0xFD8B, 0x9F91, 0xFD8C, 0x9F92, 0xFD8D, + 0x9F93, 0xFD8E, 0x9F94, 0xFD8F, 0x9F95, 0xFD90, 0x9F96, 0xFD91, 0x9F97, 0xFD92, 0x9F98, 0xFD93, 0x9F99, 0xC1FA, 0x9F9A, 0xB9A8, + 0x9F9B, 0xEDE8, 0x9F9C, 0xFD94, 0x9F9D, 0xFD95, 0x9F9E, 0xFD96, 0x9F9F, 0xB9EA, 0x9FA0, 0xD9DF, 0x9FA1, 0xFD97, 0x9FA2, 0xFD98, + 0x9FA3, 0xFD99, 0x9FA4, 0xFD9A, 0x9FA5, 0xFD9B, 0xF92C, 0xFD9C, 0xF979, 0xFD9D, 0xF995, 0xFD9E, 0xF9E7, 0xFD9F, 0xF9F1, 0xFDA0, + 0xFA0C, 0xFE40, 0xFA0D, 0xFE41, 0xFA0E, 0xFE42, 0xFA0F, 0xFE43, 0xFA11, 0xFE44, 0xFA13, 0xFE45, 0xFA14, 0xFE46, 0xFA18, 0xFE47, + 0xFA1F, 0xFE48, 0xFA20, 0xFE49, 0xFA21, 0xFE4A, 0xFA23, 0xFE4B, 0xFA24, 0xFE4C, 0xFA27, 0xFE4D, 0xFA28, 0xFE4E, 0xFA29, 0xFE4F, + 0xFE30, 0xA955, 0xFE31, 0xA6F2, 0xFE33, 0xA6F4, 0xFE34, 0xA6F5, 0xFE35, 0xA6E0, 0xFE36, 0xA6E1, 0xFE37, 0xA6F0, 0xFE38, 0xA6F1, + 0xFE39, 0xA6E2, 0xFE3A, 0xA6E3, 0xFE3B, 0xA6EE, 0xFE3C, 0xA6EF, 0xFE3D, 0xA6E6, 0xFE3E, 0xA6E7, 0xFE3F, 0xA6E4, 0xFE40, 0xA6E5, + 0xFE41, 0xA6E8, 0xFE42, 0xA6E9, 0xFE43, 0xA6EA, 0xFE44, 0xA6EB, 0xFE49, 0xA968, 0xFE4A, 0xA969, 0xFE4B, 0xA96A, 0xFE4C, 0xA96B, + 0xFE4D, 0xA96C, 0xFE4E, 0xA96D, 0xFE4F, 0xA96E, 0xFE50, 0xA96F, 0xFE51, 0xA970, 0xFE52, 0xA971, 0xFE54, 0xA972, 0xFE55, 0xA973, + 0xFE56, 0xA974, 0xFE57, 0xA975, 0xFE59, 0xA976, 0xFE5A, 0xA977, 0xFE5B, 0xA978, 0xFE5C, 0xA979, 0xFE5D, 0xA97A, 0xFE5E, 0xA97B, + 0xFE5F, 0xA97C, 0xFE60, 0xA97D, 0xFE61, 0xA97E, 0xFE62, 0xA980, 0xFE63, 0xA981, 0xFE64, 0xA982, 0xFE65, 0xA983, 0xFE66, 0xA984, + 0xFE68, 0xA985, 0xFE69, 0xA986, 0xFE6A, 0xA987, 0xFE6B, 0xA988, 0xFF01, 0xA3A1, 0xFF02, 0xA3A2, 0xFF03, 0xA3A3, 0xFF04, 0xA1E7, + 0xFF05, 0xA3A5, 0xFF06, 0xA3A6, 0xFF07, 0xA3A7, 0xFF08, 0xA3A8, 0xFF09, 0xA3A9, 0xFF0A, 0xA3AA, 0xFF0B, 0xA3AB, 0xFF0C, 0xA3AC, + 0xFF0D, 0xA3AD, 0xFF0E, 0xA3AE, 0xFF0F, 0xA3AF, 0xFF10, 0xA3B0, 0xFF11, 0xA3B1, 0xFF12, 0xA3B2, 0xFF13, 0xA3B3, 0xFF14, 0xA3B4, + 0xFF15, 0xA3B5, 0xFF16, 0xA3B6, 0xFF17, 0xA3B7, 0xFF18, 0xA3B8, 0xFF19, 0xA3B9, 0xFF1A, 0xA3BA, 0xFF1B, 0xA3BB, 0xFF1C, 0xA3BC, + 0xFF1D, 0xA3BD, 0xFF1E, 0xA3BE, 0xFF1F, 0xA3BF, 0xFF20, 0xA3C0, 0xFF21, 0xA3C1, 0xFF22, 0xA3C2, 0xFF23, 0xA3C3, 0xFF24, 0xA3C4, + 0xFF25, 0xA3C5, 0xFF26, 0xA3C6, 0xFF27, 0xA3C7, 0xFF28, 0xA3C8, 0xFF29, 0xA3C9, 0xFF2A, 0xA3CA, 0xFF2B, 0xA3CB, 0xFF2C, 0xA3CC, + 0xFF2D, 0xA3CD, 0xFF2E, 0xA3CE, 0xFF2F, 0xA3CF, 0xFF30, 0xA3D0, 0xFF31, 0xA3D1, 0xFF32, 0xA3D2, 0xFF33, 0xA3D3, 0xFF34, 0xA3D4, + 0xFF35, 0xA3D5, 0xFF36, 0xA3D6, 0xFF37, 0xA3D7, 0xFF38, 0xA3D8, 0xFF39, 0xA3D9, 0xFF3A, 0xA3DA, 0xFF3B, 0xA3DB, 0xFF3C, 0xA3DC, + 0xFF3D, 0xA3DD, 0xFF3E, 0xA3DE, 0xFF3F, 0xA3DF, 0xFF40, 0xA3E0, 0xFF41, 0xA3E1, 0xFF42, 0xA3E2, 0xFF43, 0xA3E3, 0xFF44, 0xA3E4, + 0xFF45, 0xA3E5, 0xFF46, 0xA3E6, 0xFF47, 0xA3E7, 0xFF48, 0xA3E8, 0xFF49, 0xA3E9, 0xFF4A, 0xA3EA, 0xFF4B, 0xA3EB, 0xFF4C, 0xA3EC, + 0xFF4D, 0xA3ED, 0xFF4E, 0xA3EE, 0xFF4F, 0xA3EF, 0xFF50, 0xA3F0, 0xFF51, 0xA3F1, 0xFF52, 0xA3F2, 0xFF53, 0xA3F3, 0xFF54, 0xA3F4, + 0xFF55, 0xA3F5, 0xFF56, 0xA3F6, 0xFF57, 0xA3F7, 0xFF58, 0xA3F8, 0xFF59, 0xA3F9, 0xFF5A, 0xA3FA, 0xFF5B, 0xA3FB, 0xFF5C, 0xA3FC, + 0xFF5D, 0xA3FD, 0xFF5E, 0xA1AB, 0xFFE0, 0xA1E9, 0xFFE1, 0xA1EA, 0xFFE2, 0xA956, 0xFFE3, 0xA3FE, 0xFFE4, 0xA957, 0xFFE5, 0xA3A4, + 0, 0 +}; + +static const WCHAR oem2uni936[] = { /* GBK --> Unicode pairs */ + 0x0080, 0x20AC, 0x8140, 0x4E02, 0x8141, 0x4E04, 0x8142, 0x4E05, 0x8143, 0x4E06, 0x8144, 0x4E0F, 0x8145, 0x4E12, 0x8146, 0x4E17, + 0x8147, 0x4E1F, 0x8148, 0x4E20, 0x8149, 0x4E21, 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0xFC8C, 0x9F18, 0xFC8D, 0x9F1A, 0xFC8E, 0x9F1B, 0xFC8F, 0x9F1C, 0xFC90, 0x9F1D, + 0xFC91, 0x9F1E, 0xFC92, 0x9F1F, 0xFC93, 0x9F21, 0xFC94, 0x9F23, 0xFC95, 0x9F24, 0xFC96, 0x9F25, 0xFC97, 0x9F26, 0xFC98, 0x9F27, + 0xFC99, 0x9F28, 0xFC9A, 0x9F29, 0xFC9B, 0x9F2A, 0xFC9C, 0x9F2B, 0xFC9D, 0x9F2D, 0xFC9E, 0x9F2E, 0xFC9F, 0x9F30, 0xFCA0, 0x9F31, + 0xFD40, 0x9F32, 0xFD41, 0x9F33, 0xFD42, 0x9F34, 0xFD43, 0x9F35, 0xFD44, 0x9F36, 0xFD45, 0x9F38, 0xFD46, 0x9F3A, 0xFD47, 0x9F3C, + 0xFD48, 0x9F3F, 0xFD49, 0x9F40, 0xFD4A, 0x9F41, 0xFD4B, 0x9F42, 0xFD4C, 0x9F43, 0xFD4D, 0x9F45, 0xFD4E, 0x9F46, 0xFD4F, 0x9F47, + 0xFD50, 0x9F48, 0xFD51, 0x9F49, 0xFD52, 0x9F4A, 0xFD53, 0x9F4B, 0xFD54, 0x9F4C, 0xFD55, 0x9F4D, 0xFD56, 0x9F4E, 0xFD57, 0x9F4F, + 0xFD58, 0x9F52, 0xFD59, 0x9F53, 0xFD5A, 0x9F54, 0xFD5B, 0x9F55, 0xFD5C, 0x9F56, 0xFD5D, 0x9F57, 0xFD5E, 0x9F58, 0xFD5F, 0x9F59, + 0xFD60, 0x9F5A, 0xFD61, 0x9F5B, 0xFD62, 0x9F5C, 0xFD63, 0x9F5D, 0xFD64, 0x9F5E, 0xFD65, 0x9F5F, 0xFD66, 0x9F60, 0xFD67, 0x9F61, + 0xFD68, 0x9F62, 0xFD69, 0x9F63, 0xFD6A, 0x9F64, 0xFD6B, 0x9F65, 0xFD6C, 0x9F66, 0xFD6D, 0x9F67, 0xFD6E, 0x9F68, 0xFD6F, 0x9F69, + 0xFD70, 0x9F6A, 0xFD71, 0x9F6B, 0xFD72, 0x9F6C, 0xFD73, 0x9F6D, 0xFD74, 0x9F6E, 0xFD75, 0x9F6F, 0xFD76, 0x9F70, 0xFD77, 0x9F71, + 0xFD78, 0x9F72, 0xFD79, 0x9F73, 0xFD7A, 0x9F74, 0xFD7B, 0x9F75, 0xFD7C, 0x9F76, 0xFD7D, 0x9F77, 0xFD7E, 0x9F78, 0xFD80, 0x9F79, + 0xFD81, 0x9F7A, 0xFD82, 0x9F7B, 0xFD83, 0x9F7C, 0xFD84, 0x9F7D, 0xFD85, 0x9F7E, 0xFD86, 0x9F81, 0xFD87, 0x9F82, 0xFD88, 0x9F8D, + 0xFD89, 0x9F8E, 0xFD8A, 0x9F8F, 0xFD8B, 0x9F90, 0xFD8C, 0x9F91, 0xFD8D, 0x9F92, 0xFD8E, 0x9F93, 0xFD8F, 0x9F94, 0xFD90, 0x9F95, + 0xFD91, 0x9F96, 0xFD92, 0x9F97, 0xFD93, 0x9F98, 0xFD94, 0x9F9C, 0xFD95, 0x9F9D, 0xFD96, 0x9F9E, 0xFD97, 0x9FA1, 0xFD98, 0x9FA2, + 0xFD99, 0x9FA3, 0xFD9A, 0x9FA4, 0xFD9B, 0x9FA5, 0xFD9C, 0xF92C, 0xFD9D, 0xF979, 0xFD9E, 0xF995, 0xFD9F, 0xF9E7, 0xFDA0, 0xF9F1, + 0xFE40, 0xFA0C, 0xFE41, 0xFA0D, 0xFE42, 0xFA0E, 0xFE43, 0xFA0F, 0xFE44, 0xFA11, 0xFE45, 0xFA13, 0xFE46, 0xFA14, 0xFE47, 0xFA18, + 0xFE48, 0xFA1F, 0xFE49, 0xFA20, 0xFE4A, 0xFA21, 0xFE4B, 0xFA23, 0xFE4C, 0xFA24, 0xFE4D, 0xFA27, 0xFE4E, 0xFA28, 0xFE4F, 0xFA29, + 0, 0 +}; +#endif + +#if FF_CODE_PAGE == 949 || FF_CODE_PAGE == 0 /* Korean */ +static const WCHAR uni2oem949[] = { /* Unicode --> Korean pairs */ + 0x00A1, 0xA2AE, 0x00A4, 0xA2B4, 0x00A7, 0xA1D7, 0x00A8, 0xA1A7, 0x00AA, 0xA8A3, 0x00AD, 0xA1A9, 0x00AE, 0xA2E7, 0x00B0, 0xA1C6, + 0x00B1, 0xA1BE, 0x00B2, 0xA9F7, 0x00B3, 0xA9F8, 0x00B4, 0xA2A5, 0x00B6, 0xA2D2, 0x00B7, 0xA1A4, 0x00B8, 0xA2AC, 0x00B9, 0xA9F6, + 0x00BA, 0xA8AC, 0x00BC, 0xA8F9, 0x00BD, 0xA8F6, 0x00BE, 0xA8FA, 0x00BF, 0xA2AF, 0x00C6, 0xA8A1, 0x00D0, 0xA8A2, 0x00D7, 0xA1BF, + 0x00D8, 0xA8AA, 0x00DE, 0xA8AD, 0x00DF, 0xA9AC, 0x00E6, 0xA9A1, 0x00F0, 0xA9A3, 0x00F7, 0xA1C0, 0x00F8, 0xA9AA, 0x00FE, 0xA9AD, + 0x0111, 0xA9A2, 0x0126, 0xA8A4, 0x0127, 0xA9A4, 0x0131, 0xA9A5, 0x0132, 0xA8A6, 0x0133, 0xA9A6, 0x0138, 0xA9A7, 0x013F, 0xA8A8, + 0x0140, 0xA9A8, 0x0141, 0xA8A9, 0x0142, 0xA9A9, 0x0149, 0xA9B0, 0x014A, 0xA8AF, 0x014B, 0xA9AF, 0x0152, 0xA8AB, 0x0153, 0xA9AB, + 0x0166, 0xA8AE, 0x0167, 0xA9AE, 0x02C7, 0xA2A7, 0x02D0, 0xA2B0, 0x02D8, 0xA2A8, 0x02D9, 0xA2AB, 0x02DA, 0xA2AA, 0x02DB, 0xA2AD, + 0x02DD, 0xA2A9, 0x0391, 0xA5C1, 0x0392, 0xA5C2, 0x0393, 0xA5C3, 0x0394, 0xA5C4, 0x0395, 0xA5C5, 0x0396, 0xA5C6, 0x0397, 0xA5C7, + 0x0398, 0xA5C8, 0x0399, 0xA5C9, 0x039A, 0xA5CA, 0x039B, 0xA5CB, 0x039C, 0xA5CC, 0x039D, 0xA5CD, 0x039E, 0xA5CE, 0x039F, 0xA5CF, + 0x03A0, 0xA5D0, 0x03A1, 0xA5D1, 0x03A3, 0xA5D2, 0x03A4, 0xA5D3, 0x03A5, 0xA5D4, 0x03A6, 0xA5D5, 0x03A7, 0xA5D6, 0x03A8, 0xA5D7, + 0x03A9, 0xA5D8, 0x03B1, 0xA5E1, 0x03B2, 0xA5E2, 0x03B3, 0xA5E3, 0x03B4, 0xA5E4, 0x03B5, 0xA5E5, 0x03B6, 0xA5E6, 0x03B7, 0xA5E7, + 0x03B8, 0xA5E8, 0x03B9, 0xA5E9, 0x03BA, 0xA5EA, 0x03BB, 0xA5EB, 0x03BC, 0xA5EC, 0x03BD, 0xA5ED, 0x03BE, 0xA5EE, 0x03BF, 0xA5EF, + 0x03C0, 0xA5F0, 0x03C1, 0xA5F1, 0x03C3, 0xA5F2, 0x03C4, 0xA5F3, 0x03C5, 0xA5F4, 0x03C6, 0xA5F5, 0x03C7, 0xA5F6, 0x03C8, 0xA5F7, + 0x03C9, 0xA5F8, 0x0401, 0xACA7, 0x0410, 0xACA1, 0x0411, 0xACA2, 0x0412, 0xACA3, 0x0413, 0xACA4, 0x0414, 0xACA5, 0x0415, 0xACA6, + 0x0416, 0xACA8, 0x0417, 0xACA9, 0x0418, 0xACAA, 0x0419, 0xACAB, 0x041A, 0xACAC, 0x041B, 0xACAD, 0x041C, 0xACAE, 0x041D, 0xACAF, + 0x041E, 0xACB0, 0x041F, 0xACB1, 0x0420, 0xACB2, 0x0421, 0xACB3, 0x0422, 0xACB4, 0x0423, 0xACB5, 0x0424, 0xACB6, 0x0425, 0xACB7, + 0x0426, 0xACB8, 0x0427, 0xACB9, 0x0428, 0xACBA, 0x0429, 0xACBB, 0x042A, 0xACBC, 0x042B, 0xACBD, 0x042C, 0xACBE, 0x042D, 0xACBF, + 0x042E, 0xACC0, 0x042F, 0xACC1, 0x0430, 0xACD1, 0x0431, 0xACD2, 0x0432, 0xACD3, 0x0433, 0xACD4, 0x0434, 0xACD5, 0x0435, 0xACD6, + 0x0436, 0xACD8, 0x0437, 0xACD9, 0x0438, 0xACDA, 0x0439, 0xACDB, 0x043A, 0xACDC, 0x043B, 0xACDD, 0x043C, 0xACDE, 0x043D, 0xACDF, + 0x043E, 0xACE0, 0x043F, 0xACE1, 0x0440, 0xACE2, 0x0441, 0xACE3, 0x0442, 0xACE4, 0x0443, 0xACE5, 0x0444, 0xACE6, 0x0445, 0xACE7, + 0x0446, 0xACE8, 0x0447, 0xACE9, 0x0448, 0xACEA, 0x0449, 0xACEB, 0x044A, 0xACEC, 0x044B, 0xACED, 0x044C, 0xACEE, 0x044D, 0xACEF, + 0x044E, 0xACF0, 0x044F, 0xACF1, 0x0451, 0xACD7, 0x2015, 0xA1AA, 0x2018, 0xA1AE, 0x2019, 0xA1AF, 0x201C, 0xA1B0, 0x201D, 0xA1B1, + 0x2020, 0xA2D3, 0x2021, 0xA2D4, 0x2025, 0xA1A5, 0x2026, 0xA1A6, 0x2030, 0xA2B6, 0x2032, 0xA1C7, 0x2033, 0xA1C8, 0x203B, 0xA1D8, + 0x2074, 0xA9F9, 0x207F, 0xA9FA, 0x2081, 0xA9FB, 0x2082, 0xA9FC, 0x2083, 0xA9FD, 0x2084, 0xA9FE, 0x20AC, 0xA2E6, 0x2103, 0xA1C9, + 0x2109, 0xA2B5, 0x2113, 0xA7A4, 0x2116, 0xA2E0, 0x2121, 0xA2E5, 0x2122, 0xA2E2, 0x2126, 0xA7D9, 0x212B, 0xA1CA, 0x2153, 0xA8F7, + 0x2154, 0xA8F8, 0x215B, 0xA8FB, 0x215C, 0xA8FC, 0x215D, 0xA8FD, 0x215E, 0xA8FE, 0x2160, 0xA5B0, 0x2161, 0xA5B1, 0x2162, 0xA5B2, + 0x2163, 0xA5B3, 0x2164, 0xA5B4, 0x2165, 0xA5B5, 0x2166, 0xA5B6, 0x2167, 0xA5B7, 0x2168, 0xA5B8, 0x2169, 0xA5B9, 0x2170, 0xA5A1, + 0x2171, 0xA5A2, 0x2172, 0xA5A3, 0x2173, 0xA5A4, 0x2174, 0xA5A5, 0x2175, 0xA5A6, 0x2176, 0xA5A7, 0x2177, 0xA5A8, 0x2178, 0xA5A9, + 0x2179, 0xA5AA, 0x2190, 0xA1E7, 0x2191, 0xA1E8, 0x2192, 0xA1E6, 0x2193, 0xA1E9, 0x2194, 0xA1EA, 0x2195, 0xA2D5, 0x2196, 0xA2D8, + 0x2197, 0xA2D6, 0x2198, 0xA2D9, 0x2199, 0xA2D7, 0x21D2, 0xA2A1, 0x21D4, 0xA2A2, 0x2200, 0xA2A3, 0x2202, 0xA1D3, 0x2203, 0xA2A4, + 0x2207, 0xA1D4, 0x2208, 0xA1F4, 0x220B, 0xA1F5, 0x220F, 0xA2B3, 0x2211, 0xA2B2, 0x221A, 0xA1EE, 0x221D, 0xA1F0, 0x221E, 0xA1C4, + 0x2220, 0xA1D0, 0x2225, 0xA1AB, 0x2227, 0xA1FC, 0x2228, 0xA1FD, 0x2229, 0xA1FB, 0x222A, 0xA1FA, 0x222B, 0xA1F2, 0x222C, 0xA1F3, + 0x222E, 0xA2B1, 0x2234, 0xA1C5, 0x2235, 0xA1F1, 0x223C, 0xA1AD, 0x223D, 0xA1EF, 0x2252, 0xA1D6, 0x2260, 0xA1C1, 0x2261, 0xA1D5, + 0x2264, 0xA1C2, 0x2265, 0xA1C3, 0x226A, 0xA1EC, 0x226B, 0xA1ED, 0x2282, 0xA1F8, 0x2283, 0xA1F9, 0x2286, 0xA1F6, 0x2287, 0xA1F7, + 0x2299, 0xA2C1, 0x22A5, 0xA1D1, 0x2312, 0xA1D2, 0x2460, 0xA8E7, 0x2461, 0xA8E8, 0x2462, 0xA8E9, 0x2463, 0xA8EA, 0x2464, 0xA8EB, + 0x2465, 0xA8EC, 0x2466, 0xA8ED, 0x2467, 0xA8EE, 0x2468, 0xA8EF, 0x2469, 0xA8F0, 0x246A, 0xA8F1, 0x246B, 0xA8F2, 0x246C, 0xA8F3, + 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0xD783, 0xC59A, + 0xD784, 0xC59B, 0xD785, 0xC59C, 0xD786, 0xC59D, 0xD787, 0xC59E, 0xD788, 0xC8F7, 0xD789, 0xC8F8, 0xD78A, 0xC59F, 0xD78B, 0xC5A0, + 0xD78C, 0xC8F9, 0xD78D, 0xC641, 0xD78E, 0xC642, 0xD78F, 0xC643, 0xD790, 0xC8FA, 0xD791, 0xC644, 0xD792, 0xC645, 0xD793, 0xC646, + 0xD794, 0xC647, 0xD795, 0xC648, 0xD796, 0xC649, 0xD797, 0xC64A, 0xD798, 0xC8FB, 0xD799, 0xC8FC, 0xD79A, 0xC64B, 0xD79B, 0xC8FD, + 0xD79C, 0xC64C, 0xD79D, 0xC8FE, 0xD79E, 0xC64D, 0xD79F, 0xC64E, 0xD7A0, 0xC64F, 0xD7A1, 0xC650, 0xD7A2, 0xC651, 0xD7A3, 0xC652, + 0xF900, 0xCBD0, 0xF901, 0xCBD6, 0xF902, 0xCBE7, 0xF903, 0xCDCF, 0xF904, 0xCDE8, 0xF905, 0xCEAD, 0xF906, 0xCFFB, 0xF907, 0xD0A2, + 0xF908, 0xD0B8, 0xF909, 0xD0D0, 0xF90A, 0xD0DD, 0xF90B, 0xD1D4, 0xF90C, 0xD1D5, 0xF90D, 0xD1D8, 0xF90E, 0xD1DB, 0xF90F, 0xD1DC, + 0xF910, 0xD1DD, 0xF911, 0xD1DE, 0xF912, 0xD1DF, 0xF913, 0xD1E0, 0xF914, 0xD1E2, 0xF915, 0xD1E3, 0xF916, 0xD1E4, 0xF917, 0xD1E5, + 0xF918, 0xD1E6, 0xF919, 0xD1E8, 0xF91A, 0xD1E9, 0xF91B, 0xD1EA, 0xF91C, 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0xF95A, 0xD4E6, 0xF95B, 0xD4FC, 0xF95C, 0xD5A5, 0xF95D, 0xD5AB, 0xF95E, 0xD5AE, 0xF95F, 0xD6B8, + 0xF960, 0xD6CD, 0xF961, 0xD7CB, 0xF962, 0xD7E4, 0xF963, 0xDBC5, 0xF964, 0xDBE4, 0xF965, 0xDCA5, 0xF966, 0xDDA5, 0xF967, 0xDDD5, + 0xF968, 0xDDF4, 0xF969, 0xDEFC, 0xF96A, 0xDEFE, 0xF96B, 0xDFB3, 0xF96C, 0xDFE1, 0xF96D, 0xDFE8, 0xF96E, 0xE0F1, 0xF96F, 0xE1AD, + 0xF970, 0xE1ED, 0xF971, 0xE3F5, 0xF972, 0xE4A1, 0xF973, 0xE4A9, 0xF974, 0xE5AE, 0xF975, 0xE5B1, 0xF976, 0xE5B2, 0xF977, 0xE5B9, + 0xF978, 0xE5BB, 0xF979, 0xE5BC, 0xF97A, 0xE5C4, 0xF97B, 0xE5CE, 0xF97C, 0xE5D0, 0xF97D, 0xE5D2, 0xF97E, 0xE5D6, 0xF97F, 0xE5FA, + 0xF980, 0xE5FB, 0xF981, 0xE5FC, 0xF982, 0xE5FE, 0xF983, 0xE6A1, 0xF984, 0xE6A4, 0xF985, 0xE6A7, 0xF986, 0xE6AD, 0xF987, 0xE6AF, + 0xF988, 0xE6B0, 0xF989, 0xE6B1, 0xF98A, 0xE6B3, 0xF98B, 0xE6B7, 0xF98C, 0xE6B8, 0xF98D, 0xE6BC, 0xF98E, 0xE6C4, 0xF98F, 0xE6C6, + 0xF990, 0xE6C7, 0xF991, 0xE6CA, 0xF992, 0xE6D2, 0xF993, 0xE6D6, 0xF994, 0xE6D9, 0xF995, 0xE6DC, 0xF996, 0xE6DF, 0xF997, 0xE6E1, + 0xF998, 0xE6E4, 0xF999, 0xE6E5, 0xF99A, 0xE6E6, 0xF99B, 0xE6E8, 0xF99C, 0xE6EA, 0xF99D, 0xE6EB, 0xF99E, 0xE6EC, 0xF99F, 0xE6EF, + 0xF9A0, 0xE6F1, 0xF9A1, 0xE6F2, 0xF9A2, 0xE6F5, 0xF9A3, 0xE6F6, 0xF9A4, 0xE6F7, 0xF9A5, 0xE6F9, 0xF9A6, 0xE7A1, 0xF9A7, 0xE7A6, + 0xF9A8, 0xE7A9, 0xF9A9, 0xE7AA, 0xF9AA, 0xE7AC, 0xF9AB, 0xE7AD, 0xF9AC, 0xE7B0, 0xF9AD, 0xE7BF, 0xF9AE, 0xE7C1, 0xF9AF, 0xE7C6, + 0xF9B0, 0xE7C7, 0xF9B1, 0xE7CB, 0xF9B2, 0xE7CD, 0xF9B3, 0xE7CF, 0xF9B4, 0xE7D0, 0xF9B5, 0xE7D3, 0xF9B6, 0xE7DF, 0xF9B7, 0xE7E4, + 0xF9B8, 0xE7E6, 0xF9B9, 0xE7F7, 0xF9BA, 0xE8E7, 0xF9BB, 0xE8E8, 0xF9BC, 0xE8F0, 0xF9BD, 0xE8F1, 0xF9BE, 0xE8F7, 0xF9BF, 0xE8F9, + 0xF9C0, 0xE8FB, 0xF9C1, 0xE8FE, 0xF9C2, 0xE9A7, 0xF9C3, 0xE9AC, 0xF9C4, 0xE9CC, 0xF9C5, 0xE9F7, 0xF9C6, 0xEAC1, 0xF9C7, 0xEAE5, + 0xF9C8, 0xEAF4, 0xF9C9, 0xEAF7, 0xF9CA, 0xEAFC, 0xF9CB, 0xEAFE, 0xF9CC, 0xEBA4, 0xF9CD, 0xEBA7, 0xF9CE, 0xEBA9, 0xF9CF, 0xEBAA, + 0xF9D0, 0xEBBA, 0xF9D1, 0xEBBB, 0xF9D2, 0xEBBD, 0xF9D3, 0xEBC1, 0xF9D4, 0xEBC2, 0xF9D5, 0xEBC6, 0xF9D6, 0xEBC7, 0xF9D7, 0xEBCC, + 0xF9D8, 0xEBCF, 0xF9D9, 0xEBD0, 0xF9DA, 0xEBD1, 0xF9DB, 0xEBD2, 0xF9DC, 0xEBD8, 0xF9DD, 0xECA6, 0xF9DE, 0xECA7, 0xF9DF, 0xECAA, + 0xF9E0, 0xECAF, 0xF9E1, 0xECB0, 0xF9E2, 0xECB1, 0xF9E3, 0xECB2, 0xF9E4, 0xECB5, 0xF9E5, 0xECB8, 0xF9E6, 0xECBA, 0xF9E7, 0xECC0, + 0xF9E8, 0xECC1, 0xF9E9, 0xECC5, 0xF9EA, 0xECC6, 0xF9EB, 0xECC9, 0xF9EC, 0xECCA, 0xF9ED, 0xECD5, 0xF9EE, 0xECDD, 0xF9EF, 0xECDE, + 0xF9F0, 0xECE1, 0xF9F1, 0xECE4, 0xF9F2, 0xECE7, 0xF9F3, 0xECE8, 0xF9F4, 0xECF7, 0xF9F5, 0xECF8, 0xF9F6, 0xECFA, 0xF9F7, 0xEDA1, + 0xF9F8, 0xEDA2, 0xF9F9, 0xEDA3, 0xF9FA, 0xEDEE, 0xF9FB, 0xEEDB, 0xF9FC, 0xF2BD, 0xF9FD, 0xF2FA, 0xF9FE, 0xF3B1, 0xF9FF, 0xF4A7, + 0xFA00, 0xF4EE, 0xFA01, 0xF6F4, 0xFA02, 0xF6F6, 0xFA03, 0xF7B8, 0xFA04, 0xF7C8, 0xFA05, 0xF7D3, 0xFA06, 0xF8DB, 0xFA07, 0xF8F0, + 0xFA08, 0xFAA1, 0xFA09, 0xFAA2, 0xFA0A, 0xFAE6, 0xFA0B, 0xFCA9, 0xFF01, 0xA3A1, 0xFF02, 0xA3A2, 0xFF03, 0xA3A3, 0xFF04, 0xA3A4, + 0xFF05, 0xA3A5, 0xFF06, 0xA3A6, 0xFF07, 0xA3A7, 0xFF08, 0xA3A8, 0xFF09, 0xA3A9, 0xFF0A, 0xA3AA, 0xFF0B, 0xA3AB, 0xFF0C, 0xA3AC, + 0xFF0D, 0xA3AD, 0xFF0E, 0xA3AE, 0xFF0F, 0xA3AF, 0xFF10, 0xA3B0, 0xFF11, 0xA3B1, 0xFF12, 0xA3B2, 0xFF13, 0xA3B3, 0xFF14, 0xA3B4, + 0xFF15, 0xA3B5, 0xFF16, 0xA3B6, 0xFF17, 0xA3B7, 0xFF18, 0xA3B8, 0xFF19, 0xA3B9, 0xFF1A, 0xA3BA, 0xFF1B, 0xA3BB, 0xFF1C, 0xA3BC, + 0xFF1D, 0xA3BD, 0xFF1E, 0xA3BE, 0xFF1F, 0xA3BF, 0xFF20, 0xA3C0, 0xFF21, 0xA3C1, 0xFF22, 0xA3C2, 0xFF23, 0xA3C3, 0xFF24, 0xA3C4, + 0xFF25, 0xA3C5, 0xFF26, 0xA3C6, 0xFF27, 0xA3C7, 0xFF28, 0xA3C8, 0xFF29, 0xA3C9, 0xFF2A, 0xA3CA, 0xFF2B, 0xA3CB, 0xFF2C, 0xA3CC, + 0xFF2D, 0xA3CD, 0xFF2E, 0xA3CE, 0xFF2F, 0xA3CF, 0xFF30, 0xA3D0, 0xFF31, 0xA3D1, 0xFF32, 0xA3D2, 0xFF33, 0xA3D3, 0xFF34, 0xA3D4, + 0xFF35, 0xA3D5, 0xFF36, 0xA3D6, 0xFF37, 0xA3D7, 0xFF38, 0xA3D8, 0xFF39, 0xA3D9, 0xFF3A, 0xA3DA, 0xFF3B, 0xA3DB, 0xFF3C, 0xA1AC, + 0xFF3D, 0xA3DD, 0xFF3E, 0xA3DE, 0xFF3F, 0xA3DF, 0xFF40, 0xA3E0, 0xFF41, 0xA3E1, 0xFF42, 0xA3E2, 0xFF43, 0xA3E3, 0xFF44, 0xA3E4, + 0xFF45, 0xA3E5, 0xFF46, 0xA3E6, 0xFF47, 0xA3E7, 0xFF48, 0xA3E8, 0xFF49, 0xA3E9, 0xFF4A, 0xA3EA, 0xFF4B, 0xA3EB, 0xFF4C, 0xA3EC, + 0xFF4D, 0xA3ED, 0xFF4E, 0xA3EE, 0xFF4F, 0xA3EF, 0xFF50, 0xA3F0, 0xFF51, 0xA3F1, 0xFF52, 0xA3F2, 0xFF53, 0xA3F3, 0xFF54, 0xA3F4, + 0xFF55, 0xA3F5, 0xFF56, 0xA3F6, 0xFF57, 0xA3F7, 0xFF58, 0xA3F8, 0xFF59, 0xA3F9, 0xFF5A, 0xA3FA, 0xFF5B, 0xA3FB, 0xFF5C, 0xA3FC, + 0xFF5D, 0xA3FD, 0xFF5E, 0xA2A6, 0xFFE0, 0xA1CB, 0xFFE1, 0xA1CC, 0xFFE2, 0xA1FE, 0xFFE3, 0xA3FE, 0xFFE5, 0xA1CD, 0xFFE6, 0xA3DC, + 0, 0 +}; + +static const WCHAR oem2uni949[] = { /* Korean --> Unicode pairs */ + 0x8141, 0xAC02, 0x8142, 0xAC03, 0x8143, 0xAC05, 0x8144, 0xAC06, 0x8145, 0xAC0B, 0x8146, 0xAC0C, 0x8147, 0xAC0D, 0x8148, 0xAC0E, + 0x8149, 0xAC0F, 0x814A, 0xAC18, 0x814B, 0xAC1E, 0x814C, 0xAC1F, 0x814D, 0xAC21, 0x814E, 0xAC22, 0x814F, 0xAC23, 0x8150, 0xAC25, + 0x8151, 0xAC26, 0x8152, 0xAC27, 0x8153, 0xAC28, 0x8154, 0xAC29, 0x8155, 0xAC2A, 0x8156, 0xAC2B, 0x8157, 0xAC2E, 0x8158, 0xAC32, + 0x8159, 0xAC33, 0x815A, 0xAC34, 0x8161, 0xAC35, 0x8162, 0xAC36, 0x8163, 0xAC37, 0x8164, 0xAC3A, 0x8165, 0xAC3B, 0x8166, 0xAC3D, + 0x8167, 0xAC3E, 0x8168, 0xAC3F, 0x8169, 0xAC41, 0x816A, 0xAC42, 0x816B, 0xAC43, 0x816C, 0xAC44, 0x816D, 0xAC45, 0x816E, 0xAC46, + 0x816F, 0xAC47, 0x8170, 0xAC48, 0x8171, 0xAC49, 0x8172, 0xAC4A, 0x8173, 0xAC4C, 0x8174, 0xAC4E, 0x8175, 0xAC4F, 0x8176, 0xAC50, + 0x8177, 0xAC51, 0x8178, 0xAC52, 0x8179, 0xAC53, 0x817A, 0xAC55, 0x8181, 0xAC56, 0x8182, 0xAC57, 0x8183, 0xAC59, 0x8184, 0xAC5A, + 0x8185, 0xAC5B, 0x8186, 0xAC5D, 0x8187, 0xAC5E, 0x8188, 0xAC5F, 0x8189, 0xAC60, 0x818A, 0xAC61, 0x818B, 0xAC62, 0x818C, 0xAC63, + 0x818D, 0xAC64, 0x818E, 0xAC65, 0x818F, 0xAC66, 0x8190, 0xAC67, 0x8191, 0xAC68, 0x8192, 0xAC69, 0x8193, 0xAC6A, 0x8194, 0xAC6B, + 0x8195, 0xAC6C, 0x8196, 0xAC6D, 0x8197, 0xAC6E, 0x8198, 0xAC6F, 0x8199, 0xAC72, 0x819A, 0xAC73, 0x819B, 0xAC75, 0x819C, 0xAC76, + 0x819D, 0xAC79, 0x819E, 0xAC7B, 0x819F, 0xAC7C, 0x81A0, 0xAC7D, 0x81A1, 0xAC7E, 0x81A2, 0xAC7F, 0x81A3, 0xAC82, 0x81A4, 0xAC87, + 0x81A5, 0xAC88, 0x81A6, 0xAC8D, 0x81A7, 0xAC8E, 0x81A8, 0xAC8F, 0x81A9, 0xAC91, 0x81AA, 0xAC92, 0x81AB, 0xAC93, 0x81AC, 0xAC95, + 0x81AD, 0xAC96, 0x81AE, 0xAC97, 0x81AF, 0xAC98, 0x81B0, 0xAC99, 0x81B1, 0xAC9A, 0x81B2, 0xAC9B, 0x81B3, 0xAC9E, 0x81B4, 0xACA2, + 0x81B5, 0xACA3, 0x81B6, 0xACA4, 0x81B7, 0xACA5, 0x81B8, 0xACA6, 0x81B9, 0xACA7, 0x81BA, 0xACAB, 0x81BB, 0xACAD, 0x81BC, 0xACAE, + 0x81BD, 0xACB1, 0x81BE, 0xACB2, 0x81BF, 0xACB3, 0x81C0, 0xACB4, 0x81C1, 0xACB5, 0x81C2, 0xACB6, 0x81C3, 0xACB7, 0x81C4, 0xACBA, + 0x81C5, 0xACBE, 0x81C6, 0xACBF, 0x81C7, 0xACC0, 0x81C8, 0xACC2, 0x81C9, 0xACC3, 0x81CA, 0xACC5, 0x81CB, 0xACC6, 0x81CC, 0xACC7, + 0x81CD, 0xACC9, 0x81CE, 0xACCA, 0x81CF, 0xACCB, 0x81D0, 0xACCD, 0x81D1, 0xACCE, 0x81D2, 0xACCF, 0x81D3, 0xACD0, 0x81D4, 0xACD1, + 0x81D5, 0xACD2, 0x81D6, 0xACD3, 0x81D7, 0xACD4, 0x81D8, 0xACD6, 0x81D9, 0xACD8, 0x81DA, 0xACD9, 0x81DB, 0xACDA, 0x81DC, 0xACDB, + 0x81DD, 0xACDC, 0x81DE, 0xACDD, 0x81DF, 0xACDE, 0x81E0, 0xACDF, 0x81E1, 0xACE2, 0x81E2, 0xACE3, 0x81E3, 0xACE5, 0x81E4, 0xACE6, + 0x81E5, 0xACE9, 0x81E6, 0xACEB, 0x81E7, 0xACED, 0x81E8, 0xACEE, 0x81E9, 0xACF2, 0x81EA, 0xACF4, 0x81EB, 0xACF7, 0x81EC, 0xACF8, + 0x81ED, 0xACF9, 0x81EE, 0xACFA, 0x81EF, 0xACFB, 0x81F0, 0xACFE, 0x81F1, 0xACFF, 0x81F2, 0xAD01, 0x81F3, 0xAD02, 0x81F4, 0xAD03, + 0x81F5, 0xAD05, 0x81F6, 0xAD07, 0x81F7, 0xAD08, 0x81F8, 0xAD09, 0x81F9, 0xAD0A, 0x81FA, 0xAD0B, 0x81FB, 0xAD0E, 0x81FC, 0xAD10, + 0x81FD, 0xAD12, 0x81FE, 0xAD13, 0x8241, 0xAD14, 0x8242, 0xAD15, 0x8243, 0xAD16, 0x8244, 0xAD17, 0x8245, 0xAD19, 0x8246, 0xAD1A, + 0x8247, 0xAD1B, 0x8248, 0xAD1D, 0x8249, 0xAD1E, 0x824A, 0xAD1F, 0x824B, 0xAD21, 0x824C, 0xAD22, 0x824D, 0xAD23, 0x824E, 0xAD24, + 0x824F, 0xAD25, 0x8250, 0xAD26, 0x8251, 0xAD27, 0x8252, 0xAD28, 0x8253, 0xAD2A, 0x8254, 0xAD2B, 0x8255, 0xAD2E, 0x8256, 0xAD2F, + 0x8257, 0xAD30, 0x8258, 0xAD31, 0x8259, 0xAD32, 0x825A, 0xAD33, 0x8261, 0xAD36, 0x8262, 0xAD37, 0x8263, 0xAD39, 0x8264, 0xAD3A, + 0x8265, 0xAD3B, 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0xFAB4, 0x99ED, 0xFAB5, 0x9AB8, 0xFAB6, 0x52BE, 0xFAB7, 0x6838, 0xFAB8, 0x5016, + 0xFAB9, 0x5E78, 0xFABA, 0x674F, 0xFABB, 0x8347, 0xFABC, 0x884C, 0xFABD, 0x4EAB, 0xFABE, 0x5411, 0xFABF, 0x56AE, 0xFAC0, 0x73E6, + 0xFAC1, 0x9115, 0xFAC2, 0x97FF, 0xFAC3, 0x9909, 0xFAC4, 0x9957, 0xFAC5, 0x9999, 0xFAC6, 0x5653, 0xFAC7, 0x589F, 0xFAC8, 0x865B, + 0xFAC9, 0x8A31, 0xFACA, 0x61B2, 0xFACB, 0x6AF6, 0xFACC, 0x737B, 0xFACD, 0x8ED2, 0xFACE, 0x6B47, 0xFACF, 0x96AA, 0xFAD0, 0x9A57, + 0xFAD1, 0x5955, 0xFAD2, 0x7200, 0xFAD3, 0x8D6B, 0xFAD4, 0x9769, 0xFAD5, 0x4FD4, 0xFAD6, 0x5CF4, 0xFAD7, 0x5F26, 0xFAD8, 0x61F8, + 0xFAD9, 0x665B, 0xFADA, 0x6CEB, 0xFADB, 0x70AB, 0xFADC, 0x7384, 0xFADD, 0x73B9, 0xFADE, 0x73FE, 0xFADF, 0x7729, 0xFAE0, 0x774D, + 0xFAE1, 0x7D43, 0xFAE2, 0x7D62, 0xFAE3, 0x7E23, 0xFAE4, 0x8237, 0xFAE5, 0x8852, 0xFAE6, 0xFA0A, 0xFAE7, 0x8CE2, 0xFAE8, 0x9249, + 0xFAE9, 0x986F, 0xFAEA, 0x5B51, 0xFAEB, 0x7A74, 0xFAEC, 0x8840, 0xFAED, 0x9801, 0xFAEE, 0x5ACC, 0xFAEF, 0x4FE0, 0xFAF0, 0x5354, + 0xFAF1, 0x593E, 0xFAF2, 0x5CFD, 0xFAF3, 0x633E, 0xFAF4, 0x6D79, 0xFAF5, 0x72F9, 0xFAF6, 0x8105, 0xFAF7, 0x8107, 0xFAF8, 0x83A2, + 0xFAF9, 0x92CF, 0xFAFA, 0x9830, 0xFAFB, 0x4EA8, 0xFAFC, 0x5144, 0xFAFD, 0x5211, 0xFAFE, 0x578B, 0xFBA1, 0x5F62, 0xFBA2, 0x6CC2, + 0xFBA3, 0x6ECE, 0xFBA4, 0x7005, 0xFBA5, 0x7050, 0xFBA6, 0x70AF, 0xFBA7, 0x7192, 0xFBA8, 0x73E9, 0xFBA9, 0x7469, 0xFBAA, 0x834A, + 0xFBAB, 0x87A2, 0xFBAC, 0x8861, 0xFBAD, 0x9008, 0xFBAE, 0x90A2, 0xFBAF, 0x93A3, 0xFBB0, 0x99A8, 0xFBB1, 0x516E, 0xFBB2, 0x5F57, + 0xFBB3, 0x60E0, 0xFBB4, 0x6167, 0xFBB5, 0x66B3, 0xFBB6, 0x8559, 0xFBB7, 0x8E4A, 0xFBB8, 0x91AF, 0xFBB9, 0x978B, 0xFBBA, 0x4E4E, + 0xFBBB, 0x4E92, 0xFBBC, 0x547C, 0xFBBD, 0x58D5, 0xFBBE, 0x58FA, 0xFBBF, 0x597D, 0xFBC0, 0x5CB5, 0xFBC1, 0x5F27, 0xFBC2, 0x6236, + 0xFBC3, 0x6248, 0xFBC4, 0x660A, 0xFBC5, 0x6667, 0xFBC6, 0x6BEB, 0xFBC7, 0x6D69, 0xFBC8, 0x6DCF, 0xFBC9, 0x6E56, 0xFBCA, 0x6EF8, + 0xFBCB, 0x6F94, 0xFBCC, 0x6FE0, 0xFBCD, 0x6FE9, 0xFBCE, 0x705D, 0xFBCF, 0x72D0, 0xFBD0, 0x7425, 0xFBD1, 0x745A, 0xFBD2, 0x74E0, + 0xFBD3, 0x7693, 0xFBD4, 0x795C, 0xFBD5, 0x7CCA, 0xFBD6, 0x7E1E, 0xFBD7, 0x80E1, 0xFBD8, 0x82A6, 0xFBD9, 0x846B, 0xFBDA, 0x84BF, + 0xFBDB, 0x864E, 0xFBDC, 0x865F, 0xFBDD, 0x8774, 0xFBDE, 0x8B77, 0xFBDF, 0x8C6A, 0xFBE0, 0x93AC, 0xFBE1, 0x9800, 0xFBE2, 0x9865, + 0xFBE3, 0x60D1, 0xFBE4, 0x6216, 0xFBE5, 0x9177, 0xFBE6, 0x5A5A, 0xFBE7, 0x660F, 0xFBE8, 0x6DF7, 0xFBE9, 0x6E3E, 0xFBEA, 0x743F, + 0xFBEB, 0x9B42, 0xFBEC, 0x5FFD, 0xFBED, 0x60DA, 0xFBEE, 0x7B0F, 0xFBEF, 0x54C4, 0xFBF0, 0x5F18, 0xFBF1, 0x6C5E, 0xFBF2, 0x6CD3, + 0xFBF3, 0x6D2A, 0xFBF4, 0x70D8, 0xFBF5, 0x7D05, 0xFBF6, 0x8679, 0xFBF7, 0x8A0C, 0xFBF8, 0x9D3B, 0xFBF9, 0x5316, 0xFBFA, 0x548C, + 0xFBFB, 0x5B05, 0xFBFC, 0x6A3A, 0xFBFD, 0x706B, 0xFBFE, 0x7575, 0xFCA1, 0x798D, 0xFCA2, 0x79BE, 0xFCA3, 0x82B1, 0xFCA4, 0x83EF, + 0xFCA5, 0x8A71, 0xFCA6, 0x8B41, 0xFCA7, 0x8CA8, 0xFCA8, 0x9774, 0xFCA9, 0xFA0B, 0xFCAA, 0x64F4, 0xFCAB, 0x652B, 0xFCAC, 0x78BA, + 0xFCAD, 0x78BB, 0xFCAE, 0x7A6B, 0xFCAF, 0x4E38, 0xFCB0, 0x559A, 0xFCB1, 0x5950, 0xFCB2, 0x5BA6, 0xFCB3, 0x5E7B, 0xFCB4, 0x60A3, + 0xFCB5, 0x63DB, 0xFCB6, 0x6B61, 0xFCB7, 0x6665, 0xFCB8, 0x6853, 0xFCB9, 0x6E19, 0xFCBA, 0x7165, 0xFCBB, 0x74B0, 0xFCBC, 0x7D08, + 0xFCBD, 0x9084, 0xFCBE, 0x9A69, 0xFCBF, 0x9C25, 0xFCC0, 0x6D3B, 0xFCC1, 0x6ED1, 0xFCC2, 0x733E, 0xFCC3, 0x8C41, 0xFCC4, 0x95CA, + 0xFCC5, 0x51F0, 0xFCC6, 0x5E4C, 0xFCC7, 0x5FA8, 0xFCC8, 0x604D, 0xFCC9, 0x60F6, 0xFCCA, 0x6130, 0xFCCB, 0x614C, 0xFCCC, 0x6643, + 0xFCCD, 0x6644, 0xFCCE, 0x69A5, 0xFCCF, 0x6CC1, 0xFCD0, 0x6E5F, 0xFCD1, 0x6EC9, 0xFCD2, 0x6F62, 0xFCD3, 0x714C, 0xFCD4, 0x749C, + 0xFCD5, 0x7687, 0xFCD6, 0x7BC1, 0xFCD7, 0x7C27, 0xFCD8, 0x8352, 0xFCD9, 0x8757, 0xFCDA, 0x9051, 0xFCDB, 0x968D, 0xFCDC, 0x9EC3, + 0xFCDD, 0x532F, 0xFCDE, 0x56DE, 0xFCDF, 0x5EFB, 0xFCE0, 0x5F8A, 0xFCE1, 0x6062, 0xFCE2, 0x6094, 0xFCE3, 0x61F7, 0xFCE4, 0x6666, + 0xFCE5, 0x6703, 0xFCE6, 0x6A9C, 0xFCE7, 0x6DEE, 0xFCE8, 0x6FAE, 0xFCE9, 0x7070, 0xFCEA, 0x736A, 0xFCEB, 0x7E6A, 0xFCEC, 0x81BE, + 0xFCED, 0x8334, 0xFCEE, 0x86D4, 0xFCEF, 0x8AA8, 0xFCF0, 0x8CC4, 0xFCF1, 0x5283, 0xFCF2, 0x7372, 0xFCF3, 0x5B96, 0xFCF4, 0x6A6B, + 0xFCF5, 0x9404, 0xFCF6, 0x54EE, 0xFCF7, 0x5686, 0xFCF8, 0x5B5D, 0xFCF9, 0x6548, 0xFCFA, 0x6585, 0xFCFB, 0x66C9, 0xFCFC, 0x689F, + 0xFCFD, 0x6D8D, 0xFCFE, 0x6DC6, 0xFDA1, 0x723B, 0xFDA2, 0x80B4, 0xFDA3, 0x9175, 0xFDA4, 0x9A4D, 0xFDA5, 0x4FAF, 0xFDA6, 0x5019, + 0xFDA7, 0x539A, 0xFDA8, 0x540E, 0xFDA9, 0x543C, 0xFDAA, 0x5589, 0xFDAB, 0x55C5, 0xFDAC, 0x5E3F, 0xFDAD, 0x5F8C, 0xFDAE, 0x673D, + 0xFDAF, 0x7166, 0xFDB0, 0x73DD, 0xFDB1, 0x9005, 0xFDB2, 0x52DB, 0xFDB3, 0x52F3, 0xFDB4, 0x5864, 0xFDB5, 0x58CE, 0xFDB6, 0x7104, + 0xFDB7, 0x718F, 0xFDB8, 0x71FB, 0xFDB9, 0x85B0, 0xFDBA, 0x8A13, 0xFDBB, 0x6688, 0xFDBC, 0x85A8, 0xFDBD, 0x55A7, 0xFDBE, 0x6684, + 0xFDBF, 0x714A, 0xFDC0, 0x8431, 0xFDC1, 0x5349, 0xFDC2, 0x5599, 0xFDC3, 0x6BC1, 0xFDC4, 0x5F59, 0xFDC5, 0x5FBD, 0xFDC6, 0x63EE, + 0xFDC7, 0x6689, 0xFDC8, 0x7147, 0xFDC9, 0x8AF1, 0xFDCA, 0x8F1D, 0xFDCB, 0x9EBE, 0xFDCC, 0x4F11, 0xFDCD, 0x643A, 0xFDCE, 0x70CB, + 0xFDCF, 0x7566, 0xFDD0, 0x8667, 0xFDD1, 0x6064, 0xFDD2, 0x8B4E, 0xFDD3, 0x9DF8, 0xFDD4, 0x5147, 0xFDD5, 0x51F6, 0xFDD6, 0x5308, + 0xFDD7, 0x6D36, 0xFDD8, 0x80F8, 0xFDD9, 0x9ED1, 0xFDDA, 0x6615, 0xFDDB, 0x6B23, 0xFDDC, 0x7098, 0xFDDD, 0x75D5, 0xFDDE, 0x5403, + 0xFDDF, 0x5C79, 0xFDE0, 0x7D07, 0xFDE1, 0x8A16, 0xFDE2, 0x6B20, 0xFDE3, 0x6B3D, 0xFDE4, 0x6B46, 0xFDE5, 0x5438, 0xFDE6, 0x6070, + 0xFDE7, 0x6D3D, 0xFDE8, 0x7FD5, 0xFDE9, 0x8208, 0xFDEA, 0x50D6, 0xFDEB, 0x51DE, 0xFDEC, 0x559C, 0xFDED, 0x566B, 0xFDEE, 0x56CD, + 0xFDEF, 0x59EC, 0xFDF0, 0x5B09, 0xFDF1, 0x5E0C, 0xFDF2, 0x6199, 0xFDF3, 0x6198, 0xFDF4, 0x6231, 0xFDF5, 0x665E, 0xFDF6, 0x66E6, + 0xFDF7, 0x7199, 0xFDF8, 0x71B9, 0xFDF9, 0x71BA, 0xFDFA, 0x72A7, 0xFDFB, 0x79A7, 0xFDFC, 0x7A00, 0xFDFD, 0x7FB2, 0xFDFE, 0x8A70, + 0, 0 +}; +#endif + +#if FF_CODE_PAGE == 950 || FF_CODE_PAGE == 0 /* Traditional Chinese */ +static const WCHAR uni2oem950[] = { /* Unicode --> Big5 pairs */ + 0x00A7, 0xA1B1, 0x00AF, 0xA1C2, 0x00B0, 0xA258, 0x00B1, 0xA1D3, 0x00B7, 0xA150, 0x00D7, 0xA1D1, 0x00F7, 0xA1D2, 0x02C7, 0xA3BE, + 0x02C9, 0xA3BC, 0x02CA, 0xA3BD, 0x02CB, 0xA3BF, 0x02CD, 0xA1C5, 0x02D9, 0xA3BB, 0x0391, 0xA344, 0x0392, 0xA345, 0x0393, 0xA346, + 0x0394, 0xA347, 0x0395, 0xA348, 0x0396, 0xA349, 0x0397, 0xA34A, 0x0398, 0xA34B, 0x0399, 0xA34C, 0x039A, 0xA34D, 0x039B, 0xA34E, + 0x039C, 0xA34F, 0x039D, 0xA350, 0x039E, 0xA351, 0x039F, 0xA352, 0x03A0, 0xA353, 0x03A1, 0xA354, 0x03A3, 0xA355, 0x03A4, 0xA356, + 0x03A5, 0xA357, 0x03A6, 0xA358, 0x03A7, 0xA359, 0x03A8, 0xA35A, 0x03A9, 0xA35B, 0x03B1, 0xA35C, 0x03B2, 0xA35D, 0x03B3, 0xA35E, + 0x03B4, 0xA35F, 0x03B5, 0xA360, 0x03B6, 0xA361, 0x03B7, 0xA362, 0x03B8, 0xA363, 0x03B9, 0xA364, 0x03BA, 0xA365, 0x03BB, 0xA366, + 0x03BC, 0xA367, 0x03BD, 0xA368, 0x03BE, 0xA369, 0x03BF, 0xA36A, 0x03C0, 0xA36B, 0x03C1, 0xA36C, 0x03C3, 0xA36D, 0x03C4, 0xA36E, + 0x03C5, 0xA36F, 0x03C6, 0xA370, 0x03C7, 0xA371, 0x03C8, 0xA372, 0x03C9, 0xA373, 0x2013, 0xA156, 0x2014, 0xA158, 0x2018, 0xA1A5, + 0x2019, 0xA1A6, 0x201C, 0xA1A7, 0x201D, 0xA1A8, 0x2025, 0xA14C, 0x2026, 0xA14B, 0x2027, 0xA145, 0x2032, 0xA1AC, 0x2035, 0xA1AB, + 0x203B, 0xA1B0, 0x20AC, 0xA3E1, 0x2103, 0xA24A, 0x2105, 0xA1C1, 0x2109, 0xA24B, 0x2160, 0xA2B9, 0x2161, 0xA2BA, 0x2162, 0xA2BB, + 0x2163, 0xA2BC, 0x2164, 0xA2BD, 0x2165, 0xA2BE, 0x2166, 0xA2BF, 0x2167, 0xA2C0, 0x2168, 0xA2C1, 0x2169, 0xA2C2, 0x2190, 0xA1F6, + 0x2191, 0xA1F4, 0x2192, 0xA1F7, 0x2193, 0xA1F5, 0x2196, 0xA1F8, 0x2197, 0xA1F9, 0x2198, 0xA1FB, 0x2199, 0xA1FA, 0x2215, 0xA241, + 0x221A, 0xA1D4, 0x221E, 0xA1DB, 0x221F, 0xA1E8, 0x2220, 0xA1E7, 0x2223, 0xA1FD, 0x2225, 0xA1FC, 0x2229, 0xA1E4, 0x222A, 0xA1E5, + 0x222B, 0xA1EC, 0x222E, 0xA1ED, 0x2234, 0xA1EF, 0x2235, 0xA1EE, 0x2252, 0xA1DC, 0x2260, 0xA1DA, 0x2261, 0xA1DD, 0x2266, 0xA1D8, + 0x2267, 0xA1D9, 0x2295, 0xA1F2, 0x2299, 0xA1F3, 0x22A5, 0xA1E6, 0x22BF, 0xA1E9, 0x2500, 0xA277, 0x2502, 0xA278, 0x250C, 0xA27A, + 0x2510, 0xA27B, 0x2514, 0xA27C, 0x2518, 0xA27D, 0x251C, 0xA275, 0x2524, 0xA274, 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0xC24C, 0x9EDC, 0xC24A, 0x9EDD, 0xC24B, 0x9EDE, 0xC249, 0x9EDF, 0xF1E0, 0x9EE0, 0xC35C, 0x9EE4, 0xF5B5, 0x9EE5, 0xF5B4, + 0x9EE6, 0xF5B7, 0x9EE7, 0xF5B6, 0x9EE8, 0xC4D2, 0x9EEB, 0xF6CB, 0x9EED, 0xF6CD, 0x9EEE, 0xF6CC, 0x9EEF, 0xC566, 0x9EF0, 0xF7C8, + 0x9EF2, 0xF876, 0x9EF3, 0xF877, 0x9EF4, 0xC5F0, 0x9EF5, 0xF964, 0x9EF6, 0xF97D, 0x9EF7, 0xC675, 0x9EF9, 0xDCB0, 0x9EFA, 0xECB6, + 0x9EFB, 0xEFB0, 0x9EFC, 0xF3F5, 0x9EFD, 0xE0EF, 0x9EFF, 0xEFB1, 0x9F00, 0xF1E2, 0x9F01, 0xF1E1, 0x9F06, 0xF878, 0x9F07, 0xC652, + 0x9F09, 0xF965, 0x9F0A, 0xF97E, 0x9F0E, 0xB9A9, 0x9F0F, 0xE8F2, 0x9F10, 0xE8F3, 0x9F12, 0xECB7, 0x9F13, 0xB9AA, 0x9F15, 0xC35D, + 0x9F16, 0xF1E3, 0x9F18, 0xF6CF, 0x9F19, 0xC567, 0x9F1A, 0xF6D0, 0x9F1B, 0xF6CE, 0x9F1C, 0xF879, 0x9F1E, 0xF8E9, 0x9F20, 0xB9AB, + 0x9F22, 0xEFB4, 0x9F23, 0xEFB3, 0x9F24, 0xEFB2, 0x9F25, 0xF1E4, 0x9F28, 0xF1E8, 0x9F29, 0xF1E7, 0x9F2A, 0xF1E6, 0x9F2B, 0xF1E5, + 0x9F2C, 0xC35E, 0x9F2D, 0xF3F6, 0x9F2E, 0xF5B9, 0x9F2F, 0xC4D3, 0x9F30, 0xF5B8, 0x9F31, 0xF6D1, 0x9F32, 0xF7CB, 0x9F33, 0xF7CA, + 0x9F34, 0xC5C4, 0x9F35, 0xF7C9, 0x9F36, 0xF87C, 0x9F37, 0xF87B, 0x9F38, 0xF87A, 0x9F3B, 0xBBF3, 0x9F3D, 0xECB8, 0x9F3E, 0xC24D, + 0x9F40, 0xF3F7, 0x9F41, 0xF3F8, 0x9F42, 0xF7CC, 0x9F43, 0xF87D, 0x9F46, 0xF8EA, 0x9F47, 0xF966, 0x9F48, 0xF9B9, 0x9F49, 0xF9D4, + 0x9F4A, 0xBBF4, 0x9F4B, 0xC24E, 0x9F4C, 0xF1E9, 0x9F4D, 0xF3F9, 0x9F4E, 0xF6D2, 0x9F4F, 0xF87E, 0x9F52, 0xBEA6, 0x9F54, 0xEFB5, + 0x9F55, 0xF1EA, 0x9F56, 0xF3FA, 0x9F57, 0xF3FB, 0x9F58, 0xF3FC, 0x9F59, 0xF5BE, 0x9F5B, 0xF5BA, 0x9F5C, 0xC568, 0x9F5D, 0xF5BD, + 0x9F5E, 0xF5BC, 0x9F5F, 0xC4D4, 0x9F60, 0xF5BB, 0x9F61, 0xC4D6, 0x9F63, 0xC4D5, 0x9F64, 0xF6D4, 0x9F65, 0xF6D3, 0x9F66, 0xC569, + 0x9F67, 0xC56A, 0x9F6A, 0xC5C6, 0x9F6B, 0xF7CD, 0x9F6C, 0xC5C5, 0x9F6E, 0xF8A3, 0x9F6F, 0xF8A4, 0x9F70, 0xF8A2, 0x9F71, 0xF8A1, + 0x9F72, 0xC654, 0x9F74, 0xF8EB, 0x9F75, 0xF8EC, 0x9F76, 0xF8ED, 0x9F77, 0xC653, 0x9F78, 0xF967, 0x9F79, 0xF96A, 0x9F7A, 0xF969, + 0x9F7B, 0xF968, 0x9F7E, 0xF9D3, 0x9F8D, 0xC073, 0x9F90, 0xC365, 0x9F91, 0xF5BF, 0x9F92, 0xF6D5, 0x9F94, 0xC5C7, 0x9F95, 0xF7CE, + 0x9F98, 0xF9D5, 0x9F9C, 0xC074, 0x9FA0, 0xEFB6, 0x9FA2, 0xF7CF, 0x9FA4, 0xF9A1, 0xFA0C, 0xC94A, 0xFA0D, 0xDDFC, 0xFE30, 0xA14A, + 0xFE31, 0xA157, 0xFE33, 0xA159, 0xFE34, 0xA15B, 0xFE35, 0xA15F, 0xFE36, 0xA160, 0xFE37, 0xA163, 0xFE38, 0xA164, 0xFE39, 0xA167, + 0xFE3A, 0xA168, 0xFE3B, 0xA16B, 0xFE3C, 0xA16C, 0xFE3D, 0xA16F, 0xFE3E, 0xA170, 0xFE3F, 0xA173, 0xFE40, 0xA174, 0xFE41, 0xA177, + 0xFE42, 0xA178, 0xFE43, 0xA17B, 0xFE44, 0xA17C, 0xFE49, 0xA1C6, 0xFE4A, 0xA1C7, 0xFE4B, 0xA1CA, 0xFE4C, 0xA1CB, 0xFE4D, 0xA1C8, + 0xFE4E, 0xA1C9, 0xFE4F, 0xA15C, 0xFE50, 0xA14D, 0xFE51, 0xA14E, 0xFE52, 0xA14F, 0xFE54, 0xA151, 0xFE55, 0xA152, 0xFE56, 0xA153, + 0xFE57, 0xA154, 0xFE59, 0xA17D, 0xFE5A, 0xA17E, 0xFE5B, 0xA1A1, 0xFE5C, 0xA1A2, 0xFE5D, 0xA1A3, 0xFE5E, 0xA1A4, 0xFE5F, 0xA1CC, + 0xFE60, 0xA1CD, 0xFE61, 0xA1CE, 0xFE62, 0xA1DE, 0xFE63, 0xA1DF, 0xFE64, 0xA1E0, 0xFE65, 0xA1E1, 0xFE66, 0xA1E2, 0xFE68, 0xA242, + 0xFE69, 0xA24C, 0xFE6A, 0xA24D, 0xFE6B, 0xA24E, 0xFF01, 0xA149, 0xFF03, 0xA1AD, 0xFF04, 0xA243, 0xFF05, 0xA248, 0xFF06, 0xA1AE, + 0xFF08, 0xA15D, 0xFF09, 0xA15E, 0xFF0A, 0xA1AF, 0xFF0B, 0xA1CF, 0xFF0C, 0xA141, 0xFF0D, 0xA1D0, 0xFF0E, 0xA144, 0xFF0F, 0xA1FE, + 0xFF10, 0xA2AF, 0xFF11, 0xA2B0, 0xFF12, 0xA2B1, 0xFF13, 0xA2B2, 0xFF14, 0xA2B3, 0xFF15, 0xA2B4, 0xFF16, 0xA2B5, 0xFF17, 0xA2B6, + 0xFF18, 0xA2B7, 0xFF19, 0xA2B8, 0xFF1A, 0xA147, 0xFF1B, 0xA146, 0xFF1C, 0xA1D5, 0xFF1D, 0xA1D7, 0xFF1E, 0xA1D6, 0xFF1F, 0xA148, + 0xFF20, 0xA249, 0xFF21, 0xA2CF, 0xFF22, 0xA2D0, 0xFF23, 0xA2D1, 0xFF24, 0xA2D2, 0xFF25, 0xA2D3, 0xFF26, 0xA2D4, 0xFF27, 0xA2D5, + 0xFF28, 0xA2D6, 0xFF29, 0xA2D7, 0xFF2A, 0xA2D8, 0xFF2B, 0xA2D9, 0xFF2C, 0xA2DA, 0xFF2D, 0xA2DB, 0xFF2E, 0xA2DC, 0xFF2F, 0xA2DD, + 0xFF30, 0xA2DE, 0xFF31, 0xA2DF, 0xFF32, 0xA2E0, 0xFF33, 0xA2E1, 0xFF34, 0xA2E2, 0xFF35, 0xA2E3, 0xFF36, 0xA2E4, 0xFF37, 0xA2E5, + 0xFF38, 0xA2E6, 0xFF39, 0xA2E7, 0xFF3A, 0xA2E8, 0xFF3C, 0xA240, 0xFF3F, 0xA1C4, 0xFF41, 0xA2E9, 0xFF42, 0xA2EA, 0xFF43, 0xA2EB, + 0xFF44, 0xA2EC, 0xFF45, 0xA2ED, 0xFF46, 0xA2EE, 0xFF47, 0xA2EF, 0xFF48, 0xA2F0, 0xFF49, 0xA2F1, 0xFF4A, 0xA2F2, 0xFF4B, 0xA2F3, + 0xFF4C, 0xA2F4, 0xFF4D, 0xA2F5, 0xFF4E, 0xA2F6, 0xFF4F, 0xA2F7, 0xFF50, 0xA2F8, 0xFF51, 0xA2F9, 0xFF52, 0xA2FA, 0xFF53, 0xA2FB, + 0xFF54, 0xA2FC, 0xFF55, 0xA2FD, 0xFF56, 0xA2FE, 0xFF57, 0xA340, 0xFF58, 0xA341, 0xFF59, 0xA342, 0xFF5A, 0xA343, 0xFF5B, 0xA161, + 0xFF5C, 0xA155, 0xFF5D, 0xA162, 0xFF5E, 0xA1E3, 0xFFE0, 0xA246, 0xFFE1, 0xA247, 0xFFE3, 0xA1C3, 0xFFE5, 0xA244, 0, 0 +}; + +static const WCHAR oem2uni950[] = { /* Big5 --> Unicode pairs */ + 0xA140, 0x3000, 0xA141, 0xFF0C, 0xA142, 0x3001, 0xA143, 0x3002, 0xA144, 0xFF0E, 0xA145, 0x2027, 0xA146, 0xFF1B, 0xA147, 0xFF1A, + 0xA148, 0xFF1F, 0xA149, 0xFF01, 0xA14A, 0xFE30, 0xA14B, 0x2026, 0xA14C, 0x2025, 0xA14D, 0xFE50, 0xA14E, 0xFE51, 0xA14F, 0xFE52, + 0xA150, 0x00B7, 0xA151, 0xFE54, 0xA152, 0xFE55, 0xA153, 0xFE56, 0xA154, 0xFE57, 0xA155, 0xFF5C, 0xA156, 0x2013, 0xA157, 0xFE31, + 0xA158, 0x2014, 0xA159, 0xFE33, 0xA15A, 0x2574, 0xA15B, 0xFE34, 0xA15C, 0xFE4F, 0xA15D, 0xFF08, 0xA15E, 0xFF09, 0xA15F, 0xFE35, + 0xA160, 0xFE36, 0xA161, 0xFF5B, 0xA162, 0xFF5D, 0xA163, 0xFE37, 0xA164, 0xFE38, 0xA165, 0x3014, 0xA166, 0x3015, 0xA167, 0xFE39, + 0xA168, 0xFE3A, 0xA169, 0x3010, 0xA16A, 0x3011, 0xA16B, 0xFE3B, 0xA16C, 0xFE3C, 0xA16D, 0x300A, 0xA16E, 0x300B, 0xA16F, 0xFE3D, + 0xA170, 0xFE3E, 0xA171, 0x3008, 0xA172, 0x3009, 0xA173, 0xFE3F, 0xA174, 0xFE40, 0xA175, 0x300C, 0xA176, 0x300D, 0xA177, 0xFE41, + 0xA178, 0xFE42, 0xA179, 0x300E, 0xA17A, 0x300F, 0xA17B, 0xFE43, 0xA17C, 0xFE44, 0xA17D, 0xFE59, 0xA17E, 0xFE5A, 0xA1A1, 0xFE5B, + 0xA1A2, 0xFE5C, 0xA1A3, 0xFE5D, 0xA1A4, 0xFE5E, 0xA1A5, 0x2018, 0xA1A6, 0x2019, 0xA1A7, 0x201C, 0xA1A8, 0x201D, 0xA1A9, 0x301D, + 0xA1AA, 0x301E, 0xA1AB, 0x2035, 0xA1AC, 0x2032, 0xA1AD, 0xFF03, 0xA1AE, 0xFF06, 0xA1AF, 0xFF0A, 0xA1B0, 0x203B, 0xA1B1, 0x00A7, + 0xA1B2, 0x3003, 0xA1B3, 0x25CB, 0xA1B4, 0x25CF, 0xA1B5, 0x25B3, 0xA1B6, 0x25B2, 0xA1B7, 0x25CE, 0xA1B8, 0x2606, 0xA1B9, 0x2605, + 0xA1BA, 0x25C7, 0xA1BB, 0x25C6, 0xA1BC, 0x25A1, 0xA1BD, 0x25A0, 0xA1BE, 0x25BD, 0xA1BF, 0x25BC, 0xA1C0, 0x32A3, 0xA1C1, 0x2105, + 0xA1C2, 0x00AF, 0xA1C3, 0xFFE3, 0xA1C4, 0xFF3F, 0xA1C5, 0x02CD, 0xA1C6, 0xFE49, 0xA1C7, 0xFE4A, 0xA1C8, 0xFE4D, 0xA1C9, 0xFE4E, + 0xA1CA, 0xFE4B, 0xA1CB, 0xFE4C, 0xA1CC, 0xFE5F, 0xA1CD, 0xFE60, 0xA1CE, 0xFE61, 0xA1CF, 0xFF0B, 0xA1D0, 0xFF0D, 0xA1D1, 0x00D7, + 0xA1D2, 0x00F7, 0xA1D3, 0x00B1, 0xA1D4, 0x221A, 0xA1D5, 0xFF1C, 0xA1D6, 0xFF1E, 0xA1D7, 0xFF1D, 0xA1D8, 0x2266, 0xA1D9, 0x2267, + 0xA1DA, 0x2260, 0xA1DB, 0x221E, 0xA1DC, 0x2252, 0xA1DD, 0x2261, 0xA1DE, 0xFE62, 0xA1DF, 0xFE63, 0xA1E0, 0xFE64, 0xA1E1, 0xFE65, + 0xA1E2, 0xFE66, 0xA1E3, 0xFF5E, 0xA1E4, 0x2229, 0xA1E5, 0x222A, 0xA1E6, 0x22A5, 0xA1E7, 0x2220, 0xA1E8, 0x221F, 0xA1E9, 0x22BF, + 0xA1EA, 0x33D2, 0xA1EB, 0x33D1, 0xA1EC, 0x222B, 0xA1ED, 0x222E, 0xA1EE, 0x2235, 0xA1EF, 0x2234, 0xA1F0, 0x2640, 0xA1F1, 0x2642, + 0xA1F2, 0x2295, 0xA1F3, 0x2299, 0xA1F4, 0x2191, 0xA1F5, 0x2193, 0xA1F6, 0x2190, 0xA1F7, 0x2192, 0xA1F8, 0x2196, 0xA1F9, 0x2197, + 0xA1FA, 0x2199, 0xA1FB, 0x2198, 0xA1FC, 0x2225, 0xA1FD, 0x2223, 0xA1FE, 0xFF0F, 0xA240, 0xFF3C, 0xA241, 0x2215, 0xA242, 0xFE68, + 0xA243, 0xFF04, 0xA244, 0xFFE5, 0xA245, 0x3012, 0xA246, 0xFFE0, 0xA247, 0xFFE1, 0xA248, 0xFF05, 0xA249, 0xFF20, 0xA24A, 0x2103, + 0xA24B, 0x2109, 0xA24C, 0xFE69, 0xA24D, 0xFE6A, 0xA24E, 0xFE6B, 0xA24F, 0x33D5, 0xA250, 0x339C, 0xA251, 0x339D, 0xA252, 0x339E, + 0xA253, 0x33CE, 0xA254, 0x33A1, 0xA255, 0x338E, 0xA256, 0x338F, 0xA257, 0x33C4, 0xA258, 0x00B0, 0xA259, 0x5159, 0xA25A, 0x515B, + 0xA25B, 0x515E, 0xA25C, 0x515D, 0xA25D, 0x5161, 0xA25E, 0x5163, 0xA25F, 0x55E7, 0xA260, 0x74E9, 0xA261, 0x7CCE, 0xA262, 0x2581, + 0xA263, 0x2582, 0xA264, 0x2583, 0xA265, 0x2584, 0xA266, 0x2585, 0xA267, 0x2586, 0xA268, 0x2587, 0xA269, 0x2588, 0xA26A, 0x258F, + 0xA26B, 0x258E, 0xA26C, 0x258D, 0xA26D, 0x258C, 0xA26E, 0x258B, 0xA26F, 0x258A, 0xA270, 0x2589, 0xA271, 0x253C, 0xA272, 0x2534, + 0xA273, 0x252C, 0xA274, 0x2524, 0xA275, 0x251C, 0xA276, 0x2594, 0xA277, 0x2500, 0xA278, 0x2502, 0xA279, 0x2595, 0xA27A, 0x250C, + 0xA27B, 0x2510, 0xA27C, 0x2514, 0xA27D, 0x2518, 0xA27E, 0x256D, 0xA2A1, 0x256E, 0xA2A2, 0x2570, 0xA2A3, 0x256F, 0xA2A4, 0x2550, + 0xA2A5, 0x255E, 0xA2A6, 0x256A, 0xA2A7, 0x2561, 0xA2A8, 0x25E2, 0xA2A9, 0x25E3, 0xA2AA, 0x25E5, 0xA2AB, 0x25E4, 0xA2AC, 0x2571, + 0xA2AD, 0x2572, 0xA2AE, 0x2573, 0xA2AF, 0xFF10, 0xA2B0, 0xFF11, 0xA2B1, 0xFF12, 0xA2B2, 0xFF13, 0xA2B3, 0xFF14, 0xA2B4, 0xFF15, + 0xA2B5, 0xFF16, 0xA2B6, 0xFF17, 0xA2B7, 0xFF18, 0xA2B8, 0xFF19, 0xA2B9, 0x2160, 0xA2BA, 0x2161, 0xA2BB, 0x2162, 0xA2BC, 0x2163, + 0xA2BD, 0x2164, 0xA2BE, 0x2165, 0xA2BF, 0x2166, 0xA2C0, 0x2167, 0xA2C1, 0x2168, 0xA2C2, 0x2169, 0xA2C3, 0x3021, 0xA2C4, 0x3022, + 0xA2C5, 0x3023, 0xA2C6, 0x3024, 0xA2C7, 0x3025, 0xA2C8, 0x3026, 0xA2C9, 0x3027, 0xA2CA, 0x3028, 0xA2CB, 0x3029, 0xA2CC, 0x5341, + 0xA2CD, 0x5344, 0xA2CE, 0x5345, 0xA2CF, 0xFF21, 0xA2D0, 0xFF22, 0xA2D1, 0xFF23, 0xA2D2, 0xFF24, 0xA2D3, 0xFF25, 0xA2D4, 0xFF26, + 0xA2D5, 0xFF27, 0xA2D6, 0xFF28, 0xA2D7, 0xFF29, 0xA2D8, 0xFF2A, 0xA2D9, 0xFF2B, 0xA2DA, 0xFF2C, 0xA2DB, 0xFF2D, 0xA2DC, 0xFF2E, + 0xA2DD, 0xFF2F, 0xA2DE, 0xFF30, 0xA2DF, 0xFF31, 0xA2E0, 0xFF32, 0xA2E1, 0xFF33, 0xA2E2, 0xFF34, 0xA2E3, 0xFF35, 0xA2E4, 0xFF36, + 0xA2E5, 0xFF37, 0xA2E6, 0xFF38, 0xA2E7, 0xFF39, 0xA2E8, 0xFF3A, 0xA2E9, 0xFF41, 0xA2EA, 0xFF42, 0xA2EB, 0xFF43, 0xA2EC, 0xFF44, + 0xA2ED, 0xFF45, 0xA2EE, 0xFF46, 0xA2EF, 0xFF47, 0xA2F0, 0xFF48, 0xA2F1, 0xFF49, 0xA2F2, 0xFF4A, 0xA2F3, 0xFF4B, 0xA2F4, 0xFF4C, + 0xA2F5, 0xFF4D, 0xA2F6, 0xFF4E, 0xA2F7, 0xFF4F, 0xA2F8, 0xFF50, 0xA2F9, 0xFF51, 0xA2FA, 0xFF52, 0xA2FB, 0xFF53, 0xA2FC, 0xFF54, + 0xA2FD, 0xFF55, 0xA2FE, 0xFF56, 0xA340, 0xFF57, 0xA341, 0xFF58, 0xA342, 0xFF59, 0xA343, 0xFF5A, 0xA344, 0x0391, 0xA345, 0x0392, + 0xA346, 0x0393, 0xA347, 0x0394, 0xA348, 0x0395, 0xA349, 0x0396, 0xA34A, 0x0397, 0xA34B, 0x0398, 0xA34C, 0x0399, 0xA34D, 0x039A, + 0xA34E, 0x039B, 0xA34F, 0x039C, 0xA350, 0x039D, 0xA351, 0x039E, 0xA352, 0x039F, 0xA353, 0x03A0, 0xA354, 0x03A1, 0xA355, 0x03A3, + 0xA356, 0x03A4, 0xA357, 0x03A5, 0xA358, 0x03A6, 0xA359, 0x03A7, 0xA35A, 0x03A8, 0xA35B, 0x03A9, 0xA35C, 0x03B1, 0xA35D, 0x03B2, + 0xA35E, 0x03B3, 0xA35F, 0x03B4, 0xA360, 0x03B5, 0xA361, 0x03B6, 0xA362, 0x03B7, 0xA363, 0x03B8, 0xA364, 0x03B9, 0xA365, 0x03BA, + 0xA366, 0x03BB, 0xA367, 0x03BC, 0xA368, 0x03BD, 0xA369, 0x03BE, 0xA36A, 0x03BF, 0xA36B, 0x03C0, 0xA36C, 0x03C1, 0xA36D, 0x03C3, + 0xA36E, 0x03C4, 0xA36F, 0x03C5, 0xA370, 0x03C6, 0xA371, 0x03C7, 0xA372, 0x03C8, 0xA373, 0x03C9, 0xA374, 0x3105, 0xA375, 0x3106, + 0xA376, 0x3107, 0xA377, 0x3108, 0xA378, 0x3109, 0xA379, 0x310A, 0xA37A, 0x310B, 0xA37B, 0x310C, 0xA37C, 0x310D, 0xA37D, 0x310E, + 0xA37E, 0x310F, 0xA3A1, 0x3110, 0xA3A2, 0x3111, 0xA3A3, 0x3112, 0xA3A4, 0x3113, 0xA3A5, 0x3114, 0xA3A6, 0x3115, 0xA3A7, 0x3116, + 0xA3A8, 0x3117, 0xA3A9, 0x3118, 0xA3AA, 0x3119, 0xA3AB, 0x311A, 0xA3AC, 0x311B, 0xA3AD, 0x311C, 0xA3AE, 0x311D, 0xA3AF, 0x311E, + 0xA3B0, 0x311F, 0xA3B1, 0x3120, 0xA3B2, 0x3121, 0xA3B3, 0x3122, 0xA3B4, 0x3123, 0xA3B5, 0x3124, 0xA3B6, 0x3125, 0xA3B7, 0x3126, + 0xA3B8, 0x3127, 0xA3B9, 0x3128, 0xA3BA, 0x3129, 0xA3BB, 0x02D9, 0xA3BC, 0x02C9, 0xA3BD, 0x02CA, 0xA3BE, 0x02C7, 0xA3BF, 0x02CB, + 0xA3E1, 0x20AC, 0xA440, 0x4E00, 0xA441, 0x4E59, 0xA442, 0x4E01, 0xA443, 0x4E03, 0xA444, 0x4E43, 0xA445, 0x4E5D, 0xA446, 0x4E86, + 0xA447, 0x4E8C, 0xA448, 0x4EBA, 0xA449, 0x513F, 0xA44A, 0x5165, 0xA44B, 0x516B, 0xA44C, 0x51E0, 0xA44D, 0x5200, 0xA44E, 0x5201, + 0xA44F, 0x529B, 0xA450, 0x5315, 0xA451, 0x5341, 0xA452, 0x535C, 0xA453, 0x53C8, 0xA454, 0x4E09, 0xA455, 0x4E0B, 0xA456, 0x4E08, + 0xA457, 0x4E0A, 0xA458, 0x4E2B, 0xA459, 0x4E38, 0xA45A, 0x51E1, 0xA45B, 0x4E45, 0xA45C, 0x4E48, 0xA45D, 0x4E5F, 0xA45E, 0x4E5E, + 0xA45F, 0x4E8E, 0xA460, 0x4EA1, 0xA461, 0x5140, 0xA462, 0x5203, 0xA463, 0x52FA, 0xA464, 0x5343, 0xA465, 0x53C9, 0xA466, 0x53E3, + 0xA467, 0x571F, 0xA468, 0x58EB, 0xA469, 0x5915, 0xA46A, 0x5927, 0xA46B, 0x5973, 0xA46C, 0x5B50, 0xA46D, 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0x9DDC, 0xF7BE, 0x9DD1, 0xF7BF, 0x9DDF, 0xF7C0, 0x9DE9, 0xF7C1, 0x9DD9, + 0xF7C2, 0x9DD8, 0xF7C3, 0x9DD6, 0xF7C4, 0x9DF5, 0xF7C5, 0x9DD5, 0xF7C6, 0x9DDD, 0xF7C7, 0x9EB6, 0xF7C8, 0x9EF0, 0xF7C9, 0x9F35, + 0xF7CA, 0x9F33, 0xF7CB, 0x9F32, 0xF7CC, 0x9F42, 0xF7CD, 0x9F6B, 0xF7CE, 0x9F95, 0xF7CF, 0x9FA2, 0xF7D0, 0x513D, 0xF7D1, 0x5299, + 0xF7D2, 0x58E8, 0xF7D3, 0x58E7, 0xF7D4, 0x5972, 0xF7D5, 0x5B4D, 0xF7D6, 0x5DD8, 0xF7D7, 0x882F, 0xF7D8, 0x5F4F, 0xF7D9, 0x6201, + 0xF7DA, 0x6203, 0xF7DB, 0x6204, 0xF7DC, 0x6529, 0xF7DD, 0x6525, 0xF7DE, 0x6596, 0xF7DF, 0x66EB, 0xF7E0, 0x6B11, 0xF7E1, 0x6B12, + 0xF7E2, 0x6B0F, 0xF7E3, 0x6BCA, 0xF7E4, 0x705B, 0xF7E5, 0x705A, 0xF7E6, 0x7222, 0xF7E7, 0x7382, 0xF7E8, 0x7381, 0xF7E9, 0x7383, + 0xF7EA, 0x7670, 0xF7EB, 0x77D4, 0xF7EC, 0x7C67, 0xF7ED, 0x7C66, 0xF7EE, 0x7E95, 0xF7EF, 0x826C, 0xF7F0, 0x863A, 0xF7F1, 0x8640, + 0xF7F2, 0x8639, 0xF7F3, 0x863C, 0xF7F4, 0x8631, 0xF7F5, 0x863B, 0xF7F6, 0x863E, 0xF7F7, 0x8830, 0xF7F8, 0x8832, 0xF7F9, 0x882E, + 0xF7FA, 0x8833, 0xF7FB, 0x8976, 0xF7FC, 0x8974, 0xF7FD, 0x8973, 0xF7FE, 0x89FE, 0xF840, 0x8B8C, 0xF841, 0x8B8E, 0xF842, 0x8B8B, + 0xF843, 0x8B88, 0xF844, 0x8C45, 0xF845, 0x8D19, 0xF846, 0x8E98, 0xF847, 0x8F64, 0xF848, 0x8F63, 0xF849, 0x91BC, 0xF84A, 0x9462, + 0xF84B, 0x9455, 0xF84C, 0x945D, 0xF84D, 0x9457, 0xF84E, 0x945E, 0xF84F, 0x97C4, 0xF850, 0x97C5, 0xF851, 0x9800, 0xF852, 0x9A56, + 0xF853, 0x9A59, 0xF854, 0x9B1E, 0xF855, 0x9B1F, 0xF856, 0x9B20, 0xF857, 0x9C52, 0xF858, 0x9C58, 0xF859, 0x9C50, 0xF85A, 0x9C4A, + 0xF85B, 0x9C4D, 0xF85C, 0x9C4B, 0xF85D, 0x9C55, 0xF85E, 0x9C59, 0xF85F, 0x9C4C, 0xF860, 0x9C4E, 0xF861, 0x9DFB, 0xF862, 0x9DF7, + 0xF863, 0x9DEF, 0xF864, 0x9DE3, 0xF865, 0x9DEB, 0xF866, 0x9DF8, 0xF867, 0x9DE4, 0xF868, 0x9DF6, 0xF869, 0x9DE1, 0xF86A, 0x9DEE, + 0xF86B, 0x9DE6, 0xF86C, 0x9DF2, 0xF86D, 0x9DF0, 0xF86E, 0x9DE2, 0xF86F, 0x9DEC, 0xF870, 0x9DF4, 0xF871, 0x9DF3, 0xF872, 0x9DE8, + 0xF873, 0x9DED, 0xF874, 0x9EC2, 0xF875, 0x9ED0, 0xF876, 0x9EF2, 0xF877, 0x9EF3, 0xF878, 0x9F06, 0xF879, 0x9F1C, 0xF87A, 0x9F38, + 0xF87B, 0x9F37, 0xF87C, 0x9F36, 0xF87D, 0x9F43, 0xF87E, 0x9F4F, 0xF8A1, 0x9F71, 0xF8A2, 0x9F70, 0xF8A3, 0x9F6E, 0xF8A4, 0x9F6F, + 0xF8A5, 0x56D3, 0xF8A6, 0x56CD, 0xF8A7, 0x5B4E, 0xF8A8, 0x5C6D, 0xF8A9, 0x652D, 0xF8AA, 0x66ED, 0xF8AB, 0x66EE, 0xF8AC, 0x6B13, + 0xF8AD, 0x705F, 0xF8AE, 0x7061, 0xF8AF, 0x705D, 0xF8B0, 0x7060, 0xF8B1, 0x7223, 0xF8B2, 0x74DB, 0xF8B3, 0x74E5, 0xF8B4, 0x77D5, + 0xF8B5, 0x7938, 0xF8B6, 0x79B7, 0xF8B7, 0x79B6, 0xF8B8, 0x7C6A, 0xF8B9, 0x7E97, 0xF8BA, 0x7F89, 0xF8BB, 0x826D, 0xF8BC, 0x8643, + 0xF8BD, 0x8838, 0xF8BE, 0x8837, 0xF8BF, 0x8835, 0xF8C0, 0x884B, 0xF8C1, 0x8B94, 0xF8C2, 0x8B95, 0xF8C3, 0x8E9E, 0xF8C4, 0x8E9F, + 0xF8C5, 0x8EA0, 0xF8C6, 0x8E9D, 0xF8C7, 0x91BE, 0xF8C8, 0x91BD, 0xF8C9, 0x91C2, 0xF8CA, 0x946B, 0xF8CB, 0x9468, 0xF8CC, 0x9469, + 0xF8CD, 0x96E5, 0xF8CE, 0x9746, 0xF8CF, 0x9743, 0xF8D0, 0x9747, 0xF8D1, 0x97C7, 0xF8D2, 0x97E5, 0xF8D3, 0x9A5E, 0xF8D4, 0x9AD5, + 0xF8D5, 0x9B59, 0xF8D6, 0x9C63, 0xF8D7, 0x9C67, 0xF8D8, 0x9C66, 0xF8D9, 0x9C62, 0xF8DA, 0x9C5E, 0xF8DB, 0x9C60, 0xF8DC, 0x9E02, + 0xF8DD, 0x9DFE, 0xF8DE, 0x9E07, 0xF8DF, 0x9E03, 0xF8E0, 0x9E06, 0xF8E1, 0x9E05, 0xF8E2, 0x9E00, 0xF8E3, 0x9E01, 0xF8E4, 0x9E09, + 0xF8E5, 0x9DFF, 0xF8E6, 0x9DFD, 0xF8E7, 0x9E04, 0xF8E8, 0x9EA0, 0xF8E9, 0x9F1E, 0xF8EA, 0x9F46, 0xF8EB, 0x9F74, 0xF8EC, 0x9F75, + 0xF8ED, 0x9F76, 0xF8EE, 0x56D4, 0xF8EF, 0x652E, 0xF8F0, 0x65B8, 0xF8F1, 0x6B18, 0xF8F2, 0x6B19, 0xF8F3, 0x6B17, 0xF8F4, 0x6B1A, + 0xF8F5, 0x7062, 0xF8F6, 0x7226, 0xF8F7, 0x72AA, 0xF8F8, 0x77D8, 0xF8F9, 0x77D9, 0xF8FA, 0x7939, 0xF8FB, 0x7C69, 0xF8FC, 0x7C6B, + 0xF8FD, 0x7CF6, 0xF8FE, 0x7E9A, 0xF940, 0x7E98, 0xF941, 0x7E9B, 0xF942, 0x7E99, 0xF943, 0x81E0, 0xF944, 0x81E1, 0xF945, 0x8646, + 0xF946, 0x8647, 0xF947, 0x8648, 0xF948, 0x8979, 0xF949, 0x897A, 0xF94A, 0x897C, 0xF94B, 0x897B, 0xF94C, 0x89FF, 0xF94D, 0x8B98, + 0xF94E, 0x8B99, 0xF94F, 0x8EA5, 0xF950, 0x8EA4, 0xF951, 0x8EA3, 0xF952, 0x946E, 0xF953, 0x946D, 0xF954, 0x946F, 0xF955, 0x9471, + 0xF956, 0x9473, 0xF957, 0x9749, 0xF958, 0x9872, 0xF959, 0x995F, 0xF95A, 0x9C68, 0xF95B, 0x9C6E, 0xF95C, 0x9C6D, 0xF95D, 0x9E0B, + 0xF95E, 0x9E0D, 0xF95F, 0x9E10, 0xF960, 0x9E0F, 0xF961, 0x9E12, 0xF962, 0x9E11, 0xF963, 0x9EA1, 0xF964, 0x9EF5, 0xF965, 0x9F09, + 0xF966, 0x9F47, 0xF967, 0x9F78, 0xF968, 0x9F7B, 0xF969, 0x9F7A, 0xF96A, 0x9F79, 0xF96B, 0x571E, 0xF96C, 0x7066, 0xF96D, 0x7C6F, + 0xF96E, 0x883C, 0xF96F, 0x8DB2, 0xF970, 0x8EA6, 0xF971, 0x91C3, 0xF972, 0x9474, 0xF973, 0x9478, 0xF974, 0x9476, 0xF975, 0x9475, + 0xF976, 0x9A60, 0xF977, 0x9C74, 0xF978, 0x9C73, 0xF979, 0x9C71, 0xF97A, 0x9C75, 0xF97B, 0x9E14, 0xF97C, 0x9E13, 0xF97D, 0x9EF6, + 0xF97E, 0x9F0A, 0xF9A1, 0x9FA4, 0xF9A2, 0x7068, 0xF9A3, 0x7065, 0xF9A4, 0x7CF7, 0xF9A5, 0x866A, 0xF9A6, 0x883E, 0xF9A7, 0x883D, + 0xF9A8, 0x883F, 0xF9A9, 0x8B9E, 0xF9AA, 0x8C9C, 0xF9AB, 0x8EA9, 0xF9AC, 0x8EC9, 0xF9AD, 0x974B, 0xF9AE, 0x9873, 0xF9AF, 0x9874, + 0xF9B0, 0x98CC, 0xF9B1, 0x9961, 0xF9B2, 0x99AB, 0xF9B3, 0x9A64, 0xF9B4, 0x9A66, 0xF9B5, 0x9A67, 0xF9B6, 0x9B24, 0xF9B7, 0x9E15, + 0xF9B8, 0x9E17, 0xF9B9, 0x9F48, 0xF9BA, 0x6207, 0xF9BB, 0x6B1E, 0xF9BC, 0x7227, 0xF9BD, 0x864C, 0xF9BE, 0x8EA8, 0xF9BF, 0x9482, + 0xF9C0, 0x9480, 0xF9C1, 0x9481, 0xF9C2, 0x9A69, 0xF9C3, 0x9A68, 0xF9C4, 0x9B2E, 0xF9C5, 0x9E19, 0xF9C6, 0x7229, 0xF9C7, 0x864B, + 0xF9C8, 0x8B9F, 0xF9C9, 0x9483, 0xF9CA, 0x9C79, 0xF9CB, 0x9EB7, 0xF9CC, 0x7675, 0xF9CD, 0x9A6B, 0xF9CE, 0x9C7A, 0xF9CF, 0x9E1D, + 0xF9D0, 0x7069, 0xF9D1, 0x706A, 0xF9D2, 0x9EA4, 0xF9D3, 0x9F7E, 0xF9D4, 0x9F49, 0xF9D5, 0x9F98, 0xF9D6, 0x7881, 0xF9D7, 0x92B9, + 0xF9D8, 0x88CF, 0xF9D9, 0x58BB, 0xF9DA, 0x6052, 0xF9DB, 0x7CA7, 0xF9DC, 0x5AFA, 0xF9DD, 0x2554, 0xF9DE, 0x2566, 0xF9DF, 0x2557, + 0xF9E0, 0x2560, 0xF9E1, 0x256C, 0xF9E2, 0x2563, 0xF9E3, 0x255A, 0xF9E4, 0x2569, 0xF9E5, 0x255D, 0xF9E6, 0x2552, 0xF9E7, 0x2564, + 0xF9E8, 0x2555, 0xF9E9, 0x255E, 0xF9EA, 0x256A, 0xF9EB, 0x2561, 0xF9EC, 0x2558, 0xF9ED, 0x2567, 0xF9EE, 0x255B, 0xF9EF, 0x2553, + 0xF9F0, 0x2565, 0xF9F1, 0x2556, 0xF9F2, 0x255F, 0xF9F3, 0x256B, 0xF9F4, 0x2562, 0xF9F5, 0x2559, 0xF9F6, 0x2568, 0xF9F7, 0x255C, + 0xF9F8, 0x2551, 0xF9F9, 0x2550, 0xF9FA, 0x256D, 0xF9FB, 0x256E, 0xF9FC, 0x2570, 0xF9FD, 0x256F, 0xF9FE, 0x2593, 0, 0 +}; +#endif + +#if FF_CODE_PAGE == 437 || FF_CODE_PAGE == 0 +static const WCHAR uc437[] = { /* CP437(U.S.) to Unicode conversion table */ + 0x00C7, 0x00FC, 0x00E9, 0x00E2, 0x00E4, 0x00E0, 0x00E5, 0x00E7, 0x00EA, 0x00EB, 0x00E8, 0x00EF, 0x00EE, 0x00EC, 0x00C4, 0x00C5, + 0x00C9, 0x00E6, 0x00C6, 0x00F4, 0x00F6, 0x00F2, 0x00FB, 0x00F9, 0x00FF, 0x00D6, 0x00DC, 0x00A2, 0x00A3, 0x00A5, 0x20A7, 0x0192, + 0x00E1, 0x00ED, 0x00F3, 0x00FA, 0x00F1, 0x00D1, 0x00AA, 0x00BA, 0x00BF, 0x2310, 0x00AC, 0x00BD, 0x00BC, 0x00A1, 0x00AB, 0x00BB, + 0x2591, 0x2592, 0x2593, 0x2502, 0x2524, 0x2561, 0x2562, 0x2556, 0x2555, 0x2563, 0x2551, 0x2557, 0x255D, 0x255C, 0x255B, 0x2510, + 0x2514, 0x2534, 0x252C, 0x251C, 0x2500, 0x253C, 0x255E, 0x255F, 0x255A, 0x2554, 0x2569, 0x2566, 0x2560, 0x2550, 0x256C, 0x2567, + 0x2568, 0x2564, 0x2565, 0x2559, 0x2558, 0x2552, 0x2553, 0x256B, 0x256A, 0x2518, 0x250C, 0x2588, 0x2584, 0x258C, 0x2590, 0x2580, + 0x03B1, 0x00DF, 0x0393, 0x03C0, 0x03A3, 0x03C3, 0x00B5, 0x03C4, 0x03A6, 0x0398, 0x03A9, 0x03B4, 0x221E, 0x03C6, 0x03B5, 0x2229, + 0x2261, 0x00B1, 0x2265, 0x2264, 0x2320, 0x2321, 0x00F7, 0x2248, 0x00B0, 0x2219, 0x00B7, 0x221A, 0x207F, 0x00B2, 0x25A0, 0x00A0 +}; +#endif +#if FF_CODE_PAGE == 720 || FF_CODE_PAGE == 0 +static const WCHAR uc720[] = { /* CP720(Arabic) to Unicode conversion table */ + 0x0000, 0x0000, 0x00E9, 0x00E2, 0x0000, 0x00E0, 0x0000, 0x00E7, 0x00EA, 0x00EB, 0x00E8, 0x00EF, 0x00EE, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0651, 0x0652, 0x00F4, 0x00A4, 0x0640, 0x00FB, 0x00F9, 0x0621, 0x0622, 0x0623, 0x0624, 0x00A3, 0x0625, 0x0626, 0x0627, + 0x0628, 0x0629, 0x062A, 0x062B, 0x062C, 0x062D, 0x062E, 0x062F, 0x0630, 0x0631, 0x0632, 0x0633, 0x0634, 0x0635, 0x00AB, 0x00BB, + 0x2591, 0x2592, 0x2593, 0x2502, 0x2524, 0x2561, 0x2562, 0x2556, 0x2555, 0x2563, 0x2551, 0x2557, 0x255D, 0x255C, 0x255B, 0x2510, + 0x2514, 0x2534, 0x252C, 0x251C, 0x2500, 0x253C, 0x255E, 0x255F, 0x255A, 0x2554, 0x2569, 0x2566, 0x2560, 0x2550, 0x256C, 0x2567, + 0x2568, 0x2564, 0x2565, 0x2559, 0x2558, 0x2552, 0x2553, 0x256B, 0x256A, 0x2518, 0x250C, 0x2588, 0x2584, 0x258C, 0x2590, 0x2580, + 0x0636, 0x0637, 0x0638, 0x0639, 0x063A, 0x0641, 0x00B5, 0x0642, 0x0643, 0x0644, 0x0645, 0x0646, 0x0647, 0x0648, 0x0649, 0x064A, + 0x2261, 0x064B, 0x064C, 0x064D, 0x064E, 0x064F, 0x0650, 0x2248, 0x00B0, 0x2219, 0x00B7, 0x221A, 0x207F, 0x00B2, 0x25A0, 0x00A0 +}; +#endif +#if FF_CODE_PAGE == 737 || FF_CODE_PAGE == 0 +static const WCHAR uc737[] = { /* CP737(Greek) to Unicode conversion table */ + 0x0391, 0x0392, 0x0393, 0x0394, 0x0395, 0x0396, 0x0397, 0x0398, 0x0399, 0x039A, 0x039B, 0x039C, 0x039D, 0x039E, 0x039F, 0x03A0, + 0x03A1, 0x03A3, 0x03A4, 0x03A5, 0x03A6, 0x03A7, 0x03A8, 0x03A9, 0x03B1, 0x03B2, 0x03B3, 0x03B4, 0x03B5, 0x03B6, 0x03B7, 0x03B8, + 0x03B9, 0x03BA, 0x03BB, 0x03BC, 0x03BD, 0x03BE, 0x03BF, 0x03C0, 0x03C1, 0x03C3, 0x03C2, 0x03C4, 0x03C5, 0x03C6, 0x03C7, 0x03C8, + 0x2591, 0x2592, 0x2593, 0x2502, 0x2524, 0x2561, 0x2562, 0x2556, 0x2555, 0x2563, 0x2551, 0x2557, 0x255D, 0x255C, 0x255B, 0x2510, + 0x2514, 0x2534, 0x252C, 0x251C, 0x2500, 0x253C, 0x255E, 0x255F, 0x255A, 0x2554, 0x2569, 0x2566, 0x2560, 0x2550, 0x256C, 0x2567, + 0x2568, 0x2564, 0x2565, 0x2559, 0x2558, 0x2552, 0x2553, 0x256B, 0x256A, 0x2518, 0x250C, 0x2588, 0x2584, 0x258C, 0x2590, 0x2580, + 0x03C9, 0x03AC, 0x03AD, 0x03AE, 0x03CA, 0x03AF, 0x03CC, 0x03CD, 0x03CB, 0x03CE, 0x0386, 0x0388, 0x0389, 0x038A, 0x038C, 0x038E, + 0x038F, 0x00B1, 0x2265, 0x2264, 0x03AA, 0x03AB, 0x00F7, 0x2248, 0x00B0, 0x2219, 0x00B7, 0x221A, 0x207F, 0x00B2, 0x25A0, 0x00A0 +}; +#endif +#if FF_CODE_PAGE == 771 || FF_CODE_PAGE == 0 +static const WCHAR uc771[] = { /* CP771(KBL) to Unicode conversion table */ + 0x0410, 0x0411, 0x0412, 0x0413, 0x0414, 0x0415, 0x0416, 0x0417, 0x0418, 0x0419, 0x041A, 0x041B, 0x041C, 0x041D, 0x041E, 0x041F, + 0x0420, 0x0421, 0x0422, 0x0423, 0x0424, 0x0425, 0x0426, 0x0427, 0x0428, 0x0429, 0x042A, 0x042B, 0x042C, 0x042D, 0x042E, 0x042F, + 0x0430, 0x0431, 0x0432, 0x0433, 0x0434, 0x0435, 0x0436, 0x0437, 0x0438, 0x0439, 0x043A, 0x043B, 0x043C, 0x043D, 0x043E, 0x043F, + 0x2591, 0x2592, 0x2593, 0x2502, 0x2524, 0x2561, 0x2562, 0x2556, 0x2555, 0x2563, 0x2551, 0x2557, 0x255D, 0x255C, 0x2558, 0x2510, + 0x2514, 0x2534, 0x252C, 0x251C, 0x2500, 0x253C, 0x255E, 0x255F, 0x255A, 0x2554, 0x2569, 0x2566, 0x2560, 0x2550, 0x256C, 0x2567, + 0x2568, 0x2564, 0x2565, 0x2559, 0x2558, 0x2552, 0x2553, 0x256B, 0x256A, 0x2518, 0x250C, 0x2588, 0x0104, 0x0105, 0x010C, 0x010D, + 0x0440, 0x0441, 0x0442, 0x0443, 0x0444, 0x0445, 0x0446, 0x0447, 0x0448, 0x0449, 0x044A, 0x044B, 0x044C, 0x044D, 0x044E, 0x044F, + 0x0118, 0x0119, 0x0116, 0x0117, 0x012E, 0x012F, 0x0160, 0x0161, 0x0172, 0x0173, 0x016A, 0x016B, 0x017D, 0x017E, 0x25A0, 0x00A0 +}; +#endif +#if FF_CODE_PAGE == 775 || FF_CODE_PAGE == 0 +static const WCHAR uc775[] = { /* CP775(Baltic) to Unicode conversion table */ + 0x0106, 0x00FC, 0x00E9, 0x0101, 0x00E4, 0x0123, 0x00E5, 0x0107, 0x0142, 0x0113, 0x0156, 0x0157, 0x012B, 0x0179, 0x00C4, 0x00C5, + 0x00C9, 0x00E6, 0x00C6, 0x014D, 0x00F6, 0x0122, 0x00A2, 0x015A, 0x015B, 0x00D6, 0x00DC, 0x00F8, 0x00A3, 0x00D8, 0x00D7, 0x00A4, + 0x0100, 0x012A, 0x00F3, 0x017B, 0x017C, 0x017A, 0x201D, 0x00A6, 0x00A9, 0x00AE, 0x00AC, 0x00BD, 0x00BC, 0x0141, 0x00AB, 0x00BB, + 0x2591, 0x2592, 0x2593, 0x2502, 0x2524, 0x0104, 0x010C, 0x0118, 0x0116, 0x2563, 0x2551, 0x2557, 0x255D, 0x012E, 0x0160, 0x2510, + 0x2514, 0x2534, 0x252C, 0x251C, 0x2500, 0x253C, 0x0172, 0x016A, 0x255A, 0x2554, 0x2569, 0x2566, 0x2560, 0x2550, 0x256C, 0x017D, + 0x0105, 0x010D, 0x0119, 0x0117, 0x012F, 0x0161, 0x0173, 0x016B, 0x017E, 0x2518, 0x250C, 0x2588, 0x2584, 0x258C, 0x2590, 0x2580, + 0x00D3, 0x00DF, 0x014C, 0x0143, 0x00F5, 0x00D5, 0x00B5, 0x0144, 0x0136, 0x0137, 0x013B, 0x013C, 0x0146, 0x0112, 0x0145, 0x2019, + 0x00AD, 0x00B1, 0x201C, 0x00BE, 0x00B6, 0x00A7, 0x00F7, 0x201E, 0x00B0, 0x2219, 0x00B7, 0x00B9, 0x00B3, 0x00B2, 0x25A0, 0x00A0 +}; +#endif +#if FF_CODE_PAGE == 850 || FF_CODE_PAGE == 0 +static const WCHAR uc850[] = { /* CP850(Latin 1) to Unicode conversion table */ + 0x00C7, 0x00FC, 0x00E9, 0x00E2, 0x00E4, 0x00E0, 0x00E5, 0x00E7, 0x00EA, 0x00EB, 0x00E8, 0x00EF, 0x00EE, 0x00EC, 0x00C4, 0x00C5, + 0x00C9, 0x00E6, 0x00C6, 0x00F4, 0x00F6, 0x00F2, 0x00FB, 0x00F9, 0x00FF, 0x00D6, 0x00DC, 0x00F8, 0x00A3, 0x00D8, 0x00D7, 0x0192, + 0x00E1, 0x00ED, 0x00F3, 0x00FA, 0x00F1, 0x00D1, 0x00AA, 0x00BA, 0x00BF, 0x00AE, 0x00AC, 0x00BD, 0x00BC, 0x00A1, 0x00AB, 0x00BB, + 0x2591, 0x2592, 0x2593, 0x2502, 0x2524, 0x00C1, 0x00C2, 0x00C0, 0x00A9, 0x2563, 0x2551, 0x2557, 0x255D, 0x00A2, 0x00A5, 0x2510, + 0x2514, 0x2534, 0x252C, 0x251C, 0x2500, 0x253C, 0x00E3, 0x00C3, 0x255A, 0x2554, 0x2569, 0x2566, 0x2560, 0x2550, 0x256C, 0x00A4, + 0x00F0, 0x00D0, 0x00CA, 0x00CB, 0x00C8, 0x0131, 0x00CD, 0x00CE, 0x00CF, 0x2518, 0x250C, 0x2588, 0x2584, 0x00A6, 0x00CC, 0x2580, + 0x00D3, 0x00DF, 0x00D4, 0x00D2, 0x00F5, 0x00D5, 0x00B5, 0x00FE, 0x00DE, 0x00DA, 0x00DB, 0x00D9, 0x00FD, 0x00DD, 0x00AF, 0x00B4, + 0x00AD, 0x00B1, 0x2017, 0x00BE, 0x00B6, 0x00A7, 0x00F7, 0x00B8, 0x00B0, 0x00A8, 0x00B7, 0x00B9, 0x00B3, 0x00B2, 0x25A0, 0x00A0 +}; +#endif +#if FF_CODE_PAGE == 852 || FF_CODE_PAGE == 0 +static const WCHAR uc852[] = { /* CP852(Latin 2) to Unicode conversion table */ + 0x00C7, 0x00FC, 0x00E9, 0x00E2, 0x00E4, 0x016F, 0x0107, 0x00E7, 0x0142, 0x00EB, 0x0150, 0x0151, 0x00EE, 0x0179, 0x00C4, 0x0106, + 0x00C9, 0x0139, 0x013A, 0x00F4, 0x00F6, 0x013D, 0x013E, 0x015A, 0x015B, 0x00D6, 0x00DC, 0x0164, 0x0165, 0x0141, 0x00D7, 0x010D, + 0x00E1, 0x00ED, 0x00F3, 0x00FA, 0x0104, 0x0105, 0x017D, 0x017E, 0x0118, 0x0119, 0x00AC, 0x017A, 0x010C, 0x015F, 0x00AB, 0x00BB, + 0x2591, 0x2592, 0x2593, 0x2502, 0x2524, 0x00C1, 0x00C2, 0x011A, 0x015E, 0x2563, 0x2551, 0x2557, 0x255D, 0x017B, 0x017C, 0x2510, + 0x2514, 0x2534, 0x252C, 0x251C, 0x2500, 0x253C, 0x0102, 0x0103, 0x255A, 0x2554, 0x2569, 0x2566, 0x2560, 0x2550, 0x256C, 0x00A4, + 0x0111, 0x0110, 0x010E, 0x00CB, 0x010F, 0x0147, 0x00CD, 0x00CE, 0x011B, 0x2518, 0x250C, 0x2588, 0x2584, 0x0162, 0x016E, 0x2580, + 0x00D3, 0x00DF, 0x00D4, 0x0143, 0x0144, 0x0148, 0x0160, 0x0161, 0x0154, 0x00DA, 0x0155, 0x0170, 0x00FD, 0x00DD, 0x0163, 0x00B4, + 0x00AD, 0x02DD, 0x02DB, 0x02C7, 0x02D8, 0x00A7, 0x00F7, 0x00B8, 0x00B0, 0x00A8, 0x02D9, 0x0171, 0x0158, 0x0159, 0x25A0, 0x00A0 +}; +#endif +#if FF_CODE_PAGE == 855 || FF_CODE_PAGE == 0 +static const WCHAR uc855[] = { /* CP855(Cyrillic) to Unicode conversion table */ + 0x0452, 0x0402, 0x0453, 0x0403, 0x0451, 0x0401, 0x0454, 0x0404, 0x0455, 0x0405, 0x0456, 0x0406, 0x0457, 0x0407, 0x0458, 0x0408, + 0x0459, 0x0409, 0x045A, 0x040A, 0x045B, 0x040B, 0x045C, 0x040C, 0x045E, 0x040E, 0x045F, 0x040F, 0x044E, 0x042E, 0x044A, 0x042A, + 0x0430, 0x0410, 0x0431, 0x0411, 0x0446, 0x0426, 0x0434, 0x0414, 0x0435, 0x0415, 0x0444, 0x0424, 0x0433, 0x0413, 0x00AB, 0x00BB, + 0x2591, 0x2592, 0x2593, 0x2502, 0x2524, 0x0445, 0x0425, 0x0438, 0x0418, 0x2563, 0x2551, 0x2557, 0x255D, 0x0439, 0x0419, 0x2510, + 0x2514, 0x2534, 0x252C, 0x251C, 0x2500, 0x253C, 0x043A, 0x041A, 0x255A, 0x2554, 0x2569, 0x2566, 0x2560, 0x2550, 0x256C, 0x00A4, + 0x043B, 0x041B, 0x043C, 0x041C, 0x043D, 0x041D, 0x043E, 0x041E, 0x043F, 0x2518, 0x250C, 0x2588, 0x2584, 0x041F, 0x044F, 0x2580, + 0x042F, 0x0440, 0x0420, 0x0441, 0x0421, 0x0442, 0x0422, 0x0443, 0x0423, 0x0436, 0x0416, 0x0432, 0x0412, 0x044C, 0x042C, 0x2116, + 0x00AD, 0x044B, 0x042B, 0x0437, 0x0417, 0x0448, 0x0428, 0x044D, 0x042D, 0x0449, 0x0429, 0x0447, 0x0427, 0x00A7, 0x25A0, 0x00A0 +}; +#endif +#if FF_CODE_PAGE == 857 || FF_CODE_PAGE == 0 +static const WCHAR uc857[] = { /* CP857(Turkish) to Unicode conversion table */ + 0x00C7, 0x00FC, 0x00E9, 0x00E2, 0x00E4, 0x00E0, 0x00E5, 0x00E7, 0x00EA, 0x00EB, 0x00E8, 0x00EF, 0x00EE, 0x0131, 0x00C4, 0x00C5, + 0x00C9, 0x00E6, 0x00C6, 0x00F4, 0x00F6, 0x00F2, 0x00FB, 0x00F9, 0x0130, 0x00D6, 0x00DC, 0x00F8, 0x00A3, 0x00D8, 0x015E, 0x015F, + 0x00E1, 0x00ED, 0x00F3, 0x00FA, 0x00F1, 0x00D1, 0x011E, 0x011F, 0x00BF, 0x00AE, 0x00AC, 0x00BD, 0x00BC, 0x00A1, 0x00AB, 0x00BB, + 0x2591, 0x2592, 0x2593, 0x2502, 0x2524, 0x00C1, 0x00C2, 0x00C0, 0x00A9, 0x2563, 0x2551, 0x2557, 0x255D, 0x00A2, 0x00A5, 0x2510, + 0x2514, 0x2534, 0x252C, 0x251C, 0x2500, 0x253C, 0x00E3, 0x00C3, 0x255A, 0x2554, 0x2569, 0x2566, 0x2560, 0x2550, 0x256C, 0x00A4, + 0x00BA, 0x00AA, 0x00CA, 0x00CB, 0x00C8, 0x0000, 0x00CD, 0x00CE, 0x00CF, 0x2518, 0x250C, 0x2588, 0x2584, 0x00A6, 0x00CC, 0x2580, + 0x00D3, 0x00DF, 0x00D4, 0x00D2, 0x00F5, 0x00D5, 0x00B5, 0x0000, 0x00D7, 0x00DA, 0x00DB, 0x00D9, 0x00EC, 0x00FF, 0x00AF, 0x00B4, + 0x00AD, 0x00B1, 0x0000, 0x00BE, 0x00B6, 0x00A7, 0x00F7, 0x00B8, 0x00B0, 0x00A8, 0x00B7, 0x00B9, 0x00B3, 0x00B2, 0x25A0, 0x00A0 +}; +#endif +#if FF_CODE_PAGE == 860 || FF_CODE_PAGE == 0 +static const WCHAR uc860[] = { /* CP860(Portuguese) to Unicode conversion table */ + 0x00C7, 0x00FC, 0x00E9, 0x00E2, 0x00E3, 0x00E0, 0x00C1, 0x00E7, 0x00EA, 0x00CA, 0x00E8, 0x00CD, 0x00D4, 0x00EC, 0x00C3, 0x00C2, + 0x00C9, 0x00C0, 0x00C8, 0x00F4, 0x00F5, 0x00F2, 0x00DA, 0x00F9, 0x00CC, 0x00D5, 0x00DC, 0x00A2, 0x00A3, 0x00D9, 0x20A7, 0x00D3, + 0x00E1, 0x00ED, 0x00F3, 0x00FA, 0x00F1, 0x00D1, 0x00AA, 0x00BA, 0x00BF, 0x00D2, 0x00AC, 0x00BD, 0x00BC, 0x00A1, 0x00AB, 0x00BB, + 0x2591, 0x2592, 0x2593, 0x2502, 0x2524, 0x2561, 0x2562, 0x2556, 0x2555, 0x2563, 0x2551, 0x2557, 0x255D, 0x255C, 0x2558, 0x2510, + 0x2514, 0x2534, 0x252C, 0x251C, 0x2500, 0x253C, 0x255E, 0x255F, 0x255A, 0x2554, 0x2569, 0x2566, 0x2560, 0x2550, 0x256C, 0x2567, + 0x2568, 0x2564, 0x2565, 0x2559, 0x2558, 0x2552, 0x2553, 0x256B, 0x256A, 0x2518, 0x250C, 0x2588, 0x2584, 0x258C, 0x2590, 0x2580, + 0x03B1, 0x00DF, 0x0393, 0x03C0, 0x03A3, 0x03C3, 0x00B5, 0x03C4, 0x03A6, 0x0398, 0x03A9, 0x03B4, 0x221E, 0x03C6, 0x03B5, 0x2229, + 0x2261, 0x00B1, 0x2265, 0x2264, 0x2320, 0x2321, 0x00F7, 0x2248, 0x00B0, 0x2219, 0x00B7, 0x221A, 0x207F, 0x00B2, 0x25A0, 0x00A0 +}; +#endif +#if FF_CODE_PAGE == 861 || FF_CODE_PAGE == 0 +static const WCHAR uc861[] = { /* CP861(Icelandic) to Unicode conversion table */ + 0x00C7, 0x00FC, 0x00E9, 0x00E2, 0x00E4, 0x00E0, 0x00E6, 0x00E7, 0x00EA, 0x00EB, 0x00E8, 0x00D0, 0x00F0, 0x00DE, 0x00C4, 0x00C5, + 0x00C9, 0x00E6, 0x00C6, 0x00F4, 0x00F6, 0x00FE, 0x00FB, 0x00DD, 0x00FD, 0x00D6, 0x00DC, 0x00F8, 0x00A3, 0x00D8, 0x20A7, 0x0192, + 0x00E1, 0x00ED, 0x00F3, 0x00FA, 0x00C1, 0x00CD, 0x00D3, 0x00DA, 0x00BF, 0x2310, 0x00AC, 0x00BD, 0x00BC, 0x00A1, 0x00AB, 0x00BB, + 0x2591, 0x2592, 0x2593, 0x2502, 0x2524, 0x2561, 0x2562, 0x2556, 0x2555, 0x2563, 0x2551, 0x2557, 0x255D, 0x255C, 0x255B, 0x2510, + 0x2514, 0x2534, 0x252C, 0x251C, 0x2500, 0x253C, 0x255E, 0x255F, 0x255A, 0x2554, 0x2569, 0x2566, 0x2560, 0x2550, 0x256C, 0x2567, + 0x2568, 0x2564, 0x2565, 0x2559, 0x2558, 0x2552, 0x2553, 0x256B, 0x256A, 0x2518, 0x250C, 0x2588, 0x2584, 0x258C, 0x2590, 0x2580, + 0x03B1, 0x00DF, 0x0393, 0x03C0, 0x03A3, 0x03C3, 0x00B5, 0x03C4, 0x03A6, 0x0398, 0x03A9, 0x03B4, 0x221E, 0x03C6, 0x03B5, 0x2229, + 0x2261, 0x00B1, 0x2265, 0x2264, 0x2320, 0x2321, 0x00F7, 0x2248, 0x00B0, 0x2219, 0x00B7, 0x221A, 0x207F, 0x00B2, 0x25A0, 0x00A0 +}; +#endif +#if FF_CODE_PAGE == 862 || FF_CODE_PAGE == 0 +static const WCHAR uc862[] = { /* CP862(Hebrew) to Unicode conversion table */ + 0x05D0, 0x05D1, 0x05D2, 0x05D3, 0x05D4, 0x05D5, 0x05D6, 0x05D7, 0x05D8, 0x05D9, 0x05DA, 0x05DB, 0x05DC, 0x05DD, 0x05DE, 0x05DF, + 0x05E0, 0x05E1, 0x05E2, 0x05E3, 0x05E4, 0x05E5, 0x05E6, 0x05E7, 0x05E8, 0x05E9, 0x05EA, 0x00A2, 0x00A3, 0x00A5, 0x20A7, 0x0192, + 0x00E1, 0x00ED, 0x00F3, 0x00FA, 0x00F1, 0x00D1, 0x00AA, 0x00BA, 0x00BF, 0x2310, 0x00AC, 0x00BD, 0x00BC, 0x00A1, 0x00AB, 0x00BB, + 0x2591, 0x2592, 0x2593, 0x2502, 0x2524, 0x2561, 0x2562, 0x2556, 0x2555, 0x2563, 0x2551, 0x2557, 0x255D, 0x255C, 0x255B, 0x2510, + 0x2514, 0x2534, 0x252C, 0x251C, 0x2500, 0x253C, 0x255E, 0x255F, 0x255A, 0x2554, 0x2569, 0x2566, 0x2560, 0x2550, 0x256C, 0x2567, + 0x2568, 0x2564, 0x2565, 0x2559, 0x2558, 0x2552, 0x2553, 0x256B, 0x256A, 0x2518, 0x250C, 0x2588, 0x2584, 0x258C, 0x2590, 0x2580, + 0x03B1, 0x00DF, 0x0393, 0x03C0, 0x03A3, 0x03C3, 0x00B5, 0x03C4, 0x03A6, 0x0398, 0x03A9, 0x03B4, 0x221E, 0x03C6, 0x03B5, 0x2229, + 0x2261, 0x00B1, 0x2265, 0x2264, 0x2320, 0x2321, 0x00F7, 0x2248, 0x00B0, 0x2219, 0x00B7, 0x221A, 0x207F, 0x00B2, 0x25A0, 0x00A0 +}; +#endif +#if FF_CODE_PAGE == 863 || FF_CODE_PAGE == 0 +static const WCHAR uc863[] = { /* CP863(Canadian French) to Unicode conversion table */ + 0x00C7, 0x00FC, 0x00E9, 0x00E2, 0x00C2, 0x00E0, 0x00B6, 0x00E7, 0x00EA, 0x00EB, 0x00E8, 0x00EF, 0x00EE, 0x00EC, 0x2017, 0x00C0, + 0x00C9, 0x00C8, 0x00CA, 0x00F4, 0x00CB, 0x00CF, 0x00FB, 0x00F9, 0x00A4, 0x00D4, 0x00DC, 0x00A2, 0x00A3, 0x00D9, 0x00DB, 0x0192, + 0x00A6, 0x00B4, 0x00F3, 0x00FA, 0x00A8, 0x00BB, 0x00B3, 0x00AF, 0x00CE, 0x3210, 0x00AC, 0x00BD, 0x00BC, 0x00BE, 0x00AB, 0x00BB, + 0x2591, 0x2592, 0x2593, 0x2502, 0x2524, 0x2561, 0x2562, 0x2556, 0x2555, 0x2563, 0x2551, 0x2557, 0x255D, 0x255C, 0x255B, 0x2510, + 0x2514, 0x2534, 0x252C, 0x251C, 0x2500, 0x253C, 0x255E, 0x255F, 0x255A, 0x2554, 0x2569, 0x2566, 0x2560, 0x2550, 0x256C, 0x2567, + 0x2568, 0x2564, 0x2565, 0x2559, 0x2558, 0x2552, 0x2553, 0x256B, 0x256A, 0x2518, 0x250C, 0x2588, 0x2584, 0x258C, 0x2590, 0x2580, + 0x03B1, 0x00DF, 0x0393, 0x03C0, 0x03A3, 0x03C3, 0x00B5, 0x03C4, 0x03A6, 0x0398, 0x03A9, 0x03B4, 0x221E, 0x03C6, 0x03B5, 0x2219, + 0x2261, 0x00B1, 0x2265, 0x2264, 0x2320, 0x2321, 0x00F7, 0x2248, 0x00B0, 0x2219, 0x00B7, 0x221A, 0x207F, 0x00B2, 0x25A0, 0x00A0 +}; +#endif +#if FF_CODE_PAGE == 864 || FF_CODE_PAGE == 0 +static const WCHAR uc864[] = { /* CP864(Arabic) to Unicode conversion table */ + 0x00B0, 0x00B7, 0x2219, 0x221A, 0x2592, 0x2500, 0x2502, 0x253C, 0x2524, 0x252C, 0x251C, 0x2534, 0x2510, 0x250C, 0x2514, 0x2518, + 0x03B2, 0x221E, 0x03C6, 0x00B1, 0x00BD, 0x00BC, 0x2248, 0x00AB, 0x00BB, 0xFEF7, 0xFEF8, 0x0000, 0x0000, 0xFEFB, 0xFEFC, 0x0000, + 0x00A0, 0x00AD, 0xFE82, 0x00A3, 0x00A4, 0xFE84, 0x0000, 0x20AC, 0xFE8E, 0xFE8F, 0xFE95, 0xFE99, 0x060C, 0xFE9D, 0xFEA1, 0xFEA5, + 0x0660, 0x0661, 0x0662, 0x0663, 0x0664, 0x0665, 0x0666, 0x0667, 0x0668, 0x0669, 0xFED1, 0x061B, 0xFEB1, 0xFEB5, 0xFEB9, 0x061F, + 0x00A2, 0xFE80, 0xFE81, 0xFE83, 0xFE85, 0xFECA, 0xFE8B, 0xFE8D, 0xFE91, 0xFE93, 0xFE97, 0xFE9B, 0xFE9F, 0xFEA3, 0xFEA7, 0xFEA9, + 0xFEAB, 0xFEAD, 0xFEAF, 0xFEB3, 0xFEB7, 0xFEBB, 0xFEBF, 0xFEC1, 0xFEC5, 0xFECB, 0xFECF, 0x00A6, 0x00AC, 0x00F7, 0x00D7, 0xFEC9, + 0x0640, 0xFED3, 0xFED7, 0xFEDB, 0xFEDF, 0xFEE3, 0xFEE7, 0xFEEB, 0xFEED, 0xFEEF, 0xFEF3, 0xFEBD, 0xFECC, 0xFECE, 0xFECD, 0xFEE1, + 0xFE7D, 0x0651, 0xFEE5, 0xFEE9, 0xFEEC, 0xFEF0, 0xFEF2, 0xFED0, 0xFED5, 0xFEF5, 0xFEF6, 0xFEDD, 0xFED9, 0xFEF1, 0x25A0, 0x0000 +}; +#endif +#if FF_CODE_PAGE == 865 || FF_CODE_PAGE == 0 +static const WCHAR uc865[] = { /* CP865(Nordic) to Unicode conversion table */ + 0x00C7, 0x00FC, 0x00E9, 0x00E2, 0x00E4, 0x00E0, 0x00E5, 0x00E7, 0x00EA, 0x00EB, 0x00E8, 0x00EF, 0x00EE, 0x00EC, 0x00C4, 0x00C5, + 0x00C5, 0x00E6, 0x00C6, 0x00F4, 0x00F6, 0x00F2, 0x00FB, 0x00F9, 0x00FF, 0x00D6, 0x00DC, 0x00F8, 0x00A3, 0x00D8, 0x20A7, 0x0192, + 0x00E1, 0x00ED, 0x00F3, 0x00FA, 0x00F1, 0x00D1, 0x00AA, 0x00BA, 0x00BF, 0x2310, 0x00AC, 0x00BD, 0x00BC, 0x00A1, 0x00AB, 0x00A4, + 0x2591, 0x2592, 0x2593, 0x2502, 0x2524, 0x2561, 0x2562, 0x2556, 0x2555, 0x2563, 0x2551, 0x2557, 0x255D, 0x255C, 0x2558, 0x2510, + 0x2514, 0x2534, 0x252C, 0x251C, 0x2500, 0x253C, 0x255E, 0x255F, 0x255A, 0x2554, 0x2569, 0x2566, 0x2560, 0x2550, 0x256C, 0x2567, + 0x2568, 0x2564, 0x2565, 0x2559, 0x2558, 0x2552, 0x2553, 0x256B, 0x256A, 0x2518, 0x250C, 0x2588, 0x2584, 0x258C, 0x2590, 0x2580, + 0x03B1, 0x00DF, 0x0393, 0x03C0, 0x03A3, 0x03C3, 0x00B5, 0x03C4, 0x03A6, 0x0398, 0x03A9, 0x03B4, 0x221E, 0x03C6, 0x03B5, 0x2229, + 0x2261, 0x00B1, 0x2265, 0x2264, 0x2320, 0x2321, 0x00F7, 0x2248, 0x00B0, 0x2219, 0x00B7, 0x221A, 0x207F, 0x00B2, 0x25A0, 0x00A0 +}; +#endif +#if FF_CODE_PAGE == 866 || FF_CODE_PAGE == 0 +static const WCHAR uc866[] = { /* CP866(Russian) to Unicode conversion table */ + 0x0410, 0x0411, 0x0412, 0x0413, 0x0414, 0x0415, 0x0416, 0x0417, 0x0418, 0x0419, 0x041A, 0x041B, 0x041C, 0x041D, 0x041E, 0x041F, + 0x0420, 0x0421, 0x0422, 0x0423, 0x0424, 0x0425, 0x0426, 0x0427, 0x0428, 0x0429, 0x042A, 0x042B, 0x042C, 0x042D, 0x042E, 0x042F, + 0x0430, 0x0431, 0x0432, 0x0433, 0x0434, 0x0435, 0x0436, 0x0437, 0x0438, 0x0439, 0x043A, 0x043B, 0x043C, 0x043D, 0x043E, 0x043F, + 0x2591, 0x2592, 0x2593, 0x2502, 0x2524, 0x2561, 0x2562, 0x2556, 0x2555, 0x2563, 0x2551, 0x2557, 0x255D, 0x255C, 0x255B, 0x2510, + 0x2514, 0x2534, 0x252C, 0x251C, 0x2500, 0x253C, 0x255E, 0x255F, 0x255A, 0x2554, 0x2569, 0x2566, 0x2560, 0x2550, 0x256C, 0x2567, + 0x2568, 0x2564, 0x2565, 0x2559, 0x2558, 0x2552, 0x2553, 0x256B, 0x256A, 0x2518, 0x250C, 0x2588, 0x2584, 0x258C, 0x2590, 0x2580, + 0x0440, 0x0441, 0x0442, 0x0443, 0x0444, 0x0445, 0x0446, 0x0447, 0x0448, 0x0449, 0x044A, 0x044B, 0x044C, 0x044D, 0x044E, 0x044F, + 0x0401, 0x0451, 0x0404, 0x0454, 0x0407, 0x0457, 0x040E, 0x045E, 0x00B0, 0x2219, 0x00B7, 0x221A, 0x2116, 0x00A4, 0x25A0, 0x00A0 +}; +#endif +#if FF_CODE_PAGE == 869 || FF_CODE_PAGE == 0 +static const WCHAR uc869[] = { /* CP869(Greek 2) to Unicode conversion table */ + 0x00B7, 0x00B7, 0x00B7, 0x00B7, 0x00B7, 0x00B7, 0x0386, 0x00B7, 0x00B7, 0x00AC, 0x00A6, 0x2018, 0x2019, 0x0388, 0x2015, 0x0389, + 0x038A, 0x03AA, 0x038C, 0x00B7, 0x00B7, 0x038E, 0x03AB, 0x00A9, 0x038F, 0x00B2, 0x00B3, 0x03AC, 0x00A3, 0x03AD, 0x03AE, 0x03AF, + 0x03CA, 0x0390, 0x03CC, 0x03CD, 0x0391, 0x0392, 0x0393, 0x0394, 0x0395, 0x0396, 0x0397, 0x00BD, 0x0398, 0x0399, 0x00AB, 0x00BB, + 0x2591, 0x2592, 0x2593, 0x2502, 0x2524, 0x039A, 0x039B, 0x039C, 0x039D, 0x2563, 0x2551, 0x2557, 0x255D, 0x039E, 0x039F, 0x2510, + 0x2514, 0x2534, 0x252C, 0x251C, 0x2500, 0x253C, 0x0A30, 0x03A1, 0x255A, 0x2554, 0x2569, 0x2566, 0x2560, 0x2550, 0x256C, 0x03A3, + 0x03A4, 0x03A5, 0x03A6, 0x03A7, 0x03A8, 0x03A9, 0x03B1, 0x03B2, 0x03B3, 0x2518, 0x250C, 0x2588, 0x2584, 0x03B4, 0x03B5, 0x2580, + 0x03B6, 0x03B7, 0x03B8, 0x03B9, 0x03BA, 0x03BB, 0x03BC, 0x03BD, 0x03BE, 0x03BF, 0x03C0, 0x03C1, 0x03C3, 0x03C2, 0x03C4, 0x0384, + 0x00AD, 0x00B1, 0x03C5, 0x03C6, 0x03C7, 0x00A7, 0x03C8, 0x0385, 0x00B0, 0x00A8, 0x03C9, 0x03CB, 0x03B0, 0x03CE, 0x25A0, 0x00A0 +}; +#endif + + + + +/*------------------------------------------------------------------------*/ +/* OEM <==> Unicode conversions for static code page configuration */ +/* SBCS fixed code page */ +/*------------------------------------------------------------------------*/ + +#if FF_CODE_PAGE != 0 && FF_CODE_PAGE < 900 +WCHAR ff_uni2oem ( /* Returns OEM code character, zero on error */ + DWORD uni, /* UTF-16 encoded character to be converted */ + WORD cp /* Code page for the conversion */ +) +{ + WCHAR c = 0; + const WCHAR *p = CVTBL(uc, FF_CODE_PAGE); + + + if (uni < 0x80) { /* ASCII? */ + c = (WCHAR)uni; + + } else { /* Non-ASCII */ + if (uni < 0x10000 && cp == FF_CODE_PAGE) { /* Is it in BMP and valid code page? */ + for (c = 0; c < 0x80 && uni != p[c]; c++) ; + c = (c + 0x80) & 0xFF; + } + } + + return c; +} + +WCHAR ff_oem2uni ( /* Returns Unicode character in UTF-16, zero on error */ + WCHAR oem, /* OEM code to be converted */ + WORD cp /* Code page for the conversion */ +) +{ + WCHAR c = 0; + const WCHAR *p = CVTBL(uc, FF_CODE_PAGE); + + + if (oem < 0x80) { /* ASCII? */ + c = oem; + + } else { /* Extended char */ + if (cp == FF_CODE_PAGE) { /* Is it a valid code page? */ + if (oem < 0x100) c = p[oem - 0x80]; + } + } + + return c; +} + +#endif + + + +/*------------------------------------------------------------------------*/ +/* OEM <==> Unicode conversions for static code page configuration */ +/* DBCS fixed code page */ +/*------------------------------------------------------------------------*/ + +#if FF_CODE_PAGE >= 900 +WCHAR ff_uni2oem ( /* Returns OEM code character, zero on error */ + DWORD uni, /* UTF-16 encoded character to be converted */ + WORD cp /* Code page for the conversion */ +) +{ + const WCHAR *p; + WCHAR c = 0, uc; + UINT i = 0, n, li, hi; + + + if (uni < 0x80) { /* ASCII? */ + c = (WCHAR)uni; + + } else { /* Non-ASCII */ + if (uni < 0x10000 && cp == FF_CODE_PAGE) { /* Is it in BMP and valid code page? */ + uc = (WCHAR)uni; + p = CVTBL(uni2oem, FF_CODE_PAGE); + hi = sizeof CVTBL(uni2oem, FF_CODE_PAGE) / 4 - 1; + li = 0; + for (n = 16; n; n--) { + i = li + (hi - li) / 2; + if (uc == p[i * 2]) break; + if (uc > p[i * 2]) { + li = i; + } else { + hi = i; + } + } + if (n != 0) c = p[i * 2 + 1]; + } + } + + return c; +} + + +WCHAR ff_oem2uni ( /* Returns Unicode character in UTF-16, zero on error */ + WCHAR oem, /* OEM code to be converted */ + WORD cp /* Code page for the conversion */ +) +{ + const WCHAR *p; + WCHAR c = 0; + UINT i = 0, n, li, hi; + + + if (oem < 0x80) { /* ASCII? */ + c = oem; + + } else { /* Extended char */ + if (cp == FF_CODE_PAGE) { /* Is it valid code page? */ + p = CVTBL(oem2uni, FF_CODE_PAGE); + hi = sizeof CVTBL(oem2uni, FF_CODE_PAGE) / 4 - 1; + li = 0; + for (n = 16; n; n--) { + i = li + (hi - li) / 2; + if (oem == p[i * 2]) break; + if (oem > p[i * 2]) { + li = i; + } else { + hi = i; + } + } + if (n != 0) c = p[i * 2 + 1]; + } + } + + return c; +} +#endif + + + +/*------------------------------------------------------------------------*/ +/* OEM <==> Unicode conversions for dynamic code page configuration */ +/*------------------------------------------------------------------------*/ + +#if FF_CODE_PAGE == 0 + +static const WORD cp_code[] = { 437, 720, 737, 771, 775, 850, 852, 855, 857, 860, 861, 862, 863, 864, 865, 866, 869, 0}; +static const WCHAR* const cp_table[] = {uc437, uc720, uc737, uc771, uc775, uc850, uc852, uc855, uc857, uc860, uc861, uc862, uc863, uc864, uc865, uc866, uc869, 0}; + + +WCHAR ff_uni2oem ( /* Returns OEM code character, zero on error */ + DWORD uni, /* UTF-16 encoded character to be converted */ + WORD cp /* Code page for the conversion */ +) +{ + const WCHAR *p; + WCHAR c = 0, uc; + UINT i, n, li, hi; + + + if (uni < 0x80) { /* ASCII? */ + c = (WCHAR)uni; + + } else { /* Non-ASCII */ + if (uni < 0x10000) { /* Is it in BMP? */ + uc = (WCHAR)uni; + p = 0; + if (cp < 900) { /* SBCS */ + for (i = 0; cp_code[i] != 0 && cp_code[i] != cp; i++) ; /* Get conversion table */ + p = cp_table[i]; + if (p) { /* Is it valid code page ? */ + for (c = 0; c < 0x80 && uc != p[c]; c++) ; /* Find OEM code in the table */ + c = (c + 0x80) & 0xFF; + } + } else { /* DBCS */ + switch (cp) { /* Get conversion table */ + case 932 : p = uni2oem932; hi = sizeof uni2oem932 / 4 - 1; break; + case 936 : p = uni2oem936; hi = sizeof uni2oem936 / 4 - 1; break; + case 949 : p = uni2oem949; hi = sizeof uni2oem949 / 4 - 1; break; + case 950 : p = uni2oem950; hi = sizeof uni2oem950 / 4 - 1; break; + } + if (p) { /* Is it valid code page? */ + li = 0; + for (n = 16; n; n--) { /* Find OEM code */ + i = li + (hi - li) / 2; + if (uc == p[i * 2]) break; + if (uc > p[i * 2]) { + li = i; + } else { + hi = i; + } + } + if (n != 0) c = p[i * 2 + 1]; + } + } + } + } + + return c; +} + + +WCHAR ff_oem2uni ( /* Returns Unicode character in UTF-16, zero on error */ + WCHAR oem, /* OEM code to be converted (DBC if >=0x100) */ + WORD cp /* Code page for the conversion */ +) +{ + const WCHAR *p; + WCHAR c = 0; + UINT i, n, li, hi; + + + if (oem < 0x80) { /* ASCII? */ + c = oem; + + } else { /* Extended char */ + p = 0; + if (cp < 900) { /* SBCS */ + for (i = 0; cp_code[i] != 0 && cp_code[i] != cp; i++) ; /* Get table */ + p = cp_table[i]; + if (p) { /* Is it a valid CP ? */ + if (oem < 0x100) c = p[oem - 0x80]; + } + } else { /* DBCS */ + switch (cp) { + case 932 : p = oem2uni932; hi = sizeof oem2uni932 / 4 - 1; break; + case 936 : p = oem2uni936; hi = sizeof oem2uni936 / 4 - 1; break; + case 949 : p = oem2uni949; hi = sizeof oem2uni949 / 4 - 1; break; + case 950 : p = oem2uni950; hi = sizeof oem2uni950 / 4 - 1; break; + } + if (p) { + li = 0; + for (n = 16; n; n--) { + i = li + (hi - li) / 2; + if (oem == p[i * 2]) break; + if (oem > p[i * 2]) { + li = i; + } else { + hi = i; + } + } + if (n != 0) c = p[i * 2 + 1]; + } + } + } + + return c; +} +#endif + + + +/*------------------------------------------------------------------------*/ +/* Unicode up-case conversion */ +/*------------------------------------------------------------------------*/ + +DWORD ff_wtoupper ( /* Returns up-converted code point */ + DWORD uni /* Unicode code point to be up-converted */ +) +{ + const WORD *p; + WORD uc, bc, nc, cmd; + static const WORD cvt1[] = { /* Compressed up conversion table for U+0000 - U+0FFF */ + /* Basic Latin */ + 0x0061,0x031A, + /* Latin-1 Supplement */ + 0x00E0,0x0317, + 0x00F8,0x0307, + 0x00FF,0x0001,0x0178, + /* Latin Extended-A */ + 0x0100,0x0130, + 0x0132,0x0106, + 0x0139,0x0110, + 0x014A,0x012E, + 0x0179,0x0106, + /* Latin Extended-B */ + 0x0180,0x004D,0x0243,0x0181,0x0182,0x0182,0x0184,0x0184,0x0186,0x0187,0x0187,0x0189,0x018A,0x018B,0x018B,0x018D,0x018E,0x018F,0x0190,0x0191,0x0191,0x0193,0x0194,0x01F6,0x0196,0x0197,0x0198,0x0198,0x023D,0x019B,0x019C,0x019D,0x0220,0x019F,0x01A0,0x01A0,0x01A2,0x01A2,0x01A4,0x01A4,0x01A6,0x01A7,0x01A7,0x01A9,0x01AA,0x01AB,0x01AC,0x01AC,0x01AE,0x01AF,0x01AF,0x01B1,0x01B2,0x01B3,0x01B3,0x01B5,0x01B5,0x01B7,0x01B8,0x01B8,0x01BA,0x01BB,0x01BC,0x01BC,0x01BE,0x01F7,0x01C0,0x01C1,0x01C2,0x01C3,0x01C4,0x01C5,0x01C4,0x01C7,0x01C8,0x01C7,0x01CA,0x01CB,0x01CA, + 0x01CD,0x0110, + 0x01DD,0x0001,0x018E, + 0x01DE,0x0112, + 0x01F3,0x0003,0x01F1,0x01F4,0x01F4, + 0x01F8,0x0128, + 0x0222,0x0112, + 0x023A,0x0009,0x2C65,0x023B,0x023B,0x023D,0x2C66,0x023F,0x0240,0x0241,0x0241, + 0x0246,0x010A, + /* IPA Extensions */ + 0x0253,0x0040,0x0181,0x0186,0x0255,0x0189,0x018A,0x0258,0x018F,0x025A,0x0190,0x025C,0x025D,0x025E,0x025F,0x0193,0x0261,0x0262,0x0194,0x0264,0x0265,0x0266,0x0267,0x0197,0x0196,0x026A,0x2C62,0x026C,0x026D,0x026E,0x019C,0x0270,0x0271,0x019D,0x0273,0x0274,0x019F,0x0276,0x0277,0x0278,0x0279,0x027A,0x027B,0x027C,0x2C64,0x027E,0x027F,0x01A6,0x0281,0x0282,0x01A9,0x0284,0x0285,0x0286,0x0287,0x01AE,0x0244,0x01B1,0x01B2,0x0245,0x028D,0x028E,0x028F,0x0290,0x0291,0x01B7, + /* Greek, Coptic */ + 0x037B,0x0003,0x03FD,0x03FE,0x03FF, + 0x03AC,0x0004,0x0386,0x0388,0x0389,0x038A, + 0x03B1,0x0311, + 0x03C2,0x0002,0x03A3,0x03A3, + 0x03C4,0x0308, + 0x03CC,0x0003,0x038C,0x038E,0x038F, + 0x03D8,0x0118, + 0x03F2,0x000A,0x03F9,0x03F3,0x03F4,0x03F5,0x03F6,0x03F7,0x03F7,0x03F9,0x03FA,0x03FA, + /* Cyrillic */ + 0x0430,0x0320, + 0x0450,0x0710, + 0x0460,0x0122, + 0x048A,0x0136, + 0x04C1,0x010E, + 0x04CF,0x0001,0x04C0, + 0x04D0,0x0144, + /* Armenian */ + 0x0561,0x0426, + + 0x0000 /* EOT */ + }; + static const WORD cvt2[] = { /* Compressed up conversion table for U+1000 - U+FFFF */ + /* Phonetic Extensions */ + 0x1D7D,0x0001,0x2C63, + /* Latin Extended Additional */ + 0x1E00,0x0196, + 0x1EA0,0x015A, + /* Greek Extended */ + 0x1F00,0x0608, + 0x1F10,0x0606, + 0x1F20,0x0608, + 0x1F30,0x0608, + 0x1F40,0x0606, + 0x1F51,0x0007,0x1F59,0x1F52,0x1F5B,0x1F54,0x1F5D,0x1F56,0x1F5F, + 0x1F60,0x0608, + 0x1F70,0x000E,0x1FBA,0x1FBB,0x1FC8,0x1FC9,0x1FCA,0x1FCB,0x1FDA,0x1FDB,0x1FF8,0x1FF9,0x1FEA,0x1FEB,0x1FFA,0x1FFB, + 0x1F80,0x0608, + 0x1F90,0x0608, + 0x1FA0,0x0608, + 0x1FB0,0x0004,0x1FB8,0x1FB9,0x1FB2,0x1FBC, + 0x1FCC,0x0001,0x1FC3, + 0x1FD0,0x0602, + 0x1FE0,0x0602, + 0x1FE5,0x0001,0x1FEC, + 0x1FF3,0x0001,0x1FFC, + /* Letterlike Symbols */ + 0x214E,0x0001,0x2132, + /* Number forms */ + 0x2170,0x0210, + 0x2184,0x0001,0x2183, + /* Enclosed Alphanumerics */ + 0x24D0,0x051A, + 0x2C30,0x042F, + /* Latin Extended-C */ + 0x2C60,0x0102, + 0x2C67,0x0106, 0x2C75,0x0102, + /* Coptic */ + 0x2C80,0x0164, + /* Georgian Supplement */ + 0x2D00,0x0826, + /* Full-width */ + 0xFF41,0x031A, + + 0x0000 /* EOT */ + }; + + + if (uni < 0x10000) { /* Is it in BMP? */ + uc = (WORD)uni; + p = uc < 0x1000 ? cvt1 : cvt2; + for (;;) { + bc = *p++; /* Get the block base */ + if (bc == 0 || uc < bc) break; /* Not matched? */ + nc = *p++; cmd = nc >> 8; nc &= 0xFF; /* Get processing command and block size */ + if (uc < bc + nc) { /* In the block? */ + switch (cmd) { + case 0: uc = p[uc - bc]; break; /* Table conversion */ + case 1: uc -= (uc - bc) & 1; break; /* Case pairs */ + case 2: uc -= 16; break; /* Shift -16 */ + case 3: uc -= 32; break; /* Shift -32 */ + case 4: uc -= 48; break; /* Shift -48 */ + case 5: uc -= 26; break; /* Shift -26 */ + case 6: uc += 8; break; /* Shift +8 */ + case 7: uc -= 80; break; /* Shift -80 */ + case 8: uc -= 0x1C60; break; /* Shift -0x1C60 */ + } + break; + } + if (cmd == 0) p += nc; /* Skip table if needed */ + } + uni = uc; + } + + return uni; +} + + +#endif /* #if FF_USE_LFN */ diff --git a/kernel/ff_partitions.c b/kernel/ff_partitions.c new file mode 100644 index 0000000..7bebdae --- /dev/null +++ b/kernel/ff_partitions.c @@ -0,0 +1,4 @@ +#include "ff.h" +#if FF_MULTI_PARTITION +PARTITION VolToPart[FF_VOLUMES] = { {0,1}, {0,2}, {1,0}, {2,0}, {3,0}, {4,0}, {5,0}, {6,0}, {7,0}, {8,0} }; +#endif diff --git a/kernel/ffsystem_impl.c b/kernel/ffsystem_impl.c new file mode 100644 index 0000000..973a6d1 --- /dev/null +++ b/kernel/ffsystem_impl.c @@ -0,0 +1,6 @@ +#include "ff.h" +#include +extern void* malloc(size_t s); extern void free(void* p); +void* ff_memalloc(UINT m) { return malloc((size_t)m); } +void ff_memfree(void* m) { free(m); } +DWORD get_fattime(void) { return 0; } diff --git a/kernel/idt.c b/kernel/idt.c new file mode 100644 index 0000000..391ede0 --- /dev/null +++ b/kernel/idt.c @@ -0,0 +1,26 @@ +#include "idt.h" +#include +static struct idt_entry idt[256]; static struct idtr idtr; +#define ISR_EXT(n) extern void isr##n##_stub(void); +ISR_EXT(0) ISR_EXT(1) ISR_EXT(2) ISR_EXT(3) ISR_EXT(4) ISR_EXT(5) ISR_EXT(6) ISR_EXT(7) +ISR_EXT(8) ISR_EXT(9) ISR_EXT(10) ISR_EXT(11) ISR_EXT(12) ISR_EXT(13) ISR_EXT(14) ISR_EXT(15) +ISR_EXT(16) ISR_EXT(17) ISR_EXT(18) ISR_EXT(19) ISR_EXT(20) ISR_EXT(21) ISR_EXT(22) ISR_EXT(23) +ISR_EXT(24) ISR_EXT(25) ISR_EXT(26) ISR_EXT(27) ISR_EXT(28) ISR_EXT(29) ISR_EXT(30) ISR_EXT(31) +static void idt_set(uint8_t v, void* isr) { + struct idt_entry* e = &idt[v]; uint64_t a = (uint64_t)isr; + e->isr_low = a & 0xFFFF; e->kernel_cs = 0x08; e->ist = 0; e->attributes = 0x8E; + e->isr_mid = (a >> 16) & 0xFFFF; e->isr_high = (a >> 32) & 0xFFFFFFFF; e->reserved = 0; +} +void idt_init(void) { + memset(idt, 0, sizeof(idt)); + idt_set(0, isr0_stub); idt_set(1, isr1_stub); idt_set(2, isr2_stub); idt_set(3, isr3_stub); + idt_set(4, isr4_stub); idt_set(5, isr5_stub); idt_set(6, isr6_stub); idt_set(7, isr7_stub); + idt_set(8, isr8_stub); idt_set(9, isr9_stub); idt_set(10, isr10_stub); idt_set(11, isr11_stub); + idt_set(12, isr12_stub); idt_set(13, isr13_stub); idt_set(14, isr14_stub); idt_set(15, isr15_stub); + idt_set(16, isr16_stub); idt_set(17, isr17_stub); idt_set(18, isr18_stub); idt_set(19, isr19_stub); + idt_set(20, isr20_stub); idt_set(21, isr21_stub); idt_set(22, isr22_stub); idt_set(23, isr23_stub); + idt_set(24, isr24_stub); idt_set(25, isr25_stub); idt_set(26, isr26_stub); idt_set(27, isr27_stub); + idt_set(28, isr28_stub); idt_set(29, isr29_stub); idt_set(30, isr30_stub); idt_set(31, isr31_stub); + idtr.limit = sizeof(idt)-1; idtr.base = (uint64_t)&idt; + __asm__ volatile ("lidt %0" : : "m"(idtr)); +} diff --git a/kernel/kernel.c b/kernel/kernel.c index 0b81b3e..e273411 100644 --- a/kernel/kernel.c +++ b/kernel/kernel.c @@ -1,101 +1,137 @@ #include #include #include +#include "drivers/font_8x8.h" #include "pro_os.h" #include "limine.h" #include "app_ui.h" #include "nk_software_renderer.h" +#include "serial.h" +#include "pmm.h" +#include "idt.h" + +// --- Sovereign 4-Stage Boot Architecture --- +typedef enum { STAGE_1_PRIMING=1, STAGE_2_MULTITASKING=2, STAGE_3_USB=3, STAGE_4_USER=4 } boot_stage_t; +static boot_stage_t current_stage = STAGE_1_PRIMING; + +volatile struct limine_framebuffer_request framebuffer_request = { .id = LIMINE_FRAMEBUFFER_REQUEST, .revision = 0 }; + +struct panic_framebuffer { uint64_t address; uint64_t width; uint64_t height; uint64_t pitch; }; +static struct panic_framebuffer pfb; +struct panic_framebuffer* get_kernel_framebuffer(void) { + if (framebuffer_request.response && framebuffer_request.response->framebuffer_count > 0) { + struct limine_framebuffer *fb = framebuffer_request.response->framebuffers[0]; + pfb.address = (uintptr_t)fb->address; + pfb.width = fb->width; + pfb.height = fb->height; + pfb.pitch = fb->pitch; + return &pfb; + } + return NULL; +} -// Tell the bootloader we want a graphical framebuffer -volatile struct limine_framebuffer_request framebuffer_request = { - .id = LIMINE_FRAMEBUFFER_REQUEST, - .revision = 0 -}; - -static volatile struct limine_hhdm_request hhdm_request = { - .id = LIMINE_HHDM_REQUEST, - .revision = 0 -}; - +static volatile struct limine_hhdm_request hhdm_request = { .id = LIMINE_HHDM_REQUEST, .revision = 0 }; +static volatile struct limine_memmap_request memmap_request = { .id = LIMINE_MEMMAP_REQUEST, .revision = 0 }; +static volatile struct limine_rsdp_request rsdp_request = { .id = LIMINE_RSDP_REQUEST, .revision = 0 }; uint64_t hhdm_offset = 0; -static float font_get_width(nk_handle handle, float height, const char *text, int len) { - (void)handle; (void)height; (void)text; - return (float)len * 8.0f; -} +static float font_get_width(nk_handle handle, float height, const char *text, int len) { (void)handle; (void)height; (void)text; return (float)len * 8.0f; } +static void* nk_malloc(nk_handle handle, void* old, nk_size size) { (void)handle; return old ? realloc(old, size) : malloc(size); } +static void nk_mfree(nk_handle handle, void* ptr) { (void)handle; free(ptr); } -// The true, freestanding entry point void kernel_main(void) { - // 1. Initial Proof of Life & Check Blindness - if (framebuffer_request.response == NULL || framebuffer_request.response->framebuffer_count < 1) { - while (1) { __asm__("hlt"); } - } + // STAGE 1: SYSTEM PRIMING (Interrupts DISABLED) + serial_init(); + serial_write("[STAGE 1] System Priming (Step 1-7)...\n"); - if (hhdm_request.response != NULL) { - hhdm_offset = hhdm_request.response->offset; - } + if (hhdm_request.response) hhdm_offset = hhdm_request.response->offset; + if (memmap_request.response) pmm_init(memmap_request.response); + if (rsdp_request.response) acpi_init(rsdp_request.response->address); - struct limine_framebuffer *fb = framebuffer_request.response->framebuffers[0]; - tgx_canvas_t canvas = { (uint32_t*)fb->address, fb->width, fb->height, fb->pitch }; + extern void init_gdt(void); init_gdt(); + idt_init(); + + if (!framebuffer_request.response || framebuffer_request.response->framebuffer_count < 1) { + serial_write("[ERROR] No Graphical Framebuffer\n"); while(1) __asm__("hlt"); + } - // 2. System Bootstrap - // Allocate 16MB for the kernel heap static uint8_t kernel_heap[16 * 1024 * 1024]; hal_malloc_init(kernel_heap, sizeof(kernel_heap)); - hal_storage_init(); + extern void rsl_init(void); rsl_init(); hal_input_init(); + + // STAGE 2: MULTITASKING & BUS RUNTIMES (Interrupts ENABLED) + current_stage = STAGE_2_MULTITASKING; + serial_write("[STAGE 2] Runtime Start (Step 8-11)...\n"); + __asm__ volatile("sti"); + scheduler_init(); vfs_init(); + extern void pci_scan(void); pci_scan(); + vfs_refresh_mounts(); + + // STAGE 3: USB SUBSYSTEM (Step 12-15) + current_stage = STAGE_3_USB; + serial_write("[STAGE 3] USB Subsystem Activation...\n"); + scheduler_add_task("USB Poller", hal_usb_poll); hal_usb_init(); - // 3. UI Initialization - struct nk_context ctx; - struct nk_user_font font; - font.userdata = nk_handle_ptr(0); - font.height = 8.0f; - font.width = font_get_width; + // STAGE 4: USER SPACE & GUI (Step 16-18) + current_stage = STAGE_4_USER; + serial_write("[STAGE 4] Launching User Space UI...\n"); - nk_init_default(&ctx, &font); + struct nk_context ctx; struct nk_user_font font; + font.userdata = nk_handle_ptr(0); font.height = 8.0f; font.width = font_get_width; + struct nk_allocator alloc = { .alloc = nk_malloc, .free = nk_mfree }; + nk_init(&ctx, &alloc, &font); ui_init_style(&ctx); - struct app_state app; - memset(&app, 0, sizeof(app)); + struct app_state app; memset(&app, 0, sizeof(app)); app.current_state = STATE_LOGIN; + chell_init(&app.chell); lab_init(&app.lab); installer_init(&app.installer); - int cursor_x = fb->width / 2; - int cursor_y = fb->height / 2; + struct limine_framebuffer *fb = framebuffer_request.response->framebuffers[0]; + tgx_canvas_t canvas = { (uint32_t*)fb->address, fb->width, fb->height, fb->pitch }; + int cx = fb->width / 2, cy = fb->height / 2; - // 4. Main Executive Loop while (1) { - tgx_clear(&canvas, 0x001010); // Dark Teal Background - hal_usb_poll(); - - input_event_t ev; + tgx_clear(&canvas, 0x001010); nk_input_begin(&ctx); + input_event_t ev; while (hal_input_pop_event(&ev)) { if (ev.type == INPUT_TYPE_MOUSE) { - cursor_x = ev.mouse.x; - cursor_y = ev.mouse.y; - nk_input_motion(&ctx, cursor_x, cursor_y); - nk_input_button(&ctx, NK_BUTTON_LEFT, cursor_x, cursor_y, (ev.mouse.buttons & 1)); + cx += ev.mouse.x; cy += ev.mouse.y; + if (cx < 0) cx = 0; + if (cy < 0) cy = 0; + if (cx >= (int)fb->width) cx = fb->width-1; + if (cy >= (int)fb->height) cy = fb->height-1; + nk_input_motion(&ctx, cx, cy); + nk_input_button(&ctx, NK_BUTTON_LEFT, cx, cy, (ev.mouse.buttons & 1)); + } else if (ev.type == INPUT_TYPE_KEYBOARD && ev.kbd.down) { + char c = 0; + if (ev.kbd.key >= 0x04 && ev.kbd.key <= 0x1D) c = 'a' + (ev.kbd.key - 0x04); + else if (ev.kbd.key == 0x28) c = '\n'; + if (c) nk_input_char(&ctx, c); } } nk_input_end(&ctx); - - // Run the scheduler to handle background tasks scheduler_run(); - - ui_render(&ctx, &app, fb->width, fb->height); - + ui_render(&ctx, &app, (int)fb->width, (int)fb->height); struct nk_sw_fb sw_fb = { fb->address, fb->width, fb->height, fb->pitch }; nk_sw_render(&sw_fb, &ctx); - // Draw Hardware Cursor - tgx_blit_rect(&canvas, cursor_x, cursor_y, 4, 4, 0xFFFFFF); + // Upgrade cursor to Arrow (simulated with primitive) + for(int r=0; r<8; r++) { uint8_t bits = cursor_arrow[r*2]; for(int b=0; b<8; b++) { if(bits & (0x80>>b)) tgx_blit_rect(&canvas, cx+b, cy+r, 1, 1, 0x00FFFF); } } - // Logical flow delay using scheduler-aware mechanics - // In a real system, we'd wait for a timer interrupt here. __asm__("pause"); } } + +// Minimal GDT Helper +struct gdt_ptr { uint16_t limit; uint64_t base; } __attribute__((packed)); +static uint64_t gdt_raw[3] = { 0, 0x00AF9A000000FFFF, 0x00CF92000000FFFF }; +void init_gdt(void) { + static struct gdt_ptr gp; gp.limit = sizeof(gdt_raw)-1; gp.base = (uint64_t)&gdt_raw; + __asm__ volatile("lgdt %0\n\tpush $0x08\n\tlea 1f(%%rip), %%rax\n\tpush %%rax\n\tlretq\n\t1:\n\tmov $0x10, %%ax\n\tmov %%ax, %%ds\n\tmov %%ax, %%es\n\tmov %%ax, %%fs\n\tmov %%ax, %%gs\n\tmov %%ax, %%ss" : : "m"(gp) : "rax", "memory"); +} diff --git a/kernel/limine.cfg b/kernel/limine.cfg new file mode 100644 index 0000000..d70b885 --- /dev/null +++ b/kernel/limine.cfg @@ -0,0 +1,4 @@ +TIMEOUT=3 +:Sovereign OS +PROTOCOL=limine +KERNEL_PATH=boot:///boot/kernel.elf diff --git a/kernel/malloc_glue.c b/kernel/malloc_glue.c index 7ccbec8..12d255e 100644 --- a/kernel/malloc_glue.c +++ b/kernel/malloc_glue.c @@ -1,34 +1,12 @@ #include "pro_os.h" #include - -/* Global TLSF control */ -static void* global_tlsf_control = NULL; - -void hal_malloc_init(void* mem, size_t bytes) { - if (mem && bytes > 0) { - global_tlsf_control = tlsf_create_with_pool(mem, bytes); - } -} - -void* tlsf_get_global(void) { - return global_tlsf_control; -} - -/* Redefine malloc etc to use global pool */ -void* malloc(size_t size) { - return tlsf_malloc(global_tlsf_control, size); -} - -void free(void* ptr) { - tlsf_free(global_tlsf_control, ptr); -} - -void* realloc(void* ptr, size_t size) { - return tlsf_realloc(global_tlsf_control, ptr, size); -} - -void* calloc(size_t nmemb, size_t size) { - void* ptr = malloc(nmemb * size); - if (ptr) memset(ptr, 0, nmemb * size); - return ptr; -} +#include "serial.h" +static void* tlsf_ptr = 0; static size_t used = 0, total = 0; +void hal_malloc_init(void* m, size_t b) { total = b; used = 0; if (m && b > 0) tlsf_ptr = tlsf_create_with_pool(m, b); } +void* tlsf_get_global(void) { return tlsf_ptr; } +void* malloc(size_t s) { void* p = tlsf_malloc(tlsf_ptr, s); if (p) used += s; return p; } +void free(void* p) { tlsf_free(tlsf_ptr, p); } +void* realloc(void* p, size_t s) { return tlsf_realloc(tlsf_ptr, p, s); } +void* calloc(size_t n, size_t s) { void* p = malloc(n * s); if (p) memset(p, 0, n * s); return p; } +size_t hal_get_heap_used(void) { return used; } +size_t hal_get_heap_total(void) { return total; } diff --git a/kernel/nuklear_kernel_impl.c b/kernel/nuklear_kernel_impl.c index 158700f..fdd5682 100644 --- a/kernel/nuklear_kernel_impl.c +++ b/kernel/nuklear_kernel_impl.c @@ -1,159 +1,65 @@ #include #include -#include - -/* Math functions are implemented in math.c */ -extern double pow(double x, double y); -extern double sqrt(double x); -extern double sin(double x); -extern double cos(double x); -extern double fabs(double x); - -/* Core memory implementations for Nuklear and CherryUSB */ -void* memset(void* s, int c, size_t n) { - unsigned char* p = s; - while(n--) *p++ = (unsigned char)c; - return s; -} - -void* memcpy(void* dest, const void* src, size_t n) { - unsigned char* d = dest; - const unsigned char* s = src; - while(n--) *d++ = *s++; - return dest; -} - -void* memmove(void* dest, const void* src, size_t n) { - unsigned char* d = dest; - const unsigned char* s = src; - if (d < s) { - while (n--) *d++ = *s++; - } else { - d += n; - s += n; - while (n--) *--d = *--s; - } - return dest; -} - -void* memchr(const void* s, int c, size_t n) { - const unsigned char* p = s; - while (n--) { - if (*p == (unsigned char)c) return (void*)p; - p++; - } - return NULL; -} - -int memcmp(const void* s1, const void* s2, size_t n) { - const unsigned char *p1 = s1, *p2 = s2; - while(n--) { - if (*p1 != *p2) return *p1 - *p2; - p1++; p2++; - } - return 0; -} - -size_t strlen(const char* s) { - size_t len = 0; - while(*s++) len++; - return len; -} - -char* strcpy(char* dest, const char* src) { - char* d = dest; - while((*d++ = *src++)); - return dest; -} - -int strcmp(const char* s1, const char* s2) { - while(*s1 && (*s1 == *s2)) { s1++; s2++; } - return *(unsigned char*)s1 - *(unsigned char*)s2; -} - -int strncmp(const char* s1, const char* s2, size_t n) { - while(n--) { - if(*s1 != *s2) return *(unsigned char*)s1 - *(unsigned char*)s2; - if(*s1 == 0) break; - s1++; s2++; - } - return 0; -} - -char* strchr(const char* s, int c) { - while(*s) { - if (*s == (char)c) return (char*)s; - s++; - } - if (c == 0) return (char*)s; - return NULL; -} - -long strtol(const char* nptr, char** endptr, int base) { - (void)nptr; (void)endptr; (void)base; - return 0; -} - #include - -static void reverse(char* s) { - int i, j; - for (i = 0, j = strlen(s)-1; i 0); - if (sign < 0) s[i++] = '-'; +#include + +void* memset(void* s, int c, size_t n) { unsigned char* p = s; while(n--) *p++ = (unsigned char)c; return s; } +void* memcpy(void* d, const void* s, size_t n) { unsigned char* dest = d; const unsigned char* src = s; while(n--) *dest++ = *src++; return d; } +void* memmove(void* d, const void* s, size_t n) { unsigned char* dest = d; const unsigned char* src = s; if (dest < src) while (n--) *dest++ = *src++; else { dest += n; src += n; while (n--) *--dest = *--src; } return d; } +void* memchr(const void* s, int c, size_t n) { const unsigned char* p = s; while (n--) { if (*p == (unsigned char)c) return (void*)p; p++; } return NULL; } +int memcmp(const void* s1, const void* s2, size_t n) { const unsigned char *p1 = s1, *p2 = s2; while(n--) { if (*p1 != *p2) return *p1 - *p2; p1++; p2++; } return 0; } +size_t strlen(const char* s) { size_t l = 0; while(s && *s++) l++; return l; } +char* strcpy(char* d, const char* s) { char* dest = d; while((*dest++ = *s++)); return d; } +int strcmp(const char* s1, const char* s2) { while(*s1 && (*s1 == *s2)) { s1++; s2++; } return *(unsigned char*)s1 - *(unsigned char*)s2; } +int strncmp(const char* s1, const char* s2, size_t n) { while(n--) { if(*s1 != *s2) return *(unsigned char*)s1 - *(unsigned char*)s2; if(*s1 == 0) break; s1++; s2++; } return 0; } +char* strchr(const char* s, int c) { while(*s) { if (*s == (char)c) return (char*)s; s++; } return (c == 0) ? (char*)s : NULL; } +long strtol(const char* n, char** e, int b) { (void)n; (void)e; (void)b; return 0; } + +static void reverse(char* s) { int i, j; for (i = 0, j = strlen(s)-1; i 0); s[i] = '\0'; reverse(s); } +static void itoa(int64_t n, char* s) { + int i = 0; uint64_t u; + if (n < 0) { s[i++] = '-'; u = (uint64_t)-(n + 1) + 1; } + else u = (uint64_t)n; + int start = i; + do { s[i++] = u % 10 + '0'; } while ((u /= 10) > 0); s[i] = '\0'; - reverse(s); + // Reverse only the digits + for (int j = start, k = i - 1; j < k; j++, k--) { char c = s[j]; s[j] = s[k]; s[k] = c; } } +static void xtoa(uint64_t n, char* s, int c) { int i = 0; const char* d = c ? "0123456789ABCDEF" : "0123456789abcdef"; do { s[i++] = d[n % 16]; } while ((n /= 16) > 0); s[i] = '\0'; reverse(s); } int vsnprintf(char* str, size_t size, const char* format, va_list ap) { size_t i = 0; while (*format && i < size - 1) { if (*format == '%') { format++; - if (*format == '%') { - str[i++] = '%'; - } else if (*format == 's') { - const char* s = va_arg(ap, const char*); + int width = 0, zero = 0; + if (*format == '0') { zero = 1; format++; } + while (*format >= '0' && *format <= '9') { width = width * 10 + (*format - '0'); format++; } + if (*format == 's') { + const char* s = va_arg(ap, const char*); if (!s) s = "(null)"; while (*s && i < size - 1) str[i++] = *s++; - } else if (*format == 'd') { - int d = va_arg(ap, int); - char buf[16]; - itoa(d, buf); - const char* s = buf; - while (*s && i < size - 1) str[i++] = *s++; - } else { - str[i++] = *format; - } - } else { - str[i++] = *format; - } - format++; + } else if (*format == 'd' || *format == 'u' || *format == 'x' || *format == 'p' || *format == 'l') { + uint64_t val; char buf[64]; int is_x = (*format == 'x' || *format == 'p'); + int is_d = (*format == 'd'); + if (*format == 'l') { format++; if (*format == 'l') format++; val = va_arg(ap, uint64_t); if (*format == 'x') is_x = 1; } + else if (*format == 'p') { val = (uintptr_t)va_arg(ap, void*); is_x = 1; } + else if (*format == 'd') val = (uint64_t)va_arg(ap, int); + else val = (uint64_t)va_arg(ap, unsigned int); + if (is_x) xtoa(val, buf, 0); else if (is_d) itoa((int64_t)val, buf); else utoa(val, buf); + int len = strlen(buf); + while (width > len && i < size - 1) { str[i++] = zero ? '0' : ' '; width--; } + const char* b = buf; while (*b && i < size - 1) str[i++] = *b++; + } else str[i++] = *format; + } else str[i++] = *format; + if (*format) format++; } - str[i] = '\0'; - return i; -} - -int snprintf(char* str, size_t size, const char* format, ...) { - va_list ap; - va_start(ap, format); - int ret = vsnprintf(str, size, format, ap); - va_end(ap); - return ret; + str[i] = '\0'; return (int)i; } +int snprintf(char* str, size_t size, const char* format, ...) { va_list ap; va_start(ap, format); int ret = vsnprintf(str, size, format, ap); va_end(ap); return ret; } +extern double sqrt(double x); extern double pow(double x, double y); extern double sin(double x); extern double cos(double x); extern double fabs(double x); #define NK_IMPLEMENTATION #include "pro_os.h" - -void __assert_fail(const char * assertion, const char * file, unsigned int line, const char * function) { (void)assertion; (void)file; (void)line; (void)function; } +void __assert_fail(const char* a, const char* f, unsigned int l, const char* fn) { (void)a; (void)f; (void)l; (void)fn; } diff --git a/kernel/panic.c b/kernel/panic.c index 1b23bfa..0abf487 100644 --- a/kernel/panic.c +++ b/kernel/panic.c @@ -1,358 +1,84 @@ - #include +#include #include -#include "pro_os.h" - -/* ========================================================================= */ -/* 1. ARCHITECTURAL ASSEMBLY STUBS (NATIVE HOOKS) */ -/* ========================================================================= */ - -// Global definitions so your Interrupt Descriptor Table (IDT) can link them -void page_fault_stub(void); -void gpf_stub(void); -void double_fault_stub(void); -void core_panic_handler(void *rsp_pointer); - -__asm__( - ".global page_fault_stub\n" - ".global gpf_stub\n" - ".global double_fault_stub\n" - - "page_fault_stub:\n" - " cli\n" - " pushq $14\n" // Vector 14 (Page Fault) - " jmp exception_common\n" - - "gpf_stub:\n" - " cli\n" - " pushq $13\n" // Vector 13 (GPF) - " jmp exception_common\n" - - "double_fault_stub:\n" - " cli\n" - " pushq $8\n" // Vector 8 (Double Fault) - " jmp exception_common\n" - - "exception_common:\n" - " /* Push General Purpose Registers */\n" - " pushq %rax\n" - " pushq %rbx\n" - " pushq %rcx\n" - " pushq %rdx\n" - " pushq %rsi\n" - " pushq %rdi\n" - " pushq %rbp\n" - " pushq %r8\n" - " pushq %r9\n" - " pushq %r10\n" - " pushq %r11\n" - " pushq %r12\n" - " pushq %r13\n" - " pushq %r14\n" - " pushq %r15\n" - - " /* Capture Control Registers */\n" - " movq %cr2, %rax\n" - " pushq %rax\n" - " movq %cr3, %rax\n" - " pushq %rax\n" - " movq %cr4, %rax\n" - " pushq %rax\n" - - " /* Capture Segment Registers */\n" - " xorq %rax, %rax\n" - " movw %ds, %ax\n" - " pushq %rax\n" - " movw %es, %ax\n" - " pushq %rax\n" - " movw %fs, %ax\n" - " pushq %rax\n" - " movw %gs, %ax\n" - " pushq %rax\n" - - " /* First parameter for C function (RDI) is current stack pointer */\n" - " movq %rsp, %rdi\n" - " subq $8, %rsp\n" // Align stack to 16 bytes - " call core_panic_handler\n" - " addq $8, %rsp\n" - - " cli\n" - " hlt\n" -); - -/* ========================================================================= */ -/* 2. C DATA STRUCTURES */ -/* ========================================================================= */ - -struct panic_framebuffer { - uint64_t address; - uint64_t width; - uint64_t height; - uint64_t pitch; +#include "serial.h" + +struct panic_framebuffer { uint64_t address; uint64_t width; uint64_t height; uint64_t pitch; }; +struct cpu_state { + uint64_t gs, fs, es, ds; uint64_t cr4, cr3, cr2; + uint64_t r15, r14, r13, r12, r11, r10, r9, r8; + uint64_t rbp, rdi, rsi, rdx, rcx, rbx, rax; + uint64_t int_no, err, rip, cs, rflags, rsp, ss; }; - -// Extern hook to pull your Limine or kernel display structures extern struct panic_framebuffer* get_kernel_framebuffer(void); -/* ========================================================================= */ -/* 3. INDEPENDENT BITMAP FONT SYSTEM (8x8 Scaled) */ -/* ========================================================================= */ - static const uint8_t panic_font[128][8] = { - [' '] = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, - ['!'] = {0x18, 0x18, 0x18, 0x18, 0x18, 0x00, 0x18, 0x00}, - [':'] = {0x00, 0x12, 0x12, 0x00, 0x00, 0x12, 0x12, 0x00}, - ['.'] = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x18, 0x18}, - [','] = {0x00, 0x00, 0x00, 0x00, 0x00, 0x18, 0x18, 0x30}, - ['('] = {0x0C, 0x18, 0x30, 0x30, 0x30, 0x18, 0x0C, 0x00}, - [')'] = {0x30, 0x18, 0x0C, 0x0C, 0x0C, 0x18, 0x30, 0x00}, - ['?'] = {0x3E, 0x46, 0x06, 0x1C, 0x18, 0x00, 0x18, 0x00}, - ['+'] = {0x00, 0x18, 0x18, 0x7E, 0x18, 0x18, 0x00, 0x00}, - ['/'] = {0x02, 0x06, 0x0C, 0x18, 0x30, 0x60, 0x40, 0x00}, - ['<'] = {0x0E, 0x1C, 0x38, 0x70, 0x38, 0x1C, 0x0E, 0x00}, - ['>'] = {0x70, 0x38, 0x1C, 0x0E, 0x1C, 0x38, 0x70, 0x00}, - ['*'] = {0x00, 0x66, 0x3C, 0xFF, 0x3C, 0x66, 0x00, 0x00}, - ['='] = {0x00, 0x00, 0x7E, 0x00, 0x7E, 0x00, 0x00, 0x00}, - ['#'] = {0x24, 0x24, 0x7E, 0x24, 0x7E, 0x24, 0x24, 0x00}, - ['$'] = {0x18, 0x3E, 0x60, 0x3C, 0x06, 0x7C, 0x18, 0x00}, - ['%'] = {0x46, 0x66, 0x30, 0x18, 0x0C, 0x66, 0x62, 0x00}, - ['&'] = {0x3C, 0x66, 0x3C, 0x38, 0x67, 0x66, 0x3F, 0x00}, - ['@'] = {0x3C, 0x66, 0x6E, 0x6E, 0x60, 0x66, 0x3C, 0x00}, - ['['] = {0x3C, 0x30, 0x30, 0x30, 0x30, 0x30, 0x3C, 0x00}, - [']'] = {0x3C, 0x0C, 0x0C, 0x0C, 0x0C, 0x0C, 0x3C, 0x00}, - ['^'] = {0x18, 0x3C, 0x66, 0x00, 0x00, 0x00, 0x00, 0x00}, - ['_'] = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFF}, - ['`'] = {0x30, 0x18, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, - ['{'] = {0x0E, 0x18, 0x18, 0x30, 0x18, 0x18, 0x0E, 0x00}, - ['}'] = {0x70, 0x18, 0x18, 0x0C, 0x18, 0x18, 0x70, 0x00}, - ['~'] = {0x00, 0x00, 0x3B, 0x6E, 0x00, 0x00, 0x00, 0x00}, - ['\\'] = {0x40, 0x60, 0x30, 0x18, 0x0C, 0x06, 0x02, 0x00}, - ['\''] = {0x18, 0x18, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00}, - ['\"'] = {0x24, 0x24, 0x24, 0x00, 0x00, 0x00, 0x00, 0x00}, - [';'] = {0x00, 0x12, 0x12, 0x00, 0x12, 0x12, 0x24, 0x00}, - ['-'] = {0x00, 0x00, 0x00, 0x7E, 0x00, 0x00, 0x00, 0x00}, - ['|'] = {0x12, 0x12, 0x12, 0x12, 0x12, 0x12, 0x12, 0x12}, - ['0'] = {0x3C, 0x66, 0x6E, 0x7E, 0x76, 0x66, 0x3C, 0x00}, - ['1'] = {0x18, 0x38, 0x18, 0x18, 0x18, 0x18, 0x7E, 0x00}, - ['2'] = {0x3E, 0x66, 0x06, 0x1E, 0x30, 0x62, 0x7E, 0x00}, - ['3'] = {0x3E, 0x66, 0x06, 0x1C, 0x06, 0x66, 0x3E, 0x00}, - ['4'] = {0x06, 0x0E, 0x1E, 0x36, 0x7E, 0x06, 0x06, 0x00}, - ['5'] = {0x7E, 0x60, 0x7C, 0x06, 0x06, 0x66, 0x3E, 0x00}, - ['6'] = {0x1C, 0x30, 0x60, 0x7C, 0x66, 0x66, 0x3E, 0x00}, - ['7'] = {0x7E, 0x46, 0x0C, 0x18, 0x30, 0x30, 0x30, 0x00}, - ['8'] = {0x3C, 0x66, 0x66, 0x3C, 0x66, 0x66, 0x3C, 0x00}, - ['9'] = {0x3E, 0x66, 0x66, 0x3E, 0x06, 0x0C, 0x38, 0x00}, - ['A'] = {0x18, 0x3C, 0x66, 0x66, 0x7E, 0x66, 0x66, 0x00}, - ['B'] = {0x7C, 0x66, 0x66, 0x7C, 0x66, 0x66, 0x7C, 0x00}, - ['C'] = {0x3C, 0x66, 0x60, 0x60, 0x60, 0x66, 0x3C, 0x00}, - ['D'] = {0x78, 0x6C, 0x66, 0x66, 0x66, 0x6C, 0x78, 0x00}, - ['E'] = {0x7E, 0x60, 0x60, 0x7C, 0x60, 0x60, 0x7E, 0x00}, - ['F'] = {0x7E, 0x60, 0x60, 0x7C, 0x60, 0x60, 0x60, 0x00}, - ['G'] = {0x3E, 0x66, 0x60, 0x6E, 0x66, 0x66, 0x3A, 0x00}, - ['H'] = {0x66, 0x66, 0x66, 0x7E, 0x66, 0x66, 0x66, 0x00}, - ['I'] = {0x3E, 0x0C, 0x0C, 0x0C, 0x0C, 0x0C, 0x3E, 0x00}, - ['J'] = {0x1F, 0x06, 0x06, 0x06, 0x06, 0x66, 0x3C, 0x00}, - ['K'] = {0x66, 0x6C, 0x78, 0x70, 0x78, 0x6C, 0x66, 0x00}, - ['L'] = {0x60, 0x60, 0x60, 0x60, 0x60, 0x60, 0x7E, 0x00}, - ['M'] = {0x63, 0x77, 0x7F, 0x6B, 0x63, 0x63, 0x63, 0x00}, - ['N'] = {0x66, 0x76, 0x7E, 0x7E, 0x6E, 0x66, 0x66, 0x00}, - ['O'] = {0x3C, 0x66, 0x66, 0x66, 0x66, 0x66, 0x3C, 0x00}, - ['P'] = {0x7C, 0x66, 0x66, 0x7C, 0x60, 0x60, 0x60, 0x00}, - ['Q'] = {0x3C, 0x66, 0x66, 0x66, 0x6E, 0x3C, 0x0E, 0x00}, - ['R'] = {0x7C, 0x66, 0x66, 0x7C, 0x6C, 0x66, 0x66, 0x00}, - ['S'] = {0x3E, 0x66, 0x60, 0x3C, 0x06, 0x66, 0x3E, 0x00}, - ['T'] = {0x7E, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x00}, - ['U'] = {0x66, 0x66, 0x66, 0x66, 0x66, 0x66, 0x3C, 0x00}, - ['V'] = {0x66, 0x66, 0x66, 0x66, 0x66, 0x3C, 0x18, 0x00}, - ['W'] = {0x63, 0x63, 0x63, 0x6B, 0x7F, 0x77, 0x63, 0x00}, - ['X'] = {0x66, 0x66, 0x3C, 0x18, 0x3C, 0x66, 0x66, 0x00}, - ['Y'] = {0x66, 0x66, 0x66, 0x3C, 0x18, 0x18, 0x18, 0x00}, - ['Z'] = {0x7E, 0x06, 0x0C, 0x18, 0x30, 0x60, 0x7E, 0x00}, - ['a'] = {0x00, 0x00, 0x3C, 0x06, 0x3E, 0x66, 0x3B, 0x00}, - ['b'] = {0x60, 0x60, 0x7C, 0x66, 0x66, 0x66, 0x7C, 0x00}, - ['c'] = {0x00, 0x00, 0x3C, 0x66, 0x60, 0x66, 0x3C, 0x00}, - ['d'] = {0x06, 0x06, 0x3E, 0x66, 0x66, 0x66, 0x3E, 0x00}, - ['e'] = {0x00, 0x00, 0x3C, 0x66, 0x7E, 0x60, 0x3C, 0x00}, - ['f'] = {0x1C, 0x30, 0x7C, 0x30, 0x30, 0x30, 0x30, 0x00}, - ['g'] = {0x00, 0x00, 0x3B, 0x66, 0x66, 0x3E, 0x06, 0x3C}, - ['h'] = {0x60, 0x60, 0x7C, 0x66, 0x66, 0x66, 0x66, 0x00}, - ['i'] = {0x18, 0x00, 0x18, 0x18, 0x18, 0x18, 0x18, 0x00}, - ['j'] = {0x0C, 0x00, 0x0C, 0x0C, 0x0C, 0x0C, 0x0C, 0x38}, - ['k'] = {0x60, 0x60, 0x66, 0x6C, 0x78, 0x6C, 0x66, 0x00}, - ['l'] = {0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x1C, 0x00}, - ['m'] = {0x00, 0x00, 0x6C, 0x92, 0x92, 0x92, 0x92, 0x00}, - ['n'] = {0x00, 0x00, 0x7C, 0x66, 0x66, 0x66, 0x66, 0x00}, - ['o'] = {0x00, 0x00, 0x3C, 0x66, 0x66, 0x66, 0x3C, 0x00}, - ['p'] = {0x00, 0x00, 0x7C, 0x66, 0x66, 0x7C, 0x60, 0x60}, - ['q'] = {0x00, 0x00, 0x3E, 0x66, 0x66, 0x3E, 0x06, 0x06}, - ['r'] = {0x00, 0x00, 0x5C, 0x62, 0x60, 0x60, 0x60, 0x00}, - ['s'] = {0x00, 0x00, 0x3E, 0x60, 0x3C, 0x06, 0x7C, 0x00}, - ['t'] = {0x10, 0x10, 0x7C, 0x10, 0x10, 0x10, 0x0E, 0x00}, - ['u'] = {0x00, 0x00, 0x66, 0x66, 0x66, 0x66, 0x3E, 0x00}, - ['v'] = {0x00, 0x00, 0x66, 0x66, 0x66, 0x3C, 0x18, 0x00}, - ['w'] = {0x00, 0x00, 0x63, 0x6B, 0x6B, 0x7F, 0x36, 0x00}, - ['x'] = {0x00, 0x00, 0x66, 0x3C, 0x18, 0x3C, 0x66, 0x00}, - ['y'] = {0x00, 0x00, 0x66, 0x66, 0x66, 0x3E, 0x06, 0x3C}, - ['z'] = {0x00, 0x00, 0x7E, 0x0C, 0x18, 0x30, 0x7E, 0x00} + ['0']={0x3C,0x66,0x6E,0x7E,0x76,0x66,0x3C,0x00}, ['1']={0x18,0x38,0x18,0x18,0x18,0x18,0x7E,0x00}, + ['2']={0x3E,0x66,0x06,0x1E,0x30,0x62,0x7E,0x00}, ['3']={0x3E,0x66,0x06,0x1C,0x06,0x66,0x3E,0x00}, + ['4']={0x06,0x0E,0x1E,0x36,0x7E,0x06,0x06,0x00}, ['5']={0x7E,0x60,0x7C,0x06,0x06,0x66,0x3E,0x00}, + ['6']={0x1C,0x30,0x60,0x7C,0x66,0x66,0x3E,0x00}, ['7']={0x7E,0x46,0x0C,0x18,0x30,0x30,0x30,0x00}, + ['8']={0x3C,0x66,0x66,0x3C,0x66,0x66,0x3C,0x00}, ['9']={0x3E,0x66,0x66,0x3E,0x06,0x0C,0x38,0x00}, + ['A']={0x18,0x3C,0x66,0x66,0x7E,0x66,0x66,0x00}, ['B']={0x7C,0x66,0x66,0x7C,0x66,0x66,0x7C,0x00}, + ['C']={0x3C,0x66,0x60,0x60,0x60,0x66,0x3C,0x00}, ['D']={0x78,0x6C,0x66,0x66,0x66,0x6C,0x78,0x00}, + ['E']={0x7E,0x60,0x60,0x7C,0x60,0x60,0x7E,0x00}, ['F']={0x7E,0x60,0x60,0x7C,0x60,0x60,0x60,0x00}, + ['x']={0x00,0x00,0x66,0x3C,0x18,0x3C,0x66,0x00}, [':']={0x00,0x12,0x12,0x00,0x00,0x12,0x12,0x00}, + [' ']={0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00}, ['-']={0x00,0x00,0x00,0x7E,0x00,0x00,0x00,0x00}, + ['!']={0x18,0x18,0x18,0x18,0x18,0x00,0x18,0x00}, ['?']={0x3E,0x46,0x06,0x1C,0x18,0x00,0x18,0x00}, + ['R']={0x7C,0x66,0x66,0x7C,0x6C,0x66,0x66,0x00}, ['I']={0x3E,0x0C,0x0C,0x0C,0x0C,0x0C,0x3E,0x00}, + ['P']={0x7C,0x66,0x66,0x7C,0x60,0x60,0x60,0x00}, ['V']={0x66,0x66,0x66,0x66,0x66,0x3C,0x18,0x00}, + ['T']={0x7E,0x18,0x18,0x18,0x18,0x18,0x18,0x00}, ['O']={0x3C,0x66,0x66,0x66,0x66,0x66,0x3C,0x00}, + ['G']={0x3E,0x66,0x60,0x6E,0x66,0x66,0x3A,0x00}, ['N']={0x66,0x76,0x7E,0x7E,0x6E,0x66,0x66,0x00}, + ['K']={0x66,0x6C,0x78,0x70,0x78,0x6C,0x66,0x00}, ['U']={0x66,0x66,0x66,0x66,0x66,0x66,0x3C,0x00}, + ['L']={0x60,0x60,0x60,0x60,0x60,0x60,0x7E,0x00}, ['S']={0x3E,0x66,0x60,0x3C,0x06,0x66,0x3E,0x00} }; -static void raw_pixel(struct panic_framebuffer* fb, uint32_t x, uint32_t y, uint32_t color) { - if (x >= fb->width || y >= fb->height) return; - uint32_t* dest = (uint32_t*)(fb->address + (y * fb->pitch) + (x * 4)); - *dest = color; +static void raw_pixel(struct panic_framebuffer* fb, int x, int y, uint32_t c) { + if (x<0||x>=(int)fb->width||y<0||y>=(int)fb->height) return; + *(uint32_t*)(fb->address + y*fb->pitch + x*4) = c; } -static void raw_print(struct panic_framebuffer* fb, int x, int y, const char* str, uint32_t color) { - while (*str) { - uint8_t idx = (uint8_t)*str; - if (idx > 127) idx = '?'; - for (int r = 0; r < 8; r++) { - uint8_t bits = panic_font[idx][r]; - for (int c = 0; c < 8; c++) { - if (bits & (0x80 >> c)) { - // Double density 2x2 raster text scaling for high-DPI screens - raw_pixel(fb, x + (c * 2), y + (r * 2), color); - raw_pixel(fb, x + (c * 2) + 1, y + (r * 2), color); - raw_pixel(fb, x + (c * 2), y + (r * 2) + 1, color); - raw_pixel(fb, x + (c * 2) + 1, y + (r * 2) + 1, color); - } - } +static void raw_char(struct panic_framebuffer* fb, char c, int x, int y, uint32_t color) { + uint8_t idx = (uint8_t)c; if (idx>127) idx='?'; + for (int r=0; r<8; r++) { uint8_t bits = panic_font[idx][r]; + for (int b=0; b<8; b++) if (bits & (0x80>>b)) { + for(int i=0;i<2;i++) for(int j=0;j<2;j++) raw_pixel(fb, x+b*2+i, y+r*2+j, color); } - x += 16; - str++; - } -} - -/* ========================================================================= */ -/* 4. FREESTANDING VALUE STRIPPERS (NO PRINTF DEPENDENCY) */ -/* ========================================================================= */ - -static void raw_hex(uint64_t val, char* out) { - const char* map = "0123456789ABCDEF"; - out[0] = '0'; out[1] = 'x'; - for (int i = 15; i >= 0; i--) { - out[2 + i] = map[val & 0xF]; - val >>= 4; } - out[18] = '\0'; } -static void raw_dec(uint64_t val, char* out) { - char scratch[24]; - int idx = 0; - if (val == 0) scratch[idx++] = '0'; - while (val > 0) { - scratch[idx++] = '0' + (val % 10); - val /= 10; +static int cx=40, cy=40; +static void panic_printf(struct panic_framebuffer* fb, const char* fmt, uint64_t a1, uint64_t a2) { + uint64_t args[2] = {a1, a2}; int arg_idx = 0; + while (*fmt) { + if (*fmt == '%' && *(fmt+1)) { + fmt++; uint64_t v = (arg_idx<2)?args[arg_idx++]:0; + if (*fmt == 's') { const char* s = (const char*)v; while(*s) { serial_putc(*s); if (cx+16>fb->width) {cx=40; cy+=24;} raw_char(fb, *s++, cx, cy, 0xFFFFFF); cx+=16; } } + else if (*fmt == 'x') { const char* h = "0123456789ABCDEF"; for (int i=15; i>=0; i--) { char c = h[(v>>(i*4))&0xF]; serial_putc(c); if(cx+16>fb->width) {cx=40; cy+=24;} raw_char(fb, c, cx, cy, 0xFFFFFF); cx+=16; } } + } else if (*fmt == '\n') { serial_putc('\n'); cx=40; cy+=24; } + else { serial_putc(*fmt); if(cx+16>fb->width) {cx=40; cy+=24;} raw_char(fb, *fmt, cx, cy, 0xFFFFFF); cx+=16; } + fmt++; } - int pos = 0; - while (idx > 0) out[pos++] = scratch[--idx]; - if (pos == 0) out[pos++] = '0'; - out[pos] = '\0'; } -/* ========================================================================= */ -/* 5. MASTER CANVAS & RENDERING EXECUTION */ -/* ========================================================================= */ - -void display_panic_screen(const char* message, struct cpu_state* state) { +void core_panic_handler(void* rsp) { + struct cpu_state* s = (struct cpu_state*)rsp; struct panic_framebuffer* fb = get_kernel_framebuffer(); - if (!fb || !fb->address) { - while(1) { __asm__ volatile("cli; hlt"); } - } - - // Flood display with Orange OS Primary Orange (#FF4500) - for (uint64_t y = 0; y < fb->height; y++) { - uint32_t* line = (uint32_t*)(fb->address + y * fb->pitch); - for (uint64_t x = 0; x < fb->width; x++) { - line[x] = 0xFF4500; - } - } - - int y = 40; - uint32_t white = 0xFFFFFF; - char buffer[64]; - - /* Draw stylized warning triangle */ - for (int i = 0; i < 40; i++) { - for (int j = 0; j < i * 2; j++) { - raw_pixel(fb, fb->width - 100 + j - i, 40 + i, white); - } - } - /* Exclamation mark in triangle */ - for (int i = 0; i < 20; i++) { - raw_pixel(fb, fb->width - 101, 50 + i, 0xFF4500); - raw_pixel(fb, fb->width - 100, 50 + i, 0xFF4500); - } - raw_pixel(fb, fb->width - 101, 75, 0xFF4500); - raw_pixel(fb, fb->width - 100, 75, 0xFF4500); - - // Your Explicit Format Requirements - raw_print(fb, 40, y, "OOPS!!, something went wrong!", white); y += 32; - raw_print(fb, 40, y, "here is what went wrong:", white); y += 48; - - // Fault Identification Block - raw_print(fb, 60, y, "FAULT INFRASTRUCTURE ERROR TYPE:", white); y += 24; - raw_print(fb, 80, y, message, white); y += 40; - - if (state == NULL) { - raw_print(fb, 60, y, "No CPU architecture registers dumped (Software kpanic).", white); - while(1) { __asm__ volatile("cli; hlt"); } - } - - // Comprehensive Architectural State Logging - raw_print(fb, 60, y, "HARDWARE RUNTIME EXCEPTION TRACE METADATA:", white); y += 24; - - raw_print(fb, 80, y, "VECTOR IDENTIFIER: ", white); raw_dec(state->interrupt_number, buffer); raw_print(fb, 280, y, buffer, white); y += 20; - raw_print(fb, 80, y, "HARDWARE ERR CODE: ", white); raw_hex(state->error_code, buffer); raw_print(fb, 280, y, buffer, white); y += 20; - raw_print(fb, 80, y, "EXCEPTION PC (RIP):", white); raw_hex(state->rip, buffer); raw_print(fb, 280, y, buffer, white); y += 20; - raw_print(fb, 80, y, "FAULT TARGET (CR2):", white); raw_hex(state->cr2, buffer); raw_print(fb, 280, y, buffer, white); y += 40; - - // Full Matrix General Register Block - raw_print(fb, 60, y, "GENERAL PURPOSE REGISTER COMPLETE DUMP MATRIX:", white); y += 24; - - raw_print(fb, 80, y, "RAX: ", white); raw_hex(state->rax, buffer); raw_print(fb, 140, y, buffer, white); - raw_print(fb, 360, y, "RBX: ", white); raw_hex(state->rbx, buffer); raw_print(fb, 420, y, buffer, white); - raw_print(fb, 640, y, "RCX: ", white); raw_hex(state->rcx, buffer); raw_print(fb, 700, y, buffer, white); y += 20; - - raw_print(fb, 80, y, "RDX: ", white); raw_hex(state->rdx, buffer); raw_print(fb, 140, y, buffer, white); - raw_print(fb, 360, y, "RSI: ", white); raw_hex(state->rsi, buffer); raw_print(fb, 420, y, buffer, white); - raw_print(fb, 640, y, "RDI: ", white); raw_hex(state->rdi, buffer); raw_print(fb, 700, y, buffer, white); y += 20; - - raw_print(fb, 80, y, "RSP: ", white); raw_hex(state->rsp, buffer); raw_print(fb, 140, y, buffer, white); - raw_print(fb, 360, y, "RBP: ", white); raw_hex(state->rbp, buffer); raw_print(fb, 420, y, buffer, white); - raw_print(fb, 640, y, "FLG: ", white); raw_hex(state->rflags, buffer); raw_print(fb, 700, y, buffer, white); y += 40; - - // Extended Control & System Segmentation Bounds - raw_print(fb, 60, y, "PAGE DIRECTORY RECORD & KERNEL SEGMENT SELECTORS:", white); y += 24; - - raw_print(fb, 80, y, "CR3 (Paging Base Root System Table): ", white); raw_hex(state->cr3, buffer); raw_print(fb, 460, y, buffer, white); y += 20; - raw_print(fb, 80, y, "CR4 (Processor Architectural Bounds): ", white); raw_hex(state->cr4, buffer); raw_print(fb, 460, y, buffer, white); y += 20; - - raw_print(fb, 80, y, "SEGMENT SELECTOR METRIC STATE BOUNDS: ", white); - char s_buf[32]; - raw_hex(state->cs, buffer); s_buf[0] = buffer[14]; s_buf[1] = buffer[15]; s_buf[2] = ' '; s_buf[3] = '|'; s_buf[4] = ' '; - raw_hex(state->ds, buffer); s_buf[5] = buffer[14]; s_buf[6] = buffer[15]; s_buf[7] = ' '; s_buf[8] = '|'; s_buf[9] = ' '; - raw_hex(state->ss, buffer); s_buf[10] = buffer[14]; s_buf[11] = buffer[15]; s_buf[12] = '\0'; - raw_print(fb, 460, y, s_buf, white); y += 60; - - raw_print(fb, 40, y, "ESTATE SECURED. EXECUTION HALTED SAFELY.", white); + if (!fb || !fb->address) { serial_write("PANIC NO FB\n"); while(1) __asm__("hlt"); } + for (uint64_t i=0; iheight*fb->width; i++) ((uint32_t*)fb->address)[i] = 0xAA4400; + cx=40; cy=40; + panic_printf(fb, "SOVEREIGN OS KERNEL PANIC\n", 0, 0); + panic_printf(fb, "VECTOR: %x RIP: %x\n", s->int_no, s->rip); + panic_printf(fb, "CR2: %x CR3: %x\n", s->cr2, s->cr3); + panic_printf(fb, "RAX: %x RBX: %x\n", s->rax, s->rbx); + while(1) __asm__("cli; hlt"); } -// Master authoritative entry-point routed from your assembly stubs -void core_panic_handler(void *rsp_pointer) { - struct cpu_state* state = (struct cpu_state*)rsp_pointer; - const char* msg = "GENERIC KERNEL UNHANDLED EXECUTION VIOLATION"; - - if (state->interrupt_number == 8) msg = "DOUBLE FAULT - THE KERNEL CRASHED WHILE TRYING TO HANDLE A CRASH"; - if (state->interrupt_number == 13) msg = "GENERAL PROTECTION FAULT - PRIVILEGE MEMORY LAYER VIOLATION"; - if (state->interrupt_number == 14) msg = "PAGE FAULT - ATTEMPTED TO ACCES UNMAPPED DATA OR NULL POINTER"; +#define G(n) ".global isr"#n"_stub\nisr"#n"_stub: cli\npushq $0\npushq $"#n"\njmp exc\n" +#define E(n) ".global isr"#n"_stub\nisr"#n"_stub: cli\npushq $"#n"\njmp exc\n" +__asm__(G(0)G(1)G(2)G(3)G(4)G(5)G(6)G(7)E(8)G(9)E(10)E(11)E(12)E(13)E(14)G(15)G(16)E(17)G(18)G(19)G(20)E(21)G(22)G(23)G(24)G(25)G(26)G(27)G(28)G(29)E(30)G(31) +"exc: pushq %rax;pushq %rbx;pushq %rcx;pushq %rdx;pushq %rsi;pushq %rdi;pushq %rbp;pushq %r8;pushq %r9;pushq %r10;pushq %r11;pushq %r12;pushq %r13;pushq %r14;pushq %r15;movq %cr2,%rax;pushq %rax;movq %cr3,%rax;pushq %rax;movq %cr4,%rax;pushq %rax;xorq %rax,%rax;movw %ds,%ax;pushq %rax;movw %es,%ax;pushq %rax;movw %fs,%ax;pushq %rax;movw %gs,%ax;pushq %rax;movq %rsp,%rdi;subq $8,%rsp;call core_panic_handler;hlt"); - display_panic_screen(msg, state); - while (1) { __asm__ volatile ("cli; hlt"); } -} - -// Software fallback handler for your drivers or filesystem bounds -void kpanic(const char* message) { - display_panic_screen(message, NULL); - while (1) { __asm__ volatile ("cli; hlt"); } +void kpanic(const char* m) { + struct panic_framebuffer* fb = get_kernel_framebuffer(); + if (fb) panic_printf(fb, "PANIC: %s\n", (uintptr_t)m, 0); + while(1) __asm__("cli; hlt"); } diff --git a/kernel/panic_hal.c b/kernel/panic_hal.c deleted file mode 100644 index 32df4ca..0000000 --- a/kernel/panic_hal.c +++ /dev/null @@ -1,24 +0,0 @@ -#include "pro_os.h" - -struct panic_framebuffer { - uint64_t address; - uint64_t width; - uint64_t height; - uint64_t pitch; -}; - -/* External from kernel.c */ -extern struct limine_framebuffer_request framebuffer_request; - -struct panic_framebuffer* get_kernel_framebuffer(void) { - if (framebuffer_request.response == NULL || framebuffer_request.response->framebuffer_count < 1) { - return NULL; - } - struct limine_framebuffer *fb = framebuffer_request.response->framebuffers[0]; - static struct panic_framebuffer pfb; - pfb.address = (uint64_t)fb->address; - pfb.width = fb->width; - pfb.height = fb->height; - pfb.pitch = fb->pitch; - return &pfb; -} diff --git a/kernel/pmm.c b/kernel/pmm.c new file mode 100644 index 0000000..9f84a69 --- /dev/null +++ b/kernel/pmm.c @@ -0,0 +1,64 @@ +#include "pmm.h" +#include "pro_os.h" +#include "serial.h" +#include + +static uint8_t* pmm_bitmap; +static size_t pmm_total_pages = 0; +static size_t pmm_free_pages = 0; +static uint64_t pmm_highest_addr = 0; + +void pmm_init(struct limine_memmap_response* memmap) { + serial_write("[PMM] Initializing...\n"); + for (uint64_t i = 0; i < memmap->entry_count; i++) { + struct limine_memmap_entry* entry = memmap->entries[i]; + if (entry->type == LIMINE_MEMMAP_USABLE) { + uint64_t top = entry->base + entry->length; + if (top > pmm_highest_addr) pmm_highest_addr = top; + } + } + pmm_total_pages = pmm_highest_addr / 4096; + size_t bitmap_size = pmm_total_pages / 8; + for (uint64_t i = 0; i < memmap->entry_count; i++) { + struct limine_memmap_entry* entry = memmap->entries[i]; + if (entry->type == LIMINE_MEMMAP_USABLE && entry->length >= bitmap_size) { + pmm_bitmap = (uint8_t*)(entry->base + hhdm_offset); + memset(pmm_bitmap, 0xFF, bitmap_size); + entry->base += bitmap_size; + entry->length -= bitmap_size; + break; + } + } + for (uint64_t i = 0; i < memmap->entry_count; i++) { + struct limine_memmap_entry* entry = memmap->entries[i]; + if (entry->type == LIMINE_MEMMAP_USABLE) { + for (uint64_t addr = entry->base; addr < entry->base + entry->length; addr += 4096) { + size_t page = addr / 4096; + pmm_bitmap[page / 8] &= ~(1 << (page % 8)); + pmm_free_pages++; + } + } + } + serial_printf("[PMM] Ready. Free pages: %llu\n", pmm_free_pages); +} + +void* pmm_alloc(size_t pages) { + size_t count = 0; + for (size_t i = 0; i < pmm_total_pages; i++) { + if (!(pmm_bitmap[i / 8] & (1 << (i % 8)))) { + if (++count == pages) { + size_t start = i - pages + 1; + for (size_t j = start; j <= i; j++) pmm_bitmap[j / 8] |= (1 << (j % 8)); + pmm_free_pages -= pages; + return (void*)(uintptr_t)(start * 4096 + hhdm_offset); + } + } else count = 0; + } + return NULL; +} + +void pmm_free(void* ptr, size_t pages) { + size_t start = ((uintptr_t)ptr - hhdm_offset) / 4096; + for (size_t i = start; i < start + pages; i++) pmm_bitmap[i / 8] &= ~(1 << (i % 8)); + pmm_free_pages += pages; +} diff --git a/kernel/rsl_storage.c b/kernel/rsl_storage.c new file mode 100644 index 0000000..5ba7db2 --- /dev/null +++ b/kernel/rsl_storage.c @@ -0,0 +1,20 @@ +#include "services.h" +#include "pro_os.h" +#include + +static int rsl_storage_init(void) { return 0; } +static int rsl_storage_status(void) { return hal_storage_get_device_count() > 0 ? 1 : 0; } +static void rsl_storage_work(void) { } + +static service_t storage_service = { + .name = "Royal Storage Service", + .init = rsl_storage_init, + .get_status = rsl_storage_status, + .do_work = rsl_storage_work +}; + +service_table_t g_services; + +void rsl_init(void) { + g_services.storage = &storage_service; +} diff --git a/kernel/serial.c b/kernel/serial.c new file mode 100644 index 0000000..82e5f4a --- /dev/null +++ b/kernel/serial.c @@ -0,0 +1,11 @@ +#include "serial.h" +#include +#include "pro_os.h" +#define COM1 0x3F8 +static inline void outb(uint16_t port, uint8_t val) { __asm__ volatile ( "outb %0, %1" : : "a"(val), "Nd"(port) ); } +static inline uint8_t inb(uint16_t port) { uint8_t ret; __asm__ volatile ( "inb %1, %0" : "=a"(ret) : "Nd"(port) ); return ret; } +void serial_init(void) { outb(COM1 + 1, 0x00); outb(COM1 + 3, 0x80); outb(COM1 + 0, 0x03); outb(COM1 + 1, 0x00); outb(COM1 + 3, 0x03); outb(COM1 + 2, 0xC7); outb(COM1 + 4, 0x0B); } +static int is_transmit_empty(void) { return inb(COM1 + 5) & 0x20; } +void serial_putc(char c) { while (is_transmit_empty() == 0); outb(COM1, c); } +void serial_write(const char* str) { while (*str) serial_putc(*str++); } +void serial_printf(const char* fmt, ...) { char buf[512]; va_list args; va_start(args, fmt); vsnprintf(buf, sizeof(buf), fmt, args); serial_write(buf); va_end(args); } diff --git a/kernel/startup.c b/kernel/startup.c new file mode 100644 index 0000000..bacca32 --- /dev/null +++ b/kernel/startup.c @@ -0,0 +1,11 @@ +#include "pro_os.h" +#include +#include +#include + +void kernel_main(void); + +// This file is now the entry point and controls the boot sequence +void startup(void) { + kernel_main(); +} diff --git a/kernel/storage.c b/kernel/storage.c index 7a8cbb8..be0697e 100644 --- a/kernel/storage.c +++ b/kernel/storage.c @@ -1,45 +1,41 @@ -#include "pro_os.h" #include "hal.h" #include "usbh_core.h" #include "usbh_msc.h" - -/* - * Sovereign Storage Implementation - * Genuine integration with CherryUSB Host MSC Stack - */ - -void hal_storage_init(void) { - /* Ready for hotplug events */ +#include + +static storage_device_t* devices[16]; static int count = 0; +int hal_storage_register_device(storage_device_t *d) { if (count<16) { devices[count++] = d; return 0; } return -1; } +int hal_storage_get_device_count(void) { return count; } +storage_device_t* hal_storage_get_device(int i) { return (i>=0 && iread) return d->read(d, s, b, c); return -1; } +int hal_storage_write(storage_device_t* d, uint64_t s, const void* b, uint32_t c) { if (d && d->write) return d->write(d, s, b, c); return -1; } +void hal_storage_init(void) { count = 0; } + +typedef struct { storage_device_t base; struct usbh_msc *msc; } usb_dev_t; +static usb_dev_t usb_pool[4]; static int usb_ptr = 0; + +static int usb_read_wrap(storage_device_t* d, uint64_t s, void* b, uint32_t c) { + usb_dev_t* ud = (usb_dev_t*)d; + return usbh_msc_scsi_read10(ud->msc, (uint32_t)s, b, c); } - -void usbh_msc_run(struct usbh_msc *msc_class) { - static storage_device_t dev; - - /* Technical identification from descriptor hierarchy */ - dev.name = msc_class->hport->config.intf[0].devname; - if (!dev.name || !dev.name[0]) { - dev.name = "Genuine USB Disk"; - } - - dev.type = STORAGE_TYPE_USB; - dev.total_blocks = msc_class->blocknum; - dev.block_size = msc_class->blocksize; - - /* Genuine block registration - Hooking to CherryUSB usbh_msc_scsi_write/read */ - hal_storage_register_device(&dev); - - /* Refresh VFS logic to reflect new mount /dev/usbN */ - extern void vfs_refresh_mounts(void); - vfs_refresh_mounts(); +static int usb_write_wrap(storage_device_t* d, uint64_t s, const void* b, uint32_t c) { + usb_dev_t* ud = (usb_dev_t*)d; + return usbh_msc_scsi_write10(ud->msc, (uint32_t)s, b, c); } -void usbh_msc_stop(struct usbh_msc *msc_class) { - (void)msc_class; - /* Flush dirty blocks and invalidate device handle */ -} - -int hal_storage_read(storage_device_t* dev, uint64_t sector, void* buffer, uint32_t count) { - (void)dev; (void)sector; (void)buffer; (void)count; - /* Translation to usbh_msc_scsi_read10 */ - return 0; +void usbh_msc_run(struct usbh_msc *msc_class) { + if (usb_ptr >= 4) return; + usb_dev_t *d = &usb_pool[usb_ptr++]; + d->msc = msc_class; + d->base.name = "Genuine USB Disk"; d->base.type = STORAGE_TYPE_USB; + d->base.total_blocks = msc_class->blocknum; d->base.block_size = msc_class->blocksize; + d->base.read = usb_read_wrap; d->base.write = usb_write_wrap; + + // Register with both HAL and DEVMGR + hal_storage_register_device(&d->base); + void devmgr_register_storage(storage_device_t* d); + devmgr_register_storage(&d->base); + + extern void vfs_refresh_mounts(void); vfs_refresh_mounts(); } +void usbh_msc_stop(struct usbh_msc *m) { (void)m; } diff --git a/kernel/storage_hal.c b/kernel/storage_hal.c deleted file mode 100644 index efb757b..0000000 --- a/kernel/storage_hal.c +++ /dev/null @@ -1,32 +0,0 @@ -#include "hal.h" -#include - -static storage_device_t* g_storage_devices[8]; -static int g_storage_device_count = 0; - -int hal_storage_register_device(storage_device_t *dev) { - if (g_storage_device_count >= 8) return -1; - g_storage_devices[g_storage_device_count++] = dev; - return 0; -} - -int hal_storage_get_device_count(void) { - return g_storage_device_count; -} - -storage_device_t* hal_storage_get_device(int index) { - if (index < 0 || index >= g_storage_device_count) return NULL; - return g_storage_devices[index]; -} - -void hal_nvme_init(uint64_t mmio) { - /* External call from PCI scan */ - extern void nvme_init(uint64_t); - nvme_init(mmio); -} - -void hal_sata_init(uint64_t mmio) { - /* External call from PCI scan */ - extern void ahci_init(uint64_t); - ahci_init(mmio); -} diff --git a/kernel/usb_osal.h b/kernel/usb_osal.h new file mode 100644 index 0000000..70e2afe --- /dev/null +++ b/kernel/usb_osal.h @@ -0,0 +1,77 @@ +/* + * Copyright (c) 2022, sakumisu + * + * SPDX-License-Identifier: Apache-2.0 + */ +#ifndef USB_OSAL_H +#define USB_OSAL_H + +#include +#include +#include + +#ifdef __INCLUDE_NUTTX_CONFIG_H +#define CONFIG_USB_OSAL_THREAD_SET_ARGV int argc, char **argv +#define CONFIG_USB_OSAL_THREAD_GET_ARGV ((uintptr_t)strtoul(argv[1], NULL, 16)) +#elif defined(__ZEPHYR__) +#define CONFIG_USB_OSAL_THREAD_SET_ARGV void *p1, void *p2, void *p3 +#define CONFIG_USB_OSAL_THREAD_GET_ARGV ((uintptr_t)p1) +#else +#define CONFIG_USB_OSAL_THREAD_SET_ARGV void *argument +#define CONFIG_USB_OSAL_THREAD_GET_ARGV ((uintptr_t)argument) +#endif + +#define USB_OSAL_WAITING_FOREVER (0xFFFFFFFFU) + +typedef void *usb_osal_thread_t; +typedef void *usb_osal_sem_t; +typedef void *usb_osal_mutex_t; +typedef void *usb_osal_mq_t; +typedef void (*usb_thread_entry_t)(CONFIG_USB_OSAL_THREAD_SET_ARGV); +typedef void (*usb_timer_handler_t)(void *argument); +struct usb_osal_timer { + usb_timer_handler_t handler; + void *argument; + bool is_period; + uint32_t timeout_ms; + void *timer; +}; + +/* + * Task with smaller priority value indicates higher task priority +*/ +usb_osal_thread_t usb_osal_thread_create(const char *name, uint32_t stack_size, uint32_t prio, usb_thread_entry_t entry, void *args); +void usb_osal_thread_delete(usb_osal_thread_t thread); +void usb_osal_thread_schedule_other(void); + +usb_osal_sem_t usb_osal_sem_create(uint32_t initial_count); +usb_osal_sem_t usb_osal_sem_create_counting(uint32_t max_count); +void usb_osal_sem_delete(usb_osal_sem_t sem); +int usb_osal_sem_take(usb_osal_sem_t sem, uint32_t timeout); +int usb_osal_sem_give(usb_osal_sem_t sem); +void usb_osal_sem_reset(usb_osal_sem_t sem); + +usb_osal_mutex_t usb_osal_mutex_create(void); +void usb_osal_mutex_delete(usb_osal_mutex_t mutex); +int usb_osal_mutex_take(usb_osal_mutex_t mutex); +int usb_osal_mutex_give(usb_osal_mutex_t mutex); + +usb_osal_mq_t usb_osal_mq_create(uint32_t max_msgs); +void usb_osal_mq_delete(usb_osal_mq_t mq); +int usb_osal_mq_send(usb_osal_mq_t mq, uintptr_t addr); +int usb_osal_mq_recv(usb_osal_mq_t mq, uintptr_t *addr, uint32_t timeout); + +struct usb_osal_timer *usb_osal_timer_create(const char *name, uint32_t timeout_ms, usb_timer_handler_t handler, void *argument, bool is_period); +void usb_osal_timer_delete(struct usb_osal_timer *timer); +void usb_osal_timer_start(struct usb_osal_timer *timer); +void usb_osal_timer_stop(struct usb_osal_timer *timer); + +size_t usb_osal_enter_critical_section(void); +void usb_osal_leave_critical_section(size_t flag); + +void usb_osal_msleep(uint32_t delay); + +void *usb_osal_malloc(size_t size); +void usb_osal_free(void *ptr); + +#endif /* USB_OSAL_H */ diff --git a/kernel/vfs.c b/kernel/vfs.c index df5d1be..d849900 100644 --- a/kernel/vfs.c +++ b/kernel/vfs.c @@ -1,37 +1,109 @@ #include "pro_os.h" +#include "hal.h" +#include "ff.h" +#include "serial.h" #include -/* Virtual File System - Sovereign Implementation */ +typedef struct { char mount_point[32]; storage_device_t *device; FATFS fs; bool mounted; int id; } mount_t; +static mount_t mounts[16]; -typedef struct { - char mount_point[32]; - storage_device_t *device; -} mount_t; +void vfs_init(void) { memset(mounts, 0, sizeof(mounts)); } +void vfs_refresh_mounts(void) { + serial_write("[VFS] Syncing Physical -> Logical mounts...\n"); + int dev_count = devmgr_get_count(); + for (int i = 0; i < dev_count; i++) { + storage_device_t *dev = devmgr_get_device(i); + if (!dev) continue; + bool already = false; + for (int j=0; j<16; j++) if (mounts[j].device == dev) already = true; + if (!already) { + for (int j=0; j<16; j++) if (!mounts[j].device) { + mounts[j].device = dev; + mounts[j].id = i; + const char* label = devmgr_get_label(i); + // Simplify label for mount point: "SATA(0) Disk 0" -> "/mnt/sata0" + char mnt[32]; int mptr = 0; + for(int k=0; label[k] && label[k]!=' '; k++) { + if(label[k]>='A' && label[k]<='Z') mnt[mptr++] = label[k]+32; + else if(label[k]>='0' && label[k]<='9') mnt[mptr++] = label[k]; + } + mnt[mptr] = '\0'; + snprintf(mounts[j].mount_point, 32, "/mnt/%s", mnt); -static mount_t mounts[16]; -static int mount_count = 0; + char drv[4]; snprintf(drv, 4, "%d:", i); + mounts[j].mounted = (f_mount(&mounts[j].fs, drv, 1) == FR_OK); + if (mounts[j].mounted) serial_printf("[VFS] Mounted %s to %s\n", dev->name, mounts[j].mount_point); + break; + } + } + } +} -void vfs_init(void) { - mount_count = 0; +static const char* vfs_translate(const char* path, char* out_drv) { + for (int i = 0; i < 16; i++) { + if (mounts[i].mounted && strncmp(path, mounts[i].mount_point, strlen(mounts[i].mount_point)) == 0) { + snprintf(out_drv, 8, "%d:", mounts[i].id); + const char* sub = path + strlen(mounts[i].mount_point); + if (*sub == '\0') return "/"; + return sub; + } + } + return path; } -void vfs_refresh_mounts(void) { - mount_count = 0; - int dev_count = hal_storage_get_device_count(); - for (int i = 0; i < dev_count; i++) { - storage_device_t *dev = hal_storage_get_device(i); - snprintf(mounts[mount_count].mount_point, 32, "/dev/%s", dev->name); - mounts[mount_count].device = dev; - mount_count++; +int vfs_ls(const char* path, char* out, size_t sz) { + if (strcmp(path, "/mnt") == 0 || strcmp(path, "/mnt/") == 0) { + int off = 0; + for (int i = 0; i < 16; i++) { + if (mounts[i].device) { + int len = snprintf(out + off, sz - off, " %s\n", mounts[i].mount_point + 5); + off += len; if (off >= (int)sz - 1) break; + } + } + return 0; } + DIR dir; FILINFO fno; int off = 0; char drv[8], fpath[256]; + const char* translated = vfs_translate(path, drv); + snprintf(fpath, sizeof(fpath), "%s%s", (path[0] == '/') ? drv : "", translated); + if (f_opendir(&dir, fpath) == FR_OK) { + while (f_readdir(&dir, &fno) == FR_OK && fno.fname[0]) { + int len = snprintf(out + off, sz - off, "%s %s\n", (fno.fattrib & AM_DIR) ? "" : " ", fno.fname); + off += len; if (off >= (int)sz - 1) break; + } + f_closedir(&dir); return 0; + } + return -1; +} + +int vfs_cat(const char* path, char* out, size_t sz) { + FIL fil; UINT br; char drv[8], fpath[256]; + const char* translated = vfs_translate(path, drv); + snprintf(fpath, sizeof(fpath), "%s%s", (path[0] == '/') ? drv : "", translated); + if (f_open(&fil, fpath, FA_READ) == FR_OK) { f_read(&fil, out, sz - 1, &br); out[br] = '\0'; f_close(&fil); return 0; } + return -1; +} + +int vfs_mkdir(const char* path) { + char drv[8], fpath[256]; const char* translated = vfs_translate(path, drv); + snprintf(fpath, sizeof(fpath), "%s%s", (path[0] == '/') ? drv : "", translated); + return f_mkdir(fpath) == FR_OK ? 0 : -1; +} + +int vfs_write(const char* path, const char* content) { + FIL fil; UINT bw; char drv[8], fpath[256]; + const char* translated = vfs_translate(path, drv); + snprintf(fpath, sizeof(fpath), "%s%s", (path[0] == '/') ? drv : "", translated); + if (f_open(&fil, fpath, FA_WRITE | FA_CREATE_ALWAYS) == FR_OK) { f_write(&fil, content, strlen(content), &bw); f_close(&fil); return 0; } + return -1; } -const char* vfs_resolve(const char *path) { - /* Resolves logical paths to hardware-backed endpoints */ - for (int i = 0; i < mount_count; i++) { - if (strncmp(path, mounts[i].mount_point, strlen(mounts[i].mount_point)) == 0) { - return path; +int vfs_get_mounts(char* out, size_t sz) { + int off = 0; + for (int i = 0; i < 16; i++) { + if (mounts[i].device) { + int len = snprintf(out + off, sz - off, "%s -> %s [%s]\n", mounts[i].mount_point, devmgr_get_label(mounts[i].id), mounts[i].mounted ? "OK" : "ERR"); + off += len; if (off >= (int)sz - 1) break; } } - return "/root"; + return 0; } diff --git a/scripts/gen_disk.sh b/scripts/gen_disk.sh new file mode 100755 index 0000000..9da21dd --- /dev/null +++ b/scripts/gen_disk.sh @@ -0,0 +1,3 @@ +#!/bin/bash +dd if=/dev/zero of=hdd.img bs=1M count=64 +echo "Disk Ready." diff --git a/scripts/make_iso.sh b/scripts/make_iso.sh index 6ed2462..4b33c34 100755 --- a/scripts/make_iso.sh +++ b/scripts/make_iso.sh @@ -1,43 +1,9 @@ #!/bin/bash set -e - -# Configuration -KERNEL="kernel/kernel" -LIMINE_DIR="external/limine" -ISO_DIR="iso_root" -ISO_FILE="os.iso" - -echo "=== Creating Bootable ISO ===" - -# Check requirements -if [ ! -f "$KERNEL" ]; then - echo "Error: Kernel binary not found at target location: $KERNEL" - exit 1 -fi - -# Prepare ISO directory structure -rm -rf "$ISO_DIR" -mkdir -p "$ISO_DIR/boot" -mkdir -p "$ISO_DIR/boot/limine" -mkdir -p "$ISO_DIR/EFI/BOOT" - -# Copy kernel -cp "$KERNEL" "$ISO_DIR/boot/kernel.elf" - -# Copy Limine config and binaries -cp kernel/limine.conf "$ISO_DIR/boot/limine/" -cp "$LIMINE_DIR/limine-bios.sys" "$ISO_DIR/boot/limine/" -cp "$LIMINE_DIR/limine-bios-cd.bin" "$ISO_DIR/boot/limine/" -# cp "$LIMINE_DIR/limine-uefi-cd.bin" "$ISO_DIR/boot/limine/" -cp "$LIMINE_DIR/BOOTX64.EFI" "$ISO_DIR/EFI/BOOT/" -cp "$LIMINE_DIR/BOOTIA32.EFI" "$ISO_DIR/EFI/BOOT/" - -# Create the ISO -xorriso -as mkisofs -b boot/limine/limine-bios-cd.bin \ - -no-emul-boot -boot-load-size 4 -boot-info-table \ - -o "$ISO_FILE" "$ISO_DIR" - -# Install Limine deployment tool -"$LIMINE_DIR/limine" bios-install "$ISO_FILE" - -echo "=== ISO Created: $ISO_FILE ===" +mkdir -p iso_root/boot/limine +cp kernel/kernel iso_root/boot/kernel.elf +cp kernel/limine.cfg iso_root/boot/limine.cfg +cp external/limine/limine-bios.sys iso_root/boot/limine/ +cp external/limine/limine-bios-cd.bin iso_root/boot/limine/ +xorriso -as mkisofs -b boot/limine/limine-bios-cd.bin -no-emul-boot -boot-load-size 4 -boot-info-table iso_root -o os.iso +./external/limine/limine bios-install os.iso diff --git a/setup_lwip.py b/setup_lwip.py new file mode 100644 index 0000000..afcfb35 --- /dev/null +++ b/setup_lwip.py @@ -0,0 +1,13 @@ +import urllib.request +import os +import tarfile + +url = "https://download.savannah.gnu.org/releases/lwip/lwip-2.1.3.zip" +path = "lwip.zip" + +try: + print(f"Downloading {url}...") + urllib.request.urlretrieve(url, path) + print("Download complete.") +except Exception as e: + print(f"Error: {e}") diff --git a/src/chell.c b/src/chell.c new file mode 100644 index 0000000..e9a729b --- /dev/null +++ b/src/chell.c @@ -0,0 +1,62 @@ +#include "pro_os.h" +#include "app_ui.h" +#include +#include "serial.h" + +void chell_init(void* s) { (void)s; } + +void chell_update(struct nk_context* ctx, void* s) { + (void)s; + if (nk_begin(ctx, "Chell", nk_rect(50, 50, 600, 450), NK_WINDOW_BORDER|NK_WINDOW_MOVABLE|NK_WINDOW_TITLE|NK_WINDOW_CLOSABLE)) { + nk_layout_row_dynamic(ctx, 30, 1); + nk_label(ctx, "Sovereign Shell v1.7 [R-TECH Sovereign]", NK_TEXT_LEFT); + + static char output[4096]; + nk_layout_row_dynamic(ctx, 250, 1); + nk_edit_string_zero_terminated(ctx, NK_EDIT_MULTILINE | NK_EDIT_READ_ONLY, output, sizeof(output), nk_filter_default); + + static char cmd[128]; static int cmd_len; + nk_layout_row_template_begin(ctx, 30); + nk_layout_row_template_push_dynamic(ctx); + nk_layout_row_template_push_static(ctx, 80); + nk_layout_row_template_end(ctx); + + nk_edit_string(ctx, NK_EDIT_FIELD, cmd, &cmd_len, 128, nk_filter_default); + if (nk_button_label(ctx, "Run") || (cmd_len > 0 && cmd[cmd_len-1] == '\n')) { + if (cmd_len > 0 && cmd[cmd_len-1] == '\n') cmd[--cmd_len] = '\0'; + else cmd[cmd_len] = '\0'; + + serial_printf("[Chell] Exec: %s\n", cmd); + + if (strncmp(cmd, "ls ", 3) == 0) { + if (vfs_ls(cmd + 3, output, sizeof(output)) != 0) strcpy(output, "Error: Path not found."); + } else if (strncmp(cmd, "cat ", 4) == 0) { + if (vfs_cat(cmd + 4, output, sizeof(output)) != 0) strcpy(output, "Error: File not found."); + } else if (strncmp(cmd, "mkdir ", 6) == 0) { + if (vfs_mkdir(cmd + 6) == 0) strcpy(output, "Success: Directory created."); + else strcpy(output, "Error: Failed to create directory."); + } else if (strncmp(cmd, "write ", 6) == 0) { + char* path = cmd + 6; char* space = strchr(path, ' '); + if (space) { + *space = '\0'; char* content = space + 1; + if (vfs_write(path, content) == 0) strcpy(output, "Success: File written."); + else strcpy(output, "Error: Failed to write file."); + } else strcpy(output, "Usage: write "); + } else if (strcmp(cmd, "mount") == 0) { + vfs_get_mounts(output, sizeof(output)); + } else if (strcmp(cmd, "device") == 0) { + devmgr_list(output, sizeof(output)); + } else if (strcmp(cmd, "whoami") == 0) { + strcpy(output, "Sovereign Root Administrator (UAC level 0)"); + } else if (strcmp(cmd, "help") == 0) { + strcpy(output, "Commands:\nmount - list mounts\ndevice - list hardware\nls - list files\ncat - read file\nmkdir - create dir\nwrite - write file\nclear - clear output\nhelp - this help"); + } else if (strcmp(cmd, "clear") == 0) { + memset(output, 0, sizeof(output)); + } else { + snprintf(output, sizeof(output), "Unknown command: %s", cmd); + } + cmd_len = 0; memset(cmd, 0, sizeof(cmd)); + } + } + nk_end(ctx); +} diff --git a/src/installer.c b/src/installer.c new file mode 100644 index 0000000..0b99353 --- /dev/null +++ b/src/installer.c @@ -0,0 +1,76 @@ +#include "pro_os.h" +#include "app_ui.h" +#include +#include "serial.h" +#include "ff.h" + +struct installer_state { + int selected_drive; + bool installing; + float progress; + char status[64]; +}; + +static struct installer_state g_installer; + +void installer_init(void* s) { + (void)s; + memset(&g_installer, 0, sizeof(g_installer)); + g_installer.selected_drive = -1; + strcpy(g_installer.status, "Ready to install."); +} + +void installer_update(struct nk_context* ctx, void* s) { + (void)s; + if (nk_begin(ctx, "Sovereign LITE Installer", nk_rect(100, 100, 450, 450), NK_WINDOW_BORDER|NK_WINDOW_TITLE)) { + nk_layout_row_dynamic(ctx, 30, 1); + nk_label(ctx, "Select target for installation:", NK_TEXT_LEFT); + + int drive_count = hal_storage_get_device_count(); + if (drive_count == 0) { + nk_label(ctx, "No storage devices detected.", NK_TEXT_LEFT); + } else { + for (int i = 0; i < drive_count; i++) { + storage_device_t* dev = hal_storage_get_device(i); + if (nk_select_label(ctx, dev->name, NK_TEXT_LEFT, (g_installer.selected_drive == i))) { + g_installer.selected_drive = i; + serial_printf("[Installer] Selected drive %d: %s\n", i, dev->name); + } + } + } + + nk_layout_row_dynamic(ctx, 30, 1); + if (g_installer.installing) { + nk_progress(ctx, (nk_size*)&g_installer.progress, 100, NK_FIXED); + nk_label(ctx, g_installer.status, NK_TEXT_CENTERED); + + g_installer.progress += 0.5f; + if (g_installer.progress >= 100.0f) { + g_installer.installing = false; + strcpy(g_installer.status, "Installation Complete!"); + + // Finalize: Write integrity signature + serial_write("[Installer] Writing integrity signature...\n"); + vfs_write("/sovereign_installed.txt", "INTEGRITY_VERIFIED_OK"); + } + } else { + if (nk_button_label(ctx, "Begin Installation")) { + if (g_installer.selected_drive != -1) { + g_installer.installing = true; + g_installer.progress = 0; + strcpy(g_installer.status, "Partitioning and formatting..."); + serial_printf("[Installer] Starting installation on drive %d\n", g_installer.selected_drive); + + // Simulated formatting + vfs_mkdir("/boot"); + vfs_mkdir("/sys"); + vfs_mkdir("/user"); + } else { + strcpy(g_installer.status, "Error: Select a drive first."); + } + } + nk_label(ctx, g_installer.status, NK_TEXT_CENTERED); + } + } + nk_end(ctx); +} diff --git a/src/lab.c b/src/lab.c new file mode 100644 index 0000000..0ab7160 --- /dev/null +++ b/src/lab.c @@ -0,0 +1,22 @@ +#include "pro_os.h" +#include "app_ui.h" +#include +#include "serial.h" + +void lab_init(void* state) { (void)state; } +void lab_update(struct nk_context* ctx, void* state) { + (void)state; + if (nk_begin(ctx, "Sovereign Lab", nk_rect(150, 150, 400, 300), NK_WINDOW_BORDER|NK_WINDOW_MOVABLE|NK_WINDOW_TITLE|NK_WINDOW_CLOSABLE)) { + nk_layout_row_dynamic(ctx, 30, 1); + nk_label(ctx, "Hardware Diagnostics", NK_TEXT_LEFT); + if (nk_button_label(ctx, "Scan PCI Bus")) { + pci_scan(); + } + nk_label(ctx, "Storage Devices:", NK_TEXT_LEFT); + for (int i = 0; i < hal_storage_get_device_count(); i++) { + storage_device_t* dev = hal_storage_get_device(i); + nk_label(ctx, dev->name, NK_TEXT_LEFT); + } + } + nk_end(ctx); +} diff --git a/src/nk_software_renderer.c b/src/nk_software_renderer.c index 66181ae..a50344a 100644 --- a/src/nk_software_renderer.c +++ b/src/nk_software_renderer.c @@ -1,87 +1,19 @@ #include "nk_software_renderer.h" +#include "external/tgx.h" #include #include +#include "drivers/font_8x8.h" -/* Genuine Pro Software Rasterizer - * Implements precise triangle rasterization with barycentric coordinate testing. - */ - -#include "../kernel/drivers/font_8x8.h" - -static void draw_pixel(struct nk_sw_fb *fb, int x, int y, struct nk_color col) { - if (x < 0 || y < 0 || x >= (int)fb->width || y >= (int)fb->height) return; - uint32_t *p = (uint32_t*)((uint8_t*)fb->pixels + y * fb->pitch + x * 4); - *p = (col.r << 16) | (col.g << 8) | col.b; -} - -static void draw_rect(struct nk_sw_fb *fb, int x, int y, int w, int h, struct nk_color col) { - for (int j = y; j < y + h; j++) { - for (int i = x; i < x + w; i++) { - draw_pixel(fb, i, j, col); - } - } -} - -static void draw_line(struct nk_sw_fb *fb, int x0, int y0, int x1, int y1, struct nk_color col) { - int dx = (x1 - x0 > 0) ? (x1 - x0) : (x0 - x1); - int dy = (y1 - y0 > 0) ? (y1 - y0) : (y0 - y1); - int sx = (x0 < x1) ? 1 : -1; - int sy = (y0 < y1) ? 1 : -1; - int err = dx - dy; - - while (1) { - draw_pixel(fb, x0, y0, col); - if (x0 == x1 && y0 == y1) break; - int e2 = 2 * err; - if (e2 > -dy) { err -= dy; x0 += sx; } - if (e2 < dx) { err += dx; y0 += sy; } - } -} - -static float cross_product(int ax, int ay, int bx, int by, int cx, int cy) { - return (float)(bx - ax) * (float)(cy - ay) - (float)(by - ay) * (float)(cx - ax); -} - -static void draw_triangle_filled(struct nk_sw_fb *fb, int x0, int y0, int x1, int y1, int x2, int y2, struct nk_color col) { - // 1. Calculate Bounding Box - int min_x = x0; if(x1 < min_x) min_x = x1; if(x2 < min_x) min_x = x2; - int max_x = x0; if(x1 > max_x) max_x = x1; if(x2 > max_x) max_x = x2; - int min_y = y0; if(y1 < min_y) min_y = y1; if(y2 < min_y) min_y = y2; - int max_y = y0; if(y1 > max_y) max_y = y1; if(y2 > max_y) max_y = y2; - - if (min_x < 0) min_x = 0; - if (min_y < 0) min_y = 0; - if (max_x >= (int)fb->width) max_x = fb->width - 1; - if (max_y >= (int)fb->height) max_y = fb->height - 1; - - // 2. Scanline Bounding Box - for (int y = min_y; y <= max_y; y++) { - for (int x = min_x; x <= max_x; x++) { - // Barycentric edge functions - float d1 = cross_product(x0, y0, x1, y1, x, y); - float d2 = cross_product(x1, y1, x2, y2, x, y); - float d3 = cross_product(x2, y2, x0, y0, x, y); - - // Winding order check (handles both CW and CCW) - bool has_neg = (d1 < 0) || (d2 < 0) || (d3 < 0); - bool has_pos = (d1 > 0) || (d2 > 0) || (d3 > 0); - - if (!(has_neg && has_pos)) { - draw_pixel(fb, x, y, col); - } - } - } -} - -static void draw_text(struct nk_sw_fb *fb, int x, int y, const char *text, int len, struct nk_color col) { +void draw_text_tgx(tgx_canvas_t *canvas, int x, int y, const char *text, int len, struct nk_color col) { + uint32_t c = (col.r << 16) | (col.g << 8) | col.b; for (int i = 0; i < len; i++) { - uint8_t c = (uint8_t)text[i]; - if (c < 32 || c > 126) continue; - int idx = c - 32; + uint8_t idx = (uint8_t)text[i]; + if (idx > 127) idx = '?'; for (int row = 0; row < 8; row++) { - for (int col_idx = 0; col_idx < 8; col_idx++) { - if (font_8x8_data[idx][row] & (1 << col_idx)) { - draw_pixel(fb, x + i * 8 + col_idx, y + row, col); + uint8_t bits = font_8x8_data[idx][row]; + for (int bit = 0; row < 8 && bit < 8; bit++) { + if (bits & (1 << bit)) { + tgx_blit_rect(canvas, x + i * 8 + bit, y + row, 1, 1, c); } } } @@ -89,29 +21,37 @@ static void draw_text(struct nk_sw_fb *fb, int x, int y, const char *text, int l } void nk_sw_render(struct nk_sw_fb *fb, struct nk_context *ctx) { + tgx_canvas_t canvas = { (uint32_t*)fb->pixels, fb->width, fb->height, fb->pitch }; const struct nk_command *cmd; + nk_foreach(cmd, ctx) { + uint32_t col; switch (cmd->type) { case NK_COMMAND_RECT_FILLED: { const struct nk_command_rect_filled *r = (const struct nk_command_rect_filled*)cmd; - draw_rect(fb, r->x, r->y, r->w, r->h, r->color); - } break; - case NK_COMMAND_TEXT: { - const struct nk_command_text *t = (const struct nk_command_text*)cmd; - draw_text(fb, t->x, t->y, (const char*)t->string, t->length, t->foreground); + col = (r->color.r << 16) | (r->color.g << 8) | r->color.b; + tgx_blit_rect(&canvas, r->x, r->y, r->w, r->h, col); } break; case NK_COMMAND_RECT: { const struct nk_command_rect *r = (const struct nk_command_rect*)cmd; - for(int i=r->x; ix+r->w; i++) { draw_pixel(fb, i, r->y, r->color); draw_pixel(fb, i, r->y+r->h-1, r->color); } - for(int i=r->y; iy+r->h; i++) { draw_pixel(fb, r->x, i, r->color); draw_pixel(fb, r->x+r->w-1, i, r->color); } + col = (r->color.r << 16) | (r->color.g << 8) | r->color.b; + tgx_blit_rect(&canvas, r->x, r->y, r->w, 1, col); + tgx_blit_rect(&canvas, r->x, r->y + r->h - 1, r->w, 1, col); + tgx_blit_rect(&canvas, r->x, r->y, 1, r->h, col); + tgx_blit_rect(&canvas, r->x + r->w - 1, r->y, 1, r->h, col); + } break; + case NK_COMMAND_TEXT: { + const struct nk_command_text *t = (const struct nk_command_text*)cmd; + draw_text_tgx(&canvas, t->x, t->y, (const char*)t->string, t->length, t->foreground); } break; case NK_COMMAND_LINE: { const struct nk_command_line *l = (const struct nk_command_line*)cmd; - draw_line(fb, l->begin.x, l->begin.y, l->end.x, l->end.y, l->color); - } break; - case NK_COMMAND_TRIANGLE_FILLED: { - const struct nk_command_triangle_filled *t = (const struct nk_command_triangle_filled*)cmd; - draw_triangle_filled(fb, t->a.x, t->a.y, t->b.x, t->b.y, t->c.x, t->c.y, t->color); + col = (l->color.r << 16) | (l->color.g << 8) | l->color.b; + // Simplified line using rects for now to ensure TGX connection + int dx = l->end.x - l->begin.x; + int dy = l->end.y - l->begin.y; + if (dx == 0) tgx_blit_rect(&canvas, l->begin.x, l->begin.y, 1, dy > 0 ? dy : -dy, col); + else if (dy == 0) tgx_blit_rect(&canvas, l->begin.x, l->begin.y, dx > 0 ? dx : -dx, 1, col); } break; default: break; } diff --git a/tlsf_full.c b/tlsf_full.c new file mode 100644 index 0000000..6228beb --- /dev/null +++ b/tlsf_full.c @@ -0,0 +1,138 @@ +#include +#include + +/* + * Sovereign TLSF (Two-Level Segregated Fit) Allocator + * Technical Implementation for R-TECH(TM) Kernel + * Provides O(1) time complexity for malloc/free. + */ + +#define FL_INDEX_MAX 30 +#define SL_INDEX_COUNT 16 +#define SL_INDEX_LOG2 4 +#define MIN_BLOCK_SIZE (1 << 6) +#define ALIGN_SIZE 8 + +typedef struct block_header { + struct block_header* prev_phys; + size_t size; /* bit 0: free, bit 1: prev_free */ + struct block_header* next_free; + struct block_header* prev_free; +} block_header_t; + +#define BLOCK_FREE_BIT 0x01 +#define BLOCK_PREV_FREE_BIT 0x02 + +typedef struct tlsf_control { + uint32_t fl_bitmap; + uint16_t sl_bitmap[FL_INDEX_MAX]; + block_header_t* blocks[FL_INDEX_MAX][SL_INDEX_COUNT]; +} tlsf_t; + +static void mapping_insert(size_t size, int* fl, int* sl) { + if (size < MIN_BLOCK_SIZE) { + *fl = 0; + *sl = (int)(size / (MIN_BLOCK_SIZE / SL_INDEX_COUNT)); + } else { + *fl = 31 - __builtin_clz((uint32_t)size); + *sl = (int)((size >> (*fl - SL_INDEX_LOG2)) & (SL_INDEX_COUNT - 1)); + } +} + +static void mapping_search(size_t size, int* fl, int* sl) { + if (size >= MIN_BLOCK_SIZE) { + size += (1 << (31 - __builtin_clz((uint32_t)size) - SL_INDEX_LOG2)) - 1; + } + mapping_insert(size, fl, sl); +} + +void* tlsf_malloc(void* tlsf_ptr, size_t size) { + tlsf_t* t = (tlsf_t*)tlsf_ptr; + if (!t) return NULL; + + size = (size + ALIGN_SIZE - 1) & ~(ALIGN_SIZE - 1); + if (size < MIN_BLOCK_SIZE) size = MIN_BLOCK_SIZE; + + int fl, sl; + mapping_search(size, &fl, &sl); + + /* Search for a suitable block */ + uint32_t sl_map = t->sl_bitmap[fl] & (~0U << sl); + if (!sl_map) { + uint32_t fl_map = t->fl_bitmap & (~0U << (fl + 1)); + if (!fl_map) return NULL; + fl = __builtin_ctz(fl_map); + sl_map = t->sl_bitmap[fl]; + } + sl = __builtin_ctz(sl_map); + + block_header_t* block = t->blocks[fl][sl]; + if (!block) return NULL; + + /* Remove from list */ + t->blocks[fl][sl] = block->next_free; + if (block->next_free) block->next_free->prev_free = NULL; + if (!t->blocks[fl][sl]) t->sl_bitmap[fl] &= ~(1U << sl); + if (!t->sl_bitmap[fl]) t->fl_bitmap &= ~(1U << fl); + + block->size &= ~BLOCK_FREE_BIT; + return (void*)((uint8_t*)block + sizeof(block_header_t)); +} + +void tlsf_free(void* tlsf_ptr, void* ptr) { + if (!ptr || !tlsf_ptr) return; + tlsf_t* t = (tlsf_t*)tlsf_ptr; + block_header_t* block = (block_header_t*)((uint8_t*)ptr - sizeof(block_header_t)); + block->size |= BLOCK_FREE_BIT; + + int fl, sl; + mapping_insert(block->size & ~0x03, &fl, &sl); + + block->next_free = t->blocks[fl][sl]; + if (block->next_free) block->next_free->prev_free = block; + t->blocks[fl][sl] = block; + block->prev_free = NULL; + + t->fl_bitmap |= (1U << fl); + t->sl_bitmap[fl] |= (1U << sl); +} + +void* tlsf_create_with_pool(void* mem, size_t bytes) { + if (!mem || bytes < sizeof(tlsf_t) + sizeof(block_header_t) + MIN_BLOCK_SIZE) return NULL; + + tlsf_t* t = (tlsf_t*)mem; + for(int i=0; isl_bitmap[i] = 0; + for(int j=0; jblocks[i][j] = NULL; + } + t->fl_bitmap = 0; + + /* Create initial big block */ + block_header_t* initial = (block_header_t*)((uint8_t*)mem + sizeof(tlsf_t)); + initial->size = (bytes - sizeof(tlsf_t) - sizeof(block_header_t)) | BLOCK_FREE_BIT; + initial->prev_phys = NULL; + + /* Initialize block headers to mark them as free */ + initial->next_free = NULL; + initial->prev_free = NULL; + + tlsf_free(t, (void*)((uint8_t*)initial + sizeof(block_header_t))); + + return (void*)t; +} + +void* tlsf_realloc(void* tlsf, void* ptr, size_t size) { + if (!ptr) return tlsf_malloc(tlsf, size); + block_header_t* block = (block_header_t*)((uint8_t*)ptr - sizeof(block_header_t)); + if ((block->size & ~0x03) >= size) return ptr; + + void* new_ptr = tlsf_malloc(tlsf, size); + if (new_ptr) { + size_t old_size = block->size & ~0x03; + uint8_t* src = (uint8_t*)ptr; + uint8_t* dst = (uint8_t*)new_ptr; + for (size_t i = 0; i < old_size && i < size; i++) dst[i] = src[i]; + tlsf_free(tlsf, ptr); + } + return new_ptr; +}