Improve predication

[chris-chambers]

The IfConverter pass that is built in to LLVM is unable to take full advantage of the essentially-unbounded predication available in SBBM. Currently the most predication that ever really occurs as a result of if conversion is a single level. And then the presence of that level causes the if converter to ignore all further optimization possibilities. An improved pass should be developed that will take advantage of predicate nesting.

Notes:

• Predication occurs after register allocation, which means the cleanness of virtual registers has been lost. The nesting will need to either be recovered at this stage, or preserved from an earlier stage.
• LLVM's register scheduling may or may not be fully aware of predicate registers. The current code sidesteps any potential clobbering, but a real solution may be needed.
• It would also be a very good idea to support, at least, the predication of trivial loops. Complex ones may be difficult to deal with, but at least while true or while $boolean ought to be achievable.

[chris-chambers]

Waiting on #6.