Summary
The STM32F0 WWDG driver (src/watchdog/stm32f0_wwdg.c) triggers an immediate system reset when whal_Watchdog_Init is called on the STM32F091. The IWDG driver works correctly on the same board.
Observed behavior
- Calling
whal_Watchdog_Init starts the WWDG, but the system resets before the first whal_Watchdog_Refresh can be called
- Adding debug prints inside Init (UART output) delays execution enough that Init completes and a few refreshes succeed — suggesting a timing-sensitive issue
- With debug prints, reading CR after each step shows T6=1 throughout Init
- Without debug prints, the reset is immediate and consistent
- Tested with both
whal_Reg_Update (read-modify-write) and whal_Reg_Write (direct write) for the CR register — same behavior
- Matched ST HAL approach (
WRITE_REG(CR, WDGA | counter) for both Init and Refresh) — same behavior
Configuration
- Board: NUCLEO-F091RC (STM32F091CC)
- SYSCLK: 48 MHz (PLL: HSI/2 × 12)
- WWDG config: prescaler=3 (/8), window=0x7F, counter=0x7F
- Max WWDG timeout at 48 MHz PCLK: ~44ms
- WWDG clock enabled during
Board_Init (counter free-runs before test starts)
Summary
The STM32F0 WWDG driver (
src/watchdog/stm32f0_wwdg.c) triggers an immediate system reset whenwhal_Watchdog_Initis called on the STM32F091. The IWDG driver works correctly on the same board.Observed behavior
whal_Watchdog_Initstarts the WWDG, but the system resets before the firstwhal_Watchdog_Refreshcan be calledwhal_Reg_Update(read-modify-write) andwhal_Reg_Write(direct write) for the CR register — same behaviorWRITE_REG(CR, WDGA | counter)for both Init and Refresh) — same behaviorConfiguration
Board_Init(counter free-runs before test starts)