diff --git a/Library/Interface/7-Segments-Display/seg7display_1.0/component.xml b/Library/Interface/7-Segments-Display/seg7display_1.0/component.xml new file mode 100644 index 0000000..fa7f015 --- /dev/null +++ b/Library/Interface/7-Segments-Display/seg7display_1.0/component.xml @@ -0,0 +1,525 @@ + + + xilinx.com + XUP + seg7display + 1.0 + + + signal_reset + + + + + + + RST + + + reset + + + + + + POLARITY + ACTIVE_LOW + + + + + signal_clock + + + + + + + CLK + + + clk + + + + + + ASSOCIATED_RESET + reset + + + + + + + + xilinx_verilogsynthesis + Verilog Synthesis + verilogSource:vivado.xilinx.com:synthesis + verilog + seg7display + + xilinx_verilogsynthesis_view_fileset + + + + viewChecksum + 03e6e6df + + + + + xilinx_verilogbehavioralsimulation + Verilog Simulation + verilogSource:vivado.xilinx.com:simulation + verilog + seg7display + + xilinx_verilogbehavioralsimulation_view_fileset + + + + viewChecksum + 03e6e6df + + + + + xilinx_xpgui + UI Layout + :vivado.xilinx.com:xgui.ui + + xilinx_xpgui_view_fileset + + + + viewChecksum + e7093de9 + + + + + xilinx_readme + Readme + :vivado.xilinx.com:docs.readme + + xilinx_readme_view_fileset + + + + viewChecksum + 79ea81f5 + + + + + xilinx_utilityxitfiles + Utility XIT/TTCL + :vivado.xilinx.com:xit.util + + xilinx_utilityxitfiles_view_fileset + + + + viewChecksum + 9c3b79bd + + + + + + + x_l + + in + + 15 + 0 + + + + wire + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + x_h + + in + + 15 + 0 + + + + wire + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + 0 + + + + + + optional + false + + + + + + clk + + in + + + wire + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + reset + + in + + + wire + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + a_to_g + + out + + 6 + 0 + + + + reg + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + an_l + + out + + 3 + 0 + + + + wire + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + an_h + + out + + 3 + 0 + + + + wire + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + 1 + + + + + + optional + false + + + + + + dp_l + + out + + + reg + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + dp_h + + out + + + reg + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + 0 + + + + + + optional + false + + + + + + + + MODULES + Modules + 1 + + + DP_0 + Dp 0 + 1 + + + DP_1 + Dp 1 + 1 + + + DP_2 + Dp 2 + 1 + + + DP_3 + Dp 3 + 1 + + + DP_4 + Dp 4 + 1 + + + DP_5 + Dp 5 + 1 + + + DP_6 + Dp 6 + 1 + + + DP_7 + Dp 7 + 1 + + + + + + choices_0 + ACTIVE_HIGH + ACTIVE_LOW + + + choices_1 + 1 + 2 + + + choices_2 + 1 + 0 + + + choices_3 + 1 + 0 + + + choices_4 + 1 + 0 + + + choices_5 + 1 + 0 + + + choices_6 + 1 + 0 + + + choices_7 + 1 + 0 + + + choices_8 + 1 + 0 + + + choices_9 + 1 + 0 + + + + + xilinx_verilogsynthesis_view_fileset + + src/seg7display.v + verilogSource + CHECKSUM_03e6e6df + + + + xilinx_verilogbehavioralsimulation_view_fileset + + src/seg7display.v + verilogSource + + + + xilinx_xpgui_view_fileset + + xgui/seg7display_v1_0.tcl + tclSource + XGUI_VERSION_2 + CHECKSUM_98104f18 + + + + xilinx_readme_view_fileset + + doc/readme.txt + text + + + + xilinx_utilityxitfiles_view_fileset + + misc/xup.png + image + LOGO + + + + 7-Segment Display module to drive either Four or Eight 7-segments with Number of Modules as the Configuration parameter + + + MODULES + Number of Four 7-segments Modules + 1 + + + Component_Name + seg7display_v1_0 + + + DP_0 + Decimal Point for Segment 0 + 1 + + + DP_1 + Decimal Point for Segment 1 + 1 + + + DP_2 + Decimal Point for Segment 2 + 1 + + + DP_3 + Decimal Point for Segment 3 + 1 + + + DP_4 + Decimal Point for Segment 4 + 1 + + + DP_5 + Decimal Point for Segment 5 + 1 + + + DP_6 + Decimal Point for Segment 6 + 1 + + + DP_7 + Decimal Point for Segment 7 + 1 + + + + + + virtex7 + artix7 + kintex7 + zynq + + + XUP_LIB + + seg7display_v1_0 + XUP + http://www.xilinx.com/university + 6 + 2015-06-03T16:17:25Z + + C:/xup/IPI_Lib/seg7display/seg7display.srcs/sources_1/imports + C:/xup/IPI_Lib/seg7display/seg7display.srcs/sources_1/imports + + + + 2014.4 + + + + + + + + diff --git a/Library/Interface/7-Segments-Display/seg7display_1.0/doc/readme.txt b/Library/Interface/7-Segments-Display/seg7display_1.0/doc/readme.txt new file mode 100644 index 0000000..0c91113 --- /dev/null +++ b/Library/Interface/7-Segments-Display/seg7display_1.0/doc/readme.txt @@ -0,0 +1,32 @@ +Tool and version: Vivado 2014.4 +Target Families: Artix-7, Kintex-7, Virtex-7, and Zynq + +Introduction: +This interface IP displays either a 16-bit or 32-bit input, consists of either 4 or 8 nibbles data, on either one or two modules having 4 7-segments displays each. It expects either 16-bit or 32-bit input data, typically driven through GPIO port, 100 MHz clock input, and high-level reset signal. It outputs either 4 or 8 anode controls at approximately 50 Hz. The decimal point on the display is turned ON or OFF based on the configurable parameter of individual segment's decimal point. The section is based on configurable parameter MODULES. If MODULES=0 then it expects 16-bit input and will output 4 anode and time-multiplexed one decimal point signals, otherwise it expects 32-bit input and will output 8 anode and time-multiplexed two decimal point signals. + +Input/Output Ports: +Input: +clk - 100 MHz clock +reset - high-level logic +x_l - 16-bit input composed of four nibbles. Bits [3:0] is the least significant whose value is displayed on the right-most module. Bits [31:28] is the most significant whose value is displayed on the left-most segment of the right side module. +x_h - 16-bit input composed of four nibbles. Bits [3:0] is the least significant whose value is displayed on the right-most module. Bits [31:28] is the most significant whose value is displayed on the left-most segment of the left side module. + +Output: +a_to_g - 7-bit output controlling 7 segments. The least-significant bit controls segment "a" where as the most-significant bit controls segment "g". +an_l - 4-bit output controlling enabling of four anodes of the right-most module at roughly 50 Hz rate.The least-significant bit controls right-most segment where as the most-significant bit controls left-most segment. +an_h - 4-bit output controlling enabling of four anodes of the left-most module at roughly 50 Hz rate.The least-significant bit controls right-most segment where as the most-significant bit controls left-most segment. +dp_l - controls whether the corresponding decimal point to be turned ON or not. This will be to control right-most module +dp_h - controls whether the corresponding decimal point to be turned ON or not. This will be to control left-most module + +Setting up the library path: +Create a Vivado project. Click on the Project Settings, then click on the IP block in the left panel, click on the Add Repository... button, browse to the directory where this IP directory is located, and click Select. The IP entry should be visible in the IP in the Selected Repository. + +How to use the IP: +Step 1: Create a Vivado project +Step 2: Set the Project Settings to point to the IP path +Step 3: Create a block design +Step 4: Add the desired IP on the canvas, connect them, and add external input and output ports +Step 5: Create a HDL wrapper +Step 6: Add constraints file (.xdc) +Step 7: Synthesize, implement, and generate the bitstream +Step 8: Connect the board, download the bitstream, and varify the design diff --git a/Library/Interface/7-Segments-Display/seg7display_1.0/misc/xup.png b/Library/Interface/7-Segments-Display/seg7display_1.0/misc/xup.png new file mode 100644 index 0000000..6949927 Binary files /dev/null and b/Library/Interface/7-Segments-Display/seg7display_1.0/misc/xup.png differ diff --git a/Library/Interface/7-Segments-Display/seg7display_1.0/src/seg7display.v b/Library/Interface/7-Segments-Display/seg7display_1.0/src/seg7display.v new file mode 100644 index 0000000..96db90d --- /dev/null +++ b/Library/Interface/7-Segments-Display/seg7display_1.0/src/seg7display.v @@ -0,0 +1,143 @@ +`timescale 1ns / 1ps +///////////////////////////////////////////////////////////////// +// Module Name: seg7display +// Description: 7-segment display module driving either 4 or 8 7-segments module(s) +// Input clock is 100 MHz, reset is high-level logic, input x is either 4 or 8 nibbles input +// Decimal point is turned OFF +// Segments are refreshed at approximately 50 Hz. +// MODULES=1 will use 4 modules where as MODULES=2 will use 8 modules +///////////////////////////////////////////////////////////////// +// a +// --- +// f| | b +// | g | +// --- +// e| | c +// | | +// --- +// d +///////////////////////////////////////////////////////////////// + +module seg7display#(parameter MODULES=1, + DP_0=1, DP_1=1, DP_2=1, DP_3=1, + DP_4=1, DP_5=1, DP_6=1, DP_7=1) +( + input wire [15:0] x_l, + input wire [15:0] x_h=0, + input wire clk, + input wire reset, + output reg [6:0] a_to_g, + output wire [3:0] an_l, + output wire [3:0] an_h, + output reg dp_l, + output reg dp_h +); + +wire [2:0] s; +reg [3:0] digit; +wire [3:0] aen_l; +wire [3:0] aen_h; +wire [7:0] aen; +reg [7:0] an; +reg [20:0] clkdiv; + +wire [3:0] dp_l_i; +wire [3:0] dp_h_i; +wire [7:0] dpen; + +assign dp_l_i[0] = (DP_0) ? 1'b0 : 1'b1; +assign dp_l_i[1] = (DP_1) ? 1'b0 : 1'b1; +assign dp_l_i[2] = (DP_2) ? 1'b0 : 1'b1; +assign dp_l_i[3] = (DP_3) ? 1'b0 : 1'b1; +assign dp_h_i[0] = (DP_4) ? 1'b0 : 1'b1; +assign dp_h_i[1] = (DP_5) ? 1'b0 : 1'b1; +assign dp_h_i[2] = (DP_6) ? 1'b0 : 1'b1; +assign dp_h_i[3] = (DP_7) ? 1'b0 : 1'b1; +assign s = (MODULES==1) ? {1'b0,clkdiv[19:18]} : clkdiv[20:18]; +assign aen_l = 4'b1111; // all turned off initially +assign aen_h = 4'b1111; // all turned off initially +assign aen = (MODULES==1) ? {4'b0000,aen_l} : {aen_h,aen_l}; +assign {an_h,an_l}=an; + +assign dpen = (MODULES==1) ? {4'b0000,dp_l_i} : {dp_h_i,dp_l_i}; + +// MUX +always @(posedge clk) + case(s) + 0:digit = x_l[3:0]; // s is 000 -->0 ; digit gets assigned 4 bit value assigned to x[3:0] + 1:digit = x_l[7:4]; // s is 001 -->1 ; digit gets assigned 4 bit value assigned to x[7:4] + 2:digit = x_l[11:8]; // s is 010 -->2 ; digit gets assigned 4 bit value assigned to x[11:8] + 3:digit = x_l[15:12]; // s is 011 -->3 ; digit gets assigned 4 bit value assigned to x[15:12] + 4:digit = x_h[3:0]; // s is 100 -->4 ; digit gets assigned 4 bit value assigned to x[19:16] + 5:digit = x_h[7:4]; // s is 101 -->5 ; digit gets assigned 4 bit value assigned to x[23:20] + 6:digit = x_h[11:8]; // s is 110 -->6 ; digit gets assigned 4 bit value assigned to x[27:24] + 7:digit = x_h[15:12]; // s is 111 -->7 ; digit gets assigned 4 bit value assigned to x[31:28] + default:digit = x_l[3:0]; + endcase + +//decoder or truth-table for 7a_to_g display values +always @(*) + + case(digit) + //////////////gfedcba/////////// + 0:a_to_g = 7'b1000000; //0000 + 1:a_to_g = 7'b1111001; //0001 + 2:a_to_g = 7'b0100100; //0010 + 3:a_to_g = 7'b0110000; //0011 + 4:a_to_g = 7'b0011001; //0100 + 5:a_to_g = 7'b0010010; //0101 + 6:a_to_g = 7'b0000010; //0110 + 7:a_to_g = 7'b1111000; //0111 + 8:a_to_g = 7'b0000000; //1000 + 9:a_to_g = 7'b0010000; //1001 + 'hA:a_to_g = 7'b0001000; //1010 + 'hB:a_to_g = 7'b0000011; //1011 + 'hC:a_to_g = 7'b1000110; //1100 + 'hD:a_to_g = 7'b0100001; //1101 + 'hE:a_to_g = 7'b0000110; //1110 + 'hF:a_to_g = 7'b0001110; //1111 + default: a_to_g = 7'b0000000; // all segments ON + endcase + +always @(*)begin + if(MODULES==1) + begin + an=8'b00001111; + if(aen_l[s] == 1) + an[s] = 0; + end + else + begin + an=8'b11111111; + if(aen[s] == 1) + an[s] = 0; + end +end + +always @(*)begin + if(MODULES==1) + begin + if(aen_l[s] == 1) + dp_l = dpen[s]; + end + else + begin + if(aen[s] == 1) begin + if(s<4) + dp_l = dpen[s]; + else + dp_h = dpen[s]; + end + end +end + +//clkdiv +always @(posedge clk) begin + if ( reset == 1) + clkdiv <= 0; + else + clkdiv <= clkdiv+1; +end + +endmodule + diff --git a/Library/Interface/7-Segments-Display/seg7display_1.0/xgui/seg7display_v1_0.tcl b/Library/Interface/7-Segments-Display/seg7display_1.0/xgui/seg7display_v1_0.tcl new file mode 100644 index 0000000..2c6ec35 --- /dev/null +++ b/Library/Interface/7-Segments-Display/seg7display_1.0/xgui/seg7display_v1_0.tcl @@ -0,0 +1,156 @@ +# Definitional proc to organize widgets for parameters. +proc init_gui { IPINST } { + ipgui::add_param $IPINST -name "Component_Name" + #Adding Page + set Page_0 [ipgui::add_page $IPINST -name "Page 0"] + ipgui::add_param $IPINST -name "MODULES" -parent ${Page_0} + ipgui::add_static_text $IPINST -name "Number of Modules" -parent ${Page_0} -text {Selecting 1 will provide one 16-bit input and one 4-bit anodes output ports. +Selecting 2 will provide two 16-bit input and two 4-bit anodes output ports. +The IP expects 100 MHz input clock. + +Please select Decimal Points display in the other two tabs} + + #Adding Page + set Module_1_Related_Decimal_Points [ipgui::add_page $IPINST -name "Module 1 Related Decimal Points"] + ipgui::add_param $IPINST -name "DP_0" -parent ${Module_1_Related_Decimal_Points} -widget comboBox + ipgui::add_param $IPINST -name "DP_1" -parent ${Module_1_Related_Decimal_Points} -widget comboBox + ipgui::add_param $IPINST -name "DP_2" -parent ${Module_1_Related_Decimal_Points} -widget comboBox + ipgui::add_param $IPINST -name "DP_3" -parent ${Module_1_Related_Decimal_Points} -widget comboBox + + #Adding Page + set Module_2_Related_Decimal_Points [ipgui::add_page $IPINST -name "Module 2 Related Decimal Points"] + ipgui::add_param $IPINST -name "DP_4" -parent ${Module_2_Related_Decimal_Points} -widget comboBox + ipgui::add_param $IPINST -name "DP_5" -parent ${Module_2_Related_Decimal_Points} -widget comboBox + ipgui::add_param $IPINST -name "DP_6" -parent ${Module_2_Related_Decimal_Points} -widget comboBox + ipgui::add_param $IPINST -name "DP_7" -parent ${Module_2_Related_Decimal_Points} -widget comboBox + + +} + +proc update_PARAM_VALUE.DP_0 { PARAM_VALUE.DP_0 } { + # Procedure called to update DP_0 when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.DP_0 { PARAM_VALUE.DP_0 } { + # Procedure called to validate DP_0 + return true +} + +proc update_PARAM_VALUE.DP_1 { PARAM_VALUE.DP_1 } { + # Procedure called to update DP_1 when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.DP_1 { PARAM_VALUE.DP_1 } { + # Procedure called to validate DP_1 + return true +} + +proc update_PARAM_VALUE.DP_2 { PARAM_VALUE.DP_2 } { + # Procedure called to update DP_2 when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.DP_2 { PARAM_VALUE.DP_2 } { + # Procedure called to validate DP_2 + return true +} + +proc update_PARAM_VALUE.DP_3 { PARAM_VALUE.DP_3 } { + # Procedure called to update DP_3 when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.DP_3 { PARAM_VALUE.DP_3 } { + # Procedure called to validate DP_3 + return true +} + +proc update_PARAM_VALUE.DP_4 { PARAM_VALUE.DP_4 } { + # Procedure called to update DP_4 when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.DP_4 { PARAM_VALUE.DP_4 } { + # Procedure called to validate DP_4 + return true +} + +proc update_PARAM_VALUE.DP_5 { PARAM_VALUE.DP_5 } { + # Procedure called to update DP_5 when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.DP_5 { PARAM_VALUE.DP_5 } { + # Procedure called to validate DP_5 + return true +} + +proc update_PARAM_VALUE.DP_6 { PARAM_VALUE.DP_6 } { + # Procedure called to update DP_6 when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.DP_6 { PARAM_VALUE.DP_6 } { + # Procedure called to validate DP_6 + return true +} + +proc update_PARAM_VALUE.DP_7 { PARAM_VALUE.DP_7 } { + # Procedure called to update DP_7 when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.DP_7 { PARAM_VALUE.DP_7 } { + # Procedure called to validate DP_7 + return true +} + +proc update_PARAM_VALUE.MODULES { PARAM_VALUE.MODULES } { + # Procedure called to update MODULES when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.MODULES { PARAM_VALUE.MODULES } { + # Procedure called to validate MODULES + return true +} + + +proc update_MODELPARAM_VALUE.MODULES { MODELPARAM_VALUE.MODULES PARAM_VALUE.MODULES } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.MODULES}] ${MODELPARAM_VALUE.MODULES} +} + +proc update_MODELPARAM_VALUE.DP_0 { MODELPARAM_VALUE.DP_0 PARAM_VALUE.DP_0 } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.DP_0}] ${MODELPARAM_VALUE.DP_0} +} + +proc update_MODELPARAM_VALUE.DP_1 { MODELPARAM_VALUE.DP_1 PARAM_VALUE.DP_1 } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.DP_1}] ${MODELPARAM_VALUE.DP_1} +} + +proc update_MODELPARAM_VALUE.DP_2 { MODELPARAM_VALUE.DP_2 PARAM_VALUE.DP_2 } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.DP_2}] ${MODELPARAM_VALUE.DP_2} +} + +proc update_MODELPARAM_VALUE.DP_3 { MODELPARAM_VALUE.DP_3 PARAM_VALUE.DP_3 } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.DP_3}] ${MODELPARAM_VALUE.DP_3} +} + +proc update_MODELPARAM_VALUE.DP_4 { MODELPARAM_VALUE.DP_4 PARAM_VALUE.DP_4 } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.DP_4}] ${MODELPARAM_VALUE.DP_4} +} + +proc update_MODELPARAM_VALUE.DP_5 { MODELPARAM_VALUE.DP_5 PARAM_VALUE.DP_5 } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.DP_5}] ${MODELPARAM_VALUE.DP_5} +} + +proc update_MODELPARAM_VALUE.DP_6 { MODELPARAM_VALUE.DP_6 PARAM_VALUE.DP_6 } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.DP_6}] ${MODELPARAM_VALUE.DP_6} +} + +proc update_MODELPARAM_VALUE.DP_7 { MODELPARAM_VALUE.DP_7 PARAM_VALUE.DP_7 } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.DP_7}] ${MODELPARAM_VALUE.DP_7} +} + diff --git a/Library/Interface/PWM-Generator/PWM_gen_1.0/component.xml b/Library/Interface/PWM-Generator/PWM_gen_1.0/component.xml new file mode 100644 index 0000000..bb9c661 --- /dev/null +++ b/Library/Interface/PWM-Generator/PWM_gen_1.0/component.xml @@ -0,0 +1,286 @@ + + + xilinx.com + XUP + PWM_gen + 1.0 + + + signal_reset + + + + + + + RST + + + reset + + + + + + POLARITY + ACTIVE_LOW + + + + + signal_clock + + + + + + + CLK + + + clk + + + + + + ASSOCIATED_RESET + reset + + + + + + + + xilinx_verilogsynthesis + Verilog Synthesis + verilogSource:vivado.xilinx.com:synthesis + verilog + PWM_gen + + xilinx_verilogsynthesis_view_fileset + + + + viewChecksum + bf0b65df + + + + + xilinx_verilogbehavioralsimulation + Verilog Simulation + verilogSource:vivado.xilinx.com:simulation + verilog + PWM_gen + + xilinx_verilogbehavioralsimulation_view_fileset + + + + viewChecksum + bf0b65df + + + + + xilinx_xpgui + UI Layout + :vivado.xilinx.com:xgui.ui + + xilinx_xpgui_view_fileset + + + + viewChecksum + b65df710 + + + + + xilinx_readme + Readme + :vivado.xilinx.com:docs.readme + + xilinx_readme_view_fileset + + + + viewChecksum + 0bbb6a4b + + + + + xilinx_utilityxitfiles + Utility XIT/TTCL + :vivado.xilinx.com:xit.util + + xilinx_utilityxitfiles_view_fileset + + + + viewChecksum + 9c3b79bd + + + + + + + clk + + in + + + wire + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + reset + + in + + + wire + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + duty + + in + + 9 + 0 + + + + std_logic_vector + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + PWM + + out + + + reg + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + + + FREQ + Freq + 5000 + + + + + + choices_0 + ACTIVE_HIGH + ACTIVE_LOW + + + + + xilinx_verilogsynthesis_view_fileset + + src/PWM_gen.v + verilogSource + CHECKSUM_bf0b65df + + + + xilinx_verilogbehavioralsimulation_view_fileset + + src/PWM_gen.v + verilogSource + + + + xilinx_xpgui_view_fileset + + xgui/PWM_gen_v1_0.tcl + tclSource + XGUI_VERSION_2 + CHECKSUM_11916924 + + + + xilinx_readme_view_fileset + + doc/readme.txt + text + + + + xilinx_utilityxitfiles_view_fileset + + misc/xup.png + image + LOGO + + + + PWM Generator with dynamic duty cycle input at 1% resolution and configurable output frequency + + + FREQ + Freq + 5000 + + + Component_Name + PWM_gen_v1_0 + + + + + + virtex7 + artix7 + kintex7 + zynq + + + XUP_LIB + + PWM Generator + XUP + http://www.xilinx.com/university + 3 + 2015-04-21T15:48:05Z + + C:/xup/IPI_Lib/PWM_gen/PWM_gen.srcs/sources_1/imports + C:/xup/IPI_Lib/PWM_gen/PWM_gen.srcs/sources_1/imports + + + + 2014.4 + + + + + + + + diff --git a/Library/Interface/PWM-Generator/PWM_gen_1.0/doc/readme.txt b/Library/Interface/PWM-Generator/PWM_gen_1.0/doc/readme.txt new file mode 100644 index 0000000..7da1567 --- /dev/null +++ b/Library/Interface/PWM-Generator/PWM_gen_1.0/doc/readme.txt @@ -0,0 +1,27 @@ +Tool and version: Vivado 2014.4 +Target Families: Artix-7, Kintex-7, Virtex-7, and Zynq + +Introduction: +This interface IP generates a pulse width modulated output. It expects 100 MHz clock input and produces the output whose frequency is configurable in Hz and varying duty cycle based on the 10-bit duty cycle input. The duty cycle resolution is about 0.1 percent. + +Input/Output Ports: +Input: +clk - 100 MHz clock +reset - high-level logic +duty - 10-bit input providing about 0.1 percent resolution. + +Output: +PWM - Pulse Width Modulated output + +Setting up the library path: +Create a Vivado project. Click on the Project Settings, then click on the IP block in the left panel, click on the Add Repository... button, browse to the directory where this IP directory is located, and click Select. The IP entry should be visible in the IP in the Selected Repository. + +How to use the IP: +Step 1: Create a Vivado project +Step 2: Set the Project Settings to point to the IP path +Step 3: Create a block design +Step 4: Add the desired IP on the canvas, connect them, and add external input and output ports +Step 5: Create a HDL wrapper +Step 6: Add constraints file (.xdc) +Step 7: Synthesize, implement, and generate the bitstream +Step 8: Connect the board, download the bitstream, and varify the design diff --git a/Library/Interface/PWM-Generator/PWM_gen_1.0/misc/xup.png b/Library/Interface/PWM-Generator/PWM_gen_1.0/misc/xup.png new file mode 100644 index 0000000..6949927 Binary files /dev/null and b/Library/Interface/PWM-Generator/PWM_gen_1.0/misc/xup.png differ diff --git a/Library/Interface/PWM-Generator/PWM_gen_1.0/src/PWM_gen.v b/Library/Interface/PWM-Generator/PWM_gen_1.0/src/PWM_gen.v new file mode 100644 index 0000000..49e7e7d --- /dev/null +++ b/Library/Interface/PWM-Generator/PWM_gen_1.0/src/PWM_gen.v @@ -0,0 +1,38 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Module Name: PWM_gen +// Description: This IP expects 100 MHz input clock and generates the desired output +// at PWM output with the configurable frequency (in Hz) and duty cycle. +// The configurable frequency should be less or equal to 100 MHz and the duty cycle +// can vary in step of 1/1024, i.e. 0.0009765625 or approximately 0.1% +////////////////////////////////////////////////////////////////////////////////// + +module PWM_gen #(parameter FREQ = 5000)( + input wire clk, + input wire reset, + input [9:0] duty, + output reg PWM + ); + wire [31:0]count_max = 100_000_000/FREQ; + wire [31:0]count_duty = count_max*duty/1024; + reg [31:0]count; + + always@(posedge clk)begin + if(reset)begin + PWM <= 0; + count <= 0; + end + else if(count < count_max)begin + if(count < count_duty) + PWM <= 1; + else + PWM <= 0; + count <= count + 1; + end + else begin + count <= 0; + PWM <= 0; + end + end + +endmodule diff --git a/Library/Interface/PWM-Generator/PWM_gen_1.0/xgui/PWM_gen_v1_0.tcl b/Library/Interface/PWM-Generator/PWM_gen_1.0/xgui/PWM_gen_v1_0.tcl new file mode 100644 index 0000000..5b4919c --- /dev/null +++ b/Library/Interface/PWM-Generator/PWM_gen_1.0/xgui/PWM_gen_v1_0.tcl @@ -0,0 +1,26 @@ +# Definitional proc to organize widgets for parameters. +proc init_gui { IPINST } { + ipgui::add_param $IPINST -name "Component_Name" + #Adding Page + set Page_0 [ipgui::add_page $IPINST -name "Page 0"] + ipgui::add_param $IPINST -name "FREQ" -parent ${Page_0} + ipgui::add_static_text $IPINST -name "Input Frequency Requirements" -parent ${Page_0} -text {This IP expects 100 MHz input clock} + + +} + +proc update_PARAM_VALUE.FREQ { PARAM_VALUE.FREQ } { + # Procedure called to update FREQ when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.FREQ { PARAM_VALUE.FREQ } { + # Procedure called to validate FREQ + return true +} + + +proc update_MODELPARAM_VALUE.FREQ { MODELPARAM_VALUE.FREQ PARAM_VALUE.FREQ } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.FREQ}] ${MODELPARAM_VALUE.FREQ} +} + diff --git a/Library/Interface/UART/readme.md b/Library/Interface/UART/readme.md new file mode 100644 index 0000000..fd10b08 --- /dev/null +++ b/Library/Interface/UART/readme.md @@ -0,0 +1,2 @@ +This interface IP provides serial communication using 100 MHz input clock. +It supports 9600, 19200, 38400, 57600, and 115200 baud rates diff --git a/Library/Interface/UART/uart_1.0/component.xml b/Library/Interface/UART/uart_1.0/component.xml new file mode 100644 index 0000000..ae68fb9 --- /dev/null +++ b/Library/Interface/UART/uart_1.0/component.xml @@ -0,0 +1,433 @@ + + + xilinx.com + XUP + uart + 1.0 + + + signal_reset + + + + + + + RST + + + reset + + + + + + POLARITY + ACTIVE_LOW + + + + + signal_clock + + + + + + + CLK + + + clk + + + + + + ASSOCIATED_RESET + reset + + + + + + + + xilinx_verilogsynthesis + Verilog Synthesis + verilogSource:vivado.xilinx.com:synthesis + verilog + uart + + xilinx_verilogsynthesis_view_fileset + + + + viewChecksum + 47293e40 + + + + + xilinx_verilogbehavioralsimulation + Verilog Simulation + verilogSource:vivado.xilinx.com:simulation + verilog + uart + + xilinx_verilogbehavioralsimulation_view_fileset + + + + viewChecksum + 47293e40 + + + + + xilinx_xpgui + UI Layout + :vivado.xilinx.com:xgui.ui + + xilinx_xpgui_view_fileset + + + + viewChecksum + 2228b9af + + + + + xilinx_readme + Readme + :vivado.xilinx.com:docs.readme + + xilinx_readme_view_fileset + + + + viewChecksum + 0ea7f819 + + + + + xilinx_utilityxitfiles + Utility XIT/TTCL + :vivado.xilinx.com:xit.util + + xilinx_utilityxitfiles_view_fileset + + + + viewChecksum + 9c3b79bd + + + + + + + clk + + in + + + wire + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + reset + + in + + + wire + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + 0 + + + + + + optional + true + + + + + + rx + + in + + + wire + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + send + + in + + + wire + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + data_in + + in + + 7 + 0 + + + + wire + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + data_out + + out + + 7 + 0 + + + + wire + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + rx_done + + out + + + wire + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + + optional + true + + + + + + tx_done + + out + + + wire + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + + optional + true + + + + + + tx + + out + + + wire + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + + + DVSR + Dvsr + 651 + + + DATA_WIDTH + Data Width + 8 + + + + + + choices_0 + ACTIVE_HIGH + ACTIVE_LOW + + + choices_1 + 651 + 325 + 162 + 108 + 54 + + + + + xilinx_verilogsynthesis_view_fileset + + src/clk.v + verilogSource + + + src/uart_tx.v + verilogSource + + + src/uart_rx.v + verilogSource + + + src/uart.v + verilogSource + CHECKSUM_e2c62ce6 + + + + xilinx_verilogbehavioralsimulation_view_fileset + + src/clk.v + verilogSource + + + src/uart_tx.v + verilogSource + + + src/uart_rx.v + verilogSource + + + src/uart.v + verilogSource + + + + xilinx_xpgui_view_fileset + + xgui/uart_v1_0.tcl + tclSource + XGUI_VERSION_2 + CHECKSUM_3e63ef76 + + + + xilinx_readme_view_fileset + + doc/readme.txt + text + + + + xilinx_utilityxitfiles_view_fileset + + misc/xup.png + image LOGO + + + + Standalone UART IP supporting 9600, 1920,, 38400, 57600, and 115200 baud rate using configurable parameters BAUD and DATA_WIDTH + + + DVSR + BAUD Rate + 651 + + + DATA_WIDTH + Data Width + 8 + + + Component_Name + uart_v1_0 + + + NO_RESET + NO_RESET + false + + + Status_signals_not_required + Status_signals_not_required + false + + + + + + virtex7 + artix7 + kintex7 + zynq + + + XUP_LIB + + uart_v1_0 + XUP + http://www.xilinx.com/university + 2 + 2015-04-24T21:32:04Z + + C:/xup/IPI_Lib/uart/uart.srcs/sources_1/imports + C:/xup/IPI_Lib/uart/uart.srcs/sources_1/imports + + + + 2014.4 + + + + + + + + diff --git a/Library/Interface/UART/uart_1.0/doc/readme.txt b/Library/Interface/UART/uart_1.0/doc/readme.txt new file mode 100644 index 0000000..46312f7 --- /dev/null +++ b/Library/Interface/UART/uart_1.0/doc/readme.txt @@ -0,0 +1,33 @@ +Tool and version: Vivado 2014.4 +Target Families: Artix-7, Kintex-7, Virtex-7, and Zynq + +Introduction: +This interface IP provides serial communication using 100 MHz input clock. It supports 9600, 19200, 38400, 57600, and 115200 baud rates selected through configuration. + + +Input/Output Ports: +Input: +clk - 100 MHz clock +reset - high-level logic +rx - serial data input +send - a pulse to start transmitting the data +data-in - parallel data to be serially transmitted + +Output: +data-out - parallel data received +rx_done - status signal indicating data is received +tx_done - status signal indicating data transmission is completed +tx - serial data output + +Setting up the library path: +Create a Vivado project. Click on the Project Settings, then click on the IP block in the left panel, click on the Add Repository... button, browse to the directory where this IP directory is located, and click Select. The IP entry should be visible in the IP in the Selected Repository. + +How to use the IP: +Step 1: Create a Vivado project +Step 2: Set the Project Settings to point to the IP path +Step 3: Create a block design +Step 4: Add the desired IP on the canvas, connect them, and add external input and output ports +Step 5: Create a HDL wrapper +Step 6: Add constraints file (.xdc) +Step 7: Synthesize, implement, and generate the bitstream +Step 8: Connect the board, download the bitstream, and varify the design diff --git a/Library/Interface/UART/uart_1.0/misc/xup.png b/Library/Interface/UART/uart_1.0/misc/xup.png new file mode 100644 index 0000000..6949927 Binary files /dev/null and b/Library/Interface/UART/uart_1.0/misc/xup.png differ diff --git a/Library/Interface/UART/uart_1.0/src/clk.v b/Library/Interface/UART/uart_1.0/src/clk.v new file mode 100644 index 0000000..26d3217 --- /dev/null +++ b/Library/Interface/UART/uart_1.0/src/clk.v @@ -0,0 +1,27 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Module Name: clk +////////////////////////////////////////////////////////////////////////////////// + +module clk #(parameter DVSR = 651) ( + input wire clk,reset, + output reg tick + ); + + reg [31:0]count; + + always@(posedge clk) + if(reset)begin + tick <= 0; + count <= 0; + end + else if(count < DVSR)begin + tick <= 0; + count <= count + 1'b1; + end + else begin + tick <= 1; + count <= 0; + end + +endmodule diff --git a/Library/Interface/UART/uart_1.0/src/uart.v b/Library/Interface/UART/uart_1.0/src/uart.v new file mode 100644 index 0000000..cbe8bb6 --- /dev/null +++ b/Library/Interface/UART/uart_1.0/src/uart.v @@ -0,0 +1,44 @@ +`timescale 1ns / 1ps +///////////////////////////////////////////////////////////////// +// Module Name: uart +// Description: Default baud is 9600 with 100 MHz input clock +///////////////////////////////////////////////////////////////// + +module uart #(parameter DVSR = 651,DATA_WIDTH = 8) ( + input wire clk,reset, + input wire rx,send, + input wire [DATA_WIDTH-1:0]data_in, + output wire [DATA_WIDTH-1:0]data_out, + output wire rx_done,tx_done, + output wire tx + ); + + wire s_tick; + wire [DATA_WIDTH-1:0]rx_reg; + + clk #(.DVSR(DVSR)) CLK_div( + .clk(clk), + .reset(reset), + .tick(s_tick) + ); + + uart_rx #(.DATA_WIDTH(DATA_WIDTH)) RX( + .clk(clk), + .reset(reset), + .s_tick(s_tick), + .rx(rx), + .dout(data_out), + .rx_done(rx_done) + ); + + uart_tx #(.DATA_WIDTH(DATA_WIDTH)) TX( + .clk(clk), + .reset(reset), + .s_tick(s_tick), + .din(data_in), + .tx_start(send), + .tx(tx), + .tx_done(tx_done) + ); + +endmodule diff --git a/Library/Interface/UART/uart_1.0/src/uart_rx.v b/Library/Interface/UART/uart_1.0/src/uart_rx.v new file mode 100644 index 0000000..fc624a3 --- /dev/null +++ b/Library/Interface/UART/uart_1.0/src/uart_rx.v @@ -0,0 +1,98 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Module Name: uart_rx +////////////////////////////////////////////////////////////////////////////////// + + +module uart_rx #(parameter DATA_WIDTH = 8)( + input wire clk,reset, + input wire rx,s_tick, + output wire [DATA_WIDTH-1:0]dout, + output reg rx_done + ); + + localparam [1:0] + idle = 2'b00, + start = 2'b01, + data = 2'b10, + stop = 2'b11; + + reg [1:0]state,state_next; + reg [3:0]s,s_next; + reg [3:0]n,n_next; + reg [DATA_WIDTH-1:0]rx_reg,rx_next; + reg rx_done_next; + + always@(posedge clk) + if(reset)begin + state <= 0; + s <= 0; + n <= 0; + rx_reg <= 0; + rx_done <= 0; + end + else begin + state <= state_next; + s <= s_next; + n <= n_next; + rx_reg <= rx_next; + rx_done <= rx_done_next; + end + + always@(state or s_tick or rx)begin + state_next = state; + s_next = s; + n_next = n; + rx_next = rx_reg; + rx_done_next = rx_done; + case(state) + idle:begin + if(~rx)begin + state_next = start; + s_next = 0; + rx_done_next = 0; + end + end + + start:begin + if(s_tick)begin + s_next = s + 1'b1; + if(s == 4'd7)begin + state_next = data; + s_next = 0; + n_next = 0; + end + end + end + + data:begin + if(s_tick) + if(s == 4'd15)begin + rx_next = {rx,rx_reg[7:1]}; + s_next = 0; + if(n == DATA_WIDTH-1) + state_next = stop; + else + n_next = n + 1'b1; + end + else + s_next = s + 1; + end + + stop:begin + if(s_tick) + if(s == 15)begin + state_next = idle; + rx_done_next = 1'b1; + end + else + s_next = s + 1'b1; + end + + endcase + + end + + assign dout = rx_done ? rx_reg : 8'b0; + +endmodule diff --git a/Library/Interface/UART/uart_1.0/src/uart_tx.v b/Library/Interface/UART/uart_1.0/src/uart_tx.v new file mode 100644 index 0000000..6537fb2 --- /dev/null +++ b/Library/Interface/UART/uart_1.0/src/uart_tx.v @@ -0,0 +1,107 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// + +// Module Name: uart_tx + +////////////////////////////////////////////////////////////////////////////////// + + +module uart_tx #(parameter DATA_WIDTH = 8)( + input wire clk,reset,s_tick,tx_start, + input wire [DATA_WIDTH-1:0]din, + output reg tx, + output reg tx_done + ); + + localparam [1:0] + idle = 2'b00, + start = 2'b01, + data = 2'b10, + stop = 2'b11; + + reg [1:0]state,state_next; + reg [DATA_WIDTH-1:0]data_reg,data_next; + reg tx_next,tx_done_next; + reg [3:0]s,s_next; + reg [3:0]n,n_next; //the max number of bits is 16 + + always@(posedge clk) + if(reset)begin + state <= 0; + tx <= 0; + s <= 0; + n <= 0; + tx_done <= 0; + data_reg <= 0; + end + else begin + state <= state_next; + tx <= tx_next; + s <= s_next; + n <= n_next; + tx_done <= tx_done_next; + data_reg <= data_next; + end + + always@(state or s_tick or tx_start)begin + state_next = state; + tx_next = tx; + s_next = s; + n_next = n; + tx_done_next = tx_done; + data_next = data_reg; + case(state) + idle:begin + if(tx_start)begin + data_next= din; + s_next = 0; + state_next = start; + tx_done_next = 0; + end + end + + start:begin + tx_next = 0; + if(s_tick) + if(s == 4'd15)begin + state_next = data; + s_next = 0; + n_next = 0; + end + else + s_next = s + 1'b1; + end + + data:begin + tx_next = data_reg[0]; + if(s_tick) + if(s == 4'd15)begin + data_next = data_reg >>1; + s_next = 0; + if(n == DATA_WIDTH-1)begin + state_next = stop; + n_next = 0; + end + else + n_next = n + 1'b1; + end + else + s_next = s + 1'b1; + end + + stop:begin + tx_next = 1'b1; + if(s_tick) + if(s == 15)begin + tx_done_next = 1'b1; + state_next = idle; + end + else + s_next = s + 1'b1; + end + + endcase + end + + +endmodule diff --git a/Library/Interface/UART/uart_1.0/xgui/uart_v1_0.tcl b/Library/Interface/UART/uart_1.0/xgui/uart_v1_0.tcl new file mode 100644 index 0000000..6ca8ab7 --- /dev/null +++ b/Library/Interface/UART/uart_1.0/xgui/uart_v1_0.tcl @@ -0,0 +1,61 @@ +# Definitional proc to organize widgets for parameters. +proc init_gui { IPINST } { + ipgui::add_param $IPINST -name "Component_Name" + #Adding Page + set Page_0 [ipgui::add_page $IPINST -name "Page 0"] + ipgui::add_param $IPINST -name "DATA_WIDTH" -parent ${Page_0} + ipgui::add_param $IPINST -name "DVSR" -parent ${Page_0} + set Status_signals_not_required [ipgui::add_param $IPINST -name "Status_signals_not_required" -parent ${Page_0}] + set_property tooltip {Status signals not required} ${Status_signals_not_required} + ipgui::add_param $IPINST -name "NO_RESET" -parent ${Page_0} + + +} + +proc update_PARAM_VALUE.DATA_WIDTH { PARAM_VALUE.DATA_WIDTH } { + # Procedure called to update DATA_WIDTH when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.DATA_WIDTH { PARAM_VALUE.DATA_WIDTH } { + # Procedure called to validate DATA_WIDTH + return true +} + +proc update_PARAM_VALUE.DVSR { PARAM_VALUE.DVSR } { + # Procedure called to update DVSR when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.DVSR { PARAM_VALUE.DVSR } { + # Procedure called to validate DVSR + return true +} + +proc update_PARAM_VALUE.NO_RESET { PARAM_VALUE.NO_RESET } { + # Procedure called to update NO_RESET when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.NO_RESET { PARAM_VALUE.NO_RESET } { + # Procedure called to validate NO_RESET + return true +} + +proc update_PARAM_VALUE.Status_signals_not_required { PARAM_VALUE.Status_signals_not_required } { + # Procedure called to update Status_signals_not_required when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.Status_signals_not_required { PARAM_VALUE.Status_signals_not_required } { + # Procedure called to validate Status_signals_not_required + return true +} + + +proc update_MODELPARAM_VALUE.DVSR { MODELPARAM_VALUE.DVSR PARAM_VALUE.DVSR } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.DVSR}] ${MODELPARAM_VALUE.DVSR} +} + +proc update_MODELPARAM_VALUE.DATA_WIDTH { MODELPARAM_VALUE.DATA_WIDTH PARAM_VALUE.DATA_WIDTH } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.DATA_WIDTH}] ${MODELPARAM_VALUE.DATA_WIDTH} +} + diff --git a/Library/Interface/VGA-Display/vga_1.0/component.xml b/Library/Interface/VGA-Display/vga_1.0/component.xml new file mode 100644 index 0000000..ee51e09 --- /dev/null +++ b/Library/Interface/VGA-Display/vga_1.0/component.xml @@ -0,0 +1,318 @@ + + + xilinx.com + XUP + vga + 1.0 + + + signal_reset + + + + + + + RST + + + reset + + + + + + POLARITY + ACTIVE_LOW + + + + + + + + xilinx_verilogsynthesis + Verilog Synthesis + verilogSource:vivado.xilinx.com:synthesis + verilog + vga + + xilinx_verilogsynthesis_view_fileset + + + + viewChecksum + 3ea933bb + + + + + xilinx_verilogbehavioralsimulation + Verilog Simulation + verilogSource:vivado.xilinx.com:simulation + verilog + vga + + xilinx_verilogbehavioralsimulation_view_fileset + + + + viewChecksum + 3ea933bb + + + + + xilinx_xpgui + UI Layout + :vivado.xilinx.com:xgui.ui + + xilinx_xpgui_view_fileset + + + + viewChecksum + 93ce4ea1 + + + + + xilinx_readme + Readme + :vivado.xilinx.com:docs.readme + + xilinx_readme_view_fileset + + + + viewChecksum + c564d9a1 + + + + + xilinx_utilityxitfiles + Utility XIT/TTCL + :vivado.xilinx.com:xit.util + + xilinx_utilityxitfiles_view_fileset + + + + viewChecksum + 2c94d2b2 + + + + + + + pclk + + in + + + wire + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + reset + + in + + + wire + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + hsync + + out + + + wire + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + vsync + + out + + + wire + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + valid + + out + + + wire + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + h_cnt + + out + + 10 + 0 + + + + wire + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + v_cnt + + out + + 9 + 0 + + + + wire + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + + + TYPE + Type + 0 + + + + + + choices_0 + ACTIVE_HIGH + ACTIVE_LOW + + + choices_1 + 0 + 1 + 2 + 3 + + + + + xilinx_verilogsynthesis_view_fileset + + src/vga.v + verilogSource + CHECKSUM_3ea933bb + + + + xilinx_verilogbehavioralsimulation_view_fileset + + src/vga.v + verilogSource + + + + xilinx_xpgui_view_fileset + + xgui/vga_v1_0.tcl + tclSource + XGUI_VERSION_2 + CHECKSUM_8bc1aea2 + + + + xilinx_readme_view_fileset + + doc/readme.txt + text + + + + xilinx_utilityxitfiles_view_fileset + + misc/xup.png + image + LOGO + + + gui/vga_v1_0.gtcl + GTCL + + + + Display controller supporting VGA, SVGA, XGA, and SXGA selected through configurable parameter TYPE + + + TYPE + Video Standards + 0 + + + Component_Name + vga_v1_0 + + + + + + virtex7 + artix7 + kintex7 + zynq + + + XUP_LIB + + vga_v1_0 + XUP + http://www.xilinx.com/university + 16 + 2015-04-23T18:22:24Z + + C:/xup/IPI_Lib/vga/vga.srcs/sources_1/imports + C:/xup/IPI_Lib/vga/vga.srcs/sources_1/imports + + + + 2014.4 + + + + + + + + diff --git a/Library/Interface/VGA-Display/vga_1.0/doc/readme.txt b/Library/Interface/VGA-Display/vga_1.0/doc/readme.txt new file mode 100644 index 0000000..4220f2a --- /dev/null +++ b/Library/Interface/VGA-Display/vga_1.0/doc/readme.txt @@ -0,0 +1,36 @@ +Tool and version: Vivado 2014.4 +Target Families: Artix-7, Kintex-7, Virtex-7, and Zynq + +Introduction: +This interface IP generates timing signals (HSYNC, VSYNC, and Video Valid) along with horizontal and vertical positions. It provides configurable parameter of VGA standards. The standards supported are: +VGA- 640x480 requiring 25 MHz pixel clock input +SVGA- 800x600 requiring 40 MHz pixel clock input +XVGA- 1024x768 requiring 65 MHz pixel clock input +SXGA- 1280x1024 requiring 108 MHz pixel clock input + + +Input/Output Ports: +Input: +pclk - varies depending on the TYPE +reset - high-level logic + +Output: +hsync - Horizontal sync timing signal +vsync - Vertical sync timing signal +valid - viewable (or active) video +h_cnt[10:0] - current horizontal position of a pixel +v_cnt[10:0] - current vertical position of a pixel + + +Setting up the library path: +Create a Vivado project. Click on the Project Settings, then click on the IP block in the left panel, click on the Add Repository... button, browse to the directory where this IP directory is located, and click Select. The IP entry should be visible in the IP in the Selected Repository. + +How to use the IP: +Step 1: Create a Vivado project +Step 2: Set the Project Settings to point to the IP path +Step 3: Create a block design +Step 4: Add the desired IP on the canvas, connect them, and add external input and output ports +Step 5: Create a HDL wrapper +Step 6: Add constraints file (.xdc) +Step 7: Synthesize, implement, and generate the bitstream +Step 8: Connect the board, download the bitstream, and varify the design diff --git a/Library/Interface/VGA-Display/vga_1.0/gui/vga_v1_0.gtcl b/Library/Interface/VGA-Display/vga_1.0/gui/vga_v1_0.gtcl new file mode 100644 index 0000000..c058570 --- /dev/null +++ b/Library/Interface/VGA-Display/vga_1.0/gui/vga_v1_0.gtcl @@ -0,0 +1,3 @@ +# This file is automatically written. Do not modify. +proc gen_USERPARAMETER_H_POS_SIZE_ENABLEMENT {HPOS } {expr $HPOS} +proc gen_USERPARAMETER_V_POS_SIZE_ENABLEMENT {VPOS } {expr $VPOS} diff --git a/Library/Interface/VGA-Display/vga_1.0/misc/xup.png b/Library/Interface/VGA-Display/vga_1.0/misc/xup.png new file mode 100644 index 0000000..6949927 Binary files /dev/null and b/Library/Interface/VGA-Display/vga_1.0/misc/xup.png differ diff --git a/Library/Interface/VGA-Display/vga_1.0/src/vga.v b/Library/Interface/VGA-Display/vga_1.0/src/vga.v new file mode 100644 index 0000000..a80864a --- /dev/null +++ b/Library/Interface/VGA-Display/vga_1.0/src/vga.v @@ -0,0 +1,135 @@ +`timescale 1ns / 1ps +///////////////////////////////////////////////////////////////// +// Module Name: vga +///////////////////////////////////////////////////////////////// + +module vga #( + parameter [1:0] TYPE = 0 // 0=VGA, 1=SVGA, 2=XGA, 3=SXGA + ) + ( + input wire pclk,reset, + output wire hsync,vsync,valid, + output wire [10:0]h_cnt, + output wire [9:0]v_cnt + ); + + reg [10:0]pixel_cnt; + reg [10:0]line_cnt; + reg hsync_i,vsync_i,hactive,vactive, hsync_default, vsync_default; + integer HD, HF, HA, HB, HT, VD, VF, VA, VB, VT; + + always @(TYPE) + case(TYPE) + 2'b00 : begin + HD = 640; + HF = 48; + HA = 16; + HB = 96; + HT = 800; // + VD = 480; + VF = 33; + VA = 10; + VB = 2; + VT = 525; + hsync_default = 1'b1; + vsync_default = 1'b1; + end + 2'b01 : begin + HD = 800; + HF = 88; + HA = 40; + HB = 128; + HT = 1056; + VD = 600; + VF = 27; + VA = 1; + VB = 4; + VT = 632; + hsync_default = 1'b0; + vsync_default = 1'b0; + end + 2'b10 : begin + HD = 1024; + HF = 160; + HA = 24; + HB = 136; + HT = 1344; + VD = 768; + VF = 35; + VA = 3; + VB = 6; + VT = 812; + hsync_default = 1'b1; + vsync_default = 1'b1; + end + 2'b11 : begin + HD = 1280; + HF = 248; + HA = 48; + HB = 112; + HT = 1688; + VD = 1024; + VF = 41; + VA = 1; + VB = 3; + VT = 1066; + hsync_default = 1'b0; + vsync_default = 1'b0; + end + default: begin + HD = 640; + HF = 48; + HA = 16; + HB = 96; + HT = 800; + VD = 480; + VF = 33; + VA = 10; + VB = 2; + VT = 525; + hsync_default = 1'b1; + vsync_default = 1'b1; + end + endcase + + always@(posedge pclk) + if(reset) + pixel_cnt <= 0; + else if(pixel_cnt < (HT - 1)) + pixel_cnt <= pixel_cnt + 1; + else + pixel_cnt <= 0; + + always@(posedge pclk) + if(reset) + hsync_i <= hsync_default; + else if((pixel_cnt >= (HD + HF - 1))&&(pixel_cnt < (HD + HF + HA - 1))) + hsync_i <= ~hsync_default; + else + hsync_i <= hsync_default; + + always@(posedge pclk) + if(reset) + line_cnt <= 0; + else if(pixel_cnt == (HT -1)) + if(line_cnt < (VT - 1)) + line_cnt <= line_cnt + 1; + else + line_cnt <= 0; + + always@(posedge pclk) + if(reset) + vsync_i <= vsync_default; + else if((line_cnt >= (VD + VF - 1))&&(line_cnt < (VD + VF + VA - 1))) + vsync_i <= ~vsync_default; + else + vsync_i <= vsync_default; + + assign hsync = hsync_i; + assign vsync = vsync_i; + assign valid = ((pixel_cnt < HD) && (line_cnt < VD)); + + assign h_cnt = (pixel_cnt < HD) ? pixel_cnt:11'd0; + assign v_cnt = (line_cnt < VD) ? line_cnt[9:0]:10'd0; + +endmodule diff --git a/Library/Interface/VGA-Display/vga_1.0/xgui/vga_v1_0.tcl b/Library/Interface/VGA-Display/vga_1.0/xgui/vga_v1_0.tcl new file mode 100644 index 0000000..ad87fde --- /dev/null +++ b/Library/Interface/VGA-Display/vga_1.0/xgui/vga_v1_0.tcl @@ -0,0 +1,35 @@ + +# Loading additional proc with user specified bodies to compute parameter values. +source [file join [file dirname [file dirname [info script]]] gui/vga_v1_0.gtcl] + +# Definitional proc to organize widgets for parameters. +proc init_gui { IPINST } { + ipgui::add_param $IPINST -name "Component_Name" + #Adding Page + set Page_0 [ipgui::add_page $IPINST -name "Page 0"] + ipgui::add_param $IPINST -name "TYPE" -parent ${Page_0} + ipgui::add_static_text $IPINST -name "Input Clock" -parent ${Page_0} -text {All supported video standards requires 60 Hz refresh rate monitor + +VGA - Requires 25 MHz pixel clock +SVGA - Requires 40 MHz pixel clock +XVGA - Requires 65 MHz pixel clock +SXGA - Requires 108 MHz pixel clock} + + +} + +proc update_PARAM_VALUE.TYPE { PARAM_VALUE.TYPE } { + # Procedure called to update TYPE when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.TYPE { PARAM_VALUE.TYPE } { + # Procedure called to validate TYPE + return true +} + + +proc update_MODELPARAM_VALUE.TYPE { MODELPARAM_VALUE.TYPE PARAM_VALUE.TYPE } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.TYPE}] ${MODELPARAM_VALUE.TYPE} +} + diff --git a/Library/Interface/VGA-Display/vga_1.0/xgui/vga_v1_0.tcl~ b/Library/Interface/VGA-Display/vga_1.0/xgui/vga_v1_0.tcl~ new file mode 100644 index 0000000..800bcf5 --- /dev/null +++ b/Library/Interface/VGA-Display/vga_1.0/xgui/vga_v1_0.tcl~ @@ -0,0 +1,42 @@ + +# Additional procs with user specified bodies to compute parameter values. +proc gen_USERPARAMETER_H_POS_SIZE_ENABLEMENT {HPOS } {expr $HPOS} +proc gen_HDLPARAMETER_RST_POLARITY_VALUE {RST_POLARITY } {expr { ( $RST_POLARITY eq "ACTIVE_HIGH" ) ? 1 : 0}} +proc gen_HDLPARAMETER_RESET_POLARITY_VALUE {RESET_POLARITY } {expr { ( $RESET_POLARITY eq "ACTIVE_HIGH" ) ? 1 : 0}} +proc gen_HDLPARAMETER_TOTAL_PERIOD_VALUE {PULSE_PERIOD RST_PERIOD } {expr { ( $PULSE_PERIOD > 0 ) ? [expr $PULSE_PERIOD - $RST_PERIOD] : 0 }} +proc gen_USERPARAMETER_RESET_POLARITY_ENABLEMENT {CLOCK_TYPE } {expr { $CLOCK_TYPE eq "Single_Ended"} } +proc gen_HDLPARAMETER_CLOCK_PERIOD_VALUE {FREQ_HZ } {expr { 1000000000.0 / $FREQ_HZ }} +proc gen_USERPARAMETER_INITIAL_RESET_CLOCK_CYCLES_ENABLEMENT {CLOCK_TYPE } {expr { $CLOCK_TYPE eq "Single_Ended"} } +proc gen_USERPARAMETER_V_POS_SIZE_ENABLEMENT {VPOS } {expr $VPOS} + +# Definitional proc to organize widgets for parameters. +proc init_gui { IPINST } { + ipgui::add_param $IPINST -name "Component_Name" + #Adding Page + set Page_0 [ipgui::add_page $IPINST -name "Page 0"] + ipgui::add_param $IPINST -name "TYPE" -parent ${Page_0} + ipgui::add_static_text $IPINST -name "Input Clock" -parent ${Page_0} -text {All supported video standards requires 60 Hz refresh rate monitor + +VGA - Requires 25 MHz pixel clock +SVGA - Requires 40 MHz pixel clock +XVGA - Requires 65 MHz pixel clock +SXGA - Requires 108 MHz pixel clock} + + +} + +proc update_PARAM_VALUE.TYPE { PARAM_VALUE.TYPE } { + # Procedure called to update TYPE when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.TYPE { PARAM_VALUE.TYPE } { + # Procedure called to validate TYPE + return true +} + + +proc update_MODELPARAM_VALUE.TYPE { MODELPARAM_VALUE.TYPE PARAM_VALUE.TYPE } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.TYPE}] ${MODELPARAM_VALUE.TYPE} +} + diff --git a/Library/Interface/debounce/debounce_1.0/component.xml b/Library/Interface/debounce/debounce_1.0/component.xml new file mode 100644 index 0000000..ab9f8a8 --- /dev/null +++ b/Library/Interface/debounce/debounce_1.0/component.xml @@ -0,0 +1,315 @@ + + + xilinx.com + XUP + debounce + 1.0 + + + signal_reset + + + + + + + RST + + + reset + + + + + + POLARITY + ACTIVE_LOW + + + + + signal_clock + + + + + + + CLK + + + clk + + + + + + ASSOCIATED_RESET + reset + + + + + + + + xilinx_verilogsynthesis + Verilog Synthesis + verilogSource:vivado.xilinx.com:synthesis + verilog + debounce + + xilinx_verilogsynthesis_view_fileset + + + + viewChecksum + f8c53da7 + + + + + xilinx_verilogbehavioralsimulation + Verilog Simulation + verilogSource:vivado.xilinx.com:simulation + verilog + debounce + + xilinx_verilogbehavioralsimulation_view_fileset + + + + viewChecksum + f8c53da7 + + + + + xilinx_verilogtestbench + Verilog Test Bench + verilogSource:vivado.xilinx.com:simulation.testbench + verilog + debounce_tb + + xilinx_verilogtestbench_view_fileset + + + + viewChecksum + 6dd585e6 + + + + + xilinx_xpgui + UI Layout + :vivado.xilinx.com:xgui.ui + + xilinx_xpgui_view_fileset + + + + viewChecksum + 23a72104 + + + + + xilinx_readme + Readme + :vivado.xilinx.com:docs.readme + + xilinx_readme_view_fileset + + + + viewChecksum + 5d842955 + + + + + xilinx_utilityxitfiles + Utility XIT/TTCL + :vivado.xilinx.com:xit.util + + xilinx_utilityxitfiles_view_fileset + + + + viewChecksum + 9c3b79bd + + + + + + + clk + + in + + + wire + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + reset + + in + + + wire + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + i + + in + + + wire + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + o + + out + + + wire + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + + + DEBOUNCE_TIME + Debounce Time + 0.01 + + + CLK_INPUT + Clk Input + 100 + + + + + + choices_0 + ACTIVE_HIGH + ACTIVE_LOW + + + + + xilinx_verilogsynthesis_view_fileset + + src/debounce.v + verilogSource + CHECKSUM_f8c53da7 + + + + xilinx_verilogbehavioralsimulation_view_fileset + + src/debounce.v + verilogSource + + + + xilinx_verilogtestbench_view_fileset + + src/debounce_tb.v + verilogSource + + + + xilinx_xpgui_view_fileset + + xgui/debounce_v1_0.tcl + tclSource + XGUI_VERSION_2 + CHECKSUM_3d2a98b5 + + + + xilinx_readme_view_fileset + + doc/readme.txt + text + + + + xilinx_utilityxitfiles_view_fileset + + misc/xup.png + image + LOGO + + + + Debounce circuit to debounce an input + + + DEBOUNCE_TIME + Debounce Time in Seconds + 0.01 + + + CLK_INPUT + Clk Input in MHz + 100 + + + Component_Name + debounce_v1_0 + + + + + + virtex7 + artix7 + kintex7 + zynq + + + XUP_LIB + + debounce_v1_0 + XUP + http://www.xilinx.com/university + 4 + 2015-04-21T17:54:10Z + + C:/xup/IPI_Lib/debounce/debounce.srcs + C:/xup/IPI_Lib/debounce/debounce.srcs + + + + 2014.4 + + + + + + + + diff --git a/Library/Interface/debounce/debounce_1.0/doc/readme.txt b/Library/Interface/debounce/debounce_1.0/doc/readme.txt new file mode 100644 index 0000000..537f515 --- /dev/null +++ b/Library/Interface/debounce/debounce_1.0/doc/readme.txt @@ -0,0 +1,28 @@ +Tool and version: Vivado 2014.4 +Target Families: Artix-7, Kintex-7, Virtex-7, and Zynq + +Introduction: +This interface IP debounces input typically coming from a push-button and output. It expects a clock, by default 100 MHz, an input from a button, and a high level reset input.It outputs a debounced output. The default debounce time is 10 ms. +The configurable parameters are clock input frequency in MHz and the debounce time in second. + +Input/Output Ports: +Input: +clk - 100 MHz clock, default, but can be different +reset - high-level logic +i - an input which needs to be debounced. + +Output: +o - debounced output + +Setting up the library path: +Create a Vivado project. Click on the Project Settings, then click on the IP block in the left panel, click on the Add Repository... button, browse to the directory where this IP directory is located, and click Select. The IP entry should be visible in the IP in the Selected Repository. + +How to use the IP: +Step 1: Create a Vivado project +Step 2: Set the Project Settings to point to the IP path +Step 3: Create a block design +Step 4: Add the desired IP on the canvas, connect them, and add external input and output ports +Step 5: Create a HDL wrapper +Step 6: Add constraints file (.xdc) +Step 7: Synthesize, implement, and generate the bitstream +Step 8: Connect the board, download the bitstream, and varify the design diff --git a/Library/Interface/debounce/debounce_1.0/misc/xup.png b/Library/Interface/debounce/debounce_1.0/misc/xup.png new file mode 100644 index 0000000..6949927 Binary files /dev/null and b/Library/Interface/debounce/debounce_1.0/misc/xup.png differ diff --git a/Library/Interface/debounce/debounce_1.0/src/debounce.v b/Library/Interface/debounce/debounce_1.0/src/debounce.v new file mode 100644 index 0000000..f70ee42 --- /dev/null +++ b/Library/Interface/debounce/debounce_1.0/src/debounce.v @@ -0,0 +1,85 @@ +`timescale 1ns / 1ps +///////////////////////////////////////////////////////////////// +// Module Name: debounce +// Description: This IP will debounce an input with a debounce period +// entered through configurable parameter. The default is 10 ms +// It expects input clock of 100 MHz which can be changed through +// the configurable parameter. The reset signal input is high level. +///////////////////////////////////////////////////////////////// + +module debounce #(parameter DEBOUNCE_TIME=0.01, CLK_INPUT=100) +( +input wire clk, +input wire reset, +input wire i, +output wire o +); + +function integer clogb2; + input [31:0] value; + begin + value = value - 1; + for (clogb2 = 0; value > 0; clogb2 = clogb2 + 1) begin + value = value >> 1; + end + end +endfunction + +// ---------------- internal constants -------------- + `define N clogb2((CLK_INPUT*1000000)*DEBOUNCE_TIME) // N value corresponding to 10 ms debounce time +// ---------------- internal variables --------------- + reg [`N-1 : 0] q_reg; // timing regs + reg [`N-1 : 0] q_next; + reg DB_out; + reg DFF1, DFF2; // input flip-flops + wire q_add; // control flags + wire q_reset; + +// counter control + assign q_reset = (DFF1 ^ DFF2); // xor input flip flops to look for level chage to reset counter + assign q_add = ~(q_reg[`N-1]); // add to counter when q_reg msb is equal to 0 + assign o = DB_out; + +// combo counter to manage q_next + always @ ( q_reset, q_add, q_reg) + begin + case( {q_reset , q_add}) + 2'b00 : + q_next <= q_reg; + 2'b01 : + q_next <= q_reg + 1; + default : + q_next <= { `N {1'b0} }; + endcase + end + +// Flip flop inputs and q_reg update + always @ ( posedge clk ) + begin + if(reset == 1'b1) + begin + DFF1 <= 1'b0; + DFF2 <= 1'b0; + q_reg <= { `N {1'b0} }; + end + else + begin + DFF1 <= i; + DFF2 <= DFF1; + q_reg <= q_next; + end + end + +// counter control + always @ ( posedge clk ) + begin + if(reset == 1'b1) + begin + DB_out <= 1'b0; + end + else if(q_reg[`N-1] == 1'b1) + DB_out <= DFF2; + else + DB_out <= DB_out; + end +endmodule diff --git a/Library/Interface/debounce/debounce_1.0/src/debounce_tb.v b/Library/Interface/debounce/debounce_1.0/src/debounce_tb.v new file mode 100644 index 0000000..3280eda --- /dev/null +++ b/Library/Interface/debounce/debounce_1.0/src/debounce_tb.v @@ -0,0 +1,62 @@ +`timescale 1ns / 1ps +// Define Module for Test Fixture +module DeBounce_tb(); +// Inputs + reg clk; + reg reset; + reg button_in; + +// Outputs + wire DB_out; + + parameter PERIOD = 10; + +// Instantiate the DUT +// Please check and add your parameters manually + debounce #( + .DEBOUNCE_TIME(10), + .CLK_INPUT(100)) + DUT ( + .clk(clk), + .clr(reset), + .i(button_in), + .o(DB_out) + ); + +// Initialize Inputs + initial begin + $display ($time, " << Starting the Simulation >> "); + clk = 1'b0; + reset = 1'b1; + #(PERIOD*4) reset = 1'b0; // release the reset after 2 clock cycles + button_in = 1'b0; + end + + always + #(PERIOD/2) clk = ~clk; // every ten nanoseconds invert the clock + + initial + begin + #(PERIOD*20000) button_in = 1'b1; + + #(PERIOD*4000) button_in = 1'b0; + + #(PERIOD*8000) button_in = 1'b1; + + #(PERIOD*8000) button_in = 1'b0; + + #(PERIOD*40000) button_in = 1'b1; + + #(PERIOD*1001000) button_in = 1'b0; // 10 ms delay + + #(PERIOD*4000) button_in = 1'b1; + + #(PERIOD*40000) button_in = 1'b0; + + end + + + + + +endmodule // DeBounce_tf \ No newline at end of file diff --git a/Library/Interface/debounce/debounce_1.0/xgui/debounce_v1_0.tcl b/Library/Interface/debounce/debounce_1.0/xgui/debounce_v1_0.tcl new file mode 100644 index 0000000..f7ad824 --- /dev/null +++ b/Library/Interface/debounce/debounce_1.0/xgui/debounce_v1_0.tcl @@ -0,0 +1,40 @@ +# Definitional proc to organize widgets for parameters. +proc init_gui { IPINST } { + ipgui::add_param $IPINST -name "Component_Name" + #Adding Page + set Page_0 [ipgui::add_page $IPINST -name "Page 0"] + ipgui::add_param $IPINST -name "CLK_INPUT" -parent ${Page_0} + ipgui::add_param $IPINST -name "DEBOUNCE_TIME" -parent ${Page_0} + + +} + +proc update_PARAM_VALUE.CLK_INPUT { PARAM_VALUE.CLK_INPUT } { + # Procedure called to update CLK_INPUT when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.CLK_INPUT { PARAM_VALUE.CLK_INPUT } { + # Procedure called to validate CLK_INPUT + return true +} + +proc update_PARAM_VALUE.DEBOUNCE_TIME { PARAM_VALUE.DEBOUNCE_TIME } { + # Procedure called to update DEBOUNCE_TIME when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.DEBOUNCE_TIME { PARAM_VALUE.DEBOUNCE_TIME } { + # Procedure called to validate DEBOUNCE_TIME + return true +} + + +proc update_MODELPARAM_VALUE.DEBOUNCE_TIME { MODELPARAM_VALUE.DEBOUNCE_TIME PARAM_VALUE.DEBOUNCE_TIME } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.DEBOUNCE_TIME}] ${MODELPARAM_VALUE.DEBOUNCE_TIME} +} + +proc update_MODELPARAM_VALUE.CLK_INPUT { MODELPARAM_VALUE.CLK_INPUT PARAM_VALUE.CLK_INPUT } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.CLK_INPUT}] ${MODELPARAM_VALUE.CLK_INPUT} +} + diff --git a/Library/Interface/debounce/debounce_1.0/xgui/debounce_v1_0.tcl~ b/Library/Interface/debounce/debounce_1.0/xgui/debounce_v1_0.tcl~ new file mode 100644 index 0000000..f7ad824 --- /dev/null +++ b/Library/Interface/debounce/debounce_1.0/xgui/debounce_v1_0.tcl~ @@ -0,0 +1,40 @@ +# Definitional proc to organize widgets for parameters. +proc init_gui { IPINST } { + ipgui::add_param $IPINST -name "Component_Name" + #Adding Page + set Page_0 [ipgui::add_page $IPINST -name "Page 0"] + ipgui::add_param $IPINST -name "CLK_INPUT" -parent ${Page_0} + ipgui::add_param $IPINST -name "DEBOUNCE_TIME" -parent ${Page_0} + + +} + +proc update_PARAM_VALUE.CLK_INPUT { PARAM_VALUE.CLK_INPUT } { + # Procedure called to update CLK_INPUT when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.CLK_INPUT { PARAM_VALUE.CLK_INPUT } { + # Procedure called to validate CLK_INPUT + return true +} + +proc update_PARAM_VALUE.DEBOUNCE_TIME { PARAM_VALUE.DEBOUNCE_TIME } { + # Procedure called to update DEBOUNCE_TIME when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.DEBOUNCE_TIME { PARAM_VALUE.DEBOUNCE_TIME } { + # Procedure called to validate DEBOUNCE_TIME + return true +} + + +proc update_MODELPARAM_VALUE.DEBOUNCE_TIME { MODELPARAM_VALUE.DEBOUNCE_TIME PARAM_VALUE.DEBOUNCE_TIME } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.DEBOUNCE_TIME}] ${MODELPARAM_VALUE.DEBOUNCE_TIME} +} + +proc update_MODELPARAM_VALUE.CLK_INPUT { MODELPARAM_VALUE.CLK_INPUT PARAM_VALUE.CLK_INPUT } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.CLK_INPUT}] ${MODELPARAM_VALUE.CLK_INPUT} +} + diff --git a/Library/Interface/ws2812-LED-controller/WS2812.pdf b/Library/Interface/ws2812-LED-controller/WS2812.pdf new file mode 100644 index 0000000..8ceeec7 Binary files /dev/null and b/Library/Interface/ws2812-LED-controller/WS2812.pdf differ diff --git a/Library/Interface/ws2812-LED-controller/readme.md b/Library/Interface/ws2812-LED-controller/readme.md new file mode 100644 index 0000000..42933b3 --- /dev/null +++ b/Library/Interface/ws2812-LED-controller/readme.md @@ -0,0 +1,45 @@ +#AXI IP Controller for WS2812 LED controller# + +The WS2812 controller can drive LED chains using a single data line using a timing protocol. For more details on the WS2812, please see: +[WS2812.pdf](https://github.com/xupgit/Basys3/blob/master/Library/Interface/ws2812-LED-controller/WS2812.pdf) + +The IP has been created with Vivado 2015.2 and is provided in IP-XACT form, to work with Vivado IP Integrator. It can also be used in a non-IPI design. + +LEDs can be controlled by writing data to the peripheral base address + the LED position in the chain. + +``e.g. The address for LED 1 is (Base address + 1). Data is written as 24-bit GRB (Green-Red-Blue).`` + +###Parameters### +Number of LEDs in the chain is parameterizable. (The WS2812 controller is a serial interface and can be used to control long chains of LEDs connected together in series.) + + +Clock frequency of between 50 – 250 MHz is selectable. This should be chosen to match the incoming AXI clock. + + +The ADDR Width will be automatically calculated based on the number of LEDs. + +`e.g. (ADDR Width = log2(LEDs) + 2 for 32 bit or +3 for 64 bit).` + +###Data Format### +24-bit Data should be written to the IP in Green, Red, Blue order from MSB -> LSB +23 - 16 MSB Green LSB +15 - 8 MSB Red LSB + 7 - 0 MSB Blue LSB + +``e.g. Writing 0xff3f03 `` + + Green = 0xff (Intensity = 255) + + Red = 0x3f (intensity = 63) + + Blue = 0x0f (intensity = 15) + +### Addressing LED positions ### + LED 0 (Base address) + + LED 1 (Base address + 1) + + etc. + +### Tool and device details### +This IP has been tested with Vivado 2015.2, the Digilent Basys 3 (Xilinx Artix device), and an ADAfruit 16 LED Neopixel Ring but should work on other series 7 Xilinx FPGAs (Artix, Kintex, Virtex and Zynq) and other WS2812/Adafruit LED strips, rings, with the WS2812 controller. diff --git a/Library/Interface/ws2812-LED-controller/ws2812_1.0.zip b/Library/Interface/ws2812-LED-controller/ws2812_1.0.zip new file mode 100644 index 0000000..06b1f4d Binary files /dev/null and b/Library/Interface/ws2812-LED-controller/ws2812_1.0.zip differ diff --git a/Library/XUP_LIB/xup_bin2BCD_1.0/component.xml b/Library/XUP_LIB/xup_bin2BCD_1.0/component.xml new file mode 100644 index 0000000..4ef7e7f --- /dev/null +++ b/Library/XUP_LIB/xup_bin2BCD_1.0/component.xml @@ -0,0 +1,285 @@ + + + xilinx.com + XUP + bin2bcd + 1.0 + + + + xilinx_verilogsynthesis + Verilog Synthesis + verilogSource:vivado.xilinx.com:synthesis + verilog + bin2bcd + + xilinx_verilogsynthesis_view_fileset + + + + viewChecksum + c798d906 + + + + + xilinx_verilogbehavioralsimulation + Verilog Simulation + verilogSource:vivado.xilinx.com:simulation + verilog + bin2bcd + + xilinx_verilogbehavioralsimulation_view_fileset + + + + viewChecksum + c798d906 + + + + + xilinx_xpgui + UI Layout + :vivado.xilinx.com:xgui.ui + + xilinx_xpgui_view_fileset + + + + viewChecksum + 10d8084b + + + + + xilinx_readme + Readme + :vivado.xilinx.com:docs.readme + + xilinx_readme_view_fileset + + + + viewChecksum + bb084046 + + + + + xilinx_utilityxitfiles + Utility XIT/TTCL + :vivado.xilinx.com:xit.util + + xilinx_utilityxitfiles_view_fileset + + + + viewChecksum + 9c3b79bd + + + + + + + a_in + + in + + 7 + 0 + + + + wire + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + ones + + out + + 3 + 0 + + + + reg + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + tens + + out + + 3 + 0 + + + + reg + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + + optional + true + + + + + + hundreds + + out + + 3 + 0 + + + + reg + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + + optional + true + + + + + + thousands + + out + + 3 + 0 + + + + reg + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + + optional + false + + + + + + + + SIZE + Size + 8 + + + + + + xilinx_verilogsynthesis_view_fileset + + src/bin2BCD.v + verilogSource + CHECKSUM_c798d906 + + + + xilinx_verilogbehavioralsimulation_view_fileset + + src/bin2BCD.v + verilogSource + + + + xilinx_xpgui_view_fileset + + xgui/bin2bcd_v1_0.tcl + tclSource + XGUI_VERSION_2 + CHECKSUM_51f25fd2 + + + + xilinx_readme_view_fileset + + doc/readme.txt + text + + + + xilinx_utilityxitfiles_view_fileset + + misc/xup.png + image + LOGO + + + + Binary to BCD converter with SIZE configurable parameter + + + SIZE + Size + 8 + + + Component_Name + bin2bcd_v1_0 + + + + + + virtex7 + artix7 + kintex7 + zynq + + + XUP_LIB + + bin2bcd_v1_0 + XUP + http://www.xilinx.com/university + 3 + 2015-06-15T12:43:49Z + + C:/xup/IPI_Lib/bin2bcd/bin2bcd.srcs/sources_1/imports + C:/xup/IPI_Lib/bin2bcd/bin2bcd.srcs/sources_1/imports + + + + 2014.4 + + + + + + + diff --git a/Library/XUP_LIB/xup_bin2BCD_1.0/doc/readme.txt b/Library/XUP_LIB/xup_bin2BCD_1.0/doc/readme.txt new file mode 100644 index 0000000..db818c0 --- /dev/null +++ b/Library/XUP_LIB/xup_bin2BCD_1.0/doc/readme.txt @@ -0,0 +1,31 @@ +Tool and version: Vivado 2014.4 +Target Families: Artix-7, Kintex-7, Virtex-7, and Zynq + +Introduction: +This IP is a member of XUP_LIB created by XUP. This IP provides Binary to BCD conversion. The Binary input width is constrained between 3 and 14 bits using SIZE as a configurable parameter. Depending on the width, tens, hundreds, and thousands ports may become visible. + +Setting up the library path: +Create a Vivado project. Click on the Project Settings, then click on the IP block in the left panel, click on the Add Repository... button, browse to the directory where the XUP_LIB directory is located, and click Select. The IP entry should be visible in the IP in the Selected Repository. + +Configurable Paramerter: +SIZE - constrained between 3 and 14. Size of 4, 5, or 6 will make tens port visible. Size of 7, 8 or 9 will make hundreds port visible. Size of 10 or higher will make thousands port visible. +Input: +a_in - Binary input +Output: +ones - ones output +tens - tens output +hundreds - hundreds output + +How to use the IP: +Step 1: Create a Vivado project +Step 2: Set the Project Settings to point to the XUP_LIB path +Step 3: Create a block design +Step 4: Add the desired IP on the canvas, connect them, and add external input and output ports +Step 5: Create a HDL wrapper +Step 6: Add constraints file (.xdc) +Step 7: Synthesize, implement, and generate the bitstream +Step 8: Connect the board, download the bitstream, and verify the design + + +Change log + diff --git a/Library/XUP_LIB/xup_bin2BCD_1.0/misc/xup.png b/Library/XUP_LIB/xup_bin2BCD_1.0/misc/xup.png new file mode 100644 index 0000000..6949927 Binary files /dev/null and b/Library/XUP_LIB/xup_bin2BCD_1.0/misc/xup.png differ diff --git a/Library/XUP_LIB/xup_bin2BCD_1.0/src/bin2BCD.v b/Library/XUP_LIB/xup_bin2BCD_1.0/src/bin2BCD.v new file mode 100644 index 0000000..46cb79b --- /dev/null +++ b/Library/XUP_LIB/xup_bin2BCD_1.0/src/bin2BCD.v @@ -0,0 +1,49 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Module Name: bin2bcd +// Description: Binary to BCD converter. SIZE valid range is 3 to 14. +////////////////////////////////////////////////////////////////////////////////// + +module bin2bcd #(parameter SIZE = 8)( + input wire [SIZE-1:0] a_in, + output reg [3:0] ones, + output reg [3:0] tens, + output reg [3:0] hundreds, + output reg [3:0] thousands + ); + + // Internal variable for storing bits + reg [23:-6] temp_shift_reg; + integer i; + + always @(a_in) + begin + // Clear previous number and store new number in temp_shift_reg register + temp_shift_reg[23:7] = 0; + temp_shift_reg[7:-6] = {a_in,{(14-SIZE){1'b0}}}; + + // Loop input width times + for (i=0; i= 5) + temp_shift_reg[11:8] = temp_shift_reg[11:8] + 3; + + if (temp_shift_reg[15:12] >= 5) + temp_shift_reg[15:12] = temp_shift_reg[15:12] + 3; + + if (temp_shift_reg[19:16] >= 5) + temp_shift_reg[19:16] = temp_shift_reg[19:16] + 3; + + if (temp_shift_reg[23:20] >= 5) + temp_shift_reg[23:20] = temp_shift_reg[23:20] + 3; + + // Shift entire register left once + temp_shift_reg = temp_shift_reg << 1; + end + + // Push decimal numbers to output + thousands = temp_shift_reg[23:20]; // thousands + hundreds = temp_shift_reg[19:16]; // hundreds + tens = temp_shift_reg[15:12]; // tens + ones = temp_shift_reg[11:8]; // ones + end +endmodule diff --git a/Library/XUP_LIB/xup_bin2BCD_1.0/xgui/bin2bcd_v1_0.tcl b/Library/XUP_LIB/xup_bin2BCD_1.0/xgui/bin2bcd_v1_0.tcl new file mode 100644 index 0000000..21d85e3 --- /dev/null +++ b/Library/XUP_LIB/xup_bin2BCD_1.0/xgui/bin2bcd_v1_0.tcl @@ -0,0 +1,28 @@ +# Definitional proc to organize widgets for parameters. +proc init_gui { IPINST } { + ipgui::add_param $IPINST -name "Component_Name" + #Adding Page + set Page_0 [ipgui::add_page $IPINST -name "Page 0"] + ipgui::add_param $IPINST -name "SIZE" -parent ${Page_0} + ipgui::add_static_text $IPINST -name "Output Ports" -parent ${Page_0} -text {When Size > 3 then the tens port is available +When Size > 6 then the hundreds port is available +When Size > 9 then the thousands port is available} + + +} + +proc update_PARAM_VALUE.SIZE { PARAM_VALUE.SIZE } { + # Procedure called to update SIZE when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.SIZE { PARAM_VALUE.SIZE } { + # Procedure called to validate SIZE + return true +} + + +proc update_MODELPARAM_VALUE.SIZE { MODELPARAM_VALUE.SIZE PARAM_VALUE.SIZE } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.SIZE}] ${MODELPARAM_VALUE.SIZE} +} + diff --git a/Library/XUP_LIB/xup_counters_1.0/component.xml b/Library/XUP_LIB/xup_counters_1.0/component.xml new file mode 100644 index 0000000..f33025c --- /dev/null +++ b/Library/XUP_LIB/xup_counters_1.0/component.xml @@ -0,0 +1,367 @@ + + + xilinx.com + XUP + counters + 1.0 + + + signal_clock + + + + + + + CLK + + + clk + + + + + + ASSOCIATED_RESET + reset + + + + + + + + xilinx_verilogsynthesis + Verilog Synthesis + verilogSource:vivado.xilinx.com:synthesis + verilog + counters + + xilinx_verilogsynthesis_view_fileset + + + + viewChecksum + 9ff0c762 + + + + + xilinx_verilogbehavioralsimulation + Verilog Simulation + verilogSource:vivado.xilinx.com:simulation + verilog + counters + + xilinx_verilogbehavioralsimulation_view_fileset + + + + viewChecksum + 9ff0c762 + + + + + xilinx_xpgui + UI Layout + :vivado.xilinx.com:xgui.ui + + xilinx_xpgui_view_fileset + + + + viewChecksum + cc9d309d + + + + + xilinx_readme + Readme + :vivado.xilinx.com:docs.readme + + xilinx_readme_view_fileset + + + + viewChecksum + dbeaa75a + + + + + xilinx_utilityxitfiles + Utility XIT/TTCL + :vivado.xilinx.com:xit.util + + xilinx_utilityxitfiles_view_fileset + + + + viewChecksum + 9c3b79bd + + + + + + + clk + + in + + + wire + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + up_dn + + in + + + wire + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + 1 + + + + + + optional + true + + + + + + clr + + in + + + wire + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + enable + + in + + + wire + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + 1 + + + + + + optional + true + + + + + + bin_count + + out + + 7 + 0 + + + + reg + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + + optional + true + + + + + + gray_count + + out + + 7 + 0 + + + + wire + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + + optional + false + + + + + + bcd_count + + out + + 7 + 0 + + + + wire + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + + optional + false + + + + + + + + COUNT_SIZE + Count Size + 8 + + + + + + choices_0 + ACTIVE_HIGH + ACTIVE_LOW + + + choices_1 + 0 + 1 + 2 + + + + + xilinx_verilogsynthesis_view_fileset + + src/counters.v + verilogSource + CHECKSUM_9ff0c762 + + + + xilinx_verilogbehavioralsimulation_view_fileset + + src/counters.v + verilogSource + + + + xilinx_xpgui_view_fileset + + xgui/counters_v1_0.tcl + tclSource + XGUI_VERSION_2 + CHECKSUM_2f4204ba + + + + xilinx_readme_view_fileset + + doc/readme.txt + text + + + + xilinx_utilityxitfiles_view_fileset + + misc/xup.png + image + + + + Binary, Gray, and BCD counters with COUNT_SIZE configuration parameter + + + COUNT_SIZE + Counter Size + 8 + + + Component_Name + counters_v1_0 + + + TYPE + Counter Type + 0 + + + + + + virtex7 + artix7 + kintex7 + zynq + + + XUP_LIB + + counters_v1_0 + XUP + http://www.xilinx.com/university + 3 + 2015-05-17T20:15:59Z + + C:/xup/IPI_Lib/counters/counters.srcs/sources_1/imports + C:/xup/IPI_Lib/counters/counters.srcs/sources_1/imports + + + + 2014.4 + + + + + + + + diff --git a/Library/XUP_LIB/xup_counters_1.0/doc/readme.txt b/Library/XUP_LIB/xup_counters_1.0/doc/readme.txt new file mode 100644 index 0000000..3ac7e48 --- /dev/null +++ b/Library/XUP_LIB/xup_counters_1.0/doc/readme.txt @@ -0,0 +1,18 @@ +Tool and version: Vivado 2014.4 +Target Families: Artix-7, Kintex-7, Virtex-7, and Zynq + +Introduction: +This IP is a member of XUP_LIB created by XUP. The XUP_LIB provides the basic gates/functionality that can be used in digital design. + +Setting up the library path: +Create a Vivado project. Click on the Project Settings, then click on the IP block in the left panel, click on the Add Repository... button, browse to the directory where the XUP_LIB directory is located, and click Select. The IP entry should be visible in the IP Catalog under the XUP_LIB category. + +How to use the IP: +Step 1: Create a Vivado project +Step 2: Set the Project Settings to point to the XUP_LIB path +Step 3: Create a block design +Step 4: Add the desired IP on the canvas, connect them, and add external input and output ports +Step 5: Create a HDL wrapper +Step 6: Add constraints file (.xdc) +Step 7: Synthesize, implement, and generate the bitstream +Step 8: Connect the board, download the bitstream, and varify the design diff --git a/Library/XUP_LIB/xup_counters_1.0/misc/xup.png b/Library/XUP_LIB/xup_counters_1.0/misc/xup.png new file mode 100644 index 0000000..6949927 Binary files /dev/null and b/Library/XUP_LIB/xup_counters_1.0/misc/xup.png differ diff --git a/Library/XUP_LIB/xup_counters_1.0/src/counters.v b/Library/XUP_LIB/xup_counters_1.0/src/counters.v new file mode 100644 index 0000000..085a7d6 --- /dev/null +++ b/Library/XUP_LIB/xup_counters_1.0/src/counters.v @@ -0,0 +1,77 @@ +`timescale 1ns / 1ps +///////////////////////////////////////////////////////////////// +// Module Name: counters +// Description: Models Binary, Gray, and BCD counters +///////////////////////////////////////////////////////////////// + +module counters #(parameter COUNT_SIZE = 8) +( + input wire clk, + input wire up_dn, + input wire clr, + input wire enable, + output reg [COUNT_SIZE-1:0] bin_count, + output wire [COUNT_SIZE-1:0] gray_count, + output wire [COUNT_SIZE-1:0] bcd_count +); + +reg [COUNT_SIZE-1:0] binary_value = {{COUNT_SIZE{1'b0}}, 1'b1}; +reg [COUNT_SIZE-1:0] gray_value = {COUNT_SIZE{1'b0}}; + + always @(posedge clk) + if (clr) + bin_count <= 0; + else if (enable) + if (up_dn) + bin_count <= bin_count + 1; + else + bin_count <= bin_count - 1; + + assign gray_count = gray_value; + + always @(posedge clk) + if (clr) begin + binary_value <= {{COUNT_SIZE{1'b0}}, 1'b1}; + gray_value <= {COUNT_SIZE{1'b0}}; + end + else if (enable) begin + binary_value <= binary_value + 1; + gray_value <= (binary_value >> 1) ^ binary_value; + end + + reg [15:0] count_i; + + assign bcd_count = count_i[COUNT_SIZE-1:0]; + + always @(posedge clk) begin + if (clr) + count_i <= 0; + else begin + if (COUNT_SIZE < 4) + count_i[COUNT_SIZE-1:0] <= count_i[COUNT_SIZE-1:0] + 1; + else + begin + if (count_i[3:0] == 9) begin // 3 + count_i[3:0] <= 0; + if (count_i[7:4] == 9) begin //2 + count_i[7:4] <= 0; + if (count_i[11:8] == 9) begin + count_i[11:8] <= 0; + if (count_i[15:12] == 9) + count_i[15:12] <= 0; + else + count_i[15:12] <= count_i[15:12] + 1; + end + else + count_i[11:8] <= count_i[11:8] + 1; + end + else + count_i[7:4] <= count_i[7:4] + 1; + end + else + count_i[3:0] <= count_i[3:0] + 1; + end + end + end +endmodule // bcd_count + diff --git a/Library/XUP_LIB/xup_counters_1.0/xgui/counters_v1_0.tcl b/Library/XUP_LIB/xup_counters_1.0/xgui/counters_v1_0.tcl new file mode 100644 index 0000000..79f5f5a --- /dev/null +++ b/Library/XUP_LIB/xup_counters_1.0/xgui/counters_v1_0.tcl @@ -0,0 +1,35 @@ +# Definitional proc to organize widgets for parameters. +proc init_gui { IPINST } { + ipgui::add_param $IPINST -name "Component_Name" + #Adding Page + set Page_0 [ipgui::add_page $IPINST -name "Page 0"] + ipgui::add_param $IPINST -name "COUNT_SIZE" -parent ${Page_0} + ipgui::add_param $IPINST -name "TYPE" -parent ${Page_0} -layout horizontal + + +} + +proc update_PARAM_VALUE.COUNT_SIZE { PARAM_VALUE.COUNT_SIZE } { + # Procedure called to update COUNT_SIZE when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.COUNT_SIZE { PARAM_VALUE.COUNT_SIZE } { + # Procedure called to validate COUNT_SIZE + return true +} + +proc update_PARAM_VALUE.TYPE { PARAM_VALUE.TYPE } { + # Procedure called to update TYPE when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.TYPE { PARAM_VALUE.TYPE } { + # Procedure called to validate TYPE + return true +} + + +proc update_MODELPARAM_VALUE.COUNT_SIZE { MODELPARAM_VALUE.COUNT_SIZE PARAM_VALUE.COUNT_SIZE } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.COUNT_SIZE}] ${MODELPARAM_VALUE.COUNT_SIZE} +} + diff --git a/Library/XUP_LIB/xup_or2_1.0/misc/or_2_input.png b/Library/XUP_LIB/xup_or2_1.0/misc/or_2_input.png index 45e164a..23285a1 100644 Binary files a/Library/XUP_LIB/xup_or2_1.0/misc/or_2_input.png and b/Library/XUP_LIB/xup_or2_1.0/misc/or_2_input.png differ diff --git a/Library/XUP_LIB/xup_parallel_in_serial_out_load_enable/component.xml b/Library/XUP_LIB/xup_parallel_in_serial_out_load_enable/component.xml new file mode 100644 index 0000000..76ebebc --- /dev/null +++ b/Library/XUP_LIB/xup_parallel_in_serial_out_load_enable/component.xml @@ -0,0 +1,303 @@ + + + xilinx.com + XUP + parallel_in_serial_out_load_enable + 1.0 + + + signal_clock + + + + + + + CLK + + + clk + + + + + + + + + xilinx_verilogsynthesis + Verilog Synthesis + verilogSource:vivado.xilinx.com:synthesis + verilog + parallel_in_serial_out_load_enable + + xilinx_verilogsynthesis_view_fileset + + + + viewChecksum + a3c3cfd8 + + + + + xilinx_verilogbehavioralsimulation + Verilog Simulation + verilogSource:vivado.xilinx.com:simulation + verilog + parallel_in_serial_out_load_enable + + xilinx_verilogbehavioralsimulation_view_fileset + + + + viewChecksum + a3c3cfd8 + + + + + xilinx_xpgui + UI Layout + :vivado.xilinx.com:xgui.ui + + xilinx_xpgui_view_fileset + + + + viewChecksum + ef49a798 + + + + + xilinx_readme + Readme + :vivado.xilinx.com:docs.readme + + xilinx_readme_view_fileset + + + + viewChecksum + dbeaa75a + + + + + xilinx_utilityxitfiles + Utility XIT/TTCL + :vivado.xilinx.com:xit.util + + xilinx_utilityxitfiles_view_fileset + + + + viewChecksum + 9c3b79bd + + + + + + + clk + + in + + + wire + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + shift_in + + in + + + wire + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + parallel_in + + in + + 3 + 0 + + + + wire + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + load + + in + + + wire + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + en + + in + + + wire + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + shift_out + + out + + + wire + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + parallel_out + + out + + 3 + 0 + + + + wire + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + + + SIZE + Size + 4 + + + DELAY + Delay + 3 + + + + + + xilinx_verilogsynthesis_view_fileset + + src/parallel_in_serial_out_load_enable.v + verilogSource + CHECKSUM_a3c3cfd8 + + + + xilinx_verilogbehavioralsimulation_view_fileset + + src/parallel_in_serial_out_load_enable.v + verilogSource + + + + xilinx_xpgui_view_fileset + + xgui/parallel_in_serial_out_load_enable_v1_0.tcl + tclSource + XGUI_VERSION_2 + CHECKSUM_42f4824e + + + + xilinx_readme_view_fileset + + doc/readme.txt + text + + + + xilinx_utilityxitfiles_view_fileset + + misc/xup.png + image + + + + Shift register having parallel load, serial in, serial out, and parallel out with SIZE and DELAY configutaion parameters + + + SIZE + Size + 4 + + + DELAY + Delay + 3 + + + Component_Name + parallel_in_serial_out_load_enable_v1_0 + + + + + + virtex7 + artix7 + kintex7 + zynq + + + XUP_LIB + + parallel_in_serial_out_load_enable_v1_0 + XUP + http://www.xilinx.com/university + 2 + 2015-04-17T22:14:57Z + + C:/xup/IPI_Lib/parallel_in_serial_out_load_enable/parallel_in_serial_out_load_enable.srcs/sources_1/imports + C:/xup/IPI_Lib/parallel_in_serial_out_load_enable/parallel_in_serial_out_load_enable.srcs/sources_1/imports + + + + 2014.4 + + + + + + + + diff --git a/Library/XUP_LIB/xup_parallel_in_serial_out_load_enable/doc/readme.txt b/Library/XUP_LIB/xup_parallel_in_serial_out_load_enable/doc/readme.txt new file mode 100644 index 0000000..3ac7e48 --- /dev/null +++ b/Library/XUP_LIB/xup_parallel_in_serial_out_load_enable/doc/readme.txt @@ -0,0 +1,18 @@ +Tool and version: Vivado 2014.4 +Target Families: Artix-7, Kintex-7, Virtex-7, and Zynq + +Introduction: +This IP is a member of XUP_LIB created by XUP. The XUP_LIB provides the basic gates/functionality that can be used in digital design. + +Setting up the library path: +Create a Vivado project. Click on the Project Settings, then click on the IP block in the left panel, click on the Add Repository... button, browse to the directory where the XUP_LIB directory is located, and click Select. The IP entry should be visible in the IP Catalog under the XUP_LIB category. + +How to use the IP: +Step 1: Create a Vivado project +Step 2: Set the Project Settings to point to the XUP_LIB path +Step 3: Create a block design +Step 4: Add the desired IP on the canvas, connect them, and add external input and output ports +Step 5: Create a HDL wrapper +Step 6: Add constraints file (.xdc) +Step 7: Synthesize, implement, and generate the bitstream +Step 8: Connect the board, download the bitstream, and varify the design diff --git a/Library/XUP_LIB/xup_parallel_in_serial_out_load_enable/misc/xup.png b/Library/XUP_LIB/xup_parallel_in_serial_out_load_enable/misc/xup.png new file mode 100644 index 0000000..6949927 Binary files /dev/null and b/Library/XUP_LIB/xup_parallel_in_serial_out_load_enable/misc/xup.png differ diff --git a/Library/XUP_LIB/xup_parallel_in_serial_out_load_enable/src/parallel_in_serial_out_load_enable.v b/Library/XUP_LIB/xup_parallel_in_serial_out_load_enable/src/parallel_in_serial_out_load_enable.v new file mode 100644 index 0000000..d708408 --- /dev/null +++ b/Library/XUP_LIB/xup_parallel_in_serial_out_load_enable/src/parallel_in_serial_out_load_enable.v @@ -0,0 +1,26 @@ +`timescale 1ns / 1ps +///////////////////////////////////////////////////////////////// +// Module Name: parallel_in_serial_out_load_enable +///////////////////////////////////////////////////////////////// + +module parallel_in_serial_out_load_enable #(parameter SIZE=4, DELAY=3) +( + input wire clk, + input wire shift_in, + input wire [SIZE-1:0]parallel_in, + input wire load, + input wire en, + output wire shift_out, + output wire [SIZE-1:0] parallel_out + ); + + reg [SIZE-1:0] shift_reg; + always @(posedge clk) + if(load) + shift_reg <= parallel_in; + else if (en) + shift_reg <= {shift_reg[SIZE-2:0], shift_in}; + assign #DELAY shift_out = shift_reg[SIZE-1]; + assign #DELAY parallel_out = shift_reg; + +endmodule diff --git a/Library/XUP_LIB/xup_parallel_in_serial_out_load_enable/xgui/parallel_in_serial_out_load_enable_v1_0.tcl b/Library/XUP_LIB/xup_parallel_in_serial_out_load_enable/xgui/parallel_in_serial_out_load_enable_v1_0.tcl new file mode 100644 index 0000000..71bcae7 --- /dev/null +++ b/Library/XUP_LIB/xup_parallel_in_serial_out_load_enable/xgui/parallel_in_serial_out_load_enable_v1_0.tcl @@ -0,0 +1,40 @@ +# Definitional proc to organize widgets for parameters. +proc init_gui { IPINST } { + ipgui::add_param $IPINST -name "Component_Name" + #Adding Page + set Page_0 [ipgui::add_page $IPINST -name "Page 0"] + ipgui::add_param $IPINST -name "DELAY" -parent ${Page_0} + ipgui::add_param $IPINST -name "SIZE" -parent ${Page_0} + + +} + +proc update_PARAM_VALUE.DELAY { PARAM_VALUE.DELAY } { + # Procedure called to update DELAY when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.DELAY { PARAM_VALUE.DELAY } { + # Procedure called to validate DELAY + return true +} + +proc update_PARAM_VALUE.SIZE { PARAM_VALUE.SIZE } { + # Procedure called to update SIZE when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.SIZE { PARAM_VALUE.SIZE } { + # Procedure called to validate SIZE + return true +} + + +proc update_MODELPARAM_VALUE.SIZE { MODELPARAM_VALUE.SIZE PARAM_VALUE.SIZE } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.SIZE}] ${MODELPARAM_VALUE.SIZE} +} + +proc update_MODELPARAM_VALUE.DELAY { MODELPARAM_VALUE.DELAY PARAM_VALUE.DELAY } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.DELAY}] ${MODELPARAM_VALUE.DELAY} +} + diff --git a/Library/XUP_LIB/xup_range_comparator_1.0/component.xml b/Library/XUP_LIB/xup_range_comparator_1.0/component.xml new file mode 100644 index 0000000..461d504 --- /dev/null +++ b/Library/XUP_LIB/xup_range_comparator_1.0/component.xml @@ -0,0 +1,297 @@ + + + xilinx.com + XUP + xup_range_comparator + 1.0 + + + + xilinx_verilogsynthesis + Verilog Synthesis + verilogSource:vivado.xilinx.com:synthesis + verilog + xup_range_comparator + + xilinx_verilogsynthesis_view_fileset + + + + viewChecksum + 9d3c52c2 + + + + + xilinx_verilogbehavioralsimulation + Verilog Simulation + verilogSource:vivado.xilinx.com:simulation + verilog + xup_range_comparator + + xilinx_verilogbehavioralsimulation_view_fileset + + + + viewChecksum + 9d3c52c2 + + + + + xilinx_xpgui + UI Layout + :vivado.xilinx.com:xgui.ui + + xilinx_xpgui_view_fileset + + + + viewChecksum + ef49a798 + + + + + xilinx_readme + Readme + :vivado.xilinx.com:docs.readme + + xilinx_readme_view_fileset + + + + viewChecksum + dbeaa75a + + + + + xilinx_utilityxitfiles + Utility XIT/TTCL + :vivado.xilinx.com:xit.util + + xilinx_utilityxitfiles_view_fileset + + + + viewChecksum + 9c3b79bd + + + + + + + in1 + + in + + 3 + 0 + + + + wire + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + in2 + + in + + 3 + 0 + + + + wire + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + sign + + in + + + wire + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + lt + + out + + + wire + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + le + + out + + + wire + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + eq + + out + + + wire + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + gt + + out + + + wire + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + ge + + out + + + wire + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + + + SIZE + Size + 4 + + + DELAY + Delay + 3 + + + + + + xilinx_verilogsynthesis_view_fileset + + src/xup_range_comparator.v + verilogSource + CHECKSUM_9d3c52c2 + + + + xilinx_verilogbehavioralsimulation_view_fileset + + src/xup_range_comparator.v + verilogSource + + + + xilinx_xpgui_view_fileset + + xgui/xup_range_comparator_v1_0.tcl + tclSource + XGUI_VERSION_2 + CHECKSUM_42f4824e + + + + xilinx_readme_view_fileset + + doc/readme.txt + text + + + + xilinx_utilityxitfiles_view_fileset + + misc/xup.png + image + + + + Signed/Unsigned range comparator with SIZE and DELAY configurable parameter + + + SIZE + Size + 4 + + + DELAY + Delay + 3 + + + Component_Name + xup_range_comparator_v1_0 + + + + + + artix7 + zynq + virtex7 + kintex7 + + + XUP_LIB + + xup_range_comparator_v1_0 + XUP + http://www.xilinx.com/university + 2 + 2015-04-17T12:20:40Z + + C:/xup/IPI_Lib/range_comparator/range_comparator.srcs/sources_1/imports + C:/xup/IPI_Lib/range_comparator/range_comparator.srcs/sources_1/imports + + + + 2014.4 + + + + + + + diff --git a/Library/XUP_LIB/xup_range_comparator_1.0/doc/readme.txt b/Library/XUP_LIB/xup_range_comparator_1.0/doc/readme.txt new file mode 100644 index 0000000..3ac7e48 --- /dev/null +++ b/Library/XUP_LIB/xup_range_comparator_1.0/doc/readme.txt @@ -0,0 +1,18 @@ +Tool and version: Vivado 2014.4 +Target Families: Artix-7, Kintex-7, Virtex-7, and Zynq + +Introduction: +This IP is a member of XUP_LIB created by XUP. The XUP_LIB provides the basic gates/functionality that can be used in digital design. + +Setting up the library path: +Create a Vivado project. Click on the Project Settings, then click on the IP block in the left panel, click on the Add Repository... button, browse to the directory where the XUP_LIB directory is located, and click Select. The IP entry should be visible in the IP Catalog under the XUP_LIB category. + +How to use the IP: +Step 1: Create a Vivado project +Step 2: Set the Project Settings to point to the XUP_LIB path +Step 3: Create a block design +Step 4: Add the desired IP on the canvas, connect them, and add external input and output ports +Step 5: Create a HDL wrapper +Step 6: Add constraints file (.xdc) +Step 7: Synthesize, implement, and generate the bitstream +Step 8: Connect the board, download the bitstream, and varify the design diff --git a/Library/XUP_LIB/xup_range_comparator_1.0/misc/xup.png b/Library/XUP_LIB/xup_range_comparator_1.0/misc/xup.png new file mode 100644 index 0000000..6949927 Binary files /dev/null and b/Library/XUP_LIB/xup_range_comparator_1.0/misc/xup.png differ diff --git a/Library/XUP_LIB/xup_range_comparator_1.0/src/xup_range_comparator.v b/Library/XUP_LIB/xup_range_comparator_1.0/src/xup_range_comparator.v new file mode 100644 index 0000000..5efae73 --- /dev/null +++ b/Library/XUP_LIB/xup_range_comparator_1.0/src/xup_range_comparator.v @@ -0,0 +1,43 @@ +`timescale 1ns / 1ps +///////////////////////////////////////////////////////////////// +// Module Name: xup_range_comparator +///////////////////////////////////////////////////////////////// +module xup_range_comparator #(parameter SIZE = 4 , DELAY = 3)( + input wire [SIZE-1:0] in1, + input wire [SIZE-1:0] in2, + input wire sign, + output wire lt, + output wire le, + output wire eq, + output wire gt, + output wire ge + ); + +wire signed [SIZE-1:0] in1_signed; +wire signed [SIZE-1:0] in2_signed; +wire lower, lower_same, same, higher_same, higher; +wire less, less_equal, equal, greater_equal, greater; + + assign in1_signed = in1; + assign in2_signed = in2; + assign #DELAY lt = (sign) ? less : lower; + assign #DELAY le = (sign) ? less_equal : lower_same; + assign #DELAY eq = (sign) ? equal : same; + assign #DELAY gt = (sign) ? greater : higher; + assign #DELAY ge = (sign) ? greater_equal : higher_same; + +// Unsigned data handling + assign lower = (in1 < in2)? 1'b1: 1'b0; + assign lower_same = (in1 <= in2)? 1'b1: 1'b0; + assign same = (in1 == in2)? 1'b1: 1'b0; + assign higher_same = (in1 >= in2)? 1'b1: 1'b0; + assign higher = (in1 > in2)? 1'b1: 1'b0; + +// Signed data handling + assign less = (in1_signed < in2_signed)? 1'b1: 1'b0; + assign less_equal = (in1_signed <= in2_signed)? 1'b1: 1'b0; + assign equal = (in1_signed == in2_signed)? 1'b1: 1'b0; + assign greater_equal = (in1_signed >= in2_signed)? 1'b1: 1'b0; + assign greater = (in1_signed > in2_signed)? 1'b1: 1'b0; + +endmodule diff --git a/Library/XUP_LIB/xup_range_comparator_1.0/xgui/xup_range_comparator_v1_0.tcl b/Library/XUP_LIB/xup_range_comparator_1.0/xgui/xup_range_comparator_v1_0.tcl new file mode 100644 index 0000000..71bcae7 --- /dev/null +++ b/Library/XUP_LIB/xup_range_comparator_1.0/xgui/xup_range_comparator_v1_0.tcl @@ -0,0 +1,40 @@ +# Definitional proc to organize widgets for parameters. +proc init_gui { IPINST } { + ipgui::add_param $IPINST -name "Component_Name" + #Adding Page + set Page_0 [ipgui::add_page $IPINST -name "Page 0"] + ipgui::add_param $IPINST -name "DELAY" -parent ${Page_0} + ipgui::add_param $IPINST -name "SIZE" -parent ${Page_0} + + +} + +proc update_PARAM_VALUE.DELAY { PARAM_VALUE.DELAY } { + # Procedure called to update DELAY when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.DELAY { PARAM_VALUE.DELAY } { + # Procedure called to validate DELAY + return true +} + +proc update_PARAM_VALUE.SIZE { PARAM_VALUE.SIZE } { + # Procedure called to update SIZE when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.SIZE { PARAM_VALUE.SIZE } { + # Procedure called to validate SIZE + return true +} + + +proc update_MODELPARAM_VALUE.SIZE { MODELPARAM_VALUE.SIZE PARAM_VALUE.SIZE } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.SIZE}] ${MODELPARAM_VALUE.SIZE} +} + +proc update_MODELPARAM_VALUE.DELAY { MODELPARAM_VALUE.DELAY PARAM_VALUE.DELAY } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.DELAY}] ${MODELPARAM_VALUE.DELAY} +} + diff --git a/Library/XUP_LIB/xup_shift_nbit_1.0/component.xml b/Library/XUP_LIB/xup_shift_nbit_1.0/component.xml new file mode 100644 index 0000000..000e2e1 --- /dev/null +++ b/Library/XUP_LIB/xup_shift_nbit_1.0/component.xml @@ -0,0 +1,300 @@ + + + xilinx.com + XUP + xup_shift_nbit + 1.0 + + + + xilinx_verilogsynthesis + Verilog Synthesis + verilogSource:vivado.xilinx.com:synthesis + verilog + xup_shift_nbit + + xilinx_verilogsynthesis_view_fileset + + + + viewChecksum + 06c76ac9 + + + + + xilinx_verilogbehavioralsimulation + Verilog Simulation + verilogSource:vivado.xilinx.com:simulation + verilog + xup_shift_nbit + + xilinx_verilogbehavioralsimulation_view_fileset + + + + viewChecksum + 3350e409 + + + + + xilinx_xpgui + UI Layout + :vivado.xilinx.com:xgui.ui + + xilinx_xpgui_view_fileset + + + + viewChecksum + 739ebe2f + + + + + xilinx_utilityxitfiles + Utility XIT/TTCL + :vivado.xilinx.com:xit.util + + xilinx_utilityxitfiles_view_fileset + + + + viewChecksum + 9c3b79bd + + + + + xilinx_readme + Readme + :vivado.xilinx.com:docs.readme + + xilinx_readme_view_fileset + + + + viewChecksum + e02d0062 + + + + + + + parallel_in + + in + + 3 + 0 + + + + wire + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + dir + + in + + + wire + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + 0 + + + + + + optional + false + + + + + + shift_type + + in + + + wire + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + 0 + + + + + + optional + false + + + + + + parallel_out + + out + + 3 + 0 + + + + wire + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + + + SIZE + Size + 4 + + + DELAY + Delay + 3 + + + NBITS + Nbits + 1 + + + + + + choices_0 + 0 + 1 + + + + + xilinx_verilogsynthesis_view_fileset + + src/xup_shift_nbit.v + verilogSource + CHECKSUM_06c76ac9 + + + + xilinx_verilogbehavioralsimulation_view_fileset + + src/xup_shift_nbit.v + verilogSource + + + src/shift_nbit_tb.v + verilogSource + xil_defaultlib + + + + xilinx_xpgui_view_fileset + + xgui/xup_shift_nbit_v1_0.tcl + tclSource + XGUI_VERSION_2 + CHECKSUM_fb6c0f2f + + + + xilinx_utilityxitfiles_view_fileset + + misc/xup.png + image + LOGO + + + + xilinx_readme_view_fileset + + doc/readme.txt + text + + + + N-bit arithmetic/logical shift with selectable direction, and SIZE, DELAY and NBITS Configurable Parameters + + + SIZE + PORT SIZE + 4 + + + DELAY + Delay + 3 + + + NBITS + Number of positions to shift + 1 + + + Component_Name + xup_shift_nbit_v1_0 + + + DIR + Direction + false + + + TYPE + Shift Type + false + + + + + + virtex7 + artix7 + kintex7 + zynq + + + XUP_LIB + + xup_shift_nbit_v1_0 + XUP + http://www.xilinx.com/university + 3 + 2015-06-09T00:00:34Z + + C:/xup/IPI_Lib/xup_shift_nbit/xup_shift_nbit.srcs/sources_1/imports + C:/xup/IPI_Lib/xup_shift_nbit/xup_shift_nbit.srcs/sources_1/imports + + + + 2014.4 + + + + + + + diff --git a/Library/XUP_LIB/xup_shift_nbit_1.0/doc/readme.txt b/Library/XUP_LIB/xup_shift_nbit_1.0/doc/readme.txt new file mode 100644 index 0000000..6734ae7 --- /dev/null +++ b/Library/XUP_LIB/xup_shift_nbit_1.0/doc/readme.txt @@ -0,0 +1,29 @@ +Tool and version: Vivado 2014.4 +Target Families: Artix-7, Kintex-7, Virtex-7, and Zynq + +Introduction: +This IP is a member of XUP_LIB created by XUP. The XUP_LIB provides the basic gates/functionality that can be used in digital design.This IP has selectable dir and shift_type input ports. When the ports are not selected, dir is tied to logic0 (right shift) and shift_type is tied to logic0 (logical shift). + +The configurable parameters are SIZE, DELAY, and NBITS. The SIZE is the size of parallel_in and parallel_out ports, and NBITS is the number of bits to be shifted. + +Input/Output Ports: +Input: +parallel_in - vector input port +shift_type - type of shift, when not selected it is tied to logic0 (logical) +dir - direction, 1 means left and 0 means right, when not selected it is tied to logic0 + +Output: +parallel_out - vectored output, selectable + +Setting up the library path: +Create a Vivado project. Click on the Project Settings, then click on the IP block in the left panel, click on the Add Repository... button, browse to the directory where this IP directory is located, and click Select. The IP entry should be visible in the IP in the Selected Repository. + +How to use the IP: +Step 1: Create a Vivado project +Step 2: Set the Project Settings to point to the IP path +Step 3: Create a block design +Step 4: Add the desired IP on the canvas, connect them, and add external input and output ports +Step 5: Create a HDL wrapper +Step 6: Add constraints file (.xdc) +Step 7: Synthesize, implement, and generate the bitstream +Step 8: Connect the board, download the bitstream, and varify the design diff --git a/Library/XUP_LIB/xup_shift_nbit_1.0/misc/xup.png b/Library/XUP_LIB/xup_shift_nbit_1.0/misc/xup.png new file mode 100644 index 0000000..6949927 Binary files /dev/null and b/Library/XUP_LIB/xup_shift_nbit_1.0/misc/xup.png differ diff --git a/Library/XUP_LIB/xup_shift_nbit_1.0/src/shift_nbit_tb.v b/Library/XUP_LIB/xup_shift_nbit_1.0/src/shift_nbit_tb.v new file mode 100644 index 0000000..27e3012 --- /dev/null +++ b/Library/XUP_LIB/xup_shift_nbit_1.0/src/shift_nbit_tb.v @@ -0,0 +1,31 @@ +`timescale 1ns / 1ps +///////////////////////////////////////////////////////////////// +// Module Name: shift_nbit_tb +///////////////////////////////////////////////////////////////// + +module shift_nbit_tb( + ); + + reg dir; + reg shift_type; + reg [5:0] p_in; + wire [5:0] p_out; + xup_shift_nbit #(.SIZE(6),.DELAY(4), .NBITS(3)) DUT (.dir(dir), .shift_type(shift_type), .parallel_in(p_in), .parallel_out(p_out)); + + + initial + begin + dir=0; + shift_type=0; + p_in=6'b101101; + #40; + #10 dir=1; + #40; + #10 shift_type=1; + #40; + #10 dir=0; + #40; + $stop; + end + +endmodule diff --git a/Library/XUP_LIB/xup_shift_nbit_1.0/src/xup_shift_nbit.v b/Library/XUP_LIB/xup_shift_nbit_1.0/src/xup_shift_nbit.v new file mode 100644 index 0000000..b96b7dc --- /dev/null +++ b/Library/XUP_LIB/xup_shift_nbit_1.0/src/xup_shift_nbit.v @@ -0,0 +1,41 @@ +`timescale 1ns / 1ps +///////////////////////////////////////////////////////////////// +// Module Name: xup_shift_nbit +///////////////////////////////////////////////////////////////// + +module xup_shift_nbit#(parameter SIZE=4, DELAY=3, NBITS=1) +( + input wire [SIZE-1:0]parallel_in, + input wire dir, + input wire shift_type, + output wire [SIZE-1:0] parallel_out + ); + + wire signed [SIZE-1:0]in1_signed; + reg [SIZE-1:0] shift_reg; + + assign in1_signed = parallel_in; + always @(*) + case(shift_type) + 1'b1 : begin // shift_type=1 => arithmetic + if (dir) // dir=1 then left shift + shift_reg <= {parallel_in[SIZE-NBITS-1:0], {NBITS{1'b0}}}; + else + shift_reg <= in1_signed >>> NBITS; + end + 1'b0 : begin // shift_type=0 => logical + if(dir) + shift_reg <= {parallel_in[SIZE-NBITS-1:0], {NBITS{1'b0}}}; + else + shift_reg <= in1_signed >> NBITS; + end + default : begin // default is logical + if(dir) + shift_reg <= {parallel_in[SIZE-NBITS-1:0], {NBITS{1'b0}}}; + else + shift_reg <= in1_signed >> NBITS; + end + endcase + assign #DELAY parallel_out = shift_reg; + +endmodule diff --git a/Library/XUP_LIB/xup_shift_nbit_1.0/xgui/xup_shift_nbit_v1_0.tcl b/Library/XUP_LIB/xup_shift_nbit_1.0/xgui/xup_shift_nbit_v1_0.tcl new file mode 100644 index 0000000..e1fe7cd --- /dev/null +++ b/Library/XUP_LIB/xup_shift_nbit_1.0/xgui/xup_shift_nbit_v1_0.tcl @@ -0,0 +1,78 @@ +# Definitional proc to organize widgets for parameters. +proc init_gui { IPINST } { + ipgui::add_param $IPINST -name "Component_Name" + #Adding Page + set Page_0 [ipgui::add_page $IPINST -name "Page 0"] + ipgui::add_param $IPINST -name "DELAY" -parent ${Page_0} + ipgui::add_param $IPINST -name "NBITS" -parent ${Page_0} + ipgui::add_param $IPINST -name "SIZE" -parent ${Page_0} + ipgui::add_static_text $IPINST -name "Optional Ports" -parent ${Page_0} -text {When Shift Type is not checked then logical shift + +When Direction is not checked then left shift} + ipgui::add_param $IPINST -name "TYPE" -parent ${Page_0} + ipgui::add_param $IPINST -name "DIR" -parent ${Page_0} + + +} + +proc update_PARAM_VALUE.DELAY { PARAM_VALUE.DELAY } { + # Procedure called to update DELAY when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.DELAY { PARAM_VALUE.DELAY } { + # Procedure called to validate DELAY + return true +} + +proc update_PARAM_VALUE.DIR { PARAM_VALUE.DIR } { + # Procedure called to update DIR when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.DIR { PARAM_VALUE.DIR } { + # Procedure called to validate DIR + return true +} + +proc update_PARAM_VALUE.NBITS { PARAM_VALUE.NBITS } { + # Procedure called to update NBITS when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.NBITS { PARAM_VALUE.NBITS } { + # Procedure called to validate NBITS + return true +} + +proc update_PARAM_VALUE.SIZE { PARAM_VALUE.SIZE } { + # Procedure called to update SIZE when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.SIZE { PARAM_VALUE.SIZE } { + # Procedure called to validate SIZE + return true +} + +proc update_PARAM_VALUE.TYPE { PARAM_VALUE.TYPE } { + # Procedure called to update TYPE when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.TYPE { PARAM_VALUE.TYPE } { + # Procedure called to validate TYPE + return true +} + + +proc update_MODELPARAM_VALUE.SIZE { MODELPARAM_VALUE.SIZE PARAM_VALUE.SIZE } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.SIZE}] ${MODELPARAM_VALUE.SIZE} +} + +proc update_MODELPARAM_VALUE.DELAY { MODELPARAM_VALUE.DELAY PARAM_VALUE.DELAY } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.DELAY}] ${MODELPARAM_VALUE.DELAY} +} + +proc update_MODELPARAM_VALUE.NBITS { MODELPARAM_VALUE.NBITS PARAM_VALUE.NBITS } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.NBITS}] ${MODELPARAM_VALUE.NBITS} +} + diff --git a/Library/XUP_LIB/xup_shift_register_1.0/component.xml b/Library/XUP_LIB/xup_shift_register_1.0/component.xml new file mode 100644 index 0000000..ed042b0 --- /dev/null +++ b/Library/XUP_LIB/xup_shift_register_1.0/component.xml @@ -0,0 +1,452 @@ + + + xilinx.com + ip + xup_shift_register + 1.0 + + + signal_clock + + + + + + + CLK + + + clk + + + + + + + + + xilinx_verilogsynthesis + Verilog Synthesis + verilogSource:vivado.xilinx.com:synthesis + verilog + xup_shift_register + + xilinx_verilogsynthesis_view_fileset + + + + viewChecksum + 1576e397 + + + + + xilinx_verilogbehavioralsimulation + Verilog Simulation + verilogSource:vivado.xilinx.com:simulation + verilog + xup_shift_register + + xilinx_verilogbehavioralsimulation_view_fileset + + + + viewChecksum + 1576e397 + + + + + xilinx_verilogtestbench + Verilog Test Bench + verilogSource:vivado.xilinx.com:simulation.testbench + verilog + shift_register_tb + + xilinx_verilogtestbench_view_fileset + + + + viewChecksum + 38a7c403 + + + + + xilinx_xpgui + UI Layout + :vivado.xilinx.com:xgui.ui + + xilinx_xpgui_view_fileset + + + + viewChecksum + 355527df + + + + + xilinx_readme + Readme + :vivado.xilinx.com:docs.readme + + xilinx_readme_view_fileset + + + + viewChecksum + c44355bc + + + + + xilinx_utilityxitfiles + Utility XIT/TTCL + :vivado.xilinx.com:xit.util + + xilinx_utilityxitfiles_view_fileset + + + + viewChecksum + 9c3b79bd + + + + + + + clk + + in + + + wire + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + shift_in + + in + + + wire + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + parallel_in + + in + + 3 + 0 + + + + wire + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + 0 + + + + + + optional + true + + + + + + load + + in + + + wire + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + 0 + + + + + + optional + true + + + + + + en + + in + + + wire + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + 1 + + + + + + optional + true + + + + + + dir + + in + + + wire + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + 0 + + + + + + optional + true + + + + + + shift_out + + out + + + wire + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + parallel_out + + out + + 3 + 0 + + + + wire + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + 0 + + + + + + optional + true + + + + + + + + SIZE + Size + 4 + + + DELAY + Delay + 3 + + + PARALLEL_IN + Parallel In + true + + + EN + En + true + + + LOAD + Load + true + + + DIR + Dir + true + + + PARALLEL_OUT + Parallel Out + true + + + + + + choices_0 + 0 + 1 + + + + + xilinx_verilogsynthesis_view_fileset + + src/xup_shift_register.v + verilogSource + CHECKSUM_1576e397 + + + + xilinx_verilogbehavioralsimulation_view_fileset + + src/xup_shift_register.v + verilogSource + + + + xilinx_verilogtestbench_view_fileset + + src/shift_register_tb.v + verilogSource + IMPORTED_FILE + + + + xilinx_xpgui_view_fileset + + xgui/xup_shift_register_v1_0.tcl + tclSource + XGUI_VERSION_2 + CHECKSUM_82b86c79 + + + + xilinx_readme_view_fileset + + doc/readme.txt + text + + + + xilinx_utilityxitfiles_view_fileset + + misc/xup.png + image + LOGO + + + + Shift Register with selectable load, enable, direction, parallel_in, and parallel_out pins, and SIZE and DELAY configurable parameters + + + SIZE + Size + 4 + + + DELAY + Delay + 3 + + + Component_Name + xup_shift_register_v1_0 + + + PARALLEL_IN + Parallel In Port + true + + + EN + EN Port + true + + + LOAD + LOAD Port + true + + + DIR + Direction Port + true + + + PARALLEL_OUT + Parallel Out Port + true + + + + + + virtex7 + artix7 + kintex7 + zynq + + + /BaseIP + + xup_shift_register_v1_0 + XUP + http://www.xilinx.com/university + 4 + 2015-04-22T14:52:17Z + + C:/xup/IPI_Lib/shift_register/shift_register.srcs/sources_1/imports + + + + 2014.4 + + + + + + + + diff --git a/Library/XUP_LIB/xup_shift_register_1.0/doc/readme.txt b/Library/XUP_LIB/xup_shift_register_1.0/doc/readme.txt new file mode 100644 index 0000000..dd856b7 --- /dev/null +++ b/Library/XUP_LIB/xup_shift_register_1.0/doc/readme.txt @@ -0,0 +1,33 @@ +Tool and version: Vivado 2014.4 +Target Families: Artix-7, Kintex-7, Virtex-7, and Zynq + +Introduction: +This IP is a member of XUP_LIB created by XUP. The XUP_LIB provides the basic gates/functionality that can be used in digital design.This IP has selectable load, en, dir, parallel_in input ports and parallel_out output ports. When the ports are not selected, load is tied to logic0, en is tied to logic1, dir i stied to logic0 (right-shift), and parallel_in is tied to 0. + +The configurable parameters are SIZE and DELAY. + +Input/Output Ports: +Input: +clk - 100 MHz clock, default, but can be different +shift_in - serial data in +parallel_in - vector input port, when not selected it is tied to 0 +load - load parallel data, when not selected it is tied to logic0 (no-load) +en - enable shifting, when not selected it is tied to logic1 (always shifting) +dir - direction, 1 means left and 0 means right, when not selected it is tied to logic0 + +Output: +shift_out - shifted output +parallel_out - vectored output, selectable + +Setting up the library path: +Create a Vivado project. Click on the Project Settings, then click on the IP block in the left panel, click on the Add Repository... button, browse to the directory where this IP directory is located, and click Select. The IP entry should be visible in the IP in the Selected Repository. + +How to use the IP: +Step 1: Create a Vivado project +Step 2: Set the Project Settings to point to the IP path +Step 3: Create a block design +Step 4: Add the desired IP on the canvas, connect them, and add external input and output ports +Step 5: Create a HDL wrapper +Step 6: Add constraints file (.xdc) +Step 7: Synthesize, implement, and generate the bitstream +Step 8: Connect the board, download the bitstream, and varify the design diff --git a/Library/XUP_LIB/xup_shift_register_1.0/misc/xup.png b/Library/XUP_LIB/xup_shift_register_1.0/misc/xup.png new file mode 100644 index 0000000..6949927 Binary files /dev/null and b/Library/XUP_LIB/xup_shift_register_1.0/misc/xup.png differ diff --git a/Library/XUP_LIB/xup_shift_register_1.0/src/shift_register_tb.v b/Library/XUP_LIB/xup_shift_register_1.0/src/shift_register_tb.v new file mode 100644 index 0000000..44ba27d --- /dev/null +++ b/Library/XUP_LIB/xup_shift_register_1.0/src/shift_register_tb.v @@ -0,0 +1,48 @@ +`timescale 1ns / 1ps +///////////////////////////////////////////////////////////////// +// Module Name: shift_register_tb +///////////////////////////////////////////////////////////////// + +module shift_register_tb( + ); + + reg clk; + reg shift_in; + reg load, en, dir; + reg [5:0] p_in; + wire shift_out; + wire [5:0] p_out; + + xup_shift_register #(.SIZE(6),.DELAY(4)) DUT (.clk(clk), .shift_in(shift_in), .load(load), .en(en), .dir(dir), .parallel_in(p_in), .shift_out(shift_out), .parallel_out(p_out)); + + always + #5 clk = ~clk; // every ten nanoseconds invert the clock + + initial + begin + clk=0; + load=0; + en=0; + dir=0; + shift_in=1; + p_in=5'b101101; + #10 load=1; + #10 load=0; + #30 en=1; + #40; + #10 dir=1; + #40; + #10 load=1; + #10 load=0; + #20; + #10 en=0; + #20; + #10 en=1; + #30; + #10 shift_in=0; + #40; + #10 dir=0; + #40; + end + +endmodule diff --git a/Library/XUP_LIB/xup_shift_register_1.0/src/xup_shift_register.v b/Library/XUP_LIB/xup_shift_register_1.0/src/xup_shift_register.v new file mode 100644 index 0000000..9b9f516 --- /dev/null +++ b/Library/XUP_LIB/xup_shift_register_1.0/src/xup_shift_register.v @@ -0,0 +1,31 @@ +`timescale 1ns / 1ps +///////////////////////////////////////////////////////////////// +// Module Name: xup_shift_register +///////////////////////////////////////////////////////////////// + +module xup_shift_register#(parameter SIZE=4, DELAY=3, PARALLEL_IN=1, EN=1, LOAD=1, DIR=1, PARALLEL_OUT=1) +( + input wire clk, + input wire shift_in, + input wire [SIZE-1:0]parallel_in, + input wire load, + input wire en, + input wire dir, + output wire shift_out, + output wire [SIZE-1:0] parallel_out + ); + + reg [SIZE-1:0] shift_reg; + always @(posedge clk) + if(load) + shift_reg <= parallel_in; + else if (en) + if (dir) // dir=1 then left shift + shift_reg <= {shift_reg[SIZE-2:0], shift_in}; + else + shift_reg <= {shift_in, shift_reg[SIZE-1:1]}; + + assign #DELAY shift_out = dir ? shift_reg[SIZE-1] : shift_reg[0]; + assign #DELAY parallel_out = shift_reg; + +endmodule diff --git a/Library/XUP_LIB/xup_shift_register_1.0/xgui/xup_shift_register_v1_0.tcl b/Library/XUP_LIB/xup_shift_register_1.0/xgui/xup_shift_register_v1_0.tcl new file mode 100644 index 0000000..5917449 --- /dev/null +++ b/Library/XUP_LIB/xup_shift_register_1.0/xgui/xup_shift_register_v1_0.tcl @@ -0,0 +1,123 @@ +# Definitional proc to organize widgets for parameters. +proc init_gui { IPINST } { + ipgui::add_param $IPINST -name "Component_Name" + #Adding Page + set Page_0 [ipgui::add_page $IPINST -name "Page 0"] + ipgui::add_param $IPINST -name "DELAY" -parent ${Page_0} + ipgui::add_param $IPINST -name "SIZE" -parent ${Page_0} + ipgui::add_param $IPINST -name "PARALLEL_IN" -parent ${Page_0} + ipgui::add_param $IPINST -name "EN" -parent ${Page_0} + ipgui::add_param $IPINST -name "LOAD" -parent ${Page_0} + ipgui::add_param $IPINST -name "DIR" -parent ${Page_0} + ipgui::add_param $IPINST -name "PARALLEL_OUT" -parent ${Page_0} + ipgui::add_static_text $IPINST -name "Selectable Options" -parent ${Page_0} -text {parallel_in - When not selected it is tied to 0 +load - When not selected it is tied to logic0 (no parallel load) +en - When not selected it is tied to logic1 (always shifting) +dir - When not selected it is tied to logic0 (right shift) + +parallel_out - Selectable + +} + + +} + +proc update_PARAM_VALUE.DELAY { PARAM_VALUE.DELAY } { + # Procedure called to update DELAY when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.DELAY { PARAM_VALUE.DELAY } { + # Procedure called to validate DELAY + return true +} + +proc update_PARAM_VALUE.DIR { PARAM_VALUE.DIR } { + # Procedure called to update DIR when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.DIR { PARAM_VALUE.DIR } { + # Procedure called to validate DIR + return true +} + +proc update_PARAM_VALUE.EN { PARAM_VALUE.EN } { + # Procedure called to update EN when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.EN { PARAM_VALUE.EN } { + # Procedure called to validate EN + return true +} + +proc update_PARAM_VALUE.LOAD { PARAM_VALUE.LOAD } { + # Procedure called to update LOAD when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.LOAD { PARAM_VALUE.LOAD } { + # Procedure called to validate LOAD + return true +} + +proc update_PARAM_VALUE.PARALLEL_IN { PARAM_VALUE.PARALLEL_IN } { + # Procedure called to update PARALLEL_IN when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.PARALLEL_IN { PARAM_VALUE.PARALLEL_IN } { + # Procedure called to validate PARALLEL_IN + return true +} + +proc update_PARAM_VALUE.PARALLEL_OUT { PARAM_VALUE.PARALLEL_OUT } { + # Procedure called to update PARALLEL_OUT when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.PARALLEL_OUT { PARAM_VALUE.PARALLEL_OUT } { + # Procedure called to validate PARALLEL_OUT + return true +} + +proc update_PARAM_VALUE.SIZE { PARAM_VALUE.SIZE } { + # Procedure called to update SIZE when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.SIZE { PARAM_VALUE.SIZE } { + # Procedure called to validate SIZE + return true +} + + +proc update_MODELPARAM_VALUE.SIZE { MODELPARAM_VALUE.SIZE PARAM_VALUE.SIZE } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.SIZE}] ${MODELPARAM_VALUE.SIZE} +} + +proc update_MODELPARAM_VALUE.DELAY { MODELPARAM_VALUE.DELAY PARAM_VALUE.DELAY } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.DELAY}] ${MODELPARAM_VALUE.DELAY} +} + +proc update_MODELPARAM_VALUE.PARALLEL_IN { MODELPARAM_VALUE.PARALLEL_IN PARAM_VALUE.PARALLEL_IN } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.PARALLEL_IN}] ${MODELPARAM_VALUE.PARALLEL_IN} +} + +proc update_MODELPARAM_VALUE.EN { MODELPARAM_VALUE.EN PARAM_VALUE.EN } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.EN}] ${MODELPARAM_VALUE.EN} +} + +proc update_MODELPARAM_VALUE.LOAD { MODELPARAM_VALUE.LOAD PARAM_VALUE.LOAD } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.LOAD}] ${MODELPARAM_VALUE.LOAD} +} + +proc update_MODELPARAM_VALUE.DIR { MODELPARAM_VALUE.DIR PARAM_VALUE.DIR } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.DIR}] ${MODELPARAM_VALUE.DIR} +} + +proc update_MODELPARAM_VALUE.PARALLEL_OUT { MODELPARAM_VALUE.PARALLEL_OUT PARAM_VALUE.PARALLEL_OUT } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.PARALLEL_OUT}] ${MODELPARAM_VALUE.PARALLEL_OUT} +} + diff --git a/Projects/Logic_Design/CN_Design/Carry_Look_Ahead_Adder/README.md b/Projects/Logic_Design/CN_Design/Carry_Look_Ahead_Adder/README.md new file mode 100644 index 0000000..24f4c18 --- /dev/null +++ b/Projects/Logic_Design/CN_Design/Carry_Look_Ahead_Adder/README.md @@ -0,0 +1,57 @@ +# Carry-Lookahead Adder +This project creates an 8-bit carry-lookahead adder using XUP_LIB components. You must download the XUP_LIB directory from the GitHub and then set the XUP_LIB path. You must also download Basys3 board files directory from the GitHub and place it in the **\\2014.4\data\boards\board_parts\artix7** directory. + +The project source files include a Tcl script, Xilinx Design Constraint (xdc) file targeting Basys3 board, testbench, and a wave configuration (wcfg) file. + +### Design Description: +The 8 bit adder is built from two 4-bit carry-lookahead adders. +The 4-bit carry-lookahead adder is built from four partial full adders and the carry lookahead unit (4-bit). The hierarchy of the design can be explored by opening or expanding the hierarchical blocks. + +### Tools and other requirements: +* Vivado 2014.4 +* XUP_LIB from GitHub +* Basys3 board files from GitHub + +### Procedure: +1\. Start Vivado +2\. Set the path basys3_github to the XUP_LIB using command like in the Vivado Tcl Console. Note the path uses "/" instead of "\". Substiture the path where you have stored the XUP_LIB library. + +set basys3_github {C:/xup/IPI_LIB/XUP_LIB} + +2\. Set a variable *basys3_github* to the XUP_LIB path in the Vivado Tcl Console. Note the path uses "/" instead of "\". Substitute the path to where you have saved the XUP_LIB library: + +**set basys3_github {C:/xup/IPI_LIB/XUP_LIB}** + +3\. Change to the *src* directory of this project using the *cd* command: + +**cd \** + +4\. Execute the following command to run the script + +**source ./carry_lookahead_adder.tcl** + +5\. Once the project is created, the resulting block diagram will be displayed. View the block diagram, double click or expand blocks to navigate the hierarchy and analyze the design + +6\. Execute the following command to run the behavioral simulation: + +**run_sim** + +7\. Analyze the results and notice the output transitioning after the input changes. When satisfied, close the simulator: + +**close_sim** + +8\. Generate the bitstream by clicking on the *Generate Bitstream* under the *Program and Debug* group + +9\. When the bitstream generation is completed, connect the board, power ON the board, and use the *Open Hardware Manager* option to connect to the board + +10\. *Program* the board and verify the functionality + +Input 1 : Dipswitches 0-7 + +Input 2 : Dipswitches 8-15 + +Result : Leds 0-7 + +Carry In : Centre pushbutton + +Carry Out : Led 15 diff --git a/Projects/Logic_Design/CN_Design/Carry_Look_Ahead_Adder/src/carry_lookahead_adder.tcl b/Projects/Logic_Design/CN_Design/Carry_Look_Ahead_Adder/src/carry_lookahead_adder.tcl new file mode 100644 index 0000000..ab51dd0 --- /dev/null +++ b/Projects/Logic_Design/CN_Design/Carry_Look_Ahead_Adder/src/carry_lookahead_adder.tcl @@ -0,0 +1,391 @@ +# Script to create 8-bit carry lookahead carry adder from XUP_LIB components. Set XUP_LIB path below before running +# +# The 8 bit adder is built from two 4-bit carry lookahead adders. +# The 4-bit carry lookahead adder is built from four partial full adders and the carry lookahead unit (4-bit). +# The hierarchy of the design can be explored by opening or expanding the hierarchical blocks +# +# Vivado 2014.4 +# Basys 3 board +# 1 May 2015 +# CMC +# Notes: Set the path below to the XUP_LIB, and run source carry_lookahead_adder.tcl to create the design +# It is assumed the pin constraints xdc file (carry_lookahead_adder_basys3_pins.xdc) is in the project directory. +# If the constraints file is located somewhere else, modify the constraints_directory path below +# +# After sourcing this script, run_sim can be executed to drive simulation from proc at bottom of this file +# Once simulation is running (either from the GUI, or from this script) test_pattern can be executed to drive +# simulation input values defined a the bottom of this file +# +# Two 8-bit inputs (operands), a and b, are connected to the dip switches (a sw0-7, b sw 8-15) +# The 8-bit output (s) is connected to LEDs 0-7 +# carry in is connected to the centre pushbutton +# carry out is connected to LED 15 +# -------------------------------------------------------------- # +# SET 'basys3_github' PATH TO GITHUB LIBRARY BEFORE RUNNING +# -------------------------------------------------------------- # +set basys3_github {C:/xup/IPI_LIB/XUP_LIB} + +set project_directory . +set project_name carry_lookahead_adder +set constraints_directory $project_directory +set constraints_file carry_lookahead_adder_basys3_pins.xdc +set testbench carry_lookahead_adder_tb.v +# Create project for Basys 3 +create_project -force $project_name ./$project_name -part xc7a35tcpg236-1 +set_property board_part digilentinc.com:basys3:part0:1.1 [current_project] +set_property target_language verilog [current_project] +set_property simulator_language Verilog [current_project] +set_property ip_repo_paths $basys3_github [current_project] +update_ip_catalog +create_bd_design "$project_name" + +# Steps: +# Build Partial adder +# Copy and paste 3 times to generate 4 partial adders in total +# create carry lookahead adder logic (cla) +# Connect to cla to make 4-bit carry ripple adders +# Copy and paste 4-bit adder to make 8-bit adder + +# Create Full adder +# add 1st XOR gate for a and b +create_bd_cell -type ip -vlnv xilinx.com:XUP:xup_xor2:1.0 xor_ab +# add 2nd XOR gate for s +create_bd_cell -type ip -vlnv xilinx.com:XUP:xup_xor2:1.0 xor_s +# add AND gate for Propogate +create_bd_cell -type ip -vlnv xilinx.com:XUP:xup_or2:1.0 or_propogate +# add AND gate for Generate +create_bd_cell -type ip -vlnv xilinx.com:XUP:xup_and2:1.0 and_generate + +#create partial_full_adder hierarchical block +group_bd_cells partial_full_adder [get_bd_cells xor_ab] [get_bd_cells xor_s] [get_bd_cells or_propogate] [get_bd_cells and_generate] +# create partial full adder pins +create_bd_pin -dir I partial_full_adder/a +create_bd_pin -dir I partial_full_adder/b +create_bd_pin -dir I partial_full_adder/c_in +create_bd_pin -dir O partial_full_adder/s +create_bd_pin -dir O partial_full_adder/p +create_bd_pin -dir O partial_full_adder/g +# connect partial adder nets +connect_bd_net [get_bd_pins partial_full_adder/a] [get_bd_pins partial_full_adder/xor_ab/a] +connect_bd_net [get_bd_pins partial_full_adder/b] [get_bd_pins partial_full_adder/xor_ab/b] +connect_bd_net [get_bd_pins partial_full_adder/xor_ab/y] [get_bd_pins partial_full_adder/xor_s/a] +connect_bd_net [get_bd_pins partial_full_adder/c_in] [get_bd_pins partial_full_adder/xor_s/b] +connect_bd_net [get_bd_pins partial_full_adder/xor_s/y] [get_bd_pins partial_full_adder/s] + +connect_bd_net [get_bd_pins partial_full_adder/a] [get_bd_pins partial_full_adder/or_propogate/a] +connect_bd_net [get_bd_pins partial_full_adder/b] [get_bd_pins partial_full_adder/or_propogate/b] +connect_bd_net [get_bd_pins partial_full_adder/or_propogate/y] [get_bd_pins partial_full_adder/p] + +connect_bd_net [get_bd_pins partial_full_adder/a] [get_bd_pins partial_full_adder/and_generate/a] +connect_bd_net [get_bd_pins partial_full_adder/b] [get_bd_pins partial_full_adder/and_generate/b] +connect_bd_net [get_bd_pins partial_full_adder/and_generate/y] [get_bd_pins partial_full_adder/g] + +# Copy and paste partial full adder +copy_bd_objs / [get_bd_cells {partial_full_adder}] +copy_bd_objs / [get_bd_cells {partial_full_adder}] +copy_bd_objs / [get_bd_cells {partial_full_adder}] + +# --------------------------------------------------------------------------------# +# Create carry look ahead logic +create_bd_cell -type hier cla_logic +# create cla pins +create_bd_pin -dir I cla_logic/c0 + +create_bd_pin -dir I cla_logic/p0 +create_bd_pin -dir I cla_logic/g0 +create_bd_pin -dir I cla_logic/p1 +create_bd_pin -dir I cla_logic/g1 +create_bd_pin -dir I cla_logic/p2 +create_bd_pin -dir I cla_logic/g2 +create_bd_pin -dir I cla_logic/p3 +create_bd_pin -dir I cla_logic/g3 + +create_bd_pin -dir O cla_logic/c1 +create_bd_pin -dir O cla_logic/c2 +create_bd_pin -dir O cla_logic/c3 +create_bd_pin -dir O cla_logic/c4 + +# create logic for c1 +# c1 = g0 +p0c0 +create_bd_cell -type ip -vlnv xilinx.com:XUP:xup_or2:1.0 cla_logic/c1_or +create_bd_cell -type ip -vlnv xilinx.com:XUP:xup_and2:1.0 cla_logic/c1_and +# connect +connect_bd_net [get_bd_pins cla_logic/c0] [get_bd_pins cla_logic/c1_and/a] +connect_bd_net [get_bd_pins cla_logic/p0] [get_bd_pins cla_logic/c1_and/b] + +connect_bd_net [get_bd_pins cla_logic/c1_and/y] [get_bd_pins cla_logic/c1_or/a] +connect_bd_net [get_bd_pins cla_logic/g0] [get_bd_pins cla_logic/c1_or/b] +#connect_bd_net [get_bd_pins cla_logic/c1_and/y] [get_bd_pins cla_logic/c1_or/a] +connect_bd_net [get_bd_pins cla_logic/c1_or/y] [get_bd_pins cla_logic/c1] + +# c2 = g1 + p1g0 + p1p0c0 +create_bd_cell -type ip -vlnv xilinx.com:XUP:xup_and2:1.0 cla_logic/p1g0_and +create_bd_cell -type ip -vlnv xilinx.com:XUP:xup_and3:1.0 cla_logic/p1p0c0_and +create_bd_cell -type ip -vlnv xilinx.com:XUP:xup_or3:1.0 cla_logic/c2_or +#connect +connect_bd_net [get_bd_pins cla_logic/p1] [get_bd_pins cla_logic/p1g0_and/a] +connect_bd_net [get_bd_pins cla_logic/g0] [get_bd_pins cla_logic/p1g0_and/b] + +connect_bd_net [get_bd_pins cla_logic/p1] [get_bd_pins cla_logic/p1p0c0_and/a] +connect_bd_net [get_bd_pins cla_logic/p0] [get_bd_pins cla_logic/p1p0c0_and/b] +connect_bd_net [get_bd_pins cla_logic/c0] [get_bd_pins cla_logic/p1p0c0_and/c] + +connect_bd_net [get_bd_pins cla_logic/g1] [get_bd_pins cla_logic/c2_or/a] +connect_bd_net [get_bd_pins cla_logic/p1g0_and/y] [get_bd_pins cla_logic/c2_or/b] +connect_bd_net [get_bd_pins cla_logic/p1p0c0_and/y] [get_bd_pins cla_logic/c2_or/c] + +connect_bd_net [get_bd_pins cla_logic/c2_or/y] [get_bd_pins cla_logic/c2] + +#c3 = g2 + p2g1 + p2p1g0 + p2p1p0c0 +create_bd_cell -type ip -vlnv xilinx.com:XUP:xup_and2:1.0 cla_logic/p2g1 +create_bd_cell -type ip -vlnv xilinx.com:XUP:xup_and3:1.0 cla_logic/p2p1g0 +create_bd_cell -type ip -vlnv xilinx.com:XUP:xup_and4:1.0 cla_logic/p2p1p0c0 + +create_bd_cell -type ip -vlnv xilinx.com:XUP:xup_or4:1.0 cla_logic/c3_or +# connect +connect_bd_net [get_bd_pins cla_logic/p2] [get_bd_pins cla_logic/p2g1/a] +connect_bd_net [get_bd_pins cla_logic/g1] [get_bd_pins cla_logic/p2g1/b] + +connect_bd_net [get_bd_pins cla_logic/p2] [get_bd_pins cla_logic/p2p1g0/a] +connect_bd_net [get_bd_pins cla_logic/p1] [get_bd_pins cla_logic/p2p1g0/b] +connect_bd_net [get_bd_pins cla_logic/g0] [get_bd_pins cla_logic/p2p1g0/c] + +connect_bd_net [get_bd_pins cla_logic/p2] [get_bd_pins cla_logic/p2p1p0c0/a] +connect_bd_net [get_bd_pins cla_logic/p1] [get_bd_pins cla_logic/p2p1p0c0/b] +connect_bd_net [get_bd_pins cla_logic/p0] [get_bd_pins cla_logic/p2p1p0c0/c] +connect_bd_net [get_bd_pins cla_logic/c0] [get_bd_pins cla_logic/p2p1p0c0/d] + +connect_bd_net [get_bd_pins cla_logic/g2] [get_bd_pins cla_logic/c3_or/a] +connect_bd_net [get_bd_pins cla_logic/p2g1/y] [get_bd_pins cla_logic/c3_or/b] +connect_bd_net [get_bd_pins cla_logic/p2p1g0/y] [get_bd_pins cla_logic/c3_or/c] +connect_bd_net [get_bd_pins cla_logic/p2p1p0c0/y] [get_bd_pins cla_logic/c3_or/d] + +connect_bd_net [get_bd_pins cla_logic/c3_or/y] [get_bd_pins cla_logic/c3] + +#c4 = g3 + p3g2 + p3p2g1 + p3p2p1g0 + p3p2p1p0c0 +# create gates +create_bd_cell -type ip -vlnv xilinx.com:XUP:xup_and2:1.0 cla_logic/p3g2 +create_bd_cell -type ip -vlnv xilinx.com:XUP:xup_and3:1.0 cla_logic/p3p2g1 +create_bd_cell -type ip -vlnv xilinx.com:XUP:xup_and4:1.0 cla_logic/p3p2p1g0 +create_bd_cell -type ip -vlnv xilinx.com:XUP:xup_and5:1.0 cla_logic/p3p2p1p0c0 + +create_bd_cell -type ip -vlnv xilinx.com:XUP:xup_or5:1.0 cla_logic/c4_or +# connect +connect_bd_net [get_bd_pins cla_logic/p3] [get_bd_pins cla_logic/p3g2/a] +connect_bd_net [get_bd_pins cla_logic/g2] [get_bd_pins cla_logic/p3g2/b] + +connect_bd_net [get_bd_pins cla_logic/p3] [get_bd_pins cla_logic/p3p2g1/a] +connect_bd_net [get_bd_pins cla_logic/p2] [get_bd_pins cla_logic/p3p2g1/b] +connect_bd_net [get_bd_pins cla_logic/g1] [get_bd_pins cla_logic/p3p2g1/c] + +connect_bd_net [get_bd_pins cla_logic/p3] [get_bd_pins cla_logic/p3p2p1g0/a] +connect_bd_net [get_bd_pins cla_logic/p2] [get_bd_pins cla_logic/p3p2p1g0/b] +connect_bd_net [get_bd_pins cla_logic/p1] [get_bd_pins cla_logic/p3p2p1g0/c] +connect_bd_net [get_bd_pins cla_logic/g0] [get_bd_pins cla_logic/p3p2p1g0/d] + +connect_bd_net [get_bd_pins cla_logic/p3] [get_bd_pins cla_logic/p3p2p1p0c0/a] +connect_bd_net [get_bd_pins cla_logic/p2] [get_bd_pins cla_logic/p3p2p1p0c0/b] +connect_bd_net [get_bd_pins cla_logic/p1] [get_bd_pins cla_logic/p3p2p1p0c0/c] +connect_bd_net [get_bd_pins cla_logic/p0] [get_bd_pins cla_logic/p3p2p1p0c0/d] +connect_bd_net [get_bd_pins cla_logic/c0] [get_bd_pins cla_logic/p3p2p1p0c0/e] + +connect_bd_net [get_bd_pins cla_logic/g3] [get_bd_pins cla_logic/c4_or/a] +connect_bd_net [get_bd_pins cla_logic/p3g2/y] [get_bd_pins cla_logic/c4_or/b] +connect_bd_net [get_bd_pins cla_logic/p3p2g1/y] [get_bd_pins cla_logic/c4_or/c] +connect_bd_net [get_bd_pins cla_logic/p3p2p1g0/y] [get_bd_pins cla_logic/c4_or/d] +connect_bd_net [get_bd_pins cla_logic/p3p2p1p0c0/y] [get_bd_pins cla_logic/c4_or/e] + +connect_bd_net [get_bd_pins cla_logic/c4_or/y] [get_bd_pins cla_logic/c4] + +# connect partial adders and CLA logic +connect_bd_net [get_bd_pins partial_full_adder/p] [get_bd_pins cla_logic/p0] +connect_bd_net [get_bd_pins partial_full_adder1/p] [get_bd_pins cla_logic/p1] +connect_bd_net [get_bd_pins partial_full_adder2/p] [get_bd_pins cla_logic/p2] +connect_bd_net [get_bd_pins partial_full_adder3/p] [get_bd_pins cla_logic/p3] +connect_bd_net [get_bd_pins partial_full_adder/g] [get_bd_pins cla_logic/g0] +connect_bd_net [get_bd_pins partial_full_adder1/g] [get_bd_pins cla_logic/g1] +connect_bd_net [get_bd_pins partial_full_adder2/g] [get_bd_pins cla_logic/g2] +connect_bd_net [get_bd_pins partial_full_adder3/g] [get_bd_pins cla_logic/g3] +connect_bd_net [get_bd_pins cla_logic/c1] [get_bd_pins partial_full_adder1/c_in] +connect_bd_net [get_bd_pins cla_logic/c2] [get_bd_pins partial_full_adder2/c_in] +connect_bd_net [get_bd_pins cla_logic/c3] [get_bd_pins partial_full_adder3/c_in] +# CLA block completed +# --------------------------------------------------------------------------------# + +#create full_adder hierarchical block +group_bd_cells carry_lookahead_adder_4_bit [get_bd_cells partial_full_adder] [get_bd_cells partial_full_adder1] [get_bd_cells partial_full_adder2] [get_bd_cells partial_full_adder3] [get_bd_cells cla_logic] +# create full adder pins +create_bd_pin -dir I carry_lookahead_adder_4_bit/a0 +create_bd_pin -dir I carry_lookahead_adder_4_bit/a1 +create_bd_pin -dir I carry_lookahead_adder_4_bit/a2 +create_bd_pin -dir I carry_lookahead_adder_4_bit/a3 +create_bd_pin -dir I carry_lookahead_adder_4_bit/b0 +create_bd_pin -dir I carry_lookahead_adder_4_bit/b1 +create_bd_pin -dir I carry_lookahead_adder_4_bit/b2 +create_bd_pin -dir I carry_lookahead_adder_4_bit/b3 +create_bd_pin -dir I carry_lookahead_adder_4_bit/c_in +create_bd_pin -dir O carry_lookahead_adder_4_bit/s0 +create_bd_pin -dir O carry_lookahead_adder_4_bit/s1 +create_bd_pin -dir O carry_lookahead_adder_4_bit/s2 +create_bd_pin -dir O carry_lookahead_adder_4_bit/s3 +create_bd_pin -dir O carry_lookahead_adder_4_bit/c_out + +# connect internal ports to hierarchy pins +connect_bd_net [get_bd_pins carry_lookahead_adder_4_bit/a0] [get_bd_pins carry_lookahead_adder_4_bit/partial_full_adder/a] +connect_bd_net [get_bd_pins carry_lookahead_adder_4_bit/a1] [get_bd_pins carry_lookahead_adder_4_bit/partial_full_adder1/a] +connect_bd_net [get_bd_pins carry_lookahead_adder_4_bit/a2] [get_bd_pins carry_lookahead_adder_4_bit/partial_full_adder2/a] +connect_bd_net [get_bd_pins carry_lookahead_adder_4_bit/a3] [get_bd_pins carry_lookahead_adder_4_bit/partial_full_adder3/a] +connect_bd_net [get_bd_pins carry_lookahead_adder_4_bit/b0] [get_bd_pins carry_lookahead_adder_4_bit/partial_full_adder/b] +connect_bd_net [get_bd_pins carry_lookahead_adder_4_bit/b1] [get_bd_pins carry_lookahead_adder_4_bit/partial_full_adder1/b] +connect_bd_net [get_bd_pins carry_lookahead_adder_4_bit/b2] [get_bd_pins carry_lookahead_adder_4_bit/partial_full_adder2/b] +connect_bd_net [get_bd_pins carry_lookahead_adder_4_bit/b3] [get_bd_pins carry_lookahead_adder_4_bit/partial_full_adder3/b] +connect_bd_net [get_bd_pins carry_lookahead_adder_4_bit/c_in] [get_bd_pins carry_lookahead_adder_4_bit/partial_full_adder/c_in] +connect_bd_net [get_bd_pins carry_lookahead_adder_4_bit/c_in] [get_bd_pins carry_lookahead_adder_4_bit/cla_logic/c0] +connect_bd_net [get_bd_pins carry_lookahead_adder_4_bit/s0] [get_bd_pins carry_lookahead_adder_4_bit/partial_full_adder/s] +connect_bd_net [get_bd_pins carry_lookahead_adder_4_bit/s1] [get_bd_pins carry_lookahead_adder_4_bit/partial_full_adder1/s] +connect_bd_net [get_bd_pins carry_lookahead_adder_4_bit/s2] [get_bd_pins carry_lookahead_adder_4_bit/partial_full_adder2/s] +connect_bd_net [get_bd_pins carry_lookahead_adder_4_bit/s3] [get_bd_pins carry_lookahead_adder_4_bit/partial_full_adder3/s] +connect_bd_net [get_bd_pins carry_lookahead_adder_4_bit/c_out] [get_bd_pins carry_lookahead_adder_4_bit/cla_logic/c4] +# copy and paste 4-bit adder +copy_bd_objs / [get_bd_cells {carry_lookahead_adder_4_bit}] +#connect carrys +connect_bd_net [get_bd_pins carry_lookahead_adder_4_bit/c_out] [get_bd_pins carry_lookahead_adder_4_bit1/c_in] -boundary_type upper +#Create top level i/o ports and connect to 4 bit adders +# a +create_bd_port -dir I a0 +connect_bd_net [get_bd_pins /carry_lookahead_adder_4_bit/a0] [get_bd_ports a0] +create_bd_port -dir I a1 +connect_bd_net [get_bd_pins /carry_lookahead_adder_4_bit/a1] [get_bd_ports a1] +create_bd_port -dir I a2 +connect_bd_net [get_bd_pins /carry_lookahead_adder_4_bit/a2] [get_bd_ports a2] +create_bd_port -dir I a3 +connect_bd_net [get_bd_pins /carry_lookahead_adder_4_bit/a3] [get_bd_ports a3] +create_bd_port -dir I a4 +connect_bd_net [get_bd_pins /carry_lookahead_adder_4_bit1/a0] [get_bd_ports a4] +create_bd_port -dir I a5 +connect_bd_net [get_bd_pins /carry_lookahead_adder_4_bit1/a1] [get_bd_ports a5] +create_bd_port -dir I a6 +connect_bd_net [get_bd_pins /carry_lookahead_adder_4_bit1/a2] [get_bd_ports a6] +create_bd_port -dir I a7 +connect_bd_net [get_bd_pins /carry_lookahead_adder_4_bit1/a3] [get_bd_ports a7] +# b +create_bd_port -dir I b0 +connect_bd_net [get_bd_pins /carry_lookahead_adder_4_bit/b0] [get_bd_ports b0] +create_bd_port -dir I b2 +connect_bd_net [get_bd_pins /carry_lookahead_adder_4_bit/b2] [get_bd_ports b2] +create_bd_port -dir I b1 +connect_bd_net [get_bd_pins /carry_lookahead_adder_4_bit/b1] [get_bd_ports b1] +create_bd_port -dir I b3 +connect_bd_net [get_bd_pins /carry_lookahead_adder_4_bit/b3] [get_bd_ports b3] +create_bd_port -dir I b4 +connect_bd_net [get_bd_pins /carry_lookahead_adder_4_bit1/b0] [get_bd_ports b4] +create_bd_port -dir I b5 +connect_bd_net [get_bd_pins /carry_lookahead_adder_4_bit1/b1] [get_bd_ports b5] +create_bd_port -dir I b6 +connect_bd_net [get_bd_pins /carry_lookahead_adder_4_bit1/b2] [get_bd_ports b6] +create_bd_port -dir I b7 +connect_bd_net [get_bd_pins /carry_lookahead_adder_4_bit1/b3] [get_bd_ports b7] +create_bd_port -dir O s0 +# carry in +create_bd_port -dir I c_in +connect_bd_net [get_bd_pins /carry_lookahead_adder_4_bit/c_in] [get_bd_ports c_in] +# outputs +connect_bd_net [get_bd_pins /carry_lookahead_adder_4_bit/s0] [get_bd_ports s0] +create_bd_port -dir O s1 +connect_bd_net [get_bd_pins /carry_lookahead_adder_4_bit/s1] [get_bd_ports s1] +create_bd_port -dir O s2 +connect_bd_net [get_bd_pins /carry_lookahead_adder_4_bit/s2] [get_bd_ports s2] +create_bd_port -dir O s3 +connect_bd_net [get_bd_pins /carry_lookahead_adder_4_bit/s3] [get_bd_ports s3] +create_bd_port -dir O s4 +connect_bd_net [get_bd_pins /carry_lookahead_adder_4_bit1/s0] [get_bd_ports s4] +create_bd_port -dir O s5 +connect_bd_net [get_bd_pins /carry_lookahead_adder_4_bit1/s1] [get_bd_ports s5] +create_bd_port -dir O s6 +connect_bd_net [get_bd_pins /carry_lookahead_adder_4_bit1/s2] [get_bd_ports s6] +create_bd_port -dir O s7 +connect_bd_net [get_bd_pins /carry_lookahead_adder_4_bit1/s3] [get_bd_ports s7] +# carry out +create_bd_port -dir O c_out +connect_bd_net [get_bd_pins /carry_lookahead_adder_4_bit1/c_out] [get_bd_ports c_out] + +regenerate_bd_layout +save_bd_design + +# Create top HDL wrapper +make_wrapper -files [get_files $project_directory/$project_name/$project_name.srcs/sources_1/bd/$project_name/$project_name.bd] -top +add_files -norecurse $project_directory/$project_name/$project_name.srcs/sources_1/bd/$project_name/hdl/$project_name\_wrapper.v +# Add pin constraints +add_files -fileset constrs_1 -norecurse $constraints_directory/$constraints_file +set_property -name {xsim.simulate.runtime} -value {0} -objects [current_fileset -simset] +# Add test bench +add_files -fileset sim_1 -norecurse $project_directory/$testbench +set_property -name {xsim.simulate.runtime} -value {500 ns} -objects [current_fileset -simset] + + +# run simulation with some sample test vectors +proc run_sim {} { +#check if simulation is already open +set sim_value [current_sim] +if {$sim_value != "" } { +puts "Close existing Simulation" +close_sim +} +set_property -name {xsim.simulate.xsim.more_options} -value {-view ../../../../carry_lookahead_adder_tb_behav.wcfg} -objects [current_fileset -simset] +set_property -name {xsim.simulate.runtime} -value {0 ns} -objects [current_fileset -simset] +launch_simulation + + +# Set initial input values +add_force {/carry_lookahead_adder_tb/a} -radix hex {0 0ns} +add_force {/carry_lookahead_adder_tb/b} -radix hex {0 0ns} +add_force {/carry_lookahead_adder_tb/c_in} -radix unsigned {0 0ns} + +test_pattern + +} + +# run simulation with some sample test vectors +proc test_pattern {} { + +add_force {/carry_lookahead_adder_tb/c_in} -radix unsigned {0 0ns} + +add_force {/carry_lookahead_adder_tb/a} -radix hex {0 0ns} +add_force {/carry_lookahead_adder_tb/b} -radix hex {0 0ns} +run 50 ns + +add_force {/carry_lookahead_adder_tb/a} -radix hex {0x05 0ns} +add_force {/carry_lookahead_adder_tb/b} -radix hex {0x03 0ns} +run 50 ns + +add_force {/carry_lookahead_adder_tb/a} -radix hex {0x02 0ns} +add_force {/carry_lookahead_adder_tb/b} -radix hex {0x07 0ns} +run 50 ns + +# set carry in +add_force {/carry_lookahead_adder_tb/a} -radix hex {0x0a 0ns} +add_force {/carry_lookahead_adder_tb/b} -radix hex {0x04 0ns} +add_force {/carry_lookahead_adder_tb/c_in} -radix unsigned {1 0ns} +run 50 ns + +add_force {/carry_lookahead_adder_tb/a} -radix hex {0x80 0ns} +add_force {/carry_lookahead_adder_tb/b} -radix hex {0x38 0ns} +run 50 ns + +add_force {/carry_lookahead_adder_tb/a} -radix hex {0x8c 0ns} +add_force {/carry_lookahead_adder_tb/b} -radix hex {0x96 0ns} +run 50 ns + +add_force {/carry_lookahead_adder_tb/c_in} -radix unsigned {0 0ns} +add_force {/carry_lookahead_adder_tb/a} -radix hex {0xc8 0ns} +add_force {/carry_lookahead_adder_tb/b} -radix hex {0x96 0ns} +run 50 ns + +# reset input values +add_force {/carry_lookahead_adder_tb/a} -radix hex {0 0ns} +add_force {/carry_lookahead_adder_tb/b} -radix hex {0 0ns} +add_force {/carry_lookahead_adder_tb/c_in} -radix unsigned {0 0ns} + + +} + diff --git a/Projects/Logic_Design/CN_Design/Carry_Look_Ahead_Adder/src/carry_lookahead_adder_basys3_pins.xdc b/Projects/Logic_Design/CN_Design/Carry_Look_Ahead_Adder/src/carry_lookahead_adder_basys3_pins.xdc new file mode 100644 index 0000000..bc32f19 --- /dev/null +++ b/Projects/Logic_Design/CN_Design/Carry_Look_Ahead_Adder/src/carry_lookahead_adder_basys3_pins.xdc @@ -0,0 +1,59 @@ +#Pin constraints for XUPLIB 8 bit carry lookahead adder design for Basys 3 +## Switches +set_property PACKAGE_PIN V17 [get_ports {a0}] + set_property IOSTANDARD LVCMOS33 [get_ports {a0}] +set_property PACKAGE_PIN V16 [get_ports {a1}] + set_property IOSTANDARD LVCMOS33 [get_ports {a1}] +set_property PACKAGE_PIN W16 [get_ports {a2}] + set_property IOSTANDARD LVCMOS33 [get_ports {a2}] +set_property PACKAGE_PIN W17 [get_ports {a3}] + set_property IOSTANDARD LVCMOS33 [get_ports {a3}] +set_property PACKAGE_PIN W15 [get_ports {a4}] + set_property IOSTANDARD LVCMOS33 [get_ports {a4}] +set_property PACKAGE_PIN V15 [get_ports {a5}] + set_property IOSTANDARD LVCMOS33 [get_ports {a5}] +set_property PACKAGE_PIN W14 [get_ports {a6}] + set_property IOSTANDARD LVCMOS33 [get_ports {a6}] +set_property PACKAGE_PIN W13 [get_ports {a7}] + set_property IOSTANDARD LVCMOS33 [get_ports {a7}] +set_property PACKAGE_PIN V2 [get_ports {b0}] + set_property IOSTANDARD LVCMOS33 [get_ports {b0}] +set_property PACKAGE_PIN T3 [get_ports {b1}] + set_property IOSTANDARD LVCMOS33 [get_ports {b1}] +set_property PACKAGE_PIN T2 [get_ports {b2}] + set_property IOSTANDARD LVCMOS33 [get_ports {b2}] +set_property PACKAGE_PIN R3 [get_ports {b3}] + set_property IOSTANDARD LVCMOS33 [get_ports {b3}] +set_property PACKAGE_PIN W2 [get_ports {b4}] + set_property IOSTANDARD LVCMOS33 [get_ports {b4}] +set_property PACKAGE_PIN U1 [get_ports {b5}] + set_property IOSTANDARD LVCMOS33 [get_ports {b5}] +set_property PACKAGE_PIN T1 [get_ports {b6}] + set_property IOSTANDARD LVCMOS33 [get_ports {b6}] +set_property PACKAGE_PIN R2 [get_ports {b7}] + set_property IOSTANDARD LVCMOS33 [get_ports {b7}] + +# pushbutton C +set_property PACKAGE_PIN U18 [get_ports {c_in}] + set_property IOSTANDARD LVCMOS33 [get_ports {c_in}] + +# LEDs +set_property PACKAGE_PIN U16 [get_ports {s0}] + set_property IOSTANDARD LVCMOS33 [get_ports {s0}] +set_property PACKAGE_PIN E19 [get_ports {s1}] + set_property IOSTANDARD LVCMOS33 [get_ports {s1}] +set_property PACKAGE_PIN U19 [get_ports {s2}] + set_property IOSTANDARD LVCMOS33 [get_ports {s2}] +set_property PACKAGE_PIN V19 [get_ports {s3}] + set_property IOSTANDARD LVCMOS33 [get_ports {s3}] +set_property PACKAGE_PIN W18 [get_ports {s4}] + set_property IOSTANDARD LVCMOS33 [get_ports {s4}] +set_property PACKAGE_PIN U15 [get_ports {s5}] + set_property IOSTANDARD LVCMOS33 [get_ports {s5}] +set_property PACKAGE_PIN U14 [get_ports {s6}] + set_property IOSTANDARD LVCMOS33 [get_ports {s6}] +set_property PACKAGE_PIN V14 [get_ports {s7}] + set_property IOSTANDARD LVCMOS33 [get_ports {s7}] +# LED 15 +set_property PACKAGE_PIN L1 [get_ports {c_out}] + set_property IOSTANDARD LVCMOS33 [get_ports {c_out}] diff --git a/Projects/Logic_Design/CN_Design/Carry_Look_Ahead_Adder/src/carry_lookahead_adder_tb.v b/Projects/Logic_Design/CN_Design/Carry_Look_Ahead_Adder/src/carry_lookahead_adder_tb.v new file mode 100644 index 0000000..23b1d8d --- /dev/null +++ b/Projects/Logic_Design/CN_Design/Carry_Look_Ahead_Adder/src/carry_lookahead_adder_tb.v @@ -0,0 +1,66 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Module Name: carry_lookahead_adder_tb +// Description: Testbench for carry_lookahead_adder +////////////////////////////////////////////////////////////////////////////////// + + +module carry_lookahead_adder_tb( + ); + + reg [7:0] a, b; + reg c_in; + wire [7:0] s; + wire c_out; + + carry_lookahead_adder_wrapper DUT (.a0(a[0]), .a1(a[1]), .a2(a[2]), .a3(a[3]), .a4(a[4]), .a5(a[5]), .a6(a[6]), .a7(a[7]), + .b0(b[0]), .b1(b[1]), .b2(b[2]), .b3(b[3]), .b4(b[4]), .b5(b[5]), .b6(b[6]), .b7(b[7]), .c_in(c_in), + .s0(s[0]), .s1(s[1]), .s2(s[2]), .s3(s[3]), .s4(s[4]), .s5(s[5]), .s6(s[6]), .s7(s[7]), .c_out(c_out) + ); + + initial + begin + a = 8'h0; + b = 8'h0; + c_in = 1'b0; + #50; + a = 8'h0; + b = 8'h2; + c_in = 1'b0; + #50; + a = 8'h1; + b = 8'h9; + c_in = 1'b0; + #50; + a = 8'h4; + b = 8'h40; + c_in = 1'b0; + #50; + a = 8'h11; + b = 8'h11; + c_in = 1'b1; + #50; + a = 8'h23; + b = 8'h29; + c_in = 1'b0; + #50; + a = 8'h45; + b = 8'h42; + c_in = 1'b1; + #50; + a = 8'h89; + b = 8'h94; + c_in = 1'b0; + #50; + a = 8'hc1; + b = 8'hc8; + c_in = 1'b1; + #50; + a = 8'he1; + b = 8'he2; + c_in = 1'b0; + #50; + $stop; + end + +endmodule diff --git a/Projects/Logic_Design/CN_Design/Carry_Look_Ahead_Adder/src/carry_lookahead_adder_tb_behav.wcfg b/Projects/Logic_Design/CN_Design/Carry_Look_Ahead_Adder/src/carry_lookahead_adder_tb_behav.wcfg new file mode 100644 index 0000000..cbaa0d0 --- /dev/null +++ b/Projects/Logic_Design/CN_Design/Carry_Look_Ahead_Adder/src/carry_lookahead_adder_tb_behav.wcfg @@ -0,0 +1,37 @@ + + + + + + + + + + + + + + + a[7:0] + a[7:0] + HEXRADIX + + + b[7:0] + b[7:0] + HEXRADIX + + + c_in + c_in + + + s[7:0] + s[7:0] + HEXRADIX + + + c_out + c_out + + diff --git a/Projects/Logic_Design/CN_Design/Carry_Save_Adder/README.md b/Projects/Logic_Design/CN_Design/Carry_Save_Adder/README.md new file mode 100644 index 0000000..ef18b7d --- /dev/null +++ b/Projects/Logic_Design/CN_Design/Carry_Save_Adder/README.md @@ -0,0 +1,60 @@ +# Carry-Save Adder +This project creates an 8-bit Carry-Save adder using XUP_LIB components. You must download the XUP_LIB directory from the GitHub and then set the XUP_LIB path. You must also download the Basys3 board files directory from the GitHub and place it in the **\\2014.4\data\boards\board_parts\artix7** directory. + +The project source files include a Tcl script, Xilinx Design Constraint (xdc) file targeting Basys3 board, verilog testbench, and a wave configuration (wcfg) file. + +### Design Description: +This is a 4x 4-bit input adder, and the output is 6-bits. The adder is built from two 4-bit carry-save adders and an 8 bit ripple-carry adder. The ripple carry-adder is available as a separate project as part of this repository. +The 4-bit carry save adder is built from four full adders. +The full adder is built from two half adders. +The hierarchy of the design can be explored by opening or expanding the hierarchical blocks + +### Tools and requirements: +* Vivado 2014.4 +* XUP_LIB from GitHub +* Basys3 board files from GitHub + +### Procedure: +Execute the commands **in bold** in the tcl console + +1\. Start Vivado + +2\. At the tcl command line, set a variable *basys3_github* to the XUP_LIB path. Note the path uses "/" instead of "\". Substitute the path to where you have saved the XUP_LIB library: + +**set basys3_github {C:/xup/IPI_LIB/XUP_LIB}** + +3\. Change to the *src* directory of this project using the *cd* command: + +**cd \** + +4\. Execute the following command to run the script: + +**source ./carry_save_adder.tcl** + +5\. Once the project is created, the resulting block diagram will be displayed. View the block diagram, double click or expand blocks to navigate the hierarchy and analyze the design +6\. Execute the following command to run the behavioural simulation: + +**run_sim** + +7\. Analyze the results and notice the output transitioning after the input changes. When satisfied, close the simulator: + +**close_sim** + +8\. Generate the bitstream by clicking on the *Generate Bitstream* under the *Program and Debug* group + +9\. When the bitstream generation is completed, connect the board, power ON the board, and use the *Open Hardware Manager* option to connect to the board + +10\. *Program* the board and verify the functionality + +Input 1 : Dipswitches 0-3 + +Input 2 : Dipswitches 4-7 + +Input 3 : Dipswitches 8-11 + +Input 4 : Dipswitches 12-15 + +Result : Leds 0-5 + + + diff --git a/Projects/Logic_Design/CN_Design/Carry_Save_Adder/src/carry_save_adder.tcl b/Projects/Logic_Design/CN_Design/Carry_Save_Adder/src/carry_save_adder.tcl new file mode 100644 index 0000000..8e88a3e --- /dev/null +++ b/Projects/Logic_Design/CN_Design/Carry_Save_Adder/src/carry_save_adder.tcl @@ -0,0 +1,434 @@ +# Script to create an adder capable of adding four 4-bit numbers using 4-bit carry save adder using XUP_LIB components. +# Set XUP_LIB path below before running +# +# The addition of four 4-bit numbers is built from two 4-bit carry save adders and a ripple carry adder. +# The 4-bit carry save adder is built from four full adders. +# The full adder is built from two half adders. +# The hierarchy of the design can be explored by opening or expanding the hierarchical blocks +# +# Vivado 2014.4 +# Basys 3 board +# 28 May 2015 +# CMC +# Notes: Set the path below to the XUP_LIB, and run source carry_save__adder.tcl to create the design +# It is assumed the pin constraints xdc file (carry_save_adder_basys3_pins.xdc) is in the project directory. +# If the constraints file is located somewhere else, modify the constraints_directory path below +# +# After sourcing this script, run_sim can be executed to run a simulation +# +# Four 4-bit inputs (operands), x, y, z and w, are connected to the dip switches (w sw0-3, x sw 4-7, y sw 8-11, z sw 12-15) +# The 6-bit outputs are connected to LEDs 0-5 +# +# -------------------------------------------------------------- # +# SET 'basys3_github' PATH TO GITHUB LIBRARY BEFORE RUNNING +# -------------------------------------------------------------- # +set basys3_github {C:/xup/IPI_LIB/XUP_LIB} + +set project_directory . +set project_name carry_save_adder +set constraints_directory $project_directory +set constraints_file carry_save_adder_basys3_pins.xdc +set testbench carry_save_adder_tb.v +# Create project for Basys 3 +create_project -force $project_name ./$project_name -part xc7a35tcpg236-1 +set_property board_part digilentinc.com:basys3:part0:1.1 [current_project] +set_property target_language verilog [current_project] +set_property simulator_language Verilog [current_project] +set_property ip_repo_paths $basys3_github [current_project] +update_ip_catalog +create_bd_design "$project_name" + +# Steps: +# Build Half Adder +# Copy and add OR gate to make full adders +# Copy full adder 4 times to make 4-bit carry save adders +# copy 4-bit adder 2 times to make 8-bit adder + +# Build Half Adder +# create basic gates +create_bd_cell -type ip -vlnv xilinx.com:XUP:xup_xor2:1.0 xor_s +create_bd_cell -type ip -vlnv xilinx.com:XUP:xup_and2:1.0 and_c +# create HA hierarchical block +group_bd_cells half_adder [get_bd_cells xor_s] [get_bd_cells and_c] +# create pins on hierarchy block +create_bd_pin -dir I half_adder/a +create_bd_pin -dir I half_adder/b +create_bd_pin -dir O half_adder/s +create_bd_pin -dir O half_adder/c +# connect internal signals to pins +connect_bd_net [get_bd_pins half_adder/a] [get_bd_pins half_adder/and_c/a] +connect_bd_net [get_bd_pins half_adder/b] [get_bd_pins half_adder/and_c/b] +connect_bd_net [get_bd_pins half_adder/a] [get_bd_pins half_adder/xor_s/a] +connect_bd_net [get_bd_pins half_adder/b] [get_bd_pins half_adder/xor_s/b] +connect_bd_net [get_bd_pins half_adder/c] [get_bd_pins half_adder/and_c/y] +connect_bd_net [get_bd_pins half_adder/s] [get_bd_pins half_adder/xor_s/y] + +# Create Full adder +# copy half_adder +copy_bd_objs / [get_bd_cells {half_adder}] +# add OR gate +create_bd_cell -type ip -vlnv xilinx.com:XUP:xup_or2:1.0 or_carry_out +#create full_adder hierarchical block +group_bd_cells full_adder [get_bd_cells half_adder] [get_bd_cells half_adder1] [get_bd_cells or_carry_out] +# create full adder pins +create_bd_pin -dir I full_adder/a +create_bd_pin -dir I full_adder/b +create_bd_pin -dir I full_adder/c_in +create_bd_pin -dir O full_adder/s +create_bd_pin -dir O full_adder/c_out +# connect full adder nets +connect_bd_net [get_bd_pins full_adder/a] [get_bd_pins full_adder/half_adder/a] +connect_bd_net [get_bd_pins full_adder/b] [get_bd_pins full_adder/half_adder/b] +connect_bd_net [get_bd_pins full_adder/half_adder/s] [get_bd_pins full_adder/half_adder1/a] +connect_bd_net [get_bd_pins full_adder/c_in] [get_bd_pins full_adder/half_adder1/b] +connect_bd_net [get_bd_pins full_adder/half_adder/c] [get_bd_pins full_adder/or_carry_out/a] +connect_bd_net [get_bd_pins full_adder/half_adder1/c] [get_bd_pins full_adder/or_carry_out/b] +connect_bd_net [get_bd_pins full_adder/or_carry_out/y] [get_bd_pins full_adder/c_out] +connect_bd_net [get_bd_pins full_adder/half_adder1/s] [get_bd_pins full_adder/s] +# Create 4-bit carry save adder +# Copy and paste full adder +copy_bd_objs / [get_bd_cells {full_adder}] +copy_bd_objs / [get_bd_cells {full_adder}] +copy_bd_objs / [get_bd_cells {full_adder}] + +# create 4-bit carry save adder hierarchical block +group_bd_cells carry_save_adder_4_bit [get_bd_cells full_adder] [get_bd_cells full_adder1] [get_bd_cells full_adder2] [get_bd_cells full_adder3] +# create hierarchical block pins +create_bd_pin -dir I carry_save_adder_4_bit/x0 +create_bd_pin -dir I carry_save_adder_4_bit/x1 +create_bd_pin -dir I carry_save_adder_4_bit/x2 +create_bd_pin -dir I carry_save_adder_4_bit/x3 +create_bd_pin -dir I carry_save_adder_4_bit/y0 +create_bd_pin -dir I carry_save_adder_4_bit/y1 +create_bd_pin -dir I carry_save_adder_4_bit/y2 +create_bd_pin -dir I carry_save_adder_4_bit/y3 +create_bd_pin -dir I carry_save_adder_4_bit/z0 +create_bd_pin -dir I carry_save_adder_4_bit/z1 +create_bd_pin -dir I carry_save_adder_4_bit/z2 +create_bd_pin -dir I carry_save_adder_4_bit/z3 + +create_bd_pin -dir O carry_save_adder_4_bit/c0 +create_bd_pin -dir O carry_save_adder_4_bit/c1 +create_bd_pin -dir O carry_save_adder_4_bit/c2 +create_bd_pin -dir O carry_save_adder_4_bit/c3 +create_bd_pin -dir O carry_save_adder_4_bit/s0 +create_bd_pin -dir O carry_save_adder_4_bit/s1 +create_bd_pin -dir O carry_save_adder_4_bit/s2 +create_bd_pin -dir O carry_save_adder_4_bit/s3 +# connect pins +connect_bd_net [get_bd_pins carry_save_adder_4_bit/x0] [get_bd_pins carry_save_adder_4_bit/full_adder/a] +connect_bd_net [get_bd_pins carry_save_adder_4_bit/x1] [get_bd_pins carry_save_adder_4_bit/full_adder1/a] +connect_bd_net [get_bd_pins carry_save_adder_4_bit/x2] [get_bd_pins carry_save_adder_4_bit/full_adder2/a] +connect_bd_net [get_bd_pins carry_save_adder_4_bit/x3] [get_bd_pins carry_save_adder_4_bit/full_adder3/a] + +connect_bd_net [get_bd_pins carry_save_adder_4_bit/y0] [get_bd_pins carry_save_adder_4_bit/full_adder/b] +connect_bd_net [get_bd_pins carry_save_adder_4_bit/y1] [get_bd_pins carry_save_adder_4_bit/full_adder1/b] +connect_bd_net [get_bd_pins carry_save_adder_4_bit/y2] [get_bd_pins carry_save_adder_4_bit/full_adder2/b] +connect_bd_net [get_bd_pins carry_save_adder_4_bit/y3] [get_bd_pins carry_save_adder_4_bit/full_adder3/b] + +connect_bd_net [get_bd_pins carry_save_adder_4_bit/z0] [get_bd_pins carry_save_adder_4_bit/full_adder/c_in] +connect_bd_net [get_bd_pins carry_save_adder_4_bit/z1] [get_bd_pins carry_save_adder_4_bit/full_adder1/c_in] +connect_bd_net [get_bd_pins carry_save_adder_4_bit/z2] [get_bd_pins carry_save_adder_4_bit/full_adder2/c_in] +connect_bd_net [get_bd_pins carry_save_adder_4_bit/z3] [get_bd_pins carry_save_adder_4_bit/full_adder3/c_in] + +connect_bd_net [get_bd_pins carry_save_adder_4_bit/s0] [get_bd_pins carry_save_adder_4_bit/full_adder/s] +connect_bd_net [get_bd_pins carry_save_adder_4_bit/s1] [get_bd_pins carry_save_adder_4_bit/full_adder1/s] +connect_bd_net [get_bd_pins carry_save_adder_4_bit/s2] [get_bd_pins carry_save_adder_4_bit/full_adder2/s] +connect_bd_net [get_bd_pins carry_save_adder_4_bit/s3] [get_bd_pins carry_save_adder_4_bit/full_adder3/s] + +connect_bd_net [get_bd_pins carry_save_adder_4_bit/c0] [get_bd_pins carry_save_adder_4_bit/full_adder/c_out] +connect_bd_net [get_bd_pins carry_save_adder_4_bit/c1] [get_bd_pins carry_save_adder_4_bit/full_adder1/c_out] +connect_bd_net [get_bd_pins carry_save_adder_4_bit/c2] [get_bd_pins carry_save_adder_4_bit/full_adder2/c_out] +connect_bd_net [get_bd_pins carry_save_adder_4_bit/c3] [get_bd_pins carry_save_adder_4_bit/full_adder3/c_out] + +# Create 8-bit carry save adder +copy_bd_objs / [get_bd_cells {carry_save_adder_4_bit}] + + +#Create top level i/o ports and connect to 4 bit adders +# w +create_bd_port -dir I w0 +connect_bd_net [get_bd_pins /carry_save_adder_4_bit1/x0] [get_bd_ports w0] +create_bd_port -dir I w1 +connect_bd_net [get_bd_pins /carry_save_adder_4_bit1/x1] [get_bd_ports w1] +create_bd_port -dir I w2 +connect_bd_net [get_bd_pins /carry_save_adder_4_bit1/x2] [get_bd_ports w2] +create_bd_port -dir I w3 +connect_bd_net [get_bd_pins /carry_save_adder_4_bit1/x3] [get_bd_ports w3] +# x +create_bd_port -dir I x0 +connect_bd_net [get_bd_pins /carry_save_adder_4_bit/x0] [get_bd_ports x0] +create_bd_port -dir I x1 +connect_bd_net [get_bd_pins /carry_save_adder_4_bit/x1] [get_bd_ports x1] +create_bd_port -dir I x2 +connect_bd_net [get_bd_pins /carry_save_adder_4_bit/x2] [get_bd_ports x2] +create_bd_port -dir I x3 +connect_bd_net [get_bd_pins /carry_save_adder_4_bit/x3] [get_bd_ports x3] +# y +create_bd_port -dir I y0 +connect_bd_net [get_bd_pins /carry_save_adder_4_bit/y0] [get_bd_ports y0] +create_bd_port -dir I y1 +connect_bd_net [get_bd_pins /carry_save_adder_4_bit/y1] [get_bd_ports y1] +create_bd_port -dir I y2 +connect_bd_net [get_bd_pins /carry_save_adder_4_bit/y2] [get_bd_ports y2] +create_bd_port -dir I y3 +connect_bd_net [get_bd_pins /carry_save_adder_4_bit/y3] [get_bd_ports y3] +#z +create_bd_port -dir I z0 +connect_bd_net [get_bd_pins /carry_save_adder_4_bit/z0] [get_bd_ports z0] +create_bd_port -dir I z1 +connect_bd_net [get_bd_pins /carry_save_adder_4_bit/z1] [get_bd_ports z1] +create_bd_port -dir I z2 +connect_bd_net [get_bd_pins /carry_save_adder_4_bit/z2] [get_bd_ports z2] +create_bd_port -dir I z3 +connect_bd_net [get_bd_pins /carry_save_adder_4_bit/z3] [get_bd_ports z3] + + +connect_bd_net [get_bd_pins carry_save_adder_4_bit/c0] [get_bd_pins carry_save_adder_4_bit1/z1] -boundary_type upper +connect_bd_net [get_bd_pins carry_save_adder_4_bit/c1] [get_bd_pins carry_save_adder_4_bit1/z2] -boundary_type upper +connect_bd_net [get_bd_pins carry_save_adder_4_bit/c2] [get_bd_pins carry_save_adder_4_bit1/z3] -boundary_type upper +connect_bd_net [get_bd_pins carry_save_adder_4_bit/s0] [get_bd_pins carry_save_adder_4_bit1/y0] -boundary_type upper +connect_bd_net [get_bd_pins carry_save_adder_4_bit/s1] [get_bd_pins carry_save_adder_4_bit1/y1] -boundary_type upper +connect_bd_net [get_bd_pins carry_save_adder_4_bit/s2] [get_bd_pins carry_save_adder_4_bit1/y2] -boundary_type upper +connect_bd_net [get_bd_pins carry_save_adder_4_bit/s3] [get_bd_pins carry_save_adder_4_bit1/y3] -boundary_type upper + +# ###################################################################################### +# # Ripple carry adder for last stage +# # The ripple carry adder is also available as a standalone project from the XUP github +# ###################################################################################### + +# Steps: +# Build Half Adder +# Copy and add OR gate to make full adders +# Copy full adder 4 times to make 4-bit carry ripple adders +# copy 4-bit adder 2 times to make 8-bit adder + +# Build Half Adder +# create basic gates +create_bd_cell -type ip -vlnv xilinx.com:XUP:xup_xor2:1.0 xor_s +create_bd_cell -type ip -vlnv xilinx.com:XUP:xup_and2:1.0 and_c +# create HA hierarchical block +group_bd_cells half_adder [get_bd_cells xor_s] [get_bd_cells and_c] +# create pins on hierarchy block +create_bd_pin -dir I half_adder/a +create_bd_pin -dir I half_adder/b +create_bd_pin -dir O half_adder/s +create_bd_pin -dir O half_adder/c +# connect internal signals to pins +connect_bd_net [get_bd_pins half_adder/a] [get_bd_pins half_adder/and_c/a] +connect_bd_net [get_bd_pins half_adder/b] [get_bd_pins half_adder/and_c/b] +connect_bd_net [get_bd_pins half_adder/a] [get_bd_pins half_adder/xor_s/a] +connect_bd_net [get_bd_pins half_adder/b] [get_bd_pins half_adder/xor_s/b] +connect_bd_net [get_bd_pins half_adder/c] [get_bd_pins half_adder/and_c/y] +connect_bd_net [get_bd_pins half_adder/s] [get_bd_pins half_adder/xor_s/y] + +# Create Full adder +# copy half_adder +copy_bd_objs / [get_bd_cells {half_adder}] +# add OR gate +create_bd_cell -type ip -vlnv xilinx.com:XUP:xup_or2:1.0 or_carry_out +#create full_adder hierarchical block +group_bd_cells full_adder [get_bd_cells half_adder] [get_bd_cells half_adder1] [get_bd_cells or_carry_out] +# create full adder pins +create_bd_pin -dir I full_adder/a +create_bd_pin -dir I full_adder/b +create_bd_pin -dir I full_adder/c_in +create_bd_pin -dir O full_adder/s +create_bd_pin -dir O full_adder/c_out +# connect full adder nets +connect_bd_net [get_bd_pins full_adder/a] [get_bd_pins full_adder/half_adder/a] +connect_bd_net [get_bd_pins full_adder/b] [get_bd_pins full_adder/half_adder/b] +connect_bd_net [get_bd_pins full_adder/half_adder/s] [get_bd_pins full_adder/half_adder1/a] +connect_bd_net [get_bd_pins full_adder/c_in] [get_bd_pins full_adder/half_adder1/b] +connect_bd_net [get_bd_pins full_adder/half_adder/c] [get_bd_pins full_adder/or_carry_out/a] +connect_bd_net [get_bd_pins full_adder/half_adder1/c] [get_bd_pins full_adder/or_carry_out/b] +connect_bd_net [get_bd_pins full_adder/or_carry_out/y] [get_bd_pins full_adder/c_out] +connect_bd_net [get_bd_pins full_adder/half_adder1/s] [get_bd_pins full_adder/s] +# Create 4-bit carry ripple adder +# Copy and paste full adder +copy_bd_objs / [get_bd_cells {full_adder}] +copy_bd_objs / [get_bd_cells {full_adder}] +copy_bd_objs / [get_bd_cells {full_adder}] +# Connect carrys +connect_bd_net [get_bd_pins full_adder/c_out] [get_bd_pins full_adder1/c_in] -boundary_type upper +connect_bd_net [get_bd_pins full_adder1/c_out] [get_bd_pins full_adder2/c_in] -boundary_type upper +connect_bd_net [get_bd_pins full_adder2/c_out] [get_bd_pins full_adder3/c_in] -boundary_type upper +# create 4-bit carry ripple adder hierarchical block +group_bd_cells ripple_carry_adder_4_bit [get_bd_cells full_adder] [get_bd_cells full_adder1] [get_bd_cells full_adder2] [get_bd_cells full_adder3] +# create hierarchical block pins +create_bd_pin -dir I ripple_carry_adder_4_bit/a0 +create_bd_pin -dir I ripple_carry_adder_4_bit/a1 +create_bd_pin -dir I ripple_carry_adder_4_bit/a2 +create_bd_pin -dir I ripple_carry_adder_4_bit/a3 +create_bd_pin -dir I ripple_carry_adder_4_bit/b0 +create_bd_pin -dir I ripple_carry_adder_4_bit/b1 +create_bd_pin -dir I ripple_carry_adder_4_bit/b2 +create_bd_pin -dir I ripple_carry_adder_4_bit/b3 + +create_bd_pin -dir I ripple_carry_adder_4_bit/c_in + +create_bd_pin -dir O ripple_carry_adder_4_bit/s0 +create_bd_pin -dir O ripple_carry_adder_4_bit/s1 +create_bd_pin -dir O ripple_carry_adder_4_bit/s2 +create_bd_pin -dir O ripple_carry_adder_4_bit/s3 + +create_bd_pin -dir O ripple_carry_adder_4_bit/c_out +# connect pins +connect_bd_net [get_bd_pins ripple_carry_adder_4_bit/a0] [get_bd_pins ripple_carry_adder_4_bit/full_adder/a] +connect_bd_net [get_bd_pins ripple_carry_adder_4_bit/a1] [get_bd_pins ripple_carry_adder_4_bit/full_adder1/a] +connect_bd_net [get_bd_pins ripple_carry_adder_4_bit/a2] [get_bd_pins ripple_carry_adder_4_bit/full_adder2/a] +connect_bd_net [get_bd_pins ripple_carry_adder_4_bit/a3] [get_bd_pins ripple_carry_adder_4_bit/full_adder3/a] + +connect_bd_net [get_bd_pins ripple_carry_adder_4_bit/b0] [get_bd_pins ripple_carry_adder_4_bit/full_adder/b] +connect_bd_net [get_bd_pins ripple_carry_adder_4_bit/b1] [get_bd_pins ripple_carry_adder_4_bit/full_adder1/b] +connect_bd_net [get_bd_pins ripple_carry_adder_4_bit/b2] [get_bd_pins ripple_carry_adder_4_bit/full_adder2/b] +connect_bd_net [get_bd_pins ripple_carry_adder_4_bit/b3] [get_bd_pins ripple_carry_adder_4_bit/full_adder3/b] + +connect_bd_net [get_bd_pins ripple_carry_adder_4_bit/c_in] [get_bd_pins ripple_carry_adder_4_bit/full_adder/c_in] + +connect_bd_net [get_bd_pins ripple_carry_adder_4_bit/s0] [get_bd_pins ripple_carry_adder_4_bit/full_adder/s] +connect_bd_net [get_bd_pins ripple_carry_adder_4_bit/s1] [get_bd_pins ripple_carry_adder_4_bit/full_adder1/s] +connect_bd_net [get_bd_pins ripple_carry_adder_4_bit/s2] [get_bd_pins ripple_carry_adder_4_bit/full_adder2/s] +connect_bd_net [get_bd_pins ripple_carry_adder_4_bit/s3] [get_bd_pins ripple_carry_adder_4_bit/full_adder3/s] + +connect_bd_net [get_bd_pins ripple_carry_adder_4_bit/c_out] [get_bd_pins ripple_carry_adder_4_bit/full_adder3/c_out] + +# Create 8-bit carry ripple adder +copy_bd_objs / [get_bd_cells {ripple_carry_adder_4_bit}] +connect_bd_net [get_bd_pins ripple_carry_adder_4_bit/c_out] [get_bd_pins ripple_carry_adder_4_bit1/c_in] + +group_bd_cells ripple_carry_adder_8_bit [get_bd_cells ripple_carry_adder_4_bit1] [get_bd_cells ripple_carry_adder_4_bit] + +#Create top level i/o ports and connect to 4 bit adders +# a +create_bd_pin -dir I /ripple_carry_adder_8_bit/a0 +connect_bd_net [get_bd_pins /ripple_carry_adder_8_bit/ripple_carry_adder_4_bit/a0] [get_bd_pins /ripple_carry_adder_8_bit/a0] +create_bd_pin -dir I /ripple_carry_adder_8_bit/a1 +connect_bd_net [get_bd_pins /ripple_carry_adder_8_bit/ripple_carry_adder_4_bit/a1] [get_bd_pins /ripple_carry_adder_8_bit/a1] +create_bd_pin -dir I /ripple_carry_adder_8_bit/a2 +connect_bd_net [get_bd_pins /ripple_carry_adder_8_bit/ripple_carry_adder_4_bit/a2] [get_bd_pins /ripple_carry_adder_8_bit/a2] +create_bd_pin -dir I /ripple_carry_adder_8_bit/a3 +connect_bd_net [get_bd_pins /ripple_carry_adder_8_bit/ripple_carry_adder_4_bit/a3] [get_bd_pins /ripple_carry_adder_8_bit/a3] +create_bd_pin -dir I /ripple_carry_adder_8_bit/a4 +connect_bd_net [get_bd_pins /ripple_carry_adder_8_bit/ripple_carry_adder_4_bit1/a0] [get_bd_pins /ripple_carry_adder_8_bit/a4] +create_bd_pin -dir I /ripple_carry_adder_8_bit/a5 +connect_bd_net [get_bd_pins /ripple_carry_adder_8_bit/ripple_carry_adder_4_bit1/a1] [get_bd_pins /ripple_carry_adder_8_bit/a5] +create_bd_pin -dir I /ripple_carry_adder_8_bit/a6 +connect_bd_net [get_bd_pins /ripple_carry_adder_8_bit/ripple_carry_adder_4_bit1/a2] [get_bd_pins /ripple_carry_adder_8_bit/a6] +create_bd_pin -dir I /ripple_carry_adder_8_bit/a7 +connect_bd_net [get_bd_pins /ripple_carry_adder_8_bit/ripple_carry_adder_4_bit1/a3] [get_bd_pins /ripple_carry_adder_8_bit/a7] +# b +create_bd_pin -dir I /ripple_carry_adder_8_bit/b0 +connect_bd_net [get_bd_pins /ripple_carry_adder_8_bit/ripple_carry_adder_4_bit/b0] [get_bd_pins /ripple_carry_adder_8_bit/b0] +create_bd_pin -dir I /ripple_carry_adder_8_bit/b1 +connect_bd_net [get_bd_pins /ripple_carry_adder_8_bit/ripple_carry_adder_4_bit/b1] [get_bd_pins /ripple_carry_adder_8_bit/b1] +create_bd_pin -dir I /ripple_carry_adder_8_bit/b2 +connect_bd_net [get_bd_pins /ripple_carry_adder_8_bit/ripple_carry_adder_4_bit/b2] [get_bd_pins /ripple_carry_adder_8_bit/b2] +create_bd_pin -dir I /ripple_carry_adder_8_bit/b3 +connect_bd_net [get_bd_pins /ripple_carry_adder_8_bit/ripple_carry_adder_4_bit/b3] [get_bd_pins /ripple_carry_adder_8_bit/b3] +create_bd_pin -dir I /ripple_carry_adder_8_bit/b4 +connect_bd_net [get_bd_pins /ripple_carry_adder_8_bit/ripple_carry_adder_4_bit1/b0] [get_bd_pins /ripple_carry_adder_8_bit/b4] +create_bd_pin -dir I /ripple_carry_adder_8_bit/b5 +connect_bd_net [get_bd_pins /ripple_carry_adder_8_bit/ripple_carry_adder_4_bit1/b1] [get_bd_pins /ripple_carry_adder_8_bit/b5] +create_bd_pin -dir I /ripple_carry_adder_8_bit/b6 +connect_bd_net [get_bd_pins /ripple_carry_adder_8_bit/ripple_carry_adder_4_bit1/b2] [get_bd_pins /ripple_carry_adder_8_bit/b6] +create_bd_pin -dir I /ripple_carry_adder_8_bit/b7 +connect_bd_net [get_bd_pins /ripple_carry_adder_8_bit/ripple_carry_adder_4_bit1/b3] [get_bd_pins /ripple_carry_adder_8_bit/b7] + + +# outputs +create_bd_pin -dir O /ripple_carry_adder_8_bit/o0 +connect_bd_net [get_bd_pins /ripple_carry_adder_8_bit/ripple_carry_adder_4_bit/s0] [get_bd_pins /ripple_carry_adder_8_bit/o0] +create_bd_pin -dir O /ripple_carry_adder_8_bit/o1 +connect_bd_net [get_bd_pins /ripple_carry_adder_8_bit/ripple_carry_adder_4_bit/s1] [get_bd_pins /ripple_carry_adder_8_bit/o1] +create_bd_pin -dir O /ripple_carry_adder_8_bit/o2 +connect_bd_net [get_bd_pins /ripple_carry_adder_8_bit/ripple_carry_adder_4_bit/s2] [get_bd_pins /ripple_carry_adder_8_bit/o2] +create_bd_pin -dir O /ripple_carry_adder_8_bit/o3 +connect_bd_net [get_bd_pins /ripple_carry_adder_8_bit/ripple_carry_adder_4_bit/s3] [get_bd_pins /ripple_carry_adder_8_bit/o3] +create_bd_pin -dir O /ripple_carry_adder_8_bit/o4 +connect_bd_net [get_bd_pins /ripple_carry_adder_8_bit/ripple_carry_adder_4_bit1/s0] [get_bd_pins /ripple_carry_adder_8_bit/o4] +create_bd_pin -dir O /ripple_carry_adder_8_bit/o5 +connect_bd_net [get_bd_pins /ripple_carry_adder_8_bit/ripple_carry_adder_4_bit1/s1] [get_bd_pins /ripple_carry_adder_8_bit/o5] +create_bd_pin -dir O /ripple_carry_adder_8_bit/o6 +connect_bd_net [get_bd_pins /ripple_carry_adder_8_bit/ripple_carry_adder_4_bit1/s2] [get_bd_pins /ripple_carry_adder_8_bit/o6] +create_bd_pin -dir O /ripple_carry_adder_8_bit/o7 +connect_bd_net [get_bd_pins /ripple_carry_adder_8_bit/ripple_carry_adder_4_bit1/s3] [get_bd_pins /ripple_carry_adder_8_bit/o7] +# carry out +create_bd_pin -dir O /ripple_carry_adder_8_bit/c_out +connect_bd_net [get_bd_pins /ripple_carry_adder_8_bit/ripple_carry_adder_4_bit1/c_out] [get_bd_pins /ripple_carry_adder_8_bit/c_out] +# ########################################################################## +# # END Ripple Carry Adder +# ########################################################################## + +connect_bd_net [get_bd_pins carry_save_adder_4_bit1/s1] [get_bd_pins ripple_carry_adder_8_bit/b0] -boundary_type upper +connect_bd_net [get_bd_pins carry_save_adder_4_bit1/s2] [get_bd_pins ripple_carry_adder_8_bit/b1] -boundary_type upper +connect_bd_net [get_bd_pins carry_save_adder_4_bit1/s3] [get_bd_pins ripple_carry_adder_8_bit/b2] -boundary_type upper +connect_bd_net [get_bd_pins carry_save_adder_4_bit1/c0] [get_bd_pins ripple_carry_adder_8_bit/a0] -boundary_type upper +connect_bd_net [get_bd_pins carry_save_adder_4_bit1/c1] [get_bd_pins ripple_carry_adder_8_bit/a1] -boundary_type upper +connect_bd_net [get_bd_pins carry_save_adder_4_bit1/c2] [get_bd_pins ripple_carry_adder_8_bit/a2] -boundary_type upper +connect_bd_net [get_bd_pins carry_save_adder_4_bit/c3] [get_bd_pins ripple_carry_adder_8_bit/b3] -boundary_type upper +connect_bd_net [get_bd_pins carry_save_adder_4_bit1/c3] [get_bd_pins ripple_carry_adder_8_bit/a3] -boundary_type upper + +create_bd_port -dir O s0 +connect_bd_net [get_bd_pins /carry_save_adder_4_bit1/s0] [get_bd_ports s0] +create_bd_port -dir O s1 +connect_bd_net [get_bd_pins /ripple_carry_adder_8_bit/o0] [get_bd_ports s1] +create_bd_port -dir O s2 +connect_bd_net [get_bd_pins /ripple_carry_adder_8_bit/o1] [get_bd_ports s2] +create_bd_port -dir O s3 +connect_bd_net [get_bd_pins /ripple_carry_adder_8_bit/o2] [get_bd_ports s3] +create_bd_port -dir O s4 +connect_bd_net [get_bd_pins /ripple_carry_adder_8_bit/o3] [get_bd_ports s4] +create_bd_port -dir O s5 +connect_bd_net [get_bd_pins /ripple_carry_adder_8_bit/o4] [get_bd_ports s5] + +regenerate_bd_layout +save_bd_design + +# Ground all unused signals. +create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 gnd +set_property -dict [list CONFIG.CONST_VAL {0}] [get_bd_cells gnd] +connect_bd_net [get_bd_pins gnd/dout] [get_bd_pins ripple_carry_adder_8_bit/b4] +connect_bd_net -net [get_bd_nets gnd_dout] [get_bd_pins ripple_carry_adder_8_bit/b5] +connect_bd_net -net [get_bd_nets gnd_dout] [get_bd_pins ripple_carry_adder_8_bit/b6] +connect_bd_net -net [get_bd_nets gnd_dout] [get_bd_pins ripple_carry_adder_8_bit/b7] +connect_bd_net -net [get_bd_nets gnd_dout] [get_bd_pins ripple_carry_adder_8_bit/a4] +connect_bd_net -net [get_bd_nets gnd_dout] [get_bd_pins ripple_carry_adder_8_bit/a5] +connect_bd_net -net [get_bd_nets gnd_dout] [get_bd_pins ripple_carry_adder_8_bit/a6] +connect_bd_net -net [get_bd_nets gnd_dout] [get_bd_pins ripple_carry_adder_8_bit/a7] +connect_bd_net -net [get_bd_nets gnd_dout] [get_bd_pins carry_save_adder_4_bit1/z0] + +create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 ripple_carry_adder_8_bit/gnd +set_property -dict [list CONFIG.CONST_VAL {0}] [get_bd_cells ripple_carry_adder_8_bit/gnd] +connect_bd_net [get_bd_pins ripple_carry_adder_8_bit/gnd/dout] [get_bd_pins ripple_carry_adder_8_bit/ripple_carry_adder_4_bit/c_in] + + +# Create top HDL wrapper +make_wrapper -files [get_files $project_directory/$project_name/$project_name.srcs/sources_1/bd/$project_name/$project_name.bd] -top +add_files -norecurse $project_directory/$project_name/$project_name.srcs/sources_1/bd/$project_name/hdl/$project_name\_wrapper.v +# Add pin constraints +add_files -fileset constrs_1 -norecurse $constraints_directory/$constraints_file +set_property -name {xsim.simulate.runtime} -value {0} -objects [current_fileset -simset] +# Add test bench +add_files -fileset sim_1 -norecurse $project_directory/$testbench +set_property -name {xsim.simulate.runtime} -value {500 ns} -objects [current_fileset -simset] + + +# run simulation with some sample test vectors +proc run_sim {} { +#check if simulation is already open +set sim_value [current_sim] +if {$sim_value != "" } { +puts "Close existing Simulation" +close_sim -force +} +set_property -name {xsim.simulate.xsim.more_options} -value {-view ../../../../carry_save_adder_tb_behav.wcfg} -objects [current_fileset -simset] +set_property -name {xsim.simulate.runtime} -value {0 ns} -objects [current_fileset -simset] +launch_simulation +puts "Running Simulation for 3276800 ns" +puts "The testbench will increment each input from 0-16 covering all input possibilities" +run 3276800 ns +puts "Simulation complete" + + +} diff --git a/Projects/Logic_Design/CN_Design/Carry_Save_Adder/src/carry_save_adder_basys3_pins.xdc b/Projects/Logic_Design/CN_Design/Carry_Save_Adder/src/carry_save_adder_basys3_pins.xdc new file mode 100644 index 0000000..c1a2045 --- /dev/null +++ b/Projects/Logic_Design/CN_Design/Carry_Save_Adder/src/carry_save_adder_basys3_pins.xdc @@ -0,0 +1,51 @@ +#Pin constraints for XUPLIB 8 bit carry save adder design for Basys 3 +## Switches +set_property PACKAGE_PIN V17 [get_ports {w0}] + set_property IOSTANDARD LVCMOS33 [get_ports {w0}] +set_property PACKAGE_PIN V16 [get_ports {w1}] + set_property IOSTANDARD LVCMOS33 [get_ports {w1}] +set_property PACKAGE_PIN W16 [get_ports {w2}] + set_property IOSTANDARD LVCMOS33 [get_ports {w2}] +set_property PACKAGE_PIN W17 [get_ports {w3}] + set_property IOSTANDARD LVCMOS33 [get_ports {w3}] + +set_property PACKAGE_PIN W15 [get_ports {x0}] + set_property IOSTANDARD LVCMOS33 [get_ports {x0}] +set_property PACKAGE_PIN V15 [get_ports {x1}] + set_property IOSTANDARD LVCMOS33 [get_ports {x1}] +set_property PACKAGE_PIN W14 [get_ports {x2}] + set_property IOSTANDARD LVCMOS33 [get_ports {x2}] +set_property PACKAGE_PIN W13 [get_ports {x3}] + set_property IOSTANDARD LVCMOS33 [get_ports {x3}] + +set_property PACKAGE_PIN V2 [get_ports {y0}] + set_property IOSTANDARD LVCMOS33 [get_ports {y0}] +set_property PACKAGE_PIN T3 [get_ports {y1}] + set_property IOSTANDARD LVCMOS33 [get_ports {y1}] +set_property PACKAGE_PIN T2 [get_ports {y2}] + set_property IOSTANDARD LVCMOS33 [get_ports {y2}] +set_property PACKAGE_PIN R3 [get_ports {y3}] + set_property IOSTANDARD LVCMOS33 [get_ports {y3}] + +set_property PACKAGE_PIN W2 [get_ports {z0}] + set_property IOSTANDARD LVCMOS33 [get_ports {z0}] +set_property PACKAGE_PIN U1 [get_ports {z1}] + set_property IOSTANDARD LVCMOS33 [get_ports {z1}] +set_property PACKAGE_PIN T1 [get_ports {z2}] + set_property IOSTANDARD LVCMOS33 [get_ports {z2}] +set_property PACKAGE_PIN R2 [get_ports {z3}] + set_property IOSTANDARD LVCMOS33 [get_ports {z3}] + +# LEDs +set_property PACKAGE_PIN U16 [get_ports {s0}] + set_property IOSTANDARD LVCMOS33 [get_ports {s0}] +set_property PACKAGE_PIN E19 [get_ports {s1}] + set_property IOSTANDARD LVCMOS33 [get_ports {s1}] +set_property PACKAGE_PIN U19 [get_ports {s2}] + set_property IOSTANDARD LVCMOS33 [get_ports {s2}] +set_property PACKAGE_PIN V19 [get_ports {s3}] + set_property IOSTANDARD LVCMOS33 [get_ports {s3}] +set_property PACKAGE_PIN W18 [get_ports {s4}] + set_property IOSTANDARD LVCMOS33 [get_ports {s4}] +set_property PACKAGE_PIN U15 [get_ports {s5}] + set_property IOSTANDARD LVCMOS33 [get_ports {s5}] diff --git a/Projects/Logic_Design/CN_Design/Carry_Save_Adder/src/carry_save_adder_tb.v b/Projects/Logic_Design/CN_Design/Carry_Save_Adder/src/carry_save_adder_tb.v new file mode 100644 index 0000000..7ce2a3f --- /dev/null +++ b/Projects/Logic_Design/CN_Design/Carry_Save_Adder/src/carry_save_adder_tb.v @@ -0,0 +1,58 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Module Name: carry_save_adder_tb +// Description: Testbench for carry_save_adder +////////////////////////////////////////////////////////////////////////////////// + + +module carry_save_adder_tb( + ); + + reg [3:0] w, x, y, z; + wire [5:0] s; + + integer i,j,k,l, error; + + carry_save_adder_wrapper DUT (.w0(w[0]), .w1(w[1]), .w2(w[2]), .w3(w[3]), .x0(x[0]), .x1(x[1]), .x2(x[2]), .x3(x[3]), + .y0(y[0]), .y1(y[1]), .y2(y[2]), .y3(y[3]), .z0(z[0]), .z1(z[1]), .z2(z[2]), .z3(z[3]), + .s0(s[0]), .s1(s[1]), .s2(s[2]), .s3(s[3]), .s4(s[4]), .s5(s[5]) + ); + + initial + begin + w = 4'h0; + x = 4'h0; + y = 4'h0; + z = 4'h0; + error =0; + for (i=0; i<16; i=i+1) begin + z = i; + for (j=0; j<16; j=j+1) begin + y = j; + for (k=0; k<16; k=k+1) begin + x = k; + for (l=0; l<16; l=l+1) begin + w = l; + #50; + if(s != i+j+k+l) + error = error +1; + end + end + end + end + if(error != 0) + begin + $display("***************************"); + $display("Test Failed; %d mismatches", error); + $display("***************************"); + end + else + begin + $display("*******************************************"); + $display("Test Passed! Outputs match expected results"); + $display("*******************************************"); + end + $stop; + end + +endmodule diff --git a/Projects/Logic_Design/CN_Design/Carry_Save_Adder/src/carry_save_adder_tb_behav.wcfg b/Projects/Logic_Design/CN_Design/Carry_Save_Adder/src/carry_save_adder_tb_behav.wcfg new file mode 100644 index 0000000..c2e6a48 --- /dev/null +++ b/Projects/Logic_Design/CN_Design/Carry_Save_Adder/src/carry_save_adder_tb_behav.wcfg @@ -0,0 +1,47 @@ + + + + + + + + + + + + + + + inputs (4-bit) + label + + + w[3:0] + w[3:0] + UNSIGNEDDECRADIX + + + x[3:0] + x[3:0] + UNSIGNEDDECRADIX + + + y[3:0] + y[3:0] + UNSIGNEDDECRADIX + + + z[3:0] + z[3:0] + UNSIGNEDDECRADIX + + + output (6-bit) + label + + + s[5:0] + s[5:0] + UNSIGNEDDECRADIX + + diff --git a/Projects/Logic_Design/CN_Design/Carry_Save_Adder_7Seg/README.md b/Projects/Logic_Design/CN_Design/Carry_Save_Adder_7Seg/README.md new file mode 100644 index 0000000..e8917a8 --- /dev/null +++ b/Projects/Logic_Design/CN_Design/Carry_Save_Adder_7Seg/README.md @@ -0,0 +1,43 @@ +### Carry Save Adder +This project is about creating an adder which adds four 4-bit operands using carry save adders and ripple carry adder. The inputs are from 16 switches grouped into four 4-bit input. The outputs are displayed in binary format on the six LEDs and in BCD format on the 7-segment display module. The design is created using XUP_LIB components. You must download the XUP_LIB directory from the GitHub and then set the XUP_LIB path. You must also download Basys3 board files directory from the GitHub and place it in the **\\2014.4\data\boards\board_parts\artix7** directory. + +The project source files provide Tcl script, and a Xilinx Design Constraint (xdc) file targeting Basys3 board. + +### Design Description: +Ripple carry adders are inherently slow. To speed up the addition operation of multiple operands carry save adder topology may be used. The design is built using basic gates, concat, bin2bcd, and 7-segment display IPs available in XUP_LIB. It also uses clocking wizard to provide 100 MHz clock to the 7-segment display IP to refresh the output at approximately 250 Hz. + +### Tools and other requirements: +* Vivado 2014.4 +* XUP_LIB from GitHub +* Basys3 board files from GitHub + +### Procedure: +Execute the commands **in bold** in the tcl console + +1\. Start Vivado in a GUI mode + +2\. Set the path *basys3_github* to the XUP_LIB using command like in the Vivado Tcl Console. Note the path uses "/" instead of "\". Substiture the path where you have stored the XUP_LIB library. + +**set basys3_github {C:/xup/IPI_LIB/XUP_LIB}** + +3\. Change to the *src* directory of this project directory using the cd command, keeping in mind to use "/" instead of "\" in the directory + +**cd \** + +4\. Next, execute the following command to run the script + +**source ./carry_save_adder_7seg.tcl** + +5\. Once the project is created, the resulting block diagram will be displayed. View through the block diagram, its hierarchy and analyze the design + +6\. Generate the bitstream by clicking on the Generate Bitstream under the Program and Debug group. A warning message box will appear. Click OK to ignore it + +7\. When the bitstream generation is completed, connect the board, power ON the board, and use the Open Hardware Manager option to connect to the board + +8\. Program the board and verify the functionality + +Input : Center button to reset the 7-segment display +Input : 16 switches to input four 4-bit operands +Output : 4 7-segments module displaying BCD equivalent result on the right-most two 7-segments +Output : Six LEDs displaying binary equivalent result + diff --git a/Projects/Logic_Design/CN_Design/Carry_Save_Adder_7Seg/src/carry_save_adder_7seg.tcl b/Projects/Logic_Design/CN_Design/Carry_Save_Adder_7Seg/src/carry_save_adder_7seg.tcl new file mode 100644 index 0000000..ff300a3 --- /dev/null +++ b/Projects/Logic_Design/CN_Design/Carry_Save_Adder_7Seg/src/carry_save_adder_7seg.tcl @@ -0,0 +1,476 @@ +# Script to create an adder capable of adding four 4-bit numbers +# using 4-bit carry save adder using XUP_LIB components. +# Set XUP_LIB path below before running +# +# The addition of four 4-bit numbers is built from two 4-bit carry save adders and a ripple carry adder. +# The 4-bit carry save adder is built from four full adders. +# The full adder is built from two half adders. +# The hierarchy of the design can be explored by opening or expanding the hierarchical blocks +# +# Vivado 2014.4 +# Basys 3 board +# 28 May 2015 +# CMC +# Notes: Set the path below to the XUP_LIB, and run source carry_save__adder.tcl to create the design +# It is assumed the pin constraints xdc file (carry_save_adder_basys3_pins.xdc) is in the project directory. +# If the constraints file is located somewhere else, modify the constraints_directory path below +# +# After sourcing this script, run_sim can be executed to drive simulation from proc at bottom of this file +# Once simulation is running (either from the GUI, or from this script) test_pattern can be executed to drive +# simulation input values defined at the bottom of this file +# +# Four 4-bit inputs (operands), x, y, z and w, are connected to the dip switches (a sw0-3, b sw 4-7, c sw 8-11, d sw 12-15) +# Pressing Center button resets the 7-segment display +# The 6-bit outputs are connected to LEDs 0-5 +# The outputs are also displayed on the 7-segment display in the BCD format +# +# -------------------------------------------------------------- # +# SET 'basys3_github' PATH TO GITHUB LIBRARY BEFORE RUNNING +# -------------------------------------------------------------- # +set basys3_github {C:/xup/IPI_LIB/XUP_LIB} + +set project_directory . +set project_name carry_save_adder_7seg +set constraints_directory $project_directory +set constraints_file carry_save_adder_7seg_basys3_pins.xdc +# Create project for Basys 3 +create_project -force $project_name ./$project_name -part xc7a35tcpg236-1 +set_property board_part digilentinc.com:basys3:part0:1.1 [current_project] +set_property target_language verilog [current_project] +set_property simulator_language Verilog [current_project] +set_property ip_repo_paths $basys3_github [current_project] +update_ip_catalog +create_bd_design "$project_name" + +# Steps: +# Build Half Adder +# Copy and add OR gate to make full adders +# Copy full adder 4 times to make a 4-bit carry save adder +# Copy and add another instance of the carry save adder +# Using full-adder create a 6-bit ripple carry adder +# Convert the 6-bit binary output to BCD +# Connect the BCD outputs to the 7-segment display + +# Build Half Adder +# create basic gates +create_bd_cell -type ip -vlnv xilinx.com:XUP:xup_xor2:1.0 xor_s +create_bd_cell -type ip -vlnv xilinx.com:XUP:xup_and2:1.0 and_c +# create HA hierarchical block +group_bd_cells half_adder [get_bd_cells xor_s] [get_bd_cells and_c] +# create pins on hierarchy block +create_bd_pin -dir I half_adder/a +create_bd_pin -dir I half_adder/b +create_bd_pin -dir O half_adder/s +create_bd_pin -dir O half_adder/c +# connect internal signals to pins +connect_bd_net [get_bd_pins half_adder/a] [get_bd_pins half_adder/and_c/a] +connect_bd_net [get_bd_pins half_adder/b] [get_bd_pins half_adder/and_c/b] +connect_bd_net [get_bd_pins half_adder/a] [get_bd_pins half_adder/xor_s/a] +connect_bd_net [get_bd_pins half_adder/b] [get_bd_pins half_adder/xor_s/b] +connect_bd_net [get_bd_pins half_adder/c] [get_bd_pins half_adder/and_c/y] +connect_bd_net [get_bd_pins half_adder/s] [get_bd_pins half_adder/xor_s/y] + +# Create Full adder +# copy half_adder +copy_bd_objs / [get_bd_cells {half_adder}] +# add OR gate +create_bd_cell -type ip -vlnv xilinx.com:XUP:xup_or2:1.0 or_carry_out +#create full_adder hierarchical block +group_bd_cells full_adder [get_bd_cells half_adder] [get_bd_cells half_adder1] [get_bd_cells or_carry_out] +# create full adder pins +create_bd_pin -dir I full_adder/a +create_bd_pin -dir I full_adder/b +create_bd_pin -dir I full_adder/c_in +create_bd_pin -dir O full_adder/s +create_bd_pin -dir O full_adder/c_out +# connect full adder nets +connect_bd_net [get_bd_pins full_adder/a] [get_bd_pins full_adder/half_adder/a] +connect_bd_net [get_bd_pins full_adder/b] [get_bd_pins full_adder/half_adder/b] +connect_bd_net [get_bd_pins full_adder/half_adder/s] [get_bd_pins full_adder/half_adder1/a] +connect_bd_net [get_bd_pins full_adder/c_in] [get_bd_pins full_adder/half_adder1/b] +connect_bd_net [get_bd_pins full_adder/half_adder/c] [get_bd_pins full_adder/or_carry_out/a] +connect_bd_net [get_bd_pins full_adder/half_adder1/c] [get_bd_pins full_adder/or_carry_out/b] +connect_bd_net [get_bd_pins full_adder/or_carry_out/y] [get_bd_pins full_adder/c_out] +connect_bd_net [get_bd_pins full_adder/half_adder1/s] [get_bd_pins full_adder/s] +# Create 4-bit carry save adder +# Copy and paste full adder +copy_bd_objs / [get_bd_cells {full_adder}] +copy_bd_objs / [get_bd_cells {full_adder}] +copy_bd_objs / [get_bd_cells {full_adder}] + +# create 4-bit carry save adder hierarchical block +group_bd_cells carry_save_adder_4_bit [get_bd_cells full_adder] [get_bd_cells full_adder1] [get_bd_cells full_adder2] [get_bd_cells full_adder3] +# create hierarchical block pins +create_bd_pin -dir I carry_save_adder_4_bit/x0 +create_bd_pin -dir I carry_save_adder_4_bit/x1 +create_bd_pin -dir I carry_save_adder_4_bit/x2 +create_bd_pin -dir I carry_save_adder_4_bit/x3 +create_bd_pin -dir I carry_save_adder_4_bit/y0 +create_bd_pin -dir I carry_save_adder_4_bit/y1 +create_bd_pin -dir I carry_save_adder_4_bit/y2 +create_bd_pin -dir I carry_save_adder_4_bit/y3 +create_bd_pin -dir I carry_save_adder_4_bit/z0 +create_bd_pin -dir I carry_save_adder_4_bit/z1 +create_bd_pin -dir I carry_save_adder_4_bit/z2 +create_bd_pin -dir I carry_save_adder_4_bit/z3 + +create_bd_pin -dir O carry_save_adder_4_bit/c0 +create_bd_pin -dir O carry_save_adder_4_bit/c1 +create_bd_pin -dir O carry_save_adder_4_bit/c2 +create_bd_pin -dir O carry_save_adder_4_bit/c3 +create_bd_pin -dir O carry_save_adder_4_bit/s0 +create_bd_pin -dir O carry_save_adder_4_bit/s1 +create_bd_pin -dir O carry_save_adder_4_bit/s2 +create_bd_pin -dir O carry_save_adder_4_bit/s3 +# connect pins +connect_bd_net [get_bd_pins carry_save_adder_4_bit/x0] [get_bd_pins carry_save_adder_4_bit/full_adder/a] +connect_bd_net [get_bd_pins carry_save_adder_4_bit/x1] [get_bd_pins carry_save_adder_4_bit/full_adder1/a] +connect_bd_net [get_bd_pins carry_save_adder_4_bit/x2] [get_bd_pins carry_save_adder_4_bit/full_adder2/a] +connect_bd_net [get_bd_pins carry_save_adder_4_bit/x3] [get_bd_pins carry_save_adder_4_bit/full_adder3/a] + +connect_bd_net [get_bd_pins carry_save_adder_4_bit/y0] [get_bd_pins carry_save_adder_4_bit/full_adder/b] +connect_bd_net [get_bd_pins carry_save_adder_4_bit/y1] [get_bd_pins carry_save_adder_4_bit/full_adder1/b] +connect_bd_net [get_bd_pins carry_save_adder_4_bit/y2] [get_bd_pins carry_save_adder_4_bit/full_adder2/b] +connect_bd_net [get_bd_pins carry_save_adder_4_bit/y3] [get_bd_pins carry_save_adder_4_bit/full_adder3/b] + +connect_bd_net [get_bd_pins carry_save_adder_4_bit/z0] [get_bd_pins carry_save_adder_4_bit/full_adder/c_in] +connect_bd_net [get_bd_pins carry_save_adder_4_bit/z1] [get_bd_pins carry_save_adder_4_bit/full_adder1/c_in] +connect_bd_net [get_bd_pins carry_save_adder_4_bit/z2] [get_bd_pins carry_save_adder_4_bit/full_adder2/c_in] +connect_bd_net [get_bd_pins carry_save_adder_4_bit/z3] [get_bd_pins carry_save_adder_4_bit/full_adder3/c_in] + +connect_bd_net [get_bd_pins carry_save_adder_4_bit/s0] [get_bd_pins carry_save_adder_4_bit/full_adder/s] +connect_bd_net [get_bd_pins carry_save_adder_4_bit/s1] [get_bd_pins carry_save_adder_4_bit/full_adder1/s] +connect_bd_net [get_bd_pins carry_save_adder_4_bit/s2] [get_bd_pins carry_save_adder_4_bit/full_adder2/s] +connect_bd_net [get_bd_pins carry_save_adder_4_bit/s3] [get_bd_pins carry_save_adder_4_bit/full_adder3/s] + +connect_bd_net [get_bd_pins carry_save_adder_4_bit/c0] [get_bd_pins carry_save_adder_4_bit/full_adder/c_out] +connect_bd_net [get_bd_pins carry_save_adder_4_bit/c1] [get_bd_pins carry_save_adder_4_bit/full_adder1/c_out] +connect_bd_net [get_bd_pins carry_save_adder_4_bit/c2] [get_bd_pins carry_save_adder_4_bit/full_adder2/c_out] +connect_bd_net [get_bd_pins carry_save_adder_4_bit/c3] [get_bd_pins carry_save_adder_4_bit/full_adder3/c_out] + +# Create 8-bit carry save adder +copy_bd_objs / [get_bd_cells {carry_save_adder_4_bit}] + + +#Create top level i/o ports and connect to 4 bit adders +# w +create_bd_port -dir I w0 +connect_bd_net [get_bd_pins /carry_save_adder_4_bit1/x0] [get_bd_ports w0] +create_bd_port -dir I w1 +connect_bd_net [get_bd_pins /carry_save_adder_4_bit1/x1] [get_bd_ports w1] +create_bd_port -dir I w2 +connect_bd_net [get_bd_pins /carry_save_adder_4_bit1/x2] [get_bd_ports w2] +create_bd_port -dir I w3 +connect_bd_net [get_bd_pins /carry_save_adder_4_bit1/x3] [get_bd_ports w3] +# x +create_bd_port -dir I x0 +connect_bd_net [get_bd_pins /carry_save_adder_4_bit/x0] [get_bd_ports x0] +create_bd_port -dir I x1 +connect_bd_net [get_bd_pins /carry_save_adder_4_bit/x1] [get_bd_ports x1] +create_bd_port -dir I x2 +connect_bd_net [get_bd_pins /carry_save_adder_4_bit/x2] [get_bd_ports x2] +create_bd_port -dir I x3 +connect_bd_net [get_bd_pins /carry_save_adder_4_bit/x3] [get_bd_ports x3] +# y +create_bd_port -dir I y0 +connect_bd_net [get_bd_pins /carry_save_adder_4_bit/y0] [get_bd_ports y0] +create_bd_port -dir I y1 +connect_bd_net [get_bd_pins /carry_save_adder_4_bit/y1] [get_bd_ports y1] +create_bd_port -dir I y2 +connect_bd_net [get_bd_pins /carry_save_adder_4_bit/y2] [get_bd_ports y2] +create_bd_port -dir I y3 +connect_bd_net [get_bd_pins /carry_save_adder_4_bit/y3] [get_bd_ports y3] +#z +create_bd_port -dir I z0 +connect_bd_net [get_bd_pins /carry_save_adder_4_bit/z0] [get_bd_ports z0] +create_bd_port -dir I z1 +connect_bd_net [get_bd_pins /carry_save_adder_4_bit/z1] [get_bd_ports z1] +create_bd_port -dir I z2 +connect_bd_net [get_bd_pins /carry_save_adder_4_bit/z2] [get_bd_ports z2] +create_bd_port -dir I z3 +connect_bd_net [get_bd_pins /carry_save_adder_4_bit/z3] [get_bd_ports z3] + + +connect_bd_net [get_bd_pins carry_save_adder_4_bit/c0] [get_bd_pins carry_save_adder_4_bit1/z1] -boundary_type upper +connect_bd_net [get_bd_pins carry_save_adder_4_bit/c1] [get_bd_pins carry_save_adder_4_bit1/z2] -boundary_type upper +connect_bd_net [get_bd_pins carry_save_adder_4_bit/c2] [get_bd_pins carry_save_adder_4_bit1/z3] -boundary_type upper +connect_bd_net [get_bd_pins carry_save_adder_4_bit/s0] [get_bd_pins carry_save_adder_4_bit1/y0] -boundary_type upper +connect_bd_net [get_bd_pins carry_save_adder_4_bit/s1] [get_bd_pins carry_save_adder_4_bit1/y1] -boundary_type upper +connect_bd_net [get_bd_pins carry_save_adder_4_bit/s2] [get_bd_pins carry_save_adder_4_bit1/y2] -boundary_type upper +connect_bd_net [get_bd_pins carry_save_adder_4_bit/s3] [get_bd_pins carry_save_adder_4_bit1/y3] -boundary_type upper + + + +# outputs +# create_bd_port -dir O s0 +# connect_bd_net [get_bd_pins /carry_save_adder_4_bit1/s0] [get_bd_ports s0] +# create_bd_port -dir O s1 +# connect_bd_net [get_bd_pins /carry_save_adder_4_bit1/s1] [get_bd_ports s1] +# create_bd_port -dir O s2 +# connect_bd_net [get_bd_pins /carry_save_adder_4_bit1/s2] [get_bd_ports s2] +# create_bd_port -dir O s3 +# connect_bd_net [get_bd_pins /carry_save_adder_4_bit1/s3] [get_bd_ports s3] +# create_bd_port -dir O c0 +# connect_bd_net [get_bd_pins /carry_save_adder_4_bit1/c0] [get_bd_ports c0] +# create_bd_port -dir O c1 +# connect_bd_net [get_bd_pins /carry_save_adder_4_bit1/c1] [get_bd_ports c1] +# create_bd_port -dir O c2 +# connect_bd_net [get_bd_pins /carry_save_adder_4_bit1/c2] [get_bd_ports c2] +# create_bd_port -dir O c3 +# connect_bd_net [get_bd_pins /carry_save_adder_4_bit1/c3] [get_bd_ports c3] +# create_bd_port -dir O c4 +# connect_bd_net [get_bd_pins /carry_save_adder_4_bit/c3] [get_bd_ports c4] + + +########################################################################### +## Ripple carry adder for last stage +########################################################################### + +# Steps: +# Build Half Adder +# Copy and add OR gate to make full adders +# Copy full adder 4 times to make 4-bit carry ripple adders +# copy 4-bit adder 2 times to make 8-bit adder + +# Build Half Adder +# create basic gates +create_bd_cell -type ip -vlnv xilinx.com:XUP:xup_xor2:1.0 xor_s +create_bd_cell -type ip -vlnv xilinx.com:XUP:xup_and2:1.0 and_c +# create HA hierarchical block +group_bd_cells half_adder [get_bd_cells xor_s] [get_bd_cells and_c] +# create pins on hierarchy block +create_bd_pin -dir I half_adder/a +create_bd_pin -dir I half_adder/b +create_bd_pin -dir O half_adder/s +create_bd_pin -dir O half_adder/c +# connect internal signals to pins +connect_bd_net [get_bd_pins half_adder/a] [get_bd_pins half_adder/and_c/a] +connect_bd_net [get_bd_pins half_adder/b] [get_bd_pins half_adder/and_c/b] +connect_bd_net [get_bd_pins half_adder/a] [get_bd_pins half_adder/xor_s/a] +connect_bd_net [get_bd_pins half_adder/b] [get_bd_pins half_adder/xor_s/b] +connect_bd_net [get_bd_pins half_adder/c] [get_bd_pins half_adder/and_c/y] +connect_bd_net [get_bd_pins half_adder/s] [get_bd_pins half_adder/xor_s/y] + +# Create Full adder +# copy half_adder +copy_bd_objs / [get_bd_cells {half_adder}] +# add OR gate +create_bd_cell -type ip -vlnv xilinx.com:XUP:xup_or2:1.0 or_carry_out +#create full_adder hierarchical block +group_bd_cells full_adder [get_bd_cells half_adder] [get_bd_cells half_adder1] [get_bd_cells or_carry_out] +# create full adder pins +create_bd_pin -dir I full_adder/a +create_bd_pin -dir I full_adder/b +create_bd_pin -dir I full_adder/c_in +create_bd_pin -dir O full_adder/s +create_bd_pin -dir O full_adder/c_out +# connect full adder nets +connect_bd_net [get_bd_pins full_adder/a] [get_bd_pins full_adder/half_adder/a] +connect_bd_net [get_bd_pins full_adder/b] [get_bd_pins full_adder/half_adder/b] +connect_bd_net [get_bd_pins full_adder/half_adder/s] [get_bd_pins full_adder/half_adder1/a] +connect_bd_net [get_bd_pins full_adder/c_in] [get_bd_pins full_adder/half_adder1/b] +connect_bd_net [get_bd_pins full_adder/half_adder/c] [get_bd_pins full_adder/or_carry_out/a] +connect_bd_net [get_bd_pins full_adder/half_adder1/c] [get_bd_pins full_adder/or_carry_out/b] +connect_bd_net [get_bd_pins full_adder/or_carry_out/y] [get_bd_pins full_adder/c_out] +connect_bd_net [get_bd_pins full_adder/half_adder1/s] [get_bd_pins full_adder/s] +# Create 4-bit carry ripple adder +# Copy and paste full adder +copy_bd_objs / [get_bd_cells {full_adder}] +copy_bd_objs / [get_bd_cells {full_adder}] +copy_bd_objs / [get_bd_cells {full_adder}] +# Connect carrys +connect_bd_net [get_bd_pins full_adder/c_out] [get_bd_pins full_adder1/c_in] -boundary_type upper +connect_bd_net [get_bd_pins full_adder1/c_out] [get_bd_pins full_adder2/c_in] -boundary_type upper +connect_bd_net [get_bd_pins full_adder2/c_out] [get_bd_pins full_adder3/c_in] -boundary_type upper +# create 4-bit carry ripple adder hierarchical block +group_bd_cells ripple_carry_adder_4_bit [get_bd_cells full_adder] [get_bd_cells full_adder1] [get_bd_cells full_adder2] [get_bd_cells full_adder3] +# create hierarchical block pins +create_bd_pin -dir I ripple_carry_adder_4_bit/a0 +create_bd_pin -dir I ripple_carry_adder_4_bit/a1 +create_bd_pin -dir I ripple_carry_adder_4_bit/a2 +create_bd_pin -dir I ripple_carry_adder_4_bit/a3 +create_bd_pin -dir I ripple_carry_adder_4_bit/b0 +create_bd_pin -dir I ripple_carry_adder_4_bit/b1 +create_bd_pin -dir I ripple_carry_adder_4_bit/b2 +create_bd_pin -dir I ripple_carry_adder_4_bit/b3 + +create_bd_pin -dir I ripple_carry_adder_4_bit/c_in + +create_bd_pin -dir O ripple_carry_adder_4_bit/s0 +create_bd_pin -dir O ripple_carry_adder_4_bit/s1 +create_bd_pin -dir O ripple_carry_adder_4_bit/s2 +create_bd_pin -dir O ripple_carry_adder_4_bit/s3 + +create_bd_pin -dir O ripple_carry_adder_4_bit/c_out +# connect pins +connect_bd_net [get_bd_pins ripple_carry_adder_4_bit/a0] [get_bd_pins ripple_carry_adder_4_bit/full_adder/a] +connect_bd_net [get_bd_pins ripple_carry_adder_4_bit/a1] [get_bd_pins ripple_carry_adder_4_bit/full_adder1/a] +connect_bd_net [get_bd_pins ripple_carry_adder_4_bit/a2] [get_bd_pins ripple_carry_adder_4_bit/full_adder2/a] +connect_bd_net [get_bd_pins ripple_carry_adder_4_bit/a3] [get_bd_pins ripple_carry_adder_4_bit/full_adder3/a] + +connect_bd_net [get_bd_pins ripple_carry_adder_4_bit/b0] [get_bd_pins ripple_carry_adder_4_bit/full_adder/b] +connect_bd_net [get_bd_pins ripple_carry_adder_4_bit/b1] [get_bd_pins ripple_carry_adder_4_bit/full_adder1/b] +connect_bd_net [get_bd_pins ripple_carry_adder_4_bit/b2] [get_bd_pins ripple_carry_adder_4_bit/full_adder2/b] +connect_bd_net [get_bd_pins ripple_carry_adder_4_bit/b3] [get_bd_pins ripple_carry_adder_4_bit/full_adder3/b] + +connect_bd_net [get_bd_pins ripple_carry_adder_4_bit/c_in] [get_bd_pins ripple_carry_adder_4_bit/full_adder/c_in] + +connect_bd_net [get_bd_pins ripple_carry_adder_4_bit/s0] [get_bd_pins ripple_carry_adder_4_bit/full_adder/s] +connect_bd_net [get_bd_pins ripple_carry_adder_4_bit/s1] [get_bd_pins ripple_carry_adder_4_bit/full_adder1/s] +connect_bd_net [get_bd_pins ripple_carry_adder_4_bit/s2] [get_bd_pins ripple_carry_adder_4_bit/full_adder2/s] +connect_bd_net [get_bd_pins ripple_carry_adder_4_bit/s3] [get_bd_pins ripple_carry_adder_4_bit/full_adder3/s] + +connect_bd_net [get_bd_pins ripple_carry_adder_4_bit/c_out] [get_bd_pins ripple_carry_adder_4_bit/full_adder3/c_out] + +# Create 8-bit carry ripple adder +copy_bd_objs / [get_bd_cells {ripple_carry_adder_4_bit}] +connect_bd_net [get_bd_pins ripple_carry_adder_4_bit/c_out] [get_bd_pins ripple_carry_adder_4_bit1/c_in] + +group_bd_cells ripple_carry_adder_8_bit [get_bd_cells ripple_carry_adder_4_bit1] [get_bd_cells ripple_carry_adder_4_bit] + +#Create top level i/o ports and connect to 4 bit adders +# a +create_bd_pin -dir I /ripple_carry_adder_8_bit/a0 +connect_bd_net [get_bd_pins /ripple_carry_adder_8_bit/ripple_carry_adder_4_bit/a0] [get_bd_pins /ripple_carry_adder_8_bit/a0] +create_bd_pin -dir I /ripple_carry_adder_8_bit/a1 +connect_bd_net [get_bd_pins /ripple_carry_adder_8_bit/ripple_carry_adder_4_bit/a1] [get_bd_pins /ripple_carry_adder_8_bit/a1] +create_bd_pin -dir I /ripple_carry_adder_8_bit/a2 +connect_bd_net [get_bd_pins /ripple_carry_adder_8_bit/ripple_carry_adder_4_bit/a2] [get_bd_pins /ripple_carry_adder_8_bit/a2] +create_bd_pin -dir I /ripple_carry_adder_8_bit/a3 +connect_bd_net [get_bd_pins /ripple_carry_adder_8_bit/ripple_carry_adder_4_bit/a3] [get_bd_pins /ripple_carry_adder_8_bit/a3] +create_bd_pin -dir I /ripple_carry_adder_8_bit/a4 +connect_bd_net [get_bd_pins /ripple_carry_adder_8_bit/ripple_carry_adder_4_bit1/a0] [get_bd_pins /ripple_carry_adder_8_bit/a4] +create_bd_pin -dir I /ripple_carry_adder_8_bit/a5 +connect_bd_net [get_bd_pins /ripple_carry_adder_8_bit/ripple_carry_adder_4_bit1/a1] [get_bd_pins /ripple_carry_adder_8_bit/a5] +create_bd_pin -dir I /ripple_carry_adder_8_bit/a6 +connect_bd_net [get_bd_pins /ripple_carry_adder_8_bit/ripple_carry_adder_4_bit1/a2] [get_bd_pins /ripple_carry_adder_8_bit/a6] +create_bd_pin -dir I /ripple_carry_adder_8_bit/a7 +connect_bd_net [get_bd_pins /ripple_carry_adder_8_bit/ripple_carry_adder_4_bit1/a3] [get_bd_pins /ripple_carry_adder_8_bit/a7] +# b +create_bd_pin -dir I /ripple_carry_adder_8_bit/b0 +connect_bd_net [get_bd_pins /ripple_carry_adder_8_bit/ripple_carry_adder_4_bit/b0] [get_bd_pins /ripple_carry_adder_8_bit/b0] +create_bd_pin -dir I /ripple_carry_adder_8_bit/b1 +connect_bd_net [get_bd_pins /ripple_carry_adder_8_bit/ripple_carry_adder_4_bit/b1] [get_bd_pins /ripple_carry_adder_8_bit/b1] +create_bd_pin -dir I /ripple_carry_adder_8_bit/b2 +connect_bd_net [get_bd_pins /ripple_carry_adder_8_bit/ripple_carry_adder_4_bit/b2] [get_bd_pins /ripple_carry_adder_8_bit/b2] +create_bd_pin -dir I /ripple_carry_adder_8_bit/b3 +connect_bd_net [get_bd_pins /ripple_carry_adder_8_bit/ripple_carry_adder_4_bit/b3] [get_bd_pins /ripple_carry_adder_8_bit/b3] +create_bd_pin -dir I /ripple_carry_adder_8_bit/b4 +connect_bd_net [get_bd_pins /ripple_carry_adder_8_bit/ripple_carry_adder_4_bit1/b0] [get_bd_pins /ripple_carry_adder_8_bit/b4] +create_bd_pin -dir I /ripple_carry_adder_8_bit/b5 +connect_bd_net [get_bd_pins /ripple_carry_adder_8_bit/ripple_carry_adder_4_bit1/b1] [get_bd_pins /ripple_carry_adder_8_bit/b5] +create_bd_pin -dir I /ripple_carry_adder_8_bit/b6 +connect_bd_net [get_bd_pins /ripple_carry_adder_8_bit/ripple_carry_adder_4_bit1/b2] [get_bd_pins /ripple_carry_adder_8_bit/b6] +create_bd_pin -dir I /ripple_carry_adder_8_bit/b7 +connect_bd_net [get_bd_pins /ripple_carry_adder_8_bit/ripple_carry_adder_4_bit1/b3] [get_bd_pins /ripple_carry_adder_8_bit/b7] + +# carry in +#create_bd_pin -dir I /ripple_carry_adder_8_bit/c_in +#connect_bd_net [get_bd_pins /ripple_carry_adder_8_bit/ripple_carry_adder_8_bit/c_in] [get_bd_pins /ripple_carry_adder_8_bit/c_in] +# outputs +create_bd_pin -dir O /ripple_carry_adder_8_bit/o0 +connect_bd_net [get_bd_pins /ripple_carry_adder_8_bit/ripple_carry_adder_4_bit/s0] [get_bd_pins /ripple_carry_adder_8_bit/o0] +create_bd_pin -dir O /ripple_carry_adder_8_bit/o1 +connect_bd_net [get_bd_pins /ripple_carry_adder_8_bit/ripple_carry_adder_4_bit/s1] [get_bd_pins /ripple_carry_adder_8_bit/o1] +create_bd_pin -dir O /ripple_carry_adder_8_bit/o2 +connect_bd_net [get_bd_pins /ripple_carry_adder_8_bit/ripple_carry_adder_4_bit/s2] [get_bd_pins /ripple_carry_adder_8_bit/o2] +create_bd_pin -dir O /ripple_carry_adder_8_bit/o3 +connect_bd_net [get_bd_pins /ripple_carry_adder_8_bit/ripple_carry_adder_4_bit/s3] [get_bd_pins /ripple_carry_adder_8_bit/o3] +create_bd_pin -dir O /ripple_carry_adder_8_bit/o4 +connect_bd_net [get_bd_pins /ripple_carry_adder_8_bit/ripple_carry_adder_4_bit1/s0] [get_bd_pins /ripple_carry_adder_8_bit/o4] +create_bd_pin -dir O /ripple_carry_adder_8_bit/o5 +connect_bd_net [get_bd_pins /ripple_carry_adder_8_bit/ripple_carry_adder_4_bit1/s1] [get_bd_pins /ripple_carry_adder_8_bit/o5] +create_bd_pin -dir O /ripple_carry_adder_8_bit/o6 +connect_bd_net [get_bd_pins /ripple_carry_adder_8_bit/ripple_carry_adder_4_bit1/s2] [get_bd_pins /ripple_carry_adder_8_bit/o6] +create_bd_pin -dir O /ripple_carry_adder_8_bit/o7 +connect_bd_net [get_bd_pins /ripple_carry_adder_8_bit/ripple_carry_adder_4_bit1/s3] [get_bd_pins /ripple_carry_adder_8_bit/o7] +# carry out +create_bd_pin -dir O /ripple_carry_adder_8_bit/c_out +connect_bd_net [get_bd_pins /ripple_carry_adder_8_bit/ripple_carry_adder_4_bit1/c_out] [get_bd_pins /ripple_carry_adder_8_bit/c_out] + +## END Ripple Carry Adder + + +connect_bd_net [get_bd_pins carry_save_adder_4_bit1/s1] [get_bd_pins ripple_carry_adder_8_bit/b0] -boundary_type upper +connect_bd_net [get_bd_pins carry_save_adder_4_bit1/s2] [get_bd_pins ripple_carry_adder_8_bit/b1] -boundary_type upper +connect_bd_net [get_bd_pins carry_save_adder_4_bit1/s3] [get_bd_pins ripple_carry_adder_8_bit/b2] -boundary_type upper +connect_bd_net [get_bd_pins carry_save_adder_4_bit1/c0] [get_bd_pins ripple_carry_adder_8_bit/a0] -boundary_type upper +connect_bd_net [get_bd_pins carry_save_adder_4_bit1/c1] [get_bd_pins ripple_carry_adder_8_bit/a1] -boundary_type upper +connect_bd_net [get_bd_pins carry_save_adder_4_bit1/c2] [get_bd_pins ripple_carry_adder_8_bit/a2] -boundary_type upper +connect_bd_net [get_bd_pins carry_save_adder_4_bit/c3] [get_bd_pins ripple_carry_adder_8_bit/b3] -boundary_type upper +connect_bd_net [get_bd_pins carry_save_adder_4_bit1/c3] [get_bd_pins ripple_carry_adder_8_bit/a3] -boundary_type upper + +create_bd_port -dir O s0 +connect_bd_net [get_bd_pins /carry_save_adder_4_bit1/s0] [get_bd_ports s0] +create_bd_port -dir O s1 +connect_bd_net [get_bd_pins /ripple_carry_adder_8_bit/o0] [get_bd_ports s1] +create_bd_port -dir O s2 +connect_bd_net [get_bd_pins /ripple_carry_adder_8_bit/o1] [get_bd_ports s2] +create_bd_port -dir O s3 +connect_bd_net [get_bd_pins /ripple_carry_adder_8_bit/o2] [get_bd_ports s3] +create_bd_port -dir O s4 +connect_bd_net [get_bd_pins /ripple_carry_adder_8_bit/o3] [get_bd_ports s4] +create_bd_port -dir O s5 +connect_bd_net [get_bd_pins /ripple_carry_adder_8_bit/o4] [get_bd_ports s5] + +create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 gnd +set_property -dict [list CONFIG.CONST_VAL {0}] [get_bd_cells gnd] +connect_bd_net [get_bd_pins gnd/dout] [get_bd_pins ripple_carry_adder_8_bit/b4] +connect_bd_net -net [get_bd_nets gnd_dout] [get_bd_pins ripple_carry_adder_8_bit/b5] +connect_bd_net -net [get_bd_nets gnd_dout] [get_bd_pins ripple_carry_adder_8_bit/b6] +connect_bd_net -net [get_bd_nets gnd_dout] [get_bd_pins ripple_carry_adder_8_bit/b7] +connect_bd_net -net [get_bd_nets gnd_dout] [get_bd_pins ripple_carry_adder_8_bit/a4] +connect_bd_net -net [get_bd_nets gnd_dout] [get_bd_pins ripple_carry_adder_8_bit/a5] +connect_bd_net -net [get_bd_nets gnd_dout] [get_bd_pins ripple_carry_adder_8_bit/a6] +connect_bd_net -net [get_bd_nets gnd_dout] [get_bd_pins ripple_carry_adder_8_bit/a7] +connect_bd_net -net [get_bd_nets gnd_dout] [get_bd_pins carry_save_adder_4_bit1/z0] + +create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 ripple_carry_adder_8_bit/gnd +set_property -dict [list CONFIG.CONST_VAL {0}] [get_bd_cells ripple_carry_adder_8_bit/gnd] +connect_bd_net [get_bd_pins ripple_carry_adder_8_bit/gnd/dout] [get_bd_pins ripple_carry_adder_8_bit/ripple_carry_adder_4_bit/c_in] + +# Convert the 6-bit binary output to BCD +create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 xlconcat_0 +set_property -dict [list CONFIG.NUM_PORTS {6}] [get_bd_cells xlconcat_0] +connect_bd_net -net [get_bd_nets carry_save_adder_4_bit1_s0] [get_bd_pins xlconcat_0/In0] [get_bd_pins carry_save_adder_4_bit1/s0] +connect_bd_net -net [get_bd_nets ripple_carry_adder_8_bit_o0] [get_bd_pins xlconcat_0/In1] [get_bd_pins ripple_carry_adder_8_bit/o0] +connect_bd_net -net [get_bd_nets ripple_carry_adder_8_bit_o1] [get_bd_pins xlconcat_0/In2] [get_bd_pins ripple_carry_adder_8_bit/o1] +connect_bd_net -net [get_bd_nets ripple_carry_adder_8_bit_o2] [get_bd_pins xlconcat_0/In3] [get_bd_pins ripple_carry_adder_8_bit/o2] +connect_bd_net -net [get_bd_nets ripple_carry_adder_8_bit_o3] [get_bd_pins xlconcat_0/In4] [get_bd_pins ripple_carry_adder_8_bit/o3] +connect_bd_net -net [get_bd_nets ripple_carry_adder_8_bit_o4] [get_bd_pins xlconcat_0/In5] [get_bd_pins ripple_carry_adder_8_bit/o4] +create_bd_cell -type ip -vlnv xilinx.com:XUP:bin2bcd:1.0 bin2bcd_0 +set_property -dict [list CONFIG.SIZE {6}] [get_bd_cells bin2bcd_0] +connect_bd_net [get_bd_pins xlconcat_0/dout] [get_bd_pins bin2bcd_0/a_in] + + +# Connect the BCD outputs to the 7-segment display +create_bd_cell -type ip -vlnv xilinx.com:XUP:seg7display:1.0 seg7display_0 +create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 xlconstant_0 +set_property -dict [list CONFIG.CONST_WIDTH {8} CONFIG.CONST_VAL {0}] [get_bd_cells xlconstant_0] +create_bd_cell -type ip -vlnv xilinx.com:ip:clk_wiz:5.1 clk_wiz_0 +set_property -dict [list CONFIG.USE_LOCKED {false} CONFIG.USE_RESET {false}] [get_bd_cells clk_wiz_0] +connect_bd_net [get_bd_pins clk_wiz_0/clk_out1] [get_bd_pins seg7display_0/clk] +create_bd_port -dir I -type clk sys_clock +connect_bd_net [get_bd_pins /clk_wiz_0/clk_in1] [get_bd_ports sys_clock] +create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 xlconcat_1 +set_property -dict [list CONFIG.NUM_PORTS {3}] [get_bd_cells xlconcat_1] +connect_bd_net [get_bd_pins xlconcat_1/In0] [get_bd_pins bin2bcd_0/ones] +connect_bd_net [get_bd_pins xlconcat_1/In1] [get_bd_pins bin2bcd_0/tens] +connect_bd_net [get_bd_pins xlconstant_0/dout] [get_bd_pins xlconcat_1/In2] +connect_bd_net [get_bd_pins xlconcat_1/dout] [get_bd_pins seg7display_0/x_l] +create_bd_port -dir I -type rst reset +connect_bd_net [get_bd_pins /seg7display_0/reset] [get_bd_ports reset] +create_bd_port -dir O -from 6 -to 0 a_to_g +connect_bd_net [get_bd_pins /seg7display_0/a_to_g] [get_bd_ports a_to_g] +create_bd_port -dir O -from 3 -to 0 an_l +connect_bd_net [get_bd_pins /seg7display_0/an_l] [get_bd_ports an_l] +set_property name seg [get_bd_ports a_to_g] +set_property name an [get_bd_ports an_l] +regenerate_bd_layout +save_bd_design + +# Create top HDL wrapper +make_wrapper -files [get_files $project_directory/$project_name/$project_name.srcs/sources_1/bd/$project_name/$project_name.bd] -top +add_files -norecurse $project_directory/$project_name/$project_name.srcs/sources_1/bd/$project_name/hdl/$project_name\_wrapper.v +# Add pin constraints +add_files -fileset constrs_1 -norecurse $constraints_directory/$constraints_file diff --git a/Projects/Logic_Design/CN_Design/Carry_Save_Adder_7Seg/src/carry_save_adder_7seg_basys3_pins.xdc b/Projects/Logic_Design/CN_Design/Carry_Save_Adder_7Seg/src/carry_save_adder_7seg_basys3_pins.xdc new file mode 100644 index 0000000..ccb7aec --- /dev/null +++ b/Projects/Logic_Design/CN_Design/Carry_Save_Adder_7Seg/src/carry_save_adder_7seg_basys3_pins.xdc @@ -0,0 +1,82 @@ +#Pin constraints for addition of four 4-bit operands using carry save adder design for Basys 3 +## Clock signal +set_property PACKAGE_PIN W5 [get_ports sys_clock] +set_property IOSTANDARD LVCMOS33 [get_ports sys_clock] +create_clock -period 10.000 -name sys_clk_pin -waveform {0.000 5.000} -add [get_ports sys_clock] + +# pushbutton BtnC +set_property PACKAGE_PIN U18 [get_ports reset] +set_property IOSTANDARD LVCMOS33 [get_ports reset] + +##7 segment display +set_property PACKAGE_PIN W7 [get_ports {seg[0]}] +set_property IOSTANDARD LVCMOS33 [get_ports {seg[0]}] +set_property PACKAGE_PIN W6 [get_ports {seg[1]}] +set_property IOSTANDARD LVCMOS33 [get_ports {seg[1]}] +set_property PACKAGE_PIN U8 [get_ports {seg[2]}] +set_property IOSTANDARD LVCMOS33 [get_ports {seg[2]}] +set_property PACKAGE_PIN V8 [get_ports {seg[3]}] +set_property IOSTANDARD LVCMOS33 [get_ports {seg[3]}] +set_property PACKAGE_PIN U5 [get_ports {seg[4]}] +set_property IOSTANDARD LVCMOS33 [get_ports {seg[4]}] +set_property PACKAGE_PIN V5 [get_ports {seg[5]}] +set_property IOSTANDARD LVCMOS33 [get_ports {seg[5]}] +set_property PACKAGE_PIN U7 [get_ports {seg[6]}] +set_property IOSTANDARD LVCMOS33 [get_ports {seg[6]}] + +set_property PACKAGE_PIN U2 [get_ports {an[0]}] +set_property IOSTANDARD LVCMOS33 [get_ports {an[0]}] +set_property PACKAGE_PIN U4 [get_ports {an[1]}] +set_property IOSTANDARD LVCMOS33 [get_ports {an[1]}] +set_property PACKAGE_PIN V4 [get_ports {an[2]}] +set_property IOSTANDARD LVCMOS33 [get_ports {an[2]}] +set_property PACKAGE_PIN W4 [get_ports {an[3]}] +set_property IOSTANDARD LVCMOS33 [get_ports {an[3]}] + +## Switches +set_property PACKAGE_PIN V17 [get_ports {w0}] + set_property IOSTANDARD LVCMOS33 [get_ports {w0}] +set_property PACKAGE_PIN V16 [get_ports {w1}] + set_property IOSTANDARD LVCMOS33 [get_ports {w1}] +set_property PACKAGE_PIN W16 [get_ports {w2}] + set_property IOSTANDARD LVCMOS33 [get_ports {w2}] +set_property PACKAGE_PIN W17 [get_ports {w3}] + set_property IOSTANDARD LVCMOS33 [get_ports {w3}] +set_property PACKAGE_PIN W15 [get_ports {x0}] + set_property IOSTANDARD LVCMOS33 [get_ports {x0}] +set_property PACKAGE_PIN V15 [get_ports {x1}] + set_property IOSTANDARD LVCMOS33 [get_ports {x1}] +set_property PACKAGE_PIN W14 [get_ports {x2}] + set_property IOSTANDARD LVCMOS33 [get_ports {x2}] +set_property PACKAGE_PIN W13 [get_ports {x3}] + set_property IOSTANDARD LVCMOS33 [get_ports {x3}] +set_property PACKAGE_PIN V2 [get_ports {y0}] + set_property IOSTANDARD LVCMOS33 [get_ports {y0}] +set_property PACKAGE_PIN T3 [get_ports {y1}] + set_property IOSTANDARD LVCMOS33 [get_ports {y1}] +set_property PACKAGE_PIN T2 [get_ports {y2}] + set_property IOSTANDARD LVCMOS33 [get_ports {y2}] +set_property PACKAGE_PIN R3 [get_ports {y3}] + set_property IOSTANDARD LVCMOS33 [get_ports {y3}] +set_property PACKAGE_PIN W2 [get_ports {z0}] + set_property IOSTANDARD LVCMOS33 [get_ports {z0}] +set_property PACKAGE_PIN U1 [get_ports {z1}] + set_property IOSTANDARD LVCMOS33 [get_ports {z1}] +set_property PACKAGE_PIN T1 [get_ports {z2}] + set_property IOSTANDARD LVCMOS33 [get_ports {z2}] +set_property PACKAGE_PIN R2 [get_ports {z3}] + set_property IOSTANDARD LVCMOS33 [get_ports {z3}] + +# LEDs +set_property PACKAGE_PIN U16 [get_ports {s0}] + set_property IOSTANDARD LVCMOS33 [get_ports {s0}] +set_property PACKAGE_PIN E19 [get_ports {s1}] + set_property IOSTANDARD LVCMOS33 [get_ports {s1}] +set_property PACKAGE_PIN U19 [get_ports {s2}] + set_property IOSTANDARD LVCMOS33 [get_ports {s2}] +set_property PACKAGE_PIN V19 [get_ports {s3}] + set_property IOSTANDARD LVCMOS33 [get_ports {s3}] +set_property PACKAGE_PIN W18 [get_ports {s4}] + set_property IOSTANDARD LVCMOS33 [get_ports {s4}] +set_property PACKAGE_PIN U15 [get_ports {s5}] + set_property IOSTANDARD LVCMOS33 [get_ports {s5}] diff --git a/Projects/Logic_Design/CN_Design/Ripple_Carry_Adder/README.md b/Projects/Logic_Design/CN_Design/Ripple_Carry_Adder/README.md new file mode 100644 index 0000000..4ff408b --- /dev/null +++ b/Projects/Logic_Design/CN_Design/Ripple_Carry_Adder/README.md @@ -0,0 +1,57 @@ +# Ripple-Carry Adder +This project creates an 8-bit ripple-carry adder using XUP_LIB components. You must download the XUP_LIB directory from the GitHub and then set the XUP_LIB path. You must also download the Basys3 board files directory from the GitHub and place it in the **\\2014.4\data\boards\board_parts\artix7** directory. + +The project source files include a Tcl script, Xilinx Design Constraint (xdc) file targeting Basys3 board, testbench, and a wave configuration (wcfg) file. + +### Design Description: +The 8-bit adder is built from two 4-bit ripple-carry adders. The 4-bit ripple-carry adder is built from four full adders. The full adder is built from two half adders. The hierarchy of the design can be explored by opening or expanding the hierarchical blocks. + +### Tools and requirements: +* Vivado 2014.4 +* XUP_LIB from GitHub +* Basys3 board files from GitHub + +### Procedure: +Execute the commands **in bold** in the tcl console + +1\. Start Vivado + +2\. Set a variable *basys3_github* to the XUP_LIB path in the Vivado Tcl Console. Note the path uses "/" instead of "\". Substitute the path to where you have saved the XUP_LIB library: + +**set basys3_github {C:/xup/IPI_LIB/XUP_LIB}** + +3\. Change to the *src* directory of this project using the *cd* command: + +**cd \** + +4\. Execute the following command to run the script: + +**source ./ripple_carry_adder.tcl** + +5\. Once the project is created, the resulting block diagram will be displayed. View the block diagram, double click or expand blocks to navigate the hierarchy and analyze the design +6\. Execute the following command to run the behavioral simulation: + +**run_sim** + +7\. Analyze the results and notice the output transitioning after the input changes. When satisfied, close the simulator: + +**close_sim** + +8\. Generate the bitstream by clicking on the *Generate Bitstream* under the *Program and Debug* group + +9\. When the bitstream generation is completed, connect the board, power ON the board, and use the *Open Hardware Manager* option to connect to the board + +10\. *Program* the board and verify the functionality + +Input 1 : Dipswitches 0-7 + +Input 2 : Dipswitches 8-15 + +Result : Leds 0-7 + +Carry In : Centre pushbutton + +Carry Out : Led 15 + + + diff --git a/Projects/Logic_Design/CN_Design/Ripple_Carry_Adder/src/ripple_carry_adder.tcl b/Projects/Logic_Design/CN_Design/Ripple_Carry_Adder/src/ripple_carry_adder.tcl new file mode 100644 index 0000000..3ad3124 --- /dev/null +++ b/Projects/Logic_Design/CN_Design/Ripple_Carry_Adder/src/ripple_carry_adder.tcl @@ -0,0 +1,281 @@ +# Script to create 8-bit ripple carry adder from XUP_LIB components. Set XUP_LIB path below before running +# +# The 8 bit adder is built from two 4-bit carry ripple adders. +# The 4-bit carry ripple adder is built from four full adders. +# The full adder is built from two half adders. +# The hierarchy of the design can be explored by opening or expanding the hierarchical blocks +# +# Vivado 2014.4 +# Basys 3 board +# 1 May 2015 +# CMC +# Notes: Set the path below to the XUP_LIB, and run source ripple_carry__adder.tcl to create the design +# It is assumed the pin constraints xdc file (ripple_carry_adder_basys3_pins.xdc) is in the project directory. +# If the constraints file is located somewhere else, modify the constraints_directory path below +# +# After sourcing this script, run_sim can be executed to drive simulation from proc at bottom of this file +# Once simulation is running (either from the GUI, or from this script) test_pattern can be executed to drive +# simulation input values defined a the bottom of this file +# +# Two 8-bit inputs (operands), a and b, are connected to the dip switches (a sw0-7, b sw 8-15) +# The 8-bit output (s) is connected to LEDs 0-7 +# carry in is connected to the centre pushbutton +# carry out is connected to LED 15 +# -------------------------------------------------------------- # +# SET 'basys3_github' PATH TO GITHUB LIBRARY BEFORE RUNNING +# -------------------------------------------------------------- # +set basys3_github {C:/xup/IPI_LIB/XUP_LIB} + +set project_directory . +set project_name ripple_carry_adder +set constraints_directory $project_directory +set constraints_file ripple_carry_adder_basys3_pins.xdc +set testbench ripple_carry_adder_tb.v +# Create project for Basys 3 +create_project -force $project_name ./$project_name -part xc7a35tcpg236-1 +set_property board_part digilentinc.com:basys3:part0:1.1 [current_project] +set_property target_language verilog [current_project] +set_property simulator_language Verilog [current_project] +set_property ip_repo_paths $basys3_github [current_project] +update_ip_catalog +create_bd_design "$project_name" + +# Steps: +# Build Half Adder +# Copy and add OR gate to make full adders +# Copy full adder 4 times to make 4-bit carry ripple adders +# copy 4-bit adder 2 times to make 8-bit adder + +# Build Half Adder +# create basic gates +create_bd_cell -type ip -vlnv xilinx.com:XUP:xup_xor2:1.0 xor_s +create_bd_cell -type ip -vlnv xilinx.com:XUP:xup_and2:1.0 and_c +# create HA hierarchical block +group_bd_cells half_adder [get_bd_cells xor_s] [get_bd_cells and_c] +# create pins on hierarchy block +create_bd_pin -dir I half_adder/a +create_bd_pin -dir I half_adder/b +create_bd_pin -dir O half_adder/s +create_bd_pin -dir O half_adder/c +# connect internal signals to pins +connect_bd_net [get_bd_pins half_adder/a] [get_bd_pins half_adder/and_c/a] +connect_bd_net [get_bd_pins half_adder/b] [get_bd_pins half_adder/and_c/b] +connect_bd_net [get_bd_pins half_adder/a] [get_bd_pins half_adder/xor_s/a] +connect_bd_net [get_bd_pins half_adder/b] [get_bd_pins half_adder/xor_s/b] +connect_bd_net [get_bd_pins half_adder/c] [get_bd_pins half_adder/and_c/y] +connect_bd_net [get_bd_pins half_adder/s] [get_bd_pins half_adder/xor_s/y] + +# Create Full adder +# copy half_adder +copy_bd_objs / [get_bd_cells {half_adder}] +# add OR gate +create_bd_cell -type ip -vlnv xilinx.com:XUP:xup_or2:1.0 or_carry_out +#create full_adder hierarchical block +group_bd_cells full_adder [get_bd_cells half_adder] [get_bd_cells half_adder1] [get_bd_cells or_carry_out] +# create full adder pins +create_bd_pin -dir I full_adder/a +create_bd_pin -dir I full_adder/b +create_bd_pin -dir I full_adder/c_in +create_bd_pin -dir O full_adder/s +create_bd_pin -dir O full_adder/c_out +# connect full adder nets +connect_bd_net [get_bd_pins full_adder/a] [get_bd_pins full_adder/half_adder/a] +connect_bd_net [get_bd_pins full_adder/b] [get_bd_pins full_adder/half_adder/b] +connect_bd_net [get_bd_pins full_adder/half_adder/s] [get_bd_pins full_adder/half_adder1/a] +connect_bd_net [get_bd_pins full_adder/c_in] [get_bd_pins full_adder/half_adder1/b] +connect_bd_net [get_bd_pins full_adder/half_adder/c] [get_bd_pins full_adder/or_carry_out/a] +connect_bd_net [get_bd_pins full_adder/half_adder1/c] [get_bd_pins full_adder/or_carry_out/b] +connect_bd_net [get_bd_pins full_adder/or_carry_out/y] [get_bd_pins full_adder/c_out] +connect_bd_net [get_bd_pins full_adder/half_adder1/s] [get_bd_pins full_adder/s] +# Create 4-bit carry ripple adder +# Copy and paste full adder +copy_bd_objs / [get_bd_cells {full_adder}] +copy_bd_objs / [get_bd_cells {full_adder}] +copy_bd_objs / [get_bd_cells {full_adder}] +# Connect carrys +connect_bd_net [get_bd_pins full_adder/c_out] [get_bd_pins full_adder1/c_in] -boundary_type upper +connect_bd_net [get_bd_pins full_adder1/c_out] [get_bd_pins full_adder2/c_in] -boundary_type upper +connect_bd_net [get_bd_pins full_adder2/c_out] [get_bd_pins full_adder3/c_in] -boundary_type upper +# create 4-bit carry ripple adder hierarchical block +group_bd_cells ripple_carry_adder_4_bit [get_bd_cells full_adder] [get_bd_cells full_adder1] [get_bd_cells full_adder2] [get_bd_cells full_adder3] +# create hierarchical block pins +create_bd_pin -dir I ripple_carry_adder_4_bit/a0 +create_bd_pin -dir I ripple_carry_adder_4_bit/a1 +create_bd_pin -dir I ripple_carry_adder_4_bit/a2 +create_bd_pin -dir I ripple_carry_adder_4_bit/a3 +create_bd_pin -dir I ripple_carry_adder_4_bit/b0 +create_bd_pin -dir I ripple_carry_adder_4_bit/b1 +create_bd_pin -dir I ripple_carry_adder_4_bit/b2 +create_bd_pin -dir I ripple_carry_adder_4_bit/b3 + +create_bd_pin -dir I ripple_carry_adder_4_bit/c_in + +create_bd_pin -dir O ripple_carry_adder_4_bit/s0 +create_bd_pin -dir O ripple_carry_adder_4_bit/s1 +create_bd_pin -dir O ripple_carry_adder_4_bit/s2 +create_bd_pin -dir O ripple_carry_adder_4_bit/s3 + +create_bd_pin -dir O ripple_carry_adder_4_bit/c_out +# connect pins +connect_bd_net [get_bd_pins ripple_carry_adder_4_bit/a0] [get_bd_pins ripple_carry_adder_4_bit/full_adder/a] +connect_bd_net [get_bd_pins ripple_carry_adder_4_bit/a1] [get_bd_pins ripple_carry_adder_4_bit/full_adder1/a] +connect_bd_net [get_bd_pins ripple_carry_adder_4_bit/a2] [get_bd_pins ripple_carry_adder_4_bit/full_adder2/a] +connect_bd_net [get_bd_pins ripple_carry_adder_4_bit/a3] [get_bd_pins ripple_carry_adder_4_bit/full_adder3/a] + +connect_bd_net [get_bd_pins ripple_carry_adder_4_bit/b0] [get_bd_pins ripple_carry_adder_4_bit/full_adder/b] +connect_bd_net [get_bd_pins ripple_carry_adder_4_bit/b1] [get_bd_pins ripple_carry_adder_4_bit/full_adder1/b] +connect_bd_net [get_bd_pins ripple_carry_adder_4_bit/b2] [get_bd_pins ripple_carry_adder_4_bit/full_adder2/b] +connect_bd_net [get_bd_pins ripple_carry_adder_4_bit/b3] [get_bd_pins ripple_carry_adder_4_bit/full_adder3/b] + +connect_bd_net [get_bd_pins ripple_carry_adder_4_bit/c_in] [get_bd_pins ripple_carry_adder_4_bit/full_adder/c_in] + +connect_bd_net [get_bd_pins ripple_carry_adder_4_bit/s0] [get_bd_pins ripple_carry_adder_4_bit/full_adder/s] +connect_bd_net [get_bd_pins ripple_carry_adder_4_bit/s1] [get_bd_pins ripple_carry_adder_4_bit/full_adder1/s] +connect_bd_net [get_bd_pins ripple_carry_adder_4_bit/s2] [get_bd_pins ripple_carry_adder_4_bit/full_adder2/s] +connect_bd_net [get_bd_pins ripple_carry_adder_4_bit/s3] [get_bd_pins ripple_carry_adder_4_bit/full_adder3/s] + +connect_bd_net [get_bd_pins ripple_carry_adder_4_bit/c_out] [get_bd_pins ripple_carry_adder_4_bit/full_adder3/c_out] + +# Create 8-bit carry ripple adder +copy_bd_objs / [get_bd_cells {ripple_carry_adder_4_bit}] +connect_bd_net [get_bd_pins ripple_carry_adder_4_bit/c_out] [get_bd_pins ripple_carry_adder_4_bit1/c_in] + +#Create top level i/o ports and connect to 4 bit adders +# a +create_bd_port -dir I a0 +connect_bd_net [get_bd_pins /ripple_carry_adder_4_bit/a0] [get_bd_ports a0] +create_bd_port -dir I a1 +connect_bd_net [get_bd_pins /ripple_carry_adder_4_bit/a1] [get_bd_ports a1] +create_bd_port -dir I a2 +connect_bd_net [get_bd_pins /ripple_carry_adder_4_bit/a2] [get_bd_ports a2] +create_bd_port -dir I a3 +connect_bd_net [get_bd_pins /ripple_carry_adder_4_bit/a3] [get_bd_ports a3] +create_bd_port -dir I a4 +connect_bd_net [get_bd_pins /ripple_carry_adder_4_bit1/a0] [get_bd_ports a4] +create_bd_port -dir I a5 +connect_bd_net [get_bd_pins /ripple_carry_adder_4_bit1/a1] [get_bd_ports a5] +create_bd_port -dir I a6 +connect_bd_net [get_bd_pins /ripple_carry_adder_4_bit1/a2] [get_bd_ports a6] +create_bd_port -dir I a7 +connect_bd_net [get_bd_pins /ripple_carry_adder_4_bit1/a3] [get_bd_ports a7] +# b +create_bd_port -dir I b0 +connect_bd_net [get_bd_pins /ripple_carry_adder_4_bit/b0] [get_bd_ports b0] +create_bd_port -dir I b2 +connect_bd_net [get_bd_pins /ripple_carry_adder_4_bit/b2] [get_bd_ports b2] +create_bd_port -dir I b1 +connect_bd_net [get_bd_pins /ripple_carry_adder_4_bit/b1] [get_bd_ports b1] +create_bd_port -dir I b3 +connect_bd_net [get_bd_pins /ripple_carry_adder_4_bit/b3] [get_bd_ports b3] +create_bd_port -dir I b4 +connect_bd_net [get_bd_pins /ripple_carry_adder_4_bit1/b0] [get_bd_ports b4] +create_bd_port -dir I b5 +connect_bd_net [get_bd_pins /ripple_carry_adder_4_bit1/b1] [get_bd_ports b5] +create_bd_port -dir I b6 +connect_bd_net [get_bd_pins /ripple_carry_adder_4_bit1/b2] [get_bd_ports b6] +create_bd_port -dir I b7 +connect_bd_net [get_bd_pins /ripple_carry_adder_4_bit1/b3] [get_bd_ports b7] +create_bd_port -dir O s0 +# carry in +create_bd_port -dir I c_in +connect_bd_net [get_bd_pins /ripple_carry_adder_4_bit/c_in] [get_bd_ports c_in] +# outputs +connect_bd_net [get_bd_pins /ripple_carry_adder_4_bit/s0] [get_bd_ports s0] +create_bd_port -dir O s1 +connect_bd_net [get_bd_pins /ripple_carry_adder_4_bit/s1] [get_bd_ports s1] +create_bd_port -dir O s2 +connect_bd_net [get_bd_pins /ripple_carry_adder_4_bit/s2] [get_bd_ports s2] +create_bd_port -dir O s3 +connect_bd_net [get_bd_pins /ripple_carry_adder_4_bit/s3] [get_bd_ports s3] +create_bd_port -dir O s4 +connect_bd_net [get_bd_pins /ripple_carry_adder_4_bit1/s0] [get_bd_ports s4] +create_bd_port -dir O s5 +connect_bd_net [get_bd_pins /ripple_carry_adder_4_bit1/s1] [get_bd_ports s5] +create_bd_port -dir O s6 +connect_bd_net [get_bd_pins /ripple_carry_adder_4_bit1/s2] [get_bd_ports s6] +create_bd_port -dir O s7 +connect_bd_net [get_bd_pins /ripple_carry_adder_4_bit1/s3] [get_bd_ports s7] +# carry out +create_bd_port -dir O c_out +connect_bd_net [get_bd_pins /ripple_carry_adder_4_bit1/c_out] [get_bd_ports c_out] + +regenerate_bd_layout +save_bd_design + +# Create top HDL wrapper +make_wrapper -files [get_files $project_directory/$project_name/$project_name.srcs/sources_1/bd/$project_name/$project_name.bd] -top +add_files -norecurse $project_directory/$project_name/$project_name.srcs/sources_1/bd/$project_name/hdl/$project_name\_wrapper.v +# Add pin constraints +add_files -fileset constrs_1 -norecurse $constraints_directory/$constraints_file +set_property -name {xsim.simulate.runtime} -value {0} -objects [current_fileset -simset] +# Add test bench +add_files -fileset sim_1 -norecurse $project_directory/$testbench +set_property -name {xsim.simulate.runtime} -value {500 ns} -objects [current_fileset -simset] + + +# run simulation with some sample test vectors +proc run_sim {} { +#check if simulation is already open +set sim_value [current_sim] +if {$sim_value != "" } { +puts "Close existing Simulation" +close_sim +} +set_property -name {xsim.simulate.xsim.more_options} -value {-view ../../../../ripple_carry_adder_tb_behav.wcfg} -objects [current_fileset -simset] +set_property -name {xsim.simulate.runtime} -value {0 ns} -objects [current_fileset -simset] +launch_simulation + + +# Set initial input values +add_force {/ripple_carry_adder_tb/a} -radix unsigned {0 0ns} +add_force {/ripple_carry_adder_tb/b} -radix unsigned {0 0ns} +add_force {/ripple_carry_adder_tb/c_in} -radix unsigned {0 0ns} + +test_pattern + +} + +# run simulation with some sample test vectors +proc test_pattern {} { + +add_force {/ripple_carry_adder_tb/c_in} -radix unsigned {0 0ns} + +add_force {/ripple_carry_adder_tb/a} -radix unsigned {0 0ns} +add_force {/ripple_carry_adder_tb/b} -radix unsigned {0 0ns} +run 50 ns + +add_force {/ripple_carry_adder_tb/a} -radix unsigned {5 0ns} +add_force {/ripple_carry_adder_tb/b} -radix unsigned {3 0ns} +run 50 ns + +add_force {/ripple_carry_adder_tb/a} -radix unsigned {2 0ns} +add_force {/ripple_carry_adder_tb/b} -radix unsigned {7 0ns} +run 50 ns + +# set carry in +add_force {/ripple_carry_adder_tb/a} -radix unsigned {10 0ns} +add_force {/ripple_carry_adder_tb/b} -radix unsigned {4 0ns} +add_force {/ripple_carry_adder_tb/c_in} -radix unsigned {1 0ns} +run 50 ns + +add_force {/ripple_carry_adder_tb/a} -radix unsigned {128 0ns} +add_force {/ripple_carry_adder_tb/b} -radix unsigned {56 0ns} +run 50 ns + +add_force {/ripple_carry_adder_tb/a} -radix unsigned {140 0ns} +add_force {/ripple_carry_adder_tb/b} -radix unsigned {150 0ns} +run 50 ns + +add_force {/ripple_carry_adder_tb/c_in} -radix unsigned {0 0ns} +add_force {/ripple_carry_adder_tb/a} -radix unsigned {200 0ns} +add_force {/ripple_carry_adder_tb/b} -radix unsigned {150 0ns} +run 50 ns + +# reset input values +add_force {/ripple_carry_adder_tb/a} -radix unsigned {0 0ns} +add_force {/ripple_carry_adder_tb/b} -radix unsigned {0 0ns} +add_force {/ripple_carry_adder_tb/c_in} -radix unsigned {0 0ns} + + +} + diff --git a/Projects/Logic_Design/CN_Design/Ripple_Carry_Adder/src/ripple_carry_adder_basys3_pins.xdc b/Projects/Logic_Design/CN_Design/Ripple_Carry_Adder/src/ripple_carry_adder_basys3_pins.xdc new file mode 100644 index 0000000..ba89f20 --- /dev/null +++ b/Projects/Logic_Design/CN_Design/Ripple_Carry_Adder/src/ripple_carry_adder_basys3_pins.xdc @@ -0,0 +1,59 @@ +#Pin constraints for XUPLIB 8 bit ripple carry adder design for Basys 3 +## Switches +set_property PACKAGE_PIN V17 [get_ports {a0}] + set_property IOSTANDARD LVCMOS33 [get_ports {a0}] +set_property PACKAGE_PIN V16 [get_ports {a1}] + set_property IOSTANDARD LVCMOS33 [get_ports {a1}] +set_property PACKAGE_PIN W16 [get_ports {a2}] + set_property IOSTANDARD LVCMOS33 [get_ports {a2}] +set_property PACKAGE_PIN W17 [get_ports {a3}] + set_property IOSTANDARD LVCMOS33 [get_ports {a3}] +set_property PACKAGE_PIN W15 [get_ports {a4}] + set_property IOSTANDARD LVCMOS33 [get_ports {a4}] +set_property PACKAGE_PIN V15 [get_ports {a5}] + set_property IOSTANDARD LVCMOS33 [get_ports {a5}] +set_property PACKAGE_PIN W14 [get_ports {a6}] + set_property IOSTANDARD LVCMOS33 [get_ports {a6}] +set_property PACKAGE_PIN W13 [get_ports {a7}] + set_property IOSTANDARD LVCMOS33 [get_ports {a7}] +set_property PACKAGE_PIN V2 [get_ports {b0}] + set_property IOSTANDARD LVCMOS33 [get_ports {b0}] +set_property PACKAGE_PIN T3 [get_ports {b1}] + set_property IOSTANDARD LVCMOS33 [get_ports {b1}] +set_property PACKAGE_PIN T2 [get_ports {b2}] + set_property IOSTANDARD LVCMOS33 [get_ports {b2}] +set_property PACKAGE_PIN R3 [get_ports {b3}] + set_property IOSTANDARD LVCMOS33 [get_ports {b3}] +set_property PACKAGE_PIN W2 [get_ports {b4}] + set_property IOSTANDARD LVCMOS33 [get_ports {b4}] +set_property PACKAGE_PIN U1 [get_ports {b5}] + set_property IOSTANDARD LVCMOS33 [get_ports {b5}] +set_property PACKAGE_PIN T1 [get_ports {b6}] + set_property IOSTANDARD LVCMOS33 [get_ports {b6}] +set_property PACKAGE_PIN R2 [get_ports {b7}] + set_property IOSTANDARD LVCMOS33 [get_ports {b7}] + +# pushbutton C +set_property PACKAGE_PIN U18 [get_ports {c_in}] + set_property IOSTANDARD LVCMOS33 [get_ports {c_in}] + +# LEDs +set_property PACKAGE_PIN U16 [get_ports {s0}] + set_property IOSTANDARD LVCMOS33 [get_ports {s0}] +set_property PACKAGE_PIN E19 [get_ports {s1}] + set_property IOSTANDARD LVCMOS33 [get_ports {s1}] +set_property PACKAGE_PIN U19 [get_ports {s2}] + set_property IOSTANDARD LVCMOS33 [get_ports {s2}] +set_property PACKAGE_PIN V19 [get_ports {s3}] + set_property IOSTANDARD LVCMOS33 [get_ports {s3}] +set_property PACKAGE_PIN W18 [get_ports {s4}] + set_property IOSTANDARD LVCMOS33 [get_ports {s4}] +set_property PACKAGE_PIN U15 [get_ports {s5}] + set_property IOSTANDARD LVCMOS33 [get_ports {s5}] +set_property PACKAGE_PIN U14 [get_ports {s6}] + set_property IOSTANDARD LVCMOS33 [get_ports {s6}] +set_property PACKAGE_PIN V14 [get_ports {s7}] + set_property IOSTANDARD LVCMOS33 [get_ports {s7}] +# LED 15 +set_property PACKAGE_PIN L1 [get_ports {c_out}] + set_property IOSTANDARD LVCMOS33 [get_ports {c_out}] diff --git a/Projects/Logic_Design/CN_Design/Ripple_Carry_Adder/src/ripple_carry_adder_tb.v b/Projects/Logic_Design/CN_Design/Ripple_Carry_Adder/src/ripple_carry_adder_tb.v new file mode 100644 index 0000000..5bd5348 --- /dev/null +++ b/Projects/Logic_Design/CN_Design/Ripple_Carry_Adder/src/ripple_carry_adder_tb.v @@ -0,0 +1,66 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Module Name: ripple_carry_adder_tb +// Description: Testbench for ripple_carry_adder +////////////////////////////////////////////////////////////////////////////////// + + +module ripple_carry_adder_tb( + ); + + reg [7:0] a, b; + reg c_in; + wire [7:0] s; + wire c_out; + + ripple_carry_adder_wrapper DUT (.a0(a[0]), .a1(a[1]), .a2(a[2]), .a3(a[3]), .a4(a[4]), .a5(a[5]), .a6(a[6]), .a7(a[7]), + .b0(b[0]), .b1(b[1]), .b2(b[2]), .b3(b[3]), .b4(b[4]), .b5(b[5]), .b6(b[6]), .b7(b[7]), .c_in(c_in), + .s0(s[0]), .s1(s[1]), .s2(s[2]), .s3(s[3]), .s4(s[4]), .s5(s[5]), .s6(s[6]), .s7(s[7]), .c_out(c_out) + ); + + initial + begin + a = 8'h0; + b = 8'h0; + c_in = 1'b0; + #50; + a = 8'h0; + b = 8'h2; + c_in = 1'b0; + #50; + a = 8'h1; + b = 8'h9; + c_in = 1'b0; + #50; + a = 8'h4; + b = 8'h40; + c_in = 1'b0; + #50; + a = 8'h11; + b = 8'h11; + c_in = 1'b1; + #50; + a = 8'h23; + b = 8'h29; + c_in = 1'b0; + #50; + a = 8'h45; + b = 8'h42; + c_in = 1'b1; + #50; + a = 8'h89; + b = 8'h94; + c_in = 1'b0; + #50; + a = 8'hc1; + b = 8'hc8; + c_in = 1'b1; + #50; + a = 8'he1; + b = 8'he2; + c_in = 1'b0; + #50; + $stop; + end + +endmodule diff --git a/Projects/Logic_Design/CN_Design/Ripple_Carry_Adder/src/ripple_carry_adder_tb_behav.wcfg b/Projects/Logic_Design/CN_Design/Ripple_Carry_Adder/src/ripple_carry_adder_tb_behav.wcfg new file mode 100644 index 0000000..2f314e3 --- /dev/null +++ b/Projects/Logic_Design/CN_Design/Ripple_Carry_Adder/src/ripple_carry_adder_tb_behav.wcfg @@ -0,0 +1,37 @@ + + + + + + + + + + + + + + + a[7:0] + a[7:0] + HEXRADIX + + + b[7:0] + b[7:0] + HEXRADIX + + + s[7:0] + s[7:0] + HEXRADIX + + + c_in + c_in + + + c_out + c_out + + diff --git a/Projects/Logic_Design/CN_Design/array_multiplier/README.md b/Projects/Logic_Design/CN_Design/array_multiplier/README.md new file mode 100644 index 0000000..94349f2 --- /dev/null +++ b/Projects/Logic_Design/CN_Design/array_multiplier/README.md @@ -0,0 +1,54 @@ +# Array Multiplier +This project creates an 8-bit x8-bit Array Multiplier using XUP_LIB components. You must download the XUP_LIB directory from the GitHub and then set the XUP_LIB path. You must also download the Basys3 board files directory from the GitHub and place it in the **\\2014.4\data\boards\board_parts\artix7** directory. + +The project source files include a Tcl script, Xilinx Design Constraint (xdc) file targeting Basys3 board, verilog testbench, and a wave configuration (wcfg) file. + +### Design Description: +This is a 8x8 bit array multiplier, with 16-bit output. The multiplier is built from AND gates, half adders, and full adders. +The hierarchy of the design can be explored by opening or expanding the hierarchical blocks + +### Tools and requirements: +* Vivado 2014.4 +* XUP_LIB from GitHub +* Basys3 board files from GitHub + +### Procedure: +Execute the commands **in bold** in the tcl console + +1\. Start Vivado + +2\. At the tcl command line, set a variable *basys3_github* to the XUP_LIB path. Note the path uses "/" instead of "\". Substitute the path to where you have saved the XUP_LIB library: + +**set basys3_github {C:/xup/IPI_LIB/XUP_LIB}** + +3\. Change to the *src* directory of this project using the *cd* command: + +**cd \** + +4\. Execute the following command to run the script: + +**source ./array_multiplier.tcl** + +5\. Once the project is created, the resulting block diagram will be displayed. View the block diagram, double click or expand blocks to navigate the hierarchy and analyze the design +6\. Execute the following command to run the behavioural simulation: + +**run_sim** + +7\. Analyze the results and notice the output transitioning after the input changes. When satisfied, close the simulator: + +**close_sim** + +8\. Generate the bitstream by clicking on the *Generate Bitstream* under the *Program and Debug* group + +9\. When the bitstream generation is completed, connect the board, power ON the board, and use the *Open Hardware Manager* option to connect to the board + +10\. *Program* the board and verify the functionality + +Input 1 : Dipswitches 0-7 + +Input 2 : Dipswitches 8-15 + +Result : Leds 0-15 + + + diff --git a/Projects/Logic_Design/CN_Design/array_multiplier/src/array_multiplier.tcl b/Projects/Logic_Design/CN_Design/array_multiplier/src/array_multiplier.tcl new file mode 100644 index 0000000..55a05e8 --- /dev/null +++ b/Projects/Logic_Design/CN_Design/array_multiplier/src/array_multiplier.tcl @@ -0,0 +1,552 @@ +# Script to create an 8x8 bit array multiplier using XUP_LIB components. +# Set XUP_LIB path below before running +# +# Vivado 2014.4 +# Basys 3 board +# 10 June 2015 +# CMC +# Notes: Set the path below to the XUP_LIB, and run source .tcl to create the design +# It is assumed the pin constraints xdc file (array_multiplier_basys3_pins.xdc) is in the project directory. +# If the constraints file is located somewhere else, modify the constraints_directory path below +# +# After sourcing this script, and building the project in Vivado, run_sim can be executed to run a simulation +# +# -------------------------------------------------------------- # +# SET 'basys3_github' PATH TO GITHUB LIBRARY BEFORE RUNNING +# -------------------------------------------------------------- # +set basys3_github {C:/xup/IPI_LIB/} + +set project_directory . +set project_name array_multiplier +set constraints_directory $project_directory +set constraints_file array_multiplier_basys3_pins.xdc +set testbench array_multiplier_tb.v +# Create project for Basys 3 +create_project -force $project_name ./$project_name -part xc7a35tcpg236-1 +set_property board_part digilentinc.com:basys3:part0:1.1 [current_project] +set_property target_language verilog [current_project] +set_property simulator_language Verilog [current_project] +set_property ip_repo_paths $basys3_github [current_project] +update_ip_catalog +create_bd_design "$project_name" + +# Steps: +# 1. Create the IO ports +# 2. Create a half adder +# 3. Create a full adder +# 4. create the first array of AND gates +# 5. Using the previously created blocks, create the first row of half/full adders for the array multiplier +# 6. After row 0 and row 1 has been connected, steps 4 and 5 to build the rest of the array +# 7. The design is grouped into hierarchies to make it easier to view and navigate +# Each HA/FA block is grouped with its AND gate(s) e.g. r_0_0, r0_1 etc +# Each block is grouped into a row. e.g. r0_(0 - 7) -> r0 + +# Note, in Row 0, block 0, and block 7 are half adders (and blocks 1-6 are full adders) +# In Rows 1 -> 7, block 0 is a half adder, but blocks 1 - 7 are full adders (block 7 is no longer a half adder) +# e.g. +# IO R0 R1 R2 R3 R4 R5 R6 R7 +# HA HA HA HA HA HA HA HA +# FA FA FA FA FA FA FA FA +# FA FA FA FA FA FA FA FA +# FA FA FA FA FA FA FA FA +# FA FA FA FA FA FA FA FA +# FA FA FA FA FA FA FA FA +# FA FA FA FA FA FA FA FA +# FA FA FA FA FA FA FA FA +# HA FA FA FA FA FA FA FA +# As Row 0 contains a HA at the end of the row instead of a FA, the connection of row 0 to row 1 is different to the connecting of all other rows. +# Once row 0 has been connected to row 1, the connection of all the other rows is the same and is carried out in the loop below. + + +# Create IO ports + +create_bd_port -dir I a0 +#connect_bd_net [get_bd_pins /carry_save_adder_4_bit/z0] [get_bd_ports z0] +create_bd_port -dir I a1 +#connect_bd_net [get_bd_pins /carry_save_adder_4_bit/z1] [get_bd_ports z1] +create_bd_port -dir I a2 +#connect_bd_net [get_bd_pins /carry_save_adder_4_bit/z2] [get_bd_ports z2] +create_bd_port -dir I a3 +#connect_bd_net [get_bd_pins /carry_save_adder_4_bit/z3] [get_bd_ports z3] +create_bd_port -dir I a4 +#connect_bd_net [get_bd_pins /carry_save_adder_4_bit/z0] [get_bd_ports z0] +create_bd_port -dir I a5 +#connect_bd_net [get_bd_pins /carry_save_adder_4_bit/z1] [get_bd_ports z1] +create_bd_port -dir I a6 +#connect_bd_net [get_bd_pins /carry_save_adder_4_bit/z2] [get_bd_ports z2] +create_bd_port -dir I a7 +#connect_bd_net [get_bd_pins /carry_save_adder_4_bit/z3] [get_bd_ports z3] + +create_bd_port -dir I b0 +#connect_bd_net [get_bd_pins /carry_save_adder_4_bit/z0] [get_bd_ports z0] +create_bd_port -dir I b1 +#connect_bd_net [get_bd_pins /carry_save_adder_4_bit/z1] [get_bd_ports z1] +create_bd_port -dir I b2 +#connect_bd_net [get_bd_pins /carry_save_adder_4_bit/z2] [get_bd_ports z2] +create_bd_port -dir I b3 +#connect_bd_net [get_bd_pins /carry_save_adder_4_bit/z3] [get_bd_ports z3] +create_bd_port -dir I b4 +#connect_bd_net [get_bd_pins /carry_save_adder_4_bit/z0] [get_bd_ports z0] +create_bd_port -dir I b5 +#connect_bd_net [get_bd_pins /carry_save_adder_4_bit/z1] [get_bd_ports z1] +create_bd_port -dir I b6 +#connect_bd_net [get_bd_pins /carry_save_adder_4_bit/z2] [get_bd_ports z2] +create_bd_port -dir I b7 +#connect_bd_net [get_bd_pins /carry_save_adder_4_bit/z3] [get_bd_ports z3] + +create_bd_port -dir O s0 +#connect_bd_net [get_bd_pins /carry_save_adder_4_bit1/s0] [get_bd_ports s0] +create_bd_port -dir O s1 +#connect_bd_net [get_bd_pins /ripple_carry_adder_8_bit/o0] [get_bd_ports s1] +create_bd_port -dir O s2 +#connect_bd_net [get_bd_pins /ripple_carry_adder_8_bit/o1] [get_bd_ports s2] +create_bd_port -dir O s3 +#connect_bd_net [get_bd_pins /ripple_carry_adder_8_bit/o2] [get_bd_ports s3] +create_bd_port -dir O s4 +#connect_bd_net [get_bd_pins /ripple_carry_adder_8_bit/o3] [get_bd_ports s4] +create_bd_port -dir O s5 +#connect_bd_net [get_bd_pins /ripple_carry_adder_8_bit/o4] [get_bd_ports s5] +create_bd_port -dir O s6 +#connect_bd_net [get_bd_pins /ripple_carry_adder_8_bit/o4] [get_bd_ports s5] +create_bd_port -dir O s7 +#connect_bd_net [get_bd_pins /ripple_carry_adder_8_bit/o4] [get_bd_ports s5] +create_bd_port -dir O s8 +#connect_bd_net [get_bd_pins /carry_save_adder_4_bit1/s0] [get_bd_ports s0] +create_bd_port -dir O s9 +#connect_bd_net [get_bd_pins /ripple_carry_adder_8_bit/o0] [get_bd_ports s1] +create_bd_port -dir O s10 +#connect_bd_net [get_bd_pins /ripple_carry_adder_8_bit/o1] [get_bd_ports s2] +create_bd_port -dir O s11 +#connect_bd_net [get_bd_pins /ripple_carry_adder_8_bit/o2] [get_bd_ports s3] +create_bd_port -dir O s12 +#connect_bd_net [get_bd_pins /ripple_carry_adder_8_bit/o3] [get_bd_ports s4] +create_bd_port -dir O s13 +#connect_bd_net [get_bd_pins /ripple_carry_adder_8_bit/o4] [get_bd_ports s5] +create_bd_port -dir O s14 +#connect_bd_net [get_bd_pins /ripple_carry_adder_8_bit/o4] [get_bd_ports s5] +create_bd_port -dir O s15 +#connect_bd_net [get_bd_pins /ripple_carry_adder_8_bit/o4] [get_bd_ports s5] + +# Build Half Adder +# create basic gates +create_bd_cell -type ip -vlnv xilinx.com:XUP:xup_xor2:1.0 xor_s +create_bd_cell -type ip -vlnv xilinx.com:XUP:xup_and2:1.0 and_c +# create HA hierarchical block +group_bd_cells half_adder [get_bd_cells xor_s] [get_bd_cells and_c] +# create pins on hierarchy block +create_bd_pin -dir I half_adder/a +create_bd_pin -dir I half_adder/b +create_bd_pin -dir O half_adder/s +create_bd_pin -dir O half_adder/c +# connect internal signals to pins +connect_bd_net [get_bd_pins half_adder/a] [get_bd_pins half_adder/and_c/a] +connect_bd_net [get_bd_pins half_adder/b] [get_bd_pins half_adder/and_c/b] +connect_bd_net [get_bd_pins half_adder/a] [get_bd_pins half_adder/xor_s/a] +connect_bd_net [get_bd_pins half_adder/b] [get_bd_pins half_adder/xor_s/b] +connect_bd_net [get_bd_pins half_adder/c] [get_bd_pins half_adder/and_c/y] +connect_bd_net [get_bd_pins half_adder/s] [get_bd_pins half_adder/xor_s/y] + +# 2 half_adders will be used in the full adder. +# copy half_adder for use in the full adder. This creates half_adder1. +copy_bd_objs / [get_bd_cells {half_adder}] +# Make another copy of the half_adder for use later. This creates half_adder2. +copy_bd_objs / [get_bd_cells {half_adder}] + +# Create Full adder +# add OR gate +create_bd_cell -type ip -vlnv xilinx.com:XUP:xup_or2:1.0 or_carry_out +#create full_adder hierarchical block (use original half_adder, and newly copied half_adder1) +group_bd_cells full_adder [get_bd_cells half_adder] [get_bd_cells half_adder1] [get_bd_cells or_carry_out] +# create full adder pins +create_bd_pin -dir I full_adder/a +create_bd_pin -dir I full_adder/b +create_bd_pin -dir I full_adder/c_in +create_bd_pin -dir O full_adder/s +create_bd_pin -dir O full_adder/c_out +# connect full adder nets +connect_bd_net [get_bd_pins full_adder/a] [get_bd_pins full_adder/half_adder/a] +connect_bd_net [get_bd_pins full_adder/b] [get_bd_pins full_adder/half_adder/b] +connect_bd_net [get_bd_pins full_adder/half_adder/s] [get_bd_pins full_adder/half_adder1/a] +connect_bd_net [get_bd_pins full_adder/c_in] [get_bd_pins full_adder/half_adder1/b] +connect_bd_net [get_bd_pins full_adder/half_adder/c] [get_bd_pins full_adder/or_carry_out/a] +connect_bd_net [get_bd_pins full_adder/half_adder1/c] [get_bd_pins full_adder/or_carry_out/b] +connect_bd_net [get_bd_pins full_adder/or_carry_out/y] [get_bd_pins full_adder/c_out] +connect_bd_net [get_bd_pins full_adder/half_adder1/s] [get_bd_pins full_adder/s] + +# Original half_adder is now inside the full_adder block. Rename half_adder2 back to half_adder +set_property name half_adder [get_bd_cells half_adder2] + +# ##################################################################### +# Start creating the Array multiplier +# +# The naming of the AND gate (e.g. xup_and2_a0_b0) indicates which +# inputs should be connected +# For the adder array, r{X}, X indicates the row (0->7) +# e.g. full_adder_r0_5 is the 5th block in row 0 +# ##################################################################### +# Create AND a(x)_b(0->7) +create_bd_cell -type ip -vlnv xilinx.com:XUP:xup_and2:1.0 xup_and2_a0_b0 +create_bd_cell -type ip -vlnv xilinx.com:XUP:xup_and2:1.0 xup_and2_a0_b1 +create_bd_cell -type ip -vlnv xilinx.com:XUP:xup_and2:1.0 xup_and2_a0_b2 +create_bd_cell -type ip -vlnv xilinx.com:XUP:xup_and2:1.0 xup_and2_a0_b3 +create_bd_cell -type ip -vlnv xilinx.com:XUP:xup_and2:1.0 xup_and2_a0_b4 +create_bd_cell -type ip -vlnv xilinx.com:XUP:xup_and2:1.0 xup_and2_a0_b5 +create_bd_cell -type ip -vlnv xilinx.com:XUP:xup_and2:1.0 xup_and2_a0_b6 +create_bd_cell -type ip -vlnv xilinx.com:XUP:xup_and2:1.0 xup_and2_a0_b7 +# Create FA/HA +copy_bd_objs / [get_bd_cells {half_adder}] +set_property name half_adder_r0_0 [get_bd_cells half_adder1] +copy_bd_objs / [get_bd_cells {full_adder}] +set_property name full_adder_r0_1 [get_bd_cells full_adder1] +copy_bd_objs / [get_bd_cells {full_adder}] +set_property name full_adder_r0_2 [get_bd_cells full_adder1] +copy_bd_objs / [get_bd_cells {full_adder}] +set_property name full_adder_r0_3 [get_bd_cells full_adder1] +copy_bd_objs / [get_bd_cells {full_adder}] +set_property name full_adder_r0_4 [get_bd_cells full_adder1] +copy_bd_objs / [get_bd_cells {full_adder}] +set_property name full_adder_r0_5 [get_bd_cells full_adder1] +copy_bd_objs / [get_bd_cells {full_adder}] +set_property name full_adder_r0_6 [get_bd_cells full_adder1] +copy_bd_objs / [get_bd_cells {half_adder}] +set_property name half_adder_r0_7 [get_bd_cells half_adder1] +# Connect a(x) to AND +connect_bd_net [get_bd_ports a0] [get_bd_pins xup_and2_a0_b0/a] +connect_bd_net -net [get_bd_nets a0_1] [get_bd_ports a0] [get_bd_pins xup_and2_a0_b1/a] +connect_bd_net -net [get_bd_nets a0_1] [get_bd_ports a0] [get_bd_pins xup_and2_a0_b2/a] +connect_bd_net -net [get_bd_nets a0_1] [get_bd_ports a0] [get_bd_pins xup_and2_a0_b3/a] +connect_bd_net -net [get_bd_nets a0_1] [get_bd_ports a0] [get_bd_pins xup_and2_a0_b4/a] +connect_bd_net -net [get_bd_nets a0_1] [get_bd_ports a0] [get_bd_pins xup_and2_a0_b5/a] +connect_bd_net -net [get_bd_nets a0_1] [get_bd_ports a0] [get_bd_pins xup_and2_a0_b6/a] +connect_bd_net -net [get_bd_nets a0_1] [get_bd_ports a0] [get_bd_pins xup_and2_a0_b7/a] +# connect b(0->7) to AND +connect_bd_net [get_bd_ports b0] [get_bd_pins xup_and2_a0_b0/b] +connect_bd_net [get_bd_ports b1] [get_bd_pins xup_and2_a0_b1/b] +connect_bd_net [get_bd_ports b2] [get_bd_pins xup_and2_a0_b2/b] +connect_bd_net [get_bd_ports b3] [get_bd_pins xup_and2_a0_b3/b] +connect_bd_net [get_bd_ports b4] [get_bd_pins xup_and2_a0_b4/b] +connect_bd_net [get_bd_ports b5] [get_bd_pins xup_and2_a0_b5/b] +connect_bd_net [get_bd_ports b6] [get_bd_pins xup_and2_a0_b6/b] +connect_bd_net [get_bd_ports b7] [get_bd_pins xup_and2_a0_b7/b] +# Connect s(x) to and_x_0 +connect_bd_net [get_bd_ports s0] [get_bd_pins xup_and2_a0_b0/y] +# Connect to HA/FA +connect_bd_net [get_bd_pins xup_and2_a0_b1/y] [get_bd_pins half_adder_r0_0/a] +connect_bd_net [get_bd_pins xup_and2_a0_b2/y] [get_bd_pins full_adder_r0_1/a] +connect_bd_net [get_bd_pins xup_and2_a0_b3/y] [get_bd_pins full_adder_r0_2/a] +connect_bd_net [get_bd_pins xup_and2_a0_b4/y] [get_bd_pins full_adder_r0_3/a] +connect_bd_net [get_bd_pins xup_and2_a0_b5/y] [get_bd_pins full_adder_r0_4/a] +connect_bd_net [get_bd_pins xup_and2_a0_b6/y] [get_bd_pins full_adder_r0_5/a] +connect_bd_net [get_bd_pins xup_and2_a0_b7/y] [get_bd_pins full_adder_r0_6/a] +# Create AND (X) +create_bd_cell -type ip -vlnv xilinx.com:XUP:xup_and2:1.0 xup_and2_a1_b0 +create_bd_cell -type ip -vlnv xilinx.com:XUP:xup_and2:1.0 xup_and2_a1_b1 +create_bd_cell -type ip -vlnv xilinx.com:XUP:xup_and2:1.0 xup_and2_a1_b2 +create_bd_cell -type ip -vlnv xilinx.com:XUP:xup_and2:1.0 xup_and2_a1_b3 +create_bd_cell -type ip -vlnv xilinx.com:XUP:xup_and2:1.0 xup_and2_a1_b4 +create_bd_cell -type ip -vlnv xilinx.com:XUP:xup_and2:1.0 xup_and2_a1_b5 +create_bd_cell -type ip -vlnv xilinx.com:XUP:xup_and2:1.0 xup_and2_a1_b6 +create_bd_cell -type ip -vlnv xilinx.com:XUP:xup_and2:1.0 xup_and2_a1_b7 +#Connect a(x) to AND +connect_bd_net [get_bd_ports a1] [get_bd_pins xup_and2_a1_b0/a] +connect_bd_net -net [get_bd_nets a1_1] [get_bd_ports a1] [get_bd_pins xup_and2_a1_b1/a] +connect_bd_net -net [get_bd_nets a1_1] [get_bd_ports a1] [get_bd_pins xup_and2_a1_b2/a] +connect_bd_net -net [get_bd_nets a1_1] [get_bd_ports a1] [get_bd_pins xup_and2_a1_b3/a] +connect_bd_net -net [get_bd_nets a1_1] [get_bd_ports a1] [get_bd_pins xup_and2_a1_b4/a] +connect_bd_net -net [get_bd_nets a1_1] [get_bd_ports a1] [get_bd_pins xup_and2_a1_b5/a] +connect_bd_net -net [get_bd_nets a1_1] [get_bd_ports a1] [get_bd_pins xup_and2_a1_b6/a] +connect_bd_net -net [get_bd_nets a1_1] [get_bd_ports a1] [get_bd_pins xup_and2_a1_b7/a] +# connect b(0->7) to AND +connect_bd_net [get_bd_ports b0] [get_bd_pins xup_and2_a1_b0/b] +connect_bd_net [get_bd_ports b1] [get_bd_pins xup_and2_a1_b1/b] +connect_bd_net [get_bd_ports b2] [get_bd_pins xup_and2_a1_b2/b] +connect_bd_net [get_bd_ports b3] [get_bd_pins xup_and2_a1_b3/b] +connect_bd_net [get_bd_ports b4] [get_bd_pins xup_and2_a1_b4/b] +connect_bd_net [get_bd_ports b5] [get_bd_pins xup_and2_a1_b5/b] +connect_bd_net [get_bd_ports b6] [get_bd_pins xup_and2_a1_b6/b] +connect_bd_net [get_bd_ports b7] [get_bd_pins xup_and2_a1_b7/b] +# Connect to HA/FA +connect_bd_net [get_bd_pins xup_and2_a1_b0/y] [get_bd_pins half_adder_r0_0/b] +connect_bd_net [get_bd_pins xup_and2_a1_b1/y] [get_bd_pins full_adder_r0_1/b] +connect_bd_net [get_bd_pins xup_and2_a1_b2/y] [get_bd_pins full_adder_r0_2/b] +connect_bd_net [get_bd_pins xup_and2_a1_b3/y] [get_bd_pins full_adder_r0_3/b] +connect_bd_net [get_bd_pins xup_and2_a1_b4/y] [get_bd_pins full_adder_r0_4/b] +connect_bd_net [get_bd_pins xup_and2_a1_b5/y] [get_bd_pins full_adder_r0_5/b] +connect_bd_net [get_bd_pins xup_and2_a1_b6/y] [get_bd_pins full_adder_r0_6/b] +connect_bd_net [get_bd_pins xup_and2_a1_b7/y] [get_bd_pins half_adder_r0_7/b] +# Connect carries +connect_bd_net [get_bd_pins half_adder_r0_0/c] [get_bd_pins full_adder_r0_1/c_in] -boundary_type upper +connect_bd_net [get_bd_pins full_adder_r0_1/c_out] [get_bd_pins full_adder_r0_2/c_in] -boundary_type upper +connect_bd_net [get_bd_pins full_adder_r0_2/c_out] [get_bd_pins full_adder_r0_3/c_in] -boundary_type upper +connect_bd_net [get_bd_pins full_adder_r0_3/c_out] [get_bd_pins full_adder_r0_4/c_in] -boundary_type upper +connect_bd_net [get_bd_pins full_adder_r0_4/c_out] [get_bd_pins full_adder_r0_5/c_in] -boundary_type upper +connect_bd_net [get_bd_pins full_adder_r0_5/c_out] [get_bd_pins full_adder_r0_6/c_in] -boundary_type upper +connect_bd_net [get_bd_pins full_adder_r0_6/c_out] [get_bd_pins half_adder_r0_7/a] -boundary_type upper +# Connect half_adder to s(x) +connect_bd_net [get_bd_ports s1] [get_bd_pins half_adder_r0_0/s] +# ################################# + +# Row 1 +# (As described above, connecting Row 1 to row 0 is different to connecting other rows and needs to be done separately +# Create AND a(x)_b(0->7) +create_bd_cell -type ip -vlnv xilinx.com:XUP:xup_and2:1.0 xup_and2_a2_b0 +create_bd_cell -type ip -vlnv xilinx.com:XUP:xup_and2:1.0 xup_and2_a2_b1 +create_bd_cell -type ip -vlnv xilinx.com:XUP:xup_and2:1.0 xup_and2_a2_b2 +create_bd_cell -type ip -vlnv xilinx.com:XUP:xup_and2:1.0 xup_and2_a2_b3 +create_bd_cell -type ip -vlnv xilinx.com:XUP:xup_and2:1.0 xup_and2_a2_b4 +create_bd_cell -type ip -vlnv xilinx.com:XUP:xup_and2:1.0 xup_and2_a2_b5 +create_bd_cell -type ip -vlnv xilinx.com:XUP:xup_and2:1.0 xup_and2_a2_b6 +create_bd_cell -type ip -vlnv xilinx.com:XUP:xup_and2:1.0 xup_and2_a2_b7 +# Create FA/HA R(x-1) +copy_bd_objs / [get_bd_cells {half_adder}] +set_property name half_adder_r1_0 [get_bd_cells half_adder1] +copy_bd_objs / [get_bd_cells {full_adder}] +set_property name full_adder_r1_1 [get_bd_cells full_adder1] +copy_bd_objs / [get_bd_cells {full_adder}] +set_property name full_adder_r1_2 [get_bd_cells full_adder1] +copy_bd_objs / [get_bd_cells {full_adder}] +set_property name full_adder_r1_3 [get_bd_cells full_adder1] +copy_bd_objs / [get_bd_cells {full_adder}] +set_property name full_adder_r1_4 [get_bd_cells full_adder1] +copy_bd_objs / [get_bd_cells {full_adder}] +set_property name full_adder_r1_5 [get_bd_cells full_adder1] +copy_bd_objs / [get_bd_cells {full_adder}] +set_property name full_adder_r1_6 [get_bd_cells full_adder1] +copy_bd_objs / [get_bd_cells {full_adder}] +set_property name full_adder_r1_7 [get_bd_cells full_adder1] +#Connect a(x) to AND (x) +connect_bd_net [get_bd_ports a2] [get_bd_pins xup_and2_a2_b0/a] +connect_bd_net -net [get_bd_nets a2_1] [get_bd_ports a2] [get_bd_pins xup_and2_a2_b1/a] +connect_bd_net -net [get_bd_nets a2_1] [get_bd_ports a2] [get_bd_pins xup_and2_a2_b2/a] +connect_bd_net -net [get_bd_nets a2_1] [get_bd_ports a2] [get_bd_pins xup_and2_a2_b3/a] +connect_bd_net -net [get_bd_nets a2_1] [get_bd_ports a2] [get_bd_pins xup_and2_a2_b4/a] +connect_bd_net -net [get_bd_nets a2_1] [get_bd_ports a2] [get_bd_pins xup_and2_a2_b5/a] +connect_bd_net -net [get_bd_nets a2_1] [get_bd_ports a2] [get_bd_pins xup_and2_a2_b6/a] +connect_bd_net -net [get_bd_nets a2_1] [get_bd_ports a2] [get_bd_pins xup_and2_a2_b7/a] +# connect b(0->7) to AND (x) +connect_bd_net [get_bd_ports b0] [get_bd_pins xup_and2_a2_b0/b] +connect_bd_net [get_bd_ports b1] [get_bd_pins xup_and2_a2_b1/b] +connect_bd_net [get_bd_ports b2] [get_bd_pins xup_and2_a2_b2/b] +connect_bd_net [get_bd_ports b3] [get_bd_pins xup_and2_a2_b3/b] +connect_bd_net [get_bd_ports b4] [get_bd_pins xup_and2_a2_b4/b] +connect_bd_net [get_bd_ports b5] [get_bd_pins xup_and2_a2_b5/b] +connect_bd_net [get_bd_ports b6] [get_bd_pins xup_and2_a2_b6/b] +connect_bd_net [get_bd_ports b7] [get_bd_pins xup_and2_a2_b7/b] +# Connect to HA/FA AND(x) to r(x-1) +connect_bd_net [get_bd_pins xup_and2_a2_b0/y] [get_bd_pins half_adder_r1_0/a] +connect_bd_net [get_bd_pins xup_and2_a2_b1/y] [get_bd_pins full_adder_r1_1/a] +connect_bd_net [get_bd_pins xup_and2_a2_b2/y] [get_bd_pins full_adder_r1_2/a] +connect_bd_net [get_bd_pins xup_and2_a2_b3/y] [get_bd_pins full_adder_r1_3/a] +connect_bd_net [get_bd_pins xup_and2_a2_b4/y] [get_bd_pins full_adder_r1_4/a] +connect_bd_net [get_bd_pins xup_and2_a2_b5/y] [get_bd_pins full_adder_r1_5/a] +connect_bd_net [get_bd_pins xup_and2_a2_b6/y] [get_bd_pins full_adder_r1_6/a] +connect_bd_net [get_bd_pins xup_and2_a2_b7/y] [get_bd_pins full_adder_r1_7/a] +# connect r(x-2) to r(x-1) +connect_bd_net [get_bd_pins full_adder_r0_1/s] [get_bd_pins half_adder_r1_0/b] -boundary_type upper +connect_bd_net [get_bd_pins full_adder_r0_2/s] [get_bd_pins full_adder_r1_1/b] -boundary_type upper +connect_bd_net [get_bd_pins full_adder_r0_3/s] [get_bd_pins full_adder_r1_2/b] -boundary_type upper +connect_bd_net [get_bd_pins full_adder_r0_4/s] [get_bd_pins full_adder_r1_3/b] -boundary_type upper +connect_bd_net [get_bd_pins full_adder_r0_5/s] [get_bd_pins full_adder_r1_4/b] -boundary_type upper +connect_bd_net [get_bd_pins full_adder_r0_6/s] [get_bd_pins full_adder_r1_5/b] -boundary_type upper +connect_bd_net [get_bd_pins half_adder_r0_7/s] [get_bd_pins full_adder_r1_6/b] -boundary_type upper +# Connect carries r(x-1) +connect_bd_net [get_bd_pins half_adder_r1_0/c] [get_bd_pins full_adder_r1_1/c_in] -boundary_type upper +connect_bd_net [get_bd_pins full_adder_r1_1/c_out] [get_bd_pins full_adder_r1_2/c_in] -boundary_type upper +connect_bd_net [get_bd_pins full_adder_r1_2/c_out] [get_bd_pins full_adder_r1_3/c_in] -boundary_type upper +connect_bd_net [get_bd_pins full_adder_r1_3/c_out] [get_bd_pins full_adder_r1_4/c_in] -boundary_type upper +connect_bd_net [get_bd_pins full_adder_r1_4/c_out] [get_bd_pins full_adder_r1_5/c_in] -boundary_type upper +connect_bd_net [get_bd_pins full_adder_r1_5/c_out] [get_bd_pins full_adder_r1_6/c_in] -boundary_type upper +connect_bd_net [get_bd_pins full_adder_r1_6/c_out] [get_bd_pins full_adder_r1_7/c_in] -boundary_type upper +# carry from previous row +connect_bd_net [get_bd_pins half_adder_r0_7/c] [get_bd_pins full_adder_r1_7/b] -boundary_type upper +# Output s(x) from r(x-1) +connect_bd_net [get_bd_ports s2] [get_bd_pins half_adder_r1_0/s] + +# ################################# +# Connect rows 2-7 to the previous row +for { + set i 3 + set j 2 + set k 1 + } { + $i < 8 + } { + incr i + incr j + incr k + } { + + # Create AND a(x)_b(0->7) + create_bd_cell -type ip -vlnv xilinx.com:XUP:xup_and2:1.0 xup_and2_a${i}_b0 + create_bd_cell -type ip -vlnv xilinx.com:XUP:xup_and2:1.0 xup_and2_a${i}_b1 + create_bd_cell -type ip -vlnv xilinx.com:XUP:xup_and2:1.0 xup_and2_a${i}_b2 + create_bd_cell -type ip -vlnv xilinx.com:XUP:xup_and2:1.0 xup_and2_a${i}_b3 + create_bd_cell -type ip -vlnv xilinx.com:XUP:xup_and2:1.0 xup_and2_a${i}_b4 + create_bd_cell -type ip -vlnv xilinx.com:XUP:xup_and2:1.0 xup_and2_a${i}_b5 + create_bd_cell -type ip -vlnv xilinx.com:XUP:xup_and2:1.0 xup_and2_a${i}_b6 + create_bd_cell -type ip -vlnv xilinx.com:XUP:xup_and2:1.0 xup_and2_a${i}_b7 + # Create FA/HA R(x-1) + copy_bd_objs / [get_bd_cells {half_adder}] + set_property name half_adder_r${j}_0 [get_bd_cells half_adder1] + copy_bd_objs / [get_bd_cells {full_adder}] + set_property name full_adder_r${j}_1 [get_bd_cells full_adder1] + copy_bd_objs / [get_bd_cells {full_adder}] + set_property name full_adder_r${j}_2 [get_bd_cells full_adder1] + copy_bd_objs / [get_bd_cells {full_adder}] + set_property name full_adder_r${j}_3 [get_bd_cells full_adder1] + copy_bd_objs / [get_bd_cells {full_adder}] + set_property name full_adder_r${j}_4 [get_bd_cells full_adder1] + copy_bd_objs / [get_bd_cells {full_adder}] + set_property name full_adder_r${j}_5 [get_bd_cells full_adder1] + copy_bd_objs / [get_bd_cells {full_adder}] + set_property name full_adder_r${j}_6 [get_bd_cells full_adder1] + copy_bd_objs / [get_bd_cells {full_adder}] + set_property name full_adder_r${j}_7 [get_bd_cells full_adder1] + #Connect a(x) to AND (x) + connect_bd_net [get_bd_ports a${i}] [get_bd_pins xup_and2_a${i}_b0/a] + connect_bd_net -net [get_bd_nets a${i}_1] [get_bd_ports a${i}] [get_bd_pins xup_and2_a${i}_b1/a] + connect_bd_net -net [get_bd_nets a${i}_1] [get_bd_ports a${i}] [get_bd_pins xup_and2_a${i}_b2/a] + connect_bd_net -net [get_bd_nets a${i}_1] [get_bd_ports a${i}] [get_bd_pins xup_and2_a${i}_b3/a] + connect_bd_net -net [get_bd_nets a${i}_1] [get_bd_ports a${i}] [get_bd_pins xup_and2_a${i}_b4/a] + connect_bd_net -net [get_bd_nets a${i}_1] [get_bd_ports a${i}] [get_bd_pins xup_and2_a${i}_b5/a] + connect_bd_net -net [get_bd_nets a${i}_1] [get_bd_ports a${i}] [get_bd_pins xup_and2_a${i}_b6/a] + connect_bd_net -net [get_bd_nets a${i}_1] [get_bd_ports a${i}] [get_bd_pins xup_and2_a${i}_b7/a] + # connect b(0->7) to AND (x) + connect_bd_net [get_bd_ports b0] [get_bd_pins xup_and2_a${i}_b0/b] + connect_bd_net [get_bd_ports b1] [get_bd_pins xup_and2_a${i}_b1/b] + connect_bd_net [get_bd_ports b2] [get_bd_pins xup_and2_a${i}_b2/b] + connect_bd_net [get_bd_ports b3] [get_bd_pins xup_and2_a${i}_b3/b] + connect_bd_net [get_bd_ports b4] [get_bd_pins xup_and2_a${i}_b4/b] + connect_bd_net [get_bd_ports b5] [get_bd_pins xup_and2_a${i}_b5/b] + connect_bd_net [get_bd_ports b6] [get_bd_pins xup_and2_a${i}_b6/b] + connect_bd_net [get_bd_ports b7] [get_bd_pins xup_and2_a${i}_b7/b] + # Connect to HA/FA AND(x) to r(x-1) + connect_bd_net [get_bd_pins xup_and2_a${i}_b0/y] [get_bd_pins half_adder_r${j}_0/a] + connect_bd_net [get_bd_pins xup_and2_a${i}_b1/y] [get_bd_pins full_adder_r${j}_1/a] + connect_bd_net [get_bd_pins xup_and2_a${i}_b2/y] [get_bd_pins full_adder_r${j}_2/a] + connect_bd_net [get_bd_pins xup_and2_a${i}_b3/y] [get_bd_pins full_adder_r${j}_3/a] + connect_bd_net [get_bd_pins xup_and2_a${i}_b4/y] [get_bd_pins full_adder_r${j}_4/a] + connect_bd_net [get_bd_pins xup_and2_a${i}_b5/y] [get_bd_pins full_adder_r${j}_5/a] + connect_bd_net [get_bd_pins xup_and2_a${i}_b6/y] [get_bd_pins full_adder_r${j}_6/a] + connect_bd_net [get_bd_pins xup_and2_a${i}_b7/y] [get_bd_pins full_adder_r${j}_7/a] + # connect r(x-2) to r(x-1) + connect_bd_net [get_bd_pins full_adder_r${k}_1/s] [get_bd_pins half_adder_r${j}_0/b] -boundary_type upper + connect_bd_net [get_bd_pins full_adder_r${k}_2/s] [get_bd_pins full_adder_r${j}_1/b] -boundary_type upper + connect_bd_net [get_bd_pins full_adder_r${k}_3/s] [get_bd_pins full_adder_r${j}_2/b] -boundary_type upper + connect_bd_net [get_bd_pins full_adder_r${k}_4/s] [get_bd_pins full_adder_r${j}_3/b] -boundary_type upper + connect_bd_net [get_bd_pins full_adder_r${k}_5/s] [get_bd_pins full_adder_r${j}_4/b] -boundary_type upper + connect_bd_net [get_bd_pins full_adder_r${k}_6/s] [get_bd_pins full_adder_r${j}_5/b] -boundary_type upper + connect_bd_net [get_bd_pins full_adder_r${k}_7/s] [get_bd_pins full_adder_r${j}_6/b] -boundary_type upper + # Connect carries r(x-1) + connect_bd_net [get_bd_pins half_adder_r${j}_0/c] [get_bd_pins full_adder_r${j}_1/c_in] -boundary_type upper + connect_bd_net [get_bd_pins full_adder_r${j}_1/c_out] [get_bd_pins full_adder_r${j}_2/c_in] -boundary_type upper + connect_bd_net [get_bd_pins full_adder_r${j}_2/c_out] [get_bd_pins full_adder_r${j}_3/c_in] -boundary_type upper + connect_bd_net [get_bd_pins full_adder_r${j}_3/c_out] [get_bd_pins full_adder_r${j}_4/c_in] -boundary_type upper + connect_bd_net [get_bd_pins full_adder_r${j}_4/c_out] [get_bd_pins full_adder_r${j}_5/c_in] -boundary_type upper + connect_bd_net [get_bd_pins full_adder_r${j}_5/c_out] [get_bd_pins full_adder_r${j}_6/c_in] -boundary_type upper + connect_bd_net [get_bd_pins full_adder_r${j}_6/c_out] [get_bd_pins full_adder_r${j}_7/c_in] -boundary_type upper + # carry from previous row + connect_bd_net [get_bd_pins full_adder_r${k}_7/c_out] [get_bd_pins full_adder_r${j}_7/b] -boundary_type upper + # Output s(x) from r(x-1) + connect_bd_net [get_bd_ports s${i}] [get_bd_pins half_adder_r${j}_0/s] + +} + +# connect final outputs +connect_bd_net [get_bd_ports s8] [get_bd_pins full_adder_r6_1/s] +connect_bd_net [get_bd_ports s9] [get_bd_pins full_adder_r6_2/s] +connect_bd_net [get_bd_ports s10] [get_bd_pins full_adder_r6_3/s] +connect_bd_net [get_bd_ports s11] [get_bd_pins full_adder_r6_4/s] +connect_bd_net [get_bd_ports s12] [get_bd_pins full_adder_r6_5/s] +connect_bd_net [get_bd_ports s13] [get_bd_pins full_adder_r6_6/s] +connect_bd_net [get_bd_ports s14] [get_bd_pins full_adder_r6_7/s] +connect_bd_net [get_bd_ports s15] [get_bd_pins full_adder_r6_7/c_out] +# clean up original half/full adders that were used to create (copy) all other adders in the design +delete_bd_objs [get_bd_cells half_adder] [get_bd_cells full_adder] + +# Create Hierarchy +# half adder 0_0 +group_bd_cells r0_0 [get_bd_cells xup_and2_a0_b1] [get_bd_cells xup_and2_a1_b0] [get_bd_cells half_adder_r0_0] +# row 0 +for { + set j 1 + set k 2 + } { + $j < 7 + } { + incr j + incr k + } { + group_bd_cells r0_${j} [get_bd_cells xup_and2_a0_b${k}] [get_bd_cells xup_and2_a1_b${j}] [get_bd_cells full_adder_r0_${j}] +} +# half adder 0_7 +group_bd_cells r0_7 [get_bd_cells xup_and2_a1_b7] [get_bd_cells half_adder_r0_7] + +# rows 1 - 7 +for { + set i 1 + set j 2 + } { + $i < 7 + } { + incr i + incr j + } { + # half adder 0 + group_bd_cells r${i}_0 [get_bd_cells xup_and2_a${j}_b0] [get_bd_cells half_adder_r${i}_0] + for { + set k 1 + } { + $k < 8 + } { + incr k + } { + # full adders 1 - 7 + group_bd_cells r${i}_${k} [get_bd_cells xup_and2_a${j}_b${k}] [get_bd_cells full_adder_r${i}_${k}] + } +} + set i 7 + set j 8 + +#Group blocks into rows +for { + set i 0 + } { + $i < 8 + } { + incr i + } { + group_bd_cells r${i} [get_bd_cells r${i}_0] [get_bd_cells r${i}_1] [get_bd_cells r${i}_2] [get_bd_cells r${i}_3] [get_bd_cells r${i}_4] [get_bd_cells r${i}_5] [get_bd_cells r${i}_6] [get_bd_cells r${i}_7] +} +# Move last AND gate for s0 into block r0 +move_bd_cells [get_bd_cells r0] [get_bd_cells xup_and2_a0_b0] + +# Create top HDL wrapper +make_wrapper -files [get_files $project_directory/$project_name/$project_name.srcs/sources_1/bd/$project_name/$project_name.bd] -top +add_files -norecurse $project_directory/$project_name/$project_name.srcs/sources_1/bd/$project_name/hdl/$project_name\_wrapper.v +# Add pin constraints +add_files -fileset constrs_1 -norecurse $constraints_directory/$constraints_file +set_property -name {xsim.simulate.runtime} -value {0} -objects [current_fileset -simset] +# Add test bench +add_files -fileset sim_1 -norecurse $project_directory/$testbench +set_property -name {xsim.simulate.runtime} -value {500 ns} -objects [current_fileset -simset] + + +# run simulation with some sample test vectors +proc run_sim {} { +#check if simulation is already open +set sim_value [current_sim] +if {$sim_value != "" } { +puts "Close existing Simulation" +close_sim -force +} +set_property -name {xsim.simulate.xsim.more_options} -value {-view ../../../../$project_name\_tb_behav.wcfg} -objects [current_fileset -simset] +set_property -name {xsim.simulate.runtime} -value {0 ns} -objects [current_fileset -simset] +launch_simulation +puts "Running Simulation for 3276800 ns" +puts "The testbench will increment each input from 0-256 covering all input possibilities" +run 9830400 ns +puts "Simulation complete" + + +} diff --git a/Projects/Logic_Design/CN_Design/array_multiplier/src/array_multiplier_basys3_pins.xdc b/Projects/Logic_Design/CN_Design/array_multiplier/src/array_multiplier_basys3_pins.xdc new file mode 100644 index 0000000..37c650f --- /dev/null +++ b/Projects/Logic_Design/CN_Design/array_multiplier/src/array_multiplier_basys3_pins.xdc @@ -0,0 +1,69 @@ +#Pin constraints for XUPLIB 8 bit carry save adder design for Basys 3 +## Switches +set_property PACKAGE_PIN V17 [get_ports {a0}] + set_property IOSTANDARD LVCMOS33 [get_ports {a0}] +set_property PACKAGE_PIN V16 [get_ports {a1}] + set_property IOSTANDARD LVCMOS33 [get_ports {a1}] +set_property PACKAGE_PIN W16 [get_ports {a2}] + set_property IOSTANDARD LVCMOS33 [get_ports {a2}] +set_property PACKAGE_PIN W17 [get_ports {a3}] + set_property IOSTANDARD LVCMOS33 [get_ports {a3}] +set_property PACKAGE_PIN W15 [get_ports {a4}] + set_property IOSTANDARD LVCMOS33 [get_ports {a4}] +set_property PACKAGE_PIN V15 [get_ports {a5}] + set_property IOSTANDARD LVCMOS33 [get_ports {a5}] +set_property PACKAGE_PIN W14 [get_ports {a6}] + set_property IOSTANDARD LVCMOS33 [get_ports {a6}] +set_property PACKAGE_PIN W13 [get_ports {a7}] + set_property IOSTANDARD LVCMOS33 [get_ports {a7}] +set_property PACKAGE_PIN V2 [get_ports {b0}] + set_property IOSTANDARD LVCMOS33 [get_ports {b0}] +set_property PACKAGE_PIN T3 [get_ports {b1}] + set_property IOSTANDARD LVCMOS33 [get_ports {b1}] +set_property PACKAGE_PIN T2 [get_ports {b2}] + set_property IOSTANDARD LVCMOS33 [get_ports {b2}] +set_property PACKAGE_PIN R3 [get_ports {b3}] + set_property IOSTANDARD LVCMOS33 [get_ports {b3}] +set_property PACKAGE_PIN W2 [get_ports {b4}] + set_property IOSTANDARD LVCMOS33 [get_ports {b4}] +set_property PACKAGE_PIN U1 [get_ports {b5}] + set_property IOSTANDARD LVCMOS33 [get_ports {b5}] +set_property PACKAGE_PIN T1 [get_ports {b6}] + set_property IOSTANDARD LVCMOS33 [get_ports {b6}] +set_property PACKAGE_PIN R2 [get_ports {b7}] + set_property IOSTANDARD LVCMOS33 [get_ports {b7}] + +# LEDs +set_property PACKAGE_PIN U16 [get_ports {s0}] + set_property IOSTANDARD LVCMOS33 [get_ports {s0}] +set_property PACKAGE_PIN E19 [get_ports {s1}] + set_property IOSTANDARD LVCMOS33 [get_ports {s1}] +set_property PACKAGE_PIN U19 [get_ports {s2}] + set_property IOSTANDARD LVCMOS33 [get_ports {s2}] +set_property PACKAGE_PIN V19 [get_ports {s3}] + set_property IOSTANDARD LVCMOS33 [get_ports {s3}] +set_property PACKAGE_PIN W18 [get_ports {s4}] + set_property IOSTANDARD LVCMOS33 [get_ports {s4}] +set_property PACKAGE_PIN U15 [get_ports {s5}] + set_property IOSTANDARD LVCMOS33 [get_ports {s5}] +set_property PACKAGE_PIN U14 [get_ports {s6}] + set_property IOSTANDARD LVCMOS33 [get_ports {s6}] +set_property PACKAGE_PIN V14 [get_ports {s7}] + set_property IOSTANDARD LVCMOS33 [get_ports {s7}] +set_property PACKAGE_PIN V13 [get_ports {s8}] + set_property IOSTANDARD LVCMOS33 [get_ports {s8}] +set_property PACKAGE_PIN V3 [get_ports {s9}] + set_property IOSTANDARD LVCMOS33 [get_ports {s9}] +set_property PACKAGE_PIN W3 [get_ports {s10}] + set_property IOSTANDARD LVCMOS33 [get_ports {s10}] +set_property PACKAGE_PIN U3 [get_ports {s11}] + set_property IOSTANDARD LVCMOS33 [get_ports {s11}] +set_property PACKAGE_PIN P3 [get_ports {s12}] + set_property IOSTANDARD LVCMOS33 [get_ports {s12}] +set_property PACKAGE_PIN N3 [get_ports {s13}] + set_property IOSTANDARD LVCMOS33 [get_ports {s13}] +set_property PACKAGE_PIN P1 [get_ports {s14}] + set_property IOSTANDARD LVCMOS33 [get_ports {s14}] +set_property PACKAGE_PIN L1 [get_ports {s15}] + set_property IOSTANDARD LVCMOS33 [get_ports {s15}] + diff --git a/Projects/Logic_Design/CN_Design/array_multiplier/src/array_multiplier_tb.v b/Projects/Logic_Design/CN_Design/array_multiplier/src/array_multiplier_tb.v new file mode 100644 index 0000000..7913bae --- /dev/null +++ b/Projects/Logic_Design/CN_Design/array_multiplier/src/array_multiplier_tb.v @@ -0,0 +1,56 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Module Name: array_multiplier_tb +// Description: Testbench for array_multiplier +////////////////////////////////////////////////////////////////////////////////// + + +module array_multiplier_tb( + ); + + reg [7:0] a, b; + wire [15:0] s; + + integer k,l, error; + + array_multiplier_wrapper DUT (.a0(a[0]), .a1(a[1]), .a2(a[2]), .a3(a[3]), .a4(a[4]), .a5(a[5]), .a6(a[6]), .a7(a[7]), + .b0(b[0]), .b1(b[1]), .b2(b[2]), .b3(b[3]), .b4(b[4]), .b5(b[5]), .b6(b[6]), .b7(b[7]), + .s0(s[0]), .s1(s[1]), .s2(s[2]), .s3(s[3]), .s4(s[4]), .s5(s[5]), .s6(s[6]), .s7(s[7]), + .s8(s[8]), .s9(s[9]), .s10(s[10]), .s11(s[11]), .s12(s[12]), .s13(s[13]), .s14(s[14]), .s15(s[15]) + ); + + initial + begin + a = 8'h0; + b = 8'h0; + error =0; + + for (k=0; k<256; k=k+1) begin + a = k; + for (l=0; l<256; l=l+1) begin + b = l; + #150; + if(s !== k*l) + begin + error = error +1; + $display("Mismatch %d * %d = %d != %d ", k, l, (k*l), s); + end + end + end + + if(error != 0) + begin + $display("***************************"); + $display("Test Failed; %d mismatches", error); + $display("***************************"); + end + else + begin + $display("*******************************************"); + $display("Test Passed! Outputs match expected results"); + $display("*******************************************"); + end + $stop; + end + +endmodule diff --git a/Projects/Logic_Design/CN_Design/array_multiplier/src/array_multiplier_tb_behav.wcfg b/Projects/Logic_Design/CN_Design/array_multiplier/src/array_multiplier_tb_behav.wcfg new file mode 100644 index 0000000..e1581f6 --- /dev/null +++ b/Projects/Logic_Design/CN_Design/array_multiplier/src/array_multiplier_tb_behav.wcfg @@ -0,0 +1,35 @@ + + + + + + + + + + + + + + + inputs (4-bit) + label + + + a[7:0] + a[7:0] + + + b[7:0] + b[7:0] + + + output (6-bit) + label + + + s[15:0] + s[15:0] + UNSIGNEDDECRADIX + + diff --git a/Projects/Logic_Design/SN_Design/booth_multiplier_7seg/README.md b/Projects/Logic_Design/SN_Design/booth_multiplier_7seg/README.md new file mode 100644 index 0000000..76338d2 --- /dev/null +++ b/Projects/Logic_Design/SN_Design/booth_multiplier_7seg/README.md @@ -0,0 +1,44 @@ +# Booth_Multiplier_7Seg +This project is about creating an 8-bit x 8-bit multiplier using Booth's algorithm and displaying the result on the 7-segment modules using XUP_LIB components. You must download the XUP_LIB directory from the GitHub and then set the XUP_LIB path. You must also download Basys3 board files directory from the GitHub and place it in the **\\2014.4\data\boards\board_parts\artix7** directory. + +The project source files provide Tcl script, and a Xilinx Design Constraint (xdc) file targeting Basys3 board. + +### Design Description: +The design is built using counter, comparators, concat, adder/subtractor, d-ffs, slice, or, xor, shift, multiplexors, bin2bcd, and 7-segment display IPs available in XUP_LIB and Vivado's standard installation directory. It on-board 100 MHz clock source. The unsigned result is displayed on the 7-segment modules and the sign of the result is indicated on the LED15. + +### Tools and other requirements: +* Vivado 2014.4 +* XUP_LIB from GitHub +* Basys3 board files from GitHub + +### Procedure: +Execute the commands **in bold** in the tcl console + +1\. Start Vivado in a GUI mode + +2\. Set the path *basys3_github* to the XUP_LIB using command like in the Vivado Tcl Console. Note the path uses "/" instead of "\". Substiture the path where you have stored the XUP_LIB library. + +**set basys3_github {C:/xup/IPI_LIB/XUP_LIB}** + +3\. Change to the *src* directory of this project directory using the cd command, keeping in mind to use "/" instead of "\" in the directory + +**cd \** + +4\. Next, execute the following command to run the script + +**source ./booth_multiplier_7seg.tcl** + +5\. Once the project is created, the resulting block diagram will be displayed. View through the block diagram, its hierarchy and analyze the design + +6\. Generate the bitstream by clicking on the Generate Bitstream under the Program and Debug group. + +7\. When the bitstream generation is completed, connect the board, power ON the board, and use the Open Hardware Manager option to connect to the board + +8\. Program the board and verify the functionality + +Input : SW15-SW8 for the multiplier + SW7-SW0 for the multiplicand + Center button to start the computation. +Output : 4 7-segments module showing unsigned result + LED15 showing the sign of the result + diff --git a/Projects/Logic_Design/SN_Design/booth_multiplier_7seg/src/booth_multiplier_7seg.tcl b/Projects/Logic_Design/SN_Design/booth_multiplier_7seg/src/booth_multiplier_7seg.tcl new file mode 100644 index 0000000..b962041 --- /dev/null +++ b/Projects/Logic_Design/SN_Design/booth_multiplier_7seg/src/booth_multiplier_7seg.tcl @@ -0,0 +1,251 @@ +# Script to create an 8-bit x 8-bit Booth multiplier using XUP_LIB components. +# Set XUP_LIB path below before running +# +# Vivado 2014.4 +# Basys 3 board +# 16 June 2015 +# Notes: Set the path below to the XUP_LIB, and run source booth_multiplier_7seg.tcl to create the design +# It is assumed the pin constraints xdc file (booth_multiplier_7seg_basys3_pins.xdc) is in the project directory. +# If the constraints file is located somewhere else, modify the constraints_directory path below +# +# After sourcing this script, run_sim can be executed to drive simulation from proc at bottom of this file +# Once simulation is running (either from the GUI, or from this script) test_pattern can be executed to drive +# simulation input values defined at the bottom of this file +# +# The 8-bit multiplcand is input through sw7-sw0 and the 8-bit multiplier is input through sw15-sw8. +# The multiplcation process starts by pressing BtnC +# The multiplication result (unsigned) is output on the 7-segment modules +# The sign of the result is output on LED15 +# +# -------------------------------------------------------------- # +# SET 'basys3_github' PATH TO GITHUB LIBRARY BEFORE RUNNING +# -------------------------------------------------------------- # +set basys3_github {C:/xup/IPI_LIB/XUP_LIB} + +set project_directory . +set project_name booth_multiplier_7seg +set constraints_directory $project_directory +set constraints_file booth_multiplier_7seg_basys3_pins.xdc +# Create project for Basys 3 +create_project -force $project_name ./$project_name -part xc7a35tcpg236-1 +set_property board_part digilentinc.com:basys3:part0:1.1 [current_project] +set_property target_language verilog [current_project] +set_property simulator_language Verilog [current_project] +set_property ip_repo_paths $basys3_github [current_project] +update_ip_catalog +create_bd_design "$project_name" + +# Steps: +# Create a control unit +# Add a multiplicand +# Add an accumulator +# Add multiplier +# Create Q0 +# Add Q_1 +# Form Q0_Q_1 +# Create_compare_lt_2 +# Add Adder/Subtractor +# Shifter input either from Add/Sub or straight from Accumulator +# Form AQ +# Add AQ_shifter +# Form Q and A slices and connect them as input to the accumulator and multiplier +# Latch output results +# Concat output results +# Add 7-segment result display + +# create a control unit +create_bd_port -dir I -type clk sys_clock +set_property CONFIG.FREQ_HZ 100000000 [get_bd_ports sys_clock] +create_bd_port -dir I -from 7 -to 0 -type data multiplicand_in +create_bd_port -dir I -from 7 -to 0 -type data multiplier_in +create_bd_port -dir I -type data start +# create_bd_port -dir O -from 15 -to 0 result +create_bd_cell -type ip -vlnv xilinx.com:XUP:counters:1.0 counters_0 +set_property name mul_ctr [get_bd_cells counters_0] +set_property -dict [list CONFIG.COUNT_SIZE {4}] [get_bd_cells mul_ctr] +connect_bd_net [get_bd_ports sys_clock] [get_bd_pins mul_ctr/clk] +create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 xlconstant_0 +set_property name logic_1 [get_bd_cells xlconstant_0] +connect_bd_net [get_bd_pins logic_1/dout] [get_bd_pins mul_ctr/up_dn] +connect_bd_net [get_bd_ports start] [get_bd_pins mul_ctr/clr] +create_bd_cell -type ip -vlnv xilinx.com:XUP:xup_range_comparator:1.0 xup_range_comparator_0 +set_property name count_lt_8 [get_bd_cells xup_range_comparator_0] +create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 xlconstant_0 +set_property name logic_0 [get_bd_cells xlconstant_0] +set_property -dict [list CONFIG.CONST_VAL {0}] [get_bd_cells logic_0] +connect_bd_net [get_bd_pins logic_0/dout] [get_bd_pins count_lt_8/sign] +create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 xlconstant_0 +set_property name const_7 [get_bd_cells xlconstant_0] +set_property -dict [list CONFIG.CONST_WIDTH {4} CONFIG.CONST_VAL {7}] [get_bd_cells const_7] +connect_bd_net [get_bd_pins const_7/dout] [get_bd_pins count_lt_8/in2] +connect_bd_net [get_bd_pins count_lt_8/in1] [get_bd_pins mul_ctr/bin_count] +connect_bd_net [get_bd_pins count_lt_8/le] [get_bd_pins mul_ctr/enable] +group_bd_cells control_unit [get_bd_cells const_7] [get_bd_cells count_lt_8] [get_bd_cells mul_ctr] +# Add multiplicand +create_bd_cell -type ip -vlnv xilinx.com:XUP:xup_dff_en_vector:1.0 xup_dff_en_vector_0 +set_property name multiplicand [get_bd_cells xup_dff_en_vector_0] +set_property -dict [list CONFIG.SIZE {8}] [get_bd_cells multiplicand ] +connect_bd_net [get_bd_ports multiplicand_in] [get_bd_pins multiplicand/d] +connect_bd_net -net [get_bd_nets start_1] [get_bd_ports start] [get_bd_pins multiplicand/en] +connect_bd_net -net [get_bd_nets sys_clock_1] [get_bd_ports sys_clock] [get_bd_pins multiplicand/clk] +# Add an accumulator +create_bd_cell -type ip -vlnv xilinx.com:XUP:xup_dff_en_reset_vector:1.0 xup_dff_en_reset_vector_0 +set_property name accumulator [get_bd_cells xup_dff_en_reset_vector_0] +set_property -dict [list CONFIG.SIZE {8}] [get_bd_cells accumulator] +connect_bd_net -net [get_bd_nets start_1] [get_bd_ports start] [get_bd_pins accumulator/reset] +connect_bd_net [get_bd_pins accumulator/en] [get_bd_pins control_unit/count_lt_8/le] +connect_bd_net -net [get_bd_nets sys_clock_1] [get_bd_ports sys_clock] [get_bd_pins accumulator/clk] +# Add multiplier +create_bd_cell -type ip -vlnv xilinx.com:XUP:xup_dff_en_vector:1.0 xup_dff_en_vector_0 +set_property name multiplier [get_bd_cells xup_dff_en_vector_0] +set_property -dict [list CONFIG.SIZE {8}] [get_bd_cells multiplier] +connect_bd_net -net [get_bd_nets sys_clock_1] [get_bd_ports sys_clock] [get_bd_pins multiplier/clk] +connect_bd_net -net [get_bd_nets control_unit_le] [get_bd_pins multiplier/en] [get_bd_pins control_unit/le] +# Create Q0 +create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 xlslice_0 +set_property name Q0 [get_bd_cells xlslice_0] +set_property -dict [list CONFIG.DIN_WIDTH {8}] [get_bd_cells Q0] +connect_bd_net [get_bd_pins multiplier/q] [get_bd_pins Q0/Din] +# Add Q_1 +create_bd_cell -type ip -vlnv xilinx.com:XUP:xup_dff_en_reset:1.0 xup_dff_en_reset_0 +set_property name Q_1 [get_bd_cells xup_dff_en_reset_0] +connect_bd_net -net [get_bd_nets sys_clock_1] [get_bd_ports sys_clock] [get_bd_pins Q_1/clk] +connect_bd_net -net [get_bd_nets start_1] [get_bd_ports start] [get_bd_pins Q_1/reset] +connect_bd_net -net [get_bd_nets control_unit_le] [get_bd_pins Q_1/en] [get_bd_pins control_unit/le] +connect_bd_net [get_bd_pins Q0/Dout] [get_bd_pins Q_1/d] +# Form Q0_Q_1 +create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 xlconcat_0 +set_property name Q0_Q_1 [get_bd_cells xlconcat_0] +connect_bd_net [get_bd_pins Q0_Q_1/In0] [get_bd_pins Q_1/q] +connect_bd_net -net [get_bd_nets Q0_Dout] [get_bd_pins Q0_Q_1/In1] [get_bd_pins Q0/Dout] +# Create_compare_lt_2 +create_bd_cell -type ip -vlnv xilinx.com:XUP:xup_range_comparator:1.0 xup_range_comparator_0 +set_property name comp_lt_2 [get_bd_cells xup_range_comparator_0] +set_property -dict [list CONFIG.SIZE {2}] [get_bd_cells comp_lt_2] +connect_bd_net [get_bd_pins Q0_Q_1/dout] [get_bd_pins comp_lt_2/in1] +create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 xlconstant_0 +set_property name const_2 [get_bd_cells xlconstant_0] +set_property -dict [list CONFIG.CONST_WIDTH {2} CONFIG.CONST_VAL {2}] [get_bd_cells const_2] +connect_bd_net [get_bd_pins const_2/dout] [get_bd_pins comp_lt_2/in2] +connect_bd_net -net [get_bd_nets logic_0_dout] [get_bd_pins comp_lt_2/sign] [get_bd_pins logic_0/dout] +# Add Adder/Subtractor +create_bd_cell -type ip -vlnv xilinx.com:ip:c_addsub:12.0 c_addsub_0 +set_property name addsub [get_bd_cells c_addsub_0] +set_property -dict [list CONFIG.B_Width.VALUE_SRC USER CONFIG.A_Width.VALUE_SRC USER] [get_bd_cells addsub] +set_property -dict [list CONFIG.A_Width {8} CONFIG.B_Width {8} CONFIG.Add_Mode {Add_Subtract} CONFIG.Latency {0} CONFIG.Out_Width {8} CONFIG.B_Value {00000000} CONFIG.CE {false}] [get_bd_cells addsub] +connect_bd_net [get_bd_pins accumulator/q] [get_bd_pins addsub/A] +connect_bd_net [get_bd_pins multiplicand/q] [get_bd_pins addsub/B] +connect_bd_net [get_bd_pins comp_lt_2/lt] [get_bd_pins addsub/ADD] +# Add Q0_Eq_Q_1 circuit +create_bd_cell -type ip -vlnv xilinx.com:XUP:xup_xor2:1.0 xup_xor2_0 +set_property name Q0_Eq_Q_1 [get_bd_cells xup_xor2_0] +connect_bd_net -net [get_bd_nets Q0_Dout] [get_bd_pins Q0_Eq_Q_1/a] [get_bd_pins Q0/Dout] +connect_bd_net -net [get_bd_nets Q_1_q] [get_bd_pins Q0_Eq_Q_1/b] [get_bd_pins Q_1/q] +# Shifter input either from Add/Sub or straight from Accumulator +create_bd_cell -type ip -vlnv xilinx.com:XUP:xup_2_to_1_mux_vector:1.0 xup_2_to_1_mux_vector_0 +set_property name shifter_in_sel [get_bd_cells xup_2_to_1_mux_vector_0] +set_property -dict [list CONFIG.SIZE {8}] [get_bd_cells shifter_in_sel] +connect_bd_net -net [get_bd_nets accumulator_q] [get_bd_pins shifter_in_sel/a] [get_bd_pins accumulator/q] +connect_bd_net [get_bd_pins shifter_in_sel/b] [get_bd_pins addsub/S] +connect_bd_net [get_bd_pins Q0_Eq_Q_1/y] [get_bd_pins shifter_in_sel/sel] +# Form AQ +create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 xlconcat_0 +set_property name AQ [get_bd_cells xlconcat_0] +connect_bd_net -net [get_bd_nets multiplier_q] [get_bd_pins AQ/In0] [get_bd_pins multiplier/q] +connect_bd_net [get_bd_pins AQ/In1] [get_bd_pins shifter_in_sel/y] +# Add AQ shifter +create_bd_cell -type ip -vlnv xilinx.com:XUP:xup_shift_nbit:1.0 xup_shift_nbit_0 +set_property name AQ_shifter [get_bd_cells xup_shift_nbit_0] +set_property -dict [list CONFIG.SIZE {16} CONFIG.DIR {true} CONFIG.TYPE {true}] [get_bd_cells AQ_shifter] +connect_bd_net [get_bd_pins AQ/dout] [get_bd_pins AQ_shifter/parallel_in] +connect_bd_net -net [get_bd_nets logic_0_dout] [get_bd_pins AQ_shifter/dir] [get_bd_pins logic_0/dout] +connect_bd_net -net [get_bd_nets logic_1_dout] [get_bd_pins AQ_shifter/shift_type] [get_bd_pins logic_1/dout] +# Form Q and A slices and connect them as input to the accumulator and multiplier +create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 xlslice_0 +set_property name ASR_AQ_Slice_Q [get_bd_cells xlslice_0] +create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 xlslice_0 +set_property name ASR_AQ_Slice_A [get_bd_cells xlslice_0] +set_property -dict [list CONFIG.DIN_WIDTH {16} CONFIG.DIN_FROM {7} CONFIG.DOUT_WIDTH {8}] [get_bd_cells ASR_AQ_Slice_Q] +set_property -dict [list CONFIG.DIN_WIDTH {16} CONFIG.DIN_TO {8} CONFIG.DIN_FROM {15} CONFIG.DOUT_WIDTH {8}] [get_bd_cells ASR_AQ_Slice_A] +connect_bd_net [get_bd_pins AQ_shifter/parallel_out] [get_bd_pins ASR_AQ_Slice_Q/Din] +connect_bd_net -net [get_bd_nets AQ_shifter_parallel_out] [get_bd_pins ASR_AQ_Slice_A/Din] [get_bd_pins AQ_shifter/parallel_out] +connect_bd_net [get_bd_pins ASR_AQ_Slice_A/Dout] [get_bd_pins accumulator/d] +create_bd_cell -type ip -vlnv xilinx.com:XUP:xup_2_to_1_mux_vector:1.0 xup_2_to_1_mux_vector_0 +set_property name multiplier_input [get_bd_cells xup_2_to_1_mux_vector_0] +set_property -dict [list CONFIG.SIZE {8}] [get_bd_cells multiplier_input] +connect_bd_net -net [get_bd_nets start_1] [get_bd_ports start] [get_bd_pins multiplier_input/sel] +connect_bd_net [get_bd_ports multiplier_in] [get_bd_pins multiplier_input/b] +connect_bd_net [get_bd_pins multiplier_input/a] [get_bd_pins ASR_AQ_Slice_Q/Dout] +connect_bd_net [get_bd_pins multiplier_input/y] [get_bd_pins multiplier/d] +# Latch output results +create_bd_cell -type ip -vlnv xilinx.com:XUP:xup_dff_en_reset_vector:1.0 xup_dff_en_reset_vector_0 +set_property name result_h [get_bd_cells xup_dff_en_reset_vector_0] +set_property -dict [list CONFIG.SIZE {8}] [get_bd_cells result_h] +create_bd_cell -type ip -vlnv xilinx.com:XUP:xup_dff_en_reset_vector:1.0 xup_dff_en_reset_vector_0 +set_property name result_l [get_bd_cells xup_dff_en_reset_vector_0] +set_property -dict [list CONFIG.SIZE {8}] [get_bd_cells result_l] +connect_bd_net -net [get_bd_nets sys_clock_1] [get_bd_ports sys_clock] [get_bd_pins result_l/clk] +connect_bd_net -net [get_bd_nets sys_clock_1] [get_bd_ports sys_clock] [get_bd_pins result_h/clk] +connect_bd_net [get_bd_pins control_unit/count_lt_8/eq] [get_bd_pins result_l/en] +connect_bd_net -net [get_bd_nets control_unit_eq] [get_bd_pins result_h/en] [get_bd_pins control_unit/eq] +connect_bd_net -net [get_bd_nets start_1] [get_bd_ports start] [get_bd_pins result_l/reset] +connect_bd_net -net [get_bd_nets start_1] [get_bd_ports start] [get_bd_pins result_h/reset] +connect_bd_net -net [get_bd_nets ASR_AQ_Slice_A_Dout] [get_bd_pins result_h/d] [get_bd_pins ASR_AQ_Slice_A/Dout] +connect_bd_net -net [get_bd_nets ASR_AQ_Slice_Q_Dout] [get_bd_pins result_l/d] [get_bd_pins ASR_AQ_Slice_Q/Dout] +# Concat output results +create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 xlconcat_0 +set_property name results [get_bd_cells xlconcat_0] +connect_bd_net [get_bd_pins result_l/q] [get_bd_pins results/In0] +connect_bd_net [get_bd_pins result_h/q] [get_bd_pins results/In1] +# Add 7-segment result display +create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 xlslice_0 +set_property name result_sign [get_bd_cells xlslice_0] +set_property -dict [list CONFIG.DIN_WIDTH {8} CONFIG.DIN_TO {7} CONFIG.DIN_FROM {7} CONFIG.DOUT_WIDTH {1}] [get_bd_cells result_sign] +connect_bd_net -net [get_bd_nets result_h_q] [get_bd_pins result_sign/Din] [get_bd_pins result_h/q] +create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 xlslice_0 +set_property name mul_result [get_bd_cells xlslice_0] +set_property -dict [list CONFIG.DIN_WIDTH {16} CONFIG.DIN_FROM {13} CONFIG.DOUT_WIDTH {14}] [get_bd_cells mul_result] +create_bd_cell -type ip -vlnv xilinx.com:XUP:bin2bcd:1.0 bin2bcd_0 +set_property -dict [list CONFIG.SIZE {14}] [get_bd_cells bin2bcd_0] +connect_bd_net [get_bd_pins results/dout] [get_bd_pins mul_result/Din] +create_bd_cell -type ip -vlnv xilinx.com:ip:c_addsub:12.0 c_addsub_1 +set_property name unsigned_result [get_bd_cells c_addsub_1] +set_property -dict [list CONFIG.B_Width.VALUE_SRC USER CONFIG.A_Width.VALUE_SRC USER] [get_bd_cells unsigned_result] +set_property -dict [list CONFIG.A_Width {14} CONFIG.B_Width {14} CONFIG.Add_Mode {Add_Subtract} CONFIG.Latency {0} CONFIG.Out_Width {14} CONFIG.B_Value {00000000000000} CONFIG.CE {false}] [get_bd_cells unsigned_result] +connect_bd_net [get_bd_pins unsigned_result/S] [get_bd_pins bin2bcd_0/a_in] +create_bd_cell -type ip -vlnv xilinx.com:XUP:xup_inv:1.0 xup_inv_0 +connect_bd_net [get_bd_pins result_sign/Dout] [get_bd_pins xup_inv_0/a] +connect_bd_net [get_bd_pins xup_inv_0/y] [get_bd_pins unsigned_result/ADD] +connect_bd_net [get_bd_pins mul_result/Dout] [get_bd_pins unsigned_result/B] +create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 xlconstant_0 +set_property name cons_14bit_0 [get_bd_cells xlconstant_0] +set_property -dict [list CONFIG.CONST_WIDTH {14} CONFIG.CONST_VAL {0}] [get_bd_cells cons_14bit_0] +connect_bd_net [get_bd_pins cons_14bit_0/dout] [get_bd_pins unsigned_result/A] +create_bd_cell -type ip -vlnv xilinx.com:XUP:seg7display:1.0 seg7display_0 +create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 xlconcat_0 +set_property -dict [list CONFIG.NUM_PORTS {4}] [get_bd_cells xlconcat_0] +connect_bd_net [get_bd_pins bin2bcd_0/ones] [get_bd_pins xlconcat_0/In0] +connect_bd_net [get_bd_pins bin2bcd_0/tens] [get_bd_pins xlconcat_0/In1] +connect_bd_net [get_bd_pins bin2bcd_0/hundreds] [get_bd_pins xlconcat_0/In2] +connect_bd_net [get_bd_pins bin2bcd_0/thousands] [get_bd_pins xlconcat_0/In3] +connect_bd_net [get_bd_pins xlconcat_0/dout] [get_bd_pins seg7display_0/x_l] +create_bd_port -dir O -from 6 -to 0 a_to_g +connect_bd_net [get_bd_pins /seg7display_0/a_to_g] [get_bd_ports a_to_g] +set_property name seg [get_bd_ports a_to_g] +set_property -dict [list CONFIG.DP_0 {0} CONFIG.DP_1 {0} CONFIG.DP_2 {0} CONFIG.DP_3 {0}] [get_bd_cells seg7display_0] +create_bd_port -dir O -from 3 -to 0 an_l +connect_bd_net [get_bd_pins /seg7display_0/an_l] [get_bd_ports an_l] +set_property name an [get_bd_ports an_l] +connect_bd_net -net [get_bd_nets sys_clock_1] [get_bd_ports sys_clock] [get_bd_pins seg7display_0/clk] +connect_bd_net -net [get_bd_nets start_1] [get_bd_ports start] [get_bd_pins seg7display_0/reset] +create_bd_port -dir O sign +connect_bd_net -net [get_bd_nets result_sign_Dout] [get_bd_ports sign] [get_bd_pins result_sign/Dout] +# Regerate the layout and save it +regenerate_bd_layout +save_bd_design +# Create top HDL wrapper +make_wrapper -files [get_files $project_directory/$project_name/$project_name.srcs/sources_1/bd/$project_name/$project_name.bd] -top +add_files -norecurse $project_directory/$project_name/$project_name.srcs/sources_1/bd/$project_name/hdl/$project_name\_wrapper.v +# Add pin constraints +add_files -fileset constrs_1 -norecurse $constraints_directory/$constraints_file + diff --git a/Projects/Logic_Design/SN_Design/booth_multiplier_7seg/src/booth_multiplier_7seg_basys3_pins.xdc b/Projects/Logic_Design/SN_Design/booth_multiplier_7seg/src/booth_multiplier_7seg_basys3_pins.xdc new file mode 100644 index 0000000..f00cff8 --- /dev/null +++ b/Projects/Logic_Design/SN_Design/booth_multiplier_7seg/src/booth_multiplier_7seg_basys3_pins.xdc @@ -0,0 +1,59 @@ +#Pin constraints for XUPLIB 8 bit x 8 bit multiplier design for Basys 3 +## Clock signal +set_property PACKAGE_PIN W5 [get_ports sys_clock] +set_property IOSTANDARD LVCMOS33 [get_ports sys_clock] +create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports sys_clock] + +# pushbutton BtnC +set_property PACKAGE_PIN U18 [get_ports {start}] +set_property IOSTANDARD LVCMOS33 [get_ports {start}] + +## Switches +set_property IOSTANDARD LVCMOS33 [get_ports {multiplicand_in[*]}] +set_property PACKAGE_PIN V17 [get_ports {multiplicand_in[0]}] +set_property PACKAGE_PIN V16 [get_ports {multiplicand_in[1]}] +set_property PACKAGE_PIN W16 [get_ports {multiplicand_in[2]}] +set_property PACKAGE_PIN W17 [get_ports {multiplicand_in[3]}] +set_property PACKAGE_PIN W15 [get_ports {multiplicand_in[4]}] +set_property PACKAGE_PIN V15 [get_ports {multiplicand_in[5]}] +set_property PACKAGE_PIN W14 [get_ports {multiplicand_in[6]}] +set_property PACKAGE_PIN W13 [get_ports {multiplicand_in[7]}] + +set_property IOSTANDARD LVCMOS33 [get_ports {multiplier_in[*]}] +set_property PACKAGE_PIN V2 [get_ports {multiplier_in[0]}] +set_property PACKAGE_PIN T3 [get_ports {multiplier_in[1]}] +set_property PACKAGE_PIN T2 [get_ports {multiplier_in[2]}] +set_property PACKAGE_PIN R3 [get_ports {multiplier_in[3]}] +set_property PACKAGE_PIN W2 [get_ports {multiplier_in[4]}] +set_property PACKAGE_PIN U1 [get_ports {multiplier_in[5]}] +set_property PACKAGE_PIN T1 [get_ports {multiplier_in[6]}] +set_property PACKAGE_PIN R2 [get_ports {multiplier_in[7]}] + +# LED15 +set_property IOSTANDARD LVCMOS33 [get_ports {sign}] +set_property PACKAGE_PIN L1 [get_ports {sign}] + +##7 segment display +set_property PACKAGE_PIN W7 [get_ports {seg[0]}] +set_property IOSTANDARD LVCMOS33 [get_ports {seg[0]}] +set_property PACKAGE_PIN W6 [get_ports {seg[1]}] +set_property IOSTANDARD LVCMOS33 [get_ports {seg[1]}] +set_property PACKAGE_PIN U8 [get_ports {seg[2]}] +set_property IOSTANDARD LVCMOS33 [get_ports {seg[2]}] +set_property PACKAGE_PIN V8 [get_ports {seg[3]}] +set_property IOSTANDARD LVCMOS33 [get_ports {seg[3]}] +set_property PACKAGE_PIN U5 [get_ports {seg[4]}] +set_property IOSTANDARD LVCMOS33 [get_ports {seg[4]}] +set_property PACKAGE_PIN V5 [get_ports {seg[5]}] +set_property IOSTANDARD LVCMOS33 [get_ports {seg[5]}] +set_property PACKAGE_PIN U7 [get_ports {seg[6]}] +set_property IOSTANDARD LVCMOS33 [get_ports {seg[6]}] + +set_property PACKAGE_PIN U2 [get_ports {an[0]}] +set_property IOSTANDARD LVCMOS33 [get_ports {an[0]}] +set_property PACKAGE_PIN U4 [get_ports {an[1]}] +set_property IOSTANDARD LVCMOS33 [get_ports {an[1]}] +set_property PACKAGE_PIN V4 [get_ports {an[2]}] +set_property IOSTANDARD LVCMOS33 [get_ports {an[2]}] +set_property PACKAGE_PIN W4 [get_ports {an[3]}] +set_property IOSTANDARD LVCMOS33 [get_ports {an[3]}] \ No newline at end of file diff --git a/Projects/Logic_Design/SN_Design/booth_multiplier_leds/README.md b/Projects/Logic_Design/SN_Design/booth_multiplier_leds/README.md new file mode 100644 index 0000000..6953c4d --- /dev/null +++ b/Projects/Logic_Design/SN_Design/booth_multiplier_leds/README.md @@ -0,0 +1,43 @@ +# Booth_Multiplier_leds +This project is about creating an 8-bit x 8-bit multiplier using Booth's algorithm and displaying the result on the LEDs using XUP_LIB components. You must download the XUP_LIB directory from the GitHub and then set the XUP_LIB path. You must also download Basys3 board files directory from the GitHub and place it in the **\\2014.4\data\boards\board_parts\artix7** directory. + +The project source files provide Tcl script, and a Xilinx Design Constraint (xdc) file targeting Basys3 board. + +### Design Description: +The design is built using counter, comparators, concat, adder/subtractor, d-ffs, slice, or, xor, shift, and multiplexor IPs available in XUP_LIB and Vivado's standard installation directory. It on-board 100 MHz clock source. The result is displayed on LEDs. + +### Tools and other requirements: +* Vivado 2014.4 +* XUP_LIB from GitHub +* Basys3 board files from GitHub + +### Procedure: +Execute the commands **in bold** in the tcl console + +1\. Start Vivado in a GUI mode + +2\. Set the path *basys3_github* to the XUP_LIB using command like in the Vivado Tcl Console. Note the path uses "/" instead of "\". Substiture the path where you have stored the XUP_LIB library. + +**set basys3_github {C:/xup/IPI_LIB/XUP_LIB}** + +3\. Change to the *src* directory of this project directory using the cd command, keeping in mind to use "/" instead of "\" in the directory + +**cd \** + +4\. Next, execute the following command to run the script + +**source ./booth_multiplier_leds.tcl** + +5\. Once the project is created, the resulting block diagram will be displayed. View through the block diagram, its hierarchy and analyze the design + +6\. Generate the bitstream by clicking on the Generate Bitstream under the Program and Debug group. + +7\. When the bitstream generation is completed, connect the board, power ON the board, and use the Open Hardware Manager option to connect to the board + +8\. Program the board and verify the functionality + +Input : SW15-SW8 for the multiplier + SW7-SW0 for the multiplicand + Center button to start the computation. +Output : LED15-LED0 showing the result + diff --git a/Projects/Logic_Design/SN_Design/booth_multiplier_leds/src/booth_multiplier_leds.tcl b/Projects/Logic_Design/SN_Design/booth_multiplier_leds/src/booth_multiplier_leds.tcl new file mode 100644 index 0000000..c6420dd --- /dev/null +++ b/Projects/Logic_Design/SN_Design/booth_multiplier_leds/src/booth_multiplier_leds.tcl @@ -0,0 +1,228 @@ +# Script to create an 8-bit x 8-bit Booth multiplier using XUP_LIB components. +# Set XUP_LIB path below before running +# +# Vivado 2014.4 +# Basys 3 board +# 16 June 2015 +# Notes: Set the path below to the XUP_LIB, and run source booth_multiplier_leds.tcl to create the design +# It is assumed the pin constraints xdc file (booth_multiplier_leds_basys3_pins.xdc) is in the project directory. +# If the constraints file is located somewhere else, modify the constraints_directory path below +# +# After sourcing this script, run_sim can be executed to drive simulation from proc at bottom of this file +# Once simulation is running (either from the GUI, or from this script) test_pattern can be executed to drive +# simulation input values defined at the bottom of this file +# +# The 8-bit multiplcand is input through sw7-sw0 and the 8-bit multiplier is input through sw15-sw8. +# The multiplcation process starts by pressing BtnC +# The 16-bit output is connected to LED15-LED0 +# +# -------------------------------------------------------------- # +# SET 'basys3_github' PATH TO GITHUB LIBRARY BEFORE RUNNING +# -------------------------------------------------------------- # +set basys3_github {C:/xup/IPI_LIB/XUP_LIB} + +set project_directory . +set project_name booth_multiplier_leds +set constraints_directory $project_directory +set constraints_file booth_multiplier_leds_basys3_pins.xdc +set testbench booth_multiplier_leds_tb.v +# Create project for Basys 3 +create_project -force $project_name ./$project_name -part xc7a35tcpg236-1 +set_property board_part digilentinc.com:basys3:part0:1.1 [current_project] +set_property target_language verilog [current_project] +set_property simulator_language Verilog [current_project] +set_property ip_repo_paths $basys3_github [current_project] +update_ip_catalog +create_bd_design "$project_name" + +# Steps: +# Create a control unit +# Add a multiplicand +# Add an accumulator +# Add multiplier +# Create Q0 +# Add Q_1 +# Form Q0_Q_1 +# Create_compare_lt_2 +# Add Adder/Subtractor +# Shifter input either from Add/Sub or straight from Accumulator +# Form AQ +# Add AQ_shifter +# Form Q and A slices and connect them as input to the accumulator and multiplier +# Latch output results +# Concat output results +# + +# create a control unit +create_bd_port -dir I -type clk sys_clock +set_property CONFIG.FREQ_HZ 100000000 [get_bd_ports sys_clock] +create_bd_port -dir I -from 7 -to 0 -type data multiplicand_in +create_bd_port -dir I -from 7 -to 0 -type data multiplier_in +create_bd_port -dir I -type data start +create_bd_port -dir O -from 15 -to 0 result +create_bd_cell -type ip -vlnv xilinx.com:XUP:counters:1.0 counters_0 +set_property name mul_ctr [get_bd_cells counters_0] +set_property -dict [list CONFIG.COUNT_SIZE {4}] [get_bd_cells mul_ctr] +connect_bd_net [get_bd_ports sys_clock] [get_bd_pins mul_ctr/clk] +create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 xlconstant_0 +set_property name logic_1 [get_bd_cells xlconstant_0] +connect_bd_net [get_bd_pins logic_1/dout] [get_bd_pins mul_ctr/up_dn] +connect_bd_net [get_bd_ports start] [get_bd_pins mul_ctr/clr] +create_bd_cell -type ip -vlnv xilinx.com:XUP:xup_range_comparator:1.0 xup_range_comparator_0 +set_property name count_lt_8 [get_bd_cells xup_range_comparator_0] +create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 xlconstant_0 +set_property name logic_0 [get_bd_cells xlconstant_0] +set_property -dict [list CONFIG.CONST_VAL {0}] [get_bd_cells logic_0] +connect_bd_net [get_bd_pins logic_0/dout] [get_bd_pins count_lt_8/sign] +create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 xlconstant_0 +set_property name const_7 [get_bd_cells xlconstant_0] +set_property -dict [list CONFIG.CONST_WIDTH {4} CONFIG.CONST_VAL {7}] [get_bd_cells const_7] +connect_bd_net [get_bd_pins const_7/dout] [get_bd_pins count_lt_8/in2] +connect_bd_net [get_bd_pins count_lt_8/in1] [get_bd_pins mul_ctr/bin_count] +connect_bd_net [get_bd_pins count_lt_8/le] [get_bd_pins mul_ctr/enable] +group_bd_cells control_unit [get_bd_cells const_7] [get_bd_cells count_lt_8] [get_bd_cells mul_ctr] +# Add multiplicand +create_bd_cell -type ip -vlnv xilinx.com:XUP:xup_dff_en_vector:1.0 xup_dff_en_vector_0 +set_property name multiplicand [get_bd_cells xup_dff_en_vector_0] +set_property -dict [list CONFIG.SIZE {8}] [get_bd_cells multiplicand ] +connect_bd_net [get_bd_ports multiplicand_in] [get_bd_pins multiplicand/d] +connect_bd_net -net [get_bd_nets start_1] [get_bd_ports start] [get_bd_pins multiplicand/en] +connect_bd_net -net [get_bd_nets sys_clock_1] [get_bd_ports sys_clock] [get_bd_pins multiplicand/clk] +# Add an accumulator +create_bd_cell -type ip -vlnv xilinx.com:XUP:xup_dff_en_reset_vector:1.0 xup_dff_en_reset_vector_0 +set_property name accumulator [get_bd_cells xup_dff_en_reset_vector_0] +set_property -dict [list CONFIG.SIZE {8}] [get_bd_cells accumulator] +connect_bd_net -net [get_bd_nets start_1] [get_bd_ports start] [get_bd_pins accumulator/reset] +connect_bd_net [get_bd_pins accumulator/en] [get_bd_pins control_unit/count_lt_8/le] +connect_bd_net -net [get_bd_nets sys_clock_1] [get_bd_ports sys_clock] [get_bd_pins accumulator/clk] +# Add multiplier +create_bd_cell -type ip -vlnv xilinx.com:XUP:xup_dff_en_vector:1.0 xup_dff_en_vector_0 +set_property name multiplier [get_bd_cells xup_dff_en_vector_0] +set_property -dict [list CONFIG.SIZE {8}] [get_bd_cells multiplier] +connect_bd_net -net [get_bd_nets sys_clock_1] [get_bd_ports sys_clock] [get_bd_pins multiplier/clk] +connect_bd_net -net [get_bd_nets control_unit_le] [get_bd_pins multiplier/en] [get_bd_pins control_unit/le] +# Create Q0 +create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 xlslice_0 +set_property name Q0 [get_bd_cells xlslice_0] +set_property -dict [list CONFIG.DIN_WIDTH {8}] [get_bd_cells Q0] +connect_bd_net [get_bd_pins multiplier/q] [get_bd_pins Q0/Din] +# Add Q_1 +create_bd_cell -type ip -vlnv xilinx.com:XUP:xup_dff_en_reset:1.0 xup_dff_en_reset_0 +set_property name Q_1 [get_bd_cells xup_dff_en_reset_0] +connect_bd_net -net [get_bd_nets sys_clock_1] [get_bd_ports sys_clock] [get_bd_pins Q_1/clk] +connect_bd_net -net [get_bd_nets start_1] [get_bd_ports start] [get_bd_pins Q_1/reset] +connect_bd_net -net [get_bd_nets control_unit_le] [get_bd_pins Q_1/en] [get_bd_pins control_unit/le] +connect_bd_net [get_bd_pins Q0/Dout] [get_bd_pins Q_1/d] +# Form Q0_Q_1 +create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 xlconcat_0 +set_property name Q0_Q_1 [get_bd_cells xlconcat_0] +connect_bd_net [get_bd_pins Q0_Q_1/In0] [get_bd_pins Q_1/q] +connect_bd_net -net [get_bd_nets Q0_Dout] [get_bd_pins Q0_Q_1/In1] [get_bd_pins Q0/Dout] +# Create_compare_lt_2 +create_bd_cell -type ip -vlnv xilinx.com:XUP:xup_range_comparator:1.0 xup_range_comparator_0 +set_property name comp_lt_2 [get_bd_cells xup_range_comparator_0] +set_property -dict [list CONFIG.SIZE {2}] [get_bd_cells comp_lt_2] +connect_bd_net [get_bd_pins Q0_Q_1/dout] [get_bd_pins comp_lt_2/in1] +create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 xlconstant_0 +set_property name const_2 [get_bd_cells xlconstant_0] +set_property -dict [list CONFIG.CONST_WIDTH {2} CONFIG.CONST_VAL {2}] [get_bd_cells const_2] +connect_bd_net [get_bd_pins const_2/dout] [get_bd_pins comp_lt_2/in2] +connect_bd_net -net [get_bd_nets logic_0_dout] [get_bd_pins comp_lt_2/sign] [get_bd_pins logic_0/dout] +# Add Adder/Subtractor +create_bd_cell -type ip -vlnv xilinx.com:ip:c_addsub:12.0 c_addsub_0 +set_property name addsub [get_bd_cells c_addsub_0] +set_property -dict [list CONFIG.B_Width.VALUE_SRC USER CONFIG.A_Width.VALUE_SRC USER] [get_bd_cells addsub] +set_property -dict [list CONFIG.A_Width {8} CONFIG.B_Width {8} CONFIG.Add_Mode {Add_Subtract} CONFIG.Latency {0} CONFIG.Out_Width {8} CONFIG.B_Value {00000000} CONFIG.CE {false}] [get_bd_cells addsub] +connect_bd_net [get_bd_pins accumulator/q] [get_bd_pins addsub/A] +connect_bd_net [get_bd_pins multiplicand/q] [get_bd_pins addsub/B] +connect_bd_net [get_bd_pins comp_lt_2/lt] [get_bd_pins addsub/ADD] +# Add Q0_Eq_Q_1 circuit +create_bd_cell -type ip -vlnv xilinx.com:XUP:xup_xor2:1.0 xup_xor2_0 +set_property name Q0_Eq_Q_1 [get_bd_cells xup_xor2_0] +connect_bd_net -net [get_bd_nets Q0_Dout] [get_bd_pins Q0_Eq_Q_1/a] [get_bd_pins Q0/Dout] +connect_bd_net -net [get_bd_nets Q_1_q] [get_bd_pins Q0_Eq_Q_1/b] [get_bd_pins Q_1/q] +# Shifter input either from Add/Sub or straight from Accumulator +create_bd_cell -type ip -vlnv xilinx.com:XUP:xup_2_to_1_mux_vector:1.0 xup_2_to_1_mux_vector_0 +set_property name shifter_in_sel [get_bd_cells xup_2_to_1_mux_vector_0] +set_property -dict [list CONFIG.SIZE {8}] [get_bd_cells shifter_in_sel] +connect_bd_net -net [get_bd_nets accumulator_q] [get_bd_pins shifter_in_sel/a] [get_bd_pins accumulator/q] +connect_bd_net [get_bd_pins shifter_in_sel/b] [get_bd_pins addsub/S] +connect_bd_net [get_bd_pins Q0_Eq_Q_1/y] [get_bd_pins shifter_in_sel/sel] +# Form AQ +create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 xlconcat_0 +set_property name AQ [get_bd_cells xlconcat_0] +connect_bd_net -net [get_bd_nets multiplier_q] [get_bd_pins AQ/In0] [get_bd_pins multiplier/q] +connect_bd_net [get_bd_pins AQ/In1] [get_bd_pins shifter_in_sel/y] +# Add AQ shifter +create_bd_cell -type ip -vlnv xilinx.com:XUP:xup_shift_nbit:1.0 xup_shift_nbit_0 +set_property name AQ_shifter [get_bd_cells xup_shift_nbit_0] +set_property -dict [list CONFIG.SIZE {16} CONFIG.DIR {true} CONFIG.TYPE {true}] [get_bd_cells AQ_shifter] +connect_bd_net [get_bd_pins AQ/dout] [get_bd_pins AQ_shifter/parallel_in] +connect_bd_net -net [get_bd_nets logic_0_dout] [get_bd_pins AQ_shifter/dir] [get_bd_pins logic_0/dout] +connect_bd_net -net [get_bd_nets logic_1_dout] [get_bd_pins AQ_shifter/shift_type] [get_bd_pins logic_1/dout] +# Form Q and A slices and connect them as input to the accumulator and multiplier +create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 xlslice_0 +set_property name ASR_AQ_Slice_Q [get_bd_cells xlslice_0] +create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 xlslice_0 +set_property name ASR_AQ_Slice_A [get_bd_cells xlslice_0] +set_property -dict [list CONFIG.DIN_WIDTH {16} CONFIG.DIN_FROM {7} CONFIG.DOUT_WIDTH {8}] [get_bd_cells ASR_AQ_Slice_Q] +set_property -dict [list CONFIG.DIN_WIDTH {16} CONFIG.DIN_TO {8} CONFIG.DIN_FROM {15} CONFIG.DOUT_WIDTH {8}] [get_bd_cells ASR_AQ_Slice_A] +connect_bd_net [get_bd_pins AQ_shifter/parallel_out] [get_bd_pins ASR_AQ_Slice_Q/Din] +connect_bd_net -net [get_bd_nets AQ_shifter_parallel_out] [get_bd_pins ASR_AQ_Slice_A/Din] [get_bd_pins AQ_shifter/parallel_out] +connect_bd_net [get_bd_pins ASR_AQ_Slice_A/Dout] [get_bd_pins accumulator/d] +create_bd_cell -type ip -vlnv xilinx.com:XUP:xup_2_to_1_mux_vector:1.0 xup_2_to_1_mux_vector_0 +set_property name multiplier_input [get_bd_cells xup_2_to_1_mux_vector_0] +set_property -dict [list CONFIG.SIZE {8}] [get_bd_cells multiplier_input] +connect_bd_net -net [get_bd_nets start_1] [get_bd_ports start] [get_bd_pins multiplier_input/sel] +connect_bd_net [get_bd_ports multiplier_in] [get_bd_pins multiplier_input/b] +connect_bd_net [get_bd_pins multiplier_input/a] [get_bd_pins ASR_AQ_Slice_Q/Dout] +connect_bd_net [get_bd_pins multiplier_input/y] [get_bd_pins multiplier/d] +# Latch output results +create_bd_cell -type ip -vlnv xilinx.com:XUP:xup_dff_en_reset_vector:1.0 xup_dff_en_reset_vector_0 +set_property name result_h [get_bd_cells xup_dff_en_reset_vector_0] +set_property -dict [list CONFIG.SIZE {8}] [get_bd_cells result_h] +create_bd_cell -type ip -vlnv xilinx.com:XUP:xup_dff_en_reset_vector:1.0 xup_dff_en_reset_vector_0 +set_property name result_l [get_bd_cells xup_dff_en_reset_vector_0] +set_property -dict [list CONFIG.SIZE {8}] [get_bd_cells result_l] +connect_bd_net -net [get_bd_nets sys_clock_1] [get_bd_ports sys_clock] [get_bd_pins result_l/clk] +connect_bd_net -net [get_bd_nets sys_clock_1] [get_bd_ports sys_clock] [get_bd_pins result_h/clk] +connect_bd_net [get_bd_pins control_unit/count_lt_8/eq] [get_bd_pins result_l/en] +connect_bd_net -net [get_bd_nets control_unit_eq] [get_bd_pins result_h/en] [get_bd_pins control_unit/eq] +connect_bd_net -net [get_bd_nets start_1] [get_bd_ports start] [get_bd_pins result_l/reset] +connect_bd_net -net [get_bd_nets start_1] [get_bd_ports start] [get_bd_pins result_h/reset] +connect_bd_net -net [get_bd_nets ASR_AQ_Slice_A_Dout] [get_bd_pins result_h/d] [get_bd_pins ASR_AQ_Slice_A/Dout] +connect_bd_net -net [get_bd_nets ASR_AQ_Slice_Q_Dout] [get_bd_pins result_l/d] [get_bd_pins ASR_AQ_Slice_Q/Dout] +# Concat output results +create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 xlconcat_0 +set_property name results [get_bd_cells xlconcat_0] +connect_bd_net [get_bd_pins result_l/q] [get_bd_pins results/In0] +connect_bd_net [get_bd_pins result_h/q] [get_bd_pins results/In1] +connect_bd_net [get_bd_ports result] [get_bd_pins results/dout] +# Regerate the layout and save it +regenerate_bd_layout +save_bd_design +# Create top HDL wrapper +make_wrapper -files [get_files $project_directory/$project_name/$project_name.srcs/sources_1/bd/$project_name/$project_name.bd] -top +add_files -norecurse $project_directory/$project_name/$project_name.srcs/sources_1/bd/$project_name/hdl/$project_name\_wrapper.v +# Add pin constraints +add_files -fileset constrs_1 -norecurse $constraints_directory/$constraints_file +# Add test bench +add_files -fileset sim_1 -norecurse $project_directory/$testbench +set_property -name {xsim.simulate.runtime} -value {500 ns} -objects [current_fileset -simset] + +# run simulation with some sample test vectors +proc run_sim {} { +#check if simulation is already open +set sim_value [current_sim] +if {$sim_value != "" } { +puts "Close existing Simulation" +close_sim -force +} +set_property -name {xsim.simulate.xsim.more_options} -value {-view ../../../../booth_multiplier_leds_tb_behav.wcfg} -objects [current_fileset -simset] +set_property -name {xsim.simulate.runtime} -value {0 ns} -objects [current_fileset -simset] +launch_simulation +puts "Running Simulation for 1000 ns" +run 1000 ns +puts "Simulation complete" +} + diff --git a/Projects/Logic_Design/SN_Design/booth_multiplier_leds/src/booth_multiplier_leds_basys3_pins.xdc b/Projects/Logic_Design/SN_Design/booth_multiplier_leds/src/booth_multiplier_leds_basys3_pins.xdc new file mode 100644 index 0000000..c3c14e4 --- /dev/null +++ b/Projects/Logic_Design/SN_Design/booth_multiplier_leds/src/booth_multiplier_leds_basys3_pins.xdc @@ -0,0 +1,50 @@ +#Pin constraints for XUPLIB 8 bit x 8 bit multiplier design for Basys 3 +## Clock signal +set_property PACKAGE_PIN W5 [get_ports sys_clock] +set_property IOSTANDARD LVCMOS33 [get_ports sys_clock] +create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports sys_clock] + +# pushbutton BtnC +set_property PACKAGE_PIN U18 [get_ports {start}] +set_property IOSTANDARD LVCMOS33 [get_ports {start}] + +## Switches +set_property IOSTANDARD LVCMOS33 [get_ports {multiplicand_in[*]}] +set_property PACKAGE_PIN V17 [get_ports {multiplicand_in[0]}] +set_property PACKAGE_PIN V16 [get_ports {multiplicand_in[1]}] +set_property PACKAGE_PIN W16 [get_ports {multiplicand_in[2]}] +set_property PACKAGE_PIN W17 [get_ports {multiplicand_in[3]}] +set_property PACKAGE_PIN W15 [get_ports {multiplicand_in[4]}] +set_property PACKAGE_PIN V15 [get_ports {multiplicand_in[5]}] +set_property PACKAGE_PIN W14 [get_ports {multiplicand_in[6]}] +set_property PACKAGE_PIN W13 [get_ports {multiplicand_in[7]}] + +set_property IOSTANDARD LVCMOS33 [get_ports {multiplier_in[*]}] +set_property PACKAGE_PIN V2 [get_ports {multiplier_in[0]}] +set_property PACKAGE_PIN T3 [get_ports {multiplier_in[1]}] +set_property PACKAGE_PIN T2 [get_ports {multiplier_in[2]}] +set_property PACKAGE_PIN R3 [get_ports {multiplier_in[3]}] +set_property PACKAGE_PIN W2 [get_ports {multiplier_in[4]}] +set_property PACKAGE_PIN U1 [get_ports {multiplier_in[5]}] +set_property PACKAGE_PIN T1 [get_ports {multiplier_in[6]}] +set_property PACKAGE_PIN R2 [get_ports {multiplier_in[7]}] + +# LEDs +set_property IOSTANDARD LVCMOS33 [get_ports {result[*]}] +set_property PACKAGE_PIN U16 [get_ports {result[0]}] +set_property PACKAGE_PIN E19 [get_ports {result[1]}] +set_property PACKAGE_PIN U19 [get_ports {result[2]}] +set_property PACKAGE_PIN V19 [get_ports {result[3]}] +set_property PACKAGE_PIN W18 [get_ports {result[4]}] +set_property PACKAGE_PIN U15 [get_ports {result[5]}] +set_property PACKAGE_PIN U14 [get_ports {result[6]}] +set_property PACKAGE_PIN V14 [get_ports {result[7]}] +set_property PACKAGE_PIN V13 [get_ports {result[8]}] +set_property PACKAGE_PIN V3 [get_ports {result[9]}] +set_property PACKAGE_PIN W3 [get_ports {result[10]}] +set_property PACKAGE_PIN U3 [get_ports {result[11]}] +set_property PACKAGE_PIN P3 [get_ports {result[12]}] +set_property PACKAGE_PIN N3 [get_ports {result[13]}] +set_property PACKAGE_PIN P1 [get_ports {result[14]}] +set_property PACKAGE_PIN L1 [get_ports {result[15]}] + diff --git a/Projects/Logic_Design/SN_Design/booth_multiplier_leds/src/booth_multiplier_leds_tb.v b/Projects/Logic_Design/SN_Design/booth_multiplier_leds/src/booth_multiplier_leds_tb.v new file mode 100644 index 0000000..1b65b93 --- /dev/null +++ b/Projects/Logic_Design/SN_Design/booth_multiplier_leds/src/booth_multiplier_leds_tb.v @@ -0,0 +1,83 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Module Name: booth_multiplier_leds_tb +////////////////////////////////////////////////////////////////////////////////// + + +module booth_multiplier_leds_tb( + + ); + + parameter PERIOD=20; + + reg sys_clock; + reg start; + reg [7:0] multiplier_in; + reg [7:0] multiplicand_in; + wire [15:0] result; + + booth_multiplier_leds_wrapper DUT ( + .sys_clock(sys_clock), .start(start), .multiplier_in(multiplier_in), .multiplicand_in(multiplicand_in), + .result(result) + ); + + initial begin + sys_clock = 0; + forever #(PERIOD/2) sys_clock = ~sys_clock; + end + + initial + begin + start=0; + @(posedge sys_clock); + multiplier_in = 8'b00000111; // 7 + multiplicand_in = 8'b00000111; // 7 + #5; + start = 1; + #(2*PERIOD); + start = 0; + @(negedge booth_multiplier_leds_tb.DUT.booth_multiplier_leds_i.control_unit_eq); + @(posedge sys_clock); + multiplier_in = 8'b11111100; // -4 + multiplicand_in = 8'b11111100; // -4 + #5; + start = 1; + #(2*PERIOD); + start = 0; + @(negedge booth_multiplier_leds_tb.DUT.booth_multiplier_leds_i.control_unit_eq); + @(posedge sys_clock); + multiplier_in = 8'b00000111; // 7 + multiplicand_in = 8'b11111100; // -4 + #5; + start = 1; + #(2*PERIOD); + start = 0; + @(negedge booth_multiplier_leds_tb.DUT.booth_multiplier_leds_i.control_unit_eq); + @(posedge sys_clock); + multiplier_in = 8'b11111100; // -4 + multiplicand_in = 8'b11111100; // -4 + #5; + start = 1; + #(2*PERIOD); + start = 0; + @(negedge booth_multiplier_leds_tb.DUT.booth_multiplier_leds_i.control_unit_eq); + @(posedge sys_clock); + multiplier_in = 8'b00000111; // 7 + multiplicand_in = 8'b00000111; // 7 + #5; + start = 1; + #(2*PERIOD); + start = 0; + @(negedge booth_multiplier_leds_tb.DUT.booth_multiplier_leds_i.control_unit_eq); + @(posedge sys_clock); + multiplier_in = 8'b11111100; // -4 + multiplicand_in = 8'b00000111; // 7 + #5; + start = 1; + #(2*PERIOD); + start = 0; + @(negedge booth_multiplier_leds_tb.DUT.booth_multiplier_leds_i.control_unit_eq); + @(posedge sys_clock); + $stop; + end +endmodule diff --git a/Projects/Logic_Design/SN_Design/booth_multiplier_leds/src/booth_multiplier_leds_tb_behav.wcfg b/Projects/Logic_Design/SN_Design/booth_multiplier_leds/src/booth_multiplier_leds_tb_behav.wcfg new file mode 100644 index 0000000..adaf990 --- /dev/null +++ b/Projects/Logic_Design/SN_Design/booth_multiplier_leds/src/booth_multiplier_leds_tb_behav.wcfg @@ -0,0 +1,37 @@ + + + + + + + + + + + + + + + sys_clock + sys_clock + + + start + start + + + multiplier_in[7:0] + multiplier_in[7:0] + SIGNEDDECRADIX + + + multiplicand_in[7:0] + multiplicand_in[7:0] + SIGNEDDECRADIX + + + result[15:0] + result[15:0] + SIGNEDDECRADIX + + diff --git a/Projects/Logic_Design/SN_Design/digital_clock/README.md b/Projects/Logic_Design/SN_Design/digital_clock/README.md new file mode 100644 index 0000000..e3119c6 --- /dev/null +++ b/Projects/Logic_Design/SN_Design/digital_clock/README.md @@ -0,0 +1,40 @@ +# Digital Clock +This project is about creating a digital clock showing MM.SS using XUP_LIB components. You must download the XUP_LIB directory from the GitHub and then set the XUP_LIB path. You must also download Basys3 board files directory from the GitHub and place it in the **\\2014.4\data\boards\board_parts\artix7** directory. + +The project source files provide Tcl script, and a Xilinx Design Constraint (xdc) file targeting Basys3 board. + +### Design Description: +The digital clock is built using counters, comparators, concat, bin2bcd, and 7-segment display IPs available in XUP_LIB and Vivado's standard installation directory. It also uses clocking wizard to generate 5 MHz clock from on-board 100 MHz clock source. The generated 5 MHz clock is further divided to generate 1 Hz clock signal. There are two counters and two 7-segment display instances, one set for seconds and another for the minutes. Since the board only has 4 7-segment displays, hours are not displayed. One can extend the design by displaying hours on LEDs. + +### Tools and other requirements: +* Vivado 2014.4 +* XUP_LIB from GitHub +* Basys3 board files from GitHub + +### Procedure: +Execute the commands **in bold** in the tcl console + +1\. Start Vivado in a GUI mode + +2\. Set the path *basys3_github* to the XUP_LIB using command like in the Vivado Tcl Console. Note the path uses "/" instead of "\". Substiture the path where you have stored the XUP_LIB library. + +**set basys3_github {C:/xup/IPI_LIB/XUP_LIB}** + +3\. Change to the *src* directory of this project directory using the cd command, keeping in mind to use "/" instead of "\" in the directory + +**cd \** + +4\. Next, execute the following command to run the script + +**source ./digital_clock.tcl** + +5\. Once the project is created, the resulting block diagram will be displayed. View through the block diagram, its hierarchy and analyze the design + +6\. Generate the bitstream by clicking on the Generate Bitstream under the Program and Debug group. A warning message box will appear. Click OK to ignore it + +7\. When the bitstream generation is completed, connect the board, power ON the board, and use the Open Hardware Manager option to connect to the board + +8\. Program the board and verify the functionality + +Input : Center button to reset the clock. Keep it pressed for about 1 second +Output : 4 7-segments module diff --git a/Projects/Logic_Design/SN_Design/digital_clock/src/digital_clock.tcl b/Projects/Logic_Design/SN_Design/digital_clock/src/digital_clock.tcl new file mode 100644 index 0000000..0be4240 --- /dev/null +++ b/Projects/Logic_Design/SN_Design/digital_clock/src/digital_clock.tcl @@ -0,0 +1,132 @@ +# Script to create a digital clock showing MM:SS using XUP_LIB components. Set XUP_LIB path below before running +# +# The digital clock is built using counters, comparators, concat, # bin2bcd, and 7-segment display IPs available in XUP_LIB and +# Vivado's standard installation directory. It also uses clocking # wizard to generate 5 MHz clock from on-board 100 MHz clock +# source. The generated 5 MHz clock is further divided to +# generate 1 Hz clock signal. There are two counters and two 7- +# segment display instances, one set for seconds and another for +# the minutes. Since the board only has 4 7-segment displays, +# hours are not displayed. One can extend the design by +# displaying hours on LEDs. +# +# Vivado 2014.4 +# Basys 3 board +# 29 May 2015 +# Notes: Set the path below to the XUP_LIB, and run source digital_clock.tcl to create the design +# It is assumed the pin constraints xdc file (digital_clock_basys3_pins.xdc) is in the project directory. +# If the constraints file is located somewhere else, modify the constraints_directory path below +# +# The reset is connected to the center button +# The output is displayed on the four 7-segment module +# -------------------------------------------------------------- # +# SET 'basys3_github' PATH TO GITHUB LIBRARY BEFORE RUNNING +# -------------------------------------------------------------- # +set basys3_github {C:/xup/IPI_LIB/XUP_LIB} +set project_directory . +set project_name digital_clock +set constraints_directory $project_directory +set constraints_file digital_clock_basys3_pins.xdc +# Create project for Basys 3 +create_project -force $project_name ./$project_name -part xc7a35tcpg236-1 +set_property board_part digilentinc.com:basys3:part0:1.1 [current_project] +set_property target_language verilog [current_project] +set_property simulator_language Verilog [current_project] +set_property ip_repo_paths $basys3_github [current_project] +update_ip_catalog +create_bd_design "$project_name" +# instantiate counter, comparator, and associated logic for the seconds and connect them +create_bd_cell -type ip -vlnv xilinx.com:XUP:counters:1.0 counters_0 +set_property -dict [list CONFIG.COUNT_SIZE {6}] [get_bd_cells counters_0] +create_bd_cell -type ip -vlnv xilinx.com:XUP:xup_range_comparator:1.0 xup_range_comparator_0 +set_property -dict [list CONFIG.SIZE {6}] [get_bd_cells xup_range_comparator_0] +connect_bd_net [get_bd_pins counters_0/bin_count] [get_bd_pins xup_range_comparator_0/in1] +create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 xlconstant_0 +set_property -dict [list CONFIG.CONST_WIDTH {6} CONFIG.CONST_VAL {59}] [get_bd_cells xlconstant_0] +connect_bd_net [get_bd_pins xlconstant_0/dout] [get_bd_pins xup_range_comparator_0/in2] +create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 xlconstant_1 +set_property -dict [list CONFIG.CONST_VAL {0}] [get_bd_cells xlconstant_1] +connect_bd_net [get_bd_pins xlconstant_1/dout] [get_bd_pins xup_range_comparator_0/sign] +create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 xlconstant_2 +connect_bd_net [get_bd_pins xlconstant_2/dout] [get_bd_pins counters_0/enable] +connect_bd_net -net [get_bd_nets xlconstant_2_dout] [get_bd_pins counters_0/up_dn] [get_bd_pins xlconstant_2/dout] +# instantiate clocking wizard and configure it to generate 5 MHz clock. Connect its input to the input port using the run_connection wizard +create_bd_cell -type ip -vlnv xilinx.com:ip:clk_wiz:5.1 clk_wiz_0 +set_property -dict [list CONFIG.CLKOUT2_USED {true} CONFIG.CLKOUT2_REQUESTED_OUT_FREQ {5.000} CONFIG.USE_LOCKED {false} CONFIG.USE_RESET {false} CONFIG.MMCM_CLKFBOUT_MULT_F {6.250} CONFIG.MMCM_CLKOUT0_DIVIDE_F {6.250} CONFIG.MMCM_CLKOUT1_DIVIDE {125} CONFIG.NUM_OUT_CLKS {2} CONFIG.CLKOUT1_JITTER {148.376} CONFIG.CLKOUT1_PHASE_ERROR {128.132} CONFIG.CLKOUT2_JITTER {270.159} CONFIG.CLKOUT2_PHASE_ERROR {128.132}] [get_bd_cells clk_wiz_0] +apply_bd_automation -rule xilinx.com:bd_rule:board -config {Board_Interface "sys_clock" } [get_bd_pins clk_wiz_0/clk_in1] +# add vivado IPI binary counter as it provides larger size counter. Add comparator and set its value to generate 1 Hz. Add associated logic and connect them +create_bd_cell -type ip -vlnv xilinx.com:ip:c_counter_binary:12.0 c_counter_binary_0 +set_property -dict [list CONFIG.Implementation {DSP48} CONFIG.Output_Width {23} CONFIG.Restrict_Count {true} CONFIG.Final_Count_Value {4C4B40}] [get_bd_cells c_counter_binary_0] +create_bd_cell -type ip -vlnv xilinx.com:XUP:xup_range_comparator:1.0 xup_range_comparator_1 +set_property -dict [list CONFIG.SIZE {23}] [get_bd_cells xup_range_comparator_1] +connect_bd_net [get_bd_pins c_counter_binary_0/Q] [get_bd_pins xup_range_comparator_1/in1] +connect_bd_net [get_bd_pins clk_wiz_0/clk_out2] [get_bd_pins c_counter_binary_0/CLK] +create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 xlconstant_3 +set_property -dict [list CONFIG.CONST_WIDTH {23} CONFIG.CONST_VAL {5000000}] [get_bd_cells xlconstant_3] +connect_bd_net [get_bd_pins xlconstant_3/dout] [get_bd_pins xup_range_comparator_1/in2] +connect_bd_net -net [get_bd_nets xlconstant_1_dout] [get_bd_pins xup_range_comparator_1/sign] [get_bd_pins xlconstant_1/dout] +connect_bd_net [get_bd_pins xup_range_comparator_1/eq] [get_bd_pins counters_0/clk] +# add a 7-segment display for seconds and wire it up +create_bd_cell -type ip -vlnv xilinx.com:XUP:seg7display:1.0 seg7display_0 +set_property -dict [list CONFIG.DP_0 {0} CONFIG.DP_1 {0} CONFIG.DP_3 {0}] [get_bd_cells seg7display_0] +connect_bd_net [get_bd_pins seg7display_0/clk] [get_bd_pins clk_wiz_0/clk_out1] +create_bd_port -dir I -type rst reset +connect_bd_net [get_bd_pins /seg7display_0/reset] [get_bd_ports reset] +create_bd_cell -type ip -vlnv xilinx.com:XUP:bin2bcd:1.0 bin2bcd_0 +# set the size +set_property -dict [list CONFIG.SIZE {6}] [get_bd_cells bin2bcd_0] +# add a counter and 7-segment display for the minutes and wire it up +create_bd_cell -type ip -vlnv xilinx.com:XUP:counters:1.0 counters_1 +set_property -dict [list CONFIG.COUNT_SIZE {6}] [get_bd_cells counters_1] +create_bd_cell -type ip -vlnv xilinx.com:XUP:bin2bcd:1.0 bin2bcd_1 +set_property -dict [list CONFIG.SIZE {6}] [get_bd_cells bin2bcd_1] +connect_bd_net [get_bd_pins counters_0/bin_count] [get_bd_pins bin2bcd_0/a_in] +connect_bd_net [get_bd_pins counters_1/bin_count] [get_bd_pins bin2bcd_1/a_in] +connect_bd_net -net [get_bd_nets xlconstant_2_dout] [get_bd_pins counters_1/up_dn] [get_bd_pins xlconstant_2/dout] +connect_bd_net -net [get_bd_nets xlconstant_2_dout] [get_bd_pins counters_1/enable] [get_bd_pins xlconstant_2/dout] +create_bd_cell -type ip -vlnv xilinx.com:XUP:xup_range_comparator:1.0 xup_range_comparator_2 +set_property -dict [list CONFIG.SIZE {6}] [get_bd_cells xup_range_comparator_2] +connect_bd_net -net [get_bd_nets xlconstant_1_dout] [get_bd_pins xup_range_comparator_2/sign] [get_bd_pins xlconstant_1/dout] +create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 xlconstant_4 +set_property -dict [list CONFIG.CONST_WIDTH {6} CONFIG.CONST_VAL {59}] [get_bd_cells xlconstant_4] +connect_bd_net [get_bd_pins xlconstant_4/dout] [get_bd_pins xup_range_comparator_2/in2] +connect_bd_net -net [get_bd_nets counters_1_bin_count] [get_bd_pins xup_range_comparator_2/in1] [get_bd_pins counters_1/bin_count] +# Add concat IP, set it to 4 ports and connect ones and tens of both seconds and minutes bin2bcd instances +create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 xlconcat_0 +set_property -dict [list CONFIG.NUM_PORTS {4}] [get_bd_cells xlconcat_0] +connect_bd_net [get_bd_pins bin2bcd_0/ones] [get_bd_pins xlconcat_0/In0] +connect_bd_net [get_bd_pins bin2bcd_0/tens] [get_bd_pins xlconcat_0/In1] +connect_bd_net [get_bd_pins bin2bcd_1/ones] [get_bd_pins xlconcat_0/In2] +connect_bd_net [get_bd_pins bin2bcd_1/tens] [get_bd_pins xlconcat_0/In3] +connect_bd_net [get_bd_pins xlconcat_0/dout] [get_bd_pins seg7display_0/x_l] +# create reset for minutes +create_bd_cell -type ip -vlnv xilinx.com:XUP:xup_and2:1.0 xup_and2_0 +connect_bd_net [get_bd_pins xup_and2_0/a] [get_bd_pins xup_range_comparator_0/eq] +connect_bd_net [get_bd_pins xup_and2_0/b] [get_bd_pins xup_range_comparator_2/eq] +create_bd_cell -type ip -vlnv xilinx.com:XUP:xup_or2:1.0 xup_or2_0 +create_bd_cell -type ip -vlnv xilinx.com:XUP:xup_or2:1.0 xup_or2_1 +connect_bd_net [get_bd_pins xup_or2_1/y] [get_bd_pins counters_1/clr] +connect_bd_net [get_bd_pins xup_and2_0/y] [get_bd_pins xup_or2_1/a] +connect_bd_net [get_bd_pins xup_or2_0/y] [get_bd_pins counters_0/clr] +connect_bd_net -net [get_bd_nets xup_range_comparator_0_eq] [get_bd_pins xup_or2_0/a] [get_bd_pins xup_range_comparator_0/eq] +connect_bd_net -net [get_bd_nets reset_1] [get_bd_ports reset] [get_bd_pins xup_or2_1/b] +connect_bd_net -net [get_bd_nets reset_1] [get_bd_ports reset] [get_bd_pins xup_or2_0/b] + +create_bd_cell -type ip -vlnv xilinx.com:XUP:xup_dff:1.0 xup_dff_0 +connect_bd_net -net [get_bd_nets xup_range_comparator_0_eq] [get_bd_pins xup_dff_0/d] [get_bd_pins xup_range_comparator_0/eq] +connect_bd_net -net [get_bd_nets xup_range_comparator_1_eq] [get_bd_pins xup_dff_0/clk] [get_bd_pins xup_range_comparator_1/eq] +connect_bd_net [get_bd_pins xup_dff_0/q] [get_bd_pins counters_1/clk] +create_bd_port -dir O -from 6 -to 0 a_to_g +connect_bd_net [get_bd_pins /seg7display_0/a_to_g] [get_bd_ports a_to_g] +create_bd_port -dir O -from 3 -to 0 an_l +connect_bd_net [get_bd_pins /seg7display_0/an_l] [get_bd_ports an_l] +create_bd_port -dir O dp_l +connect_bd_net [get_bd_pins /seg7display_0/dp_l] [get_bd_ports dp_l] +set_property name seg [get_bd_ports a_to_g] +set_property name an [get_bd_ports an_l] +set_property name dp [get_bd_ports dp_l] +validate_bd_design +save_bd_design +make_wrapper -files [get_files $project_directory/$project_name/$project_name.srcs/sources_1/bd/$project_name/$project_name.bd] -top +add_files -norecurse $project_directory/$project_name/$project_name.srcs/sources_1/bd/$project_name/hdl/$project_name\_wrapper.v +# Add pin constraints +add_files -fileset constrs_1 -norecurse $constraints_directory/$constraints_file diff --git a/Projects/Logic_Design/SN_Design/digital_clock/src/digital_clock_basys3_pins.xdc b/Projects/Logic_Design/SN_Design/digital_clock/src/digital_clock_basys3_pins.xdc new file mode 100644 index 0000000..1a4cf14 --- /dev/null +++ b/Projects/Logic_Design/SN_Design/digital_clock/src/digital_clock_basys3_pins.xdc @@ -0,0 +1,37 @@ +#Pin constraints for Digital Clock design for Basys 3 +## Clock signal +set_property PACKAGE_PIN W5 [get_ports sys_clock] +set_property IOSTANDARD LVCMOS33 [get_ports sys_clock] +create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports sys_clock] + +# pushbutton BtnC +set_property PACKAGE_PIN U18 [get_ports {reset}] +set_property IOSTANDARD LVCMOS33 [get_ports {reset}] + +##7 segment display +set_property PACKAGE_PIN W7 [get_ports {seg[0]}] +set_property IOSTANDARD LVCMOS33 [get_ports {seg[0]}] +set_property PACKAGE_PIN W6 [get_ports {seg[1]}] +set_property IOSTANDARD LVCMOS33 [get_ports {seg[1]}] +set_property PACKAGE_PIN U8 [get_ports {seg[2]}] +set_property IOSTANDARD LVCMOS33 [get_ports {seg[2]}] +set_property PACKAGE_PIN V8 [get_ports {seg[3]}] +set_property IOSTANDARD LVCMOS33 [get_ports {seg[3]}] +set_property PACKAGE_PIN U5 [get_ports {seg[4]}] +set_property IOSTANDARD LVCMOS33 [get_ports {seg[4]}] +set_property PACKAGE_PIN V5 [get_ports {seg[5]}] +set_property IOSTANDARD LVCMOS33 [get_ports {seg[5]}] +set_property PACKAGE_PIN U7 [get_ports {seg[6]}] +set_property IOSTANDARD LVCMOS33 [get_ports {seg[6]}] + +set_property PACKAGE_PIN V7 [get_ports dp] +set_property IOSTANDARD LVCMOS33 [get_ports dp] + +set_property PACKAGE_PIN U2 [get_ports {an[0]}] +set_property IOSTANDARD LVCMOS33 [get_ports {an[0]}] +set_property PACKAGE_PIN U4 [get_ports {an[1]}] +set_property IOSTANDARD LVCMOS33 [get_ports {an[1]}] +set_property PACKAGE_PIN V4 [get_ports {an[2]}] +set_property IOSTANDARD LVCMOS33 [get_ports {an[2]}] +set_property PACKAGE_PIN W4 [get_ports {an[3]}] +set_property IOSTANDARD LVCMOS33 [get_ports {an[3]}] diff --git a/Projects/Logic_Design/SN_Design/division_7seg/README.md b/Projects/Logic_Design/SN_Design/division_7seg/README.md new file mode 100644 index 0000000..367f935 --- /dev/null +++ b/Projects/Logic_Design/SN_Design/division_7seg/README.md @@ -0,0 +1,44 @@ +# Division_7Seg +This project is about creating an 8-bit by 8-bit unsigned divider using non-restoring algorithm and displaying the result on the 7-segment modules using XUP_LIB components. You must download the XUP_LIB directory from the GitHub and then set the XUP_LIB path. You must also download Basys3 board files directory from the GitHub and place it in the **\\2014.4\data\boards\board_parts\artix7** directory. + +The project source files provide Tcl script, and a Xilinx Design Constraint (xdc) file targeting Basys3 board. + +### Design Description: +The design is built using counter, comparators, concat, adder/subtractor, d-ffs, slice, or, xor, shift, multiplexors, bin2bcd, and 7-segment display IPs available in XUP_LIB and Vivado's standard installation directory. It uses on-board 100 MHz clock source. The unsigned quotient is displayed on the two left-most 7-segment modules, the unsigned remainder is displayed on the two right-most modules (both in BCD format) and the done status is indicated on the LED15. + +### Tools and other requirements: +* Vivado 2014.4 +* XUP_LIB from GitHub +* Basys3 board files from GitHub + +### Procedure: +Execute the commands **in bold** in the tcl console + +1\. Start Vivado in a GUI mode + +2\. Set the path *basys3_github* to the XUP_LIB using command like in the Vivado Tcl Console. Note the path uses "/" instead of "\". Substiture the path where you have stored the XUP_LIB library. + +**set basys3_github {C:/xup/IPI_LIB/XUP_LIB}** + +3\. Change to the *src* directory of this project directory using the cd command, keeping in mind to use "/" instead of "\" in the directory + +**cd \** + +4\. Next, execute the following command to run the script + +**source ./division_7seg.tcl** + +5\. Once the project is created, the resulting block diagram will be displayed. View through the block diagram, its hierarchy and analyze the design + +6\. Generate the bitstream by clicking on the Generate Bitstream under the Program and Debug group. + +7\. When the bitstream generation is completed, connect the board, power ON the board, and use the Open Hardware Manager option to connect to the board + +8\. Program the board and verify the functionality + +Input : SW15-SW8 for the divisot + SW7-SW0 for the dividend + Center button to start the computation +Output : Two left-most 7-segments modules showing unsigned quotient and the two right-most 7-segment modules showing unsigned remainder (both in BCD format) + LED15 showing the done status of the computation + diff --git a/Projects/Logic_Design/SN_Design/division_7seg/src/division_7seg.tcl b/Projects/Logic_Design/SN_Design/division_7seg/src/division_7seg.tcl new file mode 100644 index 0000000..95f3dc9 --- /dev/null +++ b/Projects/Logic_Design/SN_Design/division_7seg/src/division_7seg.tcl @@ -0,0 +1,215 @@ +# Script to create an 8-bit by 8-bit non-restoring divider using XUP_LIB components. +# Set XUP_LIB path below before running +# +# Vivado 2014.4 +# Basys 3 board +# 19 June 2015 +# Notes: Set the path below to the XUP_LIB, and run source division_7seg.tcl to create the design +# It is assumed the pin constraints xdc file (division_7seg_basys3_pins.xdc) is in the project directory. +# If the constraints file is located somewhere else, modify the constraints_directory path below +# +# +# The 8-bit dividend is input through sw7-sw0 and the 8-bit divisor is input through sw15-sw8. +# The division process starts by pressing BtnC +# The 8-bit quotient in BCD output is displayed on left two 7-segments whereas the 8-bit remainder in BCD is displayed on the right two 7-segments. The done flag is displayed on the LED15 +# +# -------------------------------------------------------------- # +# SET 'basys3_github' PATH TO GITHUB LIBRARY BEFORE RUNNING +# -------------------------------------------------------------- # +set basys3_github {C:/xup/IPI_LIB/XUP_LIB} + +set project_directory . +set project_name division_7seg +set constraints_directory $project_directory +set constraints_file division_7seg_basys3_pins.xdc + +# Create project for Basys 3 +create_project -force $project_name ./$project_name -part xc7a35tcpg236-1 +set_property board_part digilentinc.com:basys3:part0:1.1 [current_project] +set_property target_language verilog [current_project] +set_property simulator_language Verilog [current_project] +set_property ip_repo_paths $basys3_github [current_project] +update_ip_catalog +create_bd_design "$project_name" + +# Steps: +# Create a control unit +# Add a divisor +# Add an accumulator +# Add dividend +# Form AQ +# Add shift_nbit +# Slice AQ shifter output and connect +# Create A_Sign +# Add Adder/Subtractor +# Create Addsub_sign +# Create dividend input path +# create Quotient_register and connect to Quotient port +# Create restore stage and connect the output to Remainder port +# Create done_flag +# Create 7-seg display circuit + +# create a control unit +create_bd_port -dir I -type clk sys_clock +set_property CONFIG.FREQ_HZ 100000000 [get_bd_ports sys_clock] +create_bd_port -dir I -from 7 -to 0 -type data divisor_in +create_bd_port -dir I -from 7 -to 0 -type data dividend_in +create_bd_port -dir I -type data start +create_bd_port -dir O -type other done +create_bd_cell -type ip -vlnv xilinx.com:XUP:counters:1.0 counters_0 +set_property name div_ctr [get_bd_cells counters_0] +set_property -dict [list CONFIG.COUNT_SIZE {4}] [get_bd_cells div_ctr] +connect_bd_net [get_bd_ports sys_clock] [get_bd_pins div_ctr/clk] +create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 xlconstant_0 +set_property name logic_1 [get_bd_cells xlconstant_0] +connect_bd_net [get_bd_pins logic_1/dout] [get_bd_pins div_ctr/up_dn] +connect_bd_net [get_bd_ports start] [get_bd_pins div_ctr/clr] +create_bd_cell -type ip -vlnv xilinx.com:XUP:xup_range_comparator:1.0 xup_range_comparator_0 +set_property name count_lt_8 [get_bd_cells xup_range_comparator_0] +create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 xlconstant_0 +set_property name logic_0 [get_bd_cells xlconstant_0] +set_property -dict [list CONFIG.CONST_VAL {0}] [get_bd_cells logic_0] +connect_bd_net [get_bd_pins logic_0/dout] [get_bd_pins count_lt_8/sign] +create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 xlconstant_0 +set_property name const_7 [get_bd_cells xlconstant_0] +set_property -dict [list CONFIG.CONST_WIDTH {4} CONFIG.CONST_VAL {7}] [get_bd_cells const_7] +connect_bd_net [get_bd_pins const_7/dout] [get_bd_pins count_lt_8/in2] +connect_bd_net [get_bd_pins count_lt_8/in1] [get_bd_pins div_ctr/bin_count] +connect_bd_net [get_bd_pins count_lt_8/le] [get_bd_pins div_ctr/enable] +group_bd_cells control_unit [get_bd_cells const_7] [get_bd_cells count_lt_8] [get_bd_cells div_ctr] +# Add divisor +create_bd_cell -type ip -vlnv xilinx.com:XUP:xup_dff_en_vector:1.0 xup_dff_en_vector_0 +set_property name divisor [get_bd_cells xup_dff_en_vector_0] +set_property -dict [list CONFIG.SIZE {8}] [get_bd_cells divisor ] +connect_bd_net [get_bd_ports divisor_in] [get_bd_pins divisor/d] +connect_bd_net -net [get_bd_nets start_1] [get_bd_ports start] [get_bd_pins divisor/en] +connect_bd_net -net [get_bd_nets sys_clock_1] [get_bd_ports sys_clock] [get_bd_pins divisor/clk] +# Add an accumulator +create_bd_cell -type ip -vlnv xilinx.com:XUP:xup_dff_en_reset_vector:1.0 xup_dff_en_reset_vector_0 +set_property name accumulator [get_bd_cells xup_dff_en_reset_vector_0] +set_property -dict [list CONFIG.SIZE {8}] [get_bd_cells accumulator] +connect_bd_net -net [get_bd_nets start_1] [get_bd_ports start] [get_bd_pins accumulator/reset] +connect_bd_net [get_bd_pins accumulator/en] [get_bd_pins control_unit/count_lt_8/le] +connect_bd_net -net [get_bd_nets sys_clock_1] [get_bd_ports sys_clock] [get_bd_pins accumulator/clk] +# Add dividend +create_bd_cell -type ip -vlnv xilinx.com:XUP:xup_dff_en_vector:1.0 xup_dff_en_vector_0 +set_property name dividend [get_bd_cells xup_dff_en_vector_0] +set_property -dict [list CONFIG.SIZE {8}] [get_bd_cells dividend] +connect_bd_net -net [get_bd_nets sys_clock_1] [get_bd_ports sys_clock] [get_bd_pins dividend/clk] +connect_bd_net -net [get_bd_nets control_unit_le] [get_bd_pins dividend/en] [get_bd_pins control_unit/le] +# Form AQ +create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 xlconcat_0 +set_property name AQ [get_bd_cells xlconcat_0] +connect_bd_net [get_bd_pins accumulator/q] [get_bd_pins AQ/In1] +connect_bd_net [get_bd_pins dividend/q] [get_bd_pins AQ/In0] +# Add shift_nbit +create_bd_cell -type ip -vlnv xilinx.com:XUP:xup_shift_nbit:1.0 xup_shift_nbit_0 +set_property name AQ_shift [get_bd_cells xup_shift_nbit_0] +set_property -dict [list CONFIG.SIZE {16} CONFIG.DIR {true}] [get_bd_cells AQ_shift] +connect_bd_net [get_bd_pins AQ/dout] [get_bd_pins AQ_shift/parallel_in] +connect_bd_net -net [get_bd_nets logic_1_dout] [get_bd_pins AQ_shift/dir] [get_bd_pins logic_1/dout] +# Slice AQ shifter output and connect +create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 xlslice_0 +set_property name AQ_shift_slice_A [get_bd_cells xlslice_0] +set_property -dict [list CONFIG.DIN_WIDTH {16} CONFIG.DIN_TO {8} CONFIG.DIN_FROM {15} CONFIG.DOUT_WIDTH {8}] [get_bd_cells AQ_shift_slice_A] +create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 xlslice_0 +set_property name AQ_shift_slice_Q [get_bd_cells xlslice_0] +set_property -dict [list CONFIG.DIN_WIDTH {16} CONFIG.DIN_TO {1} CONFIG.DIN_FROM {7} CONFIG.DOUT_WIDTH {7}] [get_bd_cells AQ_shift_slice_Q] +connect_bd_net [get_bd_pins AQ_shift/parallel_out] [get_bd_pins AQ_shift_slice_Q/Din] +connect_bd_net -net [get_bd_nets AQ_shift_parallel_out] [get_bd_pins AQ_shift_slice_A/Din] [get_bd_pins AQ_shift/parallel_out] +# Create A_Sign +create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 xlslice_0 +set_property name A_sign [get_bd_cells xlslice_0] +set_property -dict [list CONFIG.DIN_WIDTH {8} CONFIG.DIN_TO {7} CONFIG.DIN_FROM {7} CONFIG.DOUT_WIDTH {1}] [get_bd_cells A_sign] +connect_bd_net -net [get_bd_nets accumulator_q] [get_bd_pins A_sign/Din] [get_bd_pins accumulator/q] +# Add Adder/Subtractor +create_bd_cell -type ip -vlnv xilinx.com:ip:c_addsub:12.0 c_addsub_0 +set_property name addsub [get_bd_cells c_addsub_0] +set_property -dict [list CONFIG.B_Width.VALUE_SRC USER CONFIG.A_Width.VALUE_SRC USER] [get_bd_cells addsub] +set_property -dict [list CONFIG.A_Width {8} CONFIG.B_Width {8} CONFIG.Add_Mode {Add_Subtract} CONFIG.Latency {0} CONFIG.Out_Width {8} CONFIG.B_Value {00000000} CONFIG.CE {false}] [get_bd_cells addsub] +connect_bd_net [get_bd_pins addsub/A] [get_bd_pins AQ_shift_slice_A/Dout] +connect_bd_net [get_bd_pins divisor/q] [get_bd_pins addsub/B] +connect_bd_net [get_bd_pins A_sign/Dout] [get_bd_pins addsub/ADD] +connect_bd_net [get_bd_pins addsub/S] [get_bd_pins accumulator/d] +# Create Addsub_sign +create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 xlslice_0 +set_property name addsub_sign [get_bd_cells xlslice_0] +set_property -dict [list CONFIG.DIN_WIDTH {8} CONFIG.DIN_TO {7} CONFIG.DIN_FROM {7} CONFIG.DOUT_WIDTH {1}] [get_bd_cells addsub_sign] +connect_bd_net -net [get_bd_nets addsub_S] [get_bd_pins addsub_sign/Din] [get_bd_pins addsub/S] +# Create dividend input path +create_bd_cell -type ip -vlnv xilinx.com:XUP:xup_inv:1.0 xup_inv_0 +connect_bd_net [get_bd_pins addsub_sign/Dout] [get_bd_pins xup_inv_0/a] +create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 xlconcat_0 +set_property name Q_in [get_bd_cells xlconcat_0] +connect_bd_net [get_bd_pins xup_inv_0/y] [get_bd_pins Q_in/In0] +connect_bd_net [get_bd_pins AQ_shift_slice_Q/Dout] [get_bd_pins Q_in/In1] +create_bd_cell -type ip -vlnv xilinx.com:XUP:xup_2_to_1_mux_vector:1.0 xup_2_to_1_mux_vector_0 +set_property name dividend_data_in [get_bd_cells xup_2_to_1_mux_vector_0] +set_property -dict [list CONFIG.SIZE {8}] [get_bd_cells dividend_data_in] +connect_bd_net [get_bd_pins Q_in/dout] [get_bd_pins dividend_data_in/a] +connect_bd_net [get_bd_ports dividend_in] [get_bd_pins dividend_data_in/b] +connect_bd_net -net [get_bd_nets start_1] [get_bd_ports start] [get_bd_pins dividend_data_in/sel] +connect_bd_net [get_bd_pins dividend_data_in/y] [get_bd_pins dividend/d] +# create Quotient_register and connect to Quotient port +create_bd_cell -type ip -vlnv xilinx.com:XUP:xup_dff_en_vector:1.0 xup_dff_en_vector_0 +set_property name Quotient_register [get_bd_cells xup_dff_en_vector_0] +set_property -dict [list CONFIG.SIZE {8}] [get_bd_cells Quotient_register] +connect_bd_net -net [get_bd_nets sys_clock_1] [get_bd_ports sys_clock] [get_bd_pins Quotient_register/clk] +connect_bd_net -net [get_bd_nets dividend_q] [get_bd_pins Quotient_register/d] [get_bd_pins dividend/q] +# Create restore stage and connect the output to Remainder port +create_bd_cell -type ip -vlnv xilinx.com:ip:c_addsub:12.0 c_addsub_1 +set_property name restore_stage [get_bd_cells c_addsub_1] +set_property -dict [list CONFIG.B_Width.VALUE_SRC USER CONFIG.A_Width.VALUE_SRC USER] [get_bd_cells restore_stage] +set_property -dict [list CONFIG.A_Width {8} CONFIG.B_Width {8} CONFIG.Add_Mode {Add} CONFIG.Latency {0} CONFIG.Out_Width {8} CONFIG.B_Value {00000000} CONFIG.CE {false}] [get_bd_cells restore_stage] +connect_bd_net -net [get_bd_nets accumulator_q] [get_bd_pins restore_stage/A] [get_bd_pins accumulator/q] +connect_bd_net -net [get_bd_nets divisor_q] [get_bd_pins restore_stage/B] [get_bd_pins divisor/q] +create_bd_cell -type ip -vlnv xilinx.com:XUP:xup_2_to_1_mux_vector:1.0 xup_2_to_1_mux_vector_0 +set_property name remainder_sel [get_bd_cells xup_2_to_1_mux_vector_0] +set_property -dict [list CONFIG.SIZE {8}] [get_bd_cells remainder_sel] +connect_bd_net -net [get_bd_nets accumulator_q] [get_bd_pins remainder_sel/a] [get_bd_pins accumulator/q] +connect_bd_net [get_bd_pins remainder_sel/b] [get_bd_pins restore_stage/S] +connect_bd_net -net [get_bd_nets A_sign_Dout] [get_bd_pins remainder_sel/sel] [get_bd_pins A_sign/Dout] + +# Create done_flag +create_bd_cell -type ip -vlnv xilinx.com:XUP:xup_dff_en_reset:1.0 xup_dff_en_reset_0 +set_property name done_f [get_bd_cells xup_dff_en_reset_0] +connect_bd_net [get_bd_pins done_f/q] [get_bd_pins Quotient_register/en] +connect_bd_net -net [get_bd_nets done_f_q] [get_bd_ports done] [get_bd_pins done_f/q] +connect_bd_net -net [get_bd_nets sys_clock_1] [get_bd_ports sys_clock] [get_bd_pins done_f/clk] +connect_bd_net -net [get_bd_nets logic_1_dout] [get_bd_pins done_f/d] [get_bd_pins logic_1/dout] +connect_bd_net [get_bd_pins done_f/en] [get_bd_pins control_unit/count_lt_8/eq] +connect_bd_net -net [get_bd_nets start_1] [get_bd_ports start] [get_bd_pins done_f/reset] +# Create 7-seg display circuit +create_bd_cell -type ip -vlnv xilinx.com:XUP:bin2bcd:1.0 bin2bcd_0 +set_property name Quotient_bcd [get_bd_cells bin2bcd_0] +create_bd_cell -type ip -vlnv xilinx.com:XUP:bin2bcd:1.0 bin2bcd_0 +set_property name Remainder_bcd [get_bd_cells bin2bcd_0] +connect_bd_net [get_bd_pins Quotient_register/q] [get_bd_pins Quotient_bcd/a_in] +connect_bd_net [get_bd_pins remainder_sel/y] [get_bd_pins Remainder_bcd/a_in] +create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 xlconcat_0 +set_property -dict [list CONFIG.NUM_PORTS {4}] [get_bd_cells xlconcat_0] +connect_bd_net [get_bd_pins Quotient_bcd/ones] [get_bd_pins xlconcat_0/In2] +connect_bd_net [get_bd_pins Quotient_bcd/tens] [get_bd_pins xlconcat_0/In3] +connect_bd_net [get_bd_pins Remainder_bcd/ones] [get_bd_pins xlconcat_0/In0] +connect_bd_net [get_bd_pins Remainder_bcd/tens] [get_bd_pins xlconcat_0/In1] +create_bd_cell -type ip -vlnv xilinx.com:XUP:seg7display:1.0 seg7display_0 +connect_bd_net -net [get_bd_nets sys_clock_1] [get_bd_ports sys_clock] [get_bd_pins seg7display_0/clk] +connect_bd_net [get_bd_pins seg7display_0/x_l] [get_bd_pins xlconcat_0/dout] +connect_bd_net -net [get_bd_nets start_1] [get_bd_ports start] [get_bd_pins seg7display_0/reset] +set_property -dict [list CONFIG.DP_0 {0} CONFIG.DP_1 {0} CONFIG.DP_2 {0} CONFIG.DP_3 {0}] [get_bd_cells seg7display_0] +create_bd_port -dir O -from 6 -to 0 a_to_g +connect_bd_net [get_bd_pins /seg7display_0/a_to_g] [get_bd_ports a_to_g] +create_bd_port -dir O -from 3 -to 0 an_l +connect_bd_net [get_bd_pins /seg7display_0/an_l] [get_bd_ports an_l] +set_property name seg [get_bd_ports a_to_g] +set_property name an [get_bd_ports an_l] + +# Regerate the layout and save it +regenerate_bd_layout +save_bd_design +# Create top HDL wrapper +make_wrapper -files [get_files $project_directory/$project_name/$project_name.srcs/sources_1/bd/$project_name/$project_name.bd] -top +add_files -norecurse $project_directory/$project_name/$project_name.srcs/sources_1/bd/$project_name/hdl/$project_name\_wrapper.v +# Add pin constraints +add_files -fileset constrs_1 -norecurse $constraints_directory/$constraints_file + diff --git a/Projects/Logic_Design/SN_Design/division_7seg/src/division_7seg_basys3_pins.xdc b/Projects/Logic_Design/SN_Design/division_7seg/src/division_7seg_basys3_pins.xdc new file mode 100644 index 0000000..cac4e9a --- /dev/null +++ b/Projects/Logic_Design/SN_Design/division_7seg/src/division_7seg_basys3_pins.xdc @@ -0,0 +1,62 @@ +#Pin constraints for XUPLIB 8 bit x 8 bit divisor design for Basys 3 +## Clock signal +set_property PACKAGE_PIN W5 [get_ports sys_clock] +set_property IOSTANDARD LVCMOS33 [get_ports sys_clock] +create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports sys_clock] + +# pushbutton BtnC +set_property PACKAGE_PIN U18 [get_ports {start}] +set_property IOSTANDARD LVCMOS33 [get_ports {start}] + +# LED15 +set_property IOSTANDARD LVCMOS33 [get_ports {done}] +set_property PACKAGE_PIN L1 [get_ports {done}] + +## Switches +set_property IOSTANDARD LVCMOS33 [get_ports {dividend_in[*]}] +set_property PACKAGE_PIN V17 [get_ports {dividend_in[0]}] +set_property PACKAGE_PIN V16 [get_ports {dividend_in[1]}] +set_property PACKAGE_PIN W16 [get_ports {dividend_in[2]}] +set_property PACKAGE_PIN W17 [get_ports {dividend_in[3]}] +set_property PACKAGE_PIN W15 [get_ports {dividend_in[4]}] +set_property PACKAGE_PIN V15 [get_ports {dividend_in[5]}] +set_property PACKAGE_PIN W14 [get_ports {dividend_in[6]}] +set_property PACKAGE_PIN W13 [get_ports {dividend_in[7]}] + +set_property IOSTANDARD LVCMOS33 [get_ports {divisor_in[*]}] +set_property PACKAGE_PIN V2 [get_ports {divisor_in[0]}] +set_property PACKAGE_PIN T3 [get_ports {divisor_in[1]}] +set_property PACKAGE_PIN T2 [get_ports {divisor_in[2]}] +set_property PACKAGE_PIN R3 [get_ports {divisor_in[3]}] +set_property PACKAGE_PIN W2 [get_ports {divisor_in[4]}] +set_property PACKAGE_PIN U1 [get_ports {divisor_in[5]}] +set_property PACKAGE_PIN T1 [get_ports {divisor_in[6]}] +set_property PACKAGE_PIN R2 [get_ports {divisor_in[7]}] + +# 7-seg display +##7 segment display +set_property PACKAGE_PIN W7 [get_ports {seg[0]}] +set_property IOSTANDARD LVCMOS33 [get_ports {seg[0]}] +set_property PACKAGE_PIN W6 [get_ports {seg[1]}] +set_property IOSTANDARD LVCMOS33 [get_ports {seg[1]}] +set_property PACKAGE_PIN U8 [get_ports {seg[2]}] +set_property IOSTANDARD LVCMOS33 [get_ports {seg[2]}] +set_property PACKAGE_PIN V8 [get_ports {seg[3]}] +set_property IOSTANDARD LVCMOS33 [get_ports {seg[3]}] +set_property PACKAGE_PIN U5 [get_ports {seg[4]}] +set_property IOSTANDARD LVCMOS33 [get_ports {seg[4]}] +set_property PACKAGE_PIN V5 [get_ports {seg[5]}] +set_property IOSTANDARD LVCMOS33 [get_ports {seg[5]}] +set_property PACKAGE_PIN U7 [get_ports {seg[6]}] +set_property IOSTANDARD LVCMOS33 [get_ports {seg[6]}] + +set_property PACKAGE_PIN U2 [get_ports {an[0]}] +set_property IOSTANDARD LVCMOS33 [get_ports {an[0]}] +set_property PACKAGE_PIN U4 [get_ports {an[1]}] +set_property IOSTANDARD LVCMOS33 [get_ports {an[1]}] +set_property PACKAGE_PIN V4 [get_ports {an[2]}] +set_property IOSTANDARD LVCMOS33 [get_ports {an[2]}] +set_property PACKAGE_PIN W4 [get_ports {an[3]}] +set_property IOSTANDARD LVCMOS33 [get_ports {an[3]}] + + diff --git a/Projects/Logic_Design/SN_Design/division_leds/README.md b/Projects/Logic_Design/SN_Design/division_leds/README.md new file mode 100644 index 0000000..0a3e0d4 --- /dev/null +++ b/Projects/Logic_Design/SN_Design/division_leds/README.md @@ -0,0 +1,52 @@ +# Division_leds +This project is about creating an 8-bit by 8-bit unsigned divider using non-restoring algorithm and displaying the result on the LEDs using XUP_LIB components. You must download the XUP_LIB directory from the GitHub and then set the XUP_LIB path. You must also download Basys3 board files directory from the GitHub and place it in the **\\2014.4\data\boards\board_parts\artix7** directory. + +The project source files provide Tcl script, and a Xilinx Design Constraint (xdc) file targeting Basys3 board. + +### Design Description: +The design is built using counter, comparators, concat, adder/subtractor, d-ffs, slice, or, xor, shift, and multiplexor IPs available in XUP_LIB and Vivado's standard installation directory. It uses on-board 100 MHz clock source. The result is displayed on LEDs. + +### Tools and other requirements: +* Vivado 2014.4 +* XUP_LIB from GitHub +* Basys3 board files from GitHub + +### Procedure: +Execute the commands **in bold** in the tcl console + +1\. Start Vivado in a GUI mode + +2\. Set the path *basys3_github* to the XUP_LIB using command like in the Vivado Tcl Console. Note the path uses "/" instead of "\". Substiture the path where you have stored the XUP_LIB library. + +**set basys3_github {C:/xup/IPI_LIB/XUP_LIB}** + +3\. Change to the *src* directory of this project directory using the cd command, keeping in mind to use "/" instead of "\" in the directory + +**cd \** + +4\. Next, execute the following command to run the script + +**source ./division_leds.tcl** + +5\. Once the project is created, the resulting block diagram will be displayed. View through the block diagram, its hierarchy and analyze the design + +6\. Execute the following command to run the behavioural simulation: + +**run_sim** + +7\. Analyze the results and notice the output transitioning after the input changes. When satisfied, close the simulator: + +**close_sim** + +8\. Generate the bitstream by clicking on the Generate Bitstream under the Program and Debug group. + +9\. When the bitstream generation is completed, connect the board, power ON the board, and use the Open Hardware Manager option to connect to the board + +10\. Program the board and verify the functionality + +Input : SW15-SW8 for the divisor + SW7-SW0 for the dividend + Center button to start the computation +Output : LED15-LED8 shows quotient, LED7-LED0 shows remainder + + diff --git a/Projects/Logic_Design/SN_Design/division_leds/src/division_leds.tcl b/Projects/Logic_Design/SN_Design/division_leds/src/division_leds.tcl new file mode 100644 index 0000000..b008cb3 --- /dev/null +++ b/Projects/Logic_Design/SN_Design/division_leds/src/division_leds.tcl @@ -0,0 +1,213 @@ +# Script to create an 8-bit by 8-bit non-restoring divider using XUP_LIB components. +# Set XUP_LIB path below before running +# +# Vivado 2014.4 +# Basys 3 board +# 19 June 2015 +# Notes: Set the path below to the XUP_LIB, and run source division_leds.tcl to create the design +# It is assumed the pin constraints xdc file (division_leds_basys3_pins.xdc) is in the project directory. +# If the constraints file is located somewhere else, modify the constraints_directory path below +# +# After sourcing this script, run_sim can be executed to drive simulation from proc at bottom of this file +# Once simulation is running (either from the GUI, or from this script) test_pattern can be executed to drive +# simulation input values defined at the bottom of this file +# +# The 8-bit dividend is input through sw7-sw0 and the 8-bit divisor is input through sw15-sw8. +# The division process starts by pressing BtnC +# The 8-bit quotient output is displayed on LED15-LED8 and the 8-bit remainder is displayed on LED7-LED0 +# +# -------------------------------------------------------------- # +# SET 'basys3_github' PATH TO GITHUB LIBRARY BEFORE RUNNING +# -------------------------------------------------------------- # +set basys3_github {C:/xup/IPI_LIB/XUP_LIB} + +set project_directory . +set project_name division_leds +set constraints_directory $project_directory +set constraints_file division_leds_basys3_pins.xdc +set testbench division_leds_tb.v +# Create project for Basys 3 +create_project -force $project_name ./$project_name -part xc7a35tcpg236-1 +set_property board_part digilentinc.com:basys3:part0:1.1 [current_project] +set_property target_language verilog [current_project] +set_property simulator_language Verilog [current_project] +set_property ip_repo_paths $basys3_github [current_project] +update_ip_catalog +create_bd_design "$project_name" + +# Steps: +# Create a control unit +# Add a divisor +# Add an accumulator +# Add dividend +# Form AQ +# Add shift_nbit +# Slice AQ shifter output and connect +# Create A_Sign +# Add Adder/Subtractor +# Create Addsub_sign +# Create dividend input path +# create Quotient_register and connect to Quotient port +# Create restore stage and connect the output to Remainder port +# Create done_flag + +# create a control unit +create_bd_port -dir I -type clk sys_clock +set_property CONFIG.FREQ_HZ 100000000 [get_bd_ports sys_clock] +create_bd_port -dir I -from 7 -to 0 -type data divisor_in +create_bd_port -dir I -from 7 -to 0 -type data dividend_in +create_bd_port -dir I -type data start +create_bd_port -dir O -from 7 -to 0 Quotient +create_bd_port -dir O -from 7 -to 0 Remainder +create_bd_port -dir O -type other done +create_bd_cell -type ip -vlnv xilinx.com:XUP:counters:1.0 counters_0 +set_property name div_ctr [get_bd_cells counters_0] +set_property -dict [list CONFIG.COUNT_SIZE {4}] [get_bd_cells div_ctr] +connect_bd_net [get_bd_ports sys_clock] [get_bd_pins div_ctr/clk] +create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 xlconstant_0 +set_property name logic_1 [get_bd_cells xlconstant_0] +connect_bd_net [get_bd_pins logic_1/dout] [get_bd_pins div_ctr/up_dn] +connect_bd_net [get_bd_ports start] [get_bd_pins div_ctr/clr] +create_bd_cell -type ip -vlnv xilinx.com:XUP:xup_range_comparator:1.0 xup_range_comparator_0 +set_property name count_lt_8 [get_bd_cells xup_range_comparator_0] +create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 xlconstant_0 +set_property name logic_0 [get_bd_cells xlconstant_0] +set_property -dict [list CONFIG.CONST_VAL {0}] [get_bd_cells logic_0] +connect_bd_net [get_bd_pins logic_0/dout] [get_bd_pins count_lt_8/sign] +create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 xlconstant_0 +set_property name const_7 [get_bd_cells xlconstant_0] +set_property -dict [list CONFIG.CONST_WIDTH {4} CONFIG.CONST_VAL {7}] [get_bd_cells const_7] +connect_bd_net [get_bd_pins const_7/dout] [get_bd_pins count_lt_8/in2] +connect_bd_net [get_bd_pins count_lt_8/in1] [get_bd_pins div_ctr/bin_count] +connect_bd_net [get_bd_pins count_lt_8/le] [get_bd_pins div_ctr/enable] +group_bd_cells control_unit [get_bd_cells const_7] [get_bd_cells count_lt_8] [get_bd_cells div_ctr] +# Add divisor +create_bd_cell -type ip -vlnv xilinx.com:XUP:xup_dff_en_vector:1.0 xup_dff_en_vector_0 +set_property name divisor [get_bd_cells xup_dff_en_vector_0] +set_property -dict [list CONFIG.SIZE {8}] [get_bd_cells divisor ] +connect_bd_net [get_bd_ports divisor_in] [get_bd_pins divisor/d] +connect_bd_net -net [get_bd_nets start_1] [get_bd_ports start] [get_bd_pins divisor/en] +connect_bd_net -net [get_bd_nets sys_clock_1] [get_bd_ports sys_clock] [get_bd_pins divisor/clk] +# Add an accumulator +create_bd_cell -type ip -vlnv xilinx.com:XUP:xup_dff_en_reset_vector:1.0 xup_dff_en_reset_vector_0 +set_property name accumulator [get_bd_cells xup_dff_en_reset_vector_0] +set_property -dict [list CONFIG.SIZE {8}] [get_bd_cells accumulator] +connect_bd_net -net [get_bd_nets start_1] [get_bd_ports start] [get_bd_pins accumulator/reset] +connect_bd_net [get_bd_pins accumulator/en] [get_bd_pins control_unit/count_lt_8/le] +connect_bd_net -net [get_bd_nets sys_clock_1] [get_bd_ports sys_clock] [get_bd_pins accumulator/clk] +# Add dividend +create_bd_cell -type ip -vlnv xilinx.com:XUP:xup_dff_en_vector:1.0 xup_dff_en_vector_0 +set_property name dividend [get_bd_cells xup_dff_en_vector_0] +set_property -dict [list CONFIG.SIZE {8}] [get_bd_cells dividend] +connect_bd_net -net [get_bd_nets sys_clock_1] [get_bd_ports sys_clock] [get_bd_pins dividend/clk] +connect_bd_net -net [get_bd_nets control_unit_le] [get_bd_pins dividend/en] [get_bd_pins control_unit/le] +# Form AQ +create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 xlconcat_0 +set_property name AQ [get_bd_cells xlconcat_0] +connect_bd_net [get_bd_pins accumulator/q] [get_bd_pins AQ/In1] +connect_bd_net [get_bd_pins dividend/q] [get_bd_pins AQ/In0] +# Add shift_nbit +create_bd_cell -type ip -vlnv xilinx.com:XUP:xup_shift_nbit:1.0 xup_shift_nbit_0 +set_property name AQ_shift [get_bd_cells xup_shift_nbit_0] +set_property -dict [list CONFIG.SIZE {16} CONFIG.DIR {true}] [get_bd_cells AQ_shift] +connect_bd_net [get_bd_pins AQ/dout] [get_bd_pins AQ_shift/parallel_in] +connect_bd_net -net [get_bd_nets logic_1_dout] [get_bd_pins AQ_shift/dir] [get_bd_pins logic_1/dout] +# Slice AQ shifter output and connect +create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 xlslice_0 +set_property name AQ_shift_slice_A [get_bd_cells xlslice_0] +set_property -dict [list CONFIG.DIN_WIDTH {16} CONFIG.DIN_TO {8} CONFIG.DIN_FROM {15} CONFIG.DOUT_WIDTH {8}] [get_bd_cells AQ_shift_slice_A] +create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 xlslice_0 +set_property name AQ_shift_slice_Q [get_bd_cells xlslice_0] +set_property -dict [list CONFIG.DIN_WIDTH {16} CONFIG.DIN_TO {1} CONFIG.DIN_FROM {7} CONFIG.DOUT_WIDTH {7}] [get_bd_cells AQ_shift_slice_Q] +connect_bd_net [get_bd_pins AQ_shift/parallel_out] [get_bd_pins AQ_shift_slice_Q/Din] +connect_bd_net -net [get_bd_nets AQ_shift_parallel_out] [get_bd_pins AQ_shift_slice_A/Din] [get_bd_pins AQ_shift/parallel_out] +# Create A_Sign +create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 xlslice_0 +set_property name A_sign [get_bd_cells xlslice_0] +set_property -dict [list CONFIG.DIN_WIDTH {8} CONFIG.DIN_TO {7} CONFIG.DIN_FROM {7} CONFIG.DOUT_WIDTH {1}] [get_bd_cells A_sign] +connect_bd_net -net [get_bd_nets accumulator_q] [get_bd_pins A_sign/Din] [get_bd_pins accumulator/q] +# Add Adder/Subtractor +create_bd_cell -type ip -vlnv xilinx.com:ip:c_addsub:12.0 c_addsub_0 +set_property name addsub [get_bd_cells c_addsub_0] +set_property -dict [list CONFIG.B_Width.VALUE_SRC USER CONFIG.A_Width.VALUE_SRC USER] [get_bd_cells addsub] +set_property -dict [list CONFIG.A_Width {8} CONFIG.B_Width {8} CONFIG.Add_Mode {Add_Subtract} CONFIG.Latency {0} CONFIG.Out_Width {8} CONFIG.B_Value {00000000} CONFIG.CE {false}] [get_bd_cells addsub] +connect_bd_net [get_bd_pins addsub/A] [get_bd_pins AQ_shift_slice_A/Dout] +connect_bd_net [get_bd_pins divisor/q] [get_bd_pins addsub/B] +connect_bd_net [get_bd_pins A_sign/Dout] [get_bd_pins addsub/ADD] +connect_bd_net [get_bd_pins addsub/S] [get_bd_pins accumulator/d] +# Create Addsub_sign +create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 xlslice_0 +set_property name addsub_sign [get_bd_cells xlslice_0] +set_property -dict [list CONFIG.DIN_WIDTH {8} CONFIG.DIN_TO {7} CONFIG.DIN_FROM {7} CONFIG.DOUT_WIDTH {1}] [get_bd_cells addsub_sign] +connect_bd_net -net [get_bd_nets addsub_S] [get_bd_pins addsub_sign/Din] [get_bd_pins addsub/S] +# Create dividend input path +create_bd_cell -type ip -vlnv xilinx.com:XUP:xup_inv:1.0 xup_inv_0 +connect_bd_net [get_bd_pins addsub_sign/Dout] [get_bd_pins xup_inv_0/a] +create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 xlconcat_0 +set_property name Q_in [get_bd_cells xlconcat_0] +connect_bd_net [get_bd_pins xup_inv_0/y] [get_bd_pins Q_in/In0] +connect_bd_net [get_bd_pins AQ_shift_slice_Q/Dout] [get_bd_pins Q_in/In1] +create_bd_cell -type ip -vlnv xilinx.com:XUP:xup_2_to_1_mux_vector:1.0 xup_2_to_1_mux_vector_0 +set_property name dividend_data_in [get_bd_cells xup_2_to_1_mux_vector_0] +set_property -dict [list CONFIG.SIZE {8}] [get_bd_cells dividend_data_in] +connect_bd_net [get_bd_pins Q_in/dout] [get_bd_pins dividend_data_in/a] +connect_bd_net [get_bd_ports dividend_in] [get_bd_pins dividend_data_in/b] +connect_bd_net -net [get_bd_nets start_1] [get_bd_ports start] [get_bd_pins dividend_data_in/sel] +connect_bd_net [get_bd_pins dividend_data_in/y] [get_bd_pins dividend/d] +# create Quotient_register and connect to Quotient port +create_bd_cell -type ip -vlnv xilinx.com:XUP:xup_dff_en_vector:1.0 xup_dff_en_vector_0 +set_property name Quotient_register [get_bd_cells xup_dff_en_vector_0] +set_property -dict [list CONFIG.SIZE {8}] [get_bd_cells Quotient_register] +connect_bd_net -net [get_bd_nets sys_clock_1] [get_bd_ports sys_clock] [get_bd_pins Quotient_register/clk] +connect_bd_net -net [get_bd_nets dividend_q] [get_bd_pins Quotient_register/d] [get_bd_pins dividend/q] +connect_bd_net [get_bd_ports Quotient] [get_bd_pins Quotient_register/q] +# Create restore stage and connect the output to Remainder port +create_bd_cell -type ip -vlnv xilinx.com:ip:c_addsub:12.0 c_addsub_1 +set_property name restore_stage [get_bd_cells c_addsub_1] +set_property -dict [list CONFIG.B_Width.VALUE_SRC USER CONFIG.A_Width.VALUE_SRC USER] [get_bd_cells restore_stage] +set_property -dict [list CONFIG.A_Width {8} CONFIG.B_Width {8} CONFIG.Add_Mode {Add} CONFIG.Latency {0} CONFIG.Out_Width {8} CONFIG.B_Value {00000000} CONFIG.CE {false}] [get_bd_cells restore_stage] +connect_bd_net -net [get_bd_nets accumulator_q] [get_bd_pins restore_stage/A] [get_bd_pins accumulator/q] +connect_bd_net -net [get_bd_nets divisor_q] [get_bd_pins restore_stage/B] [get_bd_pins divisor/q] +create_bd_cell -type ip -vlnv xilinx.com:XUP:xup_2_to_1_mux_vector:1.0 xup_2_to_1_mux_vector_0 +set_property name remainder_sel [get_bd_cells xup_2_to_1_mux_vector_0] +set_property -dict [list CONFIG.SIZE {8}] [get_bd_cells remainder_sel] +connect_bd_net -net [get_bd_nets accumulator_q] [get_bd_pins remainder_sel/a] [get_bd_pins accumulator/q] +connect_bd_net [get_bd_pins remainder_sel/b] [get_bd_pins restore_stage/S] +connect_bd_net -net [get_bd_nets A_sign_Dout] [get_bd_pins remainder_sel/sel] [get_bd_pins A_sign/Dout] +connect_bd_net [get_bd_ports Remainder] [get_bd_pins remainder_sel/y] +# Create done_flag +create_bd_cell -type ip -vlnv xilinx.com:XUP:xup_dff_en_reset:1.0 xup_dff_en_reset_0 +set_property name done_f [get_bd_cells xup_dff_en_reset_0] +connect_bd_net [get_bd_pins done_f/q] [get_bd_pins Quotient_register/en] +connect_bd_net -net [get_bd_nets done_f_q] [get_bd_ports done] [get_bd_pins done_f/q] +connect_bd_net -net [get_bd_nets sys_clock_1] [get_bd_ports sys_clock] [get_bd_pins done_f/clk] +connect_bd_net -net [get_bd_nets logic_1_dout] [get_bd_pins done_f/d] [get_bd_pins logic_1/dout] +connect_bd_net [get_bd_pins done_f/en] [get_bd_pins control_unit/count_lt_8/eq] +connect_bd_net -net [get_bd_nets start_1] [get_bd_ports start] [get_bd_pins done_f/reset] +# Regerate the layout and save it +regenerate_bd_layout +save_bd_design +# Create top HDL wrapper +make_wrapper -files [get_files $project_directory/$project_name/$project_name.srcs/sources_1/bd/$project_name/$project_name.bd] -top +add_files -norecurse $project_directory/$project_name/$project_name.srcs/sources_1/bd/$project_name/hdl/$project_name\_wrapper.v +# Add pin constraints +add_files -fileset constrs_1 -norecurse $constraints_directory/$constraints_file +# Add test bench +add_files -fileset sim_1 -norecurse $project_directory/$testbench +set_property -name {xsim.simulate.runtime} -value {500 ns} -objects [current_fileset -simset] +# run simulation with some sample test vectors +proc run_sim {} { +#check if simulation is already open +set sim_value [current_sim] +if {$sim_value != "" } { +puts "Close existing Simulation" +close_sim -force +} +set_property -name {xsim.simulate.xsim.more_options} -value {-view ../../../../division_leds_tb_behav.wcfg} -objects [current_fileset -simset] +set_property -name {xsim.simulate.runtime} -value {0 ns} -objects [current_fileset -simset] +launch_simulation +puts "Running Simulation for 1000 ns" +run 1000 ns +puts "Simulation complete" +} + diff --git a/Projects/Logic_Design/SN_Design/division_leds/src/division_leds_basys3_pins.xdc b/Projects/Logic_Design/SN_Design/division_leds/src/division_leds_basys3_pins.xdc new file mode 100644 index 0000000..3e7ed96 --- /dev/null +++ b/Projects/Logic_Design/SN_Design/division_leds/src/division_leds_basys3_pins.xdc @@ -0,0 +1,54 @@ +#Pin constraints for XUPLIB 8 bit x 8 bit divisor design for Basys 3 +## Clock signal +set_property PACKAGE_PIN W5 [get_ports sys_clock] +set_property IOSTANDARD LVCMOS33 [get_ports sys_clock] +create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports sys_clock] + +# pushbutton BtnC +set_property PACKAGE_PIN U18 [get_ports {start}] +set_property IOSTANDARD LVCMOS33 [get_ports {start}] + +# done routed to one of the JB pins +set_property PACKAGE_PIN A14 [get_ports {done}] +set_property IOSTANDARD LVCMOS33 [get_ports {done}] + +## Switches +set_property IOSTANDARD LVCMOS33 [get_ports {dividend_in[*]}] +set_property PACKAGE_PIN V17 [get_ports {dividend_in[0]}] +set_property PACKAGE_PIN V16 [get_ports {dividend_in[1]}] +set_property PACKAGE_PIN W16 [get_ports {dividend_in[2]}] +set_property PACKAGE_PIN W17 [get_ports {dividend_in[3]}] +set_property PACKAGE_PIN W15 [get_ports {dividend_in[4]}] +set_property PACKAGE_PIN V15 [get_ports {dividend_in[5]}] +set_property PACKAGE_PIN W14 [get_ports {dividend_in[6]}] +set_property PACKAGE_PIN W13 [get_ports {dividend_in[7]}] + +set_property IOSTANDARD LVCMOS33 [get_ports {divisor_in[*]}] +set_property PACKAGE_PIN V2 [get_ports {divisor_in[0]}] +set_property PACKAGE_PIN T3 [get_ports {divisor_in[1]}] +set_property PACKAGE_PIN T2 [get_ports {divisor_in[2]}] +set_property PACKAGE_PIN R3 [get_ports {divisor_in[3]}] +set_property PACKAGE_PIN W2 [get_ports {divisor_in[4]}] +set_property PACKAGE_PIN U1 [get_ports {divisor_in[5]}] +set_property PACKAGE_PIN T1 [get_ports {divisor_in[6]}] +set_property PACKAGE_PIN R2 [get_ports {divisor_in[7]}] + +# LEDs +set_property IOSTANDARD LVCMOS33 [get_ports {Remainder[*]}] +set_property PACKAGE_PIN U16 [get_ports {Remainder[0]}] +set_property PACKAGE_PIN E19 [get_ports {Remainder[1]}] +set_property PACKAGE_PIN U19 [get_ports {Remainder[2]}] +set_property PACKAGE_PIN V19 [get_ports {Remainder[3]}] +set_property PACKAGE_PIN W18 [get_ports {Remainder[4]}] +set_property PACKAGE_PIN U15 [get_ports {Remainder[5]}] +set_property PACKAGE_PIN U14 [get_ports {Remainder[6]}] +set_property PACKAGE_PIN V14 [get_ports {Remainder[7]}] +set_property IOSTANDARD LVCMOS33 [get_ports {Quotient[*]}] +set_property PACKAGE_PIN V13 [get_ports {Quotient[0]}] +set_property PACKAGE_PIN V3 [get_ports {Quotient[1]}] +set_property PACKAGE_PIN W3 [get_ports {Quotient[2]}] +set_property PACKAGE_PIN U3 [get_ports {Quotient[3]}] +set_property PACKAGE_PIN P3 [get_ports {Quotient[4]}] +set_property PACKAGE_PIN N3 [get_ports {Quotient[5]}] +set_property PACKAGE_PIN P1 [get_ports {Quotient[6]}] +set_property PACKAGE_PIN L1 [get_ports {Quotient[7]}] diff --git a/Projects/Logic_Design/SN_Design/division_leds/src/division_leds_tb.v b/Projects/Logic_Design/SN_Design/division_leds/src/division_leds_tb.v new file mode 100644 index 0000000..16e84c4 --- /dev/null +++ b/Projects/Logic_Design/SN_Design/division_leds/src/division_leds_tb.v @@ -0,0 +1,71 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Module Name: division_leds_tb +////////////////////////////////////////////////////////////////////////////////// + +module division_leds_tb( + ); + + parameter PERIOD=20; + + reg sys_clock; + reg start; + reg [7:0] divisor_in; + reg [7:0] dividend_in; + wire done; + wire [7:0] Remainder; + wire [7:0] Quotient; + + division_leds_wrapper DUT ( + .sys_clock(sys_clock), .start(start), .divisor_in(divisor_in), .dividend_in(dividend_in), + .done(done), .Quotient(Quotient), .Remainder(Remainder) + ); + + initial begin + sys_clock = 0; + forever #(PERIOD/2) sys_clock = ~sys_clock; + end + + initial + begin + start=0; + @(posedge sys_clock); + divisor_in = 8'b00000011; // 3 + dividend_in = 8'b0001011; // 11 + #5; + start = 1; + #(2*PERIOD); + start = 0; + @(posedge done); + @(posedge sys_clock); + divisor_in = 8'b10000000; // 128 + dividend_in = 8'b00000111; // 7 + #5; + start = 1; + #(2*PERIOD); + start = 0; + @(posedge done); + @(posedge sys_clock); + divisor_in = 8'b00000111; // 7 + dividend_in = 8'b11111100; // 252 + #5; + start = 1; + #(2*PERIOD); + start = 0; + @(posedge done); + @(posedge sys_clock); + divisor_in = 8'b00000111; // 7 + dividend_in = 8'b00000111; // 7 + #5; + start = 1; + #(2*PERIOD); + start = 0; + @(posedge done); + @(posedge sys_clock); + @(posedge sys_clock); + @(posedge sys_clock); + @(posedge sys_clock); + $stop; + end +endmodule + diff --git a/Projects/Logic_Design/SN_Design/division_leds/src/division_leds_tb_behav.wcfg b/Projects/Logic_Design/SN_Design/division_leds/src/division_leds_tb_behav.wcfg new file mode 100644 index 0000000..9a9bc8a --- /dev/null +++ b/Projects/Logic_Design/SN_Design/division_leds/src/division_leds_tb_behav.wcfg @@ -0,0 +1,46 @@ + + + + + + + + + + + + + + + sys_clock + sys_clock + + + divisor_in[7:0] + divisor_in[7:0] + UNSIGNEDDECRADIX + + + dividend_in[7:0] + dividend_in[7:0] + UNSIGNEDDECRADIX + + + start + start + + + done + done + + + Quotient[7:0] + Quotient[7:0] + UNSIGNEDDECRADIX + + + Remainder[7:0] + Remainder[7:0] + UNSIGNEDDECRADIX + + diff --git a/Projects/Logic_Design/SN_Design/sequence_detector_moore/README.md b/Projects/Logic_Design/SN_Design/sequence_detector_moore/README.md new file mode 100644 index 0000000..cfaac4a --- /dev/null +++ b/Projects/Logic_Design/SN_Design/sequence_detector_moore/README.md @@ -0,0 +1,54 @@ +# Sequence Detector Moore Machine +This project is about creating a sequence detector using Moore state machine. You must download the XUP_LIB directory from the GitHub and then set the XUP_LIB path. You must also download Basys3 board files directory from the GitHub and place it in the **\\2014.4\data\boards\board_parts\artix7** directory. + +The project source files provide Tcl script, and a Xilinx Design Constraint (xdc) file targeting Basys3 board. + +### Design Description: +Design a sequence detector implementing a Moore state machine. The state machine has one input (ain) and one output (detect). The output detect is 1 if and only if the total number of 1s received is divisible by 3 (inclusive of 0). The design is built using counter, concat, d-ffs, slice, or, and other basic logic IPs available in XUP_LIB and Vivado's standard installation directory. It uses switch 15 as the clock input, center button as a reset input, switch 0 as the ain input, and LEDS as the output. + +### Tools and other requirements: +* Vivado 2014.4 +* XUP_LIB from GitHub +* Basys3 board files from GitHub + +### Procedure: +Execute the commands **in bold** in the tcl console + +1\. Start Vivado in a GUI mode + +2\. Set the path *basys3_github* to the XUP_LIB using command like in the Vivado Tcl Console. Note the path uses "/" instead of "\". Substiture the path where you have stored the XUP_LIB library. + +**set basys3_github {C:/xup/IPI_LIB/XUP_LIB}** + +3\. Change to the *src* directory of this project directory using the cd command, keeping in mind to use "/" instead of "\" in the directory + +**cd \** + +4\. Next, execute the following command to run the script + +**source ./sequence_detector_moore.tcl** + +5\. Once the project is created, the resulting block diagram will be displayed. View through the block diagram, its hierarchy and analyze the design + +6\. Execute the following command to run the behavioural simulation: + +**run_sim** + +7\. Analyze the results and notice the output transitioning after the input changes. When satisfied, close the simulator: + +**close_sim** + +8\. Generate the bitstream by clicking on the Generate Bitstream under the Program and Debug group. + +9\. When the bitstream generation is completed, connect the board, power ON the board, and use the Open Hardware Manager option to connect to the board + +10\. Program the board and verify the functionality + +Input : SW15 for the clock input + SW0 for the ain input + Center button to reset +Output : LED15 to indicate when the sequence is detected + LED3-LED0 shows current count of number of ones + + + diff --git a/Projects/Logic_Design/SN_Design/sequence_detector_moore/problem_stmt_and_solution.pdf b/Projects/Logic_Design/SN_Design/sequence_detector_moore/problem_stmt_and_solution.pdf new file mode 100644 index 0000000..5e05f85 Binary files /dev/null and b/Projects/Logic_Design/SN_Design/sequence_detector_moore/problem_stmt_and_solution.pdf differ diff --git a/Projects/Logic_Design/SN_Design/sequence_detector_moore/src/sequence_detector_moore.tcl b/Projects/Logic_Design/SN_Design/sequence_detector_moore/src/sequence_detector_moore.tcl new file mode 100644 index 0000000..871a3cd --- /dev/null +++ b/Projects/Logic_Design/SN_Design/sequence_detector_moore/src/sequence_detector_moore.tcl @@ -0,0 +1,157 @@ +# Script to create an 8-bit by 8-bit non-restoring divider using XUP_LIB components. +# Set XUP_LIB path below before running +# +# Vivado 2014.4 +# Basys 3 board +# 19 June 2015 +# Notes: Set the path below to the XUP_LIB, and run source sequence_detector_moore.tcl to create the design +# It is assumed the pin constraints xdc file (sequence_detector_moore_basys3_pins.xdc) is in the project directory. +# If the constraints file is located somewhere else, modify the constraints_directory path below +# +# After sourcing this script, run_sim can be executed to drive simulation from proc at bottom of this file +# Once simulation is running (either from the GUI, or from this script) test_pattern can be executed to drive +# simulation input values defined at the bottom of this file +# +# The 8-bit dividend is input through sw7-sw0 and the 8-bit divisor is input through sw15-sw8. +# The division process starts by pressing BtnC +# The 8-bit quotient output is displayed on LED15-LED8 and the 8-bit remainder is displayed on LED7-LED0 +# +# -------------------------------------------------------------- # +# SET 'basys3_github' PATH TO GITHUB LIBRARY BEFORE RUNNING +# -------------------------------------------------------------- # +set basys3_github {C:/xup/IPI_LIB/XUP_LIB} + +set project_directory . +set project_name sequence_detector_moore +set constraints_directory $project_directory +set constraints_file sequence_detector_moore_basys3_pins.xdc +set testbench sequence_detector_moore_tb.v +# Create project for Basys 3 +create_project -force $project_name ./$project_name -part xc7a35tcpg236-1 +set_property board_part digilentinc.com:basys3:part0:1.1 [current_project] +set_property target_language verilog [current_project] +set_property simulator_language Verilog [current_project] +set_property ip_repo_paths $basys3_github [current_project] +update_ip_catalog +create_bd_design "$project_name" + +# Steps: +# Create a control unit +# Add a divisor +# Add an accumulator +# Add dividend +# Form AQ +# Add shift_nbit +# Slice AQ shifter output and connect +# Create A_Sign +# Add Adder/Subtractor +# Create Addsub_sign +# Create dividend input path +# create Quotient_register and connect to Quotient port +# Create restore stage and connect the output to Remainder port +# Create done_flag + +# create a control unit +create_bd_port -dir I sys_clock +create_bd_port -dir I reset +create_bd_port -dir I ain +create_bd_port -dir O detected +create_bd_port -dir O -from 3 -to 0 count +create_bd_cell -type ip -vlnv xilinx.com:XUP:xup_dff_en_reset_vector:1.0 xup_dff_en_reset_vector_0 +set_property name CS [get_bd_cells xup_dff_en_reset_vector_0] +set_property -dict [list CONFIG.SIZE {2}] [get_bd_cells CS] +connect_bd_net [get_bd_ports sys_clock] [get_bd_pins CS/clk] +connect_bd_net [get_bd_ports reset] [get_bd_pins CS/reset] +# create counter +create_bd_cell -type ip -vlnv xilinx.com:XUP:counters:1.0 counters_0 +set_property name counter [get_bd_cells counters_0] +set_property -dict [list CONFIG.COUNT_SIZE {4}] [get_bd_cells counter] +connect_bd_net -net [get_bd_nets sys_clock_1] [get_bd_ports sys_clock] [get_bd_pins counter/clk] +connect_bd_net -net [get_bd_nets reset_1] [get_bd_ports reset] [get_bd_pins counter/clr] +create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 xlconstant_0 +set_property name logic_1 [get_bd_cells xlconstant_0] +connect_bd_net [get_bd_pins logic_1/dout] [get_bd_pins counter/up_dn] +connect_bd_net [get_bd_ports count] [get_bd_pins counter/bin_count] +connect_bd_net [get_bd_ports ain] [get_bd_pins counter/enable] +# create next state logic block +create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 xlslice_0 +set_property name cs1 [get_bd_cells xlslice_0] +set_property -dict [list CONFIG.DIN_WIDTH {2} CONFIG.DIN_TO {1} CONFIG.DIN_FROM {1} CONFIG.DOUT_WIDTH {1}] [get_bd_cells cs1] +create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 xlslice_0 +set_property name cs0 [get_bd_cells xlslice_0] +set_property -dict [list CONFIG.DIN_WIDTH {2}] [get_bd_cells cs0] +connect_bd_net [get_bd_pins CS/q] [get_bd_pins cs1/Din] +connect_bd_net -net [get_bd_nets CS_q] [get_bd_pins cs0/Din] [get_bd_pins CS/q] +connect_bd_net -net [get_bd_nets logic_1_dout] [get_bd_pins CS/en] [get_bd_pins logic_1/dout] +### Create ain_n, cs1_n, cs0_n +create_bd_cell -type ip -vlnv xilinx.com:XUP:xup_inv:1.0 xup_inv_0 +set_property name ain_n [get_bd_cells xup_inv_0] +connect_bd_net -net [get_bd_nets ain_1] [get_bd_ports ain] [get_bd_pins ain_n/a] +create_bd_cell -type ip -vlnv xilinx.com:XUP:xup_inv:1.0 xup_inv_0 +set_property name cs1_n [get_bd_cells xup_inv_0] +create_bd_cell -type ip -vlnv xilinx.com:XUP:xup_inv:1.0 xup_inv_0 +set_property name cs0_n [get_bd_cells xup_inv_0] +connect_bd_net [get_bd_pins cs0/Dout] [get_bd_pins cs0_n/a] +connect_bd_net [get_bd_pins cs1/Dout] [get_bd_pins cs1_n/a] +### Create NS1 sub-circuit +create_bd_cell -type ip -vlnv xilinx.com:XUP:xup_and2:1.0 xup_and2_0 +create_bd_cell -type ip -vlnv xilinx.com:XUP:xup_and2:1.0 xup_and2_1 +create_bd_cell -type ip -vlnv xilinx.com:XUP:xup_or2:1.0 xup_or2_0 +connect_bd_net [get_bd_pins xup_and2_0/y] [get_bd_pins xup_or2_0/a] +connect_bd_net [get_bd_pins xup_and2_1/y] [get_bd_pins xup_or2_0/b] +connect_bd_net -net [get_bd_nets cs1_Dout] [get_bd_pins xup_and2_0/a] [get_bd_pins cs1/Dout] +connect_bd_net [get_bd_pins xup_and2_0/b] [get_bd_pins ain_n/y] +connect_bd_net -net [get_bd_nets cs0_Dout] [get_bd_pins xup_and2_1/a] [get_bd_pins cs0/Dout] +connect_bd_net -net [get_bd_nets ain_1] [get_bd_ports ain] [get_bd_pins xup_and2_1/b] +group_bd_cells NS1 [get_bd_cells xup_or2_0] [get_bd_cells xup_and2_1] [get_bd_cells xup_and2_0] +### Create NS0 sub-circuit +create_bd_cell -type ip -vlnv xilinx.com:XUP:xup_and2:1.0 xup_and2_0 +create_bd_cell -type ip -vlnv xilinx.com:XUP:xup_and3:1.0 xup_and3_0 +create_bd_cell -type ip -vlnv xilinx.com:XUP:xup_or2:1.0 xup_or2_0 +connect_bd_net [get_bd_pins xup_and2_0/y] [get_bd_pins xup_or2_0/a] +connect_bd_net [get_bd_pins xup_and3_0/y] [get_bd_pins xup_or2_0/b] +connect_bd_net -net [get_bd_nets cs0_Dout] [get_bd_pins xup_and2_0/a] [get_bd_pins cs0/Dout] +connect_bd_net -net [get_bd_nets ain_n_y] [get_bd_pins xup_and2_0/b] [get_bd_pins ain_n/y] +connect_bd_net [get_bd_pins cs0_n/y] [get_bd_pins xup_and3_0/a] +connect_bd_net [get_bd_pins cs1_n/y] [get_bd_pins xup_and3_0/b] +connect_bd_net -net [get_bd_nets ain_1] [get_bd_ports ain] [get_bd_pins xup_and3_0/c] +group_bd_cells NS0 [get_bd_cells xup_or2_0] [get_bd_cells xup_and3_0] [get_bd_cells xup_and2_0] +### Form NS bus and connect to the state variables input +create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 xlconcat_0 +set_property name NS [get_bd_cells xlconcat_0] +connect_bd_net [get_bd_pins NS/dout] [get_bd_pins CS/d] +connect_bd_net [get_bd_pins NS0/xup_or2_0/y] [get_bd_pins NS/In0] +connect_bd_net [get_bd_pins NS1/xup_or2_0/y] [get_bd_pins NS/In1] +### Form output logic and connect to detected port +create_bd_cell -type ip -vlnv xilinx.com:XUP:xup_nor2:1.0 xup_nor2_0 +connect_bd_net -net [get_bd_nets cs1_Dout] [get_bd_pins xup_nor2_0/a] [get_bd_pins cs1/Dout] +connect_bd_net -net [get_bd_nets cs0_Dout] [get_bd_pins xup_nor2_0/b] [get_bd_pins cs0/Dout] +connect_bd_net [get_bd_ports detected] [get_bd_pins xup_nor2_0/y] +group_bd_cells output_logic [get_bd_cells xup_nor2_0] +# Regerate the layout and save it +regenerate_bd_layout +save_bd_design +# Create top HDL wrapper +make_wrapper -files [get_files $project_directory/$project_name/$project_name.srcs/sources_1/bd/$project_name/$project_name.bd] -top +add_files -norecurse $project_directory/$project_name/$project_name.srcs/sources_1/bd/$project_name/hdl/$project_name\_wrapper.v +# Add pin constraints +add_files -fileset constrs_1 -norecurse $constraints_directory/$constraints_file +# Add test bench +add_files -fileset sim_1 -norecurse $project_directory/$testbench +set_property -name {xsim.simulate.runtime} -value {500 ns} -objects [current_fileset -simset] +# run simulation with some sample test vectors +proc run_sim {} { +#check if simulation is already open +set sim_value [current_sim] +if {$sim_value != "" } { +puts "Close existing Simulation" +close_sim -force +} +set_property -name {xsim.simulate.xsim.more_options} -value {-view ../../../../sequence_detector_moore_tb_behav.wcfg} -objects [current_fileset -simset] +set_property -name {xsim.simulate.runtime} -value {0 ns} -objects [current_fileset -simset] +launch_simulation +puts "Running Simulation for 1000 ns" +run 1000 ns +puts "Simulation complete" +} + diff --git a/Projects/Logic_Design/SN_Design/sequence_detector_moore/src/sequence_detector_moore_basys3_pins.xdc b/Projects/Logic_Design/SN_Design/sequence_detector_moore/src/sequence_detector_moore_basys3_pins.xdc new file mode 100644 index 0000000..2eb058a --- /dev/null +++ b/Projects/Logic_Design/SN_Design/sequence_detector_moore/src/sequence_detector_moore_basys3_pins.xdc @@ -0,0 +1,26 @@ +#Pin constraints for XUPLIB sequence_detector_moore design for Basys 3 +## Clock signal +## SW15 as Clock signal +set_property PACKAGE_PIN R2 [get_ports sys_clock] +set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets sys_clock_IBUF] +set_property IOSTANDARD LVCMOS33 [get_ports sys_clock] + +# pushbutton BtnC +set_property PACKAGE_PIN U18 [get_ports reset] +set_property IOSTANDARD LVCMOS33 [get_ports reset] + +# SW0 +set_property PACKAGE_PIN V17 [get_ports ain] +set_property IOSTANDARD LVCMOS33 [get_ports ain] + +# LEDs +set_property IOSTANDARD LVCMOS33 [get_ports {count[*]}] +set_property PACKAGE_PIN U16 [get_ports {count[0]}] +set_property PACKAGE_PIN E19 [get_ports {count[1]}] +set_property PACKAGE_PIN U19 [get_ports {count[2]}] +set_property PACKAGE_PIN V19 [get_ports {count[3]}] + +# LED15 +set_property PACKAGE_PIN L1 [get_ports detected] +set_property IOSTANDARD LVCMOS33 [get_ports detected] + diff --git a/Projects/Logic_Design/SN_Design/sequence_detector_moore/src/sequence_detector_moore_tb.v b/Projects/Logic_Design/SN_Design/sequence_detector_moore/src/sequence_detector_moore_tb.v new file mode 100644 index 0000000..1bdfd94 --- /dev/null +++ b/Projects/Logic_Design/SN_Design/sequence_detector_moore/src/sequence_detector_moore_tb.v @@ -0,0 +1,48 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Module Name: sequence_detector_moore_tb +////////////////////////////////////////////////////////////////////////////////// + +module sequence_detector_moore_tb( + ); + + reg clk; + reg reset; + reg ain; + wire [3:0] count; + wire detected; + parameter PERIOD=20; + + sequence_detector_moore_wrapper DUT (.sys_clock(clk), .reset(reset), .ain(ain), .count(count), .detected(detected)); + + initial + begin + clk = 0; + forever + begin + #(PERIOD/2) clk = 1; + #(PERIOD/2) clk = 0; + end + end + + initial + begin + reset = 1'b1; + ain = 1'b0; + #(2*PERIOD); // wait for 2 clock cycles + reset = 1'b0; + #(PERIOD) ain = 1'b0; + #(PERIOD) ain = 1'b1; + #(2*PERIOD) ain = 1'b0; + #(6*PERIOD) ain = 1'b1; + #(4*PERIOD) ain = 1'b0; + #(2*PERIOD) ain = 1'b1; + #(2*PERIOD); + #(PERIOD) reset = 1'b1; + #(PERIOD) reset = 1'b0; + #(PERIOD) ain = 1'b0; + #(3*PERIOD) ain = 1'b1; + #(4*PERIOD); + end + +endmodule diff --git a/Projects/Logic_Design/SN_Design/sequence_detector_moore/src/sequence_detector_moore_tb_behav.wcfg b/Projects/Logic_Design/SN_Design/sequence_detector_moore/src/sequence_detector_moore_tb_behav.wcfg new file mode 100644 index 0000000..f69abd6 --- /dev/null +++ b/Projects/Logic_Design/SN_Design/sequence_detector_moore/src/sequence_detector_moore_tb_behav.wcfg @@ -0,0 +1,34 @@ + + + + + + + + + + + + + + + clk + clk + + + reset + reset + + + ain + ain + + + count[3:0] + count[3:0] + + + detected + detected + + diff --git a/Projects/Logic_Design/SN_Design/stop_watch/README.md b/Projects/Logic_Design/SN_Design/stop_watch/README.md new file mode 100644 index 0000000..51f6f98 --- /dev/null +++ b/Projects/Logic_Design/SN_Design/stop_watch/README.md @@ -0,0 +1,41 @@ +# Stop Watch +This project is about creating a digital stop watch showing M.SS.f at a tenth of second resolution using XUP_LIB components. You must download the XUP_LIB directory from the GitHub and then set the XUP_LIB path. You must also download Basys3 board files directory from the GitHub and place it in the **\\2014.4\data\boards\board_parts\artix7** directory. + +The project source files provide Tcl script, and a Xilinx Design Constraint (xdc) file targeting Basys3 board. + +### Design Description: +The digital stop watch is built using counters, comparators, concat, bin2bcd, and 7-segment display IPs available in XUP_LIB and Vivado's standard installation directory. It also uses clocking wizard to generate 5 MHz clock from on-board 100 MHz clock source. The generated 5 MHz clock is further divided to generate 1 Hz clock signal. There are three counters and one 7-segment display instance, showing M.SS.F + +### Tools and other requirements: +* Vivado 2014.4 +* XUP_LIB from GitHub +* Basys3 board files from GitHub + +### Procedure: +Execute the commands **in bold** in the tcl console + +1\. Start Vivado in a GUI mode + +2\. Set the path *basys3_github* to the XUP_LIB using command like in the Vivado Tcl Console. Note the path uses "/" instead of "\". Substiture the path where you have stored the XUP_LIB library. + +**set basys3_github {C:/xup/IPI_LIB/XUP_LIB}** + +3\. Change to the *src* directory of this project directory using the cd command, keeping in mind to use "/" instead of "\" in the directory + +**cd \** + +4\. Next, execute the following command to run the script + +**source ./stop_watch.tcl** + +5\. Once the project is created, the resulting block diagram will be displayed. View through the block diagram, its hierarchy and analyze the design + +6\. Generate the bitstream by clicking on the Generate Bitstream under the Program and Debug group. A warning message box will appear. Click OK to ignore it + +7\. When the bitstream generation is completed, connect the board, power ON the board, and use the Open Hardware Manager option to connect to the board + +8\. Program the board and verify the functionality + +Input : Center button to reset the stop watch +Input : Right button to hold the stop watch- the count won't increment as long as the right button is pressed +Output : 4 7-segments module diff --git a/Projects/Logic_Design/SN_Design/stop_watch/src/stop_watch.tcl b/Projects/Logic_Design/SN_Design/stop_watch/src/stop_watch.tcl new file mode 100644 index 0000000..2feed54 --- /dev/null +++ b/Projects/Logic_Design/SN_Design/stop_watch/src/stop_watch.tcl @@ -0,0 +1,149 @@ +# Script to create a stop watch showing M.SS.F at a tenth of second resolution using XUP_LIB components. +# Set XUP_LIB path below before running +# +# The stop watch is built using counters, comparators, concat, +# bin2bcd, and 7-segment display IPs available in XUP_LIB and IPs available in the +# Vivado's standard installation directory. It also uses clocking # wizard to generate 5 MHz clock from +# the on-board 100 MHz clock source. The generated 5 MHz clock is further divided to +# generate 0.1 Hz clock signal. There are three counters and one # 7-segment display instance, showing M.SS.F +# +# Vivado 2014.4 +# Basys 3 board +# 2 June 2015 +# Notes: Set the path below to the XUP_LIB, and run source stop_watch.tcl to create the design +# It is assumed the pin constraints xdc file (stop_watch_basys3_pins.xdc) is in the project directory. +# If the constraints file is located somewhere else, modify the constraints_directory path below +# +# The reset is connected to the center button +# The output is displayed on the four 7-segment module +# -------------------------------------------------------------- # +# SET 'basys3_github' PATH TO GITHUB LIBRARY BEFORE RUNNING +# -------------------------------------------------------------- # +set basys3_github {C:/xup/IPI_LIB/XUP_LIB} +set project_directory . +set project_name stop_watch +set constraints_directory $project_directory +set constraints_file stop_watch_basys3_pins.xdc +# Create project for Basys 3 +create_project -force $project_name ./$project_name -part xc7a35tcpg236-1 +set_property board_part digilentinc.com:basys3:part0:1.1 [current_project] +set_property target_language verilog [current_project] +set_property simulator_language Verilog [current_project] +set_property ip_repo_paths $basys3_github [current_project] +update_ip_catalog +create_bd_design "$project_name" +# instantiate clocking wizard and configure it to generate 5 MHz clock. Connect its input to the input port using the run_connection wizard +create_bd_cell -type ip -vlnv xilinx.com:ip:clk_wiz:5.1 clk_wiz_0 +set_property -dict [list CONFIG.CLKOUT2_USED {true} CONFIG.CLKOUT2_REQUESTED_OUT_FREQ {5.000} CONFIG.USE_LOCKED {false} CONFIG.USE_RESET {false} CONFIG.MMCM_CLKFBOUT_MULT_F {6.250} CONFIG.MMCM_CLKOUT0_DIVIDE_F {6.250} CONFIG.MMCM_CLKOUT1_DIVIDE {125} CONFIG.NUM_OUT_CLKS {2} CONFIG.CLKOUT1_JITTER {148.376} CONFIG.CLKOUT1_PHASE_ERROR {128.132} CONFIG.CLKOUT2_JITTER {270.159} CONFIG.CLKOUT2_PHASE_ERROR {128.132}] [get_bd_cells clk_wiz_0] +apply_bd_automation -rule xilinx.com:bd_rule:board -config {Board_Interface "sys_clock" } [get_bd_pins clk_wiz_0/clk_in1] +# add vivado IPI binary counter as it provides larger size counter. Add comparator and set its value to generate 0.1 Hz. Add associated logic and connect them +create_bd_cell -type ip -vlnv xilinx.com:ip:c_counter_binary:12.0 c_counter_binary_0 +set_property -dict [list CONFIG.Implementation {DSP48} CONFIG.Output_Width {19} CONFIG.Restrict_Count {true} CONFIG.Final_Count_Value {7A120}] [get_bd_cells c_counter_binary_0] +create_bd_cell -type ip -vlnv xilinx.com:XUP:xup_range_comparator:1.0 tenth_second +set_property -dict [list CONFIG.SIZE {19}] [get_bd_cells tenth_second] +connect_bd_net [get_bd_pins c_counter_binary_0/Q] [get_bd_pins tenth_second/in1] +connect_bd_net [get_bd_pins clk_wiz_0/clk_out2] [get_bd_pins c_counter_binary_0/CLK] +create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 const_500000 +set_property -dict [list CONFIG.CONST_WIDTH {19} CONFIG.CONST_VAL {500000}] [get_bd_cells const_500000] +connect_bd_net [get_bd_pins const_500000/dout] [get_bd_pins tenth_second/in2] +create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 const_gnd +set_property -dict [list CONFIG.CONST_VAL {0}] [get_bd_cells const_gnd] +connect_bd_net [get_bd_pins const_gnd/dout] [get_bd_pins tenth_second/sign] +# instantiate counter, comparator, and associated logic for the tenth of a second and connect them +create_bd_cell -type ip -vlnv xilinx.com:XUP:counters:1.0 tenth_ctr +set_property -dict [list CONFIG.COUNT_SIZE {4}] [get_bd_cells tenth_ctr] +create_bd_cell -type ip -vlnv xilinx.com:XUP:xup_range_comparator:1.0 tenth_sec_compare +set_property -dict [list CONFIG.SIZE {4}] [get_bd_cells tenth_sec_compare] +connect_bd_net [get_bd_pins tenth_ctr/bin_count] [get_bd_pins tenth_sec_compare/in1] +create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 const_9 +set_property -dict [list CONFIG.CONST_WIDTH {4} CONFIG.CONST_VAL {9}] [get_bd_cells const_9] +connect_bd_net [get_bd_pins const_9/dout] [get_bd_pins tenth_sec_compare/in2] +connect_bd_net -net [get_bd_nets const_gnd_dout] [get_bd_pins tenth_sec_compare/sign] [get_bd_pins const_gnd/dout] +connect_bd_net [get_bd_pins tenth_second/eq] [get_bd_pins tenth_ctr/clk] +create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 const_1 +connect_bd_net [get_bd_pins const_1/dout] [get_bd_pins tenth_ctr/up_dn] +# Generate clr for the tenth of a second counter +create_bd_cell -type ip -vlnv xilinx.com:XUP:xup_or2:1.0 xup_or2_0 +connect_bd_net [get_bd_pins tenth_sec_compare/eq] [get_bd_pins xup_or2_0/a] +connect_bd_net [get_bd_pins xup_or2_0/y] [get_bd_pins tenth_ctr/clr] +# Add a counter and configure it for seconds. Add necessary logic to count it up to 59 and connect it +create_bd_cell -type ip -vlnv xilinx.com:XUP:counters:1.0 seconds_ctr +set_property -dict [list CONFIG.COUNT_SIZE {6}] [get_bd_cells seconds_ctr] +create_bd_cell -type ip -vlnv xilinx.com:XUP:xup_range_comparator:1.0 seconds_compare +set_property -dict [list CONFIG.SIZE {6}] [get_bd_cells seconds_compare] +connect_bd_net -net [get_bd_nets tenth_second_eq] [get_bd_pins seconds_ctr/clk] [get_bd_pins tenth_second/eq] +connect_bd_net [get_bd_pins seconds_ctr/bin_count] [get_bd_pins seconds_compare/in1] +connect_bd_net -net [get_bd_nets const_gnd_dout] [get_bd_pins seconds_compare/sign] [get_bd_pins const_gnd/dout] +create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 const_60 +set_property -dict [list CONFIG.CONST_WIDTH {6} CONFIG.CONST_VAL {60}] [get_bd_cells const_60] +connect_bd_net [get_bd_pins const_60/dout] [get_bd_pins seconds_compare/in2] +connect_bd_net -net [get_bd_nets const_1_dout] [get_bd_pins seconds_ctr/up_dn] [get_bd_pins const_1/dout] +# Add a counter and configure it for minutes. Add necessary logic to count it up to 10 and connect it +create_bd_cell -type ip -vlnv xilinx.com:XUP:counters:1.0 minutes_ctr +set_property -dict [list CONFIG.COUNT_SIZE {4}] [get_bd_cells minutes_ctr] +create_bd_cell -type ip -vlnv xilinx.com:XUP:xup_range_comparator:1.0 minutes_compare +connect_bd_net [get_bd_pins minutes_ctr/bin_count] [get_bd_pins minutes_compare/in1] +connect_bd_net -net [get_bd_nets const_gnd_dout] [get_bd_pins minutes_compare/sign] [get_bd_pins const_gnd/dout] +create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 const_10 +set_property -dict [list CONFIG.CONST_WIDTH {4} CONFIG.CONST_VAL {10}] [get_bd_cells const_10] +connect_bd_net [get_bd_pins minutes_compare/in2] [get_bd_pins const_10/dout] +connect_bd_net -net [get_bd_nets tenth_second_eq] [get_bd_pins minutes_ctr/clk] [get_bd_pins tenth_second/eq] +connect_bd_net -net [get_bd_nets const_1_dout] [get_bd_pins minutes_ctr/up_dn] [get_bd_pins const_1/dout] +create_bd_cell -type ip -vlnv xilinx.com:XUP:xup_or2:1.0 xup_or2_1 +connect_bd_net [get_bd_pins seconds_compare/eq] [get_bd_pins xup_or2_1/a] +connect_bd_net [get_bd_pins xup_or2_1/y] [get_bd_pins seconds_ctr/clr] +create_bd_cell -type ip -vlnv xilinx.com:XUP:xup_or2:1.0 xup_or2_2 +connect_bd_net [get_bd_pins minutes_compare/eq] [get_bd_pins xup_or2_2/a] +connect_bd_net [get_bd_pins xup_or2_2/y] [get_bd_pins minutes_ctr/clr] +# add a 7-segment display for seconds and wire it up +# Add concat IP, set it to 4 ports and connect ones and tens of both seconds and minutes bin2bcd instances +create_bd_cell -type ip -vlnv xilinx.com:XUP:bin2bcd:1.0 bin2bcd_0 +set_property -dict [list CONFIG.SIZE {6}] [get_bd_cells bin2bcd_0] +connect_bd_net -net [get_bd_nets seconds_ctr_bin_count] [get_bd_pins bin2bcd_0/a_in] [get_bd_pins seconds_ctr/bin_count] +create_bd_cell -type ip -vlnv xilinx.com:XUP:seg7display:1.0 seg7display_0 +set_property -dict [list CONFIG.DP_0 {0} CONFIG.DP_2 {0}] [get_bd_cells seg7display_0] +connect_bd_net [get_bd_pins seg7display_0/clk] [get_bd_pins clk_wiz_0/clk_out1] +create_bd_port -dir I -type rst reset +connect_bd_net [get_bd_pins /seg7display_0/reset] [get_bd_ports reset] +create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 xlconcat_0 +set_property -dict [list CONFIG.NUM_PORTS {4}] [get_bd_cells xlconcat_0] +connect_bd_net -net [get_bd_nets tenth_ctr_bin_count] [get_bd_pins xlconcat_0/In0] [get_bd_pins tenth_ctr/bin_count] +connect_bd_net [get_bd_pins xlconcat_0/In1] [get_bd_pins bin2bcd_0/ones] +connect_bd_net [get_bd_pins xlconcat_0/In2] [get_bd_pins bin2bcd_0/tens] +connect_bd_net -net [get_bd_nets minutes_ctr_bin_count] [get_bd_pins xlconcat_0/In3] [get_bd_pins minutes_ctr/bin_count] +connect_bd_net [get_bd_pins xlconcat_0/dout] [get_bd_pins seg7display_0/x_l] + +# Connect reset port to the clr port logic +connect_bd_net -net [get_bd_nets reset_1] [get_bd_ports reset] [get_bd_pins xup_or2_1/b] +connect_bd_net -net [get_bd_nets reset_1] [get_bd_ports reset] [get_bd_pins xup_or2_0/b] +connect_bd_net -net [get_bd_nets reset_1] [get_bd_ports reset] [get_bd_pins xup_or2_2/b] +# Create an enable port and generate enable signals for the counters +create_bd_port -dir I enable +create_bd_cell -type ip -vlnv xilinx.com:XUP:xup_inv:1.0 xup_inv_0 +connect_bd_net [get_bd_ports enable] [get_bd_pins xup_inv_0/a] +connect_bd_net [get_bd_pins tenth_ctr/enable] [get_bd_pins xup_inv_0/y] +create_bd_cell -type ip -vlnv xilinx.com:XUP:xup_and2:1.0 xup_and2_0 +create_bd_cell -type ip -vlnv xilinx.com:XUP:xup_and2:1.0 xup_and2_1 +connect_bd_net -net [get_bd_nets xup_inv_0_y] [get_bd_pins xup_and2_1/b] [get_bd_pins xup_inv_0/y] +connect_bd_net -net [get_bd_nets xup_inv_0_y] [get_bd_pins xup_and2_0/b] [get_bd_pins xup_inv_0/y] +connect_bd_net -net [get_bd_nets tenth_sec_compare_eq] [get_bd_pins xup_and2_1/a] [get_bd_pins tenth_sec_compare/eq] +connect_bd_net [get_bd_pins xup_and2_1/y] [get_bd_pins seconds_ctr/enable] +connect_bd_net -net [get_bd_nets seconds_compare_eq] [get_bd_pins xup_and2_0/a] [get_bd_pins seconds_compare/eq] +connect_bd_net [get_bd_pins xup_and2_0/y] [get_bd_pins minutes_ctr/enable] +# Create output ports and connect them +create_bd_port -dir O -from 6 -to 0 a_to_g +connect_bd_net [get_bd_pins /seg7display_0/a_to_g] [get_bd_ports a_to_g] +create_bd_port -dir O -from 3 -to 0 an_l +connect_bd_net [get_bd_pins /seg7display_0/an_l] [get_bd_ports an_l] +create_bd_port -dir O dp_l +connect_bd_net [get_bd_pins /seg7display_0/dp_l] [get_bd_ports dp_l] +set_property name seg [get_bd_ports a_to_g] +set_property name an [get_bd_ports an_l] +set_property name dp [get_bd_ports dp_l] +validate_bd_design +save_bd_design +make_wrapper -files [get_files $project_directory/$project_name/$project_name.srcs/sources_1/bd/$project_name/$project_name.bd] -top +add_files -norecurse $project_directory/$project_name/$project_name.srcs/sources_1/bd/$project_name/hdl/$project_name\_wrapper.v +# Add pin constraints +add_files -fileset constrs_1 -norecurse $constraints_directory/$constraints_file + diff --git a/Projects/Logic_Design/SN_Design/stop_watch/src/stop_watch_basys3_pins.xdc b/Projects/Logic_Design/SN_Design/stop_watch/src/stop_watch_basys3_pins.xdc new file mode 100644 index 0000000..142fdb1 --- /dev/null +++ b/Projects/Logic_Design/SN_Design/stop_watch/src/stop_watch_basys3_pins.xdc @@ -0,0 +1,42 @@ +#Pin constraints for Digital Clock design for Basys 3 +## Clock signal +set_property PACKAGE_PIN W5 [get_ports sys_clock] +set_property IOSTANDARD LVCMOS33 [get_ports sys_clock] +create_clock -period 10.000 -name sys_clk_pin -waveform {0.000 5.000} -add [get_ports sys_clock] + +# pushbutton BtnC +set_property PACKAGE_PIN U18 [get_ports reset] +set_property IOSTANDARD LVCMOS33 [get_ports reset] + +# pushbutton BtnR +set_property PACKAGE_PIN T17 [get_ports enable] +set_property IOSTANDARD LVCMOS33 [get_ports enable] + +##7 segment display +set_property PACKAGE_PIN W7 [get_ports {seg[0]}] +set_property IOSTANDARD LVCMOS33 [get_ports {seg[0]}] +set_property PACKAGE_PIN W6 [get_ports {seg[1]}] +set_property IOSTANDARD LVCMOS33 [get_ports {seg[1]}] +set_property PACKAGE_PIN U8 [get_ports {seg[2]}] +set_property IOSTANDARD LVCMOS33 [get_ports {seg[2]}] +set_property PACKAGE_PIN V8 [get_ports {seg[3]}] +set_property IOSTANDARD LVCMOS33 [get_ports {seg[3]}] +set_property PACKAGE_PIN U5 [get_ports {seg[4]}] +set_property IOSTANDARD LVCMOS33 [get_ports {seg[4]}] +set_property PACKAGE_PIN V5 [get_ports {seg[5]}] +set_property IOSTANDARD LVCMOS33 [get_ports {seg[5]}] +set_property PACKAGE_PIN U7 [get_ports {seg[6]}] +set_property IOSTANDARD LVCMOS33 [get_ports {seg[6]}] + +set_property PACKAGE_PIN V7 [get_ports dp] +set_property IOSTANDARD LVCMOS33 [get_ports dp] + +set_property PACKAGE_PIN U2 [get_ports {an[0]}] +set_property IOSTANDARD LVCMOS33 [get_ports {an[0]}] +set_property PACKAGE_PIN U4 [get_ports {an[1]}] +set_property IOSTANDARD LVCMOS33 [get_ports {an[1]}] +set_property PACKAGE_PIN V4 [get_ports {an[2]}] +set_property IOSTANDARD LVCMOS33 [get_ports {an[2]}] +set_property PACKAGE_PIN W4 [get_ports {an[3]}] +set_property IOSTANDARD LVCMOS33 [get_ports {an[3]}] + diff --git a/Projects/README.md b/Projects/README.md new file mode 100644 index 0000000..ddc3844 --- /dev/null +++ b/Projects/README.md @@ -0,0 +1,17 @@ +# Basys3 Github +This repository provides Digital Design Libraries and Projects targeting the [Xilinx University Program](www.xilinx.com/university) (XUP) [Basys3 board from Digilent](www.digilentinc.com/Products/Detail.cfm?NavPath=2,400,1288&Prod=BASYS3). + + +The board features an Artix series 7 Xilinx FPGA and is an ideal platform for low cost teaching and student projects. +For questions, please contact the [Xilinx University Program](mailto:xup@xilinx.com). + +### XUP_LIB and 74LSXX_LIB +Two libaries of basic logic elements (AND, OR, XOR, muxes etc) for use in Vivado IP Integrator are available. XUP_LIB includes basic logic gates, and 74LSXX_LIB emulates 74LSXX components. These libraries are intended for use in ditial logic teaching and can be used to build bigger projects graphically or schematically in Vivado IP Integrator. + +### Projects +Projects are grouped according to application areas. Currently, **Logic Design** projects are being developed and made available. The Logic Design projects are built from the basic component libraries. +A library of **Interfaces** will be made available in near future. + +Projects make use of the XUP_LIB and 74LSXX_LIB libraries. It is assumed that you have already downloaded these libraries. +The projects can be created using the provided Tcl script under each project directory. + diff --git a/README.md b/README.md index 36f10c4..23606e8 100644 --- a/README.md +++ b/README.md @@ -1,11 +1,33 @@ -# Basys3 Github -This repository provides Digital Design Libraries and Projects targeting the [Xilinx University Program (XUP) **Basys3 board** from Digilent](www.digilentinc.com/Products/Detail.cfm?NavPath=2,400,1288&Prod=BASYS3). +# Basys3 Github +This repository provides Digital Design Libraries and Projects for Vivado IP Integrator targeting the [Xilinx University Program (XUP) **Basys3 board** from Digilent](http://store.digilentinc.com/basys-3-artix-7-fpga-trainer-board-recommended-for-introductory-users/). The board features an Artix series 7 Xilinx FPGA and is an ideal platform for low cost teaching and student projects. For questions, please contact the [Xilinx University Program](mailto:xup@xilinx.com). +### How to use these files + +Digilient YouTube overview: +http://youtu.be/nJ4LgLWuEcM + + + +### Basys3 Board Files +Download the Basys3 board files (basys3.zip) file and extract it here: **\\2014.4\data\boards\board_parts\artix7** directory. (This has been tested with Vivado 2014.4 but should work with other versions.) After doing this, the board can be selected when creating a project in Vivado. + + ### XUP_LIB and 74LSXX -There are two digital libraries that include basic logic blocks for schematic entry and teaching basic logic design; XUP_LIB (AND, OR, NOT, XOR etc) and 74LSXX models. +There are two digital libraries for Vivado IP Integrator that include basic logic blocks for schematic entry and teaching basic logic design; XUP_LIB (AND, OR, NOT, XOR etc) and 74LSXX models. These libraries include IP blocks are intended for classroom teaching and can be used with the Vivado IP integrator graphical environment to design, simulate and build designs for Xilinx FPGAs using schematics. +## To use the libraries +Create a new Vivado project, and in the *Project settings* (In Vivado, Tools > Project Settings), select the IP tab, and in the *Repository Manager* tab, add the directory of the XUP_LIB and/or 74LSXX folders. You will then be able to add these IP blocks to your designs in IP integrator. + +## To use a project +e.g. Ripple Carry Adder: ./Projects/Logic_Design/CN_Design/Ripple_Carry_Adder +See the readme.md file in the root directory of the project. + +The project can be built by opening Vivado, and running the script provided for each project. + +You can open the script, which is commented, to understand how the project is built diff --git a/basys3.zip b/basys3.zip new file mode 100644 index 0000000..1b7ae7e Binary files /dev/null and b/basys3.zip differ diff --git a/quickstart_guide.pdf b/quickstart_guide.pdf new file mode 100644 index 0000000..bec975c Binary files /dev/null and b/quickstart_guide.pdf differ