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Board layers: make RAM separate load region for AC6 #66

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Merged
VladimirUmek merged 1 commit into from
Mar 2, 2026
Merged

Board layers: make RAM separate load region for AC6 #66

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3 changes: 3 additions & 0 deletions board/Corstone-300/RTE/Device/SSE-300-MPS3/ac6_linker_script.sct.src
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -48,6 +48,9 @@ LR_ROM1 __ROM1_BASE __ROM1_SIZE {
ER_ROM1 __ROM1_BASE __ROM1_SIZE {
*(+RO +XO)
}
}

LR_RAM0 __RAM0_BASE {

RW_NOINIT __RAM0_BASE UNINIT (__RAM0_SIZE - __HEAP_SIZE - __STACK_SIZE - __STACKSEAL_SIZE) {
*.o(.bss.noinit)
Expand Down
3 changes: 3 additions & 0 deletions board/Corstone-315/RTE/Device/SSE-315-FVP/ac6_linker_script.sct.src
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -48,6 +48,9 @@ LR_ROM1 __ROM1_BASE __ROM1_SIZE {
ER_ROM1 __ROM1_BASE __ROM1_SIZE {
*(+RO +XO)
}
}

LR_RAM0 __RAM0_BASE {

RW_NOINIT __RAM0_BASE UNINIT (__RAM0_SIZE - __HEAP_SIZE - __STACK_SIZE - __STACKSEAL_SIZE) {
*.o(.bss.noinit)
Expand Down
3 changes: 3 additions & 0 deletions board/Corstone-320/RTE/Device/SSE-320-FVP/ac6_linker_script.sct.src
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -48,6 +48,9 @@ LR_ROM1 __ROM1_BASE __ROM1_SIZE {
ER_ROM1 __ROM1_BASE __ROM1_SIZE {
*(+RO +XO)
}
}

LR_RAM0 __RAM0_BASE {

RW_NOINIT __RAM0_BASE UNINIT (__RAM0_SIZE - __HEAP_SIZE - __STACK_SIZE - __STACKSEAL_SIZE) {
*.o(.bss.noinit)
Expand Down
3 changes: 3 additions & 0 deletions example/FVP_Audio/board/Corstone-300/RTE/Device/SSE-300-MPS3/ac6_linker_script.sct.src
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -48,6 +48,9 @@ LR_ROM1 __ROM1_BASE __ROM1_SIZE {
ER_ROM1 __ROM1_BASE __ROM1_SIZE {
*(+RO +XO)
}
}

LR_RAM0 __RAM0_BASE {

RW_NOINIT __RAM0_BASE UNINIT (__RAM0_SIZE - __HEAP_SIZE - __STACK_SIZE - __STACKSEAL_SIZE) {
*.o(.bss.noinit)
Expand Down
3 changes: 3 additions & 0 deletions example/FVP_Audio/board/Corstone-315/RTE/Device/SSE-315-FVP/ac6_linker_script.sct.src
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -48,6 +48,9 @@ LR_ROM1 __ROM1_BASE __ROM1_SIZE {
ER_ROM1 __ROM1_BASE __ROM1_SIZE {
*(+RO +XO)
}
}

LR_RAM0 __RAM0_BASE {

RW_NOINIT __RAM0_BASE UNINIT (__RAM0_SIZE - __HEAP_SIZE - __STACK_SIZE - __STACKSEAL_SIZE) {
*.o(.bss.noinit)
Expand Down
3 changes: 3 additions & 0 deletions example/FVP_Audio/board/Corstone-320/RTE/Device/SSE-320-FVP/ac6_linker_script.sct.src
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -48,6 +48,9 @@ LR_ROM1 __ROM1_BASE __ROM1_SIZE {
ER_ROM1 __ROM1_BASE __ROM1_SIZE {
*(+RO +XO)
}
}

LR_RAM0 __RAM0_BASE {

RW_NOINIT __RAM0_BASE UNINIT (__RAM0_SIZE - __HEAP_SIZE - __STACK_SIZE - __STACKSEAL_SIZE) {
*.o(.bss.noinit)
Expand Down
3 changes: 3 additions & 0 deletions example/FVP_Hello/board/Corstone-300/RTE/Device/SSE-300-MPS3/ac6_linker_script.sct.src
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -48,6 +48,9 @@ LR_ROM1 __ROM1_BASE __ROM1_SIZE {
ER_ROM1 __ROM1_BASE __ROM1_SIZE {
*(+RO +XO)
}
}

LR_RAM0 __RAM0_BASE {

RW_NOINIT __RAM0_BASE UNINIT (__RAM0_SIZE - __HEAP_SIZE - __STACK_SIZE - __STACKSEAL_SIZE) {
*.o(.bss.noinit)
Expand Down
3 changes: 3 additions & 0 deletions example/FVP_Hello/board/Corstone-315/RTE/Device/SSE-315-FVP/ac6_linker_script.sct.src
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -48,6 +48,9 @@ LR_ROM1 __ROM1_BASE __ROM1_SIZE {
ER_ROM1 __ROM1_BASE __ROM1_SIZE {
*(+RO +XO)
}
}

LR_RAM0 __RAM0_BASE {

RW_NOINIT __RAM0_BASE UNINIT (__RAM0_SIZE - __HEAP_SIZE - __STACK_SIZE - __STACKSEAL_SIZE) {
*.o(.bss.noinit)
Expand Down
3 changes: 3 additions & 0 deletions example/FVP_Hello/board/Corstone-320/RTE/Device/SSE-320-FVP/ac6_linker_script.sct.src
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -48,6 +48,9 @@ LR_ROM1 __ROM1_BASE __ROM1_SIZE {
ER_ROM1 __ROM1_BASE __ROM1_SIZE {
*(+RO +XO)
}
}

LR_RAM0 __RAM0_BASE {

RW_NOINIT __RAM0_BASE UNINIT (__RAM0_SIZE - __HEAP_SIZE - __STACK_SIZE - __STACKSEAL_SIZE) {
*.o(.bss.noinit)
Expand Down
3 changes: 3 additions & 0 deletions example/FVP_Video/board/Corstone-300/RTE/Device/SSE-300-MPS3/ac6_linker_script.sct.src
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -48,6 +48,9 @@ LR_ROM1 __ROM1_BASE __ROM1_SIZE {
ER_ROM1 __ROM1_BASE __ROM1_SIZE {
*(+RO +XO)
}
}

LR_RAM0 __RAM0_BASE {

RW_NOINIT __RAM0_BASE UNINIT (__RAM0_SIZE - __HEAP_SIZE - __STACK_SIZE - __STACKSEAL_SIZE) {
*.o(.bss.noinit)
Expand Down
3 changes: 3 additions & 0 deletions example/FVP_Video/board/Corstone-315/RTE/Device/SSE-315-FVP/ac6_linker_script.sct.src
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -48,6 +48,9 @@ LR_ROM1 __ROM1_BASE __ROM1_SIZE {
ER_ROM1 __ROM1_BASE __ROM1_SIZE {
*(+RO +XO)
}
}

LR_RAM0 __RAM0_BASE {

RW_NOINIT __RAM0_BASE UNINIT (__RAM0_SIZE - __HEAP_SIZE - __STACK_SIZE - __STACKSEAL_SIZE) {
*.o(.bss.noinit)
Expand Down
3 changes: 3 additions & 0 deletions example/FVP_Video/board/Corstone-320/RTE/Device/SSE-320-FVP/ac6_linker_script.sct.src
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -48,6 +48,9 @@ LR_ROM1 __ROM1_BASE __ROM1_SIZE {
ER_ROM1 __ROM1_BASE __ROM1_SIZE {
*(+RO +XO)
}
}

LR_RAM0 __RAM0_BASE {

RW_NOINIT __RAM0_BASE UNINIT (__RAM0_SIZE - __HEAP_SIZE - __STACK_SIZE - __STACKSEAL_SIZE) {
*.o(.bss.noinit)
Expand Down