ECE graduate student working on processor microarchitecture and embedded systems.
RISC-V cores, RTL design (SystemVerilog), and hardware–software co-design.
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UW Madison
- in/abhinarayani-v
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Task__v2.0
Task__v2.0 PublicForked from Nikhilroy2205/Task__v2.0
Contains files with sorting algorithm
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multiPrecisionSystolicArray
multiPrecisionSystolicArray PublicA SystemVerilog implementation of a dynamically reconfigurable multi-precision systolic array for Quantized Neural Network workloads
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Software-Directed-Prefeching-for-Irregular-SpMV-Workloads
Software-Directed-Prefeching-for-Irregular-SpMV-Workloads PublicArchitect high-performance SpMV kernels using OpenMP/CUDA, with manual prefetching and warp-level primitives. Analyzed memory sub-system impact via Linux perf and NVIDIA Nsight Compute to optimize …
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