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Merged
AnshKetchum merged 5 commits into from
Oct 2, 2025
Merged

Feature/remove low level cas signals #20

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12cc78e
Swap bank scheduler and bank to use DRAM ops instead of low-level sig…
AnshKetchum Oct 2, 2025
c9c75b1
Port verilog modules over to use op format instead of ras/cas
AnshKetchum Oct 2, 2025
d14d97b
Map names over
AnshKetchum Oct 2, 2025
a84d2bf
Integrate non-single cycle timing matrix
AnshKetchum Oct 2, 2025
80a707e
Bump tests
AnshKetchum Oct 2, 2025
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2 changes: 1 addition & 1 deletion ...ysim/integration/src/main/scala/memorysim/integration/chipyard/SimMemorySimExecutor.scala
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Expand Up @@ -37,7 +37,7 @@ class SimMemorySimExecutor(
memConfiguration = MemoryConfigurationParameters(
addressWidth = addrBits,
dataWidth = dataBits,
numberOfChannels = 1,
numberOfChannels = 4,
numberOfRanks = 2,
numberOfBanks = 8,
memoryQueueSize = 8
Expand Down
86 changes: 31 additions & 55 deletions memorysim/memctrl/src/main/resources/vsrc/BankPhysicalMemoryRequestPerformanceStatistics.sv
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Expand Up @@ -7,70 +7,46 @@ module BankPhysicalMemoryRequestPerformanceStatistics #(
parameter int GLOBAL_CYCLE_BITS,
parameter int REQUEST_ID_BITS
)(
input wire clk,
input wire reset,
input wire req_fire,
input wire [ADDRESS_WIDTH-1:0] addr,
input wire [DATA_WIDTH-1:0] data,
input wire cs,
input wire ras,
input wire cas,
input wire we,
input wire [GLOBAL_CYCLE_BITS-1:0] globalCycle,
input wire [REQUEST_ID_BITS-1:0] request_id,
input wire [REQUEST_ID_BITS-1:0] internal_req_id,
input wire [REQUEST_ID_BITS-1:0] channel_id,
input wire [REQUEST_ID_BITS-1:0] rank_id,
input wire [REQUEST_ID_BITS-1:0] bank_id,
input wire [REQUEST_ID_BITS-1:0] scheduler_id
input wire clk,
input wire reset,
input wire req_fire,
input wire [ADDRESS_WIDTH-1:0] addr,
input wire [DATA_WIDTH-1:0] data,
input wire [DATA_WIDTH-1:0] op, // DRAMOp value (width defined upstream)
input wire [GLOBAL_CYCLE_BITS-1:0] globalCycle,
input wire [REQUEST_ID_BITS-1:0] request_id,
input wire [REQUEST_ID_BITS-1:0] internal_req_id,
input wire [REQUEST_ID_BITS-1:0] channel_id,
input wire [REQUEST_ID_BITS-1:0] rank_id,
input wire [REQUEST_ID_BITS-1:0] bank_id,
input wire [REQUEST_ID_BITS-1:0] scheduler_id
);
integer file;
reg [1023:0] filename;

reg [8*24-1:0] opString; // longest string = "SELF REFRESH ENTER"

initial begin
$sformat(filename, "bank_req_queue_stats_channel%0d_rank%0d_bank%0d.csv", CHANNEL, RANK, BANK);
file = $fopen(filename, "w");
$fwrite(file, "RequestID,InternalReqID,ChannelID,RankID,BankID,SchedulerID,Address,Type,Cycle\n");
end

always @(posedge clk) begin
if (reset) begin
end else if (req_fire) begin
if(cs == 0 && ras == 0 && cas == 0 && we == 1) begin
$fwrite(file, "%d,%d,%d,%d,%d,%d,%d,%s,%d\n",
request_id, internal_req_id, channel_id, rank_id, bank_id, scheduler_id,
addr, "REFRESH", globalCycle);
end
else if(cs == 0 && ras == 0 && cas == 1 && we == 0) begin
$fwrite(file, "%d,%d,%d,%d,%d,%d,%d,%s,%d\n",
request_id, internal_req_id, channel_id, rank_id, bank_id, scheduler_id,
addr, "PRECHARGE", globalCycle);
end
else if(cs == 0 && ras == 0 && cas == 1 && we == 1) begin
$fwrite(file, "%d,%d,%d,%d,%d,%d,%d,%s,%d\n",
request_id, internal_req_id, channel_id, rank_id, bank_id, scheduler_id,
addr, "ACTIVATE", globalCycle);
end
else if(cs == 0 && ras == 1 && cas == 0 && we == 1) begin
$fwrite(file, "%d,%d,%d,%d,%d,%d,%d,%s,%d\n",
request_id, internal_req_id, channel_id, rank_id, bank_id, scheduler_id,
addr, "READ", globalCycle);
end
else if(cs == 0 && ras == 1 && cas == 0 && we == 0) begin
$fwrite(file, "%d,%d,%d,%d,%d,%d,%d,%s,%d\n",
request_id, internal_req_id, channel_id, rank_id, bank_id, scheduler_id,
addr, "WRITE", globalCycle);
end
else if(cs == 0 && ras == 0 && cas == 0 && we == 0) begin
$fwrite(file, "%d,%d,%d,%d,%d,%d,%d,%s,%d\n",
request_id, internal_req_id, channel_id, rank_id, bank_id, scheduler_id,
addr, "SELF REFRESH ENTER", globalCycle);
end
else if(cs == 0 && ras == 1 && cas == 1 && we == 1) begin
$fwrite(file, "%d,%d,%d,%d,%d,%d,%d,%s,%d\n",
request_id, internal_req_id, channel_id, rank_id, bank_id, scheduler_id,
addr, "SELF REFRESH EXIT", globalCycle);
end
if (!reset && req_fire) begin
case (op)
0: opString = "REFRESH";
1: opString = "PRECHARGE";
2: opString = "ACTIVATE";
3: opString = "READ";
4: opString = "WRITE";
5: opString = "SELF REFRESH ENTER";
6: opString = "SELF REFRESH EXIT";
default: opString = "UNKNOWN";
endcase

$fwrite(file, "%0d,%0d,%0d,%0d,%0d,%0d,%0h,%s,%0d\n",
request_id, internal_req_id, channel_id, rank_id, bank_id, scheduler_id,
addr, opString, globalCycle);
end
end
endmodule
endmodule
68 changes: 24 additions & 44 deletions ...emctrl/src/main/resources/vsrc/BankSchedulerPhysicalMemoryRequestPerformanceStatistics.sv
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Expand Up @@ -12,10 +12,7 @@ module BankSchedulerPhysicalMemoryRequestPerformanceStatistics #(
input wire req_fire,
input wire [ADDRESS_WIDTH-1:0] addr,
input wire [DATA_WIDTH-1:0] data,
input wire cs,
input wire ras,
input wire cas,
input wire we,
input wire [DATA_WIDTH-1:0] op, // DRAMOp enum encoding
input wire [GLOBAL_CYCLE_BITS-1:0] globalCycle,
input wire [REQUEST_ID_BITS-1:0] request_id,
input wire [REQUEST_ID_BITS-1:0] internal_req_id,
Expand All @@ -27,55 +24,38 @@ module BankSchedulerPhysicalMemoryRequestPerformanceStatistics #(
integer file;
reg [1023:0] filename;

// Request type encoding (small integer IDs)
// +-----------------------+---------+
// | String | ID |
// +-----------------------+---------+
// | REFRESH | 0 |
// | PRECHARGE | 1 |
// | ACTIVATE | 2 |
// | READ | 3 |
// | WRITE | 4 |
// | SELF REFRESH ENTER | 5 |
// | SELF REFRESH EXIT | 6 |
// | UNKNOWN | 7 |
// +-----------------------+---------+
//
// Use a small packed reg to avoid wide string literal assignments
// and the associated WIDTHEXPAND warnings.
reg [2:0] reqType; // holds 0..7 per table above
// String register (max 16 chars wide here)
reg [8*16-1:0] opString;

initial begin
$sformat(filename, "memory_request_queue_stats_scheduler_channel%0d_rank%0d_bank%0d.csv", CHANNEL, RANK, BANK);
$sformat(filename,
"memory_request_queue_stats_scheduler_channel%0d_rank%0d_bank%0d.csv",
CHANNEL, RANK, BANK);
file = $fopen(filename, "w");
$fwrite(file, "RequestID,InternalReqID,ChannelID,RankID,BankID,SchedulerID,Address,Data,TypeID,Cycle\n");
$fwrite(file,
"RequestID,InternalReqID,ChannelID,RankID,BankID,SchedulerID,Address,Data,Op,Cycle\n");
end

always @(posedge clk) begin
if (!reset && req_fire) begin
// Encode DRAM command type as a small integer ID
if (cs == 0 && ras == 0 && cas == 0 && we == 1)
reqType = 0; // REFRESH
else if (cs == 0 && ras == 0 && cas == 1 && we == 0)
reqType = 1; // PRECHARGE
else if (cs == 0 && ras == 0 && cas == 1 && we == 1)
reqType = 2; // ACTIVATE
else if (cs == 0 && ras == 1 && cas == 0 && we == 1)
reqType = 3; // READ
else if (cs == 0 && ras == 1 && cas == 0 && we == 0)
reqType = 4; // WRITE
else if (cs == 0 && ras == 0 && cas == 0 && we == 0)
reqType = 5; // SELF REFRESH ENTER
else if (cs == 0 && ras == 1 && cas == 1 && we == 1)
reqType = 6; // SELF REFRESH EXIT
else
reqType = 7; // UNKNOWN
// Map op code to string name
case (op)
0: opString = "ACTIVATE";
1: opString = "READ";
2: opString = "WRITE";
3: opString = "READ_PRECHARGE";
4: opString = "WRITE_PRECHARGE";
5: opString = "PRECHARGE";
6: opString = "REFRESH";
7: opString = "SELFREF_ENTER";
8: opString = "SELFREF_EXIT";
default: opString = "UNKNOWN";
endcase

// Log CSV with numeric type ID (avoids wide string assignments)
// Fields: RequestID,InternalReqID,ChannelID,RankID,BankID,SchedulerID,Address,Data,TypeID,Cycle
$fwrite(file, "%d,%d,%d,%d,%d,%d,%d,%d,%d,%d\n",
// Log CSV with string field
$fwrite(file, "%0d,%0d,%0d,%0d,%0d,%0d,%0h,%0h,%s,%0d\n",
request_id, internal_req_id, channel_id, rank_id, bank_id, scheduler_id,
addr, data, reqType, globalCycle);
addr, data, opString, globalCycle);
end
end
endmodule
60 changes: 21 additions & 39 deletions memorysim/memctrl/src/main/resources/vsrc/CommandQueuePerformanceStatisticsInput.sv
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Expand Up @@ -9,10 +9,7 @@ module CommandQueuePerformanceStatisticsInput #(
input wire req_fire,
input wire [ADDRESS_WIDTH-1:0] addr,
input wire [DATA_WIDTH-1:0] data,
input wire cs,
input wire ras,
input wire cas,
input wire we,
input wire [DATA_WIDTH-1:0] op, // DRAMOp enum encoding
input wire [GLOBAL_CYCLE_BITS-1:0] globalCycle,
input wire [REQUEST_ID_BITS-1:0] request_id,
input wire [REQUEST_ID_BITS-1:0] internal_req_id,
Expand All @@ -22,48 +19,33 @@ module CommandQueuePerformanceStatisticsInput #(
input wire [REQUEST_ID_BITS-1:0] scheduler_id
);
integer file;
reg [8*24-1:0] opString; // wide enough to hold longest name

initial begin
file = $fopen("memory_request_queue_stats.csv", "w");
$fwrite(file, "RequestID,InternalReqID,Channel,Rank,Bank,Scheduler,Address,Type,Cycle\n");
end

always @(posedge clk) begin
if (!reset && req_fire) begin
if(cs == 0 && ras == 0 && cas == 0 && we == 1) begin
$fwrite(file, "%0d,%0d,%0d,%0d,%0d,%0d,%0d,%s,%0d\n",
request_id, internal_req_id, channel_id, rank_id, bank_id, scheduler_id,
addr, "REFRESH", globalCycle);
end
else if(cs == 0 && ras == 0 && cas == 1 && we == 0) begin
$fwrite(file, "%0d,%0d,%0d,%0d,%0d,%0d,%0d,%s,%0d\n",
request_id, internal_req_id, channel_id, rank_id, bank_id, scheduler_id,
addr, "PRECHARGE", globalCycle);
end
else if(cs == 0 && ras == 0 && cas == 1 && we == 1) begin
$fwrite(file, "%0d,%0d,%0d,%0d,%0d,%0d,%0d,%s,%0d\n",
request_id, internal_req_id, channel_id, rank_id, bank_id, scheduler_id,
addr, "ACTIVATE", globalCycle);
end
else if(cs == 0 && ras == 1 && cas == 0 && we == 1) begin
$fwrite(file, "%0d,%0d,%0d,%0d,%0d,%0d,%0d,%s,%0d\n",
request_id, internal_req_id, channel_id, rank_id, bank_id, scheduler_id,
addr, "READ", globalCycle);
end
else if(cs == 0 && ras == 1 && cas == 0 && we == 0) begin
$fwrite(file, "%0d,%0d,%0d,%0d,%0d,%0d,%0d,%s,%0d\n",
request_id, internal_req_id, channel_id, rank_id, bank_id, scheduler_id,
addr, "WRITE", globalCycle);
end
else if(cs == 0 && ras == 0 && cas == 0 && we == 0) begin
$fwrite(file, "%0d,%0d,%0d,%0d,%0d,%0d,%0d,%s,%0d\n",
request_id, internal_req_id, channel_id, rank_id, bank_id, scheduler_id,
addr, "SELF REFRESH ENTER", globalCycle);
end
else if(cs == 0 && ras == 1 && cas == 1 && we == 1) begin
$fwrite(file, "%0d,%0d,%0d,%0d,%0d,%0d,%0d,%s,%0d\n",
request_id, internal_req_id, channel_id, rank_id, bank_id, scheduler_id,
addr, "SELF REFRESH EXIT", globalCycle);
end
// Map op enum to human-readable string
case (op)
0: opString = "ACTIVATE";
1: opString = "READ";
2: opString = "WRITE";
3: opString = "READ_PRECHARGE";
4: opString = "WRITE_PRECHARGE";
5: opString = "PRECHARGE";
6: opString = "REFRESH";
7: opString = "SELFREF_ENTER";
8: opString = "SELFREF_EXIT";
default: opString = "UNKNOWN";
endcase

// Log CSV with string op
$fwrite(file, "%0d,%0d,%0d,%0d,%0d,%0d,%0h,%s,%0d\n",
request_id, internal_req_id, channel_id, rank_id, bank_id, scheduler_id,
addr, opString, globalCycle);
end
end
endmodule
1 change: 0 additions & 1 deletion memorysim/memctrl/src/main/resources/vsrc/SystemQueuePerformanceStatisticsInput.sv
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Expand Up @@ -18,7 +18,6 @@ module SystemQueuePerformanceStatisticsInput #(
initial begin
file = $fopen("input_request_stats.csv", "w");
$fwrite(file, "RequestID,Address,Read,Write,Cycle,Write Data\n");
$display("IN VERILOG INPUT");
end


Expand Down
1 change: 0 additions & 1 deletion memorysim/memctrl/src/main/resources/vsrc/SystemQueuePerformanceStatisticsOutput.sv
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Expand Up @@ -19,7 +19,6 @@ module SystemQueuePerformanceStatisticsOutput #(
initial begin
file = $fopen("output_request_stats.csv", "w");
$fwrite(file, "RequestID,Address,Read,Write,Cycle, Write Data,Response\n");
$display("IN VERILOG OUTPUT");
end


Expand Down
32 changes: 10 additions & 22 deletions ...ctrl/src/main/scala/memorysim/memctrl/controller/schedulers/ClosedPageBankScheduler.scala
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Expand Up @@ -92,20 +92,17 @@ class ClosedPageBankScheduler(
// Default command fields
cmdReg.addr := reqAddrReg
cmdReg.data := reqWdataReg
cmdReg.cs := true.B
cmdReg.ras := false.B
cmdReg.cas := false.B
cmdReg.we := false.B
cmdReg.op := DRAMOp.ACTIVATE // Default, will be overridden
cmdReg.request_id := activateReqPacket // Default, will be overridden
io.cmdOut.bits := cmdReg

// Issue commands when in command states and haven't sent yet
val issueStates = Seq(sActivate, sReadWrite, sRefresh)
io.cmdOut.valid := issueStates.map(_ === state).reduce(_ || _) && !sentCmd && !cmdReg.cs
io.cmdOut.valid := issueStates.map(_ === state).reduce(_ || _) && !sentCmd

// Response data wire
val responseDataWire = Wire(UInt(memoryConfig.dataWidth.W))
responseDataWire := Mux(reqIsRead, responseDataReg, 0.U)
responseDataWire := responseDataReg

val respReg = Wire(new ControllerResponse(memoryConfig))
respReg.addr := reqAddrReg
Expand Down Expand Up @@ -155,11 +152,8 @@ class ClosedPageBankScheduler(

is(sActivate) {
when(!sentCmd) {
// Send ACTIVATE command with internal_req_id = 1
cmdReg.cs := false.B
cmdReg.ras := false.B
cmdReg.cas := true.B
cmdReg.we := true.B
// Send ACTIVATE command
cmdReg.op := DRAMOp.ACTIVATE
cmdReg.request_id := activateReqPacket
}
when(io.cmdOut.fire) {
Expand All @@ -173,11 +167,8 @@ class ClosedPageBankScheduler(

is(sReadWrite) {
when(!sentCmd) {
// Send READ or WRITE command with internal_req_id = 2 or 3
cmdReg.cs := false.B
cmdReg.ras := true.B
cmdReg.cas := false.B
cmdReg.we := Mux(reqIsRead, true.B, false.B)
// Send READ or WRITE command
cmdReg.op := Mux(reqIsRead, DRAMOp.READ, DRAMOp.WRITE)
cmdReg.request_id := readWriteReqPacket
}
when(io.cmdOut.fire) {
Expand Down Expand Up @@ -208,11 +199,8 @@ class ClosedPageBankScheduler(

is(sRefresh) {
when(!sentCmd) {
// Send REFRESH command with internal_req_id = refreshCounter
cmdReg.cs := false.B
cmdReg.ras := false.B
cmdReg.cas := false.B
cmdReg.we := true.B
// Send REFRESH command
cmdReg.op := DRAMOp.REFRESH
cmdReg.addr := refreshAddr
cmdReg.request_id := refreshReqPacket
}
Expand Down Expand Up @@ -251,4 +239,4 @@ class ClosedPageBankScheduler(
) &&
(respDec.io.rankIndex === localConfiguration.rankIndex.U) &&
(respDec.io.bankIndex === localConfiguration.bankIndex.U)
}
}
10 changes: 2 additions & 8 deletions memorysim/memctrl/src/main/scala/memorysim/memctrl/memories/PhysicalMemoryGenerics.scala
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Expand Up @@ -17,10 +17,7 @@ class RequestPacket(params: MemoryConfigurationParameters) extends Bundle {
class PhysicalMemoryCommand(params: MemoryConfigurationParameters) extends Bundle {
val addr = UInt(params.addressWidth.W)
val data = UInt(params.dataWidth.W)
val cs = Bool()
val ras = Bool()
val cas = Bool()
val we = Bool()
val op = UInt(params.dataWidth.W) // Encoded DRAM operation
val request_id = new RequestPacket(params)
}

Expand Down Expand Up @@ -48,10 +45,7 @@ class PhysicalMemoryIO(params: MemoryConfigurationParameters) extends Bundle {
class BankMemoryCommand(params: MemoryConfigurationParameters) extends Bundle {
val addr = UInt(params.addressWidth.W)
val data = UInt(params.dataWidth.W)
val cs = Bool()
val ras = Bool()
val cas = Bool()
val we = Bool()
val op = UInt(params.dataWidth.W) // Encoded DRAM operation
val request_id = new RequestPacket(params)
val lastColBankGroup = UInt(32.W)
val lastColCycle = UInt(32.W)
Expand Down
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