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1. AHB-to-APB-Bridge-Verification AHB-to-APB-Bridge-Verification Public

   The AHB to APB Bridge is an interface bus system that builds data flow synchronization between high-speed AHB and low-peripheral APB IPs. It is based on AMBA Protocols.

   Verilog 3 1

2. 1011-sequence-detector---UVM-Verification 1011-sequence-detector---UVM-Verification Public

   The 1011 sequence detector UVM testbench verifies functionality using randomized and directed stimuli. A scoreboard compares DUT output with expected results, while coverage ensures all input patte…

   SystemVerilog 1

3. APB3-MASTER-FORMAL-VERIFICATION APB3-MASTER-FORMAL-VERIFICATION Public

   Formally verified an APB3 master design using SystemVerilog Assertions by constraining valid APB3 slave behavior and proving protocol compliance, functional correctness, reset safety, and error han…

   SystemVerilog 1

4. APB3-SLAVE-FORMAL-VERIFICATION APB3-SLAVE-FORMAL-VERIFICATION Public

   Formally verified an APB3 slave design using SystemVerilog Assertions by constraining valid APB3 master behavior and proving protocol compliance, functional correctness, reset safety, and error han…

   SystemVerilog 1

5. Router-1x3-Design-and-Verfication Router-1x3-Design-and-Verfication Public

   Router1X3 efficiently routes data from one input to three outputs based on control logic. Verified using UVM, it employs a robust, reusable testbench framework for comprehensive functional checks, …

   SystemVerilog

6. APB3_VIP_DEVELOPMENT APB3_VIP_DEVELOPMENT Public

   APB3 Master and Slave Verification IP developed in SystemVerilog using UVM, supporting read/write transactions, wait-state handling, protocol checking, and functional coverage for APB3-based designs.

   SystemVerilog