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Lab02 by benson #2

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213 changes: 141 additions & 72 deletions Lab01/bonus/RGB_LED.v
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Original file line number Diff line number Diff line change
Expand Up @@ -12,100 +12,169 @@ module RGB_LED(
output reg[3:0]led
);
reg [6:0]counter;
reg [3:0]sub_counter;
reg [3:0]timer;
reg [3:0]t1;
reg [3:0]t2;
reg [3:0]t3;
reg [6:0]a;
reg [6:0]b;
reg [6:0]c;
reg [6:0]d;
reg [6:0]e;
reg [6:0]f;
reg flag;
parameter NORMAL = 2'b00;
parameter T1 = 2'b01;
parameter T2 = 2'b10;
parameter T3 = 2'b11;

always@(negedge start)begin
case(sw)
T1:begin
t1<=timer;
timer<=4'b0;
end

T2:begin
t2<=timer;
timer<=4'b0;
end

T3:begin
t3<=timer;
timer<=4'b0;
end

default:begin

end
endcase
end
always@(posedge clk)begin
if(start)begin
timer<=timer+4'b1;
led[0]<=timer[0];
led[1]<=timer[1];
led[2]<=timer[2];
led[3]<=timer[3];
end
else
led<=4'b0;
always@(*)begin
a=t3;
b=a+t2;
c=b+t1;
d=c+t3;
e=d+t2;
f=e+t1;
end



always@(posedge clk or posedge rst)begin
if(rst)begin
counter<=7'b0;
led4_b<=0;
led4_g<=0;
led4_r<=0;
led4_r<=1;
led5_b<=0;
led5_g<=0;
led5_r<=0;
t1<=4'd1;
led5_r<=1;
t1<=4'd1;
t2<=4'd5;
t3<=4'd1;
led<=4'b0;
sub_counter<=4'b1;

end
else begin
counter<=counter+7'b1;

case(counter)
7'd0:begin
led4_g<=1'b0;
led4_b<=1'b0;
led5_g<=1'b0;
led5_b<=1'b0;
led4_r<=1'b1;
led5_r<=1'b1;
end
t3:begin
led4_r<=1'b0;
led4_g<=1'b1;
end

t3+t2:begin
led4_r<=1'b1;
end

t3+t2+t1:begin
led4_g<=1'b0;
end

t3+t2+t1+t3:begin
led5_r<=1'b0;
led5_g<=1'b1;
end

t3+t2+t1+t3+t2:begin
led5_r<=1'b1;
counter<=7'b0;
end

endcase
if(start)begin
timer<=timer+4'b1;
case(sw)
T1:begin
t1<=timer;
led<=timer;
end

T2:begin
t2<=timer;
led<=timer;
end

T3:begin
t3<=timer;
led<=timer;
end

default:begin
led<=4'b0;
end
endcase
end
else begin
timer<=4'b0;
case(sw)
NORMAL:begin
case(counter)
a:begin//GR
led4_r<=1'b0;
led4_g<=1'b1;
counter<=counter+7'b1;
sub_counter<=4'b1;
led<=4'b1;
end

b:begin//YR
led4_r<=1'b1;
counter<=counter+7'b1;
sub_counter<=4'b1;
led<=4'b1;
end

c:begin//RR
led4_g<=1'b0;
counter<=counter+7'b1;
sub_counter<=4'b1;
led<=4'b1;
end

d:begin//RG
led5_r<=1'b0;
led5_g<=1'b1;
counter<=counter+7'b1;
sub_counter<=4'b1;
led<=4'b1;
end

e:begin//RY
led5_r<=1'b1;
counter<=counter+7'b1;
sub_counter<=4'b1;
led<=4'b1;
end

f:begin//RR
led4_g<=1'b0;
led4_b<=1'b0;
led5_g<=1'b0;
led5_b<=1'b0;
led4_r<=1'b1;
led5_r<=1'b1;
counter<=7'b1;
sub_counter<=4'b1;
led<=4'b1;

end

default:begin
counter<=counter+7'b1;
sub_counter<=sub_counter+4'b1;
led<=sub_counter+4'b1;
end
endcase
end
T1:begin//yellow
led4_b<=0;
led4_g<=1;
led4_r<=1;
led5_b<=0;
led5_g<=1;
led5_r<=1;
end

T2:begin//green
led4_b<=0;
led4_g<=1;
led4_r<=0;
led5_b<=0;
led5_g<=1;
led5_r<=0;
end

T3:begin//red
led4_b<=0;
led4_g<=0;
led4_r<=1;
led5_b<=0;
led5_g<=0;
led5_r<=1;
end

default:begin
led<=4'b0;
end
endcase
end//outer else



end
end
endmodule
2 changes: 2 additions & 0 deletions Lab01/bonus/blinky.xdc
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Original file line number Diff line number Diff line change
@@ -0,0 +1,2 @@
create_clock -period 8.000 -name sys_clk_pin -waveform {0.000 4.000} -add [get_ports clk]
create_generated_clock -name clk_div -divide_by 125000000 -source [get_ports clk] [get_pins div_0/clk_div_reg/Q];
31 changes: 24 additions & 7 deletions Lab01/bonus/divider.v
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Original file line number Diff line number Diff line change
@@ -1,25 +1,42 @@
module divider(
input clk,//125MHz
input rst,
input start,
output reg clk_div
);

reg recover;
reg [26:0] cnt;

always@(posedge clk or posedge rst) begin
if (rst) begin
cnt <= 27'd0;
clk_div <= 27'b0;
clk_div <= 1'b0;
recover <= 1'b0;
end
else begin

if (cnt == 125000000 - 1) begin
cnt <= 27'd0;
clk_div <= 'b1;
clk_div <= 1'b1;
end
else begin
cnt <= cnt + 1;
clk_div <= 27'b0;
else begin
if(!recover) begin
if(start) begin
clk_div<=1'b1;
recover<=1'b1;
cnt<=27'b0;
end
else begin
cnt <= cnt + 27'b1;
clk_div <= 1'b0;
end

end
else begin
cnt <= cnt + 27'b1;
clk_div <= 1'b0;

end

end
end
end
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