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Schematic

FPGA Reaction Timer

Measures your reaction time in milliseconds. Built on a Basys 3 board for a digital design course.

How It Works

  1. Press center button to start
  2. Watch the decimal points count down (don't press early or you get "Err")
  3. When the dots turn off, press as fast as you can
  4. Your time shows on the 7-segment display

Stores your last 3 attempts and calculates min/max/average. The random delay after countdown prevents anticipation cheating.

Implementation

Written in VHDL. Uses a simple state machine:

  • WAITING → COUNTDOWN → RANDOM_DELAY → TIMING → RESULT

The millisecond counter runs off a divided clock. Display multiplexing handled by a separate module since the Basys 3 only has one set of segment pins for all 4 digits.

Most annoying bug: the countdown decimal points were active-low but I wrote the logic as active-high. Spent two hours wondering why everything was inverted.

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FPGA Reaction Timer

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