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Achievement: Pair ExtraordinaireAchievement: QuickdrawAchievement: YOLOAchievement: Pull Shark

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@PantheraLabs

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CodedRichy/README.md

RISHI PRASEETH KRISHNAN

Building backend-heavy applications, system tools, and automation pipelines.
Focused on correctness, performance, and developer ergonomics.

B.Tech Computer Science @ Muthoot Institute of Technology and Science






❖ CORE PROJECTS

Selected engineering projects. Some repositories are private; descriptions focus on architecture and technical guarantees.


↳ Expenso — Ledger-Based Group Expense System

A cross-platform group expense application designed around strict accounting invariants.

Key Engineering Decisions:
• Append-only expense revisions (no destructive updates)
• Integer minor-unit accounting to eliminate rounding errors
• Deterministic settlement computation (zero-sum invariant enforced)
• Natural-language expense parsing using Groq/Llama
• Direct UPI intent-based settlement flows
Stack: Flutter, Firebase, Groq

↳ AAE — Passive Presence Verification Framework

A decentralized, infrastructure-independent framework for high-integrity presence tracking.

Technical Highlights:
• Proximity Mesh using BLE and Union-Find DJS algorithm
• Multi-modal anti-spoofing via gyroscope and light sensor fusion
• Differential privacy core with ephemeral identity tokens
• High-frequency ingestion via Node.js and Redis
Stack: Flutter, Node.js, Redis, PostgreSQL

↳ GitPulse — Autonomous Git Synchronization Daemon

A background service that automates Git workflows with per-repo safety guarantees.

Core Mechanisms:
• File-system event debouncing per repository
• AI-generated commit summaries from diff context using Groq
• Automated push failure recovery and auth retries
• Designed for low-latency background monitoring
Stack: Python, Git, Groq

↳ LiteCPU16 — 16-bit Single-Cycle Processor

A minimal educational CPU designed to demonstrate hardware-level instruction execution.

Core Architecture Features:
• 16-bit Harvard Architecture designed in Verilog (HDL)
• Modular 8-file structure (ALU, Control Unit, Register File)
• Executes fundamental RISC instruction set (ADD, LW, SW, BEQ)
• Validated via simulation in Icarus Verilog
Stack: Verilog, Icarus Verilog



❖ EXPERIENCE

Role Organization Timeline Focus
Tech Subcommittee Member MITS Media Club Oct 2024 – Present Technical direction and infrastructure
Member MITS Motorsports Oct 2024 – Present Engineering and team operations
Apprentice Trainee Soften Technologies May 2024 – Aug 2024 Backend development (Python & JavaScript)



❖ INTERESTS

  • Backend & systems engineering
  • Developer tooling and automation
  • Correctness-first application design
  • Performance-aware architectures



❖ GITHUB STATS

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  1. PantheraLabs/IntentCompiler PantheraLabs/IntentCompiler Public

    Compile structured intent into reliable AI workflows — no prompt engineering required

    TypeScript 2

  2. GitPulse GitPulse Public

    Commit firewall for AI-generated code

    TypeScript