[Handshake] Clean up generation of LSQ ordering/port information

[MaxWipfli]

Previously, three configuration values (ldOrder, ldPortIdx, stPortIdx) used an unneeded special case if a group did not contain any load/store ports at all. There, a list with a single zero was used instead of the consistent empty list.

This behavior is not being relied upon by the Python LSQ generator. Furthermore, the legacy Chisel-based generator does not use these config fields at all.

[MaxWipfli]

It turns out removing this was already discussed in #211. Back then, this "padding" was apparently still required by the Python generator. I have confirmed this is no longer the case:

These configuration values are stored by the Python generator as gaLdOrder, gaLdPortIdx, and gaStPortIdx. Those values in turn are only used to generate the ROM/LUT multiplexers in the group allocator, which use the Mux1HROM primitive, which uses the following code:

dynamatic/tools/backend/lsq-generator-python/vhdl_gen/operators/mux.py

Lines 139 to 151 in 80ffd77

	if (type(dout) == LogicVecArray):
	length = dout.length
	for i in range(0, length):
	str_ret += ctx.get_current_indent() + f'-- Loop {i}\n'
	mux = LogicVecArray(ctx, ctx.get_temp(f'mux_{i}'), 'w', mlen, size)
	for j in range(0, mlen):
	str_value = func(GetValue(din[j], i), size)
	if (str_value == str_zero):
	str_ret += ctx.get_current_indent() + f'{mux.getNameWrite(j)} <= {str_zero};\n'
	else:
	str_ret += ctx.get_current_indent() + f'{mux.getNameWrite(j)} <= {str_value} ' + \
	f'when {sel.getNameRead(j)} else {str_zero};\n'
	str_ret += Reduce(ctx, dout[i], mux, 'or', False)

If the din list contains empty lists (which is made possible by this patch), then GetValue(din[j], i) handles this gracefully, as GetValue simply returns zero of the index (i) is out of range.