Add comprehensive 14-week course syllabus with structured timeline for teaching all modules

[Copilot]

This PR addresses the request to create a syllabus that organizes the LLM4ChipDesign course materials into a structured 14-week semester timeline, with each module taught over 2-week cycles.

What's Added

New Course Syllabus (SYLLABUS.md)

• Structured 14-week timeline organizing course content into 7 core modules (2 weeks each)
• Two-week module format: Week 1 focuses on theory and homework assignment, Week 2 on hands-on workshops and homework solutions
• Carefully selected core modules from the 12 available topics to fit the semester constraint:
  1. AutoChip - Functional Verilog Generation (Weeks 1-2)
  2. Hierarchical Prompting with ROME (Weeks 3-4)
  3. VeriThoughts - Reasoning-Based Generation (Weeks 5-6)
  4. Veritas - CNF-Guided Synthesis (Weeks 7-8)
  5. LLM-Aided Testbench Generation (Weeks 9-10)
  6. SystemVerilog Assertion Generation (Weeks 11-12)
  7. C2HLSC - Software to Hardware Bridge (Weeks 13-14)

Enhanced Course Structure

• Detailed learning objectives for each module
• Specific homework assignments with clear deliverables and expected outcomes
• Assessment framework: 50% homework, 30% projects, 20% participation
• Prerequisites and software requirements for course setup
• Resource links to papers, code repositories, and tutorial notebooks
• Comprehensive learning outcomes defining what students will achieve

Updated README.md

• Added course overview paragraph explaining the repository's educational purpose
• Prominent syllabus link in the Table of Contents with clear labeling
• Maintains existing structure while highlighting the new educational framework

Implementation Details

The syllabus follows the requested format where each 2-week module includes:

• Week 1: Introduction to basic concepts, theory coverage, and homework assignment
• Week 2: Hands-on sessions where students work through homework solutions and practical exercises

This structure ensures students get both theoretical understanding and practical experience with each LLM-based chip design tool and methodology covered in the course.

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