Add 14-week course syllabus timeline to LLM4ChipDesign PDF

[Copilot]

This PR adds a comprehensive 14-week course timeline to the LLM4ChipDesign materials by creating a new syllabus PDF that extends the existing cover letter.

What's Added

• New PDF: LLM4ChipDesign_Syllabus.pdf - A 2-page document containing:
  • Page 1: Original cover letter content (preserved unchanged)
  • Page 2: Professional 14-week timeline with structured course schedule

Course Timeline Structure

The timeline follows the requested 2-week module format:

• Week 1 of each module: Introduction to concepts + homework assignment
• Week 2 of each module: Hands-on practice solving assignments

Selected Modules (7 modules × 2 weeks = 14 weeks)

1. AutoChip: Automated Verilog Generation (Weeks 1-2)
2. VeriThoughts: Reasoning-based Code Generation (Weeks 3-4)
3. ROME: Hierarchical Prompting for Complex Designs (Weeks 5-6)
4. Veritas: CNF-guided Verilog Synthesis (Weeks 7-8)
5. Testbench Generation & Bug Detection (Weeks 9-10)
6. Hybrid-NL2SVA: Natural Language to Assertions (Weeks 11-12)
7. C2HLSC: Software-to-Hardware Design Bridge (Weeks 13-14)

The modules were selected to provide comprehensive coverage of LLM applications in chip design, from basic Verilog generation to advanced verification and synthesis techniques.

Implementation Details

• Uses PyMuPDF and ReportLab for professional PDF generation
• Maintains original document formatting and metadata
• Creates a clean, readable table format for the timeline
• Preserves all existing content while adding the new timeline page

This syllabus provides instructors with a clear roadmap for teaching LLM4ChipDesign concepts over a standard 14-week semester.

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