Transistor network minimization is an important step in designing new standard cells. Existing methods for minimizing transistor networks all rely on some heuristic techniques. Hence, there is still room for further improvement. In this work, we propose MiniTNtk, an exact synthesis-based method for minimizing transistor networks. It models the generation of the transistor network for a Boolean function as a Boolean satisfiability (SAT) problem and can return a transistor network with the fewest transistors. Furthermore, sometimes, it is necessary to limit the number of transistors in series. Our CAD tool MiniTNtk can generate the file .sp file with the minimum transistor network for implementing given Boolean functions.
[1] Weihua Xiao, Shanshan Han, Yue Yang, Shaoze Yang, Cheng Zheng, Jingsong Chen, Tingyuan Liang, Lei Li, and Weikang Qian, "MiniTNtk: An Exact Synthesis-based Method for Minimizing Transistor Network," in Proceedings of the 2023 International Conference on Computer Aided Design (ICCAD), San Francisco, CA, USA, 2023, pp. 01-09.
- OS: Linux
- Language: C++ (version >= 2017)
- visual studio (version >= 2017)
- gcc
- g++ (version >= 9.4.0)
- https://learn.microsoft.com/en-us/windows/wsl/install (link and tutorial)
- sudo apt install gcc;
- sudo apt install g++;
- sudo apt-get install build-essential;
- git clone https://github.com/niklasso/minisat.git;
- cd minisat;
- make config prefix=$PREFIX;
- make install;
- sudo cp ./build/dynamic/bin/minisat /usr/bin/minisat
- sudo apt-get install graphviz;
- Set up a new Linux project in Visual Studio 2019;
- Add all source files into the project;
- Configure Include path;
- Compile & generate executable file (MiniTNtk.out).
-
Use
MiniTNtk.out --help
-
An example of input file
Booleans.txt:
- An example of MiniTNtk's solving process:
