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Dev #2

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a58c762
,,
marwanibrahim546 Oct 2, 2021
373e677
..
marwanibrahim546 Oct 2, 2021
72781e1
mmmmm
marwanibrahim546 Oct 2, 2021
68e79e4
Update img2col.sv
youssefmehdawy99 Oct 3, 2021
0668f0f
sss
marwanibrahim546 Oct 3, 2021
6ba4567
adding reset and enable
RaneemAlaa Oct 4, 2021
4251bcc
Merge branch 'dev' of https://github.com/IEEE-SSCS/CNN-Accelerator in…
RaneemAlaa Oct 4, 2021
4e18cf5
Pooling unit control
moustafamd Oct 10, 2021
61c4c24
Merge branch 'dev' of https://github.com/IEEE-SSCS/CNN-Accelerator in…
moustafamd Oct 10, 2021
bb47233
Merge branch 'main' into dev
OYounis Oct 11, 2021
953e8ac
generating data addresses
RaneemAlaa Oct 12, 2021
7b2e305
max_avg control output added
moustafamd Oct 13, 2021
1e45fa5
Update col2img.sv
hego2022 Oct 21, 2021
3736fb6
Update img2col.sv
hego2022 Oct 21, 2021
d0907b3
.
marwanibrahim546 Nov 1, 2021
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10 changes: 0 additions & 10 deletions img2col.sv
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254 changes: 254 additions & 0 deletions rtl/PU_CTRL.sv
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Original file line number Diff line number Diff line change
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module PU_CTRL
#(parameter pooling_units = 32,
parameter H = 5)
(
input logic clk, nrst,
input logic [2:0] pooling_inst, start_pool, array_dim,
output logic in_pipe_en, out_pipe_en, max_avg, done,
output logic [4:0] address [3:0]
);

enum logic [1:0] {start = 2'b00,
data_adress = 2'b01,
pipe_ip = 2'b10,
finish = 2'b11} next_state, current_state;

// inst max/avg | pooling instruction
// 1 / 0 | 01
logic [2:0] inst;
logic [4:0] temp_add [3:0];
logic [3:0] current_count, next_count;

always_ff @(posedge clk, negedge nrst)
begin
if(!nrst)
begin
current_state <= start;
inst <= '0;
current_count <= '0;
temp_add <= '{default:5'h00};
end
else
begin
current_state <= next_state;
current_count <= next_count;
if(start_pool)
begin
inst <= pooling_inst;
temp_add <= address;
end
else
inst <= inst;
end
end


// next state logic
always_comb
begin
in_pipe_en = 0;
out_pipe_en = 0;
max_avg = 1;
next_state = current_state;
next_count = current_count;
address = temp_add;

unique case (current_state)
start:
begin
if(start_pool)
begin
next_count = '0;
next_state = data_adress;
end
else
begin
next_count = '0;
next_state = current_state;
end
end

data_adress:
begin
// here we will generate data addresses

next_state = pipe_ip;
if (current_count > 0)
begin
out_pipe_en = 1;
case (current_count)
4'h1:
begin
address[0] = address[0] + 2;
address[2] = address[0] + array_dim;
if (array_dim == 3'h3) begin
address[1] = 5'd31;
address[3] = 5'd31;
end
else begin
address[1] = address[0] + 1;
address[3] = address[0] + array_dim + 1;
end
end


4'h2:
begin
case (array_dim)
3'h3:
begin
address[0] = address[0] + 4;
address[1] = address[0] + 1;
address[2] = 5'd31;
address[3] = 5'd31;
end

3'h4:
begin
address[0] = address[0] + 6;
address[1] = address[0] + 1;
address[2] = address[0] + array_dim;
address[3] = address[0] + array_dim + 1;
end


3'h5:
begin
address[0] = address[0] + 2;
address[1] = 5'd31;
address[2] = address[0] + array_dim;
address[3] = 5'd31;
end
endcase
end


4'h3:
begin
case (array_dim)
3'h3:
begin
address[0] = address[0] + 2;
address[1] = 5'd31;
address[2] = 5'd31;
address[3] = 5'd31;
end
3'h4:
begin
address[0] = address[0] + 2;
address[1] = address[0] + 1;
address[2] = address[0] + array_dim;
address[3] = address[0] + array_dim + 1;
end

3'h5:
begin
address[0] = address[0] + 6;
address[1] = address[0] + 1;
address[2] = address[0] + array_dim;
address[3] = address[0] + array_dim + 1;
end
endcase
end


4'h4:
begin
address[0] = address[0] + 2;
address[1] = address[0] + 1;
address[2] = address[0] + array_dim;
address[3] = address[0] + array_dim + 1;
end


4'h5:
begin
address[0] = address[0] + 2;
address[1] = 5'd31;
address[2] = address[0] + array_dim;
address[3] = 5'd31;
end
4'h6:
begin
address[0] = address[0] + 6;
address[1] = address[0] + 1;
address[2] = 5'd31;
address[3] = 5'd31;
end
4'h7:
begin
address[0] = address[0] + 2;
address[1] = address[0] + 1;
address[2] = 5'd31;
address[3] = 5'd31;
end
4'h8:
begin
address[0] = address[0] + 2;
address[1] = 5'd31;
address[2] = 5'd31;
address[3] = 5'd31;
end
endcase
end
else
begin
out_pipe_en = 0;
address[0] = 5'b0;
address[1] = address[0] + 1;
address[2] = address[0] + array_dim;
address[3] = address[0] + array_dim + 1;
end
end

pipe_ip:
begin
in_pipe_en = 1;
max_avg = inst[2];
//next_count = current_count + 1;
unique case (array_dim)
3'h3, 3'h4:
if (current_count == 4'h3)
begin
next_state = finish;
next_count = '0;
end
else
begin
next_state = data_adress;
next_count = current_count + 1;
end

3'h5:
if (current_count == 4'h8)
begin
next_state = finish;
next_count = '0;
end
else
begin
next_state = data_adress;
next_count = current_count + 1;
end
endcase
end

finish:
begin
next_state = start;
out_pipe_en = 0;
in_pipe_en = 0;
done = 1;
end
default:
begin
next_state = start;
next_count = '0;
end

endcase
end


endmodule

33 changes: 33 additions & 0 deletions rtl/col2img.sv
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module col2img#
(parameter data_width = 8
parameter in_vec_size =28 )(
input logic clk,
input logic nrst ,
output logic [data_width-1:0] out_img [in_vec_size-1:0][in_vec_size-1:0] ,
input logic in_valid ,
input logic [data_width:0] cols [(in_vec_size^2)-1:0]
);


always_comb begin

if(nrst)
begin
generate genvar i , j ;
for (i=0 , i < in_vec_size , i = i+1 ) ;
begin
for (j=0 , j < in_vec_size , j = i+1 ) ;
begin
out_img[i][j]= cols[i*in_vec_size+j] ;

end
end

endgenerate

end
else begin
out_img=0;
end

end
45 changes: 45 additions & 0 deletions rtl/img2col.sv
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module img2col#
(parameter data_width = 8
parameter img_size = 5 )(
input logic clk,
input logic nrst ,
input logic [2:0] k ,
input logic stride ,
input logic [data_width-1:0] img [img_size-1:0][img_size-1:0] ,
input logic in_valid ,
output logic [7:0] out_cols [31:0]
);



always_comb begin

if(nrst)
begin
generate genvar i , j ;
for (i=0 , i < 5 , i = i+1 ) ;
begin
for (j=0 , j < 5 , j = i+1 ) ;
begin
out_cols[i*5+j] = img[i][j] ;

end
end

endgenerate
out_cols[25:31]=0;
end
else begin
out_cols=0;
end

end








endmodule
3 changes: 2 additions & 1 deletion rtl/output_buffer.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -4,7 +4,7 @@ module output_buffer
)
(
input logic clk, nrst,
input logic Wr_ctrl [width-1:0],
input logic Wr_ctrl [width-1:0], en [width-1:0],
input logic [data_width-1:0] in [width-1:0],
input logic [4:0] add_1 [width-1:0],
input logic [4:0] add_2 [width-1:0],
Expand All @@ -23,6 +23,7 @@ module output_buffer
for (i=0; i<width; i=i+1)
Register_File RF(
.clk(clk), .nrst(nrst),
.en(en[i]),
.Wr_ctrl(Wr_ctrl[i]),
.in(in[i]),
.add_1(add_1[i]),
Expand Down
13 changes: 13 additions & 0 deletions rtl/parameter_calc.sv
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module parameter_calc(
input logic stride , input logic
);


always_comb begin




end

endmodule
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