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Mem Stage#78

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snehithkondal wants to merge 14 commits intocorefrom
mem_stage
Open

Mem Stage#78
snehithkondal wants to merge 14 commits intocorefrom
mem_stage

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@snehithkondal
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Fixed:
[] Syntax errors=
[] Incorrect indentation
[] Misspelled keywords or function names
[] Incorrect use of operators
[] Invalid data types or values
[] Incorrect function parameters or arguments
[] Uninitialized variables

snehithkondal and others added 12 commits March 12, 2026 10:55
[] Syntax Errors
[] Incorrect Port List

Made Progress On:
[] Stall Logic (Mem)
[] Stall and Flush Logic (Wb)
* Fixed mislabeled signals such as `misalignment_error`
* Fixed syntax issues on module definition and signal assignments
* Switched `DATA_W` for `DATA_WIDTH`
* Removed extra character behind `timescale`
[] Syntax errors in writeback.sv and mem_stage.sv
[] Updated mem_stage.sv to properly register inputs and update writeback data on completion
[] Fixed division by zero flag handling in writeback.sv
[] Syntax errors=
[] Incorrect indentation
[] Misspelled keywords or function names
[] Incorrect use of operators
[] Invalid data types or values
[] Incorrect function parameters or arguments
[] Uninitialized variables
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2 participants