Rivuss

Rivuss is a 32-bit RISC-V processor core written in Chisel HDL, implementing the RV32I base integer instruction set. This project features a single-cycle architecture suitable for FPGA deployment and educational purposes.

Features

Instruction Set: Complete RV32I base integer instruction set

• Arithmetic instructions (ADD, SUB, ADDI, etc.)
• Logical instructions (AND, OR, XOR, etc.)
• Shift instructions (SLL, SRL, SRA, etc.)
• Comparison instructions (SLT, SLTU, etc.)
• Branch instructions (BEQ, BNE, BLT, BGE, etc.)
• Jump instructions (JAL, JALR)
• Load/Store instructions (LW, LH, LB, SW, SH, SB, etc.)
• Immediate instructions (LUI, AUIPC)

Architecture

• Single-cycle execution
• 32 general-purpose registers
• 1KB instruction/data memory
• Configurable clock divider
• Byte, half-word, and word access support

Development Tools

• Mill build system
• FuseSoC integration
• Verilator simulation
• Vivado synthesis
• RISCOF architecture testing

Requirements

• Scala
• Chisel
• FuseSoC (for build management)
• Verilator (for simulation)
• Vivado (for FPGA synthesis, optional)

Directory Structure

rivuss/
├── rivuss/              # Chisel source code
├── verilator/           # Verilator simulation files
├── constraints/         # FPGA constraint files
├── program/             # Program memory initialization files
├── riscof/              # RISC-V architecture compliance tests
├── build.sc             # Mill build configuration
└── rivuss.core          # FuseSoC core configuration

Usage

Lint

fusesoc run --target=lint imfeh2:rivuss:single32i

Simulation

fusesoc run --target=sim imfeh2:rivuss:single32i

FPGA Synthesis

export CUSTOM_PART=xc7a35tfgg484-2
fusesoc run --target=synth imfeh2:rivuss:single32i

RISC-V Architecture Testing

Run architecture compliance tests using RISCOF:

cd riscof
riscof run --config ./config.ini --suite ./riscv-arch-test/riscv-test-suite/rv32i_m --env ./riscv-arch-test/riscv-test-suite/env

References

• RISC-V Specifications
• Chisel Documentation
• RV32I Instruction Set Manual