Fix binary op order and add unsigned instructions#14
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Fixes the operand order for all non-commutative signed binary operations (div_s, gt_s, lt_s, etc.) to correctly match the WebAssembly specification (stack: val2, val1 -> result: val2 op val1). Also adds support for unsigned operation instructions: - i32.gt_u, lt_u, ge_u, le_u, div_u and rem_u have been implemented in GammaCPU - GammaALU updated appropriately to support this - Tests added and updated for this new functionality to the CPU & ALU test benches
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Fixes the operand order for all non-commutative signed binary operations (div_s, gt_s, lt_s, etc.) to correctly match the WebAssembly specification (stack: val2, val1 -> result: val2 op val1).
Also adds support for unsigned operation instructions: