course projects and labs for "Open Source Prototype Systems and Applications (2026 Spring)" in NSYSU, Taiwan
| Projects | Descriptions |
|---|---|
| Project 1 | RV32I Single-Cycle Baseline Processor |
| Project 2-1 | RV32I Pipelined Processor with Cache Subsystem |
| Project 2-2 | Histogram Binning: Control Flow Reduction and Privatization |
| Project 3 | Histogram Binning: Data Layouts on a Dual-Core MSI-Coherent Processor |
| Project 4 | 2D Convolution Acceleration and Gem5 Custom Instruction Simulation |
| Labs | Descriptions |
|---|---|
| Week 3 Lab | RV32I Smoke Test and Linker Script |
| Week 6 Lab | Cache Behavior Traces: 3C Model, Locality, and Write Reuse |
| Week 10 Lab | Debugging a Broken Snooping Invalidation Interface |
| Week 11 Lab 1 | Dual-Core Cache Coherence Prototype System Stabilization |
| Week 11 Lab 2 | Producer-Consumer: Dual-CPU pthread Synchronization via Release-Acquire Atomics |
| Week 12 Lab | Histogram Binning: Evaluating Custom Instructions across Input Distributions and Cache Sizes |
| Week 13 Lab | McPAT Energy Analysis: Cache Size and Frequency Sensitivity across Workloads |
| Week 14 Lab | Timing Side-Channel Security: Early-Exit Leakage in a Token Comparator |
| Week 15 Lab | Fair-Shared Accelerator Arbitration: Round-Robin and Aging |
