VLSI Basic Program Repository

This repository contains a collection of basic VHDL programs implementing fundamental digital electronic components. It is designed as a learning resource for students, beginners, and engineers exploring VLSI design and HDL coding practices. Each program demonstrates the structural and behavioral modeling of essential building blocks such as logic gates, flip-flops, adders, subtractors, counters, and multiplexers.

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✨ Features

• Comprehensive VHDL Examples: Includes basic combinational and sequential circuits.
• Educational Resource: Beginner-friendly implementations for learning digital design concepts.
• Reusable Modules: Each design is modular and can be integrated into larger projects.
• Simulation Ready: All files are written in synthesizable VHDL, suitable for simulation in tools like ModelSim, Vivado, or EDA Playground.
• Structured Repository: Organized by functionality (adders, subtractors, counters, etc.).

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📂 Directory Structure

File Name	Description
3 to 8 decoder.vhdl	3:8 Decoder implementation
D Flip Flop.vhdl	D-type Flip-Flop
Half_adder.vhdl	Half Adder circuit
JK Flip Flop.vhdl	JK Flip-Flop
SR Flip Flop.vhdl	SR Flip-Flop
full_adder.vhdl	Full Adder circuit
full_subtractor.vhdl	Full Subtractor circuit
half_subtractor.vhdl	Half Subtractor circuit
mod-8 upcounter.vhdl	Mod-8 Up Counter
mux_4to1.vhdl	4:1 Multiplexer

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🛠️ Specifications and Resources

• HDL Language: VHDL (IEEE Std 1076)
• Simulation Tools: Compatible with ModelSim, Vivado, Synopsys VCS, and EDA Playground.
• Learning Reference: Ideal for academic labs, tutorials, and digital design practice.

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🚀 Steps to Run Simulation

1. Open Your HDL Simulator (ModelSim, Vivado, or EDA Playground).
2. Create a New Project and add the .vhdl file of interest.
3. Compile the Design to check for syntax errors.
4. Write a Testbench or use an existing one to simulate behavior.
5. Run Simulation and observe waveforms for verification.
6. Modify Parameters (like clock, reset, inputs) to test different scenarios.

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🧩 Applications

• Basic building blocks for larger VLSI designs.
• Educational demonstrations in digital electronics courses.
• Foundation for verification testbenches and FPGA projects.

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🧑‍💻 Author

• Name: Karankumar Nevage
• Email: karanpr9423@gmail.com
• LinkedIn: Karankumar Nevage

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🤝 Contributing

Contributions are welcome! You can:

• Add new VHDL modules (e.g., counters, registers, multiplexers).
• Improve testbenches for existing designs.
• Share simulation scripts for different tools.

Fork the repo, submit issues, or create pull requests to enhance this learning resource.

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📜 License

This project is open sourced.