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38 changes: 38 additions & 0 deletions src/striga/x86/control.py
Original file line number Diff line number Diff line change
Expand Up @@ -393,6 +393,31 @@ def syscall(sem: Semantics):
return [Successor(sem.insn.address, sem.const64(fallthrough))]


@semantic
def stc(sem: Semantics):
sem.flag_write("cf", sem.i1.constant(1))


@semantic
def clc(sem: Semantics):
sem.flag_write("cf", sem.i1.constant(0))


@semantic
def int_(sem: Semantics):
sem.ir.ret_void()
return []


@semantic
def cmc(sem: Semantics):
sem.flag_write("cf", bool_not(sem, sem.flag_read("cf")))


@semantic
def int3(sem: Semantics):
sem.ir.ret_void()
return []
@semantic
def nop(sem: Semantics):
pass
Expand All @@ -401,3 +426,16 @@ def nop(sem: Semantics):
@semantic
def pause(sem: Semantics):
pass
@semantic
def lfence(sem: Semantics):
pass


@semantic
def mfence(sem: Semantics):
pass


@semantic
def sfence(sem: Semantics):
pass
10 changes: 9 additions & 1 deletion src/striga/x86/data.py
Original file line number Diff line number Diff line change
@@ -1,5 +1,5 @@
from capstone import CS_OP_REG

from llvm import lookup_intrinsic_id
from ..semantics import FLAGS, Semantics, semantic


Expand Down Expand Up @@ -148,6 +148,14 @@ def cqo(sem: Semantics):
sem.reg_write("rdx", sem.ir.ashr(rax, sem.const64(63)))


@semantic
def bswap(sem: Semantics):
value = sem.op_read(0)

intrinsic = sem.module.get_intrinsic_declaration(lookup_intrinsic_id("llvm.bswap"), [value.type])

sem.op_write(0, sem.ir.call(intrinsic, [value]))

@semantic
def xchg(sem: Semantics):
src = sem.op_read(1)
Expand Down