agnus: model the DDF sequencer start/stop flip-flops for FMODE=0 fetches

[LinuxJedi]

Summary

Replace the value-range DDF window with the Agnus DDF sequencer flop model
for FMODE=0 bitplane fetches: DDFSTRT/DDFSTOP are comparator EDGES driving
flip-flops, a stop request drains through one final fetch unit (which
applies the modulos per plane), the hardwired window ($18/$D8, HARDDIS
$E0) gates starts and forces stops, and the state carries across line
boundaries.

• src/chipset/ddf_sequencer.rs: the free-standing flop model (OCS and
  ECS rule variants, transcribed from vAmiga 4.4's Sequencer).
• src/bus/ddf_line.rs: per-line walk driving the slot arbiter and the
  DMA capture loop; register writes rebuild the line table at their
  hardware commit clocks (DDF writes +4 ccks; an old DDFSTOP still fires
  on its commit clock, an old DDFSTRT does not).
• Wide-FMODE (AGA quantum > 1) fetches keep the existing value-window
  plan; vAmiga has no AGA counterpart to transcribe.

This gives Copperline the hardware's "old stop" behaviours a value range
cannot express: missed/invalid DDFSTOP runs continue to the hardware-stop
drain, a DDFSTRT match past $D8 starts a run that wraps through
horizontal blanking into the next line, an early-blanked DDFSTRT never
starts on OCS, and ECS's latched BPHSTART restarts runs at the hard
window.

Hardware arbitration

The vAmigaTS Agnus/DDF/DDF/oldhwstop1-4 tests exercise exactly these
behaviours, and each has real A500 photos (OCS and ECS). The bottom
colour-swatch band in those tests is a cumulative hash of every preceding
row's fetched word count (a 5-plane interleaved image with modulos: every
row's word count moves the bitplane pointers), and the photos match
vAmiga's band exactly while mismatching the old Copperline model
completely - real hardware validates the flop model's per-row fetch
history in aggregate.

Scores (vs vAmiga 4.4 refs, X_SHIFT=0)

test	before	after
Agnus/DDF/DDF/oldhwstop1	51.5%	0.31%
Agnus/DDF/DDF/oldhwstop2	50.2%	2.7%
Agnus/DDF/DDF/oldhwstop3	59.8%	16.7%
Agnus/DDF/DDF/oldhwstop4	53.4%	14.2%
Agnus/DDF bucket mean (66 cases)	6.9%	4.2%

Full Agnus+Denise sweep audit (776 cases vs the post-#107 baseline):
Agnus mean 12.06% -> 10.99%, Denise flat. Large collateral improvements
from the same flop semantics: the whole Agnus/Registers/oldDMACON family
(bplen1-5/oldbplen1-5 22-47% -> 0.5-13%, bplon1-4 24-28% -> 0-0.5%,
bplon1h-4h 26-31% -> 12-18%), Agnus/Registers/BPLPTR drop/dropcpu
(15-16% -> 3.5%), DMACON resmod2-4 (8-12% -> 0.4-2.2%), BPLCON0 block0-3,
and blitter timing0/6/10/15l. Remaining small deltas are the
slot-cadence interplay in the blitter-timing family (+-2%, mixed
directions - the hires per-plane slot offsets are now the hardware ones,
so the residual sits in the blitter model) and the DDFTIM write-timing
family (parity on average; the +4-cck commit delay was sweep-calibrated,
3/4/5 all within 0.2%). One case regressed meaningfully: Copper
oldJump/jumpbpu2 (0% -> 7.4%) while its siblings improved - the
free-running copper-loop precession class, where any one-slot cadence
change re-phases the loop (a previous attempt to tune this class was
reverted; jumpbpu1 improved by the same mechanism).

diwv3/diwv4 pinned a subtlety: lines above the captured framebuffer must
not advance bitplane pointers (a DIWSTRT.V inside vertical blanking would
otherwise skew every visible row); the capture keeps the pre-FSM
semantics there, matching the vAmiga reference dumps.

The oldhwstop3/4 residuals are the render-side placement of the exotic
rows themselves (fetch runs that wrap through hblank render at a single
per-row origin today); the pointer progression - which dominates the
image - is already exact. Renderer run-origin support is the follow-up.

Verification

• cargo test --release green (1284 tests: 18 value-window tests
  re-derived to flop semantics with rule comments; new FSM rule suite +
  bus-level table tests), cargo clippy, cargo fmt --check clean.
• STATE_VERSION 15 (Bus gained the serialized sequencer flop state).
• Performance: the per-cck table lookup replaces the memoized window math
  and cache probes; a 15s KS1.3 boot runs ~12% faster than main.
• Demo screenshots byte-identical to current main across the whole gate
  set: Gen-X (110s/620s), Inside the Machine, Hamazing, KS1.3 boot,
  Second Nature, A1200 KS3.1 boot (hires FMODE=3), Zool (AGA) - the FSM
  reproduces the value model exactly on sane register patterns.
• image_regression: 7 pass (ocs_bpu7_ham is the documented host-flaky
  perf test, fails on clean main too).

Update: renderer run-origin support (second commit)

The follow-up landed in this PR too: the capture records each row's fetch
run origin, and the renderer synthesizes the row's DDF geometry from it,
so rows whose fetch diverges from the register window paint what the DMA
fetched. Further movement (vs the first commit): oldhwstop3 16.7% -> 9.5%,
oldhwstop4 14.2% -> 7.5%, single4 16.0% -> 3.1%, single5 8.1% -> 2.4%,
hwstop2 5.2% -> 1.7%, hwstop4/5 10.0% -> 6.4%, hwstop6 7.3% -> 3.7%.
STATE_VERSION 16. Byte-identity re-verified (KS1.3, Inside the Machine,
Zool). Remaining in this family: hblank-wrapped runs still paint with the
register view, and arosddf1-4 (12.7%) is a separate ECS class.

Update: shifter reload-grid placement (third commit)

A second photo arbitration rode along: the arosddf1 A500 ECS photo shows
the DDFSTRT $3C lo-res picture at the $40 shifter reload slot relative to
the copper-anchored ruler dashes (both ruler ends agree) - FMODE=0
placement rounds UP to the reload grid, not down. arosddf1-3 12.8% ->
0.008%, arosddf4 -> 0.07%, ddf3/4/7/8 1.6% -> 0.1%. On-grid starts (every
previously calibrated case) unchanged; AROS/KS1.3/Zool byte-identical.