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paula: clock the POTxDAT counters at H-sync (once per scanline)#120

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LinuxJedi merged 1 commit into
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fix/pot-counter-hsync-clocked
Jul 5, 2026
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paula: clock the POTxDAT counters at H-sync (once per scanline)#120
LinuxJedi merged 1 commit into
mainfrom
fix/pot-counter-hsync-clocked

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Problem

Denise clocks the POTxDAT counters once per horizontal line, at H-sync -- the
same per-line clock as CIA-B's TOD. Copperline advanced them on a free-running
512-colour-clock divider (~2.25 scanlines/step): the counting ran ~2.25x too
slow and was not phase-aligned to the beam, so the pot-counter register
visualisations came out with the wrong band spacing and phase.

Fix

  • Drive the pot scan from the bus's per-new-line loop (next to the CIA-B TOD
    tick), tick_pot_hsync(), instead of a colour-clock accumulator.
  • Wrap the 8-bit counter at 256 instead of saturating (a floating pin keeps
    cycling for as long as the scan runs).
  • Keep the existing "a pin driven HIGH as an output freezes at 0" gate -- the
    Gods / Bitmap Brothers controls rely on it (pot_pin_driven_high).
  • While a scan is running, cap the advance at the next line boundary (the same
    deadline CIA-B TOD uses) so a CPU read of POTxDAT lands on the current value;
    when no scan is running the pots impose no deadline (so idle software is
    unaffected).

Validation

  • vAmigaTS Mainboard/Ports/POT: summed divergence 805.7% -> 790.8%.
    pot0dat3 becomes pixel-exact (0%); pot0dat4 30->20, pot0dat6 30->10,
    stop2 15->5, pot0dat5 10->5, cmp* slightly better.
  • Known regressions (accepted): start1/2 15->25, potout1/2/3/4 by ~5% each.
    These are read-once tests gated on a vblank IRQ, so their value is the number
    of lines between the POTGO START and the IRQ read. The now-correct per-line
    counter is more sensitive to Copperline's interrupt/read beam-timing
    residual (the separate CPU/IRQ write-timing model) that the coarse 512-divider
    had masked -- they are "differently wrong", not "correct -> broken", and will
    resolve when that timing model lands. pot0dat1/cmp stay ~100% for the same
    reason (fully interrupt-timing-bound).
  • Byte-identity: phooey / tomato / roots-ecs / roots-aga / zool screenshots
    stay byte-identical at 5s and 9s (the change only affects software that reads
    POTxDAT).
  • 1303 unit tests green (POT tests rewritten for the per-line model); clippy and
    fmt clean.

Verified with the new tools/adf-compare.sh against a local vAmiga 4.4 headless
build.

Denise charges the pot capacitors and clocks the POTxDAT counters once per
horizontal line, at H-sync -- the same per-line clock as CIA-B's TOD. The
counters were instead advanced on a free-running 512-colour-clock divider,
which is roughly 2.25 scanlines per step: the counting ran ~2.25x too slow and
was not phase-aligned to the beam, so the pot-counter visualisations came out
with the wrong band spacing and phase.

Drive the pot scan from the bus's per-new-line loop (next to the CIA-B TOD
tick) instead of from a colour-clock accumulator, wrap the 8-bit counter at 256
instead of saturating (a floating pin keeps cycling for as long as the scan
runs), and keep the existing "a pin driven high as an output freezes at 0" gate
(the Gods/Bitmap-Brothers controls rely on it). While a scan is running the
advance is capped at the next line boundary, the same deadline CIA-B TOD uses,
so a CPU read of POTxDAT lands on the up-to-date value.

vAmigaTS Mainboard/Ports/POT summed divergence drops from 805.7% to 790.8%;
pot0dat3 becomes pixel-exact and pot0dat4/6 and stop2 improve markedly. The
start*/potout* read-once tests regress: their value is the number of lines
between the POTGO START and a vblank-IRQ-driven read, so the now-correct
per-line counter is more sensitive to the interrupt/read beam-timing residual
(the separate CPU/IRQ write-timing model) that the coarse divider had masked.
The standard demo screenshots stay byte-identical -- the change only affects
software that reads POTxDAT.
@LinuxJedi LinuxJedi merged commit 81e8fa8 into main Jul 5, 2026
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@LinuxJedi LinuxJedi deleted the fix/pot-counter-hsync-clocked branch July 5, 2026 14:37
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