blitter: model the line micro-programs against vAmiga's SlowBlitter

[LinuxJedi]

Was stacked on #149 (fix/unified-write-effect-pipeline); #149 has since
MERGED and this branch is rebased onto main (063af0d). The PR now carries
two commits: the line-blit micro-program model and its docs.

Reconciliation with #149 (write-effect overlap)

The original copvbl commit here made the Denise write-effect delay
source-independent from the live beam position. #149 landed the more complete
model: CPU write effects referenced from the granted chip-bus slot
(cpu_custom_access_slot), with per-class delays (Denise-class +4 cck; Agnus
two-cycle class DMACON/BPLxPT/BPLxMOD/SPRxPT +2 cck, vAmiga
recordRegisterChange(DMA_CYCLES(2))). vAmiga's pokeCustom16 positions
correspond to the granted slot, so #149's reference point is the correct one -
in my copvbl probe runs CL's live-beam positions coincided with vAmiga's
pokes, which is the same +2 bus-cycle tail #149 identifies. The copvbl render
commit and the duplicate COPPERLINE_DIAG_CPU_WRITES probe were therefore
DROPPED in favour of #149's implementations: the write-effect delay is applied
exactly once per event, in record_render_write, under #149's two-class
model. The collision-events raw-landing split from the dropped commit was not
re-added: #149 recalibrated the staged collision tests against the delayed
positions and the suite is green on the stack.

Verified on the stack: this branch adds exactly ZERO delta to Agnus/Copper vs
#149 alone (max per-case delta +0.00); #149 itself nets copvbl 236.9 -> 236.4
and coptim 44.2 -> 42.5 vs the pre-#149 main.

Line-blit micro-programs (this PR's work)

The line engine ran a fixed 4-cycle pixel cadence keyed only on USEC.
vAmiga's SlowBlitter has four line micro-programs indexed by the USEB/USEC
pair; now modelled and trace-verified cycle-for-cycle relative to the BLTSIZE
poke (two-sided COPPERLINE_DIAG_BLT_SLOTS / VAMIGA_BLT_PROBE on
bususage1l BC=00, bususage5l BC=10, bususage15l BC=11), stalls included:

• USEB lines: 6 cycles/pixel with a B fetch (adds only BLTBMOD to BLTBPT) and
  a bare bus-allocation cycle; their terminal BLTDONE micro-cycle is
  BUSIDLE-class (waits for a free bus).
• Line WRITE_D allocates the bus even when SING suppresses the store (copy
  mode's lockD-busidle rule does not apply in line mode); suppression only
  locks the store, so the minterm/BZERO still see the full inputs (zero1).
• Line texture = BLTBDAT rotated by the LIVE BSH each pixel (bsh3/bsh4);
  the write-time BLTBDAT latch applies only to the USEB-off copy hold word
  (undocumented1 unchanged).
• The Bresenham accumulator advances only with USEA (vAmiga doLine).
• C DMA fetches load BLTCDAT itself; a later USEC-off blit consumes the last
  fetched C word (zero1 blits 7-12).

STATE_VERSION 26 -> 27 (LineBlitState gained use_a/use_b/bpt and the
LB/LBus phases).

Numbers (summed diff% per bucket; pre-#149 main / #149 alone / this branch)

Agnus/Blitter: 1647.6 / 1578.6 / 1535.8 (marginal vs #149: -42.8)

• line 35.02 -> 35.02 -> 0.80; timing 114.8 -> 108.0; cputim -2.0;
  bususage -1.1
• marginal regressions vs Unify the register-write effect pipeline: slot-referenced write-effect delays for CPU writes #149: bbusy7l +1.04pp (BBUSY poll-exit
  quantization against the now-slower 6-cycle USEB lines; the blit itself is
  trace-exact), bususage4l/5l/12l/13l +0.62pp each (BC=10 group; CPU-write
  beam-phase class, blitter side trace-exact)

Agnus/Copper: 949.1 / 930.5 / 930.5 (marginal vs #149: 0.00)

Honest residual

The copvbl b/c variants (+1.5pp each under #149's model) and the small
line-mode bususage/bbusy counter-moves are the previously-characterized
interrupt-recognition/CPU beam-phase class: the copvbl1b two-sided trace shows
both emulators landing the copper MOVE INTREQ at (312,$3c), with vAmiga's
handler phase unchanged vs copvbl1 while Copperline's recognition quantizes
to a different instruction boundary (its poll-boundary grid sits ~2 cck
early). A +1 cck copper-INTREQ latch-delay experiment measured strictly worse
(copvbl 247.6 -> 273.6 under the old model), confirming the offset lives in
the CPU instruction grid, not in a recognition constant.

Gates

• cargo test --lib green (1346 passed on merged main base); clippy --all-targets --all-features --locked -- -D warnings clean; fmt clean
• 14-demo byte-identity: 14/14 IDENTICAL, verified against both the Unify the register-write effect pipeline: slot-referenced write-effect delays for CPU writes #149
  base and merged main 063af0d
• coptim guard holds (42.46, improved vs pre-Unify the register-write effect pipeline: slot-referenced write-effect delays for CPU writes #149 main); copvbl nets down vs
  pre-Unify the register-write effect pipeline: slot-referenced write-effect delays for CPU writes #149 main (236.4 vs 236.9)
• vAmiga reference: existing env-gated hooks only (snapshots in
  vamigats-reports/*.patch); no reference-source changes
• docs: docs/internals/timing.md (line micro-programs; Unify the register-write effect pipeline: slot-referenced write-effect delays for CPU writes #149's write-effect
  section kept as-is), docs/debugger/headless.md (COPPERLINE_DIAG_CPU_WRITES)