This repository contains a comprehensive collection of arithmetic multiplier benchmarks in AIG (And-Inverter Graph) format. These benchmarks are designed for evaluating logic synthesis, formal verification, and arithmetic circuit optimization algorithms.
The benchmarks primarily consist of 64x64-bit multipliers generated using various open-source arithmetic circuit generators. The dataset covers a wide range of architectures by combining different Partial Product Generators (PPG), Partial Product Accumulators (PPA), and Final Stage Adders (FSA).
- GenMul: https://github.com/amahzoon/genmul
- MultGen: https://github.com/temelmertcan/multgen
- Akoi: https://fmv.jku.at/amulet2/ (Note: The original website for Akoi is no longer accessible. We retrieved the benchmarks in an alternative website.)
The benchmarks are organized by signedness and the tool used for generation:
.
├── signed/
│ ├── genmul/ # Generated by GenMul (Signed)
│ ├── multgen/ # Generated by MultGen (Signed)
│ └── akoi/ # Generated by Akoi (Signed)
└── unsigned/
├── genmul/ # Generated by GenMul (Unsigned)
├── multgen/ # Generated by MultGen (Unsigned)
└── akoi/ # Generated by Akoi (Unsigned)
Files are generally named using the following pattern to identify the architecture:
[PPG]-[PPA]-[FSA].aig
- PPG (Partial Product Generator): e.g.,
sp(Simple/AND),bp(Booth). - PPA (Partial Product Accumulator): e.g.,
ar(Array),wt(Wallace Tree),dt(Dadda Tree). - FSA (Final Stage Adder): e.g.,
rc(Ripple Carry),ks(Kogge-Stone),lf(Ladner-Fischer).
Due to a specific bug in the GenMul tool, the generation of the Signed Array Multiplier with Carry Skip Adder fails during the Verilog generation phase.
- Missing File:
sp-ar-cs.aig - Location:
signed/genmul/
Consequently, the signed/genmul/ directory contains 27 benchmarks instead of the expected 28. All other combinations were generated successfully.