This repository contains device-agnostic RTL designs written in SystemVerilog, as well as board-specific Altera FPGA/SoC projects for experimentation and learning purposes. The aim of these tasks is to improve RTL and embedded system design skills by developing custom hardware-software co-design solutions. For the hardware-software co-design projects, I will be using the Terasic DE1-SoC board. Continuous developments are being made to this repository and suggestions for improvements and collaboration are most welcome. Majority of the RTL designs are written from scratch and may not be the most optimal for all use cases. Relevant links to referenced codes and algorithms are provided in the design and/or simulation files.
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├── Docs
├── HPS # HPS software for hardware designs in directories within RTL/
├── Images
├── LICENSE
├── README.md
└── RTL # Custom RTL designs