GitHub - NTP17/Huge_Matrix_Multiplier: My attempt to design a hardware matrix multiplier (using SystemVerilog) that multiplies very large matrices together, with as low clock cycles and as high clock speed as possible.

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My attempt to design a hardware matrix multiplier (using SystemVerilog) that multiplies very large matrices together, with as low clock cycles and as high clock speed as possible.

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Name		Name	Last commit message	Last commit date
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fastest_512_LowFmax		fastest_512_LowFmax
test cases		test cases
.gitattributes		.gitattributes
Lab 2 Report_EE4449_TT01_231_Nguyễn Trường Phú_2051058.docx		Lab 2 Report_EE4449_TT01_231_Nguyễn Trường Phú_2051058.docx

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My attempt to design a hardware matrix multiplier (using SystemVerilog) that multiplies very large matrices together, with as low clock cycles and as high clock speed as possible.