Implement memory regions iterators#104
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Co-authored-by: Copilot <copilot@github.com>
Co-authored-by: Copilot <copilot@github.com>
Co-authored-by: Copilot <copilot@github.com>
| fdt_t fdt; | ||
| error_t err = hal_riscv_init_fdt(&fdt); | ||
| if (err) | ||
| return err; |
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I don't think I like reinitializing the fdt on every step
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I added file-level static fdt variable, is it a correct approach?
Co-authored-by: Copilot <copilot@github.com>
Kamilosok
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The dt logic looks fine, didn't find anything wrong with memory stuff at a glance, though requesting a review from @frogrammer9 on this is a good idea. Noticed a few consistency issues.
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| dt_prop_t address_cells_prop; | ||
| error_t err = dt_get_prop_by_name(fdt, node, "#address-cells", &address_cells_prop); | ||
| if (err == ERR_NONE) { |
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I prefer maintaining a logic flow where errors are handled first, and normal execution continues afterward, like other dt_ functions
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| error_t err = dt_get_node_sibling(fdt, node, &node); | ||
| error_t err; | ||
| if (node != 0) |
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When doing special behavior like this document it well
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| typedef struct { | ||
| u32 idx; | ||
| u32 memreserve_idx; |
| u64 size; | ||
| err = hal_riscv_read_reg_entry(fdt, next_iter.resmem_current_node, next_iter.resmem_reg_idx, | ||
| next_iter.resmem_address_cells, next_iter.resmem_size_cells, &addr, &size); | ||
| if (err == ERR_NONE) { |
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Same with error handling flow here
| u64 addr; | ||
| u64 size; | ||
| err = hal_riscv_read_reg_entry(fdt, next_iter.node, next_iter.reg_idx, address_cells, size_cells, &addr, &size); | ||
| if (err == ERR_NONE) { |
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