Add fixes for LLVM main branch assembly and refactor#5
Open
harryrrah76 wants to merge 34 commits into
Open
Conversation
…s an extensino to remove
harryrrah76
changed the title
…BlackFormatter to format Python file
…uces incorrect results
…pported as they can be implemented in the same way as vl1re64 and vs1r
…ould , the one would also be mistakenly replaced with t0
BubbleSalt
reviewed
Mar 20, 2025
| vd, vs2 = instruction[1], instruction[2] | ||
| vm = ", " + instruction[3] if len(instruction) > 3 else "" | ||
| newline = ( | ||
| "\tvwaddu.vx, {VD}, {VS2}, x0{VM}\n" # unsigned widening add zero |
There was a problem hiding this comment.
I am confused why there are commas behind vwaddu.vx, maybe they are mistakes?
There is another problem here, when I use the original script vs2 can be '[reg]\n', the problem can be solved with letting vs2 be instruction[2].replace("\n","").
BubbleSalt
reviewed
Mar 20, 2025
| } | ||
| if name in remove_list: | ||
| newline = newline.replace("_" + attribute, "") | ||
| line_changed = True |
There was a problem hiding this comment.
These modified codes will turn former code into latter one, and it will cause gcc compilation error because there is no v0p7.
.attribute 5, "rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0_zifencei2p0_zve32f1p0_zve32x1p0_zvl32b1p0"
.attribute 5, "rv64i2p0_m2p0_a2p0_f2p0_d2p0_c2p0_zicsr2p0"
This is what the original code will generate.
.attribute 5, "rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_v0p7"
BubbleSalt
reviewed
Mar 22, 2025
| suggestion += "# Pick unused register e.g. t0\n" | ||
| suggestion += "#\taddi t0, " + AVL + '\n' | ||
| suggestion += "# " + temp + '\n' | ||
| suggestion += f"\taddi t0, x0, {AVL} \n" |
This file contains hidden or bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
Sign up for free
to join this conversation on GitHub.
Already have an account?
Sign in to comment
2 participants
Add this suggestion to a batch that can be applied as a single commit.This suggestion is invalid because no changes were made to the code.Suggestions cannot be applied while the pull request is closed.Suggestions cannot be applied while viewing a subset of changes.Only one suggestion per line can be applied in a batch.Add this suggestion to a batch that can be applied as a single commit.Applying suggestions on deleted lines is not supported.You must change the existing code in this line in order to create a valid suggestion.Outdated suggestions cannot be applied.This suggestion has been applied or marked resolved.Suggestions cannot be applied from pending reviews.Suggestions cannot be applied on multi-line comments.Suggestions cannot be applied while the pull request is queued to merge.Suggestion cannot be applied right now. Please check back later.
The PR has two parts.
The first part is a set of fixes found when converting the assembly generated by the LLVM main branch (using the Jul 25 18:49:38 commit, hash: 7304936479a7eb61adc9edcaf6ce56e4792590ad) to RVV 0.7.1. This has been tested with the riscv-gnu-toolchain XuanTie 10.2 using a simple saxpy program that uses OpenMP SIMD directives on the SG2042 RISC-V Testbed:
vmis empty in the whole register load/store/copyvl*re32andvl*64redidn't include the.vin the whole register load/store/copyuleb128and.addrsiginstructions from roll-backed assemblyaddiinstructionThe second part is a set of refactorings to improve readability and ease of maintenance:
I'm happy to turn this into two separate PRs if preferred.