Allow VGPR overflow in ForceGenerateKernel

[ssuyuanchang]

JIRA ID: https://amd-hub.atlassian.net/browse/AIHPBLAS-4130

Motivation

Forced generation of VGPR-overflowed kernel

Technical Details

Print warning if VGPR overflow instead of raising error

Test Plan

hipblaslt-test and yaml test

Test Result

passed hipblaslt-test and yaml test

Submission Checklist

• Look over the contributing guidelines at https://github.com/ROCm/ROCm/blob/develop/CONTRIBUTING.md#pull-requests.

[therock-pr-bot]

❌ PR Check — Action Required

Check	Status	Details
🌿 Branch Name	✅ Pass	—
📝 PR Title/Description	✅ Pass	—
⛔ Forbidden Files	✅ Pass	—
🧪 Unit Test	❌ Fail	Error: Source/code files changed without an accompanying unit test. Expected: add at least one test file named like test_<name>.py / test_<name>.cpp (or <name>_test.*). Current: code file(s) changed: projects/hipblaslt/tensilelite/Tensile/KernelWriter.py; no test file found
🔎 pre-commit	✅ Pass	—
🚫 Draft PR	🔜 To Be Enabled	—
🚩 Feature Flag	🔜 To Be Enabled	—
📊 Code Coverage	🔜 To Be Enabled	—

⚠️ 1 policy check(s) failed. Please address the issues above before this PR can be Reviewed.

🚫 Please fix the failed policies

• ❌ Unit Test

The Not ready to Review label was added to this PR. Once all policies pass, the label is removed automatically.

📖 Need help? See the Policy FAQ for details on every check and how to fix failures.

[therock-pr-bot]

🚫 Please fix the failed policies before requesting reviews.

The following policy checks failed:

• ❌ Unit Test

The Not ready to Review label has been added to this PR.
Once all policies pass, the label will be removed automatically.

[codecov]

Codecov Report

❌ Patch coverage is 0% with 1 line in your changes missing coverage. Please review.

Files with missing lines	Patch %	Lines
...ects/hipblaslt/tensilelite/Tensile/KernelWriter.py	0.00%	1 Missing ⚠️

❌ Your project check has failed because the head coverage (76.84%) is below the target coverage (80.00%). You can increase the head coverage or adjust the target coverage.

Additional details and impacted files

@@             Coverage Diff             @@
##           develop    #9615      +/-   ##
===========================================
- Coverage    64.32%   64.29%   -0.02%     
===========================================
  Files         2766     2766              
  Lines       451359   450878     -481     
  Branches     66390    66336      -54     
===========================================
- Hits        290304   289891     -413     
+ Misses      140231   140187      -44     
+ Partials     20824    20800      -24     

Flag	Coverage Δ		*Carryforward flag
TensileLite	34.35% <ø> (+<0.01%)	⬆️	Carriedforward from 9c9e02c
TensileLite-CPP	38.31% <ø> (ø)
TensileLite-Unit	35.57% <0.00%> (ø)
hipBLAS	90.62% <ø> (ø)		Carriedforward from 9c9e02c
hipBLASLt	34.63% <ø> (ø)
hipCUB	82.68% <ø> (ø)		Carriedforward from 9c9e02c
hipDNN	86.36% <ø> (ø)		Carriedforward from 9c9e02c
hipFFT	46.60% <ø> (ø)		Carriedforward from 9c9e02c
hipRAND	76.12% <ø> (ø)		Carriedforward from 9c9e02c
hipSOLVER	69.18% <ø> (ø)		Carriedforward from 9c9e02c
hipSPARSE	86.27% <ø> (ø)		Carriedforward from 9c9e02c
rocBLAS	47.95% <ø> (ø)		Carriedforward from 9c9e02c
rocFFT	49.03% <ø> (ø)		Carriedforward from 9c9e02c
rocRAND	57.01% <ø> (ø)		Carriedforward from 9c9e02c
rocSOLVER	76.84% <ø> (ø)		Carriedforward from 9c9e02c
rocSPARSE	72.50% <ø> (-0.08%)	⬇️	Carriedforward from 9c9e02c
rocThrust	91.36% <ø> (ø)		Carriedforward from 9c9e02c

*This pull request uses carry forward flags. Click here to find out more.

Files with missing lines	Coverage Δ
...ects/hipblaslt/tensilelite/Tensile/KernelWriter.py	23.82% <0.00%> (ø)

... and 8 files with indirect coverage changes

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